<s> operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; } code = GET_CODE ( operands [ <NUM_LIT> ] ) ; x = operands [ <NUM_LIT> ] ; y = operands [ <NUM_LIT> ] ; if ( code == EQ ) { if ( GET_MODE ( x ) == SImode ) { rtx pat ; if ( TARGET_ARCH64 ) pat = gen_seqsidi_special ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_seqsisi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } else if ( GET_MODE ( x ) == DImode ) { rtx pat = gen_seqdi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } } if ( code == NE ) { if ( GET_MODE ( x ) == SImode ) { rtx pat ; if ( TARGET_ARCH64 ) pat = gen_snesidi_special ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_snesisi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } else if ( GET_MODE ( x ) == DImode ) { rtx pat ; if ( TARGET_VIS3 ) pat = gen_snedi_special_vis3 ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_snedi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } } if ( TARGET_V9 && TARGET_ARCH64 && GET_MODE ( x ) == DImode && ! ( TARGET_VIS3 && ( code == GTU || code == LTU ) ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU ||


<s> if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg )

. addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> const <ISA_LIT>RegisterInfo * LRI = static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - <NUM_LIT> ; MFI . CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; MFI . CreateFixedObject ( <NUM_LIT> ,


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) { ( void


<s> static unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs , SubRegs


<s> unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> setDesc ( Desc ) ; MachineInstrBuilder ( MI ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MI -> getOperand ( <NUM_LIT> ) . getReg


<s> static bool DisassemblePseudo ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO ) { assert ( <NUM_LIT> && <STR_LIT> )


<s> bool usesTlsViaGlobalReg ( ) const { return


<s> if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo ,


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Register ) ; Op -> Reg . RegNum =


<s> else return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addReg ( <STR_LIT> (

MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; return true


<s> SmallVector < SDValue > HiOps ( NumOps , SDValue ( ) ) ; for ( unsigned I = <NUM_LIT> ; I != NumOps ; ++ I ) { SDValue SrcOp = Op . getOperand ( I ) ; if ( ! SrcOp . getValueType ( ) . isVector ( ) ) { LoOps [ I ] = HiOps [ I


<s> return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return mode ; default : gcc_unreachable ( )


<s> const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl


<s> vld1_s64 ( const int64_t * __a ) { return ( int64x1_t ) { *


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCSubtargetInfo &


<s> uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; unsigned Flags = MI -> getFlags ( ) ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) )

return LowerDarwinGlobalTLSAddress ( Op , DAG ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { if ( Fast ) * Fast = true ; return true


<s> static bool sh_pass_in_reg_p ( const CUMULATIVE_ARGS & cum , machine_mode mode , const_tree type ) { return ( ( type == <NUM_LIT> || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count

[ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + HARD_REGNO_NREGS ( BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ;


<s> Triple T ( TT ) ; bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( RM == Reloc :: Default ) { if ( T . isOSDarwin ( ) ) { if ( is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: DynamicNoPIC ; } else if ( T . isOSWindows ( ) && is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: Static ; } if ( RM == Reloc :: DynamicNoPIC ) { if ( is64Bit ) RM = Reloc ::


<s> std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; InstructionCost Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; Cost *= CostFactor ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > registered_target (


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> useThumbBacktraces ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG .

getEntryNode ( ) , FrameAddr , NULL , <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> || ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> || ( uint32_t ) Fixup . getKind ( )

== <STR_LIT> || ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) IsResolved = false ;


<s> unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else { MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused (


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo (


<s> x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , <NUM_LIT> ) ; PUT_NUM_ELEM ( XVEC ( x , <NUM_LIT> ) , nelt ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) XVECEXP ( x , <NUM_LIT> , i ) = GEN_INT ( perm [ i ] ) ; save_vconcat = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , <NUM_LIT> ) ; XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , <NUM_LIT> ) = op0 ; PUT_MODE ( SET_SRC ( PATTERN ( vselect_insn ) ) , GET_MODE ( target ) ) ; SET_DEST ( PATTERN ( vselect_insn ) ) = target ; icode = recog_memoized ( vselect_insn ) ; if ( icode >= <NUM_LIT> && ! testing_p ) emit_insn ( copy_rtx ( PATTERN ( vselect_insn


<s> static <STR_LIT> GetCondCode ( MachineInstr & Instr ) { assert ( IsVCMP ( Instr . getOpcode ( ) ) && <STR_LIT> ) ; return <STR_LIT> ( Instr . getOperand ( <NUM_LIT> ) . getImm


<s> assert ( dv -> hasDomain ( domain ) && <STR_LIT> ) ; while ( ! dv -> Instrs . empty ( ) ) TII -> SetSSEDomain ( dv

-> Instrs . pop_back_val ( ) , domain ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> enum aarch64_parse_opt_result parse_res = aarch64_parse_arch ( str , & tmp_arch , & aarch64_isa_flags , & invalid_extension ) ; if ( parse_res == AARCH64_PARSE_OK ) { gcc_assert ( tmp_arch ) ; selected_arch = tmp_arch ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_arch ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> <STR_LIT> , invalid_extension . c_str ( ) , str ) ; aarch64_print_hint_for_extensions ( invalid_extension ) ; break ; default : gcc_unreachable ( ) ; } return


<s> unsigned char status = _HTM_STATE ( __builtin_tend ( <NUM_LIT> ) ) ; if ( __builtin_expect ( status , _HTM_TRANSACTIONAL


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div4si (


<s> if ( ( TREE_CODE ( exp ) == VAR_DECL || TREE_CODE ( exp ) == FUNCTION_DECL ) && DECL_DLLIMPORT_P ( exp ) ) return false ; if ( DECL_P ( exp ) && ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( exp ) ) && TREE_PUBLIC ( exp ) && DECL_EXTERNAL ( exp )


<s> if ( insn . eaBase == EA_BASE_sib || insn . eaBase == EA_BASE_sib64 ) { if ( insn . sibBase != SIB_BASE_NONE ) { switch ( insn . sibBase ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_BASE_ ## x : \ baseReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; ALL_SIB_BASES } } else { baseReg = MCOperand :: createReg ( <STR_LIT> ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM } } else { if ( insn . sibScale != <NUM_LIT> || ( insn . sibBase == SIB_BASE_NONE && insn . mode != MODE_64BIT ) || ( insn . sibBase != SIB_BASE_NONE && insn . sibBase != SIB_BASE_ESP && insn . sibBase != SIB_BASE_RSP && insn . sibBase != SIB_BASE_R12D && insn . sibBase != SIB_BASE_R12 ) ) { indexReg = MCOperand :: createReg ( insn . addressSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else indexReg = MCOperand :: createReg ( <STR_LIT> ) ; } scaleAmount = MCOperand :: createImm (


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> )


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; clearFeatureBits ( <STR_LIT>


<s> } else if ( ! strncmp ( ACPV -> getSymbol ( ) , <STR_LIT> , <NUM_LIT> ) ) Name = ACPV -> getSymbol ( ) ; else Name = Mang -> makeNameProper ( ACPV -> getSymbol ( ) ) ; O << Name ; if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment ( ) != <NUM_LIT> ) { O << <STR_LIT> << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << ACPV -> getLabelId ( ) << <STR_LIT> << ( unsigned ) ACPV -> getPCAdjustment ( ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) O << <STR_LIT> ; O << <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const


<s> if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; unsigned OffsetsElemCount = cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ; assert ( Ty -> getNumElements ( ) == OffsetsElemCount ) ; ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ; if ( ZextOffs ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; FixedVectorType * OffsetType = cast < FixedVectorType > ( Offsets -> getType ( ) ) ; if ( ! ZextOffs || cast < FixedVectorType > ( ZextOffs -> getDestTy ( ) ) -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) if ( ! checkOffsetSize ( Offsets , OffsetsElemCount ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getElementType ( ) -> getScalarSizeInBits ( ) < OffsetType -> getElementType ( ) ->


<s> RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ; BB -> addSuccessor


<s> MCAsmParser & getParser ( ) const { return


<s> if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; for ( -- PrevI ; PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ; -- PrevI ) ; MachineInstr * LeaMI = PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk ) continue ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewJTMI = BuildMI ( MBB , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( MI -> getOperand ( JTOpIdx + <NUM_LIT> ) . getImm ( ) ) ; unsigned NewSize = TII -> GetInstSizeInBytes ( NewJTMI ) ; unsigned OrigSize = TII -> GetInstSizeInBytes ( AddrMI ) ; OrigSize += TII -> GetInstSizeInBytes ( LeaMI ) ; OrigSize += TII -> GetInstSizeInBytes ( MI ) ; AddrMI -> eraseFromParent ( ) ; LeaMI -> eraseFromParent ( ) ; MI -> eraseFromParent ( ) ; int delta = OrigSize - NewSize ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; AdjustBBOffsetsAfter ( MBB , - delta ) ; ++ NumTBs ; MadeChange =


<s> getParser ( ) . getStreamer ( ) . emitTPRel64Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer (


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T ,

const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) {


<s> real_from_string ( & rv , <STR_LIT> ) ; sh_fsca_int2sf_rtx = const_double_from_real_value ( rv


<s> SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0 ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck2 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; int ShufMask [ <NUM_LIT> ] = {


<s> void relaxInstruction ( const MCInst & Inst , MCInst &


<s> void <ISA_LIT>PassConfig :: addPreEmitPass


<s> unsigned MaxCSNum = <NUM_LIT> ; for ( auto & MBB : * MF ) { if ( ! MBB . isEHPad ( ) ) continue ; MCSymbol * Sym = nullptr ; for ( const auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; assert ( MI . isEHLabel ( ) && <STR_LIT> ) ; Sym = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; } if ( ! MF -> hasCallSiteLandingPad ( Sym ) ) continue ; for ( unsigned CSI : MF -> getCallSiteLandingPad ( Sym ) ) { CallSiteNumToLPad [ CSI ] . push_back ( & MBB ) ; MaxCSNum = std :: max ( MaxCSNum , CSI ) ; } } std :: vector < MachineBasicBlock * > LPadList ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > InvokeBBs ; LPadList . reserve ( CallSiteNumToLPad . size ( ) ) ; for ( unsigned CSI = <NUM_LIT> ; CSI <= MaxCSNum ; ++ CSI ) { for ( auto & LP : CallSiteNumToLPad [ CSI ] ) { LPadList . push_back ( LP ) ; InvokeBBs . insert ( LP -> pred_begin ( ) , LP -> pred_end ( ) ) ; } } assert ( ! LPadList . empty ( ) && <STR_LIT> ) ; MachineBasicBlock * DispatchBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> setIsEHPad ( true ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; DispatchBB -> addSuccessor ( TrapBB ) ; MachineBasicBlock * DispContBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> addSuccessor ( DispContBB ) ; MF -> push_back ( DispatchBB ) ; MF -> push_back ( DispContBB ) ; MF -> push_back ( TrapBB ) ; SetupEntryBlockForSjLj ( MI , BB , DispatchBB , FI ) ; MachineJumpTableInfo * JTI = MF -> getOrCreateJumpTableInfo ( getJumpTableEncoding ( ) ) ; unsigned MJTI = JTI -> createJumpTableIndex ( LPadList ) ; const <ISA_LIT>RegisterInfo & RI = TII -> getRegisterInfo ( ) ; if ( RI . hasBasePointer ( * MF )


<s> vcreate_s64 ( uint64_t __a ) { return ( int64x1_t ) {


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS


<s> bool <ISA_LIT>AsmParser :: HandleAVX512Operand ( OperandVector & Operands , const MCParsedAsmOperand & Op ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { const SMLoc consumedToken = consumeToken ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return TokError ( <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return false ; } else { std :: unique_ptr < <ISA_LIT>Operand > Z ; if ( ParseZ ( Z , consumedToken ) ) return true ; if ( ! Z || getLexer ( ) . is ( AsmToken :: LCurly ) ) { SMLoc StartLoc = Z ? consumeToken ( ) : consumedToken ; unsigned RegNo ; SMLoc RegLoc ; if ( ! ParseRegister ( RegNo , RegLoc , StartLoc ) && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) { if ( RegNo == <STR_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , StartLoc ) ) ; Operands . push_back ( <STR_LIT> ( RegNo , StartLoc , StartLoc ) ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; } else return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) && ! Z ) { if ( ParseZ ( Z , consumeToken ( ) ) || ! Z ) return Error ( getLexer ( )


<s> if ( const <ISA_LIT>InstrRelaxTableEntry * I = lookupRelaxTable ( ShortOp ) )


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::


<s> static void ix86_emit_save_regs_using_mov ( rtx pointer , HOST_WIDE_INT offset ) { unsigned int regno ; rtx insn ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , true ) ) { insn = emit_move_insn ( adjust_address ( gen_rtx_MEM ( Pmode , pointer ) , Pmode , offset ) , gen_rtx_REG ( Pmode ,


<s> option_part ++ ; for ( ; fn -> name != NULL ; fn ++ ) { if ( ! strncmp ( fn -> name , token , length ) ) { fn -> parse_override ( option_part , tune ) ; return ; } } error ( <STR_LIT> ,


<s> bool isMemVX64X ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT>


<s> case VK_<ISA_LIT>_HIGH : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHER : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHERA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHEST


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( MemVT == <STR_LIT> && VT == <STR_LIT> ) ; SDValue Value = ST -> getValue ( ) ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; SDValue UndefVec = DAG . getBuildVector ( <STR_LIT> , DL , { Undef , Undef , Undef , Undef } ) ; SDValue TruncExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value , UndefVec ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , TruncExt ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc ) ; SDValue ExtractTrunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( ST -> getChain ( ) , DL , ExtractTrunc , ST

-> getBasePtr ( ) , ST -> getMemOperand ( ) ) ;


<s> unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( RHS ) return false ; ShReg = N . getOperand ( <NUM_LIT> ) ; if ( CheckProfitability && ! isShifterOpProfitable ( N , ShOpcVal ,


<s> bool <ISA_LIT>ELFAttributeData :: usingThumb ( ) const { int arch = m_Attrs [ Tag_CPU_arch ] . getIntValue ( ) ; if ( ( arch == CPU_Arch_<ISA_LIT>_V6_M ) || ( arch == CPU_Arch_<ISA_LIT>_V6S_M ) )


<s> float32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> , REGNO ( reg ) , DF_REF_INSN_UID ( def ) ) ; bitmap_set_bit ( regs , REGNO ( reg ) ) ; break ; } } } EXECUTE_IF_SET_IN_BITMAP ( regs , <NUM_LIT> , id , bi ) { for ( df_ref def = DF_REG_DEF_CHAIN ( id ) ; def ; def = DF_REF_NEXT_REG ( def ) ) if ( bitmap_bit_p ( candidates , DF_REF_INSN_UID ( def ) ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , DF_REF_INSN_UID ( def ) ) ; bitmap_clear_bit ( candidates , DF_REF_INSN_UID ( def ) ) ; } } BITMAP_FREE ( regs


<s> if ( Subtarget . hasVNNI ( ) && ! Subtarget . hasVLX ( ) ) RegSize = std :: max ( <NUM_LIT> , RegSize ) ; unsigned NumConcat = RegSize / Vi8VT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , Vi8VT ) ) ; Ops [ <NUM_LIT> ] = LHS ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue DpOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = RHS ; SDValue DpOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto DpBuilder = [ ] ( SelectionDAG & DAG , const SDLoc


<s> } if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue SRL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , R , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; SRL = DAG . getNode ( <STR_LIT> , dl , VT , SRL ) ; SmallVector < SDValue , <NUM_LIT> > V ( <NUM_LIT> , DAG . getConstant ( uint8_t ( - <NUM_LIT> ) >> ShiftAmt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SRL , DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , <NUM_LIT> ) ) ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ShiftAmt == <NUM_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Zeros , R ) ; } SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , R , Amt ) ; SmallVector < SDValue , <NUM_LIT> > V ( <NUM_LIT> , DAG . getConstant ( <NUM_LIT> >> ShiftAmt , <STR_LIT> ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , <NUM_LIT> ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , Mask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , Mask ) ; return Res ; } llvm_unreachable ( <STR_LIT> ) ; } } } if ( ! Subtarget -> is64Bit ( ) && ( VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) ) && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; unsigned RatioInLog2 = Log2_32_Ceil ( Ratio ) ; uint64_t ShiftAmt = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Amt . getOperand ( i ) ) ; if ( C == <NUM_LIT> ) return SDValue ( ) ; ShiftAmt |= C -> getZExtValue ( ) << ( i * ( <NUM_LIT> << ( <NUM_LIT> - RatioInLog2 ) ) ) ; } for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { uint64_t ShAmt = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Amt . getOperand ( i + j ) ) ; if ( C == <NUM_LIT> ) return SDValue (


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto CC = static_cast < <STR_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) .


<s> if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ) FVal = CN -> getValueAPF ( ) ; else if ( LoadSDNode * LN = dyn_cast < LoadSDNode > ( N ) ) { if ( LN -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || ! isa < ConstantPoolSDNode > ( LN -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantPoolSDNode * CN = dyn_cast < ConstantPoolSDNode > ( LN -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ; FVal = cast < ConstantFP > ( CN -> getConstVal ( ) ) -> getValueAPF ( ) ; } else return


<s> tree decl = SYMBOL_REF_DECL ( x ) ; return decl && ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) != NULL ) ; } return


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; APInt SplatBits ,


<s> uint32x4_t result = vcombine_u32 ( a , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) :


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVPTMaskOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int Value = MO . getImm ( ) ; int Imm = <NUM_LIT> ; unsigned PrevBit = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { unsigned Bit = ( Value >> i ) & <NUM_LIT> ; if ( ( Value & ~ ( ~ <NUM_LIT> << i ) ) == <NUM_LIT> ) { Imm |= ( <NUM_LIT> <<


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> if ( ! TOCEntry ) TOCEntry = createTempSymbol ( <STR_LIT> ) ; return TOCEntry


<s> const Function & F = MF . getFunction ( ) ; NeedsAsyncDwarfUnwindInfo = needsDwarfUnwindInfo ( ) && F . getUWTableKind ( ) == UWTableKind :: Async && ! F . hasMinSize ( ) ; } return *


<s> void llvm :: Lower<ISA_LIT>MachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , AsmPrinter & AP , bool isDarwin ) { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand ::


<s> name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = <STR_LIT> ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = <STR_LIT> ; else prefix = <STR_LIT> ; len = strlen ( name ) + strlen ( prefix ) ; string = alloca ( len + <NUM_LIT> ) ; sprintf ( string , <STR_LIT> , prefix , name ) ; DECL_SECTION_NAME ( decl ) = build_string ( len


<s> static inline bool is<ISA_LIT>_64ExtendedReg ( unsigned RegNo ) { switch ( RegNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static void darwin_rs6000_extra_signals ( void ) { struct sigaction sact ; stack_t sigstk ; sigstk . ss_sp = ( char * ) xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) <


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InFlag ) ; } } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant


<s> static const char * getNanName ( uint64_t flags ) { return flags & llvm :: ELF :: EF_MIPS_NAN2008 ? <STR_LIT>


<s> static inline bool isValidCoprocessorNumber ( unsigned Num , const FeatureBitset & featureBits ) { if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT>


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; unsigned SizeReg = MRI . createGenericVirtualRegister ( IntPtrTy ) ; MIRBuilder . buildConstant ( SizeReg , alignTo ( ValSize , PtrSize ) ) ; unsigned NewList = MRI . createGenericVirtualRegister (


<s> if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val ,


<s> for ( const auto & D : <ISA_LIT>FI -> getLOHContainer ( ) ) { for ( const MachineInstr * MI : D . getArgs ( ) ) { MInstToMCSymbol :: iterator LabelIt = LOHInstToLabel . find ( MI ) ; assert ( LabelIt != LOHInstToLabel . end ( ) && <STR_LIT> ) ; MCArgs . push_back ( LabelIt -> second


<s> if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only


<s> if ( OutStreamer . hasRawTextSupport (


<s> if ( set == - <NUM_LIT> ) set = new_alias_set


<s> int getVariadicGPRIdx ( ) const { return VariadicGPRIdx


<s> bool IsDangerousLoad ( const MachineInstr & MI , int * AddrIdx ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> )


<s> if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned CurReg = FirstReg - <NUM_LIT> ; CurReg >= RD0Reg && RegsNeeded ; -- CurReg ) { if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || isAnySubRegLive ( CurReg , TRI , MI ) ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ; MachineInstrBuilder MIB ( MF , &


<s> return __extension__ ( __m128d ) { __F ,


<s>
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
true
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
int
Reg
=
SavedRegs
.
find_first
(
)
;
Reg
!=
<NUM_LIT>
;
Reg
=
SavedRegs
.
find_next
(
Reg
)
)
dbgs
(
)
<<
' '
<<
PrintReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
bool
CanEliminateFrame
=
(
NumRegsSpilled
==
<NUM_LIT>
)
&&
!
hasVarSizedRegions
(
MF
)
;
unsigned
CFSize
=
MFI
->
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
NumRegsSpilled
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
uint64_t
StackRegionsSize
=
<NUM_LIT>
;
for
(
StackRegion
*
SR
:
MFI
->
getStackRegions
(
)
)
{
auto
*
SSR
=
static_cast
<
SVEVecStackRegion
*
>
(
SR
)
;
StackRegionsSize
+=
SSR
->
estimateRegionSize
(
MF
)
;
}
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
||
(
(
StackRegionsSize
/
<NUM_LIT>
)
>
<NUM_LIT>
)
||
(
hasFP
(
MF
)
&&
StackRegionsSize
>
<NUM_LIT>
)
||
(
!
hasFP
(
MF
)
&&
StackRegionsSize
>
<NUM_LIT>
&&
CFSize
>
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
&&
!
ExtraCSSpill
)
{
if
(
UnspilledCSGPR
!=
<STR_LIT>
)
{
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
PrintReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR


<s> vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc ( ( vec_float4


<s> <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Op -> getStartLoc ( ) , Context ) ; Operands . push_back ( Operands [ <NUM_LIT> ] ) ; unsigned ZeroReg = <STR_LIT> ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ) ZeroReg = <STR_LIT> ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateReg ( ZeroReg , false , Op2

-> getStartLoc ( ) , Op2 -> getEndLoc ( ) , Context ) ;


<s> SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) || VCMPOpcodeToVPT ( PredMI . MI -> getOpcode ( ) ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( ! ValidateLiveOuts ( ) ) return false ; Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; if ( ! MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> assert ( MO1 . isImm ( ) && <STR_LIT> ( MO1 . getImm ( ) ) && <STR_LIT> ) ; unsigned V1 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary )


<s> AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID )


<s> const int DENSITY_PENALTY = <NUM_LIT> ; struct loop * loop = data -> loop_info ; basic_block * bbs = get_loop_body ( loop ) ; int nbbs = loop -> num_nodes ; int vec_cost = data -> cost [ vect_body ] , not_vec_cost = <NUM_LIT> ; int i , density_pct ; for ( i = <NUM_LIT> ; i < nbbs ; i ++ ) { basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple * stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) &&

! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ;


<s> <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( StoreInsts , Offset ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( )


<s> if ( cfun -> is_thunk ) return true ; return cfun -> machine


<s> CCValAssign & VA = ArgLocs [ i ] ; switch ( VA . getLocInfo ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case CCValAssign :: Full : if ( Subtarget -> isABI_O32 ( ) && VA . isRegLoc ( ) ) { if ( VA . getValVT ( ) == <STR_LIT> && VA . getLocVT ( ) == <STR_LIT> ) Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . getLocVT ( ) == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) + <NUM_LIT> , Hi ) ) ; continue ; } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; LastArgStackLoc = ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ; int FI = MFI -> CreateFixedObject ( VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> , LastArgStackLoc ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , NULL , <NUM_LIT> ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain .


<s> static void setMatch ( <ISA_LIT>RelocationEntry & Hi , <ISA_LIT>RelocationEntry & Lo ) { Lo . HasMatchingHi


<s> void emitRRI ( unsigned Opcode , unsigned DstReg , unsigned SrcReg , int16_t Imm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { emitRRX ( Opcode , DstReg , SrcReg , MCOperand :: createImm ( Imm ) ,


<s> bool rs6000_is_valid_and_mask ( rtx mask , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == <NUM_LIT> || nb == <NUM_LIT> || ( nb < <NUM_LIT> && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < <NUM_LIT> && ne < <NUM_LIT>


<s> int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; int Offset = - <NUM_LIT> ; if ( MFI -> adjustsStack ( ) || IsPIC ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; SavedRegs . set ( <STR_LIT> ) ; Offset -= <NUM_LIT> ; } if ( hasFP ( MF ) ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; } if ( TRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset ,


<s> StringRef getPassName ( ) const override { return


<s> AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> if ( BYTES_BIG_ENDIAN ) { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno ) ; } else { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; } } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( words


_mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( InfoAndKind . Is<ISA_LIT> ) { CCVal = DAG . getConstant ( <STR_LIT> ( InfoAndKind . Info . <ISA_LIT> . CC ) , <STR_LIT> ) ; Cmp = * InfoAndKind . Info . <ISA_LIT> . Cmp ; } else Cmp = get<ISA_LIT>Cmp ( * InfoAndKind . Info . Generic . Opnd0 , * InfoAndKind . Info . Generic . Opnd1 , <STR_LIT> ( InfoAndKind . Info . Generic . CC , true ) , CCVal , DAG , dl ) ; EVT VT = Op -> getValueType


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFIClearUnwoundToCall (


<s> SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; SDValue SubN0 = Extract128BitVector ( N0 , N2 , DAG , dl ) ; SDValue ScaledN2 = N2 ; if ( Upper ) ScaledN2 = DAG . getNode ( <STR_LIT> , dl , N2 . getValueType ( ) , N2 , DAG . getConstant ( NumElems / ( VT . getSizeInBits ( ) / <NUM_LIT> ) , N2 . getValueType ( ) ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , SubN0 . getValueType ( ) , SubN0 , N1 , ScaledN2 ) ; return Insert128BitVector ( N0 , Op , N2 , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } return SDValue (


<s> Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; enableNarrowLdOpt && MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; if ( isPromotableZeroStoreOpcode ( Opc ) || ( EnableNarrowLdMerge && isNarrowLoad ( Opc ) ) ) { if ( tryToMergeLdStInst ( MBBI ) ) { Modified = true ; } else ++ MBBI ; } else ++ MBBI ; } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; switch ( MI -> getOpcode ( ) ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( tryToPairLdStInst ( MBBI ) ) { Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == <NUM_LIT>

&& Ty -> getStructElementType ( <NUM_LIT> ) -> isFP128Ty ( ) ) return true ;


<s> return ( strncmp ( section , templ , len ) == <NUM_LIT> && ( section [ len ] == <NUM_LIT> || section [ len


<s> } int k = i % LaneSize ; if ( InLaneMask [ k ] < <NUM_LIT> ) { InLaneMask [ k ] = Mask [ i ] % LaneSize ; } else if ( InLaneMask [ k ] != Mask [ i ] % LaneSize ) { return SDValue ( ) ; } } MVT LaneVT = <STR_LIT> ( VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LaneMask ( ( unsigned ) NumLanes * <NUM_LIT> , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL ,


<s> Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , RSFIN , FIN , MachinePointerInfo ( SV ,


<s> SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo


<s> bool sh_cfun_trap_exit_p ( void ) { return ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ==


<s> SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , xFGETSIGN , DAG . getConstant ( <NUM_LIT>


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) { StackAlign = TM . getFrameLowering ( )


<s> case V16HImode : gen = gen_avx2_pbroadcastv16hi_1 ; break ; case V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16si_1 ; break ; case V8SImode : gen = gen_avx2_pbroadcastv8si_1 ; break ; case V16QImode : gen = gen_avx2_pbroadcastv16qi ; break ; case V8HImode : gen = gen_avx2_pbroadcastv8hi ; break ; case V16SFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16sf_1 ; break ; case V8SFmode : gen = gen_avx2_vec_dupv8sf_1 ; break ; case V8DFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8df_1 ; break ; case V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { perm2 [ i ] = d -> perm [ i ] & mask ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { perm2 [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; perm2 [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; } } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt , d -> testing_p ) ) return true ; if ( ! d -> one_operand_p ) { for ( i = <NUM_LIT> ; i


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> return __builtin_loongson_psubw_s ( s , t


<s> bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( DestIsHigh && SrcIsHigh ) Opcode = <STR_LIT> ; else if ( DestIsHigh && ! SrcIsHigh ) Opcode = <STR_LIT> ; else if ( ! DestIsHigh && SrcIsHigh ) Opcode = <STR_LIT> ; else { BuildMI ( MBB , MBBI , DL , get ( LowLowOpcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> :


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo (


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler


<s> const char * rs6000_indirect_sibcall_template ( rtx * operands , unsigned int


<s> return __builtin_mve_vldrbq_z_uv8hi ( ( __builtin_neon_qi * ) __base ,


<s> void <ISA_LIT>FrameLowering :: splitSPAdjustments ( uint64_t Total , uint64_t & Initial , uint64_t & Residual ) const { if ( Total <=


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins


<s> bool <ISA_LIT>ParallelDSP :: InsertParallelMACs ( Reduction & Reduction , PMACPairList & PMACPairs ) { Instruction * Acc = Reduction . Phi ; Instruction * InsertAfter = Reduction . AccIntAdd ; for ( auto & Pair : PMACPairs ) { BinOpChain * PMul0 = Pair . first ; BinOpChain * PMul1 = Pair . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; PMul0 -> Root -> dump ( ) ; dbgs ( ) << <STR_LIT> ; PMul1 -> Root -> dump ( ) ) ; auto * VecLd0 = cast < LoadInst > ( PMul0 -> VecLd [ <NUM_LIT> ] ) ; auto * VecLd1 = cast < LoadInst > ( PMul1 -> VecLd [ <NUM_LIT> ] ) ; Acc = CreateSMLADCall ( VecLd0 , VecLd1 , Acc , PMul1 -> Exchange , InsertAfter ) ; InsertAfter =


<s> ggc_add_rtx_root ( & mips_load_reg3 , <NUM_LIT> ) ; ggc_add_rtx_root ( & mips_load_reg4 , <NUM_LIT> ) ; ggc_add_rtx_root ( branch_cmp , sizeof ( branch_cmp ) / sizeof ( rtx


<s> sprintf ( l1size , <STR_LIT> , l1_sizekb ) ; sprintf ( line , <STR_LIT> , l1_line ) ; sprintf ( l2size , <STR_LIT>


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; return S


<s> KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , <NUM_LIT> ) ; computeKnownBits ( DAG , Op . getOperand ( <NUM_LIT> ) , KnownZero ,


<s> emit_insn ( gen_rtx_SET ( reg , u ) ) ; return reg ; } if ( DEFAULT_ABI == ABI_ELFv2 ) base = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; else { if ( flag_pic ) base = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; regno = <NUM_LIT> ; } rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx hi = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base , call_ref , arg ) , UNSPEC_PLT16_HA ) ; rtx lo = gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , reg , call_ref , arg ) , UNSPECV_PLT16_LO ) ; emit_insn ( gen_rtx_SET ( reg , hi ) ) ; emit_insn ( gen_rtx_SET ( reg


<s> assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII ->

getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ;


<s> rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ <NUM_LIT> ] , code , & operands [ <NUM_LIT> ] , & operands [ <NUM_LIT> ] ) ; if ( code == UNKNOWN ) { rtx temp ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case LTGT : temp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , ORDERED , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , NE , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , NULL , NULL ) ; code = AND ; break ; case UNEQ : temp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , UNORDERED , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , EQ , operands [ <NUM_LIT> ] , operands [


<s> return PairDRegs ( VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> static bool csky_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CSKY_CC_REGNUM ; * p2 = INVALID_REGNUM ; return true


<s> case GTU : case GEU : case LTU : unspec_code = UNSPEC_UNSIGNED_PCMP ; break ; default : unspec_code = UNSPEC_PCMP ; } unspec = gen_rtx_UNSPEC ( mask_mode , gen_rtvec ( <NUM_LIT> , cmp_op0 , cmp_op1 , imm ) , unspec_code ) ; emit_insn ( gen_rtx_SET ( dest , unspec


<s> if ( TargetTriple . getArch ( ) == Triple :: ppc64le ) CPUName = <STR_LIT> ; else if ( TargetTriple . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_spe ) CPUName = <STR_LIT> ; else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( ) ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le


<s> Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic =


<s> __inline__ static unsigned long long sh_media_MEXTR6 ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> SDLoc DL ( N ) ; int TagOffset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * N1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ; SDNode * N2 = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { SDValue

( N1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; int Size ; if ( Desc . getSize ( ) == <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) Size = Desc . getSize ( ) ; else llvm_unreachable ( <STR_LIT> ) ; uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( isThumb ( STI ) && Size == <NUM_LIT> ) { EmitConstant ( Binary >> <NUM_LIT> ,


<s> if ( Structors . empty ( ) ) return ; unsigned Index = <NUM_LIT> ; for ( Structor & S : Structors ) { if ( const ConstantExpr * CE = dyn_cast < ConstantExpr > ( S .

Func ) ) S . Func = CE -> getOperand ( <NUM_LIT> ) ;


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return <NUM_LIT> ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? <NUM_LIT> : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset


<s> return ( ! TARGET_64BIT && arg . mode == TImode && arg .

type && TREE_CODE ( arg . type ) != VECTOR_TYPE ) ;


<s> if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; return PerformADDCombineWithOperands ( N , N1 , N0


<s> create_input_operand ( & ops [ <NUM_LIT> ] , value0 , TYPE_MODE ( TREE_TYPE ( arg0 ) ) ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) error


<s> opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_explicit_arch = ptr


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: DefaultMemSIOperand ( SMLoc Loc ) { unsigned basereg = is64BitMode ( ) ? <STR_LIT> : (


<s> case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , getPointerTy ( ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Args [ ] = { Offset } ; SDValue Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; } assert ( false && <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> )


<s> SDValue Value = Mst -> getValue ( ) ; if ( Value . getOpcode ( ) == <STR_LIT> && Value . getNode ( ) -> hasOneUse ( ) && TLI . isTruncStoreLegal ( Value . getOperand ( <NUM_LIT> ) . getValueType ( ) , Mst -> getMemoryVT ( ) ) ) { return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Value . getOperand ( <NUM_LIT> ) , Mst -> getBasePtr ( ) , Mask , Mst -> getMemoryVT ( ) , Mst ->


<s> EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc DL = HiPart . getDebugLoc ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiPart ,


<s> SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N )


<s> assert ( ( PhysReg >= <STR_LIT> && <STR_LIT> <=


<s> OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Val = Op1 . second - Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_MULTIPLY : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = Op1 . second * Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_DIVIDE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; assert ( Op2 . second != <NUM_LIT> && <STR_LIT> ) ; Val = Op1 . second / Op2 . second ; OperandStack . push_back ( std :: make_pair


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand (


<s> unsigned Off = LoLoop . Dec == LoLoop . End ? <NUM_LIT> : <NUM_LIT> ; MIB . add ( End -> getOperand ( Off + <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( Off + <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( LoLoop . Dec ) ; LoLoop . ToRemove . insert ( End ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( isWhileLoopStart ( * LoLoop . Start ) )


<s> if ( frame_pointer_needed ) mask |= <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > <NUM_LIT> ) mask |= <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & <NUM_LIT> || thumb_force_lr_save ( ) ) mask |= ( <NUM_LIT> << LR_REGNUM ) ; if ( ( mask & <NUM_LIT> ) == <NUM_LIT> && ( ( mask & <NUM_LIT> ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( <NUM_LIT> << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= <NUM_LIT> << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= <NUM_LIT> ) { for ( reg = LAST_ARG_REGNUM + <NUM_LIT> ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( <NUM_LIT> << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= <NUM_LIT> << LAST_LO_REGNUM ; } } return mask


<s> if ( tmp == NULL_RTX ) return <NUM_LIT> ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align ,


<s> MI . clear ( ) ; result = decodeThumb2Instruction16 ( MI , insn16 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ! ITBlock . empty ( ) ) result = MCDisassembler :: SoftFail ; Check ( result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Mask >> <NUM_LIT> & <NUM_LIT> ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITBlock . insert ( ITBlock . begin ( ) , firstcond ) ; else ITBlock . insert ( ITBlock . begin ( ) , firstcond ^ <NUM_LIT> ) ; } ITBlock . push_back ( firstcond ) ; } return result ; } if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes , NULL ) == - <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeThumbInstruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . size ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return


<s> assert ( <STR_LIT> ( ShiftOpnd ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = <STR_LIT> ( ShiftOpnd ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; auto Immediate = MI . getOperand ( OpIdx ) .


<s> MachineFunction :: iterator MBBI = MBB ; if ( llvm :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = llvm :: next ( MBBI ) ; for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if (


<s> assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy ) ) ) Scalarize = true ; if ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX


<s> } safe_inc_pos ( ) ; const char * stanza_name = match_to_right_bracket ( ) ; if ( ! stanza_name ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } curr_bif_stanza = stanza_name_to_stanza ( stanza_name ) ; if ( linebuf [ pos ] != ']' ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } safe_inc_pos ( ) ; consume_whitespace ( ) ; if ( linebuf [ pos ] != '\n' && pos != LINELEN -


<s> case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } Optional < MCFixupKind > getFixupKind ( StringRef Name ) const override ; const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } Optional < MCFixupKind > <ISA_LIT>MCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_390_NONE ) . Case ( <STR_LIT> , ELF :: R_390_8 ) . Case ( <STR_LIT> , ELF :: R_390_16 ) . Case ( <STR_LIT> , ELF :: R_390_32 ) . Case ( <STR_LIT> , ELF :: R_390_64 ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend ::


<s> for ( bs0 = <NUM_LIT> ; bs0 < <NUM_LIT> ; bs0 ++ ) if ( ( mask & ( <NUM_LIT> << bs0 ) ) != <NUM_LIT> ) break ; for ( bs1 = bs0 ; bs1 < <NUM_LIT> ; bs1 ++ ) if ( ( mask & (

<NUM_LIT> << bs1 ) ) == <NUM_LIT> ) break ;


<s> unsigned SEH = MRI -> getEncodingValue ( Reg ) ; MRI -> mapLLVMRegToSEHReg ( Reg ,


<s> SDLoc DL ( N ) ; SDValue Data = N -> getOperand ( <NUM_LIT> ) ; EVT DataVT = Data . getValueType ( ) ; EVT HwSrcVt = getSVEContainerType ( DataVT ) ; SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew ; if ( Data . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , InputVT } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType (


<s> const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT ,


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT


<s> case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg =


<s> if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return & <STR_LIT> ; assert ( B == & <STR_LIT> && <STR_LIT> ) ; if ( A == & <STR_LIT> ) return A ; return & <STR_LIT> ; } if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return & <STR_LIT> ; return & <STR_LIT> ; } if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return <NUM_LIT> ; return & <STR_LIT> ; } assert ( A -> getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return & <STR_LIT> ; if ( B == & <STR_LIT> ) return <NUM_LIT> ; return A ; } if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return & <STR_LIT> ; if ( B == & <STR_LIT> ) return <NUM_LIT> ; return A ; } assert ( A -> getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( B != & <STR_LIT> ) return <NUM_LIT> ; return A ; } case <STR_LIT>


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI -> setStackSize (


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getValueSizeInBits ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; unsigned NumSrcEltBits = N00 . getScalarValueSizeInBits ( ) ; APInt ZeroMask = APInt :: getHighBitsSet ( NumSrcEltBits ,