<s> int NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; unsigned Start = <NUM_LIT> ; unsigned End = NumLaneElts ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = Start , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != End ; i += <NUM_LIT> , ++ j


<s> if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Align >= <NUM_LIT> && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Ops [ ] = { Base , NewOffset , CurDAG -> getTargetConstant ( Pred , SDLoc ( N ) , <STR_LIT> ) , PredReg , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Ops ) ; transferMemOperands ( N ,


<s> return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; bool SetFlags = false ; if ( AllowFlags ) { if ( auto * Def = SearchForDef ( MI , MBB -> end ( ) , <STR_LIT> ) ) { if ( ! SearchForUse ( MI , MBB -> end ( ) , <STR_LIT> ) && Def -> getOpcode ( ) == <STR_LIT> ) SetFlags = true ; } } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ; if ( SetFlags ) { MIB . addReg ( <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue Address = Op -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Op -> getOperand ( <NUM_LIT> ) ; EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getStore ( ChainIn , DL , Value , Address , MachinePointerInfo (


<s> return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC ==


<s> } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bextr_u64 ( unsigned long


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT>


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveMachine ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) && getLexer ( ) . isNot ( AsmToken :: String ) ) { Error ( L , <STR_LIT> ) ; return false ; } StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( L , <STR_LIT> ) ; return false ; } <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPU


<s> if ( rs6000_builtin_decls [ ( int ) code ] ) fatal_error ( input_location , <STR_LIT> , name ) ; rs6000_builtin_decls [ ( int ) code ] = t = add_builtin_function ( name , type , ( int ) code , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( ( classify & RS6000_BTC_CONST ) != <NUM_LIT> ) { TREE_READONLY ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_PURE ) != <NUM_LIT> ) { DECL_PURE_P ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_FP ) != <NUM_LIT> ) { TREE_NOTHROW ( t ) = <NUM_LIT> ; if ( flag_rounding_math ) { DECL_PURE_P ( t ) = <NUM_LIT> ; DECL_IS_NOVOPS ( t ) =


<s> Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_HA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR16_HA : Type = ELF :: R_<ISA_LIT>_ADDR16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR16_LO : Type = ELF :: R_<ISA_LIT>_ADDR16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_ENTRY : Type = ELF :: R_<ISA_LIT>64_TOC16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_LO ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF


<s> Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Trunc_bits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( Shl_imm >= VT . getSizeInBits ( ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false ; } uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; assert ( Srl_imm > <NUM_LIT> && Srl_imm < VT . getSizeInBits ( ) && <STR_LIT> ) ; int immr = Srl_imm - Shl_imm ; Immr = immr < <NUM_LIT> ? immr + VT .


<s> return false ; } MCSymbolELF * Sym = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Lex (


<s> if ( count != <NUM_LIT> ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM


<s> SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; MachineMemOperand * MMO = ST -> getMemOperand ( ) ; Value = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Value ) ; return DAG . getTruncStore ( Chain , dl ,


<s> } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ; SDNode * AD = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> , dl ) ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( AD , <NUM_LIT> ) , Op , SDValue ( AD , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue AN = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , AD , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { AN , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) ; } } } } SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) . isVector ( ) ) { if ( <ISA_LIT>SubTarget -> hasQPX ( ) ) return nullptr ; EVT VecVT = LHS . getValueType ( ) ; bool Swap ,


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF


<s> bool <ISA_LIT>AsmParser :: MatchRegisterName ( unsigned & RegNo , int64_t & IntVal ) { if ( getParser ( ) . getTok ( ) . is ( AsmToken :: Percent ) ) getParser ( ) . Lex ( ) ; if ( ! getParser ( ) . getTok ( ) . is ( AsmToken :: Identifier ) ) return true ; StringRef Name = getParser ( ) . getTok ( ) . getString ( ) ; if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> )

. getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) {


<s> SDLoc dl ( Op ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> ,


<s> if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : * Visited ) { auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) continue ; if ( Sources -> count ( I ) || Sinks -> count ( I ) ) continue ; if ( ! shouldPromote ( I ) || SafeToPromote -> count ( I ) || NewInsts . count ( I ) ) continue ; assert ( EnableDSP && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; Function * DSPInst = <STR_LIT> ( M , getNarrowIntrinsic ( I ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Args [ ] = { I -> getOperand (

<NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) } ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: restoreWin32EHStackPointers ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool RestoreSP ) const { assert ( STI . isTargetWindowsMSVC ( ) && <STR_LIT> ) ; assert ( STI . isTargetWin32 ( ) && <STR_LIT> ) ; assert ( STI . is32Bit ( ) && ! Uses64BitFramePtr && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; Register FramePtr = TRI -> getFrameRegister ( MF ) ; Register BasePtr = TRI -> getBaseRegister ( ) ; WinEHFuncInfo & FuncInfo = * MF . getWinEHFuncInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI . getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned UsedReg ; int EHRegOffset = getFrameIndexReference ( MF ,


<s> case <STR_LIT> : return expandAtomicRMW128 ( MBB , MI , NMBBI ) ; case <STR_LIT> : return expandAtomicCmpSwap128 ( MBB , MI , NMBBI ) ; case <STR_LIT> : { Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstHi = TRI -> getSubReg ( Dst , <STR_LIT> ) ; Register DstLo = TRI -> getSubReg ( Dst , <STR_LIT> ) ; Register Lo = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Hi = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; PairedCopy ( TII , MBB , MI , MI . getDebugLoc ( ) , DstHi , DstLo , Hi


<s> return ( int ) __builtin_ia32_vcvttss2si32 ( ( __v4sf ) __A ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerANDOR ( SDValue Op , SelectionDAG & DAG ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant (


<s> inline static unsigned getTruncatedShiftCount ( const MachineInstr & MI , unsigned ShiftAmtOperandIdx ) { unsigned ShiftCountMask = ( MI . getDesc ( ) . TSFlags &


<s> Type * ConsideredSExtType = Type :: getInt64Ty ( I . getParent ( ) -> getParent ( ) -> getContext ( ) ) ; if ( I . getType ( ) != ConsideredSExtType ) return false ; for ( const User * U : I . users ( ) ) { if ( const GetElementPtrInst * GEPInst = dyn_cast < GetElementPtrInst > ( U ) ) { Considerable = true ; if ( GEPInst -> getNumOperands ( ) > <NUM_LIT>


<s> if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> && <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Tmp ) ; BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> eraseFromParent ( )


<s> break ; } } if ( Subtarget . has<ISA_LIT>32r6 ( ) && ( I -> getNumOperands ( ) > <NUM_LIT> ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) || canUseShortMicro<ISA_LIT>CTI ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( <STR_LIT> , DL , { LoadVT , <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; SDValue


<s> unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo ,


<s> if ( __count <= <NUM_LIT> ) { m = ( __vector unsigned short ) vec_splats ( __m ) ; c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; r = vec_sr ( m , ( __vector unsigned short ) c ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) r , <NUM_LIT>


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerBUILD_<ISA_LIT>CTOR ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG )


<s> int size = bytesize ( type , BLKmode ) ; if ( TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return size > <NUM_LIT>


<s> linkExceptionRegistration ( Builder , Trampoline ) ; CxxLongjmpUnwind = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getVoidTy ( TheModule -> getContext ( ) ) , Int8PtrType , false ) ) ; cast < Function > ( CxxLongjmpUnwind -> stripPointerCasts ( ) ) -> setCallingConv ( CallingConv :: <ISA_LIT>_StdCall ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { RegNodeTy = getSEHRegistrationType ( ) ; RegNode = Builder . CreateAlloca ( RegNodeTy ) ; Value * SP = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , { } ) ; Builder . CreateStore ( SP , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; StateFieldIndex = <NUM_LIT> ; StringRef PersonalityName = PersonalityFn -> getName ( ) ; UseStackGuard = ( PersonalityName == <STR_LIT> ) ; ParentBaseState = UseStackGuard ? - <NUM_LIT> : - <NUM_LIT> ; insertStateNumberStore ( & * Builder . GetInsertPoint ( ) , ParentBaseState ) ; Value * LSDA = emitEHLSDA ( Builder , F ) ; Type * Int32Ty = Type :: getInt32Ty ( TheModule -> getContext ( ) ) ; LSDA = Builder . CreatePtrToInt ( LSDA , Int32Ty ) ; if ( UseStackGuard ) { Cookie = TheModule -> getOrInsertGlobal ( <STR_LIT> , Int32Ty ) ; Value * Val = Builder . CreateLoad ( Int32Ty , Cookie ) ; LSDA = Builder . CreateXor ( LSDA , Val ) ; } Builder . CreateStore ( LSDA , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; Link = Builder . CreateStructGEP ( RegNodeTy ,


<s> if ( mode == MODE_none ) { if ( mode_suffix_id == MODE_offset ) error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , get_argument_type ( argno + <NUM_LIT> ) ) ; else error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , get_argument_type (


<s> switch ( SVT ) { case <STR_LIT> : case <STR_LIT> : if ( Fast ) * Fast = true ; return


<s> bool OptForSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; if ( ! OptForSize && Subtarget -> isSHLDSlow ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT

, Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |=


<s> name = targetm . strip_name_encoding ( name ) ; if ( beimport ) prefix = name [ <NUM_LIT> ] == FASTCALL_PREFIX || user_label_prefix [ <NUM_LIT> ] == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else prefix = user_label_prefix [ <NUM_LIT> ] == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; namelen = strlen ( name ) ; prefixlen = strlen ( prefix ) ; imp_name = ( char * ) alloca ( namelen + prefixlen + <NUM_LIT> ) ; memcpy ( imp_name , prefix , prefixlen ) ; memcpy ( imp_name + prefixlen , name , namelen + <NUM_LIT> ) ; name = ggc_alloc_string ( imp_name , namelen + prefixlen ) ; rtl = gen_rtx_SYMBOL_REF ( Pmode , name ) ; SET_SYMBOL_REF_DECL ( rtl , to ) ; SYMBOL_REF_FLAGS ( rtl ) = SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_STUBVAR ; if ( ! beimport ) { SYMBOL_REF_FLAGS ( rtl ) |= SYMBOL_FLAG_EXTERNAL ; SUB_TARGET_RECORD_STUB ( name )


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; } bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return


<s> expand_float ( xa , xi , <NUM_LIT> ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; emit_move_insn ( res , xa ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; emit_move_insn ( operand0 ,


<s> } else { const MCRegisterInfo & MRI = * CTX . getRegisterInfo ( ) ; if ( ! CLRMRegs ) { assert ( std :: is_sorted ( MI . begin ( ) + Op , MI . end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; } for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo ; if ( CLRMRegs && MI . getOperand ( I ) . getReg ( )


<s> Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy ,


<s> vector_size = GET_MODE_SIZE ( vector_mode ) ; gcc_assert ( reg_size % vector_size == <NUM_LIT> ) ; nvectors = reg_size / vector_size ; gcc_assert ( POINTER_TYPE_P ( type ) ) ; elem_type = TREE_TYPE ( type ) ; if ( mem_mode == reg_mode ) nelems = vector_size * nvectors / int_size_in_bytes ( elem_type ) ; else nelems


<s> return __builtin_aarch64_ushlv4hi_uus ( __a ,


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : <NUM_LIT> ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM ) ?

RS6000_BTM_HTM : <NUM_LIT> ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : <NUM_LIT> ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : <NUM_LIT> ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : <NUM_LIT> ) ) ;


<s> if ( Kind . isData ( ) && IsGlobalInSmallSection ( GO , TM , Kind ) ) return SmallDataSection ; if ( Kind . isReadOnly ( ) && IsGlobalInSmallSection ( GO , TM , Kind )


<s> using namespace TargetOpcode ; MIRBuilder . setInstr ( MI ) ; return


<s> const unsigned SrcSz = SrcVal . getValueType ( ) . getSizeInBits ( ) ; assert ( DstSz > SrcSz && DstSz <= <NUM_LIT> && SrcSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ; assert ( ! ( DstSz == <NUM_LIT> && Subtarget -> hasFP16 ( ) ) && <STR_LIT> ) ; if ( SrcSz == <NUM_LIT> && DstSz == <NUM_LIT> && Subtarget -> hasFP64 ( ) ) { if ( IsStrict ) { SDLoc Loc ( Op ) ; SDValue Result = DAG . getNode ( <STR_LIT> , Loc , Op . getValueType ( ) , SrcVal ) ; return DAG . getMergeValues ( { Result , Op . getOperand ( <NUM_LIT> ) } , Loc ) ; } return Op ; } SDLoc Loc ( Op ) ; RTLIB :: Libcall LC ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; for ( unsigned Sz = SrcSz ; Sz <= <NUM_LIT> && Sz < DstSz ; Sz *= <NUM_LIT> ) { bool Supported = ( Sz == <NUM_LIT> ? Subtarget -> hasFP16 ( ) : Subtarget -> hasFP64 ( ) ) ; MVT SrcVT = ( Sz == <NUM_LIT> ? <STR_LIT>


<s> static bool isLEA ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9 ; } else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true


<s> emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( <STR_LIT> ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> )


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N


<s> Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc TypeLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * Val = nullptr ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return nullptr ; if ( ! Info . OpDecl ) return ErrorOperand ( Start , <STR_LIT> ) ; unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Length ; break ; case IOK_SIZE : CVal = Info . Size ; break ; case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Imm , TypeLoc , Len , CVal ) ; const MCExpr * Imm = MCConstantExpr :: create ( CVal , getContext ( ) ) ; return <STR_LIT> ( Imm , Start , End


<s> return ( __m512d ) __builtin_ia32_scalefpd512_mask ( ( __v8df ) __A , ( __v8df ) __B , (


<s> RegisterTarget < Triple :: leg > X ( The<ISA_LIT>Target


<s> unsigned IncrementIndex = Phi -> getIncomingBlock ( <NUM_LIT> ) == L -> getLoopLatch ( ) ? <NUM_LIT> : <NUM_LIT> ; Offsets = Phi -> getIncomingValue ( IncrementIndex ) ; std :: pair < Value * , int64_t > Add = getVarAndConst ( Offsets , TypeScale ) ; if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; if ( OffsetsIncoming != Phi ) return nullptr ; Builder . SetInsertPoint ( & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; unsigned NumElems = cast < FixedVectorType > ( OffsetsIncoming -> getType ( ) ) -> getNumElements ( ) ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , Phi -> getIncomingValue ( <NUM_LIT> - IncrementIndex ) , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( NumElems , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Sub , OffsetsIncoming , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( Immediate ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; Phi -> setIncomingValue ( <NUM_LIT> - IncrementIndex , OffsetsIncoming ) ; Builder . SetInsertPoint ( I ) ; Instruction * EndResult ; Instruction * NewInduction ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) { Value * Load = tryCreateMaskedGatherBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = ExtractValueInst :: Create ( Load , <NUM_LIT> , <STR_LIT> ) ; NewInduction = ExtractValueInst :: Create ( Load , <NUM_LIT> , <STR_LIT> ) ; Builder . Insert ( EndResult ) ; Builder . Insert ( NewInduction ) ; } else { EndResult = NewInduction = tryCreateMaskedScatterBaseWB ( I , Phi , Builder , Immediate ) ; } Instruction * AddInst = cast < Instruction > (


<s> unsigned getMemBase ( ) const { assert ( ( Kind == k_Memory


<s> Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT>


<s> Align <ISA_LIT>ConstantIslands :: getCPEAlign ( const MachineInstr & CPEMI ) { assert ( CPEMI . getOpcode ( ) == <STR_LIT> ) ; unsigned CPI = CPEMI . getOperand ( <NUM_LIT> ) .


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint

, MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( BaseReg , L , L ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) return <NUM_LIT> ; if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . ParseAbsoluteExpression ( Value ) ) return <NUM_LIT> ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT>


<s> vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc ( (


<s> SDNode * OrOpd1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , std :: swap ( OrOpd0 , OrOpd1 ) , OrOpd1Val = N -> getOperand ( <NUM_LIT> ) ) { unsigned BFXOpc ; int DstLSB , Width ; if ( isBitfieldExtractOp ( CurDAG , OrOpd0 , BFXOpc , Src , ImmR , ImmS , NumberOfIgnoredLowBits , true ) ) { if ( ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) || ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) ) continue ; DstLSB = <NUM_LIT> ; Width = ImmS - ImmR + <NUM_LIT> ; if ( Width <= <NUM_LIT> ) continue ; } else if ( isBitfieldPositioningOp ( CurDAG , SDValue ( OrOpd0 , <NUM_LIT> ) , Src , DstLSB , Width ) ) { ImmR = ( VT . getSizeInBits ( ) - DstLSB ) % VT . getSizeInBits ( ) ; ImmS = Width - <NUM_LIT> ; } else continue ; EVT VT = OrOpd1 -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; APInt KnownZero , KnownOne ; CurDAG -> computeKnownBits ( OrOpd1Val , KnownZero , KnownOne ) ; APInt BitsToBeInserted = APInt :: getBitsSet ( KnownZero . getBitWidth ( ) , DstLSB , DstLSB + Width ) ; if ( ( BitsToBeInserted & ~ KnownZero ) != <NUM_LIT> ) continue ; uint64_t Imm ; if ( isOpcWithIntImmediate ( OrOpd1 , <STR_LIT> , Imm ) && isBitfieldDstMask ( Imm , BitsToBeInserted , NumberOfIgnoredHighBits , VT ) ) Dst = OrOpd1 -> getOperand ( <NUM_LIT> ) ; else Dst =


<s> return ( __m256 ) __builtin_ia32_cvtudq2ps256_mask ( ( __v8si ) __A , ( __v8sf )


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; unsigned Opc = <NUM_LIT> ; bool Offset = true ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc =


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Form = TID . TSFlags & <STR_LIT> ; bool IsPrePost = ( TID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |= <STR_LIT> ( AM2Opc ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO2 . getReg ( ) ) ) ; Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( AM2Opc ) ) { Binary |= getShiftOp (


<s> return ( isPromotableZeroStoreOpcode ( MI ) ) && getLdStRegOp ( MI ) . getReg (


<s> unsigned <ISA_LIT>MCCodeEmitter :: NEONThumb2DupPostEncoder ( const MCInst & MI , unsigned EncodedValue ) const { if ( isThumb2 ( ) ) { EncodedValue &= <NUM_LIT> ; EncodedValue |= <NUM_LIT> ; } return EncodedValue


<s> return __builtin_mve_vshlq_n_sv4si ( __a ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> else if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT>


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( StringRef Name ) { const <ISA_LIT>CallEntry * & E = ExternalCallEntries [ Name ] ; if ( ! E ) E = new <ISA_LIT>CallEntry


<s> if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; LHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS2 , Mask ) ; RHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS2 , Mask ) ; <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC (


<s> void <ISA_LIT>InstPrinter :: printS16X4ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) ( MI -> getOperand ( OpNo ) . getImm ( )


<s> return ( uint64x2_t ) __builtin_aarch64_ushll2_nv4si ( ( int32x4_t ) __a ,


<s> fprintf ( asm_out_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value ) ; } pool_size = <NUM_LIT> ; } return <STR_LIT>


<s> else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( OpNo + <NUM_LIT> )


<s> return ( int32x4_t ) __builtin_neon_vrsras_nv4si ( __a ,


<s> Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } getTargetStreamer ( ) . emitObjectArch ( ID ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( getLexer ( ) . getLoc ( ) ,


<s> bool isReg ( ) const override { return Kind ==


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const Value * Op2 = I . getArgOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; if ( I . getIntrinsicID ( ) == <STR_LIT> ) Opc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> rtx mem ; mem = gen_rtx_MEM ( mode , plus_constant ( stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode ,


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes =


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op


<s> if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { unsigned RBegin , REnd ; CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false


<s> } else if ( size == <NUM_LIT> ) MachineBasicBlock :: iterator CLEAR = BuildMI ( * BBi , MCi , MCi -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addImm ( <NUM_LIT> ) ; else if ( size == <NUM_LIT> ) MachineBasicBlock :: iterator CLEAR = BuildMI ( * BBi , MCi , MCi -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addImm ( <NUM_LIT> ) ; else if ( size == <NUM_LIT> ) MachineBasicBlock :: iterator CLEAR = BuildMI ( * BBi , MCi , MCi -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState ::


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG , const bool isIndirect ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; assert ( Subtarget -> supportsTailCall ( ) ) ; if ( Outs . size ( ) >= <NUM_LIT> && ( ! isa < GlobalAddressSDNode > ( Callee . getNode ( ) ) || isIndirect ) ) { if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ) return false ; } if ( CallerF . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CalleeCC == CallerCC ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF


<s> static __inline vec_ullong2 spu_testsv ( vec_double2 a , char b ) { return ( ( vec_ullong2 ) ( si_dftsv ( ( qword ) ( a ) , b


<s> static unsigned char getVEXRegisterEncoding ( const MCInst & MI , unsigned OpNum ) { unsigned SrcReg = MI . getOperand ( OpNum ) . getReg ( ) ; unsigned SrcRegNum = Get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) ) ; if ( <STR_LIT> ( SrcReg )


<s> LLVM_FALLTHROUGH ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val ,


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >=


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant ,


<s> Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; return CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; } else { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , AMOpc , getAL ( CurDAG ) , CurDAG -> getRegister


<s> ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> )


<s> unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX512 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 (

NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ;


<s> static struct unw_reg_state * dup_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * copy , * prev = NULL , * first = NULL ; while ( rs ) { copy = alloc_reg_state ( ) ; memcpy ( copy , rs , sizeof ( *


<s> if ( arm_disable_literal_pool && SYMBOL_REF_P ( x ) && CONSTANT_POOL_ADDRESS_P (


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = isStackAligned ? <STR_LIT> : <STR_LIT> ; } else if ( RC ==


<s> std :: make_unique < GenericScheduler > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasStoreFusion ( ) ) DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createPowerPCMacroFusionDAGMutation ( ) ) ; return


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; if ( ST . hasArithmeticBccFusion ( ) && isArithmeticBccPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstMI , SecondMI )


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability


<s> StackOffset <ISA_LIT>FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > (

N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ;


<s> return ( ( GET_CODE ( x ) == ASHIFT || GET_CODE ( x ) == MULT ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( ( GET_CODE ( x ) == ASHIFT && pa_shadd_constant_p ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) || ( GET_CODE ( x ) == MULT && pa_mem_shadd_constant_p ( INTVAL ( XEXP ( x


<s> MIRef I = WorkList . pop_back_val ( ) ; if ( ! VisitedOrInserted . count ( I ) ) { if ( ! BBVisitedInfo [ I . MBB ] . TileCfgForbidden ) { InsertPoints . insert ( I ) ; } else { VisitedOrInserted . insert ( I ) ; for ( auto * Succ : I . MBB -> successors ( ) ) if ( BBVisitedInfo [ Succ ] . NeedTileCfgLiveIn ) WorkList . push_back ( MIRef ( Succ ) ) ; } } } for ( MIRef I : InsertPoints ) { if ( ShapeBBs . count ( I . MBB ) && I < ShapeBBs [ I . MBB ] . back ( ) ) I = ShapeBBs [ I . MBB ] . back ( ) ; if ( VisitedOrInserted . insert ( I ) . second ) { auto II = I . MI ? I . MI -> getIterator ( ) : I . MBB -> instr_begin ( ) ; addFrameReference ( BuildMI ( * I . MBB , ++ II , DL , TII -> get ( <STR_LIT> ) ) , SS ) ; } } } MachineBasicBlock & MBB = MF . front ( ) ; MachineInstr * MI = & * MBB . begin ( ) ; if ( ST . hasAVX512 ( ) ) { Register Zmm = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zmm ) . addReg ( Zmm , RegState :: Undef ) . addReg ( Zmm , RegState :: Undef ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , SS ) . addReg ( Zmm ) ; } else if ( ST . hasAVX2 ( ) ) { Register Ymm = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Ymm ) . addReg ( Ymm , RegState :: Undef ) . addReg ( Ymm , RegState :: Undef ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , SS ) . addReg ( Ymm ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , SS , <NUM_LIT> ) . addReg ( Ymm ) ; } else { assert ( ST . hasSSE2 ( ) && <STR_LIT> ) ; Register Xmm = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Xmm ) . addReg ( Xmm , RegState :: Undef ) . addReg ( Xmm , RegState :: Undef ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> )


<s> bool isMovImm64Shifter ( ) const { if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = <STR_LIT> ( Shifter . Val ) ; return ( Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT>


<s> return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ,

<ISA_LIT>MCExpr :: VK_DTPREL_G1_NC } ) ;


<s> const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG .


<s> assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDValue NewLd = SDValue ( ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd ; } EVT EltVT = VT . getVectorElementType ( ) ; if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && ( EltVT . getSizeInBits ( ) == <NUM_LIT> ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , false , true , false ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , ResNode ) ; } return SDValue ( )


<s> Parser . Lex ( ) ; if ( ! parsePtrReg ( Operands , RegKind ) ) return MatchOperand_NoMatch ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) return MatchOperand_NoMatch ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return


<s> bool isLane1 ( ) const { if ( ! isImm ( ) ) return false ; return cast < MCConstantExpr > ( getImm ( ) ) -> getValue (


<s> SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> } if ( ! FPIsUsed ) return false ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > I = df_ext_begin ( Entry , Processed ) , E = df_ext_end ( Entry , Processed ) ; I != E ; ++ I ) Changed |= processBasicBlock ( MF , * * I ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) if ( Processed . insert ( BB ) ) Changed |= processBasicBlock ( MF , * BB ) ; BlockBundle . clear ( )


<s> if ( pa_function_arg_size ( arg . mode , arg . type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ; if ( cum -> words + offset + pa_function_arg_size ( arg . mode , arg . type ) <= max_arg_words ) return <NUM_LIT> ; else if ( cum -> words + offset >= max_arg_words ) return <NUM_LIT> ; else return ( max_arg_words - cum -> words - offset )


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedScatterBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; auto * Ty = cast < VectorType > ( Input -> getType ( ) ) ; if ( ! ( Ty -> getNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr


<s> while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( requiresRegisterScavenging ( MF ) ) { if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex , SPAdj , RS ) ; return ; } } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; MI . getOperand ( FIOperandNo ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? ( is64Bit ? <STR_LIT> : <STR_LIT> ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) .


<s> unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( CFAOffset ) { CFAOffset = isDestroy ? - CFAOffset :


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS

, ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> rtx mmix_eh_return_stackadj_rtx ( void ) { return gen_rtx_REG ( Pmode , MMIX_EH_RETURN_STACKADJ_REGNUM


<s> return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 .


<s> FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { rtx addr = XEXP ( * loc , <NUM_LIT> ) ; rtx * x = & addr ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , <NUM_LIT> ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , <NUM_LIT> ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , <NUM_LIT> - i ) ; * loc = replace_equiv_address_nv ( * loc ,


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( hasFP ( MF ) ) { MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; } bool BigStack = MFI -> estimateStackSize ( MF ) >= TII . estimateRSStackLimit ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MFI -> adjustsStack ( ) && ! hasReservedCallFrame ( MF ) ) ; if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) .


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill )


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = ParseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT>


<s> return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT>


<s> MachineInstr * <ISA_LIT>CallFrameOptimization :: canFoldIntoRegPush ( MachineBasicBlock :: iterator FrameSetup , unsigned Reg ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> || DefMI -> getParent ( )

!= FrameSetup -> getParent ( ) ) return nullptr ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case <STR_LIT> : \ return <STR_LIT> # NAME ; switch ( ( <STR_LIT> ) Opcode ) { case


<s> RegisterTarget < Triple :: ppc64 , true > Y ( The<ISA_LIT>64Target ,


<s> if ( llvm :: ELF :: R_386_32 == pReloc . type ( ) && helper_use_relative_reloc ( * rsym , * this ) ) { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_<ISA_LIT>_64_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , pReloc . type ( ) , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_<ISA_LIT>_64_GOTPCREL : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( ! getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) helper_GOT_init ( pReloc , true , * this ) ; else helper_GOT_init ( pReloc , false , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PLT32 : if ( rsym -> reserved ( ) & ReservePLT ) return ; if ( getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) return ; if ( rsym -> isDefine ( ) && ! rsym -> isDyn ( ) && ! getTarget ( ) . isSymbolPreemptible ( * rsym ) ) { return ; } helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PC32 : case llvm :: ELF :: R_<ISA_LIT>_64_PC16 : case llvm :: ELF :: R_<ISA_LIT>_64_PC8 : if ( getTarget ( ) . symbolNeedsPLT ( * rsym ) && LinkerConfig :: DynObj != config ( ) . codeGenType


<s> if ( V -> getOpcode ( ) == <STR_LIT> || V -> getOpcode ( ) == <STR_LIT> )


<s> bool store_offset_reg_p ( rtx_insn * insn ) { if ( get_attr_type ( insn ) != TYPE_STORE


<s> for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { unsigned Idx = WhichResult ; for ( unsigned i = <NUM_LIT> ; i != Half ; ++ i ) { if ( ( unsigned ) M [ i + j * Half ] != Idx ) return false ; Idx += <NUM_LIT>


<s> unsigned FirstCommutableVecOp = <NUM_LIT> ; unsigned LastCommutableVecOp = <NUM_LIT> ; unsigned KMaskOp = - <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) { KMaskOp = <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) FirstCommutableVecOp = <NUM_LIT> ; LastCommutableVecOp ++ ; } else if ( IsIntrinsic ) { FirstCommutableVecOp = <NUM_LIT> ; } if ( isMem ( MI , LastCommutableVecOp ) ) LastCommutableVecOp -- ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = LastCommutableVecOp ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; unsigned Op2Reg = MI . getOperand ( CommutableOpIdx2 ) . getReg ( ) ; for ( CommutableOpIdx1 = LastCommutableVecOp ; CommutableOpIdx1 >= FirstCommutableVecOp ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true


<s> assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ; if ( HasSecRelSymbolRef ( Bin -> getLHS ( ) ) || HasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2 ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_1 ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr


<s> unsigned getNumFixupKinds ( ) const override { return


<s> bool isVecListOneDHWordIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed (


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; default : { unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , dl , get ( Opc ) ) . addMBB ( TBB ) ; ++ Count


<s> if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVShiftOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVShiftOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } if ( Subtarget -> isThumb ( ) ) { SDNode * Res = SelectT2CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = SelectT2CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } } SDValue Tmp2 = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , TrueVal , Tmp2 , CCR , InFlag } ; unsigned Opc = <NUM_LIT> ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT>


<s> MBB . splice ( llvm :: next ( Slot ) , & MBB , Filler ) ; MIBundleBuilder ( MBB , Slot , llvm :: next ( llvm :: next ( Slot ) ) ) ; ++ UsefulSlots


<s> <ISA_LIT>TTIImpl :: TTI :: MemCmpExpansionOptions <ISA_LIT>TTIImpl :: enableMemCmpExpansion ( bool OptSize , bool IsZeroCmp ) const { TTI :: MemCmpExpansionOptions Options ; if ( ST -> requiresStrictAlign ( )


<s> void setKind ( BaseKind K ) { Kind =


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64VectorShuffle ( DL , Mask , V1 , V2 , Subtarget ,


<s> case <STR_LIT> : return lowerV4F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I8VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; default : llvm_unreachable ( <STR_LIT> )


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI ,