<s> case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOTTPREL ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_TPREL_HI ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_TPREL_LO ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_HI ; IsGpOff = true ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_LO ; IsGpOff = true ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOT_DISP ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOT_HI16 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOT_LO16 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOT_PAGE ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_GOT_OFST ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_HIGHER ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_HIGHEST ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_CALL_HI16 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_CALL_LO16 ; break ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = AsmPrinter . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_MCSymbol : Symbol = MO . getMCSymbol ( ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( Offset ) { assert ( Offset > <NUM_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , * Ctx ) , * Ctx ) ; } if ( IsGpOff ) Expr = <ISA_LIT>MCExpr :: createGpOff ( TargetKind , Expr , * Ctx ) ; else if ( TargetKind != <ISA_LIT>MCExpr :: MEK_None ) Expr = <ISA_LIT>MCExpr :: create ( TargetKind , Expr , * Ctx ) ; return MCOperand :: createExpr (


<s> DebugLoc DL = MIB -> getDebugLoc ( ) ; unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg ,


<s> DecodePSHUFMask ( NumElems , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned OpNum = ( Index == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return getShuffleScalarElt ( V . getOperand ( OpNum ) . getNode ( ) , Index , DAG , Depth + <NUM_LIT> ) ; } case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERM2F128Mask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } Index = ShuffleMask [ Index ] ; if ( Index < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; SDValue NewV = ( Index < NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Index % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT>


<s> void <ISA_LIT>InstrInfo :: insertOutlinerEpilogue ( MachineBasicBlock & MBB , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get


) __C , ( unsigned char ) __imm , ( __mmask16 ) - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask .

push_back ( Builder . getInt32 ( Start + i ) ) ;


<s> if ( RegNo > <NUM_LIT> || ( RegNo & <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; RegNo >>= <NUM_LIT> ; unsigned Register = QPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler ::


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex


<s> break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGH : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; break ; case VK_<ISA_LIT>_HIGHA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case VK_<ISA_LIT>_HIGHESTA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; } Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol ( ) , Modifier , Context ) ; Res = MCValue :: get ( Sym , Value . getSymB ( ) , Value . getConstant ( ) ) ; } return true


<s> void printlea64mem ( const MCInst * MI , unsigned OpNo ,


<s> const RegisterBankInfo * getRegBankInfo


<s> } while ( args ) ; return true ; } if ( TREE_CODE ( args ) != STRING_CST ) { error ( <STR_LIT> ) ; return false ; } size_t len = strlen ( TREE_STRING_POINTER ( args ) ) ; char * str_to_check = ( char * ) alloca ( len + <NUM_LIT> ) ; strcpy ( str_to_check , TREE_STRING_POINTER ( args ) ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> )


<s> EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ; unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; if ( Subtarget . isLittleEndian ( ) ) for ( unsigned i = <NUM_LIT> ; i < TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult ) ; else for ( unsigned i = <NUM_LIT> ; i <= TrgNumElts ; ++

i ) ShuffV . push_back ( i * SizeMult - <NUM_LIT> ) ;


<s> assert ( ScalarDef && <STR_LIT> ) ; while ( ScalarDef -> getOpcode ( ) == TargetOpcode :: COPY ) { ScalarDef = MRI . getVRegDef ( ScalarDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( ScalarDef && <STR_LIT> ) ; } assert ( ScalarDef -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) ; Idxs . push_back ( ScalarDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) ->


<s> if ( <ISA_LIT>Relocator :: SymVal == got_entry -> getValue ( ) ) got_entry -> setValue ( pReloc . symValue ( ) ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; if ( ( dyn_rel != NULL ) && ( <ISA_LIT>Relocator :: SymVal == dyn_rel -> addend ( ) ) ) { dyn_rel -> setAddend ( pReloc . symValue ( ) ) ; } Relocator :: Address GOT_S = helper_get_GOT_address


<s> Done = true ; break ; } } } } if ( ! Done && MatchAddress ( N , AM ) ) return false ; EVT VT = N . getValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp ,


<s> return createMacroFusionDAGMutation ( shouldScheduleAdjacent )


<s> if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , <NUM_LIT> ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET


<s> if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) (


<s> if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return false


<s> return true ; case MINUS : case PLUS : if ( ! REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) return true ; addr = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & <NUM_LIT> ) == <NUM_LIT> ) && IN_RANGE ( INTVAL ( addr ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; return true ; case SYMBOL_REF


<s> argument_types . quick_insert ( <NUM_LIT> , get_svbool_t ( ) ) ; if ( ( argument_types . length ( ) == <NUM_LIT> && instance . pred == PRED_m ) || instance . shape


<s> <ISA_LIT>ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS ,


<s> initialize<ISA_LIT>CopyPhysRegsPass ( * PassRegistry :: getPassRegistry ( )


<s> } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( ( ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ElemSize == <NUM_LIT> ) ) && Alignment >= ElemSize / <NUM_LIT> ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false


<s> } MCSymbol * FnSym = Ctx . getOrCreateSymbol ( llvm :: Twine ( <STR_LIT> ) + ( IsWrite ? <STR_LIT> : <STR_LIT> ) + llvm :: Twine ( AccessSize ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> )


<s> switch ( Size ) { case <NUM_LIT> : OutStreamer -> EmitDTPRel32Value ( <ISA_LIT>Expr -> getSubExpr ( ) ) ; break ; case <NUM_LIT> : OutStreamer -> EmitDTPRel64Value ( <ISA_LIT>Expr -> getSubExpr ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> } bool Gatscat = true ; for ( User * U : I -> users ( ) ) { if ( ! isa < Instruction > ( U ) ) return false ; if ( isa < GetElementPtrInst > ( U ) || isGatherScatter ( dyn_cast < IntrinsicInst > ( U ) ) ) { return Gatscat ; } else { unsigned OpCode = cast < Instruction > ( U ) -> getOpcode


<s> if ( SelectShifterOperandReg ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR


<s> offset = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else { rtx mem = force_const_mem ( Pmode , orig ) ; return machopic_legitimize_pic_address ( mem , Pmode


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> if ( loongarch_symbolic_constant_p ( base , & type ) ) { if ( IMM12_INT ( offset ) && loongarch_symbol_insns (

type , MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ) return ResTy ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) !=

AsmToken :: Percent ) return MatchOperand_NoMatch ;


<s> void <ISA_LIT>16InstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( )


<s> Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = isSVR4ABI ? <STR_LIT> : <STR_LIT> ; Callee . setNode ( <NUM_LIT> ) ; if ( isTailCall ) Ops . push_back ( DAG


<s> _uw offset ; offset = * p ; if ( offset & ( <NUM_LIT> << <NUM_LIT> ) ) offset |= <NUM_LIT> << <NUM_LIT> ; return offset + ( _uw


<s> static SDValue combineLoopSADPattern ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue AbsOp = N -> getOperand ( <NUM_LIT> ) ; SDValue OtherOp = N -> getOperand ( <NUM_LIT> ) ; if ( AbsOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( AbsOp , OtherOp ) ; if ( AbsOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SadOp0 , SadOp1 ; if ( ! detectZextAbsDiff ( AbsOp , SadOp0 , SadOp1 ) ) return SDValue ( ) ; SDValue Sad = createPSADBW ( DAG , SadOp0 , SadOp1 , DL , Subtarget ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { assert ( VT . getSizeInBits ( ) % ResVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumConcats = VT . getSizeInBits ( ) / ResVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcats , DAG . getConstant ( <NUM_LIT> , DL , ResVT ) ) ; Ops [ <NUM_LIT> ] =


<s> return bsearch ( & val , aarch64_bitmasks , AARCH64_NUM_BITMASKS , sizeof ( aarch64_bitmasks [ <NUM_LIT> ] ) , aarch64_bitmasks_cmp )


<s> Value * <ISA_LIT>IREmitter :: visitCMOV ( const SDNode * N


<s> RegisterMCAsmLexer < <ISA_LIT>AsmLexer >


<s> unsigned <ISA_LIT>FrameLowering :: getTOCSaveOffset ( ) const { return TOCSaveOffset


<s> if ( matchVectorShuffleAsEXTRQ ( VT , V1 , V2 , Mask , BitLen , BitIdx , Zeroable ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; if ( matchVectorShuffleAsINSERTQ ( VT , V1 , V2 , Mask , BitLen , BitIdx ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ? V1 : DAG . getUNDEF ( VT ) , V2 ? V2 : DAG . getUNDEF ( VT ) , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; return SDValue (


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createDRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MBB . getParent ( ) -> getFunction ( ) -> optForMinSize ( ) ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) < <NUM_LIT> ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; unsigned Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum =


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ; return :: isUNPCKL_v_undef_Mask ( M , N ->


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain


<s> return ( __m512d ) __builtin_ia32_cvtqq2pd512_mask ( ( __v8di ) __A , ( __v8df )

_mm512_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE


<s> Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> emitInt8 ( ELF :: ODK_REGINFO ) ; Streamer -> emitInt8 ( <NUM_LIT> ) ; Streamer -> emitInt16 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( ri_gprmask ) ; Streamer -> emitInt32 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCA . registerSection ( * Sec


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveLRPair ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFReg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( Loc ) ; else if ( IDVal == <STR_LIT>


<s> static DecodeStatus DecodeIT ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mask = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) { pred =


<s> if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) .


<s> const MachineMemOperand * Dummy ; return MI . mayStore ( ) && hasStoreToStackSlot ( MI


<s> rtx mips_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base


<s> unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , ResultVT


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( ) ) ; return


<s> bool selectBDXAddr20Pair ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base , Disp


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT ) return Op ; SDValue ShiftAmt = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ; SDValue Args [ ] = { HiLHS , LHS , HiRHS , RHS } ; SDValue MulResult = TLI . makeLibCall ( DAG , RTLIB :: MUL_I128 , WideVT , Args , <NUM_LIT> , isSigned , dl ) . first ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( isSigned ) { SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , BottomHalf , ShiftAmt ) ; TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , Tmp1 , <STR_LIT> ) ; } else


<s> It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; for ( auto &


<s> if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; } break ; case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <STR_LIT> ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned e = ( isTwoAddr ? <STR_LIT> + <NUM_LIT> : <STR_LIT> ) ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; if ( NumOps > e && MI . getOperand ( e ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( e ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; for ( ; i != e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i


<s> label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor


<s> if ( ! MI . mayLoad ( ) || MI . mayStore ( ) || MI . getNumMemOperands ( ) != <NUM_LIT> ) return ; auto MO = * MI . memoperands ( ) . begin ( ) ; uint64_t Size1 = MO ->


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI -> getOperand ( i ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; return BB


<s> unsigned MatchResult ; bool PendConditionalInstruction = false ; SmallVector < NearMissInfo , <NUM_LIT> > NearMisses ; MatchResult = MatchInstruction ( Operands , Inst , NearMisses , MatchingInlineAsm , PendConditionalInstruction , Out ) ; switch ( MatchResult ) { case Match_Success : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator (

Inst ) ) flushPendingInstructions ( Out ) ;


<s> case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv ::


<s> void setVarArgsFrameOffset ( int Offset ) { VarArgsFrameOffset =


<s> return getTM < <ISA_LIT>TargetMachine >


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixLoadStoreExclusive ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { if ( ! hasRs ) EncodedValue |=


<s> rtx addr ; if ( count != <NUM_LIT> ) { offset = - <NUM_LIT> ; addr = plus_constant ( Pmode , frameaddr , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; } return get_hard_reg_initial_val ( Pmode ,


<s> if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , <NUM_LIT> , I


<s> if ( ! mi_match ( DstReg , MRI , m_GTrunc ( m_Reg ( SrcReg ) ) ) ) return false ; return MRI . getType ( SrcReg )


<s> static SDValue getAddrLocal ( SDValue Op , SelectionDAG & DAG , bool Has<ISA_LIT>64 ) { DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , GetGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; const unsigned MinParameterSaveArea = <NUM_LIT> * PtrByteSize ; CCInfo . AllocateStack ( LinkageSize + MinParameterSaveArea , PtrByteSize ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_AIX ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( VA . isRegLoc ( ) ) { EVT ValVT = VA . getValVT ( ) ; MVT LocVT = VA . getLocVT ( ) ; <STR_LIT> SVT = ValVT . getSimpleVT ( ) . SimpleTy ; unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassForSVT ( SVT , Is<ISA_LIT>64 ) ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; if ( ValVT . isScalarInteger ( ) && ( ValVT . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ) { ArgValue = truncateScalarIntegerArg ( Flags , ValVT , DAG , ArgValue ,


<s> if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) != <STR_LIT> ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; HasRet = true ; } if ( ! HasRet ) return false


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; return true


<s> StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! STI . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } STI . InitMCProcessorInfo ( CPU , <STR_LIT>


<s> TargetRegistry :: RegisterDCInstrSema ( The<ISA_LIT>_64Target , create<ISA_LIT>DCInstrSema


<s> Value * <ISA_LIT>TTIImpl :: getReductionIntrinsic ( IRBuilder < > & Builder , const RecurrenceDescriptor & Desc , bool NoNaN , Value * Src ) { auto * VTy = dyn_cast < VectorType > ( Src -> getType ( ) ) ; if ( ! VTy || ! VTy -> isScalable ( ) || ! getST ( ) -> hasSVE ( ) ) return nullptr ; <STR_LIT> IntID ; RecurrenceDescriptor :: RecurrenceKind RecKind = Desc . getRecurrenceKind ( ) ; switch ( RecKind ) { default : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_IntegerAdd : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_IntegerAnd : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_IntegerOr : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_IntegerXor : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_FloatAdd : IntID = <STR_LIT> ; break ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( ) ) { default : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_SIntMax : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor ::


<s> return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc , <STR_LIT> ) ; case Match_MRS : return Error ( Loc , <STR_LIT>


<s> if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_RegMask ; return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return


<s> MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind ,


<s> MCAsmParser & Parser = getParser ( ) ; int64_t Offset ; if ( Parser . parseIntToken ( Offset , <STR_LIT> ) || parseEOL ( ) ) return true ; return getTargetStreamer ( ) . emitFPOStackAlign ( Offset , L


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions (


<s> TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; if ( ! shouldPromote ( V ) || isPromotedResultSafe ( V ) ) continue ; assert ( EnableDSP && <STR_LIT> ) ; InsertDSPIntrinsic ( cast < Instruction > ( V ) ) ; } auto InsertTrunc = [ & ] ( Value * V ) -> Instruction * { if ( ! isa < Instruction > ( V ) || ! isa < IntegerType > ( V -> getType ( ) ) ) return nullptr ; if ( ( ! Promoted . count ( V ) && ! NewInsts . count ( V ) ) || ! TruncTysMap . count ( V ) || Sources . count ( V ) ) return nullptr ; Type * TruncTy = TruncTysMap [ V ] ; if ( TruncTy == ExtTy


<s> static LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true


<s> bool is<ISA_LIT>64 = ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X =


<s> void add<ISA_LIT>SOImmNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> MachineBasicBlock * NextBB = std :: next ( MBBI ) ; for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end (

) ; I != E ; ++ I ) if ( * I == NextBB ) return true ;


<s> void <ISA_LIT>GOT :: applyGOTPLT ( uint64_t pPLTBase ) { if ( m_pGOTPLTFront == NULL ) return ; SectionData :: iterator entry ( m_pGOTPLTFront


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; unsigned CCValid = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( TBB ) ; ++ Count ; if ( FBB


<s> rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; rtx mask = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; if ( GET_CODE ( mask ) == CONST_INT ) { if ( INTVAL ( mask ) == - <NUM_LIT> ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return <NUM_LIT> ; } if ( ! REG_P ( mask ) ) return <NUM_LIT> ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSectionImpl ( const GlobalObject * GO , const TargetMachine & TM ) const { const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy


<s> XSym -> setContainingCsect ( Csect ) ; } return XSym -> getContainingCsect ( ) -> getQualNameSymbol ( ) ; } if ( GV ) { SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; return Csect -> getQualNameSymbol ( ) ; } return getSymbol (


<s> if ( CONST_INT_P ( y ) ) { y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; y_mode = SImode ; } else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return


<s> AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> int <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands ) { if ( IsFreeOperator ( U ) )


<s> } DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( BasicTTIImpl ( this , F ) ) ; }


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsr_u32 ( unsigned int __X ) { return __blsr_u32 (


<s> else return V4SImode ; case E_DImode : if ( TARGET_AVX512F && ! TARGET_PREFER_AVX256 ) return V8DImode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V4DImode ; else return V2DImode ; case E_HFmode : if ( TARGET_AVX512FP16 ) { if ( TARGET_AVX512VL ) { if ( TARGET_PREFER_AVX128 ) return V8HFmode ; else if ( TARGET_PREFER_AVX256 ) return V16HFmode ; } return V32HFmode ; } return word_mode ; case E_SFmode


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || SUBREG_P ( dest ) ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case FCOND_F : case FCOND_T : return <STR_LIT> ; case FCOND_UN : case FCOND_OR : return <STR_LIT> ; case FCOND_EQ : case FCOND_NEQ : return <STR_LIT> ; case FCOND_UEQ : case FCOND_OGL : return <STR_LIT> ; case FCOND_OLT : case FCOND_UGE : return <STR_LIT> ; case FCOND_ULT : case FCOND_OGE : return <STR_LIT> ; case FCOND_OLE : case FCOND_UGT : return <STR_LIT> ; case FCOND_ULE : case FCOND_OGT :


<s> x = gen_rtx_IOR ( SImode , x , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; mask = NULL ; break ; case NOT : case PLUS : case MINUS : break ; default : gcc_unreachable ( ) ; } before = gen_reg_rtx ( SImode ) ; if ( after ) after = gen_reg_rtx ( SImode ) ; store_mode = mode = SImode ; } } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = expand_simple_binop ( mode , AND , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_unop ( mode , NOT , x , after , <NUM_LIT> ) ; } else { after = expand_simple_binop ( mode , code , before , val , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = after


<s> static MCOperand create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * Sym , MCContext & OutContext ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Sym , OutContext ) ; const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: create ( Kind , MCSym ,


<s> EVT VT = Vec . getValueType ( ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits (


<s> FunctionPass * llvm :: createMVETPAndVPTOptimisationsPass ( ) { return new MVETPAndVPTOptimisations (


<s> return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction ( )


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ; DEBUG


<s> case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI : return <STR_LIT> ; default : break ; } llvm_unreachable ( <STR_LIT> ) ; return NULL


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (


, LegacyLegalizerInfo :: narrowToSmallerAndWidenToSmallest ) ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ; unsigned Reg = VA . getLocReg ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , Reg , RetValue , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg ,


<s> SDLoc DL ( Op ) ; SDValue Op0 ; SDValue Op1 = skipExtensionForVectorMULL ( N1 , DAG ) ; if ( ! isMLA ) { Op0 = skipExtensionForVectorMULL ( N0 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( NewOpc , DL , VT , Op0 , Op1 ) ; } SDValue N00 = skipExtensionForVectorMULL ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; SDValue N01 = skipExtensionForVectorMULL ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; EVT Op1VT = Op1 . getValueType ( ) ; return DAG . getNode ( N0 -> getOpcode ( ) , DL , VT , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N00 ) , Op1 )

, DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N01 ) , Op1 ) ) ;


<s> unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Size = Op . getValueSizeInBits ( ) ; if ( InVT . isScalableVector ( ) ) { if ( Idx == <NUM_LIT> && isPackedVectorType ( InVT , DAG ) ) return Op ; return SDValue


<s> return ( poly64x2_t ) __builtin_neon_vextv2di ( ( int64x2_t ) __a , ( int64x2_t )


<s> MVT VT = V . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; MVT NewVT = V . getSimpleValueType ( ) ; if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) { SDValue S = V . getOperand ( Idx ) ; if ( EltVT . getSizeInBits ( ) == S . getSimpleValueType ( ) . getSizeInBits ( ) ) return DAG . getBitcast ( EltVT , S ) ; } return SDValue (


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal (


<s> bool loongarch_symbol_binds_local_p ( const_rtx x ) { if ( TARGET_DIRECT_EXTERN_ACCESS ) return true ; if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return


<s> { HandleSDNode Handle ( Upper ) ; SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceNode ( Node , Or . getNode


<s> if ( ! MaybeImmed ) return nullptr ; uint64_t C = * MaybeImmed ; switch ( P ) { default : return nullptr ; case CmpInst :: ICMP_SLT : case CmpInst :: ICMP_SGE : if ( ( Size == <NUM_LIT> && static_cast < int64_t > ( C ) == INT64_MIN ) || ( Size == <NUM_LIT> && static_cast < int32_t > ( C ) == INT32_MIN ) ) return nullptr ; P = ( P == CmpInst :: ICMP_SLT ) ? CmpInst :: ICMP_SLE : CmpInst :: ICMP_SGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_ULT : case CmpInst :: ICMP_UGE : if ( C == <NUM_LIT> ) return nullptr ; P = ( P == CmpInst :: ICMP_ULT ) ? CmpInst :: ICMP_ULE : CmpInst :: ICMP_UGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_SLE : case CmpInst :: ICMP_SGT : if ( ( Size == <NUM_LIT> && static_cast < int32_t > ( C ) == INT32_MAX ) || ( Size == <NUM_LIT> && static_cast < int64_t > ( C ) == INT64_MAX ) ) return nullptr ; P = ( P == CmpInst :: ICMP_SLE ) ? CmpInst :: ICMP_SLT : CmpInst :: ICMP_SGE ; C += <NUM_LIT> ; break ; case CmpInst :: ICMP_ULE : case CmpInst :: ICMP_UGT : if ( ( Size == <NUM_LIT> && static_cast < uint32_t > ( C ) == UINT32_MAX ) || ( Size == <NUM_LIT> && C == UINT64_MAX ) ) return nullptr ; P = ( P == CmpInst :: ICMP_ULE ) ? CmpInst :: ICMP_ULT : CmpInst :: ICMP_UGE ; C += <NUM_LIT> ; break ; } if ( Size == <NUM_LIT> ) C = static_cast < uint32_t > ( C ) ; ImmFns = select12BitValueWithLeftShift ( C ) ; if ( ! ImmFns ) return nullptr


<s> unsigned <ISA_LIT>ABIInfo :: GetEhDataReg ( unsigned I ) const { static const unsigned EhDataReg [


<s> EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , Align ) ; unsigned StoreOp = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : StoreOp = <STR_LIT> ; break ; case <NUM_LIT> : StoreOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { StoreOp = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { StoreOp = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : StoreOp = <STR_LIT> ; break ; case <NUM_LIT> : StoreOp = <STR_LIT> ; break ; case <NUM_LIT> : StoreOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> )


<s> return ( __m256i ) __builtin_ia32_pmovsdw512_mask ( ( __v16si ) __A , ( __v16hi ) _mm256_undefined_si256 ( )


<s> Value * <ISA_LIT>IREmitter :: visitVGETLANEs ( const SDNode *


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _enqcmd ( void * __P , const void * __Q ) { return __builtin_ia32_enqcmd ( __P


<s> if ( Chain == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; InputChain = LoadNode -> getChain ( ) ; } else if ( Chain . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > ChainOps ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } int LoadId = LoadNode -> getNodeId ( ) ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = UI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getNodeId ( ) > LoadId ) return false ; } ChainOps . push_back ( Op ) ; } if ( ChainCheck ) InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> , ChainOps ) ; } if ( ! ChainCheck ) return false ; return


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) )

, TLI ( TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ) {


<s> std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode ,


<s> std :: vector < SDValue > Ops ; for ( int i = <NUM_LIT> , e = OpToConvToRecForm . getNumOperands ( ) ; i < e ; i ++ ) Ops . push_back ( OpToConvToRecForm . getOperand ( i ) ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc , dl , OpToConvToRecForm . getValueType ( ) , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { assert ( ( NewOpc != - <NUM_LIT> || ! IsBitwiseNegate ) && <STR_LIT> ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc == - <NUM_LIT> ? <STR_LIT> : NewOpc , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; } SDValue SRIdxVal = CurDAG -> getTargetConstant ( SubRegToExtract , dl , <STR_LIT> ) ; SDValue CRBit = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , CR0Reg , SRIdxVal , WideOp

. getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> int ret = <NUM_LIT> ; switch ( DEFAULT_ABI ) { default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case


<s> SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops1 , <NUM_LIT> ) ; } else { Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ; Hi = DAG . getNode ( <STR_LIT> , dl , VT


<s> return ( getFramePointerReg ( ) == <STR_LIT> && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF )


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>64R5 ( )


<s> assert ( ( Opc == TargetOpcode :: G_STORE || Opc == TargetOpcode :: G_LOAD ) && <STR_LIT> ) ; const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; auto & MemOp = * * I . memoperands_begin ( ) ; if ( MemOp . getOrdering ( ) != AtomicOrdering :: NotAtomic ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned NewOpc = getLoadStoreOp ( Ty , RB ,


<s> } if ( ! LHS . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> <ISA_LIT>CC = static_cast < <STR_LIT> > ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CTVal || ! CFVal ) return SDValue ( ) ; if ( ! ( LHS . getOpcode ( ) == <STR_LIT> && ( CTVal -> isOne ( ) || CFVal -> isOne ( ) ) ) && ! ( LHS . getOpcode ( ) == <STR_LIT> && ( CTVal -> isOne ( ) || CFVal -> isAllOnes ( ) ) ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && CTVal -> isOne ( ) && ! CFVal -> isOne ( ) ) { std :: swap ( CTVal , CFVal ) ; <ISA_LIT>CC = <STR_LIT> ( <ISA_LIT>CC ) ; } SDLoc DL ( N ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && CTVal -> isOne ( ) && ! CFVal -> isAllOnes ( ) ) { APInt C = - <NUM_LIT> * CFVal -> getAPIntValue ( ) ; CTVal = cast < ConstantSDNode > ( DAG . getConstant ( C , DL , VT ) ) ; CFVal = cast < ConstantSDNode > ( DAG . getAllOnesConstant ( DL , VT ) ) ; <ISA_LIT>CC = <STR_LIT> ( <ISA_LIT>CC ) ; } APInt ADDC = CTVal -> getAPIntValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isLegalAddImmediate ( ADDC . getSExtValue ( ) ) ) return SDValue ( ) ; assert ( ( ( LHS . getOpcode ( ) == <STR_LIT> && CFVal -> isOne ( ) ) || ( LHS . getOpcode ( ) == <STR_LIT> && CFVal -> isAllOnes ( ) ) ) && <STR_LIT> ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , RHS , SDValue ( CTVal , <NUM_LIT> ) ) ; SDValue CCVal = DAG . getConstant ( <ISA_LIT>CC , DL , <STR_LIT>


<s> gcc_assert ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ; long_jump_p = ( insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) { case GT : case GE : case LT


<s> EVT VT = Data . getValueType ( ) ; bool Byte = cast < AtomicSDNode > ( Op ) -> getMemoryVT ( ) == <STR_LIT> ; SDValue NewData = DAG . getNode ( <STR_LIT> , DL , VT , Data , Bits ) ; return DAG . getNode ( <STR_LIT> , DL , VT , { NewData , DAG . getConstant ( Byte ? <NUM_LIT> : <NUM_LIT>


<s> SDLoc dl ( Op ) ; if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) return Op ; uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) { SDValue Cond = Op . getOperand ( SplatIdx ) ; assert ( Cond . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getSelect ( dl , VT , Cond , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF .


<s> prev = PREV_INSN ( insn ) ; if ( prev == NULL ) return false ; next = NEXT_INSN (


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget -> hasAVX2 ( ) ) ; if ( VT . getSizeInBits ( ) !=


<s> Sched :: Preference <ISA_LIT>TargetLowering :: getSchedulingPreference ( SDNode *


<s> nds32_isr_vectors [ i ] . category = NDS32_ISR_NONE ; strcpy ( nds32_isr_vectors [ i ] . func_name , <STR_LIT> ) ; nds32_isr_vectors [ i ] . save_reg = NDS32_PARTIAL_SAVE ; nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ]


<s> case Immediate : case ContextImmediate : return isUInt < <NUM_LIT> > ( getImmU16Context ( ) ) ; default : return


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; int64_t IntVal ; if ( ! MatchRegisterName ( Tok , RegNo , IntVal ) ) { Parser . Lex ( ) ; return false


<s> case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT>


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return Ctx . getOrCreateSymbol ( Name


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value )


<s> return Kind == k_Register && ! Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> static SDValue LowerSUB ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) . is256BitVector ( ) && Op . getValueType ( ) . isInteger (


<s> BlockInfo . clear ( ) ; BlockInfo . resize ( MF -> getNumBlockIDs ( ) ) ; int Offset = <NUM_LIT> ; for ( MachineBasicBlock & MBB : * MF ) { BlockInfo [ MBB . getNumber


<s> else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base . Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return false ; SDValue Segment ; getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ; return


<s> if ( length > <NUM_LIT> ) return false ; value = ( UINTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ; align = UINTVAL ( operands [ <NUM_LIT> ] ) ; if ( TARGET_NEON && length >= <NUM_LIT> && current_tune -> string_ops_prefer_neon && arm_block_set_vect ( dstbase , length , value , align ) ) return true ; if ( ! unaligned_access && ( align & <NUM_LIT> ) != <NUM_LIT> ) return arm_block_set_unaligned_non_vect


<s> SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) { SExtVT = <STR_LIT> ; break ; } return SDValue ( ) ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getNode ( <STR_LIT> , DL , SExtVT , N0 ) ; if ( SExtVT == <STR_LIT> ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( V , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; V = DAG . getNode ( <STR_LIT> ,


<s> if ( RegNum > <NUM_LIT> ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , RegNum )


<s> addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass


<s> if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> || InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) != <STR_LIT> ) return nullptr ; LoadSDNode * LD = cast < LoadSDNode > ( * InputLoad ) ; return <STR_LIT> ( LD ) ? InputLoad


<s> if ( Imm & ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) ) Imm |= ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm


<s> while ( ! MI -> getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) .


<s> if ( NONJUMP_INSN_P ( insn ) && single_set ( insn ) && get_attr_loads_external_address ( insn ) == LOADS_EXTERNAL_ADDRESS_YES ) pcrel_opt_address


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool isImmutable = ! ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt && ( CallConv == CallingConv :: Fast ) ) ; unsigned PtrByteSize = <NUM_LIT> ; unsigned ArgOffset = <ISA_LIT>FrameLowering :: getLinkageSize ( true , true ) ; unsigned MinReservedArea = ArgOffset ; static const uint16_t GPR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const uint16_t * FPR = GetFPR ( ) ; static const uint16_t VR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned Num_GPR_Regs = array_lengthof ( GPR ) ; const unsigned Num_FPR_Regs = <NUM_LIT> ; const unsigned Num_VR_Regs = array_lengthof ( VR ) ; unsigned GPR_idx = <NUM_LIT> , FPR_idx = <NUM_LIT> , VR_idx = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > MemOps ; unsigned nAltivecParamsAtEnd = <NUM_LIT> ; Function :: const_arg_iterator FuncArg = MF . getFunction ( ) -> arg_begin ( ) ; unsigned CurArgIdx = <NUM_LIT> ; for ( unsigned ArgNo = <NUM_LIT> , e = Ins . size ( ) ; ArgNo != e ; ++ ArgNo ) { SDValue ArgVal ; bool needsLoad = false ; EVT ObjectVT = Ins [ ArgNo ] . VT ; unsigned ObjSize = ObjectVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned ArgSize = ObjSize ; <STR_LIT> Flags = Ins [ ArgNo ] . Flags ; std :: advance ( FuncArg , Ins [ ArgNo ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ ArgNo ] . OrigArgIndex ; unsigned CurArgOffset = ArgOffset ; if ( ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> ) { if ( isVarArg ) { MinReservedArea = ( ( MinReservedArea + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; MinReservedArea += CalculateStackSlotSize ( ObjectVT , Flags , PtrByteSize ) ; } else nAltivecParamsAtEnd ++ ; } else MinReservedArea += CalculateStackSlotSize ( Ins [ ArgNo ] . VT , Flags , PtrByteSize ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; ArgSize = ( ( ObjSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; if ( ! ObjSize ) { int FI = MFI -> CreateFixedObject ( PtrByteSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; continue ; } unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > <NUM_LIT> ) { ArgOffset = ( ( ArgOffset + BVAlign - <NUM_LIT> ) / BVAlign ) * BVAlign ; CurArgOffset = ArgOffset ; } if ( ObjSize < PtrByteSize ) CurArgOffset =

CurArgOffset + ( PtrByteSize - ObjSize ) ;


<s> if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return Result ; } else if ( isSplatVector ( Node ) ) return Op ; else if ( ! isConstantOrUndefBUILD_VECTOR ( Node ) ) { EVT ResTy = Node -> getValueType ( <NUM_LIT> ) ; assert ( ResTy . isVector ( ) ) ; unsigned NumElts = ResTy . getVectorNumElements ( ) ; SDValue Vector = DAG . getUNDEF ( ResTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { Vector = DAG . getNode ( <STR_LIT> , DL , ResTy , Vector , Node -> getOperand ( i ) , DAG .


<s> void printMemExtend ( const MCInst * MI , unsigned OpNum ,


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . customFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR , G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . customFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0


<s> void Emitter < CodeEmitter > :: emitExternalSymbolAddress ( const char * ES


<s> static DecodeStatus DecodeMemMMImm12 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> uint64_t getReturnSaveOffset ( ) const { return ReturnSaveOffset


<s> if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) ==


<s> gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg


<s> void addModImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> MachineBasicBlock :: iterator FrameSetup = Context . FrameSetup ; MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; DebugLoc DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; MachineOperand PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned int Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { unsigned UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; DefMov -> eraseFromParent ( ) ; } else


<s> continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] .


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg (

Reg ) . addImm ( Lane ) . add ( predOps ( <STR_LIT> ) ) ;


<s> MachineOperand & MaskOp = Instr . getOperand ( <NUM_LIT> ) ; assert ( MaskOp . isImm ( ) && <STR_LIT> ) ; MachineBasicBlock :: iterator Iter = ++ Instr . getIterator ( ) , End =


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperandType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind ::


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat


<s> case E_V32HImode : case E_V16HImode : return V8HImode ; case E_V64QImode : case E_V32QImode : return V16QImode ; case E_V16SFmode : case


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn


<s> int op0_num = return_p ? <NUM_LIT> : <NUM_LIT> ; int op1_num = return_p ? <NUM_LIT> : <NUM_LIT> ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op1_num , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE


<s> if ( isa < SExtInst > ( Inst ) && ( Inst -> getType ( ) == ConsideredSExtType || Inst -> hasOneUse ( )


<s> O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm (


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; if ( Rs ) { assert ( <STR_LIT> ( MO2 . getImm ( ) ) == <NUM_LIT> ) ; return Binary | ( get<ISA_LIT>RegisterNumbering ( Rs ) << <STR_LIT>


<s> LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI .


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSORegRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits


<s> bool FoundUse = false ; for ( MachineRegisterInfo :: use_instr_iterator J = MRI -> use_instr_begin ( CRReg ) , JE = MRI -> use_instr_end ( ) ; J != JE ; ++ J ) if ( & * J == & * I ) { FoundUse = true ; break ; } if ( FoundUse ) break ; } MachineInstr * Sub = nullptr ; if ( SrcReg2 != <NUM_LIT> ) MI = nullptr ; else if ( MI -> getParent ( ) != CmpInstr . getParent ( ) || Value != <NUM_LIT> ) { return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; -- I ; MachineBasicBlock :: iterator E = MI , B = CmpInstr . getParent ( ) -> begin ( ) ; for ( ; I != E && ! noSub ; -- I ) { const MachineInstr & Instr = * I ; unsigned IOpC = Instr . getOpcode ( ) ; if ( & * I != & CmpInstr && ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) && ( IOpC == <STR_LIT> || IOpC == <STR_LIT> ) && ( ( Instr . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && Instr . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( Instr . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Instr . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; int NewOpC = - <NUM_LIT> ; MIOpC = MI -> getOpcode ( ) ; if ( MIOpC == <STR_LIT> || MIOpC == <STR_LIT> ) NewOpC = MIOpC ; else { NewOpC = <STR_LIT> ( MIOpC ) ; if ( NewOpC == - <NUM_LIT> && <STR_LIT> ( MIOpC ) != - <NUM_LIT> ) NewOpC = MIOpC ; } if ( NewOpC == - <NUM_LIT> ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > PredsToUpdate ; SmallVector < std :: pair < MachineOperand * , unsigned > , <NUM_LIT> > SubRegsToUpdate ; bool ShouldSwap = false ; if ( Sub ) { ShouldSwap = SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ; ShouldSwap = ! ShouldSwap ; } if ( ShouldSwap ) for ( MachineRegisterInfo :: use_instr_iterator I = MRI -> use_instr_begin ( CRReg ) , IE = MRI -> use_instr_end ( ) ; I != IE ; ++ I ) { MachineInstr * UseMI = & * I


<s> unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Size < <NUM_LIT> || Count < <NUM_LIT> ) && RegNum == PRegNum + <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch ,


<s> static MCAsmBackend * create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options , <STR_LIT> Endian ) { const Triple & TheTriple = STI . getTargetTriple ( ) ; switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> )


<s> if ( homogeneousPrologEpilog ( MF ) ) { auto MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & RPI : RegPairs ) { MIB . addReg ( RPI . Reg1 ) ; MIB . addReg ( RPI . Reg2 ) ; if ( ! MRI . isReserved ( RPI . Reg1 ) ) MBB . addLiveIn ( RPI . Reg1 ) ; if ( ! MRI . isReserved ( RPI . Reg2 ) ) MBB . addLiveIn ( RPI . Reg2 ) ; } return true ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size ; Align Alignment ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: FPR128 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: ZPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: PPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; assert ( ( ! NeedsWinCFI || ! ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn


<s> case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> APInt One ( SVTBits , <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Op = Amt -> getOperand ( i ) ; if ( Op -> isUndef ( ) ) { Elts . push_back ( Op ) ; continue ; } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Z = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , getUnpackl ( DAG , dl , VT , Amt , Z ) ) ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , getUnpackh ( DAG , dl , VT , Amt , Z ) ) ; Lo = convertShiftLeftToScale ( Lo , dl , Subtarget , DAG ) ; Hi = convertShiftLeftToScale ( Hi , dl , Subtarget , DAG ) ; if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; return DAG . getVectorShuffle ( VT , dl , DAG . getBitcast ( VT , Lo ) , DAG . getBitcast ( VT , Hi ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return SDValue (


<s> if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( &


<s> unsigned Register = ZZZDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> <ISA_LIT>AddressMode ( ) : BaseType ( RegBase ) , IndexReg ( <NUM_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } return I ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( N -> getNumOperands ( ) != <NUM_LIT> && N -> getNumOperands ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> )


<s> } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> ,


<s> return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( unsigned short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo , O


<s> static const MachineOperand & getLdStRegOp ( const MachineInstr & MI , unsigned PairedRegOp = <NUM_LIT> ) { assert ( PairedRegOp < <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = isPairedLdSt ( MI ) ? PairedRegOp : <NUM_LIT> ; return MI . getOperand


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; unsigned NumDefs = MCID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O ,


<s> } if ( LateMask ) { uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += SelectInt64Count ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( SelectInt64 ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl

, <STR_LIT> , Res , MaskVal ) , <NUM_LIT> ) ;


<s> if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return TryCand . Reason != NoCand ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return TryCand . Reason != NoCand ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return TryCand . Reason != NoCand ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return true ; if ( biasAddiCandidate ( Cand , TryCand ) ) return TryCand . Reason != NoCand ; return TryCand . Reason


<s> void printMemOffs8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemOffset ( MI , OpNo