<s> return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidOImm16 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidUImm1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm4 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm7 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm8 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm16 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5Shift1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm12Shift1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm5Shift2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Shift1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Shift2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Shift2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Shift3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Shift8 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT>


<s> return function_checker ( location , rfn . instance , fndecl , TREE_TYPE ( rfn


<s> bool hasAddLogicalFusion ( ) const { return


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy (


<s> rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( val ) ; return gen_rtx_CONST_VECTOR ( mode


<s> case IES_MINUS : case IES_NOT : case IES_OR : case IES_XOR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> return aarch64_sve_ld1rq_ld1ro_operand_p ( op , TImode , GET_MODE_INNER (


<s> bool isRegExtend ( ) const { if ( ! isShiftOrExtend ( ) ) return false ; if ( ShiftExtend . ShiftType != SHKind ) return false ; return ShiftExtend .


<s> return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; auto IsUnitDup = [ ] ( auto * I ) { auto * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; auto * SplatValue = IntrI -> getOperand ( <NUM_LIT> ) ; return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; if ( IsUnitDup ( OpMultiplicand ) || IsUnitSplat ( OpMultiplicand ) ) std :: swap ( OpMultiplier , OpMultiplicand ) ; if ( IsUnitSplat ( OpMultiplier ) ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } else if ( IsUnitDup ( OpMultiplier ) ) { auto * DupInst = cast < IntrinsicInst > ( OpMultiplier ) ; auto * DupPg = DupInst -> getOperand ( <NUM_LIT> ) ; if ( OpPredicate == DupPg ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder &&


<s> static void AnalyzeRetResult ( CCState & State , const SmallVectorImpl <


<s> return __builtin_mve_vrndnq_fv4sf ( __a )


<s> far = <NUM_LIT> ; if ( flag_pic ) { if ( TARGET_SH2 ) jump = <STR_LIT> ; else jump = <STR_LIT> ; } else jump = <STR_LIT> ; } if ( GET_CODE ( ( prev = prev_nonnote_insn ( insn ) ) ) == INSN && INSN_CODE ( prev ) == CODE_FOR_indirect_jump_scratch ) { this . reg = SET_DEST ( XVECEXP ( PATTERN ( prev ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( REGNO ( this . reg ) == R0_REG && flag_pic && ! TARGET_SH2 ) jump = <STR_LIT> ; output_asm_insn ( jump , & this . lab ) ; if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; this . reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( jump , & this . lab ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( far && flag_pic && TARGET_SH2 ) { braf_base_lab = gen_label_rtx ( ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( braf_base_lab ) ) ; } if ( far ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( this . lab ) ) ; this . op = op ; if ( far && flag_pic ) { if ( TARGET_SH2 ) this . lab = braf_base_lab ; output_asm_insn ( <STR_LIT> , & this


<s> CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Imm = <NUM_LIT> ; unsigned CurBit = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { CurBit ^= ( Val >> i ) & <NUM_LIT> ; Imm |= ( CurBit << i ) ; if ( ( Val & ~ ( ~ <NUM_LIT> << i ) ) == <NUM_LIT> ) { Imm |= <NUM_LIT> << i ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return


<s> bool <STR_LIT> ( SDNode * N ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; unsigned NumElems = N -> getNumOperands ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> , ++ j ) { SDValue BitI = N -> getOperand


<s> HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs =


<s> SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; Flags . setOrigAlign ( Align ( DL . getABITypeAlignment ( ArgTy ) ) ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget


<s> } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( )


<s> mode = GET_MODE ( val ) ; if ( mode == VOIDmode ) mode = DImode ; gcc_assert ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ; lowpart = gen_lowpart ( SImode , val ) ; highpart = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( GET_CODE ( lowpart ) == CONST_INT


<s> MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI .

getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ;


<s> const char * getPassName ( ) const override { return


<s> else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else return false ; Index = Index / DstTy . getSizeInBits ( ) ; I . getOperand ( <NUM_LIT> ) . setImm ( Index ) ; return constrainSelectedInstRegOperands ( I , TII , TRI ,


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , MachinePointerInfo


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask |= ( d -> perm [ i ] & <NUM_LIT> ) << ( i * <NUM_LIT> ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ <NUM_LIT> ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & <NUM_LIT> ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( <NUM_LIT> , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge


<s> else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = <NUM_LIT> ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = <NUM_LIT> ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode

, <NUM_LIT> , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Dest = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Mask = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Index = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ) ; if ( Dest == Mask || Dest == Index || Mask == Index ) return Warning ( Ops [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned <ISA_LIT>TargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; if ( Subtarget -> hasMVEIntegerOps ( ) )


<s> assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align


<s> int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm (


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , getPointerTy ( ) , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; DebugLoc DL = CP -> getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Result ) ; } return Result


<s> return ( int32x4_t ) __builtin_neon_vsras_nv4si ( __a ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst


<s> getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ; assert ( Scale != <NUM_LIT> && <STR_LIT> ) ; int64_t NewImm = ( Offset + <NUM_LIT> ) / Scale ; StackOffsetOperand . setImm ( NewImm


<s> static bool AEABI ( const <ISA_LIT>Subtarget & ST ) { return ST . isTargetAEABI ( ) || ST . isTargetGNUAEABI


<s> unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry ,


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_mask ( ( __v16qi ) __A , ( __v64qi )


<s> return ( __mmask64 ) __builtin_ia32_kmovq ( * ( __mmask64


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } default : break ; } return false


<s> return ( long long ) __builtin_ia32_vcvtsh2si64_round (


<s> if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Value ) ) { const MCSymbol & Sym = SRE ->


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties ::


<s> getTargetStreamer ( ) . emitCurrentConstantPool (


<s> return ( __m256i ) __builtin_ia32_pmovdw512_mask ( ( __v16si ) __A , ( __v16hi ) _mm256_undefined_si256 ( ) , ( __mmask16


<s> <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg )


<s> return ( float32x2_t ) __builtin_neon_vset_lanev2sf ( ( __builtin_neon_sf ) __a ,


<s> rtx ref = operands [ <NUM_LIT> ] ; rtx base , scratch ; HOST_WIDE_INT offset = <NUM_LIT> ; if ( GET_CODE ( ref ) == SUBREG ) { offset = SUBREG_BYTE ( ref ) ; ref = SUBREG_REG ( ref ) ; } if ( REG_P ( ref ) ) { if ( reg_equiv_mem ( REGNO ( ref ) ) ) { ref = reg_equiv_mem ( REGNO ( ref ) ) ; base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; } else base = reg_equiv_address ( REGNO ( ref ) ) ; } else base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; if ( GET_CODE ( base ) == MINUS || ( GET_CODE ( base ) == PLUS && ! CONST_INT_P ( XEXP ( base , <NUM_LIT> ) ) ) ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi )


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return &


<s> if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( )


<s> void setCalleeSavedXMMFrameInfo ( unsigned size , int origin ) { CalleeSavedXMMFrameSize = size ; CalleeSavedXMMFrameOrigin =


<s> unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = DAG . getDataLayout ( ) . getABITypeAlignment ( EltVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , EltVT ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Shuffle = ( UnaryShuffle ) ? DAG . getUNDEF ( CurrentVT ) : InVec . getOperand ( <NUM_LIT> ) ; Shuffle = DAG . getVectorShuffle ( CurrentVT , dl , InVec . getOperand ( <NUM_LIT> ) , Shuffle , & ShuffleMask [ <NUM_LIT> ] ) ; Shuffle = DAG . getBitcast (


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) )

return LowerFABS64 ( Op , DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ;


<s> SDValue LoadLinkSP = DAG . getLoad ( PtrVT , dl , Chain , StackPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( LoadLinkSP . getValue ( <NUM_LIT> ) , dl , SP , SaveSP ) ; return DAG . getStore ( Chain , dl , LoadLinkSP , StackPtr , MachinePointerInfo


<s> const TargetMachine & TM = Fn . getTarget ( ) ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; TRI = TM . getRegisterInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > (


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>AtomicExpandPass :: expandAtomicStore ( StoreInst * SI ) { IRBuilder < > Builder ( SI ) ; AtomicOrdering Order = SI -> getOrdering ( ) == Unordered ? Monotonic :


<s> machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return false ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p


<s> if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) { FrameIdx = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false


<s> void printlea32mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printLeaMemReference ( MI , OpNo , O


<s> if ( tryParseScalarRegister ( XReg ) != MatchOperand_Success ) return MatchOperand_NoMatch ; MCContext & ctx = getContext ( ) ; const MCRegisterInfo * RI = ctx . getRegisterInfo ( ) ; int X8Reg = RI -> getMatchingSuperReg ( XReg , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT>


<s> bool isMaybeDirectBranchDest ( ) const { assert ( Kind == Memory && <STR_LIT> ) ; return Mem .


<s> Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } case <STR_LIT> : { Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) != <STR_LIT> ) break ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } return


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char *


<s> SDValue getCallTargetFromCapTable ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG

, SDValue Chain , const MachinePointerInfo & PtrInfo ) const {


<s> return ( uint8x8_t ) __builtin_neon_vqrshluv8qi ( ( int8x8_t )


<s> MCDataFragment * Frag = getOrCreateDataFragment ( ) ; Frag -> getFixups ( ) . push_back ( MCFixup :: Create ( Frag -> getContents ( ) . size (


<s> if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV ,


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm


<s> unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> )


<s> bool IsLargeCodeModel = MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ; unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; const char * Symbol ; if ( Is64Bit ) { if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ; } CI -> setFlags ( CI -> getFlags ( ) | MachineInstr :: FrameSetup ) ; unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( Is64Bit ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( InProlog ) { for ( ++ ExpansionMBBI ; ExpansionMBBI != MBBI ; ++ ExpansionMBBI ) ExpansionMBBI -> setFlag ( MachineInstr :: FrameSetup ) ; } return & *


<s> if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r ,


<s> bool predictableSelectIsExpensive ( )


<s> if ( Pmode == DImode ) { upper = ( address >> <NUM_LIT> ) & <NUM_LIT> ; if ( upper == <NUM_LIT> || upper == <NUM_LIT> ) return true ; } return false


<s> Shuffle = <STR_LIT> ; return true ; } } } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && FloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return


<s> static SDValue combineADC ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; auto * LHSC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( LHSC && ! RHSC ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , RHS , LHS , CarryIn ) ; if ( LHSC && RHSC && LHSC -> isZero ( ) && RHSC -> isZero ( ) && SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue CarryOut = DAG . getConstant ( <NUM_LIT> , DL , N -> getValueType ( <NUM_LIT> ) ) ; SDValue Res1 = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , CarryIn ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DCI . CombineTo ( N , Res1 , CarryOut ) ; } if ( SDValue Flags = combineCarryThroughADD ( CarryIn , DAG ) ) { MVT VT = N ->


<s> return ST . isTargetAEABI ( ) || ST . isTargetGNUAEABI ( ) || ST


<s> } } else { for ( i = low ; i < high ; i += <NUM_LIT> ) { bool reg0 = save_p ( i , leaf_function ) ; bool reg1 = save_p ( i + <NUM_LIT> , leaf_function ) ; machine_mode mode ; int regno ; if ( reg0 && reg1 ) { mode = SPARC_INT_REG_P ( i ) ? E_DImode : E_DFmode ; regno = i ; } else if ( reg0 ) { mode = SPARC_INT_REG_P ( i ) ? E_SImode : E_SFmode ; regno = i ; } else if ( reg1 ) { mode = SPARC_INT_REG_P ( i ) ? E_SImode : E_SFmode ; regno = i + <NUM_LIT> ; offset += <NUM_LIT> ; } else { if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; continue ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 ) = <NUM_LIT>


<s> unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode (

) , ErrMsg ) ) return ErrorOperand ( Start , ErrMsg ) ;


<s> unsigned HI16Opc = <NUM_LIT> ; bool isThumb2 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isThumb2 ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } const bool ShouldUseMOV16PIC = ! STI -> useConstIslands ( ) && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT>


<s> bool <ISA_LIT>RegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI


<s> MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned NumOps = MCID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( MCID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk =


<s> bool fastcall_p = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < <NUM_LIT> || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < <NUM_LIT> && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < <NUM_LIT> && ! fastcall_p && ! thiscall_p &&


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL )


<s> assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; TFI -> recordLoadArgsFI ( FI , - StackLoc ) ; TFI -> recordLiveIn ( FI ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( ( isVarArg ) && ArgRegEnd ) { if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getRegister ( StackReg , getPointerTy ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Begin = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned Start = get<ISA_LIT>RegisterNumbering ( ArgRegEnd + <NUM_LIT> ) ; unsigned End = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned StackLoc = Start - Begin + <NUM_LIT> ; for ( ; Start <= End ; ++ Start , ++ StackLoc ) { unsigned Reg = get<ISA_LIT>RegisterFromNumbering ( Start ) ; unsigned LiveReg = MF . addLiveIn ( Reg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , LiveReg , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; TFI -> recordStoreVarArgsFI ( FI , - ( StackLoc * <NUM_LIT>


<s> fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && BARRIER_P ( fix -> insn ) ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( BARRIER_P ( ftmp -> insn ) ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address + <NUM_LIT> ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ; while ( ftmp


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressELF ( SDValue Op , SelectionDAG & DAG ) { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; }


<s> SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; const APInt & ExtIndex0 = N0 . getConstantOperandAPInt ( <NUM_LIT> ) ; const APInt & ExtIndex1 = N1 . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ExtIndex1 == <NUM_LIT> && ExtIndex0 == NumElts ) ShuffleVectorSDNode :: commuteMask ( NewMask ) ; else if ( ExtIndex0 != <NUM_LIT> || ExtIndex1 != NumElts ) return SDValue ( ) ; if ( NumElts == <NUM_LIT> && ( isSingleSHUFPSMask ( NewMask ) || is128BitUnpackShuffleMask ( NewMask ) ) ) return SDValue ( ) ; NewMask . append ( NumElts


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } return false ; } if ( FloatDomain && MaskScalarSizeInBits == <NUM_LIT> ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( ! is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) return false ; SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , SrcVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask )


<s> if ( IsPIC && static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return


<s> unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> && ISDOpc != <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT>


<s> const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! ConstExpr ) return false ; unsigned regIdx = ConstExpr -> getValue ( ) ; if ( regIdx > <NUM_LIT> || MISCRegs [ regIdx ] == <STR_LIT> ) return false ; Op . Kind = k_Register ; Op . Reg . RegNum = MISCRegs [ regIdx ] ; return true


<s> SDValue Increment = DAG . getConstant ( SclrLoadTy . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue Res = DAG . getUNDEF ( LoadUnitVecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; Chains . push_back ( ScalarLoad . getValue ( <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; else Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , Res , ScalarLoad , DAG . getIntPtrConstant ( i ) ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chains ) ; SDValue SlicedVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Res ) ; unsigned SizeRatio = RegSz / MemSz ; if ( Ext == <STR_LIT> ) { if ( Subtarget -> hasSSE41 ( ) ) { SDValue Sext = DAG . getNode ( <STR_LIT> , dl , RegVT , SlicedVec ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , TF ) ; return Sext ; } assert ( TLI . isOperationLegalOrCustom ( <STR_LIT> , RegVT ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i * SizeRatio + SizeRatio - <NUM_LIT> ] = i ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , dl , SlicedVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; Shuff = DAG . getNode ( <STR_LIT> , dl , RegVT , Shuff ) ; unsigned Amt = RegVT . getVectorElementType ( ) . getSizeInBits ( ) - MemVT . getVectorElementType ( ) . getSizeInBits ( ) ; Shuff = DAG . getNode ( <STR_LIT> , dl , RegVT , Shuff , DAG . getConstant ( Amt , RegVT ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld


<s> return create<ISA_LIT>ELFStreamer ( Ctx , TAB , OS ,


<s> void printHex64ImmOperand ( const MachineInstr * MI , int


<s> static bool aarch64_print_ldpstp_address ( FILE * f


<s> void <ISA_LIT>TargetLowering :: ReplaceExtractSubVectorResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue In = N -> getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; if ( ! InVT . isScalableVector ( ) || ! InVT . isInteger ( ) ) return ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! isTypeLegal ( InVT ) ) { if ( In -> getOpcode ( ) == <STR_LIT> ) { EVT TruncOpVT = In -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( ! isTypeLegal ( TruncOpVT ) ) return ; EVT EltVT = TruncOpVT


<s> plus0 = XEXP ( address , <NUM_LIT> ) ; plus1 = XEXP ( address , <NUM_LIT> ) ; if ( REG_P ( plus0 ) && CONST_INT_P ( plus1 ) ) { if ( satisfies_constraint_Iu03 ( plus1 ) ) return ( COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT>


<s> void addImm0_1020s4Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) / <NUM_LIT>


<s> static DecodeStatus DecodeDPR_VFP2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitMappingSymbol ( <STR_LIT> )


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { if ( MBB . empty ( ) ) return <NUM_LIT> ; unsigned NumRemoved = <NUM_LIT> ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I


<s> bool HasVLX = STI . hasVLX ( ) ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && DstTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else return false


<s> return ( __m512i ) __builtin_ia32_punpcklqdq512_mask ( ( __v8di ) __A , ( __v8di ) __B , ( __v8di ) _mm512_undefined_epi32 ( ) ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = IssueWidth * NOOPsToAdd ; i != e ; ++ i ) BuildMI ( * MBB , MBBI , DL , TSM .

getInstrInfo ( ) -> get ( <STR_LIT> ) ) ;


<s> assert ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && <STR_LIT> ) ; unsigned index_align = insn >> <NUM_LIT>


<s> } if ( ! NewOpc ) continue ; unsigned UserOffset = GetUserOffset ( U ) ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; if ( ! U . KnownAlignment ) MaxOffs -= <NUM_LIT> ; if ( CPEIsInRange ( U . MI , UserOffset , U . CPEMI , MaxOffs , false , true ) ) { U . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = U . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB ) ; ++ NumT2CPShrunk ; MadeChange = true ; } } MadeChange |= OptimizeThumb2Branches ( )


<s> int64_t BitSize = NarrowVT . getSizeInBits ( ) ; SDValue ChainIn = Node -> getOperand ( <NUM_LIT> ) ; SDValue Addr = Node -> getOperand ( <NUM_LIT> ) ; SDValue CmpVal = Node -> getOperand ( <NUM_LIT> ) ; SDValue SwapVal = Node -> getOperand ( <NUM_LIT> ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; SDLoc DL ( Node ) ; EVT PtrVT = Addr . getValueType ( ) ; SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , CmpVal , SwapVal , BitShift , NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , NarrowVT ,


<s> if ( N -> getNumOperands ( ) == <NUM_LIT> ) if ( SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ) return RV ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT


<s> static Target The<ISA_LIT>Target ; return


<s> __builtin_aarch64_simd_ci __o ; uint8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp .


<s> return ( poly8x8_t ) __builtin_neon_vsli_nv8qi ( ( int8x8_t ) __a , ( int8x8_t )


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>_32Target ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y (


<s> return false ; case InlineAsm :: Constraint_ZC : if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { if ( selectAddrRegImm12 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { if ( selectAddrRegImm9 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( selectAddrRegImm16 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } return true


<s> SDValue PopOpnd = InIdx . getOperand ( <NUM_LIT> ) ; if ( PopOpnd . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , PopOpnd , InVec ) ; } if ( isTypeLegal ( VT ) ) return Op ; EVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getZExtOrTrunc ( InIdx , DL , <STR_LIT> ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Seq = DAG . getNode ( <STR_LIT> , DL , IntVT , Zero , One ) ; EVT BoolVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; EVT PredVT = Seq . getValueType ( ) . changeVectorElementType ( BoolVT ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , DL , PredVT , Seq , SplatIdx , DAG . getCondCode (


<s> rtl_opt_pass * make_pass_fma_steering ( gcc :: context * ctxt


<s> case AddrMode4 : return <STR_LIT> ; case AddrMode5 : return <STR_LIT> ; case AddrMode6 : return <STR_LIT> ; case AddrModeT1_1 : return <STR_LIT> ; case AddrModeT1_2 : return <STR_LIT> ; case AddrModeT1_4 : return <STR_LIT> ; case AddrModeT1_s : return <STR_LIT> ; case AddrModeT2_i12 : return <STR_LIT> ; case AddrModeT2_i8 : return <STR_LIT> ; case AddrModeT2_so : return <STR_LIT> ; case AddrModeT2_pc : return <STR_LIT> ; case AddrModeT2_i8s4 : return


<s> unsigned J1 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned J2 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget >


<s> Data64bitsDirective = ( isV9 ) ? <STR_LIT> : <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; SunStyleELFSectionSwitchSyntax =


<s> HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; return BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , Zero , DAG , dl ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue EvenParts = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; EvenParts = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , EvenParts ) ; SDValue OddParts = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; OddParts = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OddParts ) ; SDValue Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Ops [ i * <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> * i + <NUM_LIT> , <STR_LIT> ) ; Ops [ i * <NUM_LIT> + <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> * i + <NUM_LIT> + <NUM_LIT> , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , EvenParts , OddParts , DAG . getNode ( <STR_LIT> ,


<s> NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( ! isAM5 && Offset == - Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else return false ; } MBB . erase ( MergeInstr ) ; <STR_LIT> AddSub = Offset < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; bool isLd = isLoadSingle ( Opcode ) ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { int Imm = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Imm ) . add ( predOps ( Pred , PredReg ) ) ; } } else { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) ; } } else { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( isAM2 && NewOpc == <STR_LIT> ) { int Imm = <STR_LIT> ( AddSub , Bytes , <STR_LIT>


<s> rtx elementsize = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( totalsize ) && CONST_INT_P ( elementsize ) && UINTVAL ( elementsize ) != <NUM_LIT> && UINTVAL ( totalsize ) != <NUM_LIT> ) { rtx lane_idx = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( lane_idx ) ) aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , UINTVAL ( totalsize ) / UINTVAL ( elementsize ) , exp ) ; else error ( <STR_LIT> , exp ) ; } else error ( <STR_LIT> , exp ) ; return const0_rtx ; } aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k -


<s> rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; if ( Pmode == DImode ) emit_insn ( gen_adddi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; else emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != <NUM_LIT> || current_function_calls_eh_return ) { if ( ! TARGET_MIPS16 ) { if ( Pmode == DImode ) emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; else emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } else { rtx g6_rtx = gen_rtx ( REG , Pmode , GP_REG_FIRST + <NUM_LIT> ) ; if ( Pmode == DImode ) { emit_insn ( gen_movdi ( g6_rtx , stack_pointer_rtx ) ) ; emit_insn ( gen_adddi3 ( g6_rtx , g6_rtx , tsize_rtx ) ) ; emit_insn ( gen_movdi ( stack_pointer_rtx , g6_rtx ) ) ; } else { emit_insn ( gen_movsi ( g6_rtx , stack_pointer_rtx ) ) ; emit_insn ( gen_addsi3 ( g6_rtx , g6_rtx , tsize_rtx ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , g6_rtx )


<s> if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_AVX512 ( Op , Subtarget , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask1 ) ; SmallVector < int , <NUM_LIT> > ShufMask2


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize ,


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBR_CC ( Op ,


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ; return


<s> SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewReturnAddrFI ) ) ; return


<s> EVT VT = Op . getValueType ( ) ; assert ( ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) && ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT )


<s> printRegName ( O , MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT> ) ; return ; } O << <STR_LIT> ; O << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) ) , <STR_LIT> ( MO3


<s> NeedMask = false ; RLAmt . resize ( Bits . size ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) if ( Bits [ i ] . hasValue ( ) ) { unsigned VBI = Bits [ i ] . getValueBitIndex ( ) ; if ( i >= VBI ) RLAmt [ i ] = i - VBI ; else RLAmt [ i ] = Bits . size ( ) - ( VBI - i ) ; } else if ( Bits [ i ] . isZero ( ) ) { NeedMask = true ; RLAmt [ i ]


<s> InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , dl , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , dl , SrcVT ) ) , DAG

. getConstant ( BytesLeft , dl , SizeVT ) , Align , isVolatile , AlwaysInline , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ;


<s> return DecodeMem ( Inst , insn , Address , Decoder ,


<s> SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue


<s> return ( __m512i ) __builtin_ia32_packusdw512_mask ( ( __v16si ) __A , ( __v16si )


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; auto * SrcVTy = dyn_cast < FixedVectorType > ( Src ) ; assert ( SrcVTy && <STR_LIT> ) ; if ( hasActiveVectorLength ( Opcode , Src , Alignment ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; InstructionCost CostFactor = vectorCostAdjustmentFactor ( Opcode , Src , nullptr ) ; if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ; InstructionCost Cost = LT . first * CostFactor ; assert ( Cost . isValid ( ) && <STR_LIT> ) ; const Align DesiredAlignment ( <NUM_LIT> ) ; if ( Alignment >= DesiredAlignment || ST -> getCPUDirective ( ) != <STR_LIT> ) return Cost ; float AlignmentProb = ( ( float ) Alignment . value ( ) ) / DesiredAlignment . value ( ) ; float MisalignmentProb = <NUM_LIT> - AlignmentProb ; return ( MisalignmentProb * P9PipelineFlushEstimate ) + ( AlignmentProb * * Cost . getValue (


<s> union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d


<s> int getFPStackOffset ( ) const { return


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo


<s> if ( NOTE_INSN_BASIC_BLOCK_P ( NEXT_INSN ( head ) ) ) head = NEXT_INSN ( head ) ; for ( r = PR_REG ( <NUM_LIT> ) ; r < PR_REG ( <NUM_LIT> ) ; r += <NUM_LIT> ) if ( REGNO_REG_SET_P ( df_get_live_in ( bb ) , r ) ) { rtx p = gen_rtx_REG ( BImode , r ) ; rtx_insn * n = emit_insn_after ( gen_pred_rel_mutex ( p ) , head ) ; if ( head == BB_END ( bb ) ) BB_END ( bb ) = n ; head = n ; } } FOR_EACH_BB_REVERSE_FN ( bb , cfun ) { rtx_insn * insn = BB_HEAD ( bb ) ; while ( <NUM_LIT> ) { if ( CALL_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { rtx_insn * b = emit_insn_before ( gen_safe_across_calls_all ( ) , insn ) ; rtx_insn * a = emit_insn_after (

gen_safe_across_calls_normal ( ) , insn ) ;


<s> break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2


<s> OperandMatchResultTy parseBDRAddr64 ( OperandVector &


<s> SDValue V1 = Ops [ <NUM_LIT> ] ; SDValue V2 = IsUnary ? V1 : Ops [ <NUM_LIT> ] ; KnownUndef = KnownZero = APInt :: getNullValue ( Size ) ; V1 = peekThroughBitcasts ( V1 ) ; V2 = peekThroughBitcasts ( V2 ) ; assert ( ( VT . getSizeInBits ( ) % Size ) == <NUM_LIT> && <STR_LIT> ) ; unsigned EltSizeInBits = VT . getSizeInBits ( ) / Size ; APInt UndefSrcElts [ <NUM_LIT> ] ; SmallVector < APInt , <NUM_LIT> > SrcEltBits [ <NUM_LIT> ] ; bool IsSrcConstant [ <NUM_LIT> ] = { getTargetConstantBitsFromNode ( V1 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) , getTargetConstantBitsFromNode ( V2 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { assert ( isUndefOrZero ( M ) && <STR_LIT> ) ; if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ; if ( SM_SentinelZero == M ) KnownZero . setBit ( i ) ; continue ; } unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) KnownUndef . setBit ( i ) ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) KnownZero . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; int NumVecElts = Vec . getValueType ( ) . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) && Size == NumVecElts ) { auto * CIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; int NumSubElts = V . getOperand ( <NUM_LIT> )


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT>


<s> emit_sf_insn ( ( * fun ) ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , get_fpscr_rtx (


<s> else if ( CM == CodeModel :: JITDefault ) CM = CodeModel :: Large ; else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ; if ( TT . isOSDarwin ( ) ) RM = Reloc :: PIC_ ; else if ( RM == Reloc :: Default || RM == Reloc :: DynamicNoPIC ) RM = Reloc :: Static ; MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL


<s> lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl )


) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return new ScheduleDAGMI ( C , std :: make_unique < <ISA_LIT>PostRASchedStrategy >


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue <ISA_LIT>CC ; SDValue Flag = EmitCmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueV


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI -> getZExtValue ( ) ; if ( VT == <STR_LIT> ) return

<ISA_LIT>Materialize64BitInt ( Imm , RC ) ;


<s> c = ( __v4sf ) vec_cmpeq ( a , b ) ; c = vec_nor ( c , c ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 (


<s> if ( V -> getType ( ) -> isIntegerTy ( ) ) return V ; if ( VectorType * VecTy = dyn_cast < VectorType > ( V -> getType ( ) ) ) { LLVMContext & Ctx = IRB . getContext ( ) ; Type * EltTy = VecTy


<s> static SDValue PerformVMOVDRRCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> static inline bool isCondBranchOpcode (


<s> raw_ostream & <ISA_LIT>MCAsmStreamer :: GetCommentOS (


<s> getJumpTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr


<s> if ( TUNE_LOONGSON_2EF ) mips_ls2_init_dfa_post_cycle_insn


<s> ieee128_mangling_gcc_8_1 = true ; lang_hooks . set_decl_assembler_name ( decl ) ; old_name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; SET_DECL_ASSEMBLER_NAME ( decl , save_asm_name ) ; ieee128_mangling_gcc_8_1 = false ; if ( strcmp ( name , old_name ) != <NUM_LIT> ) { fprintf ( stream , <STR_LIT> , old_name ) ; fprintf ( stream , <STR_LIT> , old_name


<s> InstructionCost LegalizationCost = <NUM_LIT> ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( ValTy -> getContext ( ) ) ; LegalizationCost = getArithmeticInstrCost ( Opcode , LegalVTy , CostKind ) ; LegalizationCost *= LT . first - <NUM_LIT> ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; switch ( ISD ) { case <STR_LIT> : case <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: getVFPCmp ( SDValue LHS , SDValue RHS , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( ! Subtarget -> isFPOnlySP ( ) || RHS . getValueType ( ) != <STR_LIT> ) ; SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr ,

DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> static rtx sparc_libcall_value ( machine_mode mode ,


<s> Type * ArgTys [ <NUM_LIT> ] = { Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType } ; FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: getRealLinkageName ( ParentFunc -> getName ( ) ) , TheModule ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB ) ; Value * LSDA = emitEHLSDA ( Builder , ParentFunc ) ; Value * CastPersonality = Builder . CreateBitCast ( PersonalityFn


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit

, CPUType , CPUSubtype ) , OS , false ) ;


<s> else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode ||


<s> temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ; emit_jump_insn ( temp ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT>


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned ShuffleKind , SelectionDAG & DAG ) { const <ISA_LIT>Subtarget & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasP8Vector ( ) ) return false ; bool IsLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ShuffleKind == <NUM_LIT> ) { if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT>

) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ;


<s> BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < <NUM_LIT> ) { Opc = ABI . GetPtrSubuOp ( ) ; Amount = - Amount


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( )


<s> } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( I ) ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned TSFlags = I -> getDesc ( ) . TSFlags ; switch ( TSFlags & <STR_LIT> ) { default : if ( I -> getOpcode ( ) == <STR_LIT> ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Bits = <NUM_LIT> ; break ; } assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case


<s> const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( I -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( I -> getOperand ( AddrIdx ) . getReg ( ) ) ) || I -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo


<s> if ( info -> vrsave_mask ) fprintf ( stderr , <STR_LIT> , info -> vrsave_mask ) ; if ( info -> push_p ) fprintf ( stderr , <STR_LIT> , info -> push_p ) ; if ( info -> calls_p ) fprintf ( stderr , <STR_LIT> , info -> calls_p ) ; if ( info -> gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> gp_save_offset ) ; if ( info -> fp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> fp_save_offset ) ; if ( info -> altivec_save_offset ) fprintf ( stderr , <STR_LIT> , info -> altivec_save_offset ) ; if ( info -> spe_gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_save_offset ) ; if ( info -> vrsave_save_offset ) fprintf ( stderr , <STR_LIT> , info -> vrsave_save_offset ) ; if ( info -> lr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> lr_save_offset ) ; if ( info -> cr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> cr_save_offset ) ; if ( info -> toc_save_offset ) fprintf ( stderr , <STR_LIT> , info -> toc_save_offset ) ; if ( info -> varargs_save_offset ) fprintf ( stderr , <STR_LIT> , info -> varargs_save_offset ) ; if ( info -> total_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> total_size ) ; if ( info -> vars_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> vars_size ) ; if ( info -> parm_size ) fprintf ( stderr , <STR_LIT> , info -> parm_size ) ; if ( info -> fixed_size ) fprintf ( stderr , <STR_LIT> , info -> fixed_size ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_size ) ; if ( info -> spe_gp_size ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_size ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_size ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_size ) ; if ( info -> vrsave_size ) fprintf ( stderr , <STR_LIT> , info -> vrsave_size ) ; if ( info -> altivec_padding_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_padding_size ) ; if ( info -> spe_padding_size ) fprintf ( stderr , <STR_LIT> , info -> spe_padding_size ) ; if ( info -> lr_size ) fprintf ( stderr , <STR_LIT> , info -> lr_size ) ; if ( info -> cr_size ) fprintf ( stderr , <STR_LIT> , info -> cr_size ) ; if ( info -> toc_size ) fprintf ( stderr , <STR_LIT> , info -> toc_size ) ; if ( info -> save_size ) fprintf ( stderr , <STR_LIT>


<s> static bool isUNPCKHMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 , bool V2IsSplat = false ) { assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l + NumLaneElts / <NUM_LIT> ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ; int BitI1 = Mask [ l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat ) { if ( isUndefOrEqual ( BitI1 , NumElts ) ) return false ; } else { if ( ! isUndefOrEqual ( BitI1 , j + NumElts ) ) return false ; } } } return true


<s> enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = gen_reg_rtx ( mode1 ) ; emit_move_insn ( tmp , op1 ) ; op1 = op0 ; op0 = tmp ; } if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat


<s> if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( ST -> hasMVEIntegerOps ( ) && VT == <STR_LIT> ) return SDValue ( ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { SDLoc dl ( N ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false


<s> } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts [ i ] = true ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits ) { ZeroElts [ i ] = true ; continue ; } ConstantElts [ i ] = true ; ConstantBitData [ i ] = Bits ; } assert ( ( UndefElts | ZeroElts | ConstantElts ) . count ( ) == NumMaskElts ) ; MVT MaskSVT ; if ( VT . isFloatingPoint ( ) && ( MaskSizeInBits == <NUM_LIT> || MaskSizeInBits == <NUM_LIT> ) ) MaskSVT = <STR_LIT> ( MaskSizeInBits ) ; else MaskSVT = <STR_LIT> ( MaskSizeInBits ) ; MVT MaskVT = <STR_LIT> ( MaskSVT , NumMaskElts ) ; SDLoc DL ( Root ) ; SDValue CstOp = getConstVector ( ConstantBitData , UndefElts , MaskVT , DAG , DL ) ; DCI . AddToWorklist ( CstOp . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( VT , CstOp ) ) ; return


<s> } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue (


<s> if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ; } return ix86_delegitimize_address ( x


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize


<s> bool Changed = false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage (

) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) {


<s> m1 . as_m64 = __A ; m2 . as_m64 = __B ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) res . as_char [ i ] = ( ( unsigned char ) m1 . as_char [ i ] < ( unsigned char ) m2 . as_char [ i ] ) ? m1 . as_char [ i ] : m2 . as_char [ i ] ; return ( __m64 )


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT>


<s> bool <STR_LIT> ( CallingConv :: ID CallingConv , bool is64Bit , bool IsVarArg , bool TailCallOpt ) { if ( IsVarArg ) return false ; switch ( CallingConv


<s> tree base , count ; tree t ; if ( xstormy16_interrupt_function_p ( ) ) error ( <STR_LIT> ) ; f_base = TYPE_FIELDS ( va_list_type_node ) ; f_count = TREE_CHAIN ( f_base ) ; base = build ( COMPONENT_REF , TREE_TYPE ( f_base ) , valist , f_base , NULL_TREE ) ; count = build ( COMPONENT_REF , TREE_TYPE ( f_count ) , valist , f_count , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( base ) , virtual_incoming_args_rtx ) ; t = build ( PLUS_EXPR , TREE_TYPE ( base ) , t , build_int_cst ( NULL_TREE , INCOMING_FRAME_SP_OFFSET ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( base ) , base , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( count ) , count , build_int_cst ( NULL_TREE , current_function_args_info * UNITS_PER_WORD ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx