<s> bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler =


<s> void <ISA_LIT>AsmPrinter :: printAddrMode2OffsetOperand ( const MachineInstr * MI , int Op , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . getReg


<s> return addOffset ( MIB . addReg ( Reg , getKillRegState (


<s> lowerBRCOND ( SDValue Op , SelectionDAG & DAG )


<s> bool isImm0_15 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> const int * parm_regs ; if ( TARGET_SSE && SSE_REGNO_P ( regno ) && regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) return true ; if ( ! TARGET_64BIT ) return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) ; call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs =


<s> Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 ,


<s> void <ISA_LIT>InstPrinter :: printAddSubImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { unsigned Val = ( MO . getImm ( ) & <NUM_LIT> ) ; assert ( Val == MO . getImm ( ) && <STR_LIT> ) ; unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#' <<


<s> assert ( Insn < <NUM_LIT> ) ; int32_t DecodedValues [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Inst . addOperand ( MCOperand :: createImm ( DecodedValues [ Insn ] ) ) ; return MCDisassembler


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Jmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain


<s> bool <ISA_LIT>CA53Erratum843419Stub :: isErratum843419Sequence ( unsigned insn1 , unsigned insn2 , unsigned insn3 ) { unsigned rt ; unsigned rt2 ; bool is_pair


<s> if ( ReduceLimit != - <NUM_LIT> && ( ( int ) NumNarrows >= ReduceLimit ) ) return false ; if ( ! MinimizeSize && ! OptimizeSize && Entry . AvoidMovs && STI -> avoidMOVsShifterOperand ( ) ) return false ; unsigned Limit = ~ <NUM_LIT> ; if ( Entry . Imm1Limit ) Limit = ( <NUM_LIT> << Entry . Imm1Limit ) - <NUM_LIT> ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = MCID . getNumOperands ( ) ; i != e ; ++ i ) { if ( MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> ) continue ; if ( Entry . LowRegs1 && ! is<ISA_LIT>LowRegister ( Reg ) ) return false ; } else if ( MO . isImm ( ) && ! MCID . OpInfo [ i ] . isPredicate ( ) ) { if ( ( ( unsigned ) MO . getImm ( ) ) > Limit ) return false ; } } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg


<s> if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT>


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC


<s> if ( strcmp ( s , <STR_LIT> ) == <NUM_LIT> ) { fprintf ( file , <STR_LIT> , vname ) ; fprintf ( file , <STR_LIT> , vname ) ; } else vname = s ; break ; case INTEGER_CST : vnum = TREE_INT_CST_LOW ( val_attr ) ; fprintf ( file , <STR_LIT> , vnum , vname ) ; fprintf ( file , <STR_LIT> , vnum , vname


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true


<s> static DecodeStatus DecodeThreeAddrSRegInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftHi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftLo = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shift = ( shiftHi << <NUM_LIT> ) | shiftLo ; switch ( Inst . getOpcode ( ) ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) { return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg ) , <STR_LIT> ( fh ) ) ; return res


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm

( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( Factor , SubVecTy , Alignment , DL ) ) return Factor * BaseCost * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; if ( ST -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> && NumElts / Factor > <NUM_LIT> && VecTy -> isIntOrIntVectorTy ( ) && DL . getTypeSizeInBits ( SubVecTy ) . getFixedSize ( ) <= <NUM_LIT> ) return <NUM_LIT> * BaseCost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment

, AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> bool <ISA_LIT>BaseRegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack


<s> iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET (

GET_MODE ( reg ) , dwarf_mem , reg ) ) ;


<s> RegisterMCAsmInfoFn D ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn E ( The<ISA_LIT>64LETarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64LETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64LETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target


<s> initialize<ISA_LIT>BoolRetToIntPass ( * PassRegistry :: getPassRegistry (


<s> MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { Name . erase ( Name . end ( ) - <NUM_LIT> , Name . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( Name . str ( ) ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym =


<s> ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType (


<s> unsigned long length ; rtx x ; length = strlen ( name ) + <NUM_LIT> ; alignlength = ROUND_UP_WORD ( length ) ; ASM_OUTPUT_ASCII ( stream , name , length ) ; ASM_OUTPUT_ALIGN ( stream , <NUM_LIT> ) ; x = GEN_INT ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> + alignlength ) ; assemble_aligned_integer ( UNITS_PER_WORD , x


<s> rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , <NUM_LIT> ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx


<s> MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize , Ctx , Out ) ; EmitLabel ( Out , DoneSym


<s> Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = ( SrcVector == V1 ) && ( Current . getConstantOperandVal ( <NUM_LIT> ) == i ) ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx


<s> EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; bool IsPre = AM == <STR_LIT> || AM == <STR_LIT> ; unsigned Opcode = <NUM_LIT> ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool InsertTo64 = false ; if ( VT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = true ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT


<s> static bool isMOVLPMask ( ArrayRef < int > Mask , MVT VT ) { if ( ! VT . is128BitVector ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] ,


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtedf ; case SFmode : return gen_aarch64_rsqrtesf ; case V2DFmode : return gen_aarch64_rsqrtev2df ; case V2SFmode : return gen_aarch64_rsqrtev2sf ; case V4SFmode : return


<s> FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; if ( ! REG_P ( base_reg ) )


<s> MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( ( const <ISA_LIT>InstrInfo * ) tm . getInstrInfo ( ) ) , TD ( tm . getTargetData ( ) ) , TM ( tm )

, MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> bool <ISA_LIT>TargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return ! ( VT1 == <STR_LIT> &&


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; return true


<s> SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain , NegSize , FPSIdx } ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VTs


<s> <ISA_LIT>DynAllocaExpander :: Lowering <ISA_LIT>DynAllocaExpander :: getLowering ( int64_t CurrentOffset , int64_t AllocaAmount ) { if ( AllocaAmount < <NUM_LIT> || AllocaAmount > StackProbeSize ) return Probe ; if ( CurrentOffset + AllocaAmount <= StackProbeSize ) return Sub ; return TouchAndSub


<s> if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ( CALL_P ( prev ) || ! insn_nothrow_p ( prev ) ) ) fputs ( <STR_LIT> , out_file ) ; fputs ( <STR_LIT> , out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG


<s> getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s1 } , { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { s32 , p0 } , { s1 } ) ; auto & LoadStoreBuilder = getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s1 , p0 , <NUM_LIT> , <NUM_LIT> } , { s8 , p0 , <NUM_LIT> , <NUM_LIT> } , { s16 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . unsupportedIfMemSizeNotPow2 ( ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalForTypesWithMemDesc ( { { s64 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . maxScalar ( <NUM_LIT> , s32 ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } , Lower ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . customFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . customForCartesianProduct ( { s1 } , { s32 , s64 } ) ; if ( AEABI ( ST ) ) setFCmpLibcallsAEABI ( ) ; else setFCmpLibcallsGNU (


<s> void addVectorReg128Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] .


<s> case <STR_LIT> : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; auto Q1 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto Q2 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q3 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q4 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const uint64_t Imm = MO . getImm ( ) ; Q1 = Q1 . addImm ( Imm & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q2 = Q2 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q3 = Q3 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q4 = Q4 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else


<s> return dest ; case TLS_MODEL_LOCAL_DYNAMIC : insns = csky_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , addend ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label


<s> if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) tmp_regno = AX_REG ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) tmp_regno = DX_REG ; else tmp_regno = CX_REG ; } emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( REG_P ( this_param ) ) this_reg = this_param ; else if ( vcall_offset ) { this_reg = gen_rtx_REG ( Pmode , AX_REG ) ; emit_move_insn ( this_reg , this_param ) ; } else this_reg = NULL_RTX ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; rtx delta_dst = this_reg ? this_reg : this_param ; if ( TARGET_64BIT ) { if ( ! x86_64_general_operand ( delta_rtx , Pmode ) ) { tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; emit_move_insn ( tmp , delta_rtx ) ; delta_rtx = tmp ; } } ix86_emit_binop ( PLUS , Pmode , delta_dst , delta_rtx ) ; } if ( vcall_offset ) { rtx vcall_addr , vcall_mem , this_mem ; tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; this_mem = gen_rtx_MEM ( ptr_mode , this_reg ) ; if ( Pmode != ptr_mode ) this_mem = gen_rtx_ZERO_EXTEND ( Pmode , this_mem ) ; emit_move_insn ( tmp , this_mem ) ; vcall_addr = plus_constant ( Pmode , tmp , vcall_offset ) ; if ( TARGET_64BIT && ! ix86_legitimate_address_p ( ptr_mode , vcall_addr , true ) ) { rtx tmp2 = gen_rtx_REG ( Pmode , R11_REG ) ; emit_move_insn ( tmp2 , GEN_INT ( vcall_offset ) ) ; vcall_addr = gen_rtx_PLUS ( Pmode , tmp , tmp2 ) ; } vcall_mem = gen_rtx_MEM ( ptr_mode , vcall_addr ) ; if ( Pmode != ptr_mode ) emit_insn ( gen_addsi_1_zext ( this_reg , gen_rtx_REG ( ptr_mode , REGNO ( this_reg ) ) , vcall_mem ) ) ; else ix86_emit_binop ( PLUS , Pmode , this_reg , vcall_mem ) ; } if ( this_reg && this_reg != this_param ) emit_move_insn ( this_param , this_reg ) ; fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( ! flag_pic || targetm . binds_local_p ( function ) || TARGET_PECOFF ) ; else { tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , fnaddr ) , UNSPEC_GOTPCREL ) ; tmp = gen_rtx_CONST ( Pmode , tmp ) ; fnaddr = gen_const_mem ( Pmode , tmp ) ; } } else { if ( ! flag_pic || targetm . binds_local_p


<s> bool <ISA_LIT>LegalizerInfo :: legalizeLoadStore ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs (


<s> return const_cast < <ISA_LIT>TargetLowering * > ( &


<s> break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } for ( unsigned i = <NUM_LIT> ; i != MI . getNumOperands ( ) ; ++ i ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned SrcReg = MI . getOperand ( i ) . getReg ( ) ; if ( SrcReg >= <STR_LIT> && SrcReg <= <STR_LIT> ) VEX_L = <NUM_LIT> ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ CurOp ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MCOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ++ ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp + <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg (


<s> TargetTransformInfo <ISA_LIT>BaseTargetMachine :: getTargetTransformInfo ( const Function & F


<s> int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; enum machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) return ; cum -> words += words + offset ; if ( type ) hfa_mode = hfa_element_mode ( type , <NUM_LIT> ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size


<s> } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , Subtarget , MOHiFlag , MOLoFlag ) ; if ( isPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , false , GA ) ; } SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo ,


<s> assert ( Kind == k_InstSyncBarrierOpt && <STR_LIT>


<s> } unsigned Opc = CmpInstr . getOpcode ( ) ; unsigned NewOpc = convertToNonFlagSettingOpc ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr . setDesc ( MCID ) ; CmpInstr . removeOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr

( & CmpInstr , SrcReg , SrcReg2 , MRI ) ;


<s> ComplexRendererFns selectAddrModeUnscaled128 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root


<s> case <STR_LIT> : case <STR_LIT> : if ( V . getSimpleValueType ( ) . getVectorElementType ( ) != <STR_LIT> && V . getSimpleValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned CombineOp = V . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOp ) break ; Chain . push_back ( V ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : V = V . getOperand ( <NUM_LIT> ) ; continue ; } break ; } while ( V . hasOneUse ( ) ) ; break ; } break ; } if ( ! V . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > VMask = getPSHUFShuffleMask ( V ) ; for ( int & M : Mask ) M = VMask [ M ] ; V = DAG . getNode ( V . getOpcode ( ) , DL , V . getValueType ( ) , V . getOperand ( <NUM_LIT> ) , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; while ( ! Chain . empty ( ) ) { SDValue W = Chain . pop_back_val ( ) ; if ( V . getValueType ( ) != W . getOperand ( <NUM_LIT> ) . getValueType ( ) ) V = DAG . getBitcast ( W . getOperand ( <NUM_LIT> ) . getValueType ( ) , V ) ; switch ( W . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : V = DAG . getNode ( W . getOpcode ( ) , DL , W . getValueType ( ) , V , V ) ; break ; case <STR_LIT>


<s> unsigned NumBits2 = Ty2 -> getPrimitiveSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return


<s> const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> :

<STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ;


<s> return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( ) != <NUM_LIT> ) continue ; unsigned Opcode = OperandInstr


<s> static SMLoc incrementLoc ( SMLoc L , int Offset ) { return SMLoc :: getFromPointer ( L . getPointer ( ) + Offset


<s> const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower (


<s> unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isCmseEntry && ! isTrap && AFI -> getArgumentStackToRestore ( ) == <NUM_LIT> && STI . hasV5TOps ( ) && MBB . succ_empty ( ) && ! hasPAC ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm (


<s> OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false ; OS . PopSection ( ) ; MCSymbol * CurPCSym = Context . createTempSymbol ( ) ; OS . EmitLabel ( CurPCSym ) ; const MCExpr * Size = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( CurPCSym , MCSymbolRefExpr :: VK_None , Context ) , ExprRef , Context ) ; int64_t AbsSize ; if ( ! Size -> evaluateAsAbsolute ( AbsSize , MCA ) ) llvm_unreachable ( <STR_LIT> ) ; Size = MCConstantExpr :: create ( AbsSize


<s> if ( AreSequentialLoads ( Ld0 , Ld1 , PMul0 -> VecLd ) ) { if ( AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMACPairs . push_back ( std :: make_pair ( PMul0 , PMul1 ) ) ; return true ; } else if ( AreSequentialLoads ( Ld3 , Ld2 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul1 -> Exchange = true ; PMACPairs . push_back ( std :: make_pair ( PMul0 , PMul1 ) ) ; return true ; } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul0 -> Exchange = true ; PMACPairs . push_back ( std :: make_pair ( PMul1 , PMul0 ) ) ; return true ; } } return false ; } ; SmallPtrSet < const Instruction * , <NUM_LIT> > Paired ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { BinOpChain * PMul0 = static_cast < BinOpChain * > ( Candidates [ i ] . get ( ) ) ; if ( Paired . count ( PMul0 -> Root ) ) continue ; for ( unsigned j = <NUM_LIT> ; j < Elems ; ++ j ) { if ( i == j ) continue ; BinOpChain * PMul1 = static_cast < BinOpChain * > ( Candidates [ j ] . get ( ) ) ; if ( Paired . count ( PMul1 -> Root ) ) continue ; const Instruction * Mul0 = PMul0 -> Root ; const Instruction * Mul1 = PMul1 -> Root ; if ( Mul0 == Mul1 ) continue ; assert ( PMul0 != PMul1 &&


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>_32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>_64Target ( )


<s> return ( uint16x4_t ) __builtin_neon_vceqv4hf (


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB =


<s> fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( regs_ever_live [ <NUM_LIT> ] ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ; if ( gr_saved ) fprintf ( file , <STR_LIT> , gr_saved + <NUM_LIT>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSType


<s> Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel


<s> uint64_t Value = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ( Value >>


<s> TheModule = & M ; FrameEscape = <STR_LIT> ( TheModule , <STR_LIT> ) ; FrameRecover = <STR_LIT> ( TheModule , <STR_LIT> ) ; FrameAddress = <STR_LIT> ( TheModule ,


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> bool <ISA_LIT>InstructionSelector :: tryOptSelect ( MachineInstr & I ) { MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return


<s> MachineBasicBlock * FallthroughBB = nullptr ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) { if ( Succ -> isEHPad ( ) || ( Succ == TBB && FallthroughBB )


<s> MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . addOperand ( MO ) ; } } MachineBasicBlock * MBB = InsertPt -> getParent (


<s> bool isAMXInstruction ( MachineInstr & MI ) { if ( MI . isPHI ( ) || MI . isDebugInstr ( ) || MI

. getNumOperands ( ) < <NUM_LIT> ) return false ;


<s> static void dump_target_flags ( const char * prefix , const int flags ) { fprintf ( stderr , <STR_LIT> , prefix , flags ) ; dump_target_flag_bits ( flags ) ; fprintf ( stderr , <STR_LIT>


<s> vpminnmq_f32 ( float32x4_t a , float32x4_t b ) { return __builtin_aarch64_sminpv4sf ( a ,


<s> static void checkValueMappings ( ) { assert ( checkValueMapping ( ValueMappings [ GPR3OpsIdx ] , & PartMappings [ PMI_GPR - PMI_Min ] ) && <STR_LIT> ) ; assert ( checkValueMapping ( ValueMappings [ GPR3OpsIdx + <NUM_LIT> ] , & PartMappings [ PMI_GPR - PMI_Min ] ) && <STR_LIT> ) ; assert ( checkValueMapping ( ValueMappings [ GPR3OpsIdx + <NUM_LIT> ] , & PartMappings [ PMI_GPR - PMI_Min ] ) && <STR_LIT> ) ; assert ( checkValueMapping ( ValueMappings [ SPR3OpsIdx ] , & PartMappings [


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u32 ( unsigned int __X , unsigned int __Y ) { return ( ( __X << ( <NUM_LIT> - __Y ) ) >> ( <NUM_LIT> -


<s> if ( ! MF . getFunction ( ) -> hasFnAttribute ( Attribute :: CookieCheck ) ) { DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> return __builtin_ia32_vcvtph2qq128_mask ( __A , _mm_setzero_si128 ( ) , ( __mmask8


<s> unsigned MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { std :: vector < CPEntry > & CPEs = CPEntries [ i ] ; for ( unsigned j = <NUM_LIT> , ee = CPEs . size ( ) ; j != ee ; ++ j ) { if ( CPEs [ j ] . RefCount == <NUM_LIT> && CPEs [ j ] . CPEMI ) { RemoveDeadCPEMI ( CPEs [ j


<s> void add ( MachineInstr * MI , unsigned Idx , Color C ) { LastInst = MI ; LastInstIdx = Idx ; LastColor = C ; assert ( ( KillInstIdx == <NUM_LIT> || LastInstIdx < KillInstIdx ) &&


<s> return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \


<s> if ( Splat != - <NUM_LIT> ) return Splat ; int Rot = getT2SOImmValRotateVal ( Arg ) ; if ( Rot != - <NUM_LIT> ) return Rot ; return - <NUM_LIT>


<s> unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; Type * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits ( ) ) return false ; unsigned NumDstEls = DstTyL . first * DstTyL . second . getVectorNumElements ( ) ; unsigned NumSrcEls = SrcTyL . first * SrcTyL . second .


<s> unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned * , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = NULL ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case


<s> I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) if ( CallInst * CI = dyn_cast < CallInst > ( J ) ) if ( Function * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return MadeChange ; Metrics . analyzeBasicBlock ( * I , * TTI , EphValues ) ; } unsigned LoopSize = Metrics . NumInsts ; if ( ! LoopSize ) LoopSize = <NUM_LIT> ; unsigned ItersAhead = TTI -> getPrefetchDistance ( ) / LoopSize ; if ( ! ItersAhead ) ItersAhead = <NUM_LIT> ; SmallVector < std :: pair < Instruction * , const SCEVAddRecExpr * > , <NUM_LIT> > PrefLoads ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { Value * PtrValue ; Instruction * MemI ; if ( LoadInst * LMemI = dyn_cast < LoadInst > ( J ) ) { MemI = LMemI ; PtrValue = LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( J ) ) { if ( ! PrefetchWrites ) continue ; MemI = SMemI ; PtrValue = SMemI -> getPointerOperand ( ) ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE ->


<s> if ( pFormat . hasGOT ( ) ) reserveOne (


<s> if ( TARGET_LS64 ) aarch64_init_ls64_builtins


<s> if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm =


<s> MemOpQueue MemOps ; unsigned CurrBase = <NUM_LIT> ; unsigned CurrOpc = ~ <NUM_LIT> ; <STR_LIT> CurrPred = <STR_LIT> ; unsigned Position = <NUM_LIT> ; assert ( Candidates . size ( ) == <NUM_LIT> ) ; assert ( MergeBaseCandidates . size ( ) == <NUM_LIT> ) ; LiveRegsValid = false ; for ( MachineBasicBlock :: iterator I = MBB . end ( ) , MBBI ; I != MBB . begin ( ) ; I = MBBI ) { MBBI = std :: prev ( I ) ; if ( FixInvalidRegPairOp ( MBB , MBBI ) ) continue ; ++ Position ; if ( isMemoryOp ( * MBBI ) ) { unsigned Opcode = MBBI -> getOpcode ( ) ; const MachineOperand & MO = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned Base = getLoadStoreBaseOp ( * MBBI ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MBBI , PredReg ) ; int Offset = getMemoryOpOffset ( MBBI ) ; if ( CurrBase == <NUM_LIT> ) { CurrBase = Base ; CurrOpc = Opcode ; CurrPred = Pred ; MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { bool Overlap = false ; if ( isLoadSingle ( Opcode ) ) { Overlap = ( Base == Reg ) ; if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugValue ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred =


<s> if ( ! Subtarget . hasAVX ( ) ) return ; const LLT v16s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v32s8 ,


<s> atype = ix86_get_builtin_type ( ix86_builtin_func_args [ i ] ) ; args = tree_cons ( NULL , atype , args ) ; } type = build_function_type ( rtype , args ) ; } else { unsigned index = tcode - IX86_BT_LAST_FUNC - <NUM_LIT> ; enum ix86_builtin_func_type icode ; icode = ix86_builtin_func_alias_base [ index ] ; type = ix86_get_builtin_func_type


<s> NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 = false ; IsISA3_0 = false ; UseLongCalls = false ; SecurePlt = false ; VectorsUseTwoUnits = false ; Use<ISA_LIT>PreRASchedStrategy = false ; Use<ISA_LIT>PostRASchedStrategy = false ; HasPOPCNTD =


<s> sh_media_STLO_Q ( p , <NUM_LIT> , k ) ; sh_media_STLO_Q ( p , <NUM_LIT> , k ) ; sh_media_STHI_Q ( p ,


<s> bool note_unused_pragma_disinterrupt ( const char * const & s , const pragma_entry & e ,


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! <ISA_LIT>FI || <ISA_LIT>FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( )


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; const unsigned ProbeSize = getStackProbeSize ( * MF ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( physSPReg ) . addReg ( FinalStackPtr ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor (


<s> V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ; } if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ; SmallVector < int , <NUM_LIT> > PermMask ( ( unsigned ) Size , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++


<s> return rx_expand_void_builtin_1_arg ( op , gen_clrpsw , false ) ; case RX_BUILTIN_SETPSW : if ( ! valid_psw_flag ( op , <STR_LIT> ) ) return NULL_RTX ; return rx_expand_void_builtin_1_arg ( op , gen_setpsw , false ) ; case RX_BUILTIN_INT : return rx_expand_void_builtin_1_arg ( op , gen_int , false ) ; case RX_BUILTIN_MACHI : return rx_expand_builtin_mac ( exp , gen_machi ) ; case RX_BUILTIN_MACLO : return rx_expand_builtin_mac ( exp , gen_maclo ) ; case RX_BUILTIN_MULHI : return rx_expand_builtin_mac ( exp , gen_mulhi ) ; case RX_BUILTIN_MULLO : return rx_expand_builtin_mac ( exp , gen_mullo ) ; case RX_BUILTIN_MVFACHI : return rx_expand_int_builtin_0_arg ( target , gen_mvfachi ) ; case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc ( exp ) ; case RX_BUILTIN_MVTIPL : return rx_expand_builtin_mvtipl ( op ) ; case RX_BUILTIN_RACW : return rx_expand_void_builtin_1_arg ( op , gen_racw , false ) ; case RX_BUILTIN_ROUND : return rx_expand_builtin_round


<s> unsigned Field = cast < ConstantInt > ( Idx ) -> getZExtValue ( ) ; if ( Field ) TotalOffs += DL . getStructLayout ( StTy ) -> getElementOffset ( Field ) ; } else { Type * Ty = GTI . getIndexedType ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( Idx ) ) { if ( CI -> isZero ( ) ) continue ; TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , NIsKill , TotalOffs ) ; if ( ! N ) return false ; NIsKill = true ; TotalOffs = <NUM_LIT> ; } uint64_t ElementSize = DL . getTypeAllocSize ( Ty ) ; std :: pair < unsigned , bool > Pair = getRegForGEPIndex ( Idx ) ; unsigned IdxN = Pair . first ; bool IdxNIsKill = Pair . second ; if ( ! IdxN ) return false ; if ( ElementSize != <NUM_LIT> ) { unsigned C = fastEmit_i ( VT , VT , <STR_LIT> , ElementSize ) ; if ( ! C ) return false ; IdxN = emitMul_rr ( VT , IdxN , IdxNIsKill , C , true ) ; if ( ! IdxN ) return false ; IdxNIsKill = true ; } N = fastEmit_rr ( VT , VT , <STR_LIT> ,


<s> if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear ( )


<s> unsigned R0 = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned R12 = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( * MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned


<s> bool isThumb ( const MCSubtargetInfo &


<s> int reg = I -> getOperand ( opcount ) . getReg ( ) ; if ( isGPR ( reg ) && ! ( I -> mayLoad ( ) && ! opcount ) ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg ( reg ) ) ; MBB -> insert ( I , cmpInst ) ; MachineInstr * MItest = BuildMI ( MF , DL3 , TII -> get


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32


<s> if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getBitcast ( VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) ,


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & FrameLowering


<s> } SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Passv64i1ArgInRegs ( dl , DAG , Chain , ValToCopy , RegsToPass , VA , RVLocs [ ++ I ] , Subtarget ) ; assert ( <NUM_LIT> == RegsToPass . size ( ) && <STR_LIT> ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RVLocs [ I ] . getLocReg ( ) ) ; } else { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; } for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , dl , Reg . first , Reg . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget . is64Bit ( ) && ! Subtarget . isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RetValReg ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; <STR_LIT> opcode =


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { MCE . emitByte ( Val & <NUM_LIT> ) ; Val >>= <NUM_LIT>


<s> inline vector signed int vec_msums ( vector signed short a1 , vector signed short a2 , vector signed int a3 ) { return ( vector signed int ) __builtin_altivec_vmsumshs ( ( vector signed short ) a1 , ( vector signed short ) a2 , ( vector signed


<s> __ev64_opaque__ ev ; ev = ( __ev64_opaque__ ) __ev_create_fs ( a ,


<s> switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case 'q' : case 'v' : if ( RegName [ <NUM_LIT> ] == 's' ) return RegName


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . GetEnumValue ( ) ) { case <ISA_LIT>ABIInfo :: ABI ::


<s> return __builtin_aarch64_smax_nanv2df ( __a ,


<s> if ( MBBI != MBB . begin ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { MachineInstr * PrevMI = std :: prev ( MBBI ) ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> )


<s> LOHInstToLabel [ MI ] = LOHLabel ; OutStreamer . EmitLabel ( LOHLabel ) ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > TmpStr ; raw_svector_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI


<s> if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; llvm_unreachable (


<s> ArrayRef < int > Mask = SV -> getMask ( ) ; bool CanFold = true ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = Mask [ i ] == ( int ) ( ( i & <NUM_LIT> ) ? i + NumElts : i ) ; if ( CanFold ) { SDValue Op0 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 -> getOperand ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; return DAG . getVectorShuffle ( VT , dl , Sub , Add , Mask ) ; } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! DCI . isBeforeLegalize ( ) && DCI . isBeforeLegalizeOps ( ) && N1 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue BC0 = N0 . getOperand ( <NUM_LIT> ) ; EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > (


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , SDLoc ( MemcpyCall ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> ) Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ) ; seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> TripCountPattern ( Instruction * P , Value * TC , FixedVectorType * VT ) : Predicate ( P )


<s> const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v8s16 } , Legal ) ; setAction ( { G_FPEXT , s64 } , Legal ) ; setAction ( { G_FPEXT , <NUM_LIT> ,


<s> if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { static const TypeConversionCostTblEntry < <STR_LIT> > NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT


<s> void setVarArgsFrameIndex ( int Index ) { VarArgsFrameIndex =


<s> bool SrcIsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = emitIntExt ( SrcVT . getSimpleVT ( ) , SrcReg , <STR_LIT> , ! Signed ) ; if ( ! SrcReg ) return false ; SrcIsKill = true ; } unsigned Opc ; if ( SrcVT


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } unsigned LaneTmp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp2 ) . addReg ( <STR_LIT> ) . addReg ( LaneReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg (

WdTmp2 ) . addReg ( WdTmp2 ) . addReg ( LaneTmp2 ) ;


<s> else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( MO . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Reloc = ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> static inline int getMClassFlagsMask ( StringRef Flags ) { if ( Flags . empty


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( DestVT . bitsGT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ; } return


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_conflict ( void * const TM_buff ) { texasru_t texasru = *


<s> switch ( Kind ) { case k_Immediate : break ; case k_Memory : delete Mem .


<s> if ( CStart && CStep && CStep -> isNullValue ( ) ) { if ( CStart -> isNullValue ( ) ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , VT ) , <NUM_LIT> ) ; else return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { auto EltCnt = VT . getVectorElementCount ( ) ; int ExtBits = <STR_LIT> / EltCnt . Min ; EVT ExtVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ExtBits ) ; EVT SplatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtVT , EltCnt ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , dl , SplatVT ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectVectorAddr ( MemSDNode * Parent , SDValue BasePtr , SDValue IndexOp , SDValue ScaleOp , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { <ISA_LIT>ISelAddressMode AM ; AM . IndexReg = IndexOp ; AM . Scale = cast < ConstantSDNode > ( ScaleOp ) -> getZExtValue ( ) ; unsigned AddrSpace = Parent -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( BasePtr ) ; MVT VT = BasePtr . getSimpleValueType ( ) ; if ( matchVectorAddress ( BasePtr , AM )


<s> static __inline qword si_gb ( qword a ) { vec_uint4 bits ; vec_uint4 bytes ; bits = vec_sl ( vec_and ( ( vec_uint4 ) ( a ) , vec_splat_u32 ( <NUM_LIT> ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; bytes = ( vec_uint4 ) vec_sums ( ( vec_int4 ) ( bits ) , ( ( vec_int4 ) { <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_sld ( bytes , bytes ,


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this


<s> unsigned postOffset ( Align Alignment = Align :: None ( ) ) const { unsigned PO = Offset + Size ; const Align PA = std :: max


<s> bool hasRDRAND ( ) const { return HasRDRAND


<s> MaskedScatterSDNode * MSC = cast < MaskedScatterSDNode > ( Op ) ; assert ( MSC && <STR_LIT> ) ; bool IsFixedLength = MSC -> getMemoryVT ( ) . isFixedLengthVector ( ) ; SDValue Index = MSC -> getIndex ( ) ; SDValue Chain = MSC -> getChain ( ) ; SDValue StoreVal = MSC -> getValue ( ) ; SDValue Mask = MSC -> getMask ( ) ; SDValue BasePtr = MSC -> getBasePtr ( ) ; <STR_LIT> IndexType = MSC -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool NeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; EVT VT = StoreVal . getSimpleValueType ( ) ; EVT IndexVT = Index . getSimpleValueType ( ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; EVT MemVT = MSC -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getScatterVecOpcode ( IsScaled ,


<s> if ( ! IsMemcpy ) return true ; if ( ! ConstantSize && Alignment >= Align ( <NUM_LIT> ) ) return true ; if ( ConstantSize && ConstantSize -> getZExtValue ( ) > Subtarget . getMaxInlineSizeThreshold ( ) && ConstantSize -> getZExtValue (

) < Subtarget . getMaxMemcpyTPInlineSizeThreshold ( ) ) return true ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_LONGJMP ( SDValue Op , SelectionDAG & DAG ,

const <ISA_LIT>TargetLowering & TLI ) const {


<s> virtual void * getAdjustedAnalysisPointer ( const


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , Offset , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) .


<s> unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -=


<s> llvm :: dbgs ( ) . write_hex ( Binary )


<s> if ( Disable<ISA_LIT>LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; if ( MF . getFunction ( ) -> optForMinSize ( ) ) Changed |= removeRedundantLEAs ( LEAs ) ; Changed |= removeRedundantAddrCalc


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts (


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) )


<s> if ( mips_cfg_in_reorg ( ) ) { mips_df_reorg ( ) ; free_bb_for_insn ( )


<s> MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildOr ( OriginalResult , Results [ <NUM_LIT> ] , Results [ <NUM_LIT> ] ) ; } break ; } case G_FCONSTANT


<s> int legitimate_pic_operand_p ( rtx x ) { if ( CONSTANT_P ( x ) && flag_pic && ( GET_CODE ( x ) == SYMBOL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP (

x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) ) ) return <NUM_LIT> ;


<s> return MIB . addReg ( GlobalBaseReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addConstantPoolIndex


<s> getTargetStreamer ( ) . EmitARM64WinCFIMachineFrame ( ) ; return false


<s> break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : emitMOVi2piecesInstruction ( MI


<s> inline void classify_registers ( const_tree , int bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word =


<s> __rv . __o = __builtin_neon_vld3_dupv4bf ( ( const __builtin_neon_bf * ) __ptr ) ; return __rv .


<s> bool <ISA_LIT>AsmParser :: parseParenSuffix ( StringRef Name , OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( )


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SuperReg ) ; else for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ; return nullptr


<s> auto getScaledOffsetDup = [ ] ( SDValue BitCast , int & LaneC , MVT & CastVT ) { if ( BitCast . getOpcode ( ) != <STR_LIT> || BitCast . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Extract = BitCast . getOperand ( <NUM_LIT> ) ; unsigned ExtIdx = Extract . getConstantOperandVal ( <NUM_LIT> ) ; unsigned SrcEltBitWidth = Extract . getScalarValueSizeInBits ( ) ; unsigned ExtIdxInBits = ExtIdx * SrcEltBitWidth ; unsigned CastedEltBitWidth = BitCast . getScalarValueSizeInBits ( ) ; if ( ExtIdxInBits % CastedEltBitWidth != <NUM_LIT> ) return false ; LaneC += ExtIdxInBits / CastedEltBitWidth ; unsigned SrcVecNumElts = Extract . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) / CastedEltBitWidth ; CastVT = <STR_LIT> ( BitCast . getSimpleValueType ( ) .


<s> while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; if ( isOperationLegal ( <STR_LIT> , VT ) && EltSizeInBits <= <NUM_LIT> && ( EltSizeInBits != <NUM_LIT> || ! Subtarget . isPMULLDSlow (


<s> N -> getOperand ( i ) ; if ( NextInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue PreviousInput = IsRoundOfExtLoad ? N -> getOperand ( i - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( PreviousInput ) ; LoadSDNode * LD2 = dyn_cast < LoadSDNode > ( NextInput ) ; if ( IsRoundOfExtLoad && LD2 -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isConsecutiveLS ( LD2 , LD1 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreConsecutiveLoads = false ; if ( ! isConsecutiveLS ( LD1 , LD2 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreReverseConsecutive = false ; if ( ! InputsAreConsecutiveLoads && ! InputsAreReverseConsecutive ) return SDValue ( ) ; } assert ( ! ( InputsAreConsecutiveLoads && InputsAreReverseConsecutive ) && <STR_LIT> ) ; SDValue FirstLoadOp = IsRoundOfExtLoad ? FirstInput . getOperand ( <NUM_LIT> ) : FirstInput ; SDValue LastLoadOp = IsRoundOfExtLoad ? N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( FirstLoadOp ) ; LoadSDNode * LDL = dyn_cast < LoadSDNode > ( LastLoadOp ) ; if ( InputsAreConsecutiveLoads ) { assert ( LD1 && <STR_LIT> ) ; return DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , dl , LD1 -> getChain ( ) , LD1 -> getBasePtr ( ) , LD1 -> getPointerInfo ( ) , LD1 -> getAlignment ( ) ) ; } if ( InputsAreReverseConsecutive ) { assert ( LDL && <STR_LIT> ) ; SDValue Load = DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , dl , LDL -> getChain ( ) , LDL -> getBasePtr ( ) , LDL -> getPointerInfo ( ) , LDL -> getAlignment ( ) ) ; SmallVector < int , <NUM_LIT> > Ops ; for ( int i = N -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) Ops . push_back ( i ) ; return DAG . getVectorShuffle ( N -> getValueType ( <NUM_LIT> ) , dl , Load , DAG . getUNDEF ( N -> getValueType ( <NUM_LIT> ) ) , Ops ) ; } return SDValue (


<s> bool isCortexA7 ( ) const { return CPUString ==


<s> else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> + <NUM_LIT> ) ; return true ; case DIV : * total = COSTS_N_INSNS ( <NUM_LIT>


<s> <ISA_LIT>PostRASchedStrategy ( const MachineSchedContext * C ) : MLI ( C -> MLI ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( C -> MF -> getSubtarget ( ) . getInstrInfo ( )

) ) , MBB ( nullptr ) , HazardRec ( nullptr ) {


<s> for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast


<s> return new <ISA_LIT>AddressTypePromotion (


<s> if ( bs_size > <NUM_LIT> ) emit_stack_probe ( r3 ) ; if ( size == <NUM_LIT> ) ; else if ( size <= PROBE_INTERVAL ) emit_stack_probe ( r2 ) ; else if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i ; emit_move_insn ( r2 , GEN_INT ( - ( first + PROBE_INTERVAL ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , r2 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r2 ) ) ) ; emit_stack_probe ( r2 ) ; for ( i = <NUM_LIT> * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_insn ( gen_rtx_SET ( VOIDmode , r2 , plus_constant ( Pmode , r2 , - PROBE_INTERVAL ) ) ) ; emit_stack_probe ( r2 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , r2 , plus_constant ( Pmode , r2 , ( i - PROBE_INTERVAL ) - size ) ) ) ; emit_stack_probe ( r2 ) ; } else { HOST_WIDE_INT rounded_size ; emit_move_insn ( r2 , GEN_INT ( - first ) ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , r2 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r2 ) ) ) ; if ( rounded_size > ( <NUM_LIT> << <NUM_LIT> ) ) { emit_move_insn ( r3 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , r3 , gen_rtx_PLUS ( Pmode , r2 , r3 ) ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , r3 , gen_rtx_PLUS ( Pmode , r2 , GEN_INT ( - rounded_size ) ) ) ) ; emit_insn ( gen_probe_stack_range ( r2 , r2 , r3 ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( VOIDmode , r2 , plus_constant ( Pmode , r2 , rounded_size - size ) ) ) ; emit_stack_probe ( r2 ) ; } } emit_insn ( gen_blockage ( )


<s> return decodeRegisterClass ( Inst , RegNo


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_Mask ( Op , Subtarget , DAG ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == InVT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG .


<s> if ( isLoadAfterStore ( SU ) && CurSlots < <NUM_LIT> ) { unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget


<s> return MCDisassembler :: Fail ; } if ( isBigEndian ) { insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } else { insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } return MCDisassembler


<s> unsigned Block = MI -> getParent ( ) -> getNumber ( ) ; const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; } )


<s> const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * IStart = TRI -> getCalleeSavedRegsViaCopy ( Entry -> getParent ( ) ) ; if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; Register NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind


<s> static rtx mmix_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , MMIX_RETURN_VALUE_REGNUM


<s> static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts /