<s> MI -> getParent ( ) -> erase ( MI ) ; return true ; } if ( ! WidenVMOVS || ! MI -> isCopy ( ) || Subtarget . isCortexA15 ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << * MI


<s> return __builtin_mve_vrev64q_m_sv8hi ( __arm_vuninitializedq_s16 ( )


<s> unsigned getCheriReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >=

<STR_LIT> && RegIdx . RealRegister <= <STR_LIT> ) ) ;


<s> Cond = Cond -> getOperand ( <NUM_LIT> ) ; } isAnd = false ; SDValue SetCC0 , SetCC1 ; switch ( Cond -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : isAnd = true ; case <STR_LIT> : case <STR_LIT> : SetCC0 = Cond -> getOperand ( <NUM_LIT> ) ; SetCC1 = Cond -> getOperand ( <NUM_LIT> ) ; break ; } ; if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1


<s> if ( Function * F = CI -> getCalledFunction ( ) ) { unsigned Opcode = <NUM_LIT> ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return true ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc_copysign : case LibFunc_copysignf : continue ; case LibFunc_copysignl : return true ; case LibFunc_fabs : case LibFunc_fabsf : case LibFunc_fabsl : continue ; case LibFunc_sqrt : case LibFunc_sqrtf : case LibFunc_sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc_floor : case LibFunc_floorf : case LibFunc_floorl : Opcode = <STR_LIT> ; break ; case LibFunc_nearbyint : case LibFunc_nearbyintf : case LibFunc_nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc_ceil : case LibFunc_ceilf : case LibFunc_ceill : Opcode = <STR_LIT> ; break ; case LibFunc_rint : case LibFunc_rintf : case LibFunc_rintl : Opcode = <STR_LIT> ; break ; case LibFunc_round : case LibFunc_roundf : case LibFunc_roundl : Opcode = <STR_LIT> ;


<s> DOUT << <STR_LIT> << stackSize << <STR_LIT> ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm ( ) ; DOUT << <STR_LIT> << Offset << <STR_LIT> ; DOUT << <STR_LIT> ; MI . getOperand ( i - <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; MI . getOperand ( i ) . ChangeToRegister ( getFrameRegister


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm |= <NUM_LIT> ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm8 ( Inst , imm , Address , Decoder ) ) )


<s> static bool containsOnlyConstantData ( const Constant * C ) { if ( isa < ConstantData > ( C ) ) return true ; if ( isa < GlobalValue > ( C ) || isa < BlockAddress > ( C ) || isa < ConstantExpr > ( C ) ) return false ; return all_of ( C -> operands ( ) , [ ] ( const Use & U ) { return containsOnlyConstantData ( cast < Constant > ( & U ) ) ; } )


<s> printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { if ( RegSet . count ( Reg ) ) return true ; for ( const uint16_t * Alias = TM . getRegisterInfo (


<s> case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; } unsigned EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; MachineBasicBlock :: iterator InsertPoint = MI


<s> static SDValue getAtomicLoadArithTargetConstant ( SelectionDAG * CurDAG , SDLoc dl , enum AtomicOpc & Op , MVT NVT , SDValue Val , const <ISA_LIT>Subtarget * Subtarget ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Val ) ) { int64_t CNVal = CN -> getSExtValue ( ) ; if ( ( int32_t ) CNVal != CNVal ) return Val ; if ( CNVal == INT32_MIN ) return CurDAG -> getTargetConstant ( CNVal , NVT ) ; if ( Op == ADD ) { if ( ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) && ! Subtarget -> slowIncDec ( ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal , NVT ) ; } if ( Op == ADD && Val . hasOneUse ( ) ) { if ( Val . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; return Val . getOperand ( <NUM_LIT> ) ; } if ( Val . getOpcode ( ) == <STR_LIT> && NVT == <STR_LIT> && Val . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { Op = SUB


<s> ConstantSDNode * RHSConstSplat = nullptr ; if ( auto * RHSBV = dyn_cast < BuildVectorSDNode > ( N1 ) ) RHSConstSplat = RHSBV -> getConstantSplatNode ( ) ; if ( ! RHSTrunc && ! RHSConstSplat ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , WideVT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT> ) ; if ( RHSConstSplat ) { N1 = DAG . getNode ( <STR_LIT> , DL , WideVT . getScalarType ( ) , SDValue ( RHSConstSplat , <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > C ( WideVT . getVectorNumElements ( ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , DL , WideVT , C ) ; } else if ( RHSTrunc ) { N1 = N1 -> getOperand ( <NUM_LIT> ) ; } SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , WideVT , N0 , N1 ) ; unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : return Op


<s> m = adjust_address ( op1 , mode , <NUM_LIT> ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else emit_insn ( load_unaligned ( op0 , op1 ) ) ; } else if ( MEM_P ( op0 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_STORE && optimize_insn_for_speed_p ( ) ) { m = adjust_address ( op0 , mode , <NUM_LIT> ) ; emit_insn ( extract ( m , op1 , const0_rtx )


<s> Value * <ISA_LIT>IREmitter :: visitUMUL ( const SDNode * N


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > registered_target (


<s> case Match_UImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_N1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm7_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm11_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed : case


<s> unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { unsigned NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) ,

NewIn128 ) . addReg ( In128 ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) ;


<s> MCLOHType Kind ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Id = getParser ( ) . getTok ( ) . getIntVal ( ) ; if ( Id <= - <NUM_LIT> && ! isValidMCLOHType ( Id ) ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } else { StringRef Name = getTok ( ) . getIdentifier ( ) ; int Id = MCLOHNameToId ( Name ) ; if ( Id == - <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } Lex ( ) ; int NbArgs = MCLOHIdToNbArgs ( Kind ) ; assert ( NbArgs != - <NUM_LIT> && <STR_LIT> ) ; SmallVector < MCSymbol * , <NUM_LIT> > Args ; for ( int Idx = <NUM_LIT> ; Idx < NbArgs ; ++ Idx ) { StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT> == NbArgs )


<s> if ( ! DoMerge ) return false ; bool isDPR = NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( isAM5 ) Offset = <STR_LIT> ( ( AddSub == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , true , ( isDPR ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( isAM2 ) Offset = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; else Offset = AddSub == <STR_LIT> ? - Bytes : Bytes ; if ( isLd ) { if ( isAM5 ) BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define ) ; else if ( isAM2 ) BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; else BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( isAM5 ) BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg

( MO . getReg ( ) , getKillRegState ( MO . isKill ( ) ) ) ;


<s> inline vector signed char vec_or ( vector signed char a1 , vector signed char a2 ) { return ( vector signed char ) __builtin_altivec_vor ( ( vector signed int


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return


<s> switch ( T ) { case RT64_NONE : return RT32_NONE ; case RT64_64 : llvm_unreachable ( <STR_LIT> ) ; case RT64_32 : case RT64_32S : return RT32_32


<s> void load_pic_register ( ) { int orig_flag_pic = flag_pic ; if ( ! flag_pic ) abort ( ) ; if ( get_pc_symbol_name [ <NUM_LIT> ] == <NUM_LIT> ) { int align ; ASM_GENERATE_INTERNAL_LABEL ( get_pc_symbol_name , <STR_LIT> , <NUM_LIT> ) ; text_section ( ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , <STR_LIT> , <NUM_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; } global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; get_pc_symbol = gen_rtx_SYMBOL_REF ( Pmode , get_pc_symbol_name ) ; flag_pic =


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qiv4hi ( ( int16x4_t


<s> bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE


<s> Value * <ISA_LIT>IREmitter :: visitCMPZ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> } case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , AD , Op , AD . getValue ( <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , T , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { T , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ; SDNode * AD = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> ) ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( AD , <NUM_LIT> ) , Op , SDValue ( AD , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isELF ; IsLinux = true ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isCygwin ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isMingw ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isWindows ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isWindows ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isDarwin ; DarwinVers = <NUM_LIT> ; } } if ( TargetType == isDarwin ||


<s> rtx unspec = XEXP ( body , <NUM_LIT> ) ; int half_elts = GET_MODE_NUNITS ( GET_MODE ( unspec ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ) ; lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ; INSN_CODE ( insn ) = -


<s> void setSRetReturnReg ( Register Reg


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Target : llvm_unreachable ( <STR_LIT> ) ; break ; case MCExpr :: Constant : break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS (


<s> return TargetTriple . isWindowsItaniumEnvironment ( )


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t

( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> bool <ISA_LIT>Subtarget :: useAA ( ) const { return UseAA


<s> if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { Register Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; Register DstRegX = DstMO . getReg ( ) ; Register DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; } else { LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; } LLVM_DEBUG ( dbgs ( )


<s> cfun -> machine -> callee_saved_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += <NUM_LIT> ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ?

crtl -> outgoing_args_size : <NUM_LIT> ) ;


<s> if ( write_symbols != NO_DEBUG ) { output_file_directive ( asm_out_file , main_input_filename ) ; if ( want_version ) aputs ( <STR_LIT>


<s> consume_whitespace ( ) ; int oldpos = pos ; char * token = match_identifier ( ) ; if ( ! token ) { diag ( pos , <STR_LIT> ) ; return <NUM_LIT> ; } if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_CHAR ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_SHORT ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_INT ; else if ( ! strcmp ( token , <STR_LIT> ) ) { consume_whitespace ( ) ; oldpos = pos ; char * mustbelongordbl = match_identifier ( ) ; if ( ! mustbelongordbl ) typedata -> base = BT_LONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGLONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGDOUBLE ; else { typedata -> base = BT_LONG ; pos = oldpos ; } } else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DOUBLE ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_INT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_BOOL ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_STRING ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL32 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL64 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( poly8x16_t ) __builtin_aarch64_qtbx3v16qi ( ( int8x16_t ) r , __o , ( int8x16_t )


<s> if ( ! optimize_size ) break ; case AND : case IOR : case XOR : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; else if ( rtx_equal_p ( dst , op1 ) && low_register_operand ( op0 , SImode ) ) action = action_for_partial_flag_setting == SKIP ? SKIP : SWAP_CONV ; break ; case ASHIFTRT : case ASHIFT : case LSHIFTRT : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; else if ( low_register_operand ( op0 , SImode ) && CONST_INT_P ( op1 ) && IN_RANGE ( INTVAL ( op1 ) , <NUM_LIT> , <NUM_LIT> ) ) action = action_for_partial_flag_setting ; break ; case ROTATERT : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; break ; case NOT : if ( low_register_operand ( op0 , SImode ) ) action = action_for_partial_flag_setting ; break ; case NEG : if ( low_register_operand ( op0 , SImode ) ) action = CONV ; break ; case CONST_INT : if ( CONST_INT_P ( src ) && IN_RANGE ( INTVAL ( src ) , <NUM_LIT> , <NUM_LIT> ) ) action = action_for_partial_flag_setting ; break ; case REG : break ; default : break ; } } if ( action != SKIP ) { rtx ccreg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , ccreg ) ; rtvec vec ; if ( action == SWAP_CONV ) { src = copy_rtx ( src ) ; XEXP ( src , <NUM_LIT> ) = op1 ; XEXP ( src , <NUM_LIT> ) = op0 ; pat = gen_rtx_SET ( dst , src ) ; vec = gen_rtvec ( <NUM_LIT> , pat


<s> return IsLoad ? ( STI . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasAVX ( ) ?


<s> EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; <STR_LIT> Flags = Arg . Flags ; Flags . setOrigAlign ( TLI . getABIAlignmentForCallingConv (


<s> if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) ,


<s> return ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && ( ( offset


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec -> dumpSU ( * Available . begin ( ) , dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; ) ; return * Available . begin ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; Available . dump ( * HazardRec ) ; ) ; Candidate Best ; for ( auto * SU : Available ) { Candidate c ( SU , * HazardRec ) ; if ( Best . SU == nullptr || c < Best ) { Best = c ; DEBUG ( dbgs ( ) <<


<s> Register TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> int <ISA_LIT>RegisterInfo :: getFrameIndexOffset ( MachineFunction & MF , int FI ) const { const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - TFI . getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) Offset -= TFI . getOffsetOfLocalArea ( ) ; return Offset


<s> raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT>


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large ) return <STR_LIT> ; if ( GV && GV -> isAbsoluteSymbolRef ( ) ) return <STR_LIT> ; if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) )


<s> bool isCCRegNumber ( ) const { return ( Kind == Expression && isUInt < <NUM_LIT> > ( getExprCRVal ( ) ) )

|| ( Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ) ; }


<s> if ( Ctx && ( Value >= <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Ctx && ( Value & <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Ctx && ( Value >= <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Ctx && ( Value & <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Ctx && ( Value >= <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Ctx && ( Value & <NUM_LIT> ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Ctx ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT>


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction


<s> if ( optimize_function_for_size_p ( cfun )


<s> SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) { Parser . Lex ( ) ; const MCExpr * Disp = MCConstantExpr :: Create ( Val , getContext ( ) ) ; if ( SegReg ) return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , Scale , Start , End , Size ) ; return <STR_LIT> ( Disp , Start , End , Size ) ; } else if ( getLexer ( ) . is ( AsmToken :: Star ) ) { Parser . Lex ( ) ; SMLoc IdxRegLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( IndexReg , IdxRegLoc , End ) ) return ErrorOperand ( IdxRegLoc , <STR_LIT> ) ; Scale = Val ; } else return ErrorOperand ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: Plus ) || getLexer ( ) . is ( AsmToken :: Minus ) ) { bool isPlus = getLexer ( ) . is ( AsmToken :: Plus ) ; Parser . Lex ( ) ; SMLoc PlusLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Star ) ) { Parser . Lex ( ) ; SMLoc IdxRegLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( IndexReg , IdxRegLoc , End ) ) return ErrorOperand ( IdxRegLoc , <STR_LIT> ) ; Scale = Val ; } else if ( getLexer ( ) . is


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT DestVecType ; if ( VT == <STR_LIT> ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> Addr . setOffsetReg ( constrainOperandRegClass ( II , Addr . getOffsetReg ( ) , II . getNumDefs ( ) + Idx + <NUM_LIT> ) ) ; if ( Addr . getOffsetReg ( ) ) { assert ( Addr . getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; bool IsSigned = Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ; MIB . addReg ( Addr . getReg ( ) ) ; MIB . addReg ( Addr . getOffsetReg ( ) ) ; MIB . addImm ( IsSigned ) ; MIB . addImm ( Addr . getShift ( ) != <NUM_LIT> ) ; } else MIB . addReg ( Addr . getReg ( ) ) . addImm ( Offset ) ; } if ( MMO ) MIB .


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; unsigned Limit = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) break ; const MCInstrDesc & MCID = MI . getDesc ( ) ; const TargetRegisterClass * RegClass = TII . getRegClass ( MCID , i , TRI , MF ) ; if ( RegClass && ! RegClass -> contains ( <STR_LIT> ) ) HasNonSPFrameIndex = true ; switch ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> )


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForStrnlen ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue

Src , SDValue MaxLength , MachinePointerInfo SrcPtrInfo ) const {


<s> vst1q_f64 ( float64_t * a , float64x2_t b ) { __builtin_aarch64_st1v2df ( ( __builtin_aarch64_simd_df * ) a


<s> static unsigned int rs6000_xcoff_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ( flags & SECTION_CODE ) != <NUM_LIT> || ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes

( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ;


<s> size_type getNodeIndex ( const Node &


<s> return ( uint16x8_t ) __builtin_neon_vreinterpretv8hiv16qi (


<s> unsigned char <ISA_LIT>Subtarget :: classifyLocalReference ( const GlobalValue * GV ) const { if ( is64Bit ( ) ) return <STR_LIT> ; if ( ! isPositionIndependent ( ) ) return


<s> if ( m_arglist . length ( ) < expected ) error_at ( location


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; return true


<s> return Op . isMem ( ) && ( Op . Mem . SegReg == <NUM_LIT> || Op . Mem . SegReg == <STR_LIT> ) && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast <

MCConstantExpr > ( Op . Mem . Disp ) -> getValue ( ) == <NUM_LIT> && Op . Mem . BaseReg == basereg && Op . Mem . IndexReg == <NUM_LIT> ;


<s> else if ( op_value < <NUM_LIT> || op_value >= ( ( int ) ARRAY_SIZE ( nds32_intrinsic_register_names ) + <NUM_LIT> ) ) { error ( <STR_LIT> ) ; } else { fprintf ( stream , <STR_LIT> , nds32_intrinsic_register_names [ op_value - <NUM_LIT> ] ) ; } return ; default : output_operand_lossage ( <STR_LIT> ) ; break ; } switch ( GET_CODE ( x ) ) { case LABEL_REF : case SYMBOL_REF : output_addr_const ( stream


<s> static unsigned int aarch64_min_divisions_for_recip_mul ( enum machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) == <NUM_LIT> ) return aarch64_tune_params . min_div_recip_mul_sf ; return aarch64_tune_params .


<s> bool hasCustomConstantPool ( ) const override { return true


<s> if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand


<s> static Reloc :: Model getEffectiveRelocModel ( CodeModel :: Model CM , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) || CM == CodeModel :: JITDefault ) return Reloc :: Static ; return * RM


<s> static __inline unsigned int _MM_GET_EXCEPTION_MASK ( void ) { return _mm_getcsr ( ) &


<s> TII = TM -> getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true


<s> if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned MovCCOpc = isThumb ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) ; UpdateValueMap ( I ,


<s> unsigned Size = AI -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool HasAtomicCmpXchg ; if ( Subtarget -> isMClass ( ) ) HasAtomicCmpXchg = Subtarget -> hasV8MBaselineOps ( ) ; else if ( Subtarget -> isThumb ( ) ) HasAtomicCmpXchg = Subtarget -> hasV7Ops ( ) ; else HasAtomicCmpXchg = Subtarget -> hasV6Ops (


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return


<s> <ISA_LIT>64elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model

RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) :


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( )


<s> bool hasDSPR3 ( ) const { return getSTI ( ) . getFeatureBits


<s> return ( int16x4_t ) __builtin_neon_vcvtsv4hf (


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Name = Tok . getString ( ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchRegisterNameAlias ( Head , MatchKind ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidVectorKind ( Kind , MatchKind ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Parser . Lex ( ) ; Reg =


<s> MachineBasicBlock * Succ = * MBB -> succ_begin ( ) ; MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; MachineInstr * PredMI = & Pred


<s> bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb216 , MI , Insn16 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ITBlock . instrInITBlock ( ) ) Result = MCDisassembler :: SoftFail ; Check ( Result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; ITBlock . setITState ( Firstcond , Mask ) ; if ( Firstcond == <STR_LIT> && ! isPowerOf2_32 ( Mask ) ) CS << <STR_LIT> ; } return Result ; } if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Insn32 = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; Result = decodeInstruction ( DecoderTableMVE32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( isVPTOpcode ( MI . getOpcode ( ) ) && VPTBlock . instrInVPTBlock ( ) ) Result = MCDisassembler :: SoftFail ; Check ( Result , AddThumbPredicate ( MI ) ) ; if ( isVPTOpcode ( MI . getOpcode ( ) ) ) { unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; VPTBlock . setVPTState ( Mask ) ; } return Result ; } Result = decodeInstruction ( DecoderTableThumb32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb232 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { bool ExpectLabel = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ; if ( ! ExpectLabel ) { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } LLVM_FALLTHROUGH ; } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S


<s> EmitTargetCodeForMemmove ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int


<s> switch ( relax_type ) { case RELAX_ORI : if ( ( sym_type == UNSPEC_TLSLE || sym_type == UNSPEC_GOTOFF ) && ( recog_memoized ( use_insn ) == CODE_FOR_addsi3 ) ) { pat = XEXP ( PATTERN ( use_insn ) , <NUM_LIT> ) ; new_pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , XEXP ( pat , <NUM_LIT> ) , XEXP ( pat , <NUM_LIT> ) ) , UNSPEC_ADD32 ) ; validate_replace_rtx ( pat , new_pat , use_insn ) ; nds32_group_infos . safe_push (


<s> StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ; assert ( StoreNode && <STR_LIT> ) ; SDValue Value = StoreNode -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT


<s> Blend1 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range1 . first = std :: min ( Range1 . first , M ) ; Range1 . second = std :: max ( Range1 . second , M ) ; } else { M -= NumElts ; Blend2 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range2 . first = std :: min ( Range2 . first , M ) ; Range2 . second = std :: max ( Range2 . second , M ) ; } } } if ( ! ( <NUM_LIT> <= Range1 . first && Range1 . second < NumEltsPerLane ) || ! ( <NUM_LIT> <= Range2 . first && Range2 . second < NumEltsPerLane ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && ( Blend1 || Blend2 ) ) return SDValue ( ) ; auto RotateAndPermute = [ & ] ( SDValue Lo , SDValue Hi , int RotAmt , int Ofs ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Rotate = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , DAG . getBitcast ( ByteVT , Hi ) , DAG . getBitcast ( ByteVT , Lo ) , DAG . getConstant ( Scale * RotAmt , DL , <STR_LIT> ) ) ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int Lane = <NUM_LIT> ; Lane != NumElts ; Lane += NumEltsPerLane ) { for ( int Elt = <NUM_LIT> ; Elt != NumEltsPerLane ; ++ Elt ) { int M = Mask [ Lane + Elt ] ; if ( M < <NUM_LIT> )


<s> bool hasFP ( const MachineFunction &


<s> use_sibcall_p = ( mips_function_ok_for_sibcall ( function , NULL ) && const_call_insn_operand ( fnaddr , Pmode ) ) ; if ( ! use_sibcall_p && ( mips_got_symbol_type_p ( mips_classify_symbol ( fnaddr , SYMBOL_CONTEXT_LEA ) ) ) ) { cfun -> machine -> global_pointer = TARGET_CALL_SAVED_GP ? <NUM_LIT> : GLOBAL_POINTER_REGNUM ; cfun -> machine -> must_initialize_gp_p = true ; SET_REGNO ( pic_offset_table_rtx , cfun -> machine -> global_pointer ) ; mips_emit_loadgp ( ) ; } temp1 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; temp2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { mips_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = mips_add_offset ( temp2


<s> bool <ISA_LIT>BaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == <NUM_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false ; } return true


<s> DOUT << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V32HImode : if ( TARGET_AVX512BW ) { tmp = gen_reg_rtx ( V16HImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v32hi ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v32hi ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V64QImode : if ( TARGET_AVX512BW ) { tmp = gen_reg_rtx ( V32QImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v64qi ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v64qi ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V16SFmode : tmp = gen_reg_rtx ( V8SFmode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v16sf ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v16sf ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8DFmode : tmp = gen_reg_rtx ( V4DFmode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v8df ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v8df ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V16SImode : tmp = gen_reg_rtx ( V8SImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v16si ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v16si ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8DImode : tmp = gen_reg_rtx ( V4DImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v8di ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v8di ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8QImode : default : break ; } if ( use_vec_extr ) { tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( elt ) ) ) ; tmp = gen_rtx_VEC_SELECT ( inner_mode , vec , tmp ) ; if ( inner_mode == QImode || inner_mode == HImode ) { tmp = gen_rtx_ZERO_EXTEND (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> SDValue LDL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return createLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = createLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || ( ExtType == <STR_LIT> ) ) return LWR ; assert ( ( VT == <STR_LIT> ) &&


<s> __builtin_ia32_pmovusqb512mem_mask ( ( unsigned long long * ) __P , (


<s> MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( <ISA_LIT>MCExpr :: isSupportedBinaryExpr ( VK , BE ) ) return <ISA_LIT>MCExpr :: Create ( VK , Expr , getContext ( ) ) ; const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res ; } if ( const MCUnaryExpr * UN = dyn_cast < MCUnaryExpr > ( Expr ) ) { const MCExpr * UnExp = evaluateRelocExpr ( UN -> getSubExpr ( ) , RelocStr ) ; Res = MCUnaryExpr :: Create ( UN -> getOpcode ( ) , UnExp , getContext ( ) ) ; return Res


<s> pConfig . targets ( ) . setEndian ( TargetOptions :: Little ) ; unsigned int bitclass ; llvm :: Triple :: ArchType arch = pConfig . targets ( ) . triple ( ) . getArch ( ) ; assert ( arch == llvm :: Triple :: x86 || arch == llvm :: Triple :: x86_64 ) ; if ( arch == llvm :: Triple :: x86 || pConfig . targets ( ) . triple ( ) . getEnvironment ( ) == llvm :: Triple :: GNUX32 ) { bitclass = <NUM_LIT> ; } else { bitclass = <NUM_LIT> ; } pConfig . targets ( ) . setBitClass ( bitclass ) ; pConfig . attribute ( ) . constraint ( ) . enableWholeArchive ( ) ; pConfig . attribute ( ) . constraint ( ) . enableAsNeeded ( ) ; pConfig . attribute ( ) . constraint ( ) . setSharedSystem


<s> Parser . Lex ( ) ; if ( ! has<ISA_LIT> ( ) ) return Error ( L , <STR_LIT> ) ; if ( isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; return false


<s> return ( __m256 ) __builtin_ia32_broadcastf32x4_256_mask ( ( __v4sf ) __A , ( __v8sf ) _mm256_setzero_ps ( )


<s> unsigned <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead =


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg


<s> if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; if ( RepeatedMask [ i % LaneSize ] == - <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + Size ; else if ( RepeatedMask [ i % LaneSize ] + ( i / LaneSize ) * LaneSize != Mask [ i ]


<s> MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) ; MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; } else { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } else


<s> BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) { if ( BB -> isReturnBlock ( ) ) { IP = BB -> end ( ) ; -- IP ; MachineBasicBlock :: iterator I2 = IP ; while ( I2 != BB -> begin ( ) && ( -- I2


<s> if ( offset > - <NUM_LIT> ) insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; RTX_FRAME_RELATED_P ( emit_move_insn ( tmpr , GEN_INT ( offset ) ) ) = <NUM_LIT> ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { if ( insn_const_int_ok_for_constraint ( offset , CONSTRAINT_L ) ) emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; emit_move_insn ( tmpr , GEN_INT ( offset ) ) ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr


<s> case <STR_LIT> : Opc = <STR_LIT> ; assert ( UseRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; bool IsVSFRC = ( ResultReg != <NUM_LIT> ) && isVSFRCRegister ( ResultReg ) ; if ( IsVSFRC && ( Opc == <STR_LIT> ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSFRC ? <STR_LIT> : <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Addr . Base .


<s> return ( __m512i ) __builtin_ia32_permvardi512_mask ( ( __v8di ) __Y , ( __v8di ) __X , ( __v8di ) _mm512_undefined_si512 ( ) , (


<s> case AsmToken :: Comma : case AsmToken :: RBrac : case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( BaseReg , nullptr , S , E ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Parser . Lex ( ) ; break ; case AsmToken :: Minus : break ; } <ISA_LIT>Operand * Offset = nullptr ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Offset = ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , Offset ) : <STR_LIT> ( BaseReg , Offset ) ) ; Operands . push_back ( Offset ) ; return MatchOperand_Success


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ; V0 = RegInfo . createVirtualRegister (


<s> if ( A . getSimpleValueType ( ) != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue V = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A ) ; return V


<s> gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code

== HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ;


<s> case E_V2DFmode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V2DF ] ; break ; case E_V2DImode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V2DI ] ; break ; case E_V4SFmode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V4SF ] ; break ; case E_V4SImode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V4SI ] ; break ; case E_V8HImode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V8HI ] ; break ; case E_V16QImode : call = rs6000_builtin_decls [ RS6000_BIF_VEC_EXT_V16QI ] ; break ; default : break ; } } if ( call ) { tree result = build_call_expr ( call , <NUM_LIT> , arg1 , arg2 ) ; arg1_inner_type = TREE_TYPE ( arg1_type ) ; result = fold_convert ( arg1_inner_type , result ) ; * res = resolved ; return result ; } } arg1_inner_type = TREE_TYPE ( arg1_type ) ; tree subp = build_int_cst ( TREE_TYPE ( arg2 ) , TYPE_VECTOR_SUBPARTS ( arg1_type ) - <NUM_LIT> ) ; arg2 = build_binary_op ( loc , BIT_AND_EXPR , arg2 , subp , <NUM_LIT> ) ; tree decl = build_decl ( loc , VAR_DECL , NULL_TREE , arg1_type ) ; DECL_EXTERNAL ( decl ) = <NUM_LIT> ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; DECL_CONTEXT ( decl ) = current_function_decl ; TREE_USED ( decl ) = <NUM_LIT> ; TREE_TYPE ( decl ) = arg1_type


<s> machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > <NUM_LIT> ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + <NUM_LIT> ) >> <NUM_LIT> : <NUM_LIT> ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts )


<s> if ( UnsupportedFPMode ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue (


<s> unsigned <ISA_LIT>TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const

SelectionDAG & , unsigned Depth ) const {


<s> if ( ConstraintCode . size ( ) == <NUM_LIT> ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ; case 'Q' : return InlineAsm :: Constraint_Q ; case 'R' : return InlineAsm :: Constraint_R ; case 'S' : return InlineAsm :: Constraint_S ; case 'T' : return InlineAsm


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc &&


<s> unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg ) ; if ( ResultReg == <NUM_LIT> ) return false ; UpdateValueMap ( I , ResultReg


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) { SubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg (


<s> static unsigned AlignOffset ( unsigned Offset , unsigned Align


<s> high >>= <NUM_LIT> ; if ( low == <NUM_LIT> || low == high ) return num_insns_constant_gpr ( high ) + <NUM_LIT> ; else if ( high == <NUM_LIT> ) return num_insns_constant_gpr ( low ) + <NUM_LIT> ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + <NUM_LIT> ) ; } else return


<s> void llvm :: Lower<ISA_LIT>MachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , const AsmPrinter & AP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI


<s> Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { assert ( MInfo . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( MInfo . FrameConstructionID == MachineOutlinerTailCall || MInfo . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It ,


<s> const unsigned * <ISA_LIT>BaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF


<s> const MCExpr * <ISA_LIT>ELFTargetObjectFile :: getDebugThreadLocalSymbol (


<s> MBB -> addSuccessor ( EndMBB ) ; } for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; BuildMI ( XMMSaveMBB , DL , TII -> get ( <STR_LIT> ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i )

. getReg ( ) ) . addMemOperand ( MachineMemOperand ( PseudoSourceValue :: getFixedStack ( RegSaveFrameIndex ) , MachineMemOperand :: MOStore , Offset , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> bool ix86_using_red_zone ( void ) { return TARGET_RED_ZONE &&


<s> const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const bool ArePtrs64bit = ABI . ArePtrs64bit ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; if ( Size == <NUM_LIT> ) { if ( isMicro<ISA_LIT> ) { LL = <STR_LIT> ; SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB =


<s> return ( __m128i ) __builtin_ia32_lddqu ( (


<s> const char * output_ieee_ccmpeq ( rtx_insn * insn ,


<s> return ( ( qword ) ( vec_rl ( ( vec_ushort8 ) ( a )


<s> __builtin_ia32_pmovuswb256mem_mask ( ( __v16qi * ) __P , (


<s> if ( MAYBE_MMX_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( MAYBE_SSE_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( GET_CODE ( x ) == PLUS ) return reg_class_subset_p ( class , GENERAL_REGS ) ? class : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( reg_class_subset_p ( class , Q_REGS ) ) return class ; if ( reg_class_subset_p ( Q_REGS , class )


<s> bool hasRor ( ) const { return HasRor


<s> static bool aarch64_needs_frame_chain ( void ) { if ( frame_pointer_needed || crtl -> calls_eh_return ) return true ; bool is_leaf = crtl -> is_leaf && ! df_regs_ever_live_p ( LR_REGNUM ) ; if ( flag_omit_leaf_frame_pointer && is_leaf ) return false ; return


<s> unsigned Reg = getFPReg ( MI . getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI . killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT>

|| MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) {


<s> unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i


<s> switch ( code ) { case LE : case LEU : case GT : case GTU : std :: swap ( lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ; std :: swap ( hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ; code = swap_condition ( code ) ; case LT : case LTU : case GE : case GEU : { bool uns = ( code == LTU || code == GEU ) ; rtx ( * sbb_insn ) ( machine_mode , rtx , rtx , rtx ) = uns ? gen_sub3_carry_ccc : gen_sub3_carry_ccgz ; if ( ! nonimmediate_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! x86_64_general_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! register_operand ( hi [ <NUM_LIT> ] , submode ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; if ( ( uns && ! nonimmediate_operand ( hi [ <NUM_LIT> ] , submode ) ) || ( ! uns && ! x86_64_general_operand ( hi [ <NUM_LIT> ] , submode ) ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; emit_insn ( gen_cmp_1 ( submode , lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_SCRATCH ( submode ) ; emit_insn ( sbb_insn ( submode , tmp , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_REG ( uns ? CCCmode : CCGZmode , FLAGS_REG ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } default : break ; } label2 = gen_label_rtx ( ) ; code1 = code ; code2 = swap_condition ( code ) ; code3 = unsigned_condition ( code ) ; switch ( code ) { case LT : case GT : case LTU : case GTU : break ; case LE : code1 = LT ; code2 = GT ; break ; case GE : code1 = GT ; code2 = LT ; break ; case LEU : code1 = LTU ; code2 = GTU ; break ; case GEU : code1 = GTU ; code2 = LTU ; break ; case EQ : code1 = UNKNOWN ; code2 = NE ; break ; case NE : code2 = UNKNOWN ; break ; default : gcc_unreachable ( ) ; } if ( code1 != UNKNOWN ) ix86_expand_branch ( code1 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; if ( code2 != UNKNOWN ) ix86_expand_branch ( code2 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label2 ) ; ix86_expand_branch ( code3 , lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ,


<s> return new <ISA_LIT>SEDAGToDAGISel ( TM , OptLevel


<s> DirtySuccessors . push_back ( & MBB ) ; BlockStates [ MBB . getNumber ( ) ] .


<s> if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( td )


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeLEAs ( ) ) ; addPass ( create<ISA_LIT>CallFrameOptimization (


<s> bool isFP64 ( ) const { return STI . getFeatureBits ( ) [


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property


<s> static int no_previous_def ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi ->


<s> break ; default : assert ( <NUM_LIT> ) ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; return


<s> if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' ,


<s> MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> unsigned * StubCallAddr = StubCallAddrPlus4 - <NUM_LIT> ; unsigned * OrigCallAddr = OrigCallAddrPlus4 - <NUM_LIT> ; void * Target = JITCompilerFunction ( StubCallAddr ) ; unsigned OrigCallInst = * OrigCallAddr ; if ( ( OrigCallInst >> <NUM_LIT> ) == <NUM_LIT> ) { intptr_t Offset = ( ( intptr_t ) Target - ( intptr_t ) OrigCallAddr ) >> <NUM_LIT> ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset < ( <NUM_LIT> << <NUM_LIT> ) ) { OrigCallInst &= ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ; OrigCallInst |= ( Offset & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) << <NUM_LIT> ; * OrigCallAddr =


<s> return vabs_f32 ( __a ) <= vabs_f32 (


) _mm256_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> machine_mode mode ; if ( ! TARGET_SSE ) return <NUM_LIT> ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) return <NUM_LIT> ; if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) || ( ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || GET_MODE_CLASS ( pred_mode ) == MODE_VECTOR_FLOAT ) && float_vector_all_ones_operand ( x , mode ) ) ) { if ( mode == VOIDmode ) mode = pred_mode ; switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : if ( TARGET_AVX512F ) return <NUM_LIT> ; break ; case <NUM_LIT> : if ( TARGET_AVX2 ) return <NUM_LIT> ; break ; case <NUM_LIT> : if ( TARGET_SSE2 ) return <NUM_LIT> ; break ; case <NUM_LIT> : gcc_unreachable ( ) ; default : break ; } } return <NUM_LIT>


<s> if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) { split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; count = INTVAL ( operands [ <NUM_LIT> ] ) & ( GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) ; if ( count >= half_width ) { emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; if ( count > half_width ) emit_insn ( gen_lshr3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - half_width ) ) ) ; } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { machine_mode half_mode ; gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high


<s> <ISA_LIT>Relocator :: Result gotoff32 ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: Address GOT_ORG = helper_GOT_ORG ( pParent ) ; Relocator :: Address S = pReloc . symValue ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; pReloc . target ( ) = ( ( S +


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return


<s> void emit_tfmode_unop ( enum rtx_code code , rtx * operands ) { if ( TARGET_HARD_QUAD ) emit_hard_tfmode_operation ( code , operands ) ; else emit_soft_tfmode_unop ( code , operands


<s> Register V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; V2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V2 ) . addReg ( V0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg (


<s> if ( ! Pic || ! ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCInst Inst ; if ( IsReg ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RegOrOffset ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> __rv . __o = __builtin_neon_vld4v8qi ( ( const


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue (


<s> } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isUInt < <NUM_LIT> > ( CN -> getZExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand


<s> if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= <NUM_LIT> ) return false ; if ( crtl -> is_leaf &&


<s> unsigned Imm = <STR_LIT> ( opc , PostIdxReg . ShiftImm , PostIdxReg . ShiftTy ) ; Inst . addOperand ( MCOperand :: createImm (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> ) return InsertBitToMaskVector ( Op , DAG ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; auto * N2C = cast < ConstantSDNode > ( N2 ) ; unsigned IdxVal = N2C -> getZExtValue ( ) ; if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget -> hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41


<s> static bool arm_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; struct expand_vec_perm_d d ; int i , nelt , which ; if ( ! VALID_NEON_DREG_MODE ( vmode ) && ! VALID_NEON_QREG_MODE ( vmode ) ) return false ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . testing_p = ! target ; nelt = GET_MODE_NUNITS ( d . vmode ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p


getScalarSizeInBits ( ) == <NUM_LIT> ) return true ;


<s> unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; if ( SubIdx == <STR_LIT> && Subtarget . hasMTHC1 ( ) ) { BuildMI ( MBB , I , dl , get ( FP64 ? <STR_LIT> : <STR_LIT> ) ,


<s> uint64_t Size = TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( ZCPV -> getType ( ) ) ; OutStreamer . EmitValue (


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return Subtarget -> hasMVEFloatOps ( ) ; case <STR_LIT> : return Subtarget -> useFPVFMx16 ( ) ; case <STR_LIT> : return Subtarget -> useFPVFMx ( ) ; case <STR_LIT> : return Subtarget -> useFPVFMx64 ( ) ; default : break ; } return false


<s> if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) { assert ( LHS . getValueType ( ) != <STR_LIT> ) ; if ( LHS . getValueType ( ) == <STR_LIT> && ! FullFP16 ) { LHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS ) ; } Opcode = <STR_LIT> ; } else if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = RHS . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( SubOp0 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } } if ( Opcode == <NUM_LIT> ) Opcode =


<s> static const TargetRegisterClass * getRegClassForSVT ( <STR_LIT> SVT , bool Is<ISA_LIT>64 ) { assert ( ( Is<ISA_LIT>64 || SVT != <STR_LIT> ) && <STR_LIT> ) ; switch ( SVT ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> Value = <STR_LIT> ( Value ) ; Shift = <NUM_LIT> ; } if ( isAdvSIMDModImm ) { SDLoc dl ( Op ) ; SDValue Mov ; if ( LHS ) Mov = DAG . getNode ( NewOp , dl , MovTy , * LHS , DAG . getConstant ( Value , dl , <STR_LIT> ) , DAG . getConstant ( Shift , dl , <STR_LIT> ) ) ; else Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl


<s> d . op1 = operands [ <NUM_LIT> ] ; sel = operands [ <NUM_LIT> ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; int ei = INTVAL ( e ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm ,


<s> if ( I -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! ( ( Subtarget -> hasSSE1 ( ) && RetVT == <STR_LIT> ) || ( Subtarget -> hasSSE2 ( ) && RetVT == <STR_LIT> ) ) ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( CI ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * CmpRHSC = dyn_cast < ConstantFP > ( CmpRHS ) ; if ( CmpRHSC && CmpRHSC -> isNullValue ( ) ) CmpRHS = CmpLHS ; } unsigned CC ; bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>SSEConditionCode ( Predicate ) ; if ( CC > <NUM_LIT> ) return false ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; bool HasAVX = Subtarget -> hasAVX ( ) ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill (


<s> __o = __builtin_aarch64_ld2rv2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregoiv2si (


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand (

<NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits


<s> return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE


<s> bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBUtils -> clear ( ) ; WaterList . clear ( )


<s> rtx op2 = expand_normal ( arg2 ) ; rtx pat , addr ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = Pmode ; machine_mode mode2 = Pmode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , tmode ) ) op0 = copy_to_mode_reg ( tmode , op0 ) ; op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( op1 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op2 ) ; } else { op1 = copy_to_mode_reg ( mode1 , op1


<s> MachineOperand DestBase = MI -> getOperand ( <NUM_LIT> ) ; uint64_t DestDisp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand SrcBase = MI -> getOperand ( <NUM_LIT> ) ; uint64_t SrcDisp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t Length = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( DestBase ) . addImm ( DestDisp ) . addImm ( Length ) . addOperand ( SrcBase ) . addImm ( SrcDisp ) ; MI -> eraseFromParent ( ) ; return MBB


<s> DiagnosticPredicate isSVEAddSubImm ( ) const { if ( ! isShiftedImm ( ) && ( ! isImm ( ) || ! isa < MCConstantExpr > ( getImm ( ) ) ) ) return DiagnosticPredicateTy :: NoMatch ; bool IsByte = std :: is_same < int8_t , std :: make_signed_t < T >> :: value || std :: is_same < int8_t


<s> bool isMemDisp12Len8 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange ( Mem . Length . Imm , <NUM_LIT> ,


<s> void \ read_only_private_data_section ( ) \ { \ if ( in_section != read_only_private_data ) \ { \ fprintf ( asm_out_file , <STR_LIT> , \ xcoff_private_data_section_name

) ; \ in_section = read_only_private_data ; \ } \ }


<s> return Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ||

Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ;


<s> return ( __m512i ) __builtin_ia32_pmovzxbq512_mask ( ( __v16qi ) __A , ( __v8di ) _mm512_undefined_epi32 ( ) , (


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase


<s> if ( isFP64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int )


<s> if ( TARGET_LOONGSON_MMI && VECTOR_MODE_P ( mode ) ) return <NUM_LIT> ; return GET_MODE_BITSIZE ( mode )


<s> APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( Op1 , DemandedMask , TLO ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , Known , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ; } return SDValue (


<s> darwin_file_start ( ) ; if ( X86_FILE_START_VERSION_DIRECTIVE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( X86_FILE_START_FLTUSED ) fputs (


<s> set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , <STR_LIT> ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , <STR_LIT> ) ; } } if ( TARGET_ARCH64 ) { set_optab_libfunc ( smul_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( sdiv_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( udiv_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( smod_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( umod_optab , SImode , <NUM_LIT> ) ; if ( SUN_INTEGER_MULTIPLY_64 ) { set_optab_libfunc ( smul_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( udiv_optab , DImode


<s> bool ret = false ; bool always_inline = ( DECL_DISREGARD_INLINE_LIMITS ( callee ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( callee ) ) ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( ( ! always_inline && caller_opts -> x_target_flags != callee_opts -> x_target_flags ) || ( caller_opts -> x_target_flags & ~ always_inline_safe_mask ) != ( callee_opts -> x_target_flags & ~ always_inline_safe_mask ) ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( ! always_inline && caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath && ( ! ipa_fn_summaries || ipa_fn_summaries -> get ( cgraph_node ::

get ( callee ) ) -> fp_expressions ) ) ret = false ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) { APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , <STR_LIT> , <STR_LIT> , DAG ) ) { SDLoc dl ( N ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue


<s> return ( __m128i ) __builtin_ia32_psrlv4si ( ( __v4si )


<s> static DecodeStatus DecodeF128RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo % <NUM_LIT> || RegNo >

<NUM_LIT> ) return MCDisassembler :: Fail ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } unsigned SoImm = MO . getImm ( ) ; int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( Scale


<s> ConstantInt * CInt ; if ( match ( V , m_ConstantInt ( CInt ) ) ) { return false ; } auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; Value * Val , * LHS , * RHS ; if ( match ( V , m_Trunc ( m_Value ( Val ) ) ) ) { if ( cast < TruncInst > ( I ) -> getDestTy ( ) -> getIntegerBitWidth ( ) == MaxBitWidth ) return IsNarrowSequence < MaxBitWidth > ( Val , VL ) ; } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { return false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) != MaxBitWidth ) return false ; if ( match ( Val , m_Load ( m_Value ( ) ) ) ) { VL . push_back ( Val ) ; VL . push_back ( I ) ; return true