<s> if ( b & <NUM_LIT> ) { vec_uint4 nan_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 a_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; if ( b & <NUM_LIT> ) { vec_uint4 a_nan = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; a_nan = vec_or ( a_nan , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_nan , x . v ) , a_inf ) ) ; a_nan = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_nan , ( vec_uchar16 ) a_nan , splat_hi ) ; result = vec_or ( result , a_nan ) ; } if ( b & <NUM_LIT> ) { a_inf = vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_inf , x . v ) , a_inf ) ; a_inf = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_inf , ( vec_uchar16 ) a_inf , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( a_inf , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( a_inf , sign ) , result ) ; } } if ( b & <NUM_LIT> ) { vec_uint4 iszero = ( vec_uint4 ) vec_cmpeq ( aabs , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; if ( b & <NUM_LIT> ) { vec_uint4 denorm_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 isdenorm = vec_nor ( ( vec_uint4 ) vec_cmpgt ( aabs , denorm_mask ) , iszero ) ; isdenorm = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) isdenorm , ( vec_uchar16 ) isdenorm , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( isdenorm , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) .


<s> int sparc_absnegfloat_split_legitimate ( rtx x , rtx y ) { if ( GET_CODE ( x )


<s> vmull_p8 ( poly8x8_t a , poly8x8_t b ) { poly16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; if ( LoRegList [ i ] != <STR_LIT> ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , <STR_LIT> , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ,


<s> static bool isVUZP_v_undef_Mask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; unsigned Half = NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = SelectPairHalf ( NumElts , M , i ) ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += Half ) { unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpins32 ( unsigned int __data2 , unsigned int __data1 ,


<s> bool selectBDXAddr20Pair ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base ,


<s> ME -> print ( OS , MAI ) ; return ; } else SRE = cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_None && <STR_LIT> ) ; SRE -> getSymbol ( ) . print ( OS , MAI ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS <<


<s> <ISA_LIT>LoopPreIncPrep ( ) : FunctionPass ( ID ) , TM


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable (


<s> return ! Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> :


<s> static section * rs6000_xcoff_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align


<s> static inline void aarch64_add_sp ( int scratchreg , HOST_WIDE_INT delta , bool emit_move_imm ) { aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , delta , true


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( Desc . TSFlags & <STR_LIT> ) return false ; static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex128CompressTable ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; auto I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstrBuilder MIB ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; unsigned RegSize = PVT . getStoreSize ( ) ; assert ( PVT == <STR_LIT> && <STR_LIT> ) ; unsigned Buf = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned JmpLoc = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) ; const unsigned FP = <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FP ) . addReg ( Buf ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JmpLoc , RegState :: Define ) . addReg ( Buf ) . addImm ( RegSize ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <ISA_LIT> ) . addReg ( Buf ) . addImm ( <NUM_LIT> * RegSize ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( Buf , RegState :: Kill ) . addImm ( <NUM_LIT> * RegSize ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( JmpLoc , RegState :: Kill ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return MBB


<s> assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) ) && <STR_LIT> ) ; SDValue Lo = V1 , Hi = V2 ; int Rotation = matchShuffleAsByteRotate ( Lo , Hi , Mask ) ; if ( Rotation <= <NUM_LIT> ) return SDValue


<s> newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx ,


<s> bool OtherUsers = false , KillsAddendSrc = false ; for ( auto J = std :: prev ( I ) , JE = MachineBasicBlock :: iterator ( AddendMI ) ; J != JE ; -- J ) { if ( J -> readsVirtualRegister ( AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { OtherUsers = true ; break ; } if ( J -> modifiesRegister ( AddendSrcReg , TRI ) || J -> killsRegister ( AddendSrcReg , TRI ) ) { KillsAddendSrc = true ; break ; } } if ( OtherUsers || KillsAddendSrc ) continue ; Register OldFMAReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned KilledProdOp = <NUM_LIT> , OtherProdOp = <NUM_LIT> ; Register Reg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg3 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LIS -> getInterval ( Reg2 ) . Query ( FMAIdx ) . isKill ( ) && Reg2 != OldFMAReg ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } else if ( LIS -> getInterval ( Reg3 ) . Query ( FMAIdx ) . isKill ( ) && Reg3 != OldFMAReg ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } if ( ! KilledProdOp ) continue ; if ( Register :: isVirtualRegister ( AddendSrcReg ) && ! LIS -> getInterval ( AddendSrcReg ) . liveAt ( FMAIdx ) ) continue ; Register KilledProdReg = MI . getOperand ( KilledProdOp ) . getReg ( ) ; Register OtherProdReg = MI . getOperand ( OtherProdOp ) . getReg ( ) ; unsigned AddSubReg = AddendMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned KilledProdSubReg = MI . getOperand ( KilledProdOp ) . getSubReg ( ) ; unsigned OtherProdSubReg = MI . getOperand ( OtherProdOp ) . getSubReg ( ) ; bool AddRegKill = AddendMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool KilledProdRegKill = MI . getOperand ( KilledProdOp ) . isKill ( ) ; bool OtherProdRegKill = MI . getOperand ( OtherProdOp ) . isKill ( ) ; bool AddRegUndef = AddendMI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool KilledProdRegUndef = MI . getOperand ( KilledProdOp ) . isUndef ( ) ; bool OtherProdRegUndef = MI . getOperand ( OtherProdOp


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRri ( SDNode * Op , SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } } Base = Addr


<s> rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P (

mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ;


<s> return ( __m256i ) __builtin_ia32_psubusb256_mask ( ( __v32qi ) __A , ( __v32qi )


<s> MF = & Fn ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) { Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple

:: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand


<s> if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister


<s> unsigned getT2AddrModeImm12OffsetOpValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> case TYPE_CR64 : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M16INT : case TYPE_M32INT : case TYPE_M64INT : case TYPE_M1616 : case TYPE_M1632 : case TYPE_M1664 : return translateRMMemory ( mcInst , insn , true


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_i32scatter_epi32 ( int *


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition = ~ <NUM_LIT> ; NextSymbolIsThumb = false


<s> } else { Binary |= getMachineOpValue ( MI , MO1 ) ; } if ( MI . getOperand ( OpIdx ) . isImm ( ) && ! TID . OpInfo [ OpIdx ] . isPredicate ( ) && ! TID .

OpInfo [ OpIdx ] . isOptionalDef ( ) ) Binary |= ( getMachineOpValue ( MI , OpIdx ) / <NUM_LIT> ) << <STR_LIT> ;


<s> std :: error_code FileError ; std :: string FileName = <STR_LIT> ; FileName += MF . getName ( ) ; FileName += <STR_LIT> ; raw_fd_ostream FileOut ( FileName , FileError ) ; if ( FileError ) errs ( ) << FileError . message ( ) ; writeGadgetGraph ( FileOut , MF , Graph . get ( ) ) ; FileOut . close ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( EmitDotOnly ) return false ; } int FencesInserted ; if ( ! OptimizePluginPath . empty ( ) ) { if ( ! OptimizeDL . isValid ( ) ) { std :: string ErrorMsg ; OptimizeDL = llvm :: sys :: DynamicLibrary :: getPermanentLibrary ( OptimizePluginPath . c_str ( ) , & ErrorMsg ) ; if ( ! ErrorMsg . empty ( ) ) report_fatal_error ( Twine ( <STR_LIT> ) + ErrorMsg + <STR_LIT> ) ; OptimizeCut = ( OptimizeCutT ) OptimizeDL . getAddressOfSymbol ( <STR_LIT> ) ; if ( ! OptimizeCut ) report_fatal_error ( <STR_LIT> ) ; } FencesInserted = hardenLoadsWithPlugin ( MF , std :: move ( Graph ) ) ; } else { FencesInserted = hardenLoadsWithHeuristic ( MF , std :: move ( Graph


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; auto PState = <STR_LIT> ( pstate_field ) ; if ( PState && PState -> haveFeatures ( Dis -> getSubtargetInfo (

) . getFeatureBits ( ) ) ) return Success ;


<s> void <ISA_LIT>TargetLowering :: VarArgStyleRegisters ( CCState & CCInfo , SelectionDAG & DAG , DebugLoc dl , SDValue & Chain , unsigned ArgOffset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned firstRegToSaveIndex ; if ( CCInfo . isFirstByValRegValid ( ) ) firstRegToSaveIndex = CCInfo . getFirstByValReg ( ) - <STR_LIT> ; else { firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; } unsigned VARegSize , VARegSaveSize ; computeRegArea ( CCInfo , MF , VARegSize , VARegSaveSize ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; AFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize , false ) ) ; SDValue FIN = DAG . getFrameIndex ( AFI -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; firstRegToSaveIndex < <NUM_LIT> ; ++ firstRegToSaveIndex ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC


<s> if ( Subtarget -> isThumb2 ( ) || ( Subtarget -> hasV8MBaselineOps ( ) && Subtarget -> isThumb ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg (


<s> return ( uint16x4_t ) __builtin_neon_vget_lowv8hi ( (


<s> else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT>


<s> const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = <NUM_LIT> ; i <


<s> if ( Op . getValueType ( ) == <STR_LIT> && ( ! Subtarget -> hasHardQuad ( ) || ! isTypeLegal ( OpVT ) ) ) { return LowerF128Op ( Op , DAG , getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: UINTTOFP_I32_F128 : RTLIB :: UINTTOFP_I64_F128 ) , <NUM_LIT> ) ; } if ( DAG . SignBitIsZero ( Op . getOperand ( <NUM_LIT> ) ) ) { EVT floatVT = <STR_LIT> ; unsigned IntToFloatOpcode = <STR_LIT> ; if ( OpVT == <STR_LIT> ) { floatVT = <STR_LIT> ; IntToFloatOpcode = <STR_LIT> ; } SDValue FloatTmp = DAG . getNode ( <STR_LIT> , dl , floatVT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( IntToFloatOpcode , dl , Op . getValueType ( ) , FloatTmp ) ; } if ( OpVT == <STR_LIT> && Subtarget -> is64Bit ( ) ) { SDValue Int64Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue , Size ) ; } else { getStreamer ( ) . EmitValue ( Value , Size , ExprLoc ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex (


<s> O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup (

<STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI


<s> O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) ==


<s> if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const


<s> printShiftOperand ( <STR_LIT> , MI ,


<s> unsigned ScalarSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; SDValue Op = peekThroughBitcasts ( SDValue ( N , <NUM_LIT> ) ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; if ( VT . getScalarSizeInBits ( ) != ScalarSize ) return SDValue ( ) ; if ( auto SVOp = dyn_cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ) { if ( ! SVOp -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegOp0 = isFNEG ( DAG , SVOp -> getOperand ( <NUM_LIT> ) . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegOp0 . getValueType ( ) == VT ) return DAG . getVectorShuffle ( VT , SDLoc ( SVOp ) , NegOp0 , DAG . getUNDEF ( VT ) , SVOp -> getMask ( ) ) ; return SDValue ( ) ; } unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { SDValue InsVector = Op . getOperand ( <NUM_LIT> ) ; SDValue InsVal = Op . getOperand ( <NUM_LIT> ) ; if ( ! InsVector . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegInsVal = isFNEG ( DAG , InsVal . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegInsVal . getValueType ( ) == VT . getVectorElementType ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , InsVector , NegInsVal , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> >


<s> if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_sse = true ; cum -> warn_mmx = true ; cum -> maybe_vaarg = false ; if ( fntype && ! TARGET_64BIT ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { cum -> nregs = <NUM_LIT> ; cum -> fastcall = <NUM_LIT> ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl ) ; if ( cum -> nregs || cum -> mmx_nregs || cum -> sse_nregs ) { for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : <NUM_LIT> ; param != <NUM_LIT> ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == <NUM_LIT> && TREE_VALUE ( param ) != void_type_node ) { if ( !


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { bool LocalChange = false ; for ( MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( ( qword ) ( vec_sel ( ( vec_uchar16 ) ( a ) , ( vec_uchar16


<s> static bool isPairedLdSt ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } int64_t Pow2MinusOne = ( <NUM_LIT> << Lg2 ) - <NUM_LIT> ; unsigned AddReg = emitAdd_ri_ ( VT , Src0Reg , Pow2MinusOne ) ; if ( ! AddReg ) return false ; if ( ! emitICmp_ri ( VT , Src0Reg , <NUM_LIT> ) ) return false ; unsigned SelectOpc ; const TargetRegisterClass * RC ; if ( VT == <STR_LIT> ) { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned SelectReg = fastEmitInst_rri ( SelectOpc , RC , AddReg , Src0Reg , <STR_LIT> ) ; if ( ! SelectReg ) return false ; unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg ; if ( C . isNegative ( ) ) ResultReg = emitAddSub_rs ( false , VT , ZeroReg , SelectReg , <STR_LIT> , Lg2 ) ; else ResultReg = emitASR_ri ( VT , VT , SelectReg , Lg2 ) ; if ( ! ResultReg ) return


<s> default : return MCDisassembler :: Fail ; case <STR_LIT> : break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } Inst . addOperand ( MCOperand ::


<s> unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) && hasAtomicRMW

) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> static HOST_WIDE_INT nds32_constant_alignment ( const_tree constant , HOST_WIDE_INT basic_align ) { if ( ( ( TREE_CODE ( constant ) == STRING_CST || TREE_CODE ( constant ) == CONSTRUCTOR || TREE_CODE ( constant ) == UNION_TYPE || TREE_CODE ( constant

) == RECORD_TYPE || TREE_CODE ( constant ) == ARRAY_TYPE ) && basic_align < BITS_PER_WORD ) ) return BITS_PER_WORD ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine (


<s> auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( AddrReg ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addReg ( DesiredLoReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addReg ( DesiredHiReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( StatusReg , RegState :: Kill ) . addUse ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( NewLoReg ) . addReg ( NewHiReg ) . addReg ( AddrReg ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , <ISA_LIT>Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT> ; } if ( Kind == MCExpr :: SymbolRef ) { <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_None : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : FixupKind = <STR_LIT>


<s> op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { op0 = loongarch_zero_if_equal ( op0 , op1 ) ; op1 = const0_rtx ; } else { bool invert = false ; rtx target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; loongarch_emit_int_order_test ( code , & invert , target , op0 , op1 ) ; code = invert ? EQ : NE ; op0 = target ; op1 = const0_rtx ; } } rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( INTEGRAL_MODE_P ( GET_MODE ( operands [ <NUM_LIT> ] ) ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ <NUM_LIT> ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0


<s> return ( __m512i ) __builtin_ia32_vpshrd_v16si ( ( __v16si )


<s> } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; } TargetMBB -> setHasAddressTaken ( ) ; } if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , true ) ; -- MBBI ; } if ( NeedsWinCFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( ! RetOpcode || ! isTailCallOpcode ( * RetOpcode ) ) { int Offset = - <NUM_LIT> * <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { MBBI = MBB . getFirstTerminator (


<s> unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> )


<s> static bool ix86_hard_regno_scratch_ok ( unsigned int regno ) { return ( ! cfun -> machine -> no_caller_saved_registers || ( ! epilogue_completed && df_regs_ever_live_p ( regno )


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout ,


<s> static Register genNeg ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg , unsigned MnegOpc , const TargetRegisterClass * RC ) { Register NewVR = MRI . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MnegOpc ) , NewVR ) . add ( Root . getOperand ( <NUM_LIT> ) ) ; InsInstrs . push_back ( MIB ) ; assert ( InstrIdxForVirtReg . empty ( ) ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR ,


<s> rtx el = vector ? CONST_VECTOR_ELT ( op , i ) : op ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) ; for ( unsigned int byte = <NUM_LIT> ; byte < innersize ; byte ++ ) { bytes [ idx ++ ] = ( elpart & <NUM_LIT> ) ^ invmask ; elpart >>= BITS_PER_UNIT ; } } gcc_assert ( idx == GET_MODE_SIZE ( mode ) ) ; do { CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> &&


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) ) ; return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Val ) ; if ( ! LT . second . isVector ( ) ) return


<s> bool <ISA_LIT>LongBranch :: mustRelaxABranch ( ) { for ( SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) , TE = Terminators . end ( ) ; TI != TE ;

++ TI ) if ( mustRelaxBranch ( * TI , TI -> Address ) ) return true ;


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) && ( Subtarget . useAVX512Regs ( ) || ! VT . is512BitVector ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ; bool AShift = LShift && VT != <STR_LIT> && VT != <STR_LIT> ; return ( Opcode == <STR_LIT>


<s> uint64_t <ISA_LIT>GOT :: emit ( MemoryRegion & pRegion ) { uint64_t * buffer = reinterpret_cast < uint64_t * > ( pRegion . begin ( ) ) ; <ISA_LIT>GOTEntry * got = NULL ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it


<s> if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ; return


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( InMicro<ISA_LIT>Mode && STI . has<ISA_LIT>32r6 ( ) ) { return Changed ; } for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) { bool Filled = false ; if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always ||

! TII -> getEquivalentCompactForm ( I ) ) {


<s> assert ( ( Kind == k_Register || Kind == k_PtrReg ) && <STR_LIT> ) ; Reg . Kind = RegKind


<s> FMA3_AVX512_FULL_GROUP ( VFMSUB ) ; FMA3_AVX512_FULL_GROUP ( VFNMADD ) ; FMA3_AVX512_FULL_GROUP ( VFNMSUB ) ; FMA3_AVX512_VECTOR_GROUP ( VFMADDSUB ) ; FMA3_AVX512_VECTOR_GROUP ( VFMSUBADD


<s> static void InsertReturnAddressAuth ( MachineFunction & MF , MachineBasicBlock & MBB ) { const auto & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! MFI . shouldSignReturnAddress ( ) ) return ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering (


<s> if ( ! attr ) return false ; * name = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return true


<s> void emitZeroes ( IRBuilder < > & IRB , uint64_t Offset , uint64_t Size ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << Offset


unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> if ( ArgFlags . isSplit ( ) ) { Reg = State . AllocateReg ( FloatVectorIntRegs ) ; if ( Reg == <STR_LIT> ) State . AllocateReg ( <STR_LIT> ) ; else if ( Reg == <NUM_LIT> ) State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( IntRegs ) ; } } else if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs ) ; State . AllocateReg ( IntRegs ) ; } else { Reg = State . AllocateReg ( F64Regs ) ; unsigned Reg2 = State . AllocateReg ( IntRegs ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT>


<s> bool CheckReturn ( const SmallVectorImpl < <STR_LIT> > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasF128 . clear (


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; Relocator :: DWord X = S + A


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ; return SDValue


<s> LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT>


<s> if ( TARGET_HAVE_MVE ) mask = gen_reg_rtx ( arm_mode_to_pred_mode ( cmp_result_mode ) . require ( ) ) ; else mask = gen_reg_rtx ( cmp_result_mode ) ; bool inverted = arm_expand_vector_compare ( mask , GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , true ) ; if ( inverted ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( TARGET_NEON ) emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , mask , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else { machine_mode cmp_mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; switch ( GET_MODE_CLASS ( cmp_mode ) ) { case MODE_VECTOR_INT : emit_insn ( gen_mve_vpselq ( VPSELQ_S , cmp_mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , mask ) ) ; break ; case MODE_VECTOR_FLOAT : if ( TARGET_HAVE_MVE_FLOAT ) emit_insn ( gen_mve_vpselq_f ( cmp_mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , mask ) ) ; else gcc_unreachable (


<s> abi = MS_ABI ; } else if ( abi == MS_ABI && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) abi = SYSV_ABI ; return abi


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case TargetOpcode :: COPY : return MI . getOperand ( <NUM_LIT> ) . getReg


<s> return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : return opt_machine_mode (


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } } Relocator :: DWord X = S + A ; X >>= <NUM_LIT>


<s> <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S


<s> return ( __mmask16 ) __builtin_ia32_kxnorhi ( ( __mmask16 ) __A , ( __mmask16 )


<s> unsigned postKnownBits ( Align Align = Align :: None ( ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; MachineBasicBlock :: iterator StoreI ; if ( findMatchingStore ( MBBI , LdStLimit , StoreI ) ) { ++ NumLoadsFromStoresPromoted


<s> Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true


<s> } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; SrcReg1 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg1 , <NUM_LIT> ) ; SrcReg2 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; UpdateValueMap ( I ,


<s> return hash_rtx ( p1 , VOIDmode , NULL ,


<s> SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } SDValue WideLd = DAG . getMaskedLoad ( WideVecVT , dl , Mld -> getChain ( ) , Mld -> getBasePtr ( ) , NewMask , WideSrc0 , Mld -> getMemoryVT ( ) , Mld -> getMemOperand ( ) , <STR_LIT> ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , VT , WideLd ) ; return DCI . CombineTo ( N , NewVec , WideLd . getValue ( <NUM_LIT> )


<s> void setCSRegisterIsSpilled ( unsigned Reg ) { SpilledCSRegs . set


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { assert ( Encoding == DW_EH_PE_absptr && <STR_LIT>


<s> static __inline unsigned int si_to_uint ( qword q ) { union { qword q ; unsigned int i [ <NUM_LIT> ] ; }


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int ncrn , nvrn , nregs ; bool allocate_ncrn , allocate_nvrn ; HOST_WIDE_INT size ; if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; size = ROUND_UP ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; allocate_ncrn = ( type ) ? ! ( FLOAT_TYPE_P ( type ) ) : ! FLOAT_MODE_P ( mode ) ; allocate_nvrn = aarch64_vfp_is_call_candidate ( pcum_v , mode , type , & nregs ) ; nvrn = pcum -> aapcs_nvrn ; if ( allocate_nvrn ) { if ( ! TARGET_FLOAT ) aarch64_err_no_fpadvsimd ( mode , <STR_LIT> ) ; if ( nvrn + nregs <= NUM_FP_ARG_REGS ) { pcum -> aapcs_nextnvrn = nvrn + nregs ; if ( ! aarch64_composite_type_p ( type , mode ) ) { gcc_assert ( nregs == <NUM_LIT> ) ; pcum -> aapcs_reg = gen_rtx_REG ( mode , V0_REGNUM + nvrn ) ; } else { rtx par ; int i


<s> cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = <NUM_LIT> ; return cost


<s> for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> isDeclaration ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; if ( usingMask ) { if ( functionIndex == <ISA_LIT>32FunctionMask . length ( ) ) functionIndex = <NUM_LIT> ; if ( <ISA_LIT>32FunctionMask [ functionIndex ] == '1'


<s> return ( __m128i ) __builtin_ia32_pbroadcastd128 ( (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> bool <ISA_LIT>InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT>


<s> if ( GV -> getValueID ( ) == Value :: FunctionVal ) TargetFlags = <STR_LIT> ; SDValue TargetGlobalAddr = CurDAG -> getTargetGlobalAddress ( GV , SDLoc ( N ) , <STR_LIT> , GA -> getOffset ( ) , TargetFlags ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , TargetGlobalAddr , CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ) ; CurDAG -> ReplaceAllUsesWith ( N -> getOperand ( <NUM_LIT> ) , SDValue ( Move , <NUM_LIT> ) ) ; } break ; case <STR_LIT> : { unsigned int operand2Opc = N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( operand2Opc == <STR_LIT> || operand2Opc ==


<s> if ( ! Chain . hasOneUse ( ) ) return false ; Chain = Chain . getOperand ( <NUM_LIT> ) ; } if ( Chain . getOperand ( <NUM_LIT> ) . getNode ( ) == Callee . getNode ( ) ) return true ; if ( Chain . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Callee . getValue ( <NUM_LIT> ) . isOperandOf ( Chain . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Callee . getValue ( <NUM_LIT> ) . hasOneUse ( ) ) return true ; return false


<s> for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) addFixup


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T ,

computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> <STR_LIT> getProcIFlags ( ) const { assert ( Kind == k_ProcIFlags && <STR_LIT> ) ; return IFlags .


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>SEInstrInfo ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>SEInstrInfo (


<s> if ( In64BitMode ) return false ; return isTargetELF ( ) || TM .

getRelocationModel ( ) == Reloc :: Static ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveNops ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSaveReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSaveXMM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHPushFrame ( DirectiveID . getLoc ( ) ) ; return true


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI


<s> if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( Opc , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( Lexer . getKind ( ) != AsmToken :: LParen ) { Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Lexer . Lex ( ) ; if ( Parser . parseIdentifier ( Identifier ) ) return nullptr ; } if ( Lexer . getKind ( ) == AsmToken :: Plus && Parser . parseExpression ( RHS ) ) return nullptr ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( Lexer . getKind ( ) != AsmToken :: RParen ) { Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Lexer . Lex ( ) ; } End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Kind ,


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm


<s> const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ; if ( Preds ) DAG -> addEdge ( ASU , SDep ( BSU , SDep :: Cluster ) ) ; else DAG -> addEdge ( BSU , SDep ( ASU , SDep :: Cluster ) ) ; for ( SDep & Dep : APreds ) if ( Dep . getSUnit ( ) == BSU ) Dep . setLatency ( <NUM_LIT> ) ; auto & BSuccs = Preds ? BSU -> Succs : BSU -> Preds ; for ( SDep & Dep : BSuccs ) if ( Dep . getSUnit ( ) == ASU ) Dep . setLatency ( <NUM_LIT> ) ; ++ NumFused ; DEBUG ( { SUnit * LSU = Preds ? BSU : ASU ; SUnit * RSU = Preds ? ASU : BSU ; const MachineInstr * LMI = Preds ? BMI : AMI ; const MachineInstr * RMI = Preds ? AMI : BMI ; dbgs ( ) << DAG -> MF . getName ( ) << <STR_LIT> ; LSU -> print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> ; RSU -> print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> << TII -> getName ( LMI -> getOpcode ( ) ) << <STR_LIT> << TII -> getName ( RMI -> getOpcode ( ) ) << '\n' ; }


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU ,


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { assert ( InProlog && <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreatePrefix ( unsigned Prefixes , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Prefix , StartLoc , EndLoc ) ; Res -> Pref .


<s> switch ( ireg -> nat . type ) { case UNW_NAT_VAL : if ( write ) { if ( * nat ) { addr [ <NUM_LIT> ] = <NUM_LIT> ; addr [ <NUM_LIT> ] = <NUM_LIT> ; return ; } addr [ <NUM_LIT> ] = <NUM_LIT> ; } else if ( addr [ <NUM_LIT> ] == <NUM_LIT> && addr [ <NUM_LIT> ] == <NUM_LIT> ) { * val = <NUM_LIT> ; * nat = <NUM_LIT> ; return ; } case UNW_NAT_NONE : dummy_nat = <NUM_LIT> ; nat_addr = & dummy_nat ; break ; case UNW_NAT_MEMSTK : nat_mask = <NUM_LIT> << ( ( long ) addr & <NUM_LIT> ) / <NUM_LIT> ; break ; case UNW_NAT_REGSTK : if ( ( unsigned long ) addr >= info -> regstk_top ) nat_addr = & info -> rnat ; else nat_addr = ia64_rse_rnat_addr ( addr


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void *


<s> int NumInterestingAllocas = <NUM_LIT> ; for ( auto & I : Allocas ) { AllocaInfo & Info = I . second ; assert ( Info . AI ) ; if ( ! isInterestingAlloca ( * Info . AI ) ) { Info . Tag = - <NUM_LIT> ; continue ; } alignAndPadAlloca ( Info ) ; NumInterestingAllocas ++ ; Info . Tag = NextTag ; NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base ; if ( NumInterestingAllocas > <NUM_LIT> ) { auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; if ( DTWP ) { Base = insertBaseTaggedPointer ( Allocas , & DTWP -> getDomTree ( ) ) ; } else { DominatorTree DT ( * F ) ; Base = insertBaseTaggedPointer ( Allocas , & DT ) ; } } else { Base = insertBaseTaggedPointer ( Allocas , nullptr ) ; } for ( auto & I : Allocas ) { const AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( Info . Tag < <NUM_LIT> ) continue ; IRBuilder < > IRB ( Info . AI -> getNextNode ( ) ) ; Function * TagP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> , { Info . AI -> getType ( ) } ) ; Instruction * TagPCall = IRB . CreateCall ( TagP , { Constant :: getNullValue ( Info . AI -> getType ( ) ) , Base , ConstantInt :: get ( IRB . getInt64Ty ( ) , Info . Tag ) } ) ; if ( Info . AI -> hasName ( ) ) TagPCall -> setName ( Info . AI -> getName ( ) + <STR_LIT> ) ; Info . AI -> replaceAllUsesWith ( TagPCall ) ; TagPCall -> setOperand ( <NUM_LIT> , Info . AI ) ; if ( UnrecognizedLifetimes . empty ( ) && Info . LifetimeStart . size ( ) == <NUM_LIT> && Info . LifetimeEnd . size ( ) == <NUM_LIT> ) { IntrinsicInst * Start = Info . LifetimeStart [ <NUM_LIT> ] ; uint64_t Size = dyn_cast < ConstantInt > ( Start -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Size = alignTo ( Size , kTagGranuleSize ) ; tagAlloca ( AI , Start -> getNextNode ( ) , Start -> getArgOperand ( <NUM_LIT> ) , Size ) ; untagAlloca ( AI , Info . LifetimeEnd [ <NUM_LIT> ] , Size ) ; } else { uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; Value * Ptr = IRB . CreatePointerCast ( TagPCall , IRB . getInt8PtrTy ( ) ) ; tagAlloca ( AI , & * IRB . GetInsertPoint ( ) , Ptr , Size ) ; for ( auto & RI : RetVec ) { untagAlloca ( AI , RI


<s> case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_CALL : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDO_HIX22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDO_LOX10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDO_ADD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_IE_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_IE_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_IE_LD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_IE_LDX : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_IE_ADD : OS << <STR_LIT> ; return


<s> rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vsldoi_v4sf || icode == CODE_FOR_altivec_vsldoi_v2df || icode == CODE_FOR_altivec_vsldoi_v4si || icode == CODE_FOR_altivec_vsldoi_v8hi || icode == CODE_FOR_altivec_vsldoi_v16qi ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsx_xxpermdi_v2df || icode == CODE_FOR_vsx_xxpermdi_v2di || icode == CODE_FOR_vsx_xxpermdi_v2df_be || icode == CODE_FOR_vsx_xxpermdi_v2di_be || icode == CODE_FOR_vsx_xxpermdi_v1ti || icode == CODE_FOR_vsx_xxpermdi_v4sf || icode == CODE_FOR_vsx_xxpermdi_v4si || icode == CODE_FOR_vsx_xxpermdi_v8hi || icode == CODE_FOR_vsx_xxpermdi_v16qi || icode == CODE_FOR_vsx_xxsldwi_v16qi || icode == CODE_FOR_vsx_xxsldwi_v8hi || icode == CODE_FOR_vsx_xxsldwi_v4si || icode == CODE_FOR_vsx_xxsldwi_v4sf || icode == CODE_FOR_vsx_xxsldwi_v2di || icode == CODE_FOR_vsx_xxsldwi_v2df ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsx_set_v2df || icode == CODE_FOR_vsx_set_v2di || icode == CODE_FOR_bcdadd || icode == CODE_FOR_bcdadd_lt || icode == CODE_FOR_bcdadd_eq || icode == CODE_FOR_bcdadd_gt || icode == CODE_FOR_bcdsub || icode == CODE_FOR_bcdsub_lt || icode == CODE_FOR_bcdsub_eq || icode == CODE_FOR_bcdsub_gt ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfp_ddedpd_dd || icode == CODE_FOR_dfp_ddedpd_td ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> )


<s> bool selectBDAddr12Only ( SDValue Addr , SDValue & Base , SDValue & Disp ) { return selectBDAddr ( <STR_LIT> , Addr , Base


<s> std :: map < unsigned , unsigned > Substs ; for ( MachineInstr & I : * G ) { if ( ! G -> contains ( I ) && ( & I != G -> getKill ( ) || G -> isKillImmutable ( ) ) ) continue ; std :: vector < unsigned > ToErase ; for ( auto & U : I . operands ( ) ) { if ( U . isReg ( ) && U . isUse ( ) && Substs . find ( U . getReg ( ) ) != Substs . end ( ) ) { unsigned OrigReg = U . getReg ( ) ; U . setReg ( Substs [ OrigReg ] ) ; if ( U . isKill ( ) ) ToErase . push_back ( OrigReg ) ; } else if ( U . isRegMask ( ) ) { for ( auto J : Substs ) { if ( U . clobbersPhysReg ( J . first ) ) ToErase . push_back ( J . first ) ; } } } for ( auto J : ToErase ) Substs . erase ( J ) ; if ( & I != G -> getKill ( ) ) { MachineOperand & MO = I . getOperand


<s> const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( ! ( I -> isBranch ( ) ) && ! ( I -> mayStore ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { MachineInstr * slaveinst1 = MF . CloneMachineInstr ( & * I ) ; MachineInstr * slaveinst2 = MF . CloneMachineInstr ( & * I ) ; slaveinst1 -> setFlags ( <NUM_LIT> ) ; slaveinst2 -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { if ( I -> getOperand ( opcount ) . isReg ( ) ) { slaveinst1 -> getOperand ( opcount ) . setReg ( getSlaveReg1 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; slaveinst2 -> getOperand ( opcount ) . setReg ( getSlaveReg2 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; } } MBB -> insert ( I ,


<s> bool <ISA_LIT>TargetLowering :: mergeStoresAfterLegalization (


<s> return ( __m256d ) __builtin_ia32_cvtuqq2pd256_mask ( ( __v4di ) __A , ( __v4df )

_mm256_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; int64_t IntVal ; if ( ! MatchRegisterName ( Tok , RegNo , IntVal ) ) { Parser . Lex ( ) ; return


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> )


<s> ID . AddPointer ( S ) ; ID . AddInteger ( LabelId


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget . isPICStyleRIPRel ( ) || Subtarget . is64Bit ( ) ) return

TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT>


<s> unsigned VSize = <NUM_LIT> ; if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) { auto * PtrTy = cast < PointerType > ( Ld -> getPointerOperandType ( ) ) ; VSize = PtrTy -> getElementType ( ) -> getPrimitiveSizeInBits ( ) ; } else if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) { VSize = ZExt -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; }


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> ,


<s> ASSERT_STREQ ( <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_7 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_7 ) ) ; ASSERT_EQ ( PARALLEL , GET_CODE ( PATTERN ( insn_7 ) ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( <NUM_LIT> , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl -> return_rtx )


<s> if ( LT . second . getSizeInBits ( ) <= <NUM_LIT> ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - <NUM_LIT> ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == <STR_LIT> ) for ( unsigned i = <NUM_LIT> , e = VecTy -> getNumElements ( ) ; i < e ; i += <NUM_LIT> ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation


<s> if ( STI . hasMOPS ( ) ) return EmitMOPS ( <STR_LIT> , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; return SDValue (


<s> bool HasRelocationAddend = TT . isArch64Bit ( ) ; auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , HasRelocationAddend , IsN64 , TT . isLittleEndian (


<s> Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; bool isQReg = false ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { Reg = getDRegFromQReg ( Reg ) ; isQReg = true ; } if ( ! RC -> contains ( Reg ) ) return Error ( RegLoc , <STR_LIT> ) ; if ( MRI -> getEncodingValue ( Reg ) < MRI -> getEncodingValue ( OldReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) Warning ( RegLoc , <STR_LIT> ) ; else return Error ( RegLoc , <STR_LIT> ) ; } if ( MRI -> getEncodingValue ( Reg ) == MRI -> getEncodingValue ( OldReg ) ) { Warning ( RegLoc , <STR_LIT> + RegTok . getString ( ) + <STR_LIT> ) ; continue ; } if ( RC != & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] && Reg != OldReg + <NUM_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; EReg = MRI -> getEncodingValue ( Reg ) ; Registers . push_back ( std :: pair < unsigned , unsigned > ( EReg , Reg ) ) ; if ( isQReg ) { EReg = MRI -> getEncodingValue ( ++ Reg ) ; Registers . push_back ( std :: pair < unsigned , unsigned > ( EReg , Reg ) ) ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateRegList ( Registers


<s> EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> , j = NumElems / <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i , ++ j ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , j ) || SVOp -> getMaskElt ( j ) >= <NUM_LIT> ) return false ; return


<s> if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n8_consumed_by_ex_p ( consumer ,


<s> __asm__ ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( __A ) , <STR_LIT> ( res ) , <STR_LIT> ( dtmp ) : ) ; res = __builtin_rint ( __A [ <NUM_LIT> ] ) ; return ( res


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : return earlySelectSHL ( I , MRI ) ; case TargetOpcode :: G_CONSTANT : { bool IsZero = false ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) == <NUM_LIT> ; else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; if ( ! IsZero ) return false ; Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; return true ; } default : return


<s> unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II ,


<s> bool <ISA_LIT>RetpolineThunks :: doInitialization ( Module & M ) { InsertedThunks = false


<s> switch ( mode ) { case E_QImode : gen = gen_aarch64_atomic_swpqi ; break ; case E_HImode : gen = gen_aarch64_atomic_swphi ; break ; case E_SImode : gen = gen_aarch64_atomic_swpsi ; break ; case E_DImode : gen = gen_aarch64_atomic_swpdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , value ,


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( (


<s> if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; bool UseImm = false ; if ( const auto * CFP = dyn_cast < ConstantFP > ( RHS ) ) if ( CFP -> isZero ( ) && ! CFP -> isNegative ( ) ) UseImm = true ; Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return false ; if ( UseImm ) { unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg ) ; return true ; } Register RHSReg = getRegForValue (


<s> return ( unsigned long long ) __builtin_sh_media_MCNVS_WB ( ( v4hi ) mm , (


<s> return ( __m128 ) __builtin_ia32_cmpeqps ( ( __v4sf ) __A ,


<s> if ( flags & SectionFlags :: Writeable ) Flags += <STR_LIT> ; if ( flags & SectionFlags :: TLS ) Flags += <STR_LIT> ; return Flags


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc &


<s> bool sparc_can_use_return_insn_p ( void ) { return sparc_prologue_data_valid_p && sparc_n_global_fp_regs == <NUM_LIT> && TARGET_FLAT ? ( sparc_frame_size == <NUM_LIT> && ! sparc_save_local_in_regs_p ) : (


<s> if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue >

( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo


<s> if ( isDarwinABI || is<ISA_LIT>64 ) return ( isELFv2ABI ? <NUM_LIT> : <NUM_LIT> ) * ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT>


<s> return __builtin_shuffle ( a , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> }


<s> SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } if ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && RelaxedOp == <STR_LIT> ) { Res . setOpcode ( RelaxedOp ) ; Res . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; return ; } Res =


<s> SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; return


<s> V = <STR_LIT> ( V ) ; assert ( V != - <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <STR_LIT> ( V ) ; unsigned Rot = <STR_LIT> ( V ) ; if ( Rot ) { O << <STR_LIT> << Imm << <STR_LIT> << Rot ; if ( CommentStream ) * CommentStream << ( int ) <STR_LIT> ( Imm , Rot ) << <STR_LIT> ; } else { O << <STR_LIT>


<s> StackOffset <ISA_LIT>SEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI


<s> unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) .

addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ;


<s> static void mmix_output_shiftvalue_op_from_str ( FILE * stream , const char * mainop , int64_t value ) { static const char * const op_part [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; int i ; if ( ! mmix_shiftable_wyde_value ( value ) ) { char s [ sizeof ( <STR_LIT> ) ] ; sprintf ( s , <STR_LIT> PRIx64 , value ) ; internal_error ( <STR_LIT> , s ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT>


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , VT . getVectorNumElements ( ) ) ; } SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue PassThru = DAG . getBitcast ( CastVT , ML -> getPassThru ( ) ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , CastVT , PassThru , Load , VecIndex ) ; Insert = DAG . getBitcast


<s> if ( Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N


<s> } else return false ; if ( ! strict_p && SUBREG_P ( index ) && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( index ) ) ] ) index = SUBREG_REG ( index ) ; if ( loongarch_valid_base_register_p ( index , mode , strict_p ) ) { info -> type = ADDRESS_REG_REG ; info -> offset = index ; return true ; } return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerFNEG ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>WinCOFFObjectWriter ( ) { return std :: make_unique < <ISA_LIT>WinCOFFObjectWriter


<s> return ( __mmask16 ) __builtin_ia32_kshiftrihi ( ( __mmask16 ) __A ,


<s> else for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - <NUM_LIT> ) , gen_rtx_REG ( mode , rsrc +


<s> } ; if ( ! match ( Ext1 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! match ( Ext2 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! areExtDoubled ( cast < Instruction > (

Ext1 ) ) || ! areExtDoubled ( cast < Instruction > ( Ext2 ) ) ) return false ;


<s> break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( is_mm_relaxed ( model ) || is_mm_release ( model ) || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg =


<s> MaskInst . addOperand ( MCOperand :: CreateReg ( AddrReg ) ) ; MaskInst . addOperand ( MCOperand :: CreateReg


<s> for ( auto & MO : MI -> operands ( ) ) { const MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) { OutMI . addOperand ( MCOp )


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target


<s> IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( RDRAND , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( RDRAND , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( RDRAND , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( RDSEED , <STR_LIT> , <NUM_LIT> )


<s> SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0


<s> bool isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm7 , Fixups , STI ) ; uint32_t Binary = ( Imm7 >> <NUM_LIT>


<s> static tree aarch64_get_attributes ( aarch64_simd_builtin_datum * d ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( d ) ) { if ( aarch64_reads_global_state_p ( d ) ) attrs = aarch64_add_attribute (


<s> static DecodeStatus DecodeUImm6Lsl2 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Value << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute (


<s> error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return const0_rtx ; emit_insn (


<s> SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset = getScaledOffsetForBitWidth ( DAG , Offset , DL , RetVT . getScalarSizeInBits ( ) ) ; Opcode = <STR_LIT> ; } if ( Opcode == <STR_LIT> && Offset . getValueType ( ) . isVector ( ) ) std :: swap ( Base , Offset ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( ! isValidImmForSVEVecImmAddrMode ( Offset , RetVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( RetVT . isInteger ( ) && ( RetVT != HwRetVt ) ) Load = DAG . getNode ( <STR_LIT> , DL , RetVT , Load . getValue ( <NUM_LIT> ) ) ; if ( RetVT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> , DL , RetVT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load