<s> inline vector signed int vec_sums ( vector signed int a1 , vector signed int a2 ) { return ( vector signed int ) __builtin_altivec_vsumsws ( ( vector signed int )


<s> __inline__ static void sh_media_STHI_L ( void * p , int s , unsigned int mw ) { __asm__ ( <STR_LIT> : <STR_LIT> ( ( ( char * ) p ) [


<s> MachineFunction * MF = BB -> getParent ( ) ; const Constant * PerFn = MF -> getFunction ( ) -> getPersonalityFn ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( PerFn ) ) ; if ( IsSEH && Subtarget -> is32Bit ( ) ) { const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII . get


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * Last = & MBB -> back ( ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; if ( Last -> getOpcode ( ) == <STR_LIT> ) Ignore . insert ( Last ) ; bool SetFlags = RDA -> isSafeToDefRegAt ( MI , <STR_LIT> , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ; if ( SetFlags


<s> MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) .


<s> OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext ) , PointerSize ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , PointerSize ) ; OutStreamer -> SwitchSection ( Current . first


<s> SDValue Op0Op1 = Op0 -> getOperand ( <NUM_LIT> ) ; if ( Op1 == Op0Op0 && Op2 == Op0Op1 ) return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , Ty , Op1 , Op2 ) ; else if ( Op1 == Op0Op1 && Op2 == Op0Op0 ) return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , Ty , Op1 , Op2 ) ; } else if ( ( Ty == <STR_LIT> ) || ( Ty == <STR_LIT> ) ) { SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Ty , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> )


<s> return ( __m64 ) __builtin_ia32_pcmpgtb ( ( __v8qi ) __m1 ,


<s> const MCOperand MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { O << <STR_LIT> << formatImm ( MO . getImm (


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , TLInfo ( TM , * this )

, FrameLowering ( * this , <NUM_LIT> ) {


<s> unsigned MaskValue = <NUM_LIT> ; if ( ! BUILD_VECTORtoBlendMask ( cast < BuildVectorSDNode > ( Cond ) , MaskValue ) ) return SDValue ( ) ; MVT BlendVT = VT ; if ( EltVT == <STR_LIT> || ( EltVT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) { BlendVT = <STR_LIT> ( <STR_LIT> ( EltVT . getSizeInBits ( ) ) , NumElems ) ; LHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , VT , RHS ) ; } SDValue Ret = DAG . getNode ( <STR_LIT> , dl , BlendVT , LHS , RHS , DAG . getConstant ( MaskValue , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ret


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) <


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedStore ( Type * DataType , int Consecutive ) { return isLegalMaskedLoad ( DataType


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; return StackSizeInBytes >= StackProbeSize


<s> return __builtin_ia32_vcomiss ( ( __v4sf ) __A , ( __v4sf )


<s> return SDValue ( ) ; } if ( ShiftAmt >= - <NUM_LIT> && ShiftAmt < <NUM_LIT> ) { unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NewShift = DAG . getNode ( NewOpcode , DL , N -> getVTList ( ) , Op0 , Op1 , DAG . getConstant ( - ShiftAmt , DL , <STR_LIT> ) ) ; DAG . ReplaceAllUsesWith ( N , NewShift . getNode


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer

. EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <=


<s> unsigned Byte = ( ( Elem * FromBytesPerElement ) % <STR_LIT> + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else if ( Op . getOpcode ( ) == <STR_LIT> && Op . hasOneUse ( ) ) { SmallVector < int , <STR_LIT> > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < <NUM_LIT> ) { addUndef ( ) ; return ; } Op = Op . getOperand ( unsigned ( NewByte ) / <STR_LIT> ) ; Byte = unsigned ( NewByte ) %


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> && Value <= <NUM_LIT> &&


<s> if ( ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) != VecVT . getSizeInBits ( ) || ( IdxVal != <NUM_LIT> && IdxVal != NumSubElts ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Lo , Hi ; if ( IdxVal == <NUM_LIT> ) { Lo = SubVec ; Hi = DAG . getNode ( <STR_LIT> , DL , SubVT , Vec , DAG . getVectorIdxConstant ( NumSubElts , DL ) ) ; } else { Lo = DAG . getNode ( <STR_LIT> , DL , SubVT , Vec , DAG . getVectorIdxConstant ( <NUM_LIT> , DL


<s> bool hasVectorMemoryOp ( unsigned Opcode , Type * Ty , const MemAccessInfo & Info ) { if ( ST -> hasSVE ( ) ) return true ; return BaseT :: hasVectorMemoryOp ( Opcode , Ty


<s> bool Filler :: isDelayFiller ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator candidate ) { if ( candidate == MBB . begin ( ) ) return false ; if ( candidate -> getOpcode ( ) == <STR_LIT> ) return true ; -- candidate


<s> if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ; ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ; if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ; if ( isSigned ) { if ( Hi0 -> getSExtValue ( ) == Lo0 -> getSExtValue ( ) >> <NUM_LIT> && Hi1 -> getSExtValue ( ) == Lo1 -> getSExtValue ( ) >> <NUM_LIT> ) return true ; } else { if ( Hi0 -> isZero ( ) && Hi1 -> isZero ( ) ) return true ; } return false ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned HalfSize = EltSize /


<s> EVT CCVT = N0 . getValueType ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || CCVT . getVectorNumElements ( ) != <NUM_LIT> || CCVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return SDValue ( ) ; SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SDValue SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ResVT , SetCC , IfTrue


<s> else if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , shift_op , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic , lane_count , element_char , UINTVAL ( info . value ) ) ; } else { mnemonic = info . insn == simd_immediate_info :: MVN ? <STR_LIT> : <STR_LIT> ; if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , <STR_LIT> , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , mnemonic , lane_count , element_char , UINTVAL ( info . value ) ) ; } return templ


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget <

<ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI == <ISA_LIT>Subtarget :: N64 ? <NUM_LIT> :


<s> bool SVEVecStackRegion :: allocatesType ( const Type * Type ) const { if ( auto ST = dyn_cast < StructType > ( Type ) ) if ( std :: equal ( ST -> element_begin ( ) , ST -> element_end ( ) , ST -> element_begin ( ) ) ) return ( ST -> getNumElements ( ) != <NUM_LIT> ) ? allocatesType ( * ST -> element_begin ( ) ) : false ; if ( isa < ArrayType > ( Type ) ) return allocatesType ( cast < ArrayType > ( Type ) -> getElementType ( ) ) ; const VectorType * VT = dyn_cast < const VectorType > ( Type ) ; if ( IsPredicateRegion ) return VT && VT -> isScalable ( ) && ( VT -> getBitWidth ( ) % <NUM_LIT> > <NUM_LIT> ) ; else return VT && VT -> isScalable ( ) && ( VT -> getBitWidth ( ) %


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) .


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && !

Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ;


<s> d . perm [ <NUM_LIT> ] = which + <NUM_LIT> ; emit_insn ( gen_fpack ( d . op1 , operands [ <NUM_LIT> ] , CONST0_RTX ( SFmode ) ) ) ; ok = ia64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == <STR_LIT> && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool isVZIP_v_undef_Mask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; if ( VT . is64BitVector ( ) &&


<s> static int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) || ( type && TREE_CODE ( type ) == RECORD_TYPE

&& int_size_in_bytes ( type ) == <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ;


<NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Load = DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; InVals . push_back ( Load ) ; OutChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg


<s> if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register ,

NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ;


<s> } else { if ( NewC . Op0 . getValueType ( ) != <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . ICmpType == <STR_LIT> ) return ; if ( NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> ) { if ( CmpVal == uint64_t ( - <NUM_LIT> ) ) return ; CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize ,

NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) {


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; if ( RPI . IsGPR ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx )


<s> return RegIdx . RegInfo -> getRegClass ( ClassID ) .


<s> TrueOp = <NUM_LIT> ; FalseOp = <NUM_LIT> ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Optimizable = true ; return false


<s> for ( const MachineInstr & MI : MBB ) Size


<s> static inline __ev64_opaque__ __ev_set_sfix32_fs_internal ( __ev64_opaque__ a , float b , uint32_t pos ) { __ev64_opaque__ v ; float other ; other = __ev_get_fs_internal ( a ,


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : deinterleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; break ; } for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , FixedVectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( Factor == <NUM_LIT> ) interleave8bitStride4 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; if ( Factor == <NUM_LIT> ) interleave8bitStride3 ( DecomposedVectors , TransposedVectors ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerSin ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , Op ,


<s> if ( ! ( ( __eax ^ __ebx ) & <NUM_LIT> ) ) return <NUM_LIT> ; __cpuid ( __ext , __eax , __ebx , __ecx , __edx ) ; if ( __sig ) * __sig =


<s> SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * Hi64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegEven ) ; SDNode * Lo64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegOdd ) ; unsigned alignment = StNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue OutChains [ <NUM_LIT> ] ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Hi64 , <NUM_LIT> ) , StNode -> getBasePtr ( ) , MachinePointerInfo ( ) , false , false , alignment ) ; EVT addrVT = StNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , StNode -> getBasePtr (

) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ;


<s> if ( load_p && ( REGNO ( reg1 ) == REGNO ( base1 ) || ( REGNO ( reg2 ) == REGNO ( base1 ) ) ) ) return false ; if ( load_p && REGNO ( reg1 ) == REGNO ( reg2 ) ) return false ; rc1 = REGNO_REG_CLASS ( REGNO ( reg1 ) ) ; rc2 = REGNO_REG_CLASS ( REGNO ( reg2 ) ) ; if ( rc1 != rc2 && ! reg_class_subset_p ( rc1 , rc2 ) && ! reg_class_subset_p ( rc2 , rc1 ) ) return false ; if ( abs ( offset1 - offset2 ) != GET_MODE_SIZE ( mode ) ) return false ; return true


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> if ( isThumb1 ) return false ; const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; unsigned Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( )


<s> if ( DstVT == <STR_LIT> && ! IsSigned && ! Subtarget -> hasFPCVT ( ) && ! Subtarget -> hasSPE ( ) ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) SrcReg = copyRegToRegClass ( & <STR_LIT> , SrcReg ) ; else if ( InRC == & <STR_LIT> ) SrcReg = copyRegToRegClass ( & <STR_LIT> , SrcReg ) ; unsigned DestReg ; unsigned Opc ; auto RC = MRI . getRegClass ( SrcReg ) ; if ( Subtarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( IsSigned ) Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( isVSFRCRegClass ( RC ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = Subtarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; unsigned IntReg = Subtarget -> hasSPE ( ) ? DestReg : <ISA_LIT>MoveToIntReg ( I , DstVT , DestReg , IsSigned ) ; if ( IntReg == <NUM_LIT> )


<s> Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType


<s> GPRSize = P . isGP64bit ( ) ? AFL_REG_64 :


<s> PICStyles :: Style getPICStyle ( ) const { return PICStyle


<s> const HOST_WIDE_INT offset = INTVAL ( op ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , consider_sh2a ) ; const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < <NUM_LIT> ) return false ; return offset >= <NUM_LIT> && offset <= max_disp && ( offset & align_mask )


<s> bool has<ISA_LIT>64r2 ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> inline bool sh_is_movrt_insn ( const rtx_insn * i ) { return sh_movrt_set_dest ( i


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x16_t ) __builtin_aarch64_qtbl3v16qi ( __o , ( int8x16_t


<s> return RetCC_<ISA_LIT>_APCS_Custom_f64 ( ValNo , ValVT , LocVT , LocInfo


<s> Inst . addOperand ( MCOperand :: createImm ( getBarrier (


<s> KindTy Kind = k_RegisterList ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) Kind = k_DPRRegisterList ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) Kind = k_SPRRegisterList ; array_pod_sort ( Regs . begin ( ) , Regs . end ( ) ) ; auto Op = make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , unsigned > > :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> second ) ; Op -> StartLoc =


<s> pextrh_s ( int16x4_t s , int field ) { return __builtin_loongson_pextrh_s ( s , field


<s> const TargetRegisterClass * getMinClassForRegBank ( const RegisterBank & RB , unsigned SizeInBits , bool GetAllRegSet = false ) { unsigned RegBankID = RB . getID ( ) ; if ( RegBankID == <STR_LIT> ) { if ( SizeInBits <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( SizeInBits == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; } if ( RegBankID == <STR_LIT> ) { switch ( SizeInBits ) { default : return nullptr ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT>


<s> unsigned <ISA_LIT>FrameLowering :: getPSPSlotOffsetFromSP ( const MachineFunction & MF ) const { const WinEHFuncInfo & Info = * MF . getWinEHFuncInfo ( ) ; Register SPReg ; int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx ,


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmplt_ss ( __m128 __A , __m128 __B ) { static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmplt ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf )


<s> else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE (


<s> if ( _U_Qfcmp ( a , b , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return ( _U_Qfcmp ( a , b , <NUM_LIT> ) !=


<s> rtx off = GEN_INT ( i ++ * <NUM_LIT> ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != <NUM_LIT> ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec )


<s> unsigned RegClassID = G -> getStart ( ) -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; BitVector AvailableRegs = RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( MachineBasicBlock :: iterator I = G -> begin ( ) , E = G -> end ( ) ; I != E ; ++ I ) { RS . forward ( I ) ; AvailableRegs &= RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto J : I ->


<s> struct ImmCompare { MachineInstr * MI = nullptr ; unsigned NewOpc = <NUM_LIT> ; } ; auto FindCmpForCBZ = [ this ] ( ImmBranch & Br , ImmCompare & ImmCmp , MachineBasicBlock * DestBB ) { ImmCmp . MI = nullptr ; ImmCmp . NewOpc = <NUM_LIT> ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) return false ; Register PredReg ; unsigned NewOpc = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; unsigned BrOffset = BBUtils -> getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset >= DestOffset || ( DestOffset - BrOffset ) > <NUM_LIT> ) return false ; auto * TRI = STI -> getRegisterInfo ( ) ; MachineInstr * CmpMI = findCMPToFoldIntoCBZ ( Br . MI , TRI ) ; if ( ! CmpMI || CmpMI -> getOpcode ( ) != <STR_LIT> ) return false ; ImmCmp . MI = CmpMI ; ImmCmp . NewOpc = NewOpc ; return true ; } ; auto TryConvertToLE = [ this ] ( ImmBranch & Br , ImmCompare & Cmp ) { if ( Br . MI -> getOpcode ( ) != <STR_LIT> || ! STI -> hasLOB ( ) || STI -> hasMinSize ( ) ) return false ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBUtils -> getOffsetOf ( MBB ) < BBUtils -> getOffsetOf ( DestBB ) || ! BBUtils -> isBBInRange ( Br . MI , DestBB , <NUM_LIT> ) ) return false ; if ( ! DT -> dominates ( DestBB , MBB ) ) return false ; Cmp . NewOpc = Cmp . NewOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , Br . MI , Br . MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( Br . MI -> getOperand ( <NUM_LIT> ) ) ; Br . MI -> eraseFromParent ( ) ; Br . MI = MIB ; ++ NumLEInserted ; return true ; } ; bool MadeChange = false ; for ( ImmBranch & Br : reverse ( ImmBranches ) ) { MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; MachineBasicBlock * ExitBB = & MBB -> back ( ) == Br . MI ? MBB -> getFallThrough ( ) : MBB -> back ( ) . getOperand ( <NUM_LIT> )


<s> SDLoc dl ( N ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) ,


<s> IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PostRAScheduler = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; stackAlignment = <NUM_LIT> ; MaxInlineSizeThreshold = <NUM_LIT>


<s> for ( int i = NumFPRegs - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! isLive


<s> void <ISA_LIT>AsmPrinter :: printMandatoryPredicateOperand ( const MachineInstr * MI , int OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) .


<s> const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( BaseOp1 . getType ( ) != BaseOp2 . getType ( ) ) return false ; assert ( ( BaseOp1 . isReg ( ) || BaseOp1 . isFI ( ) ) && <STR_LIT> ) ; if ( BaseOp1 . isReg ( ) && BaseOp1 . getReg ( ) != BaseOp2 . getReg ( ) ) return false ; if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode


<s> if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( needsWinCFI ( MF ) && AFI -> getCalleeSavedStackSize ( ) > <NUM_LIT> && MF . getFunction ( ) . hasOptSize ( ) ) return false ; if ( StackBumpBytes >= <NUM_LIT> || windowsRequiresStackProbe ( MF ,


<s> static unsigned CalculateStackSlotSize ( EVT ArgVT , <STR_LIT> Flags , unsigned PtrByteSize ) { unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ; if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ; ArgSize = ( ( ArgSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; return ArgSize


<s> if ( NumLaneElts == <NUM_LIT> ) return false ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { unsigned i ; for ( i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { if ( Mask [ i + l ] >= <NUM_LIT> ) break ; } if ( i == NumLaneElts ) continue ; int Start = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Start , l , l + NumLaneElts ) && ! isUndefOrInRange ( Start , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Start , Mask [ i ] + l ) ) return false ; if ( Start >= ( int ) NumElts ) Start -= NumElts - NumLaneElts ; if ( Start <= ( int ) ( i + l ) ) return false ; Start -= i ; for ( ++ i ; i != NumLaneElts ; ++ i ) { int Idx = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Idx , l , l + NumLaneElts ) && ! isUndefOrInRange ( Idx , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Idx , Mask [ i ] + l ) ) return false ; if ( Idx >= ( int ) NumElts ) Idx -= NumElts


<s> static SDValue performSELECTCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; if ( ( SetCC . getOpcode ( ) != <STR_LIT> ) || ! SetCC . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue False = N -> getOperand ( <NUM_LIT>


<s> if ( Scale == <NUM_LIT> ) { Base = LHS ; Offset = RHS ; return true ; } if ( RHS . getOpcode ( ) != <STR_LIT> ) return false ; const SDValue ShiftRHS = RHS . getOperand ( <NUM_LIT> ) ; if ( auto * C = dyn_cast < ConstantSDNode > ( ShiftRHS ) ) if ( C


<s> void <ISA_LIT>TargetAsmStreamer :: emitFPU ( unsigned FPU ) { OS << <STR_LIT> << GetFPUName ( FPU ) <<


<s> VT = TLI . getValueType ( Ty , true ) ; if ( VT == <STR_LIT> || ! VT .


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & MemOp , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = <STR_LIT> ( Desc . TSFlags ) ; if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg (


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOffsetOfOperator ( SMLoc Start ) { SMLoc OffsetOfLoc = Start ; Parser . Lex ( ) ; Start = Parser . getTok ( ) . getLoc ( ) ; assert ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; SMLoc End ; const MCExpr *


<s> bool <ISA_LIT>AsmParser :: expandLoadImm ( MCInst & Inst , bool Is32BitImm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { const MCOperand & ImmOp = Inst . getOperand (


<s> MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return true ; } return false


, machine_mode mode ATTRIBUTE_UNUSED ) {


<s> assert ( ( Kind == k_RegList ) && <STR_LIT> ) ; return * ( RegList . List


<s> static inline uint8_t encodeAdvSIMDModImmType7 (


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO .

getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( MCInstLowering , * MI ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( * MI ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT>


<s> if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM .


<s> if ( BaseType != RegBase ) return false ; if ( RegisterSDNode * RegNode = dyn_cast_or_null < RegisterSDNode > ( Base_Reg . getNode ( )

) ) return RegNode -> getReg ( ) == <STR_LIT> ;


<s> static __inline__ void \ NAME ( TYPE * _PTR , TYPE _VALUE ) \ { \ __asm__ volatile ( OPCODE <STR_LIT> \ : <STR_LIT> ( _PTR [ <NUM_LIT> ] ) \ :

<STR_LIT> ( _VALUE ) , <STR_LIT> ( FC ) ) ; \ return ; \ }


<s> if ( NewFrom != From ) { CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; continue ; } if ( ( NewToMask & CombinedToMask ) . getBoolValue ( ) ) return SDValue ( ) ; if ( BitsProperlyConcatenate ( ToMask , NewToMask ) && BitsProperlyConcatenate ( FromMask , NewFromMask ) ) return V ; if ( BitsProperlyConcatenate ( NewToMask , ToMask ) && BitsProperlyConcatenate ( NewFromMask , FromMask ) ) return V ; CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; } return SDValue


<s> static bool isUndefInRange ( ArrayRef < int > Mask , unsigned Pos


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex


<s> return ( __m128i ) __builtin_ia32_pabsw128 ( ( __v8hi )


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool VectorRegs = ( ClassID == <NUM_LIT> ) ; if ( VectorRegs ) { return <NUM_LIT> ; } return <NUM_LIT>


<s> unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; }


<s> static void resolveZeroablesFromTargetShuffle ( const SmallVectorImpl < int > & Mask , APInt & KnownUndef , APInt & KnownZero ) { unsigned NumElts = Mask . size ( ) ; KnownUndef = KnownZero = APInt :: getNullValue ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i


<s> BitGroup ( SDValue V , unsigned R , unsigned S , unsigned E ) : V ( V ) , RLAmt ( R ) , StartIdx ( S ) , EndIdx ( E ) , Repl32 ( false ) , Repl32CR ( false ) , Repl32Coalesced ( false ) { DEBUG ( dbgs ( ) << <STR_LIT> << V . getNode ( ) << <STR_LIT> << R <<

<STR_LIT> << S << <STR_LIT> << E << <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> Code , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CondCode , Ctx ) ; Op -> CondCode . Code = Code ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b =


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return ; if ( ! MRI -> hasOneDef ( Reg ) ) return ; RegDomain RD = getDomain ( MRI -> getRegClass ( Reg ) , MRI -> getTargetRegisterInfo (


<s> virtual unsigned int execute ( function * ) { return sparc_do_work_around_errata ( )


<s> static DecodeStatus DecodeLSAImm ( MCInst & Inst , unsigned Insn , uint64_t Address ,


<s> SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ I ] . OrigArgIndex ; assert ( Ins [ I ] . PartOffset == <NUM_LIT> ) ; while ( I + <NUM_LIT> != E && Ins [ I + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ I + <NUM_LIT> ] ; unsigned PartOffset = Ins [ I + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ I ; } } else InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg && Subtarget . isTargetELF ( ) ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT>


<s> <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo (

<ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , JITInfo ( ) {


<s> void <ISA_LIT>JITInfo :: emitFunctionStubAtAddr ( const Function * F , void * Fn , void * Stub , MachineCodeEmitter & MCE ) { MCE . startGVStub ( F , Stub , <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> ) ; assert ( ( ( ( ( intptr_t ) Fn - MCE . getCurrentPCValue ( ) - <NUM_LIT> ) << <NUM_LIT> ) >> <NUM_LIT> )

== ( ( intptr_t ) Fn - MCE . getCurrentPCValue ( ) - <NUM_LIT> ) && <STR_LIT> ) ;


<s> SDValue StoredVal = St -> getValue ( ) ; if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { unsigned NumElts = StoredVal . getValueType ( ) . getVectorNumElements ( ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; if ( NumElts < <NUM_LIT> ) StoredVal = DAG . getZeroExtendInReg ( StoredVal , dl , EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) || ( ( StoreVT == <STR_LIT> || StoreVT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ,

DAG ) ) return splitVectorStore ( St , DAG ) ;


mode1 ) && ! loongarch_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ;


<s> return loongarch_small_data_pattern_1 (


<s> } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_SPESpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_SPE4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex =


<s> const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( ) + Size ; if ( V1 == V2 && End1 == End2 ) return false ; return ! AA -> alias ( AliasAnalysis :: Location ( V1 , End1 , Load -> getTBAAInfo ( ) ) , AliasAnalysis :: Location (

V2 , End2 , Store -> getTBAAInfo ( ) ) ) ;


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; EmitLabel ( Symbol ) ; Symbol -> setType (


<s> if ( ! CPC ) return false ; auto M = CPC -> getModifier ( ) ; auto * F = dyn_cast_or_null < Function > ( CPC -> getGV ( ) ) ; return ( M == <STR_LIT> || M == <STR_LIT> )

&& F && F -> getSectionPrefix ( ) == BinPrefix ;


<s> if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return SDValue ( ) ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( isAfterLegalize && ! DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd


<s> uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineFunction * F = MBB -> getParent ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * newMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * nextMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , newMBB ) ; F -> insert ( MBBIter , nextMBB ) ; nextMBB -> splice ( nextMBB -> begin ( ) , thisMBB , llvm :: next ( MachineBasicBlock :: iterator ( bInstr ) ) , thisMBB -> end ( ) ) ; nextMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; assert ( bInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; MachineOperand & destOper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; int numArgs = bInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; int valArgIndx = lastAddrIndx + <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned tt = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( invSrc ) { MIB = BuildMI ( newMBB , dl , TII -> get ( notOpc ) , tt ) . addReg ( t1 ) ; } else tt = t1 ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( regOpc ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( immOpc ) , t2 ) ; MIB . addReg ( tt ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , EAXreg ) ; MIB . addReg (


<s> unsigned CurOp = <STR_LIT> ( Desc ) ; const MCOperand & Op = MI . getOperand ( CurOp ) ; if ( ! Op . isExpr ( ) ) return false ; const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; return Ref && Ref -> getKind ( ) ==


<s> if ( Func . getName ( ) != <STR_LIT> && Func . getName ( ) != <STR_LIT> ) return false ; if ( Constant * Exp = dyn_cast < Constant > ( CI -> getArgOperand ( <NUM_LIT> ) ) ) if ( ConstantFP * CFP = dyn_cast_or_null < ConstantFP > ( Exp -> getSplatValue ( ) ) ) { if ( ! CI -> hasNoInfs ( ) || ! CI -> hasApproxFunc ( ) ) return false ; if ( ! CFP -> isExactlyValue ( <NUM_LIT> ) && ! CFP -> isExactlyValue ( <NUM_LIT> ) ) return false ; if ( CFP -> isExactlyValue ( <NUM_LIT> ) && ! CI -> hasNoSignedZeros ( ) )


<s> fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT>


<s> while ( FirstEpilogSEH -> getFlag ( MachineInstr :: FrameDestroy ) && FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: prev ( FirstEpilogSEH ) ; if ( FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: next ( FirstEpilogSEH ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addMBB ( TargetMBB ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addMBB ( TargetMBB ) . addImm ( <NUM_LIT> ) ; return true ; } Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; TargetOptions Options = MI . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options ; if ( Options . StackProtectorGuard == StackProtectorGuards :: SysReg ) { const <STR_LIT> * SrcReg = <STR_LIT> ( Options . StackProtectorGuardReg ) ; if ( ! SrcReg ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg , RegState :: Renamable ) . addImm ( SrcReg -> Encoding ) ; int Offset = Options . StackProtectorGuardOffset ; if ( Offset >= <NUM_LIT> && Offset <= <NUM_LIT> && Offset % <NUM_LIT> == <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg , RegState :: Kill ) . addImm ( Offset / <NUM_LIT> ) ; } else if ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg , RegState :: Kill ) . addImm ( Offset ) ; } else if ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) { if ( Offset > <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg , RegState :: Kill ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg , RegState :: Kill ) . addImm ( - Offset ) . addImm ( <NUM_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } MBB . erase ( MI ) ; return


<s> isAdd = false ; haveEaten = true ; } SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; int Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { if ( ! haveEaten ) return MatchOperand_NoMatch ; Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } <STR_LIT> ShiftTy = <STR_LIT> ; unsigned ShiftImm = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseMemRegOffsetShift ( ShiftTy , ShiftImm ) ) return MatchOperand_ParseFail ; E = Parser . getTok ( ) . getLoc ( ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePostIdxReg ( Reg , isAdd , ShiftTy ,


<s> AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved <


<s> if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( <NUM_LIT> <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - <NUM_LIT> ; break ; } SplatIndex = i ; } if ( <NUM_LIT> <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false


<s> AssemblerDialect = AsmWriterVariant == Default ? Generic : AsmWriterVariant ; CodePointerSize = T . getEnvironment ( ) == Triple :: GNUILP32 ? <NUM_LIT> : <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; Code32Directive =


<s> Offsets = GEP -> getOperand ( <NUM_LIT> ) ; unsigned OffsetsElemCount = cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ; assert ( Ty -> getNumElements ( ) == OffsetsElemCount ) ; ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ; if ( ZextOffs ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; FixedVectorType * OffsetType = cast < FixedVectorType > ( Offsets -> getType ( ) ) ; if ( ! ZextOffs || cast < FixedVectorType > ( ZextOffs -> getDestTy ( ) ) -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) if ( ! checkOffsetSize ( Offsets , OffsetsElemCount ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getElementType ( ) -> getScalarSizeInBits ( ) < OffsetType -> getElementType ( ) -> getScalarSizeInBits ( ) ) ) { Offsets = Builder . CreateTrunc (


<s> addPass ( createCheriAddressingModeFolder ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: Level ::

None ) addPass ( & DeadMachineInstructionElimID ) ;


<s> return - <NUM_LIT> ; } StringRef Name = Tok . getString ( ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchSVEPredicateNameAlias ( Head ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidSVEKind ( Kind ) )


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue (


<s> return __builtin_ia32_vcvtw2ph256_mask ( ( __v16hi ) __A , _mm256_setzero_ph ( ) , ( __mmask16 ) -


<s> for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , TRI ) ) return & * It ; if ( It -> readsRegister ( Reg


<s> int rx_adjust_insn_length ( rtx_insn * insn , int current_length ) { rtx extend , mem , offset ; bool zero ; int factor ; if ( ! INSN_P ( insn ) ) return current_length ; switch ( INSN_CODE ( insn ) ) { default : return current_length ; case CODE_FOR_plussi3_zero_extendhi : case CODE_FOR_andsi3_zero_extendhi : case CODE_FOR_iorsi3_zero_extendhi : case CODE_FOR_xorsi3_zero_extendhi : case CODE_FOR_divsi3_zero_extendhi : case CODE_FOR_udivsi3_zero_extendhi : case CODE_FOR_minussi3_zero_extendhi : case CODE_FOR_smaxsi3_zero_extendhi : case CODE_FOR_sminsi3_zero_extendhi : case CODE_FOR_multsi3_zero_extendhi : case CODE_FOR_comparesi3_zero_extendhi : zero = true ; factor = <NUM_LIT> ; break ; case CODE_FOR_plussi3_sign_extendhi : case CODE_FOR_andsi3_sign_extendhi : case CODE_FOR_iorsi3_sign_extendhi : case CODE_FOR_xorsi3_sign_extendhi : case CODE_FOR_divsi3_sign_extendhi : case CODE_FOR_udivsi3_sign_extendhi : case CODE_FOR_minussi3_sign_extendhi : case CODE_FOR_smaxsi3_sign_extendhi : case CODE_FOR_sminsi3_sign_extendhi : case CODE_FOR_multsi3_sign_extendhi : case CODE_FOR_comparesi3_sign_extendhi : zero = false ; factor = <NUM_LIT> ; break ; case CODE_FOR_plussi3_zero_extendqi : case CODE_FOR_andsi3_zero_extendqi : case CODE_FOR_iorsi3_zero_extendqi : case CODE_FOR_xorsi3_zero_extendqi : case CODE_FOR_divsi3_zero_extendqi : case CODE_FOR_udivsi3_zero_extendqi : case CODE_FOR_minussi3_zero_extendqi : case CODE_FOR_smaxsi3_zero_extendqi : case


<s> static SDValue LowerFGETSIGN ( SDValue Op , SelectionDAG & DAG ) { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 ,

DAG . getConstant ( <NUM_LIT> , VT ) ) ;


<s> default : break ; case <STR_LIT> : Res = combineToCMPB ( N ) ; break ; } if ( ! Res ) foldBoolExts ( Res , N ) ; if ( Res ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Res . getNode ( ) -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; MadeChange = true ; } } if ( MadeChange ) CurDAG


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getTargetData ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getTargetData ( ) -> getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant


<s> void printMemOffs64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemOffset ( MI , OpNo ,


<s> if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg .


<s> if ( SrcVT == <STR_LIT> ) { if ( ! IsSigned ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( Subtarget -> hasLFIWAX ( ) ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; } } const TargetRegisterClass * RC = & <STR_LIT> ; Register ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( <STR_LIT> , ResultReg , Addr , RC , ! IsSigned , LoadOpc )


<s> reportParseError ( <STR_LIT> ) ; return false ; } if ( ( SymbolName != CurrentFn -> getName ( ) ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveEnd ( SymbolName ) ; CurrentFn = nullptr ; IsCpRestoreSet = false ; return false ; } if ( IDVal == <STR_LIT> ) { SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > TmpReg ; OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & StackRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! StackRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( StackRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } unsigned StackReg = StackRegOpnd . getGPR32Reg ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } const MCExpr * FrameSize ; int64_t FrameSizeVal ; if ( Parser . parseExpression ( FrameSize ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! FrameSize -> evaluateAsAbsolute ( FrameSizeVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } TmpReg . clear ( ) ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & ReturnRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! ReturnRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( ReturnRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitFrame ( StackReg , FrameSizeVal , ReturnRegOpnd . getGPR32Reg ( ) ) ; IsCpRestoreSet = false ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { const MCExpr * BitMask ; int64_t BitMaskVal ; if ( Parser . parseExpression ( BitMask ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! BitMask -> evaluateAsAbsolute ( BitMaskVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser


<s> if ( addend ) { x = gen_rtx_PLUS ( SImode , x , addend ) ; orig_x = x ; } else return x ; } if ( ! TARGET_ARM ) { if ( TARGET_THUMB2 ) return x ; return thumb_legitimize_address ( x , orig_x , mode ) ; } if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) && ! symbol_mentioned_p ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! CONST_INT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ; if ( ARM_BASE_REGISTER_RTX_P ( xop0 ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT n , low_n ; rtx base_reg , val ; n = INTVAL ( xop1 ) ; if ( mode == DImode || mode == DFmode ) { low_n = n & <NUM_LIT> ; n &= ~ <NUM_LIT> ; if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = plus_constant ( Pmode , base_reg , low_n ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! symbol_mentioned_p ( xop1


<s> static SDValue lowerVectorShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType (


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . init ( * TRI ) ; DomBBUsedRegs . init ( * TRI ) ; OptBBClobberedRegs . init ( * TRI ) ; OptBBUsedRegs . init ( * TRI ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF )


<s> return Op . isReg ( ) && Op . getReg ( )


<s> static DecodeStatus DecodeG8RCRegisterClass ( MCInst & Inst , uint64_t RegNo

, uint64_t Address , const MCDisassembler * Decoder ) {


<s> int FI = MFI . CreateSpillStackObject ( SlotSize , Align ( SlotSize ) ) ; <ISA_LIT>FI -> setHasSEHFramePtrSave ( true ) ; <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( )


<s> SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) <STR_LIT> || Hint . first == ( unsigned ) <STR_LIT>

) && TargetRegisterInfo :: isVirtualRegister ( Hint . second ) ) {


<s> bool <ISA_LIT>TargetLowering :: shouldNormalizeToSelectSequence ( LLVMContext & , EVT ) const { return false


<s> return __builtin_mve_uqrshll_sat64_di ( value


<s> void <ISA_LIT>InstPrinter :: printCCOperand ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O ) { int CC = ( int ) MI -> getOperand (


<s> return __builtin_aarch64_sqdmlal2v8hi ( __a ,


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C ,


<s> rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_USE_SAHF ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( <NUM_LIT> ) ) ) ; temp = gen_rtx_REG ( CCNOmode


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + <NUM_LIT> ) >> <NUM_LIT> ; else return ( size + <NUM_LIT> ) >>


<s> static ScheduleDAGInstrs * create<ISA_LIT>PostMachineScheduler ( MachineSchedContext * C ) { ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , llvm :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C )


<s> int fp_reg_size = <NUM_LIT> ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , <NUM_LIT> ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> static bool isVectorShift ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , bool & isLeft ,


<s> Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true


<s> <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue (


<s> return ( __m128i ) __builtin_ia32_expandhi128_mask ( ( __v8hi ) __C ,


<s> vld1q_dup_u64 ( const uint64_t * __a ) { return vdupq_n_u64 (


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLSMultiple ( MachineInstr * MI ) { if ( isThumb1 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; Register Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB


<s> if ( GET_CODE ( src ) == LO_SUM && symbolic_operand ( XEXP ( src , <NUM_LIT> ) , VOIDmode ) && ! read_only_operand ( XEXP ( src , <NUM_LIT> ) , VOIDmode ) ) priority >>= <NUM_LIT> ; else if ( GET_CODE ( src ) == MEM && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) priority >>= <NUM_LIT> ; else if ( GET_CODE ( dest ) == MEM && GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> )

, VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) priority >>= <NUM_LIT> ;


<s> __asm__ ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( __A ) , <STR_LIT> ( res ) , <STR_LIT> ( dtmp ) : ) ; res = __builtin_llrint ( __A [ <NUM_LIT> ] ) ; return (


<s> EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , NewEltVT , EltCnt / <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( LoOpcode , dl , NewVT , In ) ; SDValue Hi = DAG . getNode ( HiOpcode , dl , NewVT , In ) ; assert ( isTypeLegal ( NewVT ) && <STR_LIT> ) ; NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , EltCnt / <NUM_LIT> ) ; Lo = DAG . getNode ( N -> getOpcode ( ) , dl , NewVT , Lo ) ; Hi = DAG . getNode ( N -> getOpcode ( )


<s> <ISA_LIT>ConstantPoolValue * NewCPV = <NUM_LIT> ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) -> getContext ( ) , ACPV -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getBlockAddress ( ) , PCLabelId ,


<s> if ( MO . isReg ( ) ) return <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , true ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) ,


<s> OperandMatchResultTy ResTy = parseAnyRegister ( Operands ) ; if ( ResTy == MatchOperand_Success ) { assert ( Operands . size ( ) == <NUM_LIT> ) ; <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; RegNo = - <NUM_LIT> ; if ( Operand . isGPRAsmReg ( )


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index ,


<s> for ( unsigned I = <NUM_LIT> , E = Ret . getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Ret . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! <STR_LIT> . contains ( MO . getReg ( ) ) ) continue ; unsigned RegNo = TRI -> getEncodingValue ( MO . getReg ( ) ) ; UsedRegMask &= ~ ( <NUM_LIT> << ( <NUM_LIT> - RegNo ) ) ; } } if ( UsedRegMask == <NUM_LIT> ) { RemoveVRSaveCode ( MI ) ; return ; } unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; } else { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> )


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Immediate , StartLoc , EndLoc ) ; Res -> Imm . Val = Val ; return


<s> rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; value = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ; op = XEXP ( op , <NUM_LIT> ) ; early_op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( early_op ) != REG ) early_op = XEXP ( early_op , <NUM_LIT> ) ; return ! reg_overlap_mentioned_p ( value , early_op )


<s> return ( int8x8_t ) __builtin_neon_vqaddsv8qi


<s> unsigned getNumFixupKinds ( ) const { return <NUM_LIT>


<s> default : break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned RotAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i < RotAmt ? i + ( Bits . size ( ) - RotAmt ) : i - RotAmt ] ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = ShiftAmt ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i - ShiftAmt ] ; for ( unsigned i = <NUM_LIT> ; i < ShiftAmt ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) )


<s> PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = false ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 =


<s> getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32


<s> MCSection * <ISA_LIT>ElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK ,


<s> return new <ISA_LIT>WinCOFFStreamer ( Context , MAB ,


<s> auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( )

} , { Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> uint32_t Imm8 ; return isFPImm ( Val


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; MinimizeSize = MF . getFunction ( ) -> hasFnAttribute


<s> for ( CPUser & U : CPUsers ) { unsigned UserOffset = getUserOffset ( U ) ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp ( ) + <NUM_LIT> , U . NegOk , true ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> dispatch_windows * list ; int i ; if ( window_num == <NUM_LIT> ) list = dispatch_window_list ; else list = dispatch_window_list1 ; fprintf ( file , <STR_LIT> , list -> window_num ) ; fprintf ( file , <STR_LIT> , list -> num_insn , list -> num_uops , list -> window_size ) ; fprintf ( file , <STR_LIT> , list -> num_imm , list -> num_imm_32 , list -> num_imm_64 , list -> imm_size ) ; fprintf ( file , <STR_LIT> , list -> num_loads , list -> num_stores ) ; fprintf ( file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < MAX_INSN ; i ++ ) { if ( ! list -> window [ i ] . insn


<s> SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getConstant


<s> return ( __m128i ) __builtin_ia32_pmovsqd128_mask ( ( __v2di ) __A , (


<s> SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getBitcast ( MaskVT , V1Mask ) , DAG . getBitcast ( MaskVT


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand


<s> const Register DestRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser ) : MCTargetAsmParser ( ) , STI (

sti ) , Parser ( parser ) , InstInfo ( <NUM_LIT> ) {


<s> lo_sum_symbol = mips_unspec_address ( addr , type ) ; if ( type == SYMBOL_GOTOFF_CALL ) return mips_unspec_call ( high , lo_sum_symbol ) ; else return PMODE_INSN ( gen_unspec_got , ( high , lo_sum_symbol