<s> if ( Fractional ) OS << <STR_LIT> ; else OS << <STR_LIT> ; OS << LMul ; if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType )


<s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( TM . isPositionIndependent ( ) || STI . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & LuiMI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScratchReg )


<s> if ( Opt == <STR_LIT> ) { NoAliases = true ; return true ; } if ( Opt == <STR_LIT> ) { ArchRegNames =


<s> LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return false ; } assert ( LocVT == XLenVT && <STR_LIT> ) ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT


<s> static bool incompatible_avl_p ( const vector_insn_info & info1 , const vector_insn_info &


<s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin &&


<s> static unsigned riscv_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask , n

) ) return CALLEE_SAVED_REG_NUMBER ( n ) + <NUM_LIT> ;


<s> if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case VK_<ISA_LIT>_PCREL_HI : return false ; } } return true


<s> riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 > <NUM_LIT> ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) { rtx dwarf = riscv_adjust_libcall_cfi_epilogue ( ) ; insn = emit_insn ( gen_gpr_restore ( GEN_INT ( riscv_save_libcall_count ( mask ) ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; emit_jump_insn ( gen_gpr_restore_return ( ra )


<s> SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , One ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , XLenMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo ,


<s> case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr ::


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) )


<s> case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , Mask , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; return DAG . getSetCC ( DL , XLenVT , Vec , Zero , <STR_LIT> ) ; case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; return DAG . getSetCC ( DL , XLenVT , Vec , Zero , <STR_LIT> ) ; case <STR_LIT> : { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , One


<s> if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : Size - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; int MaskSrc = M < Size ? <NUM_LIT> : <NUM_LIT> ; int & TargetSrc = StartIdx < <NUM_LIT> ? HiSrc : LoSrc ; if ( TargetSrc < <NUM_LIT> ) TargetSrc = MaskSrc ; else if ( TargetSrc != MaskSrc ) return - <NUM_LIT> ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( LoSrc >= <NUM_LIT> || HiSrc >= <NUM_LIT> ) && <STR_LIT> ) ; return Rotation


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { report_fatal_error ( <STR_LIT> )


<s> SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant (


<s> case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get (


<s> } } ; auto IsReduction = [ & BinOpToRVVReduce ] ( SDValue V , unsigned Opc ) { return V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == BinOpToRVVReduce ( Opc ) ; } ; unsigned Opc = N -> getOpcode ( ) ; unsigned ReduceIdx ; if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else if ( IsReduction ( N -> getOperand ( <NUM_LIT> ) , Opc ) ) ReduceIdx = <NUM_LIT> ; else return SDValue ( ) ; if ( Opc == <STR_LIT> && ! N -> getFlags ( ) . hasAllowReassociation ( ) ) return SDValue ( ) ; SDValue Extract = N -> getOperand ( ReduceIdx ) ; SDValue Reduce = Extract . getOperand ( <NUM_LIT> ) ; if ( ! Reduce . hasOneUse ( ) ) return SDValue ( ) ; SDValue ScalarV = Reduce . getOperand ( <NUM_LIT> ) ; if ( ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> && ScalarV . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isOneConstant ( ScalarV . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsRVVNeutralElement = [ Opc , & DAG ] ( SDNode * N , SDValue V ) { if ( Opc == <STR_LIT> && N -> getFlags ( ) . hasNoSignedZeros ( ) && isNullFPConstant ( V ) ) return true ; return DAG . getNeutralElement ( Opc , SDLoc ( V ) , V . getSimpleValueType ( ) , N -> getFlags ( )


<s> return & InstrInfo . getRegisterInfo (


<s> if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res =


<s> for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg

) . addReg ( VR ) . addImm ( ShiftAmount ) ;


<s> bool IsZvlsseg = true ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ; auto MIB = BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const


<s> if ( ! SMALL_OPERAND ( min_second_step ) && frame_total_constant_size % IMM_REACH < IMM_REACH / <NUM_LIT> && frame_total_constant_size % IMM_REACH >= min_first_step ) return frame_total_constant_size % IMM_REACH ; if ( TARGET_RVC ) { if ( IN_RANGE ( min_second_step , <NUM_LIT> , ( TARGET_64BIT ? SDSP_REACH : SWSP_REACH ) ) ) return MAX ( min_second_step , min_first_step ) ; else if ( ! SMALL_OPERAND ( min_second_step ) ) return min_first_step ; } return max_first_step


<s> uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize (


<s> if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand ::


<s> SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusXLen ) ; SDValue HiFalse = IsSRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , XLenMinus1 ) : Zero ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , LoFalse ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ; SDValue Parts [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Parts , DL


<s> bool Unsigned = false ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > ( Hi52 ) ) { if ( isInt < <NUM_LIT> > ( ( uint64_t ) Hi52 << <NUM_LIT> ) ) { ShiftAmount -= <NUM_LIT> ; Hi52 = ( uint64_t ) Hi52 << <NUM_LIT> ; } else if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Hi52 << <NUM_LIT> ) && ActiveFeatures [ <STR_LIT> ] ) { ShiftAmount -= <NUM_LIT> ; Hi52 = ( ( uint64_t ) Hi52 << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Hi52 ) && ! isInt < <NUM_LIT> > ( ( uint64_t ) Hi52 ) && ActiveFeatures [ <STR_LIT> ] ) { Hi52 = ( ( uint64_t ) Hi52 ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } generateInstSeqImpl ( Hi52 , ActiveFeatures , Res ) ; if ( Unsigned ) Res . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; else Res . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( <STR_LIT>


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( Imm , VK


<s> KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT>


<s> auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; normaliseSetCC ( LHS , RHS , CCVal ) ; SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getConstant ( <STR_LIT> , DL , XLenVT ) ; SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL ,


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return false ; return any_of ( MF , [ & TII ]


<s> unsigned SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return expandAuipccInstPair ( MBB , MBBI , NextMBBI


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N1 ) && isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) && TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( ~ <NUM_LIT> , DL , <STR_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; } if ( SDValue V = combineBinOpToReduce ( N , DAG ) )


<s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return *


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char >

Data , uint64_t Value , bool IsPCRel ) const {


<s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind

Kind , const Constant * C , Align & Alignment ) const {


<s> if ( ( TREE_CODE ( decl ) != FUNCTION_DECL ) || ( ! riscv_interrupt_type_p ( TREE_TYPE ( decl ) ) ) ) return UNKNOWN_MODE ; tree attr_args = TREE_VALUE ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) ; if ( attr_args && TREE_CODE ( TREE_VALUE ( attr_args ) ) != VOID_TYPE ) { const char * string = TREE_STRING_POINTER ( TREE_VALUE ( attr_args ) ) ; if ( ! strcmp ( string , <STR_LIT> ) ) return USER_MODE ; else if ( ! strcmp ( string , <STR_LIT> ) ) return SUPERVISOR_MODE ; else return MACHINE_MODE


<s> bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg (


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; const MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( TRI && <STR_LIT> ) ; uint64_t TSFlags = MI -> getDesc ( ) . TSFlags ; int NumOps = MI -> getNumExplicitOperands ( ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { int OpNo = ( int ) MI -> getOperandNo ( & MO ) ; assert ( OpNo >= <NUM_LIT> && <STR_LIT> ) ; if ( ( TSFlags & <STR_LIT> ) && OpNo == ( NumOps - <NUM_LIT> ) ) continue ; if ( ( TSFlags & <STR_LIT> ) && OpNo == ( NumOps - <NUM_LIT> ) ) continue ; if ( ( TSFlags & <STR_LIT> ) && OpNo == <NUM_LIT> ) { assert ( MI -> getNumExplicitDefs ( )


<s> std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . hasD ( ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; }


<s> assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( Multiplier , ElementWidth , true , false ) ) ; MI . getOperand ( SEWIndex )


<s> bool willForceRelocations ( ) const { return ForceRelocs || STI . getFeatureBits ( ) [


<s> if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ; unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ; if ( LMul > Subtarget . getMaxLMULForFixedLengthVectors ( ) )


<s> assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VPOp = DAG . getNode ( <ISA_LIT>ISDOpc ,


<s> assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! Subtarget . hasVInstructions ( ) ) return SDValue ( ) ; bool HasChain = Op . getOpcode ( ) == <STR_LIT> ; unsigned IntNo = Op . getConstantOperandVal ( HasChain ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Op ) ; const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II || ! II -> hasSplatOperand ( ) ) return SDValue ( ) ; unsigned SplatOp = II -> SplatOperand + <NUM_LIT> + HasChain ; assert ( SplatOp < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ SplatOp ] ; MVT OpVT = ScalarOp . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpVT == XLenVT ) return SDValue ( ) ; if ( OpVT . bitsLT (


<s> if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ; return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> ,


<s> return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSIEAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadTLSGDAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandReadCSRs ( MBB , MBBI , <NUM_LIT> ) ; case


<s> auto Idx = <STR_LIT> ( Opc , <STR_LIT> :: frm ) ; if ( Idx < <NUM_LIT> ) return ; if ( MI . getOperand ( Idx ) . getImm (


<s> static bool riscv_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS


<s> rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ; set_new_first_and_last_insn ( NULL , NULL ) ; for ( machine_mode mode : modes ) emit_move_insn ( gen_reg_rtx ( mode ) , gen_int_mode ( BYTES_PER_RISCV_VECTOR


<s> auto Op = make_unique < <ISA_LIT>Operand > ( KindToken , Loc , Loc ) ; Op -> Token . Data = Str . data ( ) ; Op -> Token . Length = Str . size


<s> unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = fcode >> RISCV_BUILTIN_SHIFT ; switch ( fcode & RISCV_BUILTIN_CLASS ) { case RISCV_BUILTIN_VECTOR : return <STR_LIT> ( subcode , exp , target ) ; case RISCV_BUILTIN_GENERAL : { const struct riscv_builtin_description * d = & riscv_builtins [ subcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case


<s> insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size )


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize (


<s> bool isImmXLen ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( )


<s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign :: ZExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) ,


<s> bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI


<s> case VK_<ISA_LIT>_TPREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_CINCOFFSET : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_CALL_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_CCALL : return <STR_LIT> ; case VK_<ISA_LIT>_32_PCREL : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>InstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsRV64 = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Num


<s> return true ; } if ( Opt == <STR_LIT> ) { ArchRegNames = true ; return


<s> codes [ <NUM_LIT> ] . value = value ; return <NUM_LIT> ; } if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( value ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = value ; return <NUM_LIT> ; } if ( low_part != <NUM_LIT> && ( mode != HImode || value - low_part <= ( ( <NUM_LIT> << ( GET_MODE_BITSIZE ( HImode ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) ) { alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , value - low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = PLUS ; alt_codes [ alt_cost - <NUM_LIT> ] . value = low_part ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( cost > <NUM_LIT> && ( low_part < <NUM_LIT> || mode == HImode ) ) { alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , value ^ low_part , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = XOR ; alt_codes [ alt_cost - <NUM_LIT> ]


<s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm


<s> bool isUImm20LUI ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; }


<s> static unsigned getFPReg ( const <ISA_LIT>Subtarget & STI


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto * PR = PassRegistry :: getPassRegistry (


<s> return log2LdstWidth ( Opcode ) == <NUM_LIT> ? isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) :

isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ;


<s> static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; Inst . addOperand ( Inst . getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>AsmPrinter :: emitStartOfAsmFile ( Module


<s> static bool use_real_merge_p ( enum predication_type_index pred


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) if ( GET_CODE ( * iter ) == CONST_POLY_INT ) return true ; if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; const DataLayout & DL = getDataLayout


<s> for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( regno == RETURN_ADDR_REGNUM ) offset = saved_size - UNITS_PER_WORD ; else if ( regno == S0_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else if ( regno == S1_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else offset = saved_size - ( ( regno - S2_REGNUM + <NUM_LIT> ) * UNITS_PER_WORD ) ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = gen_rtx_SET ( mem , reg ) ; dwarf = alloc_reg_note ( REG_CFA_OFFSET , insn , dwarf ) ; } adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - saved_size ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { llvm_unreachable ( <STR_LIT>


<s> bool popFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ; if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ; return false


<s> auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits (


<s> int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( Expr


<s> while ( getTypeAction ( * DAG . getContext ( ) , VecEVT ) == TargetLowering :: TypeSplitVector ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Vec , DL ) ; VecEVT = Lo . getValueType ( ) ; Vec = DAG . getNode ( BaseOpc , DL , VecEVT , Lo , Hi ) ; } if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVReductionOp ( Op . getOpcode ( )


<s> static unsigned riscv_pass_mode_in_fpr_p ( machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FP_ARG ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return <NUM_LIT> ; } return <NUM_LIT>


<s> EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; } return


<s> assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; } MCInst TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) .

addOperand ( TPReg ) . addOperand ( SrcReg ) ;


<s> for ( int i = <NUM_LIT> ; op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i

) if ( FLOAT_MODE_P ( TYPE_MODE ( get_arg_type ( i ) ) ) ) return true ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable (


<s> bool isValid ( ) const { return State !=


<s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value


<s> VariantKind Kind = getKind ( ) ; bool HasVariant = ( ( Kind != VK_<ISA_LIT>_None ) && ( Kind != VK_<ISA_LIT>_CALL ) && ( Kind != VK_<ISA_LIT>_CALL_PLT ) ) ; if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT )


<s> static bool bindsLocally ( const GlobalValue * GV ,


<s> int n = MI . getOperand ( immediate ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , isset ) ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( r_pos <= l_pos ) ; unsigned opcode = isset ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder pbclrMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pbclrMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pbclrMI . addOperand ( MI . getOperand ( registr ) ) ; pbclrMI . addImm ( l_pos -


<s> static VSETVLIInfo getInfoForVSETVLI ( const MachineInstr & MI ) { VSETVLIInfo NewInfo ; if ( MI . getOpcode ( ) == <STR_LIT> ) { NewInfo . setAVLImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { assert ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ; Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( AVLReg != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && <STR_LIT> ) ; NewInfo . setAVLReg ( AVLReg ) ; } NewInfo . setVTYPE ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return NewInfo


<s> static unsigned HOST_WIDE_INT riscv_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1 <<


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; emitTextAttribute ( <STR_LIT>


<s> return ( VT == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> &&


<s> else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT ,

CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy ) ) {


<s> bool <ISA_LIT>AsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT>


<s> riscv_move_integer ( hi , hi , hival ) ; riscv_move_integer ( lo , lo , loval ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKRESTORE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setManipulatesSP ( true ) ; unsigned sp = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc (

Op ) , sp , Op . getOperand ( <NUM_LIT> ) ) ;


<s> add_input_operand ( mode , CONSTM1_RTX ( mode


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering


<s> else add_all_one_mask_operand ( mask_mode ( ) ) ; rtx vd = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( VECTOR_MODE_P ( GET_MODE ( vs1 ) ) ) { if ( ! vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs1 ) ; add_input_operand ( mode , vs2 ) ; if ( vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode ,


<s> void setCalleeSavedStackSize ( unsigned


<s> switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i


<s> void riscv_split_doubleword_move ( rtx dest , rtx src ) { rtx low_dest ; low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) &&

reg_overlap_mentioned_p ( low_dest , src ) ) {


<s> rtx expand ( function_expander & e ) const override { machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ; emit_move_insn ( e . target ,


<s> return static_cast < VLMUL > ( ( TSFlags & VLMulMask )


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI20 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI20 ) . Case ( <STR_LIT> ,

VK_<ISA_LIT>_TPREL_LO12 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI20 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) )

return outliner :: InstrType :: Invisible ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( SplatVal . getValueType ( ) == XLenVT && <STR_LIT> ) ; MVT InterVT = VT . changeVectorElementType ( <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , DL , XLenVT , SplatVal , DAG . getConstant ( <NUM_LIT> , DL


<s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; else Base =


<s> FrameSize += ( MaxStackAlign - StackAlign ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize


<s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address ( addr , symbol_type


<s> static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm (


<s> case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits


<s> if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ; unsigned LMul = divideCeil ( VT . getSizeInBits ( ) ,


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( N ) ) { int64_t ImmVal = SignExtend64 ( C -> getSExtValue


<s> bool <ISA_LIT>DAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return false ; SDValue Shl = N -> getOperand ( <NUM_LIT> ) ; uint64_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Shl . getConstantOperandVal


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI


<s> return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT>


<s> static insn_info * find_reg_killed_by ( const bb_info * bb , rtx x ) { if ( ! x || vlmax_avl_p ( x ) || ! REG_P ( x ) ) return nullptr ; for ( insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) if ( find_access ( insn -> defs ( ) , REGNO ( x ) ) ) return insn ; return nullptr


<s> void function_builder :: append_base_name ( const char * name ) { append_name ( <STR_LIT> ) ; append_name ( name )


<s> return ( HasStdExtV || HasStdExtZve32f ) && HasStdExtZfh


<s> lowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { return SDValue (


<s> MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) { PrevVSETVLI = nullptr ; } continue ; } if ( ! PrevVSETVLI || ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { PrevVSETVLI = & MI ; continue ; } if ( PrevVSETVLI -> getOpcode ( ) != MI . getOpcode ( ) ) { PrevVSETVLI = & MI ; continue ; } Register AVLReg ; bool SameAVL = false ; if ( MI . getOpcode ( ) == <STR_LIT> ) { AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) == AVLReg ; } else { SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) == MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! SameAVL || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( AVLReg == <STR_LIT> ) ) { assert ( ( PrevVSETVLI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) { PrevVSETVLI =


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target (


<s> static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPRRegisterClass ( Inst , Rs2 , Address ,


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI .


<s> if ( ArgVT . isScalableVector ( ) && ArgVT . getVectorElementType ( ) . SimpleTy == <STR_LIT> ) return ArgIdx . index ( ) ; } return None


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode


<s> if ( SEWLMULRatioOnly ) return false ; if ( Require . hasAVLReg ( ) && Require . AVLReg == <STR_LIT> ) if ( SEW == Require . SEW ) return true ; if ( Require . ScalarMovOp && Require . hasAVLImm ( ) && ( ( hasNonZeroAVL ( ) && Require . hasNonZeroAVL ( ) ) || ( hasZeroAVL ( ) && Require . hasZeroAVL ( ) ) ) && hasSameSEW ( Require ) && hasSamePolicy ( Require ) ) return true ; if ( ! hasSameAVL ( Require ) ) return false ; if ( hasCompatibleVTYPE ( Require ) ) return true ; if ( Require . StoreOp && VLMul == Require . VLMul && SEW == Require . SEW ) return true ; return


<s> VarArgsFrameIndex = YamlMFI . VarArgsFrameIndex ; VarArgsSaveSize = YamlMFI


<s> static Register getSPReg ( const <ISA_LIT>Subtarget & STI ) { return <STR_LIT>


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg ==


<s> MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA , getRegClassFor


<s> bool Res = compressInst ( CInst , Inst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ; AsmPrinter :: EmitToStreamer ( * OutStreamer ,


<s> SDValue StepVec = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; uint64_t StepValImm = Op . getConstantOperandVal ( <NUM_LIT> ) ; if ( StepValImm != <NUM_LIT> ) { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == XLenVT && <STR_LIT> ) ; if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; SDLoc DL ( V


<s> return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index || type == RVV_BASE_float_vector || type == RVV_BASE_double_trunc_float_vector || type == RVV_BASE_double_trunc_vector || type == RVV_BASE_widen_lmul1_vector || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret || type == RVV_BASE_vlmul_ext_x2

|| type == RVV_BASE_vlmul_ext_x4 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64 ;


<s> assert ( Kind == SystemRegister && <STR_LIT>


<s> <STR_LIT> getFixupKind ( ) const { return getFixupKind ( Kind


<s> if ( hasAVLReg ( ) ) return getAVLReg ( ) == <STR_LIT> ; return false


<s> } } if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) { rtx dest = get_vl ( insn -> rtl ( ) ) ; for ( insn_info * i = insn -> prev_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> prev_nondebug_insn ( ) ) { if ( find_access ( i -> uses ( ) , REGNO ( dest ) ) ) return false ; if ( find_access ( i -> defs ( ) , REGNO ( dest ) ) ) return false ; } } return


<s> void <ISA_LIT>TargetStreamer :: setTargetABI ( <STR_LIT> ABI


<s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK ==


<s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Base = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Base = ST -> getBasePtr ( ) ; } else { return false ; } if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT>


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment


<s> return isMem ( RegKind , HasIndex ) && inRange (


<s> if ( cfun -> machine -> naked_p ) return false ; if ( cfun -> machine -> interrupt_handler_p ) return false ; return true


<s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr ::


<s> inline bool function_base :: apply_tail_policy_p (


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , FS , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) { initAsmInfo (


<s> return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionNoCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> ,


<s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo ,


<s> const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable (


<s> } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; if ( base -> apply_mask_policy_p ( ) ) add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; if ( base -> apply_vl_p ( ) ) add_input_operand ( Pmode , get_avl_type_rtx ( avl_type ::


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } Register Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> static bool riscv_verify_type_context ( location_t loc , type_context_kind context , const_tree


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return


<s> static bool matchRegisterNameHelper ( bool IsRV32E , Register & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name


<s> unsigned NumArgs = Ins . size ( ) ; FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || GET_MODE_BITSIZE ( mode ) >

GET_MODE_ALIGNMENT ( mode ) ) ) return false ;


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK ==


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute TuneAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT> ( ABIName ) ; if ( TargetABI != <STR_LIT> && ModuleTargetABI -> getString ( ) != ABIName ) { report_fatal_error (


<s> void <ISA_LIT>ConstantPoolValue :: print ( raw_ostream & O ) const { O << GV


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) RTS


<s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue BAHi = DAG . getTargetBlockAddress ( BA , Ty , Offset , <STR_LIT> ) ; SDValue BALo = DAG . getTargetBlockAddress ( BA , Ty , Offset , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , BAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , BALo


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: abs ( PowDiff ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( std :: abs ( PowDiff ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( Src -> isIntOrIntVectorTy ( ) ) return <NUM_LIT> ; return std :: abs ( PowDiff ) ; } } return BaseT :: getCastInstrCost ( Opcode , Dst , Src


<s> case LT : case LTU : return SMALL_OPERAND ( x ) ; case LE : return SMALL_OPERAND ( x + <NUM_LIT> ) ; case LEU : return SMALL_OPERAND ( x + <NUM_LIT> ) && x + <NUM_LIT> != <NUM_LIT> ; case GE : case GEU : return x == <NUM_LIT> ; default : return x ==


<s> return <STR_LIT> ; } else { assert ( TT . isArch32Bit ( ) && <STR_LIT>


<s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( )


<s> bool <ISA_LIT>MCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst


<s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK !=

<ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique

< <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) {


<s> bool selectRVVSimm5 ( SDValue N , SDValue


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> auto CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ; MachineInstr & MI = * BuildMI ( & MBB , DL , get (


<s> bool hasSplatOperand ( ) const { return SplatOperand != <NUM_LIT>


<s> static hash_set < set_info * > get_all_sets ( set_info * set , bool real_p , bool phi_p , bool param_p ) { if ( real_p && phi_p && param_p ) return get_all_sets ( safe_dyn_cast < phi_info * > ( set )


<s> return parseRegister ( Operands , 'x' , GR64Regs ,


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Offset = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; Base = CurDAG -> getTargetConstant ( AM . Offset , SDLoc ( Base ) , VT ) ; return ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode ( ) , Trunc ) ; Base = Trunc ; } Offset = CurDAG -> getTargetConstant ( AM . Offset , SDLoc


<s> void setVarArgsFrameIndex ( unsigned FI


<s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT>


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT>


<s> MVT VecVT = Src . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL ,


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; if ( ! IsUnmasked ) Ops . push_back ( DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset )


<s> if ( InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW ) return true ; } if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( hasSameVTYPE ( InstrInfo ) ) return true ; if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ; if ( InstrInfo . StoreOp && VLMul == InstrInfo . VLMul && SEW == InstrInfo


<s> unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & LuiMI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScratchReg ) . addMBB ( & DestBB , <STR_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , LuiMI . getIterator ( )


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return


<s> bool vector_insn_info :: available_p ( const vector_insn_info & other ) const { return * this


<s> auto FRMArg = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( FRMArg


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : break ; } SmallVector < SDNode * , <NUM_LIT> > SetCCs ; for ( SDNode :: use_iterator UI = Src . getNode ( ) -> use_begin ( ) , UE = Src . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User == N ) continue ; if ( UI . getUse ( ) . getResNo ( ) != Src . getResNo ( ) ) continue ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SetCCs . push_back ( User ) ; continue ; } break ; } if ( SetCCs . empty ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; DCI . CombineTo ( N , SExt ) ; for ( SDNode * SetCC : SetCCs ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { SDValue SOp = SetCC -> getOperand ( j ) ; if ( SOp == Src ) Ops . push_back ( SExt ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SOp ) ) ; } Ops . push_back ( SetCC -> getOperand ( <NUM_LIT> ) ) ; DCI . CombineTo ( SetCC , DAG . getNode ( <STR_LIT> , DL , SetCC -> getValueType ( <NUM_LIT> )


<s> StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate : Imm = o . Imm ; break ; case KindTy


<s> if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM


<s> static DecodeStatus decodeFRMArg ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( ! llvm :: <STR_LIT> ( Imm ) )


<s> return calculate_vlmul ( info1 . get_sew ( )


<s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( reg_class_subset_p ( rclass , FP_REGS ) ) return riscv_hard_regno_nregs (


<s> visitUsedSymbol ( * Symbol ) ; MCContext & Context = getContext ( ) ; const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Context , Loc ) ; const MCBinaryExpr * CapExpr = MCBinaryExpr :: createAdd ( SRE , Addend , Context ) ; emitValueToAlignment ( CapSize , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; MCDataFragment * DF = new MCDataFragment ( ) ; MCFixup CapFixup = MCFixup :: create ( <NUM_LIT> , CapExpr , MCFixupKind ( <STR_LIT> ) ) ; DF -> getFixups ( ) .


<s> } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true


<s> SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result


<s> Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Store = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Store -> getChain ( ) , IntID } ; Ops . push_back ( Val ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Store -> getVTList ( ) , Ops , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ; } } return SDValue (


<s> if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; frame -> mask = <NUM_LIT> ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode ,


<s> run_poly_int_selftests ( ) ; run_const_vector_selftests (


<s> case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CVPCREL_UI12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CVPCREL_URS1 ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT>


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> )


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addImm ( Offset ) . addFrameIndex


<s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo (


<s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF


<s> if ( riscv_memmodel_needs_amo_acquire ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'F' : if ( riscv_memmodel_needs_release_fence ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'i' : if ( code != REG ) fputs ( <STR_LIT> , file ) ; break ; case 'S' : { rtx newop = GEN_INT ( ctz_hwi ( INTVAL ( op ) ) ) ; output_addr_const ( file , newop ) ; break ; } case 'T' : { rtx newop = GEN_INT ( ctz_hwi ( ~ INTVAL ( op ) ) ) ; output_addr_const ( file


<s> void <ISA_LIT>DAGToDAGISel :: addVectorLoadStoreOperands ( SDNode * Node , unsigned Log2SEW , const SDLoc & DL , unsigned CurOp , bool IsMasked , bool IsStridedOrIndexed , SmallVectorImpl < SDValue > & Operands , bool IsLoad , MVT * IndexVT ) { SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Glue ; SDValue Base ; SelectBaseAddr ( Node -> getOperand ( CurOp ++ ) , Base ) ; Operands . push_back ( Base ) ; if ( IsStridedOrIndexed ) { Operands . push_back ( Node -> getOperand ( CurOp ++ ) ) ; if ( IndexVT ) * IndexVT = Operands . back ( ) -> getSimpleValueType ( <NUM_LIT> ) ; } if ( IsMasked ) { SDValue Mask = Node -> getOperand ( CurOp ++ ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , <STR_LIT> , Mask , SDValue ( ) ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Operands . push_back ( CurDAG -> getRegister ( <STR_LIT> ,


<s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK ==


<s> static bool vector_config_insn_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type ( rinsn


<s> SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue


<s> static unsigned int riscv_min_arithmetic_precision ( void


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; for ( auto N : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setLoadExtAction ( N , XLenVT , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF


<s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; CInst . setLoc ( Inst . getLoc ( ) ) ; S . EmitInstruction ( ( Res ? CInst : Inst )


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; MachineInstr * SrcMI = MRI . getVRegDef (


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) )


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( )


<s> bool hasVInstructions ( ) const { return


<s> RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> ,


<s> StringRef getPassName ( ) const override { return


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return


<s> static bool isVLPreservingConfig ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) != <STR_LIT> ) return false ; assert ( <STR_LIT> == MI . getOperand (


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT>


<s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( STI . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1


<s> inline static bool isValidLMUL ( unsigned LMUL , bool


<s> MCRegister getSCSPReg ( ) { return <STR_LIT>


<s> static SDValue performXORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SelectionDAG & DAG = DCI .


<s> <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) || evaluateConstantImm ( Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) &&


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand ::


<s> EVT IndexVT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , <NUM_LIT> ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , <NUM_LIT> , old_flags ) ; * update = NULL_TREE


<s> const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind )


<s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SecondOpcode = SignExtend ? <STR_LIT> : <STR_LIT> ; int64_t ShAmt = ( isRV64 ( ) ? <NUM_LIT> : <NUM_LIT> ) - Width ; assert ( ShAmt > <NUM_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) . addOperand (


<s> MVT ExtVT = Op . getSimpleValueType ( ) ; if ( ! ExtVT . isFixedLengthVector ( ) ) return Op ; MVT VT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT ContainerExtVT = getContainerForFixedLengthVector ( ExtVT ) ; MVT ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , ContainerExtVT . getVectorElementCount ( ) ) ; SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask ,


<s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGFF ( SDNode * Node , bool IsMasked ) { SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp +=


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( )


<s> void <ISA_LIT>PassConfig :: addPreEmitPass (


<s> if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) { Val = N . getOperand ( <NUM_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ; return


<s> EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG


<s> switch ( ISDOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> ABI computeTargetABI ( const Triple & TT , FeatureBitset FeatureBits , StringRef ABIName ) { auto TargetABI = getTargetABI ( ABIName ) ; bool IsRV64 = TT . isArch64Bit ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( ! ABIName . empty ( ) && TargetABI == ABI_Unknown ) { errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( )


<s> inline machine_mode function_checker :: ret_mode ( ) const { return TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return


<s> void function_checker :: report_out_of_range ( unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT


<s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; return MIN ( PREFERRED_STACK_BOUNDARY , MAX ( PARM_BOUNDARY


<s> static rtx riscv_force_address ( rtx x , enum machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64_L64PC128_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64F_L64PC128F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ; case <STR_LIT> : case <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand (