<s> } Start = Tok . getLoc ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) { return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; } return <STR_LIT> ( RegNo , Start , End ) ; } return ParseIntelSegmentOverride ( RegNo , Start , Size ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( <NUM_LIT> , Start , <NUM_LIT> , false , Size ) ; AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; bool isSymbol = SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) != MCExpr :: Constant ; int64_t Imm = SM . getImm ( ) ; if ( SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) == MCExpr :: Constant ) SM . getSym ( ) -> evaluateAsAbsolute ( Imm ) ; if ( StartTok . isNot ( AsmToken :: Identifier ) && StartTok . isNot ( AsmToken :: String ) && isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Start ) ; else InstInfo -> AsmRewrites -> emplace_back ( AOK_Imm , Start , Len , Imm ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( isSymbol ) { if ( isParsingInlineAsm ( ) ) return CreateMemForInlineAsm ( <NUM_LIT> , SM . getSym ( ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( ) , Start , End , Size ) ; } const MCExpr * ImmExpr = MCConstantExpr :: create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> const MachineOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) , O ) ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) O << <STR_LIT> ; if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , O , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <NUM_LIT> , O , Modifier ) ; unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) O << ',' << ScaleVal ; } O <<


<s> bool <ISA_LIT>AsmParser :: parseDirectiveTLSDescSeq ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Parser . getTok ( ) . getIdentifier ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ , getContext ( ) ) ; Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) )


<s> if ( MI . isCall ( ) ) { assert ( MI . getDesc ( ) . getNumImplicitDefs ( ) <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getDesc ( ) . getNumImplicitDefs ( ) ; i ++ ) { MCPhysReg Reg = MI . getDesc ( ) . getImplicitDefs ( ) [ i ] ; if ( Reg == <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TargetOptions Options = Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options ; return Options . UnsafeFPMath || Options . AllowFPOpFusion == FPOpFusion :: Fast || Inst . getFlag ( MachineInstr :: FmContract ) ; return true ; } return


<s> Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; } report_fatal_error ( <STR_LIT> )


<s> case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case


<s> bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options .


<s> Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; } unsigned UsedLow = <NUM_LIT> ; unsigned UsedHigh = <NUM_LIT> ; for ( auto MOI = MI . operands_begin ( ) , MOE = MI . operands_end ( ) ; MOI != MOE ; ++ MOI ) { MachineOperand & MO = * MOI ; if ( MO . isReg ( ) ) { if ( unsigned Reg = MO . getReg ( ) ) { assert ( Reg < <STR_LIT> && <STR_LIT> ) ; if ( MO . isDef ( ) ) { LiveLow &= ~ LowGPRs [ Reg ] ; LiveHigh &= ~ HighGPRs [ Reg ] ; } else if ( ! MO . isUndef ( ) ) { UsedLow |= LowGPRs [ Reg ] ; UsedHigh |= HighGPRs [ Reg ] ; } } } } LiveLow |= UsedLow ; LiveHigh |=


<s> if ( GET_CODE ( xinsn ) == PLUS ) { rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 ; enum rtx_code code1 ; while ( GET_CODE ( xplus0 ) == SUBREG ) xplus0 = SUBREG_REG ( xplus0 ) ; code0 = GET_CODE ( xplus0 ) ; while ( GET_CODE ( xplus1 ) == SUBREG ) xplus1 = SUBREG_REG ( xplus1 ) ; code1 = GET_CODE ( xplus1 ) ; if ( code0 == REG && iq2000_reg_mode_ok_for_base_p ( xplus0 , mode , strict ) ) { if ( code1 == CONST_INT && SMALL_INT ( xplus1 ) && SMALL_INT_UNSIGNED ( xplus1 ) ) return <NUM_LIT> ; } } if ( TARGET_DEBUG_A_MODE ) GO_PRINTF ( <STR_LIT> ) ; return <NUM_LIT>


<s> MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } if ( TCI . FrameConstructionID == MachineOutlinerTailCall || TCI . FrameConstructionID == MachineOutlinerThunk ) return ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MBB . insert ( MBB . end ( ) , ret ) ; if ( TCI . FrameConstructionID == MachineOutlinerNoLRSave ) return ; fixupPostOutline (


<s> return __builtin_arm_crypto_sha1su0 ( __w0_3 ,


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OS


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Equal ) ) return reportParseError ( <STR_LIT> ) ; Parser . Lex ( ) ; StringRef Arch ; if ( Parser . parseIdentifier ( Arch ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .

Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI -> getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI -> getObjectSize ( FrameIndex ) ; MFI -> setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front (


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue (


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns ,


<s> unsigned getExpandedImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { static_assert ( shift <= <NUM_LIT> , <STR_LIT> ) ; const MCOperand MO = MI . getOperand ( Op ) ; return ( invert ? ( MO . getImm ( ) ^ <NUM_LIT>


<s> switch ( getKind ( ) ) { case CEK_None : case CEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case CEK_CALL_HI16 : case


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lzcnt32 ( unsigned int __X ) { return __builtin_clz (


<s> bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < AllCRLogicalOps . size ( ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { if ( find_mem_ref ( XVECEXP ( pat , i , j ) , mem_ref )


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand (


<s> <ISA_LIT>ELFTargetObjectFile ( ) : TargetLoweringObjectFileELF ( )


<s> static void getPrePostIndexedMemOpInfo ( const MachineInstr & MI , int & Scale , int & MinOffset , int & MaxOffset ) { bool IsPaired = isPairedLdSt


<s> if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT == <STR_LIT> )


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> unsigned AX = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; unsigned SP = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; MachineInstr * ModInst = CI ; if ( STI . isTargetWin64 ( ) || ! STI . isOSWindows ( ) ) { ModInst = BuildMI ( MBB , MBBI , DL , TII . get ( getSUBrrOpcode ( Uses64BitFramePtr ) ) , SP ) . addReg ( SP ) . addReg ( AX ) ; } if ( InstrNum ) { if ( STI . isTargetWin64 ( ) || ! STI . isOSWindows ( ) ) { MF . makeDebugValueSubstitution ( * InstrNum , { ModInst -> getDebugInstrNum


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res ,


<s> if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return <NUM_LIT> ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI


<s> if ( Subtarget . hasVSX ( ) ) { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == &


<s> return ( STI . isTargetIOS ( ) && ! STI .


<s> Op -> SysCRImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation ::


<s> return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV32I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV64I8Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; default : llvm_unreachable ( <STR_LIT> )


<s> return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; return ; } else if ( DestReg == <STR_LIT> || SrcReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( SrcReg ) ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg


<s> unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && Imm -> getAPIntValue ( ) . getBitWidth ( ) == <NUM_LIT> && Imm -> getAPIntValue ( ) . isIntN ( <NUM_LIT> ) ) return false ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) && ( - Imm -> getAPIntValue ( ) ) . isSignedIntN ( <NUM_LIT> ) ) return false ; } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand (


<s> static bool aarch64_get_sve_pred_bits ( rtx_vector_builder & builder , rtx x ) { if ( GET_CODE ( x ) != CONST_VECTOR ) return false ; unsigned int factor = vector_element_size ( GET_MODE_NUNITS ( VNx16BImode ) , GET_MODE_NUNITS ( GET_MODE ( x ) ) ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( x


<s> return ST -> getMinVectorRegisterBitWidth (


<s> const SmallVectorImpl < MachineBasicBlock * > & getOrder ( ) const { return Order


<s> if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { EVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return false ; x0 = CONST_VECTOR_ELT ( x , <NUM_LIT> ) ; if ( ! CONST_DOUBLE_P ( x0 ) ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , x0 ) ; for ( i = <NUM_LIT> ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { xi = CONST_VECTOR_ELT ( x , i ) ; if ( ! CONST_DOUBLE_P ( xi ) ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( ri , xi ) ; if ( ! REAL_VALUES_EQUAL ( r0 , ri )


<s> CommuteVectorShuffleMask ( PermMask , <NUM_LIT> ) ; std :: swap ( V1 , V2 ) ; } unsigned HiIndex ; for ( HiIndex = <NUM_LIT> ; HiIndex < <NUM_LIT> ; ++ HiIndex ) { int Val = PermMask [ HiIndex ] ; if ( Val < <NUM_LIT> ) continue ; if ( Val >= <NUM_LIT> ) break ; } Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ^ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; if ( HiIndex >= <NUM_LIT> ) { Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } int LoMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int * MaskPtr = LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i


<s> if ( EltType == <STR_LIT> || EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> } <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; auto OpSize = N -> getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; unsigned Size = DAG . getDataLayout ( ) . getLargestLegalIntTypeSizeInBits ( ) ; if ( OpSize < Size ) { switch ( CC ) { default : break ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , false , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , true , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , true , DL , DAG ) ; case <STR_LIT>


<s> } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; Type * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits ( ) ) return false ; unsigned NumDstEls = DstTyL . first * DstTyL . second . getVectorNumElements ( ) ; unsigned NumSrcEls = SrcTyL . first * SrcTyL . second . getVectorNumElements ( ) ; return NumDstEls == NumSrcEls && <NUM_LIT> * SrcElTySize


<s> void <ISA_LIT>TargetStreamer :: emitRR ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitRX ( Opcode , Reg0 , MCOperand :: createReg ( Reg1 ) , IDLoc ,


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( unsigned


<s> WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , nullptr , - <NUM_LIT> , <NUM_LIT> ) ; auto it = CurFrame -> Instructions . begin ( ) ; CurFrame -> Instructions . insert ( it


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> bool AlwaysInstrument = Attr . isStringAttribute ( ) && Attr . getValueAsString ( ) == <STR_LIT> ; Sleds . emplace_back ( XRayFunctionEntry { Sled , CurrentFnSym


<s> V = peekThroughBitcasts ( V ) ; MVT NewVT = V . getSimpleValueType ( ) ; if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT>


<s> if ( Value != <NUM_LIT> && Value != <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Value == <NUM_LIT> ) { if ( ! isABI_O32 ( ) ) { reportParseError ( <STR_LIT> + Directive + <STR_LIT> ) ; return false ; } FpABI = <STR_LIT> :: S32 ; if ( ModuleLevelOptions ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; } else { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; } } else { FpABI = <STR_LIT> :: S64 ; if ( ModuleLevelOptions ) { clearModuleFeatureBits ( <STR_LIT> ,


<s> break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MinimizeSize ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlign ( ) < Align ( <NUM_LIT> ) ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; Register Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Register PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) if ( MO . getReg ( ) == BaseReg ) return false ; break ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT>


<s> unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( A_SD -> getFlags ( ) & SF_ThumbFunc ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( A_SD -> getFlags ( ) & SF_ThumbFunc ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( Fragment -> getParent


<s> if ( ! I -> empty ( ) && I -> back ( ) . getDesc ( ) . isReturn ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &= FoundIt ; } } if ( RemovedAllMTVRSAVEs ) { MBBI = MI


<s> return ( Candidate . isTerminator ( ) || Candidate . isCall ( ) || Candidate .

isPosition ( ) || Candidate . isInlineAsm ( ) || Candidate . hasUnmodeledSideEffects ( ) ) ;


<s> void resetUnwindDirectiveParserState ( ) { FnStartLoc = SMLoc ( ) ; CantUnwindLoc = SMLoc ( ) ; PersonalityLoc = SMLoc ( ) ; HandlerDataLoc = SMLoc ( ) ; FPReg = -


<s> assert ( OperandToFixup -> isReg ( ) && <STR_LIT> ) ; Register RegToFixup = OperandToFixup -> getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( RegToFixup , TRI ) << <STR_LIT> << * FixupLoc . InsertionPt ) ; unsigned Renamable = OperandToFixup -> isRenamable ( ) ? RegState :: Renamable : <NUM_LIT> ; BuildMI ( * FixupLoc . Block , FixupLoc . InsertionPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( RegToFixup , RegState :: Define | Renamable ) . addReg ( RegToFixup

, RegState :: Kill | Renamable ) . addReg ( RegToFixup , RegState :: Kill | Renamable ) . addImm ( ( uint64_t ) <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1


<s> if ( funcInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useFastISel ( ) ) return

new <ISA_LIT>FastISel ( funcInfo , libInfo ) ;


<s> return false ; } EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FormalArg . getArgNo ( ) << <STR_LIT> << ArgVT . getEVTString ( ) << <STR_LIT> ) ; if ( ! ArgVT . isSimple ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! FormalArg . hasAttribute ( Attribute :: SExt ) && ! FormalArg . hasAttribute ( Attribute :: ZExt ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextGPR32 == GPR32ArgRegs . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NextGPR32 << <STR_LIT> ) ; Allocation . emplace_back ( & <STR_LIT> , * NextGPR32 ++ ) ; NextFGR32 = FGR32ArgRegs . end ( ) ; NextAFGR64 = AFGR64ArgRegs . end ( ) ; break ; case <STR_LIT> : if ( FormalArg . hasAttribute ( Attribute :: ZExt ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextGPR32 == GPR32ArgRegs . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NextGPR32 << <STR_LIT> ) ; Allocation . emplace_back ( & <STR_LIT> , * NextGPR32 ++ ) ; NextFGR32 = FGR32ArgRegs . end ( ) ; NextAFGR64 = AFGR64ArgRegs . end ( ) ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextFGR32 == FGR32ArgRegs . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NextFGR32 << <STR_LIT> ) ; Allocation . emplace_back ( & <STR_LIT> , * NextFGR32 ++ ) ; if ( NextGPR32 != GPR32ArgRegs . end ( ) ) NextGPR32 ++ ; if ( NextAFGR64 != AFGR64ArgRegs . end ( ) ) NextAFGR64 ++ ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextAFGR64 == AFGR64ArgRegs .


<s> const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_ABIFLAGS , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCSectionData & ABIShndxSD = MCA . getOrCreateSectionData ( * Sec ) ; ABIShndxSD . setAlignment


<s> unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; unsigned OfstFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , GOTFlag ) ; JTI = DAG . getNode ( <STR_LIT> , dl , PtrVT , GetGlobalReg ( DAG , PtrVT ) , JTI ) ; HiPart = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false


<s> assert ( ( Subtarget -> hasSSE42 ( ) || Subtarget -> hasAVX ( ) ) && <STR_LIT> ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned Opc ; if ( ! Subtarget -> hasAVX ( ) ) { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> :


<s> static int matchShuffleAsElementRotate ( SDValue & V1 , SDValue & V2 , ArrayRef < int > Mask ) { int NumElts = Mask . size ( ) ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { int M = Mask [ i ] ; assert ( ( M == SM_SentinelUndef || ( <NUM_LIT> <= M && M < ( <NUM_LIT> * NumElts ) ) ) && <STR_LIT> ) ; if ( M < <NUM_LIT> ) continue ; int StartIdx = i - ( M % NumElts ) ; if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements

( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { Register Reg = MO . getReg ( ) ; assert ( Register :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { O << MO . getImm ( ) ; break ; } case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; break ; } case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm1 ( SDValue N , SDValue & Imm ) const { llvm_unreachable (


<s> if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv ::

AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ;


<s> if ( ! isSingleSpacedVectorIndexed ( ) )


<s> unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockLogAlignment = NextBlock -> getLogAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size ; if ( CPEEnd


<s> return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > (


<s> return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSelectCCCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI -> CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; SDValue InArgsAddr = DAG . getFrameIndex ( FI , ValTy ) ; return DAG . getNode ( <STR_LIT> , Op -> getDebugLoc ( ) , ValTy

, InArgsAddr , DAG . getConstant ( <NUM_LIT> , ValTy ) ) ;


<s> assert ( ( VT . is128BitVector ( ) && ( VT . getScalarSizeInBits ( ) == <NUM_LIT> || VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) != N1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue WideVec = N0 . getOperand ( <NUM_LIT> ) ; MVT WideVT = WideVec . getSimpleValueType ( ) ; if ( ! WideVT . is256BitVector ( ) || ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; const APInt & ExtIndex0 = N0

. getConstantOperandAPInt ( <NUM_LIT> ) ;


<s> auto isTailCallableCC = [ ] ( CallingConv :: ID CC ) { return CC == CallingConv :: C || CC == CallingConv :: Fast ; } ; if ( ! isTailCallableCC ( CallerCC ) || ! isTailCallableCC ( CalleeCC


<s> MachineInstr * MI = MBBI ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; if ( ! TII -> isCandidateToMergeOrPair ( MI ) ) return false ; bool IsUnscaled = TII -> isUnscaledLdSt ( MI ) ; int Offset = getLdStOffsetOp ( MI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? getMemScale ( MI ) : <NUM_LIT> ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit , false ) ; if ( Paired != E


<s> bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ; return Changed | fixBackwardsWLS


<s> reg = gen_rtx_REG ( mode , regno ) ; insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp


<s> if ( parms -> intoffset != - <NUM_LIT> ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms -> intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = parms -> slotno + parms -> intoffset / BITS_PER_WORD ; if ( intslots > <NUM_LIT> && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( <NUM_LIT> , SPARC_INT_ARG_MAX - this_slotno ) ; parms -> stack = <NUM_LIT> ; } parms -> nregs += intslots ; parms -> intoffset = - <NUM_LIT> ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && DECL_MODE ( field ) == BLKmode ) parms -> nregs += TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) parms -> nregs += <NUM_LIT> ; else parms -> nregs += <NUM_LIT> ; } else { if ( parms -> intoffset == - <NUM_LIT> ) parms -> intoffset


<s> const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; uint32_t Sz = Subtarget . isTargetXPLINK64 ( ) ? getTargetMachine ( )

. getPointerSize ( <NUM_LIT> ) : <NUM_LIT> ;


<s> if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( )

, SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> term = XEXP ( x , <NUM_LIT> ) ; if ( has_hard_reg_initial_val ( Pmode , TP_REGNO ) && base == mep_tp_rtx ( ) ) unspec = UNS_TPREL ; else if ( has_hard_reg_initial_val ( Pmode , GP_REGNO ) && base == mep_gp_rtx ( ) ) unspec = UNS_GPREL ; else return x ; if ( GET_CODE ( term ) != CONST ) return x ; term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || XINT ( term , <NUM_LIT> ) != unspec ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT>


<s> m_MergedLocalSymbols . clear ( ) ; m_MergedGlobalSymbols . clear ( ) ; size_t uniqueCount = <NUM_LIT> ; for ( SymbolUniqueMapType :: const_iterator it = m_InputGlobalSymbols . begin ( ) , end = m_InputGlobalSymbols . end ( ) ; it != end ; ++ it ) { if ( it -> second ) ++ uniqueCount ; } m_MultipartList . back ( ) . m_LocalNum -= m_InputLocalSymbols . size (


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) *


<s> return ; } MCSymbolData * SD = <NUM_LIT> ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = RelocType ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset


<s> static bool isFPR64 ( unsigned Reg , unsigned SubReg , const MachineRegisterInfo * MRI ) { if ( Register :: isVirtualRegister ( Reg ) ) return ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <NUM_LIT> ) || ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT>


<s> if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i32scatter_ps ( void * addr , __mmask16

mask , __m512i index , int scale , int hint ) {


<s> emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = <NUM_LIT> ; break ; case CX_REG : opcode = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } else opcode = <NUM_LIT> ; if ( need_endbr ) { mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; offset += <NUM_LIT> ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , QImode ) ) ; mem = adjust_address ( m_tramp , SImode ,


<s> switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) ->


<s> if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128BRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128HRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128WRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128DRegisterClass ; } else llvm_unreachable ( <STR_LIT> ) ; assert ( NSize != <NUM_LIT> && RegDecoder != nullptr ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , NSize ) ; MI . addOperand ( MCOperand :: CreateImm ( tmp ) ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) ==


<s> ExtractValueInst * EI = cast < ExtractValueInst > ( I ) ; Value * Agg = EI -> getAggregateOperand ( ) ; if ( IntrinsicInst * CI = dyn_cast < IntrinsicInst > ( Agg ) ) { switch ( CI ->


<s> unsigned Opc ; unsigned LSB , MSB ; SDValue Opd0 , Opd1 ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; APInt NUsefulBits ; getUsefulBits ( SDValue ( N , <NUM_LIT> ) , NUsefulBits ) ; if ( ! NUsefulBits ) return CurDAG -> SelectNodeTo ( N , TargetOpcode :: IMPLICIT_DEF , VT ) ; if ( ! isBitfieldInsertOpFromOr ( N , Opc , Opd0 , Opd1 , LSB , MSB , NUsefulBits , CurDAG )


<s> static MachineBasicBlock * splitBlockBefore ( MachineInstr * MI , MachineBasicBlock * MBB ) { MachineBasicBlock * NewMBB = emitBlockAfter ( MBB ) ; NewMBB -> splice ( NewMBB -> begin ( ) , MBB , MI , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( <NUM_LIT> , rs6000_elf_output_toc_section_asm_op ,


<s> DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( isVSFRCRegClass ( RC ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .


<s> assert ( ! isPreOp ( AluOp ) && <STR_LIT> ) ; return AluOp


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNShuffle = [ & ] ( ShuffleVectorSDNode * SVN , bool Rev ) { ArrayRef < int > M = SVN -> getMask ( ) ; unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( SVN -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) NumElts /= <NUM_LIT> ; unsigned Off0 = Rev ? NumElts : <NUM_LIT> ; unsigned Off1 = Rev ? <NUM_LIT> : NumElts ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; I += <NUM_LIT> ) { if ( M [ I ] >= <NUM_LIT> && M [ I ] != ( int ) ( Off0 + I / <NUM_LIT> ) ) return false ; if ( M [ I + <NUM_LIT> ] >= <NUM_LIT> && M [ I + <NUM_LIT> ] != ( int ) ( Off1 + I / <NUM_LIT> ) ) return false ; } return true ; } ; if ( Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( SDValue U = PerformVQDMULHCombine ( Trunc . getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ) { DAG . ReplaceAllUsesWith ( Trunc . getOperand ( <NUM_LIT> ) , U ) ; return SDValue ( ) ; } } if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc . getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNShuffle ( Shuffle , false ) || isVMOVNShuffle ( Shuffle , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> >


<s> ev32 = __ev_create_s64 ( a ) ; __ev_mra (


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Check ( S , DecodeGPRwithZRRegisterClass ( Inst , RegNo , Address ,


<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) computed = MIN ( computed , <NUM_LIT> ) ; return computed


<s> return ( __mmask32 ) __builtin_ia32_ucmpw512_mask ( ( __v32hi ) __A ,


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , <STR_LIT> ) ; SDValue EndDest = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Dest , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest ,


<s> mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0 , perm2 , <NUM_LIT> ) ; gcc_assert ( ok ) ; ok = expand_vselect ( t1 , d -> op1 , perm2 , <NUM_LIT> ) ; gcc_assert ( ok ) ; x = gen_rtx_AND ( V4HImode , mask , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( V4HImode , mask


<s> MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = loongarch_force_binary ( Pmode , AND , orig_addr , GEN_INT ( <NUM_LIT> ) ) ; loongarch_emit_binary ( ASHIFT , shift , shift , GEN_INT ( <NUM_LIT> ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = loongarch_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = loongarch_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = loongarch_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_7 ( res , memsi , mask , inverted_mask , oldval , newval , model ) ; else if ( result ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , model ) ; else si_op = generator . fn_5 ( memsi , mask , inverted_mask , oldval , model ) ; emit_insn ( si_op ) ; if ( result ) { loongarch_emit_binary ( AND , res , res , mask ) ; loongarch_emit_binary ( LSHIFTRT , res , res , shiftsi


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE -> getValue (


<s> static void mips_emit_unary ( enum rtx_code code , rtx target , rtx


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { switch ( Opc ) { case <STR_LIT> : return ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT>


<s> static SDValue combineMulToPMADDWD ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( Subtarget . isPMADDWDSlow ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( WVT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( N1 ) < <NUM_LIT> || DAG . ComputeNumSignBits ( N0 ) < <NUM_LIT> ) return SDValue ( ) ; auto GetZeroableOp = [ & ] ( SDValue Op ) { APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( Op , Mask17 ) ) return Op ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getSizeInBits ( ) <= <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ; if ( ! ZeroN0 && ! ZeroN1 ) return SDValue ( ) ; N0 = ZeroN0 ? ZeroN0 : N0 ; N1 = ZeroN1 ?


<s> __builtin_aarch64_st1v8qi ( ( __builtin_aarch64_simd_qi *


<s> case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; if ( ! MI )


<s> unsigned getT2AdrLabelOpValue ( const MachineInstr & MI


<s> virtual const <ISA_LIT>Subtarget * getSubtarget


<s> std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) { if ( getRelocationModel ( ) == Reloc


<s> new <ISA_LIT>TargetELFStreamer ( * S ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( ) .


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void )


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode


<s> bool <STR_LIT> ( int64_t Offset , CodeModel :: Model M , bool hasSymbolicDisplacement ) { if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; if ( ! hasSymbolicDisplacement ) return true ; if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ; if ( M == CodeModel :: Small && Offset < <NUM_LIT> * <NUM_LIT>


<s> static void mips_multi_set_operand ( unsigned int i , unsigned int op , rtx x ) { mips_multi_members [ i ] . operands [ op ] =


<s> else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; bool retval = false ; for ( int i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( ! MEM_P ( SET_DEST ( set ) ) ) retval = true ; else return false ; } if ( set == NULL_RTX && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return false ; } if ( retval ) return true ; else if ( code == JUMP_INSN ) return false ; } rtx set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return ! MEM_P ( SET_DEST ( set ) ) ; if ( set == NULL && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) )


<s> case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefMI . print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; NewCmp = convertToFlagSetting ( DefMI , IsFlagSetting ) ; NewBr = convertToCondBr ( MI ) ; break ; } } break ; } ( void ) NewCmp ; ( void ) NewBr ; assert ( NewCmp && NewBr && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( NewCmp -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( NewBr -> print ( dbgs ( ) ) ) ; if ( ! IsFlagSetting ) DefMI . eraseFromParent ( ) ; MI . eraseFromParent ( ) ; return


<s> Function * MCR = <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ; }


<s> if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) , addr ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; addr = SET_SRC ( set ) ; return memory_address_length ( addr , true ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { constrain_operands_cached ( insn , reload_completed ) ; if ( which_alternative != - <NUM_LIT> ) { const char * constraints = recog_data . constraints [ i


<s> static unsigned getExtFactor ( SDValue & V ) { EVT EltType = V . getValueType ( ) . getVectorElementType ( ) ; return EltType . getSizeInBits (


<s> return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr )


<s> int64_t Imm = ShiftExtend . Amount / <NUM_LIT> - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm )


<s> static int rs6000_clone_priority ( tree fndecl ) { tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; HOST_WIDE_INT isa_masks ; int ret = CLONE_DEFAULT ; tree attrs = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; const char * attrs_str = NULL ; attrs = TREE_VALUE ( TREE_VALUE ( attrs ) ) ; attrs_str = TREE_STRING_POINTER ( attrs ) ; if ( strcmp ( attrs_str , <STR_LIT> ) != <NUM_LIT> ) { if ( fn_opts == NULL_TREE ) fn_opts = target_option_default_node ; if ( ! fn_opts || ! TREE_TARGET_OPTION ( fn_opts ) )


<s> unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned UBFMOpc = BitWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * ShiftNode ; if ( ShlAmount > <NUM_LIT> ) { ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , dl , VT , Op , CurDAG -> getTargetConstant ( BitWidth - ShlAmount , dl , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> - ShlAmount , dl , VT ) ) ; } else { assert ( ShlAmount < <NUM_LIT> && <STR_LIT> ) ; int ShrAmount = - ShlAmount ; ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , dl , VT , Op , CurDAG -> getTargetConstant ( ShrAmount , dl , VT ) , CurDAG ->

getTargetConstant ( BitWidth - <NUM_LIT> , dl , VT ) ) ;


<s> begin = mips_force_binary ( Pmode , AND , begin , mask ) ; length = mips_force_binary ( Pmode , MINUS , end , begin ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; emit_insn ( gen_synci ( begin ) ) ; mips_emit_binary ( MINUS , length , length , inc ) ; mips_emit_binary ( PLUS , begin , begin


<s> AU . addRequired < TargetPassConfig > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU )


<s> static SDValue combineANDXORWithAllOnesIntoANDNP ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) && ! VT

. is512BitVector ( ) ) return SDValue ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return


<s> return __builtin_aarch64_sqdmlalv4hi ( __a ,


<s> float16x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8hf ( __a ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregxiv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregxiv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregxiv8hf ( __o ,


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR1 ( ( v8qi ) mm , ( v8qi )


<s> if ( TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) return true ; if ( DEFAULT_ABI == ABI_V4 && ( flag_pic == <NUM_LIT> || ( flag_pic && TARGET_SECURE_PLT ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) return true ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic && crtl -> uses_pic_offset_table ) return true ; } return ! call_used_regs [ reg ] && df_regs_ever_live_p


<s> if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < <NUM_LIT> || DataSize > <NUM_LIT> || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == <NUM_LIT> ) return ST -> hasAVX ( ) ; else if ( DataSize == <NUM_LIT> ) return


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO .


<s> case <STR_LIT> : return lowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerADD (


<s> while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . isNot ( AsmToken :: Comma


<s> const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( const BasicBlock * SuccBB : IB -> successors ( ) ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ SuccBB ] ) ; return true


<s> Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount *


<s> return ( int16x4_t ) __builtin_neon_vqrshrns_nv4si ( __a ,


<s> if ( ! TARGET_SSE2 ) return - <NUM_LIT> ; if ( ! TARGET_AVX ) return <NUM_LIT> ; return TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; case 'c' : if ( ! TARGET_AVX ) return - <NUM_LIT> ; return TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - <NUM_LIT> ; return <NUM_LIT> ; default : gcc_unreachable ( )


<s> else if ( Layout . size ( ) == <NUM_LIT> ) IsVector = false ; if ( ! IsVector ) Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( )


<s> unsigned getImmMinusOneOpValue ( const MachineInstr &


<s> Value * <ISA_LIT>IREmitter :: visitVLD4DUP ( const SDNode


<s> void printf256mem ( const MCInst * MI , unsigned OpNo ,


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT>


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Byte , SDValue Size , unsigned Align , bool IsVolatile , MachinePointerInfo DstPtrInfo ) const { EVT PtrVT = Dst . getValueType ( ) ; if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes == <NUM_LIT> ) return SDValue ( ) ; if ( ConstantSDNode * CByte = dyn_cast < ConstantSDNode > ( Byte ) ) { uint64_t ByteVal = CByte -> getZExtValue ( ) ; if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && CountPopulation_64 ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Align , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst ,

DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;


<s> vmull_n_u16 ( uint16x4_t a , uint16_t b ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; } CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It ,


<s> rtx op0 = expand_normal ( arg0 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( TARGET_32BIT ) fatal_error ( input_location , <STR_LIT> <STR_LIT> ) ; if ( rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( CONST_INT_P ( op0 ) && ! const_0_to_7_operand ( op0 , VOIDmode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) (


<s> static __inline double spu_extract ( vec_double2 a , int element ) { union { vec_double2 v ; double d [ <NUM_LIT> ] ; } in


<s> StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . getTypeAction ( * DAG . getContext ( ) , StoreVT ) != TargetLowering :: TypeWidenVector ) return SDValue ( ) ; MVT WideVT = <STR_LIT> ( StoreVT . getVectorElementType ( ) , StoreVT . getVectorNumElements ( ) * <NUM_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2


<s> static __inline qword si_rot ( qword a


<s> if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) EFlags |= ELF :: EF_MIPS_MICROMIPS ; if ( Subtarget . isABI_O32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; Reloc :: Model RM = Subtarget . getRelocationModel ( ) ; if ( RM == Reloc :: PIC_ || RM == Reloc :: Default ) EFlags |= ELF :: EF_MIPS_PIC ; else if ( RM == Reloc :: Static ) ; else llvm_unreachable ( <STR_LIT> ) ; MCA . setELFHeaderEFlags (


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget

( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> return helper_sign_extend ( ( ( ( pValue >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( pValue >> <NUM_LIT> ) & <NUM_LIT> )

| ( ( pValue >> <NUM_LIT> ) & <NUM_LIT> ) | ( pValue & <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> static void rs6000_live_on_entry ( bitmap


<s> SmallVectorImpl < MachineInstr * > & Insts = Block . getInsts ( ) ; return isPredicatedOnVCTP ( Insts . front ( )


<s> return ( __m128i ) __builtin_ia32_movdqa64load128_mask ( ( __v2di * ) __P ,


<s> MachineBasicBlock :: iterator FrameSetup = Context . FrameSetup ; MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; DebugLoc DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; MachineOperand PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( TRC ) ; else return TRC -> contains


<s> case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; ScratchTy = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( ScratchTy ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewVal = MI . getOperand ( <NUM_LIT> )


<s> assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( MOSrc0 ) -- NumNewCopies ; if ( MOSrc0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) ++ NumRemovableCopies ; } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( MOSrc1 ) -- NumNewCopies ; if ( MOSrc1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) ++ NumRemovableCopies ; } unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool AllUsesAreCopies = true ; for ( MachineRegisterInfo :: use_instr_nodbg_iterator Use = MRI -> use_instr_nodbg_begin ( Dst ) , E = MRI -> use_instr_nodbg_end ( ) ; Use != E ; ++ Use ) { unsigned SubReg ; if ( getSrcFromCopy ( & * Use , MRI , SubReg ) || isTransformable ( & * Use ) ) ++ NumRemovableCopies ; else if ( Use -> getOpcode ( ) == <STR_LIT> || Use -> getOpcode ( ) == <STR_LIT> ) ; else AllUsesAreCopies


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op .


<s> getStreamer ( ) . EmitCFIBKeyFrame ( ) ; return


<s> void DecodeScalarMoveMask ( MVT VT , bool IsLoad , SmallVectorImpl < int > & Mask ) { unsigned NumElts = VT . getVectorNumElements (


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP


<s> int __init_environment ( void * unused __attribute__ ( ( __unused__ ) ) ) { void ( * const * pctor ) ( void ) ; static struct


<s> return ( __m128i ) __builtin_ia32_pmovzxwq128 ( ( __v8hi


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr


<s> if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) && ! Subtarget . isUsingPCRelativeCalls ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 (


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> for ( MachineInstr & MI : * MBB ) { if ( MI . isReturn ( ) && ! MI . isCall ( ) ) { VisitedBBs [ MBB ] = VisitedBBInfo ( true , CyclesToEnd ) ; Cycles += CyclesToEnd ; return true ; } CyclesToEnd += TSM . computeInstrLatency ( & MI ) ; } VisitedBBs [ MBB ] = VisitedBBInfo ( false , CyclesToEnd ) ; Cycles += CyclesToEnd


<s> gcc_assert ( reload_completed ) ; if ( ! offsettable_memref_p ( mem ) ) return <NUM_LIT> ; if ( ( REGNO ( reg ) % <NUM_LIT> ) == <NUM_LIT> && mem_min_alignment ( mem , <NUM_LIT> ) ) return <NUM_LIT> ; return


<s> if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty ,


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { assert ( GISel && <STR_LIT> ) ; return GISel -> getRegBankInfo


<s> SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT>


<s> return MLxHazardOpcodes . count ( Opcode


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm


<s> if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ( ImmediateOffsetNeedsLowering || Addr . getOffsetReg ( ) ) && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , true ) ; else if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , false ) ; else ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) ) ; } if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffsetReg ( <NUM_LIT> ) ; Addr . setShift ( <NUM_LIT> ) ; Addr . setExtendType ( <STR_LIT> ) ; } if ( ImmediateOffsetNeedsLowering ) { unsigned ResultReg ; if ( Addr . getReg ( ) ) ResultReg = emitAdd_ri_ ( <STR_LIT> , Addr . getReg ( ) , false , Offset ) ; else ResultReg = fastEmit_i ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Offset ) ; if ( ! ResultReg


<s> const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( hasGOT ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) .


<s> } for ( MachineBasicBlock :: iterator Iter = MI ; Iter != ME ; Iter ++ ) { MachineInstr & PHIInst = * Iter ; for ( unsigned i = <NUM_LIT> , e = PHIInst . getNumOperands ( ) + <NUM_LIT> ; i != e ; i += <NUM_LIT> ) { MachineOperand & MO = PHIInst . getOperand ( i ) ; if ( MO . getMBB ( ) ==


<s> if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; else return ( STI . isTargetIOS ( ) && ! STI .


<s> if ( ( Subtarget . hasVLX ( ) && Subtarget . hasBWI ( ) && Subtarget . hasDQI ( ) ) || NumElts == <NUM_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , MemVT , Op ) ; if ( MemVT . getSizeInBits ( ) < <NUM_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , Op , St -> getBasePtr ( ) , St -> getMemOperand ( ) ) ; } if ( NumElts <= <NUM_LIT> ) { if ( NumElts < <NUM_LIT> ) { MVT ExtVT = <STR_LIT> ( OpVT . getScalarType ( ) , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , ExtVT , DAG . getUNDEF ( ExtVT ) , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return DAG . getStore ( St -> getChain ( ) , dl , Op


<s> } else if ( ashiftrt_insns [ INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ] > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ) { rtx count = force_reg ( SImode , GEN_INT ( - ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ) ) ; emit_insn ( gen_ashrsi3_d ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , count ) ) ; return <NUM_LIT> ; } } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) return <NUM_LIT> ; value = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( value == <NUM_LIT> ) { if ( currently_expanding_to_rtl ) { emit_insn ( gen_cmpgtsi_t ( force_reg ( SImode , CONST0_RTX ( SImode ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_mov_neg_si_t ( operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } emit_insn ( gen_ashrsi2_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } else if ( value >= <NUM_LIT> && value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseSetEndImm ( OperandVector & Operands ) { const AsmToken & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == -


<s> HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX =


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand ::


<s> if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; const MCInstrDesc & UseMCID = UseMI -> getDesc ( ) ; if ( UseMCID . isPseudo ( ) ) return false ; unsigned UseIdx ; for ( UseIdx = <NUM_LIT> ; UseIdx < UseMI -> getNumOperands ( ) ; ++ UseIdx ) if ( UseMI -> getOperand ( UseIdx ) . isReg ( ) && UseMI -> getOperand ( UseIdx ) . getReg ( ) == Reg ) break ; assert ( UseIdx < UseMI -> getNumOperands ( ) && <STR_LIT> ) ; assert ( UseIdx < UseMCID . getNumOperands ( ) && <STR_LIT> ) ; const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI -> getOperand ( UseIdx ) . setReg ( ZeroReg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , { Chain , SymAddr } ) ; SDValue Glue = Chain .


<s> if ( ( mode == V2DImode || mode == V1TImode ) && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> ) return <STR_LIT> ; } if ( TARGET_ALTIVEC ) { rtx splat_vec ; if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; splat_vec = gen_easy_altivec_constant ( vec ) ; gcc_assert ( GET_CODE ( splat_vec ) == VEC_DUPLICATE ) ; operands [ <NUM_LIT> ] = XEXP ( splat_vec , <NUM_LIT> ) ; if ( ! EASY_VECTOR_15 ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) return <STR_LIT> ; switch ( GET_MODE ( splat_vec ) ) { case V4SImode : return <STR_LIT> ; case V8HImode : return <STR_LIT> ; case V16QImode : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } gcc_assert ( TARGET_SPE ) ; cst = INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) ; cst2 = INTVAL ( CONST_VECTOR_ELT (


<s> if ( TyAlign > <NUM_LIT> ) return TyAlign ; return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; Name = StringSwitch < StringRef > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Name ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && Parser . getTok ( ) . getIdentifier ( ) == <STR_LIT> ) { parseDirectiveReq ( Name , NameLoc ) ; return true ; } size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) { bool IsError = parseSysAlias ( Head , NameLoc , Operands ) ; if ( IsError && getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) Parser . eatToEndOfStatement ( ) ; return IsError ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + (


<s> addPass ( create<ISA_LIT>OptimizePICCallPass ( get<ISA_LIT>TargetMachine ( ) )


<s> return CurDAG -> getTargetConstant ( Imm