<s> LoadI -> eraseFromParent ( ) ; return NextI ; } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } StoreI -> clearRegisterKills ( StRt , TRI ) ; ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs (


<s> if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0


<s> return m_HasNonPICBranchSyms . count


<s> unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) .


<s> static machine_mode mips_preferred_simd_mode ( machine_mode mode ATTRIBUTE_UNUSED ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode


<s> if ( AFI -> isThumb2Function ( ) && MFI . hasVarSizedObjects ( ) && MFI . getLocalFrameSize ( ) >= <NUM_LIT> ) return true ; if ( AFI -> isThumb1OnlyFunction ( ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; return


<s> } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , MCFixupKind ( <STR_LIT> ) , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg == <NUM_LIT> ) { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , <NUM_LIT> , CurByte , OS ) ; } else { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , Get<ISA_LIT>RegNum ( Base ) , CurByte , OS ) ; } if ( ForceDisp8 ) EmitImmediate ( Disp , <NUM_LIT>


<s> addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; ShouldPrint = true ; } if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( create<ISA_LIT>NaClRewritePass ( ) ) ; ShouldPrint = true


<s> static bool mips_near_type_p ( const_tree type ) { return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) )


<s> emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_e ( code , GET_MODE ( op0 ) , op0 )


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , StringRef FS ) { bool VectorABI = UsesVectorABI ( CPU , FS ) ; std :: string Ret = <STR_LIT> ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( VectorABI ) Ret +=


<s> GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt , SeqLs ) ; AddInstr ( SeqLs , Inst ( SHL , Shamt )


<s> static void get_pc_thunk_name ( char name [ <NUM_LIT> ]


<s> static DecodeStatus DecodeSImm8OptLslByte ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { signed Val = ( int8_t ) Imm ; if ( Imm & <NUM_LIT> )


<s> if ( ! printAliasInstr ( MI , Address , STI , OS ) ) printInstruction ( MI , Address


<s> return __builtin_aarch64_ld1v8hf ( __a )


<s> if ( StackTaggingMergeSetTag ) for ( auto & BB : MF ) for ( MachineBasicBlock :: iterator II = BB . begin ( ) ; II != BB . end ( ) ; )

II = tryMergeAdjacentSTG ( II , this , RS ) ;


<s> static DecodeStatus DecodeThumbCPS ( MCInst & Inst , uint16_t Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | <NUM_LIT> ; unsigned flags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( flags ) ) ; return MCDisassembler ::


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_CCRXI16_ins ( unsigned SltiOpc , unsigned SltiXOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get

( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_pshufd ( ( __v4si


<s> SDValue C = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDNodeFlags Flags = N -> getFlags ( ) ; if ( ! IsStrict && Flags . hasAllowReassociation ( ) && TLI . isOperationExpand ( <STR_LIT> , VT ) ) { SDValue Fmul = DAG . getNode ( <STR_LIT> , dl , VT , A , B , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fmul , C , Flags ) ; } EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) && ! ( ScalarVT == <STR_LIT> && Subtarget . hasFP16 ( ) ) ) return SDValue ( ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ) { V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V


<s> bool <ISA_LIT>InstructionSelector :: insertComparison ( CmpConstants Helper , InsertInfo I , unsigned ResReg , <STR_LIT> Cond , unsigned LHSReg , unsigned RHSReg , unsigned PrevRes ) const { auto CmpI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ComparisonOpcode ) ) . addUse ( LHSReg ) . addUse ( RHSReg ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; if ( Helper . ReadFlagsOpcode != <STR_LIT> ) { auto ReadI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII .

get ( Helper . ReadFlagsOpcode ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> return ( int64x1_t ) { __builtin_aarch64_sqabsdi (


<s> bool <ISA_LIT>InstrInfo :: isLdStPairSuppressed ( const MachineInstr * MI ) const { static_assert ( MOSuppressPair < ( <NUM_LIT> << MachineMemOperand :: MOTargetNumBits ) , <STR_LIT> ) ; for ( auto * MM : MI -> memoperands ( ) ) { if ( MM -> getFlags ( ) &

( MOSuppressPair << MachineMemOperand :: MOTargetStartBit ) ) {


<s> if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return


<s> unsigned load = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return


<s> if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( F -> hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true


<s> for ( int reg = FIRST_LO_REGNUM ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( ! callee_saved_reg_p ( reg ) && ! REGNO_REG_SET_P ( prologue_live_out , reg ) ) mask |= <NUM_LIT> << ( reg - FIRST_LO_REGNUM ) ; return mask


<s> if ( ! getLexer ( ) . is ( AsmToken :: Minus ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; SMLoc End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; const MCExpr * RndModeOp = MCConstantExpr :: create ( rndMode , Parser . getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( RndModeOp , Start , End ) ) ; return false ; } if ( Tok . getIdentifier ( ) . equals ( <STR_LIT> ) ) { Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumedToken )


<s> return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID ,


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( )

) return getMachineOpValue ( MI , MO , Fixups , STI ) ;


<s> for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty ,


<s> if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) , <NUM_LIT> ) ; return


<s> virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const { const MCSectionELF & ES = static_cast < const MCSectionELF


<s> } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI .


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand (


<s> int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( Scale == <NUM_LIT> || ( AM . HasBaseReg && Scale == - <NUM_LIT> ) ) return true ; if ( ! AM . HasBaseReg && Scale == <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> )


<s> static bool matchLogicBlend ( SDNode * N , SDValue & X , SDValue & Y , SDValue & Mask ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand


<s> unsigned <ISA_LIT>_64TargetMachine :: getJITMatchQuality ( ) { return <NUM_LIT> ; return


<s> static inline unsigned getT1Imm6 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) <<

<NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT>


<s> Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , InFlag , dl ) ; InFlag = Chain . getValue ( <NUM_LIT> )


<s> if ( CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 || CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext ) return SDValue ( ) ; bool IsRHSZero = RHSValue == <NUM_LIT> ; bool IsRHSOne = RHSValue == <NUM_LIT> ; bool IsRHSNegOne = RHSValue == - <NUM_LIT> ; switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue AddInput = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Addic = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , AddInput , S -> getI32Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addic , Addic , Addic . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue SC = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Xor , S -> getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SC , SC , SC . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { if ( IsRHSZero ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GESExt ) ; std :: swap ( LHS , RHS ) ; ConstantSDNode * RHSConst = dyn_cast < ConstantSDNode > ( RHS ) ; IsRHSZero = RHSConst && RHSConst -> isZero ( ) ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { if ( IsRHSZero ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: LESExt ) ; SDValue ShiftR = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , RHS , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue ShiftL = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue SubtractCarry = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Adde = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , ShiftR , ShiftL , SubtractCarry ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Adde ) , <NUM_LIT> ) ; } case <STR_LIT> : { if ( IsRHSNegOne ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GESExt ) ; if ( IsRHSZero ) { SDValue Add = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( - <NUM_LIT> , dl ) )


<s> return __extension__ ( __m128i ) ( __v2di )


<s> return false ; case <STR_LIT> : { Type * RetTy = II -> getCalledFunction ( ) -> getReturnType ( ) ; MVT VT ; if ( ! isTypeSupported ( RetTy , VT ) ) return false ; unsigned SrcReg = getRegForValue ( II -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; if ( DestReg == <NUM_LIT> ) return false ; if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( II , DestReg ) ; return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } } else if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg


<s> rtx call , use = NULL ; if ( flag_pic && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( fnaddr , <NUM_LIT> ) ) ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; rtx hard_pic = gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) ; emit_move_insn ( hard_pic , pic_offset_table_rtx ) ; use_reg ( & use , hard_pic ) ; } if ( ! call_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , Pmode ) ) { fnaddr = copy_to_mode_reg ( Pmode , XEXP ( fnaddr , <NUM_LIT> ) ) ; fnaddr = gen_rtx_MEM ( SImode , fnaddr ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! sibcall ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , call , clob ) ) ; } call = emit_call_insn (


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken ::


<s> JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( LazyPtr - ( Addr + <NUM_LIT> + <NUM_LIT> ) ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( ( void * ) Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } else { JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( ( void * ) Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( ( void * ) Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } } else { JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( ( void * )


<s> if ( isMemoryOp ( * MBBI ) ) { unsigned Opcode = MBBI -> getOpcode ( ) ; const MachineOperand & MO = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned Base = getLoadStoreBaseOp ( * MBBI ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MBBI , PredReg ) ; int Offset = getMemoryOpOffset ( * MBBI ) ; if ( CurrBase == <NUM_LIT> ) { CurrBase = Base ; CurrOpc = Opcode ; CurrPred = Pred ; MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { bool Overlap = false ; if ( isLoadSingle ( Opcode ) ) { Overlap = ( Base == Reg ) ; if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI


<s> return ( uint8x8_t ) __builtin_neon_vhsubuv8qi ( ( int8x8_t )


<s> return MF . getFrameInfo ( ) . hasStackObjects ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences


<s> tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_extract ( true , target , op0 , elt ) ; return


<s> const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: Create ( Mang -> getSymbol ( GV ) , ( Subtarget -> isTargetDarwin ( ) ? MCSymbolRefExpr :: VK_None :

MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ;


<s> return __builtin_mve_vqrshrntq_n_sv8hi ( __a ,


<s> return ( __m128i ) __builtin_ia32_psrldqi128 ( __A ,


<s> return ( __m256 ) __builtin_ia32_extractf32x8_mask ( ( __v16sf ) __A , __imm , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 )


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv8hi ( ( int16x8_t )


<s> if ( ! isImmWithLSL ( ) ) return false ; if ( ImmWithLSL . ShiftAmount % <NUM_LIT> != <NUM_LIT> ) return false ; if ( ImmWithLSL . ShiftAmount >= RegWidth ) return false ; <ISA_LIT>MCExpr :: VariantKind Modifier ; if ( isNonConstantExpr ( ImmWithLSL . Val , Modifier )


<s> bool i386_pe_type_dllexport_p ( tree decl ATTRIBUTE_UNUSED


<s> void addKind ( <STR_LIT> Value ) { AlignBranchKind |=


<s> unsigned TargetAlign = Target . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~ AlignMask ; return NumBytes


<s> static __inline qword si_fnms ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_nmsub ( ( vec_float4 ) ( a ) , ( vec_float4 ) (


<s> for ( int M : Mask ) if ( ! isUndefOrInRange ( M , Low


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return

parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ;


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( )


<s> EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk


<s> if ( PersonalityIndex < NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 ,


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM , createTLOF ( TM ) ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 (


<s> case ESize8 : return ( insn >> <NUM_LIT> ) & <NUM_LIT> ; case ESize16 : return ( insn >> <NUM_LIT> )


<s> if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ; if ( isSVR4ABI ( ) && is64BitMode ( ) ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO .

getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> static inline bool isImmLL ( uint64_t Val


<s> unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> if ( Disasm == NULL ) return false ; unsigned NumOpsAdded = <NUM_LIT> ; bool OK = ( * Disasm ) ( MI , Opcode , insn , NumOps , NumOpsAdded , this ) ; if ( ! OK || this -> Err != <NUM_LIT> ) return false ; if ( NumOpsAdded >= NumOps ) return true


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) ->


<s> else if ( AM . BaseType == <STR_LIT> ) MIB . addFrameIndex ( AM . Base . FrameIndex ) ; else assert ( <NUM_LIT> ) ; MIB . addImm ( AM . Scale ) . addReg ( AM . IndexReg ) ; if ( AM . GV ) MIB . addGlobalAddress ( AM . GV , AM . Disp , AM . GVOpFlags ) ; else MIB . addImm ( AM . Disp ) ; return MIB . addReg ( <NUM_LIT>


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant *


<s> bool <ISA_LIT>TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == <STR_LIT> ) return Subtarget . hasSSE1 (


<s> if ( ArgFlags . isHva ( ) ) return CC_<ISA_LIT>_VectorCallAssignRegister ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; return true ; } if ( ! ( ValVT . isFloatingPoint ( ) || ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) >= <NUM_LIT> ) ) ) { return false ; } if ( ArgFlags . isHva ( ) ) return true ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } if ( ! ValVT . isFloatingPoint ( ) ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign ::


<s> for ( MachineBasicBlock :: iterator MII = MBB . getFirstTerminator ( ) , MIIE = MBB . end ( ) ; MII != MIIE ; ++ MII ) { unsigned Opc = MII -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ! verifyCTRBranch ( & MBB , MII ) ) llvm_unreachable ( <STR_LIT> ) ; } } return false


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode


<s> void <ISA_LIT>WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr )


<s> if ( RetTy -> isVectorTy ( ) && ID ==

<STR_LIT> ) return getNumVectorRegs ( RetTy ) ;


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition


<s> } ; if ( MaskNode . getOpcode ( ) == <STR_LIT> ) { if ( VT . getScalarSizeInBits ( ) != MaskEltSizeInBits ) return false ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskNode . getOperand ( <NUM_LIT> ) ) ) { const APInt & MaskElement = CN -> getAPIntValue ( ) ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { APInt RawElt = MaskElement . getLoBits ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; } } return false ; } if ( MaskNode . getOpcode ( ) == <STR_LIT> && MaskNode . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue MaskOp = MaskNode . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskOp ) ) { if ( ( MaskEltSizeInBits % VT . getScalarSizeInBits ( ) ) == <NUM_LIT> ) { RawMask . push_back ( CN -> getZExtValue ( ) ) ; RawMask . append ( NumMaskElts - <NUM_LIT> , <NUM_LIT> ) ; return true ; } if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) == <NUM_LIT> ) { unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; SplitElementToMask ( CN -> getAPIntValue ( ) ) ; RawMask . append ( ( VT . getVectorNumElements ( ) - <NUM_LIT> ) * ElementSplit , <NUM_LIT> ) ; return true ; } } return false ; } if ( MaskNode . getOpcode ( ) != <STR_LIT> ) return false ; if ( all_of ( MaskNode -> ops ( )


<s> bool <ISA_LIT>_MC :: isPredicated ( const MCInst & MI , const MCInstrInfo * MCII ) { const MCInstrDesc & Desc = MCII -> get (


<s> arm_configure_build_target ( & arm_active_target , ptr , false ) ; arm_option_reconfigure_globals ( )


<s> bool SelectAddrModeUnscaled128 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeUnscaled ( N , <NUM_LIT> , Base ,


<s> unsigned ByValSize = Flags . getByValSize ( ) ; unsigned Alignment = std :: min ( Flags . getByValAlign ( ) , ( unsigned ) <NUM_LIT> ) ; bool IsRegLoc = VA . isRegLoc ( ) ; unsigned Offset = <NUM_LIT> ; unsigned LocMemOffset = <NUM_LIT> ; unsigned MemCpySize = ByValSize ; if ( ! IsRegLoc ) LocMemOffset = VA . getLocMemOffset ( ) ; else { const uint16_t * Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; const uint16_t * RegEnd = <ISA_LIT>64IntRegs + <NUM_LIT> ; for ( ; ( Reg != RegEnd ) && ( ByValSize >= Offset + <NUM_LIT> ) ; ++ Reg , Offset += <NUM_LIT> ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( <STR_LIT> , dl , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( * Reg , LoadVal ) ) ; } if ( ! ( MemCpySize = ByValSize - Offset ) ) return ; if ( Reg != RegEnd ) { assert ( ( ByValSize < Offset + <NUM_LIT> ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned OffsetDW = ( Offset % <NUM_LIT> ) * <NUM_LIT> ; unsigned Shamt = isLittle ? OffsetDW : <NUM_LIT> - ( OffsetDW + LoadSize * <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; Val = Val . getNode ( ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Shift ) : Shift ; Offset += LoadSize ; Alignment = std :: min (


<s> VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , Size / Scale ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) if ( SDValue Unpack = TryUnpack ( ScalarSize , ScalarSize / OrigScalarSize ) ) return Unpack ; if ( <STR_LIT> ( V1 . getNode ( ) ) || <STR_LIT> ( V2 . getNode ( ) ) ) return SDValue ( ) ; if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ; SmallVector < int , <NUM_LIT> > PermMask ( ( unsigned ) Size ,


<s> Register StoreSrcReg = StoreMI . getValueReg ( ) ; LLT StoreSrcTy = MRI . getType ( StoreSrcReg ) ; if ( ! DefDstTy . isValid ( ) ) return false ; if ( DefDstTy . getSizeInBits ( ) != StoreSrcTy . getSizeInBits ( ) ) return false ; if ( StoreSrcTy . getSizeInBits ( ) != StoreMI . getMemSizeInBits ( )


<s> static void mep_rewrite_maddsi3 ( rtx_insn * insn , rtx dest , rtx src1 , rtx src2 , rtx src3 ) { rtx lo , pattern ; lo = gen_rtx_REG ( SImode , LO_REGNO ) ; emit_insn_before ( gen_movsi ( copy_rtx ( lo ) , src3 ) ,


<s> scratch_reg = clearing_reg ; } mask = ( ~ padding_bits_to_clear [ i ] ) & <NUM_LIT> ; emit_move_insn ( scratch_reg , gen_int_mode ( mask , SImode ) ) ; mask = ( ~ padding_bits_to_clear [ i ] ) >> <NUM_LIT> ; rtx16 = gen_int_mode ( <NUM_LIT> , SImode ) ; dest = gen_rtx_ZERO_EXTRACT ( SImode , scratch_reg , rtx16 , rtx16 ) ; if ( mask ) emit_insn ( gen_rtx_SET ( dest , gen_int_mode ( mask , SImode ) ) ) ; emit_insn ( gen_andsi3 ( cleared_reg , cleared_reg , scratch_reg ) ) ; } if ( saved_clearing ) emit_move_insn ( clearing_reg , saved_clearing_reg ) ; if ( TARGET_HAVE_FPCXT_CMSE ) { rtvec vunspec_vec ; int i , j , k , nb_regs ; rtx use_seq , par , reg , set , vunspec ; int to_clear_bitmap_size = SBITMAP_SIZE ( to_clear_bitmap ) ; auto_sbitmap core_regs_bitmap ( to_clear_bitmap_size ) ; auto_sbitmap to_clear_core_bitmap ( to_clear_bitmap_size ) ; for ( i = FIRST_VFP_REGNUM ; i <= maxregno ; i += nb_regs ) { for ( ; i <= maxregno && ! bitmap_bit_p ( to_clear_bitmap , i ) ; i ++ ) ; if ( i > maxregno ) break ; for ( j = i ; j <= maxregno && bitmap_bit_p ( to_clear_bitmap , j ) ; j ++ ) ; nb_regs = j - i ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nb_regs + <NUM_LIT> ) ) ; vunspec_vec = gen_rtvec ( <NUM_LIT> , gen_int_mode ( <NUM_LIT> , SImode ) ) ; vunspec = gen_rtx_UNSPEC_VOLATILE ( SImode , vunspec_vec , VUNSPEC_VSCCLRM_VPR ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = vunspec ; start_sequence ( ) ; for ( k = <NUM_LIT> , j = i ; j <= maxregno && k < nb_regs + <NUM_LIT> ; j ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap ,


<s> StoreTailCallArgumentsToStackSlot ( DAG , Chain , TailCallArguments , MemOpChains2 , dl ) ; if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains2 ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , Chain , LROp , FPOp , SPDiff , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true


<s> case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT


<s> return ( TARGET_USE_MS_BITFIELD_LAYOUT && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) )

) || lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ;


<s> if ( ! N -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) != <STR_LIT> ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( UI -> getNumOperands ( ) > <NUM_LIT> ) return false ; if ( UI -> getNumOperands ( ) == <NUM_LIT> && UI -> getOperand ( UI -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain


<s> static int rid_int128 ( void ) { int i ; for ( i = <NUM_LIT> ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == <NUM_LIT> ) return RID_INT_N_0 + i ; return RID_MAX + <NUM_LIT>


<s> void DecodeScalarMoveMask ( unsigned NumElts , bool IsLoad , SmallVectorImpl < int > & ShuffleMask ) { ShuffleMask . push_back ( NumElts


<s> bool selectBDAddr20Only ( SDValue Addr , SDValue & Base , SDValue


<s> bool isBlockAddress ( ) const { return Kind ==


<s> bool IsEVEX_V128 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) ; bool IsEVEX_V256 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ( Desc . TSFlags & <STR_LIT> ) ) ; unsigned NewOpc = <NUM_LIT> ; if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ; auto isHiRegIdx = [ ]


<s> unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address ,


<s> fprintf ( file , <STR_LIT> <STR_LIT> ) ; fprintf ( file , <STR_LIT> <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file ,


<s> if ( MIA -> evaluateMemoryOperandAddress ( * MI , nullptr , <NUM_LIT> , <NUM_LIT> ) ) return ; } const MCOperand & BaseReg = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <STR_LIT> ) ; O << markup ( <STR_LIT> ) ; printOptionalSegReg ( MI , Op + <STR_LIT> , O ) ; if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; DispSpec . getExpr ( ) -> print ( O , & MAI ) ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op + <STR_LIT> , O ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <STR_LIT> ,


<s> rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; if ( last_def_reg == NULL_RTX )


<s> InstructionSelector * llvm :: create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & Subtarget


<s> unsigned getMemOffsetReg ( ) const { assert ( ( Kind == k_MemoryReg ) && <STR_LIT>


<s> DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; } DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeSImm < <NUM_LIT> > ( Inst , offset , Addr , Decoder


<s> bool aarch_rev16_shright_mask_imm_p ( rtx val


<s> case <STR_LIT> : return lowerSelectCc ( Op , DAG ) ; case <STR_LIT> : return lowerAnd ( Op , DAG ) ; case <STR_LIT> : return lowerOr ( Op , DAG ) ; case <STR_LIT> : return lowerXor ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG


<s> static MCRelocationInfo * create<ISA_LIT>MCRelocationInfo ( StringRef TT , MCContext & Ctx ) { Triple TheTriple ( TT ) ; if ( TheTriple . isEnvironmentMachO ( ) ) return create<ISA_LIT>MachORelocationInfo ( Ctx ) ; return llvm :: createMCRelocationInfo ( TT , Ctx


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( Info . IsMustTailCall ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , Info . CallConv ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) SplitArgs . back ( ) . Flags . setZExt ( ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( Info . CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( Info . CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Info . Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Info . Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { SplitArgs . clear


<s> MCCodeEmitter * llvm :: create<ISA_LIT>BEMCCodeEmitter ( const MCInstrInfo & MCII , MCContext


<s> return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ImmMask != <NUM_LIT> ) { Register OISrcReg ; Register OISrcReg2 ; int64_t OIMask ; int64_t OIValue ; if ( analyzeCompare ( OI , OISrcReg , OISrcReg2 , OIMask , OIValue ) && SrcReg == OISrcReg && ImmMask == OIMask ) { if ( OIValue == ImmValue ) { * ImmDelta = <NUM_LIT> ; return true ; } else if ( static_cast < uint64_t > ( ImmValue ) == static_cast < uint64_t > ( OIValue ) - <NUM_LIT> ) { * ImmDelta = -


<s> switch ( mode ) { case V2SFmode : case V2SImode : if ( mmx_ok ) { tmp = gen_reg_rtx ( GET_MODE_INNER ( mode ) ) ; ix86_expand_vector_extract ( true , tmp , target , <NUM_LIT> - elt ) ; if ( elt == <NUM_LIT> ) tmp = gen_rtx_VEC_CONCAT ( mode , tmp , val ) ; else tmp = gen_rtx_VEC_CONCAT ( mode , val , tmp ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; return ; } break ; case V2DFmode : case V2DImode : { rtx op0 , op1 ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( <NUM_LIT> - elt ) ) ) ; tmp = gen_rtx_VEC_SELECT ( inner_mode , target , tmp ) ; if ( elt == <NUM_LIT> ) op0 = val , op1 = tmp ; else op0 = tmp , op1 = val ; tmp = gen_rtx_VEC_CONCAT ( mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; } return ; case V4SFmode : switch ( elt ) { case <NUM_LIT> : use_vec_merge = true ; break ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; emit_insn ( gen_sse_unpcklps ( target , target , target ) ) ; ix86_expand_vector_set ( false , target , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; ix86_expand_vector_set ( false , tmp , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; ix86_expand_vector_set ( false , tmp , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; default : gcc_unreachable ( ) ; } break ; case


<s> void addImm0_4095NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > (


<s> if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) { if ( UndefElts [ i ] ) continue ; int VecIdx = Scale * Idx + i ; ShuffleMask [ VecIdx ] = EltBits [ i ] . isNullValue ( ) ? SM_SentinelZero : VecIdx ; } if ( SDValue Shuffle = combine<ISA_LIT>ShufflesRecursively ( { SrcVec } , <NUM_LIT> , SrcVec , ShuffleMask , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shuffle , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; } } return SDValue (


<s> const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr

:: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ;


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool isZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = EmitIntExt ( RVVT , SrcReg , DestVT , isZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg )


<s> unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegN ) ; RegN = II -> getRegisterInfo ( ) . getEncodingValue ( RegN ) ; if ( ! isSPVFP ) Binary |= RegN << <STR_LIT> ; else { Binary |= ( ( RegN & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; } return Binary


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Name = Tok . getString ( ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchRegisterNameAlias ( Head , MatchKind ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidSVEKind ( Kind ) ) { TokError ( <STR_LIT>


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT MaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDLoc dl ( Op ) ; assert ( MaskVT . isSimple ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl

, MaskVT , Mask ) , Op , PreservedSrc ) ;


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; return


<s> static DecodeStatus DecodeMVEVCVTt1fp ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Qd = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned Qm = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getTargetData ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getFnAttributes ( ) . hasNoImplicitFloatAttr ( ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> case <STR_LIT> : return true ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned CallOpc , LeaOpc , Reg ; if ( Opc == <STR_LIT> ) { CallOpc = <STR_LIT> ; LeaOpc = <STR_LIT> ; Reg = <STR_LIT> ; } else { CallOpc = <STR_LIT> ; LeaOpc = <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MBBI , DL , TII -> get ( CallOpc ) ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( LeaOpc ) , Reg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Reg ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MI . eraseFromParent (


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO ; break ; } break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>64_TOC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>64_TOC16 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_ENTRY : Type = ELF :: R_<ISA_LIT>64_TOC16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO_DS ; break ; } break ; case FK_Data_8 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC : Type = ELF :: R_<ISA_LIT>64_TOC ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>64_ADDR64 ; break ; } break ; case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_ADDR32 ; break ; case FK_Data_2 : Type = ELF :: R_<ISA_LIT>_ADDR16 ; break ; } } return Type


<s> case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT>


<s> bool isCRBitMask ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> >

( getImm ( ) ) && isPowerOf2_32 ( getImm ( ) ) ; }


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; EVT SclVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! SclVT . isScalarInteger ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Vec ; SmallVector < int , <NUM_LIT> > ShuffleMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts == SclVT . getSizeInBits ( ) && <STR_LIT> ) ; if ( NumElts > EltSizeInBits ) { assert ( ( NumElts % EltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = NumElts / EltSizeInBits ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , EltSizeInBits ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; Vec = DAG . getBitcast ( VT , Vec ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) ShuffleMask . append ( EltSizeInBits , i ) ; Vec = DAG . getVectorShuffle ( VT , DL , Vec , Vec , ShuffleMask ) ; } else if ( Subtarget . hasAVX2 ( ) && NumElts < EltSizeInBits && ( SclVT == <STR_LIT> || SclVT == <STR_LIT> || SclVT == <STR_LIT> ) ) { assert ( ( EltSizeInBits % NumElts ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = EltSizeInBits / NumElts ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , NumElts * Scale ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; ShuffleMask . append ( NumElts * Scale , <NUM_LIT> ) ; Vec = DAG . getVectorShuffle ( BroadcastVT , DL , Vec , Vec , ShuffleMask ) ; Vec = DAG . getBitcast ( VT ,


<s> void <ISA_LIT>AsmParser :: onLabelParsed ( MCSymbol * Symbol ) { if ( NextSymbolIsThumb ) { getParser ( ) . getStreamer ( ) . emitThumbFunc (


<s> return false ; } int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( Val == <NUM_LIT> ) { if ( ! hasThumb (


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx

] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> return ( float32x2_t ) __builtin_neon_vreinterpretv2sfdi ( ( int64x1_t


<s> SDLoc DL ( Node ) ; const BlockAddress * BA = Node -> getBlockAddress ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; return Result


<s> for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx reg = DF_REF_REG ( ref ) ; if ( ! MEM_P ( src ) ) { replace_with_subreg_in_insn ( insn , reg , reg ) ; bitmap_clear_bit ( conv , INSN_UID ( insn ) ) ; } if ( scalar_copy ) { start_sequence ( ) ; if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; } else if ( TARGET_INTER_UNIT_MOVES_FROM_VEC ) { rtx vcopy = gen_reg_rtx ( V2DImode ) ; emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; emit_move_insn ( vcopy , gen_rtx_LSHIFTRT ( V2DImode , vcopy , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( tmp , reg ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } rtx_insn * seq = get_insns (


<s> } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable4 ; } if ( OpcodeTablePtr ) { auto I = OpcodeTablePtr -> find ( MI . getOpcode ( ) ) ; if ( I != OpcodeTablePtr -> end ( ) ) { unsigned Opcode = I -> second . first ; unsigned MinAlign = ( I -> second . second & TB_ALIGN_MASK ) >> TB_ALIGN_SHIFT ; if ( Align < MinAlign ) return nullptr ; bool NarrowToMOV32rm = false ; if ( Size ) { const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; const TargetRegisterClass * RC = getRegClass ( MI . getDesc ( ) , OpNum , & RI , MF ) ; unsigned RCSize = TRI . getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( Size < RCSize ) { if ( Opcode != <STR_LIT> || RCSize != <NUM_LIT> || Size != <NUM_LIT> ) return nullptr ; if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return nullptr ; Opcode = <STR_LIT> ; NarrowToMOV32rm = true ; } } if ( isTwoAddrFold ) NewMI = FuseTwoAddrInst ( MF , Opcode , MOs , InsertPt , MI , * this ) ; else NewMI = FuseInst ( MF , Opcode , OpNum , MOs , InsertPt , MI , * this ) ; if ( NarrowToMOV32rm ) { unsigned DstReg = NewMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) NewMI -> getOperand ( <NUM_LIT> ) . setReg ( RI . getSubReg ( DstReg , <STR_LIT> ) ) ; else NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } return NewMI ; } } if ( AllowCommute ) { unsigned CommuteOpIdx1 = OpNum , CommuteOpIdx2 = CommuteAnyOperandIndex ; if ( findCommutedOpIndices ( MI , CommuteOpIdx1 , CommuteOpIdx2 ) ) { bool HasDef = MI . getDesc ( ) . getNumDefs ( ) ; unsigned Reg0 = HasDef ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; unsigned Reg1 = MI . getOperand ( CommuteOpIdx1 ) . getReg ( ) ; unsigned Reg2 = MI . getOperand ( CommuteOpIdx2 ) . getReg ( ) ; bool Tied1 = <NUM_LIT> == MI . getDesc ( ) . getOperandConstraint ( CommuteOpIdx1


<s> bool NegA = N -> getOpcode ( ) != <STR_LIT> && invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = N -> getOpcode ( ) != <STR_LIT> && invertIfNegative ( C ) ; bool NegMul = ( NegA != NegB ) ; unsigned NewOpcode ; if ( ! NegMul ) NewOpcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else NewOpcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ;


<NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , vec_splat_u8 ( <NUM_LIT> ) ) ) ) ;


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget . hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget . hasSSE1 ( ) ) return <STR_LIT> ; } return TargetLowering :: LowerXConstraint ( ConstraintVT


<s> SDValue FPOne = DAG . getConstantFP ( <NUM_LIT> , VT . getScalarType ( ) ) ; if ( VT . isVector ( ) ) { assert ( VT . getVectorNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; FPOne = DAG . getNode ( <STR_LIT> , dl , VT , FPOne , FPOne , FPOne , FPOne ) ; } SDValue Est = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ; for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) { SDValue NewEst = DAG . getNode ( <STR_LIT> , dl , VT , Op , Est ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , FPOne , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , Est , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; Est = DAG . getNode ( <STR_LIT> , dl , VT , Est , NewEst ) ; DCI . AddToWorklist ( Est . getNode ( )


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> || windowsRequiresStackProbe ( MF , StackBumpBytes ) ) return false ; if ( MFI . hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF


<s> EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo ,


<s> static int rs6000_sched_reorder2 ( FILE * dump , int sched_verbose , rtx_insn * * ready , int * pn_ready , int clock_var ATTRIBUTE_UNUSED ) { if ( sched_verbose ) fprintf ( dump , <STR_LIT>


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW ,


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) )


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) ->


<s> MCInst MaskInst ; MaskInst . setOpcode ( <STR_LIT> ) ; MaskInst . addOperand ( MCOperand ::


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr


<s> MachineBasicBlock * LoopExit = getWhileLoopStartTargetBB ( * WlsInstr ) ; if ( ! LoopExit -> getPrevNode ( ) ) return false ; if ( blockIsBefore ( Predecessor , LoopExit ) ) return false ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << Predecessor -> getFullName ( ) << <STR_LIT> << LoopExit -> getFullName ( ) << <STR_LIT> ) ; for ( auto It = ++ LoopExit -> getIterator ( ) ; It != Predecessor -> getIterator ( ) ; ++ It ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( ! isWhileLoopStart ( Terminator ) ) continue ; MachineBasicBlock * WLSTarget = getWhileLoopStartTargetBB


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( )


<s> return __builtin_arm_smlaldx ( __a ,


<s> } const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , SrcRegOp . getReg ( ) , Is32BitImm , IDLoc , Instructions ) ) return true ; return


<s> bool aarch64_simd_imm_scalar_p ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { HOST_WIDE_INT imm = INTVAL ( x ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned int byte = imm & <NUM_LIT> ; if ( byte != <NUM_LIT> && byte != <NUM_LIT> ) return false ; imm >>= <NUM_LIT> ; } return true


<s> bool shouldConsiderGEPOffsetSplit ( ) const override { return true


<s> switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const MCInstrDesc & II = TII . get (


<s> assert ( Inst . getOperand ( OpNum - <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) { if ( inMicro<ISA_LIT>Mode ( ) && has<ISA_LIT>32r6 ( ) ) NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } Inst . setOpcode ( NewOpcode ) ; Instructions . push_back


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT SrcVT = SrcVal . getValueType ( ) ; if ( SrcVT != <STR_LIT> ) { if ( useSVEForFixedLengthVectorVT ( SrcVT ) ) return SDValue (


<s> SDValue <ISA_LIT>TargetLowering :: LowerSVEStructLoad ( unsigned Intrinsic , ArrayRef < SDValue > LoadOps , EVT VT , SelectionDAG & DAG , const SDLoc & DL ) const { assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; unsigned N , Opcode ; static std :: map < unsigned , std :: pair < unsigned , unsigned >> IntrinsicMap = { { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } } ; std :: tie ( N , Opcode ) = IntrinsicMap [ Intrinsic ] ; assert ( VT . getVectorElementCount ( ) . Min % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / N ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys , LoadOps ) ; SmallVector < SDValue , <NUM_LIT> > PseudoLoadOps ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) PseudoLoadOps . push_back ( SDValue ( PseudoLoad . getNode ( ) , I ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( ) ) . addExternalSymbol ( SymName , <STR_LIT> ) ; return DestReg


<s> for ( ++ Inst ; Inst != Seq . end ( ) ; ++ Inst ) BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDu )

, Reg ) . addReg ( Reg ) . addReg ( ATReg ) ;


<s> if ( num_suffix == <NUM_LIT> ) sprintf ( buffer , <STR_LIT> , funcname , modename ) ; else sprintf ( buffer , <STR_LIT> , funcname , modename , num_suffix ) ; set_optab_libfunc ( optable , mode ,


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t CPUType , uint32_t


<s> Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; if ( ! EmitStore ( VT , SrcReg , Addr ) ) return false ; return


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF


<s> cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ; else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= <NUM_LIT> )


<s> bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return


<s> addLeaRegOffset ( MIB , leaInReg , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : addLeaRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) . addReg ( leaInReg2 ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) . addImm ( <STR_LIT> ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; if ( LV )


<s> if ( ! MEM_SIZE_KNOWN_P ( * str_mem ) ) return false ; machine_mode mode = GET_MODE ( * str_mem ) ; HOST_WIDE_INT size = MEM_SIZE ( * str_mem ) ; if ( INTEGRAL_MODE_P ( mode ) ) return ( size == <NUM_LIT> || size == <NUM_LIT> ) ; else if ( FLOAT_MODE_P ( mode ) ) return (


<s> const Instruction * UserI = cast < Instruction > ( * FoldedValue -> user_begin ( ) ) ; assert ( UserI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( UserI -> getOperand ( i ) == FoldedValue ) continue ; if ( Instruction * OtherOp = dyn_cast < Instruction > ( UserI -> getOperand ( i ) ) ) { LoadInst * OtherLoad = dyn_cast < LoadInst > ( OtherOp ) ; if ( ! OtherLoad && ( isa < TruncInst > ( OtherOp ) || isa < SExtInst > ( OtherOp ) || isa < ZExtInst > ( OtherOp ) ) ) OtherLoad = dyn_cast < LoadInst > ( OtherOp -> getOperand ( <NUM_LIT> ) ) ; if ( OtherLoad && isFoldableLoad ( OtherLoad , FoldedValue ) ) return i == <NUM_LIT> ; } } return <NUM_LIT> ; } } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ( ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> ) || ST -> hasVectorEnhancements2 ( ) ) && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ; } else if ( const StoreInst * SI = dyn_cast < StoreInst > ( I ) ) { const Value * StoredVal = SI -> getValueOperand ( ) ; if ( StoredVal -> hasOneUse ( ) && isBswapIntrinsicCall ( StoredVal ) ) return <NUM_LIT> ; } } if ( Src -> getScalarSizeInBits ( ) == <NUM_LIT> ) NumOps *= <NUM_LIT> ; return NumOps


<s> static <ISA_LIT>Operand * CreateFPImm ( unsigned Val , SMLoc S , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_FPImm , Ctx ) ; Op -> FPImm . Val = Val ; Op -> StartLoc =


<s> case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode ; if ( ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) || ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) ) Opcode = LowerOpcode ; else Opcode = UpperOpcode ; MI . setDesc ( get ( Opcode


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo ,


<s> HOST_WIDE_INT size ; switch ( TREE_CODE ( type ) ) { case REAL_TYPE : mode = TYPE_MODE ( type ) ; if ( ! SCALAR_FLOAT_MODE_P ( mode ) ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case COMPLEX_TYPE : mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( ! SCALAR_FLOAT_MODE_P ( mode ) ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case VECTOR_TYPE : if ( ! TARGET_ALTIVEC_ABI || ! TARGET_ALTIVEC ) return - <NUM_LIT> ; size = int_size_in_bytes ( type ) ; switch ( size ) { case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE

( type ) ) != INTEGER_CST ) return - <NUM_LIT> ;


<s> if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) return tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case <STR_LIT>


<s> Fixups . push_back ( llvm :: MCFixup :: create ( <NUM_LIT> , DiffExpr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) && BranchMO . isImm ( ) ) ; int Diff = MO . getImm ( ) - BranchMO . getImm ( ) ; assert ( Diff == <NUM_LIT> || Diff ==


<s> } if ( ! isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( OffsetVal ) ) return false ; if ( Base . getOpcode ( ) != <STR_LIT> ) return false ; unsigned IntID = cast < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntID != <STR_LIT> ) return false ; unsigned IntKey = cast < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! isNullConstant ( Base . getOperand ( <NUM_LIT> ) ) ) return false ; if ( OffsetVal && ! Base . hasOneUse ( ) ) return false ; Base = Base . getOperand ( <NUM_LIT> ) ; bool needsWriteback = isPre ; if ( ! Ptr . hasOneUse ( ) ) { needsWriteback = true ; SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; SmallVector < const SDNode * , <NUM_LIT> > Worklist ; Worklist . push_back ( N ) ; for ( SDNode * U : Ptr . getNode ( ) -> uses ( ) ) if ( SDNode :: hasPredecessorHelper ( U , Visited , Worklist , <NUM_LIT> , true ) ) return false ; } unsigned Opc = <NUM_LIT> ; switch ( IntKey ) { case <STR_LIT> : Opc = needsWriteback ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = needsWriteback ? <STR_LIT> : <STR_LIT> ; break ; default : return false ; } SDLoc DL ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal / <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = needsWriteback ? CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) : CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , <STR_LIT> , Ops ) ; if ( isPre ) { assert ( needsWriteback && <STR_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> )


<s> if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMIFlags ( MI -> getFlags ( )


<s> if ( unsigned MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( )


<s> bool isCK803S ( ) const { return <ISA_LIT>ProcFamily ==


<s> case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } InstrumentMOVSImpl ( AccessSize , Ctx ,


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const { return getSubExpr ( ) -> EvaluateAsRelocatable ( Res ,


<s> case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandAtomicRMW ( MI , BB , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT>


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; }


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , HOST_WIDE_INT offset ) { return offset >= - <NUM_LIT> &&


<s> unsigned InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; if ( empty ( MI . implicit_operands ( ) ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) { MachineOperand & MO = MI . getOperand


<s> return ( __m64 ) __builtin_ia32_pcmpgtb ( ( __v8qi ) __m1 ,


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT>


<s> case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = ( ArgVT . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset (


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> void <ISA_LIT>BaseInstrInfo :: expandLoadStackGuardBase ( MachineBasicBlock :: iterator MI , unsigned LoadImmOpc , unsigned LoadOpc ) const { assert ( ! Subtarget . isROPI ( ) && ! Subtarget . isRWPI ( ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } MIB = BuildMI ( MBB , MI , DL


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; } return


<s> tmp = hard_frame_pointer_rtx ; offset = - offset ; } else { tmp = stack_pointer_rtx ; offset = current_frame_info . total_size - offset ; } if ( CONST_OK_FOR_I ( offset ) ) emit_insn ( gen_adddi3 ( pic_offset_table_rtx , tmp , GEN_INT ( offset ) ) ) ; else { emit_move_insn ( pic_offset_table_rtx , GEN_INT ( offset ) ) ; emit_insn ( gen_adddi3 ( pic_offset_table_rtx , pic_offset_table_rtx , tmp ) ) ; } tmp = gen_rtx_MEM ( DImode ,


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) , false , false , false ) ; return ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : printSymbolOperand (


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB =


<s> Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler


<s> } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex (


<s> else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetWindows ( ) || Subtarget -> isTargetMingw ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetMingw ( ) ? DAG


<s> sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } named_section_flags ( section , SECTION_WRITE ) ; assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> ,


<s> if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getGlobalVariable (


<s> O << <STR_LIT> ; printMemReference ( MI ,