<s> return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , <NUM_LIT> ) ) { if ( MO . isImplicit ( ) || ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) { if ( ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) && ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) ) { ErrInfo = <STR_LIT> ; return false ; } } } } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } <STR_LIT> AddrMode = ( <STR_LIT> ) ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Imm = <NUM_LIT> ; for ( auto Op : MI . operands ( ) ) { if ( Op . isImm ( ) ) { Imm = Op . getImm (


<s> mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: The<ISA_LIT>_32Target , mcld :: create<ISA_LIT>LDBackend ) ; mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: The<ISA_LIT>_64Target ,


<s> CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , true , true ) ; if ( valret ) return false ; } if ( rs6000_discover_homogeneous_aggregate ( TYPE_MODE ( type ) , type , NULL , NULL ) ) return false ; if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE (


<s> if ( Subtarget . hasInt256 ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT InVT = N . getValueType ( ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , Size / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize


<s> if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT>


<s> MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) { EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * I ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI ) ; return BB ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( SrcReg != <STR_LIT> ) { const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( SrcReg ) ; unsigned CopyOpc = ( RC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , dl , TII -> get ( CopyOpc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState (


<s> return __builtin_mve_vcvtq_m_from_f_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; return ret


<s> break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; if ( A -> getSize ( ) == <NUM_LIT> ) return getCommonSubClass ( A , & <STR_LIT> ) ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT>


<s> else if ( auto * UE = dyn_cast < MCUnaryExpr > ( E ) ) OS << * UE ; else if ( auto * BE = dyn_cast < MCBinaryExpr > ( E ) ) OS << * BE ; else if ( auto * SRE = dyn_cast < MCSymbolRefExpr > ( E ) ) OS << * SRE ; else OS << *


<s> uint32_t UseCount = <NUM_LIT> ; if ( ! OptForSize ) return false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ( UI != UE ) && ( UseCount < <NUM_LIT> ) ; ++ UI ) { SDNode * User = * UI ; if ( User -> isMachineOpcode ( ) ) { UseCount ++ ; continue ; } if ( User -> getOpcode ( ) == <STR_LIT> && User -> getOperand (


<s> bool isBeri ( ) const { return IsBeri


<s> bool hasMessageSecurityAssist7 ( ) const { return


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment )


<s> void addDispRIXOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: CreateImm ( getImm ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg )


<s> SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg (


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> target_flags &= ~ MASK_GPOPT ; iq2000_isa = IQ2000_ISA_DEFAULT ; iq2000_print_operand_punct [ '?' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '#' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '&' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '!' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '*' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '@' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '.' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '(' ] = <NUM_LIT> ; iq2000_print_operand_punct [ ')' ] = <NUM_LIT> ; iq2000_print_operand_punct [ '[' ]


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( TARGET_ALTIVEC || TARGET_VSX ) return altivec_builtin_mask_for_load ; else return <NUM_LIT>


<s> SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> )

, MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee


<s> if ( optab_handler ( movmisalign_optab , mode ) == CODE_FOR_nothing ) return false ; if ( misalignment == - <NUM_LIT> ) { if ( aarch64_simd_vector_alignment_reachable ( type ,


<s> static bool canUseLocalRelocation ( const MCSectionMachO & Section , const MCSymbol & Symbol , unsigned Log2Size ) { if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) return true ; if ( Log2Size != <NUM_LIT> ) return false ; if ( ! Symbol . isInSection ( ) )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned SType = <NUM_LIT> ; DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant (


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return std :: unique_ptr < MCObjectWriter > (

create<ISA_LIT>ELFObjectWriter ( OS , OSABI ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )

. addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> void setFI ( unsigned FI ) { assert ( isFIBase ( ) && <STR_LIT>


<s> EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG .

getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg


<s> bool <ISA_LIT>PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > (


<s> if ( ! Op0 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( ! Op1 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType


<s> int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue (


<s> for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; auto OpSize = N -> getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; unsigned Size = DAG . getDataLayout ( ) . getLargestLegalIntTypeSizeInBits ( ) ; if ( OpSize < Size ) { switch ( CC ) { default : break ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , false , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , true , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , true , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , false , DL , DAG ) ; } } return SDValue (


<s> assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsByteShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL

, In , DAG . getUNDEF ( <STR_LIT> ) , & Mask [ <NUM_LIT> ] ) ) ;


<s> if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( isBaseAlignmentOfN ( <NUM_LIT> , LD -> getBasePtr ( ) . getNode ( ) , TLI ) ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) ) ; return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) } ; SDValue ResNode = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } return SDValue (


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , dl , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , dl , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO )


<s> if ( Index ) O << '%' << getRegisterName ( Index ) << ',' ; O << '%' << getRegisterName ( Base ) << ')' ; } else assert ( !


<s> void <ISA_LIT>MCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler


<s> Triple TheTriple ( TT ) ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT>


<s> <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; <ISA_LIT>StackPtr = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; TD = getDataLayout ( ) ; resetOperationActions (


<s> return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Val = DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ; return ExtendedInMem ? DAG . getNode ( <STR_LIT> , dl , VA .


<s> unsigned imod = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; S = MCDisassembler ::


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else { O << * Op . getExpr (


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT>


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode


<s> case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; } return true


<s> unsigned <ISA_LIT>CodeEmitter :: getMemRIXEncoding ( const MachineInstr & MI , unsigned OpNo ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) ) << <NUM_LIT> ; const MachineOperand & MO = MI


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseCOP2 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken

:: Integer ) ) return MatchOperand_NoMatch ;


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI )


<s> emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ; return ; } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , <NUM_LIT>


<s> unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt , SDLoc ( Op ) , <STR_LIT> ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , OriginalDemandedElts ,


<s> assert ( ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) && <STR_LIT> ) ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; return getI8Imm ( ( Index * VecVT . getScalarSizeInBits ( ) ) / VecWidth


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; std :: string lowerCase = Tok . getString ( )


<s> vec_uchar16 x ; x = vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ; return ( ( qword ) ( vec_sll ( ( vec_uchar16 )


<s> static SDValue LowerMUL ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( VT . is128BitVector ( ) && VT . isInteger ( ) && <STR_LIT> ) ; SDNode * N0 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * N1 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned NewOpc = <NUM_LIT> ; bool isMLA = false ; bool isN0SExt = isSignExtended ( N0 , DAG ) ; bool isN1SExt = isSignExtended ( N1 , DAG ) ; if ( isN0SExt && isN1SExt ) NewOpc = <STR_LIT> ; else { bool isN0ZExt = isZeroExtended ( N0 , DAG ) ; bool isN1ZExt = isZeroExtended ( N1 , DAG ) ; if ( isN0ZExt && isN1ZExt ) NewOpc = <STR_LIT> ; else if ( isN1SExt || isN1ZExt ) { if ( isN1SExt && isAddSubSExt ( N0


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum )

|| Memory . Alignment != <NUM_LIT> ) return false ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState ::


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = NULL ; PrivateGlobalPrefix = <STR_LIT> ; JumpTableDataSection = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; BSSSection = <STR_LIT> ; CStringSection =


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( ValueTy ) ) ; if ( ValueTy -> isPointerTy ( ) ) Addr = Builder . CreatePointerCast ( Addr , IntEltTy

-> getPointerTo ( Addr -> getType ( ) -> getPointerAddressSpace ( ) ) ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target &


<s> ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregciv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregciv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregciv2si ( __o , <NUM_LIT> ) ; return


<s> MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) .


<s> case E_V16SFmode : case E_V8SImode : case E_V4SImode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V2SImode : vec_mode = mode ; imode = SImode ; break ; case E_V8DImode : case E_V4DImode : case E_V2DImode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : vec_mode = mode ; imode = DImode ; break ; case E_TImode : case E_TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - <NUM_LIT> , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg (


<s> assert ( ( Kind == CoprocNum || Kind == CoprocReg )


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ? & <STR_LIT>


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno ,

false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case


<s> case <STR_LIT> : break ; OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( TLS_GDCALL ) ; OPCODE ( TLS_LDCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( POPCNT ) ; OPCODE ( SMUL_LOHI ) ; OPCODE ( UMUL_LOHI ) ; OPCODE ( SDIVREM ) ; OPCODE ( UDIVREM ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t CurByte = <NUM_LIT> ; unsigned Value = getBinaryCodeForInstr ( Inst , Fixups


<s> return ( Val >> Amt ) | ( Val << ( ( <NUM_LIT> -


<s> MachineInstr * MI = MRI . getUniqueVRegDef ( SrcReg ) ; if ( ! MI ) return false ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; unsigned NewOpc = sForm ( * MI ) ; if ( NewOpc == <STR_LIT> ) return false ; if ( ! canInstrSubstituteCmpInstr ( * MI , CmpInstr , TRI ) ) return false ; MI -> setDesc ( get ( NewOpc ) ) ; CmpInstr . eraseFromParent ( ) ; bool succeeded = UpdateOperandRegClass ( *


<s> for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [ i ] + LowOffset ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [ i ]


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; align *= ( <NUM_LIT> << size ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm !=


<s> rtx src ; src = nds32_legitimize_pic_address ( operands [ <NUM_LIT>


<s> IsLittleEndian = false ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; LinkerPrivateGlobalPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT>


<s> SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , FILDOps , SrcVT , PtrInfo , Alignment , MachineMemOperand :: MOLoad ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( useSSE ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = DstVT . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( SSFISize , Align ( SSFISize ) , false ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackSlot = DAG . getFrameIndex (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage


<s> unsigned getStackAlignment ( ) const


<s> const InsertInfo I ( MIB ) ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; if ( ! validReg ( MRI , ResReg , <NUM_LIT> , <STR_LIT> ) ) return false ; auto Cond = static_cast < CmpInst :: Predicate > ( MIB -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( Cond == CmpInst :: FCMP_TRUE || Cond == CmpInst :: FCMP_FALSE ) { putConstant ( I , ResReg , Cond == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MIB -> eraseFromParent ( ) ; return true ; } auto LHSReg = MIB . getReg ( <NUM_LIT> ) ; auto RHSReg = MIB . getReg ( <NUM_LIT> ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . second , LHSReg , RHSReg , IntermediateRes ) ) return false ; } MIB -> eraseFromParent ( ) ; return true


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalMergePass ( const TargetLowering


<s> const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ; return true


<s> void addMemRegImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) )


<s> sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , carry ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == <NUM_LIT> ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case IOR : case XOR : case AND


<s> bool IsEHFuncletEpilogue = MBBI == MBB . end ( ) ? false : isFuncletReturnInstr ( * MBBI ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int FIOffset ; Register BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! hasStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) . getFixed ( ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) . getFixed ( ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } Register MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr


<s> return __builtin_mve_vcaddq_rot270v16qi ( __a ,


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return Opc ; } else switch ( MemSizeInBytes ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ? <STR_LIT> : <STR_LIT> ; case


<s> const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emit<ISA_LIT>Nops ( * OutStreamer , Num , Subtarget ) ; return ; } auto CurSled = OutContext . createTempSymbol ( <STR_LIT> ,


<s> unsigned Scratch2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Scratch1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Scratch2 ) . addReg ( Scratch1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> )

, GlobalBaseReg ) . addReg ( <STR_LIT> ) . addReg ( Scratch2 ) ;


<s> assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr (


<s> } if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; <ISA_LIT>AddressMode AM ; AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType


<s> bool SeenV1 = false ; bool SeenV2 = false ; for ( unsigned i = MaskI ; i != MaskE ; ++ i , ++ OpIdx ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx < <NUM_LIT> ) continue ; if ( Idx < ( int ) NumElems ) SeenV1 = true ; else SeenV2 =


<s> if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isOSWindows ( ) || ST . isTargetNaCl ( ) || MalignDouble ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant


<s> void <ISA_LIT>LowOverheadLoops :: RevertWhile ( MachineInstr * MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RevertWhileLoopStart ( MI ,


<s> } else { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 ,


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return <STR_LIT> ; case


<s> } } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) || Subtarget -> isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG

. getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ;


<s> int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) )


<s> Entry . IsSExt = shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Entry . IsZExt = ! shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT RetVT = Node -> getValueType ( <NUM_LIT> ) ; Type * RetTy = RetVT . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const Function & F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool isTailCall = isInTailCallPosition ( DAG , Node , TCChain ) && ( RetTy == F . getReturnType ( ) || F . getReturnType ( ) -> isVoidTy ( ) ) ; if ( isTailCall ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI (


<s> void <ISA_LIT>HazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ; <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ; if ( OptimizationGoals > <NUM_LIT> && ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetGNUAEABI ( ) ) ) ATS . emitAttribute ( <STR_LIT> , OptimizationGoals ) ; OptimizationGoals = -


<s> if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , DL , Ptr . getValueType ( ) ) ) ; } int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , EltNo ) ; return DAG . getVectorShuffle ( NVT , dl , V1 , DAG . getUNDEF ( NVT ) , & Mask [


<s> return createMCRelocationInfo ( TheTriple ,


<s> return __builtin_mve_vcmlaqv8hf ( __a ,


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) { auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI ) ; return createELFObjectWriter ( std :: move ( MOTW ) ,


<s> switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false


<s> return ( __m128i ) __builtin_ia32_vpcomfalseub ( ( __v16qi ) __A , ( __v16qi )


<s> SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr


<s> if ( GV -> isDeclaration ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; int Offset = SOffset . getBytes ( ) + ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff &&


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , unsigned VarArgsFrameIndex ) { DebugLoc dl = Op . getDebugLoc ( ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( )


<s> return ( __m512d ) __builtin_ia32_vfmaddsubpd512_maskz ( ( __v8df ) __A , ( __v8df )


<s> bool <ISA_LIT>InstrInfo :: protectRegisterSpill ( unsigned Reg , const MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) .


<s> case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; std :: vector < MVT > NodeTys ; SDValue Ops [ <NUM_LIT> ] , Result , MFFSreg , InFlag , FPreg ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; MFFSreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Lo ; Ops [ <NUM_LIT> ] = Hi ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getShifter ( )


<s> int VecSize = VT . getSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; int Len = EltVT . getSizeInBits ( ) ; auto GetShift = [ & ] ( unsigned OpCode , SDValue V , int Shifter ) { MVT VT = V . getSimpleValueType ( ) ; SDValue ShifterV = DAG . getConstant ( Shifter , DL , VT ) ; return DAG . getNode ( OpCode , DL , VT , V , ShifterV ) ; } ; auto GetMask = [ & ] ( SDValue V , APInt Mask ) { MVT VT = V . getSimpleValueType ( ) ; SDValue MaskV = DAG . getConstant ( Mask , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V , MaskV ) ; } ; MVT SrlVT = Len > <NUM_LIT> ? VT : <STR_LIT> (


<s> for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr & MI = *


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM ,


<s> SDValue FIN = TailCallArgs [ i ] . FrameIdxOp ; int FI = TailCallArgs [ i ] . FrameIdx ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> ,


<s> if ( Lane == <NUM_LIT> ) { unsigned Wt = Ws ; if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT>


<s> uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind


<s> dbgs ( ) << <STR_LIT> ; Header -> dump ( ) ; dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; bool Changed = false ; ReductionList Reductions ; MatchReductions ( F , L , Header , Reductions ) ; for ( auto & R : Reductions ) { OpChainList MACCandidates ; MatchParallelMACSequences ( R , MACCandidates ) ; if ( ! CheckMACMemory ( MACCandidates ) ) continue ; R . MACCandidates = std :: move ( MACCandidates ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto & M : R . MACCandidates ) M -> Root -> dump ( ) ; dbgs ( ) << <STR_LIT> ; ) ; } Instructions Reads , Writes ; AliasCandidates ( Header , Reads , Writes ) ; for ( auto & R :


<s> if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = ( Amount < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand (


<s> Address ( ) : BaseType ( RegBase ) , Offset ( <NUM_LIT> ) { Base . Reg =


<s> static ArrayRef < MCPhysReg > get64BitArgumentXMMs ( MachineFunction & MF , CallingConv :: ID CallConv , const <ISA_LIT>Subtarget * Subtarget ) { assert ( Subtarget -> is64Bit ( ) ) ; if ( Subtarget -> isCallingConvWin64 ( CallConv ) ) { return None ; } const Function * Fn = MF . getFunction ( ) ; bool NoImplicitFloatOps = Fn -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool isSoftFloat = Subtarget -> useSoftFloat ( ) ; assert ( ! ( isSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( isSoftFloat || NoImplicitFloatOps || ! Subtarget -> hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return makeArrayRef ( std :: begin ( XMMArgRegs64Bit ) ,


<s> void onLT ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR


<s> AssemblerOptions . front ( ) -> setFeatures ( STI . getFeatureBits ( )


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && Register :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && Register :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; return nullptr ; } } if ( MI . isCopy ( ) && Ops . size ( ) == <NUM_LIT> && ( Ops [ <NUM_LIT> ] == <NUM_LIT> || Ops [ <NUM_LIT> ] == <NUM_LIT> ) ) { bool IsSpill = Ops [ <NUM_LIT> ] == <NUM_LIT> ; bool IsFill = ! IsSpill ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineOperand & DstMO = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; Register DstReg = DstMO . getReg ( ) ; Register SrcReg = SrcMO . getReg ( ) ; auto getRegClass = [ & ] ( unsigned Reg ) { return Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : TRI . getMinimalPhysRegClass ( Reg ) ; } ; if ( DstMO . getSubReg ( ) == <NUM_LIT> && SrcMO . getSubReg ( ) == <NUM_LIT> ) { assert ( TRI . getRegSizeInBits ( * getRegClass ( DstReg ) ) == TRI . getRegSizeInBits ( * getRegClass ( SrcReg ) ) && <STR_LIT> ) ; if ( IsSpill ) storeRegToStackSlot ( MBB , InsertPt , SrcReg , SrcMO . isKill ( ) , FrameIndex , getRegClass ( SrcReg ) , & TRI ) ; else loadRegFromStackSlot ( MBB , InsertPt , DstReg , FrameIndex , getRegClass ( DstReg ) , & TRI ) ; return & * -- InsertPt ; } if ( IsSpill && DstMO . isUndef ( ) && Register :: isPhysicalRegister ( SrcReg ) ) { assert ( SrcMO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * SpillRC ; unsigned SpillSubreg ; switch ( DstMO . getSubReg ( ) ) { default : SpillRC =


<s> unsigned int <ISA_LIT>AsmBackend :: getNumFixupKinds ( ) const { return <STR_LIT> ::


<s> SDValue getI32Imm ( unsigned Imm , const SDLoc &


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTblPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTblPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > SSE42CostTblNoPairWise [


<s> unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg


<s> unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return true


<s> return get_hard_reg_initial_val ( Pmode , GP_REGNO


<s> unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsNeedingCSDBBeforeUse . set ( * AI ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , Is64Bit ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) ) . addDef ( DstReg ) . addUse ( SrcReg , RegState :: Kill ) . addUse ( Is64Bit ? MisspeculatingTaintReg : MisspeculatingTaintReg32Bit ) . addImm ( <NUM_LIT> ) ; } MI . eraseFromParent ( ) ; return true ; } return


<s> switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_OR : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; const InstructionMapping & GPRMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getValueMapping ( PMI_FirstGPR , Size ) , <NUM_LIT> ) ; const InstructionMapping & FPRMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getValueMapping ( PMI_FirstFPR , Size ) , <NUM_LIT> ) ; AltMappings . push_back ( & GPRMapping ) ; AltMappings . push_back ( & FPRMapping ) ; return AltMappings ; } case TargetOpcode :: G_BITCAST : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; const InstructionMapping & GPRMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; const InstructionMapping & FPRMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; const InstructionMapping & GPRToFPRMapping = getInstructionMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; const InstructionMapping & FPRToGPRMapping = getInstructionMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; AltMappings . push_back ( & GPRMapping ) ; AltMappings . push_back ( & FPRMapping ) ; AltMappings . push_back (


<s> pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( n ) ) ; n = <NUM_LIT> ; set = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , restore_p ? size : - size ) ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; XVECEXP ( pattern , <NUM_LIT> , n ++ ) = set ; top_offset = restore_p ? size : <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nargs ; i ++ ) { offset = top_offset + i * UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , true , offset , GP_ARG_FIRST + i ) ; XVECEXP ( pattern , <NUM_LIT> , n ++ ) = set ; } offset = top_offset ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) { regno = mips16e_save_restore_regs [ i ] ; if ( BITSET_P ( * mask_ptr , regno


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> expandLoadStackGuard ( MI ) ; MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx


<s> bool <ISA_LIT>InstructionSelector :: selectUnmergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { if ( I . getOpcode ( ) != TargetOpcode :: G_UNMERGE_VALUES ) return false ; unsigned NumDefs = I . getNumOperands ( ) - <NUM_LIT> ; unsigned SrcReg = I . getOperand ( NumDefs ) . getReg ( ) ; unsigned DefSize = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) . addImm ( Idx * DefSize ) ; if ( ! select ( ExtrInst ) ) return false ; } I . eraseFromParent ( ) ; return


<s> SDValue <ISA_LIT>DAGToDAGISel :: GetVLDSTAlign ( SDValue Align , SDLoc dl , unsigned NumVecs , bool is64BitVector ) { unsigned NumRegs = NumVecs ; if ( ! is64BitVector && NumVecs <


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static enum unwind_info_type ia64_debug_unwind_info ( void ) { return UI_TARGET


<s> if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx , bool IsLittle ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) ,


<s> static bool isVUZP_v_undef_Mask ( const SmallVectorImpl < int > & M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned Half = VT . getVectorNumElements ( ) / <NUM_LIT> ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { unsigned Idx = WhichResult ; for ( unsigned i = <NUM_LIT> ; i != Half ; ++ i ) { if ( ( unsigned ) M [ i + j * Half ] != Idx ) return false ; Idx += <NUM_LIT>


<s> void Warning ( SMLoc L , const Twine & Msg


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return *


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes )


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRn ( insn ,


<s> VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false


<s> report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) )


<s> StringRef getPassName ( ) const override


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert (


<s> for ( unsigned i = <NUM_LIT> ; i != NumEntries - <NUM_LIT> ; ++ i ) if ( ! ( Table [ i ] < Table [ i + <NUM_LIT> ] ) ) return false ; return


<s> return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb

( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( )

-> getFunction ( ) -> getContext ( ) ) , Val ) ;


<s> AnnotationsInference ( ) : FunctionPass ( ID ) { initializeAnnotationsInferencePass ( * PassRegistry ::


<s> SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; } } return SDValue (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> MCSubtargetInfo & STI = copySTI ( ) ; std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name


<s> static bool DisassembleNVCVTFrm ( MCInst & MI , unsigned Opc , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { return DisassembleNVdVmOptImm ( MI , Opc , insn , NumOps ,

NumOpsAdded , N2V_VectorConvert_Between_Float_Fixed , B ) ;


<s> void DecodePSHUFMask ( unsigned NumElts , unsigned ScalarBits , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { unsigned Size = NumElts * ScalarBits ; unsigned NumLanes = Size /


<s> if ( isa < MemSDNode > ( Root ) ) return cast < MemSDNode > ( Root ) -> getMemoryVT ( ) ; const unsigned Opcode = Root -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; default : break ; } if ( Opcode != <STR_LIT> ) return EVT ( ) ; const unsigned IntNo = cast < ConstantSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return


<s> return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { Register ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false ,


<s> static void EmitCall ( MCStreamer & OutStreamer , MCOperand & Callee , const MCSubtargetInfo & STI ) { MCInst CallInst


<s> tree type , itype ; gcc_assert ( ( unsigned ) tcode < ARRAY_SIZE ( ix86_builtin_type_tab ) ) ; type = ix86_builtin_type_tab [ ( int ) tcode ] ; if ( type != NULL ) return type ; gcc_assert ( tcode > IX86_BT_LAST_PRIM ) ; if ( tcode <= IX86_BT_LAST_VECT ) { machine_mode mode ; index = tcode - IX86_BT_LAST_PRIM - <NUM_LIT> ; itype = ix86_get_builtin_type ( ix86_builtin_type_vect_base [ index ] ) ; mode = ix86_builtin_type_vect_mode [ index ] ; type = build_vector_type_for_mode ( itype , mode ) ; } else { int quals ; index = tcode - IX86_BT_LAST_VECT - <NUM_LIT> ; if ( tcode <= IX86_BT_LAST_PTR ) quals = TYPE_UNQUALIFIED ; else quals = TYPE_QUAL_CONST ; itype = ix86_get_builtin_type ( ix86_builtin_type_ptr_base [ index ] ) ; if ( quals != TYPE_UNQUALIFIED ) itype = build_qualified_type ( itype , quals ) ; type = build_pointer_type ( itype ) ; } ix86_builtin_type_tab [ ( int ) tcode


<s> return PICStyle == PICStyles :: StubDynamicNoPIC || PICStyle


<s> Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler ::


<s> bool isX32 = T . isX32 ( ) ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect =


<s> bool MatchInstruction ( SMLoc IDLoc , const SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCInst & Inst ) { if ( ! MatchInstructionImpl ( Operands , Inst


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> MachineInstr * <ISA_LIT>OptimizeLEAPass :: replaceDebugValue ( MachineInstr & MI , unsigned VReg , int64_t AddrDispShift ) { const DIExpression * Expr = MI . getDebugExpression ( ) ; if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable ( ) ; if ( IsIndirect ) assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> &&


<s> const MCExpr * getMemOff ( ) const { assert ( Kind == k_Memory && <STR_LIT> ) ; return Mem .


R0 == <STR_LIT> && R1 == <STR_LIT> ) ) return true ;


<s> case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ; return static_cast < <STR_LIT> > ( Instr . getOperand ( Idx - <NUM_LIT> ) . getImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ; return static_cast < <STR_LIT> > ( Instr . getOperand ( Idx - <NUM_LIT> ) .


<s> bool needGPSaveRestore ( ) const { return getGPFI (


<s> bool <ISA_LIT>InstrInfo :: findFMA3CommutedOpIndices ( MachineInstr & MI , bool IsIntrinOpcode , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { unsigned RegOpsNum = isMem ( MI , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < <NUM_LIT> || SrcOpIdx1 > RegOpsNum ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < <NUM_LIT> || SrcOpIdx2 > RegOpsNum ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 =


<s> return ( __m128h ) __builtin_ia32_vfmaddcsh_round ( ( __v8hf ) __A , ( __v8hf ) __B , (


<s> if ( Triple ( TT ) . isOSNaCl ( ) ) return

new NaCl<ISA_LIT>AsmBackend ( T , true ) ;


<s> DebugLoc DL ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Reg = <NUM_LIT> ; if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ||


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return

( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , DAG ) ;


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> else if ( Val < <NUM_LIT> && Val >= - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( - Val ) . setMIFlag ( Flag ) ; else report_fatal_error ( <STR_LIT>


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O ,


<s> SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy . getSizeInBits ( ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , ValTy , Shl . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SMPos0 , <STR_LIT> ) ,

DAG . getConstant ( SMSize0 , <STR_LIT> ) , And0 . getOperand ( <NUM_LIT> ) ) ;


<s> Out . EmitBundleLock ( true ) ; MCInst CALLInst ; CALLInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; CALLInst . addOperand ( Op ) ; Out . EmitInstruction ( CALLInst ) ; Out . EmitBundleUnlock


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : ( NumVecs == <NUM_LIT> ) ? QOpcodes0 [ OpcodeIndex ] : QOpcodes1 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( IsImmUpdate ) { if ( ! isVLDfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } else { if ( isVLDfixed ( Opc ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } } if ( is64BitVector || NumVecs == <NUM_LIT> ) { } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; } else { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , <STR_LIT> , OpsA ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Chain = SDValue ( VLdA , <NUM_LIT>


<s> <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( <NUM_LIT> ) ; } if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is<ISA_LIT>64 ( ) || TM . getRelocationModel ( ) != Reloc :: PIC_ ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; if ( M . getPICLevel ( ) == PICLevel :: SmallPIC ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCSymbol * CurrentPos = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( CurrentPos ) ; const MCExpr * tocExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( CurrentPos , OutContext ) , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitAssignment ( TOCSym , tocExpr ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) .


<s> reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * <NUM_LIT> ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) =


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; TrapInfo TI = cast < GlobalAddressSDNode > ( Op ) -> getTrapInfo ( ) ; return LowerGlobalAddress ( GV , SDLoc ( Op ) , Offset , TI ,