<s> int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . count ( WaterBB ) ) { NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) ,


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getSjLjDispatchPreservedMask ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . useSoftFloat ( ) && STI . hasVFP2Base ( ) && ! STI . isThumb1Only (


<s> unsigned TrueReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCValid = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI


<s> static bool shouldPromote ( Value * V ) { if ( ! isa < IntegerType > ( V -> getType ( ) ) || isSink ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V <<


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_TLSLDM : Type = ELF :: R_<ISA_LIT>_TLS_LDM32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_MOVT_BREL ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_MOVW_ABS_NC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_MOVW_BREL_NC ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_THM_MOVT_ABS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_THM_MOVT_BREL ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_THM_MOVW_ABS_NC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_THM_MOVW_BREL_NC ; break ; } break ; } } return Type


<s> Value * <ISA_LIT>IREmitter :: visitVPERMI (


<s> bool isGPRNonZeroAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_GPR && RegIdx .

Index > <NUM_LIT> && RegIdx . Index <= <NUM_LIT> ;


<s> if ( isThumb2 ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs


<s> return __builtin_ia32_comige ( ( __v4sf ) __A ,


<s> void DecodePUNPCKLWDMask ( unsigned NElts , SmallVectorImpl


<s> return ( __m128i ) __builtin_ia32_expandloadqi128_maskz ( ( const __v16qi * ) __B , ( __v16qi ) _mm_setzero_si128 ( ) , ( __mmask16


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiPart , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ; if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DL , PtrVT ) , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi


<s> assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( MFI -> hasVarSizedObjects ( ) && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else FrameReg = RegInfo -> getBaseRegister ( ) ; } else if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister


<s> switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SmallVector < MachineMemOperand * , <NUM_LIT> > MMOs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; Register ZReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned XorRROpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , MI , DL , TII -> get ( XorRROpc ) ) . addDef ( ZReg ) . addReg ( ZReg , RegState :: Undef ) . addReg ( ZReg , RegState :: Undef ) ; Register SSPCopyReg = MRI . createVirtualRegister ( PtrRC


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned BasePtr = RegInfo -> getBaseRegister ( ) ; NumBytes = ( NumBytes + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & )


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) ==

Triple :: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> return ( ( vec_double2 ) ( si_dfnms ( ( qword ) ( a ) , ( qword ) ( b ) ,


<s> unsigned Bytes = Arg . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI !=


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM . isPositionIndependent


<s> } else if ( flag_delayed_branch ) { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_INCOMING_INT_ARG_FIRST ; } else { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } if ( TARGET_ARCH64 && aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , int_arg_first + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , int_arg_first ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! SPARC_SIMM13_P ( delta ) ) { rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ] && vcall_offset < - <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch2 , vcall_offset_rtx ) ; vcall_offset_rtx = scratch2 ; } else { rtx increment = GEN_INT ( - <NUM_LIT> ) ; while ( ! SPARC_SIMM13_P ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch , increment ) ) ; vcall_offset += <NUM_LIT> ; } vcall_offset_rtx = GEN_INT ( vcall_offset ) ; } emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , scratch , vcall_offset_rtx ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ; start_sequence ( )


<s> return GuaranteedTailCallOpt && IsTailCallConvention ( CC


<s> MCRelocationInfo * llvm :: create<ISA_LIT>_64MachORelocationInfo ( MCContext & Ctx ) { return new <ISA_LIT>_64MachORelocationInfo ( Ctx


<s> bool Filler :: searchBackward ( MachineBasicBlock & MBB , Iter Slot ) const { if ( DisableBackwardSearch ) return false ; RegDefsUses RegDU ( TM ) ; MemDefsUses MemDU ( MBB . getParent ( ) -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot


<s> unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = Subtarget . hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; assert ( ( ! MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> mustSaveTOC ( ) || ( Reg != <STR_LIT> && Reg != <STR_LIT> ) ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( I ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( I ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( I ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( I ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound =


<s> int arg_mode , regno ; rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( use , <NUM_LIT> ) ) ; if ( regno >= <NUM_LIT> &&


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsic_u64 ( unsigned long long __X ) { return ~ __X | ( __X - <NUM_LIT>


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction &


( __v4di ) __C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true


<s> } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> case <STR_LIT> : { if ( auto * ConstVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( ConstVal -> isZero ( ) ) return Op ; if ( ConstVal -> isOne ( ) ) return getPTrue ( DAG , dl , VT , <STR_LIT> ) ; } SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : report_fatal_error ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> return Kind == k_ShiftedImmediate && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> unsigned Opc = isSub ? ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) : ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset )


<s> if ( ! Subtarget -> is64Bit ( ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , OVFIN , FIN , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store


<s> return getSTI ( ) . getFeatureBits (


<s> if ( ! DCI . isBeforeLegalizeOps ( ) ) { if ( InVT == <STR_LIT> ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( Subtarget . hasAVX ( ) && VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteSextBeforeAddNSW ( N , DAG , Subtarget ) ) return NewAdd ; return SDValue ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SecondaryVCTPs . insert ( MI ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; VCTP = MI ; } } else if ( isVPTOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOpcode ( ) != <STR_LIT> ) { assert ( MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> && <STR_LIT> ) ; CurrentPredicate . insert ( MI ) ; } VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI


<s> static void LowerUnaryToTwoAddr ( MCInst & OutMI , unsigned NewOpc ) { OutMI . setOpcode ( NewOpc ) ; OutMI . addOperand ( OutMI . getOperand ( <NUM_LIT> ) ) ; OutMI . addOperand ( OutMI .


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter ) ; if ( RelaxAll ) S -> getAssembler (


<s> unsigned reg = <NUM_LIT> ; if ( Compare . isCompare ( ) ) reg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( isLoadAndTestAsCmp ( Compare ) ) reg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert (


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Context = & funcInfo . Fn -> getContext (


<s> if ( ! isLoadTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; SrcReg = getRegForValue ( Op0 ) ; if ( SrcReg == <NUM_LIT> ) return false ; Address Addr ; if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; if ( ! emitStore ( VT , SrcReg , Addr , cast < StoreInst > (

I ) -> getAlignment ( ) ) ) return false ;


<s> MVT ResVT = Op . getValueType ( ) . getSimpleVT ( ) ; assert ( ( ResVT . is256BitVector ( ) || ResVT . is512BitVector ( ) ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements (


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) { printf ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState


<s> if ( ! N . hasOneUse ( ) || ! U -> hasOneUse ( ) ) return false ; SDNode * CCUser = * U -> use_begin ( ) ; SDNode * CCRegUser = nullptr ; if ( CCUser -> getOpcode ( ) == <STR_LIT> || cast < RegisterSDNode > ( CCUser -> getOperand ( <NUM_LIT> ) ) -> getReg ( )


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups , STI ) ; assert ( ( ( Imm8 & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; uint32_t Binary = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg


<s> for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { CurBit ^= ( Val >> i ) & <NUM_LIT> ; Imm |= ( CurBit << i ) ; if ( ( Val & ~ ( ~ <NUM_LIT> << i ) ) == <NUM_LIT> ) { Imm |= <NUM_LIT> << i ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm )


<s> ++ RI ; assert ( RI -> getOpcode ( ) == <STR_LIT> && RI -> getOperand ( <NUM_LIT> ) . isReg ( ) && RI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && RI -> getOperand ( <NUM_LIT> ) . isReg ( ) && RI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; ++ RI ; MachineBasicBlock :: instr_iterator FI ( RI . base ( ) ) ; MBB . splice ( std :: next ( I ) , & MBB , FI , I ) ; FilledSlots += <NUM_LIT> ; } else { if ( ! NopDelaySlotFiller && findDelayInstr ( MBB ,


<s> void <ISA_LIT>ATTInstPrinter :: printMemOffset ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & DispSpec = MI -> getOperand ( Op ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , LHSIsKill , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT


<s> unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI ,


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> if ( is64Bit ) PointerSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; SupportsDebugInformation = true ; DwarfUsesInlineInfoSection = true ; ExceptionsType = ExceptionHandling


<s> void <ISA_LIT>ConditionalCompares :: updateDomTree ( ArrayRef < MachineBasicBlock * > Removed ) { MachineDomTreeNode * HeadNode = DomTree -> getNode ( CmpConv . Head ) ; for ( MachineBasicBlock * RemovedMBB : Removed ) { MachineDomTreeNode * Node = DomTree -> getNode ( RemovedMBB ) ; assert ( Node != HeadNode && <STR_LIT> ) ; assert ( Node -> getIDom ( )


<s> return ( ( qword ) ( vec_mulo ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) ,


<s> unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize % <NUM_LIT> == <NUM_LIT> ) ) return Factor * ( ( SubVecSize + <NUM_LIT> ) / <NUM_LIT> ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment ,


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> assert ( Last . getParent ( ) == First . getParent ( ) && <STR_LIT> ) ; assert ( InstrPos . find ( & First ) != InstrPos . end ( ) &&

InstrPos . find ( & Last ) != InstrPos . end ( ) && <STR_LIT> ) ;


<s> if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; SmallVector < const SDNode * , <NUM_LIT> > Worklist ; Visited . insert ( Addr . getNode ( ) ) ; Worklist . push_back


<s> invert = true ; break ; case GT : case LT : case LE : if ( op1 == CONST0_RTX ( mode ) && TARGET_SUPPORT_FPV2 ) op1 = force_reg ( mode , op1 ) ; break ; case ORDERED : code = UNORDERED ; invert = true ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 )


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo

:: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_insensitive ( <STR_LIT> ) ) ) return parseDirectiveSEHPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_insensitive ( <STR_LIT> ) ) ) return parseDirectiveSEHSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_insensitive ( <STR_LIT> ) ) ) return parseDirectiveSEHSaveReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_insensitive ( <STR_LIT> ) ) ) return parseDirectiveSEHSaveXMM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_insensitive ( <STR_LIT> ) ) ) return parseDirectiveSEHPushFrame ( DirectiveID .


<s> MI . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag ::


<s> if ( ! Subtarget -> is64Bit ( ) || Subtarget -> isTargetWin64 ( ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } unsigned PointerSize = TD -> getPointerSize ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( PointerSize ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , RSFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> + PointerSize ) , false , false , <NUM_LIT> ) ; MemOps . push_back (


<s> return ( __m256i ) __builtin_ia32_pmovsdw512_mask ( ( __v16si ) __A , (


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI -> eraseFromParent ( ) ; return BB


<s> } if ( ! CheckPreds && Preds . empty ( ) ) return true ; if ( CheckPreds ) { queue_preds : if ( MachineFunction :: iterator ( MBB ) == MBB -> getParent ( ) -> begin ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << BI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } for ( MachineBasicBlock :: pred_iterator PI = MBB -> pred_begin ( ) , PIE = MBB -> pred_end ( ) ; PI != PIE ; ++ PI ) Preds . push_back ( * PI ) ; } do { MBB = Preds . pop_back_val


<s> NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( isThumb ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( NewBB ) ; NumSplit ++ ; while ( ! OrigBB -> succ_empty ( ) ) { MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || Succ -> begin ( ) -> getOpcode ( ) != TargetInstrInfo :: PHI ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; std :: vector < MachineBasicBlock * > :: iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E =


<s> DCRegisterSema :: FinalizeBasicBlock


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; bool HasFP = TFI -> hasFP ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) && needsStackRealignment ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; } else { if ( ! HasFP || ( needsStackRealignment ( MF ) && FrameIndex >= <NUM_LIT> ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; FrameReg = getFrameRegister ( MF ) ; if ( FrameIndex >= <NUM_LIT> ) { if ( hasBasePointer ( MF ) ) FrameReg = getBaseRegister ( ) ; else if ( needsStackRealignment ( MF ) ) FrameReg = <STR_LIT> ; } } if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! Reg ) Reg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( Reg && <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( ( uint32_t ) Offset >> <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( Offset & <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addReg ( FrameReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( Reg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) .


<s> for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = SI -> second ; return true ; } break ; } } if ( Addr . Base . Reg == <NUM_LIT> ) Addr . Base . Reg


<s> static inline __ev64_opaque__ __internal_ev_mwhusiaaw ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhumi ( a ,


<s> BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( MI ) ; ++ MI ; } skipNonTerminators ( Position , Block ) ; while ( MI != End ) { if ( ! MI -> isDebugValue ( ) ) { assert ( MI -> isTerminator ( ) && <STR_LIT> ) ; Terminators . push_back ( describeTerminator ( MI ) ) ; skipTerminator ( Position , Terminators . back


<s> case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q


<s> if ( ( Head == <STR_LIT> || Head == <STR_LIT> ) && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , SuffixLoc , getContext ( ) , true ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , NameLoc , NameLoc , getContext ( ) ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , SuffixLoc , getContext ( ) , true ) ) ; } bool condCodeFourthOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeSecondOperand = ( Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeThirdOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { unsigned N = <NUM_LIT> ; do { if ( parseOperand ( Operands , ( N == <NUM_LIT> && condCodeFourthOperand ) || ( N == <NUM_LIT> && condCodeThirdOperand ) || ( N == <NUM_LIT> && condCodeSecondOperand ) , condCodeSecondOperand || condCodeThirdOperand ) ) { return true ; } if ( parseOptionalToken ( AsmToken :: RBrac ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; if ( parseOptionalToken ( AsmToken :: Exclaim ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; if ( parseOptionalToken ( AsmToken :: RCurly ) ) Operands . push_back ( <ISA_LIT>Operand ::


<s> bool CanNegateL ; bool MustBeFirstL ; bool ValidL = canEmitConjunction ( LHS , CanNegateL , MustBeFirstL , IsOR ) ; assert ( ValidL && <STR_LIT> ) ; ( void ) ValidL ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateR ; bool MustBeFirstR ; bool ValidR = canEmitConjunction ( RHS , CanNegateR , MustBeFirstR , IsOR ) ; assert ( ValidR && <STR_LIT> ) ; ( void ) ValidR ; if ( MustBeFirstL ) { assert ( ! MustBeFirstR && <STR_LIT> ) ; std :: swap ( LHS , RHS ) ; std :: swap ( CanNegateL , CanNegateR ) ; std :: swap ( MustBeFirstL , MustBeFirstR ) ; } bool NegateR ; bool NegateAfterR ; bool NegateL ; bool NegateAfterAll ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL ) { assert ( CanNegateR && <STR_LIT> ) ; assert ( ! MustBeFirstR && <STR_LIT> ) ; assert ( ! Negate ) ; std :: swap ( LHS , RHS ) ; NegateR = false ; NegateAfterR = true ; } else { NegateR = CanNegateR ; NegateAfterR = ! CanNegateR ; } NegateL = true ; NegateAfterAll = ! Negate ; } else { assert ( Opcode == <STR_LIT> && <STR_LIT> ) ; assert ( ! Negate && <STR_LIT> ) ; NegateL = false ; NegateR = false ; NegateAfterR = false ; NegateAfterAll = false ; } <STR_LIT> RHSCC ; SDValue CmpR = emitConjunctionRec ( DAG , RHS , RHSCC , NegateR , CCOp , Predicate ) ; if ( NegateAfterR ) RHSCC = <STR_LIT> ( RHSCC ) ; SDValue CmpL = emitConjunctionRec ( DAG , LHS , OutCC , NegateL , CmpR , RHSCC ) ; if ( NegateAfterAll ) OutCC = <STR_LIT>


<s> if ( isX87Reg ( MO . getReg ( ) ) ) return true ; } return


<s> switch ( ID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : \


<s> unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return


<s> SDValue CCVal = DAG . getConstant ( OFCC , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , CCVal , Overflow ) ; } if ( LHS . getValueType ( ) . isInteger ( ) ) { assert ( ( LHS . getValueType ( ) == RHS . getValueType ( ) ) && ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ) ; const ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> && ProduceNonFlagSettingCondBr ) { if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t SignBitPos


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode , HOST_WIDE_INT offset ) { return ( offset >= <NUM_LIT> && offset < <NUM_LIT> * GET_MODE_SIZE ( mode ) && offset % GET_MODE_SIZE ( mode


<s> Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc ,


<s> static bool ix86_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( must_pass_in_stack_var_size_or_pad ( mode , type ) ) return true ; return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) !=


<s> for ( unsigned i = StartIdx ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( std :: find ( Ops . begin ( ) , Ops . end ( ) , i ) != Ops . end ( ) ) { MIB . addOperand ( MachineOperand :: CreateImm ( StackMaps :: IndirectMemRefOp ) ) ; MIB . addOperand ( MachineOperand :: CreateFI


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT = TLI . getValueType ( SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; unsigned ResultReg = <NUM_LIT> ; bool IsZExt = isa < ZExtInst > ( I ) ; if ( const auto * Arg = dyn_cast < Argument > ( Src ) ) { if ( ( IsZExt && Arg -> hasZExtAttr ( ) ) || ( ! IsZExt && Arg -> hasSExtAttr ( ) ) ) { if ( DestVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } else ResultReg = SrcReg ; } } if ( ! ResultReg ) ResultReg = emitIntExt ( SrcVT , SrcReg , DestVT , IsZExt ) ; if ( ! ResultReg ) return false ; updateValueMap ( I ,


<s> } } if ( ConvertToUses . empty ( ) ) return false ; const auto * PTrueVTy = cast < ScalableVectorType > ( PTrue -> getType ( ) ) ; for ( IntrinsicInst * ConvertToUse : ConvertToUses ) { for ( User * User : ConvertToUse -> users ( ) ) { auto * IntrUser = dyn_cast < IntrinsicInst > ( User ) ; if ( IntrUser && IntrUser -> getIntrinsicID ( ) == <STR_LIT> ) { const auto * IntrUserVTy = cast < ScalableVectorType > ( IntrUser -> getType (


<s> static unsigned HOST_WIDE_INT aarch64_shift_truncation_mask ( machine_mode mode ) { if ( ! SHIFT_COUNT_TRUNCATED || aarch64_vector_data_mode_p ( mode ) ) return <NUM_LIT> ; return GET_MODE_UNIT_BITSIZE ( mode ) -


<s> unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && ( Op . isKill ( ) || getFPReg ( Op ) == FirstFPRegOp || MI -> killsRegister ( Op . getReg ( ) ) ) && <STR_LIT> ) ; if ( FirstFPRegOp == ~ <NUM_LIT> ) FirstFPRegOp = getFPReg ( Op ) ; else { assert ( SecondFPRegOp == ~ <NUM_LIT> && <STR_LIT> ) ; SecondFPRegOp = getFPReg ( Op ) ; } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI -> RemoveOperand ( i ) ; -- i ; -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) &&


<s> if ( ( AddcNode -> getOpcode ( ) == <STR_LIT> ) && ( AddeNode -> getOpcode ( ) == <STR_LIT> ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == AddcNode ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand

( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) } ) ;


<s> void expand_df_binop ( rtx ( * fun ) ( rtx , rtx , rtx , rtx ) , rtx * operands ) { emit_df_insn ( ( * fun ) ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , get_fpscr_rtx (


<s> return ( __m64 ) __builtin_arm_wcmpgtsw ( ( __v2si ) __m1 , ( __v2si )


<s> if ( ! RelocOp ) { FinalSize += sizeConstant ( <NUM_LIT> ) ; return FinalSize ; } if ( RelocOp -> isGlobal ( ) ) { FinalSize += sizeGlobalAddress ( false ) ; } else if ( RelocOp -> isCPI ( ) ) { FinalSize += sizeConstPoolAddress ( false ) ; } else if ( RelocOp -> isJTI ( ) ) { FinalSize += sizeJumpTableAddress (


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I !=

E ; ++ I ) Modified |= ReduceMBB ( * I ) ;


<s> DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) )


<s> if ( Op . getOpcode ( ) != <STR_LIT> || Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; auto Move = N -> use_begin ( ) ; if ( Move -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; SDValue Copy = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Ops ) ; DAG . ReplaceAllUsesWith ( * Move , & Copy ) ; return Copy ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; auto ZeroExtend = N -> use_begin ( ) ; if ( N -> use_size ( ) != <NUM_LIT> || ZeroExtend -> getOpcode ( ) != <STR_LIT> || ZeroExtend -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; auto Copy = ZeroExtend -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> && Copy -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op


<s> isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( Target . isIntrinsic ) { VecTy = N -> getOperand ( Target . AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( Target . isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } bool isVLDDUPOp = NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp || isVLDDUPOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && User . ConstInc != NumBytes ) { return false ; } if ( SimpleConstIncOnly && User . ConstInc != NumBytes ) return false ; EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment ( ) ; if ( isa < LSBaseSDNode > ( N ) ) { if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } Alignment = <NUM_LIT> ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoadOp ? NumVecs :


<s> auto * Ld = cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( ! Subtarget . hasAVX ( ) && ! Subtarget . hasSSEUnalignedMem ( ) && Ld -> getValueSizeInBits ( <NUM_LIT> ) == <NUM_LIT> && Ld -> getAlignment ( ) < <NUM_LIT> ) return false ; return


<s> static rtx gen_frame_store ( rtx reg ,


<s> if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG


<s> EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal (


<s> return ( uint16x8_t ) __builtin_neon_vsli_nv8hi ( ( int16x8_t ) __a , ( int16x8_t )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT>


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bextr_u32 ( unsigned int __X , unsigned int __Y ,


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isTargetCygMing ( ) || ST . isTargetWindows ( ) || ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) ; else if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret


<s> O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; } if ( ! printAliasInstr ( MI , Address , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case


<s> Value * <ISA_LIT>IREmitter :: visitVLD4_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> MachineInstr * findMIFromReg ( unsigned Reg , unsigned Opc , MachineIRBuilder & MIB ) const { auto * Def = MIB . getMRI ( ) -> getVRegDef ( Reg ) ; if ( ! Def || Def -> getOpcode (


<s> bool IsIndirectCall ; if ( isCall ( Inst . getOpcode ( ) , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitMask ( TargetReg , IndirectBranchMaskReg , STI ) ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; PendingCall = true ; return ; } if ( PendingCall ) { <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; EmitBundleUnlock ( ) ; PendingCall = false ; return ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI )


<s> void addRegCRBITRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( CRBITRegs


<s> return known_ge ( cfun -> machine -> frame .


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum )


<s> unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true


<s> Triple triple ( TT ) ; bool isThumb = triple . getArch ( ) == Triple :: thumb || triple . getArch ( ) == Triple :: thumbeb ; bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; switch ( triple . getSubArch ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: <ISA_LIT>SubArch_v8 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v8_1a : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7em : if ( NoCPU )


<s> else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else printRegName ( O , Reg ) ; } else printRegName ( O , Reg ) ; return ; } if ( MO . isImm ( ) ) { uint64_t TSFlags = MII . get ( MI -> getOpcode ( ) ) . TSFlags ; if ( ( ( TSFlags & <STR_LIT> ) != <STR_LIT> ) && PrintBranchImmAsAddress ) O << formatHex (


<s> static bool isPSHUFLWMask ( ArrayRef < int > Mask , EVT VT ) { if ( VT != <STR_LIT>


<s> return new <ISA_LIT>DiscriminateMemOps (


<s> typedef typename std :: make_signed < T > :: type SignedT ; typedef typename std :: make_unsigned < T > :: type UnsignedT ; uint64_t Val = MI -> getOperand ( OpNum ) .


<s> for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * NewMI = nullptr ; MachineInstr * MI = & * I ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; } break ; case <STR_LIT> : NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case <STR_LIT> : case <STR_LIT> : NewMI = tryReplaceCopy ( MI )


<s> op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; target = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; aarch64_cond = aarch64_get_condition_code_1 ( cc_mode , ( rtx_code ) cmp_code ) ; if ( bit_code != AND ) { rtx_code prev_code = GET_CODE ( prev ) ; machine_mode prev_mode = GET_MODE ( XEXP ( prev , <NUM_LIT> ) ) ; if ( ( prev_mode == CCFPmode || prev_mode == CCFPEmode ) && ! ( prev_code == EQ || prev_code == NE || prev_code == ORDERED || prev_code == UNORDERED ) ) icode = code_for_ccmp_rev ( cc_mode , cmp_mode ) ; else { rtx_code code = reverse_condition ( prev_code ) ; prev = gen_rtx_fmt_ee ( code , VOIDmode , XEXP ( prev , <NUM_LIT> ) , const0_rtx ) ; } aarch64_cond = AARCH64_INVERSE_CONDITION_CODE ( aarch64_cond ) ; } create_fixed_operand ( & ops [ <NUM_LIT> ] , XEXP ( prev , <NUM_LIT> ) ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , target ) ; create_fixed_operand ( & ops [


<s> byval_iterator byval_end ( ) const { return ByValArgs .


<s> raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT>


<s> if ( isLegalAddressImm ( Opcode , Imm , TII ) ) return true ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; switch (


<s> * popno0 = <NUM_LIT> ; * popno1 = <NUM_LIT> ; } op0 = operands [ <NUM_LIT> ] ; op1 = operands [ <NUM_LIT> ] ; break ; case MODRM_CLASS_OP01 : gcc_assert ( noperands >= <NUM_LIT> ) ; if ( popno0 ) { * popno0 = <NUM_LIT> ; * popno1 = <NUM_LIT> ; } op0 = operands [ <NUM_LIT> ] ; op1 = operands


<s> Op -> RotImm . Imm = Imm ; Op -> StartLoc = S ; Op -> EndLoc


<s> SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT>

? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;


<s> if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , false , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; initAsmInfo (


<s> SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( )


<s> initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs (


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction (


<s> HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment = <NUM_LIT> ; MaxInlineSizeThreshold = <NUM_LIT> ; UseSoftFloat =


<s> getDebugValueLocation ( const MachineInstr * MI ) const { llvm_unreachable ( <STR_LIT>


<s> MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT>


<s> if ( getT2SOImmValSplatVal ( V ) != - <NUM_LIT> ) return false ; V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( V ) ) & V ; if ( V == <NUM_LIT> ) return false ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; V =


<s> const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy


<s> if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned s = <NUM_LIT> ; s < NumLanes ; ++ s ) { unsigned Start = s * NumLaneElts


<s> static SDValue PerformADDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Result = PerformADDCombineWithOperands ( N , N0


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass (


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG ,


<s> machine_mode mode = GET_MODE ( op ) ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , <NUM_LIT> ) , SVE_BYTE_MODE

, false , ADDR_QUERY_ANY ) || addr . type != ADDRESS_REG_IMM ) return false ;


<s> unsigned getRsaSize ( void ) const { return


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB ,


<s> OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> )

: CurDAG -> getTargetConstant ( - RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( ! isShuffleMaskConsecutive ( SVOp , <NUM_LIT> , NumElems - NumZeros , NumZeros , NumElems , OpSrc ) ) return false ; isLeft = false ; ShAmt = NumZeros ; ShVal = SVOp ->


<s> void <ISA_LIT>ExpandPseudo :: ExpandVLD ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++


<s> unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize (


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize =


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT>


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_i ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm


<s> bool <ISA_LIT>BaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I ->


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> ,


<s> static unsigned getPreIndexedLoadStoreOpcode ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ;


<s> static bool ArgsAreStructReturn ( SDValue Op ) { unsigned NumArgs = Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ; if ( ! NumArgs ) return false ; return cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getArgFlags ( ) . isSRet


<s> SDValue <ISA_LIT>TargetLowering :: getRsqrtEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps , bool & UseOneConstNR ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) { RefinementSteps = Subtarget . hasRecipPrec ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( VT . getScalarType ( ) == <STR_LIT> ) ++ RefinementSteps ; UseOneConstNR =


<s> MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! Src1Ty . isVector ( ) || ! Src2Ty . isVector ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned BytesPerElt = DstTy . getElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < Constant * , <NUM_LIT> > CstIdxs ; for ( int Val : Mask ) { Val = Val < <NUM_LIT> ? <NUM_LIT> : Val ; for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg ,


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] <


<s> struct pic_chain * chain ; if ( aof_pic_chain == NULL ) return ; asm_fprintf ( f , <STR_LIT> , PIC_OFFSET_TABLE_REGNUM , PIC_OFFSET_TABLE_REGNUM ) ; fputs ( <STR_LIT> ,


<s> return __builtin_ia32_vcvtsh2ss_mask_round ( __B , __A , _mm_setzero_ps ( ) , ( __mmask8 ) -


<s> rtx d = const_double_from_real_value ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = const_double_from_real_value ( dconst , SFmode ) ; rtvec v = gen_rtvec ( <NUM_LIT> , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = const_double_from_real_value ( dconst , DFmode ) ; rtvec v = gen_rtvec ( <NUM_LIT> , d , d


<s> warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } else if ( compare_tree_int ( cst , REGPARM_MAX ) > <NUM_LIT> ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) , REGPARM_MAX ) ; * no_add_attrs = true ; } return NULL_TREE ; } if ( TARGET_64BIT ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; return NULL_TREE ; } if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } } else if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } } else if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node )


<s> if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( AddcNode == HiAdd -> getNode ( ) || AddcNode -> isPredecessorOf ( HiAdd -> getNode ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) ,


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) )


<s> Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler ::


<s> for ( unsigned i = <NUM_LIT> ; i != NElts ;


<s> GetUnderlyingObjects ( const_cast < Value * > ( V ) , Objs ) ; for ( SmallVectorImpl < Value * > :: iterator I = Objs . begin ( ) , E = Objs . end ( ) ; I != E ; ++ I ) { if ( const PseudoSourceValue * PSV = dyn_cast < PseudoSourceValue > ( * I ) ) { if ( PSV -> isAliased ( MFI ) ) return false ; } else if ( ! isIdentifiedObject ( V ) ) return false ; Objects . push_back (


<s> static MachineInstr * FuseInst ( MachineFunction & MF , unsigned Opcode , unsigned OpNo , ArrayRef < MachineOperand > MOs , MachineBasicBlock :: iterator InsertPt , MachineInstr * MI , const TargetInstrInfo & TII ) { MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) &&


<s> } printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> static bool isFPCopy ( MachineInstr & MI ) { unsigned DstReg = MI . getOperand ( <NUM_LIT>


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT>


<s> static char * aarch64_offload_options ( void ) { if ( TARGET_ILP32 ) return xstrdup ( <STR_LIT> ) ; else return xstrdup


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const


<s> void <ISA_LIT>AsmParser :: SetFrameRegister ( unsigned RegNo ) { Instrumentation -> SetInitialFrameRegister (


<s> case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case


<s> return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && REGNO ( addr . reg ) == STACK_POINTER_REGNUM && uw5_operand ( addr . offset


<s> if ( Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Narrow -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Narrow -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Narrow ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT WideVT = N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( WideVT != VT ) return SDValue ( ) ; bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> ; bool RHSConst = ( isSplatVector ( N1 . getNode ( ) ) && isa < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) ; if ( ! RHSTrunc && ! RHSConst ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , WideVT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT>


_mm256_setzero_ph ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> static DecodeStatus DecodeThumbAddrModePC ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; tryAddingPcLoadReferenceComment ( Address , ( Address & ~ <NUM_LIT> ) + imm + <NUM_LIT> , Decoder ) ; return MCDisassembler ::


<s> case <STR_LIT> : case <STR_LIT> : DecodeUNPCKLPMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( NumElems , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned OpNum = ( Index == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return getShuffleScalarElt ( V . getOperand ( OpNum ) . getNode ( ) , Index , DAG , Depth + <NUM_LIT> ) ; } default : assert ( <STR_LIT> ) ; return SDValue ( ) ; } Index = ShuffleMask [ Index ] ; if ( Index < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; SDValue NewV = ( Index < NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Index % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { V = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = V . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT .

getVectorNumElements ( ) != NumElems ) return SDValue ( ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode =


<s> unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , F ) && ! ( Size <= <NUM_LIT> && allUsersAreInFunctions ( GVar ) ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , <NUM_LIT>


<s> return true ; } } return false ; } ; struct ImmCompare { MachineInstr * MI = nullptr ; unsigned NewOpc = <NUM_LIT> ; } ; auto FindCmpForCBZ = [ this ] ( ImmBranch & Br , ImmCompare & ImmCmp , MachineBasicBlock * DestBB ) { ImmCmp . MI = nullptr ; ImmCmp . NewOpc = <NUM_LIT> ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) return false ; Register PredReg ; unsigned NewOpc = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; unsigned BrOffset = BBUtils -> getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset >= DestOffset || ( DestOffset - BrOffset ) > <NUM_LIT> ) return false ; auto * TRI = STI -> getRegisterInfo ( ) ; MachineInstr * CmpMI = findCMPToFoldIntoCBZ ( Br . MI , TRI ) ; if ( ! CmpMI || CmpMI -> getOpcode ( ) != <STR_LIT> ) return false ; ImmCmp . MI = CmpMI ; ImmCmp . NewOpc = NewOpc ; return true ; } ; auto TryConvertToLE = [ this ] ( ImmBranch & Br , ImmCompare & Cmp ) { if ( Br . MI -> getOpcode ( ) != <STR_LIT> || ! STI -> hasLOB ( ) || STI -> hasMinSize ( ) ) return false ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBUtils -> getOffsetOf ( MBB ) < BBUtils -> getOffsetOf ( DestBB ) || ! BBUtils -> isBBInRange ( Br . MI , DestBB , <NUM_LIT> ) ) return false ; if ( ! DT -> dominates ( DestBB , MBB ) ) return false ; Cmp . NewOpc = Cmp . NewOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , Br . MI , Br . MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( Br . MI -> getOperand ( <NUM_LIT> ) ) ; Br . MI -> eraseFromParent ( ) ; Br . MI


<s> if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . addOperand ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) .

addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ;


<s> DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , <NUM_LIT> ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( )


<s> inline const MachineInstrBuilder & addLeaOffset ( const MachineInstrBuilder & MIB


<s> static bool removeIPMBasedCompare ( MachineInstr & Compare , unsigned SrcReg , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI ) { MachineInstr * LGFR = nullptr ; MachineInstr * RLL = getDef ( SrcReg , MRI ) ; if ( RLL && RLL -> getOpcode ( ) == <STR_LIT> ) { LGFR = RLL ; RLL = getDef ( LGFR -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; } if ( ! RLL || ! isShift ( RLL , <STR_LIT>


<s> if ( TARGET_DEBUG_D_MODE ) { fprintf ( stderr , <STR_LIT> , ( long ) fntype ) ; if ( ! fntype ) fputc ( '\n' , stderr ) ; else { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( fntype ) ) , get_tree_code_name