<s> for ( int i = <NUM_LIT> ; i < NumOp - <NUM_LIT> ; ++ i ) { const MCOperand & MCOp1 = MI . getOperand ( i ) ; const MCOperand & MCOp2 = MI . getOperand ( i + <NUM_LIT> ) ; if ( MCOp1 . isImm ( ) && MCOp2 . isReg ( ) && ( MCOp2 . getReg ( ) == <NUM_LIT> || MCOp2 . getReg ( ) == <STR_LIT> ) ) { if ( <STR_LIT> ( MCOp1 . getImm ( ) ) != <STR_LIT> ) return true ; } } } return


<s> if ( TARGET_SVE && known_eq ( nbytes , BYTES_PER_SVE_VECTOR ) ) { unsigned int elem_nbytes = vector_element_size ( nbytes , nunits ) ; machine_mode pred_mode


<s> static inline bool isMatchingOrAlias ( unsigned ZReg , unsigned Reg ) { assert ( ( ZReg >= <STR_LIT> ) && ( ZReg <= <STR_LIT> ) ) ; return ( ZReg == ( ( Reg - <STR_LIT> ) + <STR_LIT> ) ) || ( ZReg == ( ( Reg - <STR_LIT> ) + <STR_LIT> ) ) || ( ZReg == ( ( Reg - <STR_LIT> ) + <STR_LIT> ) ) || ( ZReg == ( (

Reg - <STR_LIT> ) + <STR_LIT> ) ) || ( ZReg == ( ( Reg - <STR_LIT> ) + <STR_LIT> ) ) || ( ZReg == ( ( Reg - <STR_LIT> ) + <STR_LIT> ) ) ;


<s> bool <ISA_LIT>16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MF


<s> if ( N . getValueType ( ) == <STR_LIT> ) return N ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SDLoc ( N


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = N -> getConstVal ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDValue CPHi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; CP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load , Lo ) ; } return ResNode


<s> case SET : if ( TARGET_HAVE_MOVT && ( i & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & <NUM_LIT> ) == <NUM_LIT> || ( ( - i ) & <NUM_LIT> ) == <NUM_LIT> ) ) return <NUM_LIT> ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU


<s> void aarch64_subvti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 ,


<s> return { false , false } ; } StringRef Scope = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) return { false , false } ; if ( Scope . equals ( <STR_LIT> ) ) return { true , true } ; assert ( Scope . equals (


<s> case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR


<s> Offset = alignTo ( Offset , MFI . getObjectAlignment ( I ) ) ; if ( AssignOffsets ) Assign ( I , - Offset ) ; } } SmallVector < int , <NUM_LIT> > ObjectsToAllocate ; for ( int I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) { unsigned StackID = MFI . getStackID ( I ) ; if ( StackID != TargetStackID :: SVEVector ) continue ; if ( MaxCSFrameIndex >= I && I >= MinCSFrameIndex ) continue ; if ( MFI . isDeadObjectIndex ( I ) ) continue ; ObjectsToAllocate . push_back ( I ) ; } for ( unsigned FI : ObjectsToAllocate ) { unsigned Align = MFI . getObjectAlignment ( FI ) ; if ( Align > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; Offset = alignTo ( Offset + MFI . getObjectSize ( FI ) , Align ) ; if ( AssignOffsets ) Assign ( FI , - Offset ) ; } return


<s> if ( NewOp . getNode ( ) ) return NewOp ; SDValue InputVector = N -> getOperand ( <NUM_LIT> ) ; if ( InputVector . getNode ( ) -> getOpcode ( ) == llvm :: <STR_LIT> && InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( InputVector ) , N -> getValueType ( <NUM_LIT> ) , InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract

-> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getThumbAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup

> & Fixups , const MCSubtargetInfo & STI ) const {


<s> inline void vec_st ( vector unsigned char a1 , int a2 , void *


<s> bool isGP64 ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OI )


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return Subtarget -> in<ISA_LIT>16Mode ( ) ? nullptr : & getSubtargetImpl


<s> CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; EVT ActualVT = getValueType ( DAG . getDataLayout ( ) , CurOrigArg -> getType ( ) , true ) ; MVT ActualMVT = ActualVT . isSimple ( ) ? ActualVT . getSimpleVT ( ) : <STR_LIT> ; if ( ActualMVT == <STR_LIT> || ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; else if ( ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; } CCAssignFn * AssignFn = CCAssignFnForCall ( CallConv , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , Ins [ i ] . Flags , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void ) Res ; } assert ( ArgLocs . size ( ) == Ins . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI . CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is64BitVector ( ) ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is128BitVector ( ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; if ( ! ShowVSRNumsAsVR ) Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MII . get ( MI -> getOpcode ( ) ) , Reg , OpNo ) ; const char * RegName ; RegName = getVerboseConditionRegName ( Reg , MRI . getEncodingValue ( Reg ) ) ; if ( RegName == nullptr ) RegName = getRegisterName


<s> if ( ( Op . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOpcode ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOperand (

<NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> bool isABI_O32 ( ) const { return ABI . IsO32 ( )


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ; return false


<s> getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU )


<s> MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset -= Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset


<s> int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return


<s> bool isSPOperand ( ) const { if ( ! isReg ( ) ) return


<s> else return false ; if ( Register Reg = State . AllocateReg ( RegList ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else return false ; return true


<s> const <ISA_LIT>Subtarget * getSubtargetImpl


<s> if ( FLOAT_MODE_P ( mode ) ) return ix86_fp_cmp_code_to_pcmp_immediate


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectZExt ( Instruction * I ) { if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && I -> getOperand ( <NUM_LIT> ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg ) ; if ( ResultReg == <NUM_LIT> ) return false ; UpdateValueMap ( I , ResultReg ) ; return true ; } return


<s> const DenseMap < int , unsigned > & getWinEHXMMSlotInfo ( ) const { return WinEHXMMSlotInfo


<s> } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return


<s> return __builtin_mve_vshlltq_m_n_sv8hi ( __arm_vuninitializedq_s32 ( ) , __a


<s> bool function_checker :: require_immediate_either_or ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return


<s> SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , Tmp3 , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u64 ( unsigned long long __X , unsigned


<s> if ( GET_CODE ( x ) != UNSPEC || XINT ( x , <NUM_LIT> ) != UNSPEC_PTRUE ) return false ; if ( info ) { aarch64_svpattern pattern = ( aarch64_svpattern ) INTVAL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; machine_mode pred_mode = GET_MODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; scalar_int_mode int_mode = aarch64_sve_element_int_mode ( pred_mode ) ; * info = simd_immediate_info ( int_mode


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T ,


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS


<s> case <STR_LIT> : case <STR_LIT> : assert ( hasReservedCallFrame ( MF ) && <STR_LIT> ) ; return MBB . erase ( MI ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> bool enableMachineScheduler ( ) const override { return true


<s> Lea . addOperand ( MCOperand :: CreateReg ( StackReg ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( StackReg ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Lea . addOperand ( MCOperand ::


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = DCI . DAG . getNode ( GenericOpcode , DL , VT , N -> ops ( ) ) ; return DCI . DAG . getMergeValues ( { Res , DCI . DAG . getConstant ( <NUM_LIT>


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; EVT WideVecVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue WideVec = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Subtarget . hasAVX ( ) && ! Subtarget . hasAVX2 ( ) && TLI . isTypeLegal ( WideVecVT ) && WideVecVT . getSizeInBits ( ) == <NUM_LIT> && WideVec . getOpcode ( ) == <STR_LIT> ) { auto isConcatenatedNot = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; if ( ! isBitwiseNot ( V ) ) return false ; SDValue NotOp = V -> getOperand ( <NUM_LIT> ) ; return peekThroughBitcasts ( NotOp ) . getOpcode ( ) == <STR_LIT> ; } ; if ( isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) || isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) ) { SDValue Concat = split256IntArith ( WideVec , DAG ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( WideVecVT , Concat ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( VT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N


<s> return create<ISA_LIT>WinCOFFObjectWriter ( OS , false


<s> bool hasMSA ( ) const { return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> if ( HasVLX ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! Opc ) Opc = CopyToFromAsymmetricReg ( DestReg , SrcReg , Subtarget ) ; if ( Opc ) { BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( SrcReg == <STR_LIT> || DestReg == <STR_LIT>


<s> vpmax_u16 ( uint16x4_t a , uint16x4_t b ) { return ( uint16x4_t ) __builtin_aarch64_umaxpv4hi ( ( int16x4_t ) a


<s> return ( ( TARGET_FPU_SINGLE != <NUM_LIT> ) ^ ( n ) ?


<s> inline machine_mode function_instance :: vector_mode ( unsigned int i


<s> return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; int RegNo = op -> getReg ( ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ; if ( IdVal -> EvaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; else if ( BE -> getLHS ( ) -> getKind ( ) != MCExpr :: SymbolRef ) IdVal = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , BE -> getRHS ( ) , BE -> getLHS ( ) , getContext ( ) ) ; } Operands . push_back ( <STR_LIT> ( RegNo , IdVal ,


<s> return __builtin_aarch64_simd_bslv4hi_suss ( __a ,


<s> __builtin_aarch64_st1v8qi ( ( __builtin_aarch64_simd_qi * ) a , ( int8x8_t )


<s> else if ( mode == HFmode && TARGET_SSE2 ) return true ; else return default_scalar_mode_supported_p ( mode


<s> EVT OpVT = Op . getValueType ( ) ; if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , OpVT , Op ,

DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> void addMOVZMovAliasOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( CE ) { uint64_t Value = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ( Value >> Shift ) & <NUM_LIT> ) ) ; } else


<s> else if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( exp ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= <NUM_LIT> &&

align < BITS_PER_WORD ) return BITS_PER_WORD ;


<s> return Kind == k_Token && getToken (


<s> static DecodeStatus DecodeBlezGroupBranchMMR6 ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> ; bool HasRs = false ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success


<s> inline AddrOpc getAM3Op ( unsigned AM3Opc )


<s> EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( ! TLI . isTypeLegal ( DstVT ) ) return false ; unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) . getSimpleVT ( ) ; if ( SrcVT . SimpleTy == <STR_LIT> ) { ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT != <STR_LIT> ) { ResultReg = FastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ; if ( ResultReg == <NUM_LIT> ) return false ; } UpdateValueMap ( I , ResultReg ) ; return true


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S2 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base


<s> if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; if ( Subtarget -> isTargetWindows ( ) && Addr . getGlobalValue ( ) && Addr . getGlobalValue ( ) -> hasExternalWeakLinkage ( ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? getBLRCallOpcode ( * MF ) : ( unsigned ) <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( Addr . getGlobalValue ( ) ) CallReg = materializeGV ( Addr . getGlobalValue ( ) ) ; else if ( Addr . getReg ( ) ) CallReg = Addr . getReg ( ) ; if ( ! CallReg ) return false ; const MCInstrDesc & II = TII . get ( getBLRCallOpcode ( * MF )


<s> int <ISA_LIT>AsmParser :: tryParseShiftRegister ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = nullptr ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return -


<s> uint64_t Length = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ?


<s> Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem . OffsetReg = OffsetReg ; Op -> Mem . Offset = nullptr


<s> if ( Value < <NUM_LIT> || Value > MaxRegNum ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Reg . Num = ( unsigned ) Value ; Reg . Group = Group ; Reg . EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> static type_suffix_index long_type_suffix ( function_resolver & r , type_suffix_index type ) { unsigned int element_bits = type_suffixes [ type ] . element_bits ; if ( type_suffixes [ type ] . integer_p && element_bits < <NUM_LIT> ) return find_type_suffix ( type_suffixes [ type ] . tclass , element_bits * <NUM_LIT> ) ; r . report_no_such_form (


<s> return :: isUNPCKLMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmJMPIX ( const MCInst & MI , unsigned Idx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) ==


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <=


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ; DEBUG


<s> return ( mode1 == mode2 || ( ! mips_mode_ok_for_mov_fmt_p ( mode1

) && ! mips_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ;


<s> tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET (


<s> if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand (


<s> if ( TARGET_VXWORKS_RTP ) return false ; if ( LABEL_REF_NONLOCAL_P ( label ) ) return false ; if ( flag_reorder_blocks_and_partition ) return false ; return true


<s> bool IsLeftZeroSide = true ; if ( ! isNonZeroElementsInOrder ( Zeroable , Mask , V1 . getValueType ( ) , IsLeftZeroSide ) ) return SDValue ( ) ; unsigned VEXPANDMask = convertBitVectorToUnsigned ( Zeroable ) ; MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = - CE -> getValue (


<s> static <STR_LIT> classifyFirst ( const MachineInstr & MI ) { return <STR_LIT> ( MI . getOpcode (


<s> <ISA_LIT>AsmStreamer ( MCContext & Context , formatted_raw_ostream & os , bool isVerboseAsm , bool useLoc , bool useCFI , bool useDwarfDirectory , MCInstPrinter * printer , MCCodeEmitter * emitter , MCAsmBackend * asmbackend , bool showInst ) : MCStreamer ( SK_AsmStreamer , Context ) , OS ( os ) , MAI ( Context . getAsmInfo ( )

) , InstPrinter ( printer ) , Emitter ( emitter ) , AsmBackend ( asmbackend ) , CommentStream ( CommentToEmit ) , IsVerboseAsm ( isVerboseAsm ) {


<s> static void rs6000_xcoff_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { int smclass ; static const char * const suffix [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_TLS ) smclass =


<s> int i ; for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! regs_ever_live [ i ] ) return i ; } return INVALID_REGNUM


<s> MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> && Subtarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Tmp ) ; BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ?


<s> case DCmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm ::


<s> return ( __m256i ) __builtin_ia32_vpshld_v16hi ( ( __v16hi ) __A ,


<s> while ( state -> insns_left == <NUM_LIT> || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn

) >= <NUM_LIT> ) ) mips_sim_next_cycle ( state ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( )


<s> } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { unsigned rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( rot << <NUM_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , TTI :: CastContextHint CCH , TTI :: TargetCostKind CostKind , const Instruction * I ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; InstructionCost CostFactor = vectorCostAdjustmentFactor ( Opcode , Dst , Src ) ; if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ; InstructionCost Cost = BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH


<s> } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) { if ( ! Size ) { Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ; } } BaseReg = BaseReg ? BaseReg


<s> if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return TARGET_64BIT && from == DImode && to == SImode ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return true


<s> return MEM_P ( op ) && ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == POST_INC || REG_P


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName ,


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV ,


<s> zero = SET_SRC ( elt ) ; if ( ! REG_P ( reg ) || GET_MODE ( reg ) != expected_mode || zero != CONST0_RTX ( SImode ) ) return false ; regno = REGNO ( reg ) ; if ( vfp ) { if ( i != first_set && regno != last_regno + <NUM_LIT> ) return false ; } else { if ( regno == SP_REGNUM || regno == PC_REGNUM ) return false ; if ( i != first_set && regno


<s> unsigned int <ISA_LIT>InstrInfo :: getTailDuplicateSize ( CodeGenOpt :: Level OptLevel ) const { return OptLevel >= CodeGenOpt :: Aggressive


<s> return ( __m256h ) __builtin_ia32_vfmaddph256_mask ( ( __v16hf ) __A , ( __v16hf )


<s> static int mips_address_cost ( rtx addr , machine_mode mode

, addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {


<s> static void __attribute__ ( ( constructor )


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase (


<s> MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst . getOpcode ( ) == <STR_LIT> || SecondLastInst . getOpcode ( ) == <STR_LIT> ) && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return


<s> enum memmodel model = memmodel_from_int ( INTVAL (


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg1 ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg2 ) ) ; TmpInst . addOperand ( Op3 ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . emitInstruction ( TmpInst ,


<s> void <ISA_LIT>TargetAsmStreamer :: emitArchExtension ( unsigned ArchExt ) { OS << <STR_LIT> << <STR_LIT> ( ArchExt


<s> void <ISA_LIT>AsmParser :: printWarningWithFixIt ( const Twine & Msg , const Twine

& FixMsg , SMRange Range , bool ShowColors ) {


<s> bool <ISA_LIT>BranchExpansion :: handleForbiddenSlot ( ) { if ( ! STI -> has<ISA_LIT>32r6 ( ) || STI -> inMicro<ISA_LIT>Mode ( ) ) return false ; const <ISA_LIT>InstrInfo * TII = STI -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MFp -> begin ( ) ; FI != MFp -> end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MFp -> end ( ) ; if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; Inst = Res . first ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ; if ( std :: next ( Iit ) == FI -> end ( ) || std ::

next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) {


<s> LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128Call ( Op , DAG


<s> if ( ! checkOneUse ( M1 ) ) return false ; return matchShiftAmt ( M1 ) ; } ; SDValue X ; auto matchPatternD = [ & checkOneUse , & checkTwoUse , matchShiftAmt , & X ] ( SDNode * Node ) -> bool { if ( Node -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( N0 ) ) return false ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N1 != N01 || ! checkTwoUse ( N1 ) ) return false ; if ( ! matchShiftAmt ( N1 ) ) return false ; X = N0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchLowBitMask = [ & matchPatternA , & matchPatternB , & matchPatternC ] ( SDValue Mask ) -> bool { return matchPatternA ( Mask ) || matchPatternB ( Mask ) || matchPatternC ( Mask ) ; } ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { X = Node -> getOperand ( <NUM_LIT> ) ; SDValue Mask = Node -> getOperand ( <NUM_LIT> ) ; if ( matchLowBitMask ( Mask ) ) { } else { std :: swap ( X , Mask ) ; if ( ! matchLowBitMask ( Mask ) ) return false ; } } else if ( ! matchPatternD ( Node ) ) return false ; SDLoc DL ( Node ) ; SDValue OrigNBits = NBits ; if ( NBits . getValueType ( ) != NVT ) { NBits = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NBits ) ; insertDAGNode ( * CurDAG , OrigNBits , NBits ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , NVT


<s> int NumElems = VT . getVectorNumElements ( ) ; assert ( NumElems == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; int HalfSize = NumElems / <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( SVOp -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned Shamt = ( i % HalfSize ) * <NUM_LIT> ; unsigned Elt = SVOp -> getMaskElt ( i ) % HalfSize ; Mask |= Elt


<s> return __builtin_aarch64_clzv16qi ( __a )


<s> return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ?


<s> assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( )


<s> return In64BitMode && ( ! TargetTriple . isX32 ( )


<s> case VSX_BUILTIN_XXSEL_2DI_UNS : case CRYPTO_BUILTIN_VPERMXOR : case CRYPTO_BUILTIN_VPERMXOR_V2DI : case CRYPTO_BUILTIN_VPERMXOR_V4SI : case CRYPTO_BUILTIN_VPERMXOR_V8HI : case CRYPTO_BUILTIN_VPERMXOR_V16QI : case CRYPTO_BUILTIN_VSHASIGMAW : case CRYPTO_BUILTIN_VSHASIGMAD : case CRYPTO_BUILTIN_VSHASIGMA : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI : case ALTIVEC_BUILTIN_VPERM_8HI : case ALTIVEC_BUILTIN_VPERM_4SI : case ALTIVEC_BUILTIN_VPERM_4SF : case ALTIVEC_BUILTIN_VPERM_2DI : case ALTIVEC_BUILTIN_VPERM_2DF : case VSX_BUILTIN_VPERM_16QI : case VSX_BUILTIN_VPERM_8HI : case VSX_BUILTIN_VPERM_4SI : case VSX_BUILTIN_VPERM_4SF : case VSX_BUILTIN_VPERM_2DI : case VSX_BUILTIN_VPERM_2DF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVUXDSP : case VSX_BUILTIN_XVCVUXDDP_UNS : case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVDPUXDS_UNS : case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI : case MISC_BUILTIN_UNPACK_TD : case MISC_BUILTIN_UNPACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VCMPEQUB : case ALTIVEC_BUILTIN_VCMPEQUH : case ALTIVEC_BUILTIN_VCMPEQUW : case P8V_BUILTIN_VCMPEQUD : case VSX_BUILTIN_CMPGE_U16QI : case VSX_BUILTIN_CMPGE_U8HI : case VSX_BUILTIN_CMPGE_U4SI : case VSX_BUILTIN_CMPGE_U2DI : case ALTIVEC_BUILTIN_VCMPGTUB : case ALTIVEC_BUILTIN_VCMPGTUH : case ALTIVEC_BUILTIN_VCMPGTUW : case P8V_BUILTIN_VCMPGTUD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case MISC_BUILTIN_PACK_TD : case MISC_BUILTIN_PACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VSRB : case ALTIVEC_BUILTIN_VSRH : case ALTIVEC_BUILTIN_VSRW : case P8V_BUILTIN_VSRD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; default : break ; } while ( num_args > <NUM_LIT> && h . mode [ num_args ] == VOIDmode ) num_args -- ; ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ]


<s> rtx i_pat , d_pat ; if ( TARGET_THUMB1 && dep_type == <NUM_LIT> && recog_memoized ( insn ) == CODE_FOR_cbranchsi4_insn && recog_memoized ( dep ) >= <NUM_LIT> && get_attr_conds ( dep ) == CONDS_SET ) return <NUM_LIT> ; if ( current_tune -> sched_adjust_cost != NULL ) { if ( ! current_tune -> sched_adjust_cost ( insn , dep_type , dep , & cost ) ) return cost ; } if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT )


<s> int UnscaledLdOffset = isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize <= (


<s> return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( & * I , TmpInst , * this


<s> NewMBB -> splice ( NewMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB ->


<s> printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O


<s> static inline unsigned getAM3IdxMode ( unsigned AM3Opc


<s> EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Len = DAG . getNode ( <STR_LIT> , DL , PtrVT , End , Src ) ; return std :: make_pair ( Len ,


<s> return new <ISA_LIT>PassConfig ( * this , PM


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , createWinCOFFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer


<s> if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( got_register_rtx && regno == REGNO ( got_register_rtx ) ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno


<s> return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Value . getOperand ( <NUM_LIT> ) , Mst -> getBasePtr ( ) , Mask , Mst -> getMemoryVT ( ) , Mst -> getMemOperand ( ) , true ) ; } return SDValue ( ) ; } if ( ExperimentalVectorWideningLegalization ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getScalarSizeInBits ( ) ; unsigned ToSz = StVT . getScalarSizeInBits ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts =


<s> tree high = ub ? build_zero_cst ( pointer_sized_int_node ) : build_minus_one_cst ( pointer_sized_int_node ) ; gcc_assert ( ( lb == <NUM_LIT> && ub == - <NUM_LIT> ) || ( lb == - <NUM_LIT> && ub == <NUM_LIT> ) ) ; return build_complex ( NULL , low ,


<s> Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) { case CallingConv :: C : case CallingConv :: Fast


<s> NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( NeedsStackRealignment ) { int MaxAlign = MFI . getMaxAlignment (


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; if ( unsigned ( Fixup . getKind ( ) ) == <STR_LIT> ) FixupOffset &= ~ uint32_t ( <NUM_LIT> ) ; return FixupOffset ; } bool <ISA_LIT>MachObjectWriter :: RecordScatteredRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , unsigned Log2Size , uint64_t & FixedValue ) { const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; const MCFixupKind FK = Fixup . getKind ( ) ; const unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , FK ) ; const unsigned Type = getRelocType ( Target , FK , IsPCRel ) ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } uint32_t other_half = <NUM_LIT> ; switch ( Type ) { case MachO


<s> case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Other ; case 'Q' : return C_Memory ; case 'S' : return C_Other ; } } assert ( Constraint != <STR_LIT> && Constraint != <STR_LIT> && Constraint != <STR_LIT> && Constraint != <STR_LIT> && <STR_LIT> ) ; return TargetLowering :: getConstraintType (


<s> x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ; return x


<s> if ( ! MI ) return <STR_LIT> ; MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; assert ( MO -> isReg ( ) && <STR_LIT> ) ; if ( ! MO ) return <STR_LIT> ; if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { SReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( TargetRegisterInfo :: isVirtualRegister ( SReg ) ) { if ( MO -> getSubReg ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return false ; StringRef name = Tok . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: parseVariantKind ( name ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . getKind ( ) != AsmToken :: LParen ) return false ; Parser . Lex ( ) ; const MCExpr * subExpr ; if ( Parser . parseParenExpression ( subExpr , EndLoc ) ) return false ; bool isPIC = getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ; switch ( VK ) { default : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC10 : ( isPIC ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT10 : VK ) ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 : ( isPIC ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT22 : VK ) ) ; break ; } EVal = <ISA_LIT>MCExpr :: create ( VK , subExpr ,


<s> if ( ( FirstMI == nullptr || FirstMI -> getOpcode ( ) == <STR_LIT> ) && SecondMI . getOpcode ( ) == <STR_LIT> ) return true ; if ( ( FirstMI == nullptr || FirstMI -> getOpcode ( ) == <STR_LIT> ) && ( SecondMI . getOpcode ( ) == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; if ( ( FirstMI == nullptr || FirstMI -> getOpcode ( ) == <STR_LIT> ) && ( SecondMI . getOpcode ( ) == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; if ( ( FirstMI == nullptr || ( FirstMI -> getOpcode ( ) == <STR_LIT> && FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) && ( SecondMI . getOpcode ( ) == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; return false


<s> if ( const auto * BKey = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) return BKey -> getZExtValue ( ) ; return false ; } const StringRef Key = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT> ) ) ; return Key . equals_lower (


<s> Module * Mod = IRB -> GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; FunctionType * FT = FunctionType :: get ( Type :: getPrimitiveType ( Mod -> getContext ( ) , Type :: VoidTyID ) , false ) ; Twine TgtAddr ( Tgt ) ; AttributeSet AS ; AS = AS . addAttribute ( Mod -> getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , TgtAddr . str ( ) ) ; Value * Proto = Mod -> getOrInsertFunction ( FName , FT , AS ) ; IRB -> CreateCall ( dyn_cast < Value > ( Proto ) ) ; VisitMap [ N


<s> unsigned <ISA_LIT>SpeculativeLoadHardeningPass :: hardenValueInRegister ( Register Reg , MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , DebugLoc Loc ) { assert ( canHardenRegister ( Reg ) && <STR_LIT> ) ; assert ( Reg . isVirtual ( ) && <STR_LIT> ) ; auto * RC = MRI -> getRegClass ( Reg ) ; int Bytes = TRI -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; assert ( ( Bytes == <NUM_LIT> || Bytes == <NUM_LIT> || Bytes == <NUM_LIT> || Bytes == <NUM_LIT> ) && <STR_LIT> ) ; if ( Bytes != <NUM_LIT> ) { unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ;


<s> tentativeToken = getLexer ( ) -> Lex


<s> if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( mode , type ) && ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode


<s> if ( ! old_dst ) old_dst = gen_reg_rtx ( mode ) ; switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : emit_insn ( gen_memory_barrier ( ) ) ; case MEMMODEL_RELAXED : case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : if ( mode == SImode ) icode = CODE_FOR_fetchadd_acq_si ; else icode = CODE_FOR_fetchadd_acq_di ; break ; case MEMMODEL_RELEASE : if ( mode == SImode ) icode = CODE_FOR_fetchadd_rel_si ; else icode = CODE_FOR_fetchadd_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( model == MEMMODEL_RELAXED || model == MEMMODEL_RELEASE || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg


<s> uint64_t getPC32DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitEHSjLjSetJmp ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return emitEHSjLjLongJmp ( MI , BB )


<s> assert ( Imm > <NUM_LIT> && Imm <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) <<

<STR_LIT> << Imm << markup ( <STR_LIT> ) ;


<s> if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG


<s> return isMem ( ) && ! Mem . DefaultBaseReg && Mem .


<s> } else if ( CONST_INT_P ( src ) ) { if ( INTVAL ( src ) < <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else if ( MEM_P ( src ) ) { int ptrreg = - <NUM_LIT> ; int dreg = REGNO ( dst ) ; rtx inside = XEXP ( src , <NUM_LIT> ) ; switch ( GET_CODE ( inside ) ) { case REG : ptrreg = REGNO ( inside ) ; break ; case SUBREG : ptrreg = subreg_regno ( inside ) ; break ; case PLUS : ptrreg = REGNO ( XEXP ( inside , <NUM_LIT> ) ) ; gcc_assert ( ! REG_P ( XEXP ( inside , <NUM_LIT> ) ) ) ; break ; case


<s> unsigned Register = PPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , DL , ValTy , N -> getOperand ( <NUM_LIT> ) ,


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( hasFP ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( NumBytes ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr


<s> if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * <NUM_LIT> ; return factor ; case ADDRESS_LO_SUM : return TARGET_MIPS16 ? factor * <NUM_LIT> : factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC : return factor * mips_symbol_insns ( addr


<s> return ( ( qword ) ( vec_rl ( ( vec_ushort8 ) ( a ) ,


<s> case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ; else return makeDMB ( Builder , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> )


<s> unsigned ArgSlotSizeInBytes = ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue VAListLoad = DAG . getLoad ( getPointerTy ( DAG . getDataLayout ( ) ) , DL , Chain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue VAList = VAListLoad ; if ( Align > getMinStackArgumentAlignment ( ) ) { assert ( ( ( Align & ( Align - <NUM_LIT> ) ) == <NUM_LIT> ) && <STR_LIT> ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align , DL


<s> MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeFld , <NUM_LIT>


<s> fputs ( <STR_LIT> , file ) ; } assemble_name ( file , label ) ; fputc ( '\n' , file ) ; if ( flag_pic ) { ASM_GENERATE_INTERNAL_LABEL ( labelpc , <STR_LIT> , labelno ) ; assemble_name ( file , labelpc ) ; fputs ( <STR_LIT> , file ) ; if ( TARGET_THUMB1_ONLY ) { fputs ( <STR_LIT> , file ) ; fputs ( <STR_LIT> , file ) ; } else fputs ( <STR_LIT> , file ) ; } else if ( TARGET_THUMB1_ONLY ) fputs ( <STR_LIT> , file ) ; } if ( TARGET_THUMB1_ONLY ) { if ( mi_delta > <NUM_LIT> ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , label ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno ) ; } else if ( mi_delta != <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno , mi_delta ) ; } } else { while ( mi_delta != <NUM_LIT> ) { if ( ( mi_delta & ( <NUM_LIT> << shift ) ) == <NUM_LIT> ) shift += <NUM_LIT> ; else { asm_fprintf ( file , <STR_LIT> , mi_op , this_regno ,

this_regno , mi_delta & ( <NUM_LIT> << shift ) ) ;


<s> auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant


<s> if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , <NUM_LIT> ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = <NUM_LIT> ; else * intregs_p = <NUM_LIT> ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p =


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( ( MI . getOpcode ( ) == <STR_LIT> ) ? ( MCFixupKind ) <STR_LIT> : ( MCFixupKind ) <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( <NUM_LIT> - Val , getContext ( ) ) , S , E , * this ) ) ; return MatchOperand_Success


<s> rtx_code_label * label , * end_label ; end_label = gen_label_rtx ( ) ; cmp_result = gen_rtx_EQ ( VOIDmode , begin , end ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; inc = gen_reg_rtx ( Pmode ) ; emit_insn ( PMODE_INSN ( gen_rdhwr_synci_step , ( inc ) ) ) ; cmp_result = gen_rtx_EQ ( VOIDmode , inc , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; mask = mips_force_unary ( Pmode , NEG , inc ) ; begin = mips_force_binary ( Pmode , AND , begin , mask ) ; length = mips_force_binary ( Pmode , MINUS , end , begin ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; emit_insn ( gen_synci ( begin


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg


<s> TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCExpr * HiSym = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_None , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCExpr * LoSym = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_None , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( RegNo ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst


<s> void <ISA_LIT>FrameLowering :: emitPopInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned LdmOpc , unsigned LdrOpc , bool isVarArg , bool NoGap , bool ( * Func ) ( unsigned , bool ) ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && !


<s> if ( tryOptVectorShuffle ( I ) ) return true ; const LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Src1Ty = MRI . getType ( Src1Reg ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Src2Ty = MRI . getType ( Src2Reg ) ; ArrayRef < int > Mask = I . getOperand ( <NUM_LIT> ) . getShuffleMask ( ) ; MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! Src1Ty . isVector ( ) || ! Src2Ty . isVector ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned BytesPerElt = DstTy . getElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < Constant * , <NUM_LIT> > CstIdxs ; for ( int Val : Mask ) { Val = Val < <NUM_LIT> ? <NUM_LIT> : Val ; for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad


<s> SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV ) ; } SymToPrint -> print ( O , MAI ) ; printOffset ( MO . getOffset


<s> else if ( N -> getOpcode ( ) == <STR_LIT> ) return ( <STR_LIT> )

N -> getConstantOperandVal ( <NUM_LIT> ) ;


<s> return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case


<s> if ( Subtarget -> isGP64bit ( ) ) return lowerFCOPYSIGN64 ( Op

, DAG , Subtarget -> hasExtractInsert ( ) ) ;


<s> FnStart = getContext ( ) . createTempSymbol


<s> const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( MF , STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT>


<s> int sh2a_get_function_vector_number ( rtx x ) { int num ; tree list , t ; if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return <NUM_LIT> ; list = SH_ATTRIBUTES ( t


<s> return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [

<NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { ConstantSDNode * LHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; unsigned LHSC = LHS ? LHS -> getZExtValue ( ) : <NUM_LIT> ; unsigned RHSC = RHS ? RHS -> getZExtValue


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable (


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return <STR_LIT> ( funcInfo ,


<s> int StoreSize = getMemScale ( StoreInst ) ; int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset +

LoadSize <= ( UnscaledStOffset + StoreSize ) ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; Known . resetAll ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : Known . Zero . setBitsFrom ( <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned NumLoBits = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; Known . Zero . setBitsFrom ( NumLoBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { Known . setAllZero ( ) ; break ; } DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; if ( Opc == <STR_LIT> ) { Known . Zero <<= ShAmt ; Known . One <<= ShAmt ; Known . Zero . setLowBits ( ShAmt ) ; } else { Known . Zero . lshrInPlace (


<s> for ( i = <NUM_LIT> ; i < words ; i ++ ) if ( refers_to_regno_p ( REGNO ( operands [ <NUM_LIT> ] ) + i , operands [ <NUM_LIT> ] ) ) { if ( i == words - <NUM_LIT> ) { xop [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> * ( words - <NUM_LIT> ) ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; output_asm_insn ( <STR_LIT> , xop ) ; return <STR_LIT> ; } else if ( i == <NUM_LIT> ) { xop [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> * ( words - <NUM_LIT> ) ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT>


<s> case TargetOpcode :: EH_LABEL : case TargetOpcode :: GC_LABEL : return <NUM_LIT> ; } } return <NUM_LIT>


<s> MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) ,


<s> Options . LoadSizes = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Options . MaxNumLoads = TLI ->


<s> void <ISA_LIT>InstPrinter :: printLogicalImm32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT>


<s> SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && ( AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) && ( AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) ) { return LowerToBSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && AsmPieces . size ( ) == <NUM_LIT> && ( AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { AsmPieces . clear ( ) ; const std :: string & Constraints = IA -> getConstraintString ( ) ; SplitString ( StringRef ( Constraints ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; std :: sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) { return LowerToBSwap ( CI ) ; } } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { SmallVector < StringRef , <NUM_LIT> > Words ; SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ; if ( Words . size ( ) == <NUM_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> ) { Words . clear ( ) ; SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ; if ( Words . size ( ) == <NUM_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> ) { Words . clear ( ) ; SplitString ( AsmPieces [ <NUM_LIT> ]


<s> if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case Swift : MaxInterleaveFactor =


<s> return getSubExpr ( ) -> evaluateAsRelocatable ( Res


<s> AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequired < LoopInfoWrapperPass > (


<s> if ( ( HiTZ + LoLZ ) >= Num ) return ( <NUM_LIT> + HiTZ ) ; return


<s> return new <ISA_LIT>ExpandAtomicPseudo


<s> if ( aarch64_vector_data_mode_p ( mode1 ) && aarch64_vector_data_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2


<s> static machine_mode sh_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree funtype , int for_return ) { if ( sh_promote_prototypes ( funtype ) ) return promote_mode ( type , mode , punsignedp ) ; else return default_promote_function_mode ( type , mode , punsignedp


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; uint64_t And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N , <STR_LIT> , And_imm ) ) return false ; const SDNode * Op0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; And_imm |= ( <NUM_LIT> << NumberOfIgnoredLowBits ) - <NUM_LIT> ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) return false ; bool ClampMSB = false ; uint64_t Srl_imm = <NUM_LIT> ; if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; } else if ( isOpcWithIntImmediate ( Op0 , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ! BiggerPattern && ( Srl_imm <= <NUM_LIT> || Srl_imm >= VT . getSizeInBits ( ) ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false ; } LSB = Srl_imm ; MSB = Srl_imm + ( VT == <STR_LIT> ? countTrailingOnes < uint32_t > ( And_imm ) : countTrailingOnes < uint64_t > ( And_imm ) ) - <NUM_LIT> ; if ( ClampMSB ) MSB = MSB > <NUM_LIT> ? <NUM_LIT> : MSB ; Opc = VT == <STR_LIT> ? <STR_LIT> :


<s> MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer -> EmitLabel ( Stub ) ; OutStreamer -> EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * Anon = MCSymbolRefExpr :: create ( AnonSymbol , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: create ( LazyPtr , OutContext ) ; const MCExpr * Sub = MCBinaryExpr :: createSub ( LazyPtrExpr , Anon , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer -> EmitLabel ( AnonSymbol ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: createHa ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: createLo ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer -> SwitchSection ( LSPSection ) ; OutStreamer -> EmitLabel ( LazyPtr ) ; OutStreamer -> EmitSymbolAttribute ( RawSym


<s> if ( GET_CODE ( pat ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= <NUM_LIT> && REGNO ( SET_DEST ( pat ) ) < <NUM_LIT> ) || ! SPARC_INT_REG_P ( REGNO ( SET_DEST ( pat ) ) ) ) return <NUM_LIT> ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode ,

<NUM_LIT> ) , pat ) ) return <NUM_LIT> ;


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions (


<s> return selectBDAddr ( <STR_LIT> , Addr


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue EncodedVal = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; EVT VmovVT = VT . is128BitVector ( )


<s> initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options .


<s> <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt ::

Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ; return Copy


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { switch ( rs6000_cpu ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : if ( DECIMAL_FLOAT_MODE_P ( mode ) )


<s> PUT_MODE ( SET_DEST ( real2 ) , SImode ) ; reg = SET_SRC ( real2 ) ; real2 = replace_rtx ( real2 , reg , gen_rtx_REG ( SImode , REGNO ( reg ) ) ) ; synth = copy_rtx ( real2 ) ; if ( BYTES_BIG_ENDIAN ) { offset = XEXP ( XEXP ( SET_DEST ( real2 ) , <NUM_LIT> ) , <NUM_LIT> ) ; real2 = replace_rtx ( real2 , offset , GEN_INT ( INTVAL ( offset ) + <NUM_LIT> ) ) ; } reg = SET_SRC ( synth ) ; synth = replace_rtx ( synth , reg , gen_rtx_REG ( SImode , REGNO ( reg ) + <NUM_LIT> ) ) ; offset = XEXP ( XEXP ( SET_DEST ( synth ) , <NUM_LIT> )


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; auto * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; auto ShuffleMask = SVN -> getMask ( ) ; SDLoc DL ( Op ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Op . getOperand ( <NUM_LIT> ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; Op1 = convertToScalableVector ( DAG , ContainerVT , Op1 ) ; Op2 = convertToScalableVector ( DAG , ContainerVT , Op2 ) ; bool ReverseEXT = false


<s> getDoubleRegPair ( DestDReg , EvenDestReg , OddDestReg ) ; getDoubleRegPair ( SrcDReg , EvenSrcReg , OddSrcReg ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenDestReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenSrcReg ) ; DOUT << <STR_LIT> << * MI ; if ( DestDReg != SrcDReg ) { MI = BuildMI ( MBB , I , dl , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) , OddDestReg ) .


<s> if ( Subtarget . hasAVX512 ( ) ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Amt , EltSizeInBits , UndefElts , EltBits ) ) { if ( ! UndefElts && llvm :: all_of ( EltBits , [ EltBits ] ( APInt & V ) { return EltBits [ <NUM_LIT> ] == V ; } ) ) { unsigned Op = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; uint64_t RotateAmt = EltBits [ <NUM_LIT> ] . urem ( EltSizeInBits ) ; return DAG . getNode ( Op , DL , VT , R , DAG . getConstant ( RotateAmt , DL , <STR_LIT> ) ) ; } } return


<s> bool <ISA_LIT>TargetLowering :: areJTsAllowed ( const


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const


<s> case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT>


<s> if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64 ( ) ? - <NUM_LIT>


<s> struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return <NUM_LIT> ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && SUBREG_P ( base ) )