<s> assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getSExtOrTrunc ( Load , dl , RegVT ) ; } assert ( isPowerOf2_32 ( RegSz * MemSz * NumElems ) && <STR_LIT> ) ; MVT SclrLoadTy = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && ( ( MemSz % Tp . getSizeInBits ( ) ) == <NUM_LIT> ) ) { SclrLoadTy = Tp ; } } if ( TLI . isTypeLegal ( <STR_LIT> ) && SclrLoadTy . getSizeInBits ( ) < <NUM_LIT> && ( <NUM_LIT> <= MemSz ) ) SclrLoadTy = <STR_LIT> ; unsigned NumLoads = MemSz / SclrLoadTy . getSizeInBits ( ) ; assert ( ( Ext != <STR_LIT> || NumLoads == <NUM_LIT> ) && <STR_LIT> ) ; unsigned loadRegZize = RegSz ; if ( Ext == <STR_LIT> && RegSz >= <NUM_LIT> ) loadRegZize = <NUM_LIT> ; EVT LoadUnitVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclrLoadTy , loadRegZize / SclrLoadTy . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , loadRegZize / MemVT . getScalarSizeInBits ( ) ) ; assert ( WideVecVT . getSizeInBits ( ) == LoadUnitVecVT . getSizeInBits ( ) && <STR_LIT> ) ; assert ( TLI . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( SclrLoadTy . getSizeInBits ( ) / <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Res = DAG . getUNDEF ( LoadUnitVecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; Chains . push_back ( ScalarLoad . getValue ( <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; else Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , Res , ScalarLoad , DAG . getIntPtrConstant ( i , dl ) ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; } SDValue TF = DAG . getNode ( <STR_LIT>


<s> bool IsOptimizingSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; bool HasFastHOps = Subtarget . hasFastHorizontalOps ( ) ; return ! IsSingleSource ||


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; bool isLittleEndian = Subtarget -> isLittle ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; if ( AFI -> isCmseNSEntryFunction ( ) && MF . getFunction ( ) . hasStructRetAttr ( ) ) { DiagnosticInfoUnsupported Diag ( DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , SDLoc ( ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( Diag ) ; } for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; bool ReturnF16 = false ; if ( Subtarget -> hasFullFP16 ( ) && Subtarget -> isTargetHardFloat ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> && Arg . getOpcode ( ) == <STR_LIT> ) { SDValue ZE = Arg . getOperand ( <NUM_LIT> ) ; if ( ZE . getOpcode ( ) == <STR_LIT> && ZE . getValueType ( ) == <STR_LIT> ) { SDValue BC = ZE . getOperand ( <NUM_LIT> ) ; if ( BC . getOpcode ( ) == <STR_LIT> && BC . getValueType ( ) == <STR_LIT> ) { Arg = BC . getOperand ( <NUM_LIT> ) ; ReturnF16 = true ; } } } } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( ! ReturnF16 ) Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant (


<s> SET_NEXT_INSN ( cop ) = NEXT_INSN ( insn ) ; PUT_MODE ( core_insn , VOIDmode ) ; PUT_MODE ( cop , BImode ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( INSN_LOCATION ( core_insn ) ? core_insn : cop ) ; INSN_LOCATION ( core_insn ) = <NUM_LIT> ; INSN_LOCATION ( cop ) =


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx_insn * insn ) { mips_sim_insn = insn ; note_uses ( & PATTERN ( insn ) , mips_sim_wait_regs_1 , state


<s> if ( rem > <NUM_LIT> || ( TARGET_THUMB2 && rem > <NUM_LIT> ) ) { emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , PROBE_INTERVAL - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg1 , - rem ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr , regno1 , live_regs ) ; emit_move_insn ( reg1 , GEN_INT ( first ) ) ; rounded_size = size & - PROBE_INTERVAL ; emit_move_insn ( sr . reg , GEN_INT ( rounded_size ) ) ; emit_set_insn ( reg1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , reg1 ) ) ; emit_set_insn ( sr . reg , gen_rtx_MINUS ( Pmode , reg1 , sr . reg ) ) ; emit_insn ( gen_probe_stack_range ( reg1 , reg1 , sr . reg ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > <NUM_LIT> || ( TARGET_THUMB2 && rem > <NUM_LIT> ) ) { emit_set_insn ( sr . reg , plus_constant ( Pmode , sr . reg


<s> assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & RegOrImm = MI -> getOperand ( <NUM_LIT> ) ; if ( RegOrImm . isImm ( ) )


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> &&


<s> if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) return


<s> llvm_unreachable ( <STR_LIT> ) ; case ELF :: R_MIPS_HI16 : case ELF :: R_MIPS16_HI16 : case ELF :: R_MICROMIPS_HI16 : case ELF :: R_MIPS_LO16 : case ELF :: R_MIPS16_LO16 : case ELF :: R_MICROMIPS_LO16


<s> bool arm_valid_symbolic_address_p ( rtx addr ) { rtx xop0 , xop1 = NULL_RTX ; rtx tmp = addr ; if ( target_word_relocations ) return false ; if ( SYMBOL_REF_P ( tmp ) || LABEL_REF_P ( tmp ) ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( tmp ) ==


<s> unsigned StartIdx = StatepointOpers ( & MI ) . getVarIdx ( ) ; SM . recordStackMapOpers ( MI , <NUM_LIT> , MI . operands_begin ( ) + StartIdx , MI . operands_end ( ) , false ) ; if ( OS . hasRawTextSupport ( ) ) { std :: string s ; raw_string_ostream SS ( s ) ; SS << <STR_LIT> ; MI . print ( SS , NULL ) ; SS << <STR_LIT> ; MCContext & context = OS . getContext ( ) ; const MCRegisterInfo & MCRI = * context . getRegisterInfo ( ) ; MachineInstr :: const_mop_iterator MOI = MI . operands_begin ( ) + StartIdx ; MachineInstr :: const_mop_iterator MOE = MI . operands_end ( ) ; while ( MOI != MOE ) { StackMaps :: LocationVec Locs ; StackMaps :: LiveOutVec LiveOuts ; MOI = SM . parseOperand ( MOI , MOE , Locs , LiveOuts ) ; if ( Locs . size ( ) < <NUM_LIT> ) continue ; assert ( Locs . size ( ) == <NUM_LIT> ) ; assert ( LiveOuts . size ( ) == <NUM_LIT> ) ; StackMaps :: Location Loc = Locs [ <NUM_LIT> ] ; switch ( Loc . LocType ) { case StackMaps :: Location :: Unprocessed : case StackMaps :: Location :: Direct : llvm_unreachable ( <STR_LIT> ) ; case StackMaps :: Location :: Constant : SS << <STR_LIT> << Loc . Offset << <STR_LIT> ; break ; case StackMaps :: Location :: ConstantIndex : llvm_unreachable ( <STR_LIT> ) ; break ; case StackMaps :: Location :: Register : { SS << <STR_LIT> << MCRI . getName ( Loc . Reg ) << <STR_LIT> ; break ; } case StackMaps :: Location :: Indirect : { SS << <STR_LIT> << MCRI . getName ( Loc . Reg ) << <STR_LIT> << Loc . Offset << <STR_LIT> ; break ; } } if ( MOI != MOE ) { SS <<


<s> return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI .


<s> for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_regs_intersect_p ( mask , & reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG )


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase


<s> if ( matchVectorShuffleWithPACK ( VT , PackVT , V1 , V2 , PackOpcode , Mask , DAG , Subtarget ) ) return DAG . getNode ( PackOpcode , DL , VT , DAG . getBitcast ( PackVT , V1 ) , DAG . getBitcast ( PackVT , V2 ) ) ; return SDValue


<s> return ( uint64x2_t ) __builtin_neon_vrshluv2di ( ( int64x2_t )


<s> else if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( exp ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST &&

TREE_STRING_LENGTH ( exp ) >= <NUM_LIT> && align < BITS_PER_WORD ) return BITS_PER_WORD ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR16DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm


<s> unsigned <ISA_LIT>AsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) +


<s> unsigned HalfBits = HalfType -> getPrimitiveSizeInBits ( ) ; IntegerType * FullType = IntegerType :: get ( getContext ( ) , HalfBits * <NUM_LIT> ) ; Value * DivHi = Builder . CreateCast ( Instruction :: ZExt , Op0 , FullType ) ; Value * DivLo = Builder . CreateCast ( Instruction :: ZExt , Op1 , FullType ) ; Dividend = Builder . CreateOr ( Builder . CreateShl ( DivHi , ConstantInt :: get ( FullType , HalfBits ) ) , DivLo ) ; Divisor = getOperand ( <NUM_LIT> ) ; } else { Dividend = getOperand ( <NUM_LIT> ) ; Divisor = getOperand (


<s> const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> hasAVX512 ( ) ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return SplitBinaryOpsAndApply ( DAG , Subtarget , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] , AVGBuilder ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ; std :: swap ( Operands [ i ] ,


<s> } , { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , } ; unsigned EltIdx = Log2_32 ( SrcEltSize / <NUM_LIT> ) ; unsigned NumEltsIdx = Log2_32 ( NumElts / <NUM_LIT> ) ; unsigned Opc = OpcTable [ EltIdx ] [ NumEltsIdx ] [ PredIdx ] ; if ( ! Opc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & VecRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * SrcRC = getRegClassForTypeOnBank ( SrcTy , VecRB , RBI , true ) ; if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned NotOpc = Pred == ICmpInst :: ICMP_NE ? <STR_LIT> : <NUM_LIT> ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> ) NotOpc = NotOpc ? <STR_LIT> : <NUM_LIT> ; if ( SwapOperands ) std :: swap ( SrcReg , Src2Reg ) ; MachineIRBuilder MIB ( I ) ; auto Cmp = MIB . buildInstr ( Opc , { SrcRC } , { SrcReg , Src2Reg } ) ; constrainSelectedInstRegOperands ( * Cmp , TII , TRI , RBI ) ; if ( NotOpc ) { Cmp = MIB . buildInstr ( NotOpc , { DstReg } , {


<s> assert ( RegNo < N && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> uint64_t <ISA_LIT>GNULDBackend :: getTPOffset ( const Input & pInput )


<s> if ( BARRIER_P ( barrier_or_label ) && PREV_INSN ( barrier_or_label ) && JUMP_TABLE_DATA_P ( PREV_INSN ( barrier_or_label ) ) ) { rtx pat = PATTERN ( PREV_INSN ( barrier_or_label ) ) ; return ( ( optimize_size || ( ( unsigned ) XVECLEN ( pat , <NUM_LIT> ) * GET_MODE_SIZE ( GET_MODE ( pat ) ) <= ( unsigned ) <NUM_LIT> << ( CACHE_LOG - <NUM_LIT> ) ) ) ? <NUM_LIT> : align_jumps . levels [ <NUM_LIT> ] . log ) ; } rtx_insn * next = next_active_insn ( barrier_or_label ) ; if ( ! next ) return <NUM_LIT> ; rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> ) == UNSPECV_ALIGN ) return <NUM_LIT> ; if ( optimize_size ) return <NUM_LIT> ; if ( ! TARGET_SH2 || ! optimize ) return align_jumps . levels [ <NUM_LIT> ] . log ; if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { int slot , credit ; bool jump_to_next = false ; rtx_insn * prev = prev_real_insn ( prev_active_insn ( barrier_or_label ) ) ; for ( slot = <NUM_LIT> , credit = ( <NUM_LIT> << ( CACHE_LOG - <NUM_LIT> ) ) + <NUM_LIT> ; credit >= <NUM_LIT> && prev && NONJUMP_INSN_P ( prev ) ; prev = prev_real_insn ( prev ) ) { jump_to_next = false ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( rtx_sequence * prev_seq = dyn_cast < rtx_sequence * > ( PATTERN ( prev ) ) ) { prev = prev_seq -> insn ( <NUM_LIT> ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next =


<s> void <ISA_LIT>RegisterSema :: FinalizeFunction ( BasicBlock * ExitBB ) { DCRegisterSema :: FinalizeFunction ( ExitBB ) ; for ( size_t i = <NUM_LIT> , e = CCAssignments . size ( ) ; i != e ; ++ i )


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ! VT . isFloatingPoint ( ) && VT . getSimpleVT ( ) != <STR_LIT> && VT . getSimpleVT ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal


<s> static bool or1k_strict_argument_naming


<s> rtx value0 ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; value0 = expand_normal ( arg0 ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; create_input_operand ( & ops [ <NUM_LIT> ] , value0 , TYPE_MODE ( TREE_TYPE ( arg0 )


<s> struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; XEXP ( mem , <NUM_LIT>


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! IgnoreSPUpdates && ! TFI -> hasReservedCallFrame ( MF ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; assert ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) >= <NUM_LIT> && <STR_LIT> ) ; return getFrameIndexReferenceSP ( MF , FI ,


<s> static inline bool isLEA ( const int Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> cum -> stdarg = fntype && ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; cum -> nargs_prototype = <NUM_LIT> ; if ( incoming || cum -> prototype ) cum -> nargs_prototype = n_named_args ; if ( ( ! fntype && rs6000_default_long_calls ) || ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; if ( TARGET_DEBUG_ARG )


<s> if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE (

SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ;


<s> SDValue getAddrGlobal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , Chain , Tgt

, PtrInfo , false , false , false , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_LOAD ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op .


<s> NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , SupReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT>

) . addImm ( <NUM_LIT> * ( NextReg - R4BaseReg ) ) ) ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI )


<s> return ( uint16x4_t ) __builtin_aarch64_urhaddv4hi ( ( int16x4_t )


<s> return ( __m128i ) vec_xor ( ( __v2di )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto * UnfoldedRC = getRegClassForUnfoldedLoad ( MF , * TII , MI . getOpcode ( ) ) ; if ( ! UnfoldedRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } Register Reg = MRI -> createVirtualRegister ( UnfoldedRC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( MF , MI , Reg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; for ( auto * NewMI : NewMIs ) MBB . insert ( MI . getIterator ( ) , NewMI ) ; if ( MI . isCandidateForCallSiteEntry ( ) ) MF . eraseCallSiteInfo ( & MI ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( { dbgs ( ) <<


<s> bool nds32_e8_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer


<s> return __builtin_ia32_vcvttph2qq512_mask_round ( __A , _mm512_setzero_si512 ( ) , ( __mmask8


<s> SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0 ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck2 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F


<s> void MCLDInitialize<ISA_LIT>Emulation ( ) { mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>elTarget , mcld :: emulate<ISA_LIT>LD ) ; mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>64elTarget ,


<s> assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; bool ListContainsPC = false , ListContainsLR = false ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; switch ( MI . getOperand ( OI ) . getReg ( )


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned FIOperandNo = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( requiresRegisterScavenging ( MF ) ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( requiresRegisterScavenging ( MF ) ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg


<s> if ( __builtin_expect ( __builtin_tend ( <NUM_LIT> ) , <NUM_LIT> ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> rtx func_addr = func_desc ; gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm19Lsl2Encoding ( const MachineInstr & MI , unsigned


<s> uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += SelectInt64Count ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( SelectInt64 ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res ,


<s> operands [ <NUM_LIT> ] = lab ; return templ ; } else { int offset = ( branch_dest ( next_insn ) - INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + <NUM_LIT> ) ; if ( offset >= - <NUM_LIT> && offset <= <NUM_LIT> ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) src = XEXP ( src , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = src ; return templ ; } } } rtx_code_label * lab = gen_label_rtx ( ) ; emit_label_after ( lab ,


<s> case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : return <NUM_LIT> ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return <NUM_LIT> ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return <NUM_LIT> ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , Parser ( Parser

) , Lexer ( Parser . getLexer ( ) ) , SubtargetInfo ( STI ) {


<s> uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return false ; } return true


<s> void Emitter < CodeEmitter > :: addPCLabel ( unsigned LabelID ) { DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void

* ) MCE . getCurrentPCValue ( ) << '\n' ;


<s> struct machine_function * machine ; machine = ( machine_function * ) ggc_alloc_cleared ( sizeof ( machine_function ) ) ; machine -> func_type = ARM_FT_UNKNOWN ; return machine


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> unsigned Pos = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Pos += <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Pos ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( NumOpsAdded == <NUM_LIT> ) { <STR_LIT> Opc = ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned ShAmt = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ShAmt == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) ShAmt = <NUM_LIT> ; else Opc = <STR_LIT> ; } MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Opc , ShAmt ) ) ) ; } return true


<s> if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case


<s> if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - <NUM_LIT> ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } Parser . Lex ( ) ; return RegNum


<s> machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type =


<s> const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm (


<s> return ( __m128i ) __builtin_ia32_maskloadq ( ( const __v2di


<s> static SDValue lowerV32I8VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask ,

Zeroable , Subtarget , DAG ) ) return Shift ;


<s> bool isWydeMH ( ) const { return isLabelImm16 (


<s> SmallSet < int , <NUM_LIT> > ZeroedLocations ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) runOnMachineBasicBlock ( * FI ) ; if ( StackStores . size ( ) == <NUM_LIT> ) return false ; for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator i = Returns . begin ( ) , e = Returns . end ( ) ; i != e ; ++ i ) { MachineInstr * Ret = * i ; ZeroedLocations . clear ( ) ; for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator si = StackStores . begin ( ) , se = StackStores . end ( ) ; si != se ; ++ si ) { MachineInstr * Store = * si ; unsigned Opc = Store -> getOpcode ( ) ; MachineBasicBlock & MBB = * Ret -> getParent


<s> return ( __m256d ) __builtin_ia32_haddpd256 ( ( __v4df )


<s> case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return <NUM_LIT> ; case vec_perm : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case vec_promote_demote : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case cond_branch_taken : return <NUM_LIT> ; case unaligned_load : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case unaligned_store : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS (


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const unsigned FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs , NumGPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs , NumFPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * EVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI -> CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateStackObject ( Depth , <NUM_LIT> , false ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; for ( unsigned GPRIndex = <NUM_LIT> ; GPRIndex != NumGPArgRegs ; ++ GPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( GPArgRegs [ GPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( GPArgRegs [ GPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , PtrVT ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } for ( unsigned FPRIndex = <NUM_LIT> ; FPRIndex != NumFPArgRegs ; ++ FPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( FPArgRegs [ FPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( FPArgRegs [ FPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( EVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType (


<s> int <ISA_LIT>BaseInstrInfo :: getSTMUseCycle ( const InstrItineraryData * ItinData , const MCInstrDesc & UseMCID , unsigned UseClass , unsigned UseIdx , unsigned UseAlign ) const { int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseMCID . getNumOperands (


<s> uint64_t FeatureBits = STI . getFeatureBits ( ) ; FeatureBits &= ~ <ISA_LIT>AssemblerOptions :: AllArchRelatedMask ; STI . setFeatureBits ( FeatureBits


<s> return ( int32x2_t ) __builtin_neon_vqabsv2si (


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = <NUM_LIT> ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall =


<s> bool MatchUnpack = true ; SmallVector < int , <STR_LIT> > SrcBytes ; for ( unsigned Elt = <NUM_LIT> ; Elt < <STR_LIT> ; Elt ++ ) { unsigned ToEltSize = UnpackFromEltSize * <NUM_LIT> ; bool IsZextByte = ( Elt % ToEltSize ) < UnpackFromEltSize ; if ( ! IsZextByte ) SrcBytes . push_back ( Bytes [ Elt ] ) ; if ( Bytes [ Elt ] != - <NUM_LIT> ) { unsigned OpNo = unsigned ( Bytes [ Elt ] ) / <STR_LIT> ; if ( IsZextByte != ( OpNo == ZeroVecOpNo ) ) { MatchUnpack = false ; break ; } } } if ( MatchUnpack ) { if ( Ops . size ( ) == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> / <NUM_LIT> ; i ++ ) if ( SrcBytes [ i ] != - <NUM_LIT> && SrcBytes [ i ] % <NUM_LIT> != int ( i ) ) { UnpackFromEltSize =


<s> return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) { switch ( IntrinsicID ) { case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) { switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot =


<s> assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT


<s> excp = lookup_attribute ( <STR_LIT> , func_attrs ) ; reset = lookup_attribute ( <STR_LIT> , func_attrs ) ; if ( ! intr && ! excp && ! reset ) return ; if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( <NUM_LIT> ) : ( <NUM_LIT> ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ <NUM_LIT> ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = TREE_INT_CST_LOW ( id ) + <NUM_LIT> + <NUM_LIT> ; strcpy ( nds32_isr_vectors [ <NUM_LIT> ] . func_name , func_name ) ; nmi = lookup_attribute ( <STR_LIT> , func_attrs ) ; warm = lookup_attribute ( <STR_LIT> , func_attrs


<s> static rtx_insn * emit_window_save ( rtx increment ) { rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn )


<s> if ( sparc_leaf_function_p || TARGET_FLAT ) { gcc_assert ( ! ( LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence ) ) ; if ( final_sequence ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> ,


<s> else if ( I -> getOperand ( k ) . isCImm ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getCImm ( ) ; } else if ( I -> getOperand ( k ) . isMBB ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getMBB ( ) -> getFullName ( ) << <STR_LIT> << I -> getOperand ( k ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand ( k ) . isSymbol ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getSymbolName ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand (


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitLD_F16_PSEUDO ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; unsigned Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) MIB . addOperand ( MI . getOperand ( i ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Rt ) ; MI . eraseFromParent


<s> } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InFlag ) ; } } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( BytesCalleePops , true ) , InFlag ) ; if ( ! Ins . empty ( ) ) InFlag =


<s> return ( float32x4_t ) __builtin_neon_vld1_dupv4sf ( ( const


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ; Inst . addOperand ( MCOperand :: createImm ( IsSigned


<s> void <ISA_LIT>TargetStreamer :: emitMovSP ( unsigned Reg , int64_t Offset ) { llvm_unreachable ( <STR_LIT> )


<s> if ( mode == SFmode ) store_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : store_string = <STR_LIT> ; break ; case E_HImode : store_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode : store_string = <STR_LIT> ; break ; case E_DImode : case E_DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT>


<s> int getDynAllocFI ( ) const { if ( ! DynAllocFI ) DynAllocFI = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT>


<s> return ( uint32x2_t ) __builtin_neon_vget_highv4si ( (


<s> Value * <ISA_LIT>IREmitter :: visitWrapperJT (


<s> return ( __m512i ) __builtin_ia32_pmovzxdq512_mask ( ( __v8si ) __X , ( __v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 )


<s> RTX_FRAME_RELATED_P ( y ) = <NUM_LIT> ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , x , y ) ) ; x = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , x , NULL ) ; REG_NOTES ( insn ) = x ; emit_insn ( gen_andsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) ; x = cfun -> machine -> force_align_arg_pointer ; x = gen_frame_mem ( Pmode , plus_constant ( x , - <NUM_LIT> ) ) ; insn = emit_insn ( gen_push ( x ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; x = GEN_INT ( <NUM_LIT> ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_DEF_CFA ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; x = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , x , NULL ) ; REG_NOTES ( insn ) = x ; } if ( frame_pointer_needed ) { insn = emit_insn ( gen_push ( hard_frame_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } allocate = frame . to_allocate ; if ( ! frame . save_regs_using_mov ) ix86_emit_save_regs ( ) ; else allocate += frame . nregs * UNITS_PER_WORD ; if ( TARGET_RED_ZONE && frame . save_regs_using_mov ) ix86_emit_save_regs_using_mov ( frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx , - frame . nregs * UNITS_PER_WORD ) ; if ( allocate == <NUM_LIT> ) ; else if ( ! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - allocate ) , - <NUM_LIT> ) ; else { rtx eax = gen_rtx_REG ( SImode , <NUM_LIT> ) ; bool eax_live = ix86_eax_live_at_start_p ( ) ; rtx t ; gcc_assert ( ! TARGET_64BIT ) ; if ( eax_live ) { emit_insn ( gen_push ( eax ) ) ; allocate -= <NUM_LIT> ; } emit_move_insn ( eax , GEN_INT ( allocate ) ) ; insn = emit_insn ( gen_allocate_stack_worker ( eax ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; t = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - allocate ) ) ; t = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , t ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , t , REG_NOTES ( insn ) ) ; if ( eax_live ) { if ( frame_pointer_needed ) t = plus_constant ( hard_frame_pointer_rtx , allocate - frame . to_allocate - frame . nregs * UNITS_PER_WORD ) ; else t = plus_constant ( stack_pointer_rtx , allocate ) ; emit_move_insn ( eax , gen_rtx_MEM ( SImode , t ) ) ; } } if ( frame . save_regs_using_mov && ! TARGET_RED_ZONE ) { if ( ! frame_pointer_needed || ! frame . to_allocate ) ix86_emit_save_regs_using_mov ( stack_pointer_rtx , frame . to_allocate ) ; else ix86_emit_save_regs_using_mov ( hard_frame_pointer_rtx , - frame . nregs * UNITS_PER_WORD ) ; } pic_reg_used = false ; if ( pic_offset_table_rtx && ( regs_ever_live [ REAL_PIC_OFFSET_TABLE_REGNUM ] || current_function_profile


<s> unsigned short s [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . s [ ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> )


<s> static __inline qword si_ila ( unsigned int imm ) { return ( ( qword ) ( vec_splat ( ( vec_uint4 ) ( si_from_uint ( imm ) ) , <NUM_LIT>


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; return MIN ( align ,


<s> bool can_inherit_p = ( initial_adjust . is_constant ( ) && final_adjust . is_constant ( ) && ! flag_stack_clash_protection ) ; bool need_barrier_p = maybe_ne ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size , <NUM_LIT> ) ; if ( maybe_gt ( final_adjust , crtl -> outgoing_args_size ) || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } rtx ip0_rtx = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; rtx ip1_rtx = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; if ( frame_pointer_needed && ( maybe_ne ( final_adjust , <NUM_LIT> ) || cfun -> calls_alloca ) ) aarch64_add_offset ( Pmode , stack_pointer_rtx , hard_frame_pointer_rtx , - callee_offset , ip1_rtx , ip0_rtx , callee_adjust == <NUM_LIT> ) ; else aarch64_add_sp ( ip1_rtx , ip0_rtx , final_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP1_REGNUM ) ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || maybe_gt ( initial_adjust , <NUM_LIT> ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( ip0_rtx , ip1_rtx , initial_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP0_REGNUM ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) =


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget -> hasXMMInt ( ) , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { unsigned NumElem = VT . getVectorNumElements ( ) ; int Size = VT . getSizeInBits ( ) ; if ( NumElem <= <NUM_LIT> && CanXFormVExtractWithShuffleIntoLoad ( Op , DAG , TLI ) ) return Op ; if ( Subtarget -> hasAVX ( ) && isVectorBroadcast ( V1 ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( ( Size == <NUM_LIT> && NumElem <= <NUM_LIT> ) || ( Size == <NUM_LIT> && NumElem < <NUM_LIT> ) ) return SDValue ( ) ; return PromoteSplat ( SVOp , DAG ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp


<s> const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( )


<s> unsigned int <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = <NUM_LIT> ; if ( ! Cond .


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs


<s> bool <ISA_LIT>PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , <NUM_LIT> > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = <NUM_LIT> , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } } return


<s> IsWin64 = Subtarget . isTargetWin64 ( ) ; if ( Is64Bit ) { SlotSize = <NUM_LIT> ; StackPtr = ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) ? <STR_LIT> : <STR_LIT> ; FramePtr = ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) ? <STR_LIT> : <STR_LIT> ; } else { SlotSize = <NUM_LIT>


<s> nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = <NUM_LIT> << ia64_rse_slot_num ( addr ) ; break ; } } } else { addr = ia64_rse_skip_regs ( ( unsigned long * ) info -> bsp , regnum - <NUM_LIT> ) ; nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = <NUM_LIT> << ia64_rse_slot_num ( addr ) ; } if ( write ) { * addr = * val ; if ( * nat ) * nat_addr |= nat_mask ; else * nat_addr &= ~ nat_mask ; } else { * val = *


<s> adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT>


<s> static bif_stanza stanza_name_to_stanza ( const char * stanza_name ) { for ( int i = <NUM_LIT> ; i < NUMBIFSTANZAS ; i ++ ) if ( ! strcmp ( stanza_name , stanza_map [ i ] . stanza_name ) ) return stanza_map [ i ] . stanza ; fatal ( <STR_LIT>


<s> assert ( ! FBB && <STR_LIT> ) ; auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += <NUM_LIT> ; return <NUM_LIT> ; } auto ConditionCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto a = Cond [ <NUM_LIT> ] ; auto b = Cond [ <NUM_LIT> ] ; unsigned Count = resolveComparison ( MBB , MBB . end ( ) , DL , ConditionCode , a , b ) ; if ( BytesAdded ) * BytesAdded += ( int ) Count * <NUM_LIT> ; BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += <NUM_LIT> ; Count ++


<s> temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c )


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst *


<s> } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getTargetData ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false


<s> int TargetMBB = getTargetMBB ( * Br ) -> getNumber ( ) ; if ( ThisMBB < TargetMBB ) { for ( int N = ThisMBB + <NUM_LIT> ; N < TargetMBB ; ++ N ) Offset += MBBInfos [ N


<s> case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm (


<s> if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) ,


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SP = <STR_LIT> ; unsigned ADDiu = <STR_LIT> ; unsigned StackAlign = getStackAlignment ( ) ; unsigned LocalVarAreaOffset = <ISA_LIT>FI -> getMaxCallFrameSize ( ) ; uint64_t StackSize = RoundUpToAlignment ( LocalVarAreaOffset , StackAlign ) + RoundUpToAlignment ( MFI -> getStackSize ( ) , StackAlign ) ; MFI -> setStackSize ( StackSize ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else { assert ( <STR_LIT> ) ; } MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP ,


<s> unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static inline unsigned getThumbImmValShift ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return CountTrailingZeros_32 ( Imm


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( TT . isOSNaCl ( ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { std :: string str ; raw_string_ostream OS ( str ) ; EmitSFIHeaders ( OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } initializeNaClMCStreamer ( OutStreamer , OutContext , TT


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , <NUM_LIT> ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++ I ; CurDAG -> DeleteNode


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) { EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; return getTargetShuffleInputs ( Op , DemandedElts , Inputs , Mask , KnownUndef ,

KnownZero , DAG , Depth , ResolveKnownElts ) ;


<s> int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID ,


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SuperReg ) ; else for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT>


<s> auto TheReg = <STR_LIT> ( RegString . lower


<s> LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Cond = CreateFPCmp ( DAG , Op


<s> case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xrstor ( void * __P , long


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm (


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt


<s> int i , regno ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { regno = ( last_scratch_gr_reg + i + <NUM_LIT> ) & <NUM_LIT> ; if ( call_used_regs [ regno ] && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) &


<s> return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false ,


<s> int i ; int retval = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) { rtx this_insn = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ; rtx set = single_set ( this_insn ) ; if ( GET_CODE ( this_insn ) == CALL_INSN ) code = CALL_INSN ; else if ( GET_CODE ( this_insn ) == JUMP_INSN ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return <NUM_LIT> ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return <NUM_LIT> ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( GET_CODE ( SET_DEST ( set ) ) != MEM ) retval = <NUM_LIT> ; else return <NUM_LIT> ; } if ( set == <NUM_LIT> && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return <NUM_LIT> ; } if ( retval == <NUM_LIT> ) return <NUM_LIT> ; else if ( code == JUMP_INSN ) return <NUM_LIT> ; } set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return <NUM_LIT> ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return GET_CODE ( SET_DEST ( set ) ) != MEM ; if ( set == <NUM_LIT> && reg_overlap_mentioned_p ( reg , PATTERN ( insn )


<s> getParser ( ) . eatToEndOfStatement ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>0Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) { if ( inMicro<ISA_LIT>Mode ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetNoDspDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetNo<ISA_LIT>3DDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMsaDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMsaDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMtDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMtDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetSoftFloatDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetHardFloatDirective ( ) ; if ( IdVal == <STR_LIT> || IdVal == <STR_LIT> ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AreCheriSysRegsAccessible = IdVal == <STR_LIT> ; return false ; } if ( IdVal == <STR_LIT> ) return


<s> return ( ( ( insn ) & <NUM_LIT> ) ==


<s> return ( __m64 ) __builtin_arm_wsubhus ( ( __v4hi ) __m1 , (


<s> static Register createDTuple ( ArrayRef < Register > Regs , MachineIRBuilder & MIB ) { static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs , SubRegs


<s> MCELFStreamer :: EmitInstruction ( Inst ,


<s> if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < <NUM_LIT> ; regno ++ ) { if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info ->


<s> enum mips_symbol_type symbol_type ; return ( mips_lo_relocs [ SYMBOL_GP_RELATIVE ] && ! mips_split_p [ SYMBOL_GP_RELATIVE ] && mips_symbolic_constant_p ( x , context , &


<s> } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQ ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQMasked ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } assert ( table && <STR_LIT> ) ; MI . setDesc ( get ( table [ Domain - <NUM_LIT>


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Default


<s> return ( vector signed char ) __builtin_altivec_vpkshss ( ( vector signed short ) a1 , ( vector


<s> EVT VT = TLI . getValueType ( I -> getType ( ) , true ) ; const Type * Ty = I -> getType ( ) ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return


<s> ++ It ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfTrueReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfFalseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool NZCVKilled = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB


<s> bool <ISA_LIT>FastISel :: computeAddress ( const Value * Obj , Address & Addr ) { const User * U = nullptr ; unsigned Opcode = Instruction :: UserOp1 ; if ( const Instruction * I = dyn_cast < Instruction > ( Obj ) ) { if ( FuncInfo . StaticAllocaMap . count ( static_cast < const AllocaInst * > ( Obj ) ) || FuncInfo . MBBMap [ I -> getParent ( ) ] == FuncInfo . MBB ) { Opcode = I -> getOpcode ( ) ; U = I ; } } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int64_t TmpOffset = Addr . getOffset (


<s> void EmitByte ( unsigned char C , raw_ostream & OS


<s> rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body )


, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> int Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; int ThisVal = ( Imm > Chunk ) ? Chunk : Imm ; Imm -= ThisVal ; AddDefaultPred ( AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) ) . addImm ( ThisVal ) ) ; if ( Imm > <NUM_LIT> ) emitThumbRegPlusImmediate ( MBB , MBBI , dl , DestReg , DestReg , Imm , TII ,


<s> if ( isThumb2 ( ) ) return :: getBranchTargetOpValue ( MI


<s> union { vec_uint4 v ; unsigned long long ll [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ; return tmp ==


<s> SDValue R = CMPEQCombine ( N , DAG , DCI , Subtarget ) ; if ( R . getNode ( ) ) return R ; if ( Subtarget -> hasBMI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isZero ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isZero ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand


<s> return ( __m128i ) __builtin_ia32_vcvtph2w128_mask ( __B , (


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue SelectOp , Phi ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op0 ; Phi = Op1


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setMacro ( ) ; getTargetStreamer ( ) . emitDirectiveSetMacro ( ) ; Parser . Lex


<s> void addVectorListOperands ( MCInst & Inst , unsigned N


<s> return ( __m128i ) __builtin_ia32_movntdqa ( ( __v2di *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForceAllBaseRegAlloc ) return true ; break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * Expr )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { TargetRegistry :: RegisterMCAsmInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; int64_t Offset ; if ( TII -> getMemOpBaseRegImmOfs ( MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( MI ) ; } PrevBaseReg =


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return cfun -> machine -> frame . reg_offset [


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream


<s> bool IsStrict = N -> isTargetStrictFPOpcode ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue In = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; if ( IsStrict ) { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , DAG . getBitcast ( InVT , VZLoad ) } ) ; DCI . CombineTo ( N , Convert , Convert . getValue ( <NUM_LIT> ) ) ; } else { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert )


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr ,


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) - <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << Reg << '\n' ) ; BuildMI ( * MBB , Inst , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; pushReg ( Reg ) ; break ; } case TargetOpcode :: INLINEASM : { unsigned STUses = <NUM_LIT> , STDefs = <NUM_LIT> , STClobbers = <NUM_LIT> , STDeadDefs = <NUM_LIT> ; unsigned NumOps = <NUM_LIT> ; SmallSet < unsigned , <NUM_LIT> > FRegIdx ; unsigned RCID ; for ( unsigned i = InlineAsm :: MIOp_FirstOperand , e = MI . getNumOperands ( ) ; i != e && MI . getOperand ( i ) . isImm ( ) ; i += <NUM_LIT> + NumOps ) { unsigned Flags = MI . getOperand ( i ) . getImm ( ) ; NumOps = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumOps != <NUM_LIT> ) continue ; const MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) continue ; unsigned STReg = MO . getReg ( ) - <STR_LIT> ; if ( STReg >= <NUM_LIT> ) continue ; if ( InlineAsm :: hasRegClassConstraint ( Flags , RCID ) ) { FRegIdx . insert ( i + <NUM_LIT> ) ; continue ; } switch ( InlineAsm :: getKind ( Flags ) ) { case InlineAsm :: Kind_RegUse : STUses |= ( <NUM_LIT> << STReg ) ; break ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : STDefs |= ( <NUM_LIT> << STReg ) ; if ( MO . isDead ( ) ) STDeadDefs |= ( <NUM_LIT> << STReg ) ; break ; case InlineAsm :: Kind_Clobber : STClobbers |= ( <NUM_LIT> << STReg ) ; break ; default : break ; } } if ( STUses && ! isMask_32 ( STUses ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI . emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI . emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ;


<s> gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNoVirt


<s> TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . emitInstruction (


<s> case REG_DEP_OUTPUT : dep = <STR_LIT> ; break ; case REG_DEP_ANTI : dep = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> <STR_LIT> , ret , cost , dep ) ; debug_rtx ( insn ) ; } return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr11MM ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT>


<s> case SYMBOL_REF : output_addr_const ( stream , x ) ; break ; case REG : if ( TARGET_REDUCED_REGS && REGNO ( x ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; fputs ( reg_names [ REGNO ( x ) ] , stream ) ; break ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) ) ; break ; case CODE_LABEL : case CONST_INT : case