<s> getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm


<s> break ; case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; uint64_t TSFlags = Desc


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction


<s> SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > TmpReg ; OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal (


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo (


<s> error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; break ; default : gcc_unreachable ( ) ; } return false


<s> bool <ISA_LIT>InstructionSelector :: selectShift ( unsigned ShiftOpc , MachineInstrBuilder & MIB ) const { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( ShiftOpc ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI ,


<s> if ( Operands . size ( ) < <NUM_LIT> || ! IsRegister ( * Operands [ <NUM_LIT> ] ) || ! IsRegister ( * Operands [ <NUM_LIT> ] ) ) return false ; return StringSwitch < bool > ( static_cast < const <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getToken ( ) ) . StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true )

. StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true ) . StartsWith ( <STR_LIT> , true ) . Default ( false ) ;


<s> unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDValue Src = Op . getOperand ( OpNo ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! Subtarget . hasDQI ( ) || SrcVT != <STR_LIT> || Subtarget . is64Bit ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) return SDValue ( ) ; unsigned NumElts = Subtarget . hasVLX ( ) ? <NUM_LIT> : <NUM_LIT> ; MVT VecInVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; MVT VecVT = <STR_LIT> ( VT , NumElts ) ; SDLoc dl ( Op ) ; SDValue InVec = DAG . getNode ( <STR_LIT> , dl , VecInVT , Src ) ; if ( IsStrict )


<s> if ( OptLevel != CodeGenOpt :: None && ! DisableIfConversion && ! Subtarget . isThumb

( ) ) PM . add ( createIfConverterPass ( ) ) ;


<s> newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - <NUM_LIT> ] . value ) ) { lab = <NUM_LIT> ; pool_vector [ pool_size - <NUM_LIT> ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == <NUM_LIT> ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next =


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget (


<s> const TargetRegisterClass * GPRRC = Subtarget . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned SubRegIdx = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <NUM_LIT> ; unsigned ShiftOp = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned EltLog2Size ; unsigned InsertOp = <NUM_LIT> ; unsigned InsveOp = <NUM_LIT> ; switch ( EltSizeInBytes ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( ShiftOp ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg , <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerADDROFRETURNADDR ( SDValue Op , SelectionDAG


<s> break ; } if ( I -> readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == <NUM_LIT> && ConditionDef -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( ConditionDef -> getOperand ( <NUM_LIT> ) ) && ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) ) { MBP . LHS = ConditionDef -> getOperand ( <NUM_LIT>


<s> void LLVMInitializePowerPCTarget ( ) { RegisterTargetMachine < <ISA_LIT>32TargetMachine > A ( The<ISA_LIT>32Target ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > C


<s> return pru_add3_frame_adjust ( stack_pointer_rtx , stack_pointer_rtx , addendum , kind


<s> else if ( type_node == double_type_node ) return <STR_LIT> ; else if ( type_node == intDI_type_node ) return <STR_LIT> ; else if ( type_node == intHI_type_node ) return <STR_LIT> ; else if ( type_node == ibm128_float_type_node ) return <STR_LIT> ; else if ( type_node == ieee128_float_type_node ) return <STR_LIT> ; else if ( type_node == opaque_V4SI_type_node ) return <STR_LIT> ; else if ( POINTER_TYPE_P ( type_node ) ) return <STR_LIT> ; else if ( type_node == intQI_type_node || type_node == char_type_node ) return <STR_LIT> ; else if ( type_node == dfloat32_type_node ) return <STR_LIT> ; else if ( type_node == float_type_node ) return <STR_LIT> ; else if ( type_node == intSI_type_node || type_node == integer_type_node ) return <STR_LIT> ; else if ( type_node == dfloat128_type_node ) return <STR_LIT> ; else if ( type_node == long_double_type_node ) return <STR_LIT> ; else if ( type_node == intTI_type_node ) return <STR_LIT> ; else if ( type_node == unsigned_intDI_type_node ) return <STR_LIT> ; else if ( type_node == unsigned_intHI_type_node ) return <STR_LIT> ; else if ( type_node == unsigned_intQI_type_node ) return <STR_LIT> ; else if ( type_node == unsigned_intSI_type_node ) return <STR_LIT> ; else if ( type_node == unsigned_intTI_type_node


<s> static unsigned countMCSymbolRefExpr ( const MCExpr * Expr ) { if ( isa < MCSymbolRefExpr > ( Expr ) ) return <NUM_LIT> ; if ( const MCBinaryExpr * BExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( BExpr -> getLHS ( ) ) + countMCSymbolRefExpr ( BExpr -> getRHS ( ) ) ; if ( const MCUnaryExpr * UExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( UExpr -> getSubExpr ( ) ) ; return


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>MachObjectWriter ( false , MachO


<s> SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; unsigned StoreAddrReg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame , DAG .

getIntPtrConstant ( TD -> getPointerSize ( ) ) ) ;


<s> Instruction * <ISA_LIT>TargetLowering :: makeDMB ( IRBuilder < > & Builder , <STR_LIT> Domain ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { if ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) ) { Function * MCR = <STR_LIT> ( M ,


<s> bool isMemNoOffsetT ( bool alignOK = false , unsigned Alignment = <NUM_LIT> ) const { if ( ! isGPRMem ( ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK


<s> unsigned NumOriginalElts = OriginalVT . getVectorNumElements ( ) ; InVec = peekThroughOneUseBitcasts ( InVec ) ; EVT CurrentVT = InVec . getValueType ( ) ; if ( ! CurrentVT . isVector ( ) ) return SDValue ( ) ; unsigned NumCurrentElts = CurrentVT . getVectorNumElements ( ) ; if ( ( NumOriginalElts % NumCurrentElts ) != <NUM_LIT> ) return SDValue ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , true , ShuffleOps , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned Scale = NumOriginalElts / NumCurrentElts ; if ( Scale > <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ScaledMask ; scaleShuffleMask < int > ( Scale , ShuffleMask , ScaledMask ) ; ShuffleMask = std :: move ( ScaledMask ) ; } assert ( ShuffleMask . size ( ) == NumOriginalElts && <STR_LIT> ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumOriginalElts ) ? SM_SentinelUndef : ShuffleMask [ Elt ] ; if ( Idx == SM_SentinelZero ) return EltVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , EltVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , EltVT ) ; if ( Idx == SM_SentinelUndef ) return DAG


<s> if ( UnsupportedFPMode ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; if ( ! DestReg ) return false ; emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return


<s> GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; DebugLoc DL = GSDN -> getDebugLoc ( ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOLoFlag ) ; SDValue Ptr = LowerLabelRef ( GAHi , GALo , isPIC , DAG ) ; if ( MOHiFlag & <STR_LIT> ) Ptr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; return Ptr


<s> if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns


<s> SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } } if ( NotAlways ) continue ; Instruction * TI = ( * I ) -> getTerminator ( ) ; if ( ! TI )


<s> SMLoc Result = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; return Result


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock


<s> if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << markup ( <STR_LIT>


<s> } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml ::


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand (

<NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; } if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { addPass ( & LiveVariablesID , false


<s> bool <ISA_LIT>_MC :: is32BitMemOperand ( const MCInst & MI , unsigned Op ) { const MCOperand & Base = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & Index = MI . getOperand ( Op + <STR_LIT> ) ; if ( Base . isReg ( ) && Base . getReg ( ) == <STR_LIT> ) { assert ( Index . isReg ( ) && Index . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; return


<s> return Insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ML -> getHeader ( ) -> getName ( ) << <STR_LIT> ) ; MachineInstr * LoopEnd , * LoopPhi , * LoopStart , * LoopDec ; if ( ! findLoopComponents ( ML , MRI , LoopStart , LoopPhi , LoopDec , LoopEnd ) ) return false ; if ( LoopStart -> getOpcode ( ) != <STR_LIT> ) return false ; Register LR = LoopStart -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto WLSIt = find_if ( MRI -> use_nodbg_instructions ( LR ) , [ ] ( auto & MI ) { return MI . getOpcode ( ) == <STR_LIT> ; } ) ; if ( ! MergeEndDec || WLSIt == MRI -> use_instr_nodbg_end ( ) ) { RevertWhileLoopSetup ( LoopStart , TII ) ; RevertLoopDec ( LoopStart , TII ) ; RevertLoopEnd ( LoopStart , TII ) ; return true ; } MachineInstrBuilder MI = BuildMI ( * WLSIt -> getParent ( ) , * WLSIt , WLSIt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , LR ) . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) . add ( WLSIt -> getOperand ( <NUM_LIT> ) ) ; ( void ) MI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI . getInstr ( ) ) ; WLSIt -> eraseFromParent


<s> unsigned getLongFormOpcode ( ) const { return


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack (


<s> if ( InOp . getOpcode ( ) == <STR_LIT> && InOp . getNumOperands ( ) == <NUM_LIT> ) { SDValue N1 = InOp . getOperand ( <NUM_LIT> ) ; if ( ( <STR_LIT> ( N1 . getNode ( ) ) && FillWithZeroes ) || N1 . isUndef ( ) ) { InOp = InOp . getOperand ( <NUM_LIT> ) ; InVT = InOp . getSimpleValueType ( ) ; InNumElts = InVT . getVectorNumElements ( ) ; } } if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> ( InOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < InNumElts ; ++ i ) Ops . push_back ( InOp . getOperand ( i ) ) ; EVT EltVT = InOp . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , EltVT ) : DAG . getUNDEF ( EltVT ) ; for ( unsigned i = <NUM_LIT> ; i < WidenNumElts - InNumElts ; ++ i


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) .

addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) ;


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { gcc_assert ( sparc_leaf_function_p

== current_function_uses_only_leaf_regs ) ;


<s> int Idx = cast < ConstantSDNode > ( ExtIdx ) -> getZExtValue ( ) ; if ( ! isa < ShuffleVectorSDNode > ( ExtractedFromVec ) ) return Idx ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( ExtractedFromVec ) ; SDValue ShuffleVec = SVOp -> getOperand ( <NUM_LIT> ) ; MVT ShuffleVecVT = ShuffleVec . getSimpleValueType ( ) ; assert ( ShuffleVecVT . getVectorElementType ( ) == ExtractedFromVec . getSimpleValueType ( ) . getVectorElementType ( ) ) ; int ShuffleIdx = SVOp -> getMaskElt


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressWindows ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; assert ( ! Subtarget -> isROPI ( ) && ! Subtarget -> isRWPI ( ) && <STR_LIT> ) ; assert ( ! Subtarget -> isPIP ( ) && <STR_LIT> ) ; const TargetMachine & TM = getTargetMachine ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; <STR_LIT> TargetFlags = <STR_LIT> ; if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags = <STR_LIT> ; else if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) TargetFlags = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG .


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ,


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; bool OffsetFitsMnemonic = ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ? isUInt < <NUM_LIT> > ( Offset ) : isInt < <NUM_LIT> > ( Offset ) ; if ( ! noImmForm && ( ( OffsetFitsMnemonic && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; Register SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Offset ) ) BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset ) ; else { BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ; } unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM &&


<s> void arm_reload_in_hi ( rtx * operands ) { rtx ref = operands [ <NUM_LIT> ] ; rtx base , scratch ; HOST_WIDE_INT offset = <NUM_LIT> ; if ( SUBREG_P ( ref ) ) { offset = SUBREG_BYTE ( ref ) ; ref = SUBREG_REG ( ref ) ; } if ( REG_P ( ref ) ) { if ( reg_equiv_mem ( REGNO ( ref ) ) ) { ref = reg_equiv_mem ( REGNO ( ref ) ) ; base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; } else base = reg_equiv_address ( REGNO ( ref ) ) ; if ( base == NULL ) { gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movsi ( gen_rtx_SUBREG ( SImode , operands [ <NUM_LIT> ] , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , ref , <NUM_LIT> ) ) ) ; return ; } } else base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; if ( GET_CODE ( base ) == MINUS || ( GET_CODE ( base ) == PLUS && ! CONST_INT_P ( XEXP ( base , <NUM_LIT> ) ) ) ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi ) ) ) ; base = base_plus ; offset = lo ; } } if ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) scratch = gen_rtx_REG ( SImode , REGNO ( operands


<s> return new <ISA_LIT>SEInstrInfo ( TM


<s> int EltIdx = MaskVals [ i ] ; if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return false ; } if ( MaskOut ) * MaskOut = MaskValue ; return true


<s> switch ( BLR . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : BLOpcode = <STR_LIT> ; Reg = BLR . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) ; RegIsKilled = BLR . getOperand ( <NUM_LIT> ) . isKill ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = BLR . getDebugLoc ( ) ; MachineFunction & MF = * MBBI -> getMF ( ) ; MCContext & Context = MBB . getParent ( ) -> getContext ( ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ Reg ] ( auto T ) { return T . Reg == Reg ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( ThunkIt -> Name ) ; MachineInstr * BL = BuildMI ( MBB , MBBI , DL , TII -> get ( BLOpcode ) ) . addSym ( Sym ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> removeOperand ( FirstOpIdxToRemove ) ; BL -> removeOperand ( SecondOpIdxToRemove ) ; BL -> copyImplicitOps ( MF , BLR ) ; MF . moveCallSiteInfo ( &


<s> } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg (


<s> } else if ( CRSpillFrameIdx ) { FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( const_cast < MachineFunction & > ( MF ) ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; CRSpillFrameIdx =


<s> if ( SDValue R = FlattenVectorShuffle ( cast < ShuffleVectorSDNode > ( N ) , DAG ) ) return R ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getNumOperands ( ) != <NUM_LIT> || Op1 . getNumOperands ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! Concat0Op1 . isUndef ( ) || ! Concat1Op1 . isUndef ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG .


<s> switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Mask = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static const <ISA_LIT>MCExpr * createHi ( const MCExpr * Expr , MCContext &


<s> const unsigned CarryOutReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Def = MRI . getVRegDef


<s> __v2du lshift ; __vector __bool long long shmask ; const __v2du shmax = { <NUM_LIT> , <NUM_LIT> } ; __v2du result ; lshift = vec_splat ( ( __v2du ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( lshift , shmax ) ; result = vec_sl ( ( __v2du


<s> ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SUnit & ExitSU = DAG -> ExitSU ; MachineInstr * Branch = ExitSU . getInstr ( ) ; if ( ! shouldScheduleAdjacent ( ST , nullptr , Branch ) ) return ; for ( SDep & PredDep : ExitSU . Preds ) { if ( PredDep . isWeak ( ) ) continue ; SUnit & SU = * PredDep . getSUnit (


<s> tga_op1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_load_dtpmod ( tga_op1 , op1 ) ) ; tga_op2 = const0_rtx ; tga_ret = emit_library_call_value ( gen_tls_get_addr ( ) , NULL_RTX , LCT_CONST , Pmode , <NUM_LIT> , tga_op1 , Pmode , tga_op2 , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; tga_eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LD_BASE ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , tmp , tga_ret , tga_eqv ) ; if ( ! register_operand ( op0 , Pmode ) ) op0 = gen_reg_rtx ( Pmode ) ; if ( TARGET_TLS64 ) { emit_insn ( gen_load_dtprel ( op0 , op1 ) ) ; emit_insn ( gen_adddi3 ( op0 , tmp , op0 ) ) ; } else emit_insn ( gen_add_dtprel ( op0 , op1 , tmp ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : addend_lo = ( ( addend & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; addend_hi = addend - addend_lo ; op1 = plus_constant ( Pmode , op1 , addend_hi ) ; addend = addend_lo ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_load_tprel ( tmp , op1 ) ) ; if ( ! register_operand ( op0 , Pmode ) ) op0


<s> unsigned LaneStart = l * NumLaneElems ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , SVOps ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) : Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; Output [ l ] = DAG . getVectorShuffle ( NVT , dl , Op0


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return false ; assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT>


<s> void MBBInfo :: postVisit ( ) { delete


<s> if ( GET_CODE ( src ) == LO_SUM && symbolic_operand ( XEXP ( src , <NUM_LIT> ) , VOIDmode ) && ! read_only_operand ( XEXP ( src , <NUM_LIT> ) , VOIDmode ) ) priority >>= <NUM_LIT> ; else if ( GET_CODE ( src ) == MEM && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP (

src , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) priority >>= <NUM_LIT> ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry (


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT


<s> if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , <NUM_LIT> ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT> ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , <NUM_LIT> ) ) ; } else if ( GET_CODE ( addr ) ==


<s> return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , <NUM_LIT> ) ; SrcVec = Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( SrcVec , DL ,

SubVT ) : DAG . getZeroExtendVectorInReg ( SrcVec , DL , SubVT ) ;


<s> int idx , vlen = XVECLEN ( body , <NUM_LIT> ) ; ASM_OUTPUT_ADDR_VEC_START ( asm_out_file ) ; ASM_OUTPUT_CASE_LABEL ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) , NEXT_INSN ( lab ) ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER (


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool


<s> bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor


<s> unsigned Emitter < CodeEmitter > :: get<ISA_LIT>RegNum ( unsigned RegNo ) const { return II -> getRegisterInfo ( ) . get<ISA_LIT>RegNum ( RegNo


<s> { rtx operands [ <NUM_LIT> ] ; split_di ( & operand , <NUM_LIT> , operands , operands + <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ <NUM_LIT> ] ) ) ; } break ; case HImode : operand = gen_lowpart ( SImode , operand ) ; case


<s> SDValue SafeShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , SafeShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) ==


<s> if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg ( Memory


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ,


<s> return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand ::


<s> return __builtin_loongson_psubh_u ( s , t


<s> } current = scratch_reg ; } ix86_expand_branch ( GEU , current , limit , label ) ; rtx_insn * jump_insn = get_last_insn ( ) ; JUMP_LABEL ( jump_insn ) = label ; add_reg_br_prob_note ( jump_insn , profile_probability :: very_likely ( ) ) ; if ( split_stack_fn == NULL_RTX ) { split_stack_fn = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( split_stack_fn ) |= SYMBOL_FLAG_LOCAL ; } fn = split_stack_fn ; allocate_rtx = GEN_INT ( allocate ) ; args_size = crtl -> args . size >= <NUM_LIT> ? ( HOST_WIDE_INT ) crtl -> args . size : <NUM_LIT> ; call_fusage = NULL_RTX ; rtx pop = NULL_RTX ; if ( TARGET_64BIT ) { rtx reg10 , reg11 ; reg10 = gen_rtx_REG ( Pmode , R10_REG ) ; reg11 = gen_rtx_REG ( Pmode , R11_REG ) ; if ( DECL_STATIC_CHAIN ( cfun -> decl ) ) { rtx rax ; rax = gen_rtx_REG ( word_mode , AX_REG ) ; emit_move_insn ( rax , gen_rtx_REG ( word_mode , R10_REG ) ) ; use_reg ( & call_fusage , rax ) ; } if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ! TARGET_PECOFF ) { HOST_WIDE_INT argval ; gcc_assert ( Pmode == DImode ) ; gcc_assert ( ( allocate & HOST_WIDE_INT_C ( <NUM_LIT> ) ) == allocate ) ; gcc_assert ( ( args_size & <NUM_LIT> ) == args_size ) ; if ( split_stack_fn_large == NULL_RTX ) { split_stack_fn_large = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( split_stack_fn_large ) |= SYMBOL_FLAG_LOCAL ; } if ( ix86_cmodel == CM_LARGE_PIC ) { rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = <NUM_LIT> ; emit_insn ( gen_set_rip_rex64 ( reg10 , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( reg11 , label ) ) ; emit_insn ( ix86_gen_add3 ( reg10 , reg10 , reg11 ) ) ; x = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , split_stack_fn_large ) , UNSPEC_GOT ) ; x = gen_rtx_CONST ( Pmode , x ) ; emit_move_insn ( reg11 , x ) ; x = gen_rtx_PLUS ( Pmode , reg10 , reg11 ) ; x = gen_const_mem ( Pmode , x ) ; emit_move_insn ( reg11 , x ) ; } else emit_move_insn ( reg11 , split_stack_fn_large ) ; fn = reg11 ; argval = ( ( args_size << <NUM_LIT> ) << <NUM_LIT> ) + allocate ; emit_move_insn ( reg10 , GEN_INT ( argval ) ) ; } else { emit_move_insn ( reg10 , allocate_rtx ) ; emit_move_insn ( reg11 , GEN_INT ( args_size ) ) ; use_reg ( & call_fusage


<s> switch ( RMWOpcode ) { case <STR_LIT> : PairedCopy ( TII , * CurrentMBB , CurrentMBB -> end ( ) , DL , ScratchHi , ScratchLo , IncrHi , IncrLo ) ; break ; case <STR_LIT> : BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( IncrLo ) . addReg ( OldLo ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchHi ) . addReg ( IncrHi ) . addReg ( OldHi ) ; break ; case <STR_LIT> : BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( IncrLo ) . addReg ( OldLo ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchHi ) . addReg ( IncrHi ) . addReg ( OldHi ) ; break ; case Opcode : \ BuildMI ( CurrentMBB , DL , TII -> get ( ( Instr ) ) , ScratchLo ) \ . addReg ( IncrLo ) \ . addReg ( OldLo ) ; \ BuildMI ( CurrentMBB , DL , TII -> get ( ( Instr ) ) , ScratchHi ) \ . addReg ( IncrHi ) \ . addReg ( OldHi ) ; \ break TRIVIAL_ATOMICRMW ( <STR_LIT> , <STR_LIT> ) ; TRIVIAL_ATOMICRMW ( <STR_LIT> , <STR_LIT> ) ; TRIVIAL_ATOMICRMW ( <STR_LIT> , <STR_LIT> ) ; TRIVIAL_ATOMICRMW ( <STR_LIT> , <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( CurrentMBB , DL , SC ) . addReg ( Scratch ) . addReg ( RA ) . addReg ( RB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( LoopMBB ) ; CurrentMBB -> addSuccessor ( LoopMBB ) ; CurrentMBB -> addSuccessor ( ExitMBB ) ; recomputeLiveIns ( * LoopMBB ) ; recomputeLiveIns ( * ExitMBB ) ; NMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; return true


<s> SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ext64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Ext64 , FIdx } ; SDValue Store = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; SDValue Ld = DAG . getLoad ( <STR_LIT> , dl , Store , FIdx , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl ,


<s> bool MandarinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo (


<s> SysAlias ( const char * N , uint16_t E , FeatureBitset F ) : Name ( N ) , Encoding ( E ) , FeaturesRequired ( F


<s> union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , cc , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c


<s> Data64bitsDirective = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; HasSetDirective = false


<s> RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; } if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto SHA1Inst = MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { SrcReg } ) ; constrainSelectedInstRegOperands ( * SHA1Inst , TII , TRI , RBI ) ; if ( DstReg != I . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIRBuilder . buildCopy ( { I . getOperand ( <NUM_LIT>


<s> unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode = getOpcodeForOffset ( isHighReg ( Reg ) ? HighOpcode : LowOpcode , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MI -> setDesc ( get (


<s> const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned DefReg = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( DefReg , RegBank ) ; if ( ! emitInsertSubreg ( DefReg , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I , MRI , MF ) ) return false ; for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; ++ Idx ) { unsigned Tmp = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , STI , false


<s> if ( associated_type ( decl ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllimport_p ( decl ) ; return false


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeSoReg ( SDValue N , SDValue & Base , SDValue & OffReg , SDValue & ShImm ) { return true


<s> VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SVI -> getType ( ) -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ; SubVecs [ SVI ] . push_back ( SubVec ) ; } } for ( ShuffleVectorInst * SVI : Shuffles ) { auto & SubVec = SubVecs


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ! <STR_LIT> . hasSubClassEq (


<s> return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm3_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed


<s> unsigned getNonFlagSettingVariant ( unsigned Opc ) { switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo (


<s> } if ( mask == - <NUM_LIT> ) { if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_one_cmplsi2 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_ck801_one_cmplsi2 ( operands [ <NUM_LIT> ] , operands [


<s> static unsigned GetScratchRegister ( bool Is64Bit , bool IsLP64 , const MachineFunction & MF , bool Primary ) { CallingConv :: ID CallingConvention = MF . getFunction ( ) . getCallingConv ( ) ; if ( CallingConvention == CallingConv :: HiPE ) { if ( Is64Bit ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT> : <STR_LIT> ; } if ( Is64Bit ) { if ( IsLP64 ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT> : <STR_LIT> ; } bool IsNested = HasNestArgument ( & MF ) ; if ( CallingConvention == CallingConv :: <ISA_LIT>_FastCall || CallingConvention == CallingConv :: Fast || CallingConvention == CallingConv :: Tail ) { if ( IsNested ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return Primary ? <STR_LIT>


<s> inline vector unsigned short vec_vmrglh ( vector unsigned short


<s> return ( vector unsigned int ) __builtin_altivec_vmsumubm ( ( vector signed char ) a1 , ( vector signed char ) a2 , ( vector


<s> if ( ! IsVector && ! Op . isRegList ( ) ) return Error ( L , <STR_LIT> ) ; if ( IsVector && ! Op . isDPRRegList ( ) ) return Error ( L , <STR_LIT> ) ; getTargetStreamer ( ) . emitRegSave ( Op


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT


_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true


<s> bool aarch_rev16_shright_mask_imm_p ( rtx val , machine_mode mode ) { return CONST_INT_P ( val ) && INTVAL ( val ) == trunc_int_for_mode ( HOST_WIDE_INT_C ( <NUM_LIT> )


<s> return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) )


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { Target & T = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmInfo ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter (


<s> SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( Sel . getOpcode ( ) != <STR_LIT> || ! collectConcatOps ( Sel . getOperand ( <NUM_LIT> ) . getNode ( ) , CatOps , DAG ) ) return SDValue ( ) ; MVT VT = Ext -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; MVT SelCondVT = Sel . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! SelCondVT . is256BitVector ( ) && ! SelCondVT . is512BitVector ( ) ) return SDValue ( ) ; MVT WideVT = Ext -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT SelVT = Sel . getSimpleValueType ( ) ; assert ( ( SelVT . is256BitVector ( ) || SelVT . is512BitVector ( ) ) && <STR_LIT> ) ; unsigned SelElts = SelVT . getVectorNumElements ( ) ; unsigned CastedElts = WideVT . getVectorNumElements ( ) ; unsigned ExtIdx = Ext -> getConstantOperandVal ( <NUM_LIT> ) ; if ( SelElts % CastedElts == <NUM_LIT> ) { ExtIdx *= ( SelElts / CastedElts ) ; } else if ( CastedElts % SelElts == <NUM_LIT> ) { unsigned IndexDivisor = CastedElts / SelElts ; if ( ExtIdx % IndexDivisor != <NUM_LIT> ) return SDValue ( ) ; ExtIdx /= IndexDivisor ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NarrowingFactor = WideVT . getSizeInBits ( ) / VT . getSizeInBits ( ) ; unsigned NarrowElts = SelElts / NarrowingFactor ; MVT NarrowSelVT = <STR_LIT> ( SelVT . getVectorElementType ( ) , NarrowElts ) ; SDLoc DL ( Ext ) ; SDValue ExtCond = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtT = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtF = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG ,


<s> high = loongarch_const_insns ( loongarch_subword ( x , true ) ) ; gcc_assert ( low > <NUM_LIT>


<s> bool <ISA_LIT>AsmParser :: classifySymbolRef ( const MCExpr * Expr , <ISA_LIT>MCExpr :: VariantKind & Kind , int64_t & Addend ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Kind = RE -> getKind ( ) ; Expr = RE -> getSubExpr ( ) ; } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Wd_in = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Fs = MI . getOperand ( <NUM_LIT> ) .


<s> return decodeBDAddr12Operand ( Inst , Field


<s> DebugLoc DL ; bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { DL = MBBI -> getDebugLoc ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } int NumBytes = MFI -> getStackSize ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; uint64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; ArgumentPopSize = StackAdjust . getImm ( ) ; } else { ArgumentPopSize = AFI -> getArgumentStackToRestore ( ) ; } NumBytes += ArgumentPopSize ; unsigned NumRestores = <NUM_LIT> ; MachineBasicBlock :: iterator LastPopI = MBB . getFirstTerminator (


<s> TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getTarget ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; LIs = LI ; DEBUG ( MF -> dump ( ) ; ) ; for ( MachineFunction :: const_iterator mbbItr = MF -> begin ( ) , mbbEnd = MF -> end ( ) ; mbbItr != mbbEnd ; ++ mbbItr ) { const MachineBasicBlock * MBB = & * mbbItr ; Chains . clear ( ) ; for ( MachineBasicBlock :: const_iterator miItr = MBB -> begin ( ) , miEnd = MBB -> end ( ) ; miItr != miEnd ; ++ miItr ) { const MachineInstr * MI = & * miItr ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case


<s> Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM .


<s> MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I ++ ) ; } while ( ( I != E )


<s> if ( MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) { NewI = MIRBuilder . buildInstr ( <STR_LIT> , { s64 , s64 } , { } ) ; MIRBuilder . buildMerge ( ValReg , { NewI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) } ) ; } else { auto Split = MIRBuilder . buildUnmerge ( s64 , MI . getOperand ( <NUM_LIT> ) ) ; NewI = MIRBuilder . buildInstr ( <STR_LIT> , { } , { Split -> getOperand ( <NUM_LIT> ) , Split -> getOperand ( <NUM_LIT> ) } ) ; } Register Base ; int Offset ; matchLDPSTPAddrMode ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Base , Offset , MRI ) ; NewI . addUse ( Base ) ; NewI . addImm ( Offset / <NUM_LIT> ) ; NewI . cloneMemRefs ( MI ) ; constrainSelectedInstRegOperands ( * NewI , * ST -> getInstrInfo ( ) , * MRI . getTargetRegisterInfo ( ) , * ST -> getRegBankInfo ( ) ) ; MI . eraseFromParent ( ) ; return true ; } if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getElementCount ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; MMO . setType (


<s> if ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) return false ; } } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return


<s> void <ISA_LIT>MCCodeEmitter :: EmitImmediate ( const MCOperand & DispOp , SMLoc Loc , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { const MCExpr * Expr = nullptr ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind (


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst ) ; } else if ( HasSSE2 ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue LHS ; uint32_t ShiftLHS = <NUM_LIT> ; bool LHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , LHS , ShiftLHS , LHSFromHi ) ) return SDValue ( ) ; SDValue RHS ; uint32_t ShiftRHS = <NUM_LIT> ; bool RHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , RHS , ShiftRHS , RHSFromHi ) ) return SDValue ( ) ; if ( LHSFromHi == RHSFromHi ) return SDValue ( ) ; if ( ShiftLHS + ShiftRHS != VT . getSizeInBits ( ) ) return


<s> LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( )


<s> return ( __m256d ) __builtin_ia32_unpckhpd256 ( ( __v4df ) __A , (


) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , <NUM_LIT> ) ; dest = XEXP ( dest , <NUM_LIT> ) ; dest_uid = INSN_UID ( dest


<s> unsigned Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint , isVector ? <STR_LIT>


<s> return build_string_literal ( strlen ( objfmt ) + <NUM_LIT> , objfmt


<s> MIB . add ( TheVCMP -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; LoLoop . ToRemove . insert ( TheVCMP ) ; TheVCMP = nullptr ; } ; if ( VPTState :: isEntryPredicatedOnVCTP ( Block , true ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( VPTState :: hasUniformPredicate ( Block ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; for ( unsigned i = <NUM_LIT> ; i < Insts . size ( ) ; ++ i ) RemovePredicate ( Insts [ i ] ) ; } else { MachineInstr * Divergent = VPTState :: getDivergent ( Block ) ; MachineBasicBlock * MBB = Divergent -> getParent ( ) ; auto DivergentNext = ++ MachineBasicBlock :: iterator ( Divergent ) ; while ( DivergentNext != MBB -> end ( ) && DivergentNext -> isDebugInstr ( ) ) ++ DivergentNext ; bool DivergentNextIsPredicated = DivergentNext != MBB -> end ( ) && getVPTInstrPredicate ( * DivergentNext ) != <STR_LIT> ; for ( auto I = ++ MachineBasicBlock :: iterator ( VPST ) , E = DivergentNext ; I != E ; ++ I ) RemovePredicate ( & * I ) ; MachineInstr * VCMP = VCMPOpcodeToVPT ( Divergent -> getOpcode ( ) ) != <NUM_LIT> ? Divergent : nullptr ; if ( DivergentNextIsPredicated ) { if ( ! VCMP ) { MachineInstrBuilder MIB = BuildMI ( * Divergent -> getParent ( ) , Divergent , Divergent -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts


<s> } if ( auto * StoreN = dyn_cast < StoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStridedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedScatterSDNode > ( Op . getNode ( ) ) )


<s> return ( __m128i ) __builtin_ia32_cvttps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_di ( )


<s> return ( __m128i ) __builtin_ia32_vpcomfalseuq ( ( __v2di ) __A , ( __v2di )


<s> int NumFound = <NUM_LIT> ; unsigned MemOp = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; ) { if ( isMem ( & MI


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetDarwin ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl


<s> Mask &= ~ KnownOne . getZExtValue ( ) ; if ( ! refineRxSBGMask ( RxSBG , Mask ) ) return false ; } RxSBG . Input = Input ; return true ; } case <STR_LIT> : { if ( RxSBG . BitSize != <NUM_LIT> || N . getValueType ( ) != <STR_LIT> ) return false ; auto * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; RxSBG . Rotate = ( RxSBG . Rotate + CountNode -> getZExtValue ( ) ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : if ( RxSBG . Opcode != <STR_LIT> ) { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; if ( ! refineRxSBGMask ( RxSBG , allOnes ( InnerBitSize ) ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; if ( maskMatters ( RxSBG , allOnes ( RxSBG . BitSize ) - allOnes ( InnerBitSize ) ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) )


<s> auto IsZeroInit = [ ] ( MachineInstr * Def ) { return ! isVectorPredicated ( Def ) && Def -> getOpcode ( ) == <STR_LIT> && Def -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } ; bool AllowScalars = isHorizontalReduction ( MI ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( ! isRegInClass ( MO , QPRs ) && AllowScalars ) continue ; int PIdx = llvm ::


<s> switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( <STR_LIT> ( Op ) ) return MCTargetAsmParser ::


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo (


<s> <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = condCodeToString ( CC


<s> return new <ISA_LIT>ModuleDAGToDAGISel ( TM


<s> bool hasFPCVT ( ) const { return HasFPCVT


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue SelectOp , Phi ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op0 ; Phi = Op1 ; } else if ( Op1 . getOpcode ( ) ==


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> else if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O ,


<s> static bool isInSmallSection ( uint64_t Size


<s> } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Stubs [ i ] . second . getPointer ( ) ,


<s> unsigned getPointerSize ( ) const { StringRef Name = TheTarget . getName (


<s> SDLoc dl ( Op ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } bool AllContants = true ; uint64_t Immediate = <NUM_LIT> ; int NonConstIdx = - <NUM_LIT> ; bool IsSplat = true ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands


<s> SDValue <ISA_LIT>TargetLowering :: LowerFCOPYSIGN ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op1 . getValueType ( ) ; if ( SrcVT . bitsLT ( VT ) ) { Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 ) ; SrcVT = VT ; } if ( SrcVT . bitsGT ( VT ) ) { Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SrcVT = VT ; } SmallVector < Constant * , <NUM_LIT> > CV ; if ( SrcVT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl


<s> unsigned CRm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 )


<s> if ( ! TARGET_RELAX_PIC_CALLS || args_size_opno == - <NUM_LIT> ) return false ; args_size = operands [ args_size_opno ] ; if ( GET_CODE ( args_size ) != UNSPEC ) return false ; gcc_assert ( XINT ( args_size , <NUM_LIT> ) == UNSPEC_CALL_ATTR ) ; symbol = XVECEXP ( args_size , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( symbol ) ==


<s> int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) )


<s> bool <ISA_LIT>ConstantIslands :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MCP = mf . getConstantPool ( ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( mf ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MCP -> getConstants ( ) . size ( ) << <STR_LIT> << MCP -> getConstantPoolAlign ( ) . value ( ) << <STR_LIT> ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; isPositionIndependentOrROPI = STI -> getTargetLowering ( ) -> isPositionIndependent ( ) || STI -> isROPI ( ) ; AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; if ( STI -> hardenSlsRetBr ( ) ) GenerateTBB = false ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries


<s> raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; const SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( And . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftOpc = Shift . getOpcode ( ) ; if ( ( ShiftOpc != <STR_LIT> && ShiftOpc != <STR_LIT> ) ) return SDValue ( ) ; bool IsShiftRight = ShiftOpc == <STR_LIT> ; ConstantSDNode * C2node = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ; if ( ! C2node ) return SDValue ( ) ; uint64_t C1 ; if ( ! isAllConstantBuildVector ( And . getOperand ( <NUM_LIT> ) , C1 ) ) return SDValue ( ) ; uint64_t C2 = C2node -> getZExtValue ( ) ; unsigned ElemSizeInBits = VT . getScalarSizeInBits ( ) ; if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , DL , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( & DAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ResultSLI -> dump ( & DAG )


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq


<s> uint32_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Val <= <NUM_LIT> && <STR_LIT>


<s> Target & llvm :: getThe<ISA_LIT>elTarget ( ) { static Target The<ISA_LIT>elTarget ; return The<ISA_LIT>elTarget


<s> } if ( ! TT . isOSDarwin ( ) && ! JIT && ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ) return CodeModel :: Medium ; return CodeModel :: Small


<s> if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_UPPER_REGS_DF ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_UPPER_REGS_SF ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( bu_mask & RS6000_BTM_SPE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( bu_mask & RS6000_BTM_PAIRED ) != <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width =


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; unsigned Op0Opcode = Op0 -> getOpcode ( ) ; if ( Op0Opcode == <STR_LIT> || Op0Opcode == <STR_LIT> ) { ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ! Mask ) return SDValue ( ) ; int32_t Log2IfPositive = ( Mask -> getAPIntValue ( ) + <NUM_LIT> ) . exactLogBase2 ( ) ; if ( Log2IfPositive <= <NUM_LIT> ) return SDValue ( ) ; SDValue Op0Op2 = Op0 -> getOperand ( <NUM_LIT> ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op2 ) -> getVT ( ) ; unsigned ExtendTySize = ExtendTy . getSizeInBits ( ) ; unsigned Log2 = Log2IfPositive ; if ( ( Op0Opcode == <STR_LIT> && Log2 >= ExtendTySize ) || Log2 == ExtendTySize ) { SDValue Ops [ ] = { Op0 -> getOperand ( <NUM_LIT> ) , Op0 -> getOperand


<s> EVT VT1 = Op1 . getValueType ( ) ; unsigned EltBitWidth = VT0 . getScalarSizeInBits ( ) ; if ( VT0 != VT1 || EltBitWidth == <NUM_LIT> ) return SDValue ( ) ; assert ( VT0 . getSizeInBits ( ) == <NUM_LIT> || VT0 . getSizeInBits ( ) == <NUM_LIT> ) ; APInt SplatVal ; if ( ! <STR_LIT> ( Op1 . getNode ( ) , SplatVal ) || SplatVal != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue ShAmt = DAG . getConstant ( EltBitWidth - <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT0 ,


<s> return getSubtargetImpl ( ) -> getSelectionDAGInfo


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI ,


<s> if ( OldMI -> registerDefIsDead ( <STR_LIT> ) ) { MachineOperand * CCDef = NewMI -> findRegisterDefOperand (


<s> return ( vec_sel ( __A , c , mask ) ) ; __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] / __B [ <NUM_LIT> ] ; return ( __A


<s> switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_UNALIGNED_LOAD : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . load + extra_cost -> ldst . load_unaligned ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true ; case UNSPEC_UNALIGNED_STORE : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . store + extra_cost -> ldst . store_unaligned ) ; * cost += rtx_cost ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , VOIDmode , UNSPEC , <NUM_LIT> , speed_p ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true


__artificial__ ) ) __TM_failure_address ( void * const TM_buff ) {


<s> void printS16ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { O << ( int16_t ) MI -> getOperand (


<s> static DecodeStatus DecodeExpandedImmOperand ( MCInst & Inst , unsigned Val

, uint64_t Address , const void * Decoder ) {


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return


<s> if ( InsertedThunks ) return false ; if ( ! STI -> useRetpoline ( ) || STI -> useRetpolineExternalThunk ( ) ) return false ; if ( Is64Bit ) createThunkFunction ( M , R11ThunkName ) ; else for ( StringRef Name : { EAXThunkName , ECXThunkName , EDXThunkName , EDIThunkName } ) createThunkFunction ( M , Name ) ; InsertedThunks = true ; return true ; } if ( Is64Bit ) { assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; populateThunk ( MF ,


<s> static std :: string computeDataLayout ( const Triple & TT ) { return <STR_LIT> <STR_LIT> <STR_LIT>


<s> Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo ,


<s> if ( function_label_operand ( x , VOIDmode ) ) { tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl || ( DECL_P ( decl ) && DECL_COMDAT_GROUP ( decl ) ) ) return get_named_section (


<s> static void report_not_one_of ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return false


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI ,


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy =


<s> static MachineOperand & getLdStRegOp ( MachineInstr & MI , unsigned PairedRegOp = <NUM_LIT> ) { assert ( PairedRegOp < <NUM_LIT> && <STR_LIT> ) ; bool IsPreLdSt = <ISA_LIT>InstrInfo :: isPreLdSt (


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> && ! zeroPermitted ) S = MCDisassembler :: Fail ; uint64_t DecVal ; if ( isSigned ) DecVal = SignExtend32 < size + <NUM_LIT> > ( Val << <NUM_LIT> ) ; else DecVal = ( Val << <NUM_LIT>


<s> if ( len == <NUM_LIT> ) { error ( <STR_LIT> , str ) ; return ; } for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , str , len ) == <NUM_LIT> ) { selected_cpu = cpu ; aarch64_isa_flags = selected_cpu -> flags ; if ( ext != NULL ) { aarch64_parse_extension ( ext )


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorIndex , Ctx ) ; Op -> VectorIndex . Val = Idx ; Op -> StartLoc =


<s> bool SelectAddrMode2Base ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return SelectAddrMode2Worker ( N , Base , Offset , Opc )


<s> unsigned getReg231Opcode ( ) const { assert ( RegOpcodes && <STR_LIT> ) ; return RegOpcodes [


<s> <ISA_LIT>Relocator :: Result none ( Relocation & pReloc


<s> static __inline int __attribute__ ( ( __always_inline__ ) ) _mm_ucomineq_ss (


<s> const SmallVectorImpl < unsigned > & getMustSaveCRs ( ) const { return MustSaveCRs


<s> bool isMemOffs64_32 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem


<s> } if ( regno <= <NUM_LIT> ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return <NUM_LIT> ; if ( regno == FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( regno == ARG_POINTER_REGNUM ) return <NUM_LIT> ; if ( regno == <NUM_LIT> ) return


<s> if ( TARGET_ARM_P ( flags ) && TARGET_CALLEE_INTERWORKING ) warning ( <NUM_LIT> , <STR_LIT> ) ; if ( TARGET_ARM_P ( flags ) && write_symbols != NO_DEBUG && ! TARGET_APCS_FRAME && ( TARGET_DEFAULT & MASK_APCS_FRAME ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; if ( TARGET_THUMB_P ( flags ) && TARGET_IWMMXT ) error ( <STR_LIT> ) ; if ( TARGET_HARD_TP && TARGET_THUMB1_P ( flags ) ) error ( <STR_LIT> ) ; if ( TARGET_THUMB_P ( flags ) && TARGET_VXWORKS_RTP && flag_pic ) { error ( <STR_LIT> ) ; flag_pic = <NUM_LIT> ; } if ( ( target_pure_code || target_slow_flash_data ) && ( ! TARGET_HAVE_MOVT || arm_arch_notm


<s> if ( isTargetCOFF ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT> ; } return <STR_LIT>


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( REAL_VALUES_EQUAL ( * r , value_fp0


<s> void <ISA_LIT>CodeEmitter :: emitGlobalAddress ( const GlobalValue * GV , unsigned Reloc , bool MayNeedFarStub , bool Indirect , intptr_t ACPV ) { MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > ( GV ) , ACPV , MayNeedFarStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > (


<s> void <ISA_LIT>AsmPrinter :: printCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O


<s> return ( __m512i ) __builtin_ia32_pternlogd512_mask ( ( __v16si ) __A , ( __v16si ) __B , ( __v16si ) __C , ( unsigned char ) __imm , (


<s> return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL (

shft_amnt ) ) + <NUM_LIT> ) >= <NUM_LIT> && ( INTVAL ( mask ) & ( ( <NUM_LIT> << INTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> for ( auto & I : AllocasToInstrument ) { const memtag :: AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( ! PrologueBB ) { PrologueBB = AI -> getParent ( ) ; continue ; } PrologueBB = DT -> findNearestCommonDominator ( PrologueBB , AI -> getParent ( ) ) ; } assert ( PrologueBB


<s> const Function & Fn = MF . getFunction ( ) ; const bool IsWin64CC = STI . isCallingConvWin64 ( Fn . getCallingConv ( ) ) ; return Is64Bit && ! IsWin64CC && ! Fn . hasFnAttribute ( Attribute :: NoRedZone


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { bool is64 = getPointerSize ( ) == <NUM_LIT> ; return create<ISA_LIT>ELFObjectWriter ( OS , is64 ,


<s> unsigned new_regno = find_rename_reg ( head , super_class , & unavailable , dest_regno , false ) ; if ( new_regno != dest_regno && regrename_do_replace ( head , new_regno ) ) { if ( dump_file && ( dump_flags & TDF_DETAILS ) ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn_info -> insn ) , dest_regno , new_regno ) ; return


<s> assert ( ( Value == <NUM_LIT> || Value == <NUM_LIT> ) && <STR_LIT> ) ; return Value


<s> return __builtin_mve_vmovlbq_m_uv8hi ( __arm_vuninitializedq_u32 ( ) ,


<s> fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; write_bif_static_init ( ) ; write_ovld_static_init ( ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; rbt_inorder_callback ( & fntype_rbt , fntype_rbt . rbt_root , write_fntype_init ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; write_init_bif_table ( ) ; write_init_ovld_table ( ) ; fprintf ( init_file ,


<s> return ( __m256i ) __builtin_ia32_pternlogd256_maskz ( ( __v8si ) __A , ( __v8si ) __B , (


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE (

vfp_builtin_data ) ; i ++ , fcode ++ ) {


<s> static alias_set_type set = - <NUM_LIT> ; if ( set == - <NUM_LIT> ) set = new_alias_set