<s> if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; if ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ]


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode


<s> case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; case ENCODING_RM : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_SI


<s> } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedCmpVal ) . addReg ( CmpVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedCmpVal ) . addReg ( MaskedCmpVal ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedNewVal ) . addReg ( NewVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedNewVal ) . addReg ( MaskedNewVal ) . addReg ( ShiftAmt ) ; BB = loop1MBB ; unsigned LL = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedOldVal0 ) . addReg ( OldVal ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MaskedOldVal0 ) . addReg ( ShiftedCmpVal ) . addMBB ( sinkMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedOldVal1 ) . addReg ( OldVal ) . addReg ( Mask2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ,

StoreVal ) . addReg ( MaskedOldVal1 ) . addReg ( ShiftedNewVal ) ;


<s> virtual const Dcpu16RegisterInfo * getRegisterInfo (


<s> const MCSymbol * Symbol = CLI . Symbol ; if ( ! Callee && ! Symbol ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; Type * RetTy = CLI . RetTy ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; else if ( RetVT == <STR_LIT> && <ISA_LIT>SubTarget -> useCRBits ( ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , IsVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT>64_ELF_FIS ) ; if ( RVLocs . size ( ) > <NUM_LIT> ) return false ; } unsigned NumArgs = CLI . OutVals . size ( ) ; if ( NumArgs > <NUM_LIT> ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( NumArgs ) ; ArgRegs . reserve ( NumArgs ) ; ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs


<s> printThumbAddrModeRI5Operand ( MI , Op , O , <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>IndirectThunks ( ) { return new <ISA_LIT>IndirectThunks


<s> MachineBasicBlock :: iterator I = MI , BeforeI = I ; bool AtStart = I == MBB . begin ( ) ; if ( ! AtStart ) -- BeforeI ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> ) continue ; if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; } return true


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl


<s> const MCExpr * <ISA_LIT>64_MachoTargetObjectFile :: getExprForDwarfGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { SmallString < <NUM_LIT> > Name ; Mang -> getNameWithPrefix ( Name , GV , false ) ; const MCSymbol * Sym ; if ( GV -> hasPrivateLinkage ( ) ) Sym = getContext ( ) . GetOrCreateTemporarySymbol


<s> Value * <ISA_LIT>IREmitter :: visitCMOV (


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true


<s> return ( __m128 ) __builtin_ia32_cmpgess ( ( __v4sf ) __A , ( __v4sf )


<s> SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = <NUM_LIT> ; return


<s> case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) UpdateOffset


<s> } if ( Options . isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setNomacro ( ) ; Parser . Lex


<s> return ( __m512 ) __builtin_ia32_rcp28ps_mask ( ( __v16sf ) __A , ( __v16sf ) _mm512_setzero_ps ( ) , (


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT>


<s> NaCl<ISA_LIT>_32AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>_32AsmBackend ( T , OSABI , CPU ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo


<s> } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] )

- <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ;


<s> for ( MachineBasicBlock & MBB : MF ) { const unsigned Mask = calcLiveInMask ( & MBB ) ; if ( ! Mask )


<s> StringRef Identifier = Tok . getString ( ) ; if ( <ISA_LIT>Operand * Err = ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return Err ; unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Length ; break ; case IOK_SIZE : CVal = Info . Size ; break ; case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer


<s> if ( VTy -> getBitWidth ( ) == <NUM_LIT> ) MaxAlign = <NUM_LIT> ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign ) ; if ( EltAlign > MaxAlign )


<s> if ( ExtIntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) < IntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue LHS = DAG . getAnyExtOrTrunc ( DAG . getBitcast ( IntTy , N -> getOperand ( <NUM_LIT> ) ) , DL , ExtIntTy ) ; SDValue RHS = DAG . getAnyExtOrTrunc ( DAG . getBitcast ( IntTy , N -> getOperand ( <NUM_LIT> ) ) , DL , ExtIntTy ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Splice = DAG . getNode ( <STR_LIT> , DL ,


<s> static rtx aarch64_move_pointer ( rtx pointer , poly_int64 amount ) { rtx next = plus_constant ( Pmode , XEXP ( pointer


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = tryParseRegister ( <STR_LIT> ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ; return ( RegNo == ( unsigned )


<s> RC = & <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto Neg = MIB . buildInstr ( NegOpc , { RC } , { Src2Reg } ) ; constrainSelectedInstRegOperands ( * Neg , TII , TRI , RBI ) ; auto SShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Neg } ) ; constrainSelectedInstRegOperands ( * SShl , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI .


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = tryParseRegister ( is<ISA_LIT>64 ( ) ) ; EndLoc = Parser . getTok ( ) . getLoc


<s> int16_t imm = <NUM_LIT> ; if ( N . getOpcode ( ) == <STR_LIT> && ( ! isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) || ! N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , N


<s> if ( ! isImm ( ) ) return false ; if ( isa < MCSymbolRefExpr > ( Imm . Val ) ) return true ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Align = <NUM_LIT>


<s> if ( ! RM . hasValue ( ) ) return TT . isOSBinFormatMachO ( ) ? Reloc :: PIC_ : Reloc :: Static ; if ( * RM == Reloc :: ROPI || * RM == Reloc :: RWPI || * RM == Reloc :: ROPI_RWPI ) assert ( TT . isOSBinFormatELF ( ) && <STR_LIT> ) ; if ( * RM == Reloc :: PIP ) assert ( TT . isOSBinFormatELF ( )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; } ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; TOut . emitRRR ( <STR_LIT> , ATReg , <STR_LIT> , TReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( FirstShift , ATReg , SReg , ATReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( SecondShift , DReg , SReg , TReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( <STR_LIT> , DReg , DReg , ATReg , Inst . getLoc ( ) , STI ) ; return false ; } return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . hasOneUse ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { auto * SraAmt = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Inner = N0 . getOperand ( <NUM_LIT> ) ; if ( SraAmt && Inner . hasOneUse ( ) && Inner . getOpcode ( ) == <STR_LIT> ) { if ( auto * ShlAmt = dyn_cast < ConstantSDNode > ( Inner . getOperand ( <NUM_LIT> ) ) ) { unsigned Extra = ( VT . getSizeInBits ( ) - N0 . getValueType ( )


<s> const MCOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } else


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( )


<s> if ( Op0 . getOpcode ( ) != <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT0 = Op0 . getValueType ( ) ; EVT VT1 = Op1 . getValueType ( ) ; unsigned EltBitWidth = VT0 . getScalarType ( ) . getSizeInBits ( ) ; if ( VT0 != VT1 || EltBitWidth == <NUM_LIT> ) return SDValue ( ) ; assert ( VT0 . getSizeInBits ( ) == <NUM_LIT> || VT0 .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = <NUM_LIT> ; par_index < count ; par_index ++ ) { offset = par_index * <NUM_LIT> ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET ( reg , mem ) ; } return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> MCCodeEmitter * llvm :: create<ISA_LIT>LEMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext &


<s> return getTM < <ISA_LIT>TargetMachine >


<s> } if ( LeadingZero ) { if ( ! UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) ) return DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( ! UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) ) return DAG . getTargetConstant ( ~ <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . isUndef ( ) ) continue ; if ( ! OpVal . getNode ( ) ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( ! OpVal . getNode ( ) ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; if ( ! APInt ( ValSizeInBytes * <NUM_LIT> , Value ) . isSplat ( ByteSize * <NUM_LIT> ) ) return SDValue ( ) ; int MaskVal = SignExtend32 ( Value , ByteSize * <NUM_LIT> ) ; if ( MaskVal == <NUM_LIT> ) return SDValue ( ) ; if ( SignExtend32 < <NUM_LIT> > ( MaskVal ) == MaskVal ) return DAG . getTargetConstant ( MaskVal , SDLoc ( N ) , <STR_LIT> ) ; return SDValue (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> SDLoc DL ( JT ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( OpFlag ) Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ; return


<s> return ( __m512i ) __builtin_ia32_cvtps2qq512_mask ( ( __v8sf ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , (


<s> inline static void aarch64_print_hint_for_arch ( const


<s> if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT . SimpleTy == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ;


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return


<s> machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Expression ) ; Op -> Expr . Val = Val ; Op -> StartLoc


<s> LLVM_DUMP_METHOD void <ISA_LIT>ConstantIslands :: dumpBBs ( ) { for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) <<

format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Module & M , const std :: string & FS , bool isThumb ) : Subtarget ( M , FS , isThumb ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? ( isThumb ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> ) ) : ( isThumb ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> ) ) ) , InstrInfo ( Subtarget ) , FrameInfo ( Subtarget ) , JITInfo ( )


<s> if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) loongarch_prepare_builtin_arg ( & ops [ opno ++ ] ,


<s> SDValue Tmp = b . OR ( b . AND ( b . SHL < <NUM_LIT> > ( A1 ) , Tmp1 ) , b . AND ( A1 , b . NOT ( Tmp1 ) ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , Tmp , b .


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT>


<s> if ( InVT . isScalableVector ( ) ) { if ( ! isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) { unsigned NumElts = VT . getVectorMinNumElements ( ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , Vec0 , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , Vec0 , DAG . getVectorIdxConstant ( NumElts / <NUM_LIT> , DL ) ) ; if ( Idx < ( NumElts / <NUM_LIT> ) ) { SDValue NewLo = DAG . getNode ( <STR_LIT> , DL , HalfVT , Lo , Vec1 , DAG . getVectorIdxConstant ( Idx , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewLo , Hi ) ; } else { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , HalfVT , Hi , Vec1 , DAG . getVectorIdxConstant ( Idx - ( NumElts / <NUM_LIT> ) , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , NewHi ) ; } } if ( VT . getVectorElementCount ( ) != ( InVT . getVectorElementCount ( ) * <NUM_LIT> ) ) return SDValue ( ) ; EVT WideVT ; SDValue ExtVec ; if ( VT . isFloatingPoint ( ) ) { WideVT = VT ; ExtVec = getSVESafeBitCast ( VT , Vec1 , DAG ) ; } else { WideVT = InVT . widenIntegerVectorElementType ( * ( DAG . getContext ( ) ) ) ; ExtVec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec1 ) ; } if ( Idx == <NUM_LIT> ) { SDValue HiVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ExtVec , HiVec0 ) ; } else if ( Idx == InVT . getVectorMinNumElements ( ) ) { SDValue LoVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoVec0 , ExtVec ) ; } return SDValue ( ) ; } if ( Idx == <NUM_LIT> && isPackedVectorType ( VT , DAG ) ) { if ( Vec0 . isUndef ( ) ) return Op ; Optional < unsigned > PredPattern = getSVEPredPatternFromNumElements ( InVT . getVectorNumElements


<s> switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; } SDLoc dl ( N ) ; return DAG . getNode ( VShiftOpc , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } case <STR_LIT> : { EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; int64_t Cnt ; unsigned VShiftOpc = <NUM_LIT> ; if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) VShiftOpc = <STR_LIT> ; else if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) VShiftOpc = <STR_LIT> ; else { llvm_unreachable ( <STR_LIT> ) ; } SDLoc dl ( N ) ; return DAG . getNode ( VShiftOpc , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } case


<s> MI -> getOperand ( PIdx ) . setImm ( <STR_LIT> ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; } ; for ( auto & Block : LoLoop . getVPTBlocks ( ) ) { SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; if ( Block . HasNonUniformPredicate ( ) ) { PredicatedMI * Divergent = Block . getDivergent ( ) ; if ( isVCTP ( Divergent -> MI ) ) { LoLoop . BlockMasksToRecompute . insert ( Block . getPredicateThen ( ) ) ; } else if ( Block . isVPST ( ) && Block . IsOnlyPredicatedOn ( LoLoop . VCTP ) ) { for ( auto I = ++ MachineBasicBlock :: iterator ( Block . getPredicateThen ( ) ) , E = ++ MachineBasicBlock :: iterator ( Divergent -> MI ) ; I != E ; ++ I ) RemovePredicate ( & * I ) ; MachineInstr * VCMP = VCMPOpcodeToVPT ( Divergent -> MI -> getOpcode ( ) ) != <NUM_LIT> ? Divergent -> MI : nullptr ; unsigned Size = <NUM_LIT> ; auto E = MachineBasicBlock :: reverse_iterator ( Divergent -> MI ) ; auto I = MachineBasicBlock :: reverse_iterator ( Insts . back ( ) . MI ) ; MachineInstr * InsertAt = nullptr ; while ( I != E ) { InsertAt = & * I ; ++ Size ; ++ I ; } MachineInstrBuilder MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Block . getPredicateThen ( ) ) ; if ( VCMP ) { MIB = BuildMI ( * InsertAt -> getParent ( ) , InsertAt , InsertAt -> getDebugLoc ( ) , TII -> get ( VCMPOpcodeToVPT ( VCMP -> getOpcode ( ) ) ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( VCMP ) ; } else { MIB = BuildMI ( * InsertAt -> getParent ( ) , InsertAt , InsertAt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; } LoLoop . ToRemove . insert ( Block . getPredicateThen ( ) ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else if ( Block . isVPT ( ) ) { bool RemovedVCTP = false ; for ( PredicatedMI & Elt : Block . getInsts ( ) ) { MachineInstr * MI = Elt . MI ; if ( isVCTP ( MI )


<s> SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> ,


<s> unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT> << Count ; unsigned MaskOff = ~ ( MaskOn - <NUM_LIT> ) ; MBBI -> getOperand ( <NUM_LIT> ) . setImm (


<s> SDLoc dl ( Op ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue SafeShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , SafeShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1


<s> if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } return false


<s> return ( __m256i ) __builtin_ia32_psrawi256 ( ( __v16hi


<s> SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops


<s> case FK_Data_4 : Type = ELF :: R_MIPS_32 ; break ; case FK_Data_8 : Type = ELF :: R_MIPS_64 ; break ; case FK_GPRel_4 : if ( isN64 ( ) ) { Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; } else Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case


<s> ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; return ret


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ; } else


<s> if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; SrcReg = ANDReg ; } const MCInstrDesc & II = TII . get ( Opc ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg ) ; addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOStore , ScaleFactor ,


<s> case <ISA_LIT>Subtarget :: isELF : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_ELFTargetObjectFile ( TM ) ; return new <ISA_LIT>32_ELFTargetObjectFile ( TM ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin : case <ISA_LIT>Subtarget


<s> rs6000_call_darwin_1 ( value , func_desc ,


<s> assert ( ( Idx + Len ) <= NumElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ShuffleMask . push_back ( i ) ; for ( unsigned i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask [


<s> if ( mode . base_vector_type == base_vector_type && mode . displacement_vector_type == displacement_vector_type && mode .


<s> <ISA_LIT>ArchVersion = <ISA_LIT>1 ; ParseSubtargetFeatures ( FS , CPU ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( <STR_LIT> ) != std :: string :: npos || TT . find ( <STR_LIT> ) != std :: string :: npos ) { <ISA_LIT>ABI = EABI ; IsSingleFloat = true ; <ISA_LIT>ArchVersion = <ISA_LIT>2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap =


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( )


<s> unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> )


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA . getValVT ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; MRI . addLiveOut ( VA . getLocReg ( ) ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return


<s> ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = <NUM_LIT> ; ri_gp_value = <NUM_LIT> ; const MCRegisterInfo * TRI = Context . getRegisterInfo ( ) ; GPR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR32RegClass = & ( TRI -> getRegClass


<s> if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; auto & RegClass = Is64Bit ? <STR_LIT> : <STR_LIT> ; for ( auto Candidate : RegClass ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Candidate ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] = Candidate ; if ( FoundRegs == ( unsigned ) NumPops ) break ; } if ( FoundRegs == <NUM_LIT> ) return false ; while ( FoundRegs < ( unsigned ) NumPops ) Regs [


<s> return CurDAG -> getRegister ( <ISA_LIT>16SPAliasReg , TLI .


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> is<ISA_LIT>32 ( ) && SelectMadd ( N , & DAG ) ) return SDValue ( N


<s> rtx scratch2 = scratch ? scratch : gen_reg_rtx ( SImode ) ; y_hi = gen_int_mode ( - INTVAL ( y_hi ) , SImode ) ; if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; emit_insn ( gen_addsi3 ( scratch2 , x_hi , y_hi ) ) ; x_hi = scratch2 ; } if ( ! scratch ) { gcc_assert ( ! reload_completed ) ; scratch = gen_rtx_SCRATCH ( SImode ) ; } rtx clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; cc_reg = gen_rtx_REG ( CC_NZmode , CC_REGNUM ) ; rtx set = gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( CC_NZmode , gen_rtx_IOR ( SImode , x_lo , x_hi ) , const0_rtx ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; return cc_reg ; } if ( ! arm_add_operand ( y_lo , SImode ) ) y_lo = force_reg ( SImode , y_lo ) ; if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; rtx cmp1 = gen_rtx_NE ( SImode , x_lo , y_lo ) ; rtx cmp2 = gen_rtx_NE ( SImode , x_hi , y_hi ) ; rtx conjunction = gen_rtx_IOR ( SImode , cmp1 , cmp2 ) ; mode = SELECT_CC_MODE ( code , conjunction , const0_rtx ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , conjunction , const0_rtx ) ) ) ; return cc_reg ; } case LT : case GE : { if ( y_lo == const0_rtx ) { if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; return arm_gen_compare_reg ( code , x_hi , y_hi , NULL_RTX ) ; } if ( ! arm_add_operand ( y_lo , SImode ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , x_lo , y_lo , NULL_RTX ) , const0_rtx ) ; if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; if ( ! arm_not_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; rtx_insn * insn ; if ( y_hi == const0_rtx ) insn = emit_insn ( gen_cmpsi3_0_carryin_CC_NVout ( scratch , x_hi , cmp1 ) ) ; else if ( CONST_INT_P ( y_hi ) ) insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; else insn = emit_insn ( gen_cmpsi3_carryin_CC_NVout ( scratch , x_hi


Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ;


<s> static void rx_trampoline_init ( rtx tramp , tree fndecl , rtx chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_block_move ( tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; if ( TARGET_BIG_ENDIAN_DATA ) { emit_move_insn ( adjust_address ( tramp , SImode , <NUM_LIT> ) , chain ) ; emit_move_insn ( adjust_address ( tramp , SImode , <NUM_LIT> )


<s> StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return


<s> return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RegNo - <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; default : assert ( ( int ( RegNo ) > <NUM_LIT> ) && <STR_LIT>


<s> auto * OpPredicate = II . getOperand ( <NUM_LIT> ) ; auto BinOpCode = intrinsicIDToBinOpCode ( II . getIntrinsicID ( ) ) ; if ( BinOpCode == Instruction :: BinaryOpsEnd || ! match ( OpPredicate , m_Intrinsic < <STR_LIT> > ( m_ConstantInt < <STR_LIT> > ( ) ) ) ) return None ; IRBuilder < > Builder ( II


<s> static DecodeStatus DecodeDPR_8RegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t


<s> if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ <NUM_LIT> ] ) == DImode && ( ! body || !

dep_between_memop_and_curr ( body ) ) ) return true ;


<s> const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI ->


<s> ReverseIter FirstBr = getNonDebugInstr ( std :: next ( LastBr ) , End ) ; if ( ( FirstBr == End ) || ( ! FirstBr -> isConditionalBranch ( ) && ! FirstBr -> isUnconditionalBranch ( ) ) ) return ; assert ( ! FirstBr -> isIndirectBranch ( ) && <STR_LIT> ) ; for ( ; it != MBB -> end ( ) ; ++ it ) { if ( & * it == & * FirstBr


<s> return ( __m256d ) __builtin_ia32_loadapd256_mask ( ( __v4df * ) __P , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 )


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand & MO2 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; ShapeT Shape ( & MO1 , & MO2 , MRI ) ; return


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . useSoftFloat ( ) && STI . hasVFP2 ( ) && ! STI . isThumb1Only ( ) ) return CSR_NoRegs_RegMask ; else return


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> )


<s> unsigned int flags = d -> flags ; if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( d -> mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math )


<s> case ROTATERT : return ( mode == SImode ) ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : case MINUS : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int const_size = thumb1_size_rtx_costs ( XEXP ( x , <NUM_LIT> ) , CONST_INT , SET ) ; if ( arm_arch6m && arm_m_profile_small_mul ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) + const_size ; } return COSTS_N_INSNS ( <NUM_LIT> ) ; case SET : words = ARM_NUM_INTS ( GET_MODE_SIZE ( GET_MODE ( SET_DEST ( x ) ) ) ) ; return COSTS_N_INSNS ( words ) + COSTS_N_INSNS ( <NUM_LIT> ) * ( satisfies_constraint_J ( SET_SRC ( x ) ) || satisfies_constraint_K ( SET_SRC ( x ) ) || ( ( words > <NUM_LIT> ) && MEM_P ( SET_SRC ( x ) ) ) ) ; case CONST_INT : if ( outer == SET ) { if ( ( unsigned HOST_WIDE_INT ) INTVAL ( x ) < <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) <= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) > - <NUM_LIT> ) return <NUM_LIT> ; else if ( ( outer == IOR || outer == XOR || outer == AND ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( outer == AND ) { int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == INTVAL ( x ) || ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ; case TRUNCATE


<s> static DecodeStatus decodeU8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const


<s> void <ISA_LIT>TargetAsmStreamer :: emit<ISA_LIT>WinCFIAllocStack ( unsigned Size , bool


<s> void <ISA_LIT>16InstrInfo :: adjustStackPtrBigUnrestricted ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB

, MachineBasicBlock :: iterator I ) const {


<s> static const SpillSlot FixedSpillOffsets [ ] = { { <STR_LIT> , -


<s> Parser . Lex ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount <


<s> BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = <NUM_LIT> ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond


<s> static SDValue combineVectorHADDSUB ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; if ( SDValue V = combineHorizOpWithShuffle ( N , DAG , Subtarget ) ) return V ; return SDValue ( )


<s> } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = ( * LHSBits ) [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return std :: make_pair ( Interesting , & Bits ) ; } break ; case <STR_LIT> : { const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; const auto & RHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; bool AllDisjoint = true ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( ! AllDisjoint ) break ; return std :: make_pair ( Interesting = true , & Bits ) ; } case <STR_LIT> : { if ( V . getValueType ( ) != <STR_LIT> || V . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) break ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; const unsigned NumOperandBits = <NUM_LIT> ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumOperandBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperandBits ; ++ i ) Bits [ i ] = ( * LHSBits ) [ i ] ; for ( unsigned i = NumOperandBits ; i < NumBits ; ++ i ) Bits [ i ] = ValueBit ( ValueBit


<s> if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode )

) && ( nelems >= <NUM_LIT> && nelems <= <NUM_LIT> ) ) return true ;


<s> Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc =


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( Subtarget . enableLongBranchPass ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) || Subtarget . allowMixed16_32 ( )

) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ;


<s> case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == <NUM_LIT> ) { assert ( ( ImmVal >= - <NUM_LIT> ) && ( ImmVal <= <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( ImmVal >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : case


<s> return <ISA_LIT>ProcFamily == IntelGLM || <ISA_LIT>ProcFamily == IntelGLP ||


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand ::


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { return


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment =


<s> MVT WideVT = Ext -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT SelVT = Sel . getSimpleValueType ( ) ; assert ( ( SelVT . is256BitVector ( ) || SelVT . is512BitVector ( ) ) && <STR_LIT> ) ; unsigned SelElts = SelVT . getVectorNumElements ( ) ; unsigned CastedElts = WideVT . getVectorNumElements ( ) ; unsigned ExtIdx = Ext -> getConstantOperandVal ( <NUM_LIT> ) ; if ( SelElts % CastedElts == <NUM_LIT> ) { ExtIdx *= ( SelElts / CastedElts ) ; } else if ( CastedElts % SelElts == <NUM_LIT> ) { unsigned IndexDivisor = CastedElts / SelElts ; if ( ExtIdx % IndexDivisor != <NUM_LIT> ) return SDValue ( ) ; ExtIdx /= IndexDivisor ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NarrowingFactor = WideVT . getSizeInBits ( ) / VT . getSizeInBits ( ) ; unsigned NarrowElts = SelElts / NarrowingFactor ; MVT NarrowSelVT = <STR_LIT> ( SelVT . getVectorElementType ( ) , NarrowElts ) ; SDLoc DL ( Ext ) ; SDValue ExtCond = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtT = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtF = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue NarrowSel = DAG . getSelect ( DL , NarrowSelVT , ExtCond , ExtT , ExtF ) ; return DAG . getBitcast (


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O << 'f' ; if ( Mask & <NUM_LIT>


<s> d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type (

d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ;


<s> GlobalValue * getGV ( ) const { return GV


<s> return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT>

) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( out_words_to_go != in_words_to_go && ( ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) part_bytes_reg = gen_rtx_REG ( SImode , ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) ; for ( i = <NUM_LIT> ; in_words_to_go >= <NUM_LIT> ; i += <NUM_LIT> ) { if ( in_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , <NUM_LIT> , src , TRUE , TRUE , srcbase , & srcoffset ) ) ; else emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , in_words_to_go , src , TRUE , FALSE , srcbase , & srcoffset ) ) ; if ( out_words_to_go ) { if ( out_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , <NUM_LIT> , dst , TRUE , TRUE , dstbase , & dstoffset ) ) ; else if ( out_words_to_go != <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , out_words_to_go , dst , TRUE , ( last_bytes == <NUM_LIT> ? FALSE : TRUE ) , dstbase , & dstoffset ) ) ; else { mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; if ( last_bytes != <NUM_LIT> ) { emit_insn ( gen_addsi3 ( dst , dst , GEN_INT ( <NUM_LIT> ) ) ) ; dstoffset += <NUM_LIT> ; } } } in_words_to_go -= in_words_to_go < <NUM_LIT> ? in_words_to_go : <NUM_LIT> ; out_words_to_go -= out_words_to_go < <NUM_LIT> ? out_words_to_go : <NUM_LIT> ; } if ( out_words_to_go ) { rtx sreg ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; sreg = copy_to_reg ( mem ) ; mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , sreg ) ; in_words_to_go -- ; gcc_assert ( ! in_words_to_go ) ; } if ( in_words_to_go ) { gcc_assert ( in_words_to_go > <NUM_LIT> ) ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; part_bytes_reg = copy_to_mode_reg ( SImode , mem ) ; } gcc_assert ( ! last_bytes || part_bytes_reg ) ; if ( BYTES_BIG_ENDIAN && last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> * ( <NUM_LIT> - last_bytes ) ) ) ) ; part_bytes_reg = tmp ; while ( last_bytes


<s> llvm_unreachable ( <STR_LIT> ) ; return -


<s> F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; return convertLocVTToValVT ( DAG , Val , VA


<s> OS << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { MCSym = GetBlockAddressSymbol ( ACPV -> getBlockAddress ( ) ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = ACPV -> getGV ( ) ; MCSym = Get<ISA_LIT>GVSymbol ( GV ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; MCSym = GetExternalSymbolSymbol ( ACPV -> getSymbol ( ) ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( MAI -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext )


<s> Value * <ISA_LIT>IREmitter :: visitVUZP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> return ( uint8x8_t ) __builtin_aarch64_uqmovnv8hi (


<s> } } else { const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; bool IsIndirect = Subtarget . isGVIndirectSymbol ( GV ) ; unsigned TargetFlags = <STR_LIT> ; if ( Subtarget . isTargetMachO ( ) ) { TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags |= <STR_LIT> ; else if ( IsIndirect ) TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isGVInGOT ( GV ) ) { TargetFlags |= <STR_LIT> ; } BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , TargetFlags ) ; if ( IsIndirect ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm


<s> if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] ) ) MatchOddMask = false ; } if ( ! MatchEvenMask && ! MatchOddMask ) return SDValue ( ) ; SDValue UndefNode = DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Op0 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = SVOp -> getOperand ( <NUM_LIT> ) ; if ( MatchEvenMask ) { static const int ShiftRightMask [ ] = { - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> } ; Op1 = DAG . getVectorShuffle ( VT , dl , Op1 , UndefNode , ShiftRightMask ) ; } else { static const int ShiftLeftMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT>


<s> rtx_insn * insn ; rtx_jump_insn * jump_insn ; shorten_branches ( get_insns ( ) ) ; something_changed = false ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( ( jump_insn = dyn_cast < rtx_jump_insn * > ( insn ) ) && get_attr_length ( jump_insn ) > <NUM_LIT> && ( any_condjump_p ( jump_insn ) || any_uncondjump_p ( jump_insn ) ) ) { rtx old_label , temp , saved_temp ; rtx_code_label * new_label ; rtx target ; rtx_insn * jump , * jump_sequence ; start_sequence ( ) ; saved_temp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; temp = gen_rtx_REG ( Pmode , GP_REG_FIRST + <NUM_LIT> ) ; emit_move_insn ( saved_temp , temp ) ; old_label = JUMP_LABEL ( jump_insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump )


<s> int64_t Imm = MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Imm != <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; int StackAdjustment ; if ( Subtarget . is64Bit ( ) ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> || MIB -> getOpcode ( ) == <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getUsesRedZone ( ) ) { MIB -> setDesc ( TII . get ( MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB . getReg ( <NUM_LIT> ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MIB -> removeOperand ( <NUM_LIT> ) ; MIB -> addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget


<s> Register SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( ( Type == <STR_LIT> || Type == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> )


<s> int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int icode ; rtx pat , op0 ; tree arg0 ; switch ( fcode ) { case AARCH64_BUILTIN_GET_FPCR : case AARCH64_BUILTIN_SET_FPCR : case AARCH64_BUILTIN_GET_FPSR : case AARCH64_BUILTIN_SET_FPSR : if ( ( fcode == AARCH64_BUILTIN_GET_FPCR ) || ( fcode == AARCH64_BUILTIN_GET_FPSR ) ) { icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = force_reg ( SImode , expand_normal ( arg0 ) ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; case AARCH64_PAUTH_BUILTIN_AUTIA1716 : case AARCH64_PAUTH_BUILTIN_PACIA1716 : case AARCH64_PAUTH_BUILTIN_XPACLRI : arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = force_reg ( Pmode , expand_normal ( arg0 ) ) ; if ( ! target ) target = gen_reg_rtx ( Pmode ) ; else target = force_reg ( Pmode , target ) ; emit_move_insn ( target


<s> return ( __m512i ) __builtin_ia32_pshufd512_mask ( ( __v16si ) __A , __mask , (


<s> return ( __m128d ) __builtin_ia32_cvtps2pd ( ( __v4sf


<s> if ( isFloatingPointZero ( Op ) ) return DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> getAlignment ( ) ) ; llvm_unreachable ( <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg (


<s> case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT>


<s> hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode


<s> static DecodeStatus DecodeGPRwithZRnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >= CodeGenOpt


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFCCRegs ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; break ; } case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; uint64_t Offset = CN -> getSExtValue (


<s> return __builtin_aarch64_sshlv2si ( __a ,


<s> void aarch64_simd_lane_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high , const_tree exp ) { HOST_WIDE_INT lane ; gcc_assert ( CONST_INT_P ( operand ) ) ; lane = INTVAL ( operand


<s> if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> static SDValue performExtendCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { SDNode * ABDNode = N -> getOperand ( <NUM_LIT>


<s> initialize<ISA_LIT>PostRewritePass ( * PassRegistry ::


<s> void Emitter < CodeEmitter > :: emitGlobalAddress ( GlobalValue * GV , unsigned Reloc , intptr_t Disp , intptr_t PCAdj , bool NeedStub , bool Indirect ) { intptr_t RelocCST = <NUM_LIT> ; if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , RelocCST , NeedStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , RelocCST , NeedStub ) ; MCE . addRelocation ( MR ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE


<s> rtx addr ; unsigned long saved_regs ; offsets = arm_get_frame_offsets ( ) ; saved_regs = offsets -> saved_regs_mask ; if ( ( saved_regs & ( <NUM_LIT> << LR_REGNUM ) ) == <NUM_LIT> ) emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNUM ) , source ) ; else { if ( frame_pointer_needed ) addr = plus_constant ( Pmode , hard_frame_pointer_rtx , - <NUM_LIT> ) ; else { delta = offsets -> outgoing_args - ( offsets -> frame + <NUM_LIT> ) ; if ( delta >= <NUM_LIT> ) { emit_insn ( gen_addsi3 ( scratch , stack_pointer_rtx , GEN_INT ( delta & ~ <NUM_LIT> ) ) ) ; addr = scratch ; delta &= <NUM_LIT> ; } else addr = stack_pointer_rtx ; addr = plus_constant ( Pmode


<s> uint64_t missing_extensions = required_extensions & ~ aarch64_isa_flags ; if ( missing_extensions == <NUM_LIT> ) return check_required_registers ( location , fndecl ) ; static const struct { uint64_t flag ; const char * name ; } extensions [ ] = { SYNTHETIC , FEATURE_STRING ) \ { FLAG_CANONICAL , EXT_NAME } , } ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( extensions ) ; ++ i ) if ( missing_extensions & extensions [ i ] . flag ) { report_missing_extension ( location , fndecl , extensions [ i ] . name ) ; return false


<s> const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , Chain . getValue


<s> assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == Count - <NUM_LIT> ) LdrOpc = <STR_LIT> ; else LdrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == Count - <NUM_LIT> ) LdrOpc = <STR_LIT> ; else LdrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ i ] . getFrameIdx ( ) << <STR_LIT> << CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == Count - <NUM_LIT> ) ? Count : Count - i - <NUM_LIT> ; assert ( ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> )

MIB . addReg ( <STR_LIT> , RegState :: Define ) ;


<s> if ( T . getArch ( ) == Triple :: ppc64le ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( T ) ; if ( ! is64Bit || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; if ( is64Bit || ! T . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( code , GET_MODE


<s> static bool regJustKilledBefore ( const LiveIntervals & LIs , unsigned reg


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; } } Parser . Lex (


<s> if ( Offset > <NUM_LIT> ) { uint8_t Buff [ <NUM_LIT> ] ; Buff [ <NUM_LIT> ] = <STR_LIT> :: UNWIND_OPCODE_INC_VSP_ULEB128 ; size_t ULEBSize = encodeULEB128 ( ( Offset - <NUM_LIT> ) >> <NUM_LIT> , Buff + <NUM_LIT> ) ; emitBytes ( Buff , ULEBSize + <NUM_LIT> ) ; } else if ( Offset > <NUM_LIT> ) { if ( Offset > <NUM_LIT> ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_INC_VSP | <NUM_LIT> ) ; Offset -= <NUM_LIT> ; } EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_INC_VSP | static_cast < uint8_t > ( ( Offset - <NUM_LIT> ) >> <NUM_LIT> ) ) ; } else if ( Offset < <NUM_LIT>


<s> bool <ISA_LIT>FastISel :: SelectTrunc ( const Instruction * I ) { Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I ->


<s> if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= -


<s> auto & MF = MIRBuilder . getMF ( ) ; const auto & F = * MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv (


<s> MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) , GlobalBaseReg ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) : AsmPrinter ( O , TM , Ctx , Streamer , T ) , AFI ( NULL ) , MCP ( NULL ) { Subtarget = & TM . getSubtarget


<s> if ( ScalarType . isFloatingPoint ( ) ) { unsigned ScalarSize = ScalarType . getSizeInBits ( ) ; assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned MaskVal = ( ScalarSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 (


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) ) ; unsigned FixupKind ; if ( isa < <ISA_LIT>MCExpr > ( MO .


<s> switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT>


<s> return ( get<ISA_LIT>RegEncoding ( MI , OpNum ) >> <NUM_LIT> )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes


<s> return ( loongarch_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG_REG && REG_P


<s> return __builtin_mve_vqdmladhxq_sv16qi ( __inactive ,


<s> void <ISA_LIT>TargetStreamer :: finishAttributeSection ( ) { llvm_unreachable (


<s> Relocator :: Result unsupported ( Relocation & pReloc , <ISA_LIT>Relocator & pParent


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedGatherBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr ->

getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> const MCSymbolRefExpr * HighestExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST , getContext ( ) ) ; const MCSymbolRefExpr * HigherExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER , getContext ( ) ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateExpr ( HighestExpr ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < false > ( MCOperand :: CreateExpr ( HigherExpr ) , RegNo , SMLoc ( ) , Instructions ) ; createShiftOr < true > ( MCOperand :: CreateExpr ( HiExpr ) , RegNo , SMLoc ( ) , Instructions ) ; createShiftOr < true > ( MCOperand :: CreateExpr ( LoExpr ) , RegNo , SMLoc ( ) , Instructions ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < false > ( MCOperand :: CreateExpr ( LoExpr )


return new <ISA_LIT>DarwinTargetAsmInfo ( * this ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSImm8OptLsl ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = <STR_LIT> ( MO1 . getImm ( ) ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( MO . getImm ( ) & <NUM_LIT> ) | ( ShiftVal == <NUM_LIT> ? <NUM_LIT> : ( <NUM_LIT>


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned ArgNo = <NUM_LIT> ; for ( auto & Arg : Args ) { EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F .


<s> void MVEGatherScatterLowering :: pushOutMul ( PHINode * & Phi , Value * IncrementPerRound , Value * OffsSecondOperand , unsigned LoopIncrement , IRBuilder < > & Builder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock (

LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ;


<s> APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( BV -> getOperand ( i ) . isUndef ( ) ) DemandedElts . clearBit ( i ) ; unsigned HalfNumElts = NumElts / <NUM_LIT> ; if ( VT . is256BitVector ( ) && DemandedElts . lshr ( HalfNumElts ) == <NUM_LIT> ) { MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; V0 = extractSubVector ( V0 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; SDValue Half = DAG . getNode ( HOpcode , SDLoc ( BV ) , HalfVT , V0 , V1 ) ; return insertSubVector ( DAG . getUNDEF ( VT ) , Half , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; } return DAG . getNode ( HOpcode , SDLoc ( BV


<s> else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * <NUM_LIT> ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * <NUM_LIT> + <NUM_LIT> ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen =


<s> other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; other_root_iter ++ ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ; delete


<s> } if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; if ( ! rs6000_inner_target_options ( args , false ) || ! rs6000_option_override_internal ( false ) || ( cur_tree = build_target_option_node ( & global_options , & global_options_set ) ) == NULL_TREE ) { if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> ) ; return false ; } } target_option_current_node = cur_tree ; rs6000_activate_target_options ( target_option_current_node ) ; if ( rs6000_target_modify_macros_ptr )


<s> } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op + <STR_LIT> , O ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <STR_LIT> , O ) ; unsigned ScaleVal = MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) { O << ',' << markup ( <STR_LIT> ) << ScaleVal << markup


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { const SDValue & Op = BV -> getOperand ( i ) ; if ( Op . isUndef ( ) ) continue ; auto * ConstNode = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! ConstNode ) return - <NUM_LIT> ; if ( ConstNode -> getAPIntValue ( ) . isAllOnesValue ( ) ) { if ( TrueIndex >= <NUM_LIT> ) return - <NUM_LIT> ; TrueIndex =


<s> } uint32_t permutationEncoding = <NUM_LIT> ; switch ( RegCount ) { case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= RenumRegs [ <NUM_LIT> ] ; break ; } assert ( ( permutationEncoding & <NUM_LIT> ) == permutationEncoding && <STR_LIT> ) ; return permutationEncoding


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) setOperationAction ( Op , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; if ( DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && Subtarget -> useSVEForFixedLengthVectors ( ) && VT

. isFixedLengthVector ( ) && VT . getFixedSizeInBits ( ) >= Subtarget -> getMinSVEVectorSizeInBits ( ) ) {


<s> Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; Offset += SPAdj ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . RemoveOperand ( FIOperandNum + <NUM_LIT> ) ; if ( Offset ==


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>LEAsmBackend ) ; } for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T ,


<s> __o = __builtin_aarch64_ld3df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf


<s> rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( use , <NUM_LIT> ) ) ; if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) { if ( arg_mode == SFmode ) { xoperands [ <NUM_LIT> ] = XEXP ( use , <NUM_LIT> ) ; xoperands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> - ( regno - <NUM_LIT> ) / <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { xoperands [ <NUM_LIT> ] = XEXP ( use , <NUM_LIT> ) ; xoperands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> - ( regno - <NUM_LIT> ) / <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> ,


<s> index_to_bundle_states [ bundle_state -> insn_num ] = bundle_state ; * entry_ptr = bundle_state ; return TRUE ; } else if ( bundle_state -> cost < ( * entry_ptr ) -> cost || ( bundle_state -> cost == ( * entry_ptr ) -> cost && ( ( * entry_ptr ) -> accumulated_insns_num > bundle_state -> accumulated_insns_num || ( ( * entry_ptr ) -> accumulated_insns_num == bundle_state -> accumulated_insns_num && ( ( * entry_ptr ) -> branch_deviation > bundle_state -> branch_deviation || ( ( * entry_ptr ) -> branch_deviation == bundle_state

-> branch_deviation && ( * entry_ptr ) -> middle_bundle_stops > bundle_state -> middle_bundle_stops ) ) ) ) ) ) {


<s> rtx insn ; if ( TARGET_REALLY_IWMMXT ) for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( reg_needs_saving_p ( reg ) ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; saved_size += <NUM_LIT> ; } if ( TARGET_VFP_BASE ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM


<s> Optional < MCFixupKind > ELF<ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . is<ISA_LIT>64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>64_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>64_ADDR16 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>64_ADDR32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>64_ADDR64 ) . Default ( - <NUM_LIT> ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ADDR16

) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ADDR32 ) . Default ( - <NUM_LIT> ) ;


<s> MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle


<s> if ( N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue WiderAssertZext = N0 . getOperand ( <NUM_LIT> ) ; EVT WiderVT = cast < VTSDNode > ( WiderAssertZext -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( NarrowerVT . bitsLT ( WiderVT ) ) { SDValue NewAssertZext = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , WiderAssertZext . getValueType ( ) , WiderAssertZext . getOperand ( <NUM_LIT>

) , DAG . getValueType ( NarrowerVT ) ) ;


<s> if ( TheTriple . isOSDarwin ( ) ) return new <ISA_LIT>MCAsmInfoDarwin ( ) ; <ISA_LIT>ELFMCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; if ( TheTriple . isOSNaCl