<s> } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == TargetOpcode :: COPY_TO_REGCLASS ) return ; if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O


<s> void aarch64_register_pragmas ( void ) { targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; targetm . resolve_overloaded_builtin = aarch64_resolve_overloaded_builtin ; targetm . check_builtin_call =


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( OSABI


<s> MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT>


<s> __vector signed int a , b , c ; a = ( __vector signed int ) vec_splats ( __m1 ) ; b = ( __vector signed int ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ; __m64_union m1 , m2 ,


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; const MCExpr * Imm ; if ( parseSymbolicImmVal ( Imm ) ) return MatchOperand_ParseFail ; else if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { uint64_t ShiftAmount = <NUM_LIT> ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Imm ) ; if ( MCE ) { int64_t Val = MCE -> getValue ( ) ; if ( Val > <NUM_LIT> && ( Val & <NUM_LIT> ) == <NUM_LIT> ) { Imm = MCConstantExpr :: Create ( Val >> <NUM_LIT> , getContext ( ) ) ; ShiftAmount = <NUM_LIT> ; } } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedImm ( Imm , ShiftAmount , S , E , getContext ( ) ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount < <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedImm ( Imm , ShiftAmount , S , E , getContext ( )


<s> static rtx aarch64_bit_representation ( rtx x ) { if ( CONST_DOUBLE_P ( x ) ) x = gen_lowpart ( int_mode_for_mode ( GET_MODE ( x ) ) . require ( ) , x ) ; return x


<s> return ( __m128i ) __builtin_ia32_pmaxuq128_mask ( ( __v2di ) __A , ( __v2di ) __B , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return <STR_LIT> ; else return


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size (


<s> return ( __m512i ) __builtin_ia32_vcvttph2dq512_mask_round ( __B , ( __v16si )


<s> if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue


<s> return __builtin_ia32_minph256_mask ( __A , __B , _mm256_setzero_ph ( ) ,


<s> unsigned NumAddrOps = MOs . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; if ( NumAddrOps < <NUM_LIT> ) addOffset ( MIB , <NUM_LIT> ) ; } else { MIB . addOperand ( MO )


<s> if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( ContainerVT . isInteger ( ) && ( VT != ContainerVT ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load , LoadChain } ,


<s> inline vector signed int vec_cmpgt ( vector float a1 , vector float a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float ) a1 , ( vector float


<s> for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Tiny ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; } else { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags | <STR_LIT> | MO_NC ; if ( Subtarget . isTargetILP32 ( ) ) { unsigned Reg32 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg32 , RegState :: Dead ) . addUse ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , LoFlags ) . addMemOperand ( * MI . memoperands_begin ( ) ) . addDef


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_VectorListAllLanes ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc =


<s> static DecodeStatus decodeLRW16Imm8 ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createImm ( ( Imm & <NUM_LIT>


<s> bool isPCOk = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isLROk = ( Opc == <STR_LIT> ) ; bool isSPOk = isPCOk || isLROk || ( Opc == <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> || Reg == <STR_LIT> ) continue ; if ( isPCOk && Reg == <STR_LIT> ) continue ; if ( isLROk && Reg == <STR_LIT> ) continue ; if ( Reg == <STR_LIT> ) { if ( isSPOk ) continue ; if ( i == <NUM_LIT> && ( Opc ==

<STR_LIT> || Opc == <STR_LIT> ) ) continue ;


<s> const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= InsertVPTBlocks ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Modified


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int reg = pcum -> reg ; machine_mode mode = arg . mode ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = pcum -> freg ; if ( reg < CSKY_NPARM_FREGS ) return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM + reg ) ; else return NULL_RTX


<s> unsigned Align = std :: min ( ArgFlags . getOrigAlign ( ) , StackAlign ) ; for ( auto & It : PendingMembers ) { It . convertToMem ( State . AllocateStack ( Size , std :: max ( Align , SlotAlign ) ) ) ; State . addLoc ( It ) ; SlotAlign = <NUM_LIT>


<s> SDValue StVal = St . getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NumVecElts = VT . getVectorNumElements ( ) ; if ( NumVecElts != <NUM_LIT> && NumVecElts != <NUM_LIT> ) return SDValue ( ) ; if ( St . isTruncatingStore ( ) ) return SDValue ( ) ; std :: bitset < <NUM_LIT> > IndexNotInserted ( ( <NUM_LIT> << NumVecElts ) - <NUM_LIT> ) ; SDValue SplatVal ; for ( unsigned I = <NUM_LIT> ; I < NumVecElts ; ++ I ) { if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( I == <NUM_LIT> ) SplatVal = StVal . getOperand ( <NUM_LIT> ) ; else if ( StVal . getOperand ( <NUM_LIT> ) != SplatVal ) return SDValue ( ) ; ConstantSDNode * CIndex = dyn_cast < ConstantSDNode > ( StVal .


<s> if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: NoDeref , AddrDispShift , DIExpression :: WithStackValue ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI .


<s> return rclass ; } if ( is_constant || GET_CODE ( x ) == PLUS ) { if ( reg_class_subset_p ( GENERAL_REGS , rclass ) ) return GENERAL_REGS ; if ( reg_class_subset_p ( BASE_REGS , rclass ) ) return BASE_REGS ; return NO_REGS ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && rclass == NON_SPECIAL_REGS ) return GENERAL_REGS ; return rclass


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default :


<s> if ( VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( IsThreadLocal ) return <NUM_LIT> ; emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF , IsThreadLocal ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { unsigned TempReg = createResultReg ( RC


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI


<s> MVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = VecIns . size ( ) ; i < e ; ++ i ) VecIns [ i ] = DAG . getBitcast ( TestVT , VecIns [ i ] ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [ Slot ] ; SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> , DL


<s> for ( unsigned I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) ,

std :: max ( MaxAlign , getStackAlignment ( ) ) ) ;


<s> MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; assert ( MO -> isReg ( ) && <STR_LIT> ) ; if ( ! MO ) return <STR_LIT> ; if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { SReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( Register :: isVirtualRegister ( SReg ) ) { if ( MO -> getSubReg ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } return getDPRLaneFromSPR (


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT>


<s> function_args_iterator args_iter ; tree type ; int nvreg = <NUM_LIT> ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > <NUM_LIT> ) return


<s> const InstrItineraryData & getInstrItineraryData


<s> static rtx rs6000_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing )


<s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm


<s> return AsmToken ( lexedToken ) ; case AsmToken :: Error : SetError ( Lexer -> getErrLoc ( ) , Lexer -> getErr ( ) ) ; return AsmToken ( lexedToken ) ; case AsmToken :: Identifier : { std :: string upperCase = lexedToken . getString ( ) . str ( ) ; std :: string lowerCase = LowercaseString ( upperCase ) ; StringRef lowerRef ( lowerCase ) ; unsigned regID = MatchRegisterName ( lowerRef ) ; if ( regID ) { return AsmToken ( AsmToken :: Register , lexedToken . getString ( ) , static_cast < int64_t > ( regID


<s> return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; std :: map < unsigned , unsigned > Substs ; for ( MachineInstr & I : * G ) { if ( ! G -> contains ( I ) && ( & I != G -> getKill ( ) || G -> isKillImmutable ( ) ) ) continue ; std :: vector < unsigned > ToErase ; for ( auto & U : I . operands ( ) ) { if ( U . isReg ( ) && U . isUse ( ) && Substs . find ( U . getReg ( ) ) != Substs . end ( ) ) { unsigned OrigReg = U . getReg ( ) ; U . setReg ( Substs [ OrigReg


<s> assert ( VT . isFloatingPoint ( ) && VT != <STR_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && <STR_LIT> ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignMask ( EltSizeInBits ) ) , dl , LogicVT ) ; SDValue MagMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignedMaxValue ( EltSizeInBits ) ) , dl , LogicVT ) ; if ( IsFakeVector ) Sign = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign , SignMask ) ; SDValue MagBits ; if ( ConstantFPSDNode * Op0CN = isConstOrConstSplatFP ( Mag ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; APF . clearSign ( ) ; MagBits = DAG . getConstantFP ( APF ,


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg (


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg .


<s> if ( VT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) return splitVectorIntUnary ( Op , DAG ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Subtarget . hasGFNI ( ) ) { MVT MatrixVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue Matrix = DAG . getConstant ( <NUM_LIT> , DL , MatrixVT ) ; Matrix = DAG . getBitcast ( VT , Matrix ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , Matrix , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SmallVector < SDValue , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) GPRCS2Size += <NUM_LIT> ; else GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; if ( tryFoldSPUpdateIntoPushPop ( MF , prior ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; NumBytes = <NUM_LIT> ; } if ( HasFP ) { FramePtrOffsetInBlock += MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( <STR_LIT> ) . addImm ( FramePtrOffsetInBlock / <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( NumBytes ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ; if ( STI . isTargetELF ( ) && HasFP ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF ) )


<s> static void check_enabling ( void ) \ { \ extern long sysconf ( int ) ; \ \ int prot = ( int )

sysconf ( <NUM_LIT> ) ; \ if ( prot != <NUM_LIT> ) \ need_enable_exec_stack = <NUM_LIT> ; \ }


<s> EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff ) ; ++ i ; DstOff += VTSize ; BytesLeft -= VTSize ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [


_mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsDupOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsDupOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsDupOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; IsLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; IsLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; IsStore = true ; IsLaneOp = true ; break ; } EVT VecTy ; if ( IsStore ) VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; else VecTy = N -> getValueType ( <NUM_LIT> ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits (


<s> return ( DarwinDirective == <STR_LIT> ) &&


<s> output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands )


<s> return <ISA_LIT>SelectExtractValue ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { MVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I ->


<s> if ( isSRA16 ( Op ) ) return isSHL16 ( Op . getOperand ( <NUM_LIT> ) ) ; return DAG . ComputeNumSignBits ( Op ) ==


<s> return MatchOperand_Success ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount < <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImmWithLSL ( Imm , ShiftAmount , false , S , E ) ) ; return


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t FPOffset = Offset - <NUM_LIT> * <NUM_LIT> ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; if ( TFI -> hasFP ( MF ) && isFrameOffsetLegal ( MI , FPOffset ) ) return false ; if ( isFrameOffsetLegal ( MI , Offset ) ) return false ; return true


<s> bool moveAllToNextBlock = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I == MBB -> begin ( ) && ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) ) { continue ; } if ( std :: next ( I ) == E || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> ) && ! ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) interleavingQueue . push ( I ) ; while ( interleavingQueue . size ( ) != <NUM_LIT> ) { MachineBasicBlock :: iterator interleavedI = interleavingQueue . front ( ) ; MachineInstr * slaveinst = MF . CloneMachineInstr ( & * interleavedI ) ; slaveinst -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < interleavedI -> getNumOperands ( ) ; opcount ++ ) { if ( interleavedI -> getOperand ( opcount ) . isReg ( ) ) { slaveinst -> getOperand ( opcount ) . setReg ( getSlaveReg ( interleavedI -> getOperand ( opcount ) . getReg ( ) ) ) ; } else if ( interleavedI -> getOperand ( opcount ) . isImm ( ) && ( interleavedI -> mayStore ( ) || interleavedI -> mayLoad ( ) ) ) { slaveinst -> getOperand ( opcount ) . setImm ( interleavedI -> getOperand ( opcount ) . getImm ( ) - MEMZDC_OFFSET ) ; } } MBB -> insert ( I , slaveinst ) ; interleavingQueue . pop ( ) ; } } else if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { while ( interleavingQueue . size ( ) != <NUM_LIT> ) { MachineBasicBlock :: iterator interleavedI = interleavingQueue . front ( ) ; MachineInstr * slaveinst = MF . CloneMachineInstr ( & * interleavedI ) ; slaveinst -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < interleavedI -> getNumOperands ( ) ; opcount ++ ) { if ( interleavedI -> getOperand ( opcount ) . isReg ( ) ) { slaveinst -> getOperand ( opcount ) . setReg ( getSlaveReg ( interleavedI -> getOperand ( opcount ) . getReg


<s> std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return VSt ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand (


<s> bool loongarch_can_use_return_insn ( void ) { return reload_completed && cfun -> machine ->


<s> if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg2 ) ) MRI . constrainRegClass ( SrcReg2 , RC ) ; MachineInstrBuilder MIB ; if ( kind == FMAInstKind :: Default ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) ; else if ( kind == FMAInstKind :: Indexed ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg

( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addImm ( MUL -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> BuildMI ( MBB , I , I -> getDebugLoc (


. sym , LCT_NORMAL , VOIDmode , tramp , SImode ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S = MCDisassembler


<s> const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , Context ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , Context ) ; return MCBinaryExpr :: CreateAdd ( Res ,


<s> static DecodeStatus decodeU4ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Callee , Sym ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Callee ) ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>RegisterInfo :: lowerCRBitRestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> } for ( unsigned i = <NUM_LIT> ; i < C . VL . size ( ) ; i += <NUM_LIT> ) { auto * LdOp0 = dyn_cast < LoadInst > ( C . VL [ i ] ) ; auto * LdOp1 = dyn_cast < LoadInst > ( C . VL [ i + <NUM_LIT> ] ) ; if ( ! LdOp0 || ! LdOp1 ) return false ; C . MemLocs . push_back ( MemoryLocation ( LdOp0 -> getPointerOperand ( ) , Size ) ) ; C . MemLocs . push_back ( MemoryLocation ( LdOp1 -> getPointerOperand ( ) , Size ) ) ; } } return


<s> for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) ,


<s> const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , SFmode ) ) return - <NUM_LIT> ; HOST_WIDE_INT hwint = exact_log2 ( real_to_integer ( r ) ) ; if ( ! IN_RANGE ( hwint , <NUM_LIT> , <NUM_LIT> ) ) return - <NUM_LIT> ; return hwint


<s> default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; break ; case


<s> if ( decl && TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) flags |= SECTION_PE_SHARED ; } if ( decl && DECL_P ( decl ) && DECL_ONE_ONLY ( decl ) ) flags |= SECTION_LINKONCE ; return flags


<s> else if ( tDest ) Opc = <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; assert ( <STR_LIT> . contains ( DestReg , SrcReg


<s> assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size ) + ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; } else { assert ( ( Size == <NUM_LIT> || isIntN ( Size * <NUM_LIT> + <NUM_LIT> , SignedValue ) ) && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t


<s> bool SelectAddrModeUnscaled8 ( SDValue N , SDValue & Base , SDValue &


<s> const MCExpr * Expr = Operand . getExpr ( ) ; const MCSymbolRefExpr * SymExpr = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( ! SymExpr || SymExpr -> getKind ( ) != MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT ) return


<s> switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return None ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MO , GetSymbolFromOperand ( MO ) ) ; case MachineOperand :: MO_MCSymbol : return LowerSymbolOperand ( MO , MO . getMCSymbol ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; case MachineOperand :: MO_RegisterMask : return


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> ,

<STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> const LLT v16s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v8s16 } , Legal


<s> return ( __m128i ) __builtin_ia32_pmovzxbw128_mask ( ( __v16qi ) __A , (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % <NUM_LIT> ==


<s> if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && ( ! Alignment || * Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> &&

( ! Alignment || * Alignment >= <NUM_LIT> ) ) || EltWidth == <NUM_LIT> ) ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering (


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute ::

SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ;


<s> __builtin_altivec_dst ( ( void * ) a1


<s> SMLoc OffsetLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) ) return Error ( OffsetLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( OffsetLoc , <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } if ( parseToken ( AsmToken :: EndOfStatement


<s> OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getRepresentedCsect ( ) ) ; llvm :: for_each ( GOAliasMap [ & MF -> getFunction ( ) ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias ) ) ; } ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext ) , PointerSize ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , PointerSize ) ; OutStreamer -> SwitchSection ( Current . first


<s> for ( Loop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return


<s> SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; EVT T = Node -> getValueType ( <NUM_LIT> ) ; SDValue negOp = DAG . getNode ( <STR_LIT> , dl , T , DAG . getConstant ( <NUM_LIT> , T ) , Node -> getOperand ( <NUM_LIT> ) ) ; return DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand (

<NUM_LIT> ) , negOp , cast < AtomicSDNode > ( Node ) -> getSrcValue ( ) , cast < AtomicSDNode > ( Node ) -> getAlignment ( ) ) ;


<s> static bool isFloatingPointOpcodeUse ( unsigned Opc ) { switch ( Opc ) { case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI : case TargetOpcode ::


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI


<s> case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M , MCContext *


<s> bool <ISA_LIT>RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { llvm_unreachable ( <STR_LIT>


<s> bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) ,


<s> return ( Dest & <NUM_LIT> ) | ( ( Base & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Offset &


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit


<s> unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned s = <NUM_LIT> ; s < NumLanes ; ++ s ) { unsigned Start = s * NumLaneElts ; unsigned End = s * NumLaneElts + NumLaneElts / <NUM_LIT> ; for ( unsigned i = Start ; i != End ; ++ i ) { ShuffleMask . push_back ( i


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo )


<s> if ( CalleePopAmount == <NUM_LIT> ) { assert ( Amount > - <NUM_LIT> && Amount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , Amount , TII ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , - CalleePopAmount , TII ) ; } return MBB . erase (


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name == '*' ) name


<s> const bool MinSize = ST . hasMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideIn<ISA_LIT>Mode ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector


<s> const MCAsmInfo * MAI = MI . getMF ( ) -> getTarget ( ) . getMCAsmInfo ( ) ; bool NeedsWinCFI = MAI -> usesWindowsCFI ( ) && MI . getMF ( ) -> getFunction ( ) . needsUnwindTableEntry ( ) ; if ( NeedsWinCFI && ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } return true


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( TheARM64Target , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: aarch64 , true > Z ( The<ISA_LIT>leTarget , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: aarch64_be , true > W (


<s> uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Val ) ; unsigned BytesLeft = <NUM_LIT> ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; if ( Alignment > Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && Alignment > Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } } else if ( Alignment == Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } else { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT AddrVT = Dst . getValueType (


<s> return create<ISA_LIT>ObjectWriter ( OS ,


<s> if ( check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) ) return true ; const MCConstantExpr * Value = dyn_cast_or_null < MCConstantExpr > ( Expr ) ; if ( check ( ! Value , L , <STR_LIT> ) ) return true ; getTargetStreamer ( ) . emitInst ( Value -> getValue ( ) ) ; return false ; } ; if ( parseMany ( parseOp ) ) return addErrorSuffix ( <STR_LIT> ) ; return


<s> <ISA_LIT>ELFWriterInfo :: <ISA_LIT>ELFWriterInfo ( bool is64Bit_ , bool isLittleEndian_ ) : TargetELFWriterInfo ( is64Bit_ , isLittleEndian_ ) { EMachine =


<s> if ( address_is_prefixed ( x , mode , NON_PREFIXED_DEFAULT ) ) return <NUM_LIT> ; if ( quad_offset_p ) { if ( quad_address_p ( x , mode , reg_ok_strict ) ) return <NUM_LIT> ; } else if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; else if ( reg_offset_p ) { if ( legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; } if ( mode == TImode && TARGET_VSX ) return <NUM_LIT> ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( XEXP ( x , <NUM_LIT> ) == virtual_stack_vars_rtx || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return <NUM_LIT> ; if ( ! FLOAT128_2REG_P ( mode ) && ( TARGET_HARD_FLOAT || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , <NUM_LIT> ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addr = XEXP ( x , <NUM_LIT> ) ; return ! address_is_prefixed ( addr , mode , NON_PREFIXED_DEFAULT ) ; } if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return <NUM_LIT> ; return


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ; return FrameAddr


<s> unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) )


<s> case E_PTImode : case E_IFmode : case E_KFmode : extra = <NUM_LIT> ; break ; default : break ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = ( ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , gen_int_mode ( high_int , Pmode ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC_OR_PCREL && ! flag_pic && ! CONST_INT_P ( x ) && ! CONST_WIDE_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; return getAddr ( N


<s> void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode


<s> const unsigned ProbeSize = getStackProbeSize ( * MF ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( physSPReg ) . addReg ( FinalStackPtr ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB ) ; BuildMI ( tailMBB , DL , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg (


<s> } std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( )


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned RegOpNum = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned BaseRegNum = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isImmOpnd ) { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; ImmOffset = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; LoOffset = ImmOffset & <NUM_LIT> ; HiOffset = ( ImmOffset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; } else ExprOffset = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; TempInst . setLoc ( IDLoc ) ; TmpRegNum = ( isLoad && ( BaseRegNum != RegOpNum ) ) ? RegOpNum : AtRegNum ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } } Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( BaseRegNum ) ) ; Instructions . push_back ( TempInst ) ; TempInst . clear ( )


<s> return new <ISA_LIT>LoopInstrFormPrep ( TM


<s> if ( ! <STR_LIT> . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; } } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) &&


<s> IsEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ; if ( Subtarget -> in<ISA_LIT>16Mode ( )


<s> static std :: map < unsigned , std :: pair < unsigned , unsigned >> VFMKMap = { { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , } ; unsigned Opcode = MI . getOpcode ( ) ; auto Found = VFMKMap . find ( Opcode


<s> return ( __m512i ) __builtin_ia32_vcvtph2udq512_mask_round ( __B , ( __v16si ) _mm512_setzero_si512 ( ) , __A ,


<s> mcld :: DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const mcld :: Target & pTarget


<s> unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return Error ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) return Error ( Start , <STR_LIT> <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , Start , End ) ) ; return false ; } if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return Error ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return true ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo & Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return


<s> if ( ! ST -> hasMVEFloatOps ( ) ) return SDValue ( ) ; return LowerVecReduce ( Op , DAG ,


<s> SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR , Cmp ) ; } } } return DAG . getSelectCC ( dl , Cond , DAG . getConstant ( <NUM_LIT> , Cond .

getValueType ( ) ) , SelectTrue , SelectFalse , <STR_LIT> ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = IsN64 ? <STR_LIT>


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitLD_F16_PSEUDO ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) MIB . add ( MI . getOperand ( i ) ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( Rt , <NUM_LIT> , <STR_LIT> ) ; Rt = Tmp ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Rt ) ; MI . eraseFromParent ( ) ; return BB


<s> SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In


<s> else if ( GET_CODE ( op ) == PRE_MODIFY || GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , <NUM_LIT> ) ; if ( CONST_INT_P ( op ) )


<s> bool isDXReg ( ) const { return Kind == Memory && getMemBaseReg ( ) == <STR_LIT> && ! getMemIndexReg


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> unsigned Imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; uint64_t FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ( FeatureBits & <STR_LIT> ) == <NUM_LIT> || ( FeatureBits & <STR_LIT> ) == <NUM_LIT>


<s> movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - GPRCS2Size ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - DPRCSSize ) ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; } AFI -> setGPRCalleeSavedArea1Size


<s> BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase


<s> old_reg = gen_reg_rtx ( mode ) ; new_reg = old_reg ; old_mem = copy_to_reg ( mem ) ; loop_label = gen_label_rtx ( ) ; emit_label ( loop_label ) ; emit_move_insn ( old_reg , old_mem ) ; if ( ! after ) emit_move_insn ( target , old_reg ) ; if ( code == NOT ) { new_reg = expand_simple_binop ( mode , AND , new_reg , val , NULL_RTX , true ,


<s> DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: reverse_iterator Ins ; unsigned CRBitSpillDistance = <NUM_LIT> ; for ( Ins = MI ; Ins != MBB . rend ( ) ; Ins ++ ) { if ( Ins -> modifiesRegister ( SrcReg , TRI ) ) break ; if ( CRBitSpillDistance == MaxCRBitSpillDist ) { Ins = MI ; break ; } if ( ! Ins -> isDebugInstr ( ) ) CRBitSpillDistance ++ ; } if ( Ins == MBB . rend ( ) ) Ins = MI ; switch ( Ins -> getOpcode (


<s> SDValue Value0 , Value1 ; std :: tie ( Value0 , Value1 ) = splitVector ( StoredVal , DAG , DL ) ; unsigned HalfAlign = ( StoredVal . getValueType ( ) . is256BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , DL


<s> CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; FuncReturnHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ; return handleAssignments ( MIRBuilder , RetInfo ,


<s> unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; unsigned Rm = CTX . getRegisterInfo ( ) . getEncodingValue ( MO2 . getReg (


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizeMathLibCalls (


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return Modified


<s> static inline bool IsGPR ( unsigned RegClass ) { return RegClass == <STR_LIT> ||


<s> case 'c' : if ( ! TARGET_AVX ) return - <NUM_LIT> ; return TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - <NUM_LIT> ; return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectScalarSSELoad ( SDNode * Root , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment , SDValue & PatternNodeWithChain ) { if ( N . getOpcode ( ) == <STR_LIT> ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && PatternNodeWithChain . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD , <NUM_LIT> ) ; return


<s> else if ( CONSTANT_P ( arg0 ) && CONSTANT_P ( arg1 ) ) { output_addr_const ( file , addr ) ; break ; } else abort_with_insn ( addr , <STR_LIT> ) ; if ( ! CONSTANT_P ( offset ) ) abort_with_insn ( addr , <STR_LIT> ) ; if ( REGNO ( reg ) == ARG_POINTER_REGNUM ) abort_with_insn ( addr , <STR_LIT> ) ; output_addr_const ( file , offset ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( reg ) ] ) ; } break ; case LABEL_REF : case SYMBOL_REF : case CONST_INT : case CONST : output_addr_const ( file , addr ) ; if ( GET_CODE ( addr ) == CONST_INT ) fprintf ( file ,


<s> } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget ->


<s> case 'f' : case 't' : case 'u' : if ( type -> isFloatingPointTy ( ) ) weight = CW_SpecificReg ; break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && ! DisableMMX && Subtarget -> hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'x' : case 'Y' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasXMM ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C'


<s> return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || constant_pool_empty_p ( )


<s> else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) , OpFlag ) ; DebugLoc DL = JT -> getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( OpFlag ) Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Result ) ; return Result


<s> assert ( CPI < ConstPoolId2AddrMap . size ( ) ) ; return ConstPoolId2AddrMap [ CPI


<s> RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc = LUi ; Seq [ <NUM_LIT> ] . ImmOpnd = ( unsigned ) ( ShiftedImm & <NUM_LIT> ) ; Seq . erase ( Seq . begin ( )


<s> MI . addOperand ( MCOperand :: createImm ( <ISA_LIT>ValToRD ( cf )


<s> if ( ! IsSplat && NumOps == <NUM_LIT> && VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) && Op0 . getOperand ( <NUM_LIT> ) == Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Src ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) Src . push_back ( Ops [ i ] . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op0 . getOpcode ( ) , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! IsSplat && NumOps == <NUM_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX ( ) && Op0 . getOperand ( <NUM_LIT> ) == Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Src ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) Src . push_back ( DAG . getBitcast ( <STR_LIT> , Ops [ i ] . getOperand ( <NUM_LIT> ) ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( VT , Res ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) && ( EltSizeInBits >= <NUM_LIT> || Subtarget . useBWIRegs ( ) ) ) ) && llvm :: all_of ( Ops , [ Op0 ] ( SDValue Op ) { return Op0 . getOperand ( <NUM_LIT> ) == Op . getOperand ( <NUM_LIT> ) ; } ) ) { SmallVector < SDValue , <NUM_LIT> > Src ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) Src . push_back ( Ops [ i ] . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op0 . getOpcode ( ) , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } break ; case


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; MRI . setType ( ValVReg , LLT ::


<s> NumExtracts = <NUM_LIT> ; unsigned ExpectedOpcode = <STR_LIT> ; unsigned NextExpectedOpcode = <STR_LIT> ; bool AddFound = false ; bool SubFound = false ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return false ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return false ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return false ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . isUndef ( ) ) { InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec0 . getSimpleValueType ( ) != VT ) return false ; } if ( InVec1 . isUndef ( ) ) { InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getSimpleValueType ( ) != VT )


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return &


<s> PreAnalyzeCallOperands ( Outs , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear


<s> bool SelectCntImm ( SDValue N , SDValue & Imm ) { if ( ! isa < ConstantSDNode > ( N ) ) return false ; int64_t MulImm = cast < ConstantSDNode > ( N ) ->


<s> if ( isNonZero ) { if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V


<s> default : return false ; case TargetStackID :: Default : case TargetStackID ::


<s> static void EmitGuardReturn ( int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ]


<s> SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) { Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MCNVS_WUB ( ( v4hi ) mm


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isDereferenceableInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) { if ( ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT>


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM

, CM ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> default : gcc_unreachable ( ) ; case SH_CONST_VECTOR : { gcc_assert ( GET_CODE ( body ) == SET ) ; swap_const_vector_halves ( & SET_SRC ( body ) ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , i ) ; break ; } case SH_SUBREG : adjust_subreg_index ( body ) ; if ( dump_file ) fprintf ( dump_file ,


<s> if ( <NUM_LIT> < ByteRotation ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = ByteRotation ; return true ; } } if ( ( NumMaskElts <= <NUM_LIT> && ( ( Subtarget . hasSSE41 ( ) && MaskVT . is128BitVector ( ) ) || ( Subtarget . hasAVX ( ) && MaskVT . is256BitVector ( ) ) ) ) || ( MaskVT == <STR_LIT> && Subtarget . hasAVX2 ( ) ) ) { uint64_t BlendMask = <NUM_LIT> ; bool ForceV1Zero = false , ForceV2Zero = false ; SmallVector < int , <NUM_LIT> > TargetMask ( Mask . begin ( ) , Mask . end ( ) ) ; if ( matchVectorShuffleAsBlend ( V1 , V2 , TargetMask , ForceV1Zero , ForceV2Zero , BlendMask ) ) { if ( MaskVT == <STR_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( isRepeatedTargetShuffleMask ( <NUM_LIT> , MaskVT , TargetMask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) PermuteImm |= <NUM_LIT> << i ; V1 = ForceV1Zero ? getZeroVector ( MaskVT , Subtarget , DAG , DL ) : V1 ; V2 = ForceV2Zero ? getZeroVector ( MaskVT , Subtarget , DAG , DL ) : V2 ; Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } } else { V1 = ForceV1Zero ? getZeroVector ( MaskVT , Subtarget , DAG , DL ) : V1 ; V2 = ForceV2Zero ? getZeroVector ( MaskVT , Subtarget , DAG , DL ) : V2 ; PermuteImm = ( unsigned ) BlendMask ; Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && Subtarget . hasSSE41 ( ) && MaskVT . is128BitVector ( ) && llvm :: any_of ( Mask , [ ] ( int M ) { return M == SM_SentinelZero ; } ) && matchShuffleAsInsertPS ( V1 , V2 , PermuteImm , Zeroable , Mask , DAG ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { if ( matchShuffleWithSHUFPD ( MaskVT , V1 ,


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO

. getBlockAddress ( ) ) , AP , isDarwin ) ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . push_back ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) Mask . push_back ( i ) ; return DAG . getVectorShuffle ( VT , dl , V1 , V2


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( getWRegFromXReg


<s> unsigned getPrefLoopAlignment ( ) const { return


<s> } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getElementCount ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; MMO . setType ( NewTy ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ; } else { auto NewLoad = MIRBuilder . buildLoad ( NewTy , MI . getOperand ( <NUM_LIT> ) , MMO ) ; MIRBuilder . buildBitcast ( ValReg , NewLoad ) ; } MI . eraseFromParent ( ) ; return


<s> rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op0 , op1 )


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned B = ( ( ~ Value ) &


<s> bool enableStackSize ( ) const { return EnableStackSize


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain , FPSIdx } ; SDVTList VTs = DAG . getVTList


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > EntryBlocks ; EntryBlocks . push_back ( & MF . front ( ) ) ; for ( const LandingPadInfo & LPI : MF . getLandingPads ( ) ) EntryBlocks . push_back ( LPI . LandingPadBlock ) ; for ( auto Entry : EntryBlocks ) insertSPToRegTaintPropagation ( Entry , Entry -> SkipPHIsLabelsAndDebug ( Entry -> begin ( ) ) ) ; for ( auto & MBB : MF ) Modified |= instrumentControlFlow ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( auto & MBB : MF )

Modified |= lowerSpeculationSafeValuePseudos ( MBB ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE


<s> static inline bool mode_supports_vsx_dform_quad


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > <NUM_LIT> || getSVEStackSize ( MF


<s> return sparc_function_value_1 ( valtype , TYPE_MODE (


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) . isVector ( ) ) ; Value = DAG . getBuildVector ( <STR_LIT> , DL , { Value , DAG . getUNDEF ( <STR_LIT>


<s> if ( FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) { cfun -> machine -> force_align_arg_pointer = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; return copy_to_reg ( cfun -> machine -> force_align_arg_pointer ) ; } else return


<s> case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitSaturateInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT> : emitVFPLoadStoreInstruction ( MI )


<s> if ( mode == SImode ) icode = CODE_FOR_fetchadd_rel_si ; else icode = CODE_FOR_fetchadd_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( is_mm_relaxed ( model ) || is_mm_release ( model ) || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_binop ( DImode , AND , new_reg , val


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue CMP0 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP1 = N1 -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( CMP0 . getOpcode ( ) != <STR_LIT> || CMP0 != CMP1 ) return SDValue ( ) ; SDValue CMP00 = CMP0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP01 = CMP0 -> getOperand ( <NUM_LIT> ) ; EVT VT = CMP00 . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { bool ExpectingFlags = false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ! ExpectingFlags && UI != UE ; ++ UI ) switch ( UI -> getOpcode ( ) ) { default : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ExpectingFlags = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , FSetCC ) ; return FSetCC ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG .


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT>

) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> static rtx emit_addhi3_postreload ( rtx dest , rtx src0 , rtx src1 ) { rtx set , clobber , insn ; set = gen_rtx_SET ( VOIDmode , dest , gen_rtx_PLUS ( HImode , src0 , src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; return insn


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 ,

RHS1 , CC ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;