<s> Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( )


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( useSoftFloat ( ) || ! Subtarget . has64BitSupport ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( N ) ; SDValue Op ( N , <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> && Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) <= MVT ( <STR_LIT> ) || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) > MVT ( <STR_LIT> ) ) return SDValue ( ) ; SDValue FirstOperand ( Op . getOperand ( <NUM_LIT> ) ) ; bool SubWordLoad = FirstOperand . getOpcode ( ) == <STR_LIT> && ( FirstOperand . getValueType ( ) == <STR_LIT> || FirstOperand . getValueType ( ) == <STR_LIT> ) ; if ( Subtarget . hasP9Vector ( ) && Subtarget . hasP9Altivec ( ) && SubWordLoad ) { bool Signed = N -> getOpcode ( ) == <STR_LIT> ; bool DstDouble = Op . getValueType ( ) == <STR_LIT> ; unsigned ConvOp = Signed ? ( DstDouble ? <STR_LIT> : <STR_LIT> ) : ( DstDouble ? <STR_LIT> : <STR_LIT> ) ; SDValue WidthConst = DAG . getIntPtrConstant ( FirstOperand . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> , dl , false ) ; LoadSDNode * LDN = cast < LoadSDNode > ( FirstOperand . getNode ( ) ) ; SDValue Ops [ ] = { LDN -> getChain ( ) ,


<s> MCAsmParser & Parser = getParser ( ) ; int64_t Tag ; SMLoc TagLoc ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { StringRef Name = Parser . getTok ( ) . getIdentifier ( ) ; Tag = <STR_LIT> ( Name ) ; if ( Tag == - <NUM_LIT> ) { Error ( TagLoc , <STR_LIT> + Name ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( ! CE ) { Error ( TagLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Tag = CE -> getValue ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; StringRef StringValue = <STR_LIT> ; bool IsStringValue = false ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = false ; if ( Tag == <STR_LIT> || Tag == <STR_LIT> ) IsStringValue = true ; else if ( Tag == <STR_LIT> ) { IsStringValue = true ; IsIntegerValue = true ; } else if ( Tag < <NUM_LIT> || Tag % <NUM_LIT> == <NUM_LIT> ) IsIntegerValue = true ; else if ( Tag % <NUM_LIT> == <NUM_LIT> ) IsStringValue = true ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( ValueExpr ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) { Error ( ValueExprLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } IntegerValue = CE -> getValue ( ) ; } if ( Tag == <STR_LIT> ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) IsStringValue = false ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return


<s> bool isMicro<ISA_LIT>Enabled ( ) const { return Micro<ISA_LIT>Enabled


<s> void nds32_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype ATTRIBUTE_UNUSED , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED , int n_named_args ATTRIBUTE_UNUSED ) { cum -> gpr_offset


<s> EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & module ) { OutStreamer -> EmitRawText


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl


<s> Inst . addOperand ( MCOperand :: createReg ( getMSACtrlReg ( ) )


<s> break ; case I387_CW_FLOOR : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_FLOOR ; break ; case I387_CW_CEIL : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_CEIL ; break ; case I387_CW_MASK_PM : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_MASK_PM ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case I387_CW_TRUNC : emit_insn ( gen_movsi_insv_1 ( reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_TRUNC ; break ; case I387_CW_FLOOR


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; reloc_type type = RTYPE_DIRECT ; if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : type = RTYPE_GOT ; break ; case UNSPEC_GOTOFF : type = RTYPE_GOTOFF ; break ; case UNSPEC_TPOFF : type =


<s> unsigned Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> use_instructions ( Reg ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) { MachineOperand & TrueMO = Use . getOperand ( <NUM_LIT> ) ; MachineOperand & FalseMO = Use . getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( RC && RC != & <STR_LIT> ) { SmallSet < unsigned , <NUM_LIT> > CopyHints ; CopyHints . insert ( Hints . begin ( ) , Hints . end ( ) ) ; Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; for ( MCPhysReg Reg : Order ) if ( ! CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; return true ; } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) == & <STR_LIT>


<s> unsigned BitWidth = Op1 . getValueSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( Op1 , DemandedMask , TLO ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ; } return SDValue


<s> <STR_LIT> Code = cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> get ( ) ; <STR_LIT> ExtType = isSignedIntSetCC ( Code ) ? <STR_LIT> : <STR_LIT> ; if ( isCheapToExtend ( SetCC . getOperand ( <NUM_LIT> ) ) && isCheapToExtend ( SetCC . getOperand ( <NUM_LIT> ) ) ) { const SDValue Ext1 = DAG . getNode ( ExtType , SDLoc ( N ) ,

N -> getValueType ( <NUM_LIT> ) , CCOp0 ) ;


<s> return __builtin_mve_vqaddq_n_sv4si ( __a ,


<s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) )


<s> SDValue PtrOff = DAG . getPointerAdd ( DL , StackPtr , Offset ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Arg . getValueSizeInBits ( ) / <NUM_LIT> , Offset ,


<s> if ( Index == <NUM_LIT> && MRI . getVRegDef ( SrcReg ) -> isImplicitDef ( ) ) { if ( ! emitInsertSubreg ( DstReg , InsertReg , I , MRI , MF ) ) return false ; I . eraseFromParent ( ) ; return true ; } bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> && InsertRegTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false


<s> <STR_LIT> ET = getShiftExtendType ( ) ; if ( ET == <STR_LIT> ) ET = <STR_LIT> ; unsigned Imm = <STR_LIT> ( ET , getShiftExtendAmount ( ) ) ; Inst . addOperand ( MCOperand ::


<s> } else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) { if ( Regs . back ( ) . second == <STR_LIT> ) Kind = k_FPSRegisterListWithVPR ; else Kind = k_SPRRegisterList ; } if ( Kind == k_RegisterList && Regs . back ( ) . second == <STR_LIT> ) Kind = k_RegisterListWithAPSR ; assert ( std :: is_sorted ( Regs . begin ( ) , Regs . end ( ) ) && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( const auto & P : Regs ) Op -> Registers . push_back ( P . second ) ; Op -> StartLoc


<s> if ( BaseReg ) { static const unsigned R16Table [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned RMfield = R16Table [ BaseRegNo ] ; assert ( RMfield && <STR_LIT> ) ; if ( IndexReg . getReg ( ) ) { unsigned IndexReg16 = R16Table [ get<ISA_LIT>RegNum ( IndexReg ) ] ; assert ( IndexReg16 && <STR_LIT> ) ; assert ( ( ( IndexReg16 ^ RMfield ) & <NUM_LIT> ) && <STR_LIT> ) ; assert ( Scale . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( IndexReg16 & <NUM_LIT> ) RMfield = ( RMfield & <NUM_LIT> ) | ( ( <NUM_LIT> - IndexReg16 ) << <NUM_LIT> ) ; else RMfield = ( IndexReg16 & <NUM_LIT> ) | ( ( <NUM_LIT> - RMfield ) << <NUM_LIT> ) ; } if ( Disp . isImm ( ) && isInt < <NUM_LIT> > ( Disp . getImm ( ) ) ) { if ( Disp . getImm ( ) == <NUM_LIT> && RMfield != <NUM_LIT> ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; return ; } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups ) ; return ; } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; } else { assert ( IndexReg . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; } emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_2 , StartByte , OS , Fixups ) ; return ; } bool UseDisp8 = MI . getFlags ( ) & <STR_LIT> ; bool UseDisp32 = MI . getFlags ( ) & <STR_LIT> ; bool AllowNoDisp = ! UseDisp8 && ! UseDisp32 ; bool AllowDisp8 = ! UseDisp32 ; if ( ! ForceSIB && IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! STI . hasFeature ( <STR_LIT> ) || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_4 , StartByte , OS , Fixups ) ; return ; } if ( BaseRegNo != N86 :: EBP ) { if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } if ( Disp . isExpr ( ) ) { auto * Sym = dyn_cast < MCSymbolRefExpr > ( Disp . getExpr ( ) ) ; if ( Sym && Sym -> getKind (


<s> section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> ,


<s> static DecodeStatus DecodeShiftRight16Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const


<s> if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr .


<s> for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; Register IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF ,


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return false ; return


<s> } if ( isa < StoreInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( ( isa < Constant > ( V ) && ! isa < ConstantExpr > ( V ) ) || isa < Argument > ( V ) ) return isSupportedType ( V ) ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeSP ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> <<

getFunctionNumber ( ) << '_' << uid << '_' << uid2 ;


<s> MachineInstr * MemMI = NULL ; unsigned AddrMode = ( TSFlags & <STR_LIT> ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; bool isLoad = ! TID . mayStore ( ) ; const MachineOperand & WB = isLoad ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Offset = MI -> getOperand ( NumOps - <NUM_LIT> ) ; unsigned WBReg = WB . getReg ( ) ; unsigned BaseReg = Base . getReg ( ) ; unsigned OffReg = Offset . getReg ( ) ; unsigned OffImm = MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; switch ( AddrMode ) { default : assert ( false && <STR_LIT> ) ; return NULL ; case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) { if ( <STR_LIT> ( Amt ) == - <NUM_LIT> ) return NULL ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( Amt != <NUM_LIT> ) { <STR_LIT> ShOpc = <STR_LIT> ( OffImm ) ; unsigned SOOpc = <STR_LIT> ( ShOpc , Amt ) ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addReg ( <NUM_LIT> ) . addImm ( SOOpc ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred )


<s> Operands . push_back ( <STR_LIT> ( PatchedName , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( getLexer ( ) . is ( AsmToken :: Star ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Loc ) ) ; Parser . Lex ( ) ; } if ( <ISA_LIT>Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( <ISA_LIT>Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } if ( ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) && isa < MCConstantExpr > ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getImm ( ) ) && cast < MCConstantExpr > ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getImm ( ) ) -> getValue ( ) == <NUM_LIT> ) { delete Operands [ <NUM_LIT> ] ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; } return


<s> case <STR_LIT> : return StringRef ( <STR_LIT> ) ; case <STR_LIT> : return StringRef ( <STR_LIT> ) ; case <STR_LIT> : return StringRef ( <STR_LIT>


<s> SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SDValue Lg2Amt = DAG . getConstant ( lg2 , <STR_LIT> ) ; SDValue SRA = getTargetVShiftNode ( <STR_LIT> , dl , VT , ADD , Lg2Amt , DAG ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override { return &


<s> SDValue <ISA_LIT>TargetLowering :: addTokenForArgument ( SDValue Chain , SelectionDAG & DAG , MachineFrameInfo & MFI , int ClobberedFI ) const { SmallVector < SDValue , <NUM_LIT> > ArgChains ; int64_t FirstByte = MFI . getObjectOffset ( ClobberedFI ) ; int64_t LastByte = FirstByte + MFI . getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ; InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> ,


<s> case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; default : break ; } if ( ! ConvOpc || ! adjustCCMasksForInstr ( MI , Compare , CCUsers ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool uns_p = ( code == ASHIFTRT ) ? false : true ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ; case


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = getPointerTy ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , TM , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( IsTailCall && ! canUseSiblingCall ( ArgCCInfo , ArgLocs ) ) IsTailCall = false ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , PtrVT , true ) , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { SDValue SpillSlot = DAG . CreateStackTemporary ( VA . getValVT ( ) ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; ArgValue = SpillSlot ; } else ArgValue = convertValVTToLocVT ( DAG , DL , VA , ArgValue ) ; if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue Glue ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G ->


<s> int64_t Zero = <NUM_LIT> ; if ( ! mi_match ( ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Zero ) ) || Zero ) return false ; for ( unsigned i = <NUM_LIT> , e = ZeroVec -> getNumOperands ( ) - <NUM_LIT> ; i < e ; ++ i ) { if ( ZeroVec -> getOperand ( i ) . getReg ( ) != ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; } LLT VecTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT EltTy = VecTy . getElementType ( ) ; if ( VecTy . getSizeInBits ( ) != <NUM_LIT> || EltTy . getSizeInBits ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg , MIB ) ; if ( ! Widen ) return false ; ScalarReg = Widen -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg


<s> void <ISA_LIT>InstPrinter :: printAddrModeTBB ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT>


<s> <STR_LIT> CC = parseCondCodeString ( Cond ) ; if ( CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( invertCondCode ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S , getLoc ( ) , getContext (


<s> unsigned OpIdx = RootMaskedIdx >> OpRatioLog2 ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask [ i ] = OpMask [ OpIdx ] ; continue ; } unsigned OpMaskedIdx = OpRatio == <NUM_LIT> ? OpMask [ OpIdx ] : ( OpMask [ OpIdx ] << OpRatioLog2 ) + ( RootMaskedIdx & ( OpRatio - <NUM_LIT> ) ) ; OpMaskedIdx = OpMaskedIdx & ( MaskWidth - <NUM_LIT> ) ; int InputIdx = OpMask [ OpIdx ] / ( int ) OpMask . size ( ) ; assert ( <NUM_LIT> <= OpInputIdx [ InputIdx ] && <STR_LIT> ) ; OpMaskedIdx += OpInputIdx [ InputIdx ] * MaskWidth ; Mask [ i ] = OpMaskedIdx ; } if ( all_of ( Mask , [ ] ( int Idx ) { return Idx == SM_SentinelUndef ; } ) ) return DAG . getUNDEF ( Root . getValueType ( ) ) ; if ( all_of ( Mask , [ ] ( int Idx ) { return Idx < <NUM_LIT> ; } ) ) return getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ; resolveTargetShuffleInputsAndMask ( Ops , Mask ) ; assert ( ! Ops . empty ( ) && <STR_LIT> ) ; HasVariableMask |= isTargetShuffleVariableMask ( Op . getOpcode ( ) ) ; SmallVector < const SDNode * , <NUM_LIT> > CombinedNodes ( SrcNodes . begin ( ) , SrcNodes . end ( ) ) ; CombinedNodes . push_back ( Op . getNode ( ) ) ; if ( Ops . size ( ) < ( MaxRecursionDepth - Depth ) ) { for ( int i = <NUM_LIT> , e = Ops . size ( ) ; i < e ; ++ i ) { bool AllowVar = false ; if ( Ops [ i ] . getNode ( ) -> hasOneUse ( ) || SDNode :: areOnlyUsersOf ( CombinedNodes , Ops [ i ] . getNode ( ) ) ) AllowVar = AllowVariableMask ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Ops , i , Root , Mask , CombinedNodes , Depth + <NUM_LIT> , HasVariableMask , AllowVar , DAG , Subtarget ) ) return Res ; } } if ( SDValue Cst = combine<ISA_LIT>ShufflesConstants ( Ops , Mask , Root , HasVariableMask , DAG , Subtarget ) ) return Cst ; if ( Ops . size ( ) <=


<s> if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> CurBB = BB ; const Function * F = CurDAG -> getMachineFunction ( ) . getFunction ( ) ; OptForSize = F -> hasFnAttr ( Attribute :: OptimizeForSize ) ; DEBUG ( BB -> dump ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) PreprocessForRMW ( ) ; PreprocessForFPConvert ( ) ; DOUT << <STR_LIT> ; Indent = <NUM_LIT> ; SelectRoot ( * CurDAG )


<s> MF . setHasWinCFI ( false ) ; const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME


<s> return genFusedMultiply ( MF , MRI , TII , Root , InsInstrs , IdxMulOpd

, MaddOpc , RC , FMAInstKind :: Accumulator ) ;


<s> for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! CFlags . IsPatchPoint && ! Subtarget . isUsingPCRelativeCalls ( ) ) Ops . push_back ( DAG . getRegister ( Subtarget . getTOCPointerRegister ( ) , RegVT ) ) ; if ( CFlags . IsVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CFlags . CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask


<s> case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT>


<s> if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDValue Chain = CurDAG -> getEntryNode ( ) ; DebugLoc dl = SUBENode -> getDebugLoc ( ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MSub = CurDAG -> getNode ( MultOpc , dl , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , SUBCNode -> getOperand ( <NUM_LIT> ) , SUBENode -> getOperand ( <NUM_LIT> ) ) ; SDValue CopyFromLo = CurDAG -> getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> , MSub ) ; SDValue CopyFromHi = CurDAG -> getCopyFromReg ( CopyFromLo . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , CopyFromLo . getValue ( <NUM_LIT> ) ) ; if ( ! SDValue ( SUBCNode , <NUM_LIT> ) . use_empty ( ) ) CurDAG -> ReplaceAllUsesOfValueWith ( SDValue

( SUBCNode , <NUM_LIT> ) , CopyFromLo ) ;


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1


<s> static SDValue combineCVTP2I_CVTTP2I ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert


<s> return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG .

getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup ( <STR_LIT> )


<s> break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R'


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg


<s> if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT>


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; Is<ISA_LIT>64 = o . Is<ISA_LIT>64 ; switch ( Kind ) { case Token : Tok = o . Tok ; break ; case Immediate : Imm = o


<s> unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm !=


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( MO . getImm ( )


<s> machine_mode memory_vector_mode ( const function_instance & ) const override { return


<s> if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : nullptr ; if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ; int64_t Val1 = cast < ConstantSDNode > ( * K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( * K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; int64_t NegVal = std :: min


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg (

SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . OffsetRegNum ) ) ; if ( ! Memory . OffsetRegNum ) { if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; } else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : case 'f' : case 'e'


<s> m_pEXIDX = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_<ISA_LIT>_EXIDX , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_LINK_ORDER , config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ) ; m_pEXTAB = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC , <NUM_LIT> ) ; m_pAttributes = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , <NUM_LIT> ) ; m_pAttrData = new <ISA_LIT>ELFAttributeData ( ) ; attribute ( ) . registerAttributeData ( * m_pAttrData ) ; if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { ELFFileFormat * file_format = getOutputFormat ( ) ; LDSection & got = file_format -> getGOT ( ) ; m_pGOT = new <ISA_LIT>GOT ( got ) ; LDSection & plt = file_format -> getPLT (


<s> const unsigned MovOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const unsigned SPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( & MBB , DebugLoc ( ) , TII -> get ( MovOpc ) ) , SPReg , false , <NUM_LIT> ) . addReg


<s> rs1 = XEXP ( addr , <NUM_LIT> ) ; rs2 = XEXP ( addr , <NUM_LIT> ) ; if ( ! REG_P ( rs1 ) && GET_CODE ( rs1 ) != SUBREG && ( REG_P ( rs2 ) || GET_CODE ( rs2 ) == SUBREG || ( GET_CODE ( rs2 ) == LO_SUM && GET_CODE ( rs1 ) != LO_SUM ) ) ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; rs2 = XEXP ( addr , <NUM_LIT> ) ; } if ( ( flag_pic == <NUM_LIT> && rs1 == pic_offset_table_rtx && ! REG_P ( rs2 ) && GET_CODE ( rs2 ) != SUBREG && GET_CODE ( rs2 ) != LO_SUM && GET_CODE ( rs2 ) != MEM && ! ( GET_CODE ( rs2 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs2 ) ) && ( ! symbolic_operand ( rs2 , VOIDmode ) || mode == Pmode ) && ( GET_CODE ( rs2 ) != CONST_INT || SMALL_INT ( rs2 ) ) ) || ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && RTX_OK_FOR_OFFSET_P ( rs2 , mode ) ) ) { imm1 = rs2 ; rs2 = NULL ; } else if ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && ( REG_P ( rs2 ) || GET_CODE ( rs2 ) == SUBREG ) ) { if ( mode == TFmode && ! ( TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( mode == TImode ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 , mode ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; if ( mode == TFmode


<s> bool isToken ( ) const { return Kind


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( addIntraChainConstraint ( G , Rd , Ra ) ) addInterChainConstraint ( G , Rd , Ra ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand (


<s> if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> )


<s> bool <ISA_LIT>CallLowering :: isTypeIsValidForThisReturn ( EVT Ty ) const { return Ty . getSizeInBits


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) { OutStreamer . EmitIntValue ( <NUM_LIT> ,


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> (


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; Register Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI == NULL || ! isSignOrZeroExtended ( * SrcMI , SignExt , Depth + <NUM_LIT> ) ) return false ; } else return false ; } return true ; } case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; Register SrcReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg1 ) || ! Register :: isVirtualRegister (


<s> MIRBuilder . getMBB ( ) . addLiveIn (


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallingConv = <STR_LIT> ; return SpecialCallingConv


<s> bool isMSRPState ( ) const { if ( ! isSysReg ( ) ) return false ; bool


<s> MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) sinkMBB -> addSuccessor ( * i ) ; while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB =


<s> const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( )


<s> if ( MadeChange ) return MadeChange ; int Limit = CTRLoopLimit ; if ( Limit >= <NUM_LIT> ) { if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( TT , * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = <NUM_LIT> ; const SCEV * ExitCount = <NUM_LIT> ; BranchInst * CountedExitBranch = <NUM_LIT> ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit

( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ;


<s> BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1


<s> -- J ; if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) { slot -> setDesc ( Subtarget -> getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; return J ; } } if ( slot -> isCall ( ) ) insertCallDefsUses ( slot , RegDefs , RegUses ) ; else insertDefsUses ( slot , RegDefs , RegUses ) ; bool done = false ; MachineBasicBlock :: iterator I = slot ; while ( ! done ) { done = ( I == MBB . begin ( ) ) ; if ( ! done ) -- I ; if ( I -> isDebugInstr


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( EmitCPLoad ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } else if ( EmitCPLoad ) { SmallVector < MCInst , <NUM_LIT> > MCInsts ; MCInstLowering . LowerCPLOAD ( MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I )


<s> case <STR_LIT> : return instCombineSVEDupX ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorFAdd ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorBinOp ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; case <STR_LIT> : return instCombineSVETupleGet ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEZip ( IC , II ) ; case


<s> argsp -> regs = ( ( targetm . calls . must_pass_in_stack ( mode , type ) || ( arg_size > <NUM_LIT> && ! TARGET_LIBFUNC && ! argsp -> lib ) ) ? ( MMIX_MAX_ARGS_IN_REGS ) +

<NUM_LIT> : argsp -> regs + ( <NUM_LIT> + arg_size ) / <NUM_LIT> ) ;


<s> bool hasV6Ops ( ) const { return <ISA_LIT>ArchVersion >=


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg ,


<s> bool isCallingConvWin64 ( CallingConv ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isDereferenceableInvariantLoad ( AA ) ) { Register BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) { if ( ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) .


<s> const unsigned MaxPossiblePad = std :: min ( <NUM_LIT> - OldSize , RemainingSize ) ; const unsigned PrefixBytesToAdd = std :: min ( MaxPossiblePad , getRemainingPrefixSize ( RF . getInst ( ) , STI , Emitter ) ) ; if ( PrefixBytesToAdd == <NUM_LIT> ) return false ; const uint8_t Prefix = determinePaddingPrefix ( RF . getInst ( ) ) ; SmallString < <NUM_LIT> > Code ; Code . append ( PrefixBytesToAdd , Prefix ) ; Code . append ( RF . getContents ( ) . begin ( )


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , bool Fast , bool DumpAsm , MachineCodeEmitter & MCE ) { if ( DefRelocModel == Reloc :: Default ) setRelocationModel ( Reloc :: Static ) ; PM . add ( create<ISA_LIT>CodeEmitterPass ( * this , MCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor &&


<s> MemOpQueueEntry ( int o , int p , MachineBasicBlock :: iterator i ) : Offset ( o ) , Position ( p )


<s> PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char


<s> static bool isLegalMaskCompare ( SDNode * N , const <ISA_LIT>Subtarget * Subtarget ) { unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand (


<s> REG_NOTES ( par ) = dwarf ; RTX_FRAME_RELATED_P ( par ) = <NUM_LIT> ; } i ++ ; } tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( ! return_in_pc ) { arm_add_cfa_adjust_cfa_note ( tmp , UNITS_PER_WORD * i , stack_pointer_rtx , stack_pointer_rtx ) ; } dwarf = NULL_RTX ; if ( ( ( num_regs % <NUM_LIT> ) == <NUM_LIT> && ! return_in_pc ) || ( ( num_regs % <NUM_LIT> ) == <NUM_LIT> && return_in_pc ) ) { for ( ; ( saved_regs_mask & ( <NUM_LIT> << j ) ) == <NUM_LIT> ; j ++ ) ; tmp1 = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( tmp1 , get_frame_alias_set ( ) ) ; reg = gen_rtx_REG ( SImode , j ) ; tmp = gen_rtx_SET ( reg , tmp1 ) ; RTX_FRAME_RELATED_P ( tmp ) =


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getThisReturnPreservedMask


<s> bool <ISA_LIT>AIXAsmPrinter :: doFinalization ( Module & M ) { for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return <ISA_LIT>AsmPrinter :: doFinalization ( M


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm


<s> return get_hard_reg_initial_val ( word_mode ,


<s> MVT VT = Op . getSimpleValueType ( ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned SHDOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( SHDOp , DL , VT , Op0 , Op1


<s> const MCConstantExpr * ConstExp = nullptr ; if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Op . getExpr ( ) ) ) { RefExp = cast < MCSymbolRefExpr > ( BinExpr -> getLHS ( ) ) ; ConstExp = cast < MCConstantExpr > ( BinExpr -> getRHS ( ) ) ; } else RefExp = cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; O << RefExp -> getSymbol ( ) . getName ( ) ; if ( RefExp -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ) O << '@' << MCSymbolRefExpr :: getVariantKindName ( RefExp -> getKind ( ) ) ; O << '(' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; O <<


<s> for ( ; mode != VOIDmode ; mode = GET_MODE_WIDER_MODE ( mode ) ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) return mode ; gcc_unreachable ( ) ; } } return mode


<s> mem = gen_frame_mem ( mode , addr ) ; align = MIN ( GET_MODE_ALIGNMENT ( mode ) , align ) ; gcc_assert ( ! ( cfa_offset & ( align / BITS_PER_UNIT - <NUM_LIT> ) ) ) ; set_mem_align ( mem , align ) ; insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base == stack_pointer_rtx && m -> fs . sp_realigned && cfa_offset >= m -> fs . sp_realigned_offset ) { gcc_checking_assert ( stack_realign_fp ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m ->


<s> SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; } if ( Res . getNode ( ) ) Results . push_back


<s> void <ISA_LIT>InstPrinter :: printPrefetchOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned prfop = MI -> getOperand ( OpNum ) . getImm ( ) ; bool


<s> HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode

, & count , NULL , false ) ) return false ;


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) { Reset (


<s> if ( is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer )


<s> if ( ! CSel0 -> hasOneUse ( ) || ! CSel1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( ! isNullConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isNullConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Cmp0 = CSel0 . getOperand ( <NUM_LIT> ) ; SDValue Cmp1 = CSel1 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC0 = ( <STR_LIT> ) CSel0 . getConstantOperandVal ( <NUM_LIT> ) ; <STR_LIT> CC1 = ( <STR_LIT> ) CSel1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ! Cmp0 -> hasOneUse ( ) || ! Cmp1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( Cmp1 . getOpcode ( ) != <STR_LIT> && Cmp0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Cmp0 , Cmp1 ) ; std :: swap ( CC0 , CC1 ) ; } if ( Cmp1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue CCmp ; if ( N -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> InvCC0 = <STR_LIT> ( CC0 ) ; SDValue Condition = DAG . getConstant ( InvCC0 , DL , MVT_CC ) ; unsigned NZCV = <STR_LIT> ( CC1 ) ; SDValue NZCVOp = DAG . getConstant ( NZCV , DL , <STR_LIT> ) ; CCmp = DAG . getNode ( <STR_LIT> , DL , MVT_CC , Cmp1 . getOperand ( <NUM_LIT> ) , Cmp1 . getOperand ( <NUM_LIT> ) , NZCVOp , Condition , Cmp0 ) ; } else { SDLoc DL (


<s> if ( CondReg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; unsigned CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned ResultReg = createResultReg ( RC ) ; unsigned MovCCOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op1Reg ) . addReg ( Op2Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; UpdateValueMap ( I , ResultReg


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 ,

InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ;


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insertAfter ( MachineBasicBlock :: iterator ( MI


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( ( Instruction :: BinaryOps ) Opcode , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * Product = BinaryOperator :: Create ( ( Instruction :: BinaryOps ) Opcode , IncrementPerRound , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * NewIncrement = BinaryOperator :: Create ( Instruction :: Add , Phi , Product , <STR_LIT> , cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement ) -> back ( ) ) . getPrevNode ( ) ) ; Phi -> addIncoming ( StartIndex , Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; Phi -> addIncoming ( NewIncrement , Phi -> getIncomingBlock ( LoopIncrement ) ) ; Phi -> removeIncomingValue ( ( unsigned ) <NUM_LIT> ) ; Phi -> removeIncomingValue ( (


<s> void <ISA_LIT>PostRASchedStrategy :: enterMBB ( MachineBasicBlock * MBB ) { PostGenericScheduler :: enterMBB ( MBB


<s> Value * <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return

getDefaultSafeStackPointerLocation ( IRB , false ) ;


<s> void <ISA_LIT>InstPrinter :: printAM3PostIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; O << '#' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm


<s> return ( vector unsigned short ) __builtin_altivec_vminuh ( ( vector signed short ) a1 , ( vector


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; } BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loopMBB ) ; MI . eraseFromParent ( ) ; return exitMBB


<s> TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( )


<s> case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; } return true


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10Lsl2 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT> )


<s> static void do_isel ( rtx dest , rtx cmp , rtx src_t , rtx src_f , rtx cr ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_cc_di ( dest , cmp , src_t , src_f , cr ) ) ; else emit_insn ( gen_isel_cc_si ( dest , cmp , src_t ,


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; uint64_t Features = STI . getFeatureBits ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; Pic = ( MCA . getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) ? true : false ; unsigned EFlags = <NUM_LIT> ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; if ( T . isArch64Bit ( ) ) { if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ABI2 ; else if ( Features


<s> if ( F -> hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return


<s> if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UserMBB ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . add ( predOps ( <STR_LIT> ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( MF , UserMBB , BBInfo [ UserMBB -> getNumber ( ) ] ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex


<s> const LegalizerInfo * <ISA_LIT>Subtarget ::


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE ->


<s> SDValue SrcReg = Op . getOperand ( <NUM_LIT> ) ; SDValue ZeroUndef = LowerCTTZ_ZERO_UNDEF ( Op , DAG ) ; SDValue CC = DAG . getCondCode ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SrcReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG .

getConstant ( VT . getSizeInBits ( ) , dl , <STR_LIT> ) , ZeroUndef , CC ) ;


<s> int loadOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; break ; } default : { storeInst -> dump ( ) ; errs ( ) << <STR_LIT> ; } } assert ( loadOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ; MIload -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < storeInst -> getNumOperands ( )


<s> dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' << <STR_LIT> ; if ( ES ) dbgs ( ) << ES ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( MCSym ) dbgs ( ) << MCSym ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << JT << <STR_LIT> << Alignment .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Align MemAlign = getKnownAlignment ( II . getArgOperand ( <NUM_LIT> ) , IC . getDataLayout ( ) , & II , & IC . getAssumptionCache ( ) , & IC . getDominatorTree ( ) ) ; unsigned AlignArg = II . arg_size ( ) - <NUM_LIT> ; Value * AlignArgOp = II . getArgOperand ( AlignArg ) ; MaybeAlign Align = cast < ConstantInt > ( AlignArgOp ) -> getMaybeAlignValue ( ) ; if ( Align && * Align < MemAlign ) { return IC . replaceOperand ( II , AlignArg , ConstantInt :: get ( Type :: getInt32Ty ( II . getContext ( ) ) , MemAlign . value ( ) , false ) ) ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } Constant * XorMask ; if ( match ( Arg , m_Xor ( PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) , PatternMatch :: m_Constant ( XorMask ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { if ( auto * CI = dyn_cast < ConstantInt > ( XorMask ) ) { if ( CI -> getValue ( ) . trunc ( <NUM_LIT> ) . isAllOnes ( ) ) { auto TrueVector = IC . Builder . CreateVectorSplat ( cast < FixedVectorType > ( II . getType ( ) ) -> getNumElements ( ) , IC . Builder . getTrue ( ) ) ; return BinaryOperator :: Create ( Instruction :: Xor , ArgArg , TrueVector ) ; } } } KnownBits ScalarKnown ( <NUM_LIT> ) ; if ( IC . SimplifyDemandedBits ( & II , <NUM_LIT> , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) , ScalarKnown , <NUM_LIT> ) ) { return & II ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } if ( ! II . getMetadata ( LLVMContext :: MD_range ) ) { Type * IntTy32 = Type :: getInt32Ty ( II . getContext ( ) ) ; Metadata * M [


<s> } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } return constrainSelectedInstRegOperands ( I , TII ,


<s> void SetFrameRegister ( unsigned RegNo ) { FrameReg =


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned ATReg = <STR_LIT> ; unsigned FinalDstReg = <STR_LIT> ; unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool Is32Bit = isInt < <NUM_LIT> > ( ImmValue ) || ( ! isGP64bit ( ) && isUInt < <NUM_LIT> > ( ImmValue ) ) ; unsigned FinalOpcode = Inst . getOpcode ( ) ; if ( DstReg == SrcReg ) { ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; FinalDstReg = DstReg ; DstReg = ATReg ; } if ( ! loadImmediate ( ImmValue , DstReg , <STR_LIT> , Is32Bit , false


<s> for ( auto & Use : MI . uses ( ) ) { if ( Use . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Use . getReg ( ) ) ) { MachineInstr * DefInst = MRI -> getVRegDef ( Use . getReg ( ) ) ; if ( DefInst -> isPHI ( ) && DefInst -> getParent ( ) == MI . getParent ( ) ) { LLVM_DEBUG ( dbgs ( )


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo , Address


<s> if ( single_set ( insn ) && nds32_symbol_load_store_p ( insn ) ) { rtx pattern = PATTERN ( insn ) ; rtx mem ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; if ( GET_CODE ( SET_SRC ( pattern ) ) == REG ) mem = SET_DEST ( pattern ) ; else mem = SET_SRC ( pattern ) ; if ( GET_CODE ( mem ) == MEM ) symbol_count


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> void getAnalysisUsage ( AnalysisUsage & AU


<s> bool function_resolver :: require_matching_integer_scalar_type ( unsigned int argno , unsigned int first_argno , type_suffix_index expected_type ) { type_suffix_index actual_type = infer_integer_scalar_type ( argno ) ; if ( actual_type == NUM_TYPE_SUFFIXES ) return false ; if ( actual_type == expected_type )


<s> return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] < <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] >= <NUM_LIT> ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } if ( ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] < <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] >= <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 , DAG . getConstant ( SHUFPDMask ,


<s> NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; } return


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { RM = TT . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; } X -> initMCCodeGenInfo ( RM , CM , OL ) ; return


<s> } if ( ! TARGET_SVE ) for ( i = P0_REGNUM ; i <= P15_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } if ( aarch64_track_speculation ) { fixed_regs [ SPECULATION_TRACKER_REGNUM ] = <NUM_LIT> ; call_used_regs [ SPECULATION_TRACKER_REGNUM ] = <NUM_LIT> ; fixed_regs [ SPECULATION_SCRATCH_REGNUM ] = <NUM_LIT>


<s> mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 ,


<s> Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset ( ) ; if ( ! <ISA_LIT>EmitStore ( ArgVT , Arg , Addr ) ) return false ; } } return


<s> MCELFStreamer :: EmitBytes ( Data , AddrSpace


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>elTarget (


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFIEpilogEnd ( ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; InEpilogCFI = false ; MCSymbol * Label = S . emitCFILabel ( ) ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT>


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> if ( isParsingInlineAsm ( ) ) if ( IdentifyIntelInlineAsmOperator ( Tok . getString ( ) ) == IOK_OFFSET ) return ParseIntelOffsetOfOperator ( ) ; unsigned Size ; if ( ParseIntelMemoryOperandSize ( Size ) ) return nullptr ; bool PtrInOperand = bool ( Size ) ; Start = Tok . getLoc ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start ) ; unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) return ! PtrInOperand ? <STR_LIT> ( RegNo , Start , End ) : ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) return <STR_LIT> ( Disp , Start , End ) ; StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale (


<s> bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < AllCRLogicalOps . size ( ) ; i ++ ) Changed |= handleCROp ( AllCRLogicalOps


<s> StringRef getPassName ( ) const override { return TLSCLEANUP_PASS_NAME


<s> arm_simd_polyTI_type_node = build_distinct_type_copy ( unsigned_intTI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyTI_type_node , <STR_LIT> ) ; arm_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; arm_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; arm_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype


<s> static inline unsigned getNBit ( uint32_t insn ) { return ( insn >> <STR_LIT> )


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this


<s> SelectionDAGISel :: runOnFunction ( Fn ) ; InsertVRSaveCode ( Fn )


<s> Entry . Node = Arg ; Entry . Ty = ArgTy ; if ( ArgTy -> isFP128Ty ( ) ) { int FI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getStore ( Chain , DL , Entry . Node , FIPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Entry . Node = FIPtr ; Entry . Ty = PointerType :: getUnqual ( ArgTy ) ; } Args . push_back ( Entry ) ; return


<s> if ( flags & MASK_FMAF ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FPU ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_HARD_QUAD ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_POPC ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_PTR64 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_STACK_BIAS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_UNALIGNED_DOUBLES ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_V8PLUS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS2 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS3 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_CBCOND ) fprintf ( stderr ,


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! is_a < scalar_int_mode > ( GET_MODE ( op ) , & mode ) ) return op ; if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , <NUM_LIT> ) == const0_rtx && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == MULT && aarch64_is_extend_from_extract ( mode , XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( op , <NUM_LIT> ) ) ) return XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> )

) ) , INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) != <NUM_LIT> ) return XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( InVT . isScalableVector ( ) ) { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementCount ( ) != ( InVT . getVectorElementCount ( ) * <NUM_LIT> ) ) return SDValue ( ) ; EVT WideVT ; SDValue ExtVec


<s> static bool rx_narrow_volatile_bitfield ( void ) { return true


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getValueType ( ) . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } SDValue FIPtr = DAG . CreateStackTemporary ( <STR_LIT>


, __m512h __B , int __C , const int __D ) {


<s> void ELF<ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> )


<s> static int aapcs_select_call_coproc ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ) { int i ; for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] .

is_call_candidate ( pcum , mode , type ) ) return i ;


<s> unsigned int cost , alt_cost ; cost = mips_build_shift ( codes , value ) ; alt_cost = mips_build_lower ( alt_codes , value ) ; if ( alt_cost < cost ) { memcpy ( codes , alt_codes , alt_cost * sizeof ( codes [ <NUM_LIT> ] ) ) ; cost = alt_cost ; } return cost


<s> if ( VECTOR_MODE_P ( mode ) ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_ADVSIMD ) { if ( GET_CODE ( op0 ) == VEC_DUPLICATE ) op0 = XEXP ( op0 , <NUM_LIT> ) ; else if ( GET_CODE ( op1 ) == VEC_DUPLICATE ) op1 = XEXP ( op1 , <NUM_LIT> ) ; } cost += rtx_cost ( op0 , mode , MULT , <NUM_LIT> , speed ) ; cost += rtx_cost ( op1 , mode , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( GET_CODE ( x ) == MULT ) cost += extra_cost -> vect . mult ; else cost += extra_cost -> vect . alu ; } return cost ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( aarch64_shift_p ( GET_CODE ( x ) ) || ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > <NUM_LIT> ) ) { bool is_extend = GET_CODE ( op0 ) == ZERO_EXTEND || GET_CODE ( op0 ) == SIGN_EXTEND ; if ( speed ) { if ( compound_p ) { if ( aarch64_cheap_mult_shift_p ( x ) ) ; else if ( REG_P ( op1 ) ) cost += extra_cost -> alu . arith_shift_reg ; else if ( is_extend ) cost += extra_cost -> alu . extend_arith ; else cost += extra_cost -> alu . arith_shift ; } else cost += extra_cost -> alu . shift ; } if ( is_extend ) op0 = aarch64_strip_extend ( op0 , true ) ; cost += rtx_cost ( op0 , VOIDmode , code , <NUM_LIT> , speed ) ; return cost ; } if ( GET_CODE ( op0 ) == NEG ) { op0 = XEXP ( op0 , <NUM_LIT> ) ; compound_p = true ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , VOIDmode , MULT , <NUM_LIT> , speed ) ; cost += rtx_cost ( XEXP ( op1 , <NUM_LIT> ) , VOIDmode , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( compound_p ) cost += extra_cost -> mult [ <NUM_LIT>


<s> if ( I -> isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) == <STR_LIT> ) { BBI . PostAlign = <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printPSBHintOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned psbhintop = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( psbhintop , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name ; else O << '#' << formatImm ( psbhintop


<s> if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [