<s> inform ( DECL_SOURCE_LOCATION ( global_regs_decl [ <NUM_LIT> ] ) , <STR_LIT> , global_regs_decl [ <NUM_LIT> ] ) ; } allocate = info -> total_size ; if ( allocate > ( unsigned HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) { sorry ( <STR_LIT> ) ; return ; } if ( morestack_ref == NULL_RTX ) { morestack_ref = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( morestack_ref ) |= ( SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_FUNCTION ) ; } r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; r1 = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_load_split_stack_limit ( r0 ) ) ; alloc_hi = ( - allocate + <NUM_LIT> ) & ~ <NUM_LIT> ; alloc_lo = - allocate - alloc_hi ; if ( alloc_hi != <NUM_LIT> ) { emit_insn ( gen_add3_const ( r12 , r1 , alloc_hi ) ) ; if ( alloc_lo != <NUM_LIT> ) emit_insn ( gen_add3_const ( r12 , r12 , alloc_lo ) ) ; else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 ,


<s> return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && isa


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( Reserved<ISA_LIT>Regs ) ; ++ I ) { Reserved . set ( Reserved<ISA_LIT>Regs [ I ] ) ; } return Reserved


<s> SDLoc dl ( Op ) ; if ( IsStrict ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , SrcVal } ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , { Op . getValueType ( ) , <STR_LIT> } , { Ext . getValue ( <NUM_LIT> ) , Ext . getValue ( <NUM_LIT> ) } ) ; } return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SrcVal ) ) ; } if ( SrcVal . getValueType


<s> StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) return parseSysAlias ( Head , NameLoc , Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; unsigned CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; const MCExpr * CCExpr = MCConstantExpr :: Create (


<s> if ( AllowSP ) { RC = Opc != <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; } else { RC = Opc != <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef (


<s> initializeMVEGatherScatterLoweringPass ( * PassRegistry ::


<s> if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel ::


<s> if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrModeImm12Operand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder )


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . is256BitVector ( ) && SubVecVT . is128BitVector ( ) ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( SubVec2 . getNode ( ) && SubVec2 . getOpcode ( ) == <STR_LIT> ) SubVec2 = SubVec2 . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( SubVec2 ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2


<s> bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> unsigned JTI = MO1 . getIndex ( ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel ( JTI ) ; OutStreamer -> emitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI


<s> case MEK_GOT_OFST : case MEK_GOT_PAGE : case MEK_GPREL : case MEK_HI : case MEK_HIGHER : case MEK_HIGHEST : case MEK_LO : case MEK_NEG : case MEK_PCREL_HI16 : case MEK_PCREL_LO16 : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_DTPREL_HI : case


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & ) { MCRegisterInfo * X =


<s> return __builtin_altivec_abss_v4si (


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( isByVal ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack

( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> Nodes [ Graph -> nodes_size ( ) ] = Graph -> edges_size ( ) ; for ( const auto & E : Graph -> edges ( ) ) { Edges [ Graph -> getEdgeIndex ( E ) ] = Graph -> getNodeIndex ( * E . getDest ( ) ) ; EdgeValues [ Graph -> getEdgeIndex ( E ) ] = E . getValue ( ) ; } OptimizeCut ( Nodes . get ( ) , Graph -> nodes_size ( ) , Edges . get ( ) , EdgeValues . get ( ) , EdgeCuts . get ( ) , Graph -> edges_size ( ) ) ; for ( int I = <NUM_LIT> ; I < Graph -> edges_size ( ) ; ++ I ) if ( EdgeCuts [ I ] ) CutEdges . set ( I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf


<s> StaticDtorSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE |

ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> break ; } MatchAny &= isUndefInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; MatchZero &= isUndefOrZeroInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; } if ( MatchAny || MatchZero ) { assert ( MatchZero && <STR_LIT> ) ; unsigned SrcSize = std :: max ( <NUM_LIT> , NumDstElts * MaskEltSize ) ; MVT ScalarTy = MaskVT . isInteger ( ) ? MaskVT . getScalarType ( ) : <STR_LIT> ( MaskEltSize ) ; SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( MatchAny ? <STR_LIT> : <STR_LIT> ) ; if ( SrcVT . getVectorNumElements ( ) != NumDstElts ) Shuffle = getOpcode_EXTEND_VECTOR_INREG ( Shuffle ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasFP16 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; if ( MaskEltSize == <NUM_LIT> ) SrcVT = DstVT = MaskVT . changeVectorElementType ( <STR_LIT> ) ; else SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return


<s> if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( INSN_CODE ( insn ) == CODE_FOR_alloc ) { rtx dest = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int dest_regno = REGNO ( dest ) ; if ( dest_regno == current_frame_info . r [ reg_save_ar_pfs ] ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number ( dest_regno ) ) ; } else { if ( current_frame_info . total_size == <NUM_LIT> && ! frame_pointer_needed ) process_epilogue ( out_file , insn , unwind , frame ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> ) ; } return ; } handled_one = false ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) switch ( REG_NOTE_KIND ( note ) ) { case REG_CFA_ADJUST_CFA : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_adjust_cfa ( out_file , pat , insn , unwind , frame ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> APInt MulC ; if ( ! <STR_LIT> ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; unsigned EltSizeInBits = VT .


<s> bool <ISA_LIT>ConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return


<s> unsigned <ISA_LIT>AsmParser :: parseCondCodeString ( StringRef Cond ) { unsigned CC = StringSwitch < unsigned > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return CC


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>64 ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>64 (


<s> break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg


<s> unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT>


<s> target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode ,


<s> static bool CC_<ISA_LIT>O32_FP32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { llvm_unreachable ( <STR_LIT>


<s> if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains =

Subtarget . hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>PreAMXConfigPass ( ) { return new <ISA_LIT>PreAMXConfigPass


<s> if ( type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX || type == TYPE_LOAD_UX || type == TYPE_STORE_UX || type == TYPE_MFCR ) return true ; } return


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : bool IsPCRel = ( MO . getTargetFlags ( ) & ~ access ) == <STR_LIT> ; RefKind = IsPCRel ? MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_PCREL : MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_TPREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_PCREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ; const MachineInstr * MI = MO . getParent ( ) ; const MachineFunction * MF = MI -> getMF ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; unsigned MIOpcode = MI -> getOpcode ( ) ; assert ( ( Subtarget -> isUsingPCRelativeCalls ( ) || MIOpcode != <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget -> isUsingPCRelativeCalls ( ) ) { if ( MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> ) { RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent (


<s> if ( mep_leaf_registers [ <NUM_LIT> ] != enable ) for ( i = <NUM_LIT> ; i

< FIRST_PSEUDO_REGISTER ; i ++ ) mep_leaf_registers [ i ] = enable ;


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT>


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned Opc ; if ( ! Subtarget -> hasAVX ( ) ) { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> ; i < numArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i + <NUM_LIT> ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB


<s> case AsmToken :: PercentHi : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , E , Ctx ) ; case AsmToken :: PercentHigher : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHER , E , Ctx ) ; case AsmToken :: PercentHighest : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHEST , E , Ctx ) ; case AsmToken :: PercentLo : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , E , Ctx ) ; case AsmToken :: PercentNeg : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_NEG , E , Ctx ) ; case AsmToken :: PercentPcrel_Hi : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_PCREL_HI16 , E , Ctx ) ; case AsmToken :: PercentPcrel_Lo : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_PCREL_LO16 , E , Ctx ) ; case AsmToken :: PercentTlsgd : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_TLSGD , E , Ctx ) ; case AsmToken :: PercentTlsldm : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_TLSLDM , E , Ctx ) ; case AsmToken :: PercentTprel_Hi : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_TPREL_HI , E , Ctx


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch


<s> bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X =


<s> int skip ; while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return


<s> uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> if ( TREE_CODE ( * node ) != FUNCTION_TYPE && TREE_CODE ( * node ) != FIELD_DECL && TREE_CODE ( * node ) != TYPE_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs


<s> for ( unsigned i = <NUM_LIT> ; i < Inst . getNumOperands ( ) ; ++ i ) if ( isa < ScalableVectorType > ( Inst . getOperand ( i ) -> getType (


<s> RS6000_OUTPUT_BASENAME ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED , size , align2 ) ; fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ; putc ( '\n' , stream )


<s> Val &= <NUM_LIT> ; Val |= <NUM_LIT> ; } return Val


<s> return ( ( qword ) ( vec_add ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int ( b ) )


<s> case V4HImode : t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_2 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_3 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , IOR , t_2 , t_3 , t_2 , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_2 , sel


<s> if ( ! Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) || ! ( NextIsVL || NextIsHash ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; if ( NextIsVL ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( NextIsHash ) { Parser . Lex ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * ImmVal ; if ( ! Parser . parseExpression ( ImmVal ) ) if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( MCE -> getValue ( ) , getContext ( ) ) , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } } return Error ( getLoc (


<s> OS << <STR_LIT> << ShiftExtend . ShiftType << <STR_LIT> << ShiftExtend . Amount << <STR_LIT> ; break ; case k_SysReg : { StringRef Name ( SysReg . Data , SysReg . Length ) ; OS << <STR_LIT> << Name << '>' ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> std :: make_unique < PostGenericScheduler > ( C ) , true ) ; if ( ST . hasFusion ( ) )

DAG -> addMutation ( createPowerPCMacroFusionDAGMutation ( ) ) ;


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_TYPE ) ; } if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Real ) || getLexer ( ) . is ( AsmToken :: Minus ) ) { const MCExpr * Val ; if ( ! getParser ( ) . parseExpression ( Val , End ) ) { return <STR_LIT> ( Val , Start , End


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ? i : <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i *


<s> dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> vexXopType == TYPE_VEX_3B ) insn -> vvvv = vvvvFromVEX3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vexXopType == TYPE_VEX_2B ) insn -> vvvv = vvvvFromVEX2of2


<s> void <ISA_LIT>InstPrinter :: printMveSaturateOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo


<s> passed_in_gprs = false ; if ( cum -> vregno + n_elts > ALTIVEC_ARG_MAX_REG + <NUM_LIT> ) ret = ( ALTIVEC_ARG_MAX_REG + <NUM_LIT> - cum -> vregno ) * <NUM_LIT> ; } if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( mode , type ) ) return <NUM_LIT> ; align_words = rs6000_parm_start ( mode , type , cum -> words ) ; if ( USE_FP_FOR_ARG_P ( cum , elt_mode ) ) { unsigned long n_fpreg = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; if ( type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 )

&& TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) return <NUM_LIT> ;


<s> bool IsGPRC = RC -> hasSuperClassEq ( & <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addImm ( Imm ) ; else if ( Lo ) { Register TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT>

: <STR_LIT> ) , ResultReg ) . addImm ( Hi ) ;


<s> return ( __m256 ) __builtin_ia32_broadcastf32x4_256_mask ( ( __v4sf ) __A ,


<s> case Instruction :: FMul : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : case Instruction :: ICmp : case Instruction :: FCmp : return false ; case Instruction


<s> int Num = MatchCoprocessorOperandName ( Tok . getString ( ) . lower ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ( hasV7Ops ( ) || hasV8Ops ( ) ) && (

Num == <NUM_LIT> || Num == <NUM_LIT> ) ) return MatchOperand_NoMatch ;


<s> static DecodeStatus DecodeDoubleRegStore ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ( Rt & <NUM_LIT> ) || Rt == <NUM_LIT> || Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) return MCDisassembler


<s> if ( Modifier == MCSymbolRefExpr :: VK_None && ! IsPCRel ) return RT64_32S ; return RT64_32 ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_32 ; case FK_Data_4 : case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RT64_32 ; case FK_PCRel_2 : case


<s> NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . addOperand ( Dst ) . addOperand ( Src1 ) . addOperand ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI -> getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . addOperand ( Dst ) . addOperand ( SrcR ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( NewMI ) { MFI -> erase ( I


<s> if ( ! isLoadStoreTypeLegal ( I -> getType ( ) , VT ) || cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; Address Addr


<s> CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : <NUM_LIT> ; AssemblerDialect =


<s> const MCRegisterClass & XRegClass = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; bool isXReg = XRegClass . contains ( FirstReg ) , isWReg = WRegClass . contains ( FirstReg ) ; if ( ! isXReg && ! isWReg ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned FirstEncoding = RI -> getEncodingValue ( FirstReg ) ; if ( FirstEncoding & <NUM_LIT> ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc M = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( M , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; SMLoc E = getLoc ( ) ; int SecondReg = tryParseRegister ( ) ; if ( SecondReg == - <NUM_LIT> ) { return MatchOperand_ParseFail


<s> if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; } } return MadeChange


<s> return __builtin_mve_vidupq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a


<s> vpmin_f32 ( float32x2_t a , float32x2_t b ) { return __builtin_aarch64_smin_nanpv2sf ( a ,


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC )


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , const SMLoc & Loc ) override { EmitDataMappingSymbol ( )


<s> if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; Cost = vectorCostAdjustment ( Cost , Opcode , Src , nullptr ) ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || * Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ! ST -> hasP8Vector ( ) && IsAltivecType ) && * Alignment >= LT .

second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ;


<s> ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy


<s> switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / <NUM_LIT> : <NUM_LIT> ) ; Info . vol = false


<s> unsigned int nbits = SBITMAP_SIZE ( bmp ) ; if ( start == nbits ) return start ; gcc_assert ( start


<s> Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } if ( ! II . getMetadata ( LLVMContext :: MD_range ) ) { Type * IntTy32 = Type :: getInt32Ty ( II . getContext ( ) ) ; Metadata * M [ ] = { ConstantAsMetadata :: get ( ConstantInt :: get ( IntTy32 , <NUM_LIT> ) ) , ConstantAsMetadata :: get ( ConstantInt :: get ( IntTy32 , <NUM_LIT> ) ) } ; II . setMetadata ( LLVMContext :: MD_range , MDNode :: get ( II . getContext ( ) , M ) ) ; return & II ; } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned CarryOp = ( II . getIntrinsicID ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; assert ( II . getArgOperand ( CarryOp ) -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; KnownBits CarryKnown ( <NUM_LIT> ) ; if ( IC . SimplifyDemandedBits ( & II , CarryOp , APInt :: getOneBitSet ( <NUM_LIT> , <NUM_LIT> ) , CarryKnown ) ) { return & II ; } break ; } case <STR_LIT> : { Instruction * I = cast < Instruction > ( & II ) ; if ( I -> hasOneUse ( ) ) { auto * User = cast < Instruction > ( * I -> user_begin ( ) ) ; Value * OpZ ; if ( match ( User , m_c_Add ( m_Specific ( I ) , m_Value ( OpZ ) ) ) && match ( I -> getOperand ( <NUM_LIT> ) , m_Zero ( ) ) ) { Value * OpX = I -> getOperand ( <NUM_LIT> ) ; Value * OpY = I -> getOperand ( <NUM_LIT> ) ; Type * OpTy = OpX -> getType ( ) ; IC . Builder . SetInsertPoint ( User ) ; Value * V = IC . Builder . CreateIntrinsic ( <STR_LIT> , { OpTy } , { I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) , OpZ , OpX , OpY } ) ; IC . replaceInstUsesWith ( *


<s> Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemOffset


<s> bool isCheapToSpeculateCttz ( ) const


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; SDLoc DL ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF , DAG ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys ,


<s> void EmitARM64WinCFISaveRegPX ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT> <<


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc DL (


<s> unsigned Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm8 = MO1 . getImm ( ) ; return ( Reg << <NUM_LIT> )


<s> ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT>


<s> return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID .


<s> if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case CHAR_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE : return hfa_element_mode ( TREE_TYPE ( type


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; <STR_LIT> FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind


<s> default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr ::


<s> __attribute__ ( ( __always_inline__ ) ) vreinterpretq_f64_s8 (


<s> if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize


<s> void <ISA_LIT>64GOT :: reserveHeader ( ) { createEntry ( <NUM_LIT> ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { if ( MI -> getOpcode (


<s> output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file


<s> bool isIncomingArgumentHandler ( ) const override { return true


<s> __builtin_altivec_dstst ( ( void * ) a1


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState (


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options ) , STI ( sti ) ,


<s> return __builtin_mve_vcmpeqq_m_n_fv8hf ( __a ,


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ] && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT ,


<s> return getTargetMachine ( ) . isPositionIndependent ( ) ||


<s> return ( __m256i ) __builtin_ia32_expandloadqi256_mask ( ( const __v32qi * ) __C , (


<s> I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction

:: createGnuArgsSize ( nullptr , Amount ) ) ;


<s> inline bool AreGprs64bit ( ) const { return IsN32 ( ) ||


<s> rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < <NUM_LIT> ) { error ( <STR_LIT>


<s> if ( CPU . empty ( ) && TT . isArm64e ( ) ) return <STR_LIT> ; return


<s> if ( align > max_common_align ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT , name , max_common_align / BITS_PER_UNIT ) ; align = max_common_align ; } bss_section ( ) ; assemble_name ( stream


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering


<s> bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { <NUM_LIT> } ; neon_builtin_datum * d = & neon_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum arm_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ arg_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode


<s> } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( MAI -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr , OutContext ) ; } Expr = MCBinaryExpr :: CreateSub ( Expr , PCRelExpr


<s> } bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer == '8' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '7' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'e' && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 's' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; }


<s> <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugInstr ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( ( NCC ^ CC ) & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; MIB . addImm ( Mask


<s> EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> &&


<s> if ( PerformShift ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand ::


<s> unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg


<s> if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; } else { EarliestI = std :: prev ( EarliestI ) ; } for ( MachineInstr * MI : Cand . Instrs ) MBB . erase ( MI ) ; if ( EarliestAtBegin ) EarliestI = MBB . begin ( ) ; else EarliestI = std :: next ( EarliestI ) ; auto FixupRange = make_range ( EarliestI , iterator ( Merged ) ) ; if ( isLoadSingle ( Opcode ) ) { for ( MachineInstr & MI : FixupRange ) { for ( unsigned & ImpDefReg : ImpDefs ) { for ( MachineOperand & MO : MI . implicit_operands ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != ImpDefReg ) continue ; if ( MO . readsReg ( ) ) MO .


<s> const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == BaseReg ) return false ; if ( MO . isUse ( ) && MO . getReg ( ) == BaseReg ) { BaseRegKill = BaseRegKill || MO . isKill ( ) ; CanDeleteLEA = false ; } } } if ( ! RemovableAdd ) return true ; for ( ++ I ; & * I != JumpMI ; ++ I ) { for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( )


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> bool <ISA_LIT>LowerMASSVEntries :: isMASSVFunc ( StringRef Name ) { return llvm :: is_contained ( MASSVFuncs


<s> if ( aarch64_stack_protector_guard == SSP_GLOBAL ) return


<s> <ISA_LIT>ABIInfo <ISA_LIT>ABIInfo :: computeTargetABI ( ) { <ISA_LIT>ABIInfo abi ( <STR_LIT> ) ; abi = <STR_LIT> ; assert ( abi . ThisABI


<s> inline vector signed short vec_vminsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vminsh ( ( vector signed short ) a1


<s> static inline const MachineInstrBuilder & addConstantPoolReference ( const MachineInstrBuilder & MIB ,

unsigned CPI , unsigned GlobalBaseReg , unsigned char OpFlags ) {


<s> return new <ISA_LIT>ELFStreamer ( Context , MAB


<s> if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister

( MI -> getOperand ( <NUM_LIT> ) ) ) return false ;


<s> IsZExt = true ; unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : { IsZExt = true ; unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; assert ( ! isVarArg && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) ->


<s> AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt32 ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { Value * Op = * i ; if ( const StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; Disp += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; } else if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; } else goto unsupported_gep ; } } if ( ! isInt32 ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; unsupported_gep : break ; } } if ( GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM

. IndexReg != <NUM_LIT> ) ) return false ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned


<s> const InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrSpls ( SDValue Addr , SDValue & Base , SDValue & Offset , SDValue &


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> && ! isDarwin ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createLo ( Expr , isDarwin , Ctx ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createHa ( Expr , isDarwin , Ctx ) ; break ; } return MCOperand :: createExpr (


<s> static DecodeStatus DecodeHPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeSPRRegisterClass ( Inst , RegNo , Address


<s> uint8x16_t result = vcombine_u8 ( a , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ; return


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( !

SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) {


<s> bool function_resolver :: require_integer_immediate ( unsigned int argno ) { if ( ! scalar_argument_p ( argno


<s> IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot


<s> unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; updateValueMap ( I , ResultReg ) ; return true


<s> emitInst ( <STR_LIT> , ResultReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; break ; } case CmpInst :: ICMP_SGE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_SLE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: FCMP_OEQ : case CmpInst :: FCMP_UNE : case CmpInst :: FCMP_OLT : case CmpInst :: FCMP_OLE : case CmpInst :: FCMP_OGT : case CmpInst :: FCMP_OGE : { if ( UnsupportedFPMode ) return false ; bool IsFloat = Left -> getType ( ) -> isFloatTy ( ) ; bool IsDouble = Left -> getType ( ) -> isDoubleTy ( ) ; if ( ! IsFloat && ! IsDouble ) return false ; unsigned Opc , CondMovOpc ; switch ( P ) { case CmpInst :: FCMP_OEQ : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNE : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGT : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; CondMovOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned RegWithZero = createResultReg ( & <STR_LIT> ) ; unsigned RegWithOne = createResultReg ( &


<s> const DataLayout & DL = getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSizeInBits ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getRepresentedCsect ( ) ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( CurrentFnSym


( ) ) return CSR_Darwin_<ISA_LIT>_AAPCS_SaveList ;


<s> } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ; return true


<s> SelectionDAG & DAG = DCI . DAG ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getValueType ( N -> getValueType ( <NUM_LIT> ) ) } ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( N -> getValueType ( <NUM_LIT> )

== <STR_LIT> ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;


<s> if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N


<s> static DecodeStatus DecodeLoadI64 ( MCInst & Inst , uint64_t insn , uint64_t Address , const void *


<s> return ( __m128i ) __builtin_ia32_broadcasti32x2_128_mask ( ( __v4si ) __A , ( __v4si ) _mm_setzero_si128 ( ) ,


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM .


<s> TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> )

, NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ;


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer (


<s> if ( PrevInstrIt . getNodePtr ( ) == LoadInst ) StInst = LoadInst ; MachineInstr * NewStore = BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StoreDisp ) . addReg ( <STR_LIT> ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; if ( StoreBase . isReg ( ) ) getBaseOperand ( NewStore ) . setIsKill ( false ) ; MachineOperand & StoreSrcVReg = StoreInst -> getOperand ( <STR_LIT> ) ; assert ( StoreSrcVReg . isReg ( ) && <STR_LIT> ) ; NewStore -> getOperand ( <STR_LIT> ) . setIsKill ( StoreSrcVReg . isKill ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op


<s> return expandMOV32r1 ( MIB , * this , false ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , true ) ; case <STR_LIT> : case <STR_LIT> : return ExpandMOVImmSExti8 ( MIB ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get (


<s> Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret +=


<s> } if ( candidate -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) ) return true ; } } unsigned Opcode = candidate -> getOpcode ( ) ; if ( Subtarget -> insertNOPLoad ( ) && Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) return true ; if ( Subtarget -> fixAllFDIVSQRT ( ) && Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) return true ; return


<s> if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; return


<s> return ( vector unsigned short ) __builtin_altivec_vmuloub ( ( vector signed char )


<s> const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; } return false


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt (


<s> uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler :: Fail


<s> Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> )


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) { Tmp . back ( ) = Suffixes [ I ] ; Match [ I ] = MatchInstructionImpl ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match [ I ] == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } Op . setTokenValue ( Base ) ; unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } if ( ErrorInfo != ~ <NUM_LIT>


<s> int addp4_optimize_ok ( rtx op1 , rtx op2 ) { return ( basereg_operand ( op1 , GET_MODE ( op1 ) ) != basereg_operand ( op2 ,


<s> const MCExpr * Expr = Fixup . getValue ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { const MCBinaryExpr * BE = static_cast < const MCBinaryExpr * > ( Expr ) ; const MCExpr * LHS = BE -> getLHS ( ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS (


<s> MachineSDNode * Node = DAG . getMachineNode ( XorOp , DL , PtrTy , Val ) ; return SDValue ( Node


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { cum -> words =


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , false ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue ( )


<s> assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT>


<s> inline unsigned odd128 ( bool Is32bit


<s> RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( Registry ) ; initialize<ISA_LIT>LoadStoreOptPass ( Registry


<s> <ISA_LIT>_32ATTAsmParser ( const Target & T , MCAsmParser & _Parser ) : <ISA_LIT>ATTAsmParser


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( JIT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , isLittle ( isLittle ) , TLOF ( std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( TT , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this , Options . StackAlignmentOverride ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> :

FS . str ( ) + <STR_LIT> , isLittle , * this , Options . StackAlignmentOverride ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this , Options . StackAlignmentOverride ) {


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = getShiftExtendType ( ) ; return ( ST == <STR_LIT> || ST == <STR_LIT> || ST ==

<STR_LIT> || ST == <STR_LIT> ) && getShiftExtendAmount ( ) < width ;


<s> if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; return


<s> SMLoc SS = getLoc ( ) ; const AsmToken & TokE = getTok ( ) ; bool IsHash = TokE . is ( AsmToken :: Hash ) ; if ( ! IsHash && TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int64_t Pattern ; if ( IsHash ) { Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; auto * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; Pattern = MCE -> getValue ( ) ; } else { auto Pat = <STR_LIT> ( TokE . getString ( ) ) ; if ( ! Pat ) return MatchOperand_NoMatch ; Lex ( ) ; Pattern = Pat -> Encoding ; assert ( Pattern >= <NUM_LIT> && Pattern < <NUM_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Pattern , getContext ( ) )

, SS , getLoc ( ) , getContext ( ) ) ) ;


<s> switch ( comparison ) { case EQ : if ( TARGET_CMPEQDI_T ) { emit_insn ( gen_cmpeqdi_t ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_jump_insn ( gen_branch_true ( operands [ <NUM_LIT> ] ) ) ; return true ; } msw_skip = NE ; lsw_taken = EQ ; if ( prob >= <NUM_LIT> ) { msw_skip_prob = rev_prob ; if ( REG_BR_PROB_BASE <= <NUM_LIT> ) lsw_taken_prob = prob ? REG_BR_PROB_BASE : <NUM_LIT> ; else { lsw_taken_prob = ( prob ? ( REG_BR_PROB_BASE - ( ( gcov_type ) REG_BR_PROB_BASE * rev_prob / ( ( gcov_type ) prob << <NUM_LIT> ) ) ) : <NUM_LIT> ) ; } } break ; case NE : if ( TARGET_CMPEQDI_T ) { emit_insn ( gen_cmpeqdi_t ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_jump_insn ( gen_branch_false ( operands [ <NUM_LIT> ] ) ) ; return true ; } msw_taken = NE ; msw_taken_prob = prob ; lsw_taken = NE ; lsw_taken_prob = <NUM_LIT> ; break ; case GTU : case GT : msw_taken = comparison ; if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) break ; if ( comparison != GTU || op2h != CONST0_RTX ( SImode ) ) msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GTU ; break ; case GEU : case GE : if ( op2l == CONST0_RTX ( SImode ) ) msw_taken = comparison ; else { msw_taken = comparison == GE ? GT : GTU ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GEU ; } break ; case LTU : case LT : msw_taken = comparison ; if ( op2l == CONST0_RTX ( SImode ) ) break ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = LTU ; break ; case LEU : case LE : if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) msw_taken = comparison ; else { lsw_taken = LEU ; if ( comparison == LE ) msw_taken = LT ; else if ( op2h != CONST0_RTX ( SImode ) ) msw_taken = LTU ; else { msw_skip = swap_condition ( LTU ) ; break ; } msw_skip = swap_condition ( msw_taken ) ; } break ; default : return false ; } num_branches = ( ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) + ( msw_skip != LAST_AND_UNUSED_RTX_CODE ) + ( lsw_taken != LAST_AND_UNUSED_RTX_CODE ) ) ; if ( comparison != EQ && comparison != NE && num_branches > <NUM_LIT> ) { if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) && prob >= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && prob <= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ) { msw_taken_prob = prob / <NUM_LIT> ; msw_skip_prob = REG_BR_PROB_BASE * rev_prob / ( REG_BR_PROB_BASE + rev_prob ) ; lsw_taken_prob = prob ; } else { msw_taken_prob = prob ; msw_skip_prob = REG_BR_PROB_BASE ; lsw_taken_prob =


<s> if ( ! DummyOp ) reachingDefAlgorithm ( MF , ColorOpToReachedUses , In , Out , Gen , Kill , ReachableUses ,


<s> SDValue InvMask = DAG . getNOT ( DL , Mask , VT ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Mask , In1 ) ; SDValue SelInv = DAG . getNode ( <STR_LIT> , DL , VT , InvMask , In2 ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P10 ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_MMA ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 ) == RS6000_BTM_LDBL128 ) { if ( ! TARGET_HARD_FLOAT ) error ( <STR_LIT> , name , <STR_LIT> ) ; else error ( <STR_LIT> , name , TARGET_IEEEQUAD ? <STR_LIT> : <STR_LIT> ) ; } else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name


<s> static DecodeStatus DecodeSVCROp ( MCInst & Inst , unsigned Imm , uint64_t Address , const MCDisassembler * Decoder ) { if ( <STR_LIT> ( Imm ) ) { Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseJumpTarget ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SMLoc S = getLexer ( ) . getLoc ( ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = parseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch


<s> __slwpcb ( void ) { return __builtin_ia32_slwpcb ( )


<s> OperandMatchResultTy parseVR32 ( OperandVector & Operands


<s> if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost


<s> Value * <ISA_LIT>IREmitter :: visitATOMOR64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> std :: unique_ptr < <ISA_LIT>Operand > Offset ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Operands . push_back ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , std :: move ( Offset ) ) : <STR_LIT> ( BaseReg , std :: move ( Offset ) ) ) ; return


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i + e ] , i + NumElems ) ) return false ; return


<s> static machine_mode mips_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp


<s> auto Mapper = <STR_LIT> ( ) ; std :: string Name = Mapper . toString ( Val , STI . getFeatureBits ( ) ) ; O << StringRef ( Name )


<s> createSplat2ShuffleMask ( VT , Unpckl , true ) ; createSplat2ShuffleMask ( VT , Unpckh , false ) ; unsigned UnpackOpcode ; if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) UnpackOpcode = <STR_LIT> ; else if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) UnpackOpcode = <STR_LIT> ; else return SDValue ( ) ; V1 = DAG . getVectorShuffle ( <STR_LIT> , DL , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getUNDEF ( <STR_LIT> ) ,


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream


<s> if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; OutStreamer . EmitRawText ( O . str ( )


<s> vst3_u32 ( uint32_t * __a , uint32x2x3_t val ) { __builtin_aarch64_simd_ci __o ; uint32x4x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) temp


<s> bool Filler :: delayHasHazard ( MachineBasicBlock :: instr_iterator MI , bool & SawLoad , bool & SawStore , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { if ( MI -> isImplicitDef ( ) || MI -> isKill ( ) ) return true ; if ( MI -> mayLoad ( ) ) { if ( SawStore ) return true ; SawLoad = true ; } if ( MI -> mayStore ( ) ) { if ( SawStore ) return true ; SawStore = true ; if ( SawLoad ) return true ; } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg


<s> unsigned Size = <NUM_LIT> ; for ( const MachineInstr & MI : MBB ) Size += TII -> GetInstSizeInBytes ( MI ) ; BlockInfo [ MBB . getNumber (


<s> return ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> | ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) ; case ESize16 : return ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> | ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) ; case ESize32


<s> return JCE . finishGVStub ( F ) ; } JCE . startGVStub ( F , <NUM_LIT> * <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; if ( is64Bit ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else if ( TM . getSubtargetImpl ( ) -> isMachoABI ( ) ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } intptr_t BranchAddr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( BranchAddr , ( intptr_t ) Fn , true , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> * <NUM_LIT> ) ; return JCE . finishGVStub


<s> const TargetOperandInfo * OpInfo = TID . OpInfo ; if ( ! OpInfo ) return false ; assert ( TID . getNumDefs ( ) == <NUM_LIT> && NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; ElemSize esize = Opcode == <STR_LIT> ? ESize32 : ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> )


<s> if ( MI -> getOperand ( Op + <STR_LIT> ) . isFI ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( Op + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( Op + <STR_LIT> ) . getIndex ( ) ; return true ; } return


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) &&


<s> InConstantPool = true ; } OutStreamer -> EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MF -> getDataLayout ( ) , MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer ,


<s> float64_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm (


<s> if ( isa < PropFFInst > ( I ) && I . getType ( ) -> isVectorTy ( ) ) { Value * LHS , * RHS ; ICmpInst :: Predicate Pred ; if ( ! match ( I . getOperand ( <NUM_LIT> ) , m_ICmp ( Pred , m_Value ( LHS ) , m_Value ( RHS ) ) ) ) continue ; Value * Start , * End ; ConstantInt * Stride ; if ( match ( LHS , m_SeriesVector ( m_Value ( Start ) , m_ConstantInt ( Stride ) ) ) && match ( RHS , m_SplatVector ( m_Value ( End ) ) ) ) ; else if ( match ( LHS , m_SplatVector ( m_Value ( End ) ) ) && match ( RHS , m_SeriesVector ( m_Value ( Start ) , m_ConstantInt ( Stride ) ) ) ) Pred = ICmpInst :: getSwappedPredicate ( Pred ) ; else continue ; if ( Start -> getType ( ) -> isPointerTy ( ) ) continue ; <STR_LIT> IntID = getMatchingWhileInst ( Pred , Stride ) ; if ( IntID == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I . getOperand ( <NUM_LIT> ) << <STR_LIT> ) ; continue ; } auto * WhileInst = CreateWhile ( IntID , I . getType ( ) , Start , End ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * I . getOperand ( <NUM_LIT> ) << <STR_LIT> << *


<s> void <ISA_LIT>InstPrinter :: printU12ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI ,


<s> machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * label ; rtx cmp_reg , success , oldval ; label = gen_label_rtx ( ) ; cmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; emit_move_insn ( old_reg , cmp_reg ) ; if ( seq ) emit_insn ( seq ) ; success = NULL_RTX ; oldval = cmp_reg ; if ( ! expand_atomic_compare_and_swap ( & success , & oldval , mem , old_reg , new_reg , false , MEMMODEL_SYNC_SEQ_CST , MEMMODEL_RELAXED ) ) return false ; if ( oldval != cmp_reg ) emit_move_insn ( cmp_reg , oldval ) ; emit_cmp_and_jump_insns ( success , const0_rtx , EQ , const0_rtx , GET_MODE ( success ) , <NUM_LIT> , label , profile_probability :: guessed_never ( ) ) ; return true