<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForRet ( CC ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getValVT ( ) != TLI . getValueType ( RV -> getType ( ) ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA .


, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> isPICStyleRIPRel ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) , Result ) ; } return


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory .


<s> return std :: distance ( nodes_begin


<s> const char * getTargetDataString ( ) const { return is<ISA_LIT>64 ( ) ? <STR_LIT>


<s> static void __attribute__ ( ( format ( printf , <NUM_LIT> , <NUM_LIT> ) ) ) bif_diag ( int diagpos , const char *


<s> vdup_lane_u64 ( uint64x1_t __a , const int __b ) { return ( uint64x1_t ) __builtin_neon_vdup_lanedi ( (


<s> if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if ( A ) { const MCSymbol & Sym = A -> getSymbol ( ) ; if ( Asm . isThumbFunc ( & Sym ) ) Value |= <NUM_LIT> ; } } if ( A && ( unsigned ) Fixup . getKind (


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned


<s> Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; } break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( ATReg ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; Instr3 . setOpcode ( <STR_LIT> ) ; Instr3 . addOperand ( Target ) ; Instr3 . addOperand ( ATReg ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( Base . getReg ( ) != Target . getReg ( ) ) ; TwoInstructions = true ; MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( Name ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( ATReg ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . setOpcode ( <STR_LIT> ) ; Instr3 . addOperand ( ATReg ) ; Instr3 . addOperand ( Base ) ; Instr3 . addOperand ( AdjName ) ; break ; } default : assert ( <NUM_LIT> && <STR_LIT> )


<s> case <STR_LIT> : opNum = MI -> getNumOperands ( ) - <NUM_LIT> ; break ; } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI ,


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmplt ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c , mask


<s> ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsCheriPureCap ( ) ) return { } ; if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( )

) return makeArrayRef ( <ISA_LIT>64IntRegs ) ;


<s> code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case GE : if ( mep_imm4_operand ( op1 , SImode ) ) break ; tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op0 , op1 ) ) ; code = EQ ; op0 = tmp ; op1 = const0_rtx ; break ; case EQ : case NE : if ( ! mep_reg_or_imm4_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : case GT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) { op1 = GEN_INT ( INTVAL ( op1 ) + <NUM_LIT> ) ; code = ( code == LE ? LT : GE ) ; goto restart ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op1 , op0 ) ) ; code = ( code == LE ? EQ : NE ) ; op0 = tmp ; op1 = const0_rtx ; break ; case LTU : if ( op1 == const1_rtx ) { code = EQ ; op1 = const0_rtx ; break ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LTU , tmp , op0 , op1 ) ) ; code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case LEU : tmp = gen_reg_rtx ( SImode ) ; if ( mep_expand_setcc_1 ( LEU , tmp , op0 , op1 ) ) code = NE ; else if ( mep_expand_setcc_1 ( LTU , tmp , op1 , op0 ) ) code = EQ ; else gcc_unreachable ( ) ; op0 = tmp ; op1 = const0_rtx ; break ; case GTU : tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( GTU , tmp , op0 , op1 ) || mep_expand_setcc_1 ( LTU , tmp , op1 , op0 ) ) ; code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case GEU : tmp = gen_reg_rtx ( SImode ) ; if ( mep_expand_setcc_1 ( GEU , tmp , op0 , op1 ) ) code = NE ; else if ( mep_expand_setcc_1 ( LTU , tmp ,


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; switch ( Opcode ) { default :


<s> emit_move_insn ( target , mem ) ; return target ; } rtx_vector_builder int_builder ( VNx16QImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i < builder . encoded_nelts ( ) ; ++ i ) int_builder . quick_push ( INTVAL

( builder . elt ( i ) ) ? constm1_rtx : const0_rtx ) ;


<s> bool CloseParen = false ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( Subtarget -> isTargetCygMing ( ) ) BuildMI ( BB , DebugLoc ( ) , TII -> get ( <STR_LIT> )


<s> SmallVector < std :: pair < SMLoc , std :: string > , <NUM_LIT> > Warnings ; int RegClassID = - <NUM_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < FinalOperands . size ( ) ; ++ i ) { <ISA_LIT>Operand & OrigOp = static_cast < <ISA_LIT>Operand & > ( * OrigOperands [ i + <NUM_LIT> ] ) ; <ISA_LIT>Operand & FinalOp = static_cast < <ISA_LIT>Operand & > ( * FinalOperands [ i ] ) ; if ( FinalOp . isReg ( ) && ( ! OrigOp . isReg ( ) || FinalOp . getReg ( ) != OrigOp . getReg ( ) ) ) return false ; if ( FinalOp . isMem ( ) ) { if ( ! OrigOp . isMem ( ) ) return false ; unsigned OrigReg = OrigOp . Mem . BaseReg ; unsigned FinalReg = FinalOp . Mem . BaseReg ; if ( RegClassID != - <NUM_LIT> && ! <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( OrigReg ) ) { return Error ( OrigOp . getStartLoc ( ) , <STR_LIT> ) ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else return false ; bool IsSI = IsSIReg ( FinalReg ) ; FinalReg = GetSIDIForRegClass ( RegClassID , FinalReg ,


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const <ISA_LIT>RegisterInfo * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF )

) FrameReg = RegInfo -> getBaseRegister ( ) ;


<s> static SDValue lowerVECTOR_SHUFFLE_VSHF ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Op0 ; SDValue Op1 ; EVT MaskVecTy = ResTy . changeVectorElementTypeToInteger ( ) ; EVT MaskEltTy = MaskVecTy . getVectorElementType ( ) ; bool Using1stVec = false ; bool Using2ndVec = false ; SDLoc DL ( Op ) ; int ResTyNumElts = ResTy . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) { int Idx = Indices [ i ] ; if ( <NUM_LIT> <= Idx && Idx < ResTyNumElts ) Using1stVec = true ; if ( ResTyNumElts <= Idx && Idx < ResTyNumElts * <NUM_LIT> ) Using2ndVec = true ; } for ( SmallVector < int , <NUM_LIT> > :: iterator I = Indices . begin ( ) ; I != Indices . end ( ) ; ++ I ) Ops . push_back ( DAG . getTargetConstant ( * I , DL , MaskEltTy ) ) ; SDValue MaskVec = DAG . getNode ( <STR_LIT> , DL , MaskVecTy , Ops ) ; if ( Using1stVec && Using2ndVec ) { Op0 = Op -> getOperand ( <NUM_LIT> ) ; Op1 = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Using1stVec ) Op0 = Op1 = Op -> getOperand ( <NUM_LIT>


<s> return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } uint64_t ShiftAmount = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> && ShiftAmount ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount -=


<s> return MBBInfos [ MBB -> getNumber (


<s> bool has<ISA_LIT>32r5 ( ) const { return ( STI . getFeatureBits ( ) &


<s> bool isSpls ( uint16_t Opcode ) { return false


<s> if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; return


<s> if ( ( ! reload_completed || ! safe_group_barrier_needed ( insn ) ) && ( ! mflag_sched_mem_insns_hard_limit || ! is_load_p ( insn ) || mem_ops_in_group [ current_cycle % <NUM_LIT> ] < ia64_max_memory_insns ) ) return <NUM_LIT> ; return


<s> Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const auto * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return ComputeCallAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return ComputeCallAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction ::


<s> Op -> Kind = CondCode ; Op -> CC . Val = CC ; Op -> StartLoc


<s> if ( TM . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: <ISA_LIT> ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; assert ( Encoding == DW_EH_PE_absptr && <STR_LIT> ) ; return MCSymbolRefExpr :: create ( TM . getSymbol ( GV ) , MCSymbolRefExpr ::

VK_<ISA_LIT>_TARGET2 , getContext ( ) ) ;


<s> unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ( NumBytes - ArgRegsSaveSize ) , MachineInstr :: FrameSetup ) ; CFAOffset -= NumBytes - ArgRegsSaveSize ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . isTargetMachO ( ) ) { GPRCS2Size += <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size ) { CFAOffset -= adjustedGPRCS1Size ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr


<s> new_rtx = temp ? temp : ad ; if ( optimize && GET_CODE ( new_rtx ) == PLUS && GET_CODE ( XEXP ( new_rtx , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( new_rtx , <NUM_LIT> ) ) == CONST_INT ) { offset = INTVAL ( XEXP ( ( new_rtx ) , <NUM_LIT> ) ) ; if ( ( offset & mask ) >= ( ( mask + <NUM_LIT> ) / <NUM_LIT> ) ) newoffset = ( offset & ~ mask ) + mask + <NUM_LIT> ; else newoffset = offset & ~ mask ; if ( mask == <NUM_LIT> && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || ( TARGET_64BIT && ( mode )

== DImode ) ) ) newoffset &= ~ ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ;


<s> else { first_reg_offset = next_cum . words ; save_area = crtl -> args . internal_arg_pointer ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( type ) , type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; rs6000_move_block_from_reg ( GP_ARG_MIN_REG + first_reg_offset , mem , nregs ) ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && ! no_rtl && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { int fregno = next_cum . fregno , nregs ; rtx cr1 = gen_rtx_REG ( CCmode , CR1_REGNO ) ; rtx lab = gen_label_rtx ( ) ; int off = ( GP_ARG_NUM_REG * reg_size ) + ( ( fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , cr1 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , lab ) , pc_rtx ) ) ) ; for ( nregs = <NUM_LIT> ; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun -> va_list_fpr_size ; fregno ++ , off += UNITS_PER_FP_WORD , nregs ++ ) { mem = gen_rtx_MEM ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode , plus_constant ( Pmode , save_area , off ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ) ) ; emit_move_insn ( mem , gen_rtx_REG ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode , fregno ) ) ; } emit_label ( lab


<s> return ( __m128h ) __builtin_ia32_vfmulcsh_round ( ( __v8hf ) __A , (


<s> tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != <NUM_LIT> && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) >> <NUM_LIT> ; switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + <NUM_LIT> ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , CCValAssign :: LocInfo LocInfo , CCState & State ) { Register Reg = State .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> set2 = single_set ( load ) ; if ( ! set2 ) return false ; if ( exact_dependency_1 ( SET_DEST ( set1 ) , SET_SRC ( set2 ) )


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getSuccessOrdering ( ) ) ) return SDValue ( ) ; return Op


<s> unsigned flags = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> int idx , vlen = XVECLEN ( body , <NUM_LIT> ) ; if ( ! TARGET_SOM ) fputs ( <STR_LIT> , asm_out_file ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( <STR_LIT> , asm_out_file


<s> SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N2 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Imm = Node -> getOperand ( <NUM_LIT> ) ; const ConstantInt * Val = cast < ConstantSDNode > ( Imm ) -> getConstantIntValue ( ) ; Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && tryFoldLoad ( Node , N2 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , N2 . getOperand ( <NUM_LIT> ) , InFlag } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; InFlag = SDValue ( CNode , <NUM_LIT> ) ; ReplaceUses ( N2 . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; CurDAG -> setNodeMemRefs ( CNode , { cast < LoadSDNode > ( N2 ) -> getMemOperand ( ) } ) ; return CNode ; } SDValue Ops [ ] = { N0 , N2 , Imm , InFlag } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( ROpc , dl , VTs , Ops ) ; InFlag = SDValue ( CNode , <NUM_LIT>


<s> static bool checkAndUpdateEFLAGSKill ( MachineBasicBlock :: iterator SelectItr , MachineBasicBlock * BB , const TargetRegisterInfo * TRI ) { if ( isEFLAGSLiveAfter ( SelectItr , BB ) ) return false ; SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ; return true


<s> return __builtin_mve_vmulhq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; UpdateOther . clear (


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) & <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( encoding


<s> unsigned <ISA_LIT>TTI :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { return TargetTransformInfo :: getCmpSelInstrCost ( Opcode , ValTy , CondTy


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor


<s> static unsigned getStoreRegOpcode ( Register SrcReg , const TargetRegisterClass * RC ,

bool IsStackAligned , const <ISA_LIT>Subtarget & STI ) {


<s> vld1_dup_u32 ( const uint32_t * __a ) { return vdup_n_u32 (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft


<s> bool isN1SExt = isSignExtended ( N1 , DAG ) ; if ( isN0SExt && isN1SExt ) NewOpc = <STR_LIT> ; else { bool isN0ZExt = isZeroExtended ( N0 , DAG ) ; bool isN1ZExt = isZeroExtended ( N1 , DAG ) ; if ( isN0ZExt && isN1ZExt ) NewOpc = <STR_LIT> ; else if ( isN1SExt || isN1ZExt ) { if ( isN1SExt && isAddSubSExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN1ZExt && isAddSubZExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN0ZExt && isAddSubZExt ( N1 , DAG ) ) { std :: swap ( N0 , N1 ) ; NewOpc = <STR_LIT> ; isMLA = true ; } } if ( ! NewOpc ) { if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; } } SDLoc DL ( Op ) ; SDValue Op0 ; SDValue Op1 = skipExtensionForVectorMULL ( N1 , DAG ) ; if ( ! isMLA ) { Op0 = skipExtensionForVectorMULL ( N0 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( NewOpc , DL , VT , Op0 , Op1 ) ; } SDValue N00 = skipExtensionForVectorMULL ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; SDValue N01 = skipExtensionForVectorMULL ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; EVT Op1VT = Op1 . getValueType ( ) ; return DAG . getNode ( N0 -> getOpcode ( ) , DL , VT , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N00 ) , Op1 ) , DAG . getNode ( NewOpc , DL ,

VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N01 ) , Op1 ) ) ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) ,


<s> assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ; return ( ( __m128 ) vec_ld ( <NUM_LIT> , (


<s> bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) ) ; } if ( HasParenPart )


<s> MachineFunction :: iterator OldPrior = std :: prev ( BBi ) ; bool B = TII -> analyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != & MF -> front ( ) && ! TII -> analyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB ->


<s> static DecodeStatus DecodeMatrixTile ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { unsigned LastReg = ( <NUM_LIT> << NumBitsForTile


<s> assert ( OldOp2 . isReg ( ) && OldOp2 . getReg ( ) == <STR_LIT> && OldOp2 . isDead ( ) && <STR_LIT> ) ; ( void ) OldOp1 ; ( void ) OldOp2 ; assert ( NewOp1 . isReg ( ) && NewOp1 . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( NewOp2 . isReg ( ) && NewOp2 . getReg ( ) == <STR_LIT> &&


<s> if ( isSelectPseudo ( * NextMIIt ) ) { assert ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCValid && <STR_LIT> ) ; if ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCMask || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) { Selects . push_back ( & * NextMIIt ) ; continue ; } break ; } if ( NextMIIt -> definesRegister ( <STR_LIT> ) || NextMIIt -> usesCustomInsertionHook ( ) ) break ; bool User = false ; for ( auto SelMI : Selects ) if ( NextMIIt -> readsVirtualRegister ( SelMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { User = true ; break ; } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; } MachineInstr * LastMI = Selects . back ( ) ; bool CCKilled = ( LastMI -> killsRegister ( <STR_LIT> ) || checkCCKill ( * LastMI , MBB ) ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = <STR_LIT> ( LastMI , MBB ) ; MachineBasicBlock * FalseMBB = <STR_LIT> ( StartMBB ) ; if ( ! CCKilled ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB )


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) ,


, ( __mmask16 ) __B , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( SubRegIdx == <STR_LIT> ) { auto & MII = getTranslator ( ) . getMII ( ) ; const MCInstrDesc & MCID = MII . get ( TheMCInst . Inst .


<s> if ( ! ( TARGET_64BIT_P ( ix86_isa_flags ) )


<s> * ( __mmask16 * ) __A = __builtin_ia32_kmovw (


<s> MFI . setObjectAlignment ( FI , DNum % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( DNum == <NUM_LIT> ) MFI . setObjectAlignment ( FI , MFI . getMaxAlignment ( ) ) ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg +=


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _wbnoinvd ( void ) { __builtin_ia32_wbnoinvd (


<s> gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_DARWIN : case


<s> unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg


<s> return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp


<s> cum -> sysv_gregno = GP_ARG_MIN_REG ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> libcall = libcall ; cum -> nargs_prototype = <NUM_LIT> ; if ( incoming || cum -> prototype ) cum -> nargs_prototype = n_named_args ; if ( ( ! fntype && rs6000_default_long_calls ) || ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 ) ) { cum -> escapes = call_ABI_of_interest ( fndecl ) ; if ( cum -> escapes ) { tree return_type ; if ( fntype ) { return_type = TREE_TYPE ( fntype ) ; return_mode = TYPE_MODE ( return_type ) ; } else return_type = lang_hooks . types . type_for_mode ( return_mode , <NUM_LIT> ) ; if ( return_type != NULL ) { if ( TREE_CODE ( return_type ) == RECORD_TYPE && TYPE_TRANSPARENT_AGGR ( return_type ) ) { return_type = TREE_TYPE ( first_field ( return_type


<s> if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( Glue ) ; VTs = DAG . getVTList ( PtrVT , <STR_LIT>


<s> const <ISA_LIT>TargetLowering * <ISA_LIT>TargetLowering :: create ( const <ISA_LIT>TargetMachine & TM , const


<s> if ( ! cfun -> machine -> reg_save_slot [ REGNO ( reg ) ] ) { cfun -> machine -> reg_save_size += <NUM_LIT> ; cfun -> machine -> reg_save_slot [ REGNO ( reg

) ] = cfun -> machine -> reg_save_size ;


<s> void mmix_asm_output_addr_diff_elt ( FILE * stream , rtx body ATTRIBUTE_UNUSED , int value , int rel ) { fprintf ( stream , <STR_LIT> , value , rel


<s> return ( __m256i ) __builtin_ia32_pabsq256_mask ( ( __v4di ) __A , ( __v4di )


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter & Printer , bool isDarwin ) { MCContext & Ctx = Printer . OutContext ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; unsigned access = MO . getTargetFlags ( ) & <STR_LIT> ; switch ( access ) { case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch (


<s> SDValue Narrow = N -> getOperand ( <NUM_LIT> ) ; EVT NarrowVT = Narrow . getValueType ( ) ; SDValue Op = PromoteMaskArithmetic ( Narrow . getNode ( ) , VT , DAG , <NUM_LIT> ) ; if ( ! Op ) return SDValue ( ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi } ; return DAG . getMergeValues ( OutOps , <NUM_LIT> ,


<s> void <ISA_LIT>FrameLowering :: emitSPExtend ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { DebugLoc DL ; const <ISA_LIT>InstrInfo & TII = * STI


<s> EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; for ( <ISA_LIT>COFFMachineModuleInfo :: stub_iterator I = COFFMMI . stub_begin ( ) , E = COFFMMI . stub_end ( ) ; I != E ; ++ I ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( I -> getKeyData ( ) ) + <STR_LIT> + Twine ( COFF :: C_EXT ) + <STR_LIT> + Twine ( COFF :: DT_FCN << COFF :: N_BTSHFT ) + <STR_LIT> ) ; } if ( Subtarget -> isTargetCygMing ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getCOFFSection ( <STR_LIT> , true , SectionKind


<s> const SmallVectorImpl < unsigned > & RegList = Op . getRegList ( ) ; uint32_t Mask = <NUM_LIT> ; for ( size_t i = <NUM_LIT> ; i < RegList . size ( ) ; ++ i ) { unsigned Reg = MRI -> getEncodingValue ( RegList [ i ] ) ; if ( Reg == <NUM_LIT> ) Reg = <NUM_LIT> ; if ( Reg == <NUM_LIT> ) return Error ( L , <STR_LIT> ) ; assert ( Reg < <NUM_LIT> && <STR_LIT> ) ; unsigned Bit = ( <NUM_LIT> << Reg ) ; Mask |= Bit ; } if ( ! Wide && ( Mask & <NUM_LIT> ) != <NUM_LIT> ) return Error ( L , <STR_LIT> ) ; getTargetStreamer ( ) . emit<ISA_LIT>WinCFISaveRegMask ( Mask ,


<s> Register NewBase ; int64_t NewOffset ; if ( mi_match ( Root , MRI , m_GPtrAdd ( m_Reg ( NewBase ) , m_ICst ( NewOffset ) ) ) && isShiftedInt

< <NUM_LIT> , <NUM_LIT> > ( NewOffset ) ) {


<s> const uint64_t Chunk = getChunk ( Imm , FromIdx ) << ShiftAmt ; Imm &= ~ ( <NUM_LIT> << ShiftAmt ) ; return Imm |


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; else if ( VT == <STR_LIT> ) return <STR_LIT> (


<s> } else if ( GET_CODE ( addr ) == LO_SUM ) { output_operand ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; if ( TARGET_CM_MEDMID ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; output_address ( VOIDmode , XEXP ( addr , <NUM_LIT> ) ) ; fputc ( ')' , file ) ; } else if ( flag_pic && GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MINUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST && GET_CODE ( XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == MINUS && XEXP ( XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == pc_rtx ) { addr = XEXP ( addr , <NUM_LIT> ) ; output_addr_const ( file , XEXP ( addr , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; output_addr_const ( file , XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ; fputc ( ')'


<s> SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; unsigned ZMask = <NUM_LIT> ; int V1DstIndex = - <NUM_LIT> ; int V2DstIndex = - <NUM_LIT> ; bool V1UsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == Mask [ i ] ) { V1UsedInPlace = true ; continue ; } if ( V1DstIndex != - <NUM_LIT> || V2DstIndex != - <NUM_LIT> ) return SDValue ( ) ; if ( Mask [ i ] < <NUM_LIT> ) { V1DstIndex = i ; } else { V2DstIndex = i ; } } if ( V1DstIndex == - <NUM_LIT> && V2DstIndex == - <NUM_LIT> ) return SDValue ( ) ; unsigned V2SrcIndex = <NUM_LIT> ; if ( V1DstIndex != - <NUM_LIT> ) { V2SrcIndex = Mask [ V1DstIndex ] ; V2DstIndex = V1DstIndex ; V2 = V1 ; } else { V2SrcIndex = Mask [ V2DstIndex ] - <NUM_LIT> ; } if ( ! V1UsedInPlace ) V1 = DAG . getUNDEF ( <STR_LIT> ) ; unsigned InsertPSMask = V2SrcIndex << <NUM_LIT> | V2DstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT>


<s> case FK_Data_4 : return ELF :: R_390_TLS_LE32 ; case FK_Data_8 : return ELF :: R_390_TLS_LE64 ; } llvm_unreachable ( <STR_LIT> )


<s> NodeSet ElimNodes { * Graph } ; EdgeSet ElimEdges { * Graph } ; int RemainingGadgets = elimMitigatedEdgesAndNodes ( * Graph , ElimEdges , ElimNodes ) ; if ( ElimEdges . empty ( ) && ElimNodes . empty ( ) ) { Graph -> NumFences = <NUM_LIT> ; Graph -> NumGadgets


<s> static DecodeStatus DecodeFGR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL , false ) ) return false ; size = int_size_in_bytes ( type ) ; return ( size < <NUM_LIT> || size


<s> uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> return ( __A [ <NUM_LIT> ] < __B [ <NUM_LIT> ]


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( getThe<ISA_LIT>elTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( getThe<ISA_LIT>64elTarget ( ) ) ; PassRegistry * PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>DelaySlotFillerPass ( * PR ) ; initialize<ISA_LIT>BranchExpansionPass ( * PR ) ; initializeMicro<ISA_LIT>SizeReducePass ( *


<s> case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT>


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t MulAmt = C -> getZExtValue ( ) ; unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue (


<s> COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = <NUM_LIT> ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = <NUM_LIT> ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + <NUM_LIT> ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR32Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands ,


<s> MinReservedArea = ( ( MinReservedArea + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; MinReservedArea += <NUM_LIT> * nAltivecParamsAtEnd ; } MinReservedArea = std :: max ( MinReservedArea , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; MinReservedArea = ( MinReservedArea + AlignMask ) & ~ AlignMask ; FI -> setMinReservedArea (


<s> assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return NoHazard ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return NoHazard ; if ( NumIssued != <NUM_LIT> && ( isFirst || isSingle ) ) return Hazard ; if ( isCracked && NumIssued > <NUM_LIT> ) return Hazard ; switch ( InstrType ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; Chain = DAG . getStore ( Chain , DL , Lo , Ptr , MachinePointerInfo ( ) , Nd . getAlignment ( ) , Nd . getMemOperand ( ) -> getFlags ( ) , Nd . getAAInfo ( ) ) ; Ptr = DAG . getPointerAdd ( DL , Ptr , <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , Hi , Ptr , MachinePointerInfo ( ) , std :: min ( Nd . getAlignment ( ) ,

<NUM_LIT> ) , Nd . getMemOperand ( ) -> getFlags ( ) , Nd . getAAInfo ( ) ) ;


<s> Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = Mask . size ( ) == <NUM_LIT> ? <STR_LIT> :


<s> if ( sh_promote_prototypes ( funtype ) ) return promote_mode ( type


<s> if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps (


<s> if ( Subtarget -> hasInt256 ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof (


<s> if ( ! MI -> hasDelaySlot ( ) ) continue ; MachineBasicBlock :: iterator D = MBB . end ( ) ; if ( ! DisableDelaySlotFiller ) D = findDelayInstr ( MBB , MI ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( I , & MBB , D ) ; unsigned structSize = <NUM_LIT> ; if ( needsUnimp ( MI , structSize ) ) { MachineBasicBlock :: iterator J = MI ; ++ J ; assert ( J != MBB . end ( ) && <STR_LIT> ) ; BuildMI ( MBB , ++ J , MI -> getDebugLoc ( ) , TII ->

get ( <STR_LIT> ) ) . addImm ( structSize ) ;


<s> return DAG . getBitcast ( VT , DAG . getNOT ( SDLoc ( N ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ; } if ( <STR_LIT> ( N1 . getNode ( ) ) && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . isUndef ( ) && TLI . isTypeLegal ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getNOT ( SDLoc ( N ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) , N0 . getOperand ( <NUM_LIT> ) ) ; } if ( ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == N -> getOpcode ( ) ) { SDValue TruncExtSrc = N0 . getOperand ( <NUM_LIT> ) ; auto * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; auto * N001C = dyn_cast < ConstantSDNode > ( TruncExtSrc . getOperand ( <NUM_LIT> ) ) ; if ( N1C && ! N1C -> isOpaque ( ) && N001C && ! N001C -> isOpaque ( ) ) { SDLoc DL ( N ) ; SDValue LHS = DAG . getZExtOrTrunc ( TruncExtSrc . getOperand ( <NUM_LIT> ) , DL , VT ) ; SDValue RHS = DAG . getZExtOrTrunc ( TruncExtSrc . getOperand ( <NUM_LIT> ) ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: adjustPqBitsRmAndRrm ( const MCInst & Inst , unsigned Value , const MCSubtargetInfo & STI ) const { return adjustPqBits ( Inst , Value , <NUM_LIT> , <NUM_LIT>


<s> static const MCPhysReg ArgGPRs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return true ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg


<s> loopMBB -> addSuccessor ( sinkMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> normalizeSuccProbs ( ) ; BuildMI ( loopMBB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( IsNand ) { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( <STR_LIT> ) . addReg ( BinOpRes ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else if ( ! IsSwap ) { BuildMI ( loopMBB , DL , TII -> get ( Opcode ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( Incr ) . addReg ( Mask ) ; } BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( OldVal ) . addReg ( Mask2 ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( StoreVal ) . addReg ( BinOpRes ) ; BuildMI ( loopMBB , DL , TII -> get ( SC ) , StoreVal ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loopMBB , DL , TII -> get ( BEQ ) ) . addReg ( StoreVal ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ; sinkMBB -> addSuccessor ( exitMBB , BranchProbability :: getOne ( ) ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( Mask ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = SEOp == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest

, RegState :: Kill ) . addImm ( ShiftImm ) ;


<s> return getShuffleAlignrImmediate ( SVOp , true


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( - ( uint32_t ) CE ->


<s> unsigned Idx = isPairedLdSt ( MI ) ? PairedRegOp : <NUM_LIT> ; return MI -> getOperand ( Idx


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; switch ( Op0 . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue NewLoad [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> , ie = Op0 . getNumOperands ( ) ; i != ie ; ++ i ) { SDValue LdOp = Op0 . getOperand ( i ) ; if ( LdOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( LdOp ) ; SDValue LoadOps [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) } ; NewLoad [ i ] = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LoadOps , LD -> getMemoryVT ( ) , LD


<s> break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; } const MCParsedAsmOperand & Op3 = * Operands [ <NUM_LIT> + NumPredOps ] ; if ( ! Op3 . isReg ( ) || Op3 . getReg ( ) != RNext ) return Error ( Op3 . getStartLoc ( ) , <STR_LIT> ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> + NumPredOps ) ; Operands [ <NUM_LIT> + NumPredOps ] = <ISA_LIT>Operand :: CreateReg ( RPair , Op2 . getStartLoc ( ) ,


<s> gen = gen_atomic_compare_and_swapqi_1 ; break ; default : gcc_unreachable ( ) ; } if ( doubleword ) { rtx low_new_mem = gen_lowpart ( hmode , new_mem ) ; rtx low_exp_input = gen_lowpart ( hmode , exp_input ) ; rtx high_new_mem = gen_highpart ( hmode , new_mem ) ; rtx high_exp_input = gen_highpart ( hmode , exp_input ) ; emit_cmp_and_jump_insns ( low_new_mem , low_exp_input , NE , NULL_RTX , hmode , <NUM_LIT> , cmp_label , profile_probability :: guessed_never ( ) ) ; emit_cmp_and_jump_insns ( high_new_mem , high_exp_input , NE , NULL_RTX , hmode , <NUM_LIT> , cmp_label , profile_probability :: guessed_never ( ) ) ; } else emit_cmp_and_jump_insns ( new_mem , exp_input , NE , NULL_RTX , GET_MODE ( exp_input ) , <NUM_LIT> , cmp_label , profile_probability :: guessed_never ( ) ) ; if ( doubleword ) emit_insn ( gendw ( target_val , mem , exp_input , gen_lowpart ( hmode , new_input ) , gen_highpart ( hmode , new_input ) , mem_model ) ) ; else emit_insn ( gen ( target_val , mem , exp_input , new_input , mem_model ) ) ; if ( ! loop_label ) { emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( cmp_label


<s> BitSize = std :: min ( BitSize , OrigBitSize ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; for ( int64_t I = BitSize / <NUM_LIT> ; I >= <NUM_LIT> ; I = I / <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , VT , Op , DAG . getConstant ( I ,


<s> OutStreamer -> EmitInstruction ( Inst , getSubtargetInfo ( ) , EnablePrintSchedInfo ) ; SMShadowTracker . count ( Inst , getSubtargetInfo ( ) , CodeEmitter . get


<s> Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ <NUM_LIT> ] < <NUM_LIT> ) { Size = <NUM_LIT> ; Table = DecoderTable16 ; } else if ( Bytes [ <NUM_LIT> ] < <NUM_LIT> ) { Size =


<s> struct unw_labeled_state * ls ; labeled_state_alloced ++ ; ls = malloc ( sizeof ( struct unw_labeled_state ) ) ; if ( ! ls ) { int n = atomic_alloc ( &


<s> EVT EltVT = Elt . getValueType ( ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && Op . getValueType ( ) . getScalarSizeInBits ( ) == <NUM_LIT> ) return LowerINSERT_VECTOR_ELT_i1 ( Op , DAG , Subtarget ) ; if ( getTypeAction ( * DAG . getContext ( ) , EltVT ) == TargetLowering :: TypePromoteFloat ) { SDLoc dl ( Op ) ; EVT IEltVT = <STR_LIT> ( EltVT . getScalarSizeInBits ( ) ) ; assert ( getTypeAction ( * DAG . getContext ( ) , IEltVT ) != TargetLowering :: TypePromoteFloat ) ; SDValue VecIn = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = VecIn . getValueType ( ) ; EVT IVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , IEltVT , VecVT . getVectorNumElements ( ) ) ; SDValue IElt = DAG . getNode ( <STR_LIT> , dl , IEltVT , Elt ) ; SDValue IVecIn = DAG . getNode ( <STR_LIT> , dl , IVecVT , VecIn ) ; SDValue IVecOut = DAG . getNode ( <STR_LIT> , dl , IVecVT , IVecIn , IElt , Lane ) ; return DAG . getNode ( <STR_LIT> , dl


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { emitFrameDirective ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str


<s> unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) { assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2

) || Offset1 <= Offset2 ) && <STR_LIT> ) ;


<s> LLVMContext & Context = M -> getContext ( ) ; bool LE = TM . isLittleEndian ( ) ; std :: string Name = F . getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub


<s> void <ISA_LIT>AsmPrinter :: printRegisterList ( const MachineInstr * MI , int opNum , raw_ostream & O ) { for ( int i = opNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != opNum ) O << <STR_LIT> ; printOperand ( MI , i , O


<s> getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FABS , G_FSQRT } ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalFor ( { { s32 , s32 } , { s32 , s64 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_FCEIL , G_FFLOOR } ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } }


<s> unsigned RA = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI


<s> unsigned Value = get<ISA_LIT>RegisterNumbering ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT> ; Value |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; Value <<= <NUM_LIT> ; Value |= MO3 . getImm ( ) ; return Value


<s> return __builtin_mve_vldrbq_uv8hi ( ( __builtin_neon_qi * )


<s> dest = ia64_single_set ( consumer ) ; gcc_assert ( dest ) ; mem = SET_DEST ( dest ) ; gcc_assert ( mem && GET_CODE ( mem ) == MEM ) ; return reg_mentioned_p ( reg ,


<s> Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , DAG . getConstant ( Offset , dl , PtrVT ) ) ; return Result


<s> static bool isZExtLoad ( const MachineInstr * LI ) { switch ( LI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( uint64x1_t ) { ( __a [ <NUM_LIT> ] & __b [ <NUM_LIT> ] ) ? - <NUM_LIT> :


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts


<s> if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EVT = ( <STR_LIT> ) ( VT . getSimpleVT ( ) + <NUM_LIT> ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { Idx , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; MVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; MVT VVT = Op . getOperand ( <NUM_LIT> ) .


<s> uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue ( <NUM_LIT> ) ; return DAG . getLoad ( ArgVT , dl , Chain , VAARG , MachinePointerInfo


<s> EVT NarrowVT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || NarrowVT != <STR_LIT> ) return false ; uint64_t ShiftImm ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShiftImm ) ) return false ; SDLoc dl ( N ) ; SDValue Opd0 = Widen ( CurDAG , Op .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Ld = Sc . getOperand ( <NUM_LIT> ) ; if ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) return SDValue ( ) ; break ; } } if ( ! <STR_LIT> ( Ld . getNode ( ) ) ) return SDValue ( ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) return SDValue ( ) ; bool Is256 = VT . getSizeInBits ( ) == <NUM_LIT> ; bool Is128 = VT . getSizeInBits ( ) == <NUM_LIT> ; unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; if ( Is256 && ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) ) return Ld ; if ( Is128 && ( ScalarSize == <NUM_LIT> ) ) return Ld ; if ( Subtarget -> hasAVX2 ( ) && Ld . getValueType ( ) . isInteger ( ) ) { if ( Is256 && ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) ) return Ld ; if ( Is128 && ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> || ScalarSize


<s> bool mips_mem_fits_mode_p ( machine_mode mode , rtx x ) { return ( MEM_P ( x ) && MEM_SIZE_KNOWN_P ( x ) && MEM_SIZE ( x


<s> if ( GV -> hasLocalLinkage ( ) ) return false ; if ( ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV ->


<s> unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder )


<s> if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB . add ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; if ( unsigned OldInstrNum = MI


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( has<ISA_LIT>32r6 ( ) && isFP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r6FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } if ( hasCOP3 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_GP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( hasCn<ISA_LIT> ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCn<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result


<s> } else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && isV8M ( STI ) ) emitAttribute ( <STR_LIT>


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg ) , dwarf_address


<s> Error ( HandlerDataLoc , <STR_LIT> ) ; return true ; } if ( PersonalityLoc . isValid ( ) ) { Error ( L , <STR_LIT> ) ; Error ( PersonalityLoc , <STR_LIT> ) ; return true


<s> virtual bool isBranchWithImm ( unsigned Opc ) const { return


<s> DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo + <NUM_LIT> ) ) ; return MCDisassembler ::


<s> O << <STR_LIT> ; printRegName ( O , Op1 . getReg ( ) ) ; unsigned Offset = Op2 . getImm ( ) ; O << <STR_LIT> << <ISA_LIT>_ez_int2hex ( Offset ) <<


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : if ( ! hasV7Ops || ! hasMP ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm12 ( Inst , imm , Address , Decoder ) ) ) return


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned LL , SC , AND , XOR , ZERO , BEQ ; LL = <STR_LIT> ; SC = <STR_LIT> ; AND = <STR_LIT> ; XOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes2 = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( XOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; BuildMI ( BB , DL , TII -> get ( XOR ) , AndRes2 ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else


<s> Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS =


<s> return ( __m128d ) __builtin_ia32_vfnmsubpd ( ( __v2df ) __A , ( __v2df ) __B , (


<s> EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) ,

MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> const <ISA_LIT>Subtarget & STI = Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ( STI . isCortexA15 ( ) && STI . hasNEON ( ) ) ) return false ; TII = STI . getInstrInfo ( ) ; TRI = STI . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified = false ; DEBUG ( dbgs ( ) << <STR_LIT> << Fn . getName ( ) << <STR_LIT> ) ; DeadInstr . clear ( ) ; Replacements . clear ( ) ; for ( MachineBasicBlock & MBB : Fn ) { for ( MachineInstr & MI :


<s> Pic = MCA . getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF


<s> if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Zeros , Ones ; DAG . computeKnownBits ( Op0 , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > (


<s> if ( parseRegister ( Reg , Group , Regs ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( Kind , Reg . Num , Reg . StartLoc , Reg . EndLoc ) ) ; return MatchOperand_Success


<s> parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result =


<s> if ( const auto * Arg = dyn_cast < Argument > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( ( IsZExt && Arg -> hasZExtAttr ( ) ) || ( ! IsZExt && Arg


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg (


<s> return create<ISA_LIT>MachObjectWriter ( MachO :: CPU_TYPE_ARM64 ,


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeImm12 ( insn ) ) ) ; NumOpsAdded =


<s> if ( ! BranchRelaxation ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = ( const <ISA_LIT>InstrInfo * ) MF -> getTarget ( ) . getInstrInfo ( ) ; MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BlockInfo . clear (


<s> CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( CmpValue != <NUM_LIT> || SrcReg2 != <NUM_LIT> ) return false ; if ( ! MRI -> use_nodbg_empty ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) )


<s> case E_FCCmode : case E_SFmode : return TARGET_HARD_FLOAT ; case


<s> std :: string LowerCaseName = Name . lower ( ) ; for ( unsigned i = <NUM_LIT> ;


<s> struct machine_function * f ; f = ggc_alloc_cleared ( sizeof ( struct


<s> return false ; case <STR_LIT> : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & <NUM_LIT> ; const unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor (


<s> case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! reg_needs_saving_p ( regno ) && ! reg_needs_saving_p ( regno + <NUM_LIT> ) ) { if ( count > <NUM_LIT> ) { if ( count == <NUM_LIT> && ! arm_arch6 ) count ++ ; saved += count * <NUM_LIT> ; } count = <NUM_LIT> ; } else count ++ ; } if ( count > <NUM_LIT> ) { if ( count == <NUM_LIT> && ! arm_arch6 ) count ++ ; saved += count * <NUM_LIT> ; } } return


<s> } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT>


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type && AGGREGATE_TYPE_P ( type


<s> int64_t ThisVal = NumBytes ; if ( isInt < <NUM_LIT> > ( NumBytes ) ) Opcode = <STR_LIT> ; else { Opcode = <STR_LIT> ; int64_t MinVal = - uint64_t ( <NUM_LIT> ) << <NUM_LIT> ; int64_t MaxVal = ( int64_t ( <NUM_LIT> ) << <NUM_LIT> ) - <NUM_LIT> ; if ( ThisVal < MinVal ) ThisVal = MinVal ; else if ( ThisVal > MaxVal ) ThisVal = MaxVal ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , Reg ) . addReg ( Reg ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NumBytes -= ThisVal


<s> SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { auto CarryIn = InvertCarryFlag ( Subtarget , CurDAG , Dl , Op2 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , CarryIn } ) ; } auto CarryOut = InvertCarryFlag ( Subtarget , CurDAG , Dl


<s> vld1_u8 ( const uint8_t * a ) { return ( uint8x8_t ) __builtin_aarch64_ld1v8qi ( ( const __builtin_aarch64_simd_qi


<s> bool end = * group_end ; int i ; if ( next_insn == NULL_RTX || DEBUG_INSN_P ( next_insn ) ) return can_issue_more ; if ( rs6000_sched_insert_nops > sched_finish_regroup_exact ) return can_issue_more ; force = is_costly_group ( group_insns , next_insn ) ; if ( ! force ) return can_issue_more ; if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , * group_count , can_issue_more ) ; if ( rs6000_sched_insert_nops == sched_finish_regroup_exact ) { if ( * group_end ) can_issue_more = <NUM_LIT> ; if ( can_issue_more && ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; if ( rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7 || rs6000_cpu_attr == CPU_POWER8 ) { nop = gen_group_ending_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more = <NUM_LIT> ; } else while ( can_issue_more > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } * group_end = true ; return <NUM_LIT> ; } if ( rs6000_sched_insert_nops < sched_finish_regroup_exact ) { int n_nops = rs6000_sched_insert_nops ; if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT>


<s> unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) .


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) const ; void EmitInstrWithMacroNoAT ( const MachineInstr * MI ) ; private : bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void emitInlineAsmStart ( ) const override ; void emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const override ; void EmitJal ( const MCSubtargetInfo & STI , MCSymbol * Symbol ) ; void EmitInstrReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( const MCSubtargetInfo & STI , unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; void EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock *


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { unsigned SType = <NUM_LIT> ; DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SType ,


<s> inline MachineInstrBuilder buildPACIA ( MachineBasicBlock & MBB , const DebugLoc & DL , unsigned Ptr , unsigned Mod ,


<s> SmallVector < SDNode * , <NUM_LIT> > ToReplace ; for ( SDNode * User : N -> uses ( ) ) { assert ( ( User -> getMachineOpcode ( ) == <STR_LIT> || User -> getMachineOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; ToReplace . push_back ( User ) ; } for ( SDNode * User : ToReplace ) { SDNode * ResNode = CurDAG -> getMachineNode ( User -> getMachineOpcode ( ) , SDLoc ( User ) , User -> getValueType ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( User -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ResNode -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ReplaceUses ( User ,


, ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>CTRLoops ( <ISA_LIT>TargetMachine & TM ) : FunctionPass ( ID )


<s> void <ISA_LIT>InstPrinter :: printU6ImmOperand ( const MCInst * MI , unsigned OpNo


<s> for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef ) continue ; if ( Mask [ i ] < <NUM_LIT> ) return false ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask = false ; if ( Mask [ i ] < CommutVal || Mask [ i ] > CommutVal + <NUM_LIT> ) CommutableMask = false ; ShuffleImm |= ( Mask [ i ] % <NUM_LIT> )


<s> JTI = ( ( <ISA_LIT>BaseTargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = &

MF . getJumpTableInfo ( ) -> getJumpTables ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( )


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_unpackhi_pi8 ( __m64 __m1 , __m64 __m2 ) { __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __m1 ) ; b = ( __vector unsigned char ) vec_splats ( __m2 ) ; c = vec_mergel ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_char [ <NUM_LIT> ] = m1 . as_char [ <NUM_LIT> ] ; res . as_char [ <NUM_LIT> ] = m2 . as_char [ <NUM_LIT> ] ; res . as_char [ <NUM_LIT> ] = m1 . as_char [ <NUM_LIT> ] ; res . as_char [ <NUM_LIT> ] = m2 . as_char [ <NUM_LIT> ] ; res . as_char [ <NUM_LIT> ] = m1 . as_char