<s> ++ It ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch ) . addReg (


<s> unsigned <ISA_LIT>AsmParser :: AdjustAVX512Mem ( unsigned Size , <ISA_LIT>Operand * UnsizedMemOpNext ) { if ( ! getSTI ( ) . getFeatureBits ( ) [


<s> return getTM < Dcpu16TargetMachine >


, ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> MachineOperand & Op = MI -> getOperand ( i + <NUM_LIT> ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } BuildMI ( * BB , MI , dl , TII -> get ( Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent (


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) && ParseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement (


<s> case 'd' : case 'S' : case 'D' : case 'A' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'f' : case 't' : case 'u' : if ( type -> isFloatingPointTy ( ) ) weight = CW_SpecificReg ; break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget -> hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'x' : case 'Y' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasFp256 ( ) ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( isa < ConstantFP > ( CallOperandVal ) ) { weight =


<s> auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange


<s> assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg


<s> return ( uint32x4_t ) ( vabsq_f32 ( __a


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT . changeVectorElementTypeToInteger


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> , dl ,


<s> case E_V8HFmode : case E_V4SFmode : case E_V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_OImode : case E_XImode : gcc_unreachable ( ) ; case E_V64QImode : case E_V32HImode : case E_V16SImode : case E_V8DImode : case E_V32HFmode : case E_V16SFmode : case E_V8DFmode : case E_V16HFmode : case E_V8SFmode : case E_V8SImode : case E_V32QImode : case E_V16HImode : case E_V4DFmode : case E_V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_V8QImode : case E_V4HImode : case E_V4HFmode : case E_V2SImode : case E_V2SFmode : case E_V1TImode : case E_V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } if ( error_p ) { cum -> float_in_sse =


<s> SDLoc DL ( Op ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Op ) ; assert ( LoadNode && <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( LoadNode -> getMemoryVT ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned ExtType ; if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else if ( LoadNode -> getExtensionType ( ) == <STR_LIT> || LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else return SDValue ( )


<s> O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'y' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; if ( ! isPowerOf2_64 ( MO . getImm ( ) ) ) return true ; O << Log2_64 ( MO . getImm ( ) ) ; return false ; case 'z' : if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ; case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum +


<s> static __inline qword si_ori ( qword a , unsigned int b ) { return ( ( qword ) ( vec_or ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) ( si_from_uint ( b )


<s> Type = ELF :: R_<ISA_LIT>_REL32 ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR16_HA ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR16_LO ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>64_TOC ; break ; case


<s> void <ISA_LIT>InstPrinter :: printImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> TRI = Subtarget . getRegisterInfo ( ) ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F .


<s> if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } if ( Subtarget -> isTargetILP32 ( ) && RV -> getType ( ) -> isPointerTy ( ) ) SrcReg = emitAnd_ri ( <STR_LIT> , SrcReg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT>


<s> unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal ,


<s> static SDValue LowerToTLSGeneralDynamicModel64 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { return GetTLSADDR ( DAG , DAG . getEntryNode ( ) ,


<s> rtx dest , vdest , op0 , op1 , mask , op2 , op3 ; mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else if ( mode == TFmode ) vmode = mode ; else gcc_unreachable ( ) ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } dest = operands [ <NUM_LIT> ] ; vdest = lowpart_subreg ( vmode , dest , mode ) ; if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG ,

Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> bool function_resolver :: require_matching_pointer_type ( unsigned int argno , unsigned int first_argno , type_suffix_index type ) { type_suffix_index new_type = infer_pointer_type ( argno


<s> } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = EQOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; Invert = true ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( FlipSigns ) { EVT EltVT = VT . getVectorElementType ( ) ; SDValue SignBit = DAG . getConstant ( APInt :: getSignBit ( EltVT . getSizeInBits ( ) ) , EltVT ) ; std :: vector < SDValue > SignBits ( VT . getVectorNumElements ( ) , SignBit ) ; SDValue SignVec = DAG . getNode ( <STR_LIT> , dl , VT , & SignBits [ <NUM_LIT> ] , SignBits . size ( ) ) ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , SignVec ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , SignVec ) ; } SDValue Result = DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; if ( Invert ) Result = DAG . getNOT ( dl ,


<s> return false ; } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , cast < FixedVectorType > ( VecTy ) , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , cast < FixedVectorType > ( VecTy ) , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind ,


<s> Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str


<s> Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( DestVT . bitsGT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ; return


<s> if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF


<s> bool hasSoftFloat ( ) const { return HasSoftFloat


<s> if ( Subtarget . hasAVX512 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( <NUM_LIT> << <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL


<s> for ( unsigned i = <NUM_LIT> , e = LHS . size ( ) ; i < e ; i += <NUM_LIT> ) { if ( ! isa < LoadInst > ( LHS [ i ] ) || ! isa < LoadInst > ( RHS [ i ] ) ) return false ; } } return


<s> SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_AVX512 ( Op , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements


<s> assert ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI -> getUniqueVRegDef ( AmountReg ) ; while ( Def && Def -> isCopy ( ) && Def -> getOperand ( <NUM_LIT> ) . isReg ( ) ) Def =

MRI -> getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> unsigned <ISA_LIT>InstructionSelector :: getSubOp ( LLT & Ty , const RegisterBank & RB ) const { if ( <STR_LIT> != RB . getID ( ) ) return TargetOpcode :: G_SUB ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { if ( STI . hasAVX512 ( ) && STI . hasVLX ( ) ) { return <STR_LIT>


<s> static rtx mips_force_binary ( machine_mode mode , enum rtx_code code , rtx op0 , rtx op1 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; mips_emit_binary ( code , reg , op0 , op1 ) ; return reg


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT>


<s> case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: tryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( ! <STR_LIT> ( N . getNode ( ) ) || ! IsProfitableToFold ( N , P , P ) || ! IsLegalToFold ( N , P , P , OptLevel ) ) return false ; return selectAddr ( N . getNode ( ) , N . getOperand (

<NUM_LIT> ) , Base , Scale , Index , Disp , Segment ) ;


<s> if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return RC


<s> SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT

. getVectorNumElements ( ) ) - <NUM_LIT> ;


<s> void processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { const MCSymbolRefExpr * A = Target . getSymA ( ) ; if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if (


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT>


<s> } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT> && <STR_LIT> ) ; const MachineConstantPoolEntry & CPE = MCP -> getConstants ( ) [ CPI ] ; assert ( ! CPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; Offset = - cast < ConstantInt > ( CPE . Val . ConstVal ) -> getSExtValue ( ) ; break ; } } if ( DstReg == FramePtr && FramePtr != <STR_LIT> ) ATS . emitSetFP ( FramePtr , <STR_LIT> , - Offset ) ; else if ( DstReg == <STR_LIT> ) { ATS . emitPad ( Offset ) ; } else { MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } } else if ( DstReg == <STR_LIT> ) { MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } else { MI -> dump ( )


<s> llvm :: sort ( Table ) ; assert ( std :: adjacent_find ( Table . begin ( ) , Table . end ( ) )


<s> return __builtin_aarch64_usra_ndi_uuus ( __a ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) { TCC = <STR_LIT> ; break ; } isUnsigned = true ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) { TCC = <STR_LIT> ; break ; } isUnsigned =


<s> if ( MO . isImm ( ) ) O << ( unsigned short int ) MO .


<s> if ( ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; if ( LocVT == <STR_LIT> && ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) )


<s> bool IsLargeCodeModel = MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; const char * Symbol ; if ( Is64Bit ) { if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if (


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) { return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getBitcast ( <STR_LIT> , N1 ) ) ) ; } if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; SmallVector < APInt , <NUM_LIT> > SrcPartials ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps , & SrcPartials ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineOrShiftToFunnelShift ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT>


<s> case 'h' : RC = & <STR_LIT> ; break ; case 's' : RC = & <STR_LIT> ; break ; case 'd' : RC = & <STR_LIT> ; break ; case 'q' : RC = & <STR_LIT> ; break ; case 'z' : RC = & <STR_LIT> ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; bool hasAltName ; const TargetRegisterClass * RegClass ; if ( <STR_LIT> . contains (


<s> } std :: unique_ptr < <ISA_LIT>Operand > Offset ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Operands . push_back ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , std :: move ( Offset ) ) : <STR_LIT> ( BaseReg


<s> if ( Vector && ! ST -> hasSSE1 ( ) ) return <NUM_LIT> ; if ( ST -> is64Bit ( )


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair (


<s> void crx_expand_scond ( enum rtx_code code ,


<s> <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStandardEncoding ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; return true


<s> rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval ,


<s> unsigned Imm = <STR_LIT> ( opc , PostIdxReg . ShiftImm , PostIdxReg . ShiftTy ) ; Inst . addOperand ( MCOperand :: createImm


<s> return ( Opcode == <STR_LIT> || Opcode ==


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX20Reserved ( ) ) markSuperRegs ( Reserved


<s> static uint64_t adjustFixupValue ( unsigned Kind , uint64_t Value ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT>


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) return outliner :: TargetCostInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return outliner :: TargetCostInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> ,

MachineOutlinerDefault , MachineOutlinerDefault ) ;


<s> if ( priority != DEFAULT_INIT_PRIORITY ) { char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> , is_ctor ? <STR_LIT> : <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL_TREE


<s> vpmaxnm_f32 ( float32x2_t a , float32x2_t b ) { return __builtin_aarch64_smaxpv2sf ( a , b


<s> if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRn ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRm ( MI , OpIdx ) ; if ( IsThumb ) Binary = convertNEONDataProcToThumb ( Binary ) ; emitWordLE ( Binary )


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder


<s> EVT DestEVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( DestVT != <STR_LIT> ) return false ; unsigned DivOpc ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; case


<s> if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert (


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } } if ( VT . is256BitVector ( ) ) { SDValue R = WidenMaskArithmetic ( N , DAG


<s> int FI = getStackSpaceFor ( OrigReg ) ; const TargetRegisterClass & RC = * MRI -> getRegClass ( OrigReg ) ; Register TileReg ; if ( UseMI -> isCopy ( ) ) TileReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else TileReg = MRI -> createVirtualRegister ( & RC ) ; unsigned Opc = <STR_LIT> ; Register StrideReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( * UseMI -> getParent ( ) , UseMI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , StrideReg ) . addImm ( <NUM_LIT> ) ; NewMI = addFrameReference ( BuildMI ( * UseMI -> getParent ( ) , UseMI , DebugLoc ( ) , TII -> get ( Opc ) , TileReg ) . addReg ( RowMO -> getReg ( ) ) . addReg ( ColMO -> getReg ( ) ) , FI ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( StrideReg ) ; MO . setIsKill ( true ) ; RowMO -> setIsKill ( false ) ; ColMO -> setIsKill ( false ) ; if ( UseMI -> isCopy ( )


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op ,


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget


<s> if ( TARGET_THUMB ) memcpy ( reg_alloc_order ,

thumb_core_reg_alloc_order , sizeof ( thumb_core_reg_alloc_order ) ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType (


<s> static MachineBasicBlock * EmitWRPKRU ( MachineInstr * MI , MachineBasicBlock * BB , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg


<s> static const <ISA_LIT>MCExpr * CreateLo ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_ABS_LO , Expr , Ctx


<s> } MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; Register Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; Register Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CReg ) . addReg ( Op1Reg ) ; if ( CReg != <STR_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: KILL ) , <STR_LIT> ) . addReg ( CReg , RegState :: Kill ) ; Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get

( OpReg ) , ResultReg ) . addReg ( Op0Reg ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler


<s> bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M


<s> if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes ; NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; } MBBI -> setDesc ( ZII -> get ( NewOpcode ) ) ; MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else if ( StackSize ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , StackSize , ZII


<s> MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF .


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> void <ISA_LIT>TargetELFStreamer :: finishAttributeSection ( ) { if ( FPU != <STR_LIT> ) emitFPUDefaultAttributes ( ) ; if ( Arch != <STR_LIT> ) emitArchDefaultAttributes ( ) ; if ( Contents . empty ( ) ) return ; std :: sort ( Contents . begin ( ) , Contents . end ( ) , AttributeItem :: LessTag ) ; <ISA_LIT>ELFStreamer & Streamer = getStreamer ( ) ; if ( AttributeSection ) { Streamer . SwitchSection ( AttributeSection ) ; } else { AttributeSection = Streamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeItem :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue ) ; break ; case AttributeItem :: TextAttribute : Streamer . EmitBytes ( item . StringValue . upper ( ) ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; break ; case AttributeItem :: NumericAndTextAttributes : Streamer . EmitULEB128IntValue ( item . IntValue ) ; Streamer . EmitBytes ( item . StringValue . upper (


<s> bool isAmbiguous_64 ( InstType InstTy ,


<s> for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { perm [ i * <NUM_LIT> ] = GEN_INT ( i + high ) ; perm [ i * <NUM_LIT> + <NUM_LIT> ] = GEN_INT ( i + nelt +


<s> break ; case E_V8SImode : case E_V8SFmode : case E_V4DFmode : case E_V4DImode : if ( ! TARGET_AVX ) return false ; if ( d . testing_p && TARGET_AVX512VL ) return true ; break ; case E_V16HImode : if ( ! TARGET_SSE2 ) return false ; if ( d . testing_p && TARGET_AVX2 ) return true ; break ; case E_V32QImode : if ( ! TARGET_SSE2 ) return false ; if ( d . testing_p && TARGET_AVX2 ) return true ; break ; case E_V8HImode : case E_V16QImode : if ( ! TARGET_SSE2 ) return false ; case E_V4SImode : case E_V4SFmode : if ( ! TARGET_SSE ) return false ; if ( d . testing_p && TARGET_XOP ) return true ; if ( d . testing_p && TARGET_SSSE3 ) return true ; break ; case E_V2DImode : case E_V2DFmode : if ( ! TARGET_SSE ) return false ; if ( d . testing_p ) return true ; break ; default : return false ; } for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned char e = sel [ i ] ; gcc_assert ( e < <NUM_LIT> * nelt ) ; d . perm [ i ] = e ; perm [ i ] = e ; which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( d . testing_p ) { if ( which == <NUM_LIT> ) for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which != <NUM_LIT> ) ; if ( d . one_operand_p && ( d . vmode == V4SFmode || d . vmode == V4SImode ) ) return true ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence ( ) ; bool ret = ix86_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } two_args = canonicalize_perm ( & d ) ; if ( ix86_expand_vec_perm_const_1 ( & d ) ) return true ; if ( two_args && d . one_operand_p ) { d . one_operand_p = false ; memcpy ( d . perm , perm , sizeof (


<s> x = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( x ,


<s> MBBs . resize ( NumBlocks ) ; Terminators . clear ( ) ; Terminators . reserve ( NumBlocks ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( *


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( WidthExpr , EndLoc ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( WidthExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Width = CE -> getValue ( ) ; if ( Width < <NUM_LIT> || Width > <NUM_LIT> - LSB ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBitfield ( LSB , Width , S , EndLoc ) ) ; return MatchOperand_Success


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasDSP ) { if ( Flags . empty ( ) ) return <NUM_LIT> | ( int


<s> if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . hardenSlsRetBr ( ) && isIndirectControlFlowNotComingBack ( MI


<s> static HOST_WIDE_INT sparc_gcov_type_size ( void ) { return SPARC_GCOV_TYPE_SIZE


<s> set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode ,


<s> unsigned NumElements = DataTypeVTy -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > <NUM_LIT> && isPowerOf2_64 ( NumElements ) && EltSize >= <NUM_LIT> && EltSize <= <NUM_LIT> && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore (


<s> MachineBasicBlock :: iterator NextMIIt = MachineBasicBlock :: iterator ( MI ) ; if ( isCMOVPseudo ( MI ) ) { while ( NextMIIt != ThisMBB -> end ( ) && isCMOVPseudo ( * NextMIIt ) && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CC || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) ) { LastCMOV = & * NextMIIt ; NextMIIt = next_nodbg ( NextMIIt , ThisMBB -> end ( ) ) ; } } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } auto DbgRange = llvm :: make_range ( MachineBasicBlock :: iterator ( MI ) , MachineBasicBlock :: iterator ( LastCMOV ) ) ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( DbgRange ) ) if ( MI . isDebugInstr ( ) ) SinkMBB -> push_back ( MI . removeFromParent ( ) ) ; SinkMBB -> splice ( SinkMBB -> end ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( ThisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO .


<s> return CC_DEQmode ; case LE : return CC_DLEmode ; case LT : return CC_DLTmode ; case GE : return CC_DGEmode ; case GT : return CC_DGTmode ; case LEU


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i * <NUM_LIT> + j ) , i * RHSStartValue + j + IndexOffset ) ||

! isConstantOrUndef ( N -> getMaskElt ( i * <NUM_LIT> + j + <NUM_LIT> ) , i * RHSStartValue + j + IndexOffset + <NUM_LIT> ) ) return false ;


<s> VecOp = convertToScalableVector ( DAG , ContainerVT , VecOp ) ; EVT ResVT = ( Opcode == <STR_LIT> ) ? <STR_LIT> : SrcVT . getVectorElementType ( ) ; SDValue Rdx = DAG . getNode ( Opcode , DL , getPackedSVEVectorVT ( ResVT ) , Pg , VecOp ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , ResVT , Rdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( ResVT != ScalarOp . getValueType ( ) ) Res = DAG . getAnyExtOrTrunc ( Res


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand


<s> else return false ; else if ( ! df_regs_ever_live_p ( reg ) || call_used_or_fixed_reg_p ( reg ) ) return false ; else return true


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [

RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC ) != <NUM_LIT> ) ;


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = End . getValue (


<s> return false ; } MachineInstr * FirstVCTP = * VCTPs . begin ( ) ; for ( MachineInstr * VCTP : VCTPs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VCTP ) ; if ( VCTP -> getOpcode ( ) != FirstVCTP -> getOpcode ( ) || VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) != FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } Register CountReg = FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! CountReg . isVirtual ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * Phi = LookThroughCOPY ( MRI -> getVRegDef ( CountReg ) , MRI ) ; if ( ! Phi || Phi -> getOpcode ( ) != TargetOpcode :: PHI || Phi -> getNumOperands ( ) != <NUM_LIT> || ( Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) && Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CountReg = Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == ML -> getLoopLatch ( ) ? Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) : Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = LoopStart -> getParent


<s> static __inline vec_int4 spu_subx ( vec_int4 a , vec_int4 b , vec_int4 c ) { return ( ( vec_int4 ) ( si_sfx ( ( qword ) ( b ) , ( qword ) ( a ) ,


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNsu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> for ( auto Use : Prev -> uses ( ) ) if ( Use . isKill ( ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Use . getReg ( ) , RegState :: Kill ) ) . copyImplicitOps ( & * MBBI ) ; MBB . erase (


<s> static tree rs6000_init_stack_protect_guard ( void ) { if ( rs6000_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT>


<s> if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w' )


<s> bool isUImm7Shift2 ( ) { return isUImm < <NUM_LIT> ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue (


<s> unsigned btihintop = ( MI -> getOperand ( OpNum ) . getImm ( ) ^ <NUM_LIT> ) >> <NUM_LIT> ; auto BTI = <STR_LIT> ( btihintop ) ; if ( BTI ) O << BTI -> Name ; else O << '#' << formatImm


<s> void <ISA_LIT>InstPrinterCommon :: printInstFlags ( const MCInst * MI , raw_ostream & O ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; if ( ( Flags & <STR_LIT> ) || ( TSFlags & <STR_LIT> ) ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT>


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT>


<s> int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> unsigned getMemBaseReg ( ) const { assert ( Kind == Memory


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpOffset16OpValue ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable (


<s> static void push_minipool_barrier ( rtx insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail


<s> else { if ( cfun -> machine -> call_via [ regno ] == NULL ) cfun -> machine -> call_via [ regno ] = gen_label_rtx ( ) ; labelp = cfun -> machine -> call_via + regno ; } output_asm_insn ( <STR_LIT> , labelp ) ; return <STR_LIT>


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned SizeEncoding = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; return SizeEncoding -


<s> if ( element_mode ( type ) == BFmode && op != ADDR_EXPR ) return N_ ( <STR_LIT> ) ; return NULL


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWindows


<s> InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t Imm = <NUM_LIT> ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> )


<s> default : return true ; case AsmToken :: Integer : case AsmToken :: Minus : case AsmToken :: Plus : return ( getParser ( ) . ParseExpression ( Res ) ) ; case AsmToken :: Percent : return parseRelocOperand ( Res ) ; case AsmToken ::


<s> static SDValue LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { std :: vector < MVT > VTs ; VTs . push_back ( <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate


<s> StringRef CPU = STI . getCPU ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( )

) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ;


<s> memset ( context , <NUM_LIT> , sizeof ( struct _Unwind_Context ) ) ; context -> bsp = context -> regstk_top = ( unsigned long ) bsp ; context -> psp = ( unsigned long ) psp ; context -> rp = ( unsigned long ) rp ; asm ( <STR_LIT> : <STR_LIT> ( context -> sp ) ) ; asm ( <STR_LIT> : <STR_LIT> ( context -> pr ) ) ; context -> pri_unat_loc = & context -> initial_unat ; if ( uw_frame_state_for ( context , & fs ) != _URC_NO_REASON ) abort ( ) ; uw_update_context ( context , & fs


<s> return Op ; } } unsigned int ShuffleKind = isLittleEndian ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( SVOp , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , ShuffleKind , DAG ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) ) return Op ; ArrayRef < int > PermMask = SVOp -> getMask ( ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle && ! isLittleEndian ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask


<s> if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto MatchUSUBSAT = [ ] ( ConstantSDNode * Max , ConstantSDNode * Op ) { return Max -> getAPIntValue ( ) == ( - Op -> getAPIntValue ( ) ) ; } ; if ( ! <STR_LIT> ( Op0 . getOperand ( <NUM_LIT> ) , Op1 , MatchUSUBSAT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ,


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_extract_pi16 ( __m64 const __A , int const __N ) { return ( unsigned short ) __builtin_ia32_vec_ext_v4hi ( (


<s> TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MIPeepholeOptPass (


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { std :: unique_ptr < const MCInstrInfo > MII ( T . createMCInstrInfo


<s> InVals . push_back ( FIN ) ; ReadByValArg ( MF , Chain , dl , OutChains , DAG , NumWords , FIN , VA , Flags , & * FuncArg ) ; continue ; } if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; LastFI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( LastFI ) , false , false , false , <NUM_LIT> ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , Chain ) ; } if ( isVarArg ) { unsigned RegSize = <STR_LIT> . getSize ( ) ; int FirstVaArgOffset = RegSize ; LastFI = MFI -> CreateFixedObject ( RegSize , FirstVaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( LastFI ) ; } <ISA_LIT>FI -> setLastInArgFI ( LastFI ) ; if ( ! OutChains .


<s> MCSymbolRefExpr :: VariantKind <ISA_LIT>AsmParser :: getVariantKind ( StringRef Symbol ) { MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_PLT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr ::

VK_<ISA_LIT>_GOTPCHI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCLO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFHI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFLO ) . Default ( MCSymbolRefExpr :: VK_None ) ;


<s> static bool isIndirectBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] <


<s> LLVM_DEBUG ( if ( Start ) dbgs ( ) << <STR_LIT> << * Start ; if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; ) ; if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } else if ( ! ( Start && Dec && End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true


<s> UNW_DEC_PROLOGUE ( R3 , ( ( code & <NUM_LIT> ) == <NUM_LIT> ) , rlen , arg ) ; return dp


<s> for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> isDeclaration ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; if ( usingMask ) { if ( functionIndex == <ISA_LIT>32FunctionMask . length ( ) ) functionIndex = <NUM_LIT> ; if ( <ISA_LIT>32FunctionMask [ functionIndex ] == '1' ) { DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; F -> addFnAttr ( <STR_LIT> ) ; } functionIndex ++ ; } else { if ( needsFP ( * F


<s> if ( LABEL_P ( lab ) && LABEL_NUSES ( lab ) < uses_threshold ) return <NUM_LIT> ; if ( optimize_size ) return <NUM_LIT> ; if ( rx_cpu_type == RX100 || rx_cpu_type


<s> return __arm_vstrwq_p_s32 ( __addr ,


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_iOS_CXX_TLS_ViaCopy_SaveList ; return nullptr


<s> if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ; } EVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = VecIns . size ( ) ; i < e ; ++ i ) VecIns [ i ] = DAG . getBitcast ( TestVT , VecIns [ i ] ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [ Slot ] ; SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> , DL


<s> if ( ! dominated_by_p ( CDI_POST_DOMINATORS , bb ,


<s> if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( atomicBarrierDroppedOnZero ( MI . getOpcode ( ) ) || atomicReadDroppedOnZero ( MI . getOpcode ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; for ( int I = <NUM_LIT> , E = Desc . getNumDefs ( ) ; I != E ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) || ( ! MO . isDead ( ) && ! MRI -> use_nodbg_empty ( Reg ) ) ) continue ; assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { LLVM_DEBUG ( dbgs (


<s> if ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; } return new <ISA_LIT>AsmInstrumentation


<s> uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else


<s> MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg


<s> __rint64zf ( float __a ) { return __builtin_aarch64_frint64zsf (


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> auto TheReg = <STR_LIT> ( RegName . lower ( ) ) ; if ( ! TheReg ) return MatchOperand_NoMatch ; unsigned Encoding = TheReg -> Encoding ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBankedReg ( Encoding


<s> if ( Prev -> getOpcode ( ) != <STR_LIT> || ! Prev -> definesRegister ( <STR_LIT> ) ) return false ; for ( auto Use : Prev -> uses ( ) ) if ( Use . isKill ( ) ) { assert ( STI -> hasV4TOps ( ) ) ; BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Use . getReg ( ) , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase (


<s> HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasMPX =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Test ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: And ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Cmp ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>SEFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo (


<s> if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> ,


<s> static DecodeStatus DecodeAddrMode5FP16Operand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( U ) Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> ,


<s> EVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ]


<s> Out . EmitInstruction ( Inst , SubtargetInfo ) ; Opcode = Inst . getOpcode ( ) ; return false ; case Match_MissingFeature : return Error ( IdLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IdLoc , <STR_LIT> ) ; case Match_InvalidOperand : { ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands


<s> else O << '#' << formatDec ( Value ) ; if ( CommentStream ) { if ( getPrintImmHex ( ) ) * CommentStream << '=' << formatDec ( HexValue ) << '\n' ; else * CommentStream << '=' << formatHex ( ( uint64_t ) Value


<s> if ( CXXEHRegistrationTy ) return CXXEHRegistrationTy ; LLVMContext & Context = TheModule -> getContext ( ) ; Type * FieldTys [ ] = { Type :: getInt8PtrTy ( Context ) , getEHLinkRegistrationType ( ) , Type ::


<s> case FCOND_OGE : return <STR_LIT> ; case FCOND_OLE : case FCOND_UGT : return <STR_LIT> ; case FCOND_ULE : case FCOND_OGT : return <STR_LIT> ; case FCOND_SF : case FCOND_ST : return <STR_LIT> ; case FCOND_NGLE : case FCOND_GLE : return <STR_LIT> ; case FCOND_SEQ : case FCOND_SNE : return <STR_LIT> ; case FCOND_NGL : case FCOND_GL : return <STR_LIT> ; case FCOND_LT : case FCOND_NLT : return <STR_LIT> ; case


<s> return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> } MachineInstr * Prev = VCTPs . back ( ) ; if ( ! Prev -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( MI -> getOperand ( <NUM_LIT> ) ) || ! RDA . hasSameReachingDef ( Prev , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } VCTPs . push_back ( MI ) ; return true


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseOperand ( ) { if ( getParser ( ) . getAssemblerDialect ( )


<s> bool hasCLDEMOTE ( ) const { return HasCLDEMOTE


<s> for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( ! isUndefOrZero ( Mask [ i ] ) ) return false ; return true


<s> vtrn_u16 ( uint16x4_t a , uint16x4_t b ) { return ( uint16x4x2_t ) { vtrn1_u16 ( a , b


<s> bool is31 = needsFP ( MF ) ; unsigned FPReg = is31 ? <STR_LIT> : <STR_LIT> ; unsigned FP8Reg = is31 ? <STR_LIT> : <STR_LIT> ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( )


<s> static bool isMaskedZeroUpperBitsvXi1 ( unsigned int Opcode ) { switch ( Opcode ) { default : return false ; case


<s> static <ISA_LIT>Operand * CreateMem ( unsigned SegReg , const MCExpr * Disp , unsigned BaseReg , unsigned IndexReg , unsigned Scale , SMLoc StartLoc , SMLoc EndLoc , unsigned Size = <NUM_LIT> , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { assert ( ( SegReg || BaseReg || IndexReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Memory ,


<s> static inline uint64_t decodeAdvSIMDModImmType6 ( uint8_t Imm ) { uint64_t EncVal = Imm


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const


<s> return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( Vec . isUndef ( ) || Vec . getOpcode ( ) == <STR_LIT> ) && SubVec . getOpcode ( ) == <STR_LIT> ) { SDValue VecSrc = peekThroughBitcasts ( Vec ) ; SDValue SubVecSrc = peekThroughBitcasts ( SubVec ) ; MVT VecSrcSVT = VecSrc . getSimpleValueType ( ) . getScalarType ( ) ; MVT SubVecSrcSVT = SubVecSrc . getSimpleValueType ( ) . getScalarType ( ) ; if ( Vec . isUndef ( ) || VecSrcSVT == SubVecSrcSVT ) { MVT NewOpVT ; SDValue NewIdx ; unsigned NumElts = OpVT . getVectorNumElements ( ) ; unsigned EltSizeInBits = OpVT . getScalarSizeInBits ( ) ; if ( ( EltSizeInBits % SubVecSrcSVT . getSizeInBits ( ) ) == <NUM_LIT> ) { unsigned Scale = EltSizeInBits / SubVecSrcSVT . getSizeInBits ( ) ; NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts * Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal * Scale , dl ) ; } else if ( ( SubVecSrcSVT . getSizeInBits ( ) % EltSizeInBits ) == <NUM_LIT> ) { unsigned Scale = SubVecSrcSVT . getSizeInBits ( ) / EltSizeInBits ; if ( ( IdxVal % Scale ) == <NUM_LIT> ) { NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts / Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal / Scale , dl ) ; } } if ( NewIdx && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , NewOpVT ) ) { SDValue Res = DAG . getBitcast ( NewOpVT , VecSrc ) ; Res = DAG . getNode ( <STR_LIT> , dl , NewOpVT , Res , SubVecSrc , NewIdx ) ; return DAG . getBitcast ( OpVT , Res ) ; } } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { if ( isNullConstant ( Vec . getOperand ( <NUM_LIT> ) ) ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Fold = combineConcatVectorOps ( dl , OpVT , Ops , DAG , DCI , Subtarget ) ) return Fold ; if ( ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF ( OpVT )

, SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ;


<s> d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( REGNO_REG_SET_P ( regs_invalidated_by_call_regset , GBR_REG ) ) return NULL_RTX ; else continue ; } else return NULL_RTX ; } rtx disp = GEN_INT ( gbr_disp . disp ( ) ) ; if ( gbr_displacement ( disp , GET_MODE ( mem ) ) ) return gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , GBR_REG ) , disp ) ; } return NULL_RTX


<s> return ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) )


<s> return ( __m256i ) __builtin_ia32_expandloaddi256_mask ( ( __v4di * ) __P , ( __v4di ) __W , (


<s> b = ( __vector unsigned short ) vec_splats ( __B ) ; c = vec_avg ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128


<s> return ( __m128i ) vec_packsu ( ( __v4si ) __X , ( __v4si )


<s> bool hasFP ( const MachineFunction & MF ) const override { return true


<s> return ( unsigned char ) __builtin_ia32_kortestcdi ( __A


<s> static void clearHighBits ( const MCOperand & Reg , MCStreamer & Out , const MCSubtargetInfo & STI ) { MCInst Mov


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall (


<s> return & InstrInfo -> getRegisterInfo (


<s> StringRef getPassName ( ) const override { return


<s> TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue HiDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc , LoDesc , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SymAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> ) ; TPOff = LowerTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue HiDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc , LoDesc , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; ThreadBase = LowerTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL


<s> GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry , dl , DAG ) ; return CallResult . first ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry , dl , DAG ) ; SDValue TLSAddr = CallResult . first ; SDValue Chain = CallResult . second ; SDValue DtvOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , Chain , TLSAddr , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DtvOffsetHi , TGA ) ; } llvm_unreachable (


<s> if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Size ) ; } const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> ,


<s> if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual (

N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ UseWReg ] [ IsNegative ] ; auto TestBitMI = MIB . buildInstr ( Opc ) . addReg ( TestReg ) . addImm ( Bit ) . addMBB ( DstMBB ) ; constrainSelectedInstRegOperands ( * TestBitMI , TII


<s> return __builtin_mve_vmulhq_uv4si ( __a ,


<s> void addShifterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << <STR_LIT>


<s> inline int vec_any_nan ( vector float


<s> fprintf ( stderr , <STR_LIT> , subtree -> str ) ; rbt_dump ( t , subtree -> right


<s> static __inline qword si_shlh ( qword a , qword b ) { vec_ushort8 mask ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( ( vec_ushort8 ) ( b

) , vec_splat_u16 ( <NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ;


<s> return ( __m128i ) __builtin_ia32_pmaxud128 ( ( __v4si ) __X ,


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) ||

( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> unsigned OpCode = MI -> getOpcode ( ) ; switch ( OpCode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ShapeT Shape = getTileShape ( SrcReg , VRM , MRI ) ; VRM -> assignVirt2Shape ( VirtReg , Shape ) ; return Shape ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I )


<s> case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC (


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm ->


<s> rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ; x = expand_simple_binop ( SImode , IOR , newval , x , x


<s> SDNode * N = Use -> getOperand ( i ) . getNode ( ) ; if ( N == Def ) { if ( Use == ImmedUse || Use == Root ) continue ; assert ( N != Root ) ; return true ; } if ( findNonImmUse ( N , Def , ImmedUse , Root , Visited ) )


<s> rtx swap_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= <NUM_LIT> ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST


<s> else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onOr ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onLShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onRShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onXor ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onAnd ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onMod ( ) ; else return false ; return true


<s> } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg = N ; return


<s> const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return <NUM_LIT> ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return <NUM_LIT> ; switch ( MBBI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SmallVector < Value * , <NUM_LIT> > Args ; if ( EscapeCall ) { auto Ops = EscapeCall -> arg_operands ( ) ; Args . append ( Ops . begin ( ) , Ops . end ( ) ) ; } Args . push_back ( RegNode ) ; IRBuilder < > Builder ( & F . getEntryBlock ( ) , EscapeCall ? EscapeCall : F . getEntryBlock ( ) . end