<s> assert ( <NUM_LIT> <= FirstIndex && FirstIndex < <NUM_LIT> && <STR_LIT> ) ; int FirstElt = Mask [ FirstIndex ] ; if ( all_of ( Mask , [ FirstElt ] ( int M ) { return M < <NUM_LIT> || M == FirstElt ; } ) ) return ( FirstElt << <NUM_LIT> ) | ( FirstElt << <NUM_LIT> ) | ( FirstElt << <NUM_LIT> ) | FirstElt ; unsigned Imm = <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; return Imm


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand (


<s> { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex


<s> enum reg_class mips_preferred_reload_class ( rtx x , enum reg_class class ) { if ( mips_dangerous_for_la25_p ( x ) && reg_class_subset_p ( LEA_REGS , class ) )


<s> unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned ArgIdx = i - CS . arg_begin ( ) ; if ( CS . paramHasAttr ( ArgIdx , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( ArgIdx , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( ArgIdx , Attribute :: InReg ) || CS . paramHasAttr ( ArgIdx , Attribute :: StructRet ) || CS . paramHasAttr ( ArgIdx , Attribute :: SwiftSelf ) || CS . paramHasAttr ( ArgIdx , Attribute :: SwiftError ) || CS . paramHasAttr ( ArgIdx , Attribute :: Nest ) || CS . paramHasAttr ( ArgIdx , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV ,


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( )


<s> if ( rs6000_cpu == PROCESSOR_PPC620 || rs6000_cpu == PROCESSOR_PPC630 || rs6000_cpu == PROCESSOR_RS64A ) return <STR_LIT> ; HOST_WIDE_INT flags = rs6000_isa_flags ; flags &= ~ ( OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL ) ; if ( ( flags & ( ISA_3_1_MASKS_SERVER & ~ ISA_3_0_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_3_0_MASKS_SERVER & ~ ISA_2_7_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_7_MASKS_SERVER & ~ ISA_2_6_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_6_MASKS_SERVER & ~ ISA_2_5_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_5_MASKS_SERVER & ~ ISA_2_4_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_4_MASKS & ~ ISA_2_1_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ISA_2_1_MASKS ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) return <STR_LIT> ; return


<s> static bool supportedVectorVarShift ( MVT VT , const <ISA_LIT>Subtarget & Subtarget , unsigned Opcode ) { if ( ! Subtarget . hasInt256 ( ) || VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector


<s> return LowerSymbolOperand ( MI , MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand ::


<s> if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; return res > <NUM_LIT> ? DOUBLEWORD_ALIGNMENT : PARM_BOUNDARY


<s> assert ( ( Kind == k_Register || Kind == k_CCOut )


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode


<s> static bool ix86_rop_should_change_byte_p ( int


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI ,

MODE_32BIT , T . createMCInstrInfo ( ) ) ;


<s> EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value ,


<s> MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) ,


<s> SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( Res . getNode ( ) ) for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ;

++ I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> if ( add ) { if ( add > <NUM_LIT> ) fputc ( '+' , stream ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , add ) ; } if ( * reloc ) fputc


<s> static void report_non_ice ( location_t location , tree fndecl , unsigned int argno


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; case <STR_LIT> : \ return <STR_LIT> #


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val > High ) { Error ( Loc , <STR_LIT>


<s> } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = <NUM_LIT> ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - <NUM_LIT> ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - <NUM_LIT> ] . value ) ) { lab = <NUM_LIT> ; pool_vector [ pool_size - <NUM_LIT> ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == <NUM_LIT> ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size


<s> unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( regs == <NUM_LIT> || ( Vd + regs ) > <NUM_LIT> ) { regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ; S = MCDisassembler :: SoftFail ; } if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } return S


<s> unsigned Opc = cast < Instruction > ( V ) -> getOpcode ( ) ; return Opc == Instruction :: AShr || Opc == Instruction :: SDiv || Opc


<s> Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ( ( ( FrameReg != <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) || ( ( FrameReg == <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false ,


<s> return getTargetMachine ( ) . getSubtargetImpl ( ) ->


<s> void <ISA_LIT>InstPrinter :: printFBits16 ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . getAlignment ( ) , Nd . getMemOperand ( ) -> getFlags ( ) ) ; Ptr = DAG . getPointerAdd ( DL , Ptr , <NUM_LIT> ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) , Nd . getMemOperand ( ) -> getFlags ( ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; SDValue BP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Ops [ <NUM_LIT> ] = { BP , Hi . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues (


<s> <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx )


<s> static __inline void sh_media_FTRV_S ( const void * mtrxg , const void * fvh , void * fvf ) { typedef float v16sf __attribute__ ( ( mode ( V16SF ) ) ) ; typedef float v4sf __attribute__ ( ( mode ( V4SF ) ) ) ; v16sf mtrx = * ( v16sf * ) mtrxg ; v4sf vh = * ( v4sf *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return true


, ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ; if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> ,


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT>


<s> <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , <NUM_LIT> ) ; } MFI -> setAdjustsStack ( true ) ; SDValue Flag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , ReturnReg , PtrVT


<s> static SDValue reduceMaskedLoadToScalarLoad ( MaskedLoadSDNode * ML , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Addr , VecIndex ; unsigned Alignment ; if ( ! getParamsForOneTrueMaskedElt ( ML , DAG , Addr , VecIndex , Alignment ) ) return SDValue ( ) ; SDLoc DL ( ML ) ; EVT VT = ML -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VT . getVectorElementType ( ) ; SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML -> getPointerInfo ( ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , VT , ML -> getPassThru ( ) , Load


<s> if ( ! isMemory ( ) || ! getMemOffsetIsReg ( ) || getMemWriteback ( )


<s> return MLI -> isLoopHeader ( Header ) && MLI -> getLoopFor ( Header ) ->


<s> auto_sbitmap to_clear_bitmap ( maxregno + <NUM_LIT> ) ; rtx r1_reg , result_rtl , clearing_reg = NULL_RTX ; tree result_type ; bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , NUM_ARG_REGS ) ; bitmap_set_bit ( to_clear_bitmap , IP_REGNUM ) ; if ( TARGET_HARD_FLOAT ) { int float_bits = D7_VFP_REGNUM - FIRST_VFP_REGNUM + <NUM_LIT> ; bitmap_set_range ( to_clear_bitmap , FIRST_VFP_REGNUM , float_bits ) ; emit_use ( gen_rtx_REG ( SImode , IP_REGNUM ) ) ; bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( call_used_regs [ regno ] ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } } if ( padding_bits_to_clear != <NUM_LIT> ) { int to_clear_bitmap_size = SBITMAP_SIZE ( ( sbitmap ) to_clear_bitmap ) ; auto_sbitmap to_clear_arg_regs_bitmap ( to_clear_bitmap_size ) ; bitmap_clear ( to_clear_arg_regs_bitmap ) ; bitmap_set_range ( to_clear_arg_regs_bitmap , R1_REGNUM , NUM_ARG_REGS - <NUM_LIT> ) ; gcc_assert ( bitmap_subset_p ( to_clear_arg_regs_bitmap , to_clear_bitmap ) ) ; } clearing_reg = gen_rtx_REG ( SImode , TARGET_THUMB1 ? R0_REGNUM : LR_REGNUM ) ; r1_reg = gen_rtx_REG ( SImode , R0_REGNUM + <NUM_LIT>


<s> return ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) ->

getTypeAllocSize ( CN -> getType ( ) ) ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx )


<s> TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) { Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) && ! AFI -> shouldSignReturnAddress ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll (


<s> if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; Src = peekThroughOneUseBitcasts ( Src ) ; if ( Src . getOpcode ( ) != <STR_LIT> || Src . getScalarValueSizeInBits ( ) != ( EltSizeInBits * Scale ) ) return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; bool UndefUppers = isUndefInRange ( Mask ,


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; return


<s> unsigned NumOfLParen = <NUM_LIT> ; while ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; ++ NumOfLParen ; } switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken ::


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseGPR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int )


<s> case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align =


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF , false ) ; int NegFrameSize = - FrameSize ; bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( )


<s> return new pass_analyze_swaps ( m_ctxt


<s> DebugLoc dl = Op . getDebugLoc ( ) ; Constant * C = N -> getConstVal ( ) ; SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi


<s> return ( __m256 ) __builtin_ia32_vfmaddsubps256_mask ( ( __v8sf ) __A , ( __v8sf )


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Options . isReorder ( )


<s> std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr


<s> O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) ,


<s> return CurDAG -> getTargetConstant ( Imm


<s> return <NUM_LIT> ; } if ( ST -> is<ISA_LIT>64 ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> bool <ISA_LIT>LoadStoreOpt :: MergeOps ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int Offset , unsigned Base , bool BaseKill , int Opcode , <STR_LIT> Pred , unsigned PredReg , unsigned Scratch , DebugLoc dl , SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > & Regs ) { unsigned NumRegs = Regs . size ( ) ; if ( NumRegs <= <NUM_LIT> ) return false ; <STR_LIT> Mode = <STR_LIT> ; bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; bool haveIBAndDA = isNotVFP && ! isThumb2 ; if ( Offset == <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP ) Mode = <STR_LIT> ; else if ( Offset != <NUM_LIT> ) { if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base =


<s> for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( Cs ) ; } std :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front (


<s> __builtin_ia32_pmovsdw256mem_mask ( ( __v8hi * ) __P , ( __v8si )


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return STI . getFramePointerReg ( ) ; return


<s> } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT

) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ;


<s> } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl

, <STR_LIT> , LHS , getI64Imm ( SImm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;


<s> unsigned Reg = <NUM_LIT> ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ; getStreamer ( ) . emitWinCFIPushReg ( Reg


<s> if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) || Subtarget -> hasAVX512 ( ) ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( )


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += NextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; Res = evaluateRelocExpr ( IdVal , Str


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow =


<s> int label_num = constants ? CODE_LABEL_NUMBER ( constants -> label ) : <NUM_LIT> ; struct mips16_constant * c , * next ; int align ; align = <NUM_LIT> ; if ( constants ) insn = emit_insn_after ( gen_consttable ( GEN_INT ( label_num ) ) , insn ) ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBZDisplacementBits ; case <STR_LIT> : case <STR_LIT> : case


<s> for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = & * MBBI ++ ; if ( ! MI -> isCopy ( ) ) continue ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstReg . isVirtual ( ) && ( SrcReg == <STR_LIT> || <STR_LIT> . contains ( SrcReg ) ) ) { Register Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) ; else BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( SrcReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Tmp ) ; Modified = true ; } else if ( SrcReg . isVirtual ( ) && <STR_LIT> . contains ( DstReg ) ) { Register Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Tmp ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( Tmp ) ; Modified = true ; } } return


<s> emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , <NUM_LIT> ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT (


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> , DirectiveID . getLoc


<s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) ,


<s> case <ISA_LIT>MCExpr :: MEK_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_CALL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : { if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr ::


<s> int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isCallingConvWin64 ( F -> getFunction ( ) -> getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg

( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG ,


<s> RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { return false ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) )


<s> <STR_LIT> CC = ( <STR_LIT> ) SetCC . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = SetCC . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue NewCmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CmpOp0 , DAG . getConstant ( <NUM_LIT> , CmpOp0 . getValueType ( ) ) ) ; SDValue OtherVal = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( - <NUM_LIT> , OtherVal . getValueType


<s> <ISA_LIT>ProcFamilyEnum getProcFamily ( ) const { return <ISA_LIT>ProcFamily


<s> case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performCIncOffsetToCandAddrCombine ( N , DAG , DCI , Subtarget ) ; case


<s> return hasFMA ( ) || hasFMA4 ( ) || hasAVX512


<s> if ( ( DestVT != <STR_LIT> ) && ( DestVT != <STR_LIT> ) ) return false ; if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) return emitIntSExt32r2 ( SrcVT , SrcReg , DestVT ,


<s> uint32_t Binary = <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( Op ) ; uint32_t Reg = getMachineOpValue ( MI , MO ) ; Binary |= ( Reg << <NUM_LIT> ) ; if ( MO . isReg ( ) ) { const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( uint32_t ImmOffs = <STR_LIT> ( MO1 . getImm ( ) ) ) { if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) Binary |= <NUM_LIT> << <NUM_LIT> ; Binary |= ImmOffs & <NUM_LIT> ; return


<s> } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onXor ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onAnd ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onMod ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SMLoc OffsetLoc = getTok ( ) . getLoc ( ) ; const MCExpr * Val = nullptr ; StringRef ID ; InlineAsmIdentifierInfo Info ; ParseError = ParseIntelOffsetOperator ( Val , ID , Info , End ) ; if ( ParseError


<s> const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void emitInlineAsmStart ( const MCSubtargetInfo & StartInfo ) const override ; void emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const override ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char


<s> I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB )


<s> return isGeneric ( ) || isCortexA53 ( ) || isCortexA57


<s> return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter ::


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc dl = MBB . findDebugLoc ( MI ) ; MachineBasicBlock * BB = & MBB ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * syscallMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ( BB -> getIterator ( ) ) ; MF . insert ( It , syscallMBB ) ; MF . insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( syscallMBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = syscallMBB ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm

( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i )


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> (


<s> return AsmPrinter . MMI -> getObjFileInfo <


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget -> is64Bit ( ) ) return ; <ISA_LIT>MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return


<s> return GV != <NUM_LIT> || CP != <NUM_LIT> || ES


<s> } else O << Name ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; if ( GV -> hasExternalWeakLinkage ( ) ) ExtWeakSymbols . insert ( GV ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; if ( isCallOp && Subtarget -> isTargetDarwin ( ) && TM . getRelocationModel ( ) != Reloc :: Static ) { printSuffixedName ( Name , <STR_LIT> ) ; FnStubs . insert ( Name ) ; } else O << Name ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand ::


<s> const char * output_branchy_insn ( enum rtx_code code , const char * template , rtx insn , rtx * operands ) { rtx next_insn = NEXT_INSN ( insn ) ; if ( next_insn && GET_CODE ( next_insn ) == JUMP_INSN && condjump_p ( next_insn ) ) { rtx src = SET_SRC ( PATTERN ( next_insn ) ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != code ) { operands [ <NUM_LIT> ] = gen_label_rtx ( ) ; emit_label_after ( operands [ <NUM_LIT> ] , next_insn ) ; INSN_ADDRESSES_NEW ( operands [ <NUM_LIT> ] , INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + get_attr_length ( next_insn ) ) ; return template


<s> case <STR_LIT> : Size = <NUM_LIT> ; break ; } uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; if ( Subtarget . isThumb ( ) && Size == <NUM_LIT> ) { EmitConstant ( Binary >> <NUM_LIT> , <NUM_LIT> , OS ) ; EmitConstant ( Binary & <NUM_LIT> , <NUM_LIT> , OS ) ; } else EmitConstant ( Binary , Size ,


<s> return VT . isSimple ( ) || ! isOperationExpand ( Opcode


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return


<s> set_conv_libfunc ( trunc_optab , XFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , TImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , TImode


<s> if ( TARGET_ARCH32 ) return ( TYPE_MODE ( type ) == BLKmode || TYPE_MODE ( type ) == TFmode || ( TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) ; else return ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type )


<s> if ( i == <NUM_LIT> && isThisReturn ) { assert ( ! VA . needsCustom ( ) && VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) && ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue


<s> DiagnosticPredicate isSVEDataVectorRegOfWidth ( ) const { if ( Kind != k_Register || Reg . Kind != RegKind :: SVEDataVector ) return DiagnosticPredicateTy :: NoMatch ; if ( isSVEVectorReg < Class > ( ) && Reg . ElementWidth == ElementWidth ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy


<s> emitInst ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( CLI . Ins , RetCC_<ISA_LIT> , CLI . RetTy , CLI . Symbol ? CLI . Symbol -> getName ( ) . data ( ) : nullptr ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; if ( ! ResultReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ]


<s> } else { beyond = next_active_insn ( XEXP ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( beyond && ( GET_CODE ( beyond ) == JUMP_INSN || ( ( beyond = next_active_insn ( beyond ) ) && GET_CODE ( beyond ) == JUMP_INSN ) ) && GET_CODE ( PATTERN ( beyond ) ) == SET && recog_memoized ( beyond ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( beyond ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( beyond , INSN_ADDRESSES ( INSN_UID ( beyond ) ) , <NUM_LIT> ) ; } next = next_active_insn ( insn ) ; if ( ( GET_CODE ( next ) == JUMP_INSN || ( ( next = next_active_insn ( next ) ) && GET_CODE ( next ) == JUMP_INSN ) ) && GET_CODE ( PATTERN ( next ) ) == SET && recog_memoized ( next ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( next ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( next , INSN_ADDRESSES ( INSN_UID ( next ) ) , <NUM_LIT> ) ; } else if ( type == TYPE_JUMP || type == TYPE_RETURN ) { int addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; rtx far_label = <NUM_LIT> ; int dest_uid = <NUM_LIT> ; struct far_branch * bp ; if ( type == TYPE_JUMP ) { far_label = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; dest_uid = get_dest_uid ( far_label , max_uid ) ; if ( ! dest_uid ) { if ( ! NEXT_INSN ( far_label ) ) continue ; if ( ! optimize ) { JUMP_LABEL ( insn


<s> n = <NUM_LIT> ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++ ] = VSX_REGS ; else { if ( TARGET_ALTIVEC ) pressure_classes [ n ++ ] = ALTIVEC_REGS ; if ( TARGET_HARD_FLOAT && TARGET_FPRS ) pressure_classes [ n ++ ] = FLOAT_REGS ; } pressure_classes [ n ++ ] =


<s> unsigned Base , Index ; const MCExpr * Disp ; const MCExpr * Length ; if ( parseAddress ( Base , Disp , Index , Length , Regs , RegKind ) ) return MatchOperand_ParseFail ; if ( Index && MemKind != BDXMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem


<s> return ( uint32x2_t ) __builtin_aarch64_sqmovunv2di (


<s> needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) || F -> hasFnAttr


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> Cond = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( SDValue V = performSetCCPunpkCombine ( N , DAG ) ) return V ; if ( Cond == <STR_LIT> && isZerosVector ( RHS . getNode ( ) ) && LHS -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) ) { if ( LHS -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) == Pred ) return LHS -> getOperand ( <NUM_LIT> ) ; if ( isAllActivePredicate ( DAG , Pred ) ) return LHS -> getOperand ( <NUM_LIT> ) ; if ( DCI . isAfterLegalizeDAG ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , LHS -> getOperand


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateTokenWithStringCopy ( StringRef Str , SMLoc S , bool Is<ISA_LIT>64 ) { void * Mem = :: operator new ( sizeof ( <ISA_LIT>Operand ) + Str . size ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( new ( Mem ) <ISA_LIT>Operand ( Token ) ) ; Op -> Tok . Data = reinterpret_cast < const char * > ( Op . get ( ) + <NUM_LIT> ) ; Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( const_cast < char * > ( Op -> Tok . Data ) , Str . data ( ) , Str . size ( ) ) ; Op -> StartLoc = S


<s> TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; SchedModel . init (


<s> return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI


<s> if ( ABI . IsN64 ( ) && isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding (


<s> <ISA_LIT>LegalizerInfo :: <ISA_LIT>LegalizerInfo ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>TargetMachine & TM ) : Subtarget ( STI ) , TM ( TM ) { setLegalizerInfo32bit ( ) ; setLegalizerInfo64bit ( ) ; setLegalizerInfoSSE1 ( ) ; setLegalizerInfoSSE2 ( ) ; setLegalizerInfoSSE41 ( ) ; setLegalizerInfoAVX ( ) ; setLegalizerInfoAVX2 ( ) ; setLegalizerInfoAVX512 ( ) ; setLegalizerInfoAVX512DQ ( ) ; setLegalizerInfoAVX512BW ( ) ; getActionDefinitionsBuilder ( G_INTRINSIC_ROUNDEVEN ) . scalarize ( <NUM_LIT> ) . minScalar ( <NUM_LIT> , LLT :: scalar (


<s> static inline int getFP64Imm ( const


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Sub = N -> getOperand ( <NUM_LIT> ) ; const APInt & Idx = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; EVT VT = Src . getValueType ( ) ; EVT SubVT = Sub . getValueType ( ) ; if ( VT . getSizeInBits ( ) == ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) ) { if ( Idx == <NUM_LIT> && Src . isUndef ( ) ) { Ops . push_back ( Sub ) ; Ops . push_back ( DAG . getUNDEF ( SubVT ) ) ; return true ; } if ( Idx == ( VT . getVectorNumElements ( ) / <NUM_LIT> ) ) { if ( Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == SubVT && isNullConstant ( Src . getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( Src . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Sub ) ; return true ; } if ( Sub . getOpcode ( ) == <STR_LIT> && Sub . getOperand ( <NUM_LIT> ) == Src && isNullConstant ( Sub . getOperand ( <NUM_LIT> ) ) ) { Ops . append ( <NUM_LIT> , Sub ) ; return true ; } if ( Src . isUndef ( ) ) { Ops . push_back ( DAG . getUNDEF ( SubVT ) ) ; Ops . push_back ( Sub ) ; return true ; } } } } return


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && !


<s> return MCSymbolRefExpr :: create ( Context . getOrCreateSymbol ( Name ) , MCSymbolRefExpr ::


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> MVT VT = DataToStore . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; SDLoc dl ( Op ) ; assert ( ( ! N -> isCompressingStore ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isCompressingStore ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask , N

-> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> isTruncatingStore ( ) , N -> isCompressingStore ( ) ) ;


<s> SMLoc NumBytesLoc , ControlLoc ; const MCSubtargetInfo STI = getSTI ( ) ; NumBytesLoc = getTok ( ) . getLoc ( ) ; if ( getParser ( ) . checkForValidSection ( ) || getParser ( ) . parseAbsoluteExpression ( NumBytes ) ) return true ; if ( parseOptionalToken ( AsmToken :: Comma ) ) { ControlLoc = getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Control ) ) return true ; } if ( getParser ( ) . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( NumBytes <= <NUM_LIT> ) { Error ( NumBytesLoc , <STR_LIT>


<s> if ( shift ) { if ( val != - <NUM_LIT> ) operands [ <NUM_LIT> ] = GEN_INT ( val ) ; sprintf ( pattern , <STR_LIT> , shift , c ) ; } else sprintf ( pattern , <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_expandloadqi256_maskz ( ( const __v32qi * ) __B , (


<s> if ( ! isExtend ( ) ) return false ; <STR_LIT> ET = getShiftExtendType


<s> if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ UOps ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : UOps += <NUM_LIT> ; break ; } return UOps ; } else if ( Subtarget . isCortexA8 ( ) || Subtarget


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholeOptPass ( ) { return new <ISA_LIT>MIPeepholeOpt


<s> poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> ) ) ; return aarch64_sve_data_mode ( m_to_mode , nunits


<s> void addGPR32NonZeroAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( ! Gep || Gep -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return None ; if ( ! MRI . hasOneUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder


<s> uint64_t ValSize = VA . getValVT ( ) . getFixedSizeInBits ( ) ; uint64_t LocSize = VA . getLocVT ( ) . getFixedSizeInBits ( ) ; assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize <


<s> Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , RetTy

, Callee , std :: move ( Args ) , <NUM_LIT> ) ;


<s> if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode || GET_MODE ( SUBREG_REG ( op ) ) == IFmode || GET_MODE (

SUBREG_REG ( op ) ) == KFmode ) ) return true ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < <NUM_LIT>

) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ;


<s> void <ISA_LIT>CCState :: PreAnalyzeReturnValue


<s> else if ( orig_tune_defaulted ) opts -> x_ix86_tune_string = NULL ; if ( enum_opts_set . x_ix86_fpmath ) opts_set -> x_ix86_fpmath = ( enum fpmath_unit ) <NUM_LIT> ; else if ( ! TARGET_64BIT_P ( opts -> x_ix86_isa_flags ) && TARGET_SSE_P ( opts -> x_ix86_isa_flags ) ) { if ( TARGET_80387_P ( opts -> x_target_flags ) ) opts -> x_ix86_fpmath = ( enum fpmath_unit ) ( FPMATH_SSE | FPMATH_387 ) ; else opts -> x_ix86_fpmath = ( enum fpmath_unit ) FPMATH_SSE ; opts_set -> x_ix86_fpmath = ( enum fpmath_unit ) <NUM_LIT> ; } ix86_option_override_internal ( false , opts , opts_set ) ; ix86_add_new_builtins ( opts -> x_ix86_isa_flags ) ; t = build_target_option_node ( opts


<s> virtual unsigned int execute ( function * ) { timevar_push ( TV_MACH_DEP


<s> MCFragment * findAssociatedFragment ( ) const override { return nullptr


<s> SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) || Subtarget -> isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false


<s> } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } if ( std :: any_of ( RepeatedSequenceLocs [ <NUM_LIT> ] . first , RepeatedSequenceLocs [ <NUM_LIT> ] . second , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumInstrsToCreateFrame += <NUM_LIT> ; else if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isCall ( ) && FrameID != MachineOutlinerTailCall ) NumInstrsToCreateFrame += <NUM_LIT> ; return MachineOutlinerInfo ( NumInstrsForCall , NumInstrsToCreateFrame , CallID ,


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeSPOperand ( const MachineInstr * MI , int Op , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( Op


<s> void addSVCROperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrsAVX2 ) ; i != e ; ++ i ) if ( ReplaceableInstrsAVX2 [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrsAVX2 [ i ] ; return <NUM_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( mf . getFunction ( ) ) ) return false ; MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : mf ) if ( processMachineBasicBlock ( &


<s> if ( register_operand ( op , mode ) || memory_operand ( op , mode ) || sh_unspec_insn_p ( op ) ) return false ; if ( ! can_create_pseudo_p ( ) ) return false ; recog_data_d prev_recog_data = recog_data ; rtx_insn * i = make_insn_raw ( gen_rtx_SET ( VOIDmode , get_t_reg_rtx ( ) , op ) ) ; SET_PREV_INSN ( i ) = NULL ; SET_NEXT_INSN ( i ) = NULL ; int result = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; if ( result < <NUM_LIT> && GET_CODE ( op ) == EQ ) { PUT_CODE ( op , NE ) ; result = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; PUT_CODE ( op , EQ ) ; } if ( result < <NUM_LIT> && GET_CODE ( op ) == NE ) { PUT_CODE ( op , EQ ) ; result = recog ( PATTERN ( i


<s> const MCExpr * getMemOffset ( ) const { assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind

== k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ;


<s> gen_il = gen_avx2_interleave_lowv32qi ; gen_ih = gen_avx2_interleave_highv32qi ; break ; case V64QImode : himode = V32HImode ; gen_il = gen_avx512bw_interleave_lowv64qi ; gen_ih = gen_avx512bw_interleave_highv64qi ; break ; default : gcc_unreachable ( ) ; } op2_l = op2_h = op2 ; switch ( code ) { case MULT : op2_l = gen_reg_rtx ( qimode ) ; op2_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op2_l , op2 , op2 ) ) ; emit_insn ( gen_ih ( op2_h , op2 , op2 ) ) ; op1_l = gen_reg_rtx ( qimode ) ; op1_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op1_l , op1 , op1 ) ) ; emit_insn ( gen_ih ( op1_h , op1 , op1 ) ) ; full_interleave = qimode == V16QImode ; break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; full_interleave = true ; break ; default : gcc_unreachable ( ) ; } res_l = expand_simple_binop ( himode , code , op1_l , op2_l , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; res_h = expand_simple_binop ( himode , code , op1_h , op2_h , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( res_l && res_h ) ; d . target = dest ; d . op0 = gen_lowpart ( qimode , res_l ) ; d . op1 = gen_lowpart ( qimode , res_h ) ; d . vmode = qimode ; d . nelt = GET_MODE_NUNITS ( qimode ) ; d . one_operand_p = false ; d . testing_p = false ; if ( full_interleave ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> + ( ( i & <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : ( i & <NUM_LIT> ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; } ok = ix86_expand_vec_perm_const_1 ( & d )


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM_FALLTHROUGH ; default : Inst . addOperand ( MCOperand :: createReg


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm (


<s> getAssembler ( ) . setIsThumbFunc ( Func ) ; emitSymbolAttribute ( Func , MCSA_ELF_TypeFunction


<s> assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; return


<s> static bool mips_rtx_constant_in_small_data_p ( machine_mode mode


<s> if ( ( M0 > <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) || ( M0 < <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M0 & <NUM_LIT> ] : BigEndianShifts [ M0 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M0 < <NUM_LIT> ; return true ; } if ( ( M1 > <NUM_LIT> && M0 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) || ( M1 < <NUM_LIT> && M0 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M1 & <NUM_LIT> ] : BigEndianShifts [ M1 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M1 < <NUM_LIT> ; return true ; } if ( ( M2 > <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M3 == <NUM_LIT> ) || ( M2 < <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M3 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M2 & <NUM_LIT> ] : BigEndianShifts [ M2 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M2 < <NUM_LIT> ; return true ; } if ( ( M3 > <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> ) || ( M3 < <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M3 & <NUM_LIT> ] : BigEndianShifts [ M3 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M3 < <NUM_LIT> ; return true ; } if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) { ShiftElts = <NUM_LIT> ; Swap = true ; unsigned XXINSERTWSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; if ( M0 == XXINSERTWSrcElem && M1 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return true ; } if ( M0 == <NUM_LIT> && M1 == XXINSERTWSrcElem && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return true ; } if ( M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == XXINSERTWSrcElem && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return


<s> symb = ( * targetm . strip_name_encoding ) ( symb ) ; length = strlen ( symb ) ; symbol_name = alloca ( length + <NUM_LIT> ) ; GEN_SYMBOL_NAME_FOR_SYMBOL ( symbol_name , symb , length ) ; lazy_ptr_name = alloca ( length + <NUM_LIT> ) ; GEN_LAZY_PTR_NAME_FOR_SYMBOL ( lazy_ptr_name , symb , length ) ; if ( flag_pic == <NUM_LIT> ) machopic_picsymbol_stub1_section ( ) ; else machopic_symbol_stub1_section ( ) ; if ( flag_pic == <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; label ++ ; local_label_0 = alloca ( sizeof ( <STR_LIT> ) ) ; sprintf ( local_label_0 , <STR_LIT> , label ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT>


<s> const MCInstrDesc & ADDrr = TII -> get ( getADDrrFromLEA ( Opcode ) ) ; const MachineOperand & Src = SrcR1 == DstR ? Index : Base ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( Opcode , Offset ) ) ; const MachineOperand & SrcR = SrcR1 == DstR ? Base : Index ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDri , DstR ) . add ( SrcR ) . addImm ( Offset . getImm ( ) ) ; LLVM_DEBUG ( NewMI -> dump (


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; if ( ST !=


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> ,


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 (


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert (

TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ;


<s> Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; bool isZExt = isa < ZExtInst > ( I ) ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT = TLI . getValueType ( SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT


<s> if ( flags & SECTION_CODE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( HAVE_AS_SPARC_NOBITS ) { if ( flags & SECTION_BSS ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; } fputc ( '\n' ,


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool PreservedBaseReg = preserveBaseRegister ( MI , User . MI , DeadSize , CanDeleteLEA , BaseRegKill ) ; if ( ! jumpTableFollowsTB ( MI , User . CPEMI ) && ! PreservedBaseReg ) continue ; } else { unsigned BaseReg = User . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( User . MI -> getIterator ( ) == User . MI -> getParent ( ) -> begin ( ) ) continue ; MachineInstr * Shift = User . MI -> getPrevNode ( ) ; if ( Shift -> getOpcode ( ) != <STR_LIT> || Shift -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || ! Shift -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; IdxReg = Shift -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftedIdxReg = Shift -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == IdxReg && ! jumpTableFollowsTB ( MI , User . CPEMI ) ) continue ; MachineInstr * Load = User . MI -> getNextNode ( ) ; if ( Load -> getOpcode ( ) != <STR_LIT> ) continue ; if ( Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != ShiftedIdxReg || ! Load -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; auto * TRI = STI -> getRegisterInfo ( ) ; if ( registerDefinedBetween ( BaseReg , Load -> getNextNode ( ) , MBB -> end ( ) , TRI ) ) continue ; if ( isPositionIndependentOrROPI ) { MachineInstr * Add = Load -> getNextNode ( ) ; if ( Add -> getOpcode ( ) != <STR_LIT> || Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != Load -> getOperand ( <NUM_LIT> ) . getReg ( ) || ! Add -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; if ( registerDefinedBetween ( IdxReg , Add -> getNextNode ( ) , MI , TRI ) ) continue ; Add -> eraseFromParent ( ) ; DeadSize += <NUM_LIT> ; } else { if ( Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; if ( registerDefinedBetween ( IdxReg , Load -> getNextNode ( ) , MI , TRI ) ) continue ; } CanDeleteLEA = true ; Shift -> eraseFromParent ( ) ; Load -> eraseFromParent ( ) ; DeadSize += <NUM_LIT> ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr

, MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> inline void FillFinishOpcode ( ) { while ( Pos < Vec . size ( ) ) EmitByte (


<s> if ( x86_64_immediate_operand ( CONST_CAST_RTX ( x ) , SImode ) ) ( imm_values -> imm32 ) ++ ; else ( imm_values -> imm64 ) ++ ; break ; case CONST_DOUBLE : ( imm_values -> imm ) ++ ; ( imm_values -> imm64 ) ++ ; break ; case CODE_LABEL : if ( LABEL_KIND ( x ) == LABEL_NORMAL ) { ( imm_values -> imm


<s> pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create

( * ( m_pPLT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ;


<s> if ( ITCounter == <NUM_LIT> ) ITState = <NUM_LIT> ; else { unsigned short NewITState4_0 = slice ( ITState ,


<s> if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NewShiftVal = ShiftVal + ShiftVal2 ; if ( NewShiftVal >= NumBitsPerElt ) NewShiftVal = NumBitsPerElt - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) &&


<s> if ( ! NumVGScaledBytes ) return MCCFIInstruction :: createOffset ( nullptr , DwarfReg , NumBytes ) ; std :: string CommentBuffer ; llvm :: raw_string_ostream Comment ( CommentBuffer ) ; Comment << printReg ( Reg , & TRI ) << <STR_LIT> ; SmallString < <NUM_LIT> > OffsetExpr ; appendVGScaledOffsetExpr ( OffsetExpr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ; SmallString < <NUM_LIT> > CfaExpr ; CfaExpr . push_back ( dwarf :: DW_CFA_expression ) ; uint8_t buffer [


<s> int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; SDValue Value = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT TheVT = Value . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , Align ( MemSize ) , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP (


<s> bool <ISA_LIT>TargetAsmInfo < BaseTAI > :: LowerToBSwap ( CallInst * CI ) const { if ( CI -> getNumOperands ( ) != <NUM_LIT> || CI -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! CI -> getType ( ) -> isInteger ( ) ) return false ; const IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( ! Ty || Ty -> getBitWidth ( ) % <NUM_LIT> != <NUM_LIT> ) return false ; const Type * Tys [ ]


<s> return ( ( AM5Opc >> <NUM_LIT> ) & <NUM_LIT>


<s> return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) { DOUT << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return DecrementOldEntry ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , Addr , <STR_LIT> ) ; } else { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; } return true


<s> auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node = Op ; Entry . Ty = Op . getValueType ( ) . getTypeForEVT ( Ctx ) ; Args . push_back ( Entry ) ; } ; pushArg ( Dst ) ; pushArg ( Src ) ; pushArg ( Size ) ; SDValue memOpFn = DAG . getExternalFunctionSymbol ( fnName ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Dst . getValueType ( ) . getTypeForEVT ( Ctx ) , memOpFn , std :: move ( Args ) ) . setDiscardResult ( ) ; const <ISA_LIT>TargetLowering * TLI = STI


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const


<s> if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ; return ( GET_MODE_SIZE ( mode ) +


<s> assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { ArgInfo CurArgInfo ( VRegs [ i ] , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) ) ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( CurArgInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , VRegs [ i ] ) ; } CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ; return handleAssignments ( MIRBuilder , SplitVTs


<s> if ( <STR_LIT> ( LHS . getNode ( ) ) || <STR_LIT> ( RHS . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements (


<s> if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>=


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS2 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base ,


<s> return ( vector signed int ) __builtin_altivec_vsum4sbs ( ( vector signed char


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; AsmPrinter :: runOnMachineFunction ( MF )


<s> return getExtractVEXTRACTImmediate ( N ,


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> || Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setCallsEhDwarf


<s> OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst TC ; TC . setOpcode ( OpCode ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if

( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; if ( imm != INT32_MIN ) imm *= ( <NUM_LIT> << shift ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler


<s> static tree csky_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( csky_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( csky_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) (