<s> SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , DL , VT


<s> output_asm_insn ( <STR_LIT> , operands ) ; if ( final_sequence ) { rtx delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; output_restore ( PATTERN ( delay ) ) ; PATTERN ( delay ) = gen_blockage


<s> len = get_attr_length ( insn ) ; if ( len <= <NUM_LIT> ) return <NUM_LIT> ; if ( ! JUMP_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) return <NUM_LIT> ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < <NUM_LIT> && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = <NUM_LIT> ; } if ( l ) return <NUM_LIT> + l ; else return


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddOp1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT PtrTy = MRI . getType ( DstReg ) ; if ( PtrTy . getAddressSpace ( ) != <NUM_LIT> ) return false ; if ( PtrTy . isVector ( ) ) return false ; MachineIRBuilder MIB ( I ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; auto PtrToInt = MIB . buildPtrToInt ( s64 , AddOp1Reg ) ; MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . setDesc ( TII . get ( TargetOpcode :: G_ADD ) ) ; MRI . setType ( DstReg , s64 ) ; I . getOperand ( <NUM_LIT> ) . setReg ( PtrToInt . getReg ( <NUM_LIT> ) ) ; if ( ! select ( * PtrToInt ) ) { LLVM_DEBUG ( dbgs (


<s> <ISA_LIT>AnalyzeImmediate :: <STR_LIT> Inst = Seq . begin ( ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , TII . get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) ; ++ Inst ) BuildMI ( MBB , II , DL , TII . get (

Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;


<s> if ( MRI -> isSSA ( ) ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( TargetRegisterInfo :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ; for ( ; It != E ; ++ It


<s> void addFPDRegListWithVPROperands ( MCInst & Inst , unsigned N ) const { addRegListOperands ( Inst


<s> return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: create ( Sym , Ctx ) , Ctx ) ; } return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer


<s> Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < <ISA_LIT>MCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return <NUM_LIT>


<s> cfun -> machine -> thumb1_cc_mode = CC_NOOVmode ; if ( INSN_CODE ( insn ) == CODE_FOR_thumb1_subsi3_insn ) { rtx src1 = XEXP ( SET_SRC ( set ) , <NUM_LIT> ) ; if ( src1 == const0_rtx ) cfun -> machine -> thumb1_cc_mode = CCmode ; } else if ( REG_P ( SET_DEST ( set ) ) && REG_P ( SET_SRC ( set ) ) ) { cfun -> machine -> thumb1_cc_op0 = SET_SRC ( set ) ; } } else if ( conds != CONDS_NOCOND ) cfun -> machine ->


<s> return ( __m128d ) __builtin_ia32_maskloadpd ( ( const __v2df * ) __P ,


<s> ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success )


<s> int rot = <NUM_LIT> ; bool res = can_be_rotated_to_lowbits ( ~ c , <NUM_LIT> , & rot ) ; return res && rot


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned ConstraintID = InlineAsm :: getMemoryConstraintID ( MO . getImm ( ) ) ; switch ( ConstraintID ) { case InlineAsm :: Constraint_ZC : { const <ISA_LIT>Subtarget & Subtarget = MO . getParent ( ) -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } default : return <NUM_LIT>


<s> if ( CondCode == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CondCode , S , E


<s> FunctionPass * llvm :: create<ISA_LIT>CondBrTuning ( ) { return new <ISA_LIT>CondBrTuning


<s> const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info


<s> return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) && ! Attrs

. hasAttrSomewhere ( Attribute :: SwiftAsync ) && MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: SwiftTail ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_LOAD ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; SDValue Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Node -> getChain ( ) ) , <NUM_LIT> ) ; return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) , Node


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd (


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) ) { if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; NumLanes = <NUM_LIT> ; NumOf256BitLanes = <NUM_LIT> ; } else if ( VT . is512BitVector ( ) ) { assert ( VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; NumLanes = <NUM_LIT> ; NumOf256BitLanes = <NUM_LIT> ; } else { NumLanes = <NUM_LIT> ; NumOf256BitLanes = <NUM_LIT> ; } unsigned NumEltsInStride = NumElts / NumOf256BitLanes ; unsigned NumLaneElts = NumEltsInStride / NumLanes ; for ( unsigned l256 = <NUM_LIT> ; l256 < NumOf256BitLanes ; l256 += <NUM_LIT> ) { for ( unsigned l = <NUM_LIT> ; l != NumEltsInStride ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l256 * NumEltsInStride + l + i ] ; int BitI1 = Mask [ l256 * NumEltsInStride + l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j + l256 * NumElts ) ) return false ; if ( V2IsSplat && ! isUndefOrEqual ( BitI1 , NumElts ) ) return false ; if ( ! isUndefOrEqual ( BitI1 , j + l256 * NumElts + NumEltsInStride ) ) return false ; } } } return


<s> unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs


<s> uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t ImmOp32 = covertDoubleImmToSingleImm ( ImmOp64 ) ; return loadImmediate ( ImmOp32 , FirstReg , <STR_LIT> , true


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget


<s> else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg


<s> const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( featureBits [ <STR_LIT> ] && ! ( Val == <NUM_LIT> || Val == <NUM_LIT> ) )


<s> void emit_tfmode_unop ( enum rtx_code code , rtx * operands ) { if ( TARGET_HARD_QUAD ) emit_hard_tfmode_operation ( code , operands ) ; else emit_soft_tfmode_unop ( code


<s> if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != i + WhichResult ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] !=

i + NumElts + WhichResult ) ) return false ;


<s> static void EmitBICMask ( const MCSubtargetInfo & STI , MCStreamer & Out , unsigned Addr , int64_t Pred , unsigned Mask ) { MCInst BICInst ; const int32_t EncodedMask = <STR_LIT> ( Mask ) ; assert ( EncodedMask != - <NUM_LIT> ) ; BICInst . setOpcode ( <STR_LIT> ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( EncodedMask ) ) ; BICInst . addOperand ( MCOperand :: CreateImm


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseEOL ( ) ) return true ; getTargetStreamer ( ) . emitDirectiveVariantPCS ( Sym ) ; return false


<s> if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg )

return rs6000_complex_function_value ( mode ) ;


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; MachineMemOperand * MMO = nullptr ; for ( auto * I : MI . memoperands ( ) ) if ( I -> isStore ( ) ) { MMO = I ; break ; } BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * FalseMBB = <STR_LIT> ( StartMBB ) ; if ( ! MI . killsRegister ( <STR_LIT> ) && ! checkCCKill ( MI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB =


<s> for ( i = <NUM_LIT> ; i < last_alg ; i ++ ) if ( ( stringop_alg ) i != rep_prefix_8_byte || TARGET_64BIT ) candidates . safe_push ( stringop_alg_names [ i ] ) ; char * s ; const char * hint = candidates_list_and_hint ( alg_name , s , candidates ) ; if ( hint ) inform ( input_location , <STR_LIT> , opt , s , hint ) ; else inform ( input_location , <STR_LIT> , opt , s ) ; XDELETEVEC ( s ) ; return ; } if ( ( stringop_alg ) i == rep_prefix_8_byte && ! TARGET_64BIT ) { error ( <STR_LIT> <STR_LIT> , alg_name , opt ) ; return ; } input_ranges [ n ] . max = maxs ; input_ranges [ n ] . alg = ( stringop_alg ) i ; if ( ! strcmp ( align , <STR_LIT> ) ) input_ranges [ n ] . noalign = false ; else if ( ! strcmp ( align , <STR_LIT> ) ) input_ranges [ n ] . noalign = true ; else { error ( <STR_LIT> , align , opt ) ; return ; } n ++ ; curr_range_str = next_range_str ; } while ( curr_range_str ) ; if ( input_ranges [ n - <NUM_LIT> ] . max != - <NUM_LIT>


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC <


<s> unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg


<s> printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT>


<s> if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > <NUM_LIT> &&

! FLOAT128_2REG_P ( mode ) ) return true ;


<s> switch ( Reg ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! Subtarget . hasISEL ( ) ) return false ; if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ; CondCycles =


<s> int Reg = tryMatchSVEVectorRegister ( Parser . getTok ( ) , NextKind , false ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Kind != NextKind ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } PrevReg = Reg ; Count ++ ; } if ( Count > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const int NumElements = <NUM_LIT>


<s> } ; LowOverheadLoop LoLoop ( ML ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs (


<s> if ( ! T . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return createELFStreamer ( Context , std :: move ( MAB ) , OS , std


<s> assert ( DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; ImmVal = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) + DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ImmVal << <STR_LIT> ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( UseMI . dump ( ) ) ; unsigned NewUseOpcSImm7 ; unsigned NewUseOpcMImm ; enum InstType { rr2ri_rm , rr2ir_rm , } InstType ; using namespace llvm :: <ISA_LIT> ; case NAME ## rr : \ NewUseOpcSImm7 = NAME ## ri ; \ NewUseOpcMImm = NAME ## rm ; \ InstType = rr2ri_rm ; \ break case NAME ## rr : \ NewUseOpcSImm7 = NAME ## ir ; \ NewUseOpcMImm = NAME ## rm ; \ InstType = rr2ir_rm ; \ break switch ( UseMI . getOpcode ( ) ) { default : return false ; INSTRKIND ( ADDUL ) ; INSTRKIND ( ADDSWSX ) ; INSTRKIND ( ADDSWZX ) ; INSTRKIND ( ADDSL ) ; NCINSTRKIND ( SUBUL ) ; NCINSTRKIND ( SUBSWSX ) ; NCINSTRKIND ( SUBSWZX ) ; NCINSTRKIND ( SUBSL ) ; INSTRKIND ( MULUL ) ; INSTRKIND ( MULSWSX ) ; INSTRKIND ( MULSWZX ) ; INSTRKIND ( MULSL ) ; NCINSTRKIND ( DIVUL )


<s> break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83


<s> int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void )


<s> return ( ( regno >= GR_RET_FIRST && regno <= GR_RET_LAST ) || ( regno >= FR_RET_FIRST && regno <=


<s> SDLoc DL ( N ) ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; } if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNOT ( DL , LHS . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; return LHS . getOperand ( <NUM_LIT> ) ; } } return SDValue (


<s> rtx_code code = GET_CODE ( shift ) ; if ( sh == <NUM_LIT> ) code = ROTATE ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( nb == <NUM_LIT> || ne == <NUM_LIT> || ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> ) ; if ( ne > nb ) return false ; if ( sh < <NUM_LIT> ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> && ! ( code == LSHIFTRT && nb >= <NUM_LIT> - sh ) ) return true ; if ( code == LSHIFTRT ) sh = <NUM_LIT> - sh ; if ( nb == <NUM_LIT> || ne == <NUM_LIT> || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT>


<s> ( void ) BroadcastI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BroadcastI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( Is128Bit ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addReg ( VBStateReg ) . addReg ( OpReg ) ; ( void ) OrI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else if ( OpRC -> hasSuperClassEq ( & <STR_LIT> ) || OpRC -> hasSuperClassEq ( & <STR_LIT> ) || OpRC -> hasSuperClassEq ( & <STR_LIT> ) ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; bool Is128Bit = OpRC -> hasSuperClassEq ( & <STR_LIT> ) ; bool Is256Bit = OpRC -> hasSuperClassEq ( & <STR_LIT> ) ; if ( Is128Bit || Is256Bit ) assert ( Subtarget -> hasVLX ( ) && <STR_LIT> ) ; Register VStateReg = MRI -> createVirtualRegister ( OpRC ) ; unsigned BroadcastOp = Is128Bit ? <STR_LIT> : Is256Bit ? <STR_LIT> : <STR_LIT> ; auto BroadcastI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( BroadcastOp ) , VStateReg ) . addReg ( StateReg ) ; ( void ) BroadcastI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BroadcastI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; unsigned OrOp = Is128Bit ? <STR_LIT> : Is256Bit ? <STR_LIT> : <STR_LIT> ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOp ) , TmpReg ) . addReg ( VStateReg ) . addReg ( OpReg ) ; ( void ) OrI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { assert ( OpRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; if ( ! EFLAGSLive ) { auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( StateReg ) . addReg ( OpReg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( OpReg ) . addReg


<s> static __inline__ double __fnmsub ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT>


<s> return __builtin_sh_media_LDHI_L ( ( char * ) p +


<s> unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return


<s> if ( offset != <NUM_LIT> ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr


<s> const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( Op != nullptr ) RegNum =


<s> if ( ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; int ResTyNumElts = ResTy . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Indices ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) Indices . push_back ( Node -> getMaskElt ( i ) ) ; if ( isVECTOR_SHUFFLE_SPLATI ( Op , ResTy , Indices , DAG ) ) return lowerVECTOR_SHUFFLE_VSHF ( Op , ResTy , Indices , DAG ) ; SDValue Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVEV ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVOD ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVL ( Op , ResTy , Indices , DAG


<s> if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , LR_REGNUM


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { initAsmInfo (


<s> long mn_l = ( long ) mn ; return ( ( unsigned long long ) __builtin_sh_media_MMACNFX_WL ( ( v2hi ) mm_l , ( v2hi ) mn_l , (


<s> case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false


<s> int32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It


<s> BuildMI ( * exit , exit -> end ( ) , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! Subtarget . is64Bit ( ) ) BuildMI ( * exit , exit -> end ( ) , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * exit , exit -> end ( ) , DebugLoc ( ) , get (

<STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ;


<s> static enum arm_pcs arm_get_pcs_model ( const_tree type , const_tree decl ) { bool user_convention = false ; enum arm_pcs user_pcs = arm_pcs_default ; tree attr ; gcc_assert ( type ) ; attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { user_pcs = arm_pcs_from_attribute ( TREE_VALUE ( attr ) ) ; user_convention = true ; } if ( TARGET_AAPCS_BASED ) { bool base_rules = stdarg_p ( type


<s> return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ?


<s> else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; if ( A -> getSize ( ) == <NUM_LIT> ) return getCommonSubClass ( A , & <STR_LIT> ) ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) return A ; break ; case <STR_LIT> : if ( B == &


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: fpga32 , false > X ( The<ISA_LIT>32Target , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: fpga64 , false > Y (


<s> Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result

, PseudoSourceValue :: getGOT ( ) , <NUM_LIT> ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> void <ISA_LIT>AsmPrinter :: LowerSTACKMAP ( MCStreamer & OutStreamer , StackMaps & SM , const MachineInstr & MI ) { unsigned NumNOPBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SM . recordStackMap ( MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumNOPBytes ; i += <NUM_LIT> ) EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm


<s> if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode


<s> return Kind == Memory && ( ! Mem . Size


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { emitDataMappingSymbol (


<s> } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int NumElems = VT . getVectorNumElements ( ) ; EVT CanonVT = VT . getSizeInBits ( ) ==


<s> int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT>


<s> if ( C -> getAPIntValue ( ) == <NUM_LIT> ) return EmitTest ( Op0 , <ISA_LIT>CC , dl , DAG ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; } if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget -> isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base =


<s> double Cost = <NUM_LIT> ; for ( auto MI : Instrs ) Cost += Converters . lookup ( { DstDomain

, MI -> getOpcode ( ) } ) -> getExtraCost ( MI , MRI ) ;


<s> if ( align > max_common_align ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT , name , max_common_align / BITS_PER_UNIT ) ; align = max_common_align ; } switch_to_section ( bss_section ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , MAX ( size


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ; if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG )


<s> MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits (


<s> gcc_assert ( BYTES_BIG_ENDIAN ) ; if ( GET_CODE ( dest ) == SUBREG ) dest = SUBREG_REG ( dest ) ; if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || aarch64_classify_vector_mode ( GET_MODE ( dest ) ) != VEC_SVE_DATA || aarch64_classify_vector_mode ( GET_MODE ( src ) ) != VEC_SVE_DATA || ( GET_MODE_UNIT_SIZE ( GET_MODE ( dest ) ) == GET_MODE_UNIT_SIZE ( GET_MODE ( src ) ) ) ) return false ; rtx ptrue = force_reg ( VNx16BImode , CONSTM1_RTX ( VNx16BImode ) ) ; rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( <NUM_LIT> , ptrue , src ) , UNSPEC_REV_SUBREG ) ; emit_insn ( gen_rtx_SET ( dest


<s> if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , <NUM_LIT> ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > (


<s> if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg (


<s> MCOperand T9Reg = MCOperand :: createReg ( <STR_LIT> ) ; StringRef SymName ( <STR_LIT> ) ; const MCSymbol * Sym = Ctx -> getOrCreateSymbol ( SymName ) ; const <ISA_LIT>MCExpr * MCSym ; MCSym = <ISA_LIT>MCExpr :: create ( Sym , <ISA_LIT>MCExpr :: CEK_ABS_HI , * Ctx ) ; MCOperand SymHi = MCOperand :: createExpr ( MCSym ) ; MCSym = <ISA_LIT>MCExpr :: create ( Sym , <ISA_LIT>MCExpr :: CEK_ABS_LO , * Ctx ) ; MCOperand SymLo = MCOperand :: createExpr ( MCSym ) ; MCInsts . resize ( <NUM_LIT>


<s> unsigned LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; if ( PhysRegSize > ValSize && LocSize == ValSize ) { assert ( ( PhysRegSize == <NUM_LIT> || PhysRegSize == <NUM_LIT> ) && <STR_LIT> ) ; auto MIB = MIRBuilder . buildAnyExt ( LLT :: scalar ( PhysRegSize ) , ValVReg ) ; ExtReg = MIB . getReg ( <NUM_LIT> ) ; } else ExtReg = extendRegister (


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> SDValue InDouble = N -> getOperand ( <NUM_LIT> ) ; if ( InDouble . getOpcode ( ) == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return DCI . CombineTo ( N , InDouble . getOperand ( <NUM_LIT> ) , InDouble . getOperand ( <NUM_LIT> ) ) ; SDNode * InNode = InDouble . getNode ( ) ; if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode > ( InNode ) -> isVolatile ( ) ) { LoadSDNode * LD = cast < LoadSDNode > ( InNode ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( LD ) ; SDValue BasePtr = LD


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc !=


<s> } unsigned RetOpc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; return true


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! requiresRegisterScavenging ( MF ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI (


<s> BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; } } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; Register IgnoredFrameReg ; int64_t Offset = getFrameIndexReference ( MF , Save . getFrameIdx ( ) , IgnoredFrameReg ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , SPOffsetFromCFA + Offset ) ) ; CFIIndexes . push_back ( CFIIndex


<s> static rtx_insn * nds32_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { if ( ! flag_inline_asm_r15 ) { clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; } return NULL


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : case IES_OFFSET : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC || CurrState == IES_OFFSET ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg


<s> static <ISA_LIT>Operand * CreateReg ( unsigned RegNo , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand (


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return RegNo ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * RegNo ; } } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO .


<s> if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; return nullptr ; } if ( RB . getID ( ) == <STR_LIT> ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT>


<s> static const char * mips16_call_stub_mode_suffix ( machine_mode mode ) { if ( mode == SFmode ) return <STR_LIT> ; else if ( mode == DFmode ) return <STR_LIT> ; else if ( mode ==


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case E_V32HFmode : half_mode = V16HFmode ; break ; case E_V32BFmode : half_mode = V16BFmode ; break ; case E_V16SImode : half_mode = V8SImode ; break ; case E_V16SFmode : half_mode = V8SFmode ; break ; case E_V8DImode : half_mode = V4DImode ; break ; case E_V8DFmode : half_mode = V4DFmode ; break ; case E_V16HFmode : half_mode = V8HFmode ; break ; case E_V16BFmode : half_mode = V8BFmode ; break ; case E_V8SImode : half_mode = V4SImode ; break ; case E_V8SFmode : half_mode = V4SFmode ; break ; case E_V4DImode : half_mode = V2DImode ; break ; case E_V4DFmode : half_mode = V2DFmode ; break ; case E_V4SImode : half_mode = V2SImode ; break ; case E_V4SFmode : half_mode = V2SFmode ; break ; case E_V2DImode : half_mode = DImode ; break ; case E_V2SImode : half_mode = SImode ; break ; case E_V2DFmode : half_mode = DFmode ; break ; case E_V2SFmode : half_mode = SFmode ; break ; default : gcc_unreachable ( ) ; } if ( ! register_operand ( ops [ <NUM_LIT> ] , half_mode ) ) ops [ <NUM_LIT> ] = force_reg ( half_mode , ops [ <NUM_LIT> ] ) ; if ( ! register_operand ( ops [ <NUM_LIT> ] , half_mode ) ) ops [ <NUM_LIT> ] = force_reg ( half_mode , ops [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ) ; break ; case <NUM_LIT> : switch ( mode ) { case E_V4DImode : half_mode = V2DImode ; break ; case E_V4DFmode : half_mode = V2DFmode ; break ; case E_V4SImode : half_mode = V2SImode ; break ; case E_V4SFmode : half_mode = V2SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; case <NUM_LIT> : switch ( mode ) { case E_V8DImode : half_mode = V4DImode ; break ; case E_V8DFmode : half_mode = V4DFmode ; break ; case E_V8SImode : half_mode = V4SImode ; break ; case E_V8SFmode : half_mode = V4SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; case <NUM_LIT> : switch ( mode ) { case E_V16SImode : half_mode = V8SImode ; break ; case E_V16SFmode : half_mode = V8SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; half : i = n - <NUM_LIT> ; for ( j = <NUM_LIT> ; j != - <NUM_LIT> ; j -- ) { half [ j ] = gen_reg_rtx ( half_mode ) ; switch ( n >> <NUM_LIT> ) { case <NUM_LIT> : v = gen_rtvec ( <NUM_LIT> , ops [ i - <NUM_LIT> ] , ops [ i ] ) ; i -= <NUM_LIT> ; break ; case <NUM_LIT> : v = gen_rtvec ( <NUM_LIT> , ops [ i - <NUM_LIT> ] , ops [ i - <NUM_LIT>

] , ops [ i - <NUM_LIT> ] , ops [ i ] ) ;


<s> else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ ( ~ <NUM_LIT> << ( <NUM_LIT> - CC ) ) : <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ <NUM_LIT> << ( <NUM_LIT> - CC ) : - <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ ( ~ <NUM_LIT> << ( <NUM_LIT> - CC ) ) : <NUM_LIT> ; else llvm_unreachable ( <STR_LIT> )


<s> MVT BaseVT = MaskVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e


<s> assert ( RegOp . isReg ( ) && <STR_LIT> ) ; OS << <STR_LIT> ; if ( LPAC :: isPreOp ( AluCode ) ) OS


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII ,


<s> inline static bool isTruncatedShiftCountForLEA ( unsigned ShAmt ) { return ShAmt < <NUM_LIT> && ShAmt >


<s> auto * LoadB = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( I ) ) ; return ! LoadA -> isVolatile ( ) && canUseBlockOperation (


<s> const TargetRegisterInfo * getRegisterInfo ( ) const


<s> Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return false ; } else { std :: unique_ptr < <ISA_LIT>Operand > Z ; if ( ParseZ ( Z , consumedToken ) ) return true ; if ( ! Z || getLexer ( ) . is ( AsmToken :: LCurly ) ) { SMLoc StartLoc = Z ? consumeToken ( ) : consumedToken ; unsigned RegNo ; SMLoc RegLoc ; if ( ! ParseRegister ( RegNo , RegLoc , StartLoc ) && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) { if ( RegNo == <STR_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , StartLoc ) ) ; Operands . push_back ( <STR_LIT> ( RegNo , StartLoc , StartLoc


<s> return false ; } unsigned Reg = <NUM_LIT> ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; } TOut . emitRRI ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Reg , <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: createImm (


<s> return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE


<s> SDValue Cst = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , Ty , HigherPart , Cst ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , Ty , Shift , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) ) ; SDValue Shift2 = DAG . getNode ( <STR_LIT> , DL , Ty , Add , Cst


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I


<s> return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple )

&& IN_RANGE ( multiple , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false


<s> while ( CmpMI != Br -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred != <STR_LIT> || CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return nullptr ; if ( ! is<ISA_LIT>LowRegister ( Reg ) )


<s> static bool isVSTfixed ( unsigned Opc ) { switch ( Opc ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> ) { int NumConstants = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; int Cost = <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT>


<s> int64_t Value = CE -> getValue ( ) ; if ( Value < <NUM_LIT> || Value > MaxRegNum ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Reg . Num = ( unsigned ) Value ; Reg . Group = Group


<s> if ( CC == CallingConv :: WebKit_JS ) return CC_<ISA_LIT>_WebKit_JS ; if ( CC == CallingConv :: GHC )


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << TRI -> getAsmName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : printOperand ( MI ,


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case


<s> void <ISA_LIT>LowOverheadLoops :: Expand ( LowOverheadLoop & LoLoop ) { auto ExpandLoopEnd = [ this ] ( LowOverheadLoop & LoLoop ) { MachineInstr * End = LoLoop . End ; MachineBasicBlock * MBB = End -> getParent ( ) ; unsigned Opc = LoLoop . IsTailPredicationLegal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . Dec -> eraseFromParent ( ) ; End -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) ConvertVPTBlocks ( LoLoop ) ; for ( auto * I : LoLoop . ToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; I -> eraseFromParent ( ) ; } } PostOrderLoopTraversal DFS ( LoLoop . ML , * MLI ) ; DFS . ProcessLoop ( ) ; const SmallVectorImpl < MachineBasicBlock * > & PostOrder = DFS . getOrder ( ) ; for ( auto * MBB : PostOrder ) { recomputeLiveIns ( * MBB ) ; MBB -> sortUniqueLiveIns (


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ]


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) !=


<s> for ( Instruction & I : inst_range ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant > (


<s> if ( NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; } ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( HasSSE2 && NumElems == <NUM_LIT> ) || ! <STR_LIT> ( SVOp ) ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; else if ( HasSSE2 ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; assert ( VT != <STR_LIT>


<s> RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg =


<s> val_reg = force_reg ( DImode , val_exp ) ; reg = val_reg ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , DImode , addr , i ) ; emit_move_insn ( mem , reg ) ; } } else val_reg = force_reg ( SImode , val_exp ) ; reg = ( use_strd_p ? gen_lowpart ( SImode , val_reg ) : val_reg ) ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; } if ( i + <NUM_LIT> <=


<s> bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind (


<s> if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ; } else return


<s> static const <ISA_LIT>MCExpr * CreateHi ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_HI , Expr , Ctx


<s> SDValue V = insertSubVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ,


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant


<s> static DecodeStatus DecodeThumbAddSPReg ( MCInst & Inst , uint16_t Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Rdm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rdm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm ,

Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple T ( TT ) ; if ( T . isOSDarwin ( ) ) RM = Reloc :: DynamicNoPIC ; else RM =


<s> void arm_pr_long_calls_off ( struct cpp_reader * pfile ATTRIBUTE_UNUSED


<s> break ; case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned Option = MO . getTargetFlags ( ) & <STR_LIT> ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; switch ( Option ) { default : break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) { return MCOperand :: createExpr ( MCSym ) ; } assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: create ( Offset , * Ctx ) ; const MCBinaryExpr * Add = MCBinaryExpr :: createAdd ( MCSym , OffsetExpr , * Ctx


<s> SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , OpVT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , OpVT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( Vec . getOpcode ( ) , DL , VT , Ext0 , Ext1 , Vec . getOperand ( <NUM_LIT> ) ) ; } if ( ! ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VecVT ) { SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ext0 , Ext1 , Ext2 ) ; } switch ( Vec . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( GET_CODE ( x ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC ) pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSGD ) ; else pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSLD ) ; pat = gen_rtx_CONST ( SImode , pat ) ; reg0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; insns = emit_call_insn ( gen_tls_desc ( pat , GEN_INT ( relax_group_id ) ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insns ) , pic_offset_table_rtx ) ; RTL_CONST_CALL_P ( insns ) = <NUM_LIT> ; tmp_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp_reg , reg0 ) ; x = tmp_reg ; break ; case TLS_MODEL_INITIAL_EXEC : pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT>


<s> if ( a < <NUM_LIT> ) return - local_fixunsdfdi ( - a ) ; return local_fixunsdfdi ( a


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; if ( SDValue R = combineConcatVectorOps ( SDLoc ( N ) , VT . getSimpleVT ( ) , Ops , DAG , DCI


<s> return true ; } IndexReg = TmpReg ; Scale = TmpInt ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . popOperator ( ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; } PrevState =


<s> static bool expandXorFP ( MachineInstrBuilder & MIB , const TargetInstrInfo & TII ) { MachineBasicBlock & MBB = * MIB -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; unsigned XorOp = MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get ( XorOp ) ) ; MIB . addReg ( TRI -> getFrameRegister ( MF ) , RegState :: Undef ) ; return


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TM . is<ISA_LIT>64 ( ) )


<s> } if ( isPowerOf2_32 ( RHSC ) ) { unsigned ShAmt = Log2_32 ( RHSC ) ; Base = Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } } if ( Offset . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( Offset , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { HandleSDNode Handle ( Offset ) ; replaceDAGValue ( Offset . getOperand ( <NUM_LIT> ) , NewMulConst ) ; Offset = Handle . getValue ( ) ; ShAmt = PowerOfTwo ; ShOpcVal = <STR_LIT>


<s> void ChangeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getPreviousSection ( ) . first ] =


<s> if ( arg0 == error_mark_node ) return const0_rtx ; if ( CONST_INT_P ( op0 ) && ! const_0_to_7_operand ( op0 , VOIDmode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( op0


<s> bool isMemDisp20 ( RegisterKind RegKind , MemoryKind MemKind ) const { return isMem ( RegKind , MemKind ) && inRange ( Mem .


<s> unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) { l1_line = <NUM_LIT> ; if ( platform [ <NUM_LIT> ] == '6' ) l1_sizekb = <NUM_LIT> ; else l1_sizekb = <NUM_LIT> ; } else { l1_line = elf_dcachebsize ( ) ; l1_sizekb = <NUM_LIT> ; } l1_assoc = <NUM_LIT> ; l2_sizekb = <NUM_LIT>


<s> if ( ! reload_completed || frame_pointer_needed ) return false ; if ( optimize_function_for_size_p ( cfun ) ) return


<s> switch ( MO . getImm ( ) ) { default : break ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; } assert ( false && <STR_LIT> ) ; return


<s> if ( ExtraSteps == TargetLoweringBase :: ReciprocalEstimate :: Unspecified ) ExtraSteps = VT . getScalarType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( Opcode , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue (


<s> void EmitDataMappingSymbol ( ) { if ( LastEMS == EMS_Data


<s> * op1 = cmp_operands [ <NUM_LIT> ] ; } else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ; * op1 = const0_rtx ; } else { * op0 = cmp_operands [ <NUM_LIT> ] ; * op1 = force_reg ( GET_MODE ( * op0 ) , cmp_operands [ <NUM_LIT> ] ) ; } } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_operands [ <NUM_LIT> ] ) ) ; * op1 = const0_rtx ; mips_emit_int_relational ( * code , & invert , * op0 , cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ; * code = ( invert ? EQ : NE ) ; } } else { enum rtx_code cmp_code ; switch ( * code


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode4 ( SDNode * Op , SDValue N , SDValue & Addr , SDValue & Mode ) { Addr = N ; Mode = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> ) , <STR_LIT> ) ; return true


<s> rtx lo = GEN_INT ( lo_val ) ; if ( TARGET_THUMB1 ) return <NUM_LIT> ; switch ( code ) { case AND : case IOR : case XOR : return ( const_ok_for_op ( hi_val , code ) || hi_val == <NUM_LIT> ) && ( const_ok_for_op ( lo_val , code ) || lo_val == <NUM_LIT> ) ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ; default : return


<s> bool SelectAddrIdxX16 ( SDValue N , SDValue & Base


<s> SDValue <ISA_LIT>TargetLowering :: lowerFABS ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 ( Op , DAG , Subtarget -> hasExtractInsert ( ) ) ; return lowerFABS32 ( Op , DAG , Subtarget


<s> bool FoundMnemonic = false ; unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; FoundMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; FoundMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( FoundMnemonic ) { printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> << ( unsigned int ) SH << '\n' ; return ; } } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode (


<s> void <ISA_LIT>TargetLowering :: addDRTypeForNEON


<s> if ( TARGET_LP64 ) return xstrdup ( <STR_LIT> ) ; return xstrdup ( <STR_LIT>


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || TargetRegisterInfo :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Elements ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op = & Op1 ; if ( Op && Op -> isReg ( ) && Op -> getReg ( ) == Op2 . getReg ( ) && Coef > <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef + <NUM_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg < <NUM_LIT> ) return None ; else if ( dwarfReg < <NUM_LIT> ) Elements . push_back ( dwarf :: DW_OP_reg0 + dwarfReg ) ; else { Elements . push_back ( dwarf :: DW_OP_regx ) ; Elements . push_back ( dwarfReg


<s> EVT VT = Op . getValueType ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op )


<s> bool has<ISA_LIT>64r2 ( ) const { return getSTI ( ) . getFeatureBits ( )


<s> return new <ISA_LIT>MCCodeEmitter ( MCII


<s> const struct processor * tmp_cpu = NULL ; enum aarch64_parse_opt_result parse_res = aarch64_parse_cpu ( str , & tmp_cpu , & aarch64_isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { gcc_assert ( tmp_cpu ) ; selected_tune = tmp_cpu ; explicit_tune_core = selected_tune -> ident ; selected_arch = & all_architectures [ tmp_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str , pragma_or_attr ) ; aarch64_print_hint_for_core ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , str


<s> name_ = PredefinedFuncs [ i ] . Name ; if ( strcmp ( name , name_ ) == <NUM_LIT> ) return & PredefinedFuncs


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false


<s> IsResolved = true ; ( void ) adjustFixupValue ( Fixup , Value ,


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo ( ) const { return


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> ; i < numArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i + <NUM_LIT> ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> return __builtin_aarch64_lceiludfdi (


<s> Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand (


<s> else { emitGRX32Move ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; MI -> setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg (


<s> MachineFunction & MF = * MBB . getParent ( ) ; auto * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register BasePtr ; int64_t Offset = ( TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) . getFixed ( ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getDebugOffset ( ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) { if ( OpcodeForOffset == <STR_LIT> && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVector ( ) ) { OpcodeForOffset = <STR_LIT> ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII -> get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr ) . addImm ( HighOffset ) . addReg ( <NUM_LIT> ) ; else { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( BasePtr , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } MI -> setDesc ( TII -> get (


<s> num_bifs = <NUM_LIT> ; line = <NUM_LIT> ; if ( parse_bif ( ) == PC_PARSEFAIL ) { fprintf ( stderr , <STR_LIT> , bif_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } fclose ( bif_file ) ; create_bif_order ( ) ; fprintf ( stderr , <STR_LIT> ) ; rbt_dump ( & bif_rbt , bif_rbt . rbt_root ) ; fprintf ( stderr , <STR_LIT> ) ; num_ovld_stanzas = <NUM_LIT> ; num_ovlds = <NUM_LIT> ; line = <NUM_LIT> ; if ( parse_ovld ( ) == PC_PARSEFAIL ) { fprintf ( stderr , <STR_LIT> , ovld_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } fclose ( ovld_file ) ; fprintf ( stderr , <STR_LIT> ) ; rbt_dump ( & fntype_rbt , fntype_rbt . rbt_root ) ; fprintf ( stderr , <STR_LIT> ) ; if ( ! write_header_file ( ) ) { fprintf ( stderr , <STR_LIT> , header_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } if ( ! write_init_file ( ) ) { fprintf ( stderr , <STR_LIT> , init_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } if ( ! write_defines_file ( ) ) { fprintf ( stderr , <STR_LIT> , defines_path ) ; delete_output_files ( ) ; exit (


<s> uint32_t Value = <NUM_LIT> ; if ( OddSPReg ) Value |= ( uint32_t ) AFL_FLAGS1_ODDSPREG ; return Value


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo (

TT , CPU , FS ) , Is<ISA_LIT>64 ( is64Bit ) , TargetTriple ( TT ) {


<s> bool <ISA_LIT>PreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( * Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case


<s> CCState CCInfo ( CFlags . CallConv , CFlags . IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; const bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; const EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const unsigned PtrByteSize = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; CCInfo . AllocateStack ( LinkageSize , PtrByteSize ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_AIX ) ; const unsigned MinParameterSaveAreaSize = <NUM_LIT> * PtrByteSize ; const unsigned NumBytes = std :: max ( LinkageSize + MinParameterSaveAreaSize , CCInfo . getNextStackOffset ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const SDValue StackPtr = Is<ISA_LIT>64 ? DAG . getRegister ( <STR_LIT> , <STR_LIT> ) : DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ) { CCValAssign & VA = ArgLocs [ I ++ ] ; SDValue Arg = OutVals [ VA . getValNo ( ) ] ; if ( ! VA . isRegLoc ( ) && ! VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { switch ( VA . getLocInfo ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } if ( VA . isMemLoc ( ) ) { SDValue PtrOff = DAG . getConstant ( VA . getLocMemOffset ( ) , dl , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; continue ; } assert ( VA . isRegLoc ( ) && VA . needsCustom ( ) && CFlags . IsVarArg && VA . getValVT ( ) . isFloatingPoint ( ) && VA . getLocVT ( ) . isInteger ( ) && <STR_LIT> ) ; SDValue ArgAsInt = DAG . getBitcast ( <STR_LIT> ( VA . getValVT ( ) . getSizeInBits ( )


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> bool addPreISel ( ) override { return


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; assert ( STI . hasAVX512 ( ) && <STR_LIT> ) ; if ( isStackAligned ) return load


<s> return __builtin_arm_wacch ( ( __v4hi


<s> MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( Ret , getSubtargetInfo ( ) ) ; emit<ISA_LIT>Nops ( * OutStreamer ,