<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>TargetMachine & tm , const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <STR_LIT> , <NUM_LIT> ) , TM ( tm ) , STI ( sti ) { RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I )

RegSpillOffsets [ SpillOffsetTable [ I ] . Reg ] = SpillOffsetTable [ I ] . Offset ;


<s> bool wasVisited ( const MachineInstr * MI ) const


<s> if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> isUnconditionalBranch ( ) ) { MachineBasicBlock * NewDest = getDestBlock ( * BMI ) ; if ( isBlockInRange ( MI , * NewDest ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; changeBranchDestBlock ( * BMI , * DestBB ) ; int NewSize = insertInvertedConditionalBranch ( * MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , MI , * NewDest ) ; int OldSize = TII -> getInstSizeInBytes ( MI ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += ( NewSize - OldSize ) ; MI . eraseFromParent ( ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> analyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ]


<s> return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv ::


<s> SDValue addV = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; } if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant


<s> if ( Subtarget . hasAVX ( ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( In . getValueType ( ) ) ) if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } return SDValue ( )


( unsigned int __X , unsigned int __Y ) {


<s> bool <ISA_LIT>Subtarget :: GVRequiresExtraLoad ( const GlobalValue * GV , const TargetMachine & TM , bool isDirectCall ) const { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( isDirectCall ) return false ; if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } return


<s> if ( aarch64_simd_builtins_initialized_p ) return ; aarch64_simd_builtins_initialized_p = true ; aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( )


<s> MinSVEVectorSize *= <NUM_LIT> ; MaxSVEVectorSize *= <NUM_LIT> ; } else { MinSVEVectorSize = SVEVectorBitsMinOpt ; MaxSVEVectorSize = SVEVectorBitsMaxOpt ; } assert ( MinSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( MaxSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( ( MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( MaxSVEVectorSize == <NUM_LIT> ) MinSVEVectorSize = ( MinSVEVectorSize / <NUM_LIT> ) * <NUM_LIT> ; else { MinSVEVectorSize = ( std :: min ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; MaxSVEVectorSize = ( std :: max ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; } Key += <STR_LIT> ; Key += std :: to_string ( MinSVEVectorSize ) ; Key += <STR_LIT> ; Key += std :: to_string ( MaxSVEVectorSize ) ; Key += CPU ; Key += TuneCPU ; Key += FS ; auto & I = SubtargetMap


<s> return LowerFAULTING_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: FENTRY_CALL : return LowerFENTRY_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_OP : return LowerPATCHABLE_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : return LowerPATCHABLE_FUNCTION_ENTER ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_RET : return LowerPATCHABLE_RET ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TAIL_CALL : return LowerPATCHABLE_TAIL_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_EVENT_CALL : return LowerPATCHABLE_EVENT_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TYPED_EVENT_CALL : return LowerPATCHABLE_TYPED_EVENT_CALL ( * MI , MCInstLowering ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : return LowerASAN_CHECK_MEMACCESS ( * MI ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitSEHInstruction ( MI ) ; return ; case <STR_LIT> : { assert ( MF -> hasWinCFI ( ) && <STR_LIT> ) ; MachineBasicBlock :: const_iterator MBBI ( MI ) ; for ( MBBI = PrevCrossBBInst ( MBBI ) ; MBBI != MachineBasicBlock :: const_iterator ( ) ; MBBI = PrevCrossBBInst ( MBBI ) ) { if ( ! MBBI -> isPseudo ( ) ) { if ( MBBI -> isCall ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; break ; } } return ; } case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( <STR_LIT> ) ) ; return ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; if ( MI -> isCall ( ) ) { SMShadowTracker . count ( TmpInst , getSubtargetInfo ( ) , CodeEmitter . get ( ) ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; OutStreamer -> emitInstruction ( TmpInst , getSubtargetInfo ( )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> } ; if ( ! match ( Ext1 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! match ( Ext2 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! areExtDoubled ( cast < Instruction > ( Ext1 ) ) ||

! areExtDoubled ( cast < Instruction > ( Ext2 ) ) ) return false ;


<s> int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } if ( MInfo . FrameConstructionID == MachineOutlinerTailCall || MInfo . FrameConstructionID == MachineOutlinerThunk ) return ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MBB . insert ( MBB . end ( ) , ret ) ; if ( MInfo . FrameConstructionID == MachineOutlinerNoLRSave )


<s> return ( __m512i ) __builtin_ia32_permvardi512_mask ( ( __v8di ) __Y , ( __v8di ) __X , (


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : case IES_OFFSET : State = IES_PLUS ; IC . pushOperator ( IC_PLUS ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) return regsUseUpError ( ErrMsg ) ; IndexReg = TmpReg


<s> printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> const MCOperand & Index = MI . getOperand ( Op + <STR_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; unsigned IndexReg = Index . getReg ( ) ; if ( STI . hasFeature ( <STR_LIT> ) && BaseReg == <NUM_LIT> &&


<s> unsigned int regno ; CUMULATIVE_ARGS * cum = get_cumulative_args ( ca ) ; if ( mode == VOIDmode ) return NULL_RTX ; if ( ! named ) { if ( TARGET_HARD_FLOAT ) return NULL_RTX ; if ( NDS32_ARG_PARTIAL_IN_GPR_REG_P ( cum -> gpr_offset , mode , type ) ) { regno = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) ; return gen_rtx_REG ( mode , regno ) ; } return NULL_RTX ; } if ( TARGET_HARD_FLOAT ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && NDS32_ARG_ENTIRE_IN_FPR_REG_P ( cum -> fpr_offset , mode , type ) ) { regno = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG ( cum -> fpr_offset , mode , type ) ; return gen_rtx_REG ( mode , regno ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && NDS32_ARG_ENTIRE_IN_GPR_REG_P ( cum -> gpr_offset , mode , type ) ) { regno = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode ,


<s> int FI = TailCallArgs [ i ] . FrameIdx ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction


<s> const __vector unsigned int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __m64_union result = { <NUM_LIT> } ; a = ( __vector unsigned char ) ( __vector unsigned long long ) { <NUM_LIT> , __A } ; b = ( __vector unsigned char ) ( __vector unsigned


<s> void <ISA_LIT>TargetELFStreamer :: emitArch ( unsigned Value ) { Arch =


<s> if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; unsigned NewImm = Imm ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { ShuffleMask . push_back ( NewImm % NumLaneElts +


<s> CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ; else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ; } else CanAcceptPredicationCode


<s> return ( __m64 ) __builtin_arm_wrorw ( (


<s> bool <STR_LIT> ( SDNode * N ) { if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool Result = ( Index * ElSize ) % <NUM_LIT> == <NUM_LIT> ; return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register InsertReg = VecReg ; if ( ! DstReg ) DstReg = MRI . createVirtualRegister ( DstRC ) ; if ( LaneIdx == <NUM_LIT> ) { auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { * DstReg } , { } ) . addReg ( VecReg , <NUM_LIT> , ExtractSubReg ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ; return & * Copy ; } if ( VecTy . getSizeInBits ( ) != <NUM_LIT> ) { MachineInstr * ScalarToVector = emitScalarToVector ( VecTy . getSizeInBits ( ) , & <STR_LIT> , VecReg , MIRBuilder ) ; if ( ! ScalarToVector ) return nullptr ; InsertReg = ScalarToVector -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * LaneCopyMI = MIRBuilder . buildInstr ( CopyOpc , { * DstReg } , { InsertReg } ) . addImm ( LaneIdx ) ; constrainSelectedInstRegOperands ( * LaneCopyMI , TII , TRI , RBI ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ; return


<s> for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain .


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( )


<s> if ( ! LocalSData && GVA -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) )


<s> llvm_unreachable ( <STR_LIT> ) ; break ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal % <NUM_LIT> ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , <NUM_LIT> } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { std :: string newConstraint ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { newConstraint = <STR_LIT> + utostr ( intVal


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR : { if ( Ins . size ( ) != <NUM_LIT> || Ins [ <NUM_LIT> ] . VT != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MachineRegisterInfo & RegInfo = DAG . getMachineFunction ( ) . getRegInfo (


<s> const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState

( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ;


<s> static inline int getT2SOImmValSplatVal ( unsigned V ) { unsigned u , Vs , Imm ; if ( ( V & <NUM_LIT> ) == <NUM_LIT> ) return V ; Vs = ( ( V & <NUM_LIT> ) == <NUM_LIT> ) ? V >>


_mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> virtual const DataLayout * getDataLayout ( ) const { return &


<s> return ( ( ( TARGET_SHMEDIA ? <NUM_LIT> : TARGET_FMOVD ? <NUM_LIT> : <NUM_LIT> ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return <NUM_LIT> ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= <NUM_LIT> ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return <NUM_LIT> ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> * ( (

GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) .


<s> if ( ! SrcReg ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; UpdateValueMap ( I


<s> rtx * loc = & SET_DEST ( PATTERN ( chain -> insn ) ) ; if ( chain -> loc != loc ) continue ; if ( chain -> insn == insn ) found_insn = true ; if ( chain -> insn == cand ) found_cand = true ; if ( found_insn && found_cand ) return true ; } } return false


<s> Op -> Prefetch . Val = Val ; Op -> Barrier . Data = Str . data ( ) ; Op -> Barrier . Length = Str . size


<s> void setPICBase ( uintptr_t Base ) { PICBase =


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable (


<s> if ( Address . getOpcode ( ) == <STR_LIT> && ! MatchSegmentBaseAddress ( Address , AM ) ) return false ; return true


<s> unsigned AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) )


<s> } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg , <ISA_LIT>Pred ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( Subtarget -> hasSPE ( ) ? <STR_LIT> : <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue (


<s> DebugLoc DL = Op . getDebugLoc ( ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } NewVal = isNEONModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { DebugLoc DL = Op . getDebugLoc ( ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } return SDValue ( )


<s> aarch64_simd_type_info * type = & aarch64_simd_types [ type_index ] ; const char * vector_type_name = type -> name ; char tuple_type_name [ sizeof ( <STR_LIT> ) ] ; snprintf ( tuple_type_name , sizeof ( tuple_type_name ) , <STR_LIT> , ( int ) strlen ( vector_type_name ) - <NUM_LIT> , vector_type_name + <NUM_LIT> , num_vectors ) ; tuple_type_name [ <NUM_LIT> ] = TOLOWER ( tuple_type_name [ <NUM_LIT> ] ) ; tree vector_type = type -> itype ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; if ( type -> mode == DImode ) { if ( num_vectors == <NUM_LIT> ) SET_TYPE_MODE ( array_type , V2x1DImode ) ; else if ( num_vectors == <NUM_LIT> ) SET_TYPE_MODE ( array_type , V3x1DImode ) ; else if ( num_vectors == <NUM_LIT> ) SET_TYPE_MODE (


<s> assert ( ! isThumb ( STI ) && ! isThumb2 ( STI ) && <STR_LIT> ) ; Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; isAdd = false ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO1 . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; } } else if ( MO . isExpr ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false


<s> emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( half_width - <NUM_LIT> ) ) ) ; if ( count > half_width ) emit_insn ( gen_ashr3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - half_width ) ) ) ; } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { machine_mode half_mode ; gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands ,


<s> SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB =


<s> SectionData :: iterator e_end ; if ( m_pGOTFront == NULL ) e_end = m_SectionData -> end ( ) ; else e_end = SectionData :: iterator ( m_pGOTFront ) ; while ( entry != e_end ) { llvm :: cast < <ISA_LIT>GOTEntry > ( entry ) -> setValue ( pPLTBase ) ; ++


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; unsigned Imm = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Imm , <NUM_LIT> * Rot ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; else MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; int Imm32 = <NUM_LIT> ; if ( Opcode == <STR_LIT> ) { Imm32 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } else if ( Opcode ==


<s> MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB ( MBBOpnd ) ; if ( Br -> hasDelaySlot ( ) ) { assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II = Br . getInstrIterator ( ) ; MIBundleBuilder ( & * MIB ) . append ( ( ++ II ) -> removeFromBundle ( ) ) ; } Br -> eraseFromParent (


<s> return __builtin_aarch64_uqadddi_uuu ( __a ,


<s> if ( parseOptionalToken ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Integer ) ) { if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return


<s> unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD


<s> Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) && ! Subtarget -> isTargetDarwin ( ) ) Alignment = DL -> getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode (


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; RHSReg = constrainOperandRegClass ( II , RHSReg , II .


<s> static arm_stack_offsets * arm_get_frame_offsets ( void ) { struct arm_stack_offsets * offsets ; offsets = & cfun ->


<s> bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr


<s> isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti (


<s> SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; KnownBits Known = DAG . computeKnownBits ( SubusLHS ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT>


<s> void addAddSubImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isShiftedImm ( ) ) { addExpr ( Inst , getShiftedImmVal ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( getShiftedImmShift ( ) ) ) ; return ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) { int64_t Val = CE -> getValue ( ) ; if ( ( Val != <NUM_LIT> ) && ( ( Val >> Shift ) << Shift ) ==


<s> MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugInstr ( ) ) return NoHazard ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return NoHazard ; if ( NumIssued != <NUM_LIT> && ( isFirst || isSingle )


<s> MVT DstVT ; Type * RetTy = I -> getType ( ) ; if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) )

Opc = isSigned ? <STR_LIT> : <STR_LIT> ;


<s> static rtx nds32_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return gen_rtx_REG ( mode , NDS32_FPR_RET_FIRST_REGNUM ) ; return gen_rtx_REG ( mode , NDS32_GPR_RET_FIRST_REGNUM


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString (


<s> __vector signed short w ; w = ( __vector signed short ) vec_splats ( __w ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) w , <NUM_LIT> ) ) ; __m64_union res


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( isMemOp ) O << '[' ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( Offset ) O << '+' << Offset ; if ( isMemOp ) O << ']' ; return ; } case MachineOperand :: MO_ExternalSymbol : { bool isMemOp = Modifier && ! strcmp ( Modifier


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain .


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; return LowerGlobalAddress ( GV , SDLoc (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return getThumbInstruction ( MI , Size , Bytes , Address , CS ) ; return get<ISA_LIT>Instruction ( MI , Size ,


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr


<s> case MCK__35_24 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_3 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_32 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_4 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_48 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_6 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_64 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_8 : ExpectedVal = <NUM_LIT> ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedReg ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RegShiftedReg . SrcReg ) ) ; Inst . addOperand ( MCOperand :: createReg ( RegShiftedReg . ShiftReg ) ) ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( RegShiftedReg . ShiftTy , RegShiftedReg


<s> m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> , true ) ; create_address_operand ( & m_ops . last ( ) ,


<s> return getSTI ( ) . getFeatureBits (


<s> int getFramePointerSaveIndex ( ) const


<s> return __builtin_mve_vmvnq_m_sv4si ( __arm_vuninitializedq_s32 ( )


<s> return true ; } if ( BaseReg == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( BaseReg != <NUM_LIT> && IndexReg != <NUM_LIT> ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) || ( IndexReg != <STR_LIT> && IndexReg != <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } } } if ( ! Is64BitMode && BaseReg != <NUM_LIT> && ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return


<s> return ( __m128i ) __builtin_ia32_pbroadcastb128 (


<s> else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } if ( TARGET_THUMB2 && regno < <NUM_LIT> ) return LO_REGS ; if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS ; if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return


<s> inline MachineInstrBuilder buildMOV ( MachineBasicBlock & MBB , const DebugLoc & DL , unsigned Dst , unsigned Src , MachineInstr * MI ) const { return buildMOV ( MBB , DL , MI ) . addReg ( Dst , RegState :: Define

) . addUse ( <STR_LIT> ) . addUse ( Src ) . addImm ( <NUM_LIT> ) ;


<s> bool getHasPushSequences ( ) const { return


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Asm , Fixup , Target , Value , IsResolved , Ctx , IsLittleEndian ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FullSizeBytes && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumBytes


<s> static int lookAtByte ( struct InternalInstruction * insn , uint8_t * byte ) { return insn -> reader ( insn -> readerArg


<s> return __builtin_mve_vqshlq_n_sv4si ( __a ,


<s> printOperand ( P , MI , Op + <STR_LIT> , O , Modifier , AsmVariant ) ; O << ':' ; } O << '[' ; bool NeedPlus = false ; if ( BaseReg . getReg ( ) ) { printOperand ( P , MI , Op + <STR_LIT> , O , Modifier , AsmVariant ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( P , MI , Op + <STR_LIT> , O , Modifier , AsmVariant ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; printOperand ( P , MI , Op +


<s> if ( ! DisableDelaySlotFiller ) D = findDelayInstr ( MBB , MI ) ; ++ FilledSlots ; Changed = true ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( D == MBB . end ( ) ) BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( I , & MBB , D ) ; unsigned structSize = <NUM_LIT> ; if ( needsUnimp ( MI , structSize ) ) { MachineBasicBlock :: iterator J =


<s> static void nds32_asm_function_epilogue ( FILE


<s> bool <ISA_LIT>TargetLowering :: isJumpTableRelative ( ) const { if ( Subtarget . is<ISA_LIT>64 ( ) )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; APFloat RealVal ( FPImm . Val ) ; uint32_t ImmVal ; A64Imms :: isFPImm ( RealVal , ImmVal ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> return DecodeMem ( Inst , insn , Address , Decoder , false ,


<s> const SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = LHS . getValueType ( ) ; SDLoc DL ( N ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { SDValue Op0 = LHS ; SDValue Op1 = RHS ; <STR_LIT> TmpCC = CC ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; TmpCC = <STR_LIT> ( TmpCC ) ; } bool IsSEXT0 = ( Op0 . getOpcode ( ) == <STR_LIT> ) && ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( Op1 . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( TmpCC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT>


<s> unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum


<s> static bool ia64_legitimate_address_disp ( const_rtx reg , const_rtx disp , bool strict ) { if ( GET_CODE ( disp ) == PLUS && rtx_equal_p ( reg , XEXP ( disp , <NUM_LIT> ) ) && ( ia64_legitimate_address_reg ( XEXP ( disp , <NUM_LIT> ) , strict ) || ( CONST_INT_P ( XEXP ( disp , <NUM_LIT> ) ) && IN_RANGE ( INTVAL ( XEXP ( disp , <NUM_LIT> ) ) , - <NUM_LIT> , <NUM_LIT> ) ) ) ) return true ; return false


<s> CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [

i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ;


<s> void printi16mem ( const MCInst * MI


<s> unsigned <ISA_LIT>CodeEmitter :: getMemRIXEncoding ( const MachineInstr & MI , unsigned OpNo ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) ) << <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DemoteRegTo32 ( SrcReg ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( FlagUseZeroBasedSandbox ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg (


<s> unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end


<s> if ( i == <NUM_LIT> && isThisReturn ) { assert ( ! VA . needsCustom ( ) && VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign ::


<s> static bool GetLabelAccessInfo ( const TargetMachine & TM , unsigned & HiOpFlags , unsigned & LoOpFlags , const GlobalValue * GV = <NUM_LIT> ) { HiOpFlags = <STR_LIT> ; LoOpFlags = <STR_LIT> ; bool isPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ; if ( isPIC


<s> const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; unsigned Reg = VA . getLocReg ( ) ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ++ NumInRegs == MaxInRegs ) return false ; break ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; } bool CalleeWillPop = <STR_LIT> ( CalleeCC , Subtarget . is64Bit ( ) , isVarArg , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; if ( unsigned BytesToPop = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) { bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize ; if ( ! CalleePopMatches


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts , struct gcc_options * ) { ptr -> x_aarch64_override_tune_string = opts


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; Register SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get

( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ;


<s> unsigned int getPLT1Size ( ) const { return


<s> static DecodeStatus DecodeJumpTarget ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset ) ) ; return MCDisassembler


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const MCInstrInfo *


<s> if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; int Latency = computeOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency <= <NUM_LIT> ) return false ; return DDomain == <STR_LIT> || DDomain == <STR_LIT> || UDomain == <STR_LIT> || UDomain


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFromMCExpr ( const MCExpr * Val , SMLoc S , SMLoc E , bool Is<ISA_LIT>64 ) { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Val ) ) return CreateImm ( CE -> getValue ( ) , S , E , Is<ISA_LIT>64 ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_PCREL ) return CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ; if ( const <ISA_LIT>MCExpr * TE = dyn_cast <


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) , <STR_LIT> ( a ) : ) ; return result


<s> return __builtin_aarch64_crypto_aesimcv16qi_uu (


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ; if ( ! Store ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> replaceAllUsesWith ( Store


<s> exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; if ( w . ulow ( ) != <NUM_LIT> ) return false ; mantissa = w . elt ( <NUM_LIT> ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ; if ( ( mantissa & mask ) != <NUM_LIT> ) return false ; mantissa >>= point_pos - <NUM_LIT> ; if ( mantissa == <NUM_LIT> ) return false ; mantissa &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; gcc_assert ( mantissa <= <NUM_LIT> ) ; exponent = <NUM_LIT>


<s> std :: vector < WinEH :: Instruction > & Epilog = CurFrame -> EpilogMap [ CurrentEpilog ] . Instructions ; unsigned UnwindCode = Win64EH :: UOP_End ; if ( ! Epilog . empty ( ) ) { WinEH :: Instruction EndInstr = Epilog . back ( ) ; if ( EndInstr . Operation == Win64EH :: UOP_Nop ) { UnwindCode = Win64EH :: UOP_EndNop ; Epilog . pop_back ( ) ; } else if ( EndInstr . Operation == Win64EH :: UOP_WideNop ) { UnwindCode = Win64EH ::


<s> HOST_WIDE_INT rounded ; rounded = size ? size : <NUM_LIT> ; rounded += ( BIGGEST_ALIGNMENT / BITS_PER_UNIT ) - <NUM_LIT> ; rounded = ( rounded / ( BIGGEST_ALIGNMENT / BITS_PER_UNIT ) * ( BIGGEST_ALIGNMENT / BITS_PER_UNIT ) ) ; i386_pe_maybe_record_exported_symbol ( decl , name , <NUM_LIT> ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; if ( use_pe_aligned_common ) fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , size ? size : ( HOST_WIDE_INT ) <NUM_LIT> , exact_log2 ( align ) - exact_log2 ( CHAR_BIT ) ) ; else fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> ASM_COMMENT_START <STR_LIT> HOST_WIDE_INT_PRINT_DEC


<s> unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; if ( isInt < <NUM_LIT> > ( Imm ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Lo ) ) ; } else if ( Lo ) { unsigned OpC = Hi ? <STR_LIT> : <STR_LIT> ; Result = CurDAG -> getMachineNode ( OpC , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Lo ) ) ; } else


<s> } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset ,


<s> if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS ,


<s> unsigned <ISA_LIT>TargetLowering :: getMaximalGlobalOffset ( ) const { return <NUM_LIT>


<s> const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg (


<s> MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BP = ( PVT == <STR_LIT> ) ? <STR_LIT> : ( Subtarget . isSVR4ABI ( ) && MF -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) .


<s> const LLT DstTy = MRI . getType ( DstReg ) ; const LLT InsertRegTy = MRI . getType ( InsertReg ) ; if ( ! DstTy . isVector ( ) ) return false ; if ( Index % InsertRegTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( Index == <NUM_LIT> && MRI . getVRegDef ( SrcReg ) -> isImplicitDef ( ) ) { if ( ! emitInsertSubreg ( DstReg , InsertReg , I , MRI , MF ) ) return false ; I . eraseFromParent ( ) ; return true ; } bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> && InsertRegTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( InsertRegTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( InsertRegTy . getSizeInBits ( ) == <NUM_LIT> ) I


<s> int64_t getFrameAdjustment ( const MachineInstr &


<s> } if ( ! Subtarget -> is64Bit ( ) && ( VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) ) && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; unsigned RatioInLog2 = Log2_32_Ceil ( Ratio ) ; uint64_t ShiftAmt = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Amt . getOperand ( i ) ) ; if ( ! C ) return SDValue ( ) ; ShiftAmt |= C -> getZExtValue ( ) << ( i * ( <NUM_LIT> << ( <NUM_LIT> - RatioInLog2 ) ) ) ; } for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { uint64_t ShAmt = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Amt . getOperand ( i + j ) ) ; if ( ! C ) return SDValue ( ) ; ShAmt |= C -> getZExtValue ( ) << ( j * ( <NUM_LIT> << ( <NUM_LIT> - RatioInLog2 ) ) ) ; } if ( ShAmt != ShiftAmt ) return SDValue ( ) ; } return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl , VT , R , ShiftAmt , DAG


<s> printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { O << <STR_LIT>


<s> bool isImm0_1020s4 ( ) const { return isImmediateS4 < <NUM_LIT> , <NUM_LIT> >


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) { auto MOTW = llvm :: make_unique <


<s> unsigned NumElts = VecTy -> getNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = -


<s> base = addr ; offset = const0_rtx ; } if ( base != NULL_RTX ) { int regno = REGNO ( base ) ; if ( regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM ) { if ( ( ( cfun != <NUM_LIT> && REGNO_POINTER_ALIGN ( regno ) >= desired * BITS_PER_UNIT ) || ( optimize && reload_completed ) ) && ( INTVAL ( offset ) & ( desired - <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; } else { if ( ( ( INTVAL ( offset ) - SPARC_STACK_BIAS ) & ( desired - <NUM_LIT> )


<s> OperandMatchResultTy parseBDLAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands ,


<s> if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( ( InputVector . getOpcode ( ) == <STR_LIT> || InputVector . getOpcode ( ) == <STR_LIT> ) && InputVector . getOperand ( <NUM_LIT> ) == EltIdx ) { assert ( SrcVT == InputVector . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Scl = InputVector . getOperand ( <NUM_LIT> ) ; Scl = DAG . getNode ( <STR_LIT> , dl , SrcVT . getScalarType ( ) , Scl ) ; return DAG . getZExtOrTrunc ( Scl , dl , VT ) ; } return SDValue ( ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineHorizontalMinMaxResult ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineReductionToHorizontal ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG ) ) return V ; if ( CIdx && SrcVT . getScalarType ( ) == <STR_LIT> ) { SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; auto IsBoolExtract = [ & BoolExtracts ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Use ->

getOperand ( <NUM_LIT> ) ) && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) {


<s> } case Instruction :: PtrToInt : { if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > (


<s> bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second .

getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ;


<s> return get_hard_reg_initial_val ( HImode


<s> assert ( MOP . isReg ( ) && <STR_LIT> ) ; OriginalCall -> addOperand ( MachineOperand :: CreateReg ( MOP . getReg ( ) , false , true ) ) ; RegMaskStartIdx ++ ; } for ( ; RegMaskStartIdx < MI . getNumOperands ( ) ; ++ RegMaskStartIdx ) OriginalCall -> addOperand ( MI . getOperand ( RegMaskStartIdx ) ) ; auto * Marker = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) -> moveCallSiteInfo ( & MI , Marker ) ; MI . eraseFromParent ( ) ; finalizeBundle ( MBB , OriginalCall -> getIterator ( ) , std :: next ( Marker -> getIterator ( )


<s> static const MVT VTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; return DAG . getBitcast ( ReqVT , DAG . getConstant ( Val , dl ,


<s> static bool isEqual ( const SlotWithTag & A , const


<s> op2_hi_lo [ i ] = GEN_INT ( sub_value ) ; if ( code == AND && sub_value != - <NUM_LIT> && sub_value != <NUM_LIT> && ! and_operand ( op2_hi_lo [ i ] , SImode ) ) op2_hi_lo [ i ] = force_reg ( SImode , op2_hi_lo [ i ] ) ; } } } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( ( code == IOR || code == XOR ) && GET_CODE ( op2_hi_lo [ i ] ) == CONST_INT && ! complement_final_p && ! complement_op1_p && ! complement_op2_p && ! logical_const_operand ( op2_hi_lo [ i ] , SImode ) ) { HOST_WIDE_INT value = INTVAL ( op2_hi_lo [ i ] ) ; HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C ( <NUM_LIT> ) ; HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C ( <NUM_LIT> ) ; rtx tmp = gen_reg_rtx ( SImode ) ; if ( ( hi_16bits & sign_bit ) != <NUM_LIT> ) hi_16bits |= upper_32bits ; rs6000_split_logical_inner ( tmp , op1_hi_lo [ i ] , GEN_INT ( hi_16bits ) ,

code , SImode , false , false , false ) ;


<s> unsigned ImmIdx = ~ <NUM_LIT> ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; int Cost = <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return <ISA_LIT>TTIImpl :: getIntImmCost ( Imm ,


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; bool Success = true ; if ( VReg ) { const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex


<s> case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerBUILD_<ISA_LIT>CTOR ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_<ISA_LIT>CTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_<ISA_LIT>CTOR_ELT ( Op , DAG ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Op -> print ( dbgs ( ) ) ; ) ; if ( <STR_LIT> ( Opcode ) ) return lowerToVVP ( Op , DAG ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( getAnnotatedNodeAVL ( Op ) . second ) return Op ; return legalizeInternalVectorOp ( Op , DAG


<s> reportParseError ( ExprLoc , <STR_LIT> ) ; return false ; } Save = OffsetVal ; SaveIsReg = false ; } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } Save = SaveOpnd . getGPR32Reg ( ) ; } if ( ! eatComma ( <STR_LIT> ) ) return true ; const MCExpr * Expr ; if ( Parser . parseExpression ( Expr ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) { reportParseError ( <STR_LIT> ) ; return false


<s> } if ( lFromVEX2of2 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vexXopType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> prefixPresent [ <NUM_LIT> ] && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const char * specName , * specWithOpSizeName ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specName = x86DisassemblerGetInstrName ( instructionID , miiArg ) ; specWithOpSizeName = x86DisassemblerGetInstrName ( instructionIDWithOpsize , miiArg ) ; if ( is16BitEquivalent ( specName , specWithOpSizeName ) ) { insn -> instructionID = instructionIDWithOpsize ; insn -> spec = specifierForUID ( instructionIDWithOpsize ) ; } else { insn -> instructionID = instructionID ; insn -> spec = spec ; } return <NUM_LIT> ; } if ( insn -> opcodeType == ONEBYTE && insn -> opcode == <NUM_LIT> && insn -> rexPrefix & <NUM_LIT> ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithNewOpcode ; const struct InstructionSpecifier * specWithNewOpcode ; spec = specifierForUID ( instructionID ) ; insn -> opcode = <NUM_LIT> ; if ( getIDWithAttrMask ( & instructionIDWithNewOpcode , insn , attrMask ) ) { insn -> opcode = <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specWithNewOpcode = specifierForUID ( instructionIDWithNewOpcode ) ; insn -> opcode = <NUM_LIT> ; insn -> instructionID =


<s> SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , N -> getValueType ( <NUM_LIT> ) ) ; unsigned Opc = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( SN -> hasOneUse ( ) ) CurDAG -> SelectNodeTo ( SN , Opc , N -> getValueType ( <NUM_LIT> ) , TFI , getSmallIPtrImm ( Offset


<s> SDLoc DL ( Op ) ; uint64_t AlignVal = ( RealignOpt ? dyn_cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) : <NUM_LIT> ) ; uint64_t StackAlign = TFI -> getStackAlignment ( ) ; uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result ,


<s> if ( getTargetMachine ( ) . getOptLevel ( ) != <NUM_LIT>

&& HasAtomicCmpXchg ) return AtomicExpansionKind :: LLSC ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMCInst .


<s> tree decl = SYMBOL_REF_DECL ( symbol ) ; if ( decl && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl )


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc ==

<STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) {


<s> if ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || CONST_INT_P ( x ) || GET_CODE ( x ) == HIGH ) return true ; if ( GET_CODE ( x ) != CONST ) return false ; if ( flag_pic && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT>


<s> case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && prior ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) , & MF . getTarget ( ) ) ; while ( ++ Start != llvm ::


<s> unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = GetOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBOffsets [ DestBB -> getNumber ( ) ] ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << GetOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <=


<s> ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return false ; if ( ! performCustomAdjustments ( MI , NewOpc , ST ) ) return false ; MI . setDesc ( TII -> get ( NewOpc )


<s> int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) . getFixed ( ) ; int EndOffset = - EHRegOffset - EHRegSize ; FuncInfo . EHRegNodeEndOffset = EndOffset ; if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if ( UsedReg == BasePtr ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI -> getSEHFramePtrSaveIndex (


<s> MachineOperand * OldFlagDef2 = OldMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( ! OldFlagDef1 == ! OldFlagDef2 && <STR_LIT> ) ; if ( ! OldFlagDef1 || ! OldFlagDef2 ) return ; assert ( OldFlagDef1 -> isDead ( ) && OldFlagDef2 -> isDead ( ) && <STR_LIT> ) ; MachineOperand * NewFlagDef1 = NewMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * NewFlagDef2 = NewMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( NewFlagDef1 && NewFlagDef2 && <STR_LIT> ) ; NewFlagDef1 -> setIsDead (


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI ,


<s> return decodeRegisterClass ( Inst , RegNo


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , bool


<s> return false ; case Match_MissingFeature : { assert ( MissingFeatures . any ( ) && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = MissingFeatures . size ( ) ; I != E ; ++ I ) { if ( MissingFeatures [ I ] ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( I ) ; } } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> )


<s> VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store


<s> static void ix86_override_options_after_change


<s> if ( ParseSuffix && Kind . empty ( ) ) return MatchOperand_NoMatch ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEDataVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , S , getContext


<s> } else if ( MEM_P ( slot ) ) { addr = XEXP ( slot , <NUM_LIT> ) ; if ( ! register_operand ( addr , Pmode ) ) addr = copy_addr_to_reg ( addr ) ; } else gcc_unreachable ( ) ; return addr


<s> void sparc_emit_floatunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out ; out = operands [ <NUM_LIT> ] ; in = force_reg ( DImode , operands [ <NUM_LIT> ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0 , i1 ) ) ; emit_insn ( gen_rtx_SET ( f0 , gen_rtx_FLOAT ( mode , i0 )


<s> static DecodeStatus DecodeBranchTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) *


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm

( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Op -> getStartLoc ( ) , Context ) ; const MCExpr * Imm = MCConstantExpr :: Create ( <NUM_LIT> , Context ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Imm , Op2 -> getStartLoc ( ) , Op2 -> getEndLoc ( ) , Context ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShifter ( <STR_LIT> , <NUM_LIT> , Op2 -> getStartLoc


<s> return ( uint8x16_t ) __builtin_neon_vclzv16qi ( (


<s> return MCDisassembler :: Success ; } unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: SoftFail ; return MCDisassembler ::


<s> int ix86_data_alignment ( tree type , int align ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= <NUM_LIT> || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= <NUM_LIT> || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; int BccOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB (


<s> return ( __m128d ) __builtin_ia32_rsqrt28sd_mask_round ( ( __v2df ) __B , ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) ,


<s> return getExistingMachineCPValueImpl < <ISA_LIT>ConstantPoolMBB >


<s> gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call


<s> if ( pcum -> iwmmxt_nregs <= <NUM_LIT> ) return gen_rtx_REG ( mode , pcum -> iwmmxt_nregs + FIRST_IWMMXT_REGNUM ) ; else { pcum -> can_split = false ; return NULL_RTX ; } } if ( pcum -> nregs & <NUM_LIT> && ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type ) ) pcum -> nregs ++ ; if ( pcum -> can_split ) nregs = <NUM_LIT> ; else nregs = ARM_NUM_REGS2 ( mode , type ) ; if ( ! named || pcum -> nregs + nregs > NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , pcum ->


<s> if ( emitted_frame_related_regs [ r ] == <NUM_LIT> ) emitted_frame_related_regs [ r ] = current_frame_info . r [ r ] ; else gcc_assert ( emitted_frame_related_regs [ r ] == current_frame_info . r [


<s> RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; } <ISA_LIT>cc = DAG . getConstant ( CondCode


<s> if ( ! AfterBBI -> modifiesRegister ( Reg , TRI ) ) continue ; if ( AfterBBI -> getOpcode ( ) != Opc ) break ; assert ( AfterBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! AfterBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) || AfterBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != Imm ) break ; if ( DeadOrKillToUnset ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * DeadOrKillToUnset -> getParent ( ) ) ; if ( DeadOrKillToUnset -> isDef ( ) ) DeadOrKillToUnset -> setIsDead ( false ) ; else DeadOrKillToUnset -> setIsKill ( false ) ; } DeadOrKillToUnset = AfterBBI -> findRegisterDefOperand ( Reg , true , true , TRI ) ; if ( DeadOrKillToUnset ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; InstrsToErase . insert ( & * AfterBBI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AfterBBI -> dump ( ) ) ; } } for ( MachineInstr * MI : InstrsToErase ) { MI -> eraseFromParent ( ) ; } NumRemovedInPreEmit += InstrsToErase . size


<s> gcc_assert ( n_args <= ( int ) ARRAY_SIZE ( args ) ) ; for ( a = n_args - <NUM_LIT> ; a >= <NUM_LIT> ; a -- ) args [ a ] = NULL_TREE ; for ( a = n_args ; a >= <NUM_LIT> ; a -- ) { switch ( s16builtins [ i ] . arg_types [ a ] ) { case 's' : arg


<s> char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_align ( POINTER_SIZE


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> __rv . __o = __builtin_neon_vld3_dupv2si ( ( const __builtin_neon_si * ) __a ) ; return __rv .


<s> return ( ( qword ) ( vec_splat ( ( vec_int4 ) ( si_from_int ( ( signed int ) ( imm ) ) ) ,


<s> Target & llvm :: getTheThumbBETarget ( ) { static Target TheThumbBETarget ; return TheThumbBETarget


<s> static int vax_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( <NUM_LIT> + ( REG_P ( x ) ? <NUM_LIT> : vax_address_cost_1 ( x


<s> if ( ! satisfies_constraint_Is15 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == <NUM_LIT> && NDS32_HALF_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is16 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == <NUM_LIT> && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is17 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == <NUM_LIT> && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is17 ( gen_int_mode ( INTVAL ( index ) + <NUM_LIT> , SImode ) ) ) return false ; return true ; } return false ; case MULT : op0 = XEXP ( index , <NUM_LIT> ) ; op1 = XEXP ( index , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int multiplier ; multiplier = INTVAL ( op1 ) ; if ( multiplier != <NUM_LIT> && multiplier != <NUM_LIT> &&

multiplier != <NUM_LIT> ) return false ;


<s> static bool matchSplitStoreZero128 ( MachineInstr & MI , MachineRegisterInfo & MRI ) { GStore & Store = cast < GStore > ( MI ) ; if ( ! Store . isSimple ( ) ) return false ; LLT ValTy = MRI . getType ( Store . getValueReg ( ) ) ; if ( ! ValTy . isVector ( ) || ValTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ValTy . getSizeInBits ( ) != Store . getMemSizeInBits ( ) ) return false ; if ( ! MRI . hasOneNonDBGUse ( Store . getValueReg ( ) ) ) return false ; auto MaybeCst = isConstantOrConstantSplatVector ( * MRI . getVRegDef ( Store .


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT>


<s> MachineInstr * Call = & * -- MBB . instr_end ( ) ; unsigned TailOpcode ; if ( Call -> getOpcode ( ) == <STR_LIT> ) { TailOpcode = <STR_LIT> ; } else { assert ( Call -> getOpcode ( ) == <STR_LIT> ) ; TailOpcode = <STR_LIT> ; } MachineInstr * TC = BuildMI ( MF , DebugLoc ( ) , get ( TailOpcode ) ) . add ( Call -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB . insert ( MBB . end ( ) , TC ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset


<s> unsigned <ISA_LIT>FastISel :: emitSMULL_rr ( MVT RetVT , unsigned Op0 , bool Op0IsKill


<s> return ( __m64 ) __builtin_ia32_pmulhuw ( ( __v4hi ) __A ,


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , RM ( _RM ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = O32 ; UseSmallSection = UseSmallSectionOpt


<s> inline int getFP64Imm ( const APFloat & FPImm ) { return getFP64Imm ( FPImm .


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = <NUM_LIT>


<s> MCDisassembler ( STI ) , isBigEndian