<s> case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL_V2I64 ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op


<s> Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdDup , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> unsigned Opc = MBBI -> getOpcode ( ) ; if ( MBBI -> readsRegister ( Base ) ) { int Offset ; bool IsLoad = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( MBBI ) || MBBI -> isCall ( ) || MBBI


<s> StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; if ( Arch . empty ( ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ArchFeatureName . empty ( ) ) return reportParseError ( <STR_LIT> ) ; if ( ArchFeatureName == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) )


<s> unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , A , B ,


<s> void Emitter < CodeEmitter > :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI ,


<s> return __builtin_mve_vshlq_r_sv16qi ( __a ,


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( Size == <NUM_LIT> && <STR_LIT> ) ; auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size


<s> } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <=


<s> auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; auto & RegClass = Is64Bit ? <STR_LIT> : <STR_LIT> ; for ( auto Candidate : RegClass ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && ( TRI -> isSubRegisterEq ( MO . getReg ( ) , Candidate ) || TRI -> isSuperRegister ( MO . getReg ( ) , Candidate ) ) ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] = Candidate ; if ( FoundRegs == ( unsigned ) NumPops ) break ; } if ( FoundRegs ==


<s> for ( i = <NUM_LIT> ; i < count - <NUM_LIT> ; i ++ ) XVECEXP ( vector , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == <NUM_LIT> ? stack_pointer_rtx : plus_constant

( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ;


<s> unsigned ConstPos = <NUM_LIT> ; MachineInstr * ConstMI = nullptr ; for ( MachineInstr & MI : MF . front ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> && SS == MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) { ConstMI = & MI ; break ; } ++ ConstPos ; } assert ( ConstMI && <STR_LIT> ) ; unsigned AMXRegNum = TRI -> getRegClass ( <STR_LIT> ) -> getNumRegs ( ) ; SmallVector < Register , <NUM_LIT> > Phys2Virt ( AMXRegNum , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI . reg_nodbg_empty ( VirtReg ) ) continue ; if ( MRI . getRegClass ( VirtReg ) -> getID ( ) != <STR_LIT> ) continue ; unsigned Index = VRM . getPhys ( VirtReg ) - <STR_LIT> ; if ( ! Phys2Virt [ Index ] ) Phys2Virt [ Index ] = VirtReg ; } for ( unsigned I = <NUM_LIT> ; I < AMXRegNum ; ++ I ) { if ( ! Phys2Virt [ I ] ) continue ; DebugLoc DL ; bool IsRow = true ; MachineInstr * NewMI = nullptr ; ShapeT Shape = VRM . getShape ( Phys2Virt [ I ] ) ; for ( auto & R : { Shape . getRow ( ) -> getReg ( ) , Shape . getCol ( ) -> getReg ( ) } ) { int64_t Imm = INT64_MAX ; int Offset = IsRow ? <NUM_LIT> + I : <NUM_LIT> + I * <NUM_LIT> ; for ( auto & DefMI : MRI . def_instructions ( R ) ) { MachineBasicBlock & MBB = * DefMI . getParent ( ) ; if ( DefMI . isMoveImmediate ( ) ) { if ( Imm != INT64_MAX ) { assert ( Imm == DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) && <STR_LIT> ) ; continue ; } Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; NewMI = addFrameReference ( BuildMI ( MF . front ( ) , ++ ConstMI -> getIterator ( ) , DL , TII -> get ( IsRow ? <STR_LIT> : <STR_LIT> ) ) , SS , Offset ) . addImm ( Imm ) ; ConstMI = NewMI ; LIS . InsertMachineInstrInMaps ( * NewMI ) ; } else { unsigned SubIdx = IsRow ? <STR_LIT> :


<s> static bool sparc_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '#' || code == '*' || code == '(' || code == ')' || code == '_' || code == '&' ) return true ; return


<s> static bool get<ISA_LIT>StoreDeprecationInfo ( MCInst & MI , const MCSubtargetInfo & STI , std :: string & Info ) { assert ( ! STI . getFeatureBits ( ) [ llvm


<s> return ( __m128i ) __builtin_ia32_vpcomeqb ( ( __v16qi )


<s> int OpcodeIndex = <NUM_LIT> ; if ( RC != nullptr ) { if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SPESpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SPE4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex =


<s> ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy ) , <NUM_LIT> ) ; assert ( NumSrcVecs >= NumDstVecs && <STR_LIT> ) ; NumPermutes += std :: max ( <NUM_LIT> , NumSrcVecs - NumDstVecs ) ; } } else { unsigned NumSrcVecs = std :: min ( NumEltsPerVecReg , Factor ) ; unsigned NumDstVecs = NumVectorMemOps ; assert ( NumSrcVecs > <NUM_LIT> && <STR_LIT> ) ; NumPermutes += ( NumDstVecs * NumSrcVecs ) - NumDstVecs ; } return NumVectorMemOps


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelaPLT ( ) const { assert ( m_pRelaPLT != NULL


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool *


<s> return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) return true ; return cast < ConstantSDNode > ( Op )


<s> if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Result , StackSlot , DAG . getValueType ( Op . getValueType ( ) ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops


<s> EVT DstTy = Op . getValueType ( ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> && ( ! Subtarget . is64Bit ( ) || ! isScalarFPTypeInSSEReg ( TheVT ) ) ; if ( ! IsSigned && DstTy != <STR_LIT> && ! Subtarget . hasAVX512 ( ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget . is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; unsigned Opc ; switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( )

, TheVT ) , Value , ThreshVal , <STR_LIT> ) ;


<s> if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : return CCmode ; } case CCFPmode


<s> break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand (


<s> next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( &


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return &


<s> Value * OldSP = getReg ( <STR_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( getContext ( ) , OldSP -> getType ( ) -> getIntegerBitWidth ( ) ) , OpSize ) ; Value * NewSP = Builder . CreateSub ( OldSP , OpSizeVal ) ; Value * SPPtr = Builder . CreateIntToPtr ( NewSP , Val -> getType ( ) -> getPointerTo ( ) ) ; Builder . CreateStore ( Val , SPPtr


<s> static rtx arm_load_tp ( rtx target ) { if ( ! target ) target = gen_reg_rtx ( SImode ) ; if ( TARGET_HARD_TP ) { emit_insn ( gen_load_tp_hard (


<s> case <STR_LIT> : { const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; return NewMI ; } } if ( ! MI . isConvertibleTo3Addr ( ) ) return nullptr ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( ST -> isAtom ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( ) ) return


<s> if ( IsBase ) AM . Base = Value ; else AM . Index


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma (

) || parseImmExpr ( Offset ) ) return true ;


<s> StringRef getPassName ( ) const override { return


<s> return ( poly64x2_t ) __builtin_neon_vsli_nv2di ( ( int64x2_t ) __a ,


<s> Function * ThreadPointerFunc = <STR_LIT> ( M , <STR_LIT> ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) ->


<s> void <ISA_LIT>TargetStreamer :: emitMovSP ( unsigned Reg , int64_t Offset ) { llvm_unreachable (


<s> } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; } } else if ( searchForward ( MBB , I ) ) { Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } ++ FilledSlots ; Changed = true ; continue ; } } if ( ( InMicro<ISA_LIT>Mode || ( STI . has<ISA_LIT>32r6 ( ) && <ISA_LIT>CompactBranchPolicy != CB_Never ) ) && TII -> getEquivalentCompactForm ( I ) ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc


<s> bool isExtend ( ) const { if ( isShifter ( ) ) { <STR_LIT> ST = <STR_LIT> ( Shifter .


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , N -> getValueType ( <NUM_LIT> ) ) ; unsigned Opc = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( SN -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( SN , Opc , N -> getValueType ( <NUM_LIT> ) , TFI , getSmallIPtrImm (


<s> unsigned GPReg = IsN64 ? <STR_LIT> : <STR_LIT> ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) ->


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; model_rtx = operands [ <NUM_LIT> ] ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx ,


<s> rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn )


<s> void <ISA_LIT>CCState :: PreAnalyzeReturnForVectorFloat ( const SmallVectorImpl < <STR_LIT> > & Outs ) { for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { <STR_LIT> Out = Outs [ i ] ; OriginalRetWasFloatVector . push_back ( originalEVTTypeIsVectorFloat ( Out . ArgVT


<s> assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( )


<s> int SplatValue = * FirstDefinedIdx ; if ( any_of ( make_range ( std :: next ( FirstDefinedIdx ) , Mask . end ( ) ) , [ & SplatValue ] ( int Elt ) { return Elt >= <NUM_LIT> && Elt != SplatValue ; } ) ) return None ; return


<s> uint64_t Val = <NUM_LIT> ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; I . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Val ) ; } else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned NewOpc ; switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : { if ( isInt < <NUM_LIT> > ( Val ) ) NewOpc = <STR_LIT> ; else NewOpc = <STR_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; InVals . push_back ( ArgValue ) ; } else { unsigned Offset = VA . getLocMemOffset ( ) ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Load ; if ( VA . getValVT ( ) == <STR_LIT> ) { Load = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else


<s> SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; N01 = peekThroughBitcasts ( N01 ) ; if ( ! <STR_LIT> ( N01 . getNode ( ) ) ) { if ( ! VT . is256BitVector ( ) || N01 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V1 = N01 ->


<s> } if ( rs6000_hard_regno_nregs [ m ] [ r ] > <NUM_LIT> ) len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) , rs6000_hard_regno_nregs [ m ] [ r ] ) ; else len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) ) ; comma = <STR_LIT> ; } if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> )


<s> static bool aarch64_advsimd_ldp_stp_p ( enum vect_cost_for_stmt kind , stmt_vec_info stmt_info ) { switch ( kind ) { case vector_load : case vector_store : case unaligned_load : case unaligned_store : break ; default : return false


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : Res = LowerSADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N ,


<s> rtx cmp_result ; cmp_result = mips_expand_builtin_compare_1 ( icode , cond , exp , <NUM_LIT> ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; if ( type == MIPS_BUILTIN_MOVT ) { mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] , exp , <NUM_LIT> ) ; mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] , exp , <NUM_LIT> ) ; } else { mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] ,


<s> } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx =


<s> assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntUnary ( Op , DAG ) ; SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> static SDValue LowerSDIV ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , EltTy ) ) ; SDValue SGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT> , dl , VT , & Sz [ <NUM_LIT> ] , NumElts ) ) ; SmallVector < SDValue , <NUM_LIT> > Amt ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - Lg2 , EltTy ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , dl , VT , SGN , DAG . getNode ( <STR_LIT> , dl , VT , & Amt [ <NUM_LIT> ] , NumElts ) ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBZDisplacementBits ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> , Base ,


<s> OperandMatchResultTy parseFP32 ( OperandVector


<s> static DecodeStatus DecodeG8RC_NOX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const


<s> if ( isSetCC ( Op , Info ) ) return true ; return ( ( Op . getOpcode ( ) == <STR_LIT> ) && isSetCC ( Op ->


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crcc_w_w_w ( int _1 , int _2 ) { return ( int ) __builtin_loongarch_crcc_w_w_w ( ( int ) _1


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForReturn ( ) const { return RetCC_<ISA_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( CurDAG -> getTargetConstant ( RegClassIDs [ Regs . size ( ) - <NUM_LIT> ] , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Regs . size ( ) ; ++ i ) { Ops . push_back ( Regs [ i ]


<s> unsigned Reg = MI . getOperand ( I ) . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; if ( RegNo != <NUM_LIT> ) res ++ ; else res |= <NUM_LIT> ; } return


<s> return ( __m256 ) __builtin_ia32_loadaps256_mask ( ( __v8sf * ) __P , ( __v8sf


<s> SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; updateValueMap ( I , SrcReg


<s> break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getScalarSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } else if ( ElemBitSize ==


<s> SDValue ArgValue ; CCValAssign & VA = ArgLocs [ I ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea


<s> case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT>


<s> unsigned llvm :: get512BitSuperRegister ( unsigned Reg ) { if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return <STR_LIT> + ( Reg - <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return <STR_LIT> + ( Reg - <STR_LIT> ) ; if ( Reg >= <STR_LIT> &&


<s> unsigned Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ,

<STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ;


<s> void addZeroOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = VT . getSizeInBits (


<s> MCFragment * <ISA_LIT>AuthMCExpr :: findAssociatedFragment ( ) const { llvm_unreachable (


<s> return DecodeCPURegsRegisterClass ( Inst , RegNo , Address , Decoder


<s> gcc_assert ( GET_CODE ( rhs ) == REG ) ; arm_regno = REGNO ( rhs ) ; } first = next_nonnote_insn ( first ) ; if ( ! arm_cirrus_insn_p ( first ) ) return ; body = PATTERN ( first ) ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( body ) == FLOAT ) body = XEXP ( body , <NUM_LIT> ) ; if ( get_attr_cirrus ( first ) == CIRRUS_MOVE && GET_CODE ( XEXP ( body , <NUM_LIT> ) ) == REG && arm_regno == REGNO ( XEXP ( body , <NUM_LIT> ) ) ) emit_insn_after ( gen_nop ( ) , first ) ; return ; } } if ( ! first || GET_CODE ( first ) != INSN || GET_CODE ( PATTERN ( first ) ) == USE || GET_CODE ( PATTERN ( first ) ) == CLOBBER ) return ; attr = get_attr_cirrus (


<s> int i ; for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , <NUM_LIT> , i ) ) ) return true ; } return false


<s> inline vector signed int vec_vupklsh (


<s> gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute


<s> if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; if ( Idx -> getOpcode ( ) == <STR_LIT> ) { SDValue AllOnes = Vec -> getOperand ( <NUM_LIT> ) ; SDValue Pred = Vec -> getOperand ( <NUM_LIT> ) ; if ( getIntrinsicID ( Idx . getNode ( ) ) == <STR_LIT> && Idx -> getOperand ( <NUM_LIT> ) . getNode ( ) == Vec . getNode ( ) && Vec -> getOpcode ( ) == <STR_LIT> && AllOnes -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode

> ( AllOnes -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( AllOnes -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) {


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SDNode * Unzip = N0 . getNode ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; Ops . push_back ( Unzip -> getOperand (


<s> std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { if ( Constraint . size ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 's' && tolower ( Constraint [ <NUM_LIT> ] ) == 't' && Constraint [ <NUM_LIT> ] == '(' && ( Constraint [ <NUM_LIT> ] >= '0' && Constraint [ <NUM_LIT> ] <= '7' ) && Constraint [ <NUM_LIT> ] == ')' && Constraint [ <NUM_LIT> ] == '}' ) { Res . first = <STR_LIT> + Constraint [ <NUM_LIT> ] - '0' ; Res . second = & <STR_LIT> ; return Res ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } if ( Constraint == <STR_LIT> ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } return Res ; } if ( Res . second -> hasType ( VT ) || VT == <STR_LIT> ) return Res ; const TargetRegisterClass * Class = Res . second ; if ( isGRClass ( * Class ) ) { unsigned Size = VT . getSizeInBits ( ) ; if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; unsigned DestReg = get<ISA_LIT>SubSuperRegisterOrZero ( Res . first , Size ) ; if ( DestReg > <NUM_LIT> ) { Res . first = DestReg ; Res . second = Size == <NUM_LIT> ? & <STR_LIT> : Size == <NUM_LIT> ? & <STR_LIT> : Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; assert ( Res . second -> contains ( Res . first ) && <STR_LIT> ) ; } else { Res . first = <NUM_LIT> ; Res . second = nullptr ; } } else if ( isFRClass ( * Class ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) Res . second = & <STR_LIT> ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else { Res . first = <NUM_LIT> ; Res . second = nullptr


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return


<s> if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; if ( ! IsLoad && Subtarget -> hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( Subtarget -> hasInt256 ( ) && Ld . getValueType


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return


<s> AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; } const MachineOperand & MO = I -> getOperand ( structSizeOpNum ) ; if ( ! MO . isImm ( ) ) return false ; StructSize = MO . getImm ( ) ; return true


<s> unsigned Vd = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = Val & <NUM_LIT> ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> )


<s> bool <ISA_LIT>TTIImpl :: isWideningInstruction ( Type * DstTy , unsigned Opcode , ArrayRef < const Value * > Args ) { auto toVectorTy = [ & ] ( Type * ArgTy ) { return FixedVectorType :: get ( ArgTy -> getScalarType ( ) , cast < VectorType > ( DstTy ) -> getNumElements ( ) ) ; } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction ::


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [


<s> static DecodeStatus DecodeAddiur2Simm7 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> Subtarget ( * this , M , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) { if ( Subtarget . hasABICall ( ) ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getCodeModel ( ) == CodeModel ::

Default ) setCodeModel ( CodeModel :: Small ) ;


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , VT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> return ( int32x2_t ) __builtin_neon_vdup_lanev2si (


<s> Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { initAsmInfo (


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand ::


<s> machine_mode v2mode ; rtx x ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = gen_rtx_VEC_CONCAT ( v2mode


<s> sri -> icode = code_for_aarch64_reload_movcp ( mode , DImode ) ; return NO_REGS ; } if ( REG_P ( x ) && ( mode == TFmode || mode == TImode ) && mode == GET_MODE ( x ) && FP_REGNUM_P ( REGNO ( x ) ) && ! TARGET_SIMD && reg_class_subset_p ( rclass , FP_REGS ) ) { sri -> icode = code_for_aarch64_reload_mov ( mode ) ; return NO_REGS ; } if ( TARGET_FLOAT && rclass == GENERAL_REGS && known_eq ( GET_MODE_SIZE ( mode

) , <NUM_LIT> ) && MEM_P ( x ) ) return FP_REGS ;


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2

( ) ? new <ISA_LIT>FrameLowering ( * this , Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this , Subtarget ) ) {


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = TLI . getPointerTy ( DAG .


<s> const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I ,


<s> void EmitARM64WinCFISaveFRegX ( unsigned Reg , int Offset )


<s> if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void setGISelAccessor ( GISelAccessor &


<s> unsigned char <ISA_LIT>Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV


<s> case Others : break ; case CortexA35 : break ; case CortexA53 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA55 : break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case


<s> uint32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT>


<s> if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2AddrModeImm8s4 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> enum machine_mode op_mode ; enum rtx_code cond_code ; condition_rtx = rs6000_generate_compare ( code ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( TARGET_E500 && rs6000_compare_fp_p && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , <NUM_LIT> ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; enum machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , <NUM_LIT> ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx


<s> Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { Addr . Offset = <NUM_LIT> ; if ( ! IsSigned ) LoadOpc = <STR_LIT> ; else if ( <ISA_LIT>SubTarget . hasLFIWAX ( ) ) LoadOpc = <STR_LIT> ; } const TargetRegisterClass * RC = &


<s> static SDValue PerformSubCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N ,


<s> static section * loongarch_function_rodata_section (


<s> MachineInstr * DefMIToErase = nullptr ; if ( TII -> convertToImmediateForm ( MI , & DefMIToErase ) ) { Changed = true ; NumRRConvertedInPreEmit ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( DefMIToErase ) { InstrsToErase . push_back ( DefMIToErase ) ; } } } auto I = MBB . getFirstInstrTerminator ( ) ; if ( I == MBB . instr_end ( ) ) continue ; MachineInstr * Br = & * I ; if ( Br -> getOpcode ( ) != <STR_LIT> && Br -> getOpcode ( ) != <STR_LIT> ) continue ; MachineInstr * CRSetMI = nullptr ; unsigned CRBit = Br -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CRReg = getCRFromCRBit ( CRBit ) ; bool SeenUse = false ; MachineBasicBlock :: reverse_iterator It = Br , Er = MBB . rend ( ) ; for ( It ++ ; It != Er ; It ++ ) { if ( It -> modifiesRegister ( CRBit , TRI ) ) { if ( ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) && It -> getOperand ( <NUM_LIT> ) . getReg ( ) == CRBit ) CRSetMI = & * It ; break ; } if ( It -> readsRegister ( CRBit , TRI ) ) SeenUse = true ; } if ( ! CRSetMI ) continue ; unsigned CRSetOp = CRSetMI -> getOpcode ( ) ; if ( ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) || ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) ) { InstrsToErase . push_back ( Br ) ; MBB . removeSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; } else { MachineBasicBlock :: iterator It = Br , Er = MBB .


<s> unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: canLoadStoreByteSwapped ( EVT VT ) const { if ( VT == <STR_LIT> || VT == <STR_LIT> ||


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ) ; OutStreamer -> emitSymbolValue ( DotSym , <NUM_LIT> ) ; OutStreamer -> PopSection


<s> return ( __m64 ) __builtin_ia32_psllq ( __m ,


<s> auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; <ISA_LIT>PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT>


<s> OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR )


<s> ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = RoundUpToAlignment ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc )


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReferenceFromSP ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; assert ( ! RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getStackRegister


<s> static void swap_const_vector_halves ( rtx * op_ptr ) { int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT (


<s> vmull_high_s8 ( int8x16_t a , int8x16_t b ) { int16x8_t result


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPic0 ( ) { MCAssembler & MCA = getStreamer (


<s> if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo

( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> Addr = MaskedOp -> getBasePtr ( ) ; if ( TrueMaskElt != <NUM_LIT> ) { unsigned Offset = TrueMaskElt * EltVT . getStoreSize ( ) ; Addr = DAG . getMemBasePlusOffset ( Addr , Offset , SDLoc ( MaskedOp ) ) ; } Index = DAG . getIntPtrConstant ( TrueMaskElt , SDLoc ( MaskedOp )


<s> static bool DisassembleThumb1LdStMul ( bool Ld , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned tRt = getT1tRt ( insn ) ; NumOpsAdded = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , tRt ) ) ) ; ++ NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) { NumOpsAdded +=


<s> assert ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && <STR_LIT> ) ; unsigned index_align = insn >> <NUM_LIT>


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI . memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI . memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT>


<s> case HImode : case SImode : return true ; case QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT


<s> bool isGPRCalleeSavedArea2Frame ( int fi ) const { if ( fi < <NUM_LIT> || fi >= ( int ) GPRCS2Frames . size ( ) ) return false ; return GPRCS2Frames [ fi


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) ( MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ) ; else printOperand ( MI , OpNo , O


<s> EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return SDValue ( ) ; SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SDValue SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 .

getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ) ;


<s> return ( int16x8_t ) __builtin_neon_vqnegv8hi


<s> if ( <ISA_LIT>CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , EFLAG ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return SDValue (


<s> return ( __mmask8 ) __builtin_ia32_ucmpd256_mask ( ( __v8si ) __A , ( __v8si )


<s> else Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCExpr * Res = <ISA_LIT>MCTargetExpr :: Create ( Sym , <ISA_LIT>MCTargetExpr :: GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getExprForDwarfGlobalReference ( GV , Mang , MMI , Encoding , Streamer


<s> switch ( MI -> getOpcode ( ) ) { default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> CallingConv :: ID CC = CS . getCallingConv ( ) ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC ) return <NUM_LIT> ; if ( ! CS . paramHasAttr ( <NUM_LIT> ,

Attribute :: StructRet ) ) return <NUM_LIT> ;


<s> return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( false , isABI_O32 ( ) ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT>


<s> if ( loop -> ninsns <= <NUM_LIT> ) return MIN ( <NUM_LIT> , nunroll ) ; if ( loop -> ninsns <= <NUM_LIT> ) return MIN ( <NUM_LIT> , nunroll ) ; return <NUM_LIT>


<s> op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return


<s> if ( TARGET_HARD_FLOAT_ABI && TARGET_VFP ) size += <NUM_LIT> ; if ( TARGET_IWMMXT_ABI ) size += <NUM_LIT> ; } return size


<s> if ( ZeroVecIdx != UINT32_MAX ) { bool MaskFirst = true ; int ZeroIdx = - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx && I == <NUM_LIT> ) { ZeroIdx = <NUM_LIT> ; break ; } if ( OpNo != ZeroVecIdx && Byte == <NUM_LIT> ) { ZeroIdx = I + <STR_LIT> ; MaskFirst = false ; break ; } } if ( ZeroIdx != - <NUM_LIT> ) { SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { if ( Bytes [ I ] >= <NUM_LIT> ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx ) IndexNodes [ I ] = DAG . getConstant ( ZeroIdx , DL , <STR_LIT> ) ; else { unsigned BIdx = MaskFirst ? Byte + <STR_LIT> : Byte ; IndexNodes [ I ] = DAG . getConstant ( BIdx , DL , <STR_LIT> ) ; } } else IndexNodes [ I ] = DAG . getUNDEF ( <STR_LIT> ) ; } SDValue Mask = DAG . getBuildVector ( <STR_LIT> , DL , IndexNodes ) ; SDValue Src = ZeroVecIdx == <NUM_LIT> ? Ops [ <NUM_LIT> ] : Ops [ <NUM_LIT> ] ; if ( MaskFirst ) return DAG . getNode ( <STR_LIT> , DL ,


<s> if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <= Offset2


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t MIFlags = MCID . TSFlags ; if ( ( MIFlags & <STR_LIT> ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) ) { if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> ) ; create_address_operand ( & m_ops . last


<s> MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; DCI . recursivelyDeleteUnusedNodes ( LN ) ; return SDValue ( N


<s> UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return *


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; assert ( MF && <STR_LIT> ) ; switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; else return CSR_64_AllRegs_SaveList ; } else { if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; else return CSR_32_AllRegs_SaveList


<s> FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; unsigned VReg = MF . addLiveIn ( <STR_LIT> [ I ] , & <STR_LIT> ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; MemOps [ I ] = DAG . getStore ( ArgValue . getValue ( <NUM_LIT> ) , DL , ArgValue , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ; } Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue

> ( & MemOps [ NumFixedFPRs ] , <STR_LIT> - NumFixedFPRs ) ) ;


<s> if ( N0 . getOperand ( <NUM_LIT> ) == A ) B = N0 . getOperand ( <NUM_LIT> ) ; else if ( N0 . getOperand ( <NUM_LIT> ) == A ) B = N0 . getOperand ( <NUM_LIT> ) ; else return false ; SDLoc dl ( N ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ternlog = CurDAG -> getNode ( <STR_LIT> , dl , NVT , A , B , C , Imm ) ; ReplaceNode ( N , Ternlog . getNode ( ) ) ; SelectCode ( Ternlog . getNode


<s> return ! GenerateISEL || ! MF . getSubtarget < <ISA_LIT>Subtarget


<s> initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if (


<s> void setMaxCallFrameSize ( unsigned S


<s> } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , ANDVT , DAG . getNode ( <STR_LIT> , dl , ANDVT , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , ANDVT , Mask ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ,


<s> for ( auto LoadStoreInstPair : BlockedLoadsStoresPairs ) { MachineInstr * LoadInst = LoadStoreInstPair . first ; int64_t LdDispImm = getDispOperand ( LoadInst ) . getImm ( ) ; DisplacementSizeMap BlockingStoresDispSizeMap ; SmallVector < MachineInstr * , <NUM_LIT> > PotentialBlockers = findPotentialBlockers ( LoadInst ) ; for ( auto PBInst : PotentialBlockers ) { if ( ! isPotentialBlockingStoreInst ( PBInst -> getOpcode ( ) , LoadInst -> getOpcode ( ) ) || ! isRelevantAddressingMode ( PBInst ) ) continue ; int64_t PBstDispImm = getDispOperand ( PBInst ) . getImm ( ) ; assert ( PBInst -> hasOneMemOperand ( ) && <STR_LIT> ) ; unsigned PBstSize = ( * PBInst -> memoperands_begin ( ) ) -> getSize ( ) ; if ( hasSameBaseOpValue ( LoadInst , PBInst ) && isBlockingStore ( LdDispImm , getRegSizeInBytes ( LoadInst ) , PBstDispImm , PBstSize ) ) updateBlockingStoresDispSizeMap ( BlockingStoresDispSizeMap , PBstDispImm , PBstSize ) ; } if ( BlockingStoresDispSizeMap . empty ( ) ) continue ; MachineInstr * StoreInst = LoadStoreInstPair . second ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadInst -> dump ( ) ) ; DEBUG ( StoreInst -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; removeRedundantBlockingStores ( BlockingStoresDispSizeMap


<s> static <STR_LIT> getCondFromOpc ( unsigned Opc ) { <STR_LIT> CC = <STR_LIT> ; if ( CC == <STR_LIT> ) CC = <STR_LIT> ( Opc ) ; if ( CC == <STR_LIT> ) CC = <STR_LIT> ( Opc ) ; if ( CC == <STR_LIT> ) CC =


<s> unsigned TargetAlign = TFI -> getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ( maxCallFrameSize & ( MaxAlign - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( )


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++


<s> case CmpInst :: ICMP_SGE : if ( ( Size == <NUM_LIT> && static_cast < int64_t > ( C ) == INT64_MIN ) || ( Size == <NUM_LIT> && static_cast < int32_t > ( C ) == INT32_MIN ) ) return None ; P = ( P == CmpInst :: ICMP_SLT ) ? CmpInst :: ICMP_SLE : CmpInst :: ICMP_SGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_ULT : case CmpInst :: ICMP_UGE : if ( C == <NUM_LIT> ) return None ; P = ( P == CmpInst :: ICMP_ULT ) ? CmpInst :: ICMP_ULE : CmpInst :: ICMP_UGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_SLE : case CmpInst :: ICMP_SGT : if ( ( Size == <NUM_LIT> && static_cast < int32_t > ( C ) == INT32_MAX ) || ( Size == <NUM_LIT> && static_cast < int64_t > ( C ) == INT64_MAX ) ) return None ; P = ( P == CmpInst :: ICMP_SLE ) ? CmpInst :: ICMP_SLT : CmpInst :: ICMP_SGE ; C += <NUM_LIT> ; break ; case CmpInst :: ICMP_ULE : case CmpInst :: ICMP_UGT : if ( ( Size == <NUM_LIT> && static_cast < uint32_t > ( C ) == UINT32_MAX ) || ( Size == <NUM_LIT> &&


<s> SDValue VecIn2 ; SmallVector < unsigned , <NUM_LIT> > InsertIndices ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Opc = Op . getOperand ( i ) . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; int Idx = getUnderlyingExtractedFromVec ( ExtractedFromVec , ExtIdx ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( ! VecIn1 . getNode (


<s> switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering :: Acquire


<s> const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( MF , STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , MF ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , Info . IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB


<s> if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ) return CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ; if ( const <ISA_LIT>MCExpr * TE = dyn_cast < <ISA_LIT>MCExpr > ( Val ) ) { int64_t Res ; if ( TE -> EvaluateAsConstant ( Res ) ) return CreateContextImm ( Res , S , E , Is<ISA_LIT>64 ) ; } return CreateExpr ( Val , S , E


<s> return ( __m256d ) __builtin_ia32_gatherdiv4df ( ( __v4df ) src , base , ( __v4di ) index , (


<s> assert ( ( ~ STI . getFeatureBits ( ) & llvm :: <STR_LIT> ) && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> ) { Info = <STR_LIT> ; return


<s> bool hasRAS ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> ,


<s> MCRegAliasIterator AI ( J . getReg ( ) , TRI , true ) ; if ( J . isDead ( ) ) for ( ; AI . isValid ( ) ; ++ AI ) AvailableRegs . reset ( * AI ) ; else for ( ; AI . isValid ( ) ; ++ AI ) assert ( ! AvailableRegs [ * AI ] && <STR_LIT> ) ; } } } auto Ord = RCI . getOrder ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto Reg : Ord


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ) && MF . getFunction ( ) -> getCallingConv ( ) != CallingConv

:: HiPE && ! MF . shouldSplitStack ( ) ;


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( uint8_t REX = DetermineREXPrefix ( MI , TSFlags , MemOperand , Desc ) ) { EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; Ret = true ; } } else { assert ( ! ( TSFlags & <STR_LIT> ) && <STR_LIT> ) ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT>


<s> static void aarch64_override_options_after_change (


<s> xop [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> * ( words - <NUM_LIT> ) ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; output_asm_insn ( <STR_LIT> , xop ) ; return <STR_LIT> ; } else if ( i == <NUM_LIT> ) { xop [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> * ( words - <NUM_LIT> ) ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xop ) ; return <STR_LIT> ; } else { for ( j = <NUM_LIT> ; j < words ; j ++ ) if ( j != i ) { xop [ <NUM_LIT> ] = GEN_INT ( j * <NUM_LIT> ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + j ) ; output_asm_insn ( <STR_LIT> , xop ) ; } xop [ <NUM_LIT> ] = GEN_INT ( i * <NUM_LIT> ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; output_asm_insn ( <STR_LIT> , xop ) ; return <STR_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_cvtsepi16_storeu_epi8 ( void *


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new <ISA_LIT>PassConfig ( * this , &


<s> if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT>


<s> if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps