<s> SDValue InitVal = N -> getOperand ( <NUM_LIT> ) ; SDValue VecToReduce = N -> getOperand ( <NUM_LIT> ) ; EVT ReduceVT = VecToReduce . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; InitVal = DAG . getNode ( <STR_LIT> , DL , ReduceVT , DAG . getUNDEF ( ReduceVT ) , InitVal , Zero ) ; SDValue Reduce = DAG . getNode ( Opc , DL , ReduceVT , Pred , InitVal , VecToReduce ) ; return DAG . getNode ( <STR_LIT> , DL , N ->

getValueType ( <NUM_LIT> ) , Reduce , Zero ) ;


<s> int32_t Imm = Memory . OffsetImm -> getValue ( ) ; if ( Imm == INT32_MIN ) Imm = <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm (


<s> reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = ParseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal ( ) ; SaveIsReg = false ; Parser . Lex ( ) ; } else { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Save = SaveOpnd . getGPR32Reg ( ) ; } if ( ! eatComma ( <STR_LIT> ) ) return true ; StringRef Name ; if ( Parser . parseIdentifier ( Name


<s> OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT>


<s> static bool arm_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( TARGET_BIG_END && ! ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT> ) && ( GET_MODE_SIZE ( from ) > UNITS_PER_WORD || GET_MODE_SIZE ( to ) > UNITS_PER_WORD ) && reg_classes_intersect_p ( VFP_REGS , rclass ) ) return false ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerDarwinGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) .


<s> return gen_int_mode ( ENDIAN_LANE_N ( GET_MODE_NUNITS ( mode ) ,


<s> unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; APInt Lg2Mask = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , Lg2 ) ; SDValue Pow2MinusOne = DAG . getConstant ( Lg2Mask , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CMov . getNode ( ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CMov , DAG . getConstant ( Lg2 , DL , <STR_LIT> ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA


<s> unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base . Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity +=


<s> if ( ! TARGET_HAVE_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> )


<s> static int isSimpleMove ( const MachineInstr * MI , int & FrameIndex , unsigned Flag ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> return isNarrowLoad ( MI . getOpcode (


<s> switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF ,


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; int br_code ; SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG , br_code ) ; return DAG . getNode ( br_code , dl , Op . getValueType


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI ,


<s> if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1


<s> LEASLInst . setOpcode ( <STR_LIT> ) ; LEASLInst . addOperand ( RD ) ; LEASLInst . addOperand ( RS1 ) ; LEASLInst . addOperand ( RS2 ) ; LEASLInst . addOperand ( Imm ) ; OutStreamer . emitInstruction ( LEASLInst ,


<s> UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; * code = _TEXASRU_FAILURE_CODE ( texasru ) ; return _TEXASRU_ABORT ( texasru )


<s> static bool rs6000_elf_in_small_data_p ( tree decl ) { if ( rs6000_sdata == SDATA_NONE ) return false ; if ( TREE_CODE ( decl ) == STRING_CST ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE (


<s> unsigned int fsr ; __asm__ ( <STR_LIT> : <STR_LIT> ( fsr ) ) ; fsr |=


<s> int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false


<s> void printi64mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( ! isBaseRegConflictPossible ( DAG , ClobberSet ) ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; if ( ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize || ConstantSize -> getZExtValue ( ) > Subtarget . getMaxInlineSizeThreshold ( ) ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg =


<s> void addAlignedMemory16Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst , N


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )


<s> if ( Load -> isInvariant ( ) ) return true ; const Value * V1 = Load -> getSrcValue ( ) ; const Value * V2 = Store -> getSrcValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( ) + Size ; if ( V1 == V2 && End1 == End2


<s> output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; return true


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ?

<STR_LIT> : <STR_LIT> , N . getValueType ( ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( FRegs [ getReg (


<s> return ( poly16x4_t ) __builtin_neon_vget_lowv8hi ( ( int16x8_t


<s> else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ; if ( St == Rrx ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex


<s> <STR_LIT> ShType = getShiftTypeForNode ( N ) ; if ( ShType == <STR_LIT> ) return false ; if ( ! AllowROR && ShType == <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; unsigned Val = RHS -> getZExtValue ( ) & ( BitSize - <NUM_LIT> ) ; unsigned ShVal = <STR_LIT> ( ShType , Val ) ; Reg = N . getOperand ( <NUM_LIT> ) ; Shift = CurDAG -> getTargetConstant ( ShVal , <STR_LIT> ) ; return isWorthFolding (


<s> unsigned getFPImm ( ) const { assert ( Kind == k_FPImm && <STR_LIT>


<s> if ( given_type ) warning ( <NUM_LIT> , <STR_LIT> , name , given_type ) ; else warning ( <NUM_LIT> , <STR_LIT> , name ) ; * no_add = true ; if ( TREE_CODE ( * node ) == POINTER_TYPE && ! gave_pointer_note ) { inform ( input_location , <STR_LIT> , <STR_LIT> ) ; gave_pointer_note = <NUM_LIT> ; } if ( TREE_CODE ( * node ) == ARRAY_TYPE &&


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) { RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this ,


<s> return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( isDo ( Start ) || Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } if ( ! RDA . isSafeToDefRegAt ( Start , MCRegister :: from ( <STR_LIT> ) ) )


<s> if ( Ty -> isVectorTy ( ) && cast < VectorType > ( Ty ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( cast < VectorType > ( Ty ) -> getNumElements ( ) < ProfitableNumElements ) { unsigned NumVecElts = cast < VectorType > (


<s> fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : mips_print_operand_reloc ( file , addr . offset , SYMBOL_CONTEXT_MEM , mips_lo_relocs ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file ,


<s> static bool aarch64_frint_unspec_p ( unsigned int u ) { switch ( u ) { case UNSPEC_FRINTZ : case UNSPEC_FRINTP : case UNSPEC_FRINTM : case UNSPEC_FRINTA : case UNSPEC_FRINTN : case UNSPEC_FRINTX : case UNSPEC_FRINTI : return


<s> unsigned CPUBitmask = <NUM_LIT> , FPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff , FPUTopSavedRegOff ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned FGR32RegSize = <STR_LIT> . getSize ( ) ; unsigned AFGR64RegSize = <STR_LIT> . getSize ( ) ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; for ( const auto &


<s> if ( ldm_p && REGNO_REG_CLASS ( regno ) == HI_REGS ) return <NUM_LIT> ; for ( ; indx >= first_indx ; indx -- ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , <NUM_LIT> , indx ) , <NUM_LIT> ) ) ; if ( REGNO_REG_CLASS ( regno ) == HI_REGS && ( regno != PC_REGNUM || ldm_p ) ) return <NUM_LIT> ; } return <NUM_LIT>


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_movemask_pi8 ( __m64 __A ) { unsigned long long p = <NUM_LIT> ; <NUM_LIT> ; return __builtin_bpermd ( p , __A ) ; unsigned int mask = <NUM_LIT> ; unsigned int r1 = __builtin_bpermd ( mask , __A ) & <NUM_LIT> ; unsigned int r2 = __builtin_bpermd ( mask , __A >> <NUM_LIT> ) & <NUM_LIT> ; unsigned int mask =


<s> if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const unsigned globalRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; globalRegs [ i ] != <NUM_LIT> ; ++ i ) { unsigned reg = globalRegs [


<s> shift_mask = ~ <NUM_LIT> ; shift_mask <<= INTVAL ( shiftop ) ; c = INTVAL ( andop ) ; lsb = c & - c ; if ( ( lsb & shift_mask ) == <NUM_LIT> ) return <NUM_LIT> ; return c == - lsb && lsb != <NUM_LIT> ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == <NUM_LIT> ) { shift_mask_high = ~ <NUM_LIT> ; if ( INTVAL ( shiftop ) > <NUM_LIT> ) shift_mask_high <<= INTVAL ( shiftop ) - <NUM_LIT> ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == <NUM_LIT>


<s> static DecodeStatus DecodeDaddiGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) << <NUM_LIT> ; bool HasRs = false ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs =


<s> static bool HasImplicitCPSRDef ( const MCInstrDesc & MCID ) { for ( const uint16_t * Regs = MCID . getImplicitDefs ( ) ; * Regs ; ++ Regs ) if ( * Regs ==


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex


<s> return create<ISA_LIT>AsmBackend ( T , MRI , TT


<s> case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return NULL_RTX ; eq_rtx = rs6000_emit_vector_compare ( EQ , op0 , op1 , dmode ) ; if ( ! eq_rtx )


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs


<s> AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>TargetMachine & Target = static_cast < <ISA_LIT>TargetMachine & > ( const_cast < TargetMachine & > ( MF . getTarget ( ) ) ) ; JTI = Target . getJITInfo ( ) ; II = Target . getInstrInfo ( ) ; TD = Target . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC , Subtarget -> isLittle ( ) ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ) emitInstruction ( * I ++ , * MBB ) ; } } while ( MCE . finishFunction ( MF ) ) ; return false


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> } SDValue V1Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getBitcast ( MaskVT , V1Mask ) , DAG . getBitcast ( MaskVT , V2 ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 ,


<s> assert ( ( Kills & Defs ) == <NUM_LIT> && <STR_LIT> ) ; while ( Kills && Defs ) { unsigned KReg = CountTrailingZeros_32 ( Kills ) ; unsigned DReg = CountTrailingZeros_32 ( Defs ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> << DReg << <STR_LIT> ) ; std :: swap ( Stack [ getSlot ( KReg ) ] , Stack [ getSlot ( DReg ) ] ) ; std :: swap ( RegMap [ KReg ] , RegMap [ DReg ] ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; Defs &= ~ ( <NUM_LIT> << DReg ) ; } if ( Kills && I != MBB -> begin ( ) ) { MachineBasicBlock :: iterator I2 = llvm :: prior ( I ) ; for ( ; ; ) { unsigned KReg = getStackEntry ( <NUM_LIT> ) ; if ( ! ( Kills & ( <NUM_LIT> << KReg ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; popStackAfter ( I2 ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; } } while ( Kills ) { unsigned KReg = CountTrailingZeros_32 ( Kills ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; freeStackSlotBefore ( I


<s> bool hasMatMulInt8 ( ) const { return HasMatMulInt8


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT>


<s> mips_block_move_straight ( dest , src , bytes_per_iter ) ; mips_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; mips_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src


<s> return __aarch64_vdupq_lane_p64 ( __a ,


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ?


<s> bool hasCn<ISA_LIT> ( ) const { return ( getSTI ( ) . getFeatureBits ( ) [


<s> void <ISA_LIT>PassConfig :: addPreEmitPass (


<s> extract_base_offset_in_addr ( mem_1 , & base , & offset ) ; gcc_assert ( base != NULL_RTX && offset != NULL_RTX ) ; msize = GET_MODE_SIZE ( mode ) ; stp_off_limit = msize * <NUM_LIT> ; off_val = INTVAL ( offset ) ; abs_off = ( off_val < <NUM_LIT> ) ? - off_val : off_val ; new_off = abs_off % stp_off_limit ; adj_off = abs_off - new_off ; if ( ( new_off + msize * <NUM_LIT> ) >= stp_off_limit ) { adj_off += stp_off_limit ; new_off -= stp_off_limit ; } if ( adj_off >= <NUM_LIT> ) return false ; if ( off_val < <NUM_LIT> ) { adj_off = - adj_off ; new_off = - new_off ; } mem_1 = change_address ( mem_1 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off ) ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; msize = GET_MODE_SIZE ( mode ) ; mem_2 = change_address ( mem_2 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize ) ) ; mem_3 = change_address ( mem_3 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; mem_4 = change_address ( mem_4 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = mem_4 ; } emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , plus_constant ( DImode , base , adj_off ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; t2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , t1 , t2 ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] ,


<s> if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) .

addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ;


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> mode != MODE_16BIT && isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> mode == MODE_16BIT && insn -> opcode == <NUM_LIT> ) { const struct InstructionSpecifier * spec ; spec = specifierForUID ( instructionID ) ; if ( x86OperandSets [ spec -> operands ] [ <NUM_LIT> ] . type == TYPE_REL8 ) { attrMask ^= ATTR_ADSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask )


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePersonality ( DirectiveID .


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _AX + index ; \ case TYPE_R32 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK : \ index &= <NUM_LIT> ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_VK_PAIR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0_K1 + ( index / <NUM_LIT> ) ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( ( index & <NUM_LIT> ) > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + ( index & <NUM_LIT> ) ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case

TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_BNDR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ case TYPE_MVSIBX : \ return prefix ## _XMM0 + index ; \ case TYPE_MVSIBY : \ return prefix ## _YMM0 + index ; \ case TYPE_MVSIBZ : \ return prefix ## _ZMM0 + index ; \ } \ }


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; int NumElts = VT . getVectorNumElements ( ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerVectorShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( VT . isInteger ( ) && ! Subtarget . hasAVX2 ( ) ) { int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) { if ( SDValue V = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getBitcast ( FpVT , V1 ) ; V2 = DAG . getBitcast ( FpVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F32VectorShuffle ( Op , V1 , V2 ,


<s> TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ text_coal_section ] ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL ,


<s> static bool LdStCopOpcode ( unsigned Opcode ) { if ( ( Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) || ( Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) ) return true ; return false


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> rtx fuse_ops [ <NUM_LIT> ] ; char insn_template [ <NUM_LIT> ] ; fuse_ops [ <NUM_LIT> ] = load_store_reg ; fuse_ops [ <NUM_LIT> ] = addis_reg ; if ( CONST_INT_P ( offset ) && satisfies_constraint_I ( offset ) ) { sprintf ( insn_template , <STR_LIT> , insn_str ) ; fuse_ops [ <NUM_LIT> ] = offset ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( offset ) == UNSPEC && XINT ( offset , <NUM_LIT> ) == UNSPEC_TOCREL ) { if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template ,


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N ,


<s> vmul_n_f32 ( float32x2_t a , float32_t b ) { float32x2_t result


<s> unsigned NumElems = Mask -> getNumOperands ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask -> getOperand ( i ) , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Mask -> getOperand ( i ) , i + NumElems ) ) return false ; return true


<s> if ( NumOps == <NUM_LIT> || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - <NUM_LIT> ] .

OperandType != MCOI :: OPERAND_PCREL ) return false ;


<s> HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasSlowDivide32 =


<s> unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo ::


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ! ( MFI -> hasCalls ( ) || MRI . isPhysRegUsed ( <STR_LIT> )

|| MRI . isPhysRegUsed ( <STR_LIT> ) || hasFP ( MF ) ) ;


<s> if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 )


<s> paddh_u ( uint16x4_t s , uint16x4_t t ) { return __builtin_loongson_paddh_u ( s


<s> unsigned getMVEVectorCostFactor ( ) const { return MVEVectorCostFactor


<s> static DecodeStatus DecodeMSA128Mem ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; switch ( Inst . getOpcode ( ) ) { default : assert ( false && <STR_LIT> ) ; return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; } return MCDisassembler :: Success


<s> if ( align & <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst


<s> if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; print_rtl_single ( dump_file , cbranch_insn ) ; } unsigned int dist = <NUM_LIT> ; for ( rtx_insn * i = next_nonnote_insn ( cbranch_insn ) ; i != NULL && dist < max_dist ; i = next_nonnote_insn ( i ) ) { const unsigned int i_len = get_attr_length ( i ) ; dist += i_len ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( i ) , i_len , dist ) ; if ( rtx_code_label * l = dyn_cast < rtx_code_label * > ( i ) ) { if ( l == cbranch_insn -> jump_target ( ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , dist ) ; return dist ; } break ; } } if ( dump_file ) fprintf ( dump_file , <STR_LIT>


<s> case tcGPRRegClassID : case tGPRRegClassID : case tGPREvenRegClassID : case tGPROddRegClassID : case tGPR_and_tGPREvenRegClassID : case tGPR_and_tGPROddRegClassID : case tGPREven_and_tcGPRRegClassID : case tGPREven_and_tGPR_and_tcGPRRegClassID : case tGPROdd_and_tcGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case HPRRegClassID : case


<s> bool is_against_zero ; if ( GET_MODE ( op1 ) != compare_mode && ( ! TARGET_ISEL || ! short_cint_operand ( op1 , VOIDmode ) ) ) return <NUM_LIT> ; if ( GET_MODE ( true_cond ) != result_mode ) return <NUM_LIT> ; if ( GET_MODE ( false_cond ) != result_mode ) return <NUM_LIT> ; if ( TARGET_P9_MINMAX && ( compare_mode == SFmode || compare_mode == DFmode ) && ( result_mode == SFmode || result_mode == DFmode ) ) { if ( rs6000_emit_p9_fp_minmax ( dest , op , true_cond , false_cond ) ) return <NUM_LIT> ; if ( rs6000_emit_p9_fp_cmove ( dest , op , true_cond , false_cond ) ) return <NUM_LIT> ; } if ( FLOAT_MODE_P ( compare_mode ) && ! FLOAT_MODE_P ( result_mode ) ) return <NUM_LIT> ; if ( ! FLOAT_MODE_P ( compare_mode ) ) { if ( TARGET_ISEL ) return rs6000_emit_int_cmove ( dest , op , true_cond , false_cond ) ; return <NUM_LIT> ; } is_against_zero = op1 == CONST0_RTX ( compare_mode ) ; if ( SCALAR_FLOAT_MODE_P ( compare_mode ) && flag_trapping_math && ! is_against_zero ) return <NUM_LIT> ; if ( code == UNLT || code == UNGT || code == UNORDERED || code == NE || code == LTGT || code == LT || code == UNLE ) { code = reverse_condition_maybe_unordered ( code ) ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; } if ( code == UNEQ && HONOR_NANS ( compare_mode ) ) return <NUM_LIT> ; if ( HONOR_INFINITIES ( compare_mode ) && code != GT && code != UNGE && ( ! CONST_DOUBLE_P ( op1 ) || real_isinf ( CONST_DOUBLE_REAL_VALUE ( op1 ) ) ) && ( ( ! rtx_equal_p ( op0 , false_cond ) && ! rtx_equal_p ( op1 , false_cond ) ) || ( ! rtx_equal_p ( op0 , true_cond ) && ! rtx_equal_p ( op1 , true_cond ) ) ) ) return <NUM_LIT> ; if ( ! is_against_zero ) { temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_MINUS ( compare_mode , op0 , op1 ) ) ) ; op0 = temp ; op1 = CONST0_RTX ( compare_mode ) ; } if ( ! HONOR_NANS ( compare_mode ) ) switch ( code ) { case GT : code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; break ; case UNGE : code = GE ; break ; case UNEQ : code = EQ ; break ; default : break ; } switch ( code ) { case GE : break ; case LE : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case ORDERED


<s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( )

== <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) {


<s> if ( GET_CODE ( symbol ) == SYMBOL_REF ) fprintf ( stderr , <STR_LIT> , XSTR ( symbol , <NUM_LIT> ) ) ; else { fprintf ( stderr , <STR_LIT> , GET_RTX_NAME ( GET_CODE ( symbol ) ) ) ; debug_rtx ( symbol ) ; } } if ( ! can_create_pseudo_p ( ) ) df_set_regs_ever_live ( TOC_REGISTER , true ) ; tocreg = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; tocrel = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol , tocreg ) , UNSPEC_TOCREL ) ; if ( TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ( ) ) return tocrel ; hi = gen_rtx_HIGH ( Pmode , copy_rtx ( tocrel


<s> if ( ! isa < MemSDNode > ( * UI ) ) return false ; } bool IsExtendedRegisterWorthFolding = isWorthFolding ( N ) ; if ( IsExtendedRegisterWorthFolding && RHS . getOpcode ( ) == <STR_LIT> && SelectExtendedSHL ( RHS , Size , true , Offset , SignExtend ) ) { Base = LHS ; DoShift = CurDAG -> getTargetConstant ( true , dl , <STR_LIT> ) ; return true ; } if ( IsExtendedRegisterWorthFolding && LHS . getOpcode ( ) == <STR_LIT> && SelectExtendedSHL ( LHS , Size , true , Offset , SignExtend ) ) { Base = RHS ; DoShift = CurDAG -> getTargetConstant ( true , dl , <STR_LIT> ) ; return true ; } DoShift = CurDAG -> getTargetConstant ( false , dl , <STR_LIT> ) ; <STR_LIT> Ext = <STR_LIT> ; if ( IsExtendedRegisterWorthFolding && ( Ext = getExtendTypeForNode ( LHS , true ) ) != <STR_LIT> ) { Base = RHS ; Offset = narrowIfNeeded ( CurDAG , LHS . getOperand ( <NUM_LIT> ) ) ; SignExtend = CurDAG -> getTargetConstant ( Ext == <STR_LIT> , dl , <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR8DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( ( VECTOR_MEM_VSX_P ( mode ) && mode != TDmode && mode != TFmode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size


<s> std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) <STR_LIT> || Hint . first == ( unsigned ) <STR_LIT> ) && Register :: isVirtualRegister ( Hint . second ) ) { unsigned OtherReg = Hint


<s> void addRegQFRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF ::


<s> SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT ResVT = Op . getSimpleValueType ( ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( Subtarget -> hasFp256 ( )


<s> return & InstrInfo -> getRegisterInfo (


<s> static DecodeStatus DecodeBranchConditionAlways ( MCInst & MI , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeAS ( MI , insn ,


<s> const TargetInstrDesc & getMemoryInstr ( unsigned Opc , int64_t Offset = <NUM_LIT> ) const { if ( Offset < <NUM_LIT> || Offset >= <NUM_LIT> ) return


<s> void EmitByte ( unsigned char C , unsigned & CurByte , raw_ostream & OS ) const { OS << (


<s> assert ( ( VT . is512BitVector ( ) || VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op . getNode ( ) ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems < <NUM_LIT> || ( NumElems == <NUM_LIT> && Subtarget . canExtendTo512DQ ( ) ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; return LowerVectorCTPOPInRegLUT ( Op0 , DL , Subtarget ,


<s> return ( uint8x16_t ) __builtin_neon_vtstv16qi ( ( int8x16_t )


<s> if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isNullValue ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { auto IsAnyExt64 = [ ] ( SDValue Op ) { if ( Op . getValueType ( ) != <STR_LIT> || ! Op . hasOneUse ( ) ) return SDValue ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) return Op . getOperand ( <NUM_LIT> ) ; if ( auto * Ld = dyn_cast < LoadSDNode > ( Op ) ) if ( Ld -> getExtensionType ( ) == <STR_LIT> && Ld -> getMemoryVT ( ) . getScalarSizeInBits ( ) <= <NUM_LIT> ) return Op ; return SDValue ( ) ; } ; if ( SDValue ExtSrc = IsAnyExt64 ( peekThroughOneUseBitcasts ( Src ) ) ) return DAG . getBitcast ( VT , DAG . getNode (

<STR_LIT> , DL , <STR_LIT> , DAG . getAnyExtOrTrunc ( ExtSrc , DL , <STR_LIT> ) ) ) ;


<s> break ; case Match_Success : { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; } case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc ,


<s> parseRegForInlineAsmConstraint ( StringRef C , MVT VT ) const { const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const TargetRegisterClass * RC ; StringRef Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . startswith ( <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix


<s> return regno >= <NUM_LIT> ? ( regno - <NUM_LIT> ) :


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return false ; Parser . Lex ( ) ; unsigned regKind


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target


<s> MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( Target ) ; if ( BRCT != <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState

:: ImplicitDefine | RegState :: Dead ) ;


, <NUM_LIT> , ( __mmask32 ) - <NUM_LIT> ) ;


<s> if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB ,


<s> const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( )


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , bool


<s> for ( MachineInstr & MI : MBB ) if ( MI . getOpcode ( ) == <STR_LIT> ) CFGs . push_back ( & MI ) ; for ( auto * MI : CFGs ) materializeTileCfg


<s> if ( SDValue Result = AddCombineToVPADDL ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse (


<s> } Optional < uint64_t > C ; Register TestReg ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : case TargetOpcode :: G_XOR : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! VRegAndVal ) { std :: swap ( ConstantReg , TestReg ) ; VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) C = VRegAndVal -> Value ; break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg


<s> bool isNeg = false ; if ( OneChunks > ZeroChunks ) { isNeg = true ; Imm = ~ Imm ; } unsigned FirstOpc ; if ( BitSize == <NUM_LIT> ) { Imm &= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } else { FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } unsigned Shift = <NUM_LIT> ; unsigned LastShift = <NUM_LIT> ; if ( Imm != <NUM_LIT> ) { unsigned LZ = countLeadingZeros ( Imm ) ; unsigned TZ = countTrailingZeros ( Imm ) ; Shift = ( TZ / <NUM_LIT> ) * <NUM_LIT> ; LastShift = ( ( <NUM_LIT> - LZ ) / <NUM_LIT> ) * <NUM_LIT> ; } unsigned Imm16 = ( Imm >> Shift ) & Mask ; Insn . push_back ( { FirstOpc , Imm16 , <STR_LIT> ( <STR_LIT> , Shift ) } ) ; if ( Shift == LastShift ) return ; if ( isNeg ) Imm = ~ Imm ; unsigned Opc = ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; while ( Shift < LastShift ) { Shift += <NUM_LIT> ; Imm16 = ( Imm >> Shift )


<s> emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode ,

condition_rtx , loc_ref , pc_rtx ) ) ) ;


<s> static SDValue LowerSVEIntrinsicEXT ( SDNode * N , SelectionDAG & DAG ) { SDLoc dl ( N ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; EVT ByteVT = EVT :: getVectorVT ( Ctx , <STR_LIT> , { VT . getSizeInBits ( ) / <NUM_LIT> , true } ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> static bool isFrameLoadOpcode ( int Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m128d ) __builtin_ia32_vfmsubpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , (


<s> static int ix86_avx_u128_mode_exit ( void ) { rtx reg = crtl -> return_rtx ; if ( reg && ix86_check_avx_upper_register ( reg ) ) return AVX_U128_DIRTY ; return


<s> rtx pat = gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , x , const0_rtx ) ) ; if ( mode == SImode || ( code == NE && TARGET_VIS3 ) ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( mode == SImode ? CCmode : CCXmode , SPARC_ICC_REG ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , pat , clobber ) ) ; } emit_insn ( pat ) ; return true ; } if ( TARGET_ARCH64 && mode == DImode && ! ( ( code == LTU || code == GTU ) && TARGET_VIS3 ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU || code


<s> CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op

. getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign


<s> void mips_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; compute_frame_size ( get_frame_size ( ) ) ; gcc_assert ( ( cfun -> machine -> frame . mask >> <NUM_LIT> ) & <NUM_LIT> ) ; slot_address = mips_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; emit_move_insn ( gen_rtx_MEM ( GET_MODE ( address ) , slot_address ) , address


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm (


<s> auto LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( Src ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; return LT . first *


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> ) ShiftTy = <STR_LIT> ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { SMLoc L = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; ShiftReg = tryParseRegister ( ) ; if ( ShiftReg == - <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return - <NUM_LIT> ; } } else { Error ( Parser . getTok ( ) .


<s> if ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT


<s> rtx a , b ; if ( GET_CODE ( addr ) != PLUS ) return COSTS_N_INSNS ( <NUM_LIT> ) ; a = XEXP ( addr , <NUM_LIT> ) ; b = XEXP ( addr , <NUM_LIT>


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> static DecodeStatus DecodeBranchTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> )


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } bool FallThru = FBB == nullptr ; unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; case <STR_LIT> : if ( FBB == nullptr ) { FBB = getFallThroughMBB ( & MBB , TBB ) ; assert ( FBB && <STR_LIT> <STR_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; default : { unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB (


<s> int Elt0 = MaskVals [ i * <NUM_LIT> ] ; int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( V1Only && ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; if ( V2Only && ( Elt0 == i * <NUM_LIT> + <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ; if ( ( Elt0 & <NUM_LIT> ) != <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt0 . getValueType ( ) ) ) ) ; else if ( Elt1 >= <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; InsElt = Elt1 >= <NUM_LIT> ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , InsElt0 ) : InsElt0 ; } NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG


<s> if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , Idx . getValueType ( ) , OffsetVal , StackPtr ) ; SDValue LoadScalar = DAG . getLoad ( Extract -> getValueType ( <NUM_LIT> ) , dl , Ch , ScalarAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Extract , <NUM_LIT> ) ,


<s> fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } else { regs_off = <NUM_LIT> + <NUM_LIT> ; fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } this_cfa = ( int ) context -> cfa ; new_cfa = * ( int * ) ( ( context -> cfa ) + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ) ) ; fpu_save = * ( int * ) ( ( this_cfa ) + ( fpu_save_off ) ) ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = <NUM_LIT> ; fs -> cfa_offset = new_cfa - ( int ) context -> cfa ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) continue ; fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = this_cfa + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( i * <NUM_LIT> ) ) - new_cfa ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { fs -> regs . reg [ i + <NUM_LIT> ] .


<s> bool <ISA_LIT>FastISel :: is<ISA_LIT>NEONPred ( const MachineInstr * MI ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> || AFI -> isThumb2Function ( ) ) return MI -> isPredicable ( ) ; for ( const MCOperandInfo & opInfo : MCID . operands ( ) ) if ( opInfo


<s> return ( uint32x4_t ) __builtin_neon_vmovluv4hi (


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry (


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getTargetExternalSymbol ( <STR_LIT> , IntPtr ) , DAG . getRegister ( <STR_LIT> , IntPtr ) , DAG . getRegister ( <ISA_LIT>StackPtr , SPTy ) , Flag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , Flag ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ; SDValue Ops1 [ <NUM_LIT> ] = { Chain . getValue ( <NUM_LIT>


<s> static DecodeStatus DecodeF4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; bool IsISRRegFI = <ISA_LIT>FI -> isISRRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI || IsISRRegFI ) FrameReg = ABI . GetStackPtr ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( MFI -> hasVarSizedObjects ( ) && ! MFI -> isFixedObjectIndex ( FrameIndex ) ) FrameReg = ABI . GetBasePtr ( ) ; else if ( MFI -> isFixedObjectIndex ( FrameIndex ) ) FrameReg = getFrameRegister ( MF ) ; else FrameReg = ABI . GetStackPtr ( ) ; } else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) , MI . getOperand ( OpNo - <NUM_LIT> ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI


<s> rtx base = convert_to_pmode ( args [ <NUM_LIT> ] ) ; if ( mode_suffix_id == MODE_vnum ) { poly_int64 size = ordered_min ( GET_MODE_SIZE ( mem_mode ) ,


<s> <STR_LIT> , tm . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) , TM ( tm ) , TII ( tii ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit ( ) ; IsWin64 = Subtarget -> isTargetWin64 ( ) ; StackAlign = TM . getFrameLowering ( ) ->


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; if ( ArgTy -> isFP128Ty ( )


<s> bool aarch64_sve_arith_immediate_p ( machine_mode mode , rtx x , bool negate_p ) { rtx elt = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt


<s> BasicBlock * BB = L -> getLoopLatch ( ) ; if ( BB -> getParent ( ) -> optForSize ( ) ) return ; unsigned Cost = <NUM_LIT> ; for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) )


<s> while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { MachineInstr * Cmp ; CmpInst :: Predicate Pred ; std :: tie ( Cmp , Pred ) = emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; if ( ! Cmp ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; } else { CmpInst :: Predicate Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case


<s> MachineBasicBlock * SuccBB = selectSuccBB ( MBB ) ; if ( ! SuccBB ) return false ; RegDefsUses RegDU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * MBB . getParent ( ) ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end (

) , RegDU , * IM , Filler , Slot ) ) return false ;


<s> return ! Revert && FoundAllComponents ( ) && VCTP && !

CannotTailPredicate && ML -> getNumBlocks ( ) == <NUM_LIT> ;


<s> bool isDirectBr ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> >

( getImm ( ) ) && ( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; }


<s> llvm :: MachineBasicBlock :: iterator cmpInst = NULL ; for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) { errs ( ) << <STR_LIT> ; I -> dump ( ) ; MBB -> dump ( ) ; errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> ; } if ( I -> getOpcode ( ) == <STR_LIT> && ! ( I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ) { errs ( ) << <STR_LIT> ; I -> dump ( ) ; I -> getOperand ( <NUM_LIT> ) . print ( errs ( ) ) ; errs ( )


<s> while ( Pos < Vec . size ( ) ) EmitByte ( <STR_LIT>


<s> __builtin_neon_vst2di ( ( __builtin_neon_di * ) __a ,


, ( unsigned char ) __imm , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( ( __a & __b ) != __AARCH64_UINT64_C ( <NUM_LIT>


<s> } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( *


<s> bool <ISA_LIT>FastISel :: SelectIntExt ( const Instruction * I ) { Type * DestTy = I -> getType ( ) ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; bool IsZExt = isa < ZExtInst > ( I ) ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; Register AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI


<s> if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } return false


<s> if ( is<ISA_LIT>64 ( ) || isFP64 ( ) ) FpFormat = FP_FORMAT_D ; else FpFormat


<s> return ( __m256i ) __builtin_ia32_cvttps2qq256_mask ( ( __v4sf ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , (


<s> unsigned <ISA_LIT>InstrInfo :: GetInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( )


<s> aarch64_layout_frame ( ) ; offset = frame_size = cfun -> machine -> frame . frame_size ; hard_fp_offset = cfun -> machine -> frame . hard_fp_offset ; fp_offset = frame_size - hard_fp_offset ; if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( offset >= <NUM_LIT> ) { offset = hard_fp_offset ; if ( offset >= <NUM_LIT> ) offset = cfun -> machine -> frame . saved_regs_size ; frame_size -= ( offset + crtl -> outgoing_args_size ) ; fp_offset = <NUM_LIT> ; if ( frame_size >= <NUM_LIT> ) { rtx op0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; emit_move_insn ( op0 , GEN_INT ( - frame_size ) ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , op0 ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - frame_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( frame_size > <NUM_LIT> ) { int hi_ofs = frame_size & <NUM_LIT> ; int lo_ofs = frame_size & <NUM_LIT> ; if ( hi_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - hi_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( lo_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - lo_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } else frame_size = - <NUM_LIT> ; if ( offset > <NUM_LIT> ) { bool skip_wb = false ; if ( frame_pointer_needed ) { skip_wb = true ; if ( fp_offset ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; aarch64_save_callee_saves ( DImode , fp_offset , R29_REGNUM , R30_REGNUM , false ) ; } else aarch64_pushwb_pair_reg ( DImode , R29_REGNUM , R30_REGNUM , offset ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_stack_tie ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( fp_offset || reg1 == FIRST_PSEUDO_REGISTER || ( reg2 == FIRST_PSEUDO_REGISTER && offset >= <NUM_LIT> ) ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT>


<s> EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } if ( RegNo == <NUM_LIT> && Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo =


<s> FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB .


<s> static unsigned int aarch64_min_divisions_for_recip_mul ( enum machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) == <NUM_LIT> ) return


<s> std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; MachineBasicBlock :: iterator UnCondBrIter = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = <STR_LIT> ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT>


< <ISA_LIT>32Max ) || has<ISA_LIT>64r6 ( ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetMachO ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> return __builtin_aarch64_lceilhfdi (


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> unsigned <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum +


<s> printInstruction ( MI , O ) ; printAnnotation ( O


<s> return any_of ( MRI . reg_instructions ( <STR_LIT> ) , [ ] ( const MachineInstr & RI ) { return


<s> static const uint16_t * lookupAVX512 ( unsigned opcode , unsigned domain ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : ReplaceableInstrsAVX512 ) if ( Row [ domain - <NUM_LIT> ] == opcode || ( domain == <NUM_LIT> && Row [


<s> return true ; } if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ! const_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { loongarch_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx (


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return getOnesVector ( VT , DAG , DL ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; } return SDValue ( )


<s> int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm

-> getValue ( ) / <NUM_LIT> ) : <NUM_LIT> ;


<s> EVT ArgVT = N . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = N ; Entry . Ty = ArgTy ; Entry . IsSExt = TLI . shouldSignExtendTypeInLibCall ( ArgVT , SignExtend ) ; Entry . IsZExt = ! Entry . IsSExt ; Args . push_back ( Entry ) ; } SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const Function & F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool isTailCall = TLI . isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) && ( RetTy == F . getReturnType ( ) || F . getReturnType ( ) -> isVoidTy ( ) ) ; if ( isTailCall ) InChain = TCChain ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( InChain ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) . setTailCall ( isTailCall ) . setSExtResult ( SignExtend ) . setZExtResult ( ! SignExtend ) . setIsPostTypeLegalization ( true ) ; return TLI . LowerCallTo (


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { Offset += RI -> getSlotSize ( ) ; } else { unsigned Align = MFI -> getObjectAlignment ( FI