<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMem ( std :: unique_ptr < <ISA_LIT>Operand > Base , const MCExpr * Off , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base .


<s> static SDValue LowerMSTORE ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MaskedStoreSDNode * N = cast < MaskedStoreSDNode > ( Op . getNode ( ) ) ; SDValue DataToStore = N -> getValue ( ) ; MVT VT = DataToStore . getSimpleValueType ( ) ; SDValue Mask = N -> getMask ( ) ; SDLoc dl (


<s> static SDValue combineADC ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue CarryOut = DAG . getConstant ( <NUM_LIT> , DL , N -> getValueType ( <NUM_LIT> ) ) ; SDValue Res1 = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DCI . CombineTo ( N , Res1 , CarryOut ) ; } if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) { MVT VT = N -> getSimpleValueType


<s> Register AddrReg = getRegForValue ( BI -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( AddrReg ) ; for ( auto * Succ : BI -> successors ( ) ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap


<s> __builtin_ia32_gatherpfqpd ( mask , ( __v8di ) index , ( long long const * ) addr , scale ,


<s> MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT>


<s> else ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST


<s> else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) ) { if ( isBitwiseInverse ( Op0Op0 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op0Op0 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op0 ; } } if ( ! IfClr . getNode ( ) ) return SDValue ( ) ; assert ( Cond . getNode ( ) && IfSet . getNode ( ) ) ; if ( IsConstantMask ) { if ( Mask . isAllOnesValue ( ) ) return IfSet ; else if ( Mask ==


<s> void setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) override { InstructionSelector :: setupMF ( MF , KB ,


<s> switch ( Val & <NUM_LIT> ) { case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case


<s> void <ISA_LIT>AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , *


<s> addPass ( createNEMESISPass ( ) ) ; addPass ( createZDCPass (


<s> MCStreamer * create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , MCCodeEmitter * CE , raw_ostream & OS , bool RelaxAll ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S


<s> if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( <NUM_LIT> , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; if ( MEM_P ( if_true ) && MEM_P ( if_false ) ) if_true = force_reg


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val


<s> for ( uint64_t Byte = <NUM_LIT> , End = PltContents . size ( ) ; Byte + <NUM_LIT> < End ; ) { if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] ==


<s> DOUT ( llvm :: dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << UserOffset << <STR_LIT> << CPEOffset << <STR_LIT> << int ( CPEOffset - UserOffset ) << <STR_LIT> << * MI ) ; } return OffsetIsInRange ( UserOffset , CPEOffset ,


<s> if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; return


<s> if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , <NUM_LIT> ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = <STR_LIT> ( & M , <STR_LIT> , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true


<s> ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue > ( COp ) ) { ShuffleMask . append ( Scale , SM_SentinelUndef ) ; continue ; } APInt MaskElt = cast < ConstantInt > ( COp ) -> getValue ( ) ; for ( int j = <NUM_LIT> ; j != Scale ; ++ j ) { APInt Index = MaskElt . getLoBits ( <NUM_LIT> ) ; APInt PermuteOp = MaskElt . lshr ( <NUM_LIT> ) . getLoBits ( <NUM_LIT> ) ; MaskElt = MaskElt . lshr ( <NUM_LIT> ) ; if ( PermuteOp == <NUM_LIT> ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } if ( PermuteOp != <NUM_LIT> ) { ShuffleMask . clear


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool bigEndian

) : <ISA_LIT>DisassemblerBase ( STI , Ctx , bigEndian ) {


<s> return addLeaOffset ( MIB , Offset )


<s> return ( uint8x8_t ) __builtin_neon_vcgtuv8qi ( ( int8x8_t ) __a , (


<s> return ( __m128d ) __builtin_ia32_xorpd ( ( __v2df ) __A , (


<s> getTargetStreamer ( ) . emit<ISA_LIT>WinCFINop (


<s> if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= <NUM_LIT> && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - <NUM_LIT> || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - <NUM_LIT> || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >=

<NUM_LIT> && CR_REGNO_P ( regno ) ) return NO_REGS ;


<s> switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , MI , BB ) ; break ; case <STR_LIT> : return emitFEXT_CCRX16_ins ( <STR_LIT> , MI ,


<s> static int current_file_function_operand ( rtx sym_ref ) { if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref ,


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op2 = expand_expr ( arg2 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2

== error_mark_node ) return const0_rtx ;


<s> DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } } if ( ! isInt < <NUM_LIT> > ( Disp )


<s> if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , C ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; for ( auto Ty : { p0 , s1 , s8 , s16 , s32 } ) setAction ( { G_IMPLICIT_DEF , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_PHI , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } ,


<s> if ( TARGET_VIS ) sparc_vis_init_builtins


<s> if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) , <STR_LIT> ) ; return


<s> reg = gen_reg_rtx ( CCmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_fmt_ee ( test_code == NE ? EQ : test_code , CCmode , cmp0 , cmp1 ) ) ) ; test_code = test_code == NE ? EQ : NE ; mode = CCmode ; cmp0 = reg ; cmp1 = const0_rtx ; invert = <NUM_LIT> ; break ; default : abort_with_insn ( gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , <STR_LIT> ) ; } label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , mode , cmp0 , cmp1 ) ,


<s> bool PBlock = false ; PBlock |= Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isYMMLoadOpcode ( LoadOpcode ) ) PBlock |= Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>


<s> SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) .


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal )


<s> unsigned getSORegImmOpValue ( const MachineInstr & MI


<s> EVT PtrVT = Src . getValueType ( ) ; return getBoundedStrlen ( DAG , DL , Chain , Src , DAG . getConstant ( <NUM_LIT> , DL


<s> bool IsLoad = ( Instruction :: Load == Opcode ) ; bool IsStore = ( Instruction :: Store == Opcode ) ; VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; unsigned NumElem = SrcVTy -> getNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int MaskSplitCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { VectorType * NewMaskTy = VectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy


<s> assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; case <STR_LIT> : { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; } uint64_t LoMask = BlendMask & <NUM_LIT> ; uint64_t HiMask = ( BlendMask >> <NUM_LIT> ) & <NUM_LIT> ; if ( LoMask == <NUM_LIT> || LoMask == <NUM_LIT> || HiMask == <NUM_LIT> || HiMask == <NUM_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( LoMask , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( HiMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( <STR_LIT> , DL , Lo , Hi , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 ,


<s> case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , OutContext ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_PLT , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , OutContext ) , OutContext ) ; return MCOperand :: CreateExpr (


<s> poly8x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o


<s> case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_DTPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_DTPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_SIZE : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_SIZE64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_SIZE32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_TLSGD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSGD ; case MCSymbolRefExpr :: VK_GOTTPOFF : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_GOTTPOFF ; case MCSymbolRefExpr :: VK_TLSLD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSLD ; case MCSymbolRefExpr :: VK_PLT : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_PLT32 ; case MCSymbolRefExpr :: VK_GOTPCREL : checkIs32 ( Ctx , Loc , Type ) ; return ELF


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNo<ISA_LIT>16 (


<s> const GlobalValue * GV = GA -> getGlobal ( ) ; SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ,


<s> return ( __m128i ) __builtin_ia32_cvtpd2dq (


<s> static SDValue insert128BitVector ( SDValue Result , SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , const SDLoc & dl ) { assert ( Vec . getValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; return insertSubVector ( Result , Vec , IdxVal , DAG , dl ,


<s> } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ( ! TT . isOSAIX ( ) || STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> ) { O << <STR_LIT> ; if ( L != <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; printAnnotation ( O , Annot ) ; return ; } } if ( ! printAliasInstr ( MI , Address , STI , O ) ) printInstruction ( MI , Address ,


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( Subtarget . getFrameLowering ( ) -> getReturnSaveOffset ( ) , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( )


<s> return __builtin_loongson_pcmpgtw_u ( s ,


<s> IntrinsicInst * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI ) return false ; switch ( IntrI -> getIntrinsicID ( ) ) { case <STR_LIT> : return optimizeConvertFromSVBool ( IntrI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return optimizePTest (


<s> const AsmToken & Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_Success ; Parser . Lex ( ) ; unsigned regKind = <STR_LIT> ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> getConstantSplatNode ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT>


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const BitMode32CalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( Subtarget . isSingleFloat ( ) )


<s> <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } unsigned tlsOpNo = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( op == <NUM_LIT>


<s> return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } unsigned addrmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2AddrModeSOReg ( Inst , addrmode


<s> EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned long long __Y ) { return __builtin_ia32_bzhi_di ( __X , __Y


<s> assert ( pParent . getSymGOTPLTMap ( ) . lookUp ( * rsym ) == NULL && <STR_LIT> ) ; <ISA_LIT>GOTEntry * gotplt_entry = ld_backend . getGOT ( ) . createGOTPLT ( ) ; pParent . getSymGOTPLTMap ( ) . record ( * rsym , * gotplt_entry ) ; Relocation & rel_entry = * ld_backend . getRelPLT ( ) . create ( ) ; rel_entry . setType ( llvm ::


<s> getMemEncodingMMImm12 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI .

getOperand ( OpNo + <NUM_LIT> ) , Fixups ) ;


<s> HOST_WIDE_INT ix86_initial_elimination_offset ( int from , int to ) { struct ix86_frame frame ; ix86_compute_frame_layout ( & frame ) ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM

) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ;


<s> static inline bool equal ( tree_map * a , tree_map * b ) { return a -> base . from == b


<s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm


<s> unsigned Kind = Fixup . getTargetKind ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Target . getAccessVariant ( ) ; if ( IsPCRel ) { switch ( Kind ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Kind ) ; Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_CKCORE_NONE ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_CKCORE_PCREL32 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM16_4 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM8_4 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM26_2 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM18_2 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM16_2 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM10_2 ; case <STR_LIT> : return ELF :: R_CKCORE_PCREL_IMM7_4 ; } } switch ( Kind ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Kind ) ; Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_CKCORE_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_CKCORE_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_CKCORE_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target ) { auto TK = cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) ; if ( TK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR ) return ELF :: R_CKCORE_ADDR32 ; if ( TK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT ) return ELF :: R_CKCORE_GOT32 ; if ( TK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF ) return ELF :: R_CKCORE_GOTOFF ; if ( TK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT ) return


<s> int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OddReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( EvenReg == OddReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate (


<s> void <ISA_LIT>AsmPrinter :: printSOImmOperand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( )


<s> uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; uint64_t Index = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isInt < <NUM_LIT> > ( Disp ) && isUInt <


<s> else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { unsigned Reg = lookUpRegForValue ( IntExtVal ) ; auto * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) { if ( RetVT == <STR_LIT> && VT <= <STR_LIT> ) { if ( WantZExt ) { std :: prev ( FuncInfo . InsertPt ) -> eraseFromParent ( ) ; ResultReg = std :: prev ( FuncInfo . InsertPt ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , ResultReg , true , <STR_LIT> ) ; } updateValueMap ( I , ResultReg ) ; return true ; } while ( MI ) { Reg = <NUM_LIT> ; for ( auto & Opnd : MI -> uses ( ) ) { if ( Opnd . isReg ( ) ) { Reg = Opnd . getReg ( ) ; break ; } } MI -> eraseFromParent ( ) ; MI =


<s> for ( unsigned i = <NUM_LIT> ; i < JT . size ( ) ; ++ i ) { const std :: vector < MachineBasicBlock * > & MBBs = JT [ i ] . MBBs ; for ( unsigned j = <NUM_LIT> ; j < MBBs . size ( ) ; ++


<s> ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , LHS . getValueType ( ) ) ; } } if ( LHS . getNode ( ) ) { bool Invert = false ; if ( LHS . getOpcode ( ) == <STR_LIT> && isAllOnes ( LHS . getOperand ( <NUM_LIT> ) ) ) { Invert = true ; LHS = LHS . getOperand ( <NUM_LIT> ) ; } if ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; if ( LHS . getValueType ( ) != RHS . getValueType ( ) ) RHS = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , RHS ) ; SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ,


<s> rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0


<s> if ( ! match ( GetTuple , m_Intrinsic < <STR_LIT> > ( m_Value ( SetTuple ) , m_Value ( SetIndex ) , m_Value ( SetValue ) ) ) || SetValue -> getType ( ) != II . getType ( ) ) return None ; if ( GetIndex == SetIndex ) return IC . replaceInstUsesWith


<s> bool sh_optimize_sett_clrt :: gate ( function *


<s> } const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; if ( CombineSPBump ) { assert ( ! SVEStackSize && <STR_LIT> ) ; emitFrameOffset ( MBB , MBB . getFirstTerminator ( ) , DL , <STR_LIT> , <STR_LIT> , { NumBytes + ( int64_t ) AfterCSRPopSize , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ; if ( NeedsWinCFI && HasWinCFI ) BuildMI ( MBB , MBB . getFirstTerminator ( ) , DL , TII -> get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; return ; } NumBytes -= PrologueSaveSize ; assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; StackOffset DeallocateBefore = { } , DeallocateAfter = SVEStackSize ; MachineBasicBlock :: iterator RestoreBegin = LastPopI , RestoreEnd = LastPopI ; if ( AFI -> getSVECalleeSavedStackSize ( ) ) { RestoreBegin = std :: prev ( RestoreEnd ) ; ; while ( IsSVECalleeSave ( RestoreBegin ) && RestoreBegin != MBB . begin ( ) ) -- RestoreBegin ; ++ RestoreBegin ; assert ( IsSVECalleeSave ( RestoreBegin ) && IsSVECalleeSave ( std :: prev ( RestoreEnd ) ) && <STR_LIT> ) ; int64_t OffsetToFirstCalleeSaveFromSP = MFI . getObjectOffset ( AFI -> getMaxSVECSFrameIndex ( ) ) ; StackOffset OffsetToCalleeSavesFromSP = StackOffset ( OffsetToFirstCalleeSaveFromSP , <STR_LIT> ) + SVEStackSize ; DeallocateBefore = OffsetToCalleeSavesFromSP ; DeallocateAfter = SVEStackSize - DeallocateBefore ; } if ( SVEStackSize ) { if ( AFI -> isStackRealigned ( ) ) { if ( AFI -> getSVECalleeSavedStackSize ( ) ) emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , - SVEStackSize , TII , MachineInstr :: FrameDestroy ) ; } else { if ( AFI -> getSVECalleeSavedStackSize ( ) ) { emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , { NumBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy ) ; NumBytes = <NUM_LIT> ; } emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , DeallocateBefore , TII , MachineInstr :: FrameDestroy ) ; emitFrameOffset ( MBB , RestoreEnd , DL , <STR_LIT> , <STR_LIT> , DeallocateAfter , TII , MachineInstr :: FrameDestroy ) ; } } if ( ! hasFP ( MF ) ) { bool RedZone = canUseRedZone ( MF ) ; if ( RedZone && AfterCSRPopSize == <NUM_LIT> ) return ; bool NoCalleeSaveRestore = PrologueSaveSize == <NUM_LIT> ; int64_t StackRestoreBytes = RedZone ? <NUM_LIT> : NumBytes ; if ( NoCalleeSaveRestore ) StackRestoreBytes += AfterCSRPopSize ; bool Done = NoCalleeSaveRestore || AfterCSRPopSize == <NUM_LIT> ; if ( Done ) adaptForLdStOpt ( MBB , MBB . getFirstTerminator ( ) , LastPopI ) ; emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , { StackRestoreBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ; if ( Done


<s> assert ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] && <STR_LIT> <STR_LIT> ) ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; DecodeStatus Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return checkDecodedInstruction ( MI , Size , Address , CS , Insn , Result ) ; } struct DecodeTable { const uint8_t * P ; bool DecodePred ; } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT> , Address , this ) ) return MCDisassembler :: Fail ; return Result ; } } Result = decodeInstruction ( DecoderTableCoProc32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return checkDecodedInstruction ( MI , Size , Address


<s> if ( ! Ty . isVector ( ) ) return false ; Optional < int64_t > ImmVal = getVectorSHLImm ( Ty , Src2Reg , MRI ) ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT ::


<s> if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != <NUM_LIT> ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != <NUM_LIT> ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != <NUM_LIT> ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != <NUM_LIT> ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ; if ( pbisa2 ) * pbisa2


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetFp ( Value ) ; StringRef ModuleValue ; OS << <STR_LIT> ; OS << ABIFlagsSection . getFpABIString ( Value )


<s> if ( ! MO . isReg ( ) || ! <STR_LIT> . contains ( MO . getReg ( ) ) ) continue ; unsigned RegNo = TRI -> getEncodingValue ( MO . getReg ( ) ) ; UsedRegMask &= ~ ( <NUM_LIT> << ( <NUM_LIT> - RegNo ) ) ; } } if ( UsedRegMask == <NUM_LIT> ) { RemoveVRSaveCode ( MI ) ; return ; } unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; }


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [


<s> static void mmix_setup_incoming_varargs ( CUMULATIVE_ARGS * args_so_farp , enum machine_mode mode , tree vartype

, int * pretend_sizep , int second_time ATTRIBUTE_UNUSED ) {


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! IMM12_OPERAND ( INTVAL ( x

) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerELFTLSDescCallSeq ( SDValue SymAddr , SDLoc DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( SymAddr ) ; Chain = DAG . getNode ( <STR_LIT> , DL ,


<s> SDValue Addr , VecIndex ; unsigned Alignment ; if ( ! getParamsForOneTrueMaskedElt ( MS , DAG , Addr , VecIndex , Alignment ) ) return SDValue ( ) ; SDLoc DL ( MS ) ; EVT VT = MS -> getValue ( ) . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , MS -> getValue (


<s> default : return false ; case TargetOpcode :: G_VAARG : return legalizeVaArg ( MI , MRI , MIRBuilder


<s> SeparatorString = <STR_LIT> ; DollarIsPC = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; Data64bitsDirective = is64Bit ? <STR_LIT> : nullptr ; AssemblerDialect = <NUM_LIT> ; SupportsDebugInformation = true


<s> void ia64_profile_hook ( int labelno ) { rtx label , ip ; if ( NO_PROFILE_COUNTERS ) label = const0_rtx ; else { char buf [ <NUM_LIT> ] ; const char * label_name ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; SYMBOL_REF_FLAGS ( label ) = SYMBOL_FLAG_LOCAL ; } ip = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_ip_value ( ip )


<s> bool <ISA_LIT>AsmParser :: expandUncondBranchMMPseudo ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { assert ( getInstDesc ( Inst . getOpcode ( ) ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MCOperand Offset = Inst . getOperand ( <NUM_LIT> ) ; if ( Offset . isExpr ( ) ) { Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) { if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( ! isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode (


<s> unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value


<s> return TARGET_IEEE_FP ? CCFPUmode : CCFPmode


<s> setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 } ) { setAction ( { G_ZEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_SEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_ANYEXT , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } )

setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ;


<s> gcc_assert ( _sc != NULL ) ; free ( _sc


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = ArgLocs . size ( ) * <NUM_LIT> ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; return


<s> clearFeatureBits ( Feature , FeatureString ) ; AssemblerOptions . front ( ) -> setFeatures ( getSTI (


<s> return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ]

& RELOAD_REG_PRE_INCDEC ) != <NUM_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , EFLAGS ) , DAG . getConstant (


<s> if ( ! Subtarget . isTargetGlibc ( ) ) TargetLowering ::


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } if ( Subtarget -> hasAVX ( ) ) { if ( ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) || ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) ) { SDValue ZeroVec = getZeroVector ( OpVT , Subtarget , DAG , dl ) ; SDValue OpLo = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; SDValue OpHi = getTargetShuffleNode ( <STR_LIT> , dl , OpVT ,


<s> assert ( SrcVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( <STR_LIT> ( Op . getNode ( ) ) && <STR_LIT> ) ; APInt Imm ( SrcVT . getVectorNumElements ( ) , <NUM_LIT> ) ; for ( unsigned Idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; Idx < e ; ++ Idx ) { SDValue In = Op .


<s> MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned SrcReg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg2 = ( Compare -> getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; MachineOperand Target ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( CCMask ) . addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MBBI -> clearRegisterKills ( SrcReg


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * SrcVTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I = nullptr ) { if ( CostKind != TTI :: TCK_RecipThroughput ) { if ( ( Opcode == Instruction :: Load && isLegalMaskedGather ( SrcVTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && isLegalMaskedScatter ( SrcVTy , Align ( Alignment ) ) ) ) return <NUM_LIT> ; return BaseT :: getGatherScatterOpCost ( Opcode , SrcVTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , Align ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ; return getGSVectorCost ( Opcode , SrcVTy , Ptr , Alignment ,


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis (


<s> SDValue MultRHS = Mult -> getOperand ( <NUM_LIT> ) ; unsigned LHSSB = CurDAG . ComputeNumSignBits ( MultLHS ) ; unsigned RHSSB = CurDAG . ComputeNumSignBits ( MultRHS ) ; if ( LHSSB < <NUM_LIT> || RHSSB < <NUM_LIT> ) return SDValue ( ) ; APInt HighMask = APInt :: getHighBitsSet ( Mult -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) , <NUM_LIT> ) ; bool IsUnsigned = CurDAG . MaskedValueIsZero ( Mult -> getOperand ( <NUM_LIT> ) , HighMask ) && CurDAG . MaskedValueIsZero ( Mult -> getOperand ( <NUM_LIT> ) , HighMask ) && CurDAG . MaskedValueIsZero ( AddOperand , HighMask ) ; SDLoc DL ( ROOTNode ) ; SDValue TopHalf ; SDValue BottomHalf ; BottomHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TopHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue ACCIn = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BottomHalf , TopHalf ) ; bool IsAdd = ROOTNode -> getOpcode ( ) ==


<s> bool mayNeedRelaxation ( const MCInst & Inst


<s> MF -> insert ( ++ MBB -> getIterator ( ) , ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( ContBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT>


<s> static void sparc_output_deferred_case_vectors ( ) { rtx t ; int align ; if ( sparc_addr_list == NULL_RTX && sparc_addr_diff_list == NULL_RTX ) return ; function_section ( current_function_decl ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; for ( t = sparc_addr_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_vec ( XEXP ( t


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo


<s> case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case


<s> switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = *


<s> if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX512 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . AllowOverlappingLoads = true ; } if ( ST -> is64Bit ( ) ) { Options . LoadSizes . push_back


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return


<s> static __inline qword si_lqr ( unsigned int imm ) { return ( ( qword ) ( vec_ld ( <NUM_LIT> , ( vector unsigned char *


<s> if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Stxr = <STR_LIT> ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi


<s> } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) != <STR_LIT> || StVal . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExtElt ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( ExtElt . getNode (


<s> unsigned MyPredReg = <NUM_LIT> ; if ( ! MI ) return false ; if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm

( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> bool has<ISA_LIT>32r2 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r2

|| <ISA_LIT>ArchVersion == <ISA_LIT>64r2 ; }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI -> getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned UsedReg ; int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) ; int EndOffset = - EHRegOffset - EHRegSize ; FuncInfo . EHRegNodeEndOffset = EndOffset ; if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if (


<s> void emitARM64WinCFITrapFrame ( ) override { OS << <STR_LIT>


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> &&

VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; <ISA_LIT>CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) , Call ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; <ISA_LIT>CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) , Call ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } const <ISA_LIT>FunctionInfo * AFI_Caller = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool isZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = EmitIntExt ( RVVT , SrcReg , DestVT , isZExt


<s> bool hasStoreVarArgs ( ) const { return


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const


<s> return __builtin_mve_vrshlq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a , __b ,


<s> if ( ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst , Rs , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst

, Rs , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) ) return MCDisassembler :: Fail ;


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ; int64_t Imm = Inst . getOperand ( LblOperand ) .


<s> uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; MVT ResTy ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; switch ( NumLanes ) { default : return SDValue ( ) ; case <NUM_LIT> : ResTy = FloatBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ResTy = <STR_LIT> ; break ; } SDLoc DL ( N ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getConstant ( IntrinsicOpcode , DL , <STR_LIT>

) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , DL , <STR_LIT> ) ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI


<s> case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ; case DFmode


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_64 ; case FK_Data_8 : return RT64_64 ; case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_None && ! IsPCRel ) return RT64_32S ; return RT64_32 ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_32 ; case FK_Data_4 : case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RT64_32 ; case FK_PCRel_2 : case FK_Data_2 : return RT64_16


<s> unsigned PredCond = <STR_LIT> ( Pred ) ; return ( PredCond == <STR_LIT> || PredCond == <STR_LIT>


<s> unsigned int bytes_so_far = * get_cumulative_args ( cum ) ; unsigned int size ; unsigned int rounded_size ; size = arg . promoted_size_in_bytes ( ) ; if ( size < <NUM_LIT> ) return NULL_RTX ; rounded_size = rx_round_up ( size , UNITS_PER_WORD ) ; if ( rounded_size + bytes_so_far


<s> mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CCmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f


<s> bool hasInterlockedAccess1 ( ) const { return HasInterlockedAccess1


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( create<ISA_LIT>IssueVZeroUpperPass ( ) )


<s> CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( & CmpInstr , SrcReg , SrcReg2 , MRI ) ; if ( SrcReg2 != <NUM_LIT> ) return false ; if ( ! MRI -> use_nodbg_empty ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( CmpValue == <NUM_LIT> && substituteCmpToZero ( CmpInstr ,


<s> MCSymbol * & Sym = HwasanMemaccessSymbols [ { Reg , AccessInfo } ] ; if ( ! Sym ) { if ( ! TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; std :: string SymName = <STR_LIT> + utostr ( Reg - <STR_LIT>


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> if ( STUses && ! isMask_32 ( STUses ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI . emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI . emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ; ++ I ) if ( FRegIdx . count ( I ) ) { assert ( ( <NUM_LIT> << getFPReg ( MI . getOperand ( I ) ) & STDefs ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned FPKills = ( ( <NUM_LIT> << NumFPRegs ) - <NUM_LIT> ) & ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( Op . isUse ( ) && Op . isKill ( ) ) FPKills |= <NUM_LIT> << FPReg ; } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( FRegIdx . count ( i ) ) Op . setReg ( getSTReg (


<s> if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg (


<s> mips_split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ; if ( base != stack_pointer_rtx ) return false ; reg = adjust > <NUM_LIT> ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! REG_P ( reg ) ) return false ; if ( offset == top_offset + nargs * UNITS_PER_WORD && REGNO ( reg ) == GP_ARG_FIRST + nargs ) nargs ++ ; else if ( offset == save_offset ) { while ( mips16e_save_restore_regs [ i ++ ] != REGNO ( reg ) ) if ( i == ARRAY_SIZE ( mips16e_save_restore_regs ) ) return false ; mask |= <NUM_LIT> << REGNO ( reg ) ; save_offset -= UNITS_PER_WORD ; } else return false ; } extra = <NUM_LIT> ; mips16e_mask_registers ( & mask , mips16e_s2_s8_regs , ARRAY_SIZE ( mips16e_s2_s8_regs ) , & extra ) ; mips16e_mask_registers ( & mask , mips16e_a0_a3_regs , ARRAY_SIZE ( mips16e_a0_a3_regs ) , & extra ) ; if ( extra != <NUM_LIT> ) return false ; if ( nargs > <NUM_LIT> && BITSET_P ( mask , GP_ARG_FIRST + nargs - <NUM_LIT>


<s> if ( Subtarget . hasSSE1 ( ) && ! isa < ConstantFPSDNode > ( V ) ) { V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; V = DAG . getBitcast ( <STR_LIT> , V ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } V = DAG . getBitcast ( <STR_LIT> , V ) ; } else { V = DAG . getAnyExtOrTrunc ( V , DL , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( Splat ) { if ( Splat . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; Splat = CreateMMXElement ( Splat ) ; if ( Subtarget . hasSSE1 ( ) ) { if ( NumElts == <NUM_LIT> ) Splat = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , Splat ) ; unsigned ShufMask = ( NumElts > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , DAG . getConstant ( ShufMask , DL , <STR_LIT> ) ) ; } Ops . append ( NumElts , Splat ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Ops . push_back ( CreateMMXElement ( N . getOperand ( i ) ) ) ; } while ( Ops . size ( ) > <NUM_LIT> ) { unsigned NumOps = Ops . size ( ) ; unsigned IntrinOp = ( NumOps == <NUM_LIT> ? <STR_LIT> : ( NumOps == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; SDValue Intrin = DAG . getConstant ( IntrinOp ,


<s> hi_clobber = XVECEXP ( pattern , <NUM_LIT> , XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ) ; XEXP ( hi_clobber , <NUM_LIT> ) = gen_rtx_REG ( SImode , HI_REGNO ) ; PATTERN ( insn ) = pattern ; INSN_CODE ( insn ) = -


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (


<s> if ( ! UseUnscaled ) needsLowering = ( ( Offset & <NUM_LIT> ) != Offset ) ; else needsLowering = ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) ; break ; } if ( needsLowering && Addr . getKind ( ) == Address :: FrameIndexBase ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( needsLowering ) { uint64_t UnscaledOffset = Addr . getOffset ( ) * ScaleFactor ; unsigned ResultReg = FastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . getReg ( ) , false , UnscaledOffset , <STR_LIT> ) ; if ( ResultReg == <NUM_LIT> ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffset (


<s> <ISA_LIT>StorePairSuppress ( ) : MachineFunctionPass


<s> bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index


<s> } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT>


<s> switch ( Layout ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> } if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data (


<s> ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( COp1 && COp1 -> getZExtValue ( ) == <NUM_LIT> ) return false ; if ( ( isNaturalMemoryOperand ( Op0 , ICmpType ) && Op0 . hasOneUse ( ) ) && ! ( isNaturalMemoryOperand ( Op1 , ICmpType ) && Op1 . hasOneUse ( ) ) ) { if ( ! COp1 ) return true ; if ( ICmpType != <STR_LIT> && isUInt < <NUM_LIT> > ( COp1 -> getZExtValue ( ) ) ) return false ; if ( ICmpType != <STR_LIT> && isInt < <NUM_LIT> > ( COp1 ->


<s> static llvm :: once_flag InitializeRegisterBankFlag ; static auto InitializeRegisterBankOnce = [ & ] ( ) { const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT>


<s> return DecodeCAS ( MI , insn , Address , Decoder , false ,


<s> return ( isReg ( ) || isImm ( <NUM_LIT> ,


<s> return __arm_vstrhq_p_s16 ( __addr ,


<s> OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( GVar , Mang , TM ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) O << <STR_LIT> << name << '\n' ; O << TAI -> getCOMMDirective ( ) << name << ',' << Size ; if ( TAI -> getCOMMDirectiveTakesAlignment ( ) ) O << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: PrivateLinkage : case GlobalValue :: LinkerPrivateLinkage : case GlobalValue :: InternalLinkage : if ( CVA && CVA -> isCString ( ) ) printSizeAndType = false ; break ; case GlobalValue :: GhostLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: DLLImportLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: DLLExportLinkage : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align , GVar ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) && printSizeAndType ) { O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << Size << '\n' ; } O << name << <STR_LIT> ; EmitGlobalConstant ( C


<s> MBBs [ j ] -> setAlignment ( <NUM_LIT> ) ; } } } bool last_bb_was_constant_pool = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isLandingPad ( ) ) { I -> setAlignment ( <NUM_LIT> ) ; } if ( I -> empty ( ) ) continue ; bool is_constant_pool = I -> begin ( ) -> getOpcode ( ) == <STR_LIT> ; if ( last_bb_was_constant_pool != is_constant_pool ) { I -> setAlignment


<s> else factor = <NUM_LIT> ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : return factor ; case ADDRESS_REG_REG : return factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC : return factor * loongarch_symbol_insns ( addr .


<s> SDValue <ISA_LIT>TargetLowering :: combineSRA ( SDNode * N , DAGCombinerInfo & DCI


<s> auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> AddComment ( <STR_LIT>


<s> EmitBundleLock ( false ) ; emitMask ( AddrReg , IndirectBranchMaskReg , STI ) ; MCELFStreamer :: EmitInstruction ( MI , STI ) ; EmitBundleUnlock (


<s> SDLoc dl ( V ) ; while ( NumElems > <NUM_LIT> ) { if ( EltNo < NumElems / <NUM_LIT> ) { V = getUnpackl ( DAG , dl , VT , V , V ) ; } else { V = getUnpackh ( DAG , dl , VT ,


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ <NUM_LIT> ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == <NUM_LIT> ) { unsigned Reg = ExtraCode [ <NUM_LIT> ] == 'w' ? <STR_LIT> : <STR_LIT> ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ <NUM_LIT> ] ) { case 'b' : RC = & <STR_LIT> ; break ; case 'h' : RC = & <STR_LIT> ; break ; case 's' : RC = & <STR_LIT> ; break ; case 'd' : RC = & <STR_LIT> ; break ; case 'q'


<s> static int index_term_p ( rtx prod , enum machine_mode mode , int strict ) { rtx xfoo0 , xfoo1 ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return BASE_REGISTER_P ( prod , strict ) ; if ( GET_CODE ( prod ) != MULT || GET_MODE_SIZE ( mode ) > <NUM_LIT> ) return <NUM_LIT> ; xfoo0 = XEXP ( prod , <NUM_LIT>


<s> assert ( Kind == Memory && <STR_LIT>


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target ,


<s> if ( SPDiff ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + FL -> getReturnSaveOffset ( ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( MF , NewRetAddr ) ) ; if ( Subtarget . isDarwinABI ( ) ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject (


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) AddMACCandidate (


<s> if ( ! HasAVX || VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; int HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; bool MatchA = false , MatchB = false ; for ( int Half = <NUM_LIT> ; Half < <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( int Half = <NUM_LIT> ; Half < <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , HalfSize , HalfSize , Half * HalfSize ) ) { MatchB = true


<s> static DecodeStatus DecodeFCCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> ,


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true


<s> } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return