<s> EVT LoadVT = N -> getValueType ( <NUM_LIT> ) ; if ( LoadVT == <STR_LIT> ) LoadVT = <STR_LIT> ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( LoadVT , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SDValue ResVal = BSLoad ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ResVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSLoad ) ; DCI . CombineTo ( N , ResVal ) ; DCI . CombineTo ( Load . getNode ( ) , ResVal , BSLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N ,


<s> SDValue Cond = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( Cond . getOpcode ( ) != <STR_LIT> )


<s> bool isPICStyleStubAny ( ) const { return PICStyle == PICStyles :: StubDynamicNoPIC || PICStyle == PICStyles ::


<s> case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) * total = vax_float_literal ( x ) ? <NUM_LIT> : <NUM_LIT> ; else * total = ( ( CONST_DOUBLE_HIGH ( x ) == <NUM_LIT> && ( unsigned HOST_WIDE_INT ) CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) || ( outer_code == PLUS && CONST_DOUBLE_HIGH ( x ) == - <NUM_LIT> && ( unsigned HOST_WIDE_INT ) - CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ; return true ; case POST_INC : * total = <NUM_LIT> ; return true ; case PRE_DEC : * total = <NUM_LIT> ; return true ; case MULT : switch ( mode ) { case DFmode : * total = <NUM_LIT> ; break ; case SFmode : * total = <NUM_LIT> ; break ; case DImode : * total = <NUM_LIT> ; break ; case SImode : case HImode : case QImode : * total = <NUM_LIT> ; break ; default : * total = MAX_COST ; return true ; } break ; case UDIV : if ( mode != SImode ) { * total = MAX_COST ; return true ; } * total = <NUM_LIT> ; break ; case DIV : if ( mode == DImode ) * total = <NUM_LIT> ; else if ( mode == DFmode ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; break ; case MOD : * total = <NUM_LIT> ; break ; case UMOD : if ( mode != SImode ) { * total = MAX_COST ; return true ; } * total = <NUM_LIT> ; break ; case FLOAT : * total = ( <NUM_LIT> + ( mode == DFmode ) + ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) != SImode ) ) ; break ; case FIX : * total = <NUM_LIT> ; break ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : if ( mode == DImode ) * total = <NUM_LIT> ; else * total =


<s> tree arm_builtin_decl ( unsigned code , bool


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ; if ( ForceStackAlign ) return


<s> inline vector signed int vec_vmaxsw ( vector signed int


<s> if ( IsValidLdStrOpc ) * IsValidLdStrOpc = true ; switch ( Opc ) { default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> else if ( TARGET_DIRECT_MOVE_128 && size == <NUM_LIT> && ( ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) || ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE )

|| ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;


<s> if ( Stages > StageBias ) { unsigned DpElems = DpVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - StageBias ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( DpElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( DpVT , DL , DP , DAG . getUNDEF ( DpVT ) , Mask ) ; DP = DAG . getNode ( <STR_LIT> , DL , DpVT , DP , Shuffle ) ; } } EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtractVT , DpVT . getSizeInBits ( ) / ExtractVT . getSizeInBits ( ) ) ; DP = DAG . getBitcast ( ResVT


<s> SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) || TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType


<s> void * <ISA_LIT>JITInfo :: emitGlobalValueIndirectSym ( const GlobalValue * GV , void * Ptr , JITCodeEmitter & JCE ) { uint8_t Buffer [ <NUM_LIT> ] ; uint8_t * Cur = Buffer ; MachineCodeEmitter :: emitWordLEInto ( Cur , ( intptr_t ) Ptr ) ; void * PtrAddr = JCE . allocIndirectGV ( GV , Buffer , sizeof ( Buffer )


<s> EVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl


<s> } MachineSDNode * CmpSwap = DAG . getMachineNode ( Opcode , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; CmpSwap -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; unsigned SubReg1 = <STR_LIT> , SubReg2 = <STR_LIT> ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( SubReg1 , SubReg2 ) ; Results . push_back ( DAG . getTargetExtractSubreg ( SubReg1 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( SubReg2 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; return ; } auto Desired = splitInt128 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; auto New = splitInt128 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Desired . first , Desired . second , New . first , New . second , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap


<s> break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr ::


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterAsmInfo < <ISA_LIT>TargetAsmInfo >


<s> while ( first < last ) if ( global_regs


<s> case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false )


<s> if ( crtl -> profile ) emit_move_insn ( pic_offset_table_rtx , reg ) ; add_reg_note ( insn , REG_CFA_FLUSH_QUEUE , NULL_RTX ) ; } seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge )


<s> ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; if ( isMatchingUpdateInsn ( I , MI , BaseReg , UnscaledOffset ) ) return MBBI ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] || UsedRegs [ BaseReg ] ) return E ; } return E


<s> TargetRegistry :: RegisterDCTranslator ( getThe<ISA_LIT>leTarget ( ) ,


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Opt = <STR_LIT>


<s> unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; return CalleeCC == CallingConv :: Fast && CallerCC ==


<s> for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag )


<s> for ( s = cpu_string ; * s != <NUM_LIT> ; s ++ ) if ( ISUPPER ( * s ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; break ; } if ( strcasecmp ( cpu_string , <STR_LIT> ) == <NUM_LIT> ) return mips_cpu_info_from_isa ( ABI_NEEDS_32BIT_REGS ? <NUM_LIT> : ABI_NEEDS_64BIT_REGS ? <NUM_LIT> : ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( strcasecmp ( cpu_string , <STR_LIT> ) == <NUM_LIT> ) return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , N -> getOperand (

<NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , MaskConst ) ;


<NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ;


<s> return isThumb ( STI ) && ( STI . getFeatureBits ( ) &


<s> Value * <ISA_LIT>IREmitter :: visitVEXT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> MandarinTargetMachine :: MandarinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { initAsmInfo (


<s> unsigned long mask = <NUM_LIT> ; bitmap prologue_live_out = df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; for ( int reg = FIRST_LO_REGNUM ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( ! callee_saved_reg_p ( reg ) && ! REGNO_REG_SET_P ( prologue_live_out , reg ) ) mask |= <NUM_LIT> << ( reg - FIRST_LO_REGNUM ) ; return mask


<s> Register getStackRegister ( ) const { return StackPtr


<s> static rtx gen_movdi_x ( rtx dest , rtx src , rtx offset


<s> void printf128mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI


<s> Parser . Lex ( ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Size ) ; if ( ! ParseRegister ( SegReg , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Size ) ; } const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getParser ( ) . getContext ( ) ) ; if ( getParser ( ) . parseExpression ( Disp , End ) ) return <NUM_LIT> ; bool NeedSizeDir = false ; bool IsVarDecl = false ; if ( isParsingInlineAsm ( ) ) { if ( const MCSymbolRefExpr * SymRef = dyn_cast < MCSymbolRefExpr > ( Disp ) ) { const MCSymbol & Sym = SymRef -> getSymbol ( ) ; unsigned tLength , tSize , tType ; SemaCallback -> LookupInlineAsmIdentifier ( Sym . getName ( ) , NULL , tLength , tSize , tType , IsVarDecl ) ; if ( ! Size ) Size = tType * <NUM_LIT> ; NeedSizeDir = Size > <NUM_LIT> ; } } if ( ! isParsingInlineAsm ( ) ) return <STR_LIT> ( Disp , Start , End , Size ) ; else { if ( !


<s> return BBInfo . HasReturn ; } unsigned int CyclesToEnd = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MBBI != MBB -> end ( ) ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isReturn ( ) && ! MI -> isCall ( ) ) { VisitedBBs [ MBB ] = VisitedBBInfo ( true , CyclesToEnd ) ; Cycles +=


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg


<s> vec_uchar16 hihi_promote = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 biteq ; vec_uint4 aabs ; vec_uint4 babs ; vec_uint4 a_gt ; vec_uint4 ahi_inf ; vec_uint4 anan ; vec_uint4 iszero ; vec_uint4 result ; union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) a , ( vec_uint4 ) b ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_gt , x . v ) , ahi_inf ) ) ; iszero = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) vec_or ( aabs , babs ) , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; result = vec_or ( biteq , iszero ) ; result = vec_andc ( result


<s> static DecodeStatus DecodeZPR3RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister (


<s> MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_ABIFLAGS , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) , <NUM_LIT> , <STR_LIT> ) ; MCSectionData & ABIShndxSD = MCA . getOrCreateSectionData ( * Sec ) ; ABIShndxSD . setAlignment ( <NUM_LIT> ) ; OS . SwitchSection ( Sec ) ; OS <<


<s> static SDValue PerformVZEXT_MOVLCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op =


<s> return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) + ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> )


<s> inline static bool isGlobalRelativeToPICBase ( unsigned char TargetFlag ) { switch ( TargetFlag ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger ( )


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; const GlobalValue * GV = MO


<s> if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; } else { assert ( DispSpec . isExpr ( ) &&


<s> bool isU8Imm ( ) const { return isImm ( <NUM_LIT>


<s> SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; EVT MaskVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MaskContainerVT = getContainerForFixedLengthVector ( DAG , MaskVT ) ; auto Mask = convertToScalableVector ( DAG , MaskContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , MaskContainerVT . changeVectorElementType ( <STR_LIT> ) , Mask ) ; auto ScalableRes = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Mask , Op1 , Op2 ) ; return convertFromScalableVector ( DAG , VT


<s> if ( TARGET_ARM ) { if ( TARGET_HARD_FLOAT_ABI ) { if ( TARGET_FPA ) size += <NUM_LIT> ; if ( TARGET_MAVERICK ) size += <NUM_LIT> ; } if ( TARGET_IWMMXT_ABI ) size += <NUM_LIT> ; } return size


<s> for ( unsigned i = <NUM_LIT> ; i < P -> getNumOperands ( ) ; ++ i ) Q -> addIncoming ( Zero , P -> getIncomingBlock ( i ) ) ; return Q ; } auto * A = dyn_cast < Argument > ( V ) ; auto * I = dyn_cast < Instruction > ( V ) ; assert ( ( A || I ) && <STR_LIT> ) ; auto InstPt = A ? & * A -> getParent ( ) -> getEntryBlock ( ) . begin ( ) : I -> getNextNode ( ) ; return new ZExtInst ( V , IntTy , <STR_LIT> ,


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const MCPhysReg VR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumGPRs = array_lengthof ( GPR ) ; const unsigned NumFPRs = <NUM_LIT> ; const unsigned NumVRs = array_lengthof ( VR ) ; const unsigned ParamAreaSize = NumGPRs * PtrByteSize ; unsigned NumBytes = LinkageSize ; unsigned AvailableFPRs = NumFPRs ; unsigned AvailableVRs = NumVRs ; for ( const <STR_LIT> & Param : Outs ) { if ( Param . Flags . isNest ( ) )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> if ( ! I -> pred_empty ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printMachineInstruction ( II


<s> void addImm ( int64_t imm ) { Imm +=


<s> static inline bool isThumbImm16ShiftedVal ( unsigned


<s> } else if ( const auto * MS = dyn_cast < MemSetInst > ( I ) ) { ConstantInt * C = dyn_cast < ConstantInt > ( MS -> getLength ( ) ) ; if ( ! C ) return - <NUM_LIT> ; const unsigned Size = C -> getValue ( ) . getZExtValue ( ) ; const Align DstAlign = * MS -> getDestAlign ( ) ; MOp = MemOp :: Set ( Size , false , DstAlign , false , false ) ; DstAddrSpace = MS -> getDestAddressSpace ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned Limit , Factor = <NUM_LIT> ; switch ( I -> getIntrinsicID ( ) ) { case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemcpy ( F -> hasMinSize ( ) ) ; break ; case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemmove ( F -> hasMinSize ( ) ) ; break ; case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemset ( F -> hasMinSize (


<s> HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG =


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ; if ( Narrow ) NV = NarrowVector ( NV , * CurDAG ) ; ReplaceUses ( SDValue ( N , i ) , NV ) ; } ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; return Ld


<s> int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( V1Only && ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; if ( V2Only && ( Elt0 == i * <NUM_LIT> + <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ; if ( ( Elt0 & <NUM_LIT> ) != <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( ) ) ) ; else if ( Elt1 >= <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; InsElt = Elt1 >= <NUM_LIT> ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , InsElt0 ) : InsElt0 ; } NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = <NUM_LIT> ; break ; case MCK_1 : ImmVal = <NUM_LIT> ; break ; default : return Match_InvalidOperand


<s> Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc


<s> CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; if ( CallerCC == CallingConv :: C && <ISA_LIT>RegisterInfo :: hasSVEArgsOrReturn ( & MF ) ) CallerCC = CallingConv :: <ISA_LIT>_SVE_VectorCall ; bool CCMatch = CallerCC == CalleeCC ; if ( CallerCC == CallingConv :: Win64 && ! Subtarget -> isTargetWindows ( ) && CalleeCC != CallingConv :: Win64 ) return false ; for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) { if ( i -> hasByValAttr ( ) ) return false ; if ( i -> hasInRegAttr ( ) ) return false ; } if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) )


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> static unsigned HOST_WIDE_INT loongarch_asan_shadow_offset (


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> ,


<s> m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> ) ; create_address_operand ( & m_ops . last


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast


<s> std :: vector < llvm :: Value * > AsmArgs ; llvm :: FunctionType * AsmFTy = llvm :: FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes , false ) ; llvm :: InlineAsm * IA = llvm :: InlineAsm :: get ( AsmFTy , AsmString , <STR_LIT> , true , false , llvm :: InlineAsm :: AD_ATT ) ; CallInst :: Create ( IA , AsmArgs


<s> return MachineFunctionProperties ( ) . set (

MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> LowerGlobalTLSAddress ( SDValue Op ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID .


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState ::


<s> bool isMemoryIndexed64SImm7 ( ) const { if ( ! isMem ( ) || Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; assert ( CE && <STR_LIT> ) ; int64_t Value = CE -> getValue ( ) ; return ( ( Value % <NUM_LIT> ) == <NUM_LIT> ) &&

Value >= - <NUM_LIT> && Value <= <NUM_LIT> ;


<s> bool Fast ; const Function & F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= <NUM_LIT> && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; return <STR_LIT>


<s> return parseAddress ( Operands , BDRMem , <STR_LIT>


<s> bool SelectAddrImm ( SDValue N , SDValue &


<s> const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; for ( auto Ty : { s8 , s16 , s32 } ) setAction

( { TargetOpcode :: G_ADD , Ty } , Legal ) ;


<s> assert ( ChunkIdx < <NUM_LIT> && <STR_LIT> ) ; return ( Imm >> ( ChunkIdx * <NUM_LIT> ) ) &


<s> mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += FP_INC ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , off ) ; mem = gen_rtx_MEM ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; emit_move_insn ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>beTarget


<s> builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f ,


<s> return ( poly16x8_t ) __builtin_neon_vcombinev4hi ( ( int16x4_t )


<s> } else { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } } fprintf ( file , <STR_LIT> ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; final_end_function (


<s> virtual const TargetFrameLowering * getFrameLowering


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( getVPTInstrPredicate ( MI ) != <STR_LIT> ) return nullptr ; } return <ISA_LIT>BaseInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode6Offset ( SDNode * Op , SDValue N


<s> MCInst Inst ; Inst . setOpcode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( get<ISA_LIT>SubSuperRegister ( Reg , VT ) ) ) ; Op . addMemOperands ( Inst


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned


<s> assert ( MI -> isCopy ( ) && <STR_LIT> ) ; if ( ! ( NewRC -> hasSuperClassEq ( & <STR_LIT> ) && ( getRegSizeInBits ( * SrcRC ) <= <NUM_LIT> || getRegSizeInBits ( * DstRC ) <= <NUM_LIT> ) ) ) return true ; unsigned WideOpNo = ( getRegSizeInBits ( * SrcRC ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned GR128Reg = MI -> getOperand ( WideOpNo ) . getReg ( ) ; unsigned GRNarReg = MI -> getOperand ( ( WideOpNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; LiveInterval & IntGR128 = LIS . getInterval ( GR128Reg ) ; LiveInterval & IntGRNar = LIS . getInterval ( GRNarReg ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * FirstMI_GR128 = LIS . getInstructionFromIndex ( IntGR128 . beginIndex ( ) ) ; MachineInstr * FirstMI_GRNar = LIS . getInstructionFromIndex ( IntGRNar . beginIndex ( ) ) ; MachineInstr * LastMI_GR128 = LIS . getInstructionFromIndex ( IntGR128 . endIndex ( ) ) ; MachineInstr * LastMI_GRNar = LIS . getInstructionFromIndex ( IntGRNar . endIndex ( ) ) ; if ( ( ! FirstMI_GR128 || FirstMI_GR128 -> getParent ( ) != MBB ) || ( ! FirstMI_GRNar || FirstMI_GRNar -> getParent ( ) != MBB ) || ( ! LastMI_GR128 || LastMI_GR128 -> getParent ( ) != MBB ) || ( ! LastMI_GRNar || LastMI_GRNar -> getParent ( ) != MBB ) ) return false ; MachineBasicBlock :: iterator MII = nullptr , MEE = nullptr ; if ( WideOpNo == <NUM_LIT> ) { MII = FirstMI_GR128 ; MEE = LastMI_GRNar ; } else { MII = FirstMI_GRNar ; MEE = LastMI_GR128 ; } BitVector PhysClobbered ( getNumRegs ( )


<s> delta = bits / BITS_PER_UNIT ; regs = alloca ( sizeof ( rtx ) * length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; if ( ! mips_expand_unaligned_load ( regs [ i ] , part , bits , <NUM_LIT> ) ) gcc_unreachable ( ) ; } } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) emit_move_insn ( adjust_address ( dest , mode


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) MF . getRegInfo ( ) . addLiveOut


<s> if ( ! ConstOp1 ) return ; uint64_t CmpVal = ConstOp1 -> getZExtValue ( ) ; Comparison NewC ( C ) ; uint64_t MaskVal ; ConstantSDNode * Mask = <NUM_LIT> ; if ( C . Op0 . getOpcode ( ) == <STR_LIT> ) { NewC . Op0 = C . Op0 . getOperand ( <NUM_LIT> ) ; NewC . Op1 = C . Op0 . getOperand ( <NUM_LIT> ) ; Mask = dyn_cast < ConstantSDNode > ( NewC . Op1 ) ; if ( ! Mask ) return ; MaskVal = Mask -> getZExtValue ( ) ; } else { if ( NewC . Op0 . getValueType ( ) != <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . ICmpType == <STR_LIT> ) return ; if ( NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> ) { if ( CmpVal == uint64_t ( - <NUM_LIT> ) ) return ; CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; } else { NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal , CmpVal , NewC . ICmpType ) ; if ( ! NewCCMask ) return ; } C . Opcode


<s> rtx tocrel_expr = SET_SRC ( PATTERN ( tocrel_insn ) ) ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) gcc_unreachable ( ) ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; rtx const_vector = get_pool_constant ( base ) ; if ( SYMBOL_REF_P ( const_vector ) ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; unsigned int new_mask [ <NUM_LIT> ] , i , val ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { val = INTVAL ( XVECEXP ( const_vector , <NUM_LIT> , i ) ) ; if ( val < <NUM_LIT> ) new_mask [ i ] = ( val + <NUM_LIT> ) % <NUM_LIT> ; else new_mask [ i ] = ( ( val + <NUM_LIT> ) % <NUM_LIT> ) + <NUM_LIT> ; } rtx vals = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( vals , <NUM_LIT> , i ) = GEN_INT ( new_mask [ i ] ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( vals , <NUM_LIT> ) ) ; rtx new_mem = force_const_mem ( V16QImode , new_const_vector ) ; if ( ! REG_P ( XEXP ( new_mem , <NUM_LIT> ) ) ) { rtx base_reg = force_reg ( Pmode , XEXP ( new_mem , <NUM_LIT> ) ) ; XEXP ( new_mem , <NUM_LIT> ) = base_reg ; rtx_insn * force_insn = get_last_insn (


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdidi


<s> return __builtin_ia32_vcvttph2uqq256_mask ( __A , _mm256_setzero_si256 ( ) , ( __mmask8


<s> if ( ! isShiftedMask_64 ( Mask ) ) return - <NUM_LIT> ; uint64_t LSB = CountTrailingZeros_64 ( Mask ) ; int64_t ShiftRightRequired = LSB ; if ( MaskedVal . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( MaskedVal . getOperand ( <NUM_LIT> ) ) ) { ShiftRightRequired -= MaskedVal . getConstantOperandVal ( <NUM_LIT> ) ; MaskedVal = MaskedVal . getOperand ( <NUM_LIT> ) ; } else if ( MaskedVal . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( MaskedVal . getOperand ( <NUM_LIT> ) ) ) { ShiftRightRequired += MaskedVal . getConstantOperandVal ( <NUM_LIT> ) ; MaskedVal = MaskedVal . getOperand ( <NUM_LIT> ) ; } if ( ShiftRightRequired > <NUM_LIT> ) MaskedVal = DAG . getNode ( <STR_LIT> , DL , VT , MaskedVal , DAG . getConstant ( ShiftRightRequired , <STR_LIT> ) ) ; else if ( ShiftRightRequired < <NUM_LIT> ) { MaskedVal = DAG . getNode ( <STR_LIT> , DL , VT , MaskedVal , DAG . getConstant

( - ShiftRightRequired , <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS ,


<s> void MVEGatherScatterLowering :: pushOutMul ( PHINode * & Phi , Value * IncrementPerRound , Value * OffsSecondOperand , unsigned LoopIncrement , IRBuilder < > & Builder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( Instruction :: Mul , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * Product = BinaryOperator :: Create ( Instruction :: Mul , IncrementPerRound , OffsSecondOperand ,


<s> return ( __m128i ) __builtin_ia32_gatherdiv2di ( ( __v2di ) src , base , ( __v2di


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_NoMatch ) return false ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Tilde : case AsmToken :: String : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; return ResTy != MatchOperand_Success ; } case AsmToken :: Percent : { const MCExpr * IdVal


<s> Value * <ISA_LIT>TargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilderBase & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { assert ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && <STR_LIT> ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = Incr -> getType ( ) ; assert ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) ; Function * RMW = <STR_LIT> ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * IncrLo = Builder . CreateTrunc ( Incr ,


<s> if ( GET_MODE ( x ) == XFmode && ( optimize_size || x86_ext_80387_constants & TUNEMASK ) ) { REAL_VALUE_TYPE r ; int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( real_identical ( & r , & ext_80387_constants_table [ i ] )


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { int ISD = TLI -> InstructionOpcodeToISD


<s> bool <ISA_LIT>DAGToDAGISel :: tryScatter ( StoreSDNode * Store , unsigned Opcode ) { SDValue Value = Store -> getValue ( ) ; if ( Value . getOpcode ( ) != <STR_LIT> ) return false ; if ( Store -> getMemoryVT ( ) . getSizeInBits ( ) != Value . getValueSizeInBits ( ) ) return false ; SDValue ElemV = Value . getOperand ( <NUM_LIT> ) ; auto * ElemN = dyn_cast < ConstantSDNode > ( ElemV ) ; if ( ! ElemN ) return false ; SDValue Vec = Value . getOperand ( <NUM_LIT> ) ; EVT VT = Vec .


<s> NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end (


<s> unsigned <ISA_LIT>ELFObjectWriter :: getEFlags ( ) const { unsigned Flag = ELF :: EF_MIPS_NOREORDER ; if ( is64Bit ( ) ) Flag |= ELF :: EF_MIPS_ARCH_64R2 ; else Flag |= ELF :: EF_MIPS_ARCH_32R2 ; return Flag


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; SDLoc dl ( InputVector ) ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InputVector ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t Offset = EltSize * i ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , TLI . getPointerTy ( ) , StackPtr , OffsetVal ) ; Vals [ i ] = DAG . getLoad ( ElementType , dl , Ch , ScalarAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } } for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; uint64_t IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Extract , <NUM_LIT> ) , Vals [ IdxVal ] ) ; } return SDValue (


<s> <ISA_LIT>ExprKind getKind ( ) const { return


<s> * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) , <STR_LIT> ( subleaf ) ) ; return


<s> assert ( Kind == k_Immediate && <STR_LIT> ) ; return Imm . Val


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue (


<s> SDValue getAddrNonPIC ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG ) const { SDValue Hi = getTargetNode ( N , Ty , DAG ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadDRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU


<s> } } break ; case <STR_LIT> : NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; WasCandidate = true ; break ; case <STR_LIT> : case <STR_LIT> : NewMI = tryReplaceCopy ( MI ) ; WasCandidate = true ; break ; default : break ; } if ( NewMI ) NewMI -> sgx_type = MI -> sgx_type ; return


<s> Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset = <NUM_LIT> ; } } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; } if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result

, DAG . getConstant ( Offset , DL , PtrVT ) ) ;


<s> isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB =


<s> InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const <ISA_LIT>TargetMachine & > (


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , Get<ISA_LIT>GVSymbol ( MO . getGlobal ( ) , MO . getTargetFlags ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : if ( Subtarget -> genExecuteOnly ( ) ) llvm_unreachable


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT>


<s> newname = alloca ( strlen ( DLL_EXPORT_PREFIX ) + strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , DLL_EXPORT_PREFIX , oldname ) ; idp = get_identifier ( newname ) ; symref = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; SYMBOL_REF_DECL ( symref ) = decl ; XEXP ( DECL_RTL ( decl )


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * BO = dyn_cast < BinaryOperator > ( & I ) ; if ( ! BO ) continue ; if ( ! isVectorReductionOp ( * BO ) ) continue ; if ( BO -> getOpcode ( ) == Instruction :: Add ) { if ( tryMAddPattern ( BO ) ) { MadeChange = true ; continue ; } if ( trySADPattern ( BO ) ) { MadeChange = true


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo


<s> return new <ISA_LIT>AsmBackend ( T , TT . getOS ( ) ,


<s>
if
(
(
mask
&
RELOAD_REG_QUAD_OFFSET
)
!=
<NUM_LIT>
)
*
p
++
=
'O'
;
else
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
<NUM_LIT>
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
<NUM_LIT>
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
<NUM_LIT>


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectLoad ( const Instruction * I ) { if ( <ISA_LIT>LoadAlloca ( I ) ) return true ; EVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Reg


<s> RegisterTarget < Triple :: toy , false > X ( getThe<ISA_LIT>Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; int Idx = getUnderlyingExtractedFromVec ( ExtractedFromVec , ExtIdx ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( ! VecIn1 . getNode ( ) ) return SDValue ( ) ; VecIn2 = VecIn2 . getNode ( ) ? VecIn2 : DAG . getUNDEF ( VT ) ; SDValue NV = DAG . getVectorShuffle ( VT , DL , VecIn1 , VecIn2 , & Mask [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> , e = InsertIndices . size ( ) ; i != e ; ++ i ) { unsigned Idx = InsertIndices [ i ] ; NV = DAG . getNode ( <STR_LIT> , DL , VT , NV , Op . getOperand ( Idx )

, DAG . getIntPtrConstant ( Idx , DL ) ) ;


<s> bool Modified = false ; for ( SmallVectorImpl < unsigned > :: iterator I = Defs . begin ( ) , E = Defs . end ( ) ; I != E ; ++ I ) { SmallVector < MachineInstr * , <NUM_LIT> > DefSrcs ; if ( ! TRI -> isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified =


<s> HOST_WIDE_INT offset ; unsigned int regno , i , num_x_saved = <NUM_LIT> , num_f_saved = <NUM_LIT> ; frame = & cfun -> machine -> frame ; memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( loongarch_save_reg_p ( regno ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( loongarch_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; offset = LARCH_STACK_ALIGN ( crtl


<s> unsigned Count = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; unsigned Space = ( PrevReg < Reg ) ? ( Reg - PrevReg ) : ( Reg + <NUM_LIT> - PrevReg ) ; if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { return Error ( Loc , <STR_LIT> ) ; } Count += Space ; } else { while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc ,


<s> if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; Scale = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs =


<s> if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target ) ) { if ( reg_mentioned_p ( target , mem ) ) return false ; if ( ! peep2_reg_dead_p ( <NUM_LIT> , addis_reg ) ) return false ; if ( REG_P ( target ) && REGNO ( target ) == STACK_POINTER_REGNUM ) return false ; } base_reg = XEXP ( addr , <NUM_LIT> ) ; return REGNO ( addis_reg ) == REGNO (


<s> data -> ifetch_block_n_insns = <NUM_LIT> ; data -> ready_try_change = NULL ; data -> ready_try_change_size =


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) if ( Mask [ i ] % <NUM_LIT> != <NUM_LIT> || Mask [ i ] + <NUM_LIT> != Mask [ i + <NUM_LIT> ] ) return false ; return


<s> MachineBasicBlock :: const_instr_iterator II = ++ MI . getIterator ( ) ; assert ( II -> isInsideBundle ( ) && <STR_LIT> ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; int Idx = - <NUM_LIT> ; while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return nullptr ; } UseIdx = Idx ; return & *


<s> enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_BASE_REG || iform == INSN_FORM_D || iform

== INSN_FORM_DS || iform == INSN_FORM_DQ ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pext_u64 ( unsigned long long __X , unsigned


<s> SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , Alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; SDValue Ops [ <NUM_LIT> ] = { SDValue ( InFP128


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( )


<s> static DecodeStatus DecodeVLD3DupInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm


<s> switch ( LC ) { case RTLIB :: MEMCPY : AEABILibcall = AEABI_MEMCPY ; break ; case RTLIB :: MEMMOVE : AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . IsSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI -> getLibcallCallingConv ( LC ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( FunctionNames [ AEABILibcall ] [ AlignVariant ] ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI -> LowerCallTo (


<s> bool UseBuildVector = false ; int InputUsed [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned LaneStart = l * NumLaneElems ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_BR24 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_THUMB_RELOC_BR22 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_THUMB_RELOC_BR22 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_HALF ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_HALF ) ; Log2Size = <NUM_LIT> ; return true


<s> if ( Subtarget . systemSupportsUnalignedAccess ( LD -> getAddressSpace ( ) ) ) return Op ; assert ( ! MemVT . isFatPointer ( ) ) ; if ( ( LD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) ) { return SDValue ( ) ; } else if ( LD -> getBasePtr ( ) -> getValueType ( <NUM_LIT> ) . isFatPointer ( ) ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LD , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , SDLoc ( LD ) ) ; } else if ( ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) { return SDValue ( ) ; } bool IsLittle = Subtarget . isLittle ( ) ; EVT VT = Op . getValueType ( ) ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef =


<s> } if ( reg != <NUM_LIT> ) { unsigned excess = <NUM_LIT> * ( <STR_LIT> - reg ) ; if ( Subtarget -> isAAPCS_ABI ( ) && NSAAOffset != <NUM_LIT> && size > excess ) { while ( State -> AllocateReg ( GPRArgRegs , <NUM_LIT> ) ) ; return ; } unsigned ByValRegBegin = reg ; unsigned ByValRegEnd = ( size < excess ) ? reg + size / <NUM_LIT> : ( unsigned ) <STR_LIT> ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs , <NUM_LIT> ) ; if ( State -> getCallOrPrologue ( ) == Call ) { if ( size < excess ) size = <NUM_LIT> ; else size


<s> static DecodeStatus DecodeStoreASI64 ( MCInst & Inst , uint64_t insn , uint64_t Address ,


<s> SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / ShVal ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize *


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) || cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) return <NUM_LIT> ; return gen_rtx_REG ( mode , cum + <NUM_LIT>


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder


<s> EmitMappingSymbol ( <STR_LIT> ) ; LastEMS = EMS_Thumb


<s> <ISA_LIT>TargetStreamer & CTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) CTS


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( Reg ) { assert ( Reg == <STR_LIT> && <STR_LIT> ) ; O << 's'


<s> rtx x ; x = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( x ) |= ( SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION ) ; return x


<s> static DecodeStatus DecodeLSAImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Insn + <NUM_LIT> ) ) ; return MCDisassembler ::


<s> const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineInstr * AMI = ASU -> getInstr ( ) ; if ( ! AMI || AMI -> isPseudo ( ) || AMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , nullptr , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , nullptr ) ) ) return false ; for ( SDep & BDep : APreds ) { if ( BDep . isWeak ( ) ) continue ; SUnit * BSU = BDep . getSUnit ( ) ; const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ; if ( Preds ) DAG -> addEdge ( ASU , SDep ( BSU , SDep :: Cluster ) ) ; else DAG -> addEdge ( BSU , SDep ( ASU , SDep :: Cluster ) ) ; for ( SDep & Dep : APreds ) if ( Dep . getSUnit ( ) == BSU ) Dep . setLatency ( <NUM_LIT> ) ; auto & BSuccs = Preds ? BSU -> Succs : BSU -> Preds ; for ( SDep & Dep : BSuccs ) if ( Dep . getSUnit ( ) == ASU ) Dep . setLatency ( <NUM_LIT> ) ; ++


<s> output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT ) return <STR_LIT> ; else return


<s> LaneA = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ViaVecTy = <STR_LIT> ; } else LaneA = LaneB ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Ops , ViaVecTy . getVectorNumElements ( ) ) ; if ( ViaVecTy != ResVecTy ) Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , Result ) ; return


<s> int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = Subtarget . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( NeedsStackRealignment ) { int64_t Bias = Subtarget . getStackPointerBias ( ) ; unsigned regUnbiased


<s> if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! IsZExt ) { unsigned Opc ; if ( SrcVT == <STR_LIT> ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else if ( SrcVT == <STR_LIT> ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else { assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc )


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> std :: unique_ptr < const MCInstrInfo > MII ( T . createMCInstrInfo ( ) ) ; return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , Ctx , std


<s> { const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , Offset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( SUBOpc ) , FinalStackProbed ) . addReg ( FinalStackProbed ) . addImm ( Offset / StackProbeSize * StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } { const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , StackProbeSize ) ; BuildMI ( testMBB , DL , TII . get ( SUBOpc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } addRegOffset ( BuildMI ( testMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( StackPtr ) . addReg ( FinalStackProbed ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( testMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; testMBB -> addSuccessor ( testMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; tailMBB -> splice ( tailMBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( testMBB ) ; unsigned TailOffset = Offset


<s> GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ; TransferImpOps ( MI , MIB , MIB ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIB .


<s> static void aarch64_asm_output_variant_pcs ( FILE * stream , const tree decl , const char * name ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { arm_pcs pcs = ( arm_pcs ) fndecl_abi ( decl ) . id ( ) ; if ( pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; fprintf ( stream


<s> bool isVecListThreeDByteIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> &&


<s> return __builtin_mve_vmullbq_int_m_uv4si ( __arm_vuninitializedq_u64 ( ) , __a


<s> Reg = tryMatchSVEVectorRegister ( Parser . getTok ( ) , Kind , false ) ; if ( Reg == - <NUM_LIT> ) return true ; Parser . Lex ( ) ; RegisterKind = RegKind :: SVEVector ; } Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , RegisterKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT>


<s> unsigned tag ( ) { unsigned int_offset = <NUM_LIT> ; rtx offset = this -> offset ; unsigned dest = REGNO ( this -> dest ) ; unsigned base = REGNO ( this -> base ) ; machine_mode dest_mode = GET_MODE ( this -> dest ) ; unsigned dest_mode_size = GET_MODE_SIZE ( dest_mode ) . to_constant ( ) ; if ( ( dest_mode_size << this -> ldp ) > <NUM_LIT> ) dest = <NUM_LIT> ; if ( offset && REG_P ( offset ) ) int_offset = ( <NUM_LIT> << <NUM_LIT> ) | REGNO ( offset ) ; else if ( offset && CONST_INT_P ( offset ) ) { int_offset = INTVAL ( offset


<s> __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B ,


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; assert ( ( NumElems % <NUM_LIT> ) == <NUM_LIT> && ( SizeInBits % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Lo = extractSubVector ( Op , <NUM_LIT> , DAG , dl


<s> Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return


<s> if ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; } else { if ( isExpandWithZeros ( Op ) ) Op = Op . getOperand ( <NUM_LIT> ) ; else return SDValue (


<s> assert ( SU -> isUnbuffered ) ; if ( LastFPdOpCycleIdx == UINT_MAX ) return true ; unsigned SUCycleIdx = getCurrCycleIdx ( SU ) ; if ( LastFPdOpCycleIdx > SUCycleIdx ) return ( ( LastFPdOpCycleIdx - SUCycleIdx ) == <NUM_LIT> ) ; return ( ( SUCycleIdx - LastFPdOpCycleIdx ) ==


<s> Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES =


<s> if ( Name . front ( ) != 'w' || Name . drop_front ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; return IntVal


<s> if ( ! ( GET_MODE ( dst_reg ) == SImode || GET_MODE ( dst_reg ) == DImode ) ) return NULL ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , m_ccreg , gen_rtx_fmt_ee ( EQ , SImode , src_reg , const0_rtx ) ) ) ; if ( GET_MODE ( dst_reg ) == SImode )


<s> SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) || Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is512BitVector ( ) ) && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector (


<s> unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( Reg0 ) || ! is<ISA_LIT>LowRegister ( Reg1 ) || ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; if ( Reg0 != Reg2 ) { if ( Reg1 != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( MI ) ; if ( ! CommutedMI ) return false ; } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 , CommOpIdx2 ; if ( ! TII -> findCommutedOpIndices ( MI , CommOpIdx1 , CommOpIdx2 ) || CommOpIdx1 != <NUM_LIT> || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( MI ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT>


<s> unsigned AddrReg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SpReg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( <STR_LIT> == SpReg ) && <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( STI , Out , AddrReg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; EmitBICMask ( STI , Out , SpReg , Pred , <NUM_LIT> ) ; Out . EmitBundleUnlock (


<s> while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { Register Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } } if ( needPopSpecialFixUp ( MF )


<s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . FeatureBits = FeatureBits ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> return ( __m256d ) __builtin_ia32_vfnmaddpd256 ( ( __v4df ) __A , (


<s> bool hasSymbolicDisplacement ( ) const { return GV != nullptr || CP != nullptr || ES != nullptr || JT != -


<s> report_fatal_error ( <STR_LIT> ) ; } else Record<ISA_LIT>Relocation ( Writer , Asm , Layout , Fragment , Fixup ,


<s> assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) )


<s> if ( split_branch_probability >= <NUM_LIT> ) { probability = split_branch_probability ; if ( bypass ) bypass_probability = <NUM_LIT> ; if ( second ) second_probability = <NUM_LIT> ; } if ( bypass != NULL_RTX ) { label = gen_label_rtx ( ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , bypass , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; if ( bypass_probability >= <NUM_LIT> ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( bypass_probability ) , REG_NOTES ( i ) ) ; } i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( probability >= <NUM_LIT> ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( probability ) , REG_NOTES ( i ) ) ; if ( second != NULL_RTX ) { i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , second , target1 , target2 ) ) ) ; if ( second_probability >= <NUM_LIT> ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( second_probability


<s> if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> setScavengingFrameIndex


<s> bool <ISA_LIT>ConstantIslands :: OffsetIsInRange ( unsigned UserOffset , unsigned TrialOffset , unsigned MaxDisp , bool NegativeOK , bool IsSoImm ) { if ( UserOffset <= TrialOffset ) { if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK ) { if ( UserOffset - TrialOffset <=


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr =


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseImmediate ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch


<s> const char * const name ; const enum processor_features feature ; } const isa_names_table [ ] = { { <STR_LIT> , F_CMOV } , { <STR_LIT> , F_MMX } , { <STR_LIT> , F_POPCNT } , { <STR_LIT> , F_SSE } , { <STR_LIT> , F_SSE2 } , { <STR_LIT> , F_SSE3 } , { <STR_LIT> , F_SSSE3 } , { <STR_LIT> , F_SSE4_A } , { <STR_LIT> , F_SSE4_1 } , { <STR_LIT> , F_SSE4_2 } , { <STR_LIT> , F_AVX } , { <STR_LIT> , F_FMA4 } , { <STR_LIT> , F_XOP } , { <STR_LIT> , F_FMA } , { <STR_LIT> , F_AVX2 } , { <STR_LIT> , F_AVX512F } , { <STR_LIT> , F_BMI } , { <STR_LIT> , F_BMI2 } , { <STR_LIT> , F_AES } , { <STR_LIT> , F_PCLMUL } , { <STR_LIT> , F_AVX512VL } , { <STR_LIT> , F_AVX512BW } , { <STR_LIT> , F_AVX512DQ } , { <STR_LIT> , F_AVX512CD } , { <STR_LIT> , F_AVX512ER } , { <STR_LIT> , F_AVX512PF } , { <STR_LIT> , F_AVX512VBMI } , { <STR_LIT> , F_AVX512IFMA } , } ; tree __processor_model_type = build_processor_model_struct ( ) ; tree __cpu_model_var = make_var_decl ( __processor_model_type , <STR_LIT> ) ; varpool_node :: add ( __cpu_model_var ) ; gcc_assert ( ( args != NULL ) && ( * args != NULL ) ) ; param_string_cst = * args ; while ( param_string_cst && TREE_CODE ( param_string_cst ) != STRING_CST ) { if ( ! EXPR_P ( param_string_cst ) ) { error ( <STR_LIT> ) ; return integer_zero_node ; } param_string_cst = TREE_OPERAND ( EXPR_CHECK ( param_string_cst ) , <NUM_LIT> ) ; } gcc_assert ( param_string_cst ) ; if ( fn_code == IX86_BUILTIN_CPU_IS ) { tree ref ; tree field ; tree final ; unsigned int field_val = <NUM_LIT> ; unsigned int NUM_ARCH_NAMES = sizeof ( arch_names_table ) / sizeof ( struct _arch_names_table ) ; for ( i = <NUM_LIT> ; i < NUM_ARCH_NAMES ; i ++ ) if ( strcmp ( arch_names_table [ i ] . name , TREE_STRING_POINTER ( param_string_cst ) ) == <NUM_LIT> ) break ; if ( i == NUM_ARCH_NAMES ) { error ( <STR_LIT> , TREE_STRING_POINTER ( param_string_cst ) ) ; return integer_zero_node ; } field = TYPE_FIELDS ( __processor_model_type ) ; field_val = arch_names_table [ i ] . model ; if ( field_val > M_CPU_TYPE_START && field_val < M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( field ) ; field_val -= M_CPU_TYPE_START ; } if ( field_val > M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( DECL_CHAIN ( field ) ) ; field_val -= M_CPU_SUBTYPE_START ; } ref = build3 ( COMPONENT_REF , TREE_TYPE ( field ) , __cpu_model_var , field , NULL_TREE ) ; final = build2 ( EQ_EXPR , unsigned_type_node , ref , build_int_cstu ( unsigned_type_node , field_val ) ) ; return build1 ( CONVERT_EXPR , integer_type_node , final ) ; } else if ( fn_code == IX86_BUILTIN_CPU_SUPPORTS ) { tree


<s> return ( __m512i ) __builtin_ia32_expandloadhi512_mask ( ( const __v32hi * ) __C , ( __v32hi


<s> auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if ( ! StatusDead ) BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( LdarOp ) , Dest . getReg ( ) ) . addReg ( AddrReg ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CmpOp ) , ZeroReg ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . addImm ( ExtendImm ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; BuildMI ( StoreBB , DL , TII -> get ( StlrOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , getKillRegState

( StatusDead ) ) . addMBB ( LoadCmpBB ) ;


<s> ValueRots . clear ( ) ; for ( auto & BG : BitGroups ) { unsigned RLAmtKey = BG . RLAmt + ( BG . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; ValueRotInfo & VRI = ValueRots [ std :: make_pair ( BG . V , RLAmtKey ) ] ; VRI . V = BG . V ; VRI . RLAmt = BG . RLAmt ; VRI . Repl32 = BG . Repl32 ; VRI . NumGroups += <NUM_LIT> ; VRI . FirstGroupStartIdx = std :: min ( VRI . FirstGroupStartIdx , BG . StartIdx ) ; } ValueRotsVec . clear ( ) ; for ( auto & I : ValueRots ) { ValueRotsVec . push_back (


<s> if ( TARGET_64BIT && cfun -> stdarg && crtl -> stack_alignment_estimated

< <NUM_LIT> ) crtl -> stack_alignment_estimated = <NUM_LIT> ;


<s> elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == <NUM_LIT> ) return <NUM_LIT> ; else return max ( <NUM_LIT> , TYPE_VECTOR_SUBPARTS ( vectype )


<s> if ( MaybeImmed == None || * MaybeImmed > <NUM_LIT> ) return None ; uint64_t Enc = <NUM_LIT> - * MaybeImmed ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB .


) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI ->


<s> __rv . __o = __builtin_neon_vld2_dupv8bf ( ( const __builtin_neon_bf * ) __ptr ) ; return __rv .


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_TRUE && recog_memoized ( insn ) >= <NUM_LIT> && recog_memoized ( dep ) >= <NUM_LIT> && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = <NUM_LIT> ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = <NUM_LIT> ; return


<s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const { if ( ! Subtarget . hasBMI (


<s> return ( __m128i ) __builtin_ia32_vpopcountb_v16qi_mask ( ( __v16qi ) __A , ( __v16qi ) __B , (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSimm19Lsl2Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > &

Fixups , const MCSubtargetInfo & STI ) const {


<s> case Instruction :: GetElementPtr : if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = <NUM_LIT> ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <=


<s> EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return

<ISA_LIT>MaterializeInt ( C , VT , VT != <STR_LIT> ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ( RegNo == <NUM_LIT> && ! featureBits [ <STR_LIT> ] ) || RegNo == <NUM_LIT> ) S =


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; if ( Opcode == Instruction :: Store && Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Src -> isVectorTy ( ) && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) && Src -> getVectorNumElements ( ) < <NUM_LIT> ) { unsigned NumVecElts = Src -> getVectorNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts * <NUM_LIT> ; return NumVectorizableInstsToAmortize * NumVecElts * <NUM_LIT> ; } return LT .


<s> return ( __m512i ) __builtin_ia32_loaddquhi512_mask ( ( const short * ) __P , ( __v32hi ) __W


<s> for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI , T . Name ,