<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( VT . isVector ( ) ) { auto ExtendToVec128 = [ & DAG ] ( SDLoc DL , SDValue N ) { EVT InVT = N -> getValueType ( <NUM_LIT> ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , <NUM_LIT> / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( <NUM_LIT> / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDValue ExOp = ExtendToVec128 ( DL , N0 ) ; return DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget -> hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendToVec128 ( DL , SrcVec ) ; SrcVec = DAG . getSignExtendVectorInReg ( SrcVec , DL , SubVT ) ; Opnds . push_back ( SrcVec ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Opnds ) ; } } if ( ! Subtarget -> hasFp256 ( ) ) return SDValue


<s> return ( float32x2_t ) __builtin_neon_vcvtuv2si ( ( int32x2_t )


<s> assert ( checkPartMapping ( PartMappings [ PMI_SPR - PMI_Min ] , <NUM_LIT> , <NUM_LIT> , FPRRegBankID ) && <STR_LIT> ) ; assert ( checkPartMapping ( PartMappings [ PMI_DPR - PMI_Min ] , <NUM_LIT> , <NUM_LIT> , FPRRegBankID


<s> assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return false ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; } Root -> replaceAllUsesWith ( Load ) ; Root -> eraseFromParent ( ) ; if ( Root != I ) I -> eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true


<s> case <NUM_LIT> : if ( Opcode == Instruction :: Load && Src -> getVectorElementType ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return LT . first + ( std :: abs ( Info . getStride ( ) ) - <NUM_LIT> ) ; default : break ; } } unsigned GatherWeight = <NUM_LIT> ; if ( Info . isNonStrided ( ) ) { switch ( Info . getIndexType ( ) -> getScalarSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT>


<s> static DecodeStatus DecodeMemoryValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Register + <NUM_LIT> ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler ::


<s> else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( IsLegal ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VT . getEVTString ( ) << <STR_LIT> << ImmStrVal << <STR_LIT> ) ; return true


<s> machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode


<s> opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch


<s> if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return


<s> if ( <STR_LIT> ( DstMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( LHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( RHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( AccMO . getReg ( ) ) < <NUM_LIT> && DstMO . getReg ( ) == AccMO . getReg ( ) ) { MachineOperand Lhs ( LHSMO ) ; MachineOperand Rhs ( RHSMO ) ; MachineOperand Src ( AccMO ) ; MI . RemoveOperand ( <NUM_LIT>


<s> const char * mmix_data_section_asm_op ( void ) { return


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int *


<s> if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; if ( ! isTypeLegal ( EVT :: getEVT ( Ty1 ) ) ) return false ; assert ( Ty1 -> getPrimitiveSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; return true


<s> d . vmode = vmode ; d . nelt = nelt ; d . one_operand_p = false ; d . testing_p = false ; high = ( highp ? nelt / <NUM_LIT> : <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; ++ i ) { d . perm [ i * <NUM_LIT> ]


<s> static bool isIntrinsicWithCCAndChain ( SDValue Op , unsigned & Opcode , unsigned & CCValid ) { unsigned Id = cast < ConstantSDNode > ( Op .

getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / <NUM_LIT> && MEM_ALIGN ( dest ) == BITS_PER_WORD / <NUM_LIT> ) bits = BITS_PER_WORD / <NUM_LIT> ; else bits = BITS_PER_WORD ; } mode = int_mode_for_size ( bits , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , <NUM_LIT> , <NUM_LIT> ) ) gcc_unreachable ( ) ; } } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits


<s> getHazardType ( SUnit * m , int Stalls


<s> return new <ISA_LIT>PreLegalizerCombiner


<s> SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; Register GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ; AsmNodeOperands . push_back (


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX512 ( ) ) { int Idx = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX512CostTbl [ Idx ] . Cost ; } if ( ST -> hasAVX2 ( ) ) { int Idx = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first *


<s> return ( strict ? REGNO_MODE_OK_FOR_BASE_P ( REGNO ( reg ) , mode ) : GP_REG_OR_PSEUDO_NONSTRICT_P ( REGNO ( reg ) ,


<s> assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; if ( Opc != <STR_LIT> )


<s> if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ; int PSHUFHWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFHWMask , DAG ) ) ) ; } if ( Scale > <NUM_LIT> && EltBits == <NUM_LIT> && Subtarget -> hasSSSE3 ( ) ) { assert ( NumElements == <NUM_LIT> && <STR_LIT> ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) PSHUFBMask [ i ] = DAG . getConstant ( ( i % Scale == <NUM_LIT> ) ? i / Scale : <NUM_LIT> , <STR_LIT> ) ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ; } do { MVT InputVT = <STR_LIT> ( <STR_LIT> ( EltBits ) , NumElements ) ; SDValue Ext = AnyExt ? DAG . getUNDEF ( InputVT ) : getZeroVector ( InputVT , Subtarget , DAG , DL ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV , Ext ) ; Scale /= <NUM_LIT> ; EltBits *= <NUM_LIT> ; NumElements /= <NUM_LIT> ; } while ( Scale > <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> ,


<s> } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ; } switch ( arg_count ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat


<s> const char * abi ; if ( TARGET_HARD_FLOAT ) abi = <STR_LIT> ; else if ( TARGET_SOFT_FLOAT ) abi = <STR_LIT> ; else abi = <STR_LIT>


<s> static bool Is32BitMemOperand ( const MCInst & MI , unsigned Op ) { const MCOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; if ( BaseReg . getReg


<s> if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; MVT ByteVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( ByteVT , Lo ) ; Hi = DAG . getBitcast ( ByteVT , Hi ) ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size (


<s> if ( CustomRegAlloc ) addPass ( create<ISA_LIT>RegisterAllocator ( )


<s> if ( <STR_LIT> ( Src . getNode ( ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned Idx = <NUM_LIT> , e = Src . getNumOperands ( ) ; Idx < e ; ++ Idx ) { if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Subtarget . hasSSE2 ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits ,


<s> emit_insn ( gen_rtx_SET ( scratch_reg , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , offset ) ) ) ; } else { emit_move_insn ( scratch_reg , offset ) ; emit_insn ( ix86_gen_add3 ( scratch_reg , scratch_reg , stack_pointer_rtx ) ) ; } current = scratch_reg ; } ix86_expand_branch ( GEU , current , limit , label ) ; rtx_insn * jump_insn = get_last_insn ( ) ; JUMP_LABEL ( jump_insn ) = label ; add_int_reg_note ( jump_insn , REG_BR_PROB , REG_BR_PROB_BASE - REG_BR_PROB_BASE / <NUM_LIT> ) ; if ( split_stack_fn == NULL_RTX ) { split_stack_fn = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( split_stack_fn ) |= SYMBOL_FLAG_LOCAL ; } fn = split_stack_fn ; allocate_rtx = GEN_INT ( allocate ) ; args_size = crtl -> args . size >= <NUM_LIT> ? crtl -> args . size : <NUM_LIT> ; call_fusage = NULL_RTX ; rtx pop = NULL_RTX ; if ( TARGET_64BIT ) { rtx reg10 , reg11 ; reg10 = gen_rtx_REG ( Pmode , R10_REG ) ; reg11 = gen_rtx_REG ( Pmode , R11_REG ) ; if ( DECL_STATIC_CHAIN ( cfun -> decl ) ) { rtx rax ; rax = gen_rtx_REG ( word_mode , AX_REG ) ; emit_move_insn ( rax , gen_rtx_REG ( word_mode , R10_REG ) ) ; use_reg ( & call_fusage , rax ) ; } if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ! TARGET_PECOFF ) { HOST_WIDE_INT argval ; gcc_assert ( Pmode == DImode ) ; gcc_assert ( ( allocate & HOST_WIDE_INT_C ( <NUM_LIT> ) ) == allocate ) ; gcc_assert ( ( args_size & <NUM_LIT> ) == args_size ) ; if ( split_stack_fn_large == NULL_RTX ) { split_stack_fn_large = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( split_stack_fn_large ) |= SYMBOL_FLAG_LOCAL ; } if ( ix86_cmodel == CM_LARGE_PIC ) { rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = <NUM_LIT> ; emit_insn ( gen_set_rip_rex64 ( reg10 , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( reg11 , label ) ) ; emit_insn ( ix86_gen_add3 ( reg10 , reg10 , reg11 ) ) ; x = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , split_stack_fn_large ) , UNSPEC_GOT ) ; x = gen_rtx_CONST ( Pmode ,


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) { Micro<ISA_LIT>Enabled = false


<s> } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop2 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_rtx_SUBREG ( vimode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 , mask ) ; } bsel = gen_rtx_IOR ( vimode , gen_rtx_AND ( vimode , gen_rtx_NOT ( vimode , mask ) , src2 ) , gen_rtx_AND ( vimode , mask , src1 ) ) ; emit_insn ( gen_rtx_SET ( mask ,


<s> if ( CM ) { if ( * CM == CodeModel :: Tiny ) report_fatal_error ( <STR_LIT> ) ; if ( * CM == CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> ) ; return * CM ; } if ( JIT ) return RM == Reloc :: PIC_

? CodeModel :: Small : CodeModel :: Medium ;


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 ,


, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_805 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_807 ; else if ( Features [ <STR_LIT> ] )


<s> <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ) { int Val = ( int ) C -> getZExtValue ( ) ; if ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val )


<s> uint64_t THMToTHMStub :: initSymValue (


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _lzcnt_u32 ( unsigned int __X ) { return __builtin_clz (


<s> EVT LHSVT = LHS . getValueType ( ) ; SDLoc dl ( Op ) ; if ( LHSVT == <STR_LIT> ) { assert ( ! Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; softenSetCCOperands ( DAG , LHSVT , LHS , RHS , CC , dl , LHS , RHS , Chain , Op -> getOpcode ( ) == <STR_LIT> ) ; if ( RHS . getNode ( ) ) LHS = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , DAG . getCondCode ( CC ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { LHS , Chain } , dl ) ; return LHS ; } assert ( ! IsStrict && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue SetCC32 = DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) , CC ) ; int ShuffV [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Shuff = DAG . getVectorShuffle ( <STR_LIT> , dl ,


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; EverMadeChange = false ; bool FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; bool YMMUsed = FnHasLiveInYmm ; if ( ! YMMUsed ) { const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } } if ( ! YMMUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( FnHasLiveInYmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear (


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : if ( ! hasV7Ops || ! hasMP ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } unsigned addrmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT>


<s> if ( IsDirectBranch ( MI ) ) return false ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( Is64Bit ) { NewMI . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned RegTarget ; if ( Is64Bit ) { RegTarget = ( HideSandboxBase ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } else { RegTarget = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Is64Bit && ! FlagUseZeroBasedSandbox ? <STR_LIT> : <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } DEBUG ( DumpInstructionVerbose ( MI ) ) ; llvm_unreachable ( <STR_LIT>


<s> case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .

get ( <STR_LIT> ) , ResultReg ) . addImm ( CC ) ;


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel

) return new <ISA_LIT>FastISel ( funcInfo ) ;


<s> MachineFunction :: iterator It = MBB ; ++ It ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfTrueReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfFalseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool NZCVKilled = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; if ( ! NZCVKilled ) { TrueBB -> addLiveIn ( <STR_LIT> ) ; EndBB -> addLiveIn ( <STR_LIT> ) ; } BuildMI ( TrueBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfTrueReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; TrueBB -> addSuccessor ( EndBB ) ; MachineInstr * StartOfEnd = EndBB -> begin ( ) ; BuildMI ( * EndBB , StartOfEnd , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addFrameIndex (


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> assert ( Kind == k_Prefetch && <STR_LIT> ) ; return Prefetch .


<s> const MCExpr * <ISA_LIT>_64MCAsmInfoDarwin :: getExprForPersonalitySymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { MCContext & Context = Streamer .


<s> case FusionFeature :: FK_LoadCmp1 : case FusionFeature :: FK_LoadCmp2 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; if ( SecondMI . getOpcode ( ) == <STR_LIT> && matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ) return true ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_LoadCmp3 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_ZeroMoveCTR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_ZeroMoveLR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_AddisAddi : { const MachineOperand & RA = FirstMI . getOperand ( <NUM_LIT> ) ; const MachineOperand & SI = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! SI . isImm ( ) || ! RA . isReg ( ) ) return false ; if ( RA . getReg ( ) == <STR_LIT> || RA . getReg ( ) == <STR_LIT> ) return false ; return SignExtend64 ( SI . getImm ( ) , <NUM_LIT> ) >= <NUM_LIT> ; } case FusionFeature :: FK_AddiAddis :


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ;


<s> const REAL_VALUE_TYPE * r ; if ( GET_MODE ( op ) != SFmode ) return false ; r = CONST_DOUBLE_REAL_VALUE ( op


<s> if ( ReduceLimitLdSt != - <NUM_LIT> && ( ( int ) NumLdSts >= ReduceLimitLdSt ) ) return false ; unsigned Scale = <NUM_LIT> ; bool HasImmOffset = false ; bool HasShift = false ; bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Entry . WideOpc != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm


<s> if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget -> getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( TRI -> hasBasePointer ( DAG . getMachineFunction ( ) ) && TRI -> getBaseRegister ( ) == <STR_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal


<s> break ; case TYPE_MOFFS16 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS32 : case TYPE_REL32 : case TYPE_REL64 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS64 : default : break ; } mcInst . addOperand ( MCOperand :: CreateImm ( immediate


<s> if ( aligned_p && size == <NUM_LIT> && ( GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE ) ) { if ( TARGET_V9 ) { assemble_integer_with_op ( <STR_LIT> , x ) ; return true ; } else { assemble_aligned_integer ( <NUM_LIT> , const0_rtx


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset


<s> return new <ISA_LIT>PassConfig ( this ,


<s> if ( ShiftAmt < <NUM_LIT> ) { ShiftAmt = matchVectorShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , Size , Zeroable , Subtarget ) ; V = V2 ; } if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ShiftVT ) && <STR_LIT> ) ; V = DAG . getBitcast ( ShiftVT , V ) ; V = DAG . getNode ( Opcode , DL , ShiftVT , V , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , V


<s> addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; emit_insn ( gen_rlwinm ( shift , addr , GEN_INT ( <NUM_LIT> ) , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pmask =


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false


<s> } int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V1 = DAG . getNode ( <STR_LIT> , dl , PVT , V1 ) ; V1 = DAG . getVectorShuffle ( PVT , dl , V1 , DAG . getUNDEF ( PVT ) , & SplatMask [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( )


<s> const_tree type = TREE_TYPE ( field_or_array ) ; unsigned int num_zr , num_pr ; if ( <STR_LIT> ( type , & num_zr , & num_pr


<s> if ( OptLEA ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSLM ( ) ) processInstructionForSLM ( I , MFI ) ; else processInstruction ( I , MFI ) ; } } return false


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return


<s> Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT>


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Triple TT ( STI . getTargetTriple ( ) ) ; bool is<ISA_LIT>64 = TT . getArch ( ) == Triple :: ppc64 || TT . getArch


<s> void printwordmem ( const MCInst * MI , unsigned


<s> case 'm' : if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'p' : fprintf ( stream , <STR_LIT> , cfun -> machine -> highest_saved_stack_register + <NUM_LIT> ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT> : break ; default : internal_error ( <STR_LIT> , code ) ; } switch ( GET_CODE ( modified_x )


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return


<s> if ( EnableTZDC_WDC || EnableTZDC_SIG || EnableTZDC_3SIG ) splitMultipleTerminator ( MF ) ; if ( EnableTZDC_WDC ) { MachineFunction :: iterator It = ( MF . end ( ) ) -> getIterator ( ) ; It -- ; tzdcRecoveryMBB = MF . CreateMachineBasicBlock ( It -> getBasicBlock ( ) ) ; It -> addSuccessor ( tzdcRecoveryMBB ) ; DebugLoc DL3 = It -> begin ( ) -> getDebugLoc ( ) ; It = ( MF . end ( ) ) -> getIterator ( ) ; MF . insert ( It , tzdcRecoveryMBB ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; intSkipBlock . push_back ( tzdcRecoveryMBB ) ; } FUNCSIZE = <NUM_LIT> ; triplicateInstructionsTZDC ( MF ) ; if ( EnableTZDC_WDC ) { wrongDirectionCheckingTZDC ( MF ) ; } if ( EnableTZDC_INT ) { interleavingTZDC ( MF ) ; } else if ( EnableTZDC_INT_4INTERLEAVING ) { interleavingTZDC_4Interleaving ( MF ) ; } else if ( EnableTZDC_INT_5INTERLEAVING ) { interleavingTZDC_5Interleaving ( MF ) ; } if ( EnableTZDC_SIG ) insertTZDCSignature ( MF ) ; else if ( EnableTZDC_3SIG ) insertTZDC_3Signature ( MF ) ; else if ( EnableTZDC_3SIG_WITH_WDC ) insertTZDC_3Signature_withWDC ( MF ) ; else if ( EnableTZDC_3SIG_WITH_WDC_INT ) insertTZDC_3Signature_withWDC_INT ( MF ) ; if ( tzdcComplexVoting ) insertComplexRecoveryBlock ( MF ) ; else insertRecoveryBlock ( MF ) ; insertCopyingReturnAddress ( MF ) ; if ( EnableTZDC_jumpRegCheck ) insertRegisterCheckForJump ( MF ) ; intSkipBlock . clear ( ) ; } if ( EnableSWIFTRTriplicationOnly ) { FUNCSIZE = <NUM_LIT> ; triplicateInstructionsSWIFT ( MF ) ; insertCopyingReturnAddress ( MF ) ; } if ( EnableSWIFTREmbeddedLib ) { FUNCSIZE = <NUM_LIT> ; triplicateInstructionsSWIFT ( MF ) ; insertVotingOperations ( MF ) ; copyLoadValuesSWIFTR ( MF ) ; insertCopyingReturnAddress ( MF ) ; if ( EnableSWIFTR_jumpRegCheck ) insertSWIFTRRegisterCheckForJump ( MF ) ; } if ( EnableSWIFTR ) { FUNCSIZE = <NUM_LIT> ; triplicateInstructionsSWIFT ( MF ) ; insertVotingOperations ( MF ) ; copyLoadValuesSWIFTR ( MF ) ; checkFunctionCalls ( MF ) ; } else if ( EnableNEMESISNAIVE ) { FUNCSIZE = MF . size ( ) ; MachineBasicBlock * UnrecoverableERROR = makeErrorBB ( MF ) ; MachineBasicBlock * UnrecoverableERRORInter = makeErrorBB ( MF ) ; MachineBasicBlock * RecoverableErrorBB = makeErrorBB ( MF ) ; triplicateInstructions ( MF ) ; changeLabelsStore ( MF ) ; changeLabelsCMP ( MF ) ; changeCF ( MF ) ; storeCheckNAIVE ( MF , UnrecoverableERROR , UnrecoverableERRORInter , RecoverableErrorBB ) ; changeLabelsCALL ( MF ) ; checkFunctionCalls ( MF ) ; storeBACKUP ( MF ) ; } else if ( EnableNEMESIS ) { fixCompares ( MF ) ; FUNCSIZE = countNumberofStores ( MF ) ; MachineBasicBlock * UnrecoverableERROR =


<s> MachineOperand & JTI3 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! Reg0 . isReg ( ) ) return false ; if ( ! Reg2 . isReg ( ) ) return false ; if ( ! Reg4 . isReg ( ) ) return false ; if ( ! Imm1 . isImm ( ) ) return false ; if ( ! JTI3 . isJTI ( ) ) return false ; MI -> dump ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = STI . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned VReg1 = MF . getRegInfo ( ) . createVirtualRegister (


<s> if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo


<s> case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG


<s> char * colon = strchr ( str , ':' ) ; sscanf ( ++ colon , <STR_LIT>


<s> void <ISA_LIT>ExpandPseudo :: ExpandLaneOp ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead =


<s> if ( NumLoads > <NUM_LIT> ) return false ; if ( FirstLdSt -> getOpcode ( ) != SecondLdSt -> getOpcode ( ) ) return false ; unsigned Ofs1 = FirstLdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Ofs1 > <NUM_LIT> ) return false ; unsigned Ofs2 = SecondLdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return Ofs1 + <NUM_LIT> ==


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL


<s> Align Alignment = CalculateStackSlotAlignment ( ArgVT , OrigVT , Flags , PtrByteSize ) ; ArgOffset = alignTo ( ArgOffset , Alignment ) ; if ( ArgOffset >= LinkageSize + ParamAreaSize ) UseMemory = true ; ArgOffset += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; if ( Flags . isInConsecutiveRegsLast ( ) ) ArgOffset = ( ( ArgOffset + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; if ( ArgOffset > LinkageSize + ParamAreaSize ) UseMemory = true ; if ( ! Flags . isByVal ( ) ) { if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) if ( AvailableFPRs > <NUM_LIT> ) { -- AvailableFPRs ; return false ; } if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) if ( AvailableVRs > <NUM_LIT> ) { -- AvailableVRs ; return false ; } } return UseMemory


<s> FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: dropLLVMManglingEscape ( ParentFunc -> getName ( ) ) , TheModule ) ; if ( auto * C = ParentFunc -> getComdat ( ) ) Trampoline -> setComdat ( C ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB ) ; Value * LSDA = emitEHLSDA ( Builder ,


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( AddOpcode ) ) . addOperand ( MI -> getOperand

( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( - <NUM_LIT> ) ;


<s> if ( checkInFPOPrologue ( L ) ) return true ; if ( ! llvm :: any_of ( CurFPOData -> Instructions , [ ] ( const FPOInstruction & Inst ) { return Inst . Op == FPOInstruction :: SetFrame ; } ) )


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return RI != MF . getRegInfo ( ) . def_end ( ) || MFI


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( Op != nullptr ) RegNum = Op -> getReg


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex (


<s> void Warning ( SMLoc L , const Twine &


<s> PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; break ; case


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned RegNum = MRI -> getDwarfRegNum (


<s> static std :: pair < Value * , Value * > getShape ( PHINode * Phi ) { Use & U = * ( Phi -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; User * V = U . getUser ( ) ; while ( V ) { if ( isAMXCast ( dyn_cast < Instruction > ( V ) ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; OpNo = U . getOperandNo


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; O << getRegisterName ( Reg ) ; assert ( MO2 . isImm ( ) && <STR_LIT>


<s> SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCReg ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG

. getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> bool ret = rs6000_legitimate_address_p ( mode , x , reg_ok_strict ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , reg_ok_strict , ( reload_completed ? <STR_LIT> : <STR_LIT> )


<s> if ( ( qualifiers & qualifier_poly ) != <NUM_LIT> ) return arm_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( ( qualifiers & qualifier_unsigned ) != <NUM_LIT> ) return arm_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else if ( ( qualifiers & qualifier_predicate ) != <NUM_LIT> ) return unsigned_intHI_type_node ; else return arm_lookup_simd_builtin_type ( mode ,


<s> std :: vector < int > NewMask ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) NewMask . push_back ( VT . getVectorNumElements ( ) / <NUM_LIT> + i ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) NewMask . push_back


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool is64Bit = is<ISA_LIT>64 && VT == LLT ::


<s> unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ; if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ; } return true


<s> uint64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp


<s> StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } if ( is<ISA_LIT>64 ( ) && ( CPU == <STR_LIT> || CPU == <STR_LIT> ) ) { Error ( L , <STR_LIT> ) ; return false


<s> if ( VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == <NUM_LIT> ) MaxAlign = Align ( <NUM_LIT> ) ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { Align EltAlign ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType >


<s> if ( Res . getNode ( ) ) for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++ I )

Results . push_back ( Res . getValue ( I ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> MCSymbol * LabelSym = getContext ( ) . getOrCreateSymbol ( SymExpr -> getSymbol ( ) . getName ( ) ) ; const MCExpr * LabelExpr = MCSymbolRefExpr :: create ( LabelSym , getContext ( ) ) ; const MCExpr * Eight = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; const MCExpr * SubExpr = MCBinaryExpr :: createSub ( LabelExpr , Eight , getContext ( ) ) ; MCSymbol * CurrentLocation = getContext ( ) . createTempSymbol ( ) ; const MCExpr * CurrentLocationExpr = MCSymbolRefExpr :: create ( CurrentLocation , getContext ( ) ) ; const MCExpr * SubExpr2 = MCBinaryExpr :: createSub ( CurrentLocationExpr , SubExpr , getContext ( ) ) ; MCDataFragment * DF = static_cast < MCDataFragment * > ( LabelSym -> getFragment ( ) ) ; assert ( DF && <STR_LIT> ) ; MCFixupKind FixupKind = static_cast < MCFixupKind > ( FirstLiteralRelocationKind + ELF


<s> rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 ) return <NUM_LIT> ; if ( USE_ALTIVEC_FOR_ARG_P ( cum , elt_mode , named ) ) { if ( TARGET_64BIT && ! cum -> prototype && ( ! cum -> libcall || ! FLOAT128_VECTOR_P ( elt_mode ) ) ) return <NUM_LIT> ; passed_in_gprs = false ; if ( cum -> vregno + n_elts > ALTIVEC_ARG_MAX_REG + <NUM_LIT> ) ret = ( ALTIVEC_ARG_MAX_REG + <NUM_LIT> - cum -> vregno ) * <NUM_LIT> ; } if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( mode , type ) ) return <NUM_LIT> ; align_words = rs6000_parm_start ( mode , type , cum


<s> if ( ST -> hasMVEIntegerOps ( ) ) { if ( Opcode == Instruction :: Load && isLegalMaskedLoad ( Src , Alignment ) ) return ST -> getMVEVectorCostFactor ( CostKind ) ; if ( Opcode == Instruction :: Store && isLegalMaskedStore ( Src , Alignment ) ) return ST


<s> if ( CondBr == PredMBB -> begin ( ) ) return false ; DomBBClobberedRegs . reset ( ) ; MachineBasicBlock :: reverse_iterator RIt = CondBr . getReverseIterator ( ) ; for ( MachineInstr & PredI : make_range ( std :: next ( RIt ) , PredMBB -> rend ( ) ) ) { bool IsCMN = false ; switch ( PredI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : IsCMN = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { if ( ! PredI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; MCPhysReg DstReg = PredI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MCPhysReg SrcReg = PredI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Res = false ; if ( PredI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! DomBBClobberedRegs [ SrcReg ] && SrcReg != DstReg ) { int32_t KnownImm = PredI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t Shift = PredI . getOperand ( <NUM_LIT> ) . getImm ( ) ; KnownImm <<= Shift ; if ( IsCMN ) KnownImm = - KnownImm ; FirstUse = PredI ; KnownRegs . push_back ( RegImm ( SrcReg , KnownImm ) ) ; Res = true ; } if ( DstReg == <STR_LIT> || DstReg == <STR_LIT> ) return Res ; if ( DomBBClobberedRegs [ DstReg ] ) return Res ; FirstUse = PredI ; KnownRegs . push_back ( RegImm ( DstReg , <NUM_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI ) ; if ( Result . getNode ( ) ) return Result ; } if ( N1 . getOpcode ( ) == <STR_LIT> && N1


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _umwait ( unsigned int __A , unsigned long


<s> return is<ISA_LIT>64 ( ) ? <STR_LIT> :


<s> int FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( FirstInputOp + <NUM_LIT> ) , N -> getOperand ( FirstInputOp - <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , VT ) ; uint16_t Opcode = SelectFPOpcode ( VT , OpcodeF16


<s> vmovn_s16 ( int16x8_t a ) { int8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MIB -> setDesc ( TII . get ( MinusOne ? <STR_LIT> : <STR_LIT> ) ) ; MIB . addReg ( Reg


<s> bool doMBBSchedRegionsTopDown ( ) const override { return true


<s> case LEU : scratch0 = gen_reg_rtx ( SImode ) ; scratch1 = gen_reg_rtx ( SImode ) ; const_scratch = force_reg ( SImode , GEN_INT ( MT_MIN_INT ) ) ; emit_insn ( gen_addsi3 ( scratch0 , const_scratch , op0 ) ) ; emit_insn ( gen_addsi3 ( scratch1 , const_scratch , op1 ) ) ; break ; default : scratch0 = op0 ; scratch1 = op1 ; break ; } switch ( code ) { case GTU : code = GT ; break ; case LTU


<s> case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : if ( GV -> hasDefaultVisibility ( ) ) return false ; case GlobalValue :: ExternalLinkage : case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; } if ( RelMod == Reloc :: PIC_ &&


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { if ( Subtarget . isFlavorIntel ( ) ) return new <ISA_LIT>WinTargetAsmInfo ( * this ) ; else switch ( Subtarget . TargetType ) { case <ISA_LIT>Subtarget :: isDarwin : return new <ISA_LIT>DarwinTargetAsmInfo ( * this ) ; case <ISA_LIT>Subtarget :: isELF : return new <ISA_LIT>ELFTargetAsmInfo ( * this ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget ::


<s> DebugLoc dl = Op . getDebugLoc ( ) ; int CompareOpc ; bool isDot ; if ( ! getAltivecCompareInfo ( Op , CompareOpc , isDot ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) } ; std :: vector < EVT > VTs ; VTs . push_back ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; VTs . push_back ( <STR_LIT> ) ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case


<s> MBBI = mergeUpdateInsn ( MBBI , Update , false ) ; return true ; } if ( TII -> hasUnscaledLdStOffset ( MI . getOpcode ( ) ) ) return false ; Update = findMatchingUpdateInsnBackward ( MBBI , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } int UnscaledOffset = getLdStOffsetOp ( MI ) . getImm ( ) * TII -> getMemScale ( MI ) ; Update = findMatchingUpdateInsnForward ( MBBI , UnscaledOffset , UpdateLimit ) ; if ( Update !=


<s> virtual const char * getPassName ( ) const { return


<s> unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? E_DImode : E_DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + <NUM_LIT> ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem (


<s> void addImm0_508s4NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr >


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler (


<s> SDLoc dl ( N ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; SDNodeTreeBuilder b ( & DAG , dl ) ; if ( DCI . isBeforeLegalize ( ) && ( ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) || ( Subtarget -> hasAVX ( ) && VT == <STR_LIT> ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; N


<s> if ( MI -> memoperands_empty ( ) ) return ; Align Alignment = Align ( <NUM_LIT> ) ; for ( MachineInstr :: mmo_iterator MMOI = MI -> memoperands_begin ( ) , EE = MI -> memoperands_end ( ) ; MMOI != EE ; ++ MMOI ) if ( ( * MMOI ) -> getAlign ( ) < Alignment ) Alignment = ( * MMOI ) -> getAlign ( ) ; unsigned AlignmentHint =


<s> static void report_out_of_range ( location_t location , tree fndecl , unsigned int

argno , HOST_WIDE_INT actual , HOST_WIDE_INT min , HOST_WIDE_INT max ) {


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc dl ; assert ( Cond . empty ( ) && ! FBB && TBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return


<s> bool SelectAddrModeIndexed64 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexed ( N , <NUM_LIT>


<s> if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned CurReg = FirstReg - <NUM_LIT> ; CurReg >= RD0Reg && RegsNeeded ; -- CurReg ) { if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded


<s> } else if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; } else if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; } if ( Variant != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; } break ; } if ( getParser ( ) . parseExpression ( EVal ) ) return true ; if ( Variant != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true


<s> void Warning ( SMLoc L , const Twine &


<s> Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode


<s> return false ; } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty


<s> assert ( MemRefBeginIdx >= <NUM_LIT> && <STR_LIT> ) ; MemRefBeginIdx += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; MachineOperand & IndexMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; if ( ( BaseMO . isReg ( ) && BaseMO . getReg ( ) == DefReg ) || ( IndexMO . isReg ( ) && IndexMO . getReg ( ) == DefReg ) ) return { } ; continue ; } if ( SingleUseMI ) return { } ; if ( ! isDataInvariant ( UseMI ) || UseMI . getParent ( ) != MI . getParent ( ) ) return { } ; if ( UseMI . getDesc ( ) . getNumDefs ( ) > <NUM_LIT> ) return { } ; unsigned UseDefReg = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( UseDefReg ) || ! canHardenRegister ( UseDefReg ) ) return { } ; SingleUseMI = & UseMI ; } return { SingleUseMI } ; } ; MachineInstr * MI = & InitialMI ; while ( Optional < MachineInstr * > SingleUse = SinkCheckToSingleUse ( * MI ) ) { MI = *


<s> __builtin_aarch64_simd_xi __o ; uint8x16x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v8qi ( ( __builtin_aarch64_simd_qi * ) __a , __o


<s> break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrA = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrB = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next (

MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ;


<s> if ( ST -> getCPUDirective ( ) == <STR_LIT> ) { UP . Partial = UP


<s> void <ISA_LIT>FastISel :: addLoadStoreOperands ( Address & Addr , const MachineInstrBuilder & MIB , MachineMemOperand :: Flags Flags , unsigned ScaleFactor , MachineMemOperand * MMO ) { int64_t Offset = Addr . getOffset ( ) / ScaleFactor ; if ( Addr . isFIBase ( ) ) { int FI = Addr . getFI ( ) ; MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; MIB . addFrameIndex ( FI ) . addImm ( Offset ) ; } else { assert ( Addr . isRegBase ( ) && <STR_LIT> ) ; const MCInstrDesc & II = MIB -> getDesc ( ) ; unsigned Idx = ( Flags & MachineMemOperand :: MOStore ) ? <NUM_LIT> : <NUM_LIT> ; Addr . setReg ( constrainOperandRegClass ( II , Addr . getReg ( ) , II .


<s> <STR_LIT> getMemBarrierOpt ( ) const { assert ( Kind == k_MemBarrierOpt &&


<s> MCInst LoadMI ; LoadMI . setOpcode ( LoadOpcode ) ; LoadMI . addOperand ( MCOperand :: createReg ( LoadDefRegister ) ) ; for ( auto I = MI . operands_begin ( ) + LoadOperandsBeginIdx , E = MI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI ,

* I ) ) LoadMI . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; } return


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex

( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> unsigned Op1 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> RemoveOperand


<s> char pattern [ <NUM_LIT> ] ; rtx operands [ <NUM_LIT> ] ; int rb_va_args = cfun -> machine -> va_args_first_regno ; int re_va_args = cfun -> machine -> va_args_last_regno ; int last_argument_regno = NDS32_FIRST_GPR_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - <NUM_LIT> ; int rb_eh_data = cfun -> machine -> eh_return_data_first_regno ; int re_eh_data = cfun -> machine -> eh_return_data_last_regno ; int first_eh_data_regno = EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ; int rb_callee_saved = cfun -> machine -> callee_saved_first_gpr_regno ; int re_callee_saved = cfun -> machine -> callee_saved_last_gpr_regno ; if ( reg_mentioned_p ( gen_rtx_REG ( SImode , last_argument_regno ) , par_rtx ) ) { operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_va_args ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_va_args ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ; } if ( reg_mentioned_p ( gen_rtx_REG ( SImode , first_eh_data_regno ) , par_rtx ) ) { operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_eh_data ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_eh_data ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ; } if ( NDS32_V3PUSH_AVAILABLE_P ) { int sp_adjust ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) ) operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; } else { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; } } snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; } else { int push_en4_only_p = <NUM_LIT> ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_callee_saved ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; if ( ! cfun -> machine -> fp_size && ! cfun -> machine -> gp_size && ! cfun -> machine -> lp_size && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) { return <STR_LIT>


<s> enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> ,


<s> setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner RetAssigner ( AssignFn ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; return determineAndHandleAssignments ( RetHandler , RetAssigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( )


<s> case <STR_LIT> : return ! II -> getFastMathFlags ( ) . allowReassoc ( ) ; case <STR_LIT> : case <STR_LIT> : return ! II -> getFastMathFlags ( )


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end (


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S :


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , <NUM_LIT> ) , Pmode ) ; * quot_p = quot


<s> unsigned Opc = CallTarget . isGlobal ( ) ? <STR_LIT> : <STR_LIT> ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; OriginalCall -> addOperand ( CallTarget ) ; unsigned RegMaskStartIdx = <NUM_LIT> ; while ( ! MI . getOperand ( RegMaskStartIdx ) . isRegMask ( ) ) { auto MOP = MI . getOperand ( RegMaskStartIdx ) ; assert ( MOP . isReg ( ) && <STR_LIT> ) ; OriginalCall -> addOperand ( MachineOperand :: CreateReg ( MOP . getReg ( ) , false , true ) ) ; RegMaskStartIdx ++ ; } for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , RegMaskStartIdx ) ) OriginalCall -> addOperand ( MO ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; auto * RVCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( RVTarget ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) ->

moveCallSiteInfo ( & MI , OriginalCall ) ;


<s> if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> )

) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ;


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true


<s> MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( MachineInstr & MI : llvm :: drop_begin ( llvm :: reverse ( MBB ) ) ) { if ( MI . modifiesRegister ( <STR_LIT> , TRI ) ) { ConditionDef = & MI ; break ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition


<s> if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= <NUM_LIT> ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= <NUM_LIT> ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= <NUM_LIT> ; src_align >>= <NUM_LIT> ) { if ( ( src_align_bytes & ( src_align - <NUM_LIT> ) ) == ( align_bytes & ( src_align - <NUM_LIT> ) ) ) break ; } if ( src_align > ( unsigned int ) desired_align ) src_align = desired_align ; if ( MEM_ALIGN ( src ) < src_align * BITS_PER_UNIT ) set_mem_align ( src , src_align * BITS_PER_UNIT ) ; } if ( MEM_SIZE_KNOWN_P ( orig_src ) ) set_mem_size ( src , MEM_SIZE


<s> EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) . divideCoefficientBy ( N ) ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys ,


<s> if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( bit ) ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , dst << <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( dst ) ) ; return


<s> return ( countLeadingZeros ( Chunk ) + CountTrailingOnes_64 (


<s> uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT>


<s> if ( Opc != Instruction :: Add && Opc != Instruction :: Sub ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; auto * NewConst = ConstantInt :: get ( Ctx , Const -> getValue ( ) . abs ( ) ) ; Builder . SetInsertPoint ( I ) ; Value * NewVal = Opc == Instruction :: Sub ? Builder . CreateAdd ( I -> getOperand ( <NUM_LIT> ) , NewConst ) : Builder . CreateSub ( I -> getOperand ( <NUM_LIT> ) , NewConst ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewVal << <STR_LIT> ) ; if ( auto * NewInst = dyn_cast < Instruction > (


<s> SDValue N2 ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl ,


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; return


<s> bool getNoBTIAtReturnTwice ( ) const { return NoBTIAtReturnTwice


<s> assert ( <NUM_LIT> < Scale && <STR_LIT> ) ; size_t NumElts = Mask . size ( ) ; ScaledMask . assign ( NumElts * Scale , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != ( int ) NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale * i


<s> void setCalleeSavedFrameSize ( unsigned


<s> return Op . getOpcode ( ) == <STR_LIT> || cast < ConstantSDNode > ( Op ) -> getZExtValue (


<s> void <ISA_LIT>IntelInstPrinter :: printMemReference ( const MCInst * MI , unsigned Op , raw_ostream & O ) { if ( MI -> getOperand ( Op + <NUM_LIT> ) . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':'


<s> static DecodeStatus DecodeGRH32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void *


<s> } unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) . addImm ( ShiftAmt ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( ShiftAmt ) ; return


<s> assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; int MaskWidth = std :: max < int > ( OpMask . size ( ) , RootMask . size ( ) ) ; int RootRatio = std :: max < int > ( <NUM_LIT> , OpMask . size ( ) / RootMask . size ( ) ) ; int OpRatio = std :: max < int > ( <NUM_LIT> , RootMask . size ( ) / OpMask . size ( ) ) ; assert ( ( ( RootRatio == <NUM_LIT> && OpRatio == <NUM_LIT> ) || ( RootRatio == <NUM_LIT> ) != ( OpRatio == <NUM_LIT> ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . reserve ( MaskWidth ) ; for ( int i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { int RootIdx = i / RootRatio ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask . push_back ( RootMask [ RootIdx ] ) ; continue ; } int RootMaskedIdx = RootMask [ RootIdx ] * RootRatio + i % RootRatio ; int OpIdx = RootMaskedIdx / OpRatio ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask . push_back ( OpMask


<s> Name = ISB ? ISB -> Name : <STR_LIT> ; } else if ( Opcode == <STR_LIT> ) { auto TSB = <STR_LIT> ( Val ) ; Name = TSB ? TSB -> Name : <STR_LIT> ; } else { auto DB = <STR_LIT> ( Val ) ; Name = DB ? DB -> Name : <STR_LIT> ; } if ( ! Name . empty ( ) ) O << Name ; else O << <STR_LIT> <<


<s> if ( Amount > <NUM_LIT> ) return true ; assert ( MRI . getType ( AmtReg ) . getSizeInBits ( ) == <NUM_LIT> ) ; MIRBuilder . setInstr ( MI ) ; auto ExtCst = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , AmtReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg (


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF , false ) ; int NegFrameSize = - FrameSize ; bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI . getMaxAlignment (


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op


<s> unsigned Reg = <STR_LIT> [ FirstGPR ] ; int Offset = RegSpillOffsets [ Reg ] ; if ( StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } } } ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; CurrOffset = - <STR_LIT> ; } else { uint32_t LowGR64Num = UINT32_MAX ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned GR64Num = <STR_LIT> ( Reg ) ; int Offset = - <NUM_LIT> * ( <NUM_LIT> - GR64Num + <NUM_LIT> ) ; if ( LowGR64Num > GR64Num ) { LowGR64Num = GR64Num ; StartSPOffset = <STR_LIT> + Offset ; } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( <NUM_LIT> , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } if ( LowGR64Num < UINT32_MAX ) LowGPR = <STR_LIT> [ LowGR64Num ] ; ZFI -> setRestoreGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; CurrOffset = LowGPR ? - ( <STR_LIT> - StartSPOffset ) : <NUM_LIT> ; } for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; CurrOffset -= Size ; assert ( CurrOffset % <NUM_LIT> == <NUM_LIT>


<s> emitPopInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , isVarArg , true , & is<ISA_LIT>Area3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area2Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg ,