<s> unsigned MaskTZ = CountTrailingZeros_64 ( Mask ) ; unsigned AMShiftAmt = MaskTZ ; if ( AMShiftAmt <= <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; if ( CountTrailingOnes_64 ( Mask >> MaskTZ ) + MaskTZ + MaskLZ != <NUM_LIT> ) return true ; MaskLZ -= ( <NUM_LIT> - X . getValueSizeInBits ( ) ) + ShiftAmt ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getValueSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getValueSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; EVT VT = N . getValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , X . getDebugLoc ( ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } DebugLoc DL = N . getDebugLoc ( ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> ,


<s> if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type )

== TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType (


<s> int _U_Qfcomp ( long double a , long double b ) { if ( _U_Qfcmp ( a , b , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return ( _U_Qfcmp ( a , b , <NUM_LIT> ) != <NUM_LIT> ?


<s> if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return LOW_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return MIDDLE_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return HIGH_REGS ; else if ( regno == <NUM_LIT> ) return R15_TA_REG ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT>


<s> static SDValue LowerCTPOP ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Op . getSimpleValueType ( ) . isVector ( )


<s> static DecodeStatus DecodeI32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = I32RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> InsnType Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler


<s> SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Res , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT>


<s> insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; insertDAGNode ( DAG , N , NewMask ) ; insertDAGNode ( DAG , N , NewAnd ) ; insertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; DAG . RemoveDeadNode ( N . getNode ( ) ) ; AM . Scale =


<s> Register IndexReg = LeaI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; Register AluDestReg = AluI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator CurInst = std :: next ( LeaI ) ; while ( CurInst != AluI ) { for ( unsigned I = <NUM_LIT> , E = CurInst -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Opnd = CurInst -> getOperand ( I ) ; if ( ! Opnd . isReg ( ) ) continue ; Register Reg = Opnd . getReg ( ) ; if ( TRI -> regsOverlap ( Reg , AluDestReg ) ) AluDestRef = true ; if ( TRI -> regsOverlap ( Reg , BaseReg ) ) { if ( Opnd . isDef ( ) ) BaseIndexDef = true ; else if ( Opnd . isKill ( ) ) * KilledBase = & Opnd ; } if ( TRI -> regsOverlap ( Reg , IndexReg ) ) { if ( Opnd . isDef ( ) ) BaseIndexDef = true ; else if ( Opnd . isKill ( ) ) * KilledIndex = & Opnd ; } } ++


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl ,


<s> } FixedVectorType * PtrTy = cast < FixedVectorType > ( Ptr -> getType ( ) ) ; if ( PtrTy -> getNumElements ( ) != <NUM_LIT> || MemoryTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return nullptr ; Value * Zero = ConstantInt :: get ( Builder . getInt32Ty ( ) , <NUM_LIT> ) ; Value * BasePtr = Builder . CreateIntToPtr ( Zero , Builder . getInt8PtrTy ( ) ) ; Offsets = Builder . CreatePtrToInt ( Ptr , FixedVectorType :: get (

Builder . getInt32Ty ( ) , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case


<s> bool isHiImm16 ( ) { if ( ! isImm ( ) ) return false ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return Value != <NUM_LIT> && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return

SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> unsigned <ISA_LIT>FlagsCopyLoweringPass :: promoteCondToReg ( MachineBasicBlock & TestMBB , MachineBasicBlock :: iterator TestPos , DebugLoc TestLoc , <STR_LIT> Cond ) { unsigned Reg = MRI -> createVirtualRegister ( PromoteRC ) ; auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ( Cond ) ) , Reg ) ; ( void )


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTLZ ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getValueType ( ) ; MVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Op ) ; Ops . push_back ( DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( Op . getValue ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , & Ops [ <NUM_LIT> ] , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode


<s> void neon_reinterpret ( rtx dest , rtx src ) { emit_move_insn ( dest , gen_lowpart ( GET_MODE ( dest )


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C ) { Ctx =


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; return ( VT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget

) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ;


<s> static bool CheckTyN ( unsigned N , const LegalityQuery & Query , std :: initializer_list < LLT > SupportedValues ) { return llvm :: is_contained ( SupportedValues , Query . Types


<s> static void ReplaceREADCYCLECOUNTER ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc DL ( N ) ; SDValue Cycles32 , OutChain ; if ( Subtarget -> hasPerfMon ( ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) } ; Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Ops [ <NUM_LIT> ] , array_lengthof ( Ops ) ) ; OutChain = Cycles32 . getValue ( <NUM_LIT>


<s> V = rotr32 ( ~ <NUM_LIT> , getSOImmValRotate ( V ) ) & V ; assert ( V == ( rotr32 ( <NUM_LIT> , getSOImmValRotate ( V ) ) & V


<s> MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; BI -> getCondition ( ) ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitCmp ( CondReg , CI ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg )


<s> if ( hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> unsigned Reg = I32RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> void initPICLabelUId ( unsigned UId ) { PICLabelUId = UId


<s> floats_from_frame = ( offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) - offsets -> frame ) ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { num_regs ++ ; floats_from_frame += <NUM_LIT> ; } if ( TARGET_VFP_BASE ) { int start_reg ; rtx ip_rtx = gen_rtx_REG ( SImode , IP_REGNUM ) ; int saved_size = arm_get_vfp_saved_size ( ) ; if ( saved_size > <NUM_LIT> ) { rtx_insn * insn ; floats_from_frame += saved_size ; insn = emit_insn ( gen_addsi3 ( ip_rtx , hard_frame_pointer_rtx , GEN_INT ( - floats_from_frame ) ) ) ; arm_add_cfa_adjust_cfa_note ( insn , - floats_from_frame , ip_rtx , hard_frame_pointer_rtx ) ; } start_reg = FIRST_VFP_REGNUM ; for ( i = FIRST_VFP_REGNUM ; i < LAST_VFP_REGNUM ; i += <NUM_LIT> ) if ( ! reg_needs_saving_p ( i ) && ! reg_needs_saving_p ( i + <NUM_LIT> ) ) { if ( start_reg != i ) arm_emit_vfp_multi_reg_pop ( start_reg , ( i - start_reg ) / <NUM_LIT> , gen_rtx_REG ( SImode , IP_REGNUM ) ) ; start_reg = i + <NUM_LIT> ; } if ( start_reg != i ) arm_emit_vfp_multi_reg_pop ( start_reg , ( i - start_reg ) / <NUM_LIT> , gen_rtx_REG ( SImode , IP_REGNUM ) ) ; } if ( TARGET_IWMMXT ) { rtx_insn * insn ; int lrm_count = ( num_regs % <NUM_LIT> ) ? ( num_regs + <NUM_LIT> ) : ( num_regs + <NUM_LIT> ) ; for ( i = LAST_IWMMXT_REGNUM ; i >= FIRST_IWMMXT_REGNUM ; i -- ) if ( reg_needs_saving_p ( i ) ) { rtx addr = gen_frame_mem ( V2SImode , plus_constant ( Pmode , hard_frame_pointer_rtx , - lrm_count * <NUM_LIT> ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( V2SImode , i ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( V2SImode , i ) , NULL_RTX ) ; lrm_count += <NUM_LIT> ; } } gcc_assert ( saved_regs_mask & ( <NUM_LIT> << IP_REGNUM ) ) ; saved_regs_mask &= ~ ( <NUM_LIT>


<s> const <ISA_LIT>PLT & <ISA_LIT>GNULDBackend :: getPLT (


<s> initialize<ISA_LIT>TOCRegDepsPass ( * PassRegistry :: getPassRegistry (


<s> break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V2 = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( * tp == NULL_TREE || * tp == error_mark_node || TYPE_P ( * tp ) ) { * walk_subtrees = <NUM_LIT> ; return NULL_TREE ; } switch ( TREE_CODE ( * tp


<s> int i ; bool any_alg_usable_p = false ; * noalign = false ; * dynamic_check = - <NUM_LIT> ; if ( optimize_function_for_size_p ( cfun ) || ( optimize_insn_for_size_p ( ) && ( max_size < <NUM_LIT> || ( expected_size != - <NUM_LIT> && expected_size < <NUM_LIT> ) ) ) ) optimize_for_speed = false ; else optimize_for_speed = true ; cost = optimize_for_speed ? ix86_cost : & ix86_size_cost ; if ( memset ) algs = & cost -> memset [ TARGET_64BIT != <NUM_LIT> ] ; else algs = & cost -> memcpy [ TARGET_64BIT != <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < MAX_STRINGOP_ALGS ; i ++ ) { enum stringop_alg candidate = algs -> size [ i ] . alg ; bool usable = alg_usable_p ( candidate , memset , have_as ) ; any_alg_usable_p |= usable ; if ( candidate != libcall && candidate && usable ) max = algs -> size [ i ] . max ; } if ( ( ( max > <NUM_LIT> && ( unsigned HOST_WIDE_INT ) max >= max_size ) || max == - <NUM_LIT> ) && expected_size == - <NUM_LIT> ) expected_size = min_size / <NUM_LIT> + max_size / <NUM_LIT> ; if ( ix86_stringop_alg != no_stringop && alg_usable_p ( ix86_stringop_alg , memset , have_as ) ) return ix86_stringop_alg ; else if ( ! optimize_for_speed ) { * noalign = true ; if ( ! count || ( count & <NUM_LIT> ) || ( memset && ! zero_memset ) ) return alg_usable_p ( rep_prefix_1_byte , memset , have_as ) ? rep_prefix_1_byte : loop_1_byte ; else return alg_usable_p ( rep_prefix_4_byte , memset , have_as ) ? rep_prefix_4_byte


<s> unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ?


<s> BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size =


<s> static bool isZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ;


<s> bool <ISA_LIT>TTIImpl :: areTypesABICompatible ( const Function * Caller , const Function * Callee , const ArrayRef < Type * > & Types ) const { if ( ! BaseT :: areTypesABICompatible ( Caller , Callee , Types ) ) return false ; const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( * Caller ) . useAVX512Regs ( ) == TM . getSubtarget < <ISA_LIT>Subtarget > ( * Callee ) . useAVX512Regs ( ) ) return true ; return llvm :: none_of ( Types , [ ] ( Type * T ) { return T

-> isVectorTy ( ) || T -> isAggregateType ( ) ; } ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned MemOpc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) .

addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ;


<s> SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG .


<s> auto CreateLoad = [ & DAG , & DL , & Loads ] ( EVT VT , LoadSDNode * LDBase ) { auto MMOFlags = LDBase -> getMemOperand ( ) -> getFlags ( ) ; assert ( ! ( MMOFlags & MachineMemOperand :: MOVolatile ) && <STR_LIT> ) ; SDValue NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , MMOFlags ) ; for ( auto * LD : Loads ) DAG . makeEquivalentMemoryOrdering ( LD , NewLd ) ; return NewLd ; } ; if ( FirstLoadedElt == <NUM_LIT> && LastLoadedElt == ( int ) ( NumElems - <NUM_LIT> ) && ( IsConsecutiveLoad || IsConsecutiveLoadWithZeros ) ) { assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( LDBase -> isNonTemporal ( ) && LDBase -> getAlignment ( ) >= <NUM_LIT> && VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return SDValue ( ) ; if ( IsConsecutiveLoad ) return CreateLoad ( VT , LDBase ) ; if ( ! isAfterLegalize && NumElems == VT . getVectorNumElements ( ) ) { SmallVector < int , <NUM_LIT> > ClearMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { if ( ZeroMask [ i ] ) ClearMask [ i ] = i + NumElems ; else if ( LoadMask [ i ] ) ClearMask [ i ] = i ; } SDValue V = CreateLoad ( VT , LDBase ) ; SDValue Z = VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getVectorShuffle ( VT , DL , V , Z , ClearMask ) ; } } int LoadSize = ( <NUM_LIT> + LastLoadedElt - FirstLoadedElt ) * LDBaseVT . getStoreSizeInBits ( ) ; if ( IsConsecutiveLoad && FirstLoadedElt == <NUM_LIT> && ( LoadSize == <NUM_LIT> || LoadSize == <NUM_LIT> ) && ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) || VT . is512BitVector ( ) ) ) ) { MVT VecSVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( LoadSize ) : <STR_LIT> ( LoadSize ) ; MVT VecVT = <STR_LIT> ( VecSVT , VT . getSizeInBits ( ) / LoadSize ) ; if ( TLI . isTypeLegal (


<s> } } } SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasAVX512 ( ) && Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Mask . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( ! Subtarget . hasAVX512 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; KnownBits Known ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , Known , TLO ) ) { DCI . AddToWorklist ( Mask . getNode ( ) ) ; DCI . CommitTargetLoweringOpt ( TLO ) ; return SDValue ( N , <NUM_LIT>


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm


<s> static Constant * SegmentOffset ( IRBuilderBase & IRB , int Offset , unsigned AddressSpace ) { return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) ->


<s> static MCStreamer * createELFStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , std ::

unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {


<s> if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != <NUM_LIT> || Alignment <= <NUM_LIT> || Ty ==

LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ;


<s> unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } case <STR_LIT> : { unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp0 == <NUM_LIT> ) return <NUM_LIT> ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } } if ( isTargetShuffle ( Opcode ) ) { SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { return <NUM_LIT> ; } else if ( M == SM_SentinelZero ) { continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { return <NUM_LIT> ; } DemandedOps [ OpIdx ] . setBit ( EltIdx ) ; } unsigned Tmp0 = VTBits


<s> unsigned size = <NUM_LIT> ; switch ( T . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , EFLAGS ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) ,


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI ->

hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ;


<s> if ( OldCollisions . size ( ) <= <NUM_LIT> ) continue ; bool Fixed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( ! DebugCounter :: shouldExecute ( FixCounter ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; continue ; } for ( unsigned OpI = <NUM_LIT> , OpE = MI . getNumOperands ( ) ; OpI < OpE ; ++ OpI ) { if ( OpI == static_cast < unsigned > ( LdI . BaseRegIdx ) ) continue ; MachineOperand & MO = MI . getOperand ( OpI ) ; if ( MO . isReg ( ) && MO . readsReg ( ) ) LR . addReg ( MO . getReg ( ) ) ; } for ( unsigned ScratchReg : <STR_LIT> ) { if ( ! LR . available ( ScratchReg ) || MRI . isReserved ( ScratchReg ) ) continue ; LoadInfo NewLdI ( LdI ) ; NewLdI . BaseReg = ScratchReg ; unsigned NewTag = * getTag ( TRI , MI , NewLdI ) ; if ( TagMap . count ( NewTag ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg ( ScratchReg ) ; if ( LdI . IsPrePost ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ScratchReg ) ; BuildMI ( * MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , DL , TII -> get ( <STR_LIT> ) , LdI . BaseReg ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } for ( int I = <NUM_LIT> , E = OldCollisions . size ( ) ; I != E ; ++ I ) if ( OldCollisions [ I ] == & MI ) { std :: swap ( OldCollisions [ I ] , OldCollisions [ E - <NUM_LIT> ] ) ; OldCollisions . pop_back ( ) ; break ; } TagMap [ NewTag ] . push_back ( & MI ) ; ++ NumCollisionsAvoided ; Fixed =


<s> Value * Ptr = U -> getOperand ( <NUM_LIT> ) ; if ( auto GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) { return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ; } return TTI ::


<s> return ( int ) __builtin_loongarch_crcc_w_d_w ( ( long int ) _1 , ( int


<s> bool isRegBase ( ) const { return Kind


<s> unsigned getVectorListStart ( ) const { assert ( Kind == k_VectorList && <STR_LIT> ) ; return VectorList


<s> void <ISA_LIT>InstPrinter :: printBDAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI ->

getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) , <NUM_LIT> , O ) ;


<s> return - <NUM_LIT> ; case ENCODING_VVVV : insn -> vvvv = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> vvvv , & valid ) ; if ( ! valid ) return - <NUM_LIT> ; break ; case ENCODING_REG : insn -> reg = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> reg - insn -> regBase , & valid ) ; if ( ! valid ) return - <NUM_LIT> ; break ; CASE_ENCODING_RM : CASE_ENCODING_VSIB : if ( insn -> eaBase >= insn -> eaRegBase ) { insn -> eaBase = ( EABase ) fixupRMValue ( insn , ( OperandType ) op -> type , insn -> eaBase - insn -> eaRegBase , & valid ) ; if ( ! valid )


<s> static DecodeStatus DecodePredNoALOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val >= <STR_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> Cost = vectorCostAdjustment ( Cost , Opcode , Src , nullptr ) ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || * Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && * Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; if ( TLI -> allowsMisalignedMemoryAccesses ( LT . second , <NUM_LIT> ) ) return Cost ; assert ( Alignment


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return TargetLoweringBase :: isBinOp


<s> static bool DisassemblePseudo ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded ,


<s> return ( uint16x4_t ) __builtin_aarch64_ld1v4hi ( ( const __builtin_aarch64_simd_hi * ) a


<s> bool <ISA_LIT>TargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( ! Subtarget -> isThumb1Only ( ) )


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction (


<s> if ( prepareBaseForDispFormChain ( Bucket , Form ) ) MadeChange |= rewriteLoadStores ( L , Bucket , BBChanged , Form ) ; } if ( MadeChange ) for ( auto * BB


<s> } case <STR_LIT> : { EVT T = N -> getValueType ( <NUM_LIT> ) ; assert ( ( T == <STR_LIT> || T == <STR_LIT> ) && <STR_LIT> ) ; bool Regs64bit = T == <STR_LIT> ; EVT HalfT = Regs64bit ? <STR_LIT> : <STR_LIT> ; SDValue cpInL , cpInH ; cpInL = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; cpInH = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; cpInL = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , cpInL , SDValue ( ) ) ; cpInH = DAG . getCopyToReg ( cpInL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , cpInH , cpInL . getValue ( <NUM_LIT> ) ) ; SDValue swapInL , swapInH ; swapInL = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; swapInH = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; swapInL = DAG . getCopyToReg ( cpInH . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , swapInL , cpInH . getValue ( <NUM_LIT> ) ) ; swapInH = DAG . getCopyToReg ( swapInL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , swapInH , swapInL . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { swapInH . getValue ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , swapInH . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; unsigned Opcode = Regs64bit ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getMemIntrinsicNode ( Opcode , dl , Tys , Ops , <NUM_LIT> , T , MMO ) ; SDValue cpOutL = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , HalfT , Result . getValue ( <NUM_LIT> ) ) ; SDValue cpOutH = DAG . getCopyFromReg ( cpOutL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , HalfT , cpOutL . getValue ( <NUM_LIT> ) ) ; SDValue OpsF [ ] = { cpOutL . getValue ( <NUM_LIT> ) , cpOutH . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , T , OpsF , <NUM_LIT> ) ) ; Results . push_back ( cpOutH . getValue ( <NUM_LIT> ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static bool simplify<ISA_LIT>MaskedStore ( IntrinsicInst & II , InstCombiner & IC ) { Value * Ptr = II . getOperand ( <NUM_LIT> ) ; Value * Mask = II . getOperand ( <NUM_LIT> ) ; Value * Vec = II . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantAggregateZero > ( Mask ) ) { IC . eraseInstFromFunction ( II ) ; return true ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) return false ; if ( Value * BoolMask = getBoolVecFromMask ( Mask ) ) { unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace


<s> case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned VARegSize , VARegSaveSize ; computeRegArea ( CCInfo , MF , VARegSize , VARegSaveSize ) ; VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , <NUM_LIT> ) ; unsigned Bytes = Flags . getByValSize ( ) - VARegSize ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , false ) ; InVals . push_back ( DAG . getFrameIndex ( FI , getPointerTy ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy


<s> if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp


<s> aputs ( <STR_LIT> ) ; if ( sortspace ) aputs ( <STR_LIT> ) ; aputs ( <STR_LIT> ) ; if ( flag_tm ) aputs (


<s> break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; } base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_8 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT>


<s> assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; MVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx / Scale ; if ( ( V0Opc != <STR_LIT> || V0BroadcastIdx != <NUM_LIT> ) && V0Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Scalar = V0 .


<s> rtx rbp = gen_rtx_REG ( DImode , BP_REG ) ; gcc_assert ( m -> fs . fp_valid ) ; gcc_assert ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) ; tmp = plus_constant ( DImode , rbp , <NUM_LIT> ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_SET ( stack_pointer_rtx , tmp ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_SET ( rbp , gen_rtx_MEM ( DImode , rbp ) ) ; tmp = gen_rtx_MEM ( BLKmode , gen_rtx_SCRATCH ( VOIDmode ) ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_CLOBBER ( VOIDmode , tmp ) ; } else { gcc_assert ( ! m -> fs . fp_valid ) ; gcc_assert ( m -> fs . cfa_reg == stack_pointer_rtx ) ; gcc_assert ( m -> fs . sp_valid ) ; r10 = gen_rtx_REG ( DImode , R10_REG ) ; tmp = plus_constant ( Pmode , rsi , stub_ptr_offset ) ; emit_insn ( gen_rtx_SET ( r10 , tmp ) ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_SET ( stack_pointer_rtx , r10 ) ; } } for ( i = <NUM_LIT> ; i < ncregs ; ++ i ) { const xlogue_layout :: reginfo & r = xlogue . get_reginfo ( i ) ; machine_mode mode = SSE_REGNO_P ( r . regno ) ? V4SFmode : word_mode ; rtx reg , frame_load ; reg = gen_rtx_REG ( mode , r . regno ) ; frame_load = gen_frame_load ( reg , rsi , r . offset ) ; if ( r . regno == SI_REG ) { gcc_assert ( ! rsi_frame_load ) ; rsi_frame_load = frame_load ; rsi_restore_offset = r . offset ; } else { RTVEC_ELT ( v , vi ++ ) = frame_load ; ix86_add_cfa_restore_note ( NULL , reg , r . offset ) ; } } gcc_assert ( rsi_frame_load ) ; gcc_assert ( rsi_restore_offset != ( HOST_WIDE_INT ) - <NUM_LIT> ) ; RTVEC_ELT ( v , vi ++ ) = rsi_frame_load ; ix86_add_cfa_restore_note ( NULL , gen_rtx_REG ( DImode , SI_REG ) , rsi_restore_offset ) ; if ( ! use_call && ! frame_pointer_needed ) { gcc_assert ( m -> fs . sp_valid ) ; gcc_assert ( ! m -> fs . sp_realigned ) ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += m

-> fs . sp_offset - frame . stack_realign_offset ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF )


<s> case TYPE_R16 : case TYPE_R32 : case TYPE_R64 : case TYPE_Rv : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 : case TYPE_Mv


<s> if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode ,


<s> SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT>


<s> return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( )


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> InFlag = Result . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Result , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops1 [ ] = { Chain , DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , DAG . getRegister ( <STR_LIT> , PtrVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; N01 = peekThroughBitcasts ( N01 ) ; if ( ! <STR_LIT> ( N01 . getNode ( ) ) ) { if ( ! VT . is256BitVector ( ) || N01 -> getOpcode ( ) != <STR_LIT> )


<s> case <STR_LIT> : return combineADC ( N , DAG , DCI ) ; case <STR_LIT> : return combineMul ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAnd ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineXor ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : return combineVZextMovl ( N , DAG ) ; case


<s> if ( value == SVE_SCALABLE || value == SVE_128 ) return poly_uint16 ( <NUM_LIT> , <NUM_LIT> ) ; else return ( int ) value


<s> return __builtin_aarch64_clrsbv2si ( __a )


<s> if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || maybe_gt ( initial_adjust , <NUM_LIT> ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( tmp0_rtx , tmp1_rtx , initial_adjust , ( ! can_inherit_p || ! crtl -> is_leaf || df_regs_ever_live_p ( EP0_REGNUM ) ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { switch ( aarch64_ra_sign_key ) { case AARCH64_KEY_A : insn = emit_insn ( gen_autiasp ( ) ) ; break ; case AARCH64_KEY_B : insn = emit_insn ( gen_autibsp ( ) ) ; break ; default : gcc_unreachable ( ) ; } add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ( maxCallFrameSize & ( MaxAlign - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) )

. addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ;


<s> MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase


<s> uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , N , <STR_LIT> ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , ConstLo ) ; if ( ImmHi ) { SDValue ConstHi = CurDAG -> getTargetConstant ( ImmHi >> <NUM_LIT> , N , <STR_LIT> ) ; Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , SDValue ( Move , <NUM_LIT> ) , ConstHi ) ; } ReplaceNode ( N ,


<s> if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , InsertReg ) . addReg (

ZeroReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUnalignedMemAccessFast ( ) ) return false ; unsigned Alignment = RC -> getSize ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , TM ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first , MMOs . second ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; std :: copy ( AfterOps . begin ( ) , AfterOps . end ( ) , std :: back_inserter ( BeforeOps ) ) ; SDNode * NewNode = DAG . getMachineNode ( Opc , dl , VTs , BeforeOps ) ; NewNodes . push_back ( NewNode ) ; if ( FoldedStore ) { AddrOps . pop_back ( ) ; AddrOps . push_back ( SDValue ( NewNode , <NUM_LIT> )


<s> bool <ISA_LIT>StackTagging :: isInterestingAlloca ( const AllocaInst & AI ) { bool IsInteresting = AI . getAllocatedType ( ) -> isSized ( ) && AI . isStaticAlloca ( ) && AI . getAllocationSizeInBits ( * DL ) . getValue ( ) > <NUM_LIT> && ! AI . isUsedWithInAlloca ( ) && ! AI . isSwiftError

( ) && ! ( SSI && SSI -> isSafe ( AI ) ) ;


<s> StringRef getToken ( ) const { assert ( Kind == k_Token && <STR_LIT>


<s> for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0

} ) setAction ( { MemOp , Ty } , Legal ) ;


<s> } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; } getTargetStreamer ( ) . updateABIInfo ( * Subtarget ) ; getTargetStreamer ( ) . emitDirectiveModuleFP ( ) ; if ( Subtarget -> isABI_O32 ( ) ) getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( Subtarget -> useOddSPReg ( ) , Subtarget ->


<s> rtx comparison_rtx ( void ) const { return setcc . set_src (


<s> unsigned RetOpcode = MI -> getOpcode ( ) ; isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; isTrap = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT>


<s> LUi = <STR_LIT> ; } else { ADDiu = <STR_LIT> ; ORi = <STR_LIT> ; SLL = <STR_LIT> ; LUi = <STR_LIT> ; } InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size ,


<s> O << '#' << FP -> getValueAPF ( ) . convertToDouble ( ) ; if ( isVerbose ( ) ) { O << <STR_LIT> << MAI -> getCommentString (


<s> static void initialize_aarch64_code_model ( struct gcc_options * opts ) { if ( opts -> x_flag_pic ) { switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : aarch64_cmodel = AARCH64_CMODEL_TINY_PIC ; break ; case AARCH64_CMODEL_SMALL : aarch64_cmodel = ( flag_pic == <NUM_LIT> ? AARCH64_CMODEL_SMALL_PIC


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - ( STI -> isTargetDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> } if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT>


<s> MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition =


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>elDisassembler


<s> if ( is64Bit ) { Base = GetTLSADDR ( DAG , DAG . getEntryNode ( ) , GA , NULL , PtrVT , <STR_LIT> , <STR_LIT> , true ) ; } else { SDValue InFlag ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Base = GetTLSADDR ( DAG , Chain , GA , & InFlag ,


<s> } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , SrcReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , DstReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> ,


<s>
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
CSStackSize
+=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
MaxAlign
=
getStackAlignment
(
)
;
int64_t
SVEStackSize
=
alignTo
(
determineSVEStackSize
(
MFI
,
MaxAlign
)
,
MaxAlign
)
;
assert
(
MaxAlign
<=
<NUM_LIT>
&&
<STR_LIT>
)
;
bool
CanEliminateFrame
=
(
SavedRegs
.
count
(
)
==
<NUM_LIT>
)
&&
!
SVEStackSize
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
SVEStackSize
||
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPR
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;
int
FI
=
MFI
.
CreateStackObject
(
Size
,
Align
,
false
)
;
RS
->
addScavengingFrameIndex
(
FI
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
FI
<<
<STR_LIT>
)
;
}
}
CSStackSize
+=
<NUM_LIT>
*
(
SavedRegs
.
count
(
)
NumSavedRegs
)
;
unsigned
AlignedCSStackSize
=
alignTo
(
CSStackSize


<s> Res -> Imm . LocalRef = ! GlobalRef ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = true ; return


<s> CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode

) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ;


<s> MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( <NUM_LIT> ) ; else MCE . emitWordLE (


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { static const MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT>


<s> rtx new_rtx = orig ; if ( TARGET_MACHO && ! TARGET_64BIT ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ; return machopic_legitimize_pic_address ( orig , GET_MODE ( orig ) , reg ) ; } if ( TARGET_64BIT && TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { rtx tmp = legitimize_pe_coff_symbol ( addr , true ) ; if ( tmp ) return tmp ; } if ( TARGET_64BIT && legitimate_pic_address_disp_p ( addr ) ) new_rtx = addr ; else if ( ( ! TARGET_64BIT || ix86_cmodel != CM_SMALL_PIC ) && ! TARGET_PECOFF && gotoff_operand ( addr , Pmode ) ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , XEXP ( addr , <NUM_LIT> ) ) , UNSPEC_GOTOFF ) ; new_rtx = gen_rtx_PLUS ( Pmode , new_rtx , XEXP ( addr , <NUM_LIT> ) ) ; } else new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_GOTOFF ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; if ( TARGET_64BIT ) new_rtx = copy_to_suggested_reg ( new_rtx , reg , Pmode ) ; if ( reg != <NUM_LIT> ) { gcc_assert ( REG_P ( reg ) ) ; new_rtx = expand_simple_binop ( Pmode , PLUS , pic_offset_table_rtx , new_rtx , reg , <NUM_LIT> , OPTAB_DIRECT ) ; } else new_rtx = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , new_rtx ) ; } else if ( ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( addr ) == <NUM_LIT> ) || ( TARGET_VXWORKS_RTP && GET_CODE ( addr ) == LABEL_REF ) ) { rtx tmp = legitimize_pe_coff_symbol ( addr , true ) ; if ( tmp ) return tmp ; if ( TARGET_64BIT && TARGET_PECOFF ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_PCREL ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; } else if ( TARGET_64BIT && ix86_cmodel


<s> case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case


<s> llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT> :


<s> iq2000_va_start ( valist , nextarg ) { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ if ( Pmode == DImode ) \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ else \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \

fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ }


<s> if ( dest ) pattern = gen_maddsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) , copy_rtx ( lo ) ) ; else pattern = gen_maddsi3_lo ( lo , src1 , src2 , copy_rtx ( lo ) ) ; mep_rewrite_mult ( insn , pattern


<s> const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT>


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm || Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm ) && <STR_LIT> ) ; Mem . Offset = off


<s> bool <ISA_LIT>TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useIndirectThunkBranches ( ) ) return false ; return TargetLowering :: areJTsAllowed (


<s> unsigned <ISA_LIT>AsmParser :: parseAluOperator ( bool PreOp , bool PostOp ) { StringRef IdString ; Parser . parseIdentifier ( IdString ) ; unsigned AluCode = LPAC :: stringTo<ISA_LIT>AluCode ( IdString ) ; if ( AluCode == LPAC :: UNKNOWN ) { Error ( Parser . getTok ( ) . getLoc


<s> SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . isMIPS32 ( ) ) UseIntegratedAssembler = true ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUABI64 ) UseIntegratedAssembler = true ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUABIN32 ) UseIntegratedAssembler = true ; if ( TheTriple . getArch ( ) == Triple :: mips64el && TheTriple . isAndroid ( ) ) UseIntegratedAssembler = true ; if ( TheTriple . isOSFreeBSD ( ) || TheTriple . isOSOpenBSD ( ) ) UseIntegratedAssembler


<s> if ( n >= <NUM_LIT> ) abort ( ) ; arg = default_conversion ( arg ) ; type = TREE_TYPE ( arg ) ; if ( POINTER_TYPE_P ( type ) && TREE_CODE ( arg ) == NOP_EXPR && lang_hooks . types_compatible_p ( TREE_TYPE ( arg ) , const_ptr_type_node ) && lang_hooks . types_compatible_p ( TREE_TYPE ( TREE_OPERAND ( arg , <NUM_LIT> ) ) , ptr_type_node ) ) { arg = TREE_OPERAND ( arg , <NUM_LIT> ) ; type = TREE_TYPE ( arg ) ; } if ( POINTER_TYPE_P ( decl_type ) && POINTER_TYPE_P ( type ) && TYPE_QUALS ( TREE_TYPE ( type ) ) != <NUM_LIT> ) { if ( TYPE_READONLY ( TREE_TYPE ( type ) ) && ! TYPE_READONLY ( TREE_TYPE ( decl_type ) ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , n + <NUM_LIT> , fndecl ) ; type = build_pointer_type ( build_qualified_type ( TREE_TYPE ( type ) , <NUM_LIT> ) ) ; arg = fold_convert ( type , arg ) ; } args [ n ] = arg ; types [ n ] = type ; } if ( ! VOID_TYPE_P ( TREE_VALUE ( fnargs ) ) ||


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ;


<s> if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG .


<s> tree value = tree_cons ( NULL_TREE , mangled_name_tree , NULL_TREE ) ; value = tree_cons ( NULL_TREE , size_int ( num_pr ) , value ) ; value = tree_cons ( NULL_TREE , size_int ( num_zr ) , value


<s> return RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq (

& <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) ;


<s> else if ( Reg . Group == RegV ) RegNo = <STR_LIT> [ Reg . Num ] ; else return Error ( Reg . StartLoc , <STR_LIT> ) ; StartLoc = Reg . StartLoc ; EndLoc = Reg . EndLoc ; return


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * Var , const MDNode * Expr , const DebugLoc & DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( Var ) . addMetadata ( Expr ) ; return &


<s> case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return nullptr ; if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) { Error ( Start , <STR_LIT> , SMRange ( Start , End ) ) ; return nullptr ; } if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) . Lex ( ) ; return ParseMemOperand ( RegNo , Start )


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> << <STR_LIT> << MF . getFrameInfo (

) . getObjectAlignment ( FrameIndex ) << <STR_LIT> ) ;


<s> StringRef Name ; if ( check ( getParser ( ) . parseIdentifier ( Name ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return true ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Name ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , getContext ( ) ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . emitInstruction


<s> if ( GET_MODE_CLASS ( mode1 ) != GET_MODE_CLASS ( mode2 ) ) return false ; return


<s> case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: create ( std :: numeric_limits < int32_t > :: min ( ) , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } LLVM_FALLTHROUGH ; case AsmToken :: Colon : { S = Parser . getTok ( ) . getLoc ( ) ; <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S , E ) ) ; return false ; } case AsmToken ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DL ( getDataLayoutString ( Subtarget ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Subtarget . isBGP (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addNEONi8ReplicateOperands ( Inst ,


<s> return ! ( hasFP ( MF ) && MFI -> hasVarSizedObjects (


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false


<s> LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , Unsupported } , { <NUM_LIT> , WidenScalar } , { <NUM_LIT> , Unsupported } , { <NUM_LIT> , WidenScalar } , { <NUM_LIT> , Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest +


<s> bool isMicro<ISA_LIT> ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits (


<s> return ( __m512 ) __builtin_ia32_dpbf16ps_v16sf ( __A ,


<s> build_32_64 ( b , signature , group , MODE_u32base_index , MODE_u64base_index ,


<s> else Inst . addOperand ( MCOperand :: CreateImm ( Value ) ) ; return MCDisassembler :: Success


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> if ( SDValue SrcVector = IsSplatVector ( V , SplatIdx , DAG ) ) return DAG . getNode ( <STR_LIT> , dl , SrcVector . getValueType ( ) . getScalarType ( ) , SrcVector , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; return SDValue ( )


<s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Pg = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( SwapOperands ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( SwapOperands ? <NUM_LIT> : <NUM_LIT> ) ; if ( isAllActivePredicate ( DAG , Pg ) ) { if ( UnpredOp ) return DAG . getNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op1 , Op2 ) ; return DAG . getNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Pg , Op1


<s> SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> )


<s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx addr , addr_reg , tramp , eight = GEN_INT ( <NUM_LIT> ) ; if ( ! TARGET_GNU_AS ) { static bool declared_ia64_trampoline = false ; if ( ! declared_ia64_trampoline ) { declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , <STR_LIT> ) ; } } addr = convert_memory_address ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = copy_to_reg ( addr ) ; m_tramp = adjust_automodify_address ( m_tramp , Pmode , addr_reg , <NUM_LIT> ) ; tramp = gen_rtx_SYMBOL_REF ( Pmode


<s> OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> .


<s> if ( ! getTargetShuffleMask ( N , VT , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { V = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = V . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorNumElements ( ) != NumElems ) return SDValue ( ) ; } if ( V . getOpcode ( ) == <STR_LIT> ) return ( Index == <NUM_LIT> ) ? V . getOperand ( <NUM_LIT>

) : DAG . getUNDEF ( VT . getVectorElementType ( ) ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT>


<s> ReuseLoadInfo RLI ; LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , false , false , RLI

. IsInvariant , RLI . Alignment , RLI . AAInfo , RLI . Ranges ) ;


<s> return ( uint32x2_t ) __builtin_neon_vtstv2si (


<s> public : <ISA_LIT>MCInstLower ( MCContext & CTX , AsmPrinter & AP ) : Ctx ( CTX ) , Printer ( AP ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand &


<s> const char * ix86_output_call_insn ( rtx_insn * insn , rtx call_op ) { bool direct_p = constant_call_address_operand ( call_op , VOIDmode ) ; bool seh_nop_p = false ; const char * xasm ; if ( SIBLING_CALL_P ( insn ) ) { if ( direct_p ) xasm = <STR_LIT> ; else if ( TARGET_SEH


<s> } else if ( ! is64Bit ) { AtI [ <NUM_LIT> ] = BUILD_LIS ( <NUM_LIT> , To >> <NUM_LIT> ) ; AtI [ <NUM_LIT> ] = BUILD_ORI ( <NUM_LIT> , <NUM_LIT> , To ) ; AtI [ <NUM_LIT> ] = BUILD_MTCTR ( <NUM_LIT> ) ; AtI [ <NUM_LIT> ] = BUILD_BCTR ( isCall ) ; } else { AtI [ <NUM_LIT> ] = BUILD_LIS ( <NUM_LIT> ,


<s> static SDValue getTargetVShiftNode ( unsigned Opc , const SDLoc & dl , MVT VT , SDValue SrcOp , SDValue ShAmt , SelectionDAG & DAG ) { MVT SVT = ShAmt . getSimpleValueType ( ) ; assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Op0 = ShAmt . getOperand ( <NUM_LIT> ) ; Op0 = DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , <STR_LIT> , Op0 ) ; ShAmt = getShuffleVectorZeroOrUndef ( Op0 , <NUM_LIT> , true , Subtarget , DAG ) ; } else { SmallVector < SDValue , <NUM_LIT> > ShOps ; ShOps . push_back ( ShAmt ) ; if ( SVT == <STR_LIT> ) { ShOps . push_back ( DAG . getConstant ( <NUM_LIT> , dl , SVT ) ) ; ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; } ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; MVT BVT = SVT ==


<s> if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { O << '#' ; unsigned TF = MO . getTargetFlags ( ) ; if ( TF == <STR_LIT> ) O


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return ( __m128i ) vec_mergel ( ( __v8hu ) __A , ( __v8hu )


<s> SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm4 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI


<s> if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt ,

DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ;


<s> int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegP ( Reg , Offset


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag (


<s> static const Constant * getTargetShuffleMaskConstant ( SDValue MaskNode ) { while ( MaskNode . getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode . getOperand ( <NUM_LIT> ) ; auto * MaskLoad = dyn_cast < LoadSDNode > ( MaskNode ) ; if ( ! MaskLoad


<s> assert ( ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) && <STR_LIT> ) ; if ( OpInfo . Type == MCLOH_AdrpAddStr && OpInfo . MI1 == nullptr ) { OpInfo . Type = MCLOH_AdrpLdrGotStr ; OpInfo . IsCandidate = true ; OpInfo . MI1 = & MI ; return true ; } else if ( OpInfo . Type == MCLOH_AdrpLdr ) { OpInfo . Type = MCLOH_AdrpLdrGotLdr ; OpInfo . IsCandidate = true ; OpInfo . MI1 = & MI ; return true ; } } return false


<s> tmpInst . addOperand ( MCOperand :: createImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( SrcRegOp . getReg ( ) ) ) ; Instructions . push_back


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrModePC ( SDValue N , SDValue & Offset , SDValue & Label ) { return false


<s> unsigned EltSize = InterLane ? <NUM_LIT> : VT . getVectorElementType ( ) . getSizeInBits ( ) >> <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . is512BitVector ( ) ? <NUM_LIT> : VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; int Val = <NUM_LIT> ; unsigned i


<s> Value * <ISA_LIT>IREmitter :: visitREP_STOS ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned <STR_LIT> ( unsigned RelaxOp ) { if ( const <ISA_LIT>InstrRelaxTableEntry * I = lookupShortTable ( RelaxOp ) ) return


<s> tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , <NUM_LIT> , const0_rtx , Pmode ) ; r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( TARGET_64BIT ) insn = gen_tls_gd_aix64 ( r3 , got , addr , tga , const0_rtx ) ; else insn = gen_tls_gd_aix32 ( r3 , got , addr , tga , const0_rtx ) ; } else if ( DEFAULT_ABI == ABI_V4 ) insn = gen_tls_gd_sysvsi ( r3 , got , addr , tga , const0_rtx ) ; else gcc_unreachable ( ) ; call_insn = last_call_insn ( ) ; PATTERN ( call_insn ) = insn ; if ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; emit_library_call_value ( tga , tmp1 , LCT_CONST , Pmode , <NUM_LIT> , const0_rtx , Pmode ) ; r3 = gen_rtx_REG (


<s> if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_ATT ) O << '%' ; Register Reg = MO . getReg ( ) ; if ( strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { unsigned Size = ( strcmp ( Modifier + <NUM_LIT>


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) return std :: make_unique < TargetLoweringObjectFileMachO >


<s> bool <ISA_LIT>ConstantIslands :: fixupUnconditionalBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 ) llvm_unreachable


<s> for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( ix86_save_reg ( regno , true


<s> } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( isSmallTypeLdMerge ( Opc ) ) { if ( ! IsUnscaled ) OffsetImm /= <NUM_LIT> ; MachineInstr * RtNewDest = MergeForward ? I : Paired ; if ( ! Subtarget -> isLittleEndian ( ) ) std :: swap ( RtMI , Rt2MI ) ; MachineInstr * NewMemMI , * BitExtMI1 , * BitExtMI2 ; NewMemMI = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( RtNewDest ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; concatenateMemOperands ( NewMemMI , I , Paired ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( NewMemMI ) -> print ( dbgs ( ) ) ) ; MachineInstr * ExtDestMI = MergeForward ? Paired : I ; if ( ( ExtDestMI == Rt2MI ) == Subtarget -> isLittleEndian ( ) ) { BitExtMI1 = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BitExtMI2 = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; } else { BitExtMI1 = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; BitExtMI2 = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) .


<s> case ELF :: R_LANAI_32 : case ELF :: R_LANAI_HI16 : return true ; default : return


<s> } Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; return true


<s> if ( GET_CODE ( address ) == CONST_INT ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & <NUM_LIT> ) ; return ; } if ( CONSTANT_P ( address ) || GET_CODE ( address ) == CODE_LABEL ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( GET_CODE ( XEXP ( address , <NUM_LIT> ) ) == CONST_INT


<s> unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase


<s> DOP_ENTRY_SD ( ps , inst , ty ) { <STR_LIT> ## _B , { <STR_LIT> ## _B , <STR_LIT> ## _B , \ <STR_LIT>


<s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SignBits [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; bool IsPositive [ <NUM_LIT> ] = { false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Opd = N -> getOperand ( i ) ; if ( Opd . getOpcode ( ) == <STR_LIT> ) { if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) SignBits [ i ] = <NUM_LIT> ; else if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) SignBits [ i ] = <NUM_LIT> ; else return false ; IsPositive [ i ] = true ; } else { SignBits [ i ] = DAG . ComputeNumSignBits ( Opd ) ; if ( DAG . SignBitIsZero ( Opd ) ) IsPositive [ i ] = true ; } } bool AllPositive = IsPositive [ <NUM_LIT> ] && IsPositive [ <NUM_LIT> ] ; unsigned MinSignBits = std :: min ( SignBits [ <NUM_LIT> ] , SignBits [ <NUM_LIT> ] ) ; if ( MinSignBits >= <NUM_LIT> ) Mode = MULS8 ; else if ( AllPositive && MinSignBits >= <NUM_LIT> ) Mode = MULU8 ; else if ( MinSignBits >= <NUM_LIT> ) Mode = MULS16 ; else if ( AllPositive && MinSignBits >= <NUM_LIT> ) Mode = MULU16 ; else return false