<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> :


<s> if ( ( NumElems * Elt . getValueSizeInBits ( ) ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; } else return SDValue ( ) ; } assert ( ( ZeroMask | UndefMask | LoadMask ) . count ( ) == NumElems && <STR_LIT> ) ; if ( UndefMask . count ( ) == NumElems ) return DAG . getUNDEF ( VT ) ; if ( ( ZeroMask | UndefMask ) . count ( ) == NumElems ) return VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; int FirstLoadedElt = LoadMask . find_first ( ) ; SDValue EltBase = peekThroughBitcasts ( Elts [ FirstLoadedElt ] ) ; LoadSDNode * LDBase = cast < LoadSDNode > ( EltBase ) ; EVT LDBaseVT = EltBase . getValueType ( ) ; bool IsConsecutiveLoad = true ; bool IsConsecutiveLoadWithZeros = true ; for ( int i = FirstLoadedElt + <NUM_LIT> ; i <= LastLoadedElt ; ++ i ) { if ( LoadMask [ i ] ) { SDValue Elt = peekThroughBitcasts ( Elts [ i ] ) ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . areNonVolatileConsecutiveLoads ( LD , LDBase , Elt . getValueType ( ) . getStoreSizeInBits ( ) / <NUM_LIT> , i - FirstLoadedElt ) ) { IsConsecutiveLoad = false ; IsConsecutiveLoadWithZeros = false ; break ; } } else if ( ZeroMask [ i ] ) { IsConsecutiveLoad = false ; } } SmallVector < LoadSDNode * , <NUM_LIT> > Loads ; for ( int i = FirstLoadedElt ; i <= LastLoadedElt ; ++ i ) if ( LoadMask [ i ] ) Loads . push_back ( cast < LoadSDNode > ( peekThroughBitcasts ( Elts [ i ] ) ) ) ; auto CreateLoad = [ & DAG , & DL , & Loads ] ( EVT VT ,


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat (


<s> unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned imm10 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm11 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned tmp = ( S << <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) | ( imm10 << <NUM_LIT> ) | imm11 ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst

. addOperand ( MCOperand :: createImm ( imm32 ) ) ;


<s> if ( Mask & <NUM_LIT> ) MIB . addReg ( <STR_LIT> , Flag ) ; if ( Mask & <NUM_LIT> ) MIB . addReg ( <STR_LIT> , Flag ) ; if ( Mask & <NUM_LIT> ) MIB . addReg ( <STR_LIT> , Flag ) ; if ( Mask & <NUM_LIT> ) MIB . addReg ( <STR_LIT> , Flag ) ; if ( Mask & <NUM_LIT> ) MIB . addReg ( <STR_LIT> , Flag ) ; if ( Mask & <NUM_LIT> ) MIB . addReg (


<s> assert ( InstIn . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool IsWin64 = Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) -> getCallingConv ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumGPRArgRegs = array_lengthof ( GPRArgRegs ) ; unsigned FirstVariadicGPR = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; unsigned GPRSaveSize = <NUM_LIT> * ( NumGPRArgRegs - FirstVariadicGPR ) ; int GPRIdx = <NUM_LIT> ; if ( GPRSaveSize != <NUM_LIT> ) { if ( IsWin64 ) { GPRIdx = MFI . CreateFixedObject ( GPRSaveSize , - ( int ) GPRSaveSize , false ) ; if ( GPRSaveSize & <NUM_LIT> ) MFI . CreateFixedObject ( <NUM_LIT> - ( GPRSaveSize & <NUM_LIT> ) , - ( int ) alignTo ( GPRSaveSize , <NUM_LIT> ) , false ) ; } else GPRIdx = MFI . CreateStackObject ( GPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext *


<s> rtx tmp_reg = operands [ <NUM_LIT> ] ; rtx addis_value = operands [ <NUM_LIT> ] ; rtx target = operands [ <NUM_LIT> ] ; rtx orig_mem = operands [ <NUM_LIT> ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == FLOAT_EXTEND || GET_CODE ( orig_mem ) == ZERO_EXTEND ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , <NUM_LIT> ) ; target_mode = GET_MODE ( orig_mem


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) , <NUM_LIT> ) ; return <ISA_LIT>TargetLowering :: getNumRegisters (


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > (


<s> } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; assert ( ( MI . getNumDefs ( ) == <NUM_LIT> && MI . defs ( ) . begin ( ) -> isReg ( ) ) && <STR_LIT> ) ; Register DefReg = MI . defs ( ) . begin ( ) -> getReg ( ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isUse ( ) || MO . getReg ( ) != DefReg ) continue ; if ( auto * OpDef = RDA . getMIOperand ( & MI , MO ) ) { if ( KnownFalseZeros . count ( OpDef ) ) { KnownFalseZeros . insert ( & MI ) ; break ; } } } if ( ! KnownFalseZeros . count ( & MI ) ) UnknownFalseLanes . insert ( & MI ) ; } auto HasKnownUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Knowns ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Knowns . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( UnknownFalseLanes ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasKnownUsers ( MI


<s> while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ++ MII ; NumNOPBytes -=


<s> for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) , OverrideNEON ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) &&


<s> static bool FoldMaskAndShiftToExtract ( SelectionDAG & DAG , SDValue N , uint64_t Mask , SDValue Shift , SDValue X , <ISA_LIT>ISelAddressMode & AM ) { if ( Shift . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) || ! Shift . hasOneUse ( ) ) return true ; int ScaleLog = <NUM_LIT> - Shift . getConstantOperandVal ( <NUM_LIT> ) ; if ( ScaleLog <= <NUM_LIT> || ScaleLog >= <NUM_LIT> || Mask != ( <NUM_LIT> << ScaleLog ) ) return true ; EVT VT = N . getValueType ( ) ; DebugLoc DL = N . getDebugLoc ( ) ; SDValue Eight = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue NewMask = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , VT , X , Eight ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Srl , NewMask ) ; SDValue ShlCount = DAG . getConstant ( ScaleLog , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , And , ShlCount ) ; InsertDAGNode ( DAG , N , Eight ) ; InsertDAGNode ( DAG , N , Srl


<s> TargetRegistry :: RegisterDCTranslator ( getThe<ISA_LIT>_64Target


<s> break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode = <STR_LIT> ; LongFormBits = <NUM_LIT> ; LongFormScale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; unsigned LongFormMaxOffs = ( ( <NUM_LIT> << LongFormBits ) - <NUM_LIT> )


<s> bool isMemOffs16 ( ) const { return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT>

&& ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; return true ; } if ( isPostIncrementForm ( MI , AddOffset ) ) { OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << decIncOperator ( MI ) << <STR_LIT> ; return true ; } return


<s> return MFI -> getStackSize ( ) && needsFP (


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { Addr . setGlobalValue ( GV ) ; return true ; } return false


<s> SDValue V1_HI = extract128BitVector ( V1 , NumElts / <NUM_LIT> , DAG , DL ) ; MVT NewVT = V0_LO . getSimpleValueType ( ) ; SDValue LO = DAG . getUNDEF ( NewVT ) ; SDValue HI = DAG . getUNDEF ( NewVT ) ; if ( Mode ) { if ( ! isUndefLO && ! V0 -> isUndef ( ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V0_HI ) ; if ( ! isUndefHI && ! V1 -> isUndef ( ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V1_LO , V1_HI ) ; } else { if ( ! isUndefLO && ( ! V0_LO -> isUndef ( ) || ! V1_LO -> isUndef ( ) ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V1_LO ) ; if ( ! isUndefHI && ( ! V0_HI -> isUndef ( ) || ! V1_HI -> isUndef ( ) ) ) HI = DAG

. getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_HI , V1_HI ) ;


<s> if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return


<s> unsigned <ISA_LIT>AsmParser :: matchRegisterNameAlias ( StringRef Name , bool isVector ) { unsigned RegNum = isVector ? matchVectorRegName ( Name ) : MatchRegisterName ( Name ) ; RegKind Kind = isVector ? RegKind :: NeonVector : RegKind ::


<s> } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT>


<s> if ( ! const_vector_equal_evenodd_p ( orig_op1 ) ) op1 = expand_binop ( wmode , lshr_optab , gen_lowpart ( wmode , op1 ) , x , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; if ( ! const_vector_equal_evenodd_p ( orig_op2 ) ) op2 = expand_binop ( wmode , lshr_optab , gen_lowpart ( wmode , op2 ) , x , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; op1 = gen_lowpart ( mode , op1 ) ; op2 = gen_lowpart ( mode , op2 ) ; } if ( mode == V16SImode ) { if ( uns_p ) x = gen_vec_widen_umult_even_v16si ( dest , op1 , op2 ) ; else x = gen_vec_widen_smult_even_v16si ( dest , op1 , op2 ) ; } else if ( mode == V8SImode ) { if ( uns_p ) x = gen_vec_widen_umult_even_v8si ( dest , op1 , op2 ) ; else x = gen_vec_widen_smult_even_v8si ( dest , op1 , op2 ) ; } else if ( uns_p ) x = gen_vec_widen_umult_even_v4si ( dest , op1 , op2 ) ; else if ( TARGET_SSE4_1 ) x = gen_sse4_1_mulv2siv2di3 ( dest , op1 , op2 ) ; else { rtx s1 , s2 , t0 , t1 , t2 ; s1 = ix86_expand_sse_cmp ( gen_reg_rtx ( mode ) , GT , CONST0_RTX ( mode ) , op1 , pc_rtx


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSysReg ( OperandVector & Operands ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , false , S , getLoc ( ) , Ctx ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * ImmVal ; if ( Parser . parseExpression ( ImmVal ) || ! isa < MCConstantExpr > ( ImmVal ) || cast < MCConstantExpr > ( ImmVal ) -> getValue ( ) != <NUM_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , false , S , getLoc ( )


<s> EVT VT = LHS . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; unsigned Opcode = <STR_LIT> ; if ( RHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) == <NUM_LIT> && ! isUnsignedIntSetCC ( CC ) ) { Opcode =


<s> int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( isShiftedInt < <NUM_LIT> , Shift > ( RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout


<s> SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , P ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT VT = Ld -> getValueType ( <NUM_LIT> ) ; if ( ! Ld -> isVolatile ( ) && ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! XTLI -> getSubtarget ( ) -> is64Bit ( ) && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { SDValue FILDChain = XTLI -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , Ld -> getValueType ( <NUM_LIT> ) , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue (


<s>
bool
<ISA_LIT>AsmParser
::
MatchAndEmitATTInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
assert
(
!
Operands
.
empty
(
)
&&
<STR_LIT>
)
;
<ISA_LIT>Operand
&
Op
=
static_cast
<
<ISA_LIT>Operand
&
>
(
*
Operands
[
<NUM_LIT>
]
)
;
assert
(
Op
.
isToken
(
)
&&
<STR_LIT>
)
;
SMRange
EmptyRange
=
;
MatchFPUWaitAlias
(
IDLoc
,
Op
,
Operands
,
Out
,
MatchingInlineAsm
)
;
bool
WasOriginallyInvalidOperand
=
false
;
MCInst
Inst
;
switch
(
MatchInstruction
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
Match_Success
:
if
(
!
MatchingInlineAsm
)
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
ErrorInfo
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
uint64_t
ErrorInfoMissingFeature
=
<NUM_LIT>
;
unsigned
Match
[
<NUM_LIT>
]
;
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
Match
[
I
]
=
MatchInstruction
(
Operands
,
Inst
,
ErrorInfoIgnore
,
MatchingInlineAsm
,
isParsingIntelSyntax
(


<s> SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; if ( Opcode != <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( <NUM_LIT> - BitSize , WideVT ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( uint32_t ( - <NUM_LIT> ) >> BitSize , WideVT ) ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , Src2 , BitShift , NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( Opcode , DL , VTList , Ops , array_lengthof ( Ops ) , NarrowVT , MMO ) ; SDValue ResultShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ,

DAG . getConstant ( BitSize , WideVT ) ) ;


<s> unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; } } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> static SDValue performST1Combine ( SDNode * N , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Data = N -> getOperand ( <NUM_LIT> ) ; EVT DataVT = Data . getValueType ( ) ; EVT HwSrcVt = getSVEContainerType ( DataVT ) ; SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue


<s> } else { SDValue ShiftValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewRM , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , ShiftValue ) ; RMBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shifted , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } CWD = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , RMBits ) ; Chain = DAG . getStore ( Chain , DL , CWD , StackSlot , MPI , <NUM_LIT> ) ; SDValue OpsLD [ ] = { Chain , StackSlot } ; MachineMemOperand * MMOL = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , OpsLD , <STR_LIT> , MMOL ) ; if ( Subtarget . hasSSE1 ( ) ) { Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , StackSlot ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL ,


<s> bool isTargetLinux ( ) const { return TargetTriple . getOS ( )


<s> return ELF :: R_<ISA_LIT>_PREL31 ; } case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_PLT : return ELF :: R_<ISA_LIT>_CALL ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_CALL ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ELF :: R_<ISA_LIT>_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP11 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP8 ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_THM_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_THM_CALL ; } case <STR_LIT> : case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_PC8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_ALU_PREL_11_0 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_PC12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF18 ; } } switch ( Fixup . getTargetKind ( ) ) { default : Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_NONE : return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr ::


<s> return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( low [ <NUM_LIT> ] == const0_rtx ) pattern = <NUM_LIT> , carry = <NUM_LIT> ; else if ( low [ <NUM_LIT> ] == constm1_rtx ) pattern = <STR_LIT> ; else pattern = <STR_LIT> ; } else { if ( low [ <NUM_LIT> ] == constm1_rtx ) pattern = <STR_LIT> ; else if ( low [ <NUM_LIT> ] == const0_rtx ) pattern = get_insn_template ( CODE_FOR_movsi , insn ) , carry = <NUM_LIT> ; else pattern = <STR_LIT> ; } if ( pattern ) output_asm_insn ( pattern , low ) ; if ( carry ) { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; return <STR_LIT> ; } return get_insn_template ( CODE_FOR_subsi3 , insn ) ; } default : gcc_unreachable ( )


<s> return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseArithmeticLogic (

) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ;


<s> void nds32_split_ashiftrtdi3 ( rtx dst , rtx src ,


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand (


<s> getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s8 } , { s8 , s16 , s32 , s64 , p0 } ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s8 } , { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s8 ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 , s64 } )

. clampScalar ( <NUM_LIT> , s8 , s64 ) ;


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++


<s> bool isValidForTie ( const <ISA_LIT>Operand & Other ) const { if ( Kind != Other . Kind ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case k_RegisterIndex :


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget


<s> SDLoc DL ( Op ) ; Result = DAG . getNode ( getGlobalWrapperKind ( ) , DL , PtrVT , Result ) ; if ( isPositionIndependent ( ) && ! Subtarget . is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return


<s> static DecodeStatus DecodeDSPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPR32RegisterClass ( Inst , RegNo , Address


<s> bool <ISA_LIT>InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != <NUM_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && <STR_LIT> . hasSubClassEq ( RC ) ) || <STR_LIT> . hasSubClassEq

( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << '#' << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT>


<s> static DecodeStatus decodeCondBrTarget ( MCInst & Inst , unsigned Imm , uint64_t , const void * ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Imm ) ) ) ; return MCDisassembler ::


<s> bool useNEONForSinglePrecisionFP ( ) const { return hasNEON (


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val > - <NUM_LIT>


<s> return ( __m128 ) __builtin_ia32_unpcklps ( ( __v4sf ) __A , (


_mm512_setzero_ps ( ) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) { SDValue BAHi = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALo = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getBlockAddress ( BA , ValTy , true , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , BAGOTOffset ) ; SDValue BALOOffset = DAG . getBlockAddress ( BA , ValTy , true , OFSTFlag ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , BAGOTOffset , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , ValTy , BALOOffset ) ; return DAG . getNode ( <STR_LIT> , dl , ValTy ,


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) ||

thumb_far_jump_used_p ( ) || regs_ever_live [ LR_REGNUM ] ) ;


<s> static unsigned encodeVFPRn ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary =


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc , <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension


<s> bool isRegSeqV2 ( ) const { return isRegSeqTemplate < <STR_LIT> , <STR_LIT>


<s> SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT>


<s> int <ISA_LIT>FrameInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg ,


<s> return ( unsigned int ) __builtin_ia32_kmovd ( ( __mmask32 )


<s> void x86_elf_aligned_common ( FILE * file , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fputs ( <STR_LIT> , file ) ; else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file


<s> bool SelectAddrIdxOnly ( SDNode * Op , SDValue N


<s> if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ; else if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; return false


<s> MCObjectWriter * create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter (


<s> for ( MachineBasicBlock * S : MBB -> successors ( ) ) if ( S != Succ ) return S ; llvm_unreachable (


<s> int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { assert ( isUndefOrZero ( M ) && <STR_LIT> ) ; if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ; if ( SM_SentinelZero == M ) KnownZero . setBit ( i ) ; continue ; } unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) KnownUndef . setBit ( i ) ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) KnownZero . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; int NumVecElts = Vec . getValueType ( ) . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) && Size == NumVecElts ) { int Idx = V . getConstantOperandVal (


<s> SelectionDAG & DAG = DCI . DAG ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( ( N0 . getValueType ( ) == <STR_LIT> || N0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) return SDValue ( ) ; int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , NumMaskElts ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; if ( CCVT . getSizeInBits ( ) != ResVT . getSizeInBits ( ) ) return SDValue ( ) ; assert ( DCI . isBeforeLegalize ( ) || DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > DUPMask ( CCVT . getVectorNumElements ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getVectorShuffle ( CCVT , DL , SetCC , SetCC , DUPMask . data ( ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , ResVT . changeVectorElementTypeToInteger (


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( )


<s> return ( __m512i ) __builtin_ia32_pbroadcastd512_gpr_mask ( __A , ( __v16si ) _mm512_undefined_si512 ( ) , ( __mmask16 ) ( -


<s> static SetOfMachineInstr & getSet ( BlockToSetOfInstrsPerColor & sets , const MachineBasicBlock & MBB , unsigned reg , unsigned nbRegs ) { SetOfMachineInstr * result ; BlockToSetOfInstrsPerColor :: iterator it = sets . find ( & MBB ) ; if ( it != sets . end ( ) ) result = it -> second ; else result = sets [ & MBB ] = new


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign )

|| F -> hasFnAttr ( Attribute :: StackAlignment ) ) ;


<s> unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned MaxScale = <NUM_LIT> / EltSizeInBits ; for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale += Scale ) { unsigned NumSrcElts = NumElts / Scale ; unsigned UpperElts = NumElts - NumSrcElts ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , NumSrcElts , <NUM_LIT> , Scale ) || ! Zeroable . extractBits ( UpperElts , NumSrcElts ) . isAllOnesValue ( ) ) continue ; SDValue Src = V1 ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; Src = peekThroughOneUseBitcasts ( Src ) ; if ( Src . getOpcode ( ) != <STR_LIT> || Src . getScalarValueSizeInBits ( ) != ( EltSizeInBits * Scale ) ) return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; bool UndefUppers = isUndefInRange ( Mask , NumSrcElts , UpperElts ) ; return getAVX512TruncNode ( DL , VT , Src , Subtarget , DAG , ! UndefUppers ) ; } return SDValue ( )


<s> auto StatusOrErr = RealVal . convertFromString ( Tok . getString ( ) , APFloat :: rmTowardZero ) ; if ( errorToBool ( StatusOrErr . takeError ( ) ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isNegative ) RealVal . changeSign ( ) ; if ( AddFPZeroAsLiteral && RealVal . isPosZero ( ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; } else Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( RealVal , * StatusOrErr == APFloat :: opOK , S , getContext ( ) ) ) ; } Parser . Lex ( ) ; return


<s> constexpr int SET_TO_ZERO = <NUM_LIT> ; constexpr int PAC = <NUM_LIT> ; constexpr int EOR = <NUM_LIT> ; constexpr int RESET_TO_ZERO = <NUM_LIT> ; auto state = SET_TO_ZERO ; for ( auto MBBI = MBB . begin ( ) , end = MBB . end ( ) ; MBBI != end ; ++ MBBI ) { if ( nullptr != MBBI -> findRegisterUseOperand ( PACStack :: maskReg ) || nullptr != MBBI -> findRegisterDefOperand ( PACStack :: maskReg ) ) { switch ( state ) { case SET_TO_ZERO : assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == PACStack :: maskReg && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; ++ state ; break ; case PAC : assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; ++ state ; break ; case EOR : assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; ++ state ; break ; case RESET_TO_ZERO : assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == PACStack :: maskReg && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand (


<s> unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: ZPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: PPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; assert ( ( ! NeedsWinCFI || ! ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn


<s> switch ( RelTy ) { case R_386_PC32 : return Modifier - <NUM_LIT> ; case R_386_32 : return Modifier ; default : llvm_unreachable ( <STR_LIT> ) ; } } return


<s> GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( RC == <STR_LIT> ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( RC == <STR_LIT> ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { } else if ( RC == <STR_LIT> ) { HasVRSAVESaveArea = true ; } else if ( RC == <STR_LIT> ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( PerformTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - getRegisterNumbering ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset (


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( ) { AsmTransCBE = arm_asm_table ; Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ; return ( ( qword ) ( dd . v


<s> void addImm8s4Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> )


<s> if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) .


<s> return ( __m128d ) __builtin_ia32_extractf64x2_512_mask ( ( __v8df ) __A , __imm , (

__v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> int64_t AbiVersion ; if ( check ( getParser ( ) . parseAbsoluteExpression ( AbiVersion ) , L , <STR_LIT> ) ||

parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ;


<s> subreg = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( subreg , gen_rtx_ABS ( vmode , src ) ) , insn ) ; src = subreg ; } else convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_move_insn ( subreg , CONST0_RTX ( vmode ) ) , insn ) ; src = gen_rtx_MINUS ( vmode , subreg , src ) ; break ; case NOT : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_move_insn ( subreg , CONSTM1_RTX ( vmode ) ) , insn ) ; src = gen_rtx_XOR ( vmode , src , subreg ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == vmode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; gcc_assert ( REG_P ( src ) && GET_MODE ( src ) == DImode ) ; subreg = gen_rtx_SUBREG ( V2DImode , src , <NUM_LIT> ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) ) , insn ) ; dst = gen_rtx_REG ( CCmode , FLAGS_REG ) ; src = gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) ) , UNSPEC_PTEST ) ; break ; case CONST_INT : convert_op ( & src , insn ) ; break ; default : gcc_unreachable ( ) ; } SET_SRC ( def_set ) = src ; SET_DEST ( def_set ) = dst ; PATTERN ( insn ) = def_set ; INSN_CODE ( insn ) = - <NUM_LIT> ; int patt = recog_memoized


<s> else if ( GEPElemSize == <NUM_LIT> ) return <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) <<


<s> Inst . addOperand ( MCOperand :: CreateReg ( getCOP2Reg


<s> void <ISA_LIT>ALFWriter :: initFrames ( ) { b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ,


<s> if ( post_update_insn_p ( producer ) ) return false ; rtx last_def_reg = extract_nth_access_reg ( producer


<s> type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != <NUM_LIT> || ix86_preferred_stack_boundary >= <NUM_LIT> ) return align ; if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ( ! TYPE_USER_ALIGN ( type ) && ! TYPE_ATOMIC ( strip_array_types ( type ) ) ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) { gcc_checking_assert ( ! TARGET_STV ) ; return


<s> } SDValue HOp = N -> getOperand ( <NUM_LIT> ) ; if ( HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && HOp . getOperand ( <NUM_LIT> ) != HOp . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( HOp . getScalarValueSizeInBits ( ) == <NUM_LIT> ) { assert ( ( HOp . getValueType ( ) == <STR_LIT> || HOp . getValueType ( ) == <STR_LIT> ) && HOp . getValueType ( ) == VT && <STR_LIT> ) ; return HOp


<s> for ( I = <NUM_LIT> ; I > <NUM_LIT> ; I -- ) if ( Opcode & ( <NUM_LIT>


<s> break ; case DIV : case MOD : if ( FLOAT_MODE_P ( mode ) ) { * total = mode == DFmode ? rs6000_cost -> ddiv : rs6000_cost -> sdiv ; return false ; } case UDIV : case UMOD : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && exact_log2 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) >= <NUM_LIT> ) { if ( code == DIV || code == MOD ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { if ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == DImode ) * total = rs6000_cost -> divdi ; else * total = rs6000_cost -> divsi ; } if ( code == MOD || code == UMOD ) * total += COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case CTZ : case FFS : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case POPCOUNT : * total = COSTS_N_INSNS ( TARGET_POPCNTD ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case PARITY : * total = COSTS_N_INSNS ( TARGET_CMPB ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case NOT : if ( outer_code == AND || outer_code == IOR || outer_code == XOR ) { * total = <NUM_LIT> ; return false ; } case AND : case CLZ : case IOR : case XOR : case ZERO_EXTRACT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATE : case ROTATERT : if ( outer_code == TRUNCATE && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) { if ( mode == DImode ) * total = rs6000_cost -> muldi ; else * total = rs6000_cost -> mulsi ; return true ; } else if ( outer_code == AND ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SIGN_EXTEND : case ZERO_EXTEND : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MEM ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case COMPARE : case NEG : case ABS : if ( ! FLOAT_MODE_P ( mode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case FLOAT : case UNSIGNED_FLOAT : case FIX : case UNSIGNED_FIX : case FLOAT_TRUNCATE : * total = rs6000_cost -> fp ; return false ; case FLOAT_EXTEND : if ( mode == DFmode ) * total = rs6000_cost -> sfdf_convert ; else * total = rs6000_cost -> fp ; return false ; case


<s> return __builtin_mve_vshrq_n_sv16qi ( __a ,


<s> if ( CPEOffset < UserOffset ) UserOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return OffsetIsInRange ( UserOffset , CPEOffset , MaxDisp , U .


<s> static std :: string computeDataLayout ( ) { return <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT>


<s> unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField * <NUM_LIT> ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField ) *


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget -> hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41


<s> vld4_s8 ( const int8_t * __a ) { int8x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; return


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoDsp ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNoDsp


<s> else Op -> Mem . Offset . Value = Offset ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( StackOffsetVal < <NUM_LIT> ) { Warning ( Loc , <STR_LIT> ) ; IsCpRestoreSet = false ; } else { IsCpRestoreSet = true ; CpRestoreOffset = StackOffsetVal ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( )


<s> EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT FixedWidenedVT = HalfVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; EVT ScalableWidenedVT = getContainerForFixedLengthVector ( DAG , FixedWidenedVT ) ; EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Div ) ; } SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op1 ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi ,


<s> return ( __m256i ) __builtin_ia32_vcvtph2uw256_mask ( __A , ( __v16hi ) _mm256_setzero_si256 ( ) ,


<s> return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB . getReg ( <NUM_LIT> ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsDwarfCFI = ! IsWin64Prologue && MF . needsFrameMoves ( ) ; bool EmitCFI = ! TFL -> hasFP ( MF ) && NeedsDwarfCFI ; if ( EmitCFI ) { TFL -> BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , StackAdjustment ) ) ; TFL -> BuildCFI ( MBB , std :: next ( I ) , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr ,


<s> bool pru_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno )


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo (


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get (


<s> static void ia64_asm_unwind_emit ( FILE * out_file , rtx_insn * insn ) { bool unwind = ia64_except_unwind_info ( & global_options ) == UI_TARGET ; bool frame = dwarf2out_do_frame ( ) ; rtx note , pat ; bool handled_one ; if ( ! unwind && ! frame ) return ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) { last_block = NOTE_BASIC_BLOCK ( insn ) -> next_bb == EXIT_BLOCK_PTR_FOR_FN ( cfun ) ; if ( need_copy_state ) { if ( unwind ) { fprintf ( out_file , <STR_LIT> ) ; fprintf ( out_file , <STR_LIT> , cfun -> machine -> state_num ) ; } need_copy_state = false ; } } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( INSN_CODE ( insn ) == CODE_FOR_alloc ) { rtx dest = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int dest_regno = REGNO ( dest ) ; if ( dest_regno == current_frame_info . r [ reg_save_ar_pfs ] ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; } else { if ( current_frame_info . total_size == <NUM_LIT> && ! frame_pointer_needed ) process_epilogue ( out_file , insn , unwind , frame ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> ) ; } return ; } handled_one = false ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) switch ( REG_NOTE_KIND ( note ) ) { case REG_CFA_ADJUST_CFA : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_adjust_cfa ( out_file , pat , insn , unwind , frame ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_offset ( out_file , pat , unwind ) ; handled_one = true ; break ; case REG_CFA_REGISTER : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_register ( out_file ,


<s> if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return false ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc =


<s> Register RegHi = TRI -> getSubReg ( Reg . getReg ( ) , <STR_LIT> ) ; MIB . addReg ( RegLo , Flags ) ; MIB . addReg ( RegHi ,


<s> void \ sbss_section ( ) \ { \ if ( in_section != in_sbss ) \ { \ in_section

= in_sbss ; \ fprintf ( asm_out_file , <STR_LIT> , SBSS_SECTION_ASM_OP ) ; \ } \ }


<s> FunctionPass * llvm :: create<ISA_LIT>BranchExpansion ( ) { return new <ISA_LIT>BranchExpansion ( )


<s> if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> SDValue Other = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Sel ) ; if ( isOneConstant ( Other ) && isOverflowIntrOpRes ( Sel ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Sel -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > (


<s> EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == ( ( <NUM_LIT> << ( SplatSize * <NUM_LIT> ) ) - <NUM_LIT> ) ) { SplatSize = <NUM_LIT> ; Val = <NUM_LIT> ; } EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT>


<s> PersonalityIndex = <STR_LIT> :: NUM_PERSONALITY_INDEX ; size_t TotalSize = Ops . size ( ) + <NUM_LIT> ; size_t RoundUpSize = ( TotalSize + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> ; Result . resize ( RoundUpSize ) ; OpStreamer . EmitSize ( RoundUpSize ) ; } else { if ( PersonalityIndex == <STR_LIT> :: NUM_PERSONALITY_INDEX ) PersonalityIndex = ( Ops . size ( ) <= <NUM_LIT> ) ? <STR_LIT> :: AEABI_UNWIND_CPP_PR0 : <STR_LIT> :: AEABI_UNWIND_CPP_PR1 ; if ( PersonalityIndex == <STR_LIT>


<s> unsigned VF = VecTy -> getVectorNumElements ( ) / Factor ; Type * ScalarTy = VecTy -> getVectorElementType ( ) ; unsigned VecTySize = DL . getTypeStoreSize ( VecTy ) ; unsigned LegalVTSize = LegalVT . getStoreSize ( ) ; unsigned NumOfMemOps = ( VecTySize + LegalVTSize - <NUM_LIT> ) / LegalVTSize ; Type * SingleMemOpTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( CPU . empty (


<s> return __builtin_aarch64_lrounddfdi ( __a )


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break


<s> assert ( VecTy == Src0 -> getType ( ) && VecTy == Src1 -> getType ( ) ) ; unsigned NumElt = VecTy -> getVectorNumElements ( ) ; Value * Res = UndefValue :: get ( VecTy ) ; Value * Srcs [ <NUM_LIT> ] = { Src0 , Src1 } ; for ( int opi = <NUM_LIT> , ope = <NUM_LIT> ; opi != ope ; ++ opi ) { for ( int i = <NUM_LIT> , e = NumElt / <NUM_LIT> ; i


<s> int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { auto * NewMaskTy = FixedVectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , <NUM_LIT> , MaskTy ) ; } if ( ! ST -> hasAVX512 ( ) ) return Cost + LT . first * ( IsLoad ? <NUM_LIT> : <NUM_LIT> ) ; return Cost +


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT>

) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isJumpTableBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true


<s> int CCValid = CCValidOp -> getZExtValue ( ) ; int CCMask = CCMaskOp -> getZExtValue ( ) ; SDLoc DL ( Node ) ; SDValue CCReg = Node -> getOperand ( <NUM_LIT> ) ; IPMConversion IPM = getIPMConversion ( CCValid , CCMask ) ; SDValue Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , CCReg ) ; if ( IPM . XORValue ) Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . XORValue , DL , <STR_LIT> ) ) ; if ( IPM . AddValue ) Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . AddValue , DL , <STR_LIT> ) ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && IPM . Bit == <NUM_LIT> ) { unsigned ShiftOp = TrueOp -> getSExtValue ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Result = CurDAG -> getNode ( ShiftOp , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . Bit , DL , <STR_LIT> ) ) ; } else


<s> assert ( <ISA_LIT>Adj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) { MI . getOperand ( i ) . ChangeToRegister (


<s> static SDValue LowerATOMIC_LOAD_STORE ( SDValue Op , SelectionDAG


<s> void <ISA_LIT>SpeculationHardening :: insertSPToRegTaintPropagation ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { if ( UseControlFlowSpeculationBarrier ) { insertFullSpeculationBarrier ( MBB , MBBI , DebugLoc ( ) ) ; return ; } BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse (

<STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> rtx low_reg = NULL_RTX ; rtx hi_reg = NULL_RTX ; if ( ! src_aligned || ! dst_aligned ) { low_reg = gen_lowpart ( SImode , reg0 ) ; hi_reg = gen_highpart_mode ( SImode , DImode , reg0 ) ; } if ( MEM_ALIGN ( src ) >= <NUM_LIT> * BITS_PER_WORD ) emit_move_insn ( reg0 , src ) ; else if ( src_aligned ) emit_insn ( gen_unaligned_loaddi ( reg0 , src ) ) ; else { emit_insn ( gen_unaligned_loadsi ( low_reg , src ) ) ; src = next_consecutive_mem ( src ) ; emit_insn ( gen_unaligned_loadsi ( hi_reg , src ) ) ; } if ( MEM_ALIGN ( dst ) >= <NUM_LIT> * BITS_PER_WORD ) emit_move_insn ( dst , reg0 ) ; else if ( dst_aligned ) emit_insn ( gen_unaligned_storedi ( dst , reg0 ) ) ; else { emit_insn ( gen_unaligned_storesi ( dst , low_reg ) ) ; dst = next_consecutive_mem ( dst ) ; emit_insn ( gen_unaligned_storesi ( dst , hi_reg ) ) ; } src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; } gcc_assert ( len < <NUM_LIT> ) ; if ( len >= <NUM_LIT> ) { reg0 = gen_reg_rtx ( SImode ) ; src = adjust_address ( src , SImode , <NUM_LIT> ) ; dst = adjust_address ( dst , SImode , <NUM_LIT> ) ; if ( src_aligned ) emit_move_insn ( reg0 , src ) ; else emit_insn ( gen_unaligned_loadsi ( reg0 , src ) ) ; if ( dst_aligned ) emit_move_insn ( dst , reg0 ) ; else emit_insn ( gen_unaligned_storesi ( dst , reg0 ) ) ; src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; len -=


<s> return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitCOPY_FW ( MI , BB ) ; case <STR_LIT> : return emitCOPY_FD ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FW ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FD ( MI , BB ) ; case <STR_LIT>


<s> UC . recordHandlerData ( L ) ; if ( ! UC . hasFnStart ( ) ) return Error ( L , <STR_LIT> ) ; if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return true ; } getTargetStreamer ( ) . emitHandlerData ( ) ; return false


<s> bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ;


<s> SDValue <ISA_LIT>TargetLowering :: duplicateCmp ( SDValue Cmp , SelectionDAG & DAG ) const { unsigned Opc = Cmp . getOpcode ( ) ; SDLoc DL ( Cmp ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return DAG . getNode ( Opc , DL , <STR_LIT> , Cmp . getOperand ( <NUM_LIT> ) , Cmp . getOperand ( <NUM_LIT> ) ) ; assert ( Opc == <STR_LIT> && <STR_LIT> ) ; Cmp = Cmp . getOperand ( <NUM_LIT> ) ; Opc = Cmp . getOpcode ( )


<s> bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ; if ( ! RHSTrunc && ! <STR_LIT> ( N1 . getNode ( ) ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , VT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT> ) ; if ( RHSTrunc ) N1 = N1 -> getOperand ( <NUM_LIT> ) ; else N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , VT , N0 , N1 ) ; unsigned Opcode = N ->


<s> printOperand ( MI , Op , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm (


<s> static <ISA_LIT>Operand * CreateToken ( StringRef Str , bool IsSuffix , SMLoc S , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token , Ctx ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size (


<s> bool i386_pe_type_dllexport_p ( tree


<s> const MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( <STR_LIT> ) ; MachineRegisterInfo & MRI = MBB -> getParent ( )


<s> emitCodeAlignment ( <NUM_LIT> , & STI , <NUM_LIT> ) ; MCXCOFFStreamer :: emitInstruction ( Inst ,


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) return true ; if ( Ty == <STR_LIT> ) { if ( cast < LoadSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getMemoryVT ( ) == <STR_LIT> ) { if ( <STR_LIT> ( InputNode ) ) Opcode = <STR_LIT> ; if ( <STR_LIT> ( InputNode ) ) Opcode = <STR_LIT> ; } return true


<s> static bool hasMFENCE ( const <ISA_LIT>Subtarget & Subtarget ) { return Subtarget . hasSSE2 ( ) ||


<s> InstrInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > instrs ; std :: set < MachineBasicBlock * > bbs ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) ) { instrs . push_back ( & MI ) ; bbs . insert ( & MBB ) ; } if ( instrs . empty ( ) ) return false ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( auto * MI : instrs ) { Register tag_before = RI . createVirtualRegister ( & <STR_LIT> ) ; Register tag_after = RI . createVirtualRegister ( & <STR_LIT> ) ; auto & MBB = * MI -> getParent ( ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addDef ( tag_before ) . addUse ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineBasicBlock :: iterator after = BuildMI ( * MI -> getParent ( ) , ++ MachineBasicBlock :: iterator ( MI ) , MI -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addDef ( tag_after ) . addUse ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . getInstr ( ) ; auto Sink = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . insert ( ++ MachineFunction :: iterator ( MBB ) , Sink ) ; Sink -> splice ( Sink -> begin ( ) , & MBB , std :: next ( after ) , MBB . end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( Sink ) ; assert ( Sink -> getParent ( ) == & MF ) ; after = BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addUse ( tag_after , RegState :: Kill ) . addUse ( tag_before , RegState :: Kill ) . addMBB ( Sink ) ; BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) ; } return


<s> if ( Subtarget . isTarget64BitILP32 ( ) ) FrameReg = get<ISA_LIT>SubSuperRegister ( FrameReg , <NUM_LIT> ) ; return FrameReg


<s> std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } else if ( CTVal && CFVal && CTVal -> isOne ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( TVal . getOperand ( <NUM_LIT> ) ) ; if ( CVal && CVal -> isAllOnesValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( TVal . getOperand ( <NUM_LIT> ) ) ; if ( CVal && CVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( CTVal && CFVal ) { const int64_t TrueVal = CTVal -> getSExtValue ( ) ; const int64_t FalseVal = CFVal -> getSExtValue ( ) ; bool Swap = false ; if ( TrueVal == ~ FalseVal ) { Opcode = <STR_LIT> ; } else if ( TrueVal == - FalseVal ) { Opcode = <STR_LIT> ; } else if ( TVal . getValueType ( ) == <STR_LIT> ) { const uint32_t TrueVal32 = CTVal -> getZExtValue ( ) ; const uint32_t FalseVal32 = CFVal -> getZExtValue ( ) ; if ( ( TrueVal32 == FalseVal32 + <NUM_LIT> ) || ( TrueVal32 + <NUM_LIT> == FalseVal32 ) ) { Opcode = <STR_LIT> ; if ( TrueVal32 > FalseVal32 ) { Swap = true ; } } } else if ( ( TrueVal == FalseVal + <NUM_LIT> ) || ( TrueVal + <NUM_LIT> == FalseVal ) ) { Opcode = <STR_LIT> ; if ( TrueVal > FalseVal ) { Swap = true ; } } if ( Swap ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } if ( Opcode != <STR_LIT> ) { FVal = TVal ; } } SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; EVT VT = Op . getValueType ( ) ; return DAG . getNode ( Opcode , dl , VT , TVal , FVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; assert ( LHS . getValueType ( ) == RHS .


<s> Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } } Locs . clear ( ) ; SmallVector < int , <NUM_LIT> > LoMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > HiMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > * MaskPtr = & LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = & HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; ( * MaskPtr ) [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; ( * MaskPtr ) [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > MaskOps ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( Locs [ i ] . first == - <NUM_LIT> ) { MaskOps . push_back ( - <NUM_LIT> ) ; }


<s> EXECUTE_IF_SET_IN_BITMAP ( defs , <NUM_LIT> , id , bi ) convert_reg ( id ) ; EXECUTE_IF_AND_COMPL_IN_BITMAP ( defs_conv , defs , <NUM_LIT> , id , bi ) make_vector_copies ( id ) ; EXECUTE_IF_SET_IN_BITMAP ( insns , <NUM_LIT> , id , bi ) { convert_insn ( DF_INSN_UID_GET ( id ) -> insn ) ; converted_insns ++ ; } return converted_insns


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; while ( X . getValueType ( ) != VT && X -> getOpcode ( ) == <STR_LIT> ) X = X -> getOperand ( <NUM_LIT> ) ; if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> )


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName != <STR_LIT> && ShiftName != <STR_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( !


<s> IterTy CurrI = I ; ++ I ; if ( CurrI -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * CurrI ) ) break ; assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; if ( IsReverseIter && I != End ) I = CurrI ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler =


<s> const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_NoMatch ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = <STR_LIT> ; } else if ( el_mode == SFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = <STR_LIT> ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = <NUM_LIT> ; DECL_EXTERNAL ( new_fndecl ) = <NUM_LIT> ; DECL_IS_NOVOPS ( new_fndecl ) = <NUM_LIT>


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr


<s> ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , ST . use<ISA_LIT>PostRASchedStrategy ( ) ? llvm :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C ) : llvm :: make_unique < PostGenericScheduler > (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> case ELF :: R_MIPS_TLS_TPREL64 : case ELF :: R_MIPS_TLS_TPREL_HI16 : case ELF :: R_MIPS_TLS_TPREL_LO16 : case ELF :: R_MIPS_GLOB_DAT : case ELF :: R_MIPS_PC21_S2 : case ELF :: R_MIPS_PC26_S2 : case ELF :: R_MIPS_PC18_S3 : case ELF :: R_MIPS_PC19_S2 : case ELF :: R_MIPS_PCHI16 : case ELF :: R_MIPS_PCLO16 : case ELF :: R_MIPS_COPY : case ELF :: R_MIPS_JUMP_SLOT : case ELF :: R_MIPS_NUM : case ELF :: R_MIPS_PC32 : case ELF :: R_MIPS_EH : case ELF :: R_MICROMIPS_26_S1 : case ELF :: R_MICROMIPS_GPREL16 : case ELF :: R_MICROMIPS_LITERAL : case ELF :: R_MICROMIPS_PC7_S1 : case ELF :: R_MICROMIPS_PC10_S1 : case ELF :: R_MICROMIPS_PC16_S1 : case ELF :: R_MICROMIPS_CALL16 : case ELF :: R_MICROMIPS_GOT_DISP : case ELF :: R_MICROMIPS_GOT_HI16 : case ELF :: R_MICROMIPS_GOT_LO16 : case ELF :: R_MICROMIPS_SUB : case ELF :: R_MICROMIPS_HIGHER : case ELF :: R_MICROMIPS_HIGHEST : case ELF :: R_MICROMIPS_CALL_HI16 : case ELF :: R_MICROMIPS_CALL_LO16 : case ELF :: R_MICROMIPS_SCN_DISP : case ELF :: R_MICROMIPS_JALR : case ELF :: R_MICROMIPS_HI0_LO16 : case ELF :: R_MICROMIPS_TLS_GD : case ELF :: R_MICROMIPS_TLS_LDM : case ELF :: R_MICROMIPS_TLS_DTPREL_HI16 : case ELF :: R_MICROMIPS_TLS_DTPREL_LO16 : case ELF :: R_MICROMIPS_TLS_GOTTPREL : case ELF :: R_MICROMIPS_TLS_TPREL_HI16 : case ELF :: R_MICROMIPS_TLS_TPREL_LO16 : case ELF :: R_MICROMIPS_GPREL7_S2 : case ELF :: R_MICROMIPS_PC23_S2 : case ELF :: R_MICROMIPS_PC21_S1 : case ELF :: R_MICROMIPS_PC26_S1 : case ELF :: R_MICROMIPS_PC18_S3 : case ELF :: R_MICROMIPS_PC19_S2 : return true ; case ELF ::


<s> static SDValue LowerCTTZ ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op .


<s> EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InVT = Regs [ <NUM_LIT> ] . getValueType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; SDLoc DL ( N ) ; assert ( ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && <STR_LIT> ) ; APInt Mask = APInt :: getLowBitsSet ( InSVT . getSizeInBits ( ) , OutSVT . getSizeInBits ( ) ) ; SDValue MaskVal = DAG . getConstant ( Mask , DL , InVT ) ; for ( auto & Reg : Regs ) Reg = DAG . getNode ( <STR_LIT> , DL , InVT , MaskVal , Reg ) ; MVT UnpackedVT , PackedVT ; if ( OutSVT == <STR_LIT> ) { UnpackedVT = <STR_LIT> ; PackedVT = <STR_LIT> ; } else { UnpackedVT = <STR_LIT> ; PackedVT = <STR_LIT> ; } auto RegNum = Regs . size ( ) ; for ( unsigned j = <NUM_LIT> , e = InSVT . getSizeInBits ( ) / OutSVT . getSizeInBits ( ) ; j < e ; j *= <NUM_LIT> , RegNum /= <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , UnpackedVT , Regs [ i ] ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum / <NUM_LIT> ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , PackedVT , Regs [ i * <NUM_LIT> ] , Regs


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn , std :: vector <

TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) {


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { assert ( MF &&


<s> llvm :: reverse ( llvm :: make_range ( MBB . begin ( ) , TestPos ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI ) ; if ( Cond != <STR_LIT> && ! MI . mayStore ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) && <STR_LIT> ) ; CondRegs [ Cond ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI . findRegisterDefOperand ( <STR_LIT> ) ) break ; } return CondRegs


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) ; MI -> eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor ( JoinMBB )


<s> if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V ) ) return false ; return true


<s> Parser . Lex ( ) ; const MCExpr * IdVal ; SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { while ( <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & nextTok = Parser . getTok ( ) ; if ( nextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; Res = evaluateRelocExpr ( IdVal , Str ) ; return false


<s> const auto * BVN = cast < BuildVectorSDNode > ( N ) ; unsigned Idx ; for ( Idx = <NUM_LIT> ; Idx < BVN -> getNumOperands ( ) ; ++ Idx ) { auto ElemV = BVN -> getOperand (


<s> return __builtin_aarch64_nearbyintv2df (


<s> while ( -- MBBI != MBB -> begin ( ) ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; <STR_LIT> NCC = llvm :: getInstrPredicate ( NMI , PredReg ) ; if ( ! ( NCC == CC || NCC == OCC ) || NMI -> modifiesRegister ( SrcReg , & TRI ) || NMI -> modifiesRegister ( <STR_LIT> , & TRI ) ) break ; if ( ++ NumInsts == <NUM_LIT> )


<s> int NumElts = VT . getVectorNumElements ( ) ; const int Mask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Odd0 = DAG . getVectorShuffle ( VT , dl , Op0 , Op0 , makeArrayRef ( & Mask [ <NUM_LIT> ] , NumElts ) ) ; SDValue Odd1 = DAG . getVectorShuffle ( VT , dl , Op1 , Op1 , makeArrayRef ( & Mask [ <NUM_LIT> ] , NumElts ) ) ; MVT MulVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget . hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SmallVector < int , <NUM_LIT> > HighMask ( NumElts ) ; SmallVector < int , <NUM_LIT> > LowMask ( NumElts ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { HighMask [ i ] = ( i / <NUM_LIT> ) * <NUM_LIT> + ( ( i % <NUM_LIT> ) * NumElts ) + <NUM_LIT> ; LowMask [ i ] = ( i / <NUM_LIT> ) * <NUM_LIT> + ( ( i % <NUM_LIT> ) * NumElts ) ; } SDValue Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; SDValue Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ReachingDefAnalysis > ( ) ; AU . setPreservesCFG ( )


<s> return ( __m256d ) __builtin_ia32_reducepd256_mask ( ( __v4df ) __A , __B , (


<s> bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( ! isTailCall && CLI . CS && CLI . CS -> isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . is<ISA_LIT>64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg ,

isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;