<s> MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; MIRBuilder . insertInstr ( MIB ) ; if ( OrigRet . Reg ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT>


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G0_NC , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC } ; return isMovWSymbol ( Variants


<s> if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD -> getAlignment ( ) ; RLI . AAInfo = LD -> getAAInfo ( ) ; RLI . Ranges = LD


<s> return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) !=


<s> void EmitMappingSymbol ( StringRef Name , SMLoc Loc , MCFragment * F , uint64_t Offset ) { auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; EmitLabelAtPos ( Symbol , Loc , F , Offset ) ; Symbol -> setType ( ELF ::


<s> else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> static bool IsFrameChange ( MachineInstr & MI


<s> return new <ISA_LIT>16DAGToDAGISel ( TM


<s> void sparc_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ]


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) !=


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , bool fast ) { return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo


<s> Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( !


<s> const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; MachineInstr & MI = * MBBI ; for ( unsigned Offset = <NUM_LIT> ; Offset < N ; ++ Offset ) { int ImmOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) + Offset ; bool Kill = ( Offset + <NUM_LIT> == N ) ? MI . getOperand ( <NUM_LIT> ) . isKill ( ) : false ; assert ( ImmOffset >= - <NUM_LIT> && ImmOffset < <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( TRI -> getSubReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> + Offset ) , Opc == <STR_LIT> ? RegState :: Define : <NUM_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , getKillRegState ( Kill ) ) . addImm ( ImmOffset ) ; } MI . eraseFromParent ( ) ; return true


<s> return reinterpret_cast < const uint8_t *


<s> unsigned postOffset ( ) const { return Offset +


<s> Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; Offset = BA -> getOffset ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( foldOffsetIntoAddress ( Offset , AM


<s> return ++ MachineBasicBlock :: iterator ( KillInst ? KillInst :


<s> bool <ISA_LIT>GNULDBackend :: needsLA25Stub ( Relocation :: Type pType , const mcld :: ResolveInfo *


<s> bool isVecListOneD ( ) const { if ( ! isSingleSpacedVectorList (


<s> unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS


<s> unsigned Register = VectorDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> unsigned BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegs . reset (


<s> unsigned NumElems = SVOp -> getSimpleValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , false , DAG , SVOp -> getMaskElt ( <NUM_LIT> ) ) ; unsigned OpSrc ; if ( ! NumZeros ) return


<s> if ( AFI . isThumb1OnlyFunction ( ) ) return - AFI . getArgRegsSaveSize ( ) - ( <NUM_LIT> * <NUM_LIT> ) ; return - AFI . getArgRegsSaveSize ( ) - ( <NUM_LIT>


<s> } return TYPE_MODE ( type ) ; } else if ( size == <NUM_LIT> && ! TARGET_AVX && ! TARGET_IAMCU ) { static bool warnedavx ; static bool warnedavx_ret ; if ( cum && cum -> warn_avx && ! warnedavx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx = true ; } else if ( in_return && ! warnedavx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx_ret = true ; } return TYPE_MODE ( type ) ; } else if ( ( ( size == <NUM_LIT> && TARGET_64BIT ) || size == <NUM_LIT> ) && ! TARGET_SSE && ! TARGET_IAMCU ) { static bool warnedsse ; static bool warnedsse_ret ; if ( cum && cum -> warn_sse && ! warnedsse ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse = true ; } else if ( ! TARGET_64BIT && in_return && ! warnedsse_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse_ret = true ; } } else if ( ( size == <NUM_LIT> && ! TARGET_64BIT ) && ( ! cfun || cfun -> machine -> func_type == TYPE_NORMAL ) && ! TARGET_MMX && ! TARGET_IAMCU ) { static bool warnedmmx ; static bool warnedmmx_ret ; if ( cum && cum -> warn_mmx && ! warnedmmx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedmmx = true ; } else if ( in_return && ! warnedmmx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedmmx_ret = true ; } } return mode ; } gcc_unreachable ( ) ; } } return mode


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isCallingConvWin64 ( F -> getFunction ( ) -> getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget -> hasFp256 ( ) ?


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( Reg - <STR_LIT> + <STR_LIT>


<s> vec_ushort8 mask ; neg_b = ( vec_ushort8 ) vec_sub ( vec_splat_s16 ( <NUM_LIT> ) , ( vec_short8 ) ( b ) ) ; mask = vec_sra ( vec_sl ( neg_b , vec_splat_u16 ( <NUM_LIT> ) ) ,


<s> if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return mode == HImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < <NUM_LIT> ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ) ; return false


<s> bool <ISA_LIT>TargetMachine :: addSimpleCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this ,


<s> if ( CurWord >= O32IntRegsSize ) break ; unsigned SrcReg = O32IntRegs [ CurWord ] ; unsigned Reg = AddLiveIn ( MF , SrcReg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FIN , DAG . getConstant ( i * <NUM_LIT> , <STR_LIT> ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( Reg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( FuncArg

, i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ;


<s> __builtin_ia32_pmovsqw128mem_mask ( ( unsigned int * ) __P , (


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > FalseLanesZero ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Predicated ; MachineBasicBlock * Header = ML . getHeader ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto & MI : * Header ) { if ( ! shouldInspect ( MI ) ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; bool isPredicated = isVectorPredicated ( & MI ) ; bool retainsOrReduces = retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ; if ( isPredicated ) Predicated . insert ( & MI ) ; if ( producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) FalseLanesZero . insert ( & MI ) ; else if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; else if ( ! isPredicated && retainsOrReduces ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return false ; } else if ( ! isPredicated && MI . getOpcode ( ) != <STR_LIT> ) FalseLanesUnknown . insert ( & MI ) ; } LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto * I : Predicated ) dbgs ( ) << <STR_LIT> << *


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( <ISA_LIT>ProcFamily == IntelSkylake || hasAVX512 ( ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead =


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun = gen_rtx_SYMBOL_REF (

Pmode , MCOUNT_NAME ) ; \ emit_library_call ( fun , LCT_NORMAL , VOIDmode , <NUM_LIT> , lr , Pmode ) ; \ }


<s> } if ( ST -> is<ISA_LIT>64 ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this

-> Options . EABIVersion = EABI :: GNU ;


<s> DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc ) , VR0 ) . addReg ( Src ) ; TII . storeRegToStack ( MBB , I , VR0 , true , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( MFHiOpc ) , VR1 )


<s> static rtx rs6000_expand_mtfsf_builtin ( enum insn_code icode , tree exp ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( ! CONST_INT_P ( op0 ) || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg (


<s> Tmp += Base ; Tmp += ( is64BitMode ( ) ) ? <STR_LIT> : ( is32BitMode ( ) ) ? <STR_LIT> : ( is16BitMode ( ) ) ? <STR_LIT> : <STR_LIT> ; Op . setTokenValue ( Tmp ) ; Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , false ) ) ; Op . setTokenValue ( Base ) ; } } } if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = llvm :: count ( Match , Match_Success ) ; if ( UnsizedMemOp && NumSuccessfulMatches > <NUM_LIT> && UnsizedMemOp -> getMemFrontendSize ( ) ) { UnsizedMemOp -> Mem . Size = UnsizedMemOp -> getMemFrontendSize ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( M == Match_Success ) NumSuccessfulMatches


<s> if ( ! first_exit_blocks_p ) return false ; exit_bb = e -> src ; first_exit_blocks_p = false ; } if ( ! exit_bb ) return false ; FOR_EACH_BB_FN ( bb , cfun ) { if ( ! dominated_by_p ( CDI_POST_DOMINATORS , bb , exit_bb ) ) return false ; } if ( TARGET_FORCE_FP_AS_GP ) { return true ; } else { bool good_gain = false ; int symbol_count ; int threshold ; if ( flag_pic || nds32_have_prologue_p ( ) ) { threshold = <NUM_LIT> ; } else { threshold = <NUM_LIT> + ( TARGET_V3PUSH ? <NUM_LIT> : <NUM_LIT> ) ; } symbol_count = nds32_get_symbol_count ( )


<s> addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) addPass ( & IfConverterID ) ; } addPass ( createThumb2ITBlockPass (


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) &&


<s> SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( )


<s> return true ; } if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getRefKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; if ( Res . isAbsolute ( ) && Fixup == nullptr ) { int64_t AbsVal = Res . getConstant ( ) ; switch ( Kind ) { case MEK_None : case MEK_Special : llvm_unreachable ( <STR_LIT> ) ; case MEK_DTPREL : return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ; case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_GOT : case MEK_GOTTPREL : case MEK_GOT_CALL : case MEK_GOT_DISP : case MEK_GOT_HI16 : case MEK_GOT_LO16 : case MEK_GOT_OFST : case MEK_GOT_PAGE : case MEK_GPREL : case MEK_PCREL_HI16 : case MEK_PCREL_LO16 : case MEK_TLSGD : case MEK_TLSLDM : case MEK_TPREL_HI : case MEK_TPREL_LO : return false


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , false


<s> unsigned RegC = OpC . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegA ) ) MRI . constrainRegClass ( RegA , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegB ) ) MRI . constrainRegClass ( RegB , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegX ) ) MRI . constrainRegClass ( RegX , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegY ) ) MRI . constrainRegClass ( RegY , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegC ) ) MRI . constrainRegClass ( RegC , RC ) ; unsigned NewVR = MRI . createVirtualRegister ( RC ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR , <NUM_LIT> ) ) ; unsigned Opcode = Root . getOpcode ( ) ; bool KillA = OpA . isKill ( ) ; bool KillX = OpX . isKill ( ) ; bool KillY = OpY . isKill ( ) ; MachineInstrBuilder MIB1 = BuildMI ( * MF , Prev . getDebugLoc ( ) , TII -> get ( Opcode ) , NewVR ) . addReg ( RegX , getKillRegState ( KillX ) ) . addReg ( RegY , getKillRegState ( KillY ) ) ; InsInstrs . push_back ( MIB1 ) ; MachineInstrBuilder MIB2 = BuildMI ( * MF , Root . getDebugLoc ( ) , TII -> get ( Opcode ) , RegC ) . addReg ( RegA , getKillRegState ( KillA ) ) . addReg ( NewVR , getKillRegState ( true ) ) ; InsInstrs . push_back ( MIB2 ) ; DelInstrs . push_back ( & Prev


<s> unsigned MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > <NUM_LIT> ) { MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasSSSE3 ( ) ) { MaxOps = <NUM_LIT> ; } else { return ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , E = L -> block_end ( ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; for ( BasicBlock :: iterator J = BB -> begin ( ) , JE = BB -> end ( ) ; J != JE ; ++ J ) if ( isa < CallInst > ( J ) || isa < InvokeInst > ( J ) ) { ImmutableCallSite CS (


<s> unsigned getRegisterBitWidthUpperBound ( bool Vector


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addReg ( Op1 , getKillRegState ( Op1IsKill ) ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; return ResultReg ; } return FastISel :: fastEmitInst_rr ( MachineInstOpcode , RC , Op0 ,


<s> void addMemTBHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( ) ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple


<s> if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V4HFmode || mode == V8HFmode || mode == V1DFmode ) ) return true ; return false


<s> return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Aligned || ( imm & <NUM_LIT> ) == <NUM_LIT> ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( imm , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! Aligned || ( Imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) && ( ! Aligned || ( CN -> getZExtValue ( )


<s> EVT VecVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue Conv = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op -> getOperand ( <NUM_LIT> ) ) ; unsigned Lane = cast < ConstantSDNode > ( Op . getOperand (


<s> SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDValue FPSCR = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , Ops ) ; Chain = FPSCR . getValue ( <NUM_LIT> ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> <<


<s> LinkageAttr = MCSA_Weak ; break ; case GlobalValue :: AvailableExternallyLinkage : LinkageAttr = MCSA_Extern ; break ; case GlobalValue :: PrivateLinkage : return ; case GlobalValue :: InternalLinkage : assert ( GV -> getVisibility ( ) == GlobalValue :: DefaultVisibility && <STR_LIT> ) ; LinkageAttr = MCSA_LGlobal ; break ; case GlobalValue :: AppendingLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: CommonLinkage : llvm_unreachable ( <STR_LIT> ) ; } assert ( LinkageAttr != MCSA_Invalid && <STR_LIT> ) ; MCSymbolAttr VisibilityAttr = MCSA_Invalid ; switch ( GV -> getVisibility ( ) ) { case GlobalValue ::


, ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; } SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , InVT . getVectorElementType ( ) ) ; const Constant * C = ( dyn_cast < ConstantSDNode > ( Cst ) ) -> getConstantIntValue ( ) ; SDValue CP = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; SDValue Ld = DAG . getLoad ( Cst . getValueType ( ) , DL , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; SDValue OneV = DAG . getNode ( <STR_LIT> , DL , InVT , Ld ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , InVT , OneV , In ) ; return DAG . getNode ( <STR_LIT> , DL , VT , And , And ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Undef = DAG . getUNDEF ( VT ) ; OpLo = DAG . getVectorShuffle ( VT , DL , OpLo , Undef , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( VT , DL , OpHi , Undef , ShufMask1 ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask2 ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getNode ( <STR_LIT> , DL


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler * mang , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( ctx ) , Mang ( mang ) , AsmPrinter ( asmprinter ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetPICBaseSymbol ( ) const ; MCSymbol * GetSymbolFromOperand ( const MachineOperand &


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode ( ) ) ) ) ; unsigned RegNum = getCondCode ( ) == <STR_LIT> ? <NUM_LIT> : <STR_LIT> ; Inst . addOperand ( MCOperand ::


<s> if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! Subtarget . hasAVX512 ( ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT .


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; gcc_assert ( pcum -> pcs_variant == ARM_PCS_AAPCS64 ) ; if ( mode == VOIDmode ) return NULL_RTX ; aarch64_layout_arg ( pcum_v , mode , type , named


<s> if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > <NUM_LIT> ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ <NUM_LIT> ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true


<s> Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false

) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT ==


<s> if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == <NUM_LIT> ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + <NUM_LIT> ) ) ; dwarf_par_index = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ) , gen_rtx_UNSPEC (

BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ;


<s> O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm (


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> bool shouldIgnoreForPipelining ( const MachineInstr * MI ) const override { return MI == EndLoop || MI


<s> int NumLaneElts = NumElts / NumLanes ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget . hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( AlignVT , Lo ) ; Hi = DAG . getBitcast ( AlignVT , Hi ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , AlignVT , Lo , Hi , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> ,

DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned reglist = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( ! Check ( S , DecodeDPRRegListOperand ( Inst , reglist , Address , Decoder ) ) ) { return MCDisassembler :: Fail ; } } else { unsigned reglist = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) |


<s> bool Changed = false ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get


<s> return ( __m512i ) __builtin_ia32_pminuq512_mask ( ( __v8di ) __A , (


<s> SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( DAG , V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { if ( SDValue NegVal = isFNEG ( DAG , V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { NegVal = DAG . getBitcast ( V . getOperand ( <NUM_LIT>


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ; return true ; } MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new <ISA_LIT>MCAsmBackend ( OSABI )


<s> IsV1Zeroable = false ; break ; } SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL ,


<s> void addHI32DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getHI32DSPReg ( )


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return


<s> static bool isPredicateCCSettingOp ( SDValue N ) { if ( ( N . getOpcode ( ) == <STR_LIT> ) || ( N . getOpcode ( ) == <STR_LIT> && ( N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT>

|| N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) ) ) return true ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcVecReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LaneReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcValReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * VecRC = nullptr ; const TargetRegisterClass * GPRRC = Subtarget . isGP64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned EltLog2Size ; unsigned InsertOp = <NUM_LIT> ; unsigned InsveOp = <NUM_LIT> ; switch ( EltSizeInBytes ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister (


<s> Color <ISA_LIT>A57FPLoadBalancing :: getColor ( unsigned Reg ) { if ( ( TRI -> getEncodingValue ( Reg ) % <NUM_LIT> ) == <NUM_LIT> ) return Color :: Even ; else return Color ::


<s> bool sh_reg_dead_or_unused_after_insn ( const rtx_insn * i , int regno ) { return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno


<s> if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr *


<s> bool <ISA_LIT>ParallelDSP :: IsNarrowSequence ( Value * V ) { if ( auto * SExt = dyn_cast < SExtInst > ( V ) ) { if ( SExt -> getSrcTy ( ) -> getIntegerBitWidth ( ) != MaxBitWidth ) return false ; if ( auto * Ld = dyn_cast < LoadInst > ( SExt -> getOperand ( <NUM_LIT> ) ) ) { return LoadPairs . count ( Ld ) || OffsetLoads . count ( Ld ) ; } } return false


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addFrameIndex (


<s> if ( MemOps [ i ] . Position < Position ) { Position = MemOps [ i ] . Position ; Loc = MemOps [ i ] . MBBI ; } } if ( Loc != MBB . begin ( ) ) RS -> forward ( std :: prev (


<s> case CM_MEDIUM : ptr -> x_ix86_cmodel = CM_MEDIUM_PIC ; break ; case CM_LARGE : ptr -> x_ix86_cmodel = CM_LARGE_PIC ; break ; case CM_KERNEL : error ( <STR_LIT> , <STR_LIT> ) ; break ; default : break ; } else switch ( ptr -> x_ix86_cmodel ) { case CM_SMALL_PIC : ptr -> x_ix86_cmodel = CM_SMALL ; break ; case CM_MEDIUM_PIC : ptr -> x_ix86_cmodel = CM_MEDIUM ; break ; case CM_LARGE_PIC : ptr -> x_ix86_cmodel =


<s> if ( ! TARGET_SSE_MATH ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( )


<s> static DecodeStatus DecodeZPR4RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> static DecodeStatus DecodeCASI32 ( MCInst & MI , uint64_t insn , uint64_t Address


<s> return std :: make_pair ( Loc -> getFilename (


<s> MCSection * ELFSection = getContext ( ) . getELFSection ( Section , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; getParser ( ) . getStreamer ( ) . SwitchSection ( ELFSection ) ; getParser ( ) . Lex ( )


<s> void llvm :: addUnpredicatedMveVpredNOp ( MachineInstrBuilder & MIB ) { MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , llvm :: CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> UserOffset -= <NUM_LIT> ; TotalAdj = <NUM_LIT> ; } if ( isThumb && TrialOffset % <NUM_LIT> != <NUM_LIT> ) { TrialOffset += <NUM_LIT> ; TotalAdj += <NUM_LIT> ; } if ( isThumb2 && TotalAdj != <NUM_LIT> ) MaxDisp -= ( <NUM_LIT> - TotalAdj ) ; if ( UserOffset <= TrialOffset ) { if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK ) { if ( UserOffset - TrialOffset <= MaxDisp ) return true ; } return


<s> if ( TARGET_SPE && regno < <NUM_LIT> && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SFmode && mode != SDmode && mode != SCmode ) ) ) ; else return NULL_RTX ; regno = REGNO ( reg ) ; words = ( GET_MODE_SIZE ( mode ) +


<s> else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , <STR_LIT> ) ; if ( AM . Segment . getNode ( ) ) Segment = AM . Segment ; else Segment = CurDAG -> getRegister ( <NUM_LIT> ,


<s> if ( isa < InlineAsm > ( Callee ) ) return false ; if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( CI ) ) return <ISA_LIT>VisitIntrinsicCall ( * II ) ; if ( cast < CallInst > ( I ) -> isTailCall ( ) ) return false ; return DoSelectCall ( I


<s> if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI . readsRegister ( Reg , TRI )


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; model_rtx = operands [ <NUM_LIT> ] ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setManipulatesSP ( true ) ; bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue NewSP = Op . getOperand ( <NUM_LIT> ) ; SDValue Backchain ; SDLoc DL ( Op


<s> static DecodeStatus DecodeFMOVLaneInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned IsToVec = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( IsToVec ) { DecodeFPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd ,


<s> return new <ISA_LIT>DAGToDAGISel ( TM )


<s> void dumpStack ( ) const { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != StackTop ;


<s> case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width =


<s> auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else { switch ( Val ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( * MF


<s> initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU ,


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT


<s> if ( MFI -> getCalleeSavedInfo ( ) . size ( ) ) { splitSPAdjustments ( MFI -> getStackSize ( ) , NumInitialBytes , NumResidualBytes ) ; } else { NumInitialBytes = MFI -> getStackSize ( ) ; NumResidualBytes = <NUM_LIT> ; } FuncInfo -> setInitialStackAdjust ( NumInitialBytes ) ; emitSPUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , - NumInitialBytes , MachineInstr :: FrameSetup ) ; if ( NeedsFrameMoves && NumInitialBytes ) { MCSymbol * SPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( SPLabel ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , NumInitialBytes ) ; Moves . push_back ( MachineMove ( SPLabel , Dst , Src ) ) ; } bool FPNeedsSetting = hasFP ( MF ) ; for ( ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( FPNeedsSetting && MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { int64_t X29FrameIdx = MBBI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; FuncInfo -> setFramePointerOffset ( MFI -> getObjectOffset ( X29FrameIdx ) ) ; ++ MBBI ; emitRegUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , <STR_LIT> , <STR_LIT> , NumInitialBytes + MFI -> getObjectOffset ( X29FrameIdx ) , MachineInstr :: FrameSetup ) ; MFI -> setOffsetAdjustment ( - MFI -> getObjectOffset ( X29FrameIdx ) - MFI -> getStackSize ( ) ) ; if ( NeedsFrameMoves ) { MCSymbol * FPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( FPLabel ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , - MFI -> getObjectOffset ( X29FrameIdx ) ) ; Moves . push_back ( MachineMove ( FPLabel , Dst , Src ) ) ; } FPNeedsSetting = false


<s> bool MOVToLEAPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; if ( Seed != <NUM_LIT> ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( Seed , this , Fn . getFunction ( ) -> getName ( ) ) ) ; else if ( ! RNG ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( this ) ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { ++ PreMOVtoLEAInstructionCount ; if ( I -> getNumOperands ( ) != <NUM_LIT> || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { ++ I ; continue ; } unsigned leaOpc ; if ( I -> getOpcode ( ) == <STR_LIT> ) { leaOpc = <STR_LIT> ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { leaOpc = <STR_LIT> ; } else { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( <NUM_LIT> ) ; ++


<s> return ( int ) __builtin_ia32_vcvtss2si32 ( ( __v4sf ) __A


<s> if ( ! TII -> isBranchWithImm ( Br -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MIB . addImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MIB . addMBB ( MBBOpnd ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( Br -> hasDelaySlot ( ) ) { assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II = Br


<s> __builtin_aarch64_st1v8hi ( ( __builtin_aarch64_simd_hi * ) a ,


<s> getStreamer ( ) . emitLabel ( Label ) ; return Label


<s> void emitA64MappingSymbol ( ) { if ( LastEMS == EMS_A64 ) return ; emitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> if ( Subtarget -> isTargetCygMing ( ) ) { TargetLowering :: ArgListTy Args ; auto & DL = CurDAG -> getDataLayout ( ) ; TargetLowering :: CallLoweringInfo CLI ( * CurDAG ) ; CLI . setChain ( CurDAG -> getRoot ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * CurDAG -> getContext ( ) ) , CurDAG -> getExternalSymbol ( <STR_LIT> , TLI -> getPointerTy ( DL ) ) , std :: move ( Args ) ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; std :: pair < SDValue , SDValue > Result = TLI . LowerCallTo ( CLI ) ; CurDAG -> setRoot ( Result .


<s> getStreamer ( ) . emitCFINegateRAState ( ) ; return


<s> StringRef Name = <STR_LIT> ( ) . toString ( psbhintop , STI . getFeatureBits ( ) , Valid ) ; if ( Valid )


<s> } if ( Ctx && <STR_LIT> ( Value ) == - <NUM_LIT> ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( Value ) | ( opc << <NUM_LIT> ) ; } case <STR_LIT> : { Value -= <NUM_LIT> ; unsigned opc = <NUM_LIT> ; if ( ( int64_t ) Value < <NUM_LIT> ) { Value = - Value ; opc = <NUM_LIT> ; } uint32_t out = ( opc << <NUM_LIT> ) ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint64_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> & ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : { Value = Value - <NUM_LIT> ; Value >>= <NUM_LIT> ; uint32_t out = <NUM_LIT> ; bool I = Value & <NUM_LIT> ; bool J1 = Value & <NUM_LIT> ; bool J2 = Value & <NUM_LIT> ; J1 ^= I ; J2 ^= I ; out |= I << <NUM_LIT> ; out |= ! J1 << <NUM_LIT> ; out |= ! J2 << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint64_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { Value = Value - <NUM_LIT> ; Value >>= <NUM_LIT> ; uint64_t out = <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint32_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { uint32_t offset = ( Value - <NUM_LIT> ) >> <NUM_LIT> ; uint32_t signBit = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t I1Bit = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J1Bit = ( I1Bit ^ <NUM_LIT> ) ^ signBit ; uint32_t I2Bit = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J2Bit = ( I2Bit ^ <NUM_LIT> ) ^ signBit ; uint32_t imm10Bits = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t imm11Bits = ( offset & <NUM_LIT> ) ; uint32_t Binary


<s> rtx var = XVECEXP ( vals , <NUM_LIT> , one_var ) ; enum machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , <NUM_LIT> , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , <NUM_LIT> ) ) ; switch ( mode ) { case V2DFmode : case V2DImode : case V2SFmode : case V2SImode : return false ; case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) &


<s> static void verifyIntrinsicTables ( ) { assert ( std :: is_sorted ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) && std :: is_sorted ( std :: begin ( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain


<s> return getSubExpr ( ) -> FindAssociatedSection


<s> num_bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return rx_round_up ( num_bytes


<s> MVT IntVT = <STR_LIT> ( IntScalar , VT . getVectorNumElements ( ) ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT>


<s> static SDValue Widen ( SelectionDAG * CurDAG , SDValue N ) { SDLoc dl ( N ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue ImpDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , ImpDef , N , SubReg ) ; return SDValue ( Node ,


<s> bool hasMiscellaneousExtensions3 ( ) const { return HasMiscellaneousExtensions3


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok . Length


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] =


<s> static DecodeStatus DecodeFixedPointScaleImm32 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm


<s> bool isNEONi32splatNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE ->


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . useConstIslands ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( create<ISA_LIT>NaClRewritePass


<s> if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } else if ( Subtarget . hasAVX2 ( ) ) { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } else { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } if ( NumSubs == <NUM_LIT> ) return Builder ( DAG , DL , Op0 , Op1 ) ; SmallVector < SDValue , <NUM_LIT> > Subs ; EVT InVT = Op0 . getValueType ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , InVT . getVectorNumElements ( ) / NumSubs ) ; for ( unsigned i = <NUM_LIT> ; i != NumSubs ; ++ i ) { unsigned Idx = i * SubVT . getVectorNumElements ( ) ; SDValue LHS = extractSubVector ( Op0 , Idx , DAG , DL ,


<s> return ( __m128d ) __builtin_ia32_xorpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) ,


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; if ( OpIdx == TID . getNumOperands ( ) || TID . OpInfo [ OpIdx ] . isPredicate ( ) || TID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary


<s> mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = getTargetVShiftUniformOpcode ( Opcode , false ) ; unsigned <ISA_LIT>OpcV = getTargetVShiftUniformOpcode ( Opcode , true ) ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> return ( vector signed int ) __builtin_altivec_vsubsws ( ( vector signed int ) a1 , ( vector signed int )


<s> void <ISA_LIT>SEDAGToDAGISel :: processFunctionAfterISel ( MachineFunction & MF ) { MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> initGlobalBaseReg ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : addDSPCtrlRegOperands ( false , MI , MF ) ; break ; case <STR_LIT> : addDSPCtrlRegOperands ( true , MI , MF ) ; break ; case <STR_LIT>


<s> int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) :

getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ;


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame


<s> if ( operands [ <NUM_LIT> ] != const1_rtx && operands [ <NUM_LIT> ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , <NUM_LIT> ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( ( code == LTU ) == ( operands [ <NUM_LIT> ] == constm1_rtx ) ) { switch ( mode ) { case E_QImode : insn = gen_subqi3_carry ; break ; case E_HImode : insn = gen_subhi3_carry ; break ; case E_SImode : insn = gen_subsi3_carry ; break ; case E_DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : insn =


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg ReservedGPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isFP64bit ( ) ) { for ( MCPhysReg Reg : <STR_LIT> ) Reserved . set ( Reg ) ; } else { for ( MCPhysReg Reg : <STR_LIT> ) Reserved . set ( Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( needsStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( MCPhysReg Reg : <STR_LIT> ) Reserved . set ( Reg ) ; if ( Subtarget . in<ISA_LIT>16Mode ( )


<s> unsigned int nargs , regno ; push_topmost_sequence ( ) ; nargs = <NUM_LIT> ; memset ( reg_values , <NUM_LIT> , sizeof ( reg_values ) ) ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( ! INSN_P ( insn ) ) break ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) != SET ) break ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( mips16e_collect_argument_save_p ( dest , src , reg_values , & regno ) ) { if ( ! BITSET_P ( cfun -> machine -> frame . mask , regno


<s> return MatchOperand_NoMatch ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * EVal ; if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Offset = <STR_LIT> ( EVal , S , E ) ; else return MatchOperand_NoMatch ; break ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( ! getParser ( ) . parseIdentifier ( Identifier ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal = parseIdentifier ( Identifier ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Offset = <STR_LIT> ( EVal , S , E ) ; } break ; } case AsmToken :: LParen : Offset = <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , S , E ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: LParen : Parser . Lex ( ) ; break ; } const MCExpr * IndexValue = nullptr ; unsigned IndexReg = <NUM_LIT> ; switch ( getLexer ( ) . getKind ( ) ) { default : if ( ParseRegister ( IndexReg , S , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( getParser ( ) . parseExpression ( IndexValue , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Comma : IndexValue = MCConstantExpr :: create ( <NUM_LIT>


<s> Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . is256BitVector ( ) ) { if ( Subtarget -> hasInt256 ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; }


<s> if ( <ISA_LIT>FI -> hasPreallocatedCall ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; bool CantUseFP = hasStackRealignment ( MF


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( TM . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: <ISA_LIT> ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; assert ( Encoding == DW_EH_PE_absptr && <STR_LIT> ) ; return MCSymbolRefExpr :: create ( TM . getSymbol ( GV ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2


<s> uint64_t Used = allOnes ( Op . getValueSizeInBits ( ) ) ; if ( Used != ( AndMask | InsertMask ) ) { KnownBits Known ; CurDAG -> computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known ) ; if ( Used != ( AndMask | InsertMask | Known . Zero . getZExtValue ( ) ) ) return false ; } Op = Op . getOperand ( <NUM_LIT>


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )

. addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = <STR_LIT> ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( )


<s> if ( MMO -> isVolatile ( ) ) return false ; if ( MMO -> getAlignment ( ) < <NUM_LIT> ) return false ; if ( MI -> getNumOperands ( ) > <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; if ( MI -> getNumOperands ( ) > <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; int Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned SoImm = MI . getOperand ( Op ) . getImm ( ) ; unsigned Encoded = <STR_LIT> ( SoImm


<s> void printU16ImmOperand ( const MachineInstr * MI


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast <


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT )


<s> MCSymbol * TypeInfoSym = TM . getSymbol ( GV ) ; MCSymbol * TOCEntry = lookUpOrCreateTOCEntry ( TypeInfoSym ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; auto & Ctx = OutStreamer


<s> Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 , II . getNumDefs ( ) + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; return


<s> if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rn , Address , Decoder


<s> jump = emit_jump_insn_after ( gen_jump ( bp -> far_label ) , insn ) ; LABEL_NUSES ( bp -> far_label ) ++ ; } else jump = emit_jump_insn_after ( gen_return ( ) , insn ) ; if ( optimize ) emit_barrier_after ( jump ) ; emit_label_after ( bp -> near_label , insn ) ; if ( bp -> far_label ) JUMP_LABEL ( jump ) = bp -> far_label ; else { rtx pat = PATTERN ( jump ) ; gcc_assert ( ANY_RETURN_P ( pat ) ) ; JUMP_LABEL ( jump )


<s> return __builtin_mve_vnegq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg

( ZeroReg , getKillRegState ( true ) ) ;


<s> mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return - <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( HOST_WIDE_INT_1U << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ; if ( ( mantissa & mask ) != <NUM_LIT> ) return - <NUM_LIT> ; mantissa >>= point_pos - <NUM_LIT> ; if ( mantissa == <NUM_LIT> ) return - <NUM_LIT> ; gcc_assert ( mantissa >= <NUM_LIT> && mantissa <= <NUM_LIT> ) ; exponent = <NUM_LIT> - exponent ; if ( exponent < <NUM_LIT> || exponent > <NUM_LIT> ) return - <NUM_LIT> ; return ( sign << <NUM_LIT> ) | ( ( exponent ^ <NUM_LIT> ) << <NUM_LIT> ) | ( mantissa -


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( (


<s> return ( vector unsigned char ) __builtin_altivec_vspltb ( ( vector signed char ) a1 ,


<s> Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { if ( ! isInt < <NUM_LIT> > ( Offset ) && ( Offset == ( Offset & <NUM_LIT> ) ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = MBB . getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Offset ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> >


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>MCAsmStreamer :: reset ( ) { LabelToEmit . clear ( ) ; ExplicitCommentToEmit . clear ( ) ; CommentToEmit . clear ( ) ; Symbols . clear ( ) ; CurrentAlignmentToValue =


<s> return new <ISA_LIT>AsmBackend ( T , TT . getOS ( )


<s> MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) ==


<s> static void appendAndTransferDominatedUses ( Instruction * NewPt , Instruction * User , unsigned OpNo , InsertionPoints :: iterator & IPI , InsertionPoints & InsertPts ) { IPI -> second . emplace_back ( User , OpNo ) ; Instruction * OldInstr = IPI -> first ; Uses OldUses = std :: move ( IPI -> second ) ; InsertPts [ NewPt ] = std :: move ( OldUses ) ; InsertPts . erase ( OldInstr


<s> uint32_t getParameterType ( ) const { return ParameterType


<s> return make_unique < <ISA_LIT>DCModule > ( *


<s> if ( ! isSingleSpacedVectorList ( ) ) return false ; return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList


<s> BHi = DAG . getBitcast ( ExVT , getUnpackh ( DAG , dl , VT , Zero , B ) ) ; } else { BLo = DAG . getBitcast ( ExVT , getUnpackl ( DAG , dl , VT , B , Zero ) ) ; BHi = DAG . getBitcast ( ExVT , getUnpackh ( DAG , dl , VT , B , Zero ) ) ; } unsigned MulOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue RLo = DAG . getNode ( MulOpc , dl , ExVT , ALo , BLo ) ; SDValue RHi = DAG . getNode ( MulOpc , dl , ExVT , AHi , BHi ) ; if ( Low ) { SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ; SDValue LLo = DAG . getNode ( <STR_LIT> , dl , ExVT , RLo , Mask ) ; SDValue LHi = DAG . getNode ( <STR_LIT> , dl , ExVT , RHi , Mask ) ; * Low = DAG . getNode ( <STR_LIT> , dl , VT , LLo , LHi ) ; } RLo = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , RLo , <NUM_LIT> , DAG ) ; RHi = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , RHi , <NUM_LIT>


<s> SDValue CPHi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue CP = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , GOTFlag ) ; CP = DAG . getNode ( <STR_LIT> , dl , ValTy , CP ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) ,


<s> MCInst I ; if ( Opcode == <STR_LIT> ) { unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; } I . setOpcode (


<s> if ( AM . hasIndexField ( ) && ! AM . Index . getNode ( ) ) { AM . Base = Base ; AM . Index = Index ; return true


<s> RegisterTarget < Triple :: aarch64 , true > X ( The<ISA_LIT>Target


<s> if ( current_frame_info . r [ reg_fp ] != <NUM_LIT> && ( grsave_prev == <NUM_LIT> || current_frame_info . r [ reg_fp ] == grsave_prev + <NUM_LIT> ) ) { mask |= <NUM_LIT> ; if ( grsave_prev == <NUM_LIT> ) grsave = HARD_FRAME_POINTER_REGNUM ; grsave_prev = current_frame_info . r [ reg_fp ] ; } if ( current_frame_info . r [ reg_save_pr ] != <NUM_LIT> && ( grsave_prev == <NUM_LIT> || current_frame_info . r [ reg_save_pr ] == grsave_prev + <NUM_LIT> ) ) { mask |= <NUM_LIT> ; if ( grsave_prev == <NUM_LIT> ) grsave = current_frame_info . r [ reg_save_pr ] ; } if ( mask && TARGET_GNU_AS ) fprintf ( file ,

<STR_LIT> , mask , ia64_dbx_register_number ( grsave ) ) ;


<s> int64_t ImmValue ; if ( ! GetImm ( MI , Entry . ImmField ( ) , ImmValue ) ) return false ; if ( ! AddiuspImmValue ( ImmValue )


<s> return __builtin_aarch64_usqaddhi_uus ( __a ,


<s> reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_pic_add_dot_plus_eight ( reg , reg , labelno ) ) ; else emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , <NUM_LIT> , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC )


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) )


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( )


<s> SDNode * N = & * -- Position ; if ( N -> use_empty ( ) ) continue ; SDValue Res ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : Res = combineToCMPB ( N ) ; break ; } if ( ! Res ) foldBoolExts ( Res , N ) ; if ( Res ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Res . getNode ( ) -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; MadeChange =


<s> if ( ! OutVT . isVector ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned RegNum = InVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > SubVec ( RegNum ) ; unsigned NumSubRegElts = <NUM_LIT> / InSVT . getSizeInBits ( ) ; EVT SubRegVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubRegElts ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) SubVec [ i ] = DAG . getNode ( <STR_LIT> , DL , SubRegVT , In , DAG . getIntPtrConstant ( i * NumSubRegElts , DL ) ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DAG , SubVec ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N


<s> O << ( int16_t ) MI -> getOperand ( OpNum )


<s> Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp (


<s> RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr ::


<s> isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>MachineFunctionInfo &


<s> SDValue ImpDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SDLoc ( N ) , <STR_LIT> ) , <NUM_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( N ) , <STR_LIT> , ImpDef , N , SubReg ) ; return SDValue ( Node , <NUM_LIT>


<s> OutStreamer . EmitInstruction ( prefix ) ; } MCSymbol * sym = MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) ; const MCSymbolRefExpr * symRef = MCSymbolRefExpr :: Create ( sym , MCSymbolRefExpr :: VK_TLSGD , context ) ; MCInst LEA ; if ( is64Bits ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } OutStreamer . EmitInstruction ( LEA ) ; if ( is64Bits ) { MCInst prefix ; prefix . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( prefix ) ; prefix . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( prefix ) ; prefix . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction


<s> RegisterTarget < Triple :: or1k > X ( The<ISA_LIT>Target , <STR_LIT> ,


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitter


<s> SDValue Op0 = DAG . getBitcast ( VT , Op . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Op0 . getNode ( ) ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; MVT Op1VT = <STR_LIT> ( EltVT , Op1 . getSimpleValueType ( ) . getSizeInBits ( ) / EltSize ) ; Op1 = DAG . getBitcast ( Op1VT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , DAG . getIntPtrConstant ( Imm , DL ) ) ) ; return true ; } case <STR_LIT> : { unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; MVT OpEltVT = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . isInteger ( ) != OpEltVT . isInteger ( ) ) return false ; uint64_t Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Imm = ( Imm * OpEltVT . getSizeInBits ( ) ) / EltSize ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = <STR_LIT> ( EltVT , Op0 . getSimpleValueType ( ) . getSizeInBits ( ) / EltSize ) ; Op0 = DAG . getBitcast ( Op0VT , Op0 ) ; DCI . AddToWorklist ( Op0 . getNode ( ) ) ; DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , DAG . getIntPtrConstant ( Imm , DL ) ) ) ; return true ; } case <STR_LIT> : { unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; if ( VT . isInteger ( ) != Op . getSimpleValueType ( ) . isInteger ( ) ) return false ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = <STR_LIT> ( EltVT , Op0 . getSimpleValueType ( ) . getSizeInBits ( ) / EltSize ) ; Op0 = DAG . getBitcast ( Op0VT , Op . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Op0 . getNode ( ) ) ; DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL ,


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> static void rs6000_function_specific_print ( FILE * file , int indent , struct cl_target_option * ptr ) { rs6000_print_isa_options ( file , indent , <STR_LIT> , ptr -> x_rs6000_isa_flags ) ; rs6000_print_isa_options ( file , indent , <STR_LIT> , ptr ->