<s> SmallVector < LoadInst * , <NUM_LIT> > Loads ; SmallVector < Instruction * , <NUM_LIT> > Writes ; LoadPairs . clear ( ) ; WideLoads . clear ( ) ; OrderedBasicBlock OrderedBB ( BB ) ; for ( auto & I : * BB ) { if ( I . mayWriteToMemory ( ) ) Writes . push_back ( & I ) ; auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ; } if ( Loads . empty ( ) || Loads . size ( ) > NumLoadLimit ) return false ; using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: unknown ( ) ; for ( auto Write : Writes ) { for ( auto Read : Loads ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( OrderedBB . dominates ( Write , Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { LoadInst * Dominator = OrderedBB . dominates ( Base , Offset ) ? Base : Offset ; LoadInst * Dominated = OrderedBB . dominates ( Base , Offset ) ? Offset : Base ; if ( RAWDeps . count ( Dominated ) ) { InstSet & WritesBefore = RAWDeps [ Dominated ] ; for ( auto Before


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex


<s> static bool isEAXLiveIn ( MachineFunction & MF ) { for ( MachineRegisterInfo :: livein_iterator II = MF . getRegInfo ( ) . livein_begin ( ) , EE = MF . getRegInfo ( ) . livein_end ( ) ; II != EE ; ++ II ) { unsigned Reg = II -> first ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return true ; } return


<s> case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_dq_form (


<s> MCSection * <ISA_LIT>WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) || Kind . isMergeableConst8 ( ) ) COMDATSymName = <STR_LIT> + scalarConstantToHexString ( C ) ; else if ( Kind . isMergeableConst16 ( ) ) COMDATSymName


<s> static MCSymbol * createMCSymbolForTlsGetAddr ( MCContext & Ctx ) { return Ctx . getXCOFFSection ( <STR_LIT> , SectionKind :: getText ( ) , XCOFF :: CsectProperties ( XCOFF ::

XMC_PR , XCOFF :: XTY_ER ) ) -> getQualNameSymbol ( ) ;


<s> assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubElts = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , NumSubElts ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = {


<s> case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return


<s> SDValue getAddrGlobal ( NodeTy * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , Chain , Tgt ,

PtrInfo , false , false , false , <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; MVT VT = Op . getSimpleValueType ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & DAG . getTarget ( ) ) ; TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( <STR_LIT> ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , <NUM_LIT> ) ; if ( isPositionIndependent ( ) ) { Addr = makeHiLoPair ( Addr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> TargetRegistry :: RegisterMCDisassembler (


<s> if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ; ClearRegs . reset ( R * <NUM_LIT> , ( R + <NUM_LIT> ) * <NUM_LIT> ) ; } else if ( Reg >= <STR_LIT> && Reg


<s> unsigned SecondReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ThirdReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( has<ISA_LIT>1 ( ) && ! has<ISA_LIT>2 ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ThirdReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , <STR_LIT> , ATReg , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; emitRR ( IsDouble ? ( Is64FPU ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> , FirstReg , SecondReg , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , <STR_LIT> , ThirdReg , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; return false ; } emitRR ( IsDouble ? ( Is64FPU ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> , FirstReg , SecondReg , IDLoc


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( ArgFlags . isByVal ( ) ) { if ( ArgFlags . getNonZeroByValAlign ( ) > PtrAlign ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const unsigned ByValSize = ArgFlags . getByValSize ( ) ; if ( ByValSize == <NUM_LIT> ) { State . addLoc ( CCValAssign :: getMem ( ValNo , <STR_LIT> , State . getNextStackOffset ( ) , RegVT , LocInfo ) ) ; return false ; } const unsigned StackSize = alignTo ( ByValSize , PtrAlign ) ; unsigned Offset = State . AllocateStack ( StackSize , PtrAlign ) ; for ( const unsigned E = Offset + StackSize ; Offset < E ; Offset += PtrAlign . value ( ) ) { if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else { State . addLoc ( CCValAssign :: getMem ( ValNo , <STR_LIT> , Offset , <STR_LIT> , LocInfo ) ) ; break ; } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrAlign . value ( ) , PtrAlign ) ; if ( ValVT . getFixedSizeInBits ( ) < RegVT . getFixedSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> :


<s> static MachineBasicBlock :: iterator maybeMoveCFI ( MachineInstr & MI , MachineBasicBlock :: iterator MaybeCFI ) { auto End = MI . getParent ( ) -> end ( ) ; if ( MaybeCFI == End || MaybeCFI -> getOpcode ( ) != TargetOpcode :: CFI_INSTRUCTION || ! ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) || getLdStBaseOp ( MI ) . getReg ( ) != <STR_LIT> ) return End ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; unsigned CFIIndex = MaybeCFI -> getOperand ( <NUM_LIT> ) . getCFIIndex ( ) ; const MCCFIInstruction & CFI = MF . getFrameInstructions ( ) [ CFIIndex ] ; switch ( CFI . getOperation ( )


<s> MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( J -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( * I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( * I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size


<s> return isVectorIndexInRange < <NUM_LIT> > ( )


<s> if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI )


<s> switch ( v ) { case VECTOR_NONE : ret = <STR_LIT> ; break ; case VECTOR_ALTIVEC : ret = <STR_LIT> ; break ; case VECTOR_VSX : ret


<s> if ( IsVSReg ( DstMO . getReg ( ) , MRI ) && ! IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * SrcRC = IsVRReg ( SrcMO . getReg ( ) , MRI ) ? & <STR_LIT> : & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVRReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( IsVRReg ( SrcMO . getReg ( ) , MRI ) ? <STR_LIT> : <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( )


<s> case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineSHIFTROT ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N , DCI


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) { report_fatal_error ( <STR_LIT>


<s> case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SPFI ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MPI , Align ( <NUM_LIT> ) ) ; Type * ArgTy = ArgVT . getTypeForEVT (


<s> arg_rtx = arm_function_arg ( args_so_far , arg ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } first_param =


<s> if ( DefSymbol . startswith ( <STR_LIT> ) ) { OperandMatchResultTy ResTy = MatchAnyRegisterNameWithoutDollar ( Operands , DefSymbol . substr ( <NUM_LIT> ) , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; return true ; } else if ( ResTy == MatchOperand_ParseFail ) llvm_unreachable ( <STR_LIT> ) ; return false ; } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) { Parser . Lex (


<s> Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , Align ( <NUM_LIT> ) ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) && shouldUseHorizontalOp ( true , DAG , Subtarget ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue Shuffle = DAG . getVectorShuffle ( <STR_LIT> , dl , Sub


<s> return applyDefaultMapping ( OpdMapper )


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . getBrCond ( CC ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg

( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ShapeT Shape = getTileShape ( SrcReg , VRM , MRI ) ; VRM -> assignVirt2Shape ( VirtReg , Shape ) ; return Shape ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = MI -> getOperand


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( VT == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , IsSigned , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( VT , SDLoc ( Op ) , FIST , StackSlot


<s> bool isT2MemRegOffset ( ) const { if ( ! isMem ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType == <STR_LIT> )


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return


<s> RegKind = <STR_LIT> ; return true ; } if ( name . equals ( <STR_LIT> ) ) { RegNo = <STR_LIT> ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = <STR_LIT> + intVal ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = FloatRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal >= <NUM_LIT> && intVal <= <NUM_LIT> && ( intVal % <NUM_LIT> == <NUM_LIT> ) ) { RegNo = DoubleRegs [ intVal / <NUM_LIT> ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal


<s> if ( DCI . Level == BeforeLegalizeTypes && VT . isVector ( ) && isTypeLegal ( VT ) && DAG . isConstantIntBuildVectorOrConstantInt ( N ->

getOperand ( <NUM_LIT> ) ) ) return DAG . UnrollVectorOp ( N ) ;


<s> return ( vector signed int ) __builtin_altivec_vupkhsh ( ( vector signed


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) != <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || ! isNegativeZeroSplat ( Op1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue FAdd = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 . getOperand ( <NUM_LIT> ) , N -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 .

getOperand ( <NUM_LIT> ) , FAdd , Op0 ) ;


<s> auto LastMappingSymbol = LastMappingSymbols . find ( Section ) ; if ( LastMappingSymbol != LastMappingSymbols . end ( ) ) { LastEMSInfo = std :: move ( LastMappingSymbol


<s> return ( __m512i ) __builtin_ia32_vgf2p8mulb_v64qi ( ( __v64qi ) __A , ( __v64qi )


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( )


<s> EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal


<s> bool isImm0_65535 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue


<s> } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag , GV ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , DL , GA ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN ->


<s> static const <ISA_LIT>RegisterBankInfo :: ValueMapping * getGprbOrCustomMapping ( unsigned Size , unsigned & MappingID ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> [ <STR_LIT> ] ; MappingID =


<s> bool <ISA_LIT>AtomicExpandPass :: needsCmpXchgNb ( llvm :: Type * MemType ) { const <ISA_LIT>Subtarget & Subtarget = TM -> getSubtarget < <ISA_LIT>Subtarget


<s> static bool sh_ms_bitfield_layout_p (


<s> uint64_t getPLT16DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> bool isFP64bit ( ) const { return IsFP64bit


<s> for ( auto * U : V -> users ( ) ) Worklist . push_back ( U ) ; while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > ( U ) ) { for ( auto * UU : U -> users ( ) ) Worklist . push_back ( UU ) ; continue ; } auto * I = dyn_cast < Instruction > ( U ) ; if ( ! I || I -> getParent ( ) -> getParent ( ) !=


<s> if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ; if ( I != E


<s> return ( vector signed short ) __builtin_altivec_vaddshs ( ( vector signed short ) a1 ,


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg ,

int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> if ( auto C = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return C -> getSExtValue ( ) < <NUM_LIT> && C ->


<s> } if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst ,


<s> ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: AExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; Emitted = Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset ( ) ; if ( ! <ISA_LIT>EmitStore ( ArgVT , Arg , Addr


<s> if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State


<s> if ( VT . isVector ( ) ) { unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && MemVT . getVectorElementCount ( ) . Min % <NUM_LIT> == <NUM_LIT> && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( MemVT . getVectorElementCount ( ) . Min / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT>


<s> SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ?


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory


<s> auto * PTrue2VTy = cast < ScalableVectorType > ( PTrue2 -> getType ( ) ) ; return PTrue1VTy -> getElementCount ( ) . getKnownMinValue ( ) < PTrue2VTy -> getElementCount ( ) . getKnownMinValue ( ) ; } ) ; PTrues . remove ( MostEncompassingPTrue ) ; PTrues . remove_if ( isPTruePromoted ) ; MostEncompassingPTrue -> moveBefore ( BB , BB . getFirstInsertionPt ( ) ) ; LLVMContext & Ctx = BB . getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( & BB , ++ MostEncompassingPTrue -> getIterator ( ) ) ; auto * MostEncompassingPTrueVTy = cast < VectorType > ( MostEncompassingPTrue -> getType ( ) ) ; auto * ConvertToSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { MostEncompassingPTrueVTy } , { MostEncompassingPTrue } ) ; bool ConvertFromCreated = false ; for ( auto * PTrue : PTrues ) { auto * PTrueVTy = cast < VectorType > ( PTrue -> getType ( ) ) ; if ( MostEncompassingPTrueVTy != PTrueVTy


<s> int8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , FixedVectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( Factor == <NUM_LIT> ) interleave8bitStride4 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; if ( Factor == <NUM_LIT> ) interleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; break ; default : return false ; } Value * WideVec = concatenateVectors


<s> <ISA_LIT>SSELevel = NoMMXSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false


<s> if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getMoveWideImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) &&


<s> return __builtin_mve_vbicq_sv16qi ( __a ,


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF &


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseArithmeticLogic ( ) ||

hasFuseCCSelect ( ) || hasFuseAdrpAdd ( ) || hasFuseLiterals ( ) ;


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return <NUM_LIT>


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \

return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getSizeInBits ( ) <= <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ; if ( ! ZeroN0 && ! ZeroN1 ) return SDValue ( ) ; N0 = ZeroN0 ? ZeroN0 : N0 ; N1 = ZeroN1 ? ZeroN1 : N1 ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT OpVT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OpVT , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { DAG . getBitcast ( WVT , N0 ) , DAG . getBitcast


<s> void <ISA_LIT>AsmPrinter :: printThumbITMask ( const MachineInstr * MI , int Op ) { unsigned Mask = MI -> getOperand ( Op ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( Mask & ( <NUM_LIT> << Pos ) )


<s> unsigned int factor = ( TARGET_THUMB || ! arm_tune_xscale ? <NUM_LIT> : <NUM_LIT> ) ; if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD * factor ) ; return


<s> Inst . addOperand ( MCOperand :: createReg ( AsmParser . getABI ( ) . ArePtrs64bit ( ) ? getMemBase ( ) ->

getGPR64Reg ( ) : getMemBase ( ) -> getGPR32Reg ( ) ) ) ;


<s> if ( ! Reg ) return ; unsigned Excess = <NUM_LIT> * ( <STR_LIT> - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != <NUM_LIT> && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / <NUM_LIT> , <STR_LIT> ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i )


The<ISA_LIT>_32Target , mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> if ( ! InstDesc . isConditionalBranch ( ) ) return false ; if ( ! isFirstMacroFusibleInst ( Cmp , * MCII ) ) return false ; const <STR_LIT> CmpKind = <STR_LIT> ( Cmp . getOpcode (


<s> static inline unsigned getSORegOffset ( unsigned Op ) { return Op >>


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo (


<s> } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pop ( f , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) { int stack_pointer ; stack_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , stack_pointer ) ; } else { regs_available_for_popping |= ( <NUM_LIT> << frame_pointer ) ; } } if ( regs_available_for_popping == <NUM_LIT> && pops_needed > <NUM_LIT> ) { regs_available_for_popping |= <NUM_LIT> << reg_containing_return_addr ; asm_fprintf ( f , <STR_LIT> , LR_REGNUM , reg_containing_return_addr ) ; reg_containing_return_addr = LR_REGNUM ; } if ( pops_needed > <NUM_LIT> ) { int popped_into ; int move_to ; thumb_pop ( f , regs_available_for_popping ) ; popped_into = number_of_first_bit_set ( regs_available_for_popping ) ; move_to = number_of_first_bit_set ( regs_to_pop ) ; asm_fprintf ( f , <STR_LIT> , move_to , popped_into ) ; regs_to_pop &= ~ ( <NUM_LIT> << move_to ) ; -- pops_needed ; } if ( pops_needed > <NUM_LIT> ) { int popped_into ; thumb_pop ( f , regs_available_for_popping ) ; popped_into = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , popped_into ) ; } if ( restore_a4 ) { if ( reg_containing_return_addr != LR_REGNUM


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned NumOperands = MI . getNumOperands ( ) ; MI . RemoveOperand ( NumOperands - <NUM_LIT> ) ; MI . addOperand ( MF , MachineOperand ::


<s> inline vector unsigned int vec_vmsumuhm ( vector unsigned short a1 , vector unsigned short a2 , vector unsigned int a3 ) { return ( vector unsigned int ) __builtin_altivec_vmsumuhm ( ( vector signed short ) a1 , (

vector signed short ) a2 , ( vector signed int ) a3 ) ;


<s> return new TargetLoweringObjectFileMachO ( ) ; case <ISA_LIT>Subtarget :: isELF : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_ELFTargetObjectFile ( TM ) ; return new <ISA_LIT>32_ELFTargetObjectFile ( TM ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin : case <ISA_LIT>Subtarget ::


<s> static <STR_LIT> Translate<ISA_LIT>CC ( <STR_LIT> SetCCOpcode , const SDLoc & DL , bool isFP , SDValue & LHS , SDValue & RHS , SelectionDAG & DAG ) { if ( ! isFP ) { if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) { if ( SetCCOpcode == <STR_LIT> && RHSC -> isAllOnes ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isZero ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isZero ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isOne ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : std :: swap ( LHS , RHS ) ; break ; } switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt . trunc ( EltSize ) , TruncVT ) ) ; } return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , <STR_LIT> (

TruncVT , NumElts ) , Ops . data ( ) , NumElts ) ;


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall && ! InternalLinkage && IsCallReloc ) { unsigned GPReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT Ty = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee


<s> static bool CC_<ISA_LIT>_Intr ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { const MachineFunction & MF = State . getMachineFunction ( ) ; size_t ArgCount = State . getMachineFunction ( ) . getFunction ( ) . arg_size ( ) ; bool Is64Bit = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned Offset ; if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> * SlotSize , Align ( <NUM_LIT> ) ) ; } else if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = SlotSize ; } else if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = <NUM_LIT> ; ( void ) State . AllocateStack ( <NUM_LIT> * SlotSize ,


<s> int nvreg = <NUM_LIT> ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > <NUM_LIT> ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ! DECL_WEAK ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( <STR_LIT> , attr_list ) || lookup_attribute ( <STR_LIT> , attr_list ) ) return true ; } return false


<s> bool hasBitPreservingFPLogic ( EVT VT ) const override { return VT == <STR_LIT> || VT == <STR_LIT>


<s> static SDValue LowerInterruptReturn ( SmallVectorImpl < SDValue > & RetOps , SDLoc DL , SelectionDAG & DAG ) { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT>


<s> unsigned int getSlaveReg1 ( unsigned int regNUM ) { std :: unordered_map < unsigned int , unsigned int > :: const_iterator got = GPRregistersMap1 . find ( regNUM ) ; if ( got == GPRregistersMap1 . end ( )


, pred , src ) , UNSPEC_MERGE_PTRUE ) ) ) ;


<s> static DecodeStatus DecodeVecShiftL16Imm ( MCInst & Inst , unsigned Imm , uint64_t

Addr , const MCDisassembler * Decoder ) {


<s> if ( Rs ) { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; if ( Rs ) { assert ( <STR_LIT> ( MO2 . getImm


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: FRAME_ALLOC ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; if ( IsWinEH ) Offset = static_cast < const <ISA_LIT>FrameLowering * > ( TFI ) -> getFrameIndexOffsetFromSP ( MF , FrameIndex ) ; else Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long )


<s> case ENCODING_IB : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : readImmediate ( insn , insn -> immediateSize ) ; break ; case ENCODING_Ia : readImmediate ( insn , insn -> addressSize ) ; break ; case ENCODING_RB


<s> if ( in_p ) { if ( REGCLASS_HAS_FP_REG ( rclass ) && ! TARGET_SHMEDIA && immediate_operand ( ( x ) , mode ) && ! ( ( fp_zero_operand ( x ) || fp_one_operand ( x ) ) && mode == SFmode ) ) switch ( mode ) { case SFmode : sri -> icode = CODE_FOR_reload_insf__frn ; return NO_REGS ; case DFmode : sri -> icode = CODE_FOR_reload_indf__frn ; return NO_REGS ; case SImode : return FPUL_REGS ; default : abort ( ) ; } if ( rclass == FPUL_REGS && ( ( REG_P ( x ) && ( REGNO ( x ) == MACL_REG || REGNO ( x ) == MACH_REG || REGNO ( x ) == T_REG ) ) || GET_CODE ( x ) == PLUS ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && immediate_operand ( x , mode ) ) { if ( satisfies_constraint_I08 ( x ) || fp_zero_operand ( x ) ) return GENERAL_REGS ; else if ( mode == SFmode ) return FP_REGS ; sri -> icode = CODE_FOR_reload_insi__i_fpul ; return NO_REGS ; } if ( rclass == FPSCR_REGS && ( ( REG_P ( x ) && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) || ( MEM_P ( x ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) ) ) return GENERAL_REGS ; if ( REGCLASS_HAS_FP_REG ( rclass ) && TARGET_SHMEDIA && immediate_operand ( x , mode ) && x != CONST0_RTX ( GET_MODE ( x ) ) && GET_MODE ( x ) != V4SFmode ) return GENERAL_REGS ; if ( ( mode == QImode || mode == HImode ) && TARGET_SHMEDIA && inqhi_operand ( x , mode ) ) { sri -> icode = ( ( mode == QImode ) ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi ) ; return NO_REGS ; } if ( TARGET_SHMEDIA && rclass == GENERAL_REGS && ( GET_CODE ( x ) == LABEL_REF || PIC_ADDR_P ( x ) ) ) return TARGET_REGS ; } if ( ( ( REGCLASS_HAS_FP_REG ( rclass ) && ( REG_P ( x ) && ( GENERAL_OR_AP_REGISTER_P ( REGNO ( x ) ) || ( FP_REGISTER_P ( REGNO ( x ) ) && mode == SImode && TARGET_FMOVD ) ) ) ) || ( REGCLASS_HAS_GENERAL_REG ( rclass ) && REG_P ( x ) && FP_REGISTER_P ( REGNO ( x )

) ) ) && ! TARGET_SHMEDIA && ( mode == SFmode || mode == SImode ) ) return FPUL_REGS ;


<s> SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc = getZeroVector (


<s> switch ( MI . getOperand ( SegOperand ) . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > LoadChains ; unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumVecs ; ++ Idx ) { SDValue Load = DAG . getLoad ( <STR_LIT> , dl , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * <NUM_LIT> ) , commonAlignment ( Alignment , Idx * <NUM_LIT> ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , BasePtr . getValueType ( ) ) ) ; Loads . push_back ( Load ) ; LoadChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isLittleEndian ( ) ) { std :: reverse ( Loads . begin ( ) , Loads . end ( ) ) ; std :: reverse ( LoadChains . begin ( ) , LoadChains . end ( ) ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl


<s> void <ISA_LIT>16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = nullptr ; bool Need<ISA_LIT>16Helper = false ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = llvm :: lower_bound ( <ISA_LIT>16IntrinsicHelper , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast

< GlobalAddressSDNode > ( CLI . Callee ) ) {


<s> case IES_RPAREN : case IES_REGISTER : case IES_OFFSET : State = IES_PLUS ; IC . pushOperator ( IC_PLUS ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) return regsUseUpError ( ErrMsg ) ; IndexReg = TmpReg ; Scale = <NUM_LIT> ; } } break ; } PrevState =


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef _CPU ) : MCAsmBackend ( ) , CPU ( _CPU ) { HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT>

&& CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> if ( CALL_P ( insn ) ) return false ; insn = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == PARALLEL ) insn = XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( insn ) != SET ) return false ; dst = SET_DEST ( insn ) ; if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ix86_function_arg_regno_p ( REGNO ( dst ) ) ) { if ( ! TEST_HARD_REG_BIT ( fixed_reg_set , REGNO ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) ) * is_spilled = true ; return true ; } return false


<s> <ISA_LIT>ConstantPoolValue :: print (


<s> require_pic_register ( NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_FDPIC ) { rtx fdpic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , fdpic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode ,


<s> bool HasFlag = ConstPoolNode && ConstPoolNode -> getTargetFlags ( ) == <STR_LIT> ; bool HasNode = N . getOpcode ( ) == <STR_LIT> ; if ( HasFlag || HasNode ) { Base = N ; return true ; } return false


<s> Value * BasePtr = II . getOperand ( <NUM_LIT> ) ; Value * Index = II . getOperand ( <NUM_LIT> ) ; Type * Ty = II . getType ( ) ; Value * PassThru = ConstantAggregateZero :: get ( Ty ) ; Value * IndexBase ; if ( match ( Index , m_Intrinsic < <STR_LIT> > ( m_Value ( IndexBase ) , m_SpecificInt ( <NUM_LIT> ) ) ) ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Align Alignment = BasePtr -> getPointerAlignment ( II . getModule ( ) -> getDataLayout ( ) ) ; Type * VecPtrTy = PointerType :: getUnqual ( Ty ) ; Value * Ptr = Builder . CreateGEP ( cast < VectorType > ( Ty ) -> getElementType ( ) , BasePtr , IndexBase ) ; Ptr = Builder . CreateBitCast ( Ptr , VecPtrTy ) ; CallInst * MaskedLoad = Builder . CreateMaskedLoad ( Ty , Ptr , Alignment ,


<s> static bool isLegalArithImmed ( uint64_t C ) { return ( C >> <NUM_LIT> == <NUM_LIT> ) || ( ( C & <NUM_LIT> ) == <NUM_LIT> && C >> <NUM_LIT> ==


<s> case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MCID . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Offset = Inst . getOperand ( <NUM_LIT> ) ; if ( ! Offset . isImm ( ) ) break ; if ( ! isIntN ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> , Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ; break ; } } if ( MCID . hasDelaySlot ( ) && Options . isReorder ( ) ) { Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY )

|| ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; MVT SadVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; return SplitOpsAndApply ( DAG , Subtarget , DL , SadVT , { SadOp0 , SadOp1


<s> getAddrModeISOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm5 = MO1


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return false


<s> auto BuildFn = [ & ] ( unsigned SubregIndex ) { auto Ins = MIRBuilder . buildInstr ( TargetOpcode :: INSERT_SUBREG , { DstRC } , { Undef , Scalar } ) . addImm ( SubregIndex ) ; constrainSelectedInstRegOperands ( * Undef , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * Ins , TII , TRI , RBI ) ; return & * Ins ; } ; switch ( EltSize )


<s> return <STR_LIT> ( Opcode ) == Opcode


<s> emit_move_insn ( low [ <NUM_LIT> ] , const0_rtx ) ; if ( count > half_width ) ix86_expand_ashl_const ( high [ <NUM_LIT> ] , count - half_width , mode ) ; } else { gen_shld = mode == DImode ? gen_x86_shld : gen_x86_64_shld ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shld ( high [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; ix86_expand_ashl_const ( low [ <NUM_LIT> ] , count , mode ) ; } return ; } split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; gen_ashl3 = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; if ( operands [ <NUM_LIT> ] == const1_rtx ) { if ( ANY_QI_REG_P ( low [ <NUM_LIT> ] ) && ANY_QI_REG_P ( high [ <NUM_LIT> ] ) ) { rtx s , d , flags = gen_rtx_REG ( CCZmode , FLAGS_REG ) ; ix86_expand_clear ( low [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; emit_insn ( gen_testqi_ccz_1 ( operands [ <NUM_LIT> ] , GEN_INT ( half_width ) ) ) ; d = gen_lowpart ( QImode , low [ <NUM_LIT> ] ) ; d = gen_rtx_STRICT_LOW_PART ( VOIDmode , d ) ; s = gen_rtx_EQ ( QImode , flags , const0_rtx ) ; emit_insn ( gen_rtx_SET ( d , s ) ) ; d = gen_lowpart ( QImode , high [ <NUM_LIT> ] ) ; d = gen_rtx_STRICT_LOW_PART ( VOIDmode , d ) ; s = gen_rtx_NE ( QImode , flags , const0_rtx ) ; emit_insn ( gen_rtx_SET ( d , s ) ) ; } else { machine_mode half_mode ; rtx ( * gen_lshr3 ) ( rtx , rtx , rtx ) ; rtx ( * gen_and3 ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor3 ) ( rtx , rtx , rtx ) ; HOST_WIDE_INT bits ; rtx x ; if ( mode == DImode ) { half_mode = SImode ; gen_lshr3 = gen_lshrsi3 ; gen_and3 = gen_andsi3 ; gen_xor3 = gen_xorsi3 ; bits = <NUM_LIT> ; } else { half_mode = DImode ; gen_lshr3 = gen_lshrdi3 ; gen_and3 = gen_anddi3 ; gen_xor3 = gen_xordi3 ; bits = <NUM_LIT> ; } if ( TARGET_PARTIAL_REG_STALL && ! optimize_insn_for_size_p ( ) ) x = gen_rtx_ZERO_EXTEND ( half_mode , operands [ <NUM_LIT> ] ) ; else x = gen_lowpart ( half_mode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( high [ <NUM_LIT> ] , x ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( bits


<s> if ( width != <NUM_LIT> && ( ! TARGET_64BIT || width != <NUM_LIT> ) ) return false ; if ( bitpos % BITS_PER_UNIT != <NUM_LIT> ) return false ; if ( MEM_ALIGN ( op )


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID


<s> bool <ISA_LIT>FrameLowering :: enableStackSlotScavenging ( const MachineFunction & MF


<s> void markPhysRegUsed ( unsigned PhysReg ) override { MIRBuilder . getMRI ( )


<s> SMShadowTracker . emitShadowPadding ( OutStreamer , getSubtargetInfo ( ) ) ; SM . recordStackMap ( MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SMShadowTracker . reset (


<s> break ; case E_BLKmode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += ( ( int_size_in_bytes ( arg . type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += <NUM_LIT> ; break ; case E_TImode


<s> if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; }


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( false ) ; EmitTST ( STI , Out , Reg ) ; Out . EmitInstruction ( Saved [ <NUM_LIT>


<s> bool can_invert_condition ( void ) const { return reg_dead_after_insn ( XEXP ( branch_condition_rtx ( ) , <NUM_LIT>


<s> Target & llvm :: getThe<ISA_LIT>Target


<s> return ( uint32_t ) __builtin_neon_vget_laneuv2si ( ( int32x2_t ) __a ,


<s> bool reg1 = save_p ( i + <NUM_LIT> , leaf_function ) ; machine_mode mode ; int regno ; if ( reg0 && reg1 ) { mode = SPARC_INT_REG_P ( i ) ? DImode : DFmode ; regno = i ; } else if ( reg0 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i ; } else if ( reg1 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i + <NUM_LIT> ; offset += <NUM_LIT> ; } else { if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; continue ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( VOIDmode , mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 ) = <NUM_LIT> ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) ; set2 = gen_rtx_SET ( VOIDmode , mem , gen_rtx_REG ( SImode , regno + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( set2 ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; } } else emit_move_insn ( gen_rtx_REG ( mode , regno ) , mem ) ; offset = ( offset + <NUM_LIT> ) & - <NUM_LIT> ; } } return offset


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase


<s> ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getWinAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case TouchAndSub : Offset = Amount ; break ; case Probe : Offset = <NUM_LIT> ; break ; } } else if ( MI . isCall ( ) || isPushPop ( MI ) ) { Offset = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { Offset -= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( MI . getOpcode ( ) == <STR_LIT> ||


<s> return ( int32x4_t ) __builtin_neon_vqdmullv4hi ( __a ,


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName =


<s> static bool rx_allocate_stack_slots_for_args (


<s> } auto OpIsZero = [ N ] ( size_t OpNo ) { if ( ConstantSDNode * OpConst = dyn_cast < ConstantSDNode > ( N -> getOperand ( OpNo ) ) ) if ( OpConst -> getZExtValue ( ) == <NUM_LIT> ) return true ; return false ; } ; bool IsAccum = ! ( OpIsZero ( <NUM_LIT> ) && OpIsZero ( <NUM_LIT> ) ) ; const uint16_t * Opcodes = IsUnsigned ? OpcodesU : OpcodesS ; if ( IsSub ) Opcodes += <NUM_LIT> * Stride ; if ( IsExchange ) Opcodes += <NUM_LIT> * Stride ; if ( IsAccum ) Opcodes += Stride ; uint16_t Opcode = Opcodes [ TySize ] ; SDLoc Loc ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsAccum ) { Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand


<s> if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue V = combineAddOrSubToHADDorHSUB ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt


<s> case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) || ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) ) OS << <STR_LIT> ; else if ( Kind != MCSymbolRefExpr :: VK_None ) OS


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> bool Thumb2ITBlockPass :: MoveCopyOutOfITBlock ( MachineInstr * MI , <STR_LIT> CC , <STR_LIT> OCC , SmallSet < unsigned , <NUM_LIT> > & Defs , SmallSet < unsigned , <NUM_LIT> > & Uses ) { if ( ! isCopy ( MI ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs .


<s> case <NUM_LIT> : insn -> opcodeRegister = ( Reg ) ( MODRM_REG_AX + ( ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) | insn -> opcodeModifier ) ) ; break ; case <NUM_LIT> : insn -> opcodeRegister = ( Reg ) ( MODRM_REG_EAX + + ( ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) | insn -> opcodeModifier ) ) ; break ; case <NUM_LIT> : insn -> opcodeRegister = ( Reg ) ( MODRM_REG_RAX + ( ( bFromREX ( insn -> rexPrefix ) <<


<s> MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return


<s> if ( ( MEM_P ( x ) || ( ( GET_CODE ( x ) == SUBREG || REG_P ( x ) ) && ( true_regnum ( x ) == -

<NUM_LIT> || true_regnum ( x ) >= FIRST_PSEUDO_REGISTER ) ) ) && ! reg_class_subset_p ( rclass , EIGHT_REGS ) ) return EIGHT_REGS ;


<s> rtx base_reg , val ; n = INTVAL ( xop1 ) ; if ( mode == DImode || mode == DFmode ) { low_n = n & <NUM_LIT> ; n &= ~ <NUM_LIT> ; if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = plus_constant ( Pmode , base_reg , low_n ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode ,


<s> std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & IT : * MBB ) { if ( IT . getOpcode ( ) != <STR_LIT> ) continue ; RDA . getReachingLocalUses ( & IT , <STR_LIT> , ITBlocks [ & IT ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > RemoveITs ; for ( auto * Dead : Killed ) { if ( MachineOperand * MO = Dead -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA . getMIOperand ( Dead , * MO ) ; RemoveITs . insert ( IT ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( Dead ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ! ModifiedITs . empty ( ) ) return false ; Killed . insert ( RemoveITs . begin ( ) , RemoveITs . end ( ) ) ; return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; if ( ! RDA . isSafeToRemove ( MI , Uses , Ignore ) ) return false ; if ( WontCorruptITs ( Uses , RDA ) ) { ToRemove . insert ( Uses . begin ( ) , Uses . end ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ; for ( auto * Use : Uses ) dbgs ( ) << <STR_LIT> << * Use ) ; SmallPtrSet < MachineInstr * , <NUM_LIT>


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT>


<s> } if ( code == GTU ) { cop0 = force_reg ( mode , cop0 ) ; switch ( mode ) { case V16SImode : case V8DImode : case V8SImode : case V4DImode : case V4SImode : case V2DImode : { rtx t1 , t2 , mask ; rtx ( * gen_sub3 ) ( rtx , rtx , rtx ) ; switch ( mode ) { case V16SImode : gen_sub3 = gen_subv16si3 ; break ; case V8DImode : gen_sub3 = gen_subv8di3 ; break ; case V8SImode : gen_sub3 = gen_subv8si3 ; break ; case V4DImode : gen_sub3 = gen_subv4di3 ; break ; case V4SImode : gen_sub3 = gen_subv4si3 ; break ; case V2DImode : gen_sub3 = gen_subv2di3 ; break ; default : gcc_unreachable ( ) ; } mask = ix86_build_signbit_mask ( mode , true , false ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t1 , cop0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t2 , cop1 , mask ) ) ; cop0 = t1 ; cop1 = t2 ; code = GT ; } break ; case V64QImode : case V32HImode : case V32QImode : case V16HImode : case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; cop0 = x ; cop1 = CONST0_RTX ( mode ) ; code = EQ ; * negate = ! *


<s> if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth == <NUM_LIT> || DataWidth == <NUM_LIT> ) && ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( )


<s> for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL


<s> const <ISA_LIT>FrameLowering * getFrameLowering


<s> return selectAddrModeUnscaled ( Root , <NUM_LIT>


<s> if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EVT , Base , DAG , MFI , TLI ) ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Base ) ; if ( isBaseAlignmentOfN ( <NUM_LIT> , Base -> getOperand ( <NUM_LIT> ) . getNode ( ) , TLI ) ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) ) ; return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue

( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> getAlignment ( ) ) ;


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned ZMask = <NUM_LIT> ; int V1DstIndex = - <NUM_LIT> ; int V2DstIndex = - <NUM_LIT> ; bool V1UsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == Mask [ i ] ) { V1UsedInPlace = true ; continue ; } if ( V1DstIndex >= <NUM_LIT> || V2DstIndex >= <NUM_LIT> ) return false ; if ( Mask [ i ] < <NUM_LIT> ) { V1DstIndex = i ; } else { V2DstIndex = i ; } } if ( V1DstIndex < <NUM_LIT> &&


<s> unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( Value ) { Value -> first = FrameReg ; Value -> second = Offset ; } if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg ,


<s> void DecodeUNPCKHMask ( MVT VT , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = l + NumLaneElts / <NUM_LIT> , e


<s> bool hasDSP ( ) const { return HasDSP


<s> if ( RegNo > <NUM_LIT> || ( RegNo & <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; RegNo >>=


<s> Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; switch ( VT . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : break ; case <NUM_LIT> : { Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; SDValue Shift = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , VT , Op , Shift ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Shift ) ; break ; } case <NUM_LIT> : { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; break ; } case <NUM_LIT> : { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , Tmp ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } return Op ; } APInt KnownZero , KnownOne ; DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; unsigned NumSignificantBits = ( ~ KnownZero ) . getActiveBits ( ) ; if ( NumSignificantBits == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; int64_t OrigBitSize = VT . getSizeInBits ( ) ; int64_t BitSize = ( int64_t ) <NUM_LIT> << Log2_32_Ceil ( NumSignificantBits ) ; BitSize = std :: min ( BitSize , OrigBitSize ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL ,


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , CalleeReg , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; }


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || (

<NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg )


<s> MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT>


<s> break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLD ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * Sym = MCSymbolRefExpr :: create ( MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) , SRVK , Ctx ) ; bool UseGot = MMI -> getModule ( ) -> getRtLibUseGOT ( ) ; if ( Is64Bits ) { bool NeedsPadding = SRVK == MCSymbolRefExpr :: VK_TLSGD ; if ( NeedsPadding ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; const MCSymbol * TlsGetAddr = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; if ( NeedsPadding ) { if ( ! UseGot ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; } if ( UseGot ) { const MCExpr * Expr = MCSymbolRefExpr :: create (

TlsGetAddr , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ;


<s> rtx reg = gen_rtx_REG ( Pmode , IQ2000_TEMP2_REGNUM ) ; rtx offset_rtx = GEN_INT ( offset ) ; emit_move_insn ( reg , offset_rtx ) ; emit_insn ( gen_addsi3 ( reg ,


<s> bool <ISA_LIT>TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasAVX512 ( ) && ! LoadVT . isVector ( ) && BitcastVT .

isVector ( ) && BitcastVT . getVectorElementType ( ) == <STR_LIT> ) return false ;


<s> return ( __m256i ) __builtin_ia32_vcvtph2udq256_mask ( __A , ( __v8si ) _mm256_setzero_si256 ( )


<s> rtvec v = rtvec_alloc ( <NUM_LIT> ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , &


<s> if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ; } return SDValue ( )


<s> printIntelMemReference ( MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false


<s> } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i


<s> return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = <STR_LIT> ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( ValueTy ) ) ; CallInst * CI = Builder . CreateCall ( Ldxr , Addr ) ; CI -> addParamAttr ( <NUM_LIT> , Attribute :: get ( Builder . getContext ( ) , Attribute :: ElementType , ValueTy ) ) ; Value * Trunc = Builder . CreateTrunc ( CI , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , ValueTy


<s> else type ++ ; } if ( found && res == AARCH64_PARSE_OK ) { bool found_subtype = true ; while ( found_subtype ) { found_subtype = false ; const aarch64_branch_protect_type * subtype = type -> subtypes ; while ( str && subtype && subtype -> name && ! found_subtype && res == AARCH64_PARSE_OK ) { if ( strcmp ( str , subtype -> name ) == <NUM_LIT> ) { found_subtype = true ; res = subtype -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , <STR_LIT> , & token_save ) ; } else subtype ++ ; } } } else if ( ! found ) res = AARCH64_PARSE_INVALID_ARG ; } } if ( last_str ) { if ( str ) strcpy ( * last_str , str ) ; else * last_str = NULL ; } if ( res


<s> Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegN >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return Binary


<s> if ( Is64Bit ) return & <STR_LIT> ; else return & <STR_LIT> ; } return NULL


<s> static DecodeStatus DecodeTAddrModeImm7 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) )


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm


<s> if ( FP_REGNUM_P ( dst_regno ) && GP_REGNUM_P ( src_regno ) ) { src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; if ( mode == TImode ) { emit_insn ( gen_aarch64_movtilow_di ( dst , src_lo ) ) ; emit_insn ( gen_aarch64_movtihigh_di ( dst , src_hi ) ) ; } else { emit_insn ( gen_aarch64_movtflow_di ( dst , src_lo ) ) ; emit_insn ( gen_aarch64_movtfhigh_di ( dst , src_hi ) ) ; } return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; if ( mode == TImode ) { emit_insn ( gen_aarch64_movdi_tilow ( dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_tihigh ( dst_hi , src ) ) ; } else { emit_insn ( gen_aarch64_movdi_tflow ( dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_tfhigh ( dst_hi , src ) ) ; } return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart_mode ( word_mode , mode , src ) ; if ( reg_overlap_mentioned_p ( dst_lo , src_hi ) ) { aarch64_emit_move ( dst_hi , src_hi ) ; aarch64_emit_move ( dst_lo


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { SignedCmp = true ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { SignedCmp = false


<s> if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( Write -> comesBefore ( Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { bool BaseFirst = Base -> comesBefore ( Offset ) ; LoadInst * Dominator = BaseFirst ? Base : Offset ; LoadInst * Dominated = BaseFirst ? Offset : Base ; if ( RAWDeps . count ( Dominated ) ) { InstSet & WritesBefore = RAWDeps [ Dominated ] ; for ( auto Before : WritesBefore ) { if ( Dominator -> comesBefore ( Before ) ) return false ; } } return true ; } ; for ( auto * Base : Loads ) { for ( auto * Offset : Loads ) { if ( Base == Offset || OffsetLoads . count ( Offset ) ) continue ; if ( isConsecutiveAccess ( Base , Offset , * DL , * SE ) && SafeToPair ( Base , Offset ) ) { LoadPairs [ Base ] = Offset ; OffsetLoads . insert ( Offset ) ; break ; } } } LLVM_DEBUG ( if ( ! LoadPairs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; for ( auto & MapIt : LoadPairs ) { LLVM_DEBUG ( dbgs ( ) << * MapIt . first <<

<STR_LIT> << * MapIt . second << <STR_LIT> ) ;


<s> unsigned int <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int &


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON


<s> return __builtin_ia32_comisdle ( ( __v2df ) __A , (


<s> assert ( getStreamer ( ) . Contents . empty ( ) && <STR_LIT> ) ; CurrentVendor =


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_ostream &

OS , MCCodeEmitter * Emitter , bool RelaxAll ) {


<s> return Kind == Memory && ( ! Mem . Size


<s> static SDNode * SelectInt64 ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl (


<s> static bool expandNOVLXLoad ( MachineInstrBuilder & MIB , const TargetRegisterInfo * TRI , const MCInstrDesc & LoadDesc , const MCInstrDesc & BroadcastDesc , unsigned SubIdx ) { unsigned DestReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TRI -> getEncodingValue ( DestReg ) < <NUM_LIT> ) { MIB -> setDesc ( LoadDesc ) ; } else { MIB -> setDesc ( BroadcastDesc ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg (


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase &


<s> if ( reg && ix86_check_avx256_register (


<s> auto GetPackNode = [ ] ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget -> hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG .


<s> return __builtin_loongson_punpckhhw_u ( s ,


<s> return ( ( vec_ullong2 ) ( si_dfceq ( ( qword ) ( a ) , ( qword ) (


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; if ( RPI . IsGPR ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg (


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( )


<s> void <ISA_LIT>CodeEmitter :: emitInstruction ( const MachineInstr & MI ) { DEBUG ( errs ( ) << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << MI ) ; MCE . processDebugLoc ( MI . getDebugLoc ( ) , true ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; emitWord ( getBinaryCodeForInstr ( MI ) ) ; ++ NumEmitted ; MCE . processDebugLoc ( MI . getDebugLoc ( ) , false


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] .


<s> unsigned rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool hasAsi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned asi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler


<s> static DecodeStatus DecodeGR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT>


<s> if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue ShufPS = lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ; return DAG . getBitcast ( <STR_LIT> , ShufPS ) ; } if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask

, Zeroable , Subtarget , DAG ) ) return Blend ;


<s> return pParent . getTarget ( ) . getGOT


<s> static DecodeStatus DecodeBranch16Target ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int BranchOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( BranchOffset > <NUM_LIT> ) BranchOffset = -

<NUM_LIT> * ( <NUM_LIT> - BranchOffset ) ;