<s> if ( ST -> hasMVEFloatOps ( ) ) { Opc = <STR_LIT> ; break ; } else { Invert = true ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue TmpOp0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 , Op0 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue TmpOp1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 , Op1 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; if ( Invert ) Result = DAG . getNOT ( dl , Result , VT ) ; return Result ; } case <STR_LIT> : Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue TmpOp0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 , Op0 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue TmpOp1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 , Op1 , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; if ( Invert ) Result = DAG . getNOT ( dl , Result , VT ) ; return Result ; } } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ST -> hasMVEIntegerOps ( ) ) { Opc = <STR_LIT> ; break ; } else { Invert = true ; LLVM_FALLTHROUGH ; } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( Is<ISA_LIT>64


<s> InstructionCost <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , CmpInst :: Predicate VecPred , TTI :: TargetCostKind CostKind , const Instruction * I ) { InstructionCost Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind , I ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; return vectorCostAdjustment ( Cost , Opcode ,


<s> if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode

) ? <NUM_LIT> : materializeFP ( CFP , VT ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; MVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const Value * Op2 = I . getArgOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = FuncInfo . CreateRegs ( I . getType ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned Opc = <STR_LIT> ; if ( I . getIntrinsicID ( ) == <STR_LIT> ) Opc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg + <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { assert ( ! MI . isBundle ( ) && <STR_LIT> ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF


<s> static bool moxie_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REG ; * p2 = INVALID_REGNUM ; return true


<s> tree ix86_handle_selectany_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) == VAR_DECL && TREE_PUBLIC ( * node ) && ( DECL_INITIAL ( * node ) || TYPE_NEEDS_CONSTRUCTING ( TREE_TYPE ( * node ) ) ) ) make_decl_one_only ( * node ) ; else { error ( <STR_LIT> <STR_LIT> , IDENTIFIER_POINTER (


<s> SDLoc dl ( Op ) ; const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_i64gather_ps ( __m128 src , float const * base , __m128i index , __m128 mask , const int scale ) { return ( __m128 ) __builtin_ia32_gatherdiv4sf ( ( __v4sf ) src , base , ( __v2di ) index , ( __v4sf ) mask


<s> } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( )


<s> bool FPNeedsSetting = hasFP ( MF ) ; for ( ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( FPNeedsSetting && MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { int64_t X29FrameIdx = MBBI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; FuncInfo -> setFramePointerOffset ( MFI -> getObjectOffset ( X29FrameIdx ) ) ; ++ MBBI ; emitRegUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , <STR_LIT> , <STR_LIT> , NumInitialBytes + MFI -> getObjectOffset ( X29FrameIdx ) , MachineInstr :: FrameSetup ) ; MFI -> setOffsetAdjustment ( - MFI -> getObjectOffset ( X29FrameIdx ) - MFI -> getStackSize ( ) ) ; if ( NeedsFrameMoves ) { MCSymbol * FPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( FPLabel ) ; unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = MFI -> getObjectOffset ( X29FrameIdx ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( FPLabel , Reg , Offset ) ) ; } FPNeedsSetting = false ; } if ( ! MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) break ; } assert ( ! FPNeedsSetting && <STR_LIT> ) ; emitSPUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , - NumResidualBytes , MachineInstr :: FrameSetup ) ; if ( ! NeedsFrameMoves ) return ; MCSymbol * CSLabel = <NUM_LIT> ; if ( ! hasFP ( MF ) && NumResidualBytes ) { CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = NumResidualBytes + NumInitialBytes ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( CSLabel , Reg , - Offset ) ) ; } const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { if ( ! CSLabel ) { CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; } for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = MRI -> getDwarfRegNum ( I -> getReg ( ) , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , Reg , Offset )


<s> for ( unsigned i = <NUM_LIT> ; i != StackTop ; ++ i ) { dbgs ( ) << <STR_LIT> << Stack [ i ] ; assert ( RegMap [ Stack [ i ] ] == i && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumPendingSTs ; ++ i ) dbgs ( ) << <STR_LIT> << i << <STR_LIT> << unsigned ( PendingST


<s> vpminq_f64 ( float64x2_t a , float64x2_t b ) { return __builtin_aarch64_smin_nanpv2df ( a ,


<s> if ( VA . needsCustom ( ) ) continue ; report_fatal_error ( <STR_LIT> ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; EVT ValVT = VA . getValVT ( ) ; MVT LocVT = VA . getLocVT ( ) ; <STR_LIT> SVT = ValVT . getSimpleVT ( ) . SimpleTy ; unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassForSVT ( SVT , Is<ISA_LIT>64 ) ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; if ( ValVT . isScalarInteger ( ) && ( ValVT . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ) { <STR_LIT> Flags = Ins [ VA . getValNo ( ) ] . Flags ; ArgValue = truncateScalarIntegerArg ( Flags , ValVT , DAG , ArgValue , LocVT


<s> return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { assert ( ( VT . is128BitVector ( ) || Subtarget . hasAVX2 ( ) ) && <STR_LIT> ) ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast (


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> ComplexRendererFns selectAddrModeUnscaled8 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT VT1 , EVT


<s> if ( optimize == <NUM_LIT> || ! flag_schedule_insns_after_reload ) return ! satisfies_constraint_Da ( mem ) || MEM_VOLATILE_P ( mem ) ; if ( current_pass == NULL ) return false ; const char * pass_name = current_pass -> name ; if ( pass_name && ( ( strcmp ( pass_name , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp ( pass_name ,

<STR_LIT> ) == <NUM_LIT> ) ) ) return ! satisfies_constraint_Da ( mem ) || MEM_VOLATILE_P ( mem ) ;


<s> virtual void initializePass ( ) override { pushTTIStack ( this )


<s> UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; HasLEB128 = true ; ExceptionsType = ExceptionHandling ::


<s> SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N ,


<s> void ix86_output_patchable_area ( unsigned int patch_area_size , bool record_p


<s> if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent (


<s> unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX


<s> printSymbolOperand ( P , MI -> getOperand ( Op + <NUM_LIT> ) , O ) ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) O << <STR_LIT> ; if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( P , MI , Op , O , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( P , MI , Op + <NUM_LIT> , O , Modifier ) ; unsigned ScaleVal = MI -> getOperand ( Op


<s> x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , of ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , x ) ) ; } else if ( of == CONST0_RTX ( mode ) ) { x = gen_rtx_AND ( mode , cmp , ot ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , x ) ) ; } else { rtx t , f ; t = gen_reg_rtx ( mode ) ; x = gen_rtx_AND ( mode , cmp ,


<s> void addTraceSyncBarrierOptOperands ( MCInst & Inst , unsigned N )


<s> for ( int i = <NUM_LIT> ; i != ( int ) NumElts ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i ) break ; ++ SubvecElts ; } assert ( SubvecElts != NumElts && <STR_LIT> ) ; SubvecElts = PowerOf2Floor ( SubvecElts ) ; if ( Zeroable . countLeadingOnes ( ) >= ( NumElts - SubvecElts ) ) { MVT ExtractVT = <STR_LIT> ( <STR_LIT> , SubvecElts ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , Extract , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( NumElts >= <NUM_LIT> || ( Subtarget . hasDQI ( ) && NumElts == <NUM_LIT> ) ) { unsigned Offset = <NUM_LIT> ; for ( SDValue V : { V1 , V2 } ) { unsigned Opcode ; int ShiftAmt = match1BitShuffleAsKSHIFT ( Opcode , Mask , Offset , Zeroable ) ; if ( ShiftAmt >= <NUM_LIT> ) return DAG . getNode ( Opcode , DL , VT , V , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; Offset += NumElts ; } } MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . canExtendTo512DQ ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; ExtVT = Subtarget . canExtendTo512BW ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT ,


<s> case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandBranchImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandCondBranches ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandDiv ( Inst , IDLoc , Instructions , false , true ) ; case <STR_LIT> : return expandDiv ( Inst , IDLoc , Instructions , true , true ) ; case <STR_LIT> : return expandDiv ( Inst , IDLoc , Instructions


<s> const MCExpr * ImmVal ; SMLoc ExprLoc = getLoc ( ) ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; unsigned Opt = <STR_LIT> ( ) . fromString ( Tok . getString ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Mnemonic == <STR_LIT> && Opt != <STR_LIT> ) { TokError ( <STR_LIT> ) ; return


<s> Op -> PSBHint . Val = Val ; Op -> PSBHint . Data = Str . data ( ) ; Op -> PSBHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) ,


<s> machine_mode memory_vector_mode ( const function_instance & ) const override { return m_mode


<s> unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned QuotReg = FastEmitInst_rr ( DivOpc , RC , Src0Reg , false , Src1Reg , false ) ; assert ( QuotReg && <STR_LIT> ) ; unsigned ResultReg = FastEmitInst_rrr ( MSubOpc , RC , QuotReg , true , Src1Reg , Src1IsKill , Src0Reg , Src0IsKill ) ; UpdateValueMap ( I , ResultReg ) ; return true


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> else return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; } SDValue LowerSatConstant ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( )


<s> if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } if ( FlagSfiDisableCP


<s> } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else


<s> PredicationCode = <STR_LIT> ; CarrySetting = false ; ProcessorIMod = <NUM_LIT> ; if ( ( Mnemonic == <STR_LIT> && isThumb ( ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) return Mnemonic ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) { unsigned CC = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode =


<s> return create ( VK_<ISA_LIT>_HA , Expr , IsDarwin ,


<s> bool isLegalMaskedScatter ( Type * Ty


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Info . SwiftErrorVReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! mayTailCallThisCC ( CalleeCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Info . IsVarArg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( any_of ( CallerF . args ( ) , [ ] ( const Argument & A ) { return A . hasByValAttr ( ) || A . hasInRegAttr


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter & Printer , bool IsDarwin ) { MCContext & Ctx = Printer . OutContext ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; unsigned access = MO . getTargetFlags ( ) & <STR_LIT> ; switch ( access ) { case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) ->


<s> MIB . addUse ( PhysReg , RegState :: Implicit ) ; unsigned ExtReg = extendRegister ( ValVReg , VA


<s> bool isMemImm12Offset ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_REL32 ; break ; case MCSymbolRefExpr :: VK_TLSGD : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == <NUM_LIT> ) ; if ( Vector && ! ST -> hasSSE1 ( ) ) return <NUM_LIT> ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } return


<s> void addFBits16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - CE ->


<s> case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; }


<s>
if
(
(
mask
&
RELOAD_REG_VALID
)
!=
<NUM_LIT>
)
*
p
++
=
'v'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_MULTIPLE
)
!=
<NUM_LIT>
)
*
p
++
=
'm'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_INDEXED
)
!=
<NUM_LIT>
)
*
p
++
=
'i'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_QUAD_OFFSET
)
!=
<NUM_LIT>
)
*
p
++
=
'O'
;
else
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
<NUM_LIT>
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
<NUM_LIT>
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
<NUM_LIT>
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { llvm_unreachable ( <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> X = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Add1 , CurDAG -> getZExtOrTrunc ( Add0 , DL , SubVT ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , X ) ; } else return false ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , X ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewShiftAmt ) ; if ( UpdatedNode !=


<s> static rtx moxie_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < <NUM_LIT> ) return gen_rtx_REG ( mode , * cum ) ; else return


<s> static bool MorphToI32Reg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT>


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv ::


<s> Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx +


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName ,


<s> return condition_rtx_in_insn != NULL ? *


<s> Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI . reg_nodbg_empty ( VirtReg ) ) continue ; if ( MRI . getRegClass ( VirtReg ) -> getID ( ) != <STR_LIT> ) continue ; unsigned Index = VRM . getPhys ( VirtReg ) - <STR_LIT> ; if ( ! Phys2Virt [ Index ] ) Phys2Virt [ Index ] = VirtReg ; } for ( unsigned I = <NUM_LIT> ; I < AMXRegNum ; ++ I ) { if ( ! Phys2Virt [ I ] ) continue ; DebugLoc DL ; bool IsRow = true ; MachineInstr * NewMI = nullptr ; ShapeT Shape = VRM . getShape ( Phys2Virt [ I ] ) ; for ( auto & R : { Shape . getRow ( ) -> getReg ( ) , Shape . getCol ( ) -> getReg ( ) } ) { int64_t Imm = INT64_MAX ; int Offset = IsRow ? <NUM_LIT> + I : <NUM_LIT> + I * <NUM_LIT> ; for ( auto & DefMI : MRI . def_instructions ( R ) ) { MachineBasicBlock & MBB = * DefMI . getParent ( ) ; if ( DefMI . isMoveImmediate ( ) ) { if ( Imm != INT64_MAX ) { assert ( Imm == DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) && <STR_LIT> ) ; continue ; } Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; NewMI = addFrameReference ( BuildMI ( MF . front ( ) , ++ ConstMI -> getIterator ( ) , DL , TII -> get ( IsRow ? <STR_LIT> : <STR_LIT> ) ) , SS , Offset ) . addImm ( Imm ) ; ConstMI = NewMI ; LIS . InsertMachineInstrInMaps ( * NewMI ) ; } else { unsigned SubIdx = IsRow ? <STR_LIT> : <STR_LIT> ; unsigned RegSize = TRI -> getRegSizeInBits ( * MRI


<s> if ( do_begin_end ) fprintf ( stream , <STR_LIT> ) ; if ( ( value < ( int64_t ) <NUM_LIT> && value > ( int64_t ) - <NUM_LIT> ) || ( value >= ( int64_t

) <NUM_LIT> && value <= ( int64_t ) <NUM_LIT> ) ) fprintf ( stream , <STR_LIT> , ( int ) value ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> CC , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CondCode ) ; Op -> CC . Val = CC ; Op -> StartLoc =


<s> const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { assert ( opA != <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm5 ( insn ) ) ) ; ++ OpIdx ; }


<s> } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ; if ( isa < InsertElementInst > ( LoadUser ) ) IsVectorAccess = true ; } if ( IsFPAccess || IsVectorAccess ) return AddressingMode ( false , true ) ; } return AddressingMode ( true


) _mm512_setzero_si512 ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant ( InNVT . getVectorNumElements ( ) , DL ,


<s> if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) ) ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } else if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelSLM ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT> ) { <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasLZCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPRFCHW =


<s> while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( * MI ) ; ++ MI ; } skipNonTerminators ( Position , Block ) ; while ( MI != End ) { if ( ! MI -> isDebugInstr ( ) ) { assert ( MI -> isTerminator ( ) && <STR_LIT> ) ; Terminators . push_back ( describeTerminator ( *


<s> return getEstimate ( * Subtarget , DCI , <STR_LIT> , Operand , ExtraSteps


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return emitCustomConstantPool ( MI ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer ,


<s> __arm_uqrshll_sat48 ( uint64_t value , int32_t shift ) { return __builtin_mve_uqrshll_sat48_di ( value


<s> FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > I = df_ext_begin ( Entry , Processed )

, E = df_ext_end ( Entry , Processed ) ;


<s> else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , true ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI


<s> return MCDisassembler :: Success ; } unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; if ( RegNo == <NUM_LIT> )


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue Glue = emitCmp ( DAG , DL , C ) ; SDValue Ops [ ] = { TrueOp , FalseOp , DAG . getConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getConstant ( C . CCMask , DL , <STR_LIT> ) , Glue } ; return DAG . getNode ( <STR_LIT> , DL , Op .


<s> if ( load_p ) { reg1 = operands [ <NUM_LIT> ] ; reg2 = operands [ <NUM_LIT> ] ; mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } else { reg1 = operands [ <NUM_LIT> ] ; reg2 = operands [ <NUM_LIT> ] ; mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } if ( loongarch_address_insns ( XEXP ( mem1 , <NUM_LIT> ) , mode , false ) == <NUM_LIT> || loongarch_address_insns ( XEXP ( mem2 , <NUM_LIT> ) , mode , false ) == <NUM_LIT> ) return false ; loongarch_split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; loongarch_split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; if ( ! REG_P ( base1 ) || ! rtx_equal_p ( base1 , base2 ) ) return false ; if ( load_p && ( REGNO ( reg1 ) == REGNO ( base1 ) || ( REGNO ( reg2 ) == REGNO ( base1 ) ) ) ) return false ; if ( load_p && REGNO ( reg1 ) == REGNO ( reg2 ) ) return false ; rc1 = REGNO_REG_CLASS ( REGNO ( reg1 ) ) ; rc2 = REGNO_REG_CLASS ( REGNO ( reg2 ) ) ; if ( rc1 != rc2 && ! reg_class_subset_p ( rc1 , rc2 ) && ! reg_class_subset_p ( rc2 , rc1 ) ) return false ; if ( abs ( offset1 - offset2 ) != GET_MODE_SIZE ( mode ) ) return false ; return


<s> break ; case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx )


<s> <ISA_LIT>CallEntry :: <ISA_LIT>CallEntry ( const


<s> if ( STI . splitFramePushPop ( ) ) { GPRCS2Size += <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; } unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , & * std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size ) { CFAOffset -= adjustedGPRCS1Size ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; int FI = I -> getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . splitFramePushPop ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI -> getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; break ; } } if ( HasFP ) { FramePtrOffsetInBlock += MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size + ArgRegsSaveSize ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( <STR_LIT> ) . addImm ( FramePtrOffsetInBlock / <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( FramePtrOffsetInBlock )


<s> inline unsigned getRegAsVR128 ( unsigned Reg


<s> assert ( N == <NUM_LIT> && isMemorySIMDNoIndex ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> SDLoc DL ( Op ) ; auto Pg = getPredicateForVector ( DAG , DL , VT ) ; if ( useSVEForFixedLengthVectorVT ( VT , OverrideNEON ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) , OverrideNEON ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( ! V . getValueType ( ) . isVector ( ) || V . getValueType ( ) . isScalableVector (


<s> static bool mep_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( decl == NULL ) return false ; if ( mep_section_tag ( DECL_RTL ( decl ) ) == 'f' ) return


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm (


<s> if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode || m2 == CCNOmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode || m1 == CCNOmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode


<s> return ( unsigned long long ) __builtin_ia32_vcvttsd2usi64 (


<s> unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned Opc ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : Opc = DOpcodes [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : Opc = QOpcodes [ <NUM_LIT> ] ; break ; } SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc ,


<s> return new <ISA_LIT>PassConfig ( this , PM , Subtarget . is64Bit (


<s> void RecordRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { if ( Writer -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> )


<s> static unsigned encodeNEONRn ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegN = get<ISA_LIT>RegisterNumbering ( RegN ) ; Binary |= ( RegN &


<s> return ( REG_P ( x ) && loongarch_regno_mode_ok_for_base_p ( REGNO ( x )


<s> if ( ! isMem ( ) ) return false ; if ( Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return


<s> else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else return MCDisassembler :: Fail ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM == Reloc :: Static ) ; if ( in<ISA_LIT>16Mode ( ) ) HasBitCount


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; MVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutLo = DAG . getSelectCC ( dl , Tmp5 , DAG . getConstant ( <NUM_LIT> , AmtVT )


<s> UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != Flags . getResNo ( ) ) continue ; unsigned UIOpc = UI -> getOpcode ( ) ; if ( UIOpc == <STR_LIT> ) { if ( cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromNode ( * FlagUI ) ; if ( mayUseCarryFlag ( CC ) ) return false ; } continue ; } unsigned CCOpNo ; switch ( UIOpc ) { default : return false ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; } <STR_LIT> CC = ( <STR_LIT> ) UI -> getConstantOperandVal ( CCOpNo ) ; if ( mayUseCarryFlag ( CC ) ) return false ; } return


<s> static section * iq2000_select_rtx_section ( machine_mode mode , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ) { return mergeable_constant_section ( mode , align , <NUM_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const Target & , TargetMachine & TM , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( TM


<s> if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg , <ISA_LIT>Pred ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( Subtarget -> hasSPE ( ) ? <STR_LIT> : <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true


<s> ELFRefKind = <ISA_LIT>MCExpr :: VK_INVALID ; DarwinRefKind = MCSymbolRefExpr :: VK_None ; Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * AE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { ELFRefKind = AE -> getKind ( ) ; Expr = AE -> getSubExpr ( ) ; } const MCSymbolRefExpr * SE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; if ( SE ) { DarwinRefKind = SE -> getKind ( ) ; return true


<s> for ( unsigned I : CSRs ) { BuildMI ( MBB , MBBI , DL , * Insn ) . addReg ( I , IsSave ? RegState :: Undef : RegState :: Define ) . addReg ( Basereg ) . addImm ( Adjust + Idx ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( IsSave ? <STR_LIT> : <STR_LIT> ) << TRI -> getName ( I ) << ( IsSave ? <STR_LIT> : <STR_LIT> ) << ( TRI -> isVirtualRegister

( Basereg ) ? <STR_LIT> : TRI -> getName ( Basereg ) ) << <STR_LIT> << ( Adjust + Idx ) << <STR_LIT> ) ;


<s> bool hasFineGrainedTraps ( ) const { return HasFineGrainedTraps


<s> const InstrItineraryData * getInstrItineraryData (


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { RegisterBankInfo :: InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_GEP : case TargetOpcode :: G_MUL : case TargetOpcode :: G_SDIV : case TargetOpcode :: G_UDIV : case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameKindOfOperandsMapping ( MI ) ; case TargetOpcode :: G_BITCAST : { LLT DstTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT SrcTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Size = DstTy . getSizeInBits ( ) ; bool DstIsGPR = ! DstTy . isVector ( ) ; bool SrcIsGPR = ! SrcTy . isVector ( ) ; const RegisterBank & DstRB = DstIsGPR ? <STR_LIT> : <STR_LIT> ; const RegisterBank & SrcRB = SrcIsGPR ? <STR_LIT> : <STR_LIT> ; return InstructionMapping { DefaultMappingID , copyCost ( DstRB , SrcRB , Size ) , getCopyMapping ( DstRB . getID ( ) , SrcRB . getID ( ) , Size ) , <NUM_LIT> } ; } case TargetOpcode :: G_SEQUENCE : return InstructionMapping ( ) ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : { OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; } case TargetOpcode :: G_FPTOSI : case TargetOpcode ::


<s> bool <STR_LIT> ( int64_t Offset , CodeModel :: Model M , bool hasSymbolicDisplacement ) { if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; if ( ! hasSymbolicDisplacement ) return true ; if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ; if ( M == CodeModel :: Small && Offset < <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ) return true ; if ( M == CodeModel :: Kernel


<s> unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F . getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? & <STR_LIT> : & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI )


<s> return selectBDAddr ( <STR_LIT> , Addr , Base


<s> EVT PtrVT = Op . getValueType ( ) ; BlockAddressSDNode * BASDN = cast < BlockAddressSDNode > ( Op ) ; const BlockAddress * BA = BASDN -> getBlockAddress ( ) ; if ( Subtarget . isSVR4ABI ( ) && ( Subtarget . is<ISA_LIT>64 ( ) || isPositionIndependent ( ) ) ) { if ( Subtarget . is<ISA_LIT>64 ( ) ) setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , SDLoc ( BASDN ) , Subtarget . is<ISA_LIT>64 ( ) , GA ) ; } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag ,


<s> ParseOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal ; <ISA_LIT>Operand * Op ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } return Error ( S , <STR_LIT> ) ; case AsmToken :: Identifier : if ( isDarwin ( ) ) { unsigned RegNo ; int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken


<s> return ResTy ; } else if ( Token . is ( AsmToken :: Integer ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc


<s> bool runOnUse ( Use & U , const PHINodeSet & PromotablePHINodes , B2IMap & BoolToIntMap ) { auto Defs = findAllDefs ( U ) ; if ( llvm :: none_of ( Defs , isa < Instruction , Value * > ) ) return false ; for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const auto * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { auto * First = dyn_cast < User > ( Pair . first ) ; auto * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [


<s> return ( __m128 ) __builtin_ia32_maxps ( ( __v4sf ) __A , (


<s> MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else { unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI .


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCOPY_FD ( MachineInstr & MI , MachineBasicBlock * BB ) const { assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; DebugLoc DL = MI


<s> if ( MO . isReg ( ) ) { rv = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) { rv = <NUM_LIT> >> rv ; } } else if ( MO . isImm ( ) ) { rv = MO . getImm ( ) ; } else if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) { unsigned Reloc = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) Reloc = <STR_LIT> ; else { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; } switch ( MI . getOpcode ( ) ) { default : MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : break ; } const MCExpr * IdVal ; SMLoc S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return


<s> SDLoc DL ( Op ) ; SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op

. getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> virtual void emitAbiVersion ( int AbiVersion ) override { llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI ,


<s> return ( vector unsigned char ) __builtin_altivec_vmaxub ( ( vector signed char ) a1 , ( vector signed char )


<s> bool mayNeedRelaxation ( const MCInst &


<s> if ( match ( Start , m_Intrinsic < <STR_LIT> > ( ) ) ) return ; IRBuilder < > Builder


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg


<s> if ( I . getOpcode ( ) == TargetOpcode :: G_PTR_ADD ) { if ( auto COff = getIConstantVRegSExtVal ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { int64_t Imm = * COff ; if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I . getOperand ( <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printImm8OptLsl ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned UnscaledVal = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Shift = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Shift ) == <STR_LIT> && <STR_LIT> ) ; if ( ( UnscaledVal == <NUM_LIT> ) && ( <STR_LIT> ( Shift ) != <NUM_LIT> ) ) { O << '#' << formatImm ( UnscaledVal ) ; printShifter ( MI , OpNum + <NUM_LIT> , STI , O ) ; return ; } T Val


<s> for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i ) return false ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] < <NUM_LIT> ||

Mask [ i ] > <NUM_LIT> ) ) return false ;


<s> unsigned NextBlockOffset , NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = ++ Water -> getIterator ( ) ; if ( NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber (


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( x


<s> ExtractSubReg = <STR_LIT> ; break ; case <NUM_LIT> : CopyOpc = <STR_LIT> ; ExtractSubReg = <STR_LIT> ; break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EltSize <<


<s> if ( ! addr ) return FALSE ; tree fntype = TREE_TYPE


<s> break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2


<s> water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , NewBB , CompareMBBNumbers ) ; WaterList . insert ( IP ,


<s> if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return


<s> unsigned getReturnRegsCount ( ) const { return ReturnRegsCount


<s> tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx pat ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode2 ) ) op0 = copy_to_mode_reg ( mode2 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode1 , op2 ) ; pat = GEN_FCN ( icode ) ( op1 , op2


<s> if ( isLEA ( MI ) ) List . push_back ( const_cast <


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TargetTriple ) { AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( isPositionIndependent ( ) && Subtarget . isPICStyleGOT ( ) ) ; return MCSymbolRefExpr :: create ( MBB -> getSymbol ( )

, MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> return Kind == k_Register && Reg . Kind ==


<s> MemoryObject * region = static_cast < MemoryObject * > ( arg ) ; return region -> readByte ( address , byte


<s> static __inline unsigned long long sh_media_MSHARD_W ( unsigned long long mm , unsigned int mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_ashrv4hi3 ( ( v4hi ) mm ,


<s> if ( ! Subtarget . hasAVX ( ) || ShuffleVecSize != ExpectedShuffleVecSize || DL . getTypeSizeInBits ( ShuffleEltTy ) != <NUM_LIT> || Factor != <NUM_LIT> ) return false ; return true


<s> return selectAddrRiSpls ( Addr , Base ,


<s> unsigned Get<ISA_LIT>RegNum ( const MCOperand & MO ) const { return Ctx . getRegisterInfo ( ) -> getEncodingValue (


<s> static tree parse_signature ( const function_instance & instance , const char * format , vec < tree > & argument_types ) { tree return_type = parse_type ( instance , format ) ; while ( format [ <NUM_LIT> ] ==


<s> else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r3 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > <NUM_LIT> ) { emit_move_insn ( r12 , GEN_INT


<s> for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) { assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment


<s> bool softPromoteHalfType ( ) const override { return


<s> if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return


<s> unsigned fastEmitInst_riir ( uint64_t inst , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t imm1 , uint64_t

imm2 , unsigned Op3 , bool Op3IsKill ) {


<s> if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t M = RawMask [ i ] ; M &= EltMaskSize ; ShuffleMask . push_back ( ( int


<s> } ; const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return

MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) && SrcVT . isVector ( ) && SrcVT . getVectorNumElements ( ) > <NUM_LIT> ) Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Op ) ) ; else Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue ( <NUM_LIT> ) ) ; } return SDValue (


<s> unsigned RegOpsNum = isMem ( MI , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < <NUM_LIT> || SrcOpIdx1 > RegOpsNum ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < <NUM_LIT> || SrcOpIdx2 > RegOpsNum ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 ==


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MCELFStreamer :: EmitAssemblerFlag ( Flag ) ; switch ( Flag ) { case MCAF_SyntaxUnified : return ; case MCAF_Code16 : IsThumb =


<s> } CC = <STR_LIT> ( CC , ! IsFP ) ; if ( unsigned Opcode = getVectorComparison ( CC , IsFP ) ) { Invert = true ; return Opcode ; } return <NUM_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> void addSImm7s8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE &&


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , dl ) ; SDValue Args [ ] = { Chain , Label , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) } ; Chain = DAG . getNode ( <STR_LIT> ,


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; if ( ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) || MF . hasMSInlineAsm ( ) ) return true ; return


<s> if ( V . getOpcode ( ) == <STR_LIT> && ( isNullConstant ( V . getOperand ( <NUM_LIT> ) ) || V . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { if ( SDValue Not = IsNOT ( V . getOperand ( <NUM_LIT> ) , DAG ) ) { Not = DAG . getBitcast ( V . getOperand ( <NUM_LIT> ) . getValueType ( ) , Not ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Not ) , V . getValueType ( ) , Not , V . getOperand ( <NUM_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( collectConcatOps ( V . getNode ( ) , CatOps ) ) { for ( SDValue & CatOp : CatOps ) { SDValue NotCat = IsNOT ( CatOp , DAG ) ; if ( ! NotCat ) return SDValue


<s> return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_INDNTPOFF : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_TLS_IEENT ; llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLDOReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSLDM : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLDMReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSGD : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSGDReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_GOTENT ; llvm_unreachable ( <STR_LIT>


<s> <ISA_LIT>GenPreLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; return ( ! EnableMinSize ) ? Helper . tryCombineMemCpyFamily ( MI , MaxLen ) : false ; } default : break ; } } if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector (


<s> return isExtImm < <NUM_LIT> > ( true ,


<s> case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerADD ( Op , DAG ) ; case <STR_LIT> : return lowerFP_TO_SINT ( Op


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> )


<s> vmvn_s32 ( int32x2_t __a ) { return ~


<s> if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx


<s> if ( dslots_number_nops > <NUM_LIT> ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == <NUM_LIT> || ( iq2000_load_reg != <NUM_LIT> && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != <NUM_LIT> && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != <NUM_LIT> && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != <NUM_LIT> && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( <STR_LIT> , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; iq2000_load_reg = <NUM_LIT> ; iq2000_load_reg2 = <NUM_LIT> ; iq2000_load_reg3 = <NUM_LIT> ; iq2000_load_reg4 = <NUM_LIT> ; } if ( ( JUMP_P ( insn ) || CALL_P ( insn ) || ( GET_CODE ( PATTERN ( insn

) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) {


<s> if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; Instruction * Call = Builder . CreateCall ( SMLAD , Args ) ; NumSMLAD ++ ; return Call ; } ; Instruction * InsertAfter = R . getRoot ( ) ; Value * Acc = R . getAccumulator ( ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; MulCandList & MulCands = R . getMuls ( ) ; for ( auto & MulCand : MulCands ) { if ( MulCand -> Paired ) continue ; Value * Mul = MulCand -> Root ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Mul << <STR_LIT> ) ; if ( R . getType ( ) != Mul ->


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseScalarRegister ( unsigned & RegNum ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned Reg = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( Reg == <NUM_LIT> )


<s> } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumValues ( ) ; ++ i ) Results . push_back ( Res . getValue (


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) , V1 ) ; } if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget


<s> static void assertUnsignedWidth ( unsigned Width , uint64_t Value , std :: string Description , const MCFixup & Fixup , MCContext * Ctx = nullptr ) { if ( ! isUIntN ( Width , Value


<s> unsigned ctrl = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ctrl == <NUM_LIT> ) { unsigned byte = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( byte ) { case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( ( imm << <NUM_LIT> ) | imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | imm ) ) ; break ; } } else { unsigned unrot = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) | <NUM_LIT> ; unsigned rot = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = ( unrot >> rot ) | ( unrot << (


<s> static DecodeStatus DecodeHIRegsDSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder


<s> } else if ( MEM_P ( dst ) && INT_REGNO_P ( reg ) ) { rtx breg ; if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_DEC ) { rtx delta_rtx ; breg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; delta_rtx = ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC ? GEN_INT ( GET_MODE_SIZE ( GET_MODE ( dst ) ) ) : GEN_INT ( - GET_MODE_SIZE ( GET_MODE ( dst ) ) ) ) ; if ( TARGET_UPDATE ) { rtx nsrc = simplify_gen_subreg ( reg_mode , src , mode , <NUM_LIT> ) ; emit_insn ( TARGET_32BIT ? ( TARGET_POWERPC64 ? gen_movdi_si_update ( breg , breg , delta_rtx , nsrc ) : gen_movsi_update ( breg , breg , delta_rtx , nsrc ) ) : gen_movdi_di_update ( breg , breg , delta_rtx , nsrc ) ) ; used_update = true ; } else emit_insn ( gen_add3_insn ( breg , breg , delta_rtx ) ) ; dst = replace_equiv_address ( dst , breg ) ; } else if ( ! rs6000_offsettable_memref_p ( dst , reg_mode ) && GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) != LO_SUM ) { if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_MODIFY ) { rtx basereg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; if ( TARGET_UPDATE ) { rtx nsrc = simplify_gen_subreg ( reg_mode , src , mode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( reg_mode , XEXP ( dst , <NUM_LIT> ) ) , nsrc ) ) ; used_update = true ; } else emit_insn ( gen_rtx_SET ( VOIDmode , basereg , XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; dst = replace_equiv_address ( dst , basereg ) ; } else { rtx basereg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; rtx offsetreg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PLUS && REG_P ( basereg ) && REG_P ( offsetreg ) && REGNO ( basereg ) != REGNO ( offsetreg ) ) ; if ( REGNO ( basereg ) == <NUM_LIT> ) { rtx tmp = offsetreg ; offsetreg = basereg ; basereg = tmp ; } emit_insn ( gen_add3_insn ( basereg , basereg , offsetreg ) ) ; restore_basereg = gen_sub3_insn ( basereg


<s> static SmallVector < int , <NUM_LIT> > getPSHUFShuffleMask ( SDValue N ) { MVT VT = N . getSimpleValueType ( ) ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; bool IsUnary ; bool HaveMask = getTargetShuffleMask ( N . getNode ( ) , VT , false , Ops , Mask , IsUnary ) ; ( void ) HaveMask ; assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> /


<s> const MCExpr * getExpr ( ) const { assert ( Kind == Expression && <STR_LIT>


<s> int regs = MT_NUM_ARG_REGS - * cum ; * pretend_size = regs < <NUM_LIT> ? <NUM_LIT> : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < MT_NUM_ARG_REGS ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , FIRST_ARG_REGNUM


<s> if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; gcc_assert ( ! stack_realign_drap ) ; seh = XCNEW ( struct seh_frame_state ) ; cfun -> machine -> seh = seh ; seh -> sp_offset =


<s> RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; } EVT VT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( MBB , DL , TII . get ( OpImm ) , ResultReg ) . addReg ( Op0Reg ) . addImm ( CI -> getZExtValue ( ) & <NUM_LIT> ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; TII . copyRegToReg ( * MBB , MBB -> end (


<s> unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr (


<s> void <ISA_LIT>InstPrinter :: printSOImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm (


<s> OutStreamer . EmitLabel ( StubLabel ) ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer

. EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> uint32x4_t result = vcombine_u32 ( a , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b