<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses


<s> MCELFStreamer :: emitValueImpl ( Value


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( )


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return <ISA_LIT>RDToVal ( static_cast < <STR_LIT> > ( getMachineOpValue ( MI , MO ,


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) || isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) ; return isLegalMaskCompare ( N


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc ::


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitAtomicCmpSwap ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It


<s> if ( ResTyNumElts <= Idx && Idx < ResTyNumElts * <NUM_LIT> ) Using2ndVec = true ; } for ( SmallVector < int , <NUM_LIT> > :: iterator I = Indices . begin ( ) ; I != Indices . end ( ) ; ++ I ) Ops . push_back ( DAG . getTargetConstant ( * I , MaskEltTy ) ) ; SDValue MaskVec = DAG . getNode ( <STR_LIT> , DL , MaskVecTy , Ops ) ; if ( Using1stVec && Using2ndVec ) { Op0 = Op -> getOperand ( <NUM_LIT> ) ; Op1 = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Using1stVec ) Op0 = Op1


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> static __inline int __attribute__ ( ( __always_inline__ )


<s> unsigned Index = ZerosFromLeft ? i : NumElems - i - <NUM_LIT> ; SDValue Elt = getShuffleScalarElt ( SVOp , Index , DAG , <NUM_LIT> ) ; if ( ! Elt . getNode ( ) ) break ; if ( <STR_LIT> ( Elt ) ) ++ NumZeros ; else if ( Elt . getOpcode ( ) == <STR_LIT> ) NumZeros =

std :: min ( NumZeros + <NUM_LIT> , PreferredNum ) ;


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) return aarch64_simd_abi ( ) ; if ( aarch64_returns_value_in_sve_regs_p ( fntype ) || aarch64_takes_arguments_in_sve_regs_p ( fntype ) ) return aarch64_sve_abi


<s> } else { MachineInstrBuilder InvertedMI ; int InvertedOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; } InvertedMI = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( InvertedOpcode ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { InvertedMI . addOperand ( MI -> getOperand ( i ) ) ; if ( MI -> getOperand ( i ) . isMBB ( ) ) CondBrMBBOperand = i ; } MI -> eraseFromParent ( ) ; MI = Br . MI = InvertedMI ; } MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . OffsetBits ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( CondBrMBBOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; splitBlockBeforeInstr ( MBBI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << NextBB


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; return St


<s> __v4sf temp = ( __v4sf ) vec_cmpeq ( ( __v4sf ) __A , ( __v4sf ) __B ) ; return ( ( __m128 ) vec_nor ( temp , temp )


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = DFPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> if ( TARGET_LDRD ) return val > - <NUM_LIT> && val < <NUM_LIT> ; else return val > - <NUM_LIT> && val < <NUM_LIT> ; } return TARGET_LDRD && arm_address_register_rtx_p ( index , strict_p ) ; } if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ! ( arm_arch4 && ( mode == HImode || ( mode == QImode && outer == SIGN_EXTEND ) ) ) ) { if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && power_of_two_operand ( xiop1 , SImode ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && power_of_two_operand ( xiop0 , SImode ) ) ) ; } else if ( code == LSHIFTRT || code == ASHIFTRT || code == ASHIFT || code == ROTATERT ) { rtx op = XEXP ( index , <NUM_LIT> ) ; return ( arm_address_register_rtx_p ( XEXP ( index , <NUM_LIT> ) , strict_p ) && GET_CODE ( op ) == CONST_INT && INTVAL ( op ) > <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ; } } if ( arm_arch4 ) { if ( mode == HImode || ( outer == SIGN_EXTEND && mode == QImode ) ) range = <NUM_LIT> ; else range =


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . use<ISA_LIT>PostRASchedStrategy ( ) ) return create<ISA_LIT>PostMachineScheduler


<s> inline bool isPCREL ( unsigned Opcode ) { return Opcode == PCREL_WRAPPER || Opcode


<s> for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB . add ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; return


<s> DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , <NUM_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; final_end_function ( ) ; init_insn_lengths ( ) ; free_after_compilation ( cfun ) ; set_cfun ( NULL )


<s> vcltz_s8 ( int8x8_t __a ) { return ( uint8x8_t ) (


<s> BuildMI ( * MBB , MachineBasicBlock :: iterator ( MI ) , DL , TII -> get ( <STR_LIT> ) , RetAddr ) . addReg ( SPReg . getReg ( ) ) . addImm ( <NUM_LIT> ) . addReg ( NoRegister ) . addImm ( <NUM_LIT> ) . addReg ( NoRegister ) ; MachineInstr * TCRet = MF -> CreateMachineInstr ( TII -> get ( <STR_LIT> ) , DL ) ; MBB -> insertAfter ( MachineBasicBlock :: iterator ( MI ) , TCRet ) ; TCRet -> RemoveOperand ( <NUM_LIT> ) ; TCRet -> addOperand ( MachineOperand :: CreateReg ( RetAddr , false ) ) ; MachineOperand StackAdjustVal = MI . getOperand ( <NUM_LIT> ) ; assert ( StackAdjustVal . isImm ( ) && <STR_LIT> ) ; TCRet -> addOperand ( StackAdjustVal ) ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) ) { MachineOperand newOp = MachineOperand :: CreateReg ( MO . getReg ( ) , false ) ; newOp . setIsUse ( true ) ; newOp . setImplicit ( true


<s> static SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode * N , SelectionDAG & DAG ) { SDValue Trunc = N -> getOperand ( <NUM_LIT> ) ; EVT VT = Trunc . getValueType ( ) ; if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , false ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , true ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return SDValue (


<s> void addBDXAddrOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( Kind == KindMem && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem .


<s> SMLoc Start = Lex ( ) . getLoc ( ) ; ID = getTok ( ) . getString ( ) ; if ( ! isParsingMSInlineAsm ( ) ) { if ( ( getTok ( ) . isNot ( AsmToken :: Identifier ) && getTok ( ) . isNot ( AsmToken :: String ) ) || getParser ( ) . parsePrimaryExpr ( Val , End , nullptr )


<s> auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateImm , getContext ( ) ) ) ; Lex ( )


<s> assert ( VecVT . getSizeInBits ( ) < <NUM_LIT> && <STR_LIT> ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned WideNumElts = <NUM_LIT> / EltVT . getSizeInBits ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ; unsigned NumConcat = WideNumElts / VecVT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; Ops [ <NUM_LIT> ] =


<s> if ( TARGET_GENERAL_REGS_ONLY ) if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> , <STR_LIT> ) ; else if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT>


<s> return ( ( qword ) ( vec_perm ( av , vec_sra ( av , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx ,


<s> unsigned NumElts = Mask . size ( ) ; KnownUndef = KnownZero = APInt :: getNullValue ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( SM_SentinelUndef == M ) KnownUndef . setBit


<s> if ( Opc != <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> && <ISA_LIT>SubTarget -> useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == <NUM_LIT> ? <STR_LIT>


<s> unsigned Opc = I -> getOpcode ( ) ; bool IsScaled = ! TII -> isUnscaledLdSt ( Opc ) ; int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I ->


<s> static void getLabelAccessInfo ( bool IsPIC , const <ISA_LIT>Subtarget & Subtarget , unsigned & HiOpFlags , unsigned & LoOpFlags , const GlobalValue * GV = nullptr ) { HiOpFlags = <STR_LIT> ; LoOpFlags = <STR_LIT> ; if ( IsPIC )


<s> unsigned Opc = I . getOpcode ( ) ; if ( I . isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { RTLIB :: Libcall LC = RTLIB :: getFPEXT ( SVT , VT ) ; return LowerF128Call ( Op , DAG , LC


<s> ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , ST . use<ISA_LIT>PreRASchedStrategy ( ) ? std

:: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) :


<s> static __inline int __attribute__ ( ( __always_inline__ ) ) cmse_nonsecure_caller ( void ) { return __builtin_arm_cmse_nonsecure_caller ( )


<s> void arm_lang_object_attributes_init ( void ) { arm_lang_output_object_attributes_hook =


<s> bool isStackEmpty ( ) const { return StackTop


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: x86 , true > X ( getThe<ISA_LIT>_32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: x86_64 , true > Y ( getThe<ISA_LIT>_64Target ( )


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg (


<s> static bool isMOVHLPS_v_undef_Mask ( ArrayRef < int > Mask , EVT VT ) { if ( ! VT . is128BitVector (


<s> if ( FI < <NUM_LIT> ) { Offset += RI -> getSlotSize ( ) ; } else { unsigned Align = MFI -> getObjectAlignment ( FI ) ; assert ( ( - ( Offset + StackSize ) ) % Align == <NUM_LIT> ) ; Align = <NUM_LIT> ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += RI -> getSlotSize ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > (


<s> splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addMBB ( NextBB ) ; } Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> if ( Opc == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT>


<s> if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI -> readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; } else


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool little , Reloc :: Model _RM , <ISA_LIT>TargetMachine * _TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasSwap ( false ) , HasBitCount ( false ) , HasFPIdx ( false ) , In<ISA_LIT>16Mode ( false ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , RM ( _RM ) , OverrideMode ( NoOverride ) , TM ( _TM ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName =


<s> void <ISA_LIT>StackTagging :: tagAlloca ( AllocaInst * AI , Instruction * InsertBefore , Value * Ptr , uint64_t Size ) { auto SetTagZeroFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; auto StgpFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; InitializerBuilder IB ( Size , DL , Ptr , SetTagFunc , SetTagZeroFunc , StgpFunc ) ; bool LittleEndian = Triple ( AI -> getModule ( ) -> getTargetTriple ( ) ) . isLittleEndian ( ) ; if ( MergeInit && ! F -> hasOptNone ( ) && LittleEndian && Size < ClMergeInitSizeLimit ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * AI << <STR_LIT> << Size << <STR_LIT> ) ; InsertBefore = collectInitializers ( InsertBefore , Ptr , Size , IB ) ; } IRBuilder < > IRB ( InsertBefore


<s> SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT>


<s> else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ; assert ( AM . SymbolFlags == <NUM_LIT> && <STR_LIT> ) ; Disp = CurDAG -> getMCSymbol ( AM . MCSym , <STR_LIT> ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM


_mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; TII . adjustStackPtr ( <STR_LIT> , Amount , MBB , I ) ; } MBB . erase ( I


<s> case MCExpr :: SymbolRef : return false ; case MCExpr :: Binary :


<s> SMLoc SRegLoc , ERegLoc ; if ( check ( ParseRegister ( Reg , SRegLoc , ERegLoc ) , SRegLoc , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( RegisterReqs . insert ( std :: make_pair ( Name , Reg ) ) . first -> second != Reg ) return Error ( SRegLoc , <STR_LIT> + Name + <STR_LIT> ) ; return


<s> if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { if ( Kind == TTI :: SK_Broadcast ) { static const CostTblEntry NEONDupTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONDupTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; } if ( Kind == TTI :: SK_Reverse ) { static const CostTblEntry NEONShuffleTbl [


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v2s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector


<s> return ( __m128i ) vec_min ( ( __v4si ) __X ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ! Subtarget -> hasSSSE3 ( ) || ( VT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( Y . getOpcode ( ) == <STR_LIT> && Y . getOperand ( <NUM_LIT> ) == X && <STR_LIT> ( Y . getOperand ( <NUM_LIT> ) . getNode ( ) ) && X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { assert ( ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) && <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( VT , Mask ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; EVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) )


<s> if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops


<s> assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in

) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ;


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( SymAddr ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys


<s> TSTInst . setOpcode ( <STR_LIT> ) ; TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; if ( FlagSfiZeroMask ) { TSTInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; } else { TSTInst . addOperand ( MCOperand ::


<s> unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes


<s> unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits << <NUM_LIT>


<s> cmp_mode = CCNOmode ; tmp = gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , tmp ) , UNSPEC_FNSTSW ) ; scratch = gen_reg_rtx ( HImode ) ; emit_insn ( gen_rtx_SET ( scratch , tmp ) ) ; switch ( code ) { case GT : case UNGT : if ( code == GT || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; cmp_mode = CCmode ; code = GEU ; } break ; case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; cmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_1_ccno ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_ext_1_cc ( scratch , scratch , const1_rtx ) ) ; code =


<s> return ( int16x8_t ) __builtin_aarch64_sqrdmulhv8hi ( __a ,


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ?


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_footprint_exceeded ( void *


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_LONGJMP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt =


<s> if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op )


<s> case <STR_LIT> : MaxEncoding = <NUM_LIT> ; ShiftSize = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { MaxEncoding = <NUM_LIT> ; Sign = - <NUM_LIT> ; Offset = - Offset ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; do { unsigned ThisVal = std :: min < unsigned > ( Offset , MaxEncodableValue ) ; unsigned LocalShiftSize = <NUM_LIT> ; if ( ThisVal > MaxEncoding ) { ThisVal = ThisVal >> ShiftSize ; LocalShiftSize = ShiftSize ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; auto MBI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( Sign * ( int ) ThisVal ) ; if ( ShiftSize ) MBI = MBI . addImm ( <STR_LIT> ( <STR_LIT> , LocalShiftSize ) ) ; MBI = MBI . setMIFlag ( Flag ) ; if ( NeedsWinCFI ) { assert ( Sign == <NUM_LIT> && <STR_LIT> ) ; int Imm = ( int ) ( ThisVal << LocalShiftSize ) ; if ( ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) || ( SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) ) { if ( HasWinCFI ) * HasWinCFI = true ; if ( Imm == <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . setMIFlag ( Flag ) ; else BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( Imm ) . setMIFlag ( Flag ) ; assert ( ( Offset - Imm ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else if ( DestReg == <STR_LIT> ) { if ( HasWinCFI ) * HasWinCFI = true ; assert ( SrcReg == <STR_LIT>


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned RegNum = Tok . getIntVal ( ) ; if ( RegNum != <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * op = <STR_LIT> ( <STR_LIT> , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( op ) ; Parser . Lex ( ) ; return


<s> int NumWideParts = ( ( WideBits % <NUM_LIT> ) ? ( ( WideBits / <NUM_LIT> ) + <NUM_LIT> ) : ( WideBits / <NUM_LIT> ) ) ; int NumElsPerVector = ( VecTy -> getVectorNumElements ( ) / NumWideParts ) ; int NumSrcParts = ( ( NumWideParts > NumElsPerVector ) ? NumElsPerVector : NumWideParts ) ; unsigned NumOperands = ( ( Opcode == Instruction :: Load ) ? Indices . size ( ) : Factor ) ; if ( NumSrcParts > <NUM_LIT> )


<s> unsigned getPgReg ( ) const { assert ( Predicated ) ; return Pg


<s> static bool isVSplat ( SDValue N , APInt & Imm , bool IsLittleEndian ) { BuildVectorSDNode * Node = dyn_cast < BuildVectorSDNode > ( N . getNode ( ) ) ; if ( Node == NULL ) return false ; APInt SplatValue ,


<s> case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( getReg


<s> EVT <ISA_LIT>TargetLowering :: getPromotedVTForPredicate ( EVT


<s> uint8_t Buff [ <NUM_LIT> ] ; Buff [ <NUM_LIT> ] = <STR_LIT> :: UNWIND_OPCODE_INC_VSP_ULEB128 ; size_t ULEBSize = encodeULEB128 ( ( Offset - <NUM_LIT> ) >> <NUM_LIT> , Buff + <NUM_LIT> ) ; EmitBytes ( Buff , ULEBSize + <NUM_LIT> ) ; } else if ( Offset > <NUM_LIT> ) { if ( Offset > <NUM_LIT> ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_INC_VSP | <NUM_LIT> ) ; Offset -= <NUM_LIT> ; } EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_INC_VSP | static_cast < uint8_t > ( ( Offset - <NUM_LIT> ) >> <NUM_LIT> ) ) ; } else if ( Offset < <NUM_LIT> ) { while ( Offset < - <NUM_LIT> ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_DEC_VSP |


<s> virtual const MandarinTargetLowering * getTargetLowering


<s> gcc_assert ( REG_P ( countreg ) ) ; sc = expand_simple_binop ( GET_MODE ( countreg ) , LSHIFTRT , countreg , GEN_INT ( exact_log2 ( scale ) ) , NULL


<s> if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; bool IsLittleEndian = ( Endian == <STR_LIT> ) ; bool IsInstFixup = ( Kind >= FirstTargetFixupKind ) ; if ( IsLittleEndian && IsInstFixup && ( NumBytes == <NUM_LIT> ) ) { Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( Value & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; } else


<s> return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocOption (


<s> SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue DestBB = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative


<s> SDLoc dl ( Op ) ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && Mask . getValueType ( ) == <STR_LIT> ) { unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( VT . getScalarType ( ) , NumEltsInWideVec ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; SDValue Src0 = N -> getSrc0 ( ) ; Src0 = ExtendToType ( Src0 , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG


_mm_undefined_si128 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> Type * VecBasePtrTy = SubVecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Value * VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; i ++ ) { Value * NewBasePtr = Builder . CreateGEP ( VecBasePtr , Builder . getInt32 ( i ) ) ; Instruction * NewLoad = Builder . CreateAlignedLoad ( NewBasePtr , LI -> getAlignment ( ) ) ; DecomposedVectors . push_back ( NewLoad ) ; } return true


<s> static void mips_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct mips_arg_info info ; mips_get_arg_info ( & info , cum , mode , type , named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < <NUM_LIT> && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? <NUM_LIT> : <NUM_LIT> ) << ( cum -> arg_number * <NUM_LIT> ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs

= info . reg_offset + info . reg_words ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT>


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; loongarch_get_arg_info ( & info , cum , arg . mode , arg


<s> else if ( Info . isStrided ( ) && std :: abs ( Info . getStride ( ) ) == <NUM_LIT> ) { if ( Info . isMasked ( ) ) Cost = getMaskedMemoryOpCost ( Opcode , Src ,


<s> break ; } } std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( Res . second == <NUM_LIT> ) { if ( StringsEqualNoCase ( <STR_LIT> , Constraint ) ) { Res . first = <STR_LIT> ; Res . second = <STR_LIT> ; } if ( Constraint == <STR_LIT> ) { Res . first = <STR_LIT> ; Res . second = <STR_LIT> ; } return Res ; } if ( Res . second -> hasType ( VT ) ) return Res ; if ( Res . second == <STR_LIT> ) { if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second


<s> return ( __m128i ) __builtin_ia32_vpermi2vard128_mask ( ( __v4si ) __A , ( __v4si )


<s> static inline bool isValidDecodeLogicalImmediate ( uint64_t val , unsigned regSize ) { unsigned N = ( val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned imms = val & <NUM_LIT> ; if ( regSize == <NUM_LIT> && N


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < uint32_t , <NUM_LIT> > MaskHigh ; SmallVector < uint32_t , <NUM_LIT> > MaskLow ; SmallVector < uint32_t , <NUM_LIT> > LowHighMask [ <NUM_LIT> ] ; SmallVector < uint32_t , <NUM_LIT> > MaskHighTemp ; SmallVector < uint32_t , <NUM_LIT> > MaskLowTemp ; createUnpackShuffleMask < uint32_t > ( VT , MaskLow , true , false ) ; createUnpackShuffleMask < uint32_t > ( VT , MaskHigh , false , false ) ; createUnpackShuffleMask < uint32_t > ( HalfVT , MaskLowTemp , true , false ) ; createUnpackShuffleMask < uint32_t > ( HalfVT , MaskHighTemp , false , false ) ; scaleShuffleMask < uint32_t > ( <NUM_LIT> , MaskLowTemp , LowHighMask [ <NUM_LIT> ] ) ; scaleShuffleMask < uint32_t > ( <NUM_LIT> , MaskHighTemp , LowHighMask [ <NUM_LIT> ] ) ; Value * IntrVec [ <NUM_LIT> ] ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskHigh ) ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [


<s> <ISA_LIT>ELFStreamer & MEF = static_cast < <ISA_LIT>ELFStreamer & > ( Streamer ) ; MEF . createPendingLabelRelocs (


<s> t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = <NUM_LIT> ; break ; case V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ; bmask = <NUM_LIT>


<s> static <ISA_LIT>Operand * createInvalid ( SMLoc StartLoc , SMLoc


<s> return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBCombine ( N , DAG


<s> } Options . setNoreorder ( ) ; Parser . Lex ( ) ; return


<s> static bool regIsPICBase ( unsigned BaseReg , const MachineRegisterInfo & MRI ) { if ( ! Register :: isVirtualRegister ( BaseReg ) ) return false ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = & * I ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase


<s> return __builtin_aarch64_usra_nv4hi_uuus ( __a ,


<s> if ( Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Basic ; return <NUM_LIT> * TTI :: TCC_Basic ; } return <NUM_LIT> * TTI


<s> auto isSupportedOnAVX512 = [ ] ( Type * VecTy , bool HasBW ) { Type * EltTy = cast < VectorType > ( VecTy ) -> getElementType ( ) ; if ( EltTy -> isFloatTy ( ) || EltTy -> isDoubleTy ( ) || EltTy -> isIntegerTy ( <NUM_LIT> ) || EltTy -> isIntegerTy ( <NUM_LIT> ) || EltTy -> isPointerTy ( ) ) return true ; if ( EltTy -> isIntegerTy ( <NUM_LIT> ) || EltTy -> isIntegerTy ( <NUM_LIT> ) ) return HasBW ; return false ; } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy


<s>
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
OrigErrorInfo
)
)
{
case
Match_Success
:
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
case
Match_MissingFeature
:
Error
(
IDLoc
,
<STR_LIT>
)
;
return
true
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
MatchResultTy
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)
)
;
return
true
;
}
if
(
(
Match1
==
Match_MnemonicFail
)
&&
(
Match2
==
Match_MnemonicFail
)
&&
(
Match3
==
Match_MnemonicFail
)
&&
(
Match4
==
Match_MnemonicFail
)
)
{
if
(
!
WasOriginallyInvalidOperand
)
{
Error
(
IDLoc
,
<STR_LIT>
+
Base
+
<STR_LIT>
)
;
return
true
;
}
SMLoc
ErrorLoc
=


<s> return getSubExpr ( ) -> findAssociatedFragment


<s> if ( BitWidth < <NUM_LIT> || BitWidth > <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( VT . is128BitVector ( ) && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; auto OnlyUsedAsSelectCond = [ ] ( SDValue Cond ) { for ( SDNode :: use_iterator UI = Cond -> use_begin ( ) , UE = Cond -> use_end ( ) ; UI != UE ; ++ UI ) if ( ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) || UI . getOperandNo ( ) != <NUM_LIT> ) return false ; return true ; } ; if ( OnlyUsedAsSelectCond ( Cond ) ) { APInt DemandedMask ( APInt :: getSignMask ( BitWidth ) ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; if ( ! TLI . SimplifyDemandedBits ( Cond , DemandedMask , Known , TLO , <NUM_LIT> , true ) ) return SDValue ( ) ; for ( SDNode * U : Cond -> uses ( ) ) { if ( U -> getOpcode ( ) == <STR_LIT> ) continue ; SDValue SB = DAG . getNode ( <STR_LIT> , SDLoc ( U ) , U -> getValueType ( <NUM_LIT> ) , Cond , U -> getOperand ( <NUM_LIT> ) , U -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( U , <NUM_LIT> ) , SB ) ; DCI . AddToWorklist ( U ) ; } DCI . CommitTargetLoweringOpt (


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction (


<s> return ( uint32x2_t ) __builtin_neon_vcgev2si (


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT> ; } return


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 . getImm (


<s> case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; case MachineOperand :: MO_Register : O << '(' ; printOperand ( * this , MI , OpNo , O ) ; O << ')' ; return false ; } case 'c' : switch ( MO . getType ( ) ) { default : printOperand ( * this , MI , OpNo , O ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( * this , MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( * this , MI , OpNo , O ) ; return false


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target


<s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc (


<s> ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; } return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , Op0 -> getOperand ( <NUM_LIT> )


<s> ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregciv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregciv4si (


<s> return __builtin_mve_vctp32q_mhi ( __a ,


<s> if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_Darwin_<ISA_LIT>_AAVPCS_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) report_fatal_error ( <STR_LIT> ) ; if ( CC == CallingConv :: CFGuard_Check ) report_fatal_error ( <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) .


<s> Op -> MMask . Val = MMask ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } if ( Need0FPrefix ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case


<s> emitFrameOffset ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , FrameReg , Offset , TII , MachineInstr :: NoFlags , ( Opcode == <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; Offset = StackOffset ( ) ; return true ; } int64_t NewOffset ; unsigned UnscaledOp ; bool UseUnscaledOp ; int Status = is<ISA_LIT>FrameOffsetLegal ( MI , Offset , & UseUnscaledOp , & UnscaledOp , & NewOffset ) ; if ( Status & <ISA_LIT>FrameOffsetCanUpdate ) { if ( Status & <ISA_LIT>FrameOffsetIsLegal ) MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( UseUnscaledOp ) MI . setDesc ( TII -> get ( UnscaledOp ) ) ; MI . getOperand ( ImmIdx ) . ChangeToImmediate ( NewOffset ) ; return !


<s> if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't'


<s> if ( isTargetShuffle ( U -> getOpcode ( ) ) ) return true ; if ( U -> getOpcode ( ) == <STR_LIT> ) return isUseOfShuffle ( U ) ; } return false


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol


<s> SDLoc DL ( Op ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; MVT VT = Op . getSimpleValueType ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & DAG . getTarget ( ) ) ; TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( <STR_LIT> ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT


<s> rtx pat , new_pat ; gen_func_t gen_load ; gen_load = get_spec_load_gen_function ( ts , mode_no ) ; new_pat = gen_load ( copy_rtx ( recog_data . operand [ <NUM_LIT> ] ) , copy_rtx ( recog_data . operand [ <NUM_LIT> ] ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) new_pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( pat ) ) , new_pat ) ; return new_pat


<s> bool useRetpolineIndirectBranches ( ) const { return UseRetpolineIndirectBranches


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholePass ( ) { return new <ISA_LIT>MIPeephole (


<s> if ( N -> getNumValues ( ) != <NUM_LIT> ) return false ; if ( ! N -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) == <STR_LIT> ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , <NUM_LIT> > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > <NUM_LIT> ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( <NUM_LIT> ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain =


<s> bool function_checker :: require_immediate_range ( unsigned int rel_argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; gcc_assert ( min >= <NUM_LIT> && min <= max ) ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( location , fndecl , argno , actual , min , max ) ; return false


<s> void <ISA_LIT>BranchRelaxation :: computeBlockSize ( const MachineBasicBlock & MBB ) { unsigned Size = <NUM_LIT> ; for ( const MachineInstr & MI : MBB ) Size += TII -> getInstSizeInBytes ( MI ) ; BlockInfo [ MBB . getNumber ( ) ] . Size =


<s> CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg (

CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ;


<s> if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ) ) ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , <NUM_LIT> ) ; } else for ( i = <NUM_LIT> ; i <


<s> const char * rs6000_indirect_call_template ( rtx * operands ,


<s> split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF || GET_CODE ( base )


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; SmallVector < MachineMemOperand * , <NUM_LIT> > MMOs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; unsigned DstReg ; unsigned MemOpndSlot = <NUM_LIT> ; unsigned CurOp = <NUM_LIT> ; DstReg = MI . getOperand ( CurOp ++ ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; ( void ) TRI ; Register mainDstReg = MRI . createVirtualRegister ( RC ) ; Register restoreDstReg = MRI . createVirtualRegister ( RC ) ; MemOpndSlot = CurOp ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; restoreMBB -> setHasAddressTaken ( ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ! isPositionIndependent ( ) ; if ( !


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWin64EHHandlerData ( ) { MCStreamer :: EmitWin64EHHandlerData ( )


<s> else if ( regno == REG_VOLATILE ) rws_insn [ <NUM_LIT>


<s> } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { if ( inMicro<ISA_LIT>Mode ( ) ) { Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoDspDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMsaDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMsaDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetSoftFloatDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetHardFloatDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoCRCDirective ( ) ; }


<s> for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator si = StackStores . begin ( ) , se = StackStores . end ( ) ; si != se ; ++ si ) { MachineInstr * Store = * si ; unsigned Opc = Store -> getOpcode ( ) ; MachineBasicBlock & MBB = * Ret -> getParent ( ) ; int FI = Store -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ZeroedLocations . count ( FI ) ) continue ; ZeroedLocations . insert ( FI ) ; if ( Opc == <STR_LIT> ) { MachineInstrBuilder MIB ( F , Ret ) ; BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( Opc ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) . addImm ( ShiftImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( ScrReg ) . addImm


<s> SmallVector < int , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > VPAlign2 ; SmallVector < int , <NUM_LIT> > VPAlign3 ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( <STR_LIT> , VecElems ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ i ] , VPAlign [ i ] ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , false , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , false , true ) ; Vec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ <NUM_LIT> ] , UndefValue :: get ( InVec [ <NUM_LIT> ] -> getType ( ) ) , VPAlign2 ) ; Vec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ <NUM_LIT> ] , UndefValue :: get ( InVec [ <NUM_LIT> ] -> getType


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { llvm :: erase_if ( RepeatedSequenceLocs , CantGuaranteeValueAcrossCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { FrameID =


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModels ( GA , DAG


<s> return __builtin_mve_vpselq_fv4sf ( __a ,


<s> if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy ,

VariableMask , Alignment , AddressSpace ) ;


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( In . getSimpleValueType ( ) != <STR_LIT> ) return


<s> if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) { if ( ( mode == P2QImode || mode == P2HImode ) ) return MASK_PAIR_REGNO_P ( regno ) ; return ( ( TARGET_AVX512F && VALID_MASK_REG_MODE ( mode ) ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( VALID_AVX512F_REG_OR_XI_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; if ( TARGET_SSE2 && mode == HImode ) return true ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) || VALID_FP_MODE_P ( mode ) ) return


<s> printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' << getRegisterName ( Dst . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO3 . getImm ( ) ) == <STR_LIT> ) return ; O << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; } else { O << <STR_LIT> << <STR_LIT> ( MO3 . getImm ( ) ) ; } return ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const MCOperand & MO1 = MI -> getOperand


<s> assert ( ConstraintCode == 'm' && <STR_LIT> ) ; SDValue Base , Offset , Opc ; if ( ! SelectAddrMode2 ( Op , Op , Base , Offset , Opc ) ) return true ; OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; OutOps . push_back ( Opc ) ; return


<s> MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; Register SrcReg = SrcMO . getReg ( ) ; Register DstReg = DstMO . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstReg , SrcReg ) ) continue ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( <STR_LIT> ) ; Align Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( <STR_LIT> ) ; Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = <STR_LIT> ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) . addImm ( <NUM_LIT> ) ; unsigned Opc = <STR_LIT> ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) ) , TileSS ) . addReg ( SrcReg , getKillRegState ( SrcMO . isKill ( ) ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( GR64Cand ) ; MO . setIsKill (


<s> MI -> getOperand ( <NUM_LIT> ) . setImm ( Control ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ; MI -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } if ( ! NoFloat && ( Control & <NUM_LIT> ) != <NUM_LIT> ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { unsigned Reg = <STR_LIT> [ I ] ; MI -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } return


<s> case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : llvm_unreachable ( <STR_LIT> ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] ) ; break ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; break ; case ENCODING_I


<s> if ( sym ) { tree decl = SYMBOL_REF_DECL ( sym ) ; if ( TARGET_MACHO && flag_pic && ! machopic_offs_p ) return false ; if ( MACHO_SYMBOL_INDIRECTION_P ( sym ) ) ; else if ( decl && DECL_ALIGN ( decl ) ) align = DECL_ALIGN_UNIT ( decl ) ; } unsigned int extra = <NUM_LIT> ; switch ( mode ) { case E_DFmode : case E_DDmode : case E_DImode : if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( ( offset & <NUM_LIT> ) || ( align & <NUM_LIT> ) ) return false ; break ; case E_TFmode : case E_IFmode : case E_KFmode : case E_TDmode : case E_TImode : case E_PTImode : extra = <NUM_LIT> ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( ( offset & <NUM_LIT> ) || ( align


<s> if ( ! fndecl || fndecl == aarch64_previous_fndecl ) return ; tree old_tree = ( aarch64_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( aarch64_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! new_tree && old_tree )


<s> addPass ( create<ISA_LIT>FiMalkrzPass ( ) )


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE


<s> for ( int R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) PopMIB2 . addReg ( <STR_LIT> + R , RegState :: Define ) ; } else { MachineInstrBuilder PopMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PopMIB . addReg ( Reg ,


<s> assert ( Alignment >= Align ( RegSizeInBytes ) && <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs ) ; if ( ( Alignment > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = alignTo ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && ( I


) ) _blsr_u64 ( unsigned long long __X ) {


<s> bool <ISA_LIT>FastISel :: isLoadTypeLegal ( Type * Ty , MVT & VT ) { if ( isTypeLegal ( Ty ,


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget


<s> return ( ( qword ) ( vec_sub ( ( vec_ushort8 ) ( b ) , ( vec_ushort8 )


<s> if ( const MCUnaryExpr * UnExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) { if ( UnExpr -> getOpcode ( ) == MCUnaryExpr :: Minus ) { Inst . addOperand ( MCOperand :: createExpr ( UnExpr -> getSubExpr ( ) ) ) ; return ; } } else if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) { if ( BinExpr -> getOpcode ( ) == MCBinaryExpr :: Sub ) { const MCExpr * NE = MCBinaryExpr :: createSub ( BinExpr -> getRHS ( ) , BinExpr -> getLHS ( ) , Ctx ) ; Inst . addOperand ( MCOperand ::


<s> return nullptr ; } const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( ScalarTy , DstRB , RBI , true ) ; if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const RegisterBank & VecRB = * RBI . getRegBank ( VecReg , MRI , TRI ) ; const LLT & VecTy = MRI . getType ( VecReg ) ; const TargetRegisterClass * VecRC = getRegClassForTypeOnBank ( VecTy , VecRB , RBI , true ) ; if ( ! VecRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertReg = VecReg ; if ( ! DstReg ) DstReg = MRI . createVirtualRegister ( DstRC ) ; if ( LaneIdx == <NUM_LIT> ) { auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { * DstReg } , { } ) . addReg ( VecReg , <NUM_LIT> , ExtractSubReg ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ; return & *


<s> if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode ) ) return aarch64_simd_builtin_std_type ( mode , q ) ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { if ( aarch64_simd_types [ i ] . mode == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_types [ i ] . itype ; if ( aarch64_simd_tuple_types [ i ] [ <NUM_LIT> ] != NULL_TREE ) for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) if ( aarch64_simd_tuple_modes [ i ] [ j ] == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_tuple_types [ i ] [ j ] ; } return


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( OSABI ,


<s> rettype = gpr_type_node ; argtype = gpr_type_node ; } else if ( d -> code == HTM_BUILTIN_TABORTDC || d -> code == HTM_BUILTIN_TABORTDCI ) { rettype = unsigned_type_node ; argtype = gpr_type_node ; } else { rettype = unsigned_type_node ; argtype = unsigned_type_node ; } if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } if ( d -> name == <NUM_LIT> ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , ( long unsigned ) i ) ; continue ; } op [ nopnds ++ ] = ( void_func ) ? void_type_node : rettype ; if ( attr_args == RS6000_BTC_UNARY ) op [ nopnds ++ ] = argtype ; else if ( attr_args == RS6000_BTC_BINARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } else if ( attr_args == RS6000_BTC_TERNARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } switch ( nopnds


<s> Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( isRepeatedTargetShuffleMask ( <NUM_LIT> , MaskVT , Mask , RepeatedMask ) ) { auto MatchHalf = [ & ] ( unsigned Offset , int & S0 , int & S1 ) { int M0 = RepeatedMask [ Offset ] ; int M1 = RepeatedMask [ Offset + <NUM_LIT> ] ; if ( isUndefInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { return DAG . getUNDEF ( MaskVT ) ; } else if ( isUndefOrZeroInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : <NUM_LIT> ) ; return getZeroVector ( MaskVT , Subtarget , DAG , DL ) ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V1 ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V2 ; } return SDValue ( ) ; } ; int ShufMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Lo = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask


<s> BuildMI ( MBB , I , DL , AddiuSpImm ( Imm ) ) . addImm


<s> if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( regno == PIC_OFFSET_TABLE_REGNUM && crtl -> uses_pic_offset_table ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return


<s> for ( int i = <NUM_LIT> ; i < XVECLEN ( op , <NUM_LIT> ) ; ++ i ) if ( ! CONST_INT_P ( XVECEXP ( op , <NUM_LIT> , i ) ) || UINTVAL (

XVECEXP ( op , <NUM_LIT> , i ) ) != base + i * step ) return false ;


<s> virtual const char * getPassName ( )


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> static std :: string computeDataLayout ( StringRef TT , StringRef CPU , const TargetOptions & Options , bool isLittle ) { std :: string Ret = <STR_LIT> ; <ISA_LIT>ABIInfo ABI = <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( TT ) , CPU , Options . MCOptions ) ; if ( isLittle ) Ret


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; LLVMContext * Context = DAG . getContext ( ) ; assert ( Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ConstantInt * CI = ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; std :: vector < Constant * > CV ( <NUM_LIT> , CI ) ; Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Addend = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Addend ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op , R ) ; } if ( VT == <STR_LIT> )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( create<ISA_LIT>GlobalBaseRegPass ( )


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo


<s> SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( GlobalValue *


<s> if ( VT == <STR_LIT> ) return <ISA_LIT>ScalarSSEf64 ; return true


<s> MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; MIB . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand