<s> void ExpandPseudo :: expandLoadACC ( MachineBasicBlock & MBB , Iter I , unsigned RegSize ) { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Lo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 , FI , RC


<s> void printlea32mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; bool hasGPR = false ; unsigned LastReg = <NUM_LIT> ; if ( MF . protectCSRs ( ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; hasGPR = true ; LastReg = CSI [ i ] . getReg ( ) ; } if ( hasGPR ) { assert ( LastReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , LastReg ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i


<s> float32x2x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv2sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregoiv2sf ( __o ,


<s> deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [


<s> CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT>


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) *


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std ::


<s> int _U_Qfle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , <NUM_LIT> )


<s> EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> ) { if ( InSVT == <STR_LIT> ) return SDValue ( ) ; if ( InSVT == <STR_LIT> && ( OutSVT == <STR_LIT> || ! Subtarget . hasSSE41 ( ) || Subtarget . hasInt256 ( ) ) ) return SDValue ( ) ; } SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL , Subtarget , DAG ) ; return SDValue


<s> return __builtin_mve_vmulhq_m_uv4si ( __arm_vuninitializedq_u32 ( ) ,


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> TargetSelectionDAGInfo ( TM ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TLI ( * TM . getTargetLowering (


<s> return ( uint16x4_t ) __builtin_neon_vcgtv4hi


<s> return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return legalizeShlAshrLshr ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeSmallCMGlobalValue ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_TRUNC : return legalizeVectorTrunc ( MI , Helper ) ; case TargetOpcode :: G_SBFX : case TargetOpcode :: G_UBFX : return legalizeBitfieldExtract ( MI , MRI , Helper ) ; case TargetOpcode :: G_ROTR : return legalizeRotate ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTPOP : return legalizeCTPOP ( MI , MRI , Helper ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpxchg128 ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTTZ : return legalizeCTTZ ( MI , Helper ) ; case TargetOpcode ::


<s> static DecodeStatus DecodeJumpTargetMM ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_suspend ( void ) { __builtin_tsuspend (


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'A' : return C_Register ; case 'f' : case 'r' : case 'R' : case 'l' : case 'q' : case 'Q' : case 'x' : case 'y' : case 'Y' : return C_RegisterClass ; case 'e' : case 'Z' : return C_Other


<s> const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( )


<s> SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low ,


<s> return Op + <NUM_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op ) . isReg ( ) && isScale ( MI -> getOperand ( Op + <NUM_LIT> ) ) && MI -> getOperand ( Op + <NUM_LIT> ) . isReg ( ) && ( MI -> getOperand ( Op + <NUM_LIT> ) . isImm ( ) || MI

-> getOperand ( Op + <NUM_LIT> ) . isGlobal ( ) || MI -> getOperand ( Op + <NUM_LIT> ) . isCPI ( ) || MI -> getOperand ( Op + <NUM_LIT> ) . isJTI ( ) ) ;


<s> static bool jumpTableFollowsTB ( MachineInstr * JTMI , MachineInstr * CPEMI ) { MachineFunction :: iterator MBB = JTMI -> getParent ( ) -> getIterator ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; ++ MBB ; return MBB != MF -> end ( ) && MBB -> begin ( ) != MBB -> end ( )


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vmlal_high_n_s16 ( int32x4_t a , int16x8_t b , int16_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedPred = NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( is<ISA_LIT>LowRegister ( DestReg ) && is<ISA_LIT>LowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; const TargetInstrDesc & TID = TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TID , DestReg ) ) ; AddDefaultPred ( MIB . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT>


<s> assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT> :


<s> case CondCode : OS << <STR_LIT> << <ISA_LIT>CondCodeToString ( getCondCode ( ) ) << <STR_LIT> ; break ; case CCOut : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case CoprocNum : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case CoprocReg : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case MSRMask : OS << <STR_LIT> << getMSRMask ( ) << <STR_LIT> ; break ; case Immediate : getImm ( ) -> print ( OS ) ; break ; case MemBarrierOpt : OS << <STR_LIT> << MemBOptToString ( getMemBarrierOpt ( ) ) << <STR_LIT> ; break ; case Memory : OS << <STR_LIT> << <STR_LIT> << getMemBaseRegNum ( ) ; if ( getMemOffsetIsReg ( ) ) { OS << <STR_LIT> << getMemOffsetRegNum ( ) ; if ( getMemOffsetRegShifted ( ) ) { OS << <STR_LIT> << getMemShiftType ( ) ; OS << <STR_LIT> << * getMemShiftAmount ( ) ; } } else { OS << <STR_LIT> << * getMemOffset ( ) ; } if ( getMemOffsetIsReg ( ) ) OS << <STR_LIT> ; if ( getMemPreindexed ( ) ) OS << <STR_LIT> ; if ( getMemPostindexed ( ) ) OS << <STR_LIT> ; if ( getMemNegative ( ) ) OS << <STR_LIT> ; if ( getMemWriteback ( ) ) OS << <STR_LIT> ; OS << <STR_LIT> ; break ; case ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case Register : OS << <STR_LIT> << getReg ( )


<s> assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; unsigned NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const


<s> int unspec_for ( const function_instance & instance ) const { return ( ! instance . type_suffix ( <NUM_LIT> ) . integer_p ? m_unspec_for_fp : instance . type_suffix ( <NUM_LIT> ) .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; } SDValue Val ; if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } Val = DAG . getNode ( <STR_LIT> , dl , CopyVT , Val ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue (


<s> const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) .

CreateStackObject ( TRI . getSpillSize ( RC ) , TRI . getSpillAlignment ( RC ) , false ) ;


<s> Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , InFlag , dl ) ; InFlag = Chain . getValue


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true :


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString


<s> if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , ( ( is64Bit ) ? <STR_LIT> : <STR_LIT>


<s> if ( Ty -> isVectorTy ( ) && AM . BaseOffs != <NUM_LIT> ) return false ; if ( AM . BaseOffs <= - ( <NUM_LIT> << <NUM_LIT> ) || AM . BaseOffs >= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT>


<s> } MachineInstr * TC = BuildMI ( MF , DebugLoc ( ) , get ( TailOpcode ) ) . add ( Call -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB . insert ( MBB . end ( ) , TC ) ; Call -> eraseFromParent ( ) ; FI -> setOutliningStyle ( <STR_LIT> ) ; } bool IsLeafFunction = true ; auto IsNonTailCall = [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; IsLeafFunction = false ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> needsDwarfUnwindInfo ( ) ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const auto & MFI = * OF . Candidates . front ( ) . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool ShouldSignReturnAddr = MFI .

shouldSignReturnAddress ( ! IsLeafFunction ) ;


<s> void <ISA_LIT>InstPrinter :: printPostIdxRegOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << ( MO2 . getImm ( )


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNs ( const SDNode *


<s> void <ISA_LIT>AsmPrinter :: EmitBasicBlockEnd ( const MachineBasicBlock


<s> else { name_buf [ <NUM_LIT> ] = '_' ; strcpy ( name_buf + <NUM_LIT> , name ) ; } strcpy ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; if ( write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG ) dbxout_stabd ( N_SLINE , BRANCH_ISLAND_LINE_NUMBER ( branch_island ) ) ; if ( flag_pic ) { strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT>


<s> TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( Model == TLSModel :: LocalExec ) { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TLSReg = is64bit ? DAG . getRegister ( <STR_LIT> , <STR_LIT> ) : DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV ,


<s> return new <ISA_LIT>CodeEmitter ( TM , JCE


<s> const <ISA_LIT>InstrFMA3Group * llvm :: getFMA3Group ( unsigned Opcode , uint64_t TSFlags ) { uint8_t BaseOpcode = <STR_LIT> ( TSFlags ) ; bool IsFMA3Opcode = ( ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) ) ; bool IsFMA3Encoding = ( ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( TSFlags & <STR_LIT> ) == <STR_LIT> ) || ( ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( ( TSFlags & <STR_LIT> ) == <STR_LIT> || ( TSFlags & <STR_LIT> ) == <STR_LIT> ) ) ; bool IsFMA3Prefix = ( TSFlags & <STR_LIT> ) == <STR_LIT> ; if ( ! IsFMA3Opcode || ! IsFMA3Encoding || ! IsFMA3Prefix


<s> int standard_sse_constant_p ( rtx x ) { if ( x == const0_rtx ) return <NUM_LIT> ; return ( x == CONST0_RTX (


<s> unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) { if ( ST -> hasNEON ( ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; else if ( isLegalMVEShuffleOp ( PFEntry ) ) { unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned PFEntryLHS = PerfectShuffleTable [ LHSID ] ; unsigned PFEntryRHS = PerfectShuffleTable [ RHSID ] ; if ( isLegalMVEShuffleOp ( PFEntryLHS ) && isLegalMVEShuffleOp ( PFEntryRHS ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } } } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( ST -> hasNEON ( ) && VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; if ( ST -> hasMVEIntegerOps ( ) ) if ( SDValue NewOp =

LowerVECTOR_SHUFFLEUsingMovs ( Op , ShuffleMask , DAG ) ) return NewOp ;


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue NOOP ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , VTs , Ops ) , <NUM_LIT> ) ; return


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index

> <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_BNDR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ } \ }


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , <NUM_LIT>


<s> unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) .


<s> RegisterTargetMachine < <ISA_LIT>32TargetMachine > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( getThe<ISA_LIT>64Target


<s> emit_insn ( gen_addxf3 ( e2 , e2 , e1 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = <NUM_LIT> ; half = force_reg ( XFmode ,


<s> if ( MergeInit ) AU . addRequired < AAResultsWrapperPass >


<s> MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue InVec = Op -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; MVT SVT = SrcVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , InVec , DAG . getIntPtrConstant ( i , dl ) ) ) ; Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , NewVT , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return


<s> tree mxcsr_mod_var = create_tmp_var_raw ( unsigned_type_node ) ; tree stmxcsr = ix86_builtins [ IX86_BUILTIN_STMXCSR ] ; tree ldmxcsr = ix86_builtins [ IX86_BUILTIN_LDMXCSR ] ; tree stmxcsr_hold_call = build_call_expr ( stmxcsr , <NUM_LIT> ) ; tree hold_assign_orig = build2 ( MODIFY_EXPR , unsigned_type_node , mxcsr_orig_var , stmxcsr_hold_call ) ; tree hold_mod_val = build2 ( BIT_IOR_EXPR , unsigned_type_node , mxcsr_orig_var , build_int_cst ( unsigned_type_node , <NUM_LIT> ) ) ; hold_mod_val = build2 ( BIT_AND_EXPR , unsigned_type_node , hold_mod_val , build_int_cst ( unsigned_type_node , <NUM_LIT> ) ) ; tree hold_assign_mod = build2 ( MODIFY_EXPR , unsigned_type_node , mxcsr_mod_var , hold_mod_val ) ; tree ldmxcsr_hold_call = build_call_expr ( ldmxcsr , <NUM_LIT> , mxcsr_mod_var ) ; tree hold_all = build2 ( COMPOUND_EXPR , unsigned_type_node , hold_assign_orig , hold_assign_mod ) ; hold_all = build2 ( COMPOUND_EXPR , void_type_node , hold_all , ldmxcsr_hold_call ) ; if ( * hold ) * hold = build2 ( COMPOUND_EXPR , void_type_node , * hold , hold_all ) ; else * hold = hold_all ; tree ldmxcsr_clear_call = build_call_expr ( ldmxcsr , <NUM_LIT> , mxcsr_mod_var ) ; if ( * clear ) * clear = build2 ( COMPOUND_EXPR , void_type_node , * clear , ldmxcsr_clear_call ) ; else * clear =


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( )


<s> if ( TT . getObjectFormat ( ) == Triple :: ELF

) return new <ISA_LIT>TargetELFStreamer ( S ) ;


<s> uint64_t EltMaskSize = RawMask . size ( ) - <NUM_LIT> ; for ( auto M : RawMask


<s> return ( __m128d ) __builtin_ia32_cvtusi2sd32 ( ( __v2df


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } std :: string LowerTok = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; StringRef Tok ( LowerTok ) ; if ( Tok [ <NUM_LIT> ] != 'c' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * CRImm = MCConstantExpr :: Create ( CRNum , getContext ( ) ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CRImm , S , E ) ) ; return MatchOperand_Success


<s> } const MCSymbolRefExpr * SR = dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ; assert ( SR && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr (


<s> if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= <NUM_LIT> ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / <NUM_LIT> ; if ( ninsns == <NUM_LIT> ) return ; if ( * hilo_delay < <NUM_LIT> && reg_set_p ( lo_reg , pattern ) ) nops = <NUM_LIT> - * hilo_delay ; else if ( * delayed_reg != <NUM_LIT> && reg_referenced_p ( * delayed_reg , pattern ) ) nops = <NUM_LIT> ; else nops = <NUM_LIT> ; * hilo_delay += nops ; while ( nops -- > <NUM_LIT> ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = <NUM_LIT> ; if ( INSN_CODE ( insn ) >= <NUM_LIT> ) switch (


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( real_equal ( r ,


<s> if ( CHECK_STACK_LIMIT > <NUM_LIT> ) alt = tree_cons ( get_identifier ( <STR_LIT> ) , NULL , NULL ) ; else { alt = tree_cons ( NULL , build_int_cst ( NULL ,


<s> SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op1 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> static bool fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset , bool * is_load ) { rtx x , dest , src ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return false ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; if ( REG_P ( src ) && MEM_P ( dest ) ) { * is_load = false ; extract_base_offset_in_addr ( dest , base


<s> ( void ) SrcSize ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false


<s> FS = CheriFeatures ; } } ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isCheri ( ) ) { if ( isCheri256 ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; else stackAlignment = Align ( <NUM_LIT> ) ; } else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ; stackAlignment = Align ( <NUM_LIT> )


<s> mode = GET_MODE ( reg ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( IS_VFP_REGNUM ( REGNO ( reg ) ) ) ; gcc_assert ( mode == SFmode || mode == DFmode || mode == SImode || mode == DImode || ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) ) ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_INC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; default : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; break ; } sprintf ( buff , templ , load ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : <STR_LIT> , integer_p ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; return


<s> if ( VT . isVector ( ) ) return false ; if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) )


<s> void <ISA_LIT>TargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { getStreamer ( ) . setAttributeItem (


<s> FunctionPass * llvm :: create<ISA_LIT>PadShortFunctions ( ) { return new PadShortFunc


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return CE -> getValue ( ) >= - ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) && CE -> getValue ( ) < (

<NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ;


<s> if ( Op == ADD ) { if ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal , NVT ) ; } if ( Op == ADD && Val . hasOneUse ( ) ) { if ( Val . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; return Val . getOperand ( <NUM_LIT> ) ; } if ( Val . getOpcode ( ) == <STR_LIT> && NVT == <STR_LIT> && Val . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; Val = Val . getOperand ( <NUM_LIT> ) ; return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , NVT , Val . getOperand ( <NUM_LIT> ) ) ; } } return


<s> if ( arch -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = arch -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + <NUM_LIT> ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } for ( cpu = all_cores ; cpu -> common . name !=


<s> Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = true ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> return ( uint32x4_t ) __builtin_aarch64_subhn2v2di ( ( int32x2_t ) __a , ( int64x2_t )


<s> return false ; } Triple T ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( <STR_LIT> , ( <STR_LIT> + <STR_LIT> ( ID ) ) . str ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitArch ( ID ) ; return false


<s> mask = offsets -> saved_regs_mask ; if ( mask & ( <NUM_LIT> << LR_REGNUM ) ) { limit = <NUM_LIT> ; if ( frame_pointer_needed ) { delta = offsets -> soft_frame - offsets -> saved_args ; reg = THUMB_HARD_FRAME_POINTER_REGNUM ; if ( TARGET_THUMB1 ) limit = <NUM_LIT> ; } else { delta = offsets -> outgoing_args - offsets -> saved_args ; reg = SP_REGNUM ; } if ( TARGET_THUMB1 && TARGET_BACKTRACE ) delta -= <NUM_LIT> ; delta -= <NUM_LIT> ; addr = gen_rtx_REG ( SImode , reg ) ; if ( delta > limit ) { emit_insn ( gen_movsi ( scratch , GEN_INT ( delta ) ) ) ; emit_insn ( gen_addsi3 ( scratch , scratch , stack_pointer_rtx ) ) ; addr = scratch ; } else addr = plus_constant ( Pmode , addr , delta ) ; mem = gen_frame_mem ( Pmode , addr ) ; MEM_VOLATILE_P ( mem ) = true ; emit_move_insn ( mem , source ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode ,


<s> return __builtin_mve_vhsubq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a


<s> case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_8 : return <NUM_LIT> ; case


<s> unsigned Cost2 = ConstantMaterializationCost ( Val2 , Subtarget , ForCodesize ) ; if ( Cost1 < Cost2 ) return true ; if ( Cost1 > Cost2 )


<s> llvm :: Triple :: ArchType arch = pConfig . targets ( ) . triple ( ) . getArch ( ) ; assert ( arch == llvm :: Triple :: x86 || arch == llvm :: Triple :: x86_64 ) ; if ( arch == llvm :: Triple :: x86 || pConfig . targets ( ) . triple ( ) . getEnvironment ( ) == llvm :: Triple :: GNUX32 ) { m_RelEntrySize = <NUM_LIT> ; m_RelaEntrySize = <NUM_LIT> ; if ( arch == llvm :: Triple :: x86 ) m_PointerRel = llvm :: ELF :: R_386_32 ; else m_PointerRel = llvm :: ELF :: R_<ISA_LIT>_64_32 ; } else { m_RelEntrySize =


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>LETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>BETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbLETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbBETarget ( ) , create<ISA_LIT>Disassembler


<s> static const uint16_t CalleeSavedRegs [ ]


<s> assert ( ! isPreISelGenericOpcode ( Opcode ) && <STR_LIT> ) ; auto MI = MIRBuilder . buildInstr ( Opcode , DstOps , SrcOps ) ; if ( RenderFns ) for ( auto & Fn : * RenderFns ) Fn ( MI ) ; constrainSelectedInstRegOperands ( * MI , TII


<s> if ( Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder


<s> case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , CVal ) ) ; const MCExpr * Imm = MCConstantExpr :: create ( CVal , getContext ( ) ) ; return <STR_LIT> ( Imm , Start


<s> vabdl_u8 ( uint8x8_t a , uint8x8_t b ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; assert ( Diff . getBitWidth ( ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) && <STR_LIT> ) ; bool isFastMultiplier = false ; if ( Diff . ult ( <NUM_LIT> ) ) { switch ( Diff . getZExtValue ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , DL , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } } } } if ( ! DCI . isBeforeLegalize ( ) && ! DCI . isBeforeLegalizeOps ( ) ) { ConstantSDNode * CmpAgainst = nullptr ; if ( ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) && ( CmpAgainst = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) && ! isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) { if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( FalseOp ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( TrueOp ) ) { SDValue Ops [ ] = { FalseOp , Cond . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( CC , DL , <STR_LIT> ) , Cond } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } } } if ( CC == <STR_LIT> ) { SDValue Flags ; <STR_LIT> CC0 , CC1 ; bool isAndSetCC ; if ( checkBoolTestAndOrSetCCCombine ( Cond , CC0 , CC1 , Flags ,


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue TEB = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; Chain = TLSArray . getValue ( <NUM_LIT> ) ; SDValue TLSIndexHi = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue TLSIndexLo = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndexHi ) ; SDValue TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , TLSIndexLo ) ; TLSIndex = DAG . getLoad ( <STR_LIT> , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; Chain = TLSIndex . getValue ( <NUM_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; Chain = TLS . getValue ( <NUM_LIT> ) ; const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue Addr = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TLS , TGAHi , DAG

. getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> RestoreMBB -> setHasAddressTaken ( ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; Register LabelReg = prepareMBB ( * MBB , MachineBasicBlock :: iterator ( MI ) , RestoreMBB , DL ) ; const <ISA_LIT>FrameLowering * TFI = Subtarget -> getFrameLowering ( ) ; if ( TFI -> hasBP ( * MF ) ) { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( BufReg ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB . setMemRefs ( MMOs ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( LabelReg , getKillRegState ( true ) ) ; MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * ThisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( RestoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; ThisMBB -> addSuccessor ( MainMBB ) ; ThisMBB -> addSuccessor (


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getUsesRedZone ( ) ) { MIB -> setDesc ( get ( MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return <NUM_LIT> ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == GBR_REG && gbr_displacement ( XEXP ( x , <NUM_LIT> ) , mode ) ) return <NUM_LIT> ; const HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( offset == <NUM_LIT> ) return <NUM_LIT> ; if ( offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2A && offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; return


<s> NextMII = std :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) || MI -> isTransient ( ) ) continue ; Modified |= ReduceMI ( MII )


<s> return ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>


<s> STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; unsigned InsPosition = <NUM_LIT> ; unsigned InsSize = <NUM_LIT> ; unsigned SrcReg = <STR_LIT> ; if ( IntKind == <STR_LIT> ) { SrcReg = <STR_LIT> ; InsPosition = <NUM_LIT> ; InsSize = <NUM_LIT> ; } else InsSize = StringSwitch < unsigned > ( IntKind ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; assert ( InsSize != <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( InsPosition ) . addImm ( InsSize ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! STI . useSoftFloat ( ) ) BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> )


<s> } } live_regs_mask &= ~ <NUM_LIT> ; } had_to_push_lr = ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ; live_regs_mask &= <NUM_LIT> ; if ( crtl -> args . pretend_args_size == <NUM_LIT> || TARGET_BACKTRACE ) { if ( had_to_push_lr ) live_regs_mask |= <NUM_LIT> << PC_REGNUM ; if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( ! had_to_push_lr ) thumb_exit ( asm_out_file , LR_REGNUM ) ; } else { if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( had_to_push_lr ) { if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } thumb_pop ( asm_out_file , <NUM_LIT> << LAST_ARG_REGNUM ) ; if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; asm_fprintf ( asm_out_file , <STR_LIT> , LAST_ARG_REGNUM , IP_REGNUM ) ; regno = LR_REGNUM ; } else regno = LAST_ARG_REGNUM


<s> void <ISA_LIT>AuthMCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const { llvm_unreachable (


<s> assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ?

<NUM_LIT> : RegShiftedImm . ShiftImm ) ;


<s> mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>elTarget , mcld :: emulate<ISA_LIT>LD ) ; mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>64elTarget , mcld ::


<s> StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ; assert ( StoreNode && <STR_LIT> ) ; SDValue Value = StoreNode -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthVectorStoreToSVE ( Op , DAG ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment . value ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) ->

getValueType ( <NUM_LIT> ) == <STR_LIT> ) ;


<s> rtx fpu_insn ; rtx reg , mem ; unsigned int regno = cfun -> machine -> callee_saved_first_fpr_regno ; unsigned int last_fpr = cfun -> machine -> callee_saved_last_fpr_regno ; while ( regno <= last_fpr ) { reg = gen_rtx_REG ( DFmode , regno ) ; mem = gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , base_offset ) ) ; base_offset += <NUM_LIT> ; regno += <NUM_LIT> ; fpu_insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( fpu_insn ) =


<s> EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) { int Iterations = Subtarget . hasRecipPrec ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( VT . getScalarType ( ) == <STR_LIT> ) ++ Iterations ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( Op ) ; SDValue FPThreeHalves = DAG . getConstantFP ( <NUM_LIT> , VT . getScalarType ( ) ) ; if ( VT . isVector ( ) ) { assert ( VT . getVectorNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; FPThreeHalves = DAG . getNode ( <STR_LIT> , dl , VT , FPThreeHalves , FPThreeHalves , FPThreeHalves , FPThreeHalves ) ; } SDValue Est = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ; SDValue HalfArg = DAG . getNode ( <STR_LIT> , dl , VT , FPThreeHalves , Op ) ; DCI . AddToWorklist ( HalfArg . getNode ( ) ) ; HalfArg = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg , Op ) ; DCI . AddToWorklist ( HalfArg . getNode ( ) ) ; for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) { SDValue NewEst = DAG . getNode ( <STR_LIT> , dl , VT , Est , Est ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg


<s> return ( __mmask32 ) __builtin_ia32_ptestmb256 ( ( __v32qi ) __A , (


<s> return ( __m128d ) __builtin_ia32_vfmaddsd3 ( ( __v2df ) __A , (


<s> return ( __m64 ) __builtin_ia32_pmuludq ( ( __v2si )


<s> addPass ( new Legalizer ( ) ) ; return


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; Pic = MCA . getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; ABI = <ISA_LIT>ABIInfo ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mipsel || STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mips ? <ISA_LIT>ABIInfo :: O32 ( ) : <ISA_LIT>ABIInfo :: N64 ( ) ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features [ <STR_LIT> ] ) EFlags |=


<s> EVT ArgVT = Arg . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( ArgVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( ArgVT , VT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDLoc dl ( Op ) ; MakeLibCallOptions CallOptions ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , <STR_LIT> , Arg , CallOptions , dl , Chain ) ; Result = DAG . getBitcast ( VT


<s> HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; UseSqrtEst =


<s> Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain .


<s> static SDValue PerformABSCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; return TLI . expandABS ( N , DAG


<s> if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( )


<s> assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( TREE_PUBLIC ( decl ) && ! DECL_WEAK ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; putc ( '\n' , file ) ; } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) && ! TARGET_SECURE_PLT && ( ! constant_pool_empty_p ( ) || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name == '.' ) desc_name ++ ; if ( TREE_PUBLIC ( decl ) ) fprintf ( file , <STR_LIT> , desc_name ) ; fprintf ( file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; fprintf ( file , <STR_LIT> , desc_name ) ; fprintf ( file , <STR_LIT> ,


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment


<s> default : gcc_unreachable ( ) ; } } if ( y == const0_rtx && ( REG_P ( x ) || SUBREG_P ( x ) ) && ( code == EQ || code == NE ) && ( mode_x == HImode || mode_x == QImode ) ) return CC_NZmode ; if ( y == const0_rtx && code_x == ZERO_EXTEND && ( mode_x == SImode || mode_x == DImode ) && ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == HImode || GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == QImode ) && ( code == EQ || code == NE ) ) return CC_NZmode ; if ( ( mode_x == SImode || mode_x == DImode ) && y == const0_rtx && ( code == EQ || code == NE || code == LT || code == GE ) && ( code_x == PLUS || code_x == MINUS || code_x == AND || code_x == NEG || ( code_x == ZERO_EXTRACT && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ) ) return CC_NZmode ; if ( ( mode_x == SImode || mode_x == DImode ) && ( REG_P ( y ) || SUBREG_P ( y ) || y == const0_rtx ) && ( code_x == ASHIFT || code_x == ASHIFTRT || code_x == LSHIFTRT || code_x == ZERO_EXTEND || code_x == SIGN_EXTEND ) ) return CC_SWPmode ; if ( ( mode_x == SImode || mode_x == DImode ) && ( REG_P ( y ) || SUBREG_P ( y

) ) && ( code == EQ || code == NE ) && code_x == NEG ) return CC_Zmode ;


<s> uint64_t CurrBlockFreq = MBFI -> getBlockFreq ( MI -> getParent ( ) ) . getFrequency ( ) ; if ( CurrBlockFreq > EntryFreq || MPDT -> dominates ( MI -> getParent ( ) , Entry ) ) FI -> setMustSaveTOC ( true ) ; if ( FI -> mustSaveTOC ( ) ) { for ( auto & TOCSave : TOCSaves ) TOCSave . second = false ; TOCSaves [ MI ] = false ; return ; } bool Keep = true ; for ( auto It = TOCSaves . begin ( ) ; It != TOCSaves . end ( ) ; It ++ ) { MachineInstr * CurrInst = It -> first ; if ( It -> second && MDT -> dominates ( MI , CurrInst ) ) It -> second = false ; if ( MDT -> dominates ( CurrInst , MI ) ) { Keep = false ; break ; } } TOCSaves [ MI ]


<s> return ( __m128h ) __builtin_ia32_getexpsh_mask_round ( ( __v8hf ) __A , ( __v8hf ) __B , ( __v8hf ) _mm_setzero_ph ( ) , ( __mmask8 )


<s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst ,


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? ( is64Bit ? <STR_LIT> : <STR_LIT> ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( requiresRegisterScavenging ( MF ) ) { const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; SReg = findScratchRegister ( II , RS , is64Bit ? G8RC : GPRC , SPAdj ) ; } else SReg = is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg )

. addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ;


<s> NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) ,


<s> return __builtin_shuffle ( a , ( uint16x8_t ) { <NUM_LIT> , <NUM_LIT> ,


<s> if ( InputLoad && InputLoad -> getExtensionType ( ) != <STR_LIT> ) return addExtOrTrunc ( Input , ExtOrTruncConversion :: Ext ) ; SDLoc dl ( Input ) ; ZeroExtensionsAdded ++ ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Input , S -> getI64Imm ( <NUM_LIT> , dl ) , S ->

getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum +


<s> return & InstrInfo . getRegisterInfo (


<s> inline bool isImmZExtu32u8Value ( uint64_t Value ) { return ( Value <=


<s> __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] / __B [ <NUM_LIT> ] ; return (


<s> if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86 ) addPass ( create<ISA_LIT>WinEHStatePass ( ) ) ; return true


<s> static __inline qword si_mpyhh ( qword a , qword b


<s> void neg ( ) { asm_fprintf ( t_file , <STR_LIT> ,


<s> static void mips_start_ll_sc_sync_block ( void ) { if ( !


<s> if ( ! isAMXIntrinsic ( Tile ) ) return ; auto * II = cast < IntrinsicInst > ( Tile ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( ST ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( ST -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Tile } ; Builder . CreateIntrinsic ( <STR_LIT> , None ,


<s> getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAdduOp ( ) ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg = Reg ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ; MI . getOperand ( OpNo + <NUM_LIT> )


<s> Lea . addOperand ( MCOperand :: CreateReg ( getReg64 ( Op . getReg ( ) ) ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> )


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , Op . getDebugLoc ( ) , getPointerTy ( ) , Offset ) ; return DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , getPointerTy (


<s> return ( __m256i ) __builtin_ia32_palignr256 ( ( __v4di ) __A ,


<s> unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; if ( SubIdx == <STR_LIT> && FP64 ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DstReg ) . addReg ( SubReg ) ; else BuildMI ( MBB , I , dl , get (


<s> } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> )


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOpcode ( ) == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; Offset = TFI -> getNonLocalFrameIndexReference ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( )

, ScratchReg , FrameReg , Offset , TII ) ;


<s> static bool printModifiedFPRAsmOperand ( const MachineOperand & MO , const TargetRegisterInfo * TRI , char RegType , raw_ostream & O ) { if ( ! MO . isReg ( ) ) return true ; for ( MCRegAliasIterator AR ( MO . getReg ( ) , TRI , true ) ; AR . isValid ( ) ; ++ AR ) { if ( <STR_LIT> . contains ( * AR ) ) { O << RegType << TRI -> getEncodingValue ( MO . getReg ( ) ) ; return false ; } } return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile >

( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) {


<s> const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext ) , PointerSize ) ; OutStreamer -> emitIntValue ( <NUM_LIT> ,


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Equal ) ) return reportParseError ( <STR_LIT> ) ; Parser . Lex ( ) ; StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; if ( Arch . empty ( ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ArchFeatureName . empty ( ) ) return reportParseError ( <STR_LIT> ) ; if ( ArchFeatureName == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) return reportParseError ( <STR_LIT> ) ; selectArch ( ArchFeatureName ) ; getTargetStreamer ( ) . emitDirectiveSetArch


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) { object :: mach :: CPUSubtype<ISA_LIT> CS = StringSwitch < object :: mach :: CPUSubtype<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7F

) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7S ) . Default ( object :: mach :: CS<ISA_LIT>_V7 ) ;


<s> assert ( isPositionIndependent ( ) ) ; SDLoc DL ( Table ) ; Function * Function = & DAG . getMachineFunction ( ) . getFunction ( ) ; assert ( Function != nullptr ) ; auto PtrTy = getPointerTy ( DAG . getDataLayout ( ) ,


<s> const struct mips_builtin_description * d ; unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DL ( Subtarget . getDataLayoutString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Subtarget . isBGP ( ) ) setMCUseCFI


<s> void addDstIdxOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg (


<s> if ( code == ASHIFT ) { max = ext_ashl_lshr_seq [ value ] . insn_count ; for ( i = <NUM_LIT> ; i < max ; i ++ ) gen_fun ( code , ext_ashl_lshr_seq [ value ] . amount [ i ] , operands [ <NUM_LIT> ] ) ; } else for ( i = ext_ashl_lshr_seq [ value ] . insn_count - <NUM_LIT> ; i >= <NUM_LIT> ; i --


<s> return ; } unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; } else { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII .


<s> BusyRegs . push_back ( convReg ( AddressReg , <NUM_LIT> ) ) ; BusyRegs . push_back ( convReg ( ShadowReg ,


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned


<s> static inline bool hasInefficientLEABaseReg ( const MachineOperand & Base ,


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) -> optForSize ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget >


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case


<s> if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; Peephole<ISA_LIT>64 ( ) ; PeepholeCROps (


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isHalfTy ( ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace (


<s> int i ; int check_regno ; rtx elt ; rtx elt_reg ; rtx elt_mem ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { elt = XVECEXP ( op , <NUM_LIT> , i + par_index ) ; if ( GET_CODE ( elt ) != SET ) return false ; elt_reg = load_p ? SET_DEST ( elt ) : SET_SRC ( elt ) ; elt_mem = load_p ? SET_SRC ( elt ) : SET_DEST ( elt ) ; if ( GET_CODE ( elt_reg ) != REG || GET_MODE ( elt_reg ) != SImode ) return false ; if ( GET_CODE ( elt_mem ) != MEM || GET_MODE ( elt_mem )


<s> if ( fpscr_values == NULL ) { tree t ; t = build_index_type ( integer_one_node ) ; t = build_array_type ( integer_type_node , t ) ; t = build_decl ( VAR_DECL , get_identifier ( <STR_LIT> ) , t ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_EXTERNAL ( t ) = <NUM_LIT> ; TREE_STATIC ( t ) = <NUM_LIT> ; TREE_PUBLIC ( t ) = <NUM_LIT> ; TREE_USED ( t ) = <NUM_LIT> ; fpscr_values = t ; } src = DECL_RTL ( fpscr_values ) ; if ( no_new_pseudos ) { emit_move_insn ( scratch , XEXP ( src , <NUM_LIT> ) ) ; if ( index != <NUM_LIT> ) emit_insn ( gen_addsi3 ( scratch , scratch , GEN_INT ( index * <NUM_LIT> ) ) ) ; src = adjust_automodify_address ( src , PSImode , scratch , index * <NUM_LIT> ) ; } else src = adjust_address ( src , PSImode , index * <NUM_LIT> ) ; dst = get_fpscr_rtx ( ) ; emit_move_insn ( dst , src )


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( RV ) ) { CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( CI , <STR_LIT> , VA . getLocInfo ( ) != CCValAssign :: ZExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , dl , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , dl , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; } else { strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf ,


<s> ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregxiv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregxiv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto * Regs = Subtarget -> getSpecialRegisters


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT>

, MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable ) ;


<s> if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return <NUM_LIT> ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC


<s> return ( x * ( y >> <NUM_LIT> ) + ( y >>


<s> RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { return false ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( Op0Reg ) . addReg ( Op0Reg ) ; unsigned ResultReg = createResultReg


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; return true


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc = Cond . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( Cond . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Cond -> getValueType (


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) { PSHUFBMask [ <NUM_LIT> * i ] = PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } int M = i < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> ; assert ( M >= <NUM_LIT> && M


<s> static int pru_arg_partial_bytes ( cumulative_args_t , const function_arg_info


<s> bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType )

&& Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ;


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto LoadMnemonic = <STR_LIT> ; auto StoreMnemonic = <STR_LIT> ; switch ( AtomicSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; assert ( Subtarget . hasPartwordAtomics ( ) && <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; assert ( Subtarget . hasPartwordAtomics ( ) && <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; unsigned dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = CmpOpcode ? F -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; if ( CmpOpcode ) F -> insert ( It , loop2MBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB )


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << getRegisterName ( MO2 .


<s> static TargetLoweringObjectFile * createTLOF ( <ISA_LIT>TargetMachine & TM ) { switch ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . TargetType ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>Subtarget :: isDarwin : if ( Enable<ISA_LIT>EHTest ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_test_MachoTargetObjectFile ( ) ; else return new <ISA_LIT>_test_MachoTargetObjectFile ( ) ; } if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; case <ISA_LIT>Subtarget :: isELF


<s> case FpABIKind :: S32 : return Val_GNU_MIPS_ABI_FP_DOUBLE ; case FpABIKind :: S64 : if ( Is32BitABI ) return OddSPReg ? Val_GNU_MIPS_ABI_FP_64 : Val_GNU_MIPS_ABI_FP_64A ; return Val_GNU_MIPS_ABI_FP_DOUBLE


<s> if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT>


<s> if ( ( InNumEltBits - NumPackedZeroBits ) <= Known . countMinLeadingZeros ( ) ) if ( SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( InNumEltBits - NumPackedSignBits ) < DAG . ComputeNumSignBits ( In ) ) if ( SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getBitcast ( <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL


<s> sysctl ( l1_line_name , <NUM_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; sysctl ( l2_size_name , <NUM_LIT> , & l2_sizekb , & len , NULL , <NUM_LIT> ) ; l1_assoc = <NUM_LIT> ; return describe_cache ( l1_sizekb / <NUM_LIT> , l1_line , l1_assoc , l2_sizekb / <NUM_LIT>


<s> LoadSDNode * LdNode = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; assert ( LdNode && LdNode -> getOffset ( ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned alignment = LdNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> ,


<s> Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / <NUM_LIT> : <NUM_LIT> ) ; Info . readMem = true ; break ; } case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = <NUM_LIT> ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . align = <NUM_LIT> ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = <NUM_LIT> ; Info . writeMem = true ; break ; } case STOREA : case STOREANT : case STOREU


<s> MIRBuilder . setInstr ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( { NewTy } , { ValReg } ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) ,