<s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> case <STR_LIT> : return EmitLoweredWinAlloca ( MI , BB ) ; case <STR_LIT> : return EmitLoweredSegAlloca ( MI , BB , false ) ; case <STR_LIT> : return EmitLoweredSegAlloca ( MI , BB , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitLoweredTLSCall ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return EmitLoweredSelect ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineFunction * F = BB -> getParent ( ) ; const TargetInstrInfo * TII = F -> getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int CWFrameIdx = F -> getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; addFrameReference ( BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) , CWFrameIdx ) ; unsigned OldCW = F -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; addFrameReference ( BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , OldCW ) , CWFrameIdx ) ; addFrameReference ( BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) , CWFrameIdx ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) , CWFrameIdx ) ; addFrameReference ( BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) , CWFrameIdx ) . addReg ( OldCW ) ; unsigned Opc ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> } MachineInstr * ToErase = nullptr ; if ( TII -> simplifyRotateAndMaskInstr ( MI , ToErase ) ) { Changed = true ; NumRotateInstrFoldInPreEmit ++ ; if ( ToErase ) InstrsToErase . push_back ( ToErase ) ; } } auto I = MBB . getFirstInstrTerminator ( ) ; if ( I == MBB . instr_end ( ) ) continue ; MachineInstr * Br = & * I ; if ( Br -> getOpcode ( ) != <STR_LIT> && Br -> getOpcode ( ) != <STR_LIT> ) continue ; MachineInstr * CRSetMI = nullptr ; Register CRBit = Br -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CRReg = getCRFromCRBit ( CRBit ) ; bool SeenUse = false ; MachineBasicBlock :: reverse_iterator It = Br , Er = MBB . rend ( ) ; for ( It ++ ; It != Er ; It ++ ) { if ( It -> modifiesRegister ( CRBit , TRI ) ) { if ( ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) && It -> getOperand ( <NUM_LIT> ) . getReg ( ) == CRBit ) CRSetMI = & * It ; break ; } if ( It -> readsRegister ( CRBit , TRI ) ) SeenUse = true ; } if ( ! CRSetMI ) continue ; unsigned CRSetOp = CRSetMI -> getOpcode ( ) ; if ( ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) || ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) ) { InstrsToErase . push_back ( Br ) ; MBB . removeSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; } else { MachineBasicBlock :: iterator It = Br , Er = MBB . end ( ) ; for ( ; It != Er ; It ++


<s> void printOperand ( const MachineInstr * MI , unsigned OpNo , const char * Modifier = <NUM_LIT> ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . Name ; } else { printOp ( MO ,


<s> if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> MVT VT = OrigOp . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; SDLoc DL ( Op . getNode ( ) ) ; auto BitcastAndCombineShuffle = [ & ] ( unsigned Opcode , SDValue Op0 , SDValue Op1 , SDValue Op2 ) { Op0 = DAG . getBitcast ( VT , Op0 ) ; DCI . AddToWorklist ( Op0 . getNode ( ) ) ; Op1 = DAG . getBitcast ( VT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , Op2 ) ) ; return true ; } ; unsigned Opcode = Op . getOpcode ( ) ; switch (


<s> bool <ISA_LIT>RegisterInfo :: isLowRegister ( unsigned Reg ) const { using namespace <ISA_LIT> ; switch ( Reg ) { case R0 : case R1 : case R2 : case R3 : case R4 : case R5 :


<s> for ( unsigned R : AllocSet . set_bits ( ) ) for ( MCRegAliasIterator AI ( R , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AllocSet . set ( * AI ) ; AllocSet . set (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { APInt SubMask = APInt :: getSplat ( VWidth , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt AddMask = APInt :: getSplat ( VWidth , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; bool IsSubOnly = DemandedElts . isSubsetOf ( SubMask ) ; bool IsAddOnly = DemandedElts . isSubsetOf ( AddMask ) ; if ( IsSubOnly || IsAddOnly ) { assert ( ( IsSubOnly ^ IsAddOnly ) && <STR_LIT> ) ; IRBuilderBase :: InsertPointGuard Guard ( IC . Builder ) ; IC . Builder . SetInsertPoint ( & II ) ; Value * Arg0 = II . getArgOperand ( <NUM_LIT> ) , * Arg1 = II . getArgOperand ( <NUM_LIT> ) ; return IC . Builder . CreateBinOp ( IsSubOnly ? Instruction :: FSub : Instruction :: FAdd , Arg0 , Arg1 ) ; } simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; UndefElts &= UndefElts2 ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto * Ty0 = II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; unsigned InnerVWidth = cast < FixedVectorType > ( Ty0 ) -> getNumElements ( ) ; assert ( VWidth == ( InnerVWidth * <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = Ty0 -> getPrimitiveSizeInBits ( ) / <NUM_LIT> ; unsigned VWidthPerLane = VWidth / NumLanes ; unsigned InnerVWidthPerLane = InnerVWidth / NumLanes ; for ( int OpNum = <NUM_LIT> ; OpNum != <NUM_LIT> ; ++ OpNum ) { APInt OpDemandedElts ( InnerVWidth , <NUM_LIT> ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { unsigned LaneIdx = Lane * VWidthPerLane ; for ( unsigned Elt = <NUM_LIT> ; Elt != InnerVWidthPerLane ; ++ Elt ) { unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum ; if ( DemandedElts [ Idx ] ) OpDemandedElts . setBit ( ( Lane * InnerVWidthPerLane ) + Elt ) ; } } APInt OpUndefElts ( InnerVWidth , <NUM_LIT> ) ; simplifyAndSetOp ( & II , OpNum , OpDemandedElts , OpUndefElts ) ; OpUndefElts = OpUndefElts . zext ( VWidth ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { APInt LaneElts = OpUndefElts . lshr ( InnerVWidthPerLane * Lane ) ; LaneElts = LaneElts . getLoBits ( InnerVWidthPerLane ) ; LaneElts <<= InnerVWidthPerLane * ( <NUM_LIT> * Lane + OpNum ) ; UndefElts |= LaneElts ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget -> useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue ( <NUM_LIT> ) ; return DAG . getLoad ( ArgVT , dl , Chain , VAARG , MachinePointerInfo ( ) , false , false , false


<s> type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type

) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isDereferenceableInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT>


<s> unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size (


<s> if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & TRI ) ; return


<s> } else if ( STI . isRWPI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) || STI . isROPI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . FPDenormalMode == FPDenormal :: PreserveSign ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . FPDenormalMode == FPDenormal :: PositiveZero ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else { if ( ! STI . hasVFP2Base ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3Base ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . NoTrappingFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT>


<s> void emitCantUnwindLocNotes ( ) const { for ( Locs :: const_iterator UI = CantUnwindLocs . begin ( ) , UE = CantUnwindLocs . end ( ) ; UI != UE ;

++ UI ) Parser . Note ( * UI , <STR_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( )


<s> InstructionCost <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { const unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; } return BaseT :: getAddressComputationCost ( Ty , SE


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , STI . getFramePointerReg ( ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasD32 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> +


<s> if ( isAnyMOVZMovAlias ( Value , RegWidth ) ) return false ; Value = ~ Value ; if ( RegWidth == <NUM_LIT> )


<s> name += skip ; } if ( verbatim ) fputs ( name , stream ) ; else asm_fprintf ( stream , <STR_LIT>


<s> LowerXConstraint ( MVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 (


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( CallingConv :: ID CC , bool Return , bool isVarArg ) { switch ( CC ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: Fast : if ( Subtarget -> hasVFP2Base ( ) && ! isVarArg ) { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; } LLVM_FALLTHROUGH ; case CallingConv :: C : case CallingConv :: CXX_FAST_TLS : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2Base ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : if ( ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; LLVM_FALLTHROUGH ; case CallingConv ::


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc

:: PIC_ ) Reserved . set ( <STR_LIT> ) ;


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill


<s> if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; Align Alignment = GV -> getPointerAlignment ( CurDAG -> getDataLayout ( ) ) ; MaxDisplacement = std :: min ( ( int ) Alignment . value ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else { if ( auto * C = dyn_cast < ConstantSDNode > ( ImmOpnd ) ) { Offset += C -> getSExtValue ( ) ; if ( RequiresMod4Offset && ( Offset % <NUM_LIT> ) != <NUM_LIT> ) continue ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) continue ; ImmOpnd = CurDAG -> getTargetConstant ( Offset , SDLoc ( ImmOpnd ) , ImmOpnd . getValueType ( ) ) ; } else if ( Offset != <NUM_LIT> ) { continue ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; Align Alignment = GV -> getPointerAlignment (


<s> virtual ~ <ISA_LIT>CallingConventionRegisters (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID ) ; } } if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( createThumb2ITBlockPass ( ) ) ; return


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent (


<s> if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition (


<s> bool IsInteresting = AI . getAllocatedType ( ) -> isSized ( ) && AI . isStaticAlloca ( ) && AI . getAllocationSizeInBits ( * DL ) . getValue ( ) >

<NUM_LIT> && ! AI . isUsedWithInAlloca ( ) && ! AI . isSwiftError ( ) && ! ( SSI && SSI -> isSafe ( AI ) ) ;


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != <NUM_LIT> )

add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ;


<s> Inst >>= <NUM_LIT> ; } getStreamer ( ) . EmitBytes ( StringRef (


<s> static inline bool isAdvSIMDModImmType2 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> std :: unique_ptr < ScheduleDAGMutation > create<ISA_LIT>MacroFusionDAGMutation ( ) { return createBranchMacroFusionDAGMutation ( shouldScheduleAdjacent


<s> bool Filler :: searchBackward ( MachineBasicBlock & MBB , Iter Slot ) const { if ( DisableBackwardSearch ) return false ; auto * Fn = MBB . getParent ( ) ; RegDefsUses RegDU ( * Fn -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MemDefsUses MemDU ( Fn -> getDataLayout ( ) , & Fn


<s> auto * Mask = dyn_cast < ConstantSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask ) return ; KnownBits Known = DAG . computeKnownBits ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ( ~ Known . Zero ) . getZExtValue ( ) & ~ Mask -> getZExtValue ( ) ) return ; C . Op0 = C . Op0 . getOperand ( <NUM_LIT>


<s> if ( size < <NUM_LIT> * UNITS_PER_WORD ) { pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( type ) ) return false ; return true ; } } return !


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? <STR_LIT> : <STR_LIT> ) ; return RegNum


<s> static inline bool getPreviousInstr ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { if ( I == MFI -> begin ( )


<s> if ( pool_size ) { fprintf ( asm_out_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value ) ; } pool_size = <NUM_LIT> ; } return


<s> Value = <STR_LIT> ( ~ Value & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> if ( ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || ! isImmSExti16i8Value (

Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ;


<s> case <STR_LIT> : LowerPATCHABLE_TAIL_CALL ( * MI ) ; return ; } if ( EmitJalrReloc && ( MI -> isReturn ( ) || MI -> isCall ( ) || MI -> isIndirectBranch ( ) ) ) { emitDirectiveRelocJalr ( * MI , OutContext , TM , * OutStreamer , * Subtarget ) ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isBundle ( ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( &


<s> LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { LoadOpcode = <STR_LIT> ; StoreOpcode =


<s> CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> HOST_WIDE_INT loongarch_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == <NUM_LIT> ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame .


<s> return __aarch64_vset_lane_any ( * __src ,


<s> for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << unsigned ( BBI . PostAlign ) << format ( <STR_LIT> , BBInfo [


<s> static bool mips_tls_symbol_p ( rtx x


<s> Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget


<s> rtx sub ; gcc_assert ( float_mode_p ) ; * total = sparc_costs -> float_mul ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , FMA , <NUM_LIT> , speed ) ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , FMA , <NUM_LIT> , speed ) ; return true ; } case MULT : if ( float_mode_p ) * total = sparc_costs -> float_mul ; else if ( TARGET_ARCH32 && ! TARGET_HARD_MUL ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else { int bit_cost ; bit_cost = <NUM_LIT> ; if ( sparc_costs -> int_mul_bit_factor ) { int nbits ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; for ( nbits = <NUM_LIT> ; value != <NUM_LIT> ; value &= value - <NUM_LIT> ) nbits ++ ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_DOUBLE && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == VOIDmode ) { rtx x1 = XEXP ( x , <NUM_LIT> ) ; unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW ( x1 ) ; unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH ( x1 ) ; for ( nbits = <NUM_LIT> ; value1 != <NUM_LIT> ; value1 &= value1 - <NUM_LIT> ) nbits ++ ; for ( ; value2 != <NUM_LIT> ; value2 &= value2 - <NUM_LIT> ) nbits ++ ; } else nbits = <NUM_LIT> ; if ( nbits < <NUM_LIT> ) nbits = <NUM_LIT> ; bit_cost = ( nbits - <NUM_LIT> ) / sparc_costs -> int_mul_bit_factor ; bit_cost = COSTS_N_INSNS ( bit_cost ) ; } if ( mode == DImode || ! TARGET_HARD_MUL ) * total = sparc_costs -> int_mulX + bit_cost ; else * total = sparc_costs -> int_mul + bit_cost ; } return false ; case ASHIFT : case


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; return


<s> SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= <NUM_LIT> ) IndexNodes [ I ] = DAG . getConstant ( Bytes [ I ] , DL , <STR_LIT> ) ; else IndexNodes [ I ] = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IndexNodes ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT>


<s> return getLinkageSize ( LP64 , isMacho ) + getMinCallArgumentsSize ( LP64


<s> return ( vector unsigned short ) __builtin_altivec_vminuh ( ( vector signed short ) a1 , (


<s>
void
FPOStateMachine
::
emitFrameDataRecord
(
MCStreamer
&
OS
,
MCSymbol
*
Label
)
{
unsigned
CurFlags
=
Flags
;
if
(
Label
==
FPO
->
Begin
)
CurFlags
|=
FrameData
::
IsFunctionStart
;
FrameFunc
.
clear
(
)
;
raw_svector_ostream
FuncOS
(
FrameFunc
)
;
const
MCRegisterInfo
*
MRI
=
OS
.
getContext
(
)
.
getRegisterInfo
(
)
;
assert
(
(
StackAlign
==
<NUM_LIT>
||
FrameReg
!=
<NUM_LIT>
)
&&
<STR_LIT>
)
;
StringRef
CFAVar
=
StackAlign
==
<NUM_LIT>
<STR_LIT>
:
<STR_LIT>
;
if
(
FrameReg
)
{
FuncOS
<<
CFAVar
<<
' '
<<
printFPOReg
(
MRI
,
FrameReg
)
<<
' '
<<
FrameRegOff


<s> int ret ; if ( TARGET_DEBUG_COST ) dbg_cost_ctrl ++ ; if ( reg_classes_intersect_p ( to , GENERAL_REGS ) || reg_classes_intersect_p ( from , GENERAL_REGS ) ) { reg_class_t rclass = from ; if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) rclass = to ; if ( rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS ) ret = ( rs6000_memory_move_cost ( mode , rclass , false ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , false ) ) ; else if ( rclass == CR_REGS ) ret = <NUM_LIT> ; else if ( ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names


<s> static bool gvNeedsNonLazyPtr ( const MachineOperand & GVOp , const TargetMachine & TM ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return false ; return isGlobalStubReference ( GVOp . getTargetFlags


<s> } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) && canRealignStack ( MF ) ) ) { if ( isFrameOffsetLegal ( MI , FPOffset )


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiv16qi (


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == <NUM_LIT> ) return base_align ; return MIN ( base_align , offset &


<s> if ( Fields . size ( ) > <NUM_LIT> ) { bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; } assert ( AllIntFields &&


<s> bool isLegalAndnType = VT == <STR_LIT> || VT == <STR_LIT> ; if ( ! Subtarget . hasBMI ( ) || ! isAndn || ! isLegalAndnType ) break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { if ( SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; } if ( ConvertedOp ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( WideVal . getOpcode ( ) , WideVT ) ) { SDValue V0 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( ConvertedOp , dl , VT , V0 , V1 ) ; } } } if ( Opcode == <NUM_LIT> ) { if ( auto Node = EmitKTEST ( Op , DAG ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getWindowsStackProbePreservedMask


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> , Base


<s> const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ; SDValue RegNodeBase = DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , DAG . getConstant ( RegNodeSize , dl , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , RegNodeBase ,


<s> AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setReorder ( ) ; getTargetStreamer ( ) . emitDirectiveSetReorder (


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask1 ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask2 ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getSignExtendVectorInReg ( OpLo , dl , HalfVT ) ; OpHi = DAG . getSignExtendVectorInReg ( OpHi , dl , HalfVT ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> return <NUM_LIT> ; } if ( int_size_in_bytes ( type ) < <NUM_LIT> ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; warned_for_pass_big_vectors = true ; } return <NUM_LIT>


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; Result = DAG . getNode ( isAdd ? <STR_LIT> : <STR_LIT> , DL , VT , Result , N -> getOperand ( <NUM_LIT> ) ) ; return Result ; } ; switch ( MulAmt ) { default : break ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , false ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , false ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateITMask ( unsigned Mask , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_ITCondMask ) ; Op -> ITMask . Mask = Mask ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Clz = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor ) , <NUM_LIT> ) ; SDValue ShiftOps [ ] = { Clz , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; } case <STR_LIT>


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind


<s> if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; assert ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties

:: Property :: Legalized ) && <STR_LIT> ) ;


<s> CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_Fast ) ; } else { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else


<s> assert ( Align > <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (

Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ;


<s> getDwarfRegNum ( unsigned RegNum , bool isEH ) const { assert ( <NUM_LIT> && <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const


<s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I

) Offset = alignTo ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ;


<s> unsigned getPointerSize ( ) const { return


<s> MVT MaskVT = Mask . getValueType ( ) ; MVT EltVT = MaskVT . getVectorElementType ( ) ; unsigned NumElems = Mask . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; DebugLoc dl = Op . getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Arg = Mask . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { MaskVec . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val < NumElems ) MaskVec . push_back ( DAG . getConstant ( Val + NumElems , EltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( Val - NumElems , EltVT ) ) ; } std :: swap ( V1 , V2 ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , & MaskVec [ <NUM_LIT> ] , NumElems ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ,

Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ;


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCA . setELFHeaderEFlags (


<s> static inline unsigned getIImm3Imm8 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> |


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; auto ceil = [ ] ( unsigned A , unsigned B ) { return ( A + B - <NUM_LIT> ) / B ; } ; unsigned NumElts = VecTy -> getVectorNumElements ( ) ; assert ( Factor > <NUM_LIT> && NumElts % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned VF = NumElts / Factor ; unsigned NumEltsPerVecReg = ( <NUM_LIT> / getScalarSizeInBits ( VecTy ) ) ; unsigned NumVectorMemOps = getNumVectorRegs ( VecTy ) ; unsigned NumPermutes = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) { BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector ( NumVectorMemOps , false ) ) ; for ( unsigned Index : Indices ) for ( unsigned Elt = <NUM_LIT> ; Elt < VF ; ++ Elt ) { unsigned Vec = ( Index + Elt * Factor ) / NumEltsPerVecReg ; UsedInsts . set ( Vec ) ; ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy ) , <NUM_LIT> ) ; assert ( NumSrcVecs >= NumDstVecs


<s> static BOOL isPrefixAtLocation ( struct InternalInstruction * insn , uint8_t prefix , uint64_t location ) { if ( insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [ prefix ] == location ) return TRUE ; else return


<s> unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? <NUM_LIT> : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - <NUM_LIT> ; } if ( TARGET_64BIT ) return <NUM_LIT> ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < <NUM_LIT> ) || distance < <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( flag_pic


<s> bool <ISA_LIT>TargetLowering :: isVectorClearMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( ! Subtarget . hasAVX2 ( ) ) if ( VT == <STR_LIT> || VT == <STR_LIT>


<s> return new <ISA_LIT>PostSelectOptimize (


<s> VariantKind getKind ( ) const { return Kind


<s> SmallVector < int , <NUM_LIT> > Mask ; Mask . push_back ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) Mask


<s> return ( uint16x4_t ) ( vabs_f16 ( __a )


<s> if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getNode ( useSSE ? <STR_LIT> : <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction (


<s> if ( ! ( isABI_N32 ( ) || isABI_N64 ( ) ) ) return CC ; if ( <NUM_LIT> <= CC && CC <= <NUM_LIT> ) { AsmToken RegTok = getLexer ( ) . peekTok ( ) ; SMRange RegRange = RegTok . getLocRange ( ) ; StringRef FixedName = StringSwitch < StringRef > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; assert ( FixedName != <STR_LIT> && <STR_LIT> ) ; printWarningWithFixIt ( <STR_LIT> , <STR_LIT> + FixedName + <STR_LIT> , RegRange ) ; } if ( <NUM_LIT> <= CC && CC <= <NUM_LIT> ) CC += <NUM_LIT> ; if ( CC == - <NUM_LIT> ) CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; return CC


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHTrapFrame ( SMLoc L ) { getTargetStreamer ( ) . EmitARM64WinCFITrapFrame ( ) ; return false


<s> else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : { unsigned Imm = ( OpNum - OP_VEXT1 + <NUM_LIT> ) * getExtFactor ( OpLHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } case OP_VUZPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VUZPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VTRNL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS ,


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const


<s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset


<s> bool isCortexA15 ( ) const { return <ISA_LIT>ProcFamily


<s> if ( SYMBOL_REF_P ( x ) && ! TARGET_MACHO ) { enum tls_model model = SYMBOL_REF_TLS_MODEL ( x ) ; if ( model != <NUM_LIT> ) return rs6000_legitimize_tls_address ( x , model ) ; } extra = <NUM_LIT> ; switch ( mode ) { case E_TFmode : case E_TDmode : case E_TImode : case E_PTImode : case E_IFmode : case E_KFmode : extra = <NUM_LIT> ; break ; default : break ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = sext_hwi ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , gen_int_mode ( high_int , Pmode ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC_OR_PCREL && ! flag_pic && ! CONST_INT_P ( x ) && ! CONST_WIDE_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg ,


<s> } if ( PointerType * Ty = dyn_cast < PointerType > ( Obj -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr


<s> bool <ISA_LIT>BaseInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI . getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI . getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT>


<s> static void ix86_emit_move_max ( rtx dst , rtx src


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << LowercaseString ( getRegisterName ( RegNo )


<s> case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> )


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; assert ( ! isVarArg && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT>


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegFixed ( ) const { return FixGlobalBaseReg


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent (


<s> MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = macho :: RIT_Difference ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == macho :: RIT_Difference || Type == macho :: RIT_Generic_LocalDifference ) { macho :: RelocationEntry MRE ; MRE . Word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( macho :: RIT_Pair << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } macho :: RelocationEntry MRE ; MRE . Word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value ; Writer -> addRelocation ( Fragment -> getParent ( )


<s> static DecodeStatus DecodeGPRnopcRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo ,

uint64_t Address , const void * Decoder ) {


<s> memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ; maximum_field_alignment = m_old_maximum_field_alignment


<s> void <ISA_LIT>AsmPrinter :: printSavedRegsBitmask ( ) { unsigned CPUBitmask = <NUM_LIT> , FPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff , FPUTopSavedRegOff ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned FGR32RegSize = <STR_LIT> . getSize ( ) ; unsigned AFGR64RegSize = <STR_LIT> . getSize ( ) ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; unsigned i , e = CSI . size (


<s> emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_AND ( SImode , addr1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; memsi = gen_rtx_MEM ( SImode , addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; val = copy_to_reg ( memsi ) ; emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_XOR ( SImode , off , GEN_INT ( GET_MODE ( mem ) == QImode ? <NUM_LIT> : <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_ASHIFT ( SImode , off , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( GET_MODE ( mem ) == QImode ) mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; else mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_ASHIFT ( SImode , mask , off ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , val , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , val ) ) ) ; oldval = gen_lowpart ( SImode , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , oldv , gen_rtx_ASHIFT ( SImode , oldval , off ) ) ) ; newval = gen_lowpart_common ( SImode , newval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , newv , gen_rtx_ASHIFT ( SImode , newval , off ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , oldv , gen_rtx_AND ( SImode , oldv , mask ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , newv , gen_rtx_AND ( SImode , newv , mask ) ) ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; rtx_code_label * loop_label = gen_label_rtx ( ) ; emit_label ( loop_label ) ; emit_insn ( gen_rtx_SET ( VOIDmode , oldvalue , gen_rtx_IOR ( SImode , oldv , val ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , newvalue , gen_rtx_IOR ( SImode , newv , val ) ) ) ; emit_move_insn ( bool_result , const1_rtx ) ; emit_insn ( gen_atomic_compare_and_swapsi_1 ( res , memsi , oldvalue , newvalue ) ) ; emit_cmp_and_jump_insns ( res , oldvalue , EQ , NULL , SImode , <NUM_LIT> , end_label ) ; emit_insn ( gen_rtx_SET ( VOIDmode , resv , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode ,


<s> static const char * aarch64_invalid_conversion ( const_tree fromtype , const_tree totype ) { if ( element_mode ( fromtype ) != element_mode


<s> if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm .

getSExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> if ( vectype != NULL && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) && costs -> sve != NULL ) return costs -> sve ; return costs


<s> BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex ) . addImm

( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ! ConstExpr ) return false ; int64_t Value = ConstExpr -> getValue ( ) ; return isInt < <NUM_LIT>


<s> vld2q_u64 ( const uint64_t * __a ) { uint64x2x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t )


<s> static unsigned getSPReg ( const <ISA_LIT>Subtarget & STI ) { return


<s> unsigned long func_type = get_csky_current_func_type ( ) ; switch ( ( int ) CSKY_FUNCTION_TYPE ( func_type ) ) { default : case CSKY_FT_NORMAL : break ; case CSKY_FT_INTERRUPT : { asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> ) ; break ; } case CSKY_FT_FIQ : asm_fprintf ( f , <STR_LIT> ) ; break ; case


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; int64_t Imm ; if ( CI -> isNegative ( ) ) Imm = CI -> getSExtValue ( ) ; else Imm = CI -> getZExtValue (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N , DAG . getConstant ( <NUM_LIT> , DL


<s> static bool MorphToCoprocPairReg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; assert ( Op . Reg . Kind == rk_CoprocReg ) ; unsigned regIdx = <NUM_LIT> ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum = CoprocPairRegs [ regIdx / <NUM_LIT> ] ; Op . Reg . Kind


<s> return new <ISA_LIT>GenericDisassembler ( STI , Ctx , std :: move ( MII


<s> static rtx add_crlr_cfa_restore ( const rs6000_stack_t * info , rtx cfa_restores ) { if ( DEFAULT_ABI == ABI_ELFv2 ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx cr = gen_rtx_REG ( SImode , CR0_REGNO + i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , cr , cfa_restores ) ; } } else if ( info -> cr_save_p ) cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR2_REGNO )


<s> if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString


<s> const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue

( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; if ( ( NumBitsPerElt % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; APInt ShiftVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . zextOrTrunc ( <NUM_LIT> ) . uge ( NumBitsPerElt ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( ! ShiftVal ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) ==


<s> break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: <ISA_LIT>_FP80Ty || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPoint ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: DoubleTy ) ) { ContainsFPCode = true ; break ; } } } } if ( ContainsFPCode ) { BuildMI ( * MBB , MBBI -> getFirstTerminator ( ) , DebugLoc :: getUnknownLoc ( ) , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; ++ NumFPKill ; Changed = true ; } } return Changed


<s> else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) ) { SmallVector < int , <STR_LIT> > Bytes ; if ( ! getVPermMask ( Op , Bytes ) ) break ; int First ; if ( ! getShuffleInput ( Bytes , Index * BytesPerElement , BytesPerElement , First ) ) break ; if ( First < <NUM_LIT> ) return DAG . getUNDEF ( ResVT ) ; unsigned Byte = unsigned ( First ) % Bytes . size ( ) ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte = Byte


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler


<s> return __builtin_mve_uqshll_di ( value


<s> do_load_for_compare_from_addr ( load_mode , d2 , src2_addr , orig_src2 ) ; do_sub3 ( shift_amount , GEN_INT ( load_mode_size ) , cmp_rem ) ; if ( word_mode == DImode ) { emit_insn ( gen_ashldi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrdi3 ( d1 , d1 , gen_lowpart ( SImode , shift_amount ) ) ) ; emit_insn ( gen_lshrdi3 ( d2 , d2 , gen_lowpart ( SImode , shift_amount ) ) ) ; } else { emit_insn ( gen_ashlsi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrsi3 ( d1 , d1 , shift_amount ) ) ; emit_insn ( gen_lshrsi3 ( d2 , d2 , shift_amount ) ) ; } if ( TARGET_P9_MISC ) { rtx cmp = gen_rtx_COMPARE ( CCUNSmode , d1 , d2 ) ; emit_insn ( gen_rtx_SET ( dcond , cmp ) ) ; } else { if ( word_mode == DImode ) emit_insn ( gen_subfdi3_carry ( diff , d2 , d1 ) ) ; else emit_insn ( gen_subfsi3_carry ( diff , d2 ,


<s> int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , <NUM_LIT> ) ; } else for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p


<s> return TargetTriple . isOSBinFormatELF (


<s> static bool sh_rtx_costs ( rtx x , int code , int outer_code , int * total ) { switch ( code ) { case CONST_INT : if ( TARGET_SHMEDIA ) { if ( INTVAL ( x ) == <NUM_LIT> ) * total = <NUM_LIT> ; else if ( outer_code == AND && and_operand ( ( x ) , DImode ) ) * total = <NUM_LIT> ; else if ( ( outer_code == IOR || outer_code == XOR || outer_code == PLUS ) && CONST_OK_FOR_I10 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) ) ) * total = COSTS_N_INSNS ( outer_code != SET ) ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( ( outer_code != SET ) + <NUM_LIT> ) ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( x ) >> <NUM_LIT> ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( CONST_OK_FOR_I08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( ( outer_code == AND || outer_code == IOR || outer_code == XOR ) && CONST_OK_FOR_K08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_SHMEDIA64 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_SHMEDIA32 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( TARGET_SHMEDIA ) * total =


<s> IC . pushOperator ( IC_PLUS ) ; break ; case IES_INIT : assert ( ! BracCount && <STR_LIT> ) ; State = IES_LBRAC ; break ; } MemExpr = true


<s> static <ISA_LIT>Operand * CreateMem ( unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , int OffsetRegNum , bool OffsetRegShifted , enum <STR_LIT> ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback , SMLoc S , SMLoc E ) { assert ( ( OffsetRegNum == - <NUM_LIT> || OffsetIsReg ) && <STR_LIT> ) ; assert ( ( ! OffsetRegShifted || OffsetIsReg ) && <STR_LIT> ) ; assert ( ( Offset || OffsetIsReg ) && <STR_LIT> ) ; assert ( ( ! ShiftAmount || ( OffsetIsReg && OffsetRegShifted ) ) && <STR_LIT> ) ; assert ( ( ! Offset || ! OffsetIsReg ) && <STR_LIT> ) ; <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Memory ) ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; if ( OffsetIsReg ) Op -> Mem .


<s> static DecodeStatus DecodeCRRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_loadu_epi16 ( void const * __P ) { return ( __m128i ) ( * (


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_SHL || I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const static struct ShiftEntry { unsigned SizeInBits ; unsigned CReg ; unsigned OpLSHR ; unsigned OpASHR ; unsigned OpSHL ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; auto ShiftEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ DstTy ] ( const ShiftEntry & El ) { return El . SizeInBits == DstTy . getSizeInBits ( ) ; } ) ; if ( ShiftEntryIt == std :: end ( OpTable ) ) return false ; unsigned CReg = ShiftEntryIt -> CReg ; unsigned Opcode = <NUM_LIT> ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : Opcode = ShiftEntryIt -> OpSHL ; break ; case TargetOpcode :: G_ASHR : Opcode = ShiftEntryIt -> OpASHR ; break ; case TargetOpcode :: G_LSHR : Opcode = ShiftEntryIt -> OpLSHR ; break ; default : return false


<s> It . convertToMem ( State . AllocateStack ( Size , std :: max ( Align , SlotAlign ) ) ) ; State . addLoc ( It ) ; SlotAlign = <NUM_LIT> ; } PendingMembers . clear (


<s> SDLoc DL ( Op ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false


<s> return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo ::


<s> if ( auto * II = dyn_cast < InvokeInst > ( & Call ) ) { assert ( FuncInfo . InvokeStateMap . count ( II ) &&


<s> if ( INSN_P ( insn ) ) return PATTERN


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < <ISA_LIT>HazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; if ( BHR ) MHR -> AddHazardRecognizer ( std ::

unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ;


<s> poly_int64 nelt = d -> perm . length ( ) ; if ( known_ge ( d -> perm [ <NUM_LIT> ] , nelt ) ) { d -> perm . rotate_inputs ( <NUM_LIT> ) ; std :: swap ( d -> op0 , d -> op1 ) ; } if ( ( d -> vec_flags == VEC_ADVSIMD || d -> vec_flags == VEC_SVE_DATA || d -> vec_flags == VEC_SVE_PRED ) && known_gt ( nelt , <NUM_LIT> ) ) { if ( aarch64_evpc_rev_local ( d ) ) return true ; else if ( aarch64_evpc_rev_global ( d ) ) return true ; else if ( aarch64_evpc_ext ( d ) ) return true ; else if ( aarch64_evpc_dup ( d ) ) return true ; else if ( aarch64_evpc_zip ( d


<s> enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = SIMD_ARG_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = SIMD_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG ; } else args [ k ] = SIMD_ARG_COPY_TO_REG ; } args [ k ]


<s> } } bool IsIndirectCall ; if ( isCall ( Inst , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitMask ( TargetReg , IndirectBranchMaskReg , STI ) ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; PendingCall = true ; return ; } if ( PendingCall ) { <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; EmitBundleUnlock ( ) ; PendingCall = false ; return ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst ,


<s> int M = ShuffleMask [ i ] ; if ( SM_SentinelUndef == M || ! DemandedElts [ i ] ) continue ; AllUndef = false ; int Op = M / NumElts ; int Index = M % NumElts ; if ( M < <NUM_LIT> || Index != i ) { IdentityOp . clearAllBits ( ) ; break ; } IdentityOp &= APInt :: getOneBitSet ( NumOps , Op ) ; if ( IdentityOp == <NUM_LIT> ) break ; } if ( AllUndef ) return DAG . getUNDEF ( VT ) ; assert ( ( IdentityOp == <NUM_LIT> || IdentityOp . countPopulation ( ) == <NUM_LIT> ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( IdentityOp [ i ] ) return

DAG . getBitcast ( VT , ShuffleOps [ i ] ) ;


<s> DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState (


<s> break ; } TemporaryReg = Register ; } } if ( ! DoIt && ! PopReg && ! TemporaryReg ) return false ; assert ( ( PopReg || TemporaryReg ) && <STR_LIT> ) ; if ( TemporaryReg ) { assert ( ! PopReg && <STR_LIT> ) ; PopReg = PopFriendly . find_first ( ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( TemporaryReg , RegState :: Define ) . addReg ( PopReg , RegState :: Kill ) ) ; } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) ; bool Popped = false ; for ( auto MO : MBBI -> operands ( ) ) if ( MO . isReg ( ) && ( MO . isImplicit ( ) || MO . isDef ( ) ) && MO . getReg ( ) != <STR_LIT> ) { MIB . addOperand ( MO ) ; if ( ! MO . isImplicit ( ) ) Popped = true ; } if ( ! Popped ) MBB . erase ( MIB . getInstr ( ) ) ; MBB . erase ( MBBI ) ; MBBI = AddDefaultPred ( BuildMI ( MBB , MBB . end ( ) , dl , TII . get ( <STR_LIT> ) ) ) ; } assert ( PopReg && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( PopReg , RegState :: Define ) ; emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , ArgRegsSaveSize ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( PopReg , RegState :: Kill ) ) ; if ( TemporaryReg ) AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( PopReg , RegState :: Define ) . addReg ( TemporaryReg , RegState :: Kill ) ) ; return true


<s> case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) ImmedOffset |= <NUM_LIT> << NumBits ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ; } } Offset = ( isSub ) ? -


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! DAG . getTarget ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , <STR_LIT> ) , DAG . getConstant ( ArgMode , <STR_LIT> ) , DAG . getConstant ( Align , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> unsigned int i ; if ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || REGNO ( operands [ <NUM_LIT> ] ) < REGNO ( operands [ <NUM_LIT> ] ) ) { for ( i = <NUM_LIT> ; i < count ; i ++ ) { operands [ <NUM_LIT> * i ] =


<s> if ( n > <NUM_LIT> ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_DCACHEBSIZE


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ! Desc . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) { duplicatePendingSTBeforeKill ( Reg , I ) ; moveToTop ( Reg , I ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; -- StackTop ; pushReg ( getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ) ; } else { duplicateToTop ( Reg , getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) , I ) ; } MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode (


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS


<s> rtx label , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) x = gen_rtx_AND ( mode , gen_rtx_NOT ( mode , before ) , val ) ; else if ( code == AND ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , before , val ) , UNSPEC_AND ) ; else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after != NULL_RTX ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode ,


<s> static bool isAllActivePredicate ( Value * Pred ) { Value * UncastedPred ; if ( match ( Pred , m_Intrinsic < <STR_LIT> > ( m_Intrinsic < <STR_LIT> > ( m_Value ( UncastedPred ) ) ) ) ) if ( cast < ScalableVectorType > ( Pred -> getType

( ) ) -> getMinNumElements ( ) <= cast < ScalableVectorType > ( UncastedPred -> getType ( ) ) -> getMinNumElements ( ) ) Pred = UncastedPred ;


<s> rtx temp = op0 ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( mode , temp ,

GEN_INT ( INTVAL ( op1 ) & <NUM_LIT> ) ) ) ) ;


<s> static std :: string computeDataLayout ( bool is64Bit ) { std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return


<s> static bool isVShiftRImm ( SDValue Op , EVT VT , bool isNarrow , bool isIntrinsic , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getVectorElementType


<s> if ( GET_CODE ( op0 ) == PLUS && rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) ) return CCCmode ; else return CCmode ; case GTU : case LEU : return CCmode ; case GE : case LT : if ( op1 == const0_rtx ) return CCGOCmode ; else return


<s> } else if ( Subtarget . hasAVX2 ( ) ) { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } else { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } if ( NumSubs == <NUM_LIT> ) return Builder ( DAG , DL , Op0 , Op1 ) ; SmallVector < SDValue , <NUM_LIT> > Subs ; EVT InVT = Op0 . getValueType ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , InVT . getVectorNumElements ( ) / NumSubs ) ; for ( unsigned i = <NUM_LIT> ; i != NumSubs ; ++ i ) { unsigned Idx = i * SubVT . getVectorNumElements ( ) ; SDValue LHS = extractSubVector ( Op0 , Idx , DAG , DL , SubVT . getSizeInBits ( ) ) ; SDValue RHS = extractSubVector ( Op1 , Idx , DAG , DL , SubVT . getSizeInBits ( ) ) ; Subs . push_back ( Builder ( DAG , DL , LHS , RHS ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT


<s> InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs )


<s> return isNEONReplicate ( FromW , ToW / FromW , true ,


<s> if ( GenerateSignBits ( V ) ) return false ; if ( ! isa < Instruction >


<s> Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> , DL ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex (


<s> return ( __m512i ) __builtin_ia32_pbroadcastw512_mask ( ( __v8hi ) __A , ( __v32hi ) _mm512_undefined_si512 ( ) , (


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<s> unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset +

i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE2 ) return <NUM_LIT> ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) return <NUM_LIT> ; case


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; Register DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , * LdMI , * LdMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestOddReg ) ; Offset += <NUM_LIT> ; } } replaceFI ( MF , II , MI , dl , FIOperandNum ,


<s> return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT>


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const { return nullptr


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo ,