<s> default : return SDValue ( ) ; } EVT SignExtSrcVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT SrcMemVT = cast < VTSDNode > ( Src -> getOperand ( MemVTOpNum ) ) -> getVT ( ) ; if ( ( SignExtSrcVT != SrcMemVT ) || ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( DstVT , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < Src -> getNumOperands ( ) ; ++ I ) Ops . push_back ( Src -> getOperand ( I ) ) ; SDValue ExtLoad = DAG . getNode ( NewOpc , SDLoc ( N ) ,


<s> static bool isTargetShuffleVariableMask ( unsigned Opcode ) { switch ( Opcode


<s> Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo .


<s> RegDomain Domain = NoDomain ; visitRegister ( C , Reg , Domain , Worklist ) ; while ( ! Worklist . empty ( ) ) { unsigned CurReg = Worklist . pop_back_val ( ) ; if ( ! C . insertEdge ( CurReg ) ) continue ; EnclosedEdges . set ( Register :: virtReg2Index ( Reg ) ) ; MachineInstr * DefMI = MRI -> getVRegDef ( CurReg ) ; encloseInstr ( C , DefMI ) ; int OpEnd = DefMI -> getNumOperands ( ) ; const MCInstrDesc & Desc = DefMI -> getDesc ( ) ; int MemOp = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOp != - <NUM_LIT> ) MemOp += <STR_LIT> ( Desc ) ; for ( int OpIdx = <NUM_LIT> ; OpIdx < OpEnd ; ++ OpIdx ) { if ( OpIdx == MemOp ) { OpIdx += ( <STR_LIT> - <NUM_LIT> ) ; continue ; } auto & Op = DefMI


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> for ( const auto & I : Outs ) { if ( I . ArgVT == llvm :: <STR_LIT> ) OriginalArgWas<ISA_LIT>F128


<s> STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex ,


<s> if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= <NUM_LIT> || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( TYPE_MODE ( type ) == XCmode && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < <NUM_LIT> )


<s> EVT VT = Op . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; SDValue Ins128Idx = DAG . getConstant ( Upper ? NumElems / <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) ; SDValue V = Extract128BitVector ( N0 , Ins128Idx , DAG , dl ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , Upper ? DAG . getConstant ( IdxVal - NumElems / <NUM_LIT> , <STR_LIT> ) : N2 ) ; return Insert128BitVector ( N0 , V , Ins128Idx , DAG , dl ) ; } if ( Subtarget -> hasSSE41orAVX ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 (


<s> bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = llvm :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; bool NextInSameBundle = NextMII != E && NextMII -> isBundledWithPred ( ) ; if ( ReduceMI ( MBB , MI , LiveCPSR


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) { MCAsmParserExtension :: Initialize ( _Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , const <ISA_LIT>LegalizerInfo * LI ) : CombinerInfo ( false , true , LI , EnableOpt , OptSize , MinSize


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [


<s> case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : return true ; case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : case


<s> EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> Is64Bit = STI . is64Bit ( ) ; IsLP64 = STI . isTarget64BitLP64 ( ) ; Uses64BitFramePtr = STI . isTarget64BitLP64 ( ) || STI . isTargetNaCl64 ( ) ; StackPtr = TRI -> getStackRegister


<s> SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getBitcast ( MaskVT , V1Mask ) , DAG . getBitcast ( MaskVT , V2 ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1


<s> EVT FPVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( ! FPVT . isSimple ( ) ) return false ; MVT VT = FPVT . getSimpleVT ( ) ; Type * Ty = I -> getType ( ) ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Opc ; bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor


<s> case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , nullptr ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . second ) return R ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint


<s> IntID = <STR_LIT> ; break ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( ) ) { default : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_SIntMax : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_SIntMin : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_UIntMax : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_UIntMin : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_FloatMin : IntID = NoNaN ? <STR_LIT> : <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_FloatMax : IntID = NoNaN ? <STR_LIT> : <STR_LIT> ; break ; } } if ( IntID == <STR_LIT> ) return nullptr ; Constant * Pred = ConstantInt :: getTrue ( VectorType :: getBool ( VTy ) ) ; if ( VTy -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { Type * SrcTy = VectorType :: get ( Builder . getInt8Ty ( ) , VTy -> getElementCount ( ) ) ; Src = Builder . CreateZExt ( Src , SrcTy ) ; } Module * M = Builder . GetInsertBlock ( ) -> getParent ( )


<s> bool isMemMode5 ( ) const { if ( ! isMemory ( ) || Mem . OffsetIsReg || Mem . OffsetRegShifted || Mem . Writeback || Mem . Negative ) return false ; if ( ! Mem . Offset ) return true ; const MCConstantExpr * CE = dyn_cast <


<s> if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( Rt == Rt2 ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder


<s> std :: unique_ptr < DCBasicBlock > <ISA_LIT>DCTranslator :: createDCBasicBlock ( DCFunction & DCF , const MCBasicBlock &


<s> auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { MachineOperand & op = MI . getOperand ( <NUM_LIT> ) ; if ( op . isMBB ( ) ) { MachineBasicBlock * dst = op . getMBB ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addMBB ( dst ) ; } else { int64_t dst = op . getImm ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( dst ) ; } break ; } case <STR_LIT> : { MachineOperand & op = MI .


<s> if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } else data -> int_regs


<s> assert ( MovePCtoLROffset && <STR_LIT> ) ; Cst = - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ; } if ( MO . isGlobal ( ) ) return MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , RelocID , const_cast < GlobalValue * > ( MO . getGlobal ( ) ) , Cst , isa < Function > ( MO . getGlobal ( ) ) ) ; if ( MO . isSymbol ( ) ) return MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , RelocID , MO . getSymbolName ( ) , Cst ) ; if ( MO . isCPI ( ) ) return MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , RelocID , MO . getIndex ( ) , Cst ) ; if ( MO . isMBB ( ) ) return MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , RelocID , MO . getMBB ( ) ) ; assert ( MO . isJTI ( ) ) ; return MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , RelocID


<s> return ! arm_no_early_store_addr_dep ( producer ,


<s> rtx mips_pic_base_register ( rtx temp ) { if ( ! TARGET_MIPS16 ) return pic_offset_table_rtx ; if ( currently_expanding_to_rtl ) return mips16_gp_pseudo_reg ( ) ; if ( can_create_pseudo_p ( ) ) temp =


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode ::

COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ;


<s> static DecodeStatus DecodePCRelLabel19 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { int64_t ImmVal = Imm ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; return


<s> llvm_unreachable ( <STR_LIT> ) ; return false


<s> if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) .

addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;


<s> const Function & F = MF . getFunction ( ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; <ISA_LIT>O0PreLegalizerCombinerInfo PCInfo ( false , F . hasOptSize ( ) , F . hasMinSize (


<s> fixIMPLICITDEF ( MF ) ; fixNoReturn ( MF ) ; return true


<s> ScheduleHazardRecognizer :: HazardType <ISA_LIT>HazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( LastMI && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) { MachineInstr * DefMI = LastMI ; const MCInstrDesc & LastMCID = LastMI -> getDesc (


<s> const <ISA_LIT>BaseInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * BB = MI -> getParent ( ) ; MachineInstrBuilder LDM , STM ; if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps (


<s> pops_needed = <NUM_LIT> ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop |= <NUM_LIT> << LR_REGNUM ; ++ pops_needed ; } if ( TARGET_BACKTRACE ) { regs_to_pop |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << SP_REGNUM ) ; pops_needed += <NUM_LIT> ; } if ( pops_needed == <NUM_LIT> ) { if ( crtl -> calls_eh_return ) asm_fprintf ( f , <STR_LIT> , SP_REGNUM , ARM_EH_STACKADJ_REGNUM ) ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) { asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; } else asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; return ; } else if ( ! TARGET_INTERWORK && ! TARGET_BACKTRACE && ! is_called_in_ARM_mode ( current_function_decl ) && ! crtl -> calls_eh_return && ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) { asm_fprintf ( f , <STR_LIT> , PC_REGNUM ) ; return ; } regs_available_for_popping = <NUM_LIT> ; if ( crtl -> calls_eh_return ) size = <NUM_LIT> ; else { if ( crtl -> return_rtx != <NUM_LIT> ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; size = GET_MODE_SIZE ( mode ) ; if ( size == <NUM_LIT> ) { if ( mode == VOIDmode ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> &&


<s> bool isImmZero ( ) const { return Kind == Immediate && getImm (


<s> SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A2 ) ; SDValue TmpAns = b . OR ( b . AND ( A1 , Tmp ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; bool IsN64 = Subtarget . isABI_N64 ( ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ? (


<s> switch ( mode ) { case E_CCFmode : case E_SFmode : return TARGET_HARD_FLOAT ; case E_DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case E_V2SFmode


<s> if ( ! IN_RANGE ( index , <NUM_LIT> , <NUM_LIT> ) ) return NULL ; struct loongarch_address_info info ; if ( ( loongarch_classify_address ( & info , x , mode , false ) && ! ( info . type == ADDRESS_REG_REG ) ) || ! loongarch_legitimate_address_p ( mode , x , false ) ) return NULL ; const char * const insn [ ] [


<s> bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false


<s> MachineInstr * <ISA_LIT>LoadStoreOpt :: CreateLoadStoreDouble ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , int Offset , unsigned Base , bool BaseKill , unsigned Opcode , <STR_LIT> Pred , unsigned PredReg , const DebugLoc & DL , ArrayRef < std :: pair < unsigned , bool >> Regs ) const { bool IsLoad = isi32Load ( Opcode ) ; assert ( ( IsLoad || isi32Store ( Opcode ) ) && <STR_LIT> ) ; unsigned LoadStoreOpcode = IsLoad ? <STR_LIT> : <STR_LIT> ; assert ( Regs . size ( ) == <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , InsertBefore , DL , TII -> get ( LoadStoreOpcode ) ) ; if ( IsLoad ) { MIB . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) ; } else { MIB . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( Regs [ <NUM_LIT>

] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) ;


<s> if ( isSpecialLLVMGlobalArrayForStaticInit ( GV ) ) return ; MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GV -> isDeclarationForLinker ( ) ) { emitLinkage ( GV , GVSym ) ; return ; } SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment (


<s> if ( IsWinEH ) { assert ( ! MFI -> hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI -> hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment (


<s> return ( float32x2_t ) __builtin_neon_vrintpv2sf (


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / <NUM_LIT> - <NUM_LIT> ) ; unsigned which = ( ( d -> perm [ i ] ^ i ) & ( nelt / <NUM_LIT> ) ) * eltsz ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ ! ! which ] [ ( i * eltsz + j ) ^ which ] = GEN_INT ( e * eltsz + j ) ; rperm [ ! which ] [ ( i * eltsz + j ) ^ ( which ^ <NUM_LIT> ) ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( h , op , vperm ) ) ; hp = gen_reg_rtx ( V4DImode ) ; op = gen_lowpart ( V4DImode , h


<s> Reduction ( PHINode * P , Instruction * Acc ) :


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; SMLoc S , E ; switch ( getLexer ( ) . getKind ( ) ) { default : { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( parseSymbolicImmVal ( Expr ) ) return Error ( S , <STR_LIT> ) ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: LBrac : { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return parseOperand ( Operands , false , false ) ; } case AsmToken :: LCurly : { if ( ! parseNeonVectorList ( Operands ) ) return false ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return parseOperand ( Operands , false , false ) ; } case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; if ( ! parseOptionalMulOperand ( Operands ) ) return false ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) return parseKeywordOperand ( Operands ) ; OperandMatchResultTy GotShift = tryParseOptionalShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; if ( Mnemonic == <STR_LIT> ) return parseKeywordOperand ( Operands ) ; const MCExpr * IdVal ; S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Integer : case AsmToken


<s> if ( DECL_VIRTUAL_P ( decl ) || DECL_VINDEX ( decl ) ) sorry ( <STR_LIT> ) ; version_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( version_attr != NULL_TREE ) ; orig_name = IDENTIFIER_POINTER ( id ) ; version_string = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( version_attr ) ) ) ; if ( strcmp ( version_string , <STR_LIT> ) == <NUM_LIT> ) return id ; attr_str = sorted_attr_string ( TREE_VALUE ( version_attr ) ) ; assembler_name = XNEWVEC ( char , strlen ( orig_name ) + strlen ( attr_str ) + <NUM_LIT> ) ; sprintf ( assembler_name , <STR_LIT> , orig_name , attr_str ) ; if ( DECL_ASSEMBLER_NAME_SET_P ( decl ) )


<s> unsigned RawVal = MI -> getOperand ( OpNo ) . getImm ( ) ; uint64_t Val = <STR_LIT> (


<s> case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return legalizeSVEGatherPrefetchOffsVec ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLDNF1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLDNF1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performSTNT1Combine ( N , DAG ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT>


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) != - <NUM_LIT> ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else


<s> int getIntImmCost ( <STR_LIT> IID , unsigned Idx , const APInt &


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI ,


<s> Parser . Lex ( ) ; } if ( <ISA_LIT>Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( <ISA_LIT>Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } if ( ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) && isa < MCConstantExpr > ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getImm ( ) ) && cast

< MCConstantExpr > ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getImm ( ) ) -> getValue ( ) == <NUM_LIT> ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override


<s> if ( shift_amount_i == <NUM_LIT> ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & ASHL_CLOBBERS_T )


<s> return ( ( ( TARGET_ALIGN_DOUBLE || ( TARGET_FPU_DOUBLE && ( mode == DFmode || mode == DCmode ) && cum . arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( mode ) ) ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_WORD ) ? ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] + (

cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] & <NUM_LIT> ) ) : cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT>


<s> else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , NULL


<s> psrah_u ( uint16x4_t s , uint8_t amount ) { return __builtin_loongson_psrah_u ( s


<s> return ! getReservedRegs ( MF ) . test


<s> if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) return Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; getTargetStreamer ( ) . emitObjectArch ( ID ) ; return


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock


<s> if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask << <NUM_LIT> ; return SYSmvalue


<s> Value * <ISA_LIT>IREmitter :: visitBEXTR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> return ( __m128i ) __builtin_ia32_paddusw128 ( ( __v8hi


<s> while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; if ( NumBytes ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) TII -> copyPhysReg ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , false ) ; if ( needsFrameMoves ) { const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; const int StackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) { unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> * StackGrowth ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION


<s> MachineOperand & Count = LoLoop . getLoopStartOperand ( ) ; MachineInstr * NewStart ; if ( Opc == <STR_LIT> && Count . isReg ( ) && Count . getReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; NewStart = nullptr ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , Start -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count ) ; if ( ! isDo ( Start ) ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; NewStart = & * MIB ; } LoLoop . ToRemove .


<s> const struct loongarch_isa * isa2 = & isa_required ( abi ) ; compatible = compatible && isa_base_compat_p ( isa , isa2


<s> uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) - <NUM_LIT> ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp


<s> return ( __m128i ) __builtin_ia32_pminuw128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_di ( ) , (


<s> return ( __m128i ) __builtin_ia32_pmovqw128_mask ( ( __v2di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , (


<s> if ( Operands . size ( ) < <NUM_LIT> ) return false ; else if ( Operands [ <NUM_LIT> ] -> isToken ( ) && Operands [ <NUM_LIT> ] -> isReg ( ) && Operands [ <NUM_LIT> ] -> isImm ( ) && Operands [ <NUM_LIT> ] -> isImm ( ) && Operands [ <NUM_LIT> ] -> isReg ( ) ) Offset = <NUM_LIT> ; else if ( Operands [ <NUM_LIT> ] -> isToken ( ) && Operands [ <NUM_LIT> ] -> isToken ( ) && Operands [ <NUM_LIT> ] -> isReg ( ) && Operands [ <NUM_LIT> ] -> isImm ( ) && Operands [ <NUM_LIT> ] -> isImm ( ) && Operands [ <NUM_LIT> ] -> isReg ( ) ) Offset = <NUM_LIT> ; else return false ; int PossibleAluOpIdx = Offset + <NUM_LIT> ; int PossibleBaseIdx = Offset


<s> node = copy_node ( node ) ; TYPE_MAIN_VARIANT ( node


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; const bool IsCalleeGlobalPIC = Callee . isGlobal ( ) && TM . isPositionIndependent ( ) ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) || IsCalleeGlobalPIC ? <STR_LIT> : <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; if ( IsCalleeGlobalPIC ) { Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Callee . getGlobal ( ) ) ; if ( ! Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo (


<s> MachineBasicBlock :: iterator NI = doMergeWithPrevious ? <NUM_LIT> : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI


<s> bool <ISA_LIT>InstrInfo :: isADDInstrEligibleForFolding ( MachineInstr


<s> for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = *


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef


<s> MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = FFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) && ! needsFP ( MF ) ) { return ; } unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasCRSaveArea = false ; bool HasVRSAVESaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> -> contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) || <STR_LIT> -> contains ( Reg ) ) { } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i


<s> if ( RHS . Disp == PtrInfo :: getEmptyKey ( ) ) return LHS . Disp == PtrInfo ::


<s> const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> getPointerAlignment ( DL ) == <NUM_LIT> && ! GV -> getValueType ( ) -> isFunctionTy ( ) ) return false ; if ( CM == CodeModel :: Small ) return TLInfo . getTargetMachine ( ) .

shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef (


<s> int fma_forest :: get_target_parity ( ) { return this ->


<s> uint8_t <ISA_LIT>MCCodeEmitter :: DetermineREXPrefix ( const MCInst & MI , uint64_t TSFlags , int MemOperand , const MCInstrDesc & Desc ) const { uint8_t REX = <NUM_LIT> ; bool UsesHighByteReg = false ; if ( TSFlags & <STR_LIT> ) REX |= <NUM_LIT> << <NUM_LIT> ; if ( MI . getNumOperands ( ) == <NUM_LIT> ) return REX ; unsigned NumOps = MI . getNumOperands ( ) ; unsigned CurOp = <STR_LIT> ( Desc ) ; for ( unsigned i = CurOp ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) UsesHighByteReg = true ; if ( ! <STR_LIT> ( Reg ) ) continue ; REX |= <NUM_LIT> ; break ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : { REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; } case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= is<ISA_LIT>_64ExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= is<ISA_LIT>_64ExtendedReg ( MI ,


<s> <ISA_LIT>DCTranslator :: <ISA_LIT>DCTranslator ( LLVMContext & Ctx , const DataLayout & DL , unsigned OptLevel , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCInstPrinter & MIP ) : DCTranslator ( Ctx , DL , OptLevel , MII , MRI , STI

, MIP , build<ISA_LIT>RegSetDesc ( Ctx , MRI ) ) {


<s> static bool ix86_valid_mask_cmp_mode ( machine_mode mode ) { if ( TARGET_XOP && ! TARGET_AVX512F ) return false ; if ( TARGET_AVX512FP16 && mode == HFmode


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs , Mask ) ; return


<s> unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler ::


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return new ELF<ISA_LIT>AsmBackend ( T , Triple ( TT )


<s> return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal . getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ; CC = <STR_LIT> ; } return LowerSELECT_CC ( CC , LHS , RHS , TVal ,


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> getDarwinVers ( )

> <NUM_LIT> ) return PrivateGlobalPrefix ;


<s> static DecodeStatus DecodeSystemPStateInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { uint64_t op1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; bool


<s> bool noCost ( ) const { return ( GroupingCost <= <NUM_LIT> && ! ResourcesCost


<s> ++ FixedParamNum ; return ; } ++ FloatingPointParamNum ; for ( int I = <NUM_LIT> ; I < static_cast < int > ( FloatingPointParamNum + FixedParamNum - <NUM_LIT> ) ; ++ I ) { if ( CopyParamType & XCOFF :: TracebackTable :: ParmTypeIsFloatingBit ) { CopyParamType <<= <NUM_LIT>


<s> PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO


<s> void <ISA_LIT>BankConflictHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr & MI = * SU -> getInstr ( ) ; if ( ! MI . mayLoad ( ) || MI . mayStore ( ) || MI . getNumMemOperands ( ) != <NUM_LIT> ) return ; auto MO = * MI . memoperands ( ) . begin ( ) ; uint64_t Size1 = MO -> getSize ( ) ; if ( Size1 > <NUM_LIT> )


<s> if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; ActiveLaneMask = dyn_cast < IntrinsicInst > ( Predicate ) ; if ( ! ActiveLaneMask || ActiveLaneMask -> getIntrinsicID ( ) != <STR_LIT> ) continue ; Predicates . insert ( Predicate ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ActiveLaneMask << <STR_LIT> ) ; VecTy = getVectorType ( I ) ; if ( ! IsSafeActiveMask ( TripCount , VecTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; InsertVCTPIntrinsic ( ActiveLaneMask , TripCount


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo


<s> MCInstrInfo * llvm :: create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_lfence ( void ) { __builtin_ia32_lfence (


<s> for ( Target * T : { & The<ISA_LIT>leTarget , & The<ISA_LIT>beTarget , & TheARM64Target } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: registerMCAdjustCodeGenOpts ( * T , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer


<s> unsigned ATReg = <STR_LIT> ; unsigned DReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FirstShift = <STR_LIT> ; unsigned SecondShift = <STR_LIT> ; if ( has<ISA_LIT>32r2 ( ) ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) { uint64_t MaxShift = <NUM_LIT> ; uint64_t ShiftValue = ImmValue ; if ( ImmValue != <NUM_LIT> ) ShiftValue = MaxShift - ImmValue ; TOut . emitRRI ( <STR_LIT> , DReg , SReg , ShiftValue , Inst . getLoc ( ) , STI ) ; return false ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , ImmValue , Inst . getLoc ( ) , STI ) ; return false ; } return


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineBasicBlock * ContBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( ++ MBB -> getIterator ( ) , ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( ContBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; MF -> push_back ( TrapBB ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TrapBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( )


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm ) { if ( ! isUInt < N > ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; Traces = & getAnalysis <


<s> gcc_assert ( REG_P ( op ) ) ; if ( ! strict || REGNO ( op ) < FIRST_PSEUDO_REGISTER || ! reg_renumber || reg_renumber [ REGNO ( op ) ] < <NUM_LIT> ) return REGNO ( op ) ; return reg_renumber [ REGNO (


<s> SDLoc DL ( Op ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElt = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > TBLMask ; for ( int Val : ShuffleMask ) { for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; TBLMask . push_back ( DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; } } MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( V2 . getNode ( ) -> isUndef


<s> switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ECX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ECX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RegNo - <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> void <ISA_LIT>ELFStreamer :: emitHandlerData ( ) { FlushUnwindOpcodes ( false )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo ) const { const MCOperand & RegMO = MI . getOperand ( OpNo ) . isReg ( ) ? MI . getOperand ( OpNo ) : MI . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand & OffsetMO = MI . getOperand ( OpNo ) . isImm ( ) ? MI . getOperand ( OpNo ) : MI . getOperand ( OpNo


<s> MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState


<s> bool hasFloat128 ( ) const { return HasFloat128


<s> vec = gen_rtx_EXPR_LIST ( VOIDmode , lab , vec ) ; if ( diff ) sparc_addr_diff_list = gen_rtx_EXPR_LIST ( VOIDmode , vec , sparc_addr_diff_list


<s> ASSERT_RTL_DUMP_EQ ( <STR_LIT> , gen_raw_REG ( SImode ,


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; EmitLabel ( Symbol , Loc , F ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF :: STB_LOCAL ) ; Symbol -> setExternal ( false ) ; Symbol -> setOffset (


<s> if ( recog_memoized ( insn ) >= <NUM_LIT> && get_attr_slot ( insn ) == slot && get_attr_length ( insn ) == length ) return insn ; } return


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind


<s> return ( __m128i ) __builtin_ia32_pmovsdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_setzero_si128 ( )


<s> if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef


<s> return ( uint16x4_t ) __builtin_neon_vmla_lanev4hi ( ( int16x4_t ) __a , (


<s> return ( long long ) __builtin_ia32_vcvttsd2si64 ( ( __v2df


<s> } if ( SetCCOpcode == <STR_LIT> && RHSC -> isNullValue ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isOne ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : std :: swap ( LHS , RHS ) ; break ; } switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> static DecodeStatus DecodeMem ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Reg = ( int ) fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int Offset = SignExtend32 < <NUM_LIT> > ( ( Insn & <NUM_LIT> ) >> <NUM_LIT> ) ; int Base = ( int ) fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [


<s> unsigned <ISA_LIT>SEDAGToDAGISel :: getMSACtrlReg ( const SDValue RegIdx ) const { switch ( cast < ConstantSDNode > ( RegIdx ) -> getZExtValue (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , false ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CM , OL ) , isLittle ( false ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , false , * this ) { initAsmInfo ( )


<s> void setFeatures ( const FeatureBitset & Features_ ) { Features = Features_


<s> inline vector unsigned char vec_vsububm ( vector unsigned


<s> if ( TARGET_64BIT ) return gen_adddi3 ( rt , ra , GEN_INT (


<s> tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ( Value & ( <NUM_LIT> << Shift ) ) >> Shift ) ) ) ; tmpInst . setLoc


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> detectRoundChange ( ) ) { addPass ( new DetectRoundChange


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( CE


<s> bool isCheapToSpeculateCttz ( ) const override { return


<s> return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB


<s> if ( <STR_LIT> <= RegNo && RegNo <= <STR_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> <= RegNo && RegNo <= <STR_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> <= RegNo && RegNo <= <STR_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> <= RegNo && RegNo <= <STR_LIT> ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> unsigned i ; rtx x ; x = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( MAX_VECT_LEN ) ) ; for ( i = <NUM_LIT> ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , <NUM_LIT> , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) ,


== X86_64_INTEGERSI_CLASS ) return X86_64_INTEGER_CLASS ;


<s> const Type * Int32Ty = Type :: getInt32Ty ( M . getContext ( ) ) ; for ( size_t i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ) { size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < const Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; MergedSize < MaxOffset && j != e ; ++ j ) { const Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { SmallVector < Constant * , <NUM_LIT> > Idx ; Idx . push_back ( ConstantInt :: get ( Int32Ty , <NUM_LIT> )


<s> case MachineOperand :: MO_Immediate : MO . setImm ( MO . getImm ( ) + <NUM_LIT> ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ConstantPoolIndex


<s> SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load


<s> if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= <NUM_LIT> ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( store_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == store_insn ) { rtx note = find_reg_note ( store_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete (


<s> SDValue Const1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Const31 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Res ; SDValue X = ( TyX == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasExtractInsert ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , Const31 , Const1 ,


<s> MachineBasicBlock * BB = MF . begin ( ) ; if ( Fn . hasExternalLinkage ( ) && Fn . getName ( ) == <STR_LIT> )

EmitSpecialCodeForMain ( BB , MF . getFrameInfo ( ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( RealignStack && ( ! MFI -> hasVarSizedObjects


<s> __rv . __o = __builtin_neon_vld3v8hi ( ( const __builtin_neon_hi * ) __a ) ; return __rv .


<s> return ( uint16_t ) __builtin_neon_vget_laneuv4hi ( ( int16x4_t


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( F . getParent (


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { const MachineRegisterInfo & MRI = MI . getParent ( )


<s> static __inline qword si_ceqb ( qword


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success


<s> return new <ISA_LIT>64Disassembler ( STI ,


<s> return ( ByteA == <NUM_LIT> || ByteA == <NUM_LIT> ) && ( ByteB == <NUM_LIT> || ByteB == <NUM_LIT> ) && ( ByteC == <NUM_LIT> || ByteC == <NUM_LIT> ) && ( ByteD == <NUM_LIT> || ByteD == <NUM_LIT> ) && ( ByteE == <NUM_LIT> || ByteE ==

<NUM_LIT> ) && ( ByteF == <NUM_LIT> || ByteF == <NUM_LIT> ) && ( ByteG == <NUM_LIT> || ByteG == <NUM_LIT> ) && ( ByteH == <NUM_LIT> || ByteH == <NUM_LIT> ) ;


<s> if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , Idx . getValueType ( ) , StackPtr , OffsetVal ) ; SDValue LoadScalar = DAG . getLoad ( Extract -> getValueType ( <NUM_LIT> ) , dl , Ch , ScalarAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Extract , <NUM_LIT> )


<s> if ( Idx == SM_SentinelZero ) return EltVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , EltVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , EltVT ) ; if ( Idx == SM_SentinelUndef ) return DAG . getUNDEF ( EltVT ) ; if ( llvm :: any_of ( ShuffleMask , [ ] ( int M ) { return M == SM_SentinelZero ; } ) ) return SDValue ( ) ; assert ( <NUM_LIT> <= Idx && Idx < ( int ) ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; unsigned AllowedUses = ( ShuffleOps . size ( ) > <NUM_LIT> && ShuffleOps [ <NUM_LIT> ] == ShuffleOps [ <NUM_LIT> ] ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue


<s> return emitAtomicBinary ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB


<s> assert ( isInt < <NUM_LIT> > ( Offset ) && ( Offset >= <NUM_LIT> ) && <STR_LIT> ) ; MCOperand SPReg = MCOperand :: CreateReg ( <STR_LIT> ) , BaseReg = SPReg ; MCOperand GPReg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand ZEROReg = MCOperand :: CreateReg ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { unsigned Hi = ( ( Offset + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; Offset &= <NUM_LIT> ; MCOperand ATReg = MCOperand :: CreateReg (


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) )


<s> MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedSignBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL ,


<s> static tree arm_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( ! get<ISA_LIT>Subtarget ( ) . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true


<s> bool useSoftMulDiv ( ) const { return UseSoftMulDiv


<s> if ( TARGET_SVE && known_eq ( nbytes , BYTES_PER_SVE_VECTOR ) ) { unsigned int elem_nbytes = vector_element_size ( nbytes , nunits ) ; machine_mode pred_mode ; if ( aarch64_sve_pred_mode ( elem_nbytes ) . exists ( & pred_mode ) ) return


<s> rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( <NUM_LIT> , ptrue , op ) , UNSPEC_MERGE_PTRUE ) ; rtx_insn * insn = emit_set_insn ( target , unspec ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( op


<s> void <ISA_LIT>InstPrinter :: printMulImm4 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT>


<s> LLVM_FALLTHROUGH ; } case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; }


<s> } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols


<s> const char * p ; if ( is64Bit ( ) ) p = <STR_LIT> ; else if ( isTargetDarwin ( ) ) p = <STR_LIT> ; else if ( isTargetMingw ( ) || isTargetWindows


<s> if ( ! hasSymbolicDisplacement ) return true ; if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ; if ( M == CodeModel :: Small && Offset < <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ) return true ; if ( M == CodeModel :: Kernel && Offset >


<s> uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Name = Parser . getTok ( ) . getString ( ) ; SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> + Name ) ; for ( const auto & Extension : Extensions ) { if ( Extension . Kind != FeatureKind ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc , <STR_LIT> + Name ) ; if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) return Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ STI . getFeatureBits ( ) & Extension . Features ) : ( STI . getFeatureBits ( ) & Extension . Features ) ; uint64_t Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; return false ; } return Error ( ExtLoc , <STR_LIT> + Name


<s> if ( isa < MemSDNode > ( Chain . getNode ( ) ) && cast < MemSDNode > ( Chain . getNode ( ) ) -> writeMem ( ) ) return false ; if ( Chain . getOperand ( <NUM_LIT> ) . getNode ( ) == Callee . getNode ( ) ) return true ; if ( Chain . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Callee . getValue ( <NUM_LIT> ) . isOperandOf ( Chain . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Callee . getValue ( <NUM_LIT>


<s> if ( MemVT . isVector ( ) && ! isMaskType ( MemVT ) ) return lowerToVVP ( Op , DAG ) ; SDValue BasePtr = LdNode -> getBasePtr ( ) ; if ( isa < FrameIndexSDNode > ( BasePtr . getNode ( ) ) ) { return Op ; } if ( MemVT == <STR_LIT> ) return lowerLoadF128 ( Op , DAG ) ; return Op


<s> if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_RegMask ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask


<s> inline static bool isPostOp ( unsigned AluOp


<s> break ; case k_Token : Tok = o . Tok ; break ; case k_CCOut : case k_Register : Reg = o . Reg ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : Registers = o . Registers ; break ; case k_VectorList : case k_VectorListAllLanes : case k_VectorListIndexed : VectorList = o . VectorList ; break ; case k_CoprocNum : case k_CoprocReg : Cop = o . Cop ; break ; case k_CoprocOption : CoprocOption = o . CoprocOption ; break ; case k_Immediate : Imm = o . Imm ; break ; case k_MemBarrierOpt : MBOpt = o . MBOpt ; break ; case k_InstSyncBarrierOpt : ISBOpt = o . ISBOpt ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask


<s> reportParseError ( <STR_LIT> ) ; return false ; } const MCExpr * StackOffset ; int64_t StackOffsetVal ; if ( Parser . parseExpression ( StackOffset ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! StackOffset -> evaluateAsAbsolute ( StackOffsetVal , getStreamer ( ) ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( StackOffsetVal < <NUM_LIT> ) { Warning ( Loc , <STR_LIT> ) ; IsCpRestoreSet = false ; } else { IsCpRestoreSet = true ; CpRestoreOffset = StackOffsetVal ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! getTargetStreamer ( ) . emitDirectiveCpRestore ( CpRestoreOffset , [ & ] ( ) { return getATReg ( Loc ) ; } , Loc , STI ) ) return true ; Parser . Lex ( ) ; return


<s> return ( ( int ) SubMode << <NUM_LIT> ) | ( ( int ) WB <<


<s> } f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ; f_ovf = DECL_CHAIN ( f_res ) ; f_sav = DECL_CHAIN ( f_ovf ) ; valist = build_simple_mem_ref ( valist ) ; gpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , unshare_expr ( valist ) , f_fpr , NULL_TREE ) ; ovf = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , unshare_expr ( valist ) , f_ovf , NULL_TREE ) ; sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = MIN ( crtl -> args . info . sysv_gregno - GP_ARG_MIN_REG , GP_ARG_NUM_REG ) ; n_fpr = MIN ( crtl -> args . info . fregno - FP_ARG_MIN_REG , FP_ARG_NUM_REG ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT>


<s> bool isBDAddr32Disp12 ( ) const { return isMemDisp12 ( BDMem


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx


<s> factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / <NUM_LIT> ; if ( factor == <NUM_LIT> ) factor = <NUM_LIT> ; if ( TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT ) * total = factor * factor * COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = factor * factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case DIV : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case UDIV : case MOD : case UMOD : factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / <NUM_LIT> ; if ( factor == <NUM_LIT> ) factor = <NUM_LIT> ; * total = factor * factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x )


<s> SDLoc DL ( Node ) ; const GlobalValue * GV = Node -> getGlobal ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RM = DAG . getTarget ( ) . getRelocationModel ( ) ; CodeModel :: Model CM = DAG . getTarget ( ) . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset =


<s> bool lastInITBlock ( ) { return ITState . CurPosition == <NUM_LIT> - countTrailingZeros (


<s> assert ( MI . getOpcode ( ) == <STR_LIT> ) ; return cast < Function > ( MI . getOperand ( <NUM_LIT> ) .


<s> if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && CountPopulation_64 ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Align , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ; if ( CByte && CByte -> getZExtValue ( ) == <NUM_LIT> ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , Dst , Dst , Bytes ) ; Chain = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; SDValue DstPlus1 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , DstPlus1 , Dst , Bytes - <NUM_LIT> ) ; } return SDValue (


<s> return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG


<s> } const bool ShouldUseMOV16PIC = FlagSfiDisableCP && IsRelocPIC && ( MO . isCPI ( ) || MO . isJTI ( ) || MO . isGlobal ( ) ) ; if ( ShouldUseMOV16PIC ) { if ( isThumb2 ) llvm_unreachable ( <STR_LIT> ) ; LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags


<s> unsigned Bits = V . getValueSizeInBits ( ) ; if ( DAG . MaskedValueIsZero ( VOp0 , APInt :: getHighBitsSet ( InBits , InBits

- Bits ) ) ) return V . getOperand ( <NUM_LIT> ) ;


<s> assert ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) && <STR_LIT> ) ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & BaseRegTok = Parser . getTok ( ) ; if ( BaseRegTok . isNot ( AsmToken :: Identifier ) ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } int BaseRegNum = TryParseRegister ( ) ; if ( BaseRegNum == - <NUM_LIT> ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Comma ) && ! Tok . is ( AsmToken :: RBrac ) ) return true ; bool Preindexed = false ; bool Postindexed = false ; bool OffsetIsReg = false ; bool Negative = false ; bool Writeback = false ; <ISA_LIT>Operand * WBOp = <NUM_LIT> ; int OffsetRegNum = - <NUM_LIT> ; bool OffsetRegShifted = false ; enum <STR_LIT> ShiftType = <STR_LIT> ; const MCExpr * ShiftAmount = <NUM_LIT> ; const MCExpr * Offset = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Comma ) ) { Preindexed = true ; Parser . Lex ( ) ; if ( ParseMemoryOffsetReg ( Negative , OffsetRegShifted , ShiftType , ShiftAmount , Offset , OffsetIsReg , OffsetRegNum , E ) ) return true ; const AsmToken & RBracTok = Parser . getTok ( ) ; if ( RBracTok . isNot ( AsmToken :: RBrac ) ) { Error ( RBracTok . getLoc ( ) , <STR_LIT> ) ; return true ; } E = RBracTok . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { WBOp = <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ; Writeback =


<s> if ( insn . spec -> operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . spec -> operands [ index ] , insn ) ) { return true


<s> if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr


<s> InstClassification Classification ; DenseSet < unsigned int > UsedRegs ; while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp & ( SlotSize - <NUM_LIT> ) ) return ; StackDisp >>= Log2SlotSize ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp ] != nullptr ) return ; Context . MovVector [ StackDisp ] = & * I ; for ( const MachineOperand & MO : I -> uses ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( RegInfo . isPhysicalRegister ( Reg ) ) UsedRegs . insert ( Reg ) ; } ++ I ; } if ( I == MBB . end ( ) || ! I -> isCall ( ) ) return ; Context . Call = & * I ; if ( ( ++ I ) -> getOpcode ( ) != FrameDestroyOpcode ) return ; auto MMI = Context . MovVector . begin ( ) , MME = Context . MovVector . end ( ) ; for ( ; MMI != MME ; ++ MMI , Context . ExpectedDist += SlotSize ) if ( * MMI == nullptr ) break ; if ( MMI == Context . MovVector . begin ( ) ) return ; for ( ; MMI != MME ; ++ MMI ) if


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT