<s> targetm . sched . first_cycle_multipass_issue = core2i7_first_cycle_multipass_issue ; targetm . sched . first_cycle_multipass_backtrack = core2i7_first_cycle_multipass_backtrack ; targetm . sched . first_cycle_multipass_end = core2i7_first_cycle_multipass_end ; targetm . sched . first_cycle_multipass_fini = core2i7_first_cycle_multipass_fini ; core2i7_secondary_decoder_max_insn_size = <NUM_LIT> ; core2i7_ifetch_block_size =


<s> SDLoc dl ( Op ) ; assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind )


<s> case <STR_LIT> : return Mask ; case <STR_LIT> : Mask . resize ( <NUM_LIT> ) ; return Mask ; case <STR_LIT> : Mask . erase ( Mask . begin ( ) , Mask . begin ( ) + <NUM_LIT> ) ; for ( int & M : Mask ) M -=


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>MachObjectWriter ( false , cantFail ( MachO :: getCPUType ( TT )


<s> SDValue AVL = getNodeAVL ( Op ) ; if ( ! AVL ) return { SDValue ( ) , true } ; if ( isLegalAVL ( AVL ) ) return {

AVL -> getOperand ( <NUM_LIT> ) , true } ;


<s> tp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TP ) ; if ( ! to_reg )


<s> unsigned E = MI -> isCall ( ) || MI -> isReturn ( ) ? MCID . getNumOperands ( ) : MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) RegDefs . insert ( Reg ) ; else if ( MO . isUse ( ) ) RegUses


<s> std :: unique_ptr < MCObjectTargetWriter >

createObjectTargetWriter ( ) const override {


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : case MachineOperand ::


<s> return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : if ( is64Bit ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MICROMIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MICROMIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF


<s> if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode ) ; else { char buf [ <NUM_LIT> ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno =


<s> return isMem128 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT>


<s> MVT DstVT , SrcVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY_TO_REGCLASS ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = TmpReg ; } unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = <ISA_LIT>SubTarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( I , DstVT , DestReg , IsSigned ) ; if ( IntReg == <NUM_LIT> ) return false ; UpdateValueMap ( I ,


<s> unsigned FrameReg = RegInfo -> getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO .


<s> if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( * TM . getDataLayout ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None


<s> if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } { bool wasInITBlock = inITBlock ( ) ; while ( processInstruction ( Inst , Operands , Out ) ) ; if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out ) ; } else


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC =


<s> unsigned <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , Align Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind ) { if ( ST -> hasMVEIntegerOps ( ) ) { if ( Opcode == Instruction :: Load && isLegalMaskedLoad ( Src , Alignment ) ) return ST -> getMVEVectorCostFactor ( ) ; if ( Opcode == Instruction :: Store && isLegalMaskedStore ( Src , Alignment ) ) return ST -> getMVEVectorCostFactor ( ) ; } if ( ! isa < FixedVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; return cast < FixedVectorType > ( Src ) -> getNumElements (


<s> if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements || ! L -> isLoopInvariant ( BECount ) ) return false ; return


<s> Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET )

, false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << JTI << '_' << MO2 . getImm ( ) << <STR_LIT> ; const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset = false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ;


<s> else return false ; const TargetRegisterClass * RC = nullptr ; switch ( RetVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg )


<s> unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF


<s> SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = getTargetVShiftUniformOpcode ( Opcode , false ) ; int BaseShAmtIdx = - <NUM_LIT> ; if ( SDValue BaseShAmt = DAG . getSplatSourceVector ( Amt , BaseShAmtIdx ) ) { if ( supportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , BaseShAmtIdx , Subtarget , DAG ) ; if ( ( ( VT == <STR_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) || ( VT == <STR_LIT> && ! Subtarget . canExtendTo512BW ( ) ) || VT == <STR_LIT> ) && ! Subtarget . hasXOP ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( supportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , Opcode ) ) { unsigned LogicalOp = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned Logical<ISA_LIT>Op = getTargetVShiftUniformOpcode ( LogicalOp , false ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , BaseShAmtIdx , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , BaseShAmtIdx ,


<s> if ( isPlus ) Disp += TmpInteger ; else Disp -= TmpInteger ; break ; case IBES_REGISTER : State = IBES_START ; if ( ! BaseReg ) { BaseReg = TmpReg ; } else


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; II = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; TD = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getTargetData ( ) ; JTI = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; JTI -> Initialize ( MF , IsPIC ) ; do { DOUT << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB


<s> <ISA_LIT>CTRLoops ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>CTRLoopsPass ( * PassRegistry ::


<s> unsigned ConvOpc = IsSingle ? ( IsSigned ? <STR_LIT> : <STR_LIT> ) : ( IsSigned ? <STR_LIT> : <STR_LIT> ) ; EVT ConvTy = IsSingle ? <STR_LIT> : <STR_LIT> ; if ( Op -> isStrictFPOpcode ( ) ) { if ( ! Chain ) Chain = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( get<ISA_LIT>StrictOpcode ( ConvOpc ) , dl , DAG . getVTList ( ConvTy , <STR_LIT> ) , { Chain , Src } , Flags ) ; } else return DAG . getNode ( ConvOpc , dl


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) )


<s> const_tree decl = SYMBOL_REF_DECL ( sym ) ; if ( flag_pic && decl && ( ! flag_plt || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) && ! targetm . binds_local_p ( decl ) ) return true ; return false


<s> const std :: string & <ISA_LIT>To<ISA_LIT>Stub :: name ( ) const { return m_Name


<s> void addImm0_4095NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI -> getFalseValue ( ) ) ; unsigned CondReg = getRegForValue ( Cond ) ; if ( ! Src1Reg || ! Src2Reg || ! CondReg ) return false ; unsigned ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! ZExtCondReg ) return false ; if ( ! emitIntExt ( <STR_LIT> , CondReg , <STR_LIT> , ZExtCondReg , true ) ) return false ; unsigned ResultReg = createResultReg ( RC ) ; unsigned TempReg = createResultReg ( RC ) ; if ( ! ResultReg || ! TempReg ) return false ; emitInst ( TargetOpcode :: COPY , TempReg ) . addReg ( Src2Reg ) ; emitInst ( CondMovOpc , ResultReg ) . addReg ( Src1Reg ) . addReg ( ZExtCondReg ) . addReg ( TempReg ) ; updateValueMap ( I , ResultReg )


<s> for ( i = lower ; i < higher ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ i ] =


<s> SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , StackPtr , TOCOff ) ; Ops . push_back ( AddTOC ) ; } if ( Subtarget . usesFunctionDescriptors ( ) && ! hasNest ) Ops . push_back ( DAG . getRegister ( Subtarget . getEnvironmentPointerRegister ( ) , RegVT ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! isPatchPoint ) Ops . push_back ( DAG . getRegister ( Subtarget . getTOCPointerRegister ( ) , RegVT ) ) ; if ( isVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; const TargetRegisterInfo * TRI = Subtarget .


<s> got_entry = getTarget ( ) . getGOT ( ) . create ( ) ; getTarget ( ) . getGOT ( ) . create ( ) -> setValue ( <NUM_LIT> ) ; helper_DynRel_init ( NULL , * got_entry , <NUM_LIT> , llvm :: ELF :: R_386_TLS_DTPMOD32 , * this ) ; return *


<s> static void arm_asm_init_sections ( void )


<s> rtx_insn * tmp ; enum attr_type type , type2 ; type = get_attr_type ( last_scheduled_insn ) ; if ( type == TYPE_DIV && divide_cnt == <NUM_LIT> ) { divide_cnt = <NUM_LIT> ; pos = lastpos ; while ( pos >= <NUM_LIT> ) { if ( recog_memoized ( ready [ pos ] ) >= <NUM_LIT> && get_attr_type ( ready [ pos ] ) == TYPE_DIV ) { tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; break ; } pos -- ; } } else { divide_cnt = <NUM_LIT> ; if ( type == TYPE_VECLOAD ) { if ( vec_pairing == <NUM_LIT> ) { int vecload_pos = - <NUM_LIT> ; pos = lastpos ; while ( pos >= <NUM_LIT> ) { if ( recog_memoized ( ready [ pos ] ) >= <NUM_LIT> ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( is_power9_pairable_vec_type ( type2 ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; vec_pairing = <NUM_LIT> ; return cached_can_issue_more ; } else if ( type2 == TYPE_VECLOAD && vecload_pos == - <NUM_LIT> ) vecload_pos = pos ; } pos -- ; } if ( vecload_pos >= <NUM_LIT> ) { tmp = ready [ vecload_pos ] ; for ( i = vecload_pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; vec_pairing = <NUM_LIT> ; return cached_can_issue_more ; } } } else if ( is_power9_pairable_vec_type ( type ) ) { if ( vec_pairing == <NUM_LIT> ) { int vec_pos = - <NUM_LIT> ; pos = lastpos ; while ( pos >=


<s> Inst . addOperand ( MCOperand :: createImm


<s> unsigned getSize ( ) const { return CurType .


<s> uint32_t C = isC ? cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) : ~ <NUM_LIT> ; if ( C <= <NUM_LIT> && ( ( C & <NUM_LIT> ) == <NUM_LIT> ) ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , CurDAG -> getTargetConstant ( C / <NUM_LIT> , <STR_LIT> ) , Chain ) ; if ( Subtarget -> isThumb1Only ( ) ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , Size , Chain ) ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT> (


<s> sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned LabelReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned LabelReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) . addImm ( <STR_LIT> ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( mainDstReg ,

RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno )


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregoiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t


<s> Sched :: Preference <ISA_LIT>TargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref || <ISA_LIT>SubTarget . enableMachineScheduler ( ) ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched ::


<s> if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = <NUM_LIT> ; DECL_EXTERNAL ( new_fndecl ) = <NUM_LIT> ; DECL_IS_NOVOPS ( new_fndecl ) = <NUM_LIT> ; TREE_READONLY ( new_fndecl ) = <NUM_LIT> ; return new_fndecl


<s> } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) )


<s> case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( TARGET_AVX ) break ; if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : std :: swap ( * pop0 , * pop1 ) ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( )


<s> unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( Size != <NUM_LIT> && <STR_LIT> ) ; switch ( Size ) { case <NUM_LIT> : return IsLoadStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return IsLoadStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } } if ( Opc != TargetOpcode :: G_AND ) return <STR_LIT> ; Optional < uint64_t > MaybeAndMask = getImmedFromMO ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! MaybeAndMask )


<s> case <STR_LIT> : return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT>


<s> insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vexXopType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vexXopType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , &


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> auto * ZeroVec = getOpcodeDef ( G_BUILD_VECTOR , I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! ZeroVec ) return false ; int64_t Zero = <NUM_LIT> ; if ( ! mi_match ( ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Zero ) ) || Zero ) return false ; for ( unsigned i = <NUM_LIT> , e = ZeroVec -> getNumOperands ( ) - <NUM_LIT> ; i < e ; ++ i ) { if ( ZeroVec -> getOperand ( i ) . getReg ( ) != ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; } LLT VecTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT EltTy = VecTy . getElementType ( ) ; if ( VecTy . getSizeInBits ( ) != <NUM_LIT> || EltTy . getSizeInBits ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg


<s> assert ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; SMLoc End ; const MCExpr * Val ; if ( getParser ( ) . ParseExpression ( Val , End ) ) return <NUM_LIT> ; End = Parser . getTok ( ) . getLoc ( ) ; unsigned Size = <NUM_LIT> ; if ( const MCSymbolRefExpr * SymRef = dyn_cast < MCSymbolRefExpr > ( Val ) ) { const MCSymbol & Sym = SymRef -> getSymbol ( ) ; if ( ! SemaCallback -> LookupInlineAsmIdentifier ( Sym . getName ( ) , NULL , Size ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Size /= <NUM_LIT> ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , Size


<s> static int rs6000_variable_issue_1 ( rtx_insn * insn , int more ) { last_scheduled_insn = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) { cached_can_issue_more = more ; return


<s> unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get


<s> const char * addend = ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( ! speculate ) { s += sprintf ( s , <STR_LIT> , tls , rel64 , notoc , funop , addend ) ; s += sprintf ( s , <STR_LIT> ) ; } s += sprintf ( s , <STR_LIT> , tls , rel64 , notoc , funop , addend ) ; } else if ( ! speculate ) s += sprintf ( s , <STR_LIT> ) ; if ( rs6000_pcrel_p ( ) ) { if ( speculate ) sprintf ( s , <STR_LIT> , funop ) ; else sprintf ( s , <STR_LIT> , funop ) ; } else if ( DEFAULT_ABI == ABI_AIX ) { if ( speculate ) sprintf ( s , <STR_LIT> <STR_LIT> , funop , ptrload , funop + <NUM_LIT> ) ; else sprintf ( s , <STR_LIT> <STR_LIT> , funop , ptrload , funop + <NUM_LIT> ) ; } else if ( DEFAULT_ABI == ABI_ELFv2


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent (


<s> MBBInfo -> TBB = NewDest ; MBBInfo -> BrInstr = MIB . getInstr ( ) ; } else { MachineBasicBlock :: iterator UncondBrI = findUncondBrI ( MBB ) ; BuildMI ( * MBB , UncondBrI , MBB -> findDebugLoc ( UncondBrI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewDest ) ; MBBInfo -> FBB = NewDest ; BrMI = & * UncondBrI ; } fixPHIsInSucc ( NewDest , OrigDest , MBB ) ; BrMI -> eraseFromParent ( ) ; MBB -> addSuccessor ( NewDest )


<s> if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode0 , op2 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op3 , mode1 ) ) op3 = copy_to_mode_reg ( mode0 , op3 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; if ( mode0 == V2SImode ) emit_insn ( gen_spe_evsel ( target , op2 , op3 , scratch ) ) ; else emit_insn ( gen_spe_evsel_fs ( target ,


<s> void * <ISA_LIT>JITInfo :: emitGlobalValueIndirectSym ( const GlobalValue * GV , void * ptr , MachineCodeEmitter & MCE ) { MCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; MCE . emitWordLE ( ( unsigned


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { CommentStream =


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> case <STR_LIT> : case <STR_LIT> : return AddressingMode ( false , false ) ; } } if ( isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { auto * SingleUser = dyn_cast < Instruction > ( * I -> user_begin ( ) ) ; if ( SingleUser -> getParent ( ) == I -> getParent ( ) ) { if ( isa < ICmpInst > ( SingleUser ) ) { if ( auto * C = dyn_cast < ConstantInt > ( SingleUser -> getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) || isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) return AddressingMode ( false , false ) ; } else if ( isa < StoreInst > ( SingleUser ) ) return getLoadStoreAddrMode ( HasVector , I -> getType ( ) ) ; } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ; if ( isa < InsertElementInst > ( LoadUser ) ) IsVectorAccess = true ; } if ( IsFPAccess || IsVectorAccess ) return AddressingMode ( false , true


<s> return ( __m64 ) __builtin_ia32_pcmpeqb ( ( __v8qi ) __m1 , (


<s> unsigned VecWidth = DataType -> getPrimitiveSizeInBits ( ) ; return VecWidth == <NUM_LIT> ; } Type * ScalarTy = DataType -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy ->


<s> return GV != nullptr || CP != nullptr || ES != nullptr || JT

!= - <NUM_LIT> || BlockAddr != nullptr ;


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return S


<s> OutMI . clear ( ) ; OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OutMI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> )


<s> BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits0 ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits1 ; if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs && SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { return DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand

( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( )


<s> auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None || * MaybeImmed


<s> } gen_check = get_spec_check_gen_function ( ds , mode_no , label == NULL_RTX , true ) ; check_pat = gen_check ( copy_rtx ( recog_data . operand [ <NUM_LIT> ] ) , op1 ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) check_pat = gen_rtx_COND_EXEC ( VOIDmode ,

copy_rtx ( COND_EXEC_TEST ( pat ) ) , check_pat ) ;


<s> return generateCompactUnwindEncodingImpl ( Instrs


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Offset = - Offset ; int64_t AbsPostOffset = std :: abs ( Offset - Size ) ; const int64_t kMaxOffset = <NUM_LIT> ; if ( AbsPostOffset <= kMaxOffset && AbsPostOffset % <NUM_LIT> == <NUM_LIT> ) { * TotalOffset = Offset ; return true ; } } return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Op1 , DemandedMask ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne , TLO ) ) DCI


<s> if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt


<s> do next = next_nonnote_insn ( next ) ; while ( next && GET_CODE ( next ) == CODE_LABEL ) ; if ( ! next || ! INSN_P ( next ) || GET_CODE ( PATTERN ( next ) ) == ADDR_DIFF_VEC ||

recog_memoized ( next ) == CODE_FOR_consttable_2 ) return <NUM_LIT> ;


<s> static int rid_int128 ( void ) { int i ; for ( i = <NUM_LIT> ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ]

&& int_n_data [ i ] . bitsize == <NUM_LIT> ) return RID_INT_N_0 + i ;


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return


<s> for ( unsigned i = EltSize , e = <NUM_LIT> ; i != e ; i += EltSize ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( N -> getOperand ( i ) ) && <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != EltSize ; ++ j ) if ( N -> getOperand ( i + j ) != N -> getOperand ( j ) ) return false ; } return


<s> switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , NULL ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , & Args , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned )


<s> void <ISA_LIT>ConditionalCompares :: updateDomTree ( ArrayRef < MachineBasicBlock * > Removed ) { MachineDomTreeNode * HeadNode = DomTree -> getNode ( CmpConv . Head ) ; for ( MachineBasicBlock * RemovedMBB : Removed


<s> return ( int16x8_t ) __builtin_aarch64_saddl2v16qi ( __a ,


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) )


<s> const MachineOperand & BaseReg = MI -> getOperand ( Op ) ; const MachineOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) ) ; } if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <NUM_LIT> , Modifier ) ; unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) O << ',' << ScaleVal ; } O << ')'


<s> } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) > - <NUM_LIT> && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && ( ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) > - <NUM_LIT> ) || REGNO ( operands [ <NUM_LIT> ] ) > <NUM_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; case HImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; case QImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx )


<s> } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , <NUM_LIT> > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * <NUM_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ; PerformArgSplit ( SplitRegs , BitOffsets


<s> int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlign ( FrameIndex ) . value ( ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset -


<s> if ( ( TARGET_LONG_CALLS && ! mips_near_type_p ( type ) ) ||

mips_far_type_p ( type ) ) SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_LONG_CALL ;


<s> unsigned Reg = RS ? RS -> FindUnusedReg ( RC , true ) : ( unsigned ) <STR_LIT> ; assert ( ! AFI ->


<s> unsigned M = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode )


<s> MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; } bool BigStack = ( RS && estimateStackSize ( MF ) >= TII . estimateRSStackLimit ( MF ) ) || MFI -> hasVarSizedObjects ( ) || ( MFI -> adjustsStack ( ) && ! hasReservedCallFrame ( MF ) ) ; if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) { ExtraReg = CSRegs [ i ] ; break ; } } if ( ExtraReg !=


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger


<s> SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask ,

Zeroable , Subtarget , DAG ) ) return Masked ;


<s> switch ( ContainerVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Val = DAG . getNode ( ExtendOpc , DL , <STR_LIT> , Val ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : Val = DAG . getNode ( ExtendOpc , DL , <STR_LIT> , Val ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT>


<s> TargetLDBackend * create<ISA_LIT>LDBackend ( const LinkerConfig & pConfig ) { if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT>


<s> if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; auto FindBases = [ & ] ( Base2InstMap & Base2Ops , BaseVec & Bases ) { MapIt BI = Base2Ops . find ( Base ) ; if ( BI == Base2Ops . end ( ) ) { Base2Ops [ Base ] . push_back ( & MI ) ; Bases . push_back ( Base ) ; return ; } for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } ; if ( isLd ) FindBases ( Base2LdsMap , LdBases ) ; else FindBases ( Base2StsMap , StBases ) ; if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear ( ) ; LdBases . clear ( ) ; StBases . clear (


<s> const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT>


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } else if ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { return


<s> static void rs6000_elf_unique_section ( tree decl


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne


<s> rtx regbuf ; ns = cfun -> machine -> arg_regs_to_save ; if ( TARGET_IVC2 ) { bufsize = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> * ns ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } else { bufsize = ns * <NUM_LIT> ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } move_block_from_reg ( <NUM_LIT> - ns , regbuf , ns ) ; if ( TARGET_IVC2 ) { rtx tmp = gen_rtx_MEM ( DImode , XEXP ( regbuf , <NUM_LIT> ) ) ; int ofs = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < ns ; i ++ ) { int rn = ( <NUM_LIT> - ns ) + i + <NUM_LIT> ; rtx ptr ; ptr = offset_address ( tmp , GEN_INT ( ofs ) , <NUM_LIT> ) ; emit_move_insn ( ptr , gen_rtx_REG ( DImode , rn ) ) ; ofs += <NUM_LIT>


<s> static bool UpdateOperandRegClass ( MachineInstr * Instr ) { MachineBasicBlock * MBB = Instr -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetMachine * TM = & MF -> getTarget ( ) ; const TargetInstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = TM -> getSubtargetImpl ( ) -> getRegisterInfo ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx )


<s> if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; EVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , ExtVT . getScalarType ( ) ) ; const Constant * C = ( dyn_cast < ConstantSDNode > ( Cst ) ) -> getConstantIntValue ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP


<s> if ( Triple ( TT ) . isOSDarwin ( ) ) { MCStreamer * S = createMachOStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ; new <ISA_LIT>TargetMachOStreamer ( * S ) ; return S ; } MCStreamer * S = createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ; new <ISA_LIT>TargetELFStreamer (


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; unsigned Opc = <NUM_LIT> ; bool Offset = true ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) &&


<s> O << <STR_LIT> << getFunctionNumber ( )


<s> int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_or_fixed_reg_p ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ; if (


<s> unsigned <ISA_LIT>CodeEmitter :: getMSAMemEncoding ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF


<s> return __builtin_ia32_cvttsd2si ( ( __v2df


<s> return __builtin_aarch64_simd_bslv2di_suss ( __a ,


<s> vec_uint4 neg_b ; vec_uint4 mask ; neg_b = vec_splat ( ( vec_uint4 ) ( si_from_int ( - b ) ) , <NUM_LIT> ) ; mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> ,


<s> void <ISA_LIT>CallEntry :: printCustom ( raw_ostream & O ) const { O << <STR_LIT> ; if ( Val ) O << Val -> getName


<s> unsigned op = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned length = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } for ( unsigned i = <NUM_LIT> ; i < length ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rn + i ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> rtx tmp , op1_subreg ; rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > <NUM_LIT> ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = <NUM_LIT> << ( <NUM_LIT> - shift_amount - <NUM_LIT> ) ; and_constant = ( code == ASHIFT ? <NUM_LIT> - ( <NUM_LIT> << shift_amount ) : ( <NUM_LIT> << ( <NUM_LIT> - shift_amount ) ) - <NUM_LIT> ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode =


<s> void relaxInstruction ( const MCInst & Inst ,


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler ::


<s> EVT VT = Op . getValueType ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || ( Op0 . getOpcode ( ) != <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Min = Op ; SDValue Max = Op0 ; SDValue Input = Op0 . getOperand ( <NUM_LIT> ) ; if ( Min . getOpcode ( ) == <STR_LIT> ) std :: swap ( Min , Max ) ; APInt MinC = Min . getConstantOperandAPInt


<s> if ( MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) return ; if ( ! MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! RegInfo -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! MRI . isPhysRegOrOverlapUsed ( <STR_LIT>


<s> return CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( )


<s> void <ISA_LIT>TargetStreamer :: emitRI ( unsigned Opcode , unsigned Reg0 , int32_t Imm , SMLoc


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU ,


<s> } Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int32_t Val = CE -> getValue ( ) / <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned VARegSize = ( <NUM_LIT> - NumGPRs ) * <NUM_LIT> ; unsigned VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; VarArgsFrameIndex = MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; NumGPRs < <NUM_LIT> ; ++ NumGPRs ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , NULL , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } if ( ! MemOps . empty ( ) ) Root = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ]


<s> EVT PromotedVT = VT . changeVectorElementType ( <STR_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || Index . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) PromotedVT = VT . changeVectorElementType ( <STR_LIT> ) ; unsigned ExtOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; Index = DAG . getNode ( ExtOpcode , DL , PromotedVT , Index ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PromotedVT , Mask ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , PromotedVT , StoreVal ) ; if ( PromotedVT != VT ) Truncating = true ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , PromotedVT ) ; MemVT = ContainerVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; Index = convertToScalableVector ( DAG , ContainerVT , Index ) ; Mask = convertFixedMaskToScalableVector ( Mask , DAG ) ; StoreVal = convertToScalableVector ( DAG , ContainerVT , StoreVal ) ; SDValue Ops [ ] = { Chain , StoreVal , Mask , BasePtr , Index , Scale } ; return DAG . getMaskedScatter ( MSC -> getVTList ( ) , MemVT , DL , Ops , MSC -> getMemOperand ( ) , IndexType , Truncating ) ; } bool NeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; SDVTList VTs = DAG . getVTList ( <STR_LIT>


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case <STR_LIT> : { Register Src = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( Src , MRI ) ; if ( ! ValAndVReg ) return false ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto * CV = ConstantDataVector :: getSplat ( MRI . getType ( Dst ) . getNumElements ( ) , ConstantInt :: get ( Type :: getIntNTy ( Ctx , MRI . getType ( Src ) . getSizeInBits ( ) ) , ValAndVReg -> Value ) ) ; if ( ! emitConstantVector ( Dst , CV , MIB , MRI ) ) return false ; I . eraseFromParent ( ) ; return true ; } case TargetOpcode :: G_BR : { bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None ; if ( EnableOpt || ! MBB . isLayoutSuccessor ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) return false ; I . eraseFromParent ( ) ; return true ; } case TargetOpcode :: G_SHL : return earlySelectSHL ( I , MRI ) ; case TargetOpcode :: G_CONSTANT : { bool IsZero = false ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) == <NUM_LIT> ; else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; if ( ! IsZero ) return false ; Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; return true ; } case TargetOpcode :: G_ADD : { Register X = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( X ) ; if ( Ty . isVector ( ) || Ty . getSizeInBits ( ) != <NUM_LIT> ) return false ; Register CmpReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Cmp = getOpcodeDef ( TargetOpcode :: G_ICMP , CmpReg , MRI ) ; if ( !


<s> CmpInstr -> getParent ( ) -> rend ( ) ; MachineInstr * Movr0Inst = <NUM_LIT> ; for ( ; RI != RE ; ++ RI ) { MachineInstr * Instr = & * RI ; if ( isRedundantFlagInstr ( CmpInstr , SrcReg , SrcReg2 , CmpValue , Instr ) ) { Sub = Instr ; break ; } if ( Instr -> modifiesRegister ( <STR_LIT> , TRI ) || Instr -> readsRegister ( <STR_LIT> , TRI ) ) { if ( ! Movr0Inst && ( Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> ) && Instr -> registerDefIsDead ( <STR_LIT> , TRI ) ) { Movr0Inst = Instr ; continue ; } return false ; } } if ( ! Sub ) return false ; bool IsSwapped = ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ; bool IsSafe = false ; SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > OpsToUpdate ; MachineBasicBlock :: iterator E = CmpInstr -> getParent ( ) -> end ( ) ; for ( ++ I ; I != E ; ++ I ) { const MachineInstr & Instr = * I ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) ) { IsSafe = true


<s> MachineInstr * DPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DPRMI && SPRMI ) { MachineInstr * ECDef = elideCopies ( DPRMI ) ; if ( ECDef && ECDef -> isImplicitDef ( ) ) { MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> bool <ISA_LIT>AsmParser :: validatetSTMRegList ( MCInst Inst , const OperandVector & Operands , unsigned ListNo ) { const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ListContainsSP && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode3Offset ( SDValue Op , SDValue N , SDValue & Offset , SDValue & Opc ) { unsigned Opcode = Op . getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast <

StoreSDNode > ( Op ) -> getAddressingMode ( ) ;


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; HasLEB128 =


<s> static SDValue getTargetShuffleNode ( unsigned Opc , SDLoc dl , EVT VT , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( auto * Ld1 : Loads ) { if ( Ld0 == Ld1 ) continue ; if ( AreSequentialAccesses < LoadInst > ( Ld0 , Ld1 , * DL , * SE ) ) { LoadPairs [ Ld0 ] = Ld1 ; if ( BaseLoads . count ( Ld0 ) ) { LoadInst * Base = BaseLoads [ Ld0 ] ; BaseLoads [ Ld1 ] = Base ; SequentialLoads [ Base ] . push_back ( Ld1 ) ; } else


<s> Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( DstVT == <STR_LIT> && ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) && ! <ISA_LIT>SubTarget -> hasSPE ( ) ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( SrcReg ) ; SrcReg = TmpReg ; } unsigned DestReg ; unsigned Opc ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { DestReg = createResultReg (


<s> par_index = <NUM_LIT> ; offset = <NUM_LIT> ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { if ( regno == SP_REGNUM ) break ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_fp ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_gp ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_lp ) { reg = gen_rtx_REG ( SImode ,


<s> op0 = gen_lowpart ( vmode , dest ) ; memset ( perm2 , elt , <NUM_LIT> ) ; dest = gen_reg_rtx ( vmode ) ; ok = expand_vselect ( dest , op0 , perm2 , <NUM_LIT> , d -> testing_p ) ; gcc_assert ( ok ) ; emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , dest ) ) ; return true ; case E_V8QImode : if ( d -> testing_p ) return true ; do { if ( elt >= nelt2 ) { gen = vmode == V8QImode ? gen_mmx_punpckhbw : gen_mmx_punpckhwd ; elt -= nelt2 ; } else gen = vmode == V8QImode ? gen_mmx_punpcklbw : gen_mmx_punpcklwd ; nelt2 /= <NUM_LIT> ; dest = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( dest , op0 , op0 ) ) ; vmode = get_mode_wider_vector ( vmode ) ; op0 = gen_lowpart ( vmode , dest ) ; } while ( vmode != V2SImode ) ; memset ( perm2 , elt , <NUM_LIT> ) ; dest = gen_reg_rtx ( vmode ) ; ok = expand_vselect ( dest , op0 , perm2 , <NUM_LIT> , d -> testing_p ) ; gcc_assert ( ok ) ; emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , dest ) ) ; return true ; case E_V8HImode : case E_V16QImode : if ( d -> testing_p ) return true ; do { if ( elt >= nelt2 ) { gen = vmode == V16QImode ? gen_vec_interleave_highv16qi : gen_vec_interleave_highv8hi ; elt -= nelt2 ; } else gen = vmode == V16QImode ? gen_vec_interleave_lowv16qi : gen_vec_interleave_lowv8hi ; nelt2 /= <NUM_LIT> ; dest = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( dest , op0 , op0 ) ) ; vmode = get_mode_wider_vector ( vmode ) ; op0 = gen_lowpart ( vmode , dest ) ; } while ( vmode != V4SImode ) ; memset ( perm2 , elt , <NUM_LIT> ) ; dest = gen_reg_rtx ( vmode ) ; ok = expand_vselect ( dest , op0 , perm2 , <NUM_LIT> , d -> testing_p ) ; gcc_assert ( ok ) ; emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , dest ) ) ; return true ; case E_V8HFmode : case E_V8BFmode : if ( d -> testing_p ) return true ; rtx ( * maybe_gen ) ( machine_mode , int , rtx , rtx , rtx ) ; if ( elt >= nelt2 ) { maybe_gen = maybe_gen_vec_interleave_high ; elt -= nelt2 ; } else maybe_gen = maybe_gen_vec_interleave_low ; nelt2 /= <NUM_LIT> ; dest = gen_reg_rtx ( vmode ) ; emit_insn ( maybe_gen ( vmode , <NUM_LIT> , dest , op0 , op0 ) ) ; vmode = V4SImode ; op0 = gen_lowpart ( vmode , dest ) ; memset ( perm2 , elt , <NUM_LIT> ) ; dest = gen_reg_rtx (


<s> RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( The<ISA_LIT>elTarget


<s> static SDValue PerformVDUPLANECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( CombineVLDDUP ( N , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( )


<s> const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( * I . getParent ( ) , ++ I . getIterator ( ) , I . getDebugLoc ( ) , TII

-> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ;


<s> Register NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI ->


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const


<s> return ( int8x8x2_t ) { vtrn1_s8 ( a , b ) , vtrn2_s8 (


<s> case <STR_LIT> : { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; if ( shiftedInBitsMatter ( RxSBG , RxSBG . BitSize - InnerBitSize , false ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { ConstantSDNode * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> ) { if ( shiftedInBitsMatter ( RxSBG , Count , true ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) << Count ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate + Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( shiftedInBitsMatter ( RxSBG , Count , false ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate -


<s> static bool isUndefOrInRange ( SDValue Op , unsigned Low , unsigned Hi ) { if ( Op . getOpcode ( ) == <STR_LIT> ) return true ; unsigned Val = cast < ConstantSDNode > (


<s> unsigned getMemSegReg ( ) const { assert ( Kind == Memory && <STR_LIT>


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) f [ i ] = g [ i ] - h [ i ] ; f [ <NUM_LIT> ] = g [ <NUM_LIT> ] - h [ <NUM_LIT> ] ; f [ <NUM_LIT> ] = g [ <NUM_LIT> ] - h [ <NUM_LIT> ] ; f [ <NUM_LIT> ] = g [ <NUM_LIT> ] - h


<s> SDValue V1 = IsZero ? getZeroVector ( VT , Subtarget , DAG , SDLoc ( V2 ) ) : DAG . getUNDEF ( VT ) ; int NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > MaskVec ( NumElems


<s> EVT VT = getPointerTy ( ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI


<s> SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( i == Idx ? NumElems : i ) ; return DAG . getVectorShuffle ( VT , V2 . getDebugLoc ( ) , V1 , V2 , & MaskVec


<s> int getFramePointerOffset ( ) const { return FramePointerOffset


<s> rtx base , index ; if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) ) : REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) ) ) ) base = XEXP ( x , <NUM_LIT> ) , index = XEXP ( x , <NUM_LIT> ) ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) ) : REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) ) ) ) base = XEXP ( x , <NUM_LIT> ) , index = XEXP ( x , <NUM_LIT> ) ; else return false ; if ( GET_CODE ( index ) == CONST_INT ) { if ( INT_5_BITS ( index ) ) return true ; if ( ! INT14_OK_STRICT && ( strict || ! ( reload_in_progress || reload_completed ) ) && mode != QImode && mode != HImode ) return false ; return base14_operand ( index , mode ) ; } if ( ! TARGET_DISABLE_INDEXING && ( TARGET_NO_SPACE_REGS ? REG_P ( index ) : ( base == XEXP ( x , <NUM_LIT> ) && REG_P ( index ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( base ) ) || REG_POINTER ( base ) ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( index ) ) || ! REG_POINTER ( index ) ) ) ) && MODE_OK_FOR_UNSCALED_INDEXING_P ( mode ) && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( index ) : REG_OK_FOR_INDEX_P ( index ) ) && borx_reg_operand ( base , Pmode ) && borx_reg_operand ( index , Pmode ) ) return true ; if ( ! TARGET_DISABLE_INDEXING && GET_CODE ( index ) == MULT && MODE_OK_FOR_SCALED_INDEXING_P ( mode ) && REG_P ( XEXP ( index , <NUM_LIT> ) ) && GET_MODE ( XEXP ( index , <NUM_LIT> ) ) == Pmode && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) : REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) ) && GET_CODE ( XEXP ( index , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( index , <NUM_LIT> ) ) == ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) && borx_reg_operand ( base , Pmode ) ) return true ; return false ; } if ( GET_CODE ( x ) == LO_SUM ) { rtx y = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( y ) == SUBREG ) y = SUBREG_REG (


<s> T = <NUM_LIT> ; } else { S = pReloc . symValue ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; } S = S + A ; if ( T == <NUM_LIT> ) { if ( pReloc . type ( ) == llvm :: ELF :: R_<ISA_LIT>_THM_JUMP24 ) return Relocator :: BadReloc ; S = helper_bit_select ( S , P , <NUM_LIT> ) ; lower_inst &= ~ <NUM_LIT> ; } else { lower_inst |= <NUM_LIT> ; } Relocator :: DWord X = ( S | T ) - P ; if ( helper_check_signed_overflow ( X , <NUM_LIT> ) ) { return Relocator :: Overflow ; } upper_inst = helper_thumb32_branch_upper ( upper_inst , X ) ; lower_inst = helper_thumb32_branch_lower ( lower_inst ,


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( <NUM_LIT> ) , II -> getParent ( )


<s> MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto R : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) VLSTM . addReg ( R , RegState :: Implicit | ( LiveRegs . contains ( R ) ? <NUM_LIT> : RegState :: Undef ) ) ; } else { MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ,

<STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , aarch64_cpu_string , aarch64_arch_string ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( aarch64_enable_bti


<s> static void aarch64_conditional_register_usage ( void ) { int i ; if ( ! TARGET_FLOAT ) { for ( i = V0_REGNUM ; i <= V31_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( ! TARGET_SVE ) for ( i = P0_REGNUM ; i <= P15_REGNUM ;


<s> assert ( MemOffsetOp . isImm ( ) && <STR_LIT> ) ; unsigned OpCode = <NUM_LIT> ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : OpCode = <STR_LIT> ; break ; case <STR_LIT> : OpCode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } int64_t ImmValue = ImmOp . getImm ( ) ; if ( ImmValue == <NUM_LIT> ) { MCInst BranchInst ; BranchInst . setOpcode ( OpCode ) ; BranchInst . addOperand ( DstRegOp ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MemOffsetOp ) ; Instructions . push_back ( BranchInst ) ; } else


<s> static SDValue lowerFABS32 ( SDValue Op , SelectionDAG & DAG , bool HasR2 ) { SDValue Res , Const1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL


<s> virtual void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC


<s> } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) { switch ( It -> getOpcode ( ) ) { default : break ; case


<s> bool isN32 ( ) const { return Subtarget -> isABI_N32


<s> } unsigned NumElts = I . getNumOperands ( ) - <NUM_LIT> ; Register SrcReg = I . getOperand ( NumElts ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( ( WideTy . isVector ( ) || WideTy . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; assert ( WideTy . getSizeInBits ( ) > NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( ! NarrowTy . isScalar ( ) ) return selectSplitVectorUnmerge ( I , MRI ) ; unsigned CopyOpc = <NUM_LIT> ; unsigned ExtractSubReg = <NUM_LIT> ; if ( ! getLaneCopyOpcode ( CopyOpc , ExtractSubReg , NarrowTy . getSizeInBits ( ) ) ) return false ; MachineBasicBlock & MBB = * I . getParent ( ) ; SmallVector < Register , <NUM_LIT> > InsertRegs ; unsigned NumInsertRegs = NumElts - <NUM_LIT> ; if ( NarrowTy . getSizeInBits ( ) * NumElts == <NUM_LIT> ) { InsertRegs = SmallVector < Register , <NUM_LIT> > ( NumInsertRegs , SrcReg ) ; } else { for ( unsigned Idx = <NUM_LIT> ; Idx < NumInsertRegs ; ++ Idx ) { Register ImpDefReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & ImpDefMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImpDefReg ) ; Register InsertReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & InsMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: INSERT_SUBREG ) , InsertReg ) . addUse ( ImpDefReg ) . addUse ( SrcReg ) . addImm ( <STR_LIT> ) ; constrainSelectedInstRegOperands ( ImpDefMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( InsMI , TII , TRI , RBI ) ; InsertRegs . push_back ( InsertReg ) ; } } Register CopyTo = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FirstCopy = MIB . buildInstr ( TargetOpcode :: COPY , { CopyTo } , { } ) . addReg ( InsertRegs [ <NUM_LIT> ] , <NUM_LIT> , ExtractSubReg ) ; constrainSelectedInstRegOperands ( * FirstCopy , TII , TRI , RBI ) ; unsigned LaneIdx = <NUM_LIT> ; for ( Register InsReg : InsertRegs ) { Register CopyTo = I . getOperand ( LaneIdx ) . getReg ( ) ; MachineInstr & CopyInst = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( CopyOpc ) , CopyTo ) . addUse ( InsReg ) . addImm ( LaneIdx ) ; constrainSelectedInstRegOperands ( CopyInst , TII , TRI , RBI ) ; ++ LaneIdx ; } const TargetRegisterClass * RC = MRI . getRegClassOrNull ( I .


<s> alias_set_type get_TOC_alias_set ( void ) { if ( set == - <NUM_LIT> ) set = new_alias_set ( ) ; return


<s> static bool rx_return_in_msb ( const_tree valtype ) { return TARGET_BIG_ENDIAN_DATA && ( AGGREGATE_TYPE_P ( valtype ) ||

TREE_CODE ( valtype ) == COMPLEX_TYPE ) ;


<s> } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) .


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> ExtSize = TypeSize ; } } } TruncInst * T ; if ( ( I -> getOpcode ( ) == Instruction :: Store || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && ( T = dyn_cast < TruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) { unsigned TypeSize = T -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( EltSize == <NUM_LIT> && TypeSize == <NUM_LIT> ) || ( EltSize == <NUM_LIT> && ( TypeSize == <NUM_LIT> || TypeSize == <NUM_LIT> ) ) ) && TypeSize * NumElems == <NUM_LIT> ) ExtSize = TypeSize ; } } if ( ExtSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( ExtSize == <NUM_LIT> ) return VectorCost ; if ( ExtSize != <NUM_LIT> && ExtSize != <NUM_LIT> ) return ScalarCost ; if ( const auto * BC = dyn_cast < BitCastInst > ( Ptr ) ) Ptr = BC -> getOperand ( <NUM_LIT> ) ; if ( const auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) return ScalarCost ; unsigned Scale = DL . getTypeAllocSize (


<s> Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; } SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDNode * VStA = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Opc = QOpcodes1 [ OpcodeIndex ] ; SDNode * VStB = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStB , <NUM_LIT>


<s> temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] ,