<s> } Group . push_back ( & I ) ; if ( FoundNonCMOVInst || ( CC != FirstCC && CC != FirstOppCC ) ) SkipGroup = true ; continue ; } if ( Group . empty ( ) ) continue ; FoundNonCMOVInst = true ; if ( I . definesRegister ( <STR_LIT> ) ) { if ( ! SkipGroup ) CmovInstGroups . push_back ( Group ) ; else ++ NumOfSkippedCmovGroups ; Group . clear (


<s> return true ; } mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT>


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ; return FastISel :: fastEmitInst_r ( MachineInstOpcode ,


<s> if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl (


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( Subtarget -> isTargetNaCl ( ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { std :: string str ; raw_string_ostream OS ( str ) ; Emit<ISA_LIT>SFIHeaders ( OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) )


<s> } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) ) ; RetAddrOffset = <NUM_LIT> ; } RetOps [ <NUM_LIT> ] = Chain ; RetOps [ <NUM_LIT> ] = DAG . getConstant ( RetAddrOffset ,


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT>


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; return N0


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = & * std


<s> Target & llvm :: getThe<ISA_LIT>32Target ( ) { static Target


<s> RegisterMCAsmInfoFn A ( TheThumbLETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( TheThumbBETarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbLETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbBETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbLETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbBETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbLETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbBETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>LETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>BETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbLETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbBETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbLETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbBETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>LETarget , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter (


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Align Alignment = MFI . getObjectAlign ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Alignment ) ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB ; if ( Subtarget . hasV5TEOps ( ) ) { MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> return __builtin_shuffle ( a , ( uint8x8_t ) { <NUM_LIT> , <NUM_LIT> ,


<s> if ( Register :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = getRegClassForTypeOnBank ( DstReg , MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI


<s> BICInst . addOperand ( MCOperand :: CreateImm ( Pred ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; BICInst . addOperand ( MCOperand :: CreateReg


<s> static bool onlyTileDef ( IntrinsicInst * II ) { for ( Value * Operand : II -> operands ( ) ) if ( Operand -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return false ; return II -> getType ( )


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT>


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget * Subtarget = & MF

. getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> vld1_dup_f32 ( const float32_t * __a ) { return ( float32x2_t ) __builtin_neon_vld1_dupv2sf ( ( const


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg (


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , ArrayRef < MachineMemOperand * > MMOs , SmallVectorImpl < MachineInstr * > & NewMIs ) const { const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . add ( Addr [ i ] ) ; MIB . setMemRefs ( MMOs ) ; NewMIs . push_back ( MIB


<s> return ( int32x4_t ) __builtin_aarch64_sqdmulhv4si (


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat


<s> if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( MImm . Val ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return isUInt < <NUM_LIT> >


<s> Op -> CC . Val = CC ; Op -> StartLoc = S ; Op -> EndLoc


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF


<s> if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case RS6000_BIF_TENDALL : case RS6000_BIF_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; case RS6000_BIF_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; default : break ; } rtx cr = NULL_RTX ; if ( uses_spr ) { machine_mode mode = TARGET_POWERPC64 ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; } else if ( bif_is_htmcr ( * bifaddr ) ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } rtx pat ; switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [


<s> FunctionPass * llvm :: create<ISA_LIT>MachineInstrPrinter (


<s> range = INTVAL ( op ) ; if ( ! IN_RANGE ( range , - <NUM_LIT> , <NUM_LIT> ) ) return false ; return ( range % <NUM_LIT> ) == <NUM_LIT> ; } case PRE_INC : case POST_INC : case PRE_DEC : case POST_DEC : return REG_P ( XEXP ( op , <NUM_LIT> ) ) ; default : gcc_unreachable (


<s> StringRef getSysReg ( ) const { assert ( Kind == k_SysReg && <STR_LIT>


<s> case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc ( exp ) ; case RX_BUILTIN_MVTIPL : return rx_expand_builtin_mvtipl ( op ) ; case RX_BUILTIN_RACW : return rx_expand_void_builtin_1_arg ( op , gen_racw , false ) ; case RX_BUILTIN_ROUND : return rx_expand_builtin_round ( op , target ) ; case RX_BUILTIN_REVW : return rx_expand_int_builtin_1_arg ( op , target , gen_revw , false ) ; case RX_BUILTIN_WAIT : emit_insn ( gen_wait ( ) ) ; return NULL_RTX ; default : internal_error (


<s> cfun -> machine -> seh -> after_prologue = true ; fputs ( <STR_LIT> , f


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClasses64Bit [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClassesWin64 [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( Is64Bit )


<s> PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> )


<s> SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG .

getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | (

<NUM_LIT> - MO . getImm ( ) ) << <NUM_LIT> ;


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; SDValue ResValue = OutVals [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ResValue = DAG . getNode (

<STR_LIT> , dl , VA . getLocVT ( ) , ResValue ) ;


<s> MI . eraseFromParent ( ) ; return true ; case <STR_LIT> : { MachineInstr * Trap = MIRBuilder . buildInstr ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Trap , TII , TRI , RBI ) ; } case <STR_LIT> : { Register Tmp = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachinePointerInfo MPO ; MIRBuilder . buildLoad ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; MIRBuilder . buildStore ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_ADD , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SUB , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_MUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FADD , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSUB , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT>


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC = DAG . getTargetConstant ( get<ISA_LIT>CC ( CC ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { FalseV , TrueV , LHS , RHS ,


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> )


<s> SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) { unsigned VReg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { if ( Subtarget )


<s> break ; } else if ( Offset == I -> Offset ) { break ; } } } } } } if ( Advance ) { ++ Position ; ++ MBBI ; } else TryMerge = true ; if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( & <STR_LIT> , true ) ; if ( ! Scratch ) Scratch = RS -> FindUnusedReg ( & <STR_LIT> , AFI -> getSpilledCSRegisters ( ) ) ; RS -> forward ( prior ( MBBI ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > MBBII = MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps ) ; for ( unsigned i = <NUM_LIT> , e = MBBII . size ( ) ; i < e ; ++ i ) if ( mergeBaseUpdateLSMultiple ( MBB , MBBII [ i ] , Advance , MBBI ) ) NumMerges ++ ; NumMerges += MBBII . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( mergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) NumMerges ++ ; RS -> skipTo ( prior ( MBBI ) ) ; } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear ( ) ; NumMemOps = <NUM_LIT> ; } if ( ! Advance && ! isMemOp && MBBI != E ) { ++ Position ; ++ MBBI ; } } } return NumMerges


<s> if ( ConstantEntry . isMachineConstantPoolEntry ( ) ) return nullptr ; auto * C = dyn_cast < Constant > ( ConstantEntry . Val . ConstVal ) ; assert ( ( ! C || ConstantEntry . getType ( ) ==


<s> } ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , labelno ) ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == TFmode ) { REAL_VALUE_TYPE rv ; long k [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_LONG_DOUBLE ( rv , k ) ; if ( TARGET_64BIT ) { if ( TARGET_MINIMAL_TOC ) fputs ( DOUBLE_INT_ASM_OP , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } else { if ( TARGET_MINIMAL_TOC ) fputs ( <STR_LIT> , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } } else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == DFmode ) { REAL_VALUE_TYPE rv ; long k [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv , k ) ; if ( TARGET_64BIT ) { if ( TARGET_MINIMAL_TOC ) fputs ( DOUBLE_INT_ASM_OP , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } else { if ( TARGET_MINIMAL_TOC ) fputs ( <STR_LIT> , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } } else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == SFmode ) { REAL_VALUE_TYPE


<s> return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ; return true ; } MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>MCAsmBackend ( OSABI


<s> SDLoc DL ( N ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; Results . push_back ( Cycles32 . getValue ( <NUM_LIT>


<s> SDValue Four = DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Chain , Addr , MachinePointerInfo ( ) ) ; Chain = CWD . getValue ( <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; RetVal = DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ; return DAG . getMergeValues ( { RetVal , Chain } , dl


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true ; rtx x ; int i ; if ( GET_CODE ( vals ) != CONST_VECTOR ) return NULL_RTX ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = CONST_VECTOR_ELT ( vals , i ) ; if ( ! rtx_equal_p ( x , CONST_VECTOR_ELT ( vals , <NUM_LIT> ) ) ) all_same = false ; } if ( ! all_same ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , CONST_VECTOR_ELT ( vals ,


<s> if ( rclass == NO_REGS && TARGET_SHMEDIA && ( CONST_DOUBLE_P ( x ) || GET_CODE ( x ) == SYMBOL_REF || PIC_ADDR_P ( x ) ) ) return GENERAL_REGS ; return


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>Target (


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false


<s> bool ThreeReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx


<s> unsigned NumElementsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; unsigned ControlBitsMask = NumLanes - <NUM_LIT> ; unsigned NumControlBits = NumLanes / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l !=


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) )


<s> { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } } ; std :: tie ( N , Opcode ) = IntrinsicMap [ Intrinsic ] ; assert ( VT . getVectorElementCount ( ) . getKnownMinValue ( ) % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( )

, VT . getVectorElementCount ( ) . divideCoefficientBy ( N ) ) ;


<s> return mode == DFmode ? loongarch_cost ->


<s> SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; auto * Constant = dyn_cast < ConstantSDNode > ( Cmp . getOperand ( <NUM_LIT> ) ) ; assert ( Constant && <STR_LIT> ) ; int64_t NegConstant = <NUM_LIT> - Constant -> getSExtValue ( ) ; switch ( cast < CondCodeSDNode > ( Cmp . getOperand ( <NUM_LIT> ) ) -> get ( ) ) { default : break ; case <STR_LIT> : { SDValue Add = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , DAG . getConstant ( NegConstant , DL , <STR_LIT> ) ) ; SDValue AddOrZ = NegConstant != <NUM_LIT> ? Add : Z ; SDValue Addc = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddOrZ , DAG . getConstant ( - <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VTs , LHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , SDValue ( Addc . getNode ( ) , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue Add = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , DAG . getConstant ( NegConstant , DL , <STR_LIT> ) ) ; SDValue AddOrZ = NegConstant != <NUM_LIT> ? Add : Z ; SDValue Subc = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , AddOrZ ) ; return DAG . getNode ( <STR_LIT> , DL , VTs , LHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , SDValue ( Subc . getNode ( ) , <NUM_LIT> ) ) ; } } return SDValue (


<s> NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBUtils -> insert ( NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , NewBB , CompareMBBNumbers


<s> MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor (


<s> getDebugValueLocation ( const MachineInstr * MI


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_X : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 ,


<s> unsigned CCValid = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) ; MI -> eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor ( JoinMBB


<s> OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = CurrentFnSymForSize ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( Current . first


<s> if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN64 ( ) ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( Subtarget . useXGOT ( ) ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode

( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx


<s> } else { if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else { if ( Identifier . find ( '.' ) != StringRef :: npos && PrevTK == AsmToken :: RBrac ) { return false ; } else { InlineAsmIdentifierInfo & Info = SM . getIdentifierInfo ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return true ; } } SM . onIdentifierExpr ( Val , Identifier ) ; UpdateLocLex = false ; break ; } return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } case AsmToken :: Integer : { StringRef ErrMsg ; if ( isParsingInlineAsm ( ) && SM . getAddImmPrefix ( ) ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Tok . getLoc ( ) ) ; SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef IDVal = getTok ( ) . getString ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { MCSymbol * Sym = getContext ( ) . getDirectionalLocalSymbol ( IntVal , IDVal == <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; const MCExpr * Val = MCSymbolRefExpr :: create ( Sym , Variant , getContext ( ) ) ; if ( IDVal == <STR_LIT> && Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> ) ; StringRef Identifier = Sym -> getName ( ) ; SM . onIdentifierExpr ( Val , Identifier ) ; End = consumeToken ( ) ; } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } } else


<s> bool mayNeedRelaxation ( const MCInst & ) const { return false


<s> MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) { if ( tryOptSelectConjunction ( I , * CondDef ) ) return true ; return false ; } <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg (


<s> if ( REG_NOTE_KIND ( link ) != <NUM_LIT> ) return <NUM_LIT> ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < <NUM_LIT> || recog_memoized ( insn ) < <NUM_LIT> ) return cost ; insn_type = get_attr_type ( insn ) ; dep_insn_type = get_attr_type ( dep_insn ) ; switch ( ix86_tune ) { case PROCESSOR_PENTIUM : if ( ix86_agi_dependant ( insn , dep_insn , insn_type ) ) cost += <NUM_LIT> ; if ( ix86_flags_dependant ( insn , dep_insn , insn_type ) ) cost = <NUM_LIT> ; if ( insn_type == TYPE_FMOV && get_attr_memory ( insn ) == MEMORY_STORE && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) cost += <NUM_LIT> ; break ; case PROCESSOR_PENTIUMPRO : memory = get_attr_memory ( insn ) ; if ( get_attr_fp_int_src ( dep_insn ) ) cost += <NUM_LIT> ; if ( insn_type == TYPE_FMOV && ( set = single_set ( dep_insn ) ) != NULL_RTX && ( set2 = single_set ( insn ) ) != NULL_RTX && rtx_equal_p ( SET_DEST ( set ) , SET_SRC ( set2 ) ) && GET_CODE ( SET_DEST ( set2 ) ) == MEM ) cost += <NUM_LIT> ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { if ( dep_insn_type == TYPE_IMOV || dep_insn_type == TYPE_FMOV ) cost = <NUM_LIT> ; else if ( cost > <NUM_LIT> ) cost -- ; } break ; case PROCESSOR_K6 : memory = get_attr_memory ( insn ) ; if ( ( insn_type == TYPE_PUSH || insn_type == TYPE_POP ) && ( dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP ) ) return <NUM_LIT> ; if ( get_attr_fp_int_src ( dep_insn ) ) cost += <NUM_LIT> ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { if ( dep_insn_type == TYPE_IMOV || dep_insn_type == TYPE_FMOV ) cost = <NUM_LIT> ; else if ( cost > <NUM_LIT> ) cost -= <NUM_LIT> ; else cost = <NUM_LIT> ; } break ; case PROCESSOR_ATHLON : case PROCESSOR_K8 : memory = get_attr_memory ( insn ) ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { enum attr_unit unit = get_attr_unit ( insn ) ; int loadcost = <NUM_LIT> ; if ( unit == UNIT_INTEGER || unit == UNIT_UNKNOWN ) loadcost = <NUM_LIT> ; else loadcost = TARGET_ATHLON ? <NUM_LIT> : <NUM_LIT> ; if ( cost >= loadcost ) cost


<s> return DAG . getExtLoad ( LD -> getExtensionType ( ) , LD -> getDebugLoc ( ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getMemoryVT (

) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS <<


<s> break ; case RegPairInfo :: FPR128 : if ( <STR_LIT> . contains ( NextReg ) ) RPI . Reg2 = NextReg ; break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; int Scale = RPI . Type == RegPairInfo :: FPR128 ? <NUM_LIT> : <NUM_LIT> ; Offset -= RPI . isPaired ( ) ? <NUM_LIT> * Scale : Scale ; if ( AFI -> hasCalleeSaveStackFreeSpace ( ) && ! FixupDone && RPI . Type != RegPairInfo :: FPR128 && ! RPI . isPaired ( ) ) { FixupDone = true ; Offset -= <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT>


<s> return __builtin_loongson_pmullh ( s , t


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT>


<s> static __inline vec_double2 spu_extend ( vec_float4 a ) { return ( ( vec_double2 ) ( si_fesd ( ( qword ) ( a )


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget >


<s> return ( __m128i ) vec_min ( ( __v8hi )


<s> Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * const Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeList A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( ! TM . isPositionIndependent ( )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoopsVerify ( ) ) ; addPass ( create<ISA_LIT>VSXCopyPass ( )


<s> goto xop_rotl ; case CODE_FOR_xop_rotlv16qi3 : new_icode = CODE_FOR_rotlv16qi3 ; xop_rotl : if ( CONST_INT_P ( op ) ) { int mask = GET_MODE_BITSIZE ( GET_MODE_INNER ( tmode ) ) - <NUM_LIT> ; op = GEN_INT ( INTVAL ( op ) & mask ) ; gcc_checking_assert ( insn_data [ icode ] . operand [ i + <NUM_LIT> ] . predicate ( op , mode ) ) ; } else { gcc_checking_assert ( nargs == <NUM_LIT> && insn_data [ new_icode ] . operand [ <NUM_LIT> ] . mode == tmode && insn_data [ new_icode ] . operand [ <NUM_LIT> ] . mode == tmode && insn_data [ new_icode ] . operand [ <NUM_LIT> ] . mode == mode && insn_data [ new_icode ] . operand [ <NUM_LIT> ] . predicate == insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate && insn_data [ new_icode ] . operand [ <NUM_LIT> ] . predicate == insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ; icode = new_icode ; goto non_constant ; } break ; default : gcc_unreachable ( ) ; } } } else { non_constant : if ( VECTOR_MODE_P ( mode ) ) op = safe_vector_operand ( op , mode ) ; if ( memory_operand ( op , mode ) ) num_memory ++ ; gcc_assert ( GET_MODE ( op ) == mode || GET_MODE ( op ) == VOIDmode ) ; if ( optimize || ! insn_data [ icode ] . operand [ i + adjust + <NUM_LIT> ] . predicate ( op , mode ) || num_memory > <NUM_LIT> ) op = force_reg ( mode , op ) ; } args [ i ] . op = op ; args [ i ] . mode = mode ; } switch ( nargs ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : if ( tf_p ) pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , GEN_INT ( ( int ) sub_code ) ) ; else if ( ! comparison_p ) pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args


<s> static <ISA_LIT>Operand * CreateFPImm ( double Val , SMLoc


<s> static Target The<ISA_LIT>BETarget ; return


<s> return StoreSpillOpcodesArray [ getSpillTarget


<s> } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset


<s> void \ sdata2_section ( ) \ { \ if ( in_section != in_sdata2 ) \ { \ in_section = in_sdata2 ; \ fprintf (

asm_out_file , <STR_LIT> , SDATA2_SECTION_ASM_OP ) ; \ } \ }


<s> Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode (


<s> const auto & ST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; const bool MinSize = ST . optForMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideIn<ISA_LIT>Mode ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBitfield ( unsigned LSB , unsigned Width , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_BitfieldDescriptor ) ; Op -> Bitfield . LSB = LSB ; Op -> Bitfield . Width = Width ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> inline vector unsigned short vec_vsubsuhs ( vector unsigned short a1


<s> fprintf ( stderr , <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( addr ) ; return ret


<s> constexpr aarch64_feature_flags get_flags ( T1 i , Ts ... args ) { return i ( ) . flag | get_flags ( args ...


<s> unsigned Opcode = Inst . getOpcode ( ) ; unsigned NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( OpNum - <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) { if ( inMicro<ISA_LIT>Mode ( ) && has<ISA_LIT>32r6 ( ) ) NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } Inst . setOpcode ( NewOpcode ) ; Out . EmitInstruction ( Inst


<s> case CortexA75 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize =


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { bool ClobbersEFLAGS = Orig . modifiesRegister ( <STR_LIT> , & TRI ) ; if ( ClobbersEFLAGS && MBB . computeRegisterLiveness ( & TRI , <STR_LIT> , I ) != MachineBasicBlock :: LQR_Dead ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig . getDebugLoc


<s> assert ( MI -> getOpcode ( ) == <STR_LIT> ) ; int count = <NUM_LIT> ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) count += <NUM_LIT> ; return


<s> int regsize = mep_reg_size ( i ) ; if ( ( i != TP_REGNO && i != GP_REGNO && i != LP_REGNO ) || mep_reg_set_in_function ( i ) ) really_need_stack_frame = true ; if ( cfun -> machine -> reg_save_slot [ i ] ) continue ; if ( regsize < <NUM_LIT> ) { cfun -> machine -> reg_save_size


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ; return getInstrPredicate ( MI , PredReg


<s> unsigned Lo32 = Lo_32 ( Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; auto getI64Imm = [ CurDAG , dl ] ( uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; InstCnt = <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ) ; InstCnt = <NUM_LIT> ; SDNode * Result = nullptr ; if ( ( LZ + FO + TZ ) > <NUM_LIT> ) { APInt SignedInt34 = APInt ( <NUM_LIT> , ( Imm >> TZ ) & <NUM_LIT> ) ; APInt Extended = SignedInt34 . sext ( <NUM_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI64Imm ( * Extended . getRawData ( ) ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( TZ ) , getI32Imm ( LZ ) ) ; } if ( ( LZ + TO ) > <NUM_LIT> ) { APInt SignedInt34 = APInt ( <NUM_LIT> , ( Imm >> ( <NUM_LIT> - LZ ) ) & <NUM_LIT> ) ; APInt Extended = SignedInt34 . sext ( <NUM_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI64Imm ( * Extended . getRawData (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : Type = ELF :: R_MIPS_32 ; break ; case FK_Data_8 : Type = ELF :: R_MIPS_64 ; break ; case FK_GPRel_4 : if ( isN64 ( ) ) { Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; } else Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF


<s> for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr * MI = & * I ; ++ I ; bool RemovedMI = false ; bool IsCopy = MI -> isCopy ( ) ; bool IsMoveImm = MI -> isMoveImmediate ( ) ; if ( IsCopy || IsMoveImm ) { MCPhysReg DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MCPhysReg SrcReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; int64_t SrcImm = IsMoveImm ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! MRI -> isReserved ( DefReg ) && ( ( IsCopy && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) || IsMoveImm ) ) { for ( RegImm & KnownReg : KnownRegs ) { if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister ( KnownRegs [ RI ] . Reg , TRI ) ) { std :: swap ( KnownRegs [ RI ] , KnownRegs [ KnownRegs . size ( ) - <NUM_LIT> ] ) ; KnownRegs . pop_back


<s> bool <ISA_LIT>DAGToDAGISel :: selectBITCAST_TO_LOHI ( SDNode * N ) { SDLoc Dl ( N ) ; auto VT = N -> getValueType ( <NUM_LIT> ) ; auto V = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasFPUv2DoubleFloat ( ) ) return false ; SDValue V1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , Dl , VT


<s> unsigned StoreSize = N -> getMemoryVT ( ) . getStoreSize ( ) ; if ( N -> getAlignment ( ) < StoreSize ) return false ; switch ( StoreSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : case <NUM_LIT> : return false ; case


<s> SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , Ty , <STR_LIT> ) ; SDValue MatAddr = DAG . getNode ( <STR_LIT> , DL , Ty , GA ) ; return MatAddr ; } if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return getTOCEntry ( DAG , SDLoc ( JT ) ,


<s> inline vector float vec_vminfp ( vector float a1 , vector float a2 ) { return ( vector float ) __builtin_altivec_vminfp ( ( vector float ) a1


<s> for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode ,


<s> bool isMemModeRegThumb ( ) const { if ( ! isMemory ( ) || ! getMemOffsetIsReg ( ) || getMemWriteback ( ) ) return false ; return true


<s> bool rs6000_must_pass_in_stack ( const function_arg_info & arg ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; } O << ( <NUM_LIT> >> RegNo


<s> return <ISA_LIT>Lowering -> SelectOptimalAddrMode ( Parent , N , Disp , Base , * CurDAG


<s> if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = std :: max ( ArgSize , MinSlotSize ) ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; VANext = DAG . getZExtOrTrunc ( VANext , DL , PtrMemVT ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) ) ; SDValue NarrowFP = DAG . getNode ( <STR_LIT> , DL , VT , WideFP . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Ops [ ] = { NarrowFP , WideFP . getValue ( <NUM_LIT>


<s> __vector signed int a , b , c ; a = ( __vector signed int ) vec_splats ( __m1 ) ; b = ( __vector signed int ) vec_splats ( __m2 ) ; c = vec_sub ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] - m2 . as_int [ <NUM_LIT> ] ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] - m2 . as_int [ <NUM_LIT> ] ; return ( __m64 )


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I ) ; Pos = CountTrailingZeros_64 ( I ) ; return true


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdDup , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdDup , <NUM_LIT> ) ) ; return


<s> bool flushCacheLineSWAP ( ) const { return


<s> return ( ( vec_double2 ) ( si_nand ( ( qword ) ( a ) , ( qword ) ( b


<s> const std :: string & <ISA_LIT>CA53ErratumStub :: name ( ) const { return m_Name


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA =


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( F . getParent ( ) -> getDataLayout ( ) ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ,


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { SDValue Address = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && ( Subtarget -> isTargetGlibc ( ) || Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) { case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT>


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode


<s> void <ISA_LIT>InstPrinter :: printAddress ( const MCAsmInfo * MAI , unsigned Base , const MCOperand & DispMO , unsigned Index , raw_ostream & O ) { printOperand ( DispMO , MAI , O ) ; if ( Base ||


<s> unsigned Index = I -> second . second & TB_INDEX_MASK ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; const MCInstrDesc & MCID = get ( Opc ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = getRegClass ( MCID , Index , & RI , MF ) ; unsigned NumDefs = MCID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; SDLoc dl ( N ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget

. isUnalignedMem16Slow ( ) ) return false ;


<s> llvm_unreachable ( <STR_LIT> ) ; case CSYNC : return


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> if ( Op . isReg ( ) ) { O << '%' << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << '$' << Op


<s> } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , TrueC -> getValueType ( <NUM_LIT> ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , <STR_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier =


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setHasCalls ( true ) ; SDValue TGA = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 , DAG ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , TGA ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , withTargetFlags ( Op , ldTF , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , Offset , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD , DAG ) ) ; } assert ( model == TLSModel :: LocalExec ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10


<s> if ( CALL_P ( insn ) ) return <STR_LIT> ; if ( JUMP_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC || GET_CODE ( PATTERN (

insn ) ) == ADDR_VEC ) ) return <STR_LIT> ;


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) . release ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = nullptr ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> ) ShiftTy = <STR_LIT> ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { SMLoc L = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; ShiftReg = tryParseRegister ( ) ; if ( ShiftReg == - <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return - <NUM_LIT> ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( ShiftReg && ShiftTy != <STR_LIT> ) Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedRegister ( ShiftTy , SrcReg , ShiftReg , Imm , S , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedImmediate ( ShiftTy , SrcReg , Imm , S , EndLoc ) ) ; return


<s> int arg_size = MMIX_FUNCTION_ARG_SIZE ( mode , type ) ; argsp -> regs = ( ( targetm . calls . must_pass_in_stack ( mode , type ) || ( arg_size > <NUM_LIT> && ! TARGET_LIBFUNC && ! argsp -> lib ) ) ? ( MMIX_MAX_ARGS_IN_REGS )

+ <NUM_LIT> : argsp -> regs + ( <NUM_LIT> + arg_size ) / <NUM_LIT> ) ;


<s> case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_IMM18_BY4 : case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TLSLE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSIE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD : return


<s> sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; } gcc_assert ( SPARC_SYMBOL_REF_TLS_P ( sym ) ) ; sym = legitimize_tls_address ( sym ) ; if ( addend ) { sym = gen_rtx_PLUS ( mode , sym , addend ) ; sym = force_operand ( sym , operands [ <NUM_LIT> ] ) ; } operands [ <NUM_LIT> ] = sym ; } if ( flag_pic && CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( pic_address_needs_scratch ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && mode == SImode ) { emit_insn ( gen_movsi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && mode == DImode ) { gcc_assert ( TARGET_ARCH64 ) ; emit_insn ( gen_movdi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , ( reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && const_zero_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; if ( REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG && ( mode == SFmode || ( mode == DFmode && ( reload_completed || reload_in_progress ) ) ) ) return false ; operands [ <NUM_LIT> ] = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ; if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = validize_mem ( operands [ <NUM_LIT> ] ) ; return false ; } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; switch ( mode ) { case QImode : break ; case HImode : case SImode


<s> assert ( V1 . getSimpleValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; auto matchAsInsertPS = [ & ] ( SDValue VA , SDValue VB , ArrayRef < int > CandidateMask ) { unsigned ZMask = <NUM_LIT> ; int VADstIndex = - <NUM_LIT> ; int VBDstIndex = - <NUM_LIT> ; bool VAUsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == CandidateMask [ i ] ) { VAUsedInPlace = true ; continue ; } if ( VADstIndex >= <NUM_LIT> || VBDstIndex >= <NUM_LIT> ) return false ; if ( CandidateMask [ i ] < <NUM_LIT> ) { VADstIndex = i ; } else { VBDstIndex =


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Node ) ; SDValue Upper = CurDAG -> getConstant ( UpperVal , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper


<s> if ( & I != G -> getKill ( ) ) { MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; bool Change = TransformAll || getColor ( MO . getReg ( ) ) != C ; if ( G -> requiresFixup ( ) && & I == G -> getLast ( ) ) Change = false ; if ( Change ) { Substs [ MO . getReg ( ) ] = Reg ; MO . setReg ( Reg ) ; Changed = true ; } } } assert ( Substs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( G -> getKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } return


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: Tail : case CallingConv :: Fast : return true


<s> inline vector unsigned char vec_vsububm ( vector unsigned char a1 , vector unsigned char a2 ) { return ( vector unsigned char ) __builtin_altivec_vsububm ( ( vector signed char


<s> if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetKFreeBSD ( ) || isTargetNaCl ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit ) PreferVectorWidth = <NUM_LIT> ; else if ( Prefer256Bit )


<s> else size = GET_MODE_SIZE ( arg . mode ) ; bytes_left = ( <NUM_LIT> * <NUM_LIT> ) - ( ( * cum - <NUM_LIT> ) * <NUM_LIT> ) ; if ( size > bytes_left ) return


<s> case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization ,


<s> vqdmulh_n_s16 ( int16x4_t a , int16_t b ) { int16x4_t result


<s> struct sigcontext * sc ; } * frame_ = ( struct sigframe * ) context -> psp ; struct sigcontext * sc = frame_ -> sc ; { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; } context -> fpsr_loc = & ( sc -> sc_ar_fpsr ) ; context -> pfs_loc = & ( sc -> sc_ar_pfs ) ; context -> lc_loc = & ( sc -> sc_ar_lc ) ; context -> unat_loc = & ( sc -> sc_ar_unat ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> br_loc [ <NUM_LIT> ] = & (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSizeInsEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo - <NUM_LIT> ) . isImm ( ) ) ; assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Position = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) , Fixups


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . is256BitVector ( ) && SubVecVT . is128BitVector ( ) ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( SubVec2 . getNode ( ) && SubVec2 . getOpcode ( ) == <STR_LIT> ) SubVec2 = SubVec2 . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( SubVec2 ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment (


<s> if ( fitsRegularPattern < int > ( Begin + <NUM_LIT> , <NUM_LIT> , End , <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Begin + <NUM_LIT> , <NUM_LIT> , End , Indices . size ( ) , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else return SDValue (


__index , void const * __addr , int __scale ) {


<s> uint64_t SplatUndefZ = SplatUndef . getZExtValue ( ) ; uint64_t Lower = ( SplatUndefZ & ( ( uint64_t ( <NUM_LIT> ) << findFirstSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Upper = ( SplatUndefZ & ~ ( ( uint64_t ( <NUM_LIT> ) << findLastSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Value = SplatBitsZ | Upper | Lower ; SDValue Op = tryBuildVectorReplicate ( DAG , TII , DL , VT , Value , SplatBitSize ) ; if ( Op . getNode ( ) ) return Op ; uint64_t Middle = SplatUndefZ & ~ Upper & ~ Lower ; Value = SplatBitsZ | Middle ; Op = tryBuildVectorReplicate ( DAG , TII , DL , VT , Value , SplatBitSize ) ; if ( Op . getNode ( ) ) return


<s> uint64_t Base = Imm >> <NUM_LIT> ; uint64_t Disp = Imm & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp <<


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const { return Subtarget -> isTargetNaCl (


<s> MI = Front . pop_back_val ( ) ; if ( Reached . find ( MI ) != Reached . end ( ) ) continue ; Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { Register Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) { continue ; } MachineInstr * NewMI = MRI -> getVRegDef ( Reg ) ; if ( ! NewMI ) continue ; Front . push_back ( NewMI


<s> if ( Subtarget -> isTargetMachO ( ) && TM . getCodeModel ( ) == CodeModel :: Large ) { unsigned Opc1 = Is64Bit ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc1 ) , TmpReg ) . addImm ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; return ResultReg ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit


<s> if ( ! isAM5 && Offset == Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( Offset == - Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( ! isAM5 && Offset == - Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else return false ; } MBB . erase ( MergeInstr ) ; <STR_LIT> AddSub = Offset < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; bool isLd = isLoadSingle ( Opcode ) ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) . cloneMemRefs ( * MI ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . cloneMemRefs ( * MI ) ; } else { int Imm = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Imm ) . add ( predOps ( Pred , PredReg ) ) . cloneMemRefs ( * MI ) ; } } else


<s> BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get (


<s> static __inline qword si_ceqbi ( qword a , signed char b ) { return ( ( qword ) ( vec_cmpeq ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModeImm12OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Reg , Imm12 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else


<s> return DAG . getRegister ( FI -> getGlobalBaseReg ( ) ,


<s> ImmutableCallSite :: arg_iterator CalleeArgEnd = CS . arg_end ( ) ; Function :: const_arg_iterator CallerArgIter = CallerFn -> arg_begin ( ) ; for ( ; CalleeArgIter != CalleeArgEnd ; ++ CalleeArgIter , ++ CallerArgIter ) { const Value * CalleeArg = * CalleeArgIter ; const Value * CallerArg = & ( * CallerArgIter ) ; if ( CalleeArg == CallerArg ) continue ; if ( CalleeArg -> getType ( ) == CallerArg -> getType ( ) && isa < UndefValue > ( CalleeArg ) ) continue ; return


<s> for ( unsigned Pos = NumTZ + <NUM_LIT> ; Pos <= <NUM_LIT> ; ++ Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == <NUM_LIT> ; if ( T ) VPTStates . push_back ( <STR_LIT> ) ; else VPTStates . push_back ( <STR_LIT> ) ; } VPTStates . push_back


<s> default : break ; case 'd' : case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'a' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f'


<s> case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N


<s> if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == VOIDmode ) return CONST_DOUBLE_HIGH ( x ) ; if ( GET_CODE ( x ) == CONST_DOUBLE ) { if ( GET_MODE ( x ) == DFmode ) { long bits [ <NUM_LIT> ] ; REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , bits ) ; return ( ( uint64_t ) ( unsigned long ) bits [ <NUM_LIT> ] << ( uint64_t ) <NUM_LIT> ) | ( uint64_t

) ( unsigned long ) bits [ <NUM_LIT> ] ;


<s> EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV =


<s> static __inline int __attribute__ ( ( __always_inline__ ) )


<s> PrivateLabelPrefix = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> return ( MI . getNumOperands ( ) > <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg

( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> GeneralShuffle GS ( VT ) ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { int Elt = VSN -> getMaskElt ( I ) ; if ( Elt < <NUM_LIT> ) GS . addUndef ( ) ; else GS . add ( Op . getOperand ( unsigned ( Elt ) / NumElements ) , unsigned ( Elt ) % NumElements ) ; } return GS . getNode ( DAG , SDLoc ( VSN


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( )


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ; OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize / Scale


<s> Offset *= NumMaskElts ; } if ( llvm :: all_of ( Offsets , [ ] ( unsigned Offset ) { return Offset == <NUM_LIT> ; } ) ) return SDValue ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( SDValue & NewInput : WideInputs ) { assert ( ( WideSizeInBits % NewInput . getValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( WideSizeInBits > NewInput . getValueSizeInBits ( ) ) NewInput = widenSubVector ( NewInput , false , Subtarget , DAG , SDLoc ( NewInput ) , WideSizeInBits ) ; assert ( WideSizeInBits == NewInput . getValueSizeInBits ( ) && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts ] ; } WideMask . append ( ( Scale - <NUM_LIT> ) * NumMaskElts , SM_SentinelUndef ) ; resolveTargetShuffleInputsAndMask ( WideInputs , WideMask ) ; assert ( ! WideInputs . empty ( ) && <STR_LIT> ) ; if ( WideInputs . size ( ) > <NUM_LIT> ) return SDValue ( ) ; Depth += count_if ( Offsets , [ ] ( unsigned Offset ) { return Offset > <NUM_LIT> ; } ) ; SDValue WideRoot = WideInputs


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getTestBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; return


<s> static DecodeStatus DecodeLoadCP ( MCInst & Inst , unsigned insn , uint64_t Address , const


<s> void IncomingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt || VA

. getLocInfo ( ) == CCValAssign :: AExt ) {


<s> SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) . hasFnAttribute ( Attribute ::

NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ;


<s> if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - <NUM_LIT> ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - <NUM_LIT> ; } else regno = - <NUM_LIT> ; if ( class == GENERAL_REGS || class == BASE_REGS || ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || FP_REGNO_P ( regno ) ) && ( class == FLOAT_REGS || class == NON_SPECIAL_REGS ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || ALTIVEC_REGNO_P ( regno ) ) &&

class == ALTIVEC_REGS ) return NO_REGS ;


<s> static bool arm_cookie_has_size ( void ) { return TARGET_AAPCS_BASED


<s> LLVMContext * Context = DAG . getContext ( ) ; std :: vector < Constant * > CV0 ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Constant * C0 = ConstantVector :: get ( CV0 ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context ,


<s> OperandMatchResultTy parseADDR64 ( OperandVector & Operands


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT8 ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT16 ) ; } for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth == <NUM_LIT> ) { EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MBBSymbolExpr ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; continue ; } const MCExpr * Expr = MCBinaryExpr :: CreateSub ( MBBSymbolExpr , MCSymbolRefExpr :: Create ( JTISymbol , OutContext ) , OutContext ) ; Expr = MCBinaryExpr :: CreateDiv ( Expr , MCConstantExpr ::

Create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> return IsRegInClass ( Reg , & <STR_LIT> ,


<s> if ( TARGET_AVX512ER ) { emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP28 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x0 ) ) ) ; return ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , e0