<s> if ( ! findMoreOptimalIndexType ( MGS , BasePtr , Index , DAG ) ) return SDValue ( ) ; if ( auto * MGT = dyn_cast < MaskedGatherSDNode > ( MGS ) ) { SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Ops [ ] = { Chain , PassThru , Mask , BasePtr , Index , Scale } ; return DAG . getMaskedGather ( DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) , MGT -> getMemoryVT ( ) , DL , Ops , MGT -> getMemOperand ( ) , IndexType , MGT -> getExtensionType ( ) ) ; } auto * MSC = cast < MaskedScatterSDNode > ( MGS ) ; SDValue Data = MSC -> getValue ( ) ; SDValue Ops [ ] = { Chain , Data , Mask , BasePtr , Index , Scale } ; return DAG . getMaskedScatter ( DAG . getVTList ( <STR_LIT> ) , MSC -> getMemoryVT ( ) , DL , Ops , MSC

-> getMemOperand ( ) , IndexType , MSC -> isTruncatingStore ( ) ) ;


<s> if ( IsTailCall ) return false ; CodeModel :: Model CM = TM . getCodeModel ( ) ; if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) return false ; if ( CM == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; MachineInstrBuilder MIB ; if ( CM == CodeModel :: Small


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get


<s> if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) == <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) +


<s> F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; MachineInstr * LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ; if ( ! LastEFLAGSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastEFLAGSUser , BB , TRI ) ) { copy0MBB -> addLiveIn ( <STR_LIT> ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; } sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; if ( CascadedCMOV ) { BB -> addSuccessor ( jcc1MBB ) ; jcc1MBB -> addSuccessor ( copy0MBB ) ; jcc1MBB -> addSuccessor ( sinkMBB ) ; } else { BB -> addSuccessor ( copy0MBB ) ; } BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( sinkMBB ) ; } copy0MBB -> addSuccessor ( sinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = sinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB


<s> for ( unsigned i = <NUM_LIT> , e = BI -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ BI -> getSuccessor ( i ) ] ) ; return


<s> return ( __m128i ) __builtin_ia32_loaddquqi128_mask ( ( const char * ) __P , (


<s> static rtx mips_unspec_call ( rtx reg , rtx symbol ) { rtvec


<s> if ( ( lsb & shift_mask ) == <NUM_LIT> ) return <NUM_LIT> ; return c == - lsb && lsb != <NUM_LIT> ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == <NUM_LIT> ) { shift_mask_high = ~ <NUM_LIT> ; if ( INTVAL ( shiftop ) > <NUM_LIT> ) shift_mask_high <<= INTVAL ( shiftop ) - <NUM_LIT> ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == <NUM_LIT> ) return <NUM_LIT> ; return high == -


<s> bool isDecl = GV -> isDeclaration ( ) && ! GV -> hasNotBeenReadFromBitcode ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ; return RelocM != Reloc :: Static && ( isDecl || GV ->


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL ,


<s> static void aarch64_init_simd_builtin_types ( void ) { int i ; int nelts = sizeof ( aarch64_simd_types ) / sizeof ( aarch64_simd_types [ <NUM_LIT> ] ) ; tree tdecl ; aarch64_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; aarch64_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; aarch64_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; aarch64_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; aarch64_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; aarch64_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; aarch64_simd_types [ Int64x1_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint64x1_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Poly8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype = build_distinct_type_copy ( unsigned_intQI_type_node ) ; aarch64_simd_types [ Poly16_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype = build_distinct_type_copy ( unsigned_intHI_type_node ) ; aarch64_simd_types [ Poly64_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype = build_distinct_type_copy ( unsigned_intDI_type_node ) ; aarch64_simd_types [ Poly128_t ] . eltype = aarch64_simd_types [ Poly128_t ] . itype = build_distinct_type_copy ( unsigned_intTI_type_node ) ; aarch64_simd_types [ Poly8x8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly8x16_t ] . eltype =


<s> static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse ( MachineRegisterInfo * MRI ) { for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if ( ! MRI -> reg_nodbg_empty ( reg ) ) return false ; for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if ( ! MRI -> reg_nodbg_empty ( reg )


<s> O << <STR_LIT> << JTI ; <ISA_LIT>ConstantPoolValue :: print (


<s> <ISA_LIT>ABIInfo ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getABI ( ) ; <ISA_LIT>PtrClass PtrClassKind = static_cast < <ISA_LIT>PtrClass > ( Kind ) ; switch ( PtrClassKind ) { case <STR_LIT> : return ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; case


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( CPU . empty ( ) ) CPU = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS


<s> Chunk = ( Chunk << <NUM_LIT> ) | ( Chunk << <NUM_LIT> ) | ( Chunk << <NUM_LIT> ) | Chunk ; return <STR_LIT> ( Chunk , <NUM_LIT> ,


<s> PromoteTree ( Visited , Sources , Sinks , SafeToPromote ) ; TruncateSinks ( Sources , Sinks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) ; for ( auto * V : Sources ) V -> dump ( ) ; for ( auto * I : NewInsts ) I -> dump ( ) ; for ( auto * V : Visited ) { if ( ! Sources . count ( V ) ) V -> dump ( ) ; } )


<s> if ( LABEL_REF_P ( x ) || ! ( decl = SYMBOL_REF_DECL


<s> if ( <ISA_LIT>EarlyIfConv && Subtarget . hasCMov ( ) ) PC -> enablePass ( & EarlyIfConverterID ) ; return


<s> if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) return SYMBOL_FORCE_TO_MEM ; if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE


<s> case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCode ( SMLoc L ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser .


<s> static void register_svpattern ( ) { auto_vec < string_int_pair , <NUM_LIT> > values ; values . quick_push ( string_int_pair ( <STR_LIT> # UPPER , VALUE


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps


<s> assert ( N0 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Subtarget . hasAVX512 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( ( double ) ( <NUM_LIT> << <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0


<s> unsigned offset = getMachineOpValue ( MI , MI . getOperand ( <NUM_LIT> ) ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( base << <NUM_LIT> ) | ( src << <NUM_LIT> ) | ( offset & <NUM_LIT> ) ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( base << <NUM_LIT> ) | ( src << <NUM_LIT>

) | ( ( offset + <NUM_LIT> ) & <NUM_LIT> ) ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; Register DestReg = MI . getOperand ( <NUM_LIT> )


<s> if ( TheTriple . isMIPS64 ( ) && ! ABI . IsN32 ( ) ) CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; if ( ABI . IsO32 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; else if ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = PrivateGlobalPrefix ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> if ( MO . getReg ( ) == <NUM_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> << getRegisterName (


<s> break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It


<s> if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> return ( __m128i ) __builtin_ia32_vpconflictdi_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_di ( )


<s> bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast


<s> switch ( code ) { case CONST_INT : if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) < <NUM_LIT> ) * total = <NUM_LIT> ; else if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) < <NUM_LIT> ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case SYMBOL_REF


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> void printf64mem ( const MCInst * MI , unsigned OpNo ) { printMemReference ( MI , OpNo )


<s> return ( in ? <NUM_LIT> : <NUM_LIT> ) + REGISTER_MOVE_COST ( mode ,


<s> ModulePass * llvm :: create<ISA_LIT>Os16Pass (


<s> MCContext & Context = getContext ( ) ; const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Context , Loc ) ; const MCBinaryExpr * CapExpr = MCBinaryExpr :: createAdd ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_CHERI_CAP , SRE , Context


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo


<s> bool <ISA_LIT>RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg ,

const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const {


<s> <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned SP = <STR_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML ,


<s> return ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks (


<s> int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) if ( MO . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> if ( AluIter -> getNumOperands ( ) != <NUM_LIT> ) return false ; MachineOperand & Dest = AluIter -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op1 = AluIter -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op2 = AluIter -> getOperand ( <NUM_LIT> ) ; if ( ! isSameOperand ( Dest , Base ) || ! isSameOperand ( Dest , Op1 ) ) return false ; if ( Op2 . isImm ( ) ) { if ( Offset . isReg ( ) && Offset . getReg ( ) == <STR_LIT> ) return true ; if ( Offset . isImm ( ) && ( ( Offset . getImm ( ) == <NUM_LIT> && ( ( IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) || ( ! IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) ) ) || Offset . getImm ( ) == Op2 . getImm ( ) ) ) return true ; } else if ( Op2 . isReg ( ) ) { if ( Offset . isReg ( ) && Op2 . getReg ( ) == Offset . getReg ( ) ) return true ; } else return


<s> rtx tmp = addr ; if ( GET_CODE ( tmp ) == SYMBOL_REF || GET_CODE ( tmp ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( tmp ) ==


<s> SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) .


<s> if ( type_suffix ( <NUM_LIT> ) . tclass == TYPE_bool ) { gcc_assert ( pred == PRED_z && code_for_uint == code_for_sint ) ; return use_exact_insn ( code_for_aarch64_pred_z ( code , mode ) ) ; } if ( pred == PRED_x ) { if ( type_suffix ( <NUM_LIT> ) . integer_p ) icode = maybe_code_for_aarch64_pred ( code , mode ) ; else icode = maybe_code_for_aarch64_pred ( unspec_for_fp , mode ) ; if ( icode != CODE_FOR_nothing ) return use_pred_x_insn ( icode ) ; } if ( pred == PRED_none || pred == PRED_x ) { icode = direct_optab_handler ( code_to_optab ( code ) , <NUM_LIT> ) ; if ( icode == CODE_FOR_nothing ) icode = code_for_aarch64_sve ( code , mode ) ; return use_unpred_insn (


<s> int i ; if ( cpu_table == NULL ) goto not_found ; for ( i = <NUM_LIT> ; cpu_table [ i ] . part_no != NULL ; i ++ ) if ( strstr ( buf , cpu_table [ i ] . part_no ) != NULL ) { val = arch ? cpu_table [ i ] . arch_name : cpu_table [ i ] . cpu_name ; break ; } break ; } } if ( val ) { fclose ( f ) ; return concat ( <STR_LIT> , argv [ <NUM_LIT> ] , <STR_LIT> , val , NULL ) ; } not_found : { unsigned int i ; unsigned int opt ; const char * search [ ] = { NULL , <STR_LIT> } ; if ( f ) fclose ( f ) ; search [ <NUM_LIT> ] = argv [ <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { isTailCall = false ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs


<s> return __builtin_aarch64_urshr_nv2si_uus ( __a ,


<s> if ( Subtarget -> isTargetNaCl ( ) ) { FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; } else { FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; } assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = Has64BitPointers ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O <<


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc (


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MachineOperandType MOTy , unsigned Offset ) const { MCSymbolRefExpr :: VariantKind Kind ; const MCSymbol * Symbol ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_None ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO


<s> SDValue NewBase = OldBase ; SDValue NewOffset = OldOffset ; const bool IsRegImm = SelectAddrModeIndexedSVE < - <NUM_LIT> , <NUM_LIT> > ( N , OldBase , NewBase , NewOffset ) ; const bool IsRegReg = ! IsRegImm && SelectSVERegRegAddrMode ( OldBase


<s> if ( rs >= <NUM_LIT> ) break ; for ( re = rs + <NUM_LIT> ; re < <NUM_LIT> && ! call_used_regs [ PR_REG ( re ) ] ; re ++ ) continue ; if ( out_state == <NUM_LIT> ) { fputs ( <STR_LIT> , asm_out_file ) ; out_state =


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getMemExtendOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned SignExtend = MI . getOperand ( OpIdx ) . getImm ( ) ; unsigned DoShift = MI . getOperand ( OpIdx + <NUM_LIT>


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI -> hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent (


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX2 ( )


<s> return ( ( vec_double2 ) ( si_rotqmby ( ( qword ) ( a ) , si_from_int ( count ) )


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { gcc_assert ( sparc_leaf_function_p == current_function_uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file )


<s> case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> )


<s> EVT SrcVecVT = ExtElt . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned VecWidth = SrcVecVT . getSizeInBits ( ) ; unsigned NumElts = VecWidth / DestWidth ; EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , NumElts ) ; SDValue BitcastVec = DAG . getBitcast ( BitcastVT , ExtElt . getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; SDValue NewExtElt = DAG . getNode ( <STR_LIT> , DL , TruncVT , BitcastVec , ExtElt . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( N -> getOpcode ( ) , DL , N

-> getValueType ( <NUM_LIT> ) , NewExtElt ) ;


<s> if ( ! isBrAnalysisUnpredicatedTerminator ( I , * this ) ) break ; if ( ! I -> getDesc ( ) . isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } while ( next ( I ) != MBB . end ( ) ) next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty


<s> t = __ev_mwhsmf ( a , b ) ; return __ev_mwsmiaa ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> }


<s> initializeMVELaneInterleavingPass ( * PassRegistry ::


<s> return DAG . getStore ( SD -> getChain ( ) , SDLoc ( SD ) , Tr , SD -> getBasePtr ( ) , SD -> getPointerInfo ( ) , SD

-> getAlignment ( ) , SD -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> static bool areCFlagsAliveInSuccessors ( const MachineBasicBlock * MBB ) { for ( auto * BB : MBB -> successors ( ) ) if ( BB -> isLiveIn ( <STR_LIT> ) ) return true ; return false


<s> } break ; } while ( Itr != PredMBB -> begin ( ) && Itr -> isTerminator ( ) ) ; if ( KnownRegs . empty ( ) ) return false ; bool Changed = false ; SmallSetVector < unsigned , <NUM_LIT> > UsedKnownRegs ; MachineBasicBlock :: iterator LastChange = MBB -> begin ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr * MI = & * I ; ++ I ; bool RemovedMI = false ; bool IsCopy = MI -> isCopy ( ) ; bool IsMoveImm = MI -> isMoveImmediate ( ) ; if ( IsCopy || IsMoveImm ) { MCPhysReg DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MCPhysReg SrcReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; int64_t SrcImm = IsMoveImm ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! MRI -> isReserved ( DefReg ) && ( ( IsCopy && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) || IsMoveImm ) ) { for ( RegImm & KnownReg : KnownRegs ) { if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister ( KnownRegs [ RI ] . Reg , TRI ) ) { std :: swap ( KnownRegs [ RI ] , KnownRegs [ KnownRegs . size ( ) - <NUM_LIT> ] ) ; KnownRegs . pop_back ( ) ; } else


<s> unsigned CmpOpcode = Ty -> isFPOrFPVectorTy ( ) ? Instruction :: FCmp : Instruction :: ICmp ; LegalizationCost = getCmpSelInstrCost ( CmpOpcode , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) + getCmpSelInstrCost ( Instruction :: Select , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; LegalizationCost *= LT . first - <NUM_LIT> ; } return LegalizationCost +


<s> else if ( ! ( SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) ) assert ( false && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS <<


<s> if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ResultReg ; } return <NUM_LIT>


<s> auto UsesNarrowValue = [ ] ( Value * V ) { return V -> getType ( ) -> getScalarSizeInBits ( ) == <ISA_LIT>CodeGenPrepare :: TypeSize ; } ; if ( auto * Store = dyn_cast < StoreInst > ( V ) ) return UsesNarrowValue ( Store -> getValueOperand ( ) ) ; if ( auto * Return = dyn_cast < ReturnInst > ( V ) ) return UsesNarrowValue ( Return -> getReturnValue ( ) ) ; if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return UsesNarrowValue ( Trunc -> getOperand ( <NUM_LIT> ) ) ; if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) return

UsesNarrowValue ( ZExt -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) return ; BuildMI ( MBB , MBB . begin ( ) , MBB . findDebugLoc ( MBB . begin (

) ) , TII -> get ( <STR_LIT> ) ) . addImm ( HintNum ) ;


<s> extern __inline __m128d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmpge_sd ( __m128d __A , __m128d __B ) { __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmpge ( a , b ) ; return ( __m128d ) _mm_setr_pd ( c [ <NUM_LIT> ]


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge && ! get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) addPass ( createGlobalMergePass (


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned thisSubRegIdx = ( <STR_LIT> . contains ( Reg ) ? <STR_LIT> : <STR_LIT> ) ; unsigned otherSubRegIdx = ( thisSubRegIdx == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned GR64BitReg = TRI -> getMatchingSuperReg ( Reg , thisSubRegIdx , & <STR_LIT> ) ; Register OtherReg = TRI -> getSubReg ( GR64BitReg , otherSubRegIdx ) ; if ( LiveRegs . contains ( OtherReg ) ) return false ; uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <STR_LIT> ( Imm ) ) { MI . setDesc ( TII -> get ( LLIxL ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ( Reg ) ) ; return true ; } if ( <STR_LIT> ( Imm ) ) { MI . setDesc ( TII -> get ( LLIxH ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ( Reg ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( Imm >> <NUM_LIT> ) ; return true ; } return false


<s> case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: Fast : return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS_GHC ) ; case CallingConv :: PreserveMost : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: Mono : if ( Return ) { return CCAssignFnForNode ( CallingConv :: C , true , isVarArg ) ; } else


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS )


<s> const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind


<s> if ( ! Subtarget . hasVLX ( ) ) return ; Register XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { Register XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI


<s> unsigned Cost = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Ty -> getVectorNumElements ( ) ; i < e ; ++ i ) { if ( Insert ) Cost += TopTTI -> getVectorInstrCost ( Instruction :: InsertElement , Ty , i ) ; if ( Extract ) Cost += TopTTI -> getVectorInstrCost ( Instruction :: ExtractElement , Ty , i ) ; } return


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) ; addFrameReference ( MIB , FrameIx , <NUM_LIT> , false ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & * MIB


<s> unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( ! Subtarget -> hasAVX ( ) ) return false ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || NumElts != <NUM_LIT> ) return false ; int LaneSize = NumElts / NumLanes ; for ( int i = <NUM_LIT> ; i < LaneSize ; ++ i ) { int HighElt = i + LaneSize ; bool HighValid = isUndefOrInRange ( Mask [ HighElt ] , LaneSize , NumElts ) ; bool LowValid = isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , LaneSize ) ; if ( ! HighValid || ! LowValid ) return false ; if ( Mask [ i ] < <NUM_LIT> || Mask [ HighElt ] <


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return


<s> case <STR_LIT> : return true ; } return false


<s> if ( ! Outs . empty ( ) && Caller . hasStructRetAttr ( ) != Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ) return false ; for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry


<s> else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc ( CCmode ) ; else * op0 = gen_rtx_REG ( CCmode , FPSW_REGNUM ) ; } * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_op0 ,


<s> bool <ISA_LIT>FastISel :: emitICmp ( MVT RetVT , const Value * LHS , const Value * RHS , bool IsZExt ) { return emitSub ( RetVT , LHS , RHS , true , false , IsZExt


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y


<s> if ( VTy -> getElementType ( ) == Type :: getInt64Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt32Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt16Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get


<s> ReductionList Reductions = MatchReductions ( F , L , Header ) ; for ( auto & R : Reductions ) { ParallelMACList MACCandidates = MatchParallelMACs ( R ) ; if ( ! SetMemoryLocations ( MACCandidates ) ) continue ; R . MACCandidates = MACCandidates ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto & M : R . MACCandidates


<s> if ( TARGET_LINUX_ABI ) init_sync_libfuncs ( UNITS_PER_WORD )


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_BitfieldDescriptor ) ; Op -> Bitfield . LSB = LSB ; Op -> Bitfield .


<s> if ( IsTailPredicationLegal ( ) ) return TPNumElements ; return isDo ( Start ) ? Start -> getOperand ( <NUM_LIT> ) : Start -> getOperand (


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF .


<s> unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ; if ( Flags . isByVal ( ) )


<s> void EmitByte ( uint8_t C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ; ++ CurByte


<s> std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor (


<s> bool emulate<ISA_LIT>LD ( LinkerScript & pScript , LinkerConfig & pConfig ) { if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } return MCLDEmulate<ISA_LIT>ELF ( pScript


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> &&


<s> if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : if ( ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveCode ( StringRef IDVal , SMLoc L ) { if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT>


<s> K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB ) ; if ( Changed && ! ReturnMBB


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return *


<s> } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> ) , DAG . getConstant ( End , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> <ISA_LIT>GOTEntry * <ISA_LIT>GOT :: createGOT ( ) { <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry ( <NUM_LIT> , NULL ) ; m_GOT . push_back (


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFP128Ty ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF .

getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ;


<s> if ( MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return true ; } return


<s> uint64_t <ISA_LIT>GOT :: getGPDispAddress ( ) const { return addr ( ) + <ISA_LIT>GOTGpOffset


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { assert ( CC != CallingConv :: GHC && <STR_LIT> ) ; return


<s> int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && FrameIndex == RS -> getScavengingFrameIndex ( ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> HOST_WIDE_INT mips_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = <NUM_LIT>


<s> static rtx aarch64_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src )


<s> } if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( Op . type == TYPE_XMM128 || Op . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case ENCODING_RB : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RW : if ( readOpcodeRegister ( insn , <NUM_LIT> ) )


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> ParseSubtargetFeatures ( CPUName , FS ) ; PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( TT . find ( <STR_LIT> ) == std :: string


<s> return ImplicitItMode == ImplicitItModeTy :: Always || ImplicitItMode == ImplicitItModeTy


<s> void <ISA_LIT>CCState :: PreAnalyzeCallOperand ( const Type * ArgTy , bool IsFixed , const char * Func ) { OriginalArgWasF128 . push_back ( originalTypeIsF128 ( ArgTy , Func


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val


<s> static <ISA_LIT>Operand * CreateRotImm ( unsigned Imm , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_RotateImmediate


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return getThumbInstruction (

MI , Size , Bytes , Address , OS , CS ) ;


<s> assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef ( ) ) if ( SDValue Rotate = lowerShuffleAsBitRotate ( DL , <STR_LIT> , V1 , Mask


<s> if ( ! isPowerOf2_32 ( RegSz * MemSz * NumElems ) ) return SDValue ( ) ; MVT SclrLoadTy = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) == MemSz ) { SclrLoadTy = Tp ; break ; } } if ( SclrLoadTy . getSizeInBits ( ) != MemSz ) return SDValue ( ) ; EVT LoadUnitVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclrLoadTy , RegSz / SclrLoadTy . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , RegSz / MemVT . getScalarType ( ) . getSizeInBits ( ) ) ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; SDValue ScalarInVector = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT


<s> if ( TrueVal == <NUM_LIT> ) C . CCMask ^= C . CCValid ; SDValue Result = emitSETCC ( DAG , DL , Glue , C . CCValid , C . CCMask ) ; EVT VT = Op . getValueType ( ) ; if ( ! is32Bit ( VT ) ) Result = DAG . getNode ( <STR_LIT> , DL , VT , Result ) ; SDValue ShAmt = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , Result , ShAmt ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Shl , ShAmt ) ; } } SDValue Ops [ ] = { TrueOp , FalseOp , DAG . getConstant ( C . CCValid , <STR_LIT> ) , DAG . getConstant ( C . CCMask , <STR_LIT> ) , Glue } ; SDVTList VTs = DAG . getVTList ( Op . getValueType


<s> void <ISA_LIT>CodeEmitter :: addPCLabel ( unsigned LabelID ) { DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << '\n' ; JTI -> addPCLabelAddr ( LabelID , MCE . getCurrentPCValue (


<s> return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerIS_FPCLASS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT ResultVT = Op . getSimpleValueType ( ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; auto CNode = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; unsigned Check = CNode -> getZExtValue ( ) ; unsigned TDCMask = <NUM_LIT> ; if ( Check & fcSNan ) TDCMask |= <STR_LIT> | <STR_LIT> ; if ( Check & fcQNan ) TDCMask |= <STR_LIT> | <STR_LIT> ; if ( Check & fcPosInf ) TDCMask |= <STR_LIT> ; if ( Check & fcNegInf ) TDCMask |= <STR_LIT> ; if ( Check & fcPosNormal ) TDCMask |= <STR_LIT> ; if ( Check & fcNegNormal ) TDCMask |= <STR_LIT> ; if ( Check & fcPosSubnormal ) TDCMask |= <STR_LIT> ; if ( Check & fcNegSubnormal ) TDCMask


, __mmask16 mask , void * addr , int scale , int hint ) {


<s> const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( )


<s> case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; } return Imm


<s> if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; rtx src = SET_SRC ( pattern ) ; rtx sel = GET_CODE ( src ) == VEC_DUPLICATE ? XEXP ( src , <NUM_LIT> ) : src ; rtx par = XEXP ( sel , <NUM_LIT> ) ; int half_elts = GET_MODE_NUNITS ( GET_MODE ( XEXP ( sel , <NUM_LIT> ) ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) ; lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ; INSN_CODE ( insn ) = -


<s> if ( ( VT == <STR_LIT> && OpVT == <STR_LIT> ) || ( VT == <STR_LIT> && OpVT == <STR_LIT> ) ) { unsigned NumElems = OpVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; i ++ ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , ShufMask1 . data ( ) ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; i ++ ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , ShufMask2 . data ( ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ; } return SDValue (


<s> unsigned int mips_case_values_threshold ( void ) { if ( TARGET_MIPS16 && optimize_size ) return


<s> void EmitARM64WinCFISaveFReg ( unsigned Reg , int


<s> <ISA_LIT>ELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer


<s> __builtin_neon_vst1_lanev2di ( ( __builtin_neon_di * ) __a ,


<s> SMLoc TypeLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * Val = nullptr ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . OpDecl ) { Error ( Start , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT>


<s> SDValue Op1 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; } SDValue IntOp = DAG . getNode ( IntOpcode , dl , IntVT , Op0 , Op1 ) ; return DAG . getBitcast ( VT , IntOp ) ; } return SDValue (


<s> } TII = ( const <ISA_LIT>16InstrInfo * ) STI -> getInstrInfo ( ) ; MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! PrescannedForConstants ) prescanForConstants ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) )


<s> for ( auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) ) Regs . push_back ( MO . getReg ( ) ) ; int Size = ( int ) Regs . size ( ) ; if ( Size == <NUM_LIT> ) return false ; assert ( Size % <NUM_LIT> == <NUM_LIT> ) ; assert ( MI . getOpcode ( ) == <STR_LIT> ) ; auto Return = NextMBBI ; if ( shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: EpilogTail ) ) { auto * EpilogTailHelper = getOrCreateFrameHelper ( M , MMI , Regs , FrameHelperType :: EpilogTail ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( EpilogTailHelper ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) . copyImplicitOps ( MI ) . copyImplicitOps ( * Return ) ; NextMBBI = std :: next ( Return ) ; Return -> removeFromParent ( ) ; } else if ( shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: Epilog ) ) { auto * EpilogHelper = getOrCreateFrameHelper ( M , MMI , Regs , FrameHelperType :: Epilog ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( EpilogHelper ) . setMIFlag ( MachineInstr :: FrameDestroy ) . copyImplicitOps ( MI ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadFPAndRetAddr ( SelectionDAG & DAG , int SPDiff , SDValue Chain , SDValue & LROpOut , SDValue & FPOpOut , bool isDarwinABI , DebugLoc dl ) const { if ( SPDiff ) { EVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , NULL , <NUM_LIT> , false ,


<s> for ( ; i != NULL && i != PREV_INSN ( BB_HEAD ( bb ) ) ; i = PREV_INSN ( i ) ) if ( is_conditional_insn ( i ) ) try_optimize_cbranch ( i ) ; } log_msg ( <STR_LIT> ) ; if ( m_split_insns ) for ( std :: vector < rtx > :: const_iterator i = m_touched_insns . begin ( ) ; i != m_touched_insns . end ( ) ; ++ i ) { log_msg ( <STR_LIT> ) ; log_insn ( * i ) ; log_msg ( <STR_LIT> ) ; try_split ( PATTERN ( * i ) , safe_as_a < rtx_insn * > ( * i ) , <NUM_LIT> ) ; } m_touched_insns . clear


<s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & Subtarget , <ISA_LIT>RegisterBankInfo


<s> virtual gimple * fold ( gimple_folder


<s> df_ref def , use ; if ( ! prev || ! next ) return distance + ( distance & <NUM_LIT> ) + <NUM_LIT> ; if ( ! DF_INSN_USES ( next ) || ! DF_INSN_DEFS ( prev ) ) return distance + <NUM_LIT> ; FOR_EACH_INSN_USE ( use , next ) FOR_EACH_INSN_DEF ( def , prev ) if ( ! DF_REF_IS_ARTIFICIAL ( def ) && DF_REF_REGNO ( use ) == DF_REF_REGNO ( def ) ) return distance + ( distance & <NUM_LIT> ) + <NUM_LIT> ; return distance +


<s> FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ; else FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed


<s> static tree nds32_merge_decl_attributes ( tree olddecl , tree newdecl ) { tree combined_attrs ; combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl


<s> if ( Imm == <NUM_LIT> ) return false ; for ( RepeatWidth = RegWidth ; RepeatWidth > <NUM_LIT> ; RepeatWidth /= <NUM_LIT> ) { uint64_t RepeatMask = RepeatWidth == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << RepeatWidth ) - <NUM_LIT> ; uint64_t ReplicatedMask = Imm & RepeatMask ; if ( ReplicatedMask == <NUM_LIT> ) continue ; bool IsReplicatedMask = true ; for ( unsigned i = RepeatWidth ; i < RegWidth ; i += RepeatWidth ) { if ( ( ( Imm >> i ) & RepeatMask ) != ReplicatedMask ) { IsReplicatedMask = false ; break ; } } if ( ! IsReplicatedMask ) continue ; Rotation = CountTrailingZeros_64 ( Imm ) ; if ( Rotation == <NUM_LIT> ) { Rotation = RegWidth == <NUM_LIT> ? CountLeadingOnes_64 ( Imm ) : CountLeadingOnes_32 ( Imm ) ; Rotation = RepeatWidth - Rotation ; } uint64_t ReplicatedOnes = ( ReplicatedMask >> Rotation ) | ( ( ReplicatedMask << ( RepeatWidth - Rotation ) ) & RepeatMask ) ; if ( ! isMask_64 ( ReplicatedOnes ) ) continue ; Num1s = CountTrailingOnes_64 ( ReplicatedOnes ) ; break ; } if ( RepeatWidth == <NUM_LIT> || Num1s == RepeatWidth ) return false ; uint32_t N = RepeatWidth == <NUM_LIT> ; uint32_t ImmR = RepeatWidth - Rotation


<s> EVT VT = Op . getValueType ( ) ; EVT MaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDLoc dl ( Op )


<s> gcc_assert ( GET_CODE ( XEXP ( reg_save_area , <NUM_LIT> ) ) == CONST_INT ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset = offset ; save_area = plus_constant ( Pmode , virtual_stack_vars_rtx , offset ) ; } } else { first_reg_offset = next_cum . words ; save_area = virtual_incoming_args_rtx ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( type ) , type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; rs6000_move_block_from_reg ( GP_ARG_MIN_REG + first_reg_offset , mem , nregs ) ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && TARGET_FPRS && ! no_rtl && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { int fregno = next_cum . fregno , nregs ; rtx cr1 = gen_rtx_REG ( CCmode , CR1_REGNO ) ; rtx lab = gen_label_rtx ( ) ; int off = ( GP_ARG_NUM_REG * reg_size ) + ( ( fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , cr1 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , lab ) , pc_rtx ) ) ) ; for ( nregs = <NUM_LIT> ; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun -> va_list_fpr_size ; fregno ++ , off += UNITS_PER_FP_WORD , nregs ++ ) { mem = gen_rtx_MEM ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode , plus_constant ( Pmode , save_area , off ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ) ) ; emit_move_insn ( mem , gen_rtx_REG ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT


<s> unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ e + i


<s> SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore (


<s> return selectAddrModeUnscaled ( Root , <NUM_LIT>


<s> return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond


<s> if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } else if ( isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp8 = true ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg == <NUM_LIT> ) { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = get<ISA_LIT>RegNum ( IndexReg . getReg ( ) ) ; else IndexRegNo = <NUM_LIT> ; emitSIBByte ( SS , IndexRegNo , <NUM_LIT> ) ; } else { unsigned BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = get<ISA_LIT>RegNum ( IndexReg . getReg ( ) ) ; else IndexRegNo = <NUM_LIT> ; emitSIBByte ( SS , IndexRegNo , BaseRegNo ) ; } if ( ForceDisp8


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static void mips_prepare_pch_save ( void ) { mips_set_compression_mode ( <NUM_LIT> ) ; mips16_globals =


<s> Parser . Lex ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned RegNo , RegKind ; if ( ! matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , RegKind , S , E ) ) ; ResTy = MatchOperand_Success ; } else { ResTy = parseMEMOperand ( Operands


<s> MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy , <NUM_LIT> } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult ,


<s> unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB =


<s> static void sh_file_start ( void ) { default_file_start ( ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , <STR_LIT> , TEXT_SECTION_ASM_OP ) ; else switch_to_section ( data_section ) ; if ( TARGET_LITTLE_ENDIAN ) fputs (


<s> if ( IntrinsicID == <STR_LIT> ) { if ( Subtarget . is<ISA_LIT>64 ( ) ) return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget . hasP9Vector ( ) && ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ) { SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( V1 . getSimpleValueType ( ) == V2 . getSimpleValueType ( ) && ( V1 . getSimpleValueType ( ) == <STR_LIT> || V1 . getSimpleValueType ( ) == <STR_LIT> || V1 . getSimpleValueType ( ) == <STR_LIT> ) ) { if ( V1 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( V1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) && V1 . getOperand ( <NUM_LIT> ) == V2 ) { return DAG . getNode ( <STR_LIT> , dl , V2 . getValueType ( ) , V2 ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) && V2 . getOperand ( <NUM_LIT> ) == V1 ) { return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 ) ; } } } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT>


<s> mutex -> counter = - <NUM_LIT> ; mutex -> depth = <NUM_LIT> ; mutex -> owner


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & , unsigned SyntaxVariant , const MCAsmInfo

& MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I


<s> return ( __m128i ) __builtin_ia32_vpmadd52huq128 ( ( __v2di ) __X , ( __v2di )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; const MachineOperand & BaseOp = MI . getOperand ( <NUM_LIT> ) ; Register Base = BaseOp . getReg ( ) ; const MachineOperand & Reg0Op = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Reg1Op = MI . getOperand ( <NUM_LIT> ) ; if ( Reg0Op . getReg ( ) == Base || Reg1Op . getReg ( ) == Base ) return false ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( MergeInstr == MBB . end ( ) ) return false ; NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isLegalAddressImm ( NewOpc , Offset , TII ) ) return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; assert ( TII -> get ( Opcode ) . getNumOperands ( ) == <NUM_LIT> && TII -> get ( NewOpc ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( const MachineOperand & MO : MI . implicit_operands ( ) ) MIB . add ( MO ) ; MIB . cloneMemRefs (


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , SDLoc (


<s> DebugLoc dl = N -> getDebugLoc ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT>


<s> auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState (


<s> __builtin_ia32_scatterpfdpd ( mask , ( __v8si ) index , ( long long const * ) addr , scale


<s> bool hasModifier ( ) const { return Modifier != NULL


<s> return ( int32x2_t ) __builtin_neon_vreinterpretv2siv2sf (


<s> Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasMMA = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false


<s> if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode


<s> for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { BBI . Size += TII -> GetInstSizeInBytes ( I ) ; if ( I -> isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( I ) ) BBI


<s> llvm_unreachable ( <STR_LIT> ) ; break ; CASE_VSHUF ( <NUM_LIT> , m ) HasMemOp = true ; CASE_VSHUF ( <NUM_LIT> , r ) VT = getRegOperandVectorVT (


<s> bool <ISA_LIT>TargetLowering :: shouldExpandBuildVectorWithShuffles ( EVT VT , unsigned DefinedValues ) const { if ( VT == <STR_LIT> ) return Subtarget . hasDirectMove


<s> MCInst MI ; MI . setOpcode ( Opcode ) ; if ( DefRegister != <STR_LIT> ) MI . addOperand ( MCOperand :: createReg ( DefRegister ) ) ; for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> AddComment ( <STR_LIT> + HandlerLabel -> getName


<s> ( void ) RS ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned Reg = LP64 ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned ShiftBits = get<ISA_LIT>RegisterNumbering ( DestReg ) *


<s> unsigned TZ2 = CountTrailingZeros_32 ( Imm & ~ ( ( <NUM_LIT> << TrailingOnes ) - <NUM_LIT> ) ) ; unsigned RotAmt2 = TZ2 & ~ <NUM_LIT> ; if ( RotAmt2 != <NUM_LIT> && ( rotr32 ( Imm , RotAmt2 ) & ~ <NUM_LIT> ) == <NUM_LIT> ) return ( <NUM_LIT> - RotAmt2 ) & <NUM_LIT> ; } } return ( <NUM_LIT> - RotAmt )


<s> enum aarch64_parse_opt_result res = aarch64_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH64_PARSE_INVALID_ARG ) error ( <STR_LIT> , str ) ; else if ( res == AARCH64_PARSE_MISSING_ARG ) error ( <STR_LIT> ) ; free ( str )


<s> if ( ShiftOp0Opc == <STR_LIT> ) { SDValue Xor = ShiftOp0 . getOperand ( <NUM_LIT> ) ; if ( Xor . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; uint64_t C ; if ( ! isAllConstantBuildVector ( Xor . getOperand ( <NUM_LIT> ) , C ) ) return SDValue ( ) ; unsigned ElemSizeInBits = VT . getScalarSizeInBits ( ) ; APInt CAsAPInt ( ElemSizeInBits , C ) ; if ( CAsAPInt != APInt :: getAllOnesValue ( ElemSizeInBits ) ) return SDValue ( ) ; ExtendOpA = Xor . getOperand ( <NUM_LIT> ) ; ExtendOpB = ShiftOp0 . getOperand ( <NUM_LIT> ) ; } else if ( ShiftOp0Opc == <STR_LIT> ) { ExtendOpA = ShiftOp0 . getOperand ( <NUM_LIT> ) ; ExtendOpB = ShiftOp0 . getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; unsigned ExtendOpAOpc = ExtendOpA . getOpcode ( ) ; unsigned ExtendOpBOpc = ExtendOpB . getOpcode ( ) ; if ( ! ( ExtendOpAOpc == ExtendOpBOpc && ( ExtendOpAOpc == <STR_LIT> || ExtendOpAOpc == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue OpA = ExtendOpA . getOperand ( <NUM_LIT> ) ; SDValue OpB = ExtendOpB . getOperand ( <NUM_LIT> ) ; EVT OpAVT = OpA .


<s> if ( offset < - <NUM_LIT> || offset + num_gfregs * <NUM_LIT> > <NUM_LIT> ) { base = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , base , gen_rtx_PLUS ( Pmode , frame_base_reg , base ) ) ) ; offset = <NUM_LIT> ; } else base = frame_base_reg


<s> EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ; } } return SDValue


<s> else if ( Subtarget . usesFunctionDescriptors ( ) ) prepareDescriptorIndirectCall ( DAG , Callee , Glue , Chain , CallSeqStart , CS , dl , CFlags . HasNest , Subtarget ) ; else prepareIndirectCall ( DAG , Callee , Glue , Chain , dl ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; buildCallOperands ( Ops , CFlags , dl , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget ) ; if ( CFlags . IsTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ; Chain = DAG . getNode ( CallOpc , dl


<s> SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : (


<s> MachineBasicBlock :: iterator end ( ) const { return ++ MachineBasicBlock :: iterator (


<s> if ( IDENTIFIER_POINTER ( STUB_FUNCTION_NAME ( stub ) ) [ <NUM_LIT> ] == '*' ) strcpy ( label_buf , IDENTIFIER_POINTER ( STUB_FUNCTION_NAME ( stub ) ) + <NUM_LIT> ) ; else { label_buf [ <NUM_LIT> ] = '_' ; strcpy ( label_buf + <NUM_LIT> , IDENTIFIER_POINTER ( STUB_FUNCTION_NAME ( stub ) ) ) ; } strcpy ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label_buf ) ; strcat ( tmp_buf , <STR_LIT>


<s> EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = Subtarget . isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize


<s> int getGPStackOffset ( ) const { return GPHolder .


<s> static MachineInstr * LookThroughCOPY ( MachineInstr * MI , MachineRegisterInfo * MRI ) { while ( MI && MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) MI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return MI


<s> Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> )


<s> void <ISA_LIT>TargetStreamer :: emitUnwindRaw ( int64_t StackOffset , const SmallVectorImpl < uint8_t > & Opcodes ) { llvm_unreachable ( <STR_LIT>


<s> static DecodeStatus DecodePCRelLabel19 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { int64_t ImmVal = Imm ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ;