<s> case TYPE_VK64 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : case TYPE_BNDR : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M1616 : case TYPE_M1632 : case TYPE_M1664 : case TYPE_LEA : return translateRMMemory ( mcInst , insn


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerTailCall , <NUM_LIT> ) ; } else if ( LastInstrOpcode == <STR_LIT> || ( LastInstrOpcode == <STR_LIT> && ! HasBTI ) ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerThunk , <NUM_LIT> ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; if ( C . LRU . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerRegSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . UsedInSequence . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else { NumBytesNoStackCalls += SequenceSize ; } } if ( ! AllStackInstrsSafe || NumBytesNoStackCalls <= RepeatedSequenceLocs . size ( ) * <NUM_LIT> ) { RepeatedSequenceLocs = CandidatesWithoutStackFixups ; FrameID = MachineOutlinerNoLRSave ; } else { SetCandidateCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; } if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) { RepeatedSequenceLocs . clear ( ) ; return outliner :: OutlinedFunction ( ) ; } } if ( FlagsSetInAll & MachineOutlinerMBBFlags :: HasCalls ) { bool ModStackToSaveLR = false ; if ( std :: any_of ( FirstCand . front ( ) , FirstCand . back ( ) , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) ModStackToSaveLR = true ; else if ( FrameID != MachineOutlinerThunk && FrameID != MachineOutlinerTailCall && FirstCand .

back ( ) -> isCall ( ) ) ModStackToSaveLR = true ;


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumOperands = MI . getNumOperands ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( NumOperands != <NUM_LIT> || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) llvm_unreachable ( <STR_LIT> ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , isFP ) , <NUM_LIT> ) ; return getInstructionMapping ( DefaultMappingID , <NUM_LIT> ,


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RotateImmediate ) ; Op -> RotImm . Imm


<s> void <ISA_LIT>WinCOFFStreamer :: emitCVFPOData ( const MCSymbol * ProcSym , SMLoc Loc ) { <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer


<s> if ( IsFlagSetting ) { for ( unsigned I = MI . getNumExplicitOperands ( ) , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . isDead ( ) && MO . getReg ( ) == <STR_LIT> ) MO . setIsDead ( false ) ; } return & MI ; } bool Is64Bit ; unsigned NewOpc = TII -> convertToFlagSettingOpc ( MI . getOpcode ( ) , Is64Bit ) ; unsigned NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> hasOneNonDBGUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) NewDestReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MI . getParent ( ) , MI , MI .

getDebugLoc ( ) , TII -> get ( NewOpc ) , NewDestReg ) ;


<s> return __builtin_mve_vldrhq_uv4si ( ( __builtin_neon_hi * ) __base


<s> const MCSection * <ISA_LIT>MCSymbolRefExpr :: FindAssociatedSection ( ) const { return Symbol -> isDefined ( ) ? & Symbol -> getSection ( ) :


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT>


<s> V1InUse = false ; V2InUse = false ; int Size = Mask . size ( ) ; int Scale = <NUM_LIT> / Size ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i / Scale ] < <NUM_LIT> ) { V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size )


<s> MI . addOperand ( MOp2 ) ; MI . addOperand ( MOp1 ) ; } else { SmallVector < MachineOperand , <NUM_LIT> > MOps ; unsigned TotalOps = MI . getNumOperands ( ) + <NUM_LIT> ; for ( unsigned i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= MinOp ; i -- ) { MOps . push_back ( MI . getOperand ( i ) ) ; MI . RemoveOperand ( i ) ; } MI . addOperand ( MOp2 ) ; for ( unsigned i = MI . getNumOperands ( ) ; i < TotalOps ; i ++ ) { if ( i == MaxOp ) MI . addOperand ( MOp1 ) ; else { MI . addOperand ( MOps . back ( ) ) ; MOps . pop_back (


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return new <ISA_LIT>_64MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( TT . isOSLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( TT . isOSNaCl ( ) ) return new


<s> const unsigned MMOpc = Subtarget . has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; const unsigned Opc = Subtarget . inMicro<ISA_LIT>Mode ( ) ? MMOpc : <STR_LIT> ; return BuildMI ( MBB , MI , DL , get ( Opc ) , <STR_LIT> )

. addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack (

LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> bool UseMemory = false ; Align Alignment = CalculateStackSlotAlignment ( ArgVT , OrigVT , Flags , PtrByteSize ) ; ArgOffset = alignTo ( ArgOffset , Alignment ) ; if ( ArgOffset >= LinkageSize + ParamAreaSize ) UseMemory = true ; ArgOffset += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; if ( Flags . isInConsecutiveRegsLast ( ) ) ArgOffset = ( ( ArgOffset + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; if ( ArgOffset > LinkageSize + ParamAreaSize ) UseMemory = true ; if ( ! Flags . isByVal ( )


<s> SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> return ( vector unsigned short ) __builtin_altivec_vsubuhs ( ( vector signed short ) a1 , ( vector signed short


<s> if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) ==


<s> bool isVPST ( ) const { return PredicateThen -> MI -> getOpcode ( )


<s> if ( isa < ScalableVectorType > ( F . getReturnType ( ) ) ) return true ; return llvm :: any_of ( F . args ( )


<s> const <ISA_LIT>Subtarget * getSubtargetImpl (


<s> OS << <STR_LIT> << SU -> NodeNum << <STR_LIT> ; OS << TII -> getName ( SU -> getInstr ( ) -> getOpcode ( ) ) ; const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return ; for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) { const MCProcResourceDesc & PRD = * SchedModel -> getProcResource ( PI -> ProcResourceIdx ) ; std :: string FU ( PRD . Name ) ; FU = FU . substr ( FU . find ( '_' ) + <NUM_LIT> ) ; size_t Pos = FU . find ( <STR_LIT> ) ; if ( Pos != std :: string :: npos ) FU . resize ( Pos ) ; if ( FU == <STR_LIT> ) FU = <STR_LIT> ; OS << <STR_LIT> <<


<s> return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar ( b


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( ImmVal ) ) ; return Success


<s> BuildMI ( Entry , DebugLoc ( ) , TII -> get ( CallOpc ) ) . addSym ( TargetSym ) ; Entry -> addSuccessor ( CaptureSpec ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( CaptureSpec ) ; CaptureSpec -> setHasAddressTaken ( ) ; CaptureSpec -> addSuccessor ( CaptureSpec ) ; CallTarget -> addLiveIn ( Reg ) ; CallTarget -> setHasAddressTaken ( )


<s> d . op1 = op1 ; d . vmode = vmode ; d . nelt = nelt ; d . one_operand_p = false ; d . testing_p = false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ]


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr (


<s> return ( __m128i ) __builtin_ia32_pandn128 ( ( __v2di )


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand (


<s> return loongarch_hard_regno_mode_ok_p [ mode ]


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ; Inst . addOperand ( MCOperand :: createImm


<s> Value * <ISA_LIT>IREmitter :: visitDYN_ALLOC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned Divisor = <NUM_LIT> << Bits ; if ( Val % Divisor != <NUM_LIT> ) return false ; Val /= Divisor ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT>


<s> bool <ISA_LIT>BranchExpansion :: handlePossibleLongBranch ( ) { LongBranchSeqSize = IsPIC ? ( ( ABI . IsN64 ( ) || STI -> isTargetNaCl ( ) ) ? <NUM_LIT> : <NUM_LIT> ) : ( STI -> has<ISA_LIT>32r6 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( STI -> in<ISA_LIT>16Mode ( ) || ! STI -> enableLongBranchPass ( ) ) return false ; if ( SkipLongBranch ) return false ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int64_t Offset = computeOffset ( I -> Br ) ; if ( STI -> isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranchFirstPass && TII -> isBranchOffsetInRange ( I -> Br -> getOpcode ( ) , Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } ForceLongBranchFirstPass = false ; if ( ! EverMadeChange


<s> bool <ISA_LIT>InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = <NUM_LIT> ; unsigned LowReg = <NUM_LIT> , HighReg = <NUM_LIT> , StartOffset = - <NUM_LIT> , EndOffset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg


<s> if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ) ; case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( OpNum - OP_VEXT1 + <NUM_LIT> , dl , <STR_LIT> ) ) ; case OP_VUZPL : case OP_VUZPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS ,

OpRHS ) . getValue ( OpNum - OP_VUZPL ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger


<s> <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , VecIns . back ( ) , CC , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V ; } } if ( Op . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> BinOp ; if ( SDValue Match = DAG . matchBinOpReduction ( Op . getNode ( ) , BinOp , { <STR_LIT> } ) ) { <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , Match , CC , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode ,


<s> return ( __m256d ) __builtin_ia32_xorpd256 ( ( __v4df )


<s> if ( T . getOS ( ) == llvm :: Triple :: FreeBSD || ( T . getOS ( ) == llvm :: Triple :: NetBSD && ! is64Bit ) || ( T . getOS ( ) == llvm :: Triple :: OpenBSD &&

! is64Bit ) ) UseIntegratedAssembler = true ;


<s> const char * IntrMemName = isa < MemCpyInst > ( I ) ? <STR_LIT> : <STR_LIT> ; return SelectCall ( & I , IntrMemName ) ; } case <STR_LIT> : { const MemSetInst & MSI = cast < MemSetInst > ( I ) ; if ( MSI . isVolatile ( ) ) return false ; if ( ! MSI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MSI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; return SelectCall ( & I , <STR_LIT> ) ; } case <STR_LIT> : { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; return


<s> if ( Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> ) return false ; if ( isStrongerThanMonotonic ( cast < MemSDNode > ( Use ) -> getOrdering ( ) ) ) return false ; } return true


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex (


<s> case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case


<s> bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getPointerAdd ( DL , Arg , OffsetInBytes ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val


<s> Options . NumLoadsPerBlock = Options . MaxNumLoads ; Options . LoadSizes = { <NUM_LIT> ,


<s> SMLoc StartLoc = getLoc ( ) ; unsigned RegNum ; OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } getParser ( ) . Lex ( ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > ExtOpnd ; Res = tryParseOptionalShiftExtend ( ExtOpnd ) ; if ( Res != MatchOperand_Success ) return Res ; auto Ext = static_cast < <ISA_LIT>Operand * > ( ExtOpnd . back ( ) . get ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , Ext -> getEndLoc ( ) , getContext ( ) , Ext -> getShiftExtendType ( ) ,

Ext -> getShiftExtendAmount ( ) , Ext -> hasShiftExtendAmount ( ) ) ) ;


<s> return ( int8x8_t ) __builtin_neon_vqabsv8qi


<s> cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & <NUM_LIT> ) && type != NULL_TREE &&


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size


<s> CastVT = VT . changeVectorElementType ( EltVT ) ; } SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue PassThru = DAG . getBitcast ( CastVT , ML -> getPassThru ( ) ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , CastVT , PassThru , Load , VecIndex ) ; Insert = DAG . getBitcast


<s> } else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && isV8M ( STI ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute (


<s> static const SpillSlot Offsets [ ] = { { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } } ; NumEntries = array_lengthof (


<s> switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true


<s> while ( I != ChainEnd ) { -- I ; Units . stepBackward ( * I ) ; } MachineBasicBlock :: iterator ChainBegin = G -> begin ( ) ; assert ( ChainBegin != ChainEnd && <STR_LIT> ) ; do { -- I ; Units . accumulate ( * I ) ; } while ( I != ChainBegin ) ; unsigned RegClassID = ChainBegin -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; auto Ord = RCI . getOrder ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto Reg : Ord ) { if ( ! Units . available (


<s> if ( Memory . ShiftType == <STR_LIT> ) return true ; if ( Memory . ShiftType != <STR_LIT> || Memory . ShiftImm > <NUM_LIT> ) return false ; return true


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( false && <STR_LIT> )


<s> TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! hasV8Ops ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill (


<s> c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V4SImode ; gen_and = gen_andv4si3 ; gen_pack = gen_sse4_1_packusdw ; gen_shift = gen_lshrv4si3 ; break ; case V16QImode : c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8HImode ; gen_and = gen_andv8hi3 ; gen_pack = gen_sse2_packuswb ; gen_shift = gen_lshrv8hi3 ; break ; case V16HImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8SImode ; gen_and = gen_andv8si3 ; gen_pack = gen_avx2_packusdw ; gen_shift = gen_lshrv8si3 ; end_perm = true ; break ; case V32QImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V16HImode ; gen_and = gen_andv16hi3 ; gen_pack = gen_avx2_packuswb ; gen_shift = gen_lshrv16hi3 ; end_perm = true ; break ; default : return false ; } odd = d -> perm [ <NUM_LIT> ] ; if ( odd > <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != <NUM_LIT> * i + odd ) return false ; if ( d -> testing_p ) return true ; dop0 = gen_reg_rtx ( half_mode ) ; dop1 = gen_reg_rtx ( half_mode ) ; if ( odd == <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) rperm [ i ] = GEN_INT ( c ) ; t = gen_rtx_CONST_VECTOR ( half_mode , gen_rtvec_v ( nelt / <NUM_LIT> , rperm ) ) ; t = force_reg ( half_mode , t ) ; emit_insn ( gen_and ( dop0 , t , gen_lowpart ( half_mode , d -> op0 ) ) ) ; emit_insn ( gen_and ( dop1 , t , gen_lowpart ( half_mode , d -> op1 ) ) ) ; } else { emit_insn ( gen_shift ( dop0 , gen_lowpart ( half_mode , d -> op0 ) , GEN_INT ( s


<s> Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG .

getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ;


<s> return <ISA_LIT>3DNowLevel >= ThreeDNowA


<s> unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != TheCall -> getNumArgs ( ) ; i ++ ) { <STR_LIT> Flags = TheCall -> getArgFlags ( i ) ; if ( Flags . isByVal ( ) ) return false ; } SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel (


<s> void <ISA_LIT>IncomingValueHandler :: assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) { auto BuildLoad = [ ] ( MachineIRBuilder & MIRBuilder , MachinePointerInfo & MPO , LLT MemTy , const DstOp & Res , Register Addr ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo (


<s> unsigned <ISA_LIT>AsmParser :: getReg ( int RC , int


<s> void <ISA_LIT>IntelInstPrinter :: printSTiRegOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { const MCOperand & Op = MI -> getOperand (


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineSoRegOpValue ( const MachineInstr & MI , const TargetInstrDesc & TID , const MachineOperand & MO , unsigned OpIdx ) { unsigned Binary = getMachineOpValue ( MI , MO ) ; const MachineOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MachineOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = <NUM_LIT> ; unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable


<s> MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { MachineOperand FirstOp = MI . getOperand ( <NUM_LIT> ) ; const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addOperand ( FirstOp ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT>


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> SUnit SU ( MI , <NUM_LIT> ) ; SU . isCall = MI -> isCall ( ) ; const MCSchedClassDesc * SC = SchedModel -> resolveSchedClass ( MI ) ; for ( const MCWriteProcResEntry & PRE : make_range ( SchedModel -> getWriteProcResBegin ( SC ) , SchedModel -> getWriteProcResEnd ( SC ) ) ) { switch ( SchedModel -> getProcResource ( PRE . ProcResourceIdx ) -> BufferSize ) { case <NUM_LIT> : SU . hasReservedResource = true


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ,


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetOddSPReg


<s> if ( TT . isOSAIX ( ) ) return llvm :: make_unique < TargetLoweringObjectFileXCOFF > ( ) ; return llvm :: make_unique < <ISA_LIT>64LinuxTargetObjectFile


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) && Predicate_simm13 ( Addr . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT>


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI ,


<s> return ( ( insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD ) &&

get_attr_check_load ( insn ) == CHECK_LOAD_NO ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ?


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForNode ( CallConv , false , isVarArg ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break


<s> void <ISA_LIT>SEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; TII . adjustStackPtr ( SP , Amount , MBB ,


<s> unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SubReg = Is16BitOp ? <STR_LIT> : <STR_LIT> ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA ) ; MachineInstr * InsMI = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA , RegState :: Define , SubReg ) . addReg ( Src , getKillRegState ( IsKill ) ) ; MachineInstrBuilder MIB = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( Opcode ) , OutRegLEA ) ; switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { unsigned ShAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> << ShAmt ) . addReg ( InRegLEA , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , <NUM_LIT> ) ; break ; case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill2 = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned InRegLEA2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , InRegLEA , true , InRegLEA , false ) ; } else { if ( Subtarget . is64Bit ( ) ) InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA2 , RegState :: Define , SubReg ) . addReg ( Src2 , getKillRegState ( IsKill2 ) ) ; addRegReg ( MIB , InRegLEA , true , InRegLEA2 ,


<s> if ( isShifter ( ) ) { assert ( <STR_LIT> ( getShifter ( ) ) == <STR_LIT> ) ; unsigned imm = getArithExtendImm ( <STR_LIT> , <STR_LIT> ( getShifter ( ) ) ) ; Inst . addOperand ( MCOperand ::


<s> MachineBasicBlock :: iterator SlotI = Slot ; if ( ! searchRange ( MBB , ++ SlotI . getReverse ( ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( SlotI ) , & MBB , Filler . getReverse ( ) ) ; MIBundleBuilder ( MBB , SlotI , std :: next ( SlotI , <NUM_LIT> ) ) ; ++ UsefulSlots ; return true


<s> if ( ! chooseBestLEA ( Insns -> second , MI , DefMI , AddrDispShift , Dist ) ) continue ; if ( Dist < <NUM_LIT> ) { DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; InstrPos [ DefMI ] = InstrPos [ & MI ] - <NUM_LIT> ; assert ( ( ( InstrPos [ DefMI ] == <NUM_LIT> && MachineBasicBlock :: iterator ( DefMI ) == MBB -> begin ( ) ) || InstrPos [ DefMI ] > InstrPos [ & * std :: prev ( MachineBasicBlock :: iterator ( DefMI ) ) ] ) && <STR_LIT> ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( MemOpNo + <STR_LIT>

) . ChangeToImmediate ( AddrDispShift ) ;


<s> * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , insn -> modRM ) ; } else { * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , <NUM_LIT> ) ; } return


<s> for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; Register DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << * MI ) ; auto G = std :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else if ( isMla ( MI ) ) { Register DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AccumReg , TRI ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ActiveChains [ AccumReg ] -> add ( MI , Idx , getColor ( DestReg ) ) ; if ( DestReg != AccumReg


<s> static SDValue getAVX2GatherNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Src , SDValue Mask , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( Op ) ; auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast <


<s> AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg ,


<s> for ( unsigned i = <NUM_LIT> ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * <NUM_LIT> : (


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts


<s> Relocator :: Address GOT_ORG = helper_GOT_ORG ( pParent ) ; pReloc . target ( ) = GOT_ORG + A - pReloc . place ( ) ; return Relocator ::


<s> } if ( ! RLL || ! isShift ( RLL , <STR_LIT> , <NUM_LIT> ) ) return false ; MachineInstr * SRL = getDef ( RLL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! SRL || ! isShift ( SRL , <STR_LIT> , <STR_LIT> ) ) return false ; MachineInstr * IPM = getDef ( SRL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! IPM || IPM -> getOpcode ( ) != <STR_LIT> ) return false ; if ( IPM -> getParent ( ) != Compare -> getParent ( ) ) return false ; MachineBasicBlock :: iterator MBBI = IPM , MBBE = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return false ; } Compare -> eraseFromParent (


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ] . attr

& RS6000_BTC_OVERLOADED ) != <NUM_LIT> ;


<s> static void createPHIsForSelects ( MachineBasicBlock :: iterator MIItBegin , MachineBasicBlock :: iterator MIItEnd , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB , MachineBasicBlock * SinkMBB ) { MachineFunction * MF = TrueMBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; unsigned CCValid = MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MIItBegin -> getDebugLoc ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; MIIt = skipDebugInstructionsForward ( ++ MIIt , MIItEnd ) ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable [ FalseReg ] . second ; BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB

( TrueMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! isConstantSplat ( N -> getOperand ( <NUM_LIT> ) , SplatVal ) || ! SplatVal . isOneValue ( ) ) return SDValue ( ) ; SDValue AllOnesVec = getOnesVector ( VT , DAG , SDLoc ( N ) ) ; unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpcode , SDLoc ( N ) , VT ,

N -> getOperand ( <NUM_LIT> ) , AllOnesVec ) ;


<s> case <STR_LIT> : return ELF :: R_390_PC16DBL ; case <STR_LIT> : return ELF :: R_390_PC32DBL ; } llvm_unreachable (


<s> case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize


<s> TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer -> AddBlankLine (


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = Op . getValueType ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( TgtBAHi , TgtBALo , isPIC , DAG


<s> } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> Pred = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CRReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ( Pred ) ) . addReg ( CRReg ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm


<s> default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_NE ; IC . pushOperator ( IC_NE ) ; break ; } PrevState =


<s> CurDAG -> computeKnownBits ( And , Known ) ; uint64_t NotKnownZero = ( ~ Known . Zero ) . getZExtValue ( ) ; if ( ! isShiftedMask ( Known . Zero . getZExtValue ( ) , VT ) ) return false ; if ( ( OrImm & NotKnownZero ) != <NUM_LIT> ) { return false ; } int LSB = countTrailingOnes ( NotKnownZero ) ; int Width = BitWidth - APInt ( BitWidth , NotKnownZero ) . countPopulation ( ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; bool IsBFI = LSB != <NUM_LIT> ; uint64_t BFIImm = OrImm >> LSB ; if ( IsBFI && ! <STR_LIT> ( BFIImm , BitWidth ) ) { unsigned OrChunks = <NUM_LIT> , BFIChunks = <NUM_LIT> ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitWidth ; Shift += <NUM_LIT> ) { if ( ( ( OrImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ OrChunks ; if ( ( ( BFIImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ BFIChunks ; } if ( BFIChunks > OrChunks ) return false ; } SDLoc DL ( N )


<s> tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return NUM_TYPE_SUFFIXES ; for ( unsigned int size_i = <NUM_LIT> ; size_i < MAX_TUPLE_SIZE ; ++ size_i ) for ( unsigned int suffix_i = <NUM_LIT> ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) { vector_type_index type_i = type_suffixes [ suffix_i ] . vector_type ; tree type = acle_vector_types [ size_i ] [ type_i ] ; if ( type && matches_type_p ( type , actual ) ) { if ( size_i + <NUM_LIT> == num_vectors ) return type_suffix_index ( suffix_i ) ; if ( num_vectors == <NUM_LIT> ) error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl ) ; else if ( size_i == <NUM_LIT> && type_i != VECTOR_TYPE_svbool_t ) error_n ( location , num_vectors ,

<STR_LIT> , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , num_vectors ) ;


<s> Instruction * SVEExpandLibCall :: CreateMergeCpy ( Value * Merge , Value * GP , Value * Scalar ) { auto VecTy = Merge -> getType ( ) ; SmallVector < Value * , <NUM_LIT> > Args { Merge , GP , Scalar } ; <STR_LIT> IntID = <STR_LIT> ; Function * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , {


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) )


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; if ( DstSize > SrcSize && SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> ) { const TargetRegisterClass * SrcRC = getRegClass ( MRI . getType ( SrcReg ) , SrcRegBank ) ; const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { unsigned ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI


<s> Module * M = Builder . GetInsertBlock ( )


<s> static <STR_LIT> GetInitialBlockMask ( unsigned BlockSize ) { switch ( BlockSize ) { case <NUM_LIT> : return <STR_LIT> ::


<s> rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= <NUM_LIT> ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ; } return par


<s> } register_builtin_types ( ) ; for ( unsigned int type_i = <NUM_LIT> ; type_i < NUM_VECTOR_TYPES ; ++ type_i ) { vector_type_index type = vector_type_index


<s> static DecodeStatus decodeU12ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeUImmOperand < <NUM_LIT> > (


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return <NUM_LIT> ; if ( ScalarType -> isIntegerTy ( ) ) return <NUM_LIT> ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ST -> isSLM ( ) ) if ( auto * Entry = CostTableLookup ( SLMCostTbl , ISD , MScalarTy ) ) return Entry -> Cost ; } int RegisterFileMoveCost =


<s> case AARCH64_CMODEL_TINY : if ( aarch64_tls_size > <NUM_LIT> ) aarch64_tls_size = <NUM_LIT> ; break ; case AARCH64_CMODEL_SMALL : if ( aarch64_tls_size > <NUM_LIT> ) aarch64_tls_size = <NUM_LIT> ; break ; case AARCH64_CMODEL_LARGE : if ( aarch64_tls_size > <NUM_LIT> ) aarch64_tls_size =


<s> UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; HasLEB128 = true ; ExceptionsType = ExceptionHandling ::


<s> if ( i != <NUM_LIT> ) O << <STR_LIT> ; if ( MI -> getOperand ( i ) . isReg ( ) ) printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ; else printUImm < <NUM_LIT> > ( MI , i


<s> bool <ISA_LIT>TTIImpl :: enableMemCmpExpansion ( unsigned & MaxLoadSize ) { MaxLoadSize =


<s> if ( Subtarget . hasInt256 ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT InVT = N . getValueType ( ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , Size / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT .


<s> bool <ISA_LIT>ConstantIslands :: undoLRSpillRestore ( ) { bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = PushPopMIs . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = PushPopMIs [ i ] ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> eraseFromParent ( ) ; MadeChange = true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , STI . getFeatureBits ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( )


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeVMOVModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - imm ) ) ; return S


<s> const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned FirstEncoding = RI -> getEncodingValue ( FirstReg ) ; if ( FirstEncoding & <NUM_LIT> ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc M = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( M , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; SMLoc E = getLoc ( ) ; int SecondReg = tryParseRegister ( ) ; if ( SecondReg == - <NUM_LIT> ) { return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( SecondReg ) != FirstEncoding + <NUM_LIT> || ( isXReg && ! XRegClass . contains ( SecondReg ) ) || ( isWReg && ! WRegClass . contains ( SecondReg ) ) ) { Error ( E , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned Pair = <NUM_LIT> ; if ( isXReg


<s> if ( SPDiff ) { EVT VT = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) ) ; Chain = SDValue ( LROpOut . getNode


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) SavedRegs . set ( <STR_LIT> [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; } if ( HasFP ) SavedRegs . set ( <STR_LIT> ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( <STR_LIT> ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs


<s> if ( isThumb ( ) ) { assert ( ( ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write16 ( <NUM_LIT> ) ; return


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { if ( GET_CODE ( XEXP ( link , <NUM_LIT> ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ix86_check_avx256_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; } subrtx_iterator ::


<s> bool isAM3Offset ( ) const { if ( isPostIdxReg ( ) ) return true ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < <NUM_LIT> ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , <NUM_LIT> ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % <NUM_LIT> ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ <NUM_LIT> ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int Mask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; EVT VT = ( PVT == <STR_LIT> )


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * CRImm = MCConstantExpr :: Create ( CRNum , getContext ( ) ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CRImm , S , E ) ) ; return MatchOperand_Success


<s> MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . add ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) .


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc (


<s> static MachineInstr * findWLSInBlock ( MachineBasicBlock * MBB ) { for ( auto & Terminator : MBB -> terminators


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4


<s> static <ISA_LIT>Operand * createToken ( StringRef Str , SMLoc Loc ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindToken , Loc , Loc ) ; Op -> Token . Data =


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , DAG . getConstant

( FPCondCCodeToFCC ( CC ) , <STR_LIT> ) ) ;


<s> if ( ! Op . isExpr ( ) ) return false ; const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; return Ref && Ref -> getKind ( ) == MCSymbolRefExpr ::


<s> BalTgtMBB -> addSuccessor ( TgtMBB ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BalOp = <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else { BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT>


<s> Op -> VectorList . Count = Count ; Op -> VectorList . LaneIndex = Index ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = <NUM_LIT> ; if ( FP_REG_RTX_P ( op ) ) { offset = ( UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != <NUM_LIT> ) ; return gen_rtx_REG ( word_mode , REGNO (


<s> return __builtin_loongson_punpckhbh_u ( s


<s> SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AhiBlo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , AloBlo


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( SrcOpMap . begin ( ) != SrcOpMap . end ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt EltCount = APInt :: getNullValue ( NumElts ) ; M = SrcOpMap . insert ( std :: make_pair ( Src , EltCount ) ) . first ; SrcOps . push_back ( Src ) ; } unsigned CIdx = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( M -> second [ CIdx ] ) return false ; M -> second . setBit ( CIdx ) ; } if ( SrcMask ) { for ( SDValue & SrcOp : SrcOps ) SrcMask -> push_back ( SrcOpMap [ SrcOp ] ) ; } else { for ( DenseMap < SDValue , APInt > :: const_iterator I = SrcOpMap . begin ( ) , E = SrcOpMap . end ( ) ; I != E ; ++ I ) { if ( ! I -> second . isAllOnesValue ( )


<s> bool <ISA_LIT>DAGToDAGISel :: shrinkAndImmediate ( SDNode * And ) { MVT VT = And -> getSimpleValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; auto * And1C = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! And1C ) return false ; APInt MaskVal = And1C -> getAPIntValue ( ) ; unsigned MaskLZ = MaskVal . countLeadingZeros ( ) ; if ( ! MaskLZ ) return false ; SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( VT . getSizeInBits ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ; unsigned MinWidth = NegMaskVal . getMinSignedBits ( ) ; if ( MinWidth > <NUM_LIT> || ( MinWidth > <NUM_LIT> && MaskVal

. getMinSignedBits ( ) <= <NUM_LIT> ) ) return false ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( CRRegs [ getCRBitMask ( ) ]


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ops [ ] = { Op -> getOperand ( <NUM_LIT> ) ,

Op -> getOperand ( <NUM_LIT> ) , Lo , Hi } ;


<s> bool hasHRESET ( ) const { return HasHRESET


<s> static bool isZero ( SDValue V ) { ConstantSDNode * C = dyn_cast <


<s> const auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; const auto it = WinEHXMMSlotInfo . find ( FI ) ; if ( it == WinEHXMMSlotInfo . end ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; FrameReg = TRI -> getStackRegister ( ) ; return alignTo ( MFI . getMaxCallFrameSize ( ) , getStackAlignment ( )


<s> SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( ! is64bit ) llvm_unreachable ( <STR_LIT> ) ; if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TPOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , TPOffsetHi ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGA ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTEntryHi , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , ParmReg , TGA ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TLSAddr ) ; return DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; } if ( Model == TLSModel ::


<s> auto * CCMask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValid || ! CCMask ) return SDValue ( ) ; int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Select = N -> getOperand ( <NUM_LIT> ) ; if ( Select -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * SelectCCValid = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * SelectCCMask = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! SelectCCValid || ! SelectCCMask ) return SDValue ( ) ; int SelectCCValidVal = SelectCCValid -> getZExtValue ( ) ; int SelectCCMaskVal = SelectCCMask -> getZExtValue ( ) ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal || ! FalseVal ) return SDValue ( ) ; if ( TrueVal -> getZExtValue ( ) != <NUM_LIT> && FalseVal -> getZExtValue ( ) == <NUM_LIT> ) ; else if ( TrueVal -> getZExtValue ( ) == <NUM_LIT> && FalseVal -> getZExtValue ( ) != <NUM_LIT> ) SelectCCMaskVal ^= SelectCCValidVal ; else return SDValue (


<s> if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < <NUM_LIT> ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm5 = MO1 .


<s> const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering . getPointerTy ( ) == <STR_LIT> ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else


<s> User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; Instruction * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set


<s> EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget


<s> MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> void <ISA_LIT>MCInstLower :: lowerInstruction ( const MachineInstr & MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI . getOpcode ( ) ) ; for ( MachineOperand const & MO : MI . operands ( ) ) { MCOperand


<s> if ( ( I -> mayLoad ( ) ) && std :: next ( I ) == E && I != MBB -> begin ( ) ) { MachineBasicBlock * newBB = MF . CreateMachineBasicBlock ( ( I -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; MF . insert ( It , newBB ) ; newBB -> splice ( newBB -> end ( ) , I -> getParent ( ) , I ) ; MBB -> addSuccessor ( newBB ) ; newBB -> setHasAddressTaken ( ) ; break ; } } } return


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint32_t > ( OS , Binary ,


<s> <STR_LIT> Cond = <STR_LIT> ( CMovI ) ; unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! LegalOperations ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { char V = isNegatibleForFree ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; if ( V == <NUM_LIT> ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; } bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB ,


<s> if ( IsBFI && ! <STR_LIT> ( BFIImm , BitWidth ) ) { unsigned OrChunks = <NUM_LIT> , BFIChunks = <NUM_LIT> ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitWidth ; Shift += <NUM_LIT> ) { if ( ( ( OrImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ OrChunks ; if ( ( ( BFIImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ BFIChunks ; } if ( BFIChunks > OrChunks ) return false ; } SDLoc DL ( N ) ; unsigned MOVIOpc = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * MOVI = CurDAG -> getMachineNode ( MOVIOpc , DL , VT , CurDAG -> getTargetConstant ( BFIImm , DL , VT ) ) ; SDValue Ops [ ] = { And . getOperand ( <NUM_LIT> ) , SDValue ( MOVI , <NUM_LIT> ) , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT


<s> } else if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else return false ; TypeSize Scale ( <NUM_LIT> , false ) ; int64_t Dummy1 , Dummy2 ; if ( ! getMemOpInfo ( LdSt . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { BaseOp = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) * Scale


<s> CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Constant * C0 = ConstantVector :: get ( CV0 ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0


<s> void <ISA_LIT>TargetStreamer :: emitRegSave ( const SmallVectorImpl < unsigned > & RegList


<s> return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt )

) + <NUM_LIT> ) >= <NUM_LIT> && ( INTVAL ( mask ) & ( ( <NUM_LIT> << INTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> int src_regno ; if ( src == pc_rtx ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number ( dest_regno ) ) ; return ; } src_regno = REGNO ( src ) ; switch ( src_regno ) { case PR_REG ( <NUM_LIT> ) : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_pr ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number ( dest_regno ) ) ; break ; case AR_UNAT_REGNUM : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_ar_unat ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number (


<s> if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default :


<s> aarch64_add_constant_internal ( mode , regnum , scratchreg , delta , false ,


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> isThreadLocal ( ) ? MMIMachO . getThreadLocalGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ; if ( ! IsIndirect ) return getSymbol ( GV


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode


<s> inline vector signed char vec_splat_s8


<s> KMaskOp = <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) FirstCommutableVecOp = <NUM_LIT> ; LastCommutableVecOp ++ ; } else if ( IsIntrinsic ) { FirstCommutableVecOp = <NUM_LIT> ; } if ( isMem ( MI , LastCommutableVecOp ) ) LastCommutableVecOp -- ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = LastCommutableVecOp ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex


<s> uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; Register SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF ) ) { NewSP = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , OldSP , NeededSpace ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; } else { NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; } SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ~ ( RequiredAlign - <NUM_LIT> ) , DL , <STR_LIT> ) ) ; } if ( StoreBackchain ) Chain = DAG . getStore ( Chain , DL , Backchain , getBackchainAddress ( NewSP , DAG )


<s> assert ( isPowerOf2_32 ( SlotSize ) && <STR_LIT> ) ; Log2SlotSize = Log2_32 ( SlotSize ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( MI . getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , MBB , MI , Context ) ; CallSeqVector . push_back ( Context )


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock ::


<s> } if ( regno <= <NUM_LIT> ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return <NUM_LIT> ; if ( regno == FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( regno == ARG_POINTER_REGNUM ) return <NUM_LIT> ; if ( regno == <NUM_LIT> ) return


<s> static inline void adjustRowCfg ( unsigned TIdx


<s> if ( TT . isOSFreeBSD ( ) ) return std :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return std :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSSolaris ( ) ) return std :: make_unique < <ISA_LIT>SolarisTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return std :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return std :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable ( <STR_LIT>


<s> void EmitThumbFunc ( MCSymbol * Func ) override { getAssembler ( ) . setIsThumbFunc ( Func ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Func ) ; SD . setFlags ( SD . getFlags ( ) | ELF_Other_ThumbFunc


<s> if ( InsertElt . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ExtractVec = InsertElt . getOperand ( <NUM_LIT> ) ; SDValue ExtractIdx = InsertElt . getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( ExtractIdx ) ) return SDValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) != ExtractVec . getValueType ( ) ) return SDValue ( ) ; if ( ! isLanes1toNKnownZero ( ExtractVec ) ) return


<s> SDValue OrigShiftAmt = N -> getOperand ( <NUM_LIT> ) ; SDValue ShiftAmt = OrigShiftAmt ; SDLoc DL ( N ) ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> ) ShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; SDValue NewShiftAmt ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> || ShiftAmt -> getOpcode ( ) == <STR_LIT> ) { SDValue Add0 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; SDValue Add1 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Add1 ) && cast < ConstantSDNode > ( Add1 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { NewShiftAmt = Add0 ; } else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Add0 ) && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) != <NUM_LIT> && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { EVT SubVT = ShiftAmt . getValueType ( ) ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant (


<s> gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P ( mode ) ) x = expand_vector_broadcast ( mode , x ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; x = gen_lowpart ( mode , x ) ; } m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> , true ) ; create_input_operand ( & m_ops . last ( ) ,


<s> SDValue Glue = End . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( Glue ) ; VTs = DAG . getVTList ( PtrVT , <STR_LIT> ) ; End = DAG . getNode ( <STR_LIT> , DL , VTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return std :: make_pair ( End ,


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! <ISA_LIT>FI -> getLOHRelated ( ) . empty ( )


<s> auto Shift = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CmpLHS , Val ) ; auto Or = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shift , N -> getOperand ( <NUM_LIT> ) ) ; return Or ; } } if ( N0 . getOpcode ( ) != <STR_LIT> || CCVT . getVectorElementCount ( ) != ElementCount :: getFixed ( <NUM_LIT> ) || CCVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return SDValue ( ) ; SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode > ( N0 . getOperand


<s> int mmix_register_move_cost ( enum machine_mode mode ATTRIBUTE_UNUSED , enum reg_class from , enum reg_class to ) { return ( from == GENERAL_REGS && from == to ) ?


<s> std :: string <ISA_LIT>Name = CPU ; if ( <ISA_LIT>Name . empty ( ) ) <ISA_LIT>Name = <STR_LIT> ; std :: string


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ; isKill = true


<s> Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG .

getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ;