<s> y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , ( vec_uint4

) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> auto * VTy = cast < FixedVectorType > ( Ty ) ; unsigned WideBits = getScalarSizeInBits ( Ty ) * VTy -> getNumElements ( ) ; assert ( WideBits > <NUM_LIT> && <STR_LIT> ) ; return ( ( WideBits % <NUM_LIT> ) ? ( ( WideBits / <NUM_LIT> ) + <NUM_LIT> )


<s> break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet (


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2


<s> case <NUM_LIT> : switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> )


<s> ShadowCallStack ( ) : MachineFunctionPass ( ID ) { initializeShadowCallStackPass ( * PassRegistry :: getPassRegistry


<s> bool Is64Bit = Subtarget . is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned I = <NUM_LIT> , InsIndex = <NUM_LIT> , E = RVLocs . size ( ) ; I != E ; ++ I , ++ InsIndex ) { CCValAssign & VA = RVLocs [ I ] ; EVT CopyVT = VA . getLocVT ( ) ; if ( RegMask && CallConv == CallingConv :: <ISA_LIT>_RegCall ) { for ( MCSubRegIterator SubRegs ( VA . getLocReg ( ) , TRI , true ) ; SubRegs . isValid ( ) ; ++ SubRegs ) RegMask [ * SubRegs / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( * SubRegs % <NUM_LIT> ) ) ; } if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ InsIndex ] . Flags . isInReg ( ) ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned


<s> static __inline vec_int4 spu_addx ( vec_int4 a , vec_int4 b , vec_int4 c ) { return ( ( vec_int4 ) ( si_addx ( ( qword ) ( a ) , ( qword ) ( b )


<s> vtrnq_s8 ( int8x16_t a , int8x16_t b ) { return ( int8x16x2_t ) { vtrn1q_s8 ( a , b ) , vtrn2q_s8 ( a


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> void onLShift ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State =


<s> static Mnode * move_minipool_fix_forward_ref ( Mnode * mp , Mnode * max_mp , HOST_WIDE_INT max_address ) { gcc_assert ( mp != max_mp ) ; if ( max_mp == NULL ) { if ( max_address < mp -> max_address ) mp -> max_address = max_address ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> prev -> next = mp -> next ; if ( mp -> next != NULL ) mp -> next -> prev = mp -> prev ; else minipool_vector_tail = mp -> prev ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO


<s> typedef typename std :: make_signed < T > :: type SignedT ; typedef typename std :: make_unsigned < T > :: type UnsignedT ; uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; UnsignedT PrintVal = <STR_LIT> ( Val , <NUM_LIT> ) ; if ( ( int16_t ) PrintVal == ( SignedT ) PrintVal ) printSVEImm ( ( T ) PrintVal , O ) ; else if ( ( uint16_t ) PrintVal == PrintVal ) printSVEImm ( PrintVal , O ) ; else O << '#' << formatHex (


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> static bool StartsWithGlobalOffsetTable ( const MCExpr * Expr ) { if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BE = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BE -> getLHS ( ) ; } if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) return false ; const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr


<s> case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> )


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> &&


<s> continue ; } if ( ! IsControlFlow && CurState == EXITS_DIRTY ) continue ; if ( hasYmmOrZmmReg ( MI ) ) { CurState = EXITS_DIRTY ; continue ; } if ( ! IsControlFlow ) continue ; if ( IsCall && ! callHasRegMask ( MI ) ) continue ; if ( CurState == EXITS_DIRTY ) { insertVZeroUpper ( MI , MBB ) ; CurState = EXITS_CLEAN ; } else if ( CurState == PASS_THROUGH ) { BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = MI ; CurState = EXITS_CLEAN


<s> CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals ,


<s> tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return false ; if ( ! scalar_argument_p ( argno ) && ! VECTOR_TYPE_P ( actual ) ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl ) ; return false ; } return true


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I -> eraseFromParent (


<s> isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return true ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; Base = Ptr -> getOperand (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( )


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> const GlobalVariable * getPromotedGlobal ( ) const { return dyn_cast_or_null < GlobalVariable > (


<s> case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : fputs ( <STR_LIT> , file


<s> asm_fprintf ( asm_out_file , <STR_LIT> , num , val ) ; if ( flag_verbose_asm || flag_debug_asm ) asm_fprintf ( asm_out_file , <STR_LIT> , ASM_COMMENT_START , name


<s> if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . is<ISA_LIT>64


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ,


<s> if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList )


<s> Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) return <STR_LIT> ( Disp , Start , End ) ; StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , ErrMsg ) ) return ErrorOperand ( Start , ErrMsg ) ; if ( isParsingInlineAsm ( ) ) return CreateMemForInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) ) ; if ( ! ( BaseReg || IndexReg || RegNo ) ) return <STR_LIT>

( getPointerWidth ( ) , Disp , Start , End , Size ) ;


<s> assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; while ( <NUM_LIT> ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange


<s> if ( ! REG_P ( reg1 ) || ! REG_P ( reg2 ) ) return false ; regno1 = REGNO ( reg1 ) ; regno2 = REGNO ( reg2 ) ; if ( ! GP_REG_P ( regno1 ) || ! GP_REG_P ( regno2 ) ) return false ; pair = ( <NUM_LIT> << regno1 ) | ( <NUM_LIT> << regno2 ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( match ) ; i ++ ) if ( pair == match [ i ] ) return true ; return false


<s> SmallVector < int , <NUM_LIT> > V1Mask ( Mask . size ( ) , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > V2Mask ( Mask . size ( ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int UnpackIdx = i / Scale ; if ( ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) != ( Mask [ i ] < Size ) ) return SDValue ( ) ; SmallVectorImpl < int > & VMask = ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) ? V1Mask : V2Mask ; VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getNode ( <STR_LIT> , DL , UnpackVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , UnpackVT , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ; } if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ; SmallVector < int , <NUM_LIT> > PermMask ; PermMask . assign ( Size , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; assert ( Mask [ i ] %


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , & Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment


<s> if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : case TYPE_SLOAD


<s> if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) - INSN_LUID (


<s> if ( ! REG_P ( operands [ <NUM_LIT> ] ) || ! REG_P ( operands [ <NUM_LIT> ] ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ; return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , <NUM_LIT>


<s> auto LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ; auto PhysRegToVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( LocSize ) ) ; MIRBuilder . buildCopy ( PhysRegToVReg , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg ,


<s> static bool rs6000_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_32BIT && mode ==


<s> int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; FrameReg = <STR_LIT>


<s> SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , BitNo ) ; <STR_LIT> Cond = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG

. getConstant ( Cond , dl , <STR_LIT> ) , BT ) ;


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int ) Value


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( ) +


<s> assert ( ( VT . is256BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> ) || ( VT . is512BitVector ( ) && ( Op . getNumOperands ( ) == <NUM_LIT> || Op . getNumOperands ( ) == <NUM_LIT> ) ) ) ; return LowerAVXCONCAT_VECTORS ( Op


<s> static bool mips_can_inline_p ( tree caller , tree callee ) { if ( mips_get_compress_mode ( callee ) != mips_get_compress_mode ( caller ) ) return false ; return default_target_can_inline_p ( caller , callee )


<s> void <ISA_LIT>TargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { llvm_unreachable ( <STR_LIT>


<s> if ( SDValue V = lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } if ( Subtarget . hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL ,

<STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ;


<s> bool SelectPDForm ( SDNode * Parent , SDValue N , SDValue &


<s> if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) aarch64_adjust_sve_callee_save_base ( mode , base_rtx , anchor_reg , offset , ptrue ) ; else if ( GP_REGNUM_P ( regno ) && ( ! offset . is_constant ( & const_offset ) || const_offset >= <NUM_LIT> ) ) { gcc_assert ( known_eq ( start_offset , <NUM_LIT> ) ) ; poly_int64 fp_offset = cfun -> machine -> frame . below_hard_fp_saved_regs_size ; if ( hard_fp_valid_p ) base_rtx = hard_frame_pointer_rtx ; else { if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( fp_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; } offset -= fp_offset ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; bool need_cfa_note_p = ( base_rtx != stack_pointer_rtx ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; if ( aarch64_emit_cfi_for_reg_p ( regno2 ) ) { if ( need_cfa_note_p ) aarch64_add_cfa_expression ( insn , reg2 , stack_pointer_rtx , sp_offset + GET_MODE_SIZE ( mode ) ) ; else RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) { insn = emit_insn ( gen_aarch64_pred_mov ( mode , mem , ptrue , reg ) ) ; need_cfa_note_p = true ; } else if ( aarch64_sve_mode_p ( mode ) ) insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ; else insn = emit_move_insn (


<s> struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) return <NUM_LIT> ; for ( ; link ; link = link -> next ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; rtx use_body = PATTERN ( use_insn ) ; if ( GET_CODE ( use_body ) != SET || GET_CODE ( SET_SRC ( use_body ) ) != UNSPEC || XINT ( SET_SRC ( use_body ) , <NUM_LIT> ) != UNSPEC_VSX_XXSPLTW || XEXP ( XEXP ( SET_SRC ( use_body ) , <NUM_LIT> ) , <NUM_LIT> ) != const0_rtx ) return <NUM_LIT> ; } } return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_CONCAT && ( GET_MODE ( SET_SRC ( body ) ) == V2DFmode || GET_MODE ( SET_SRC ( body ) ) == V2DImode ) ) { * special = SH_CONCAT ; return <NUM_LIT> ; } if ( GET_CODE ( body ) == PARALLEL ) { rtx expr = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( expr ) == SET && v2df_reduction_p ( SET_SRC ( expr ) ) ) return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VPERM && XVECLEN ( SET_SRC ( body ) , <NUM_LIT> ) == <NUM_LIT> && GET_CODE ( XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ) == REG ) { rtx mask_reg = XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) if ( rtx_equal_p ( DF_REF_REG ( use ) , mask_reg ) ) { struct df_link * def_link =


<s> BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT ) ; if ( CompareOpc == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( Op1 ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( MBB , DL , TII . get ( CompareOpc ) ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; return true


<s> tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target =


<s> StringRef Name = Sym -> getName ( ) ; Triple TT ( TM . getTargetTriple ( ) ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( ( TT . isWindowsGNUEnvironment ( ) || TT . isWindowsCygwinEnvironment ( ) ) && ( Name [ <NUM_LIT> ] == getDataLayout ( ) . getGlobalPrefix ( ) ) ) Name = Name . drop_front ( ) ; OS << Name ; if ( IsData ) { if ( TT . isKnownWindowsMSVCEnvironment (


<s> Parser . Lex ( ) ; const MCExpr * Val ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; void * Decl = nullptr ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_EnumVal ) ) return ErrorOperand ( Start , <STR_LIT> ) ; else if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) Decl = Info . Var . Decl ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ; bool Parse32 = is32BitMode ( ) || Code16GCC ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : ( Parse32 ? <STR_LIT>


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg (


<s> unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm ) ; if ( HeadCmp == <STR_LIT> ) { adjustHeadCond = ! adjustHeadCond ; } if ( adjustHeadCond ) { Changed |= adjustTo ( HeadCmpMI , HeadCmp , TrueCmpMI ,


<s> if ( aarch64_vector_data_mode_p ( mode1 ) && aarch64_vector_data_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) )


<s> unsigned <ISA_LIT>BaseInstrInfo :: getInstBundleLength ( const MachineInstr * MI ) const { unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle (


<s> case CPU_PPC8548 : return <NUM_LIT> ; case CPU_CELL : return ( reload_completed ? <NUM_LIT> : <NUM_LIT> ) ; default : return <NUM_LIT>


<s> const TargetRegisterClass * RC = RegInfo . intRegClass ( VRegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc )


<s> unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / vectorWidth ) * ElemsPerChunk ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , Vec -> op_begin ( ) + NormalizedIdxVal , ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , ResultVT , Vec , VecIdx ) ; return


<s> if ( TARGET_OLDABI ) return ( VECTOR_FLOAT_TYPE_P ( type ) || TYPE_MODE ( type ) == BLKmode ) ; return ( ! IN_RANGE ( int_size_in_bytes ( type ) ,


<s> getEmergencySpillSlotSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = MFFrame -> getStackSize ( ) + <STR_LIT> * <NUM_LIT> ; return isUInt < <NUM_LIT> > ( MaxReach ) ? <NUM_LIT>


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt (


<s> if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( pat ) , NONCONST ) { const_rtx x = * iter ; if ( REG_P ( x ) && REGNO ( x ) != LO_REGNO && REGNO ( x ) != HI_REGNO && reg_set_p ( x , prev ) ) return false ; } return


<s> unsigned <ISA_LIT>HazardRecognizer :: getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; assert ( ( SC -> NumMicroOps != <NUM_LIT> || ( SC -> BeginGroup && ! SC ->


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameDestroyOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , IsVarArg , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT>64_ELF_FIS ) ; CCValAssign & VA = RVLocs [ <NUM_LIT> ] ; assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MVT DestVT = VA . getValVT ( ) ; MVT CopyVT = DestVT ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned SourcePhysReg = VA . getLocReg ( ) ; unsigned ResultReg = <NUM_LIT> ; if ( RetVT == CopyVT ) { const TargetRegisterClass * CpyRC = TLI . getRegClassFor ( CopyVT ) ; ResultReg = createResultReg ( CpyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( CopyVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( RetVT == <STR_LIT> || RetVT


<s> return ( __m128 ) __builtin_ia32_vfmaddss ( - ( __v4sf ) __A ,


<s> bool aarch64_harden_sls_retbr_p ( void ) { return aarch64_sls_hardening


<s> MinReservedArea = EnsureStackAlignment ( Subtarget . getFrameLowering ( ) , MinReservedArea ) ; FuncInfo -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const MCPhysReg GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const MCPhysReg FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; if ( useSoftFloat ( ) || hasSPE ( ) ) NumFPArgRegs = <NUM_LIT> ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI . CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI . CreateStackObject ( Depth , <NUM_LIT> , false ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; for ( unsigned GPRIndex = <NUM_LIT> ; GPRIndex != NumGPArgRegs ; ++ GPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( GPArgRegs [ GPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( GPArgRegs [ GPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , PtrVT ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } for ( unsigned FPRIndex = <NUM_LIT> ; FPRIndex != NumFPArgRegs ; ++ FPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( FPArgRegs [ FPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( FPArgRegs [ FPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) ,


<s> call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = <NUM_LIT> ; i < ( call_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return


<s> return ( uint16x4_t ) __builtin_aarch64_subhnv4si ( ( int32x4_t ) __a , ( int32x4_t )


<s> return ( __m128i ) __builtin_ia32_pclmulqdq128 ( ( __v2di ) __X ,


<s> if ( n >= <NUM_LIT> ) abort ( ) ; arg = default_conversion ( arg ) ; type = TREE_TYPE ( arg ) ; if ( POINTER_TYPE_P ( type ) && TREE_CODE ( arg ) == NOP_EXPR && lang_hooks . types_compatible_p ( TREE_TYPE ( arg ) , const_ptr_type_node ) && lang_hooks . types_compatible_p ( TREE_TYPE ( TREE_OPERAND ( arg , <NUM_LIT> ) ) , ptr_type_node ) ) { arg = TREE_OPERAND ( arg , <NUM_LIT> ) ; type = TREE_TYPE ( arg ) ; } if ( POINTER_TYPE_P ( decl_type ) && POINTER_TYPE_P ( type ) && TYPE_QUALS ( TREE_TYPE ( type ) ) != <NUM_LIT> ) { if ( TYPE_READONLY ( TREE_TYPE ( type ) ) && ! TYPE_READONLY ( TREE_TYPE ( decl_type ) ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , n + <NUM_LIT> , fndecl ) ; type = build_pointer_type ( build_qualified_type ( TREE_TYPE ( type ) , <NUM_LIT> ) ) ; arg = fold_convert ( type , arg ) ; } args [ n ] = arg ; types [ n ] = type ; } if ( ! VOID_TYPE_P ( TREE_VALUE ( fnargs ) ) || arglist ) return NULL ; if ( n == <NUM_LIT> ) abort ( ) ; if ( fcode == ALTIVEC_BUILTIN_VEC_STEP ) { if ( TREE_CODE ( types [ <NUM_LIT> ] ) != VECTOR_TYPE ) goto bad ; return build_int_cst ( NULL_TREE , TYPE_VECTOR_SUBPARTS ( types [ <NUM_LIT> ] ) ) ; } for ( desc = altivec_overloaded_builtins ; desc -> code && desc -> code != fcode ; desc ++ ) continue ; for ( ; desc -> code == fcode ; desc ++ ) if ( ( desc -> op1 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible ( types [ <NUM_LIT> ] , desc -> op1 ) ) && ( desc -> op2 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible ( types [ <NUM_LIT> ] , desc -> op2 ) ) && (

desc -> op3 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible ( types [ <NUM_LIT> ] , desc -> op3 ) ) ) return altivec_build_resolved_builtin ( args , n , desc ) ;


<s> A = A . addAttribute ( F . getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , <STR_LIT> ) ; F . removeAttributes ( AttributeSet :: FunctionIndex , A ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { DEBUG ( errs (


<s> AsmText += MI + <STR_LIT> ; break ; case FFSig : AsmText += MI + <STR_LIT> ; AsmText += MI + <STR_LIT> ; break ; case FDSig : AsmText += MI + <STR_LIT> ; if ( LE ) { AsmText += MI + <STR_LIT> ; AsmText += MI + <STR_LIT> ; } else { AsmText += MI + <STR_LIT> ; AsmText += MI + <STR_LIT> ; } break ; case DSig : if ( LE ) { AsmText += MI + <STR_LIT> ; AsmText += MI + <STR_LIT> ; } else { AsmText += MI + <STR_LIT> ; AsmText += MI + <STR_LIT> ; } break ; case


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MVT RegTy = MemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( RegTy , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> else llvm_unreachable ( <STR_LIT> ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_FRAME_INDEX ) { addOffset ( MIB , <NUM_LIT> ) ; } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT>


<s> LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand


<s> if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [ CPI ] . getAlignment (


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>LETarget ( ) , create<ISA_LIT>LEAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>BETarget ( ) , create<ISA_LIT>BEAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getTheThumbLETarget ( ) ,


<s> bypass = <NUM_LIT> ; PUT_CODE ( test , reverse_condition_maybe_unordered ( GET_CODE ( test ) ) ) ; } PUT_MODE ( test , QImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp2 , test ) ) ; if ( bypass ) emit_insn ( gen_andqi3 ( tmp , tmpreg , tmp2 ) ) ; else emit_insn ( gen_iorqi3 ( tmp , tmpreg , tmp2 ) ) ; } if ( ix86_compare_op0 && ix86_compare_op1 ) { equiv = simplify_gen_relational ( code , QImode , GET_MODE ( ix86_compare_op0 ) ,


<s> OW -> WriteZeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor (


<s> const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == <STR_LIT> || EltVT ==


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: ParseImmediate ( const MCExpr * & ExprVal ) { if ( getLexer ( ) . is ( AsmToken :: Colon ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind ; OperandMatchResultTy ResTy = ParseRelocPrefix ( RefKind ) ; if ( ResTy != MatchOperand_Success ) return ResTy ; const MCExpr


<s> EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node =


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR )


<s> EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success


<s> void <ISA_LIT>InstPrinter :: printAddSubImmLSL12Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printAddSubImmLSL0Operand ( MI ,


<s> return <ISA_LIT>ABIInfo ( ABI :: N64


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT>


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , StringRef TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT


<s> return Reg == <STR_LIT> || Reg == <STR_LIT> || Reg


<s> int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent


<s> O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z'


<s> for ( SDValue & Op : Ops ) if ( Op . getValueType ( ) != VT ) Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; unsigned NumElemsPow2 = PowerOf2Ceil ( NumElems ) ; EVT Pow2VT = EVT :: getVectorVT ( * DAG . getContext ( ) , ScalarVT , NumElemsPow2 ) ; if ( NumElemsPow2 != NumElems ) { for ( SDValue & Op : Ops ) { SmallVector < SDValue , <NUM_LIT> > EltsOfOp ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Idx = DAG . getIntPtrConstant ( i , DL ) ; EltsOfOp [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op , Idx ) ; } Op = DAG . getBuildVector ( Pow2VT , DL , EltsOfOp ) ; } } SDValue Res = SplitOpsAndApply ( DAG , Subtarget , DL , Pow2VT , Ops , AVGBuilder ) ; if ( NumElemsPow2 == NumElems ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && IsZExtLike ( Operands [ <NUM_LIT> ] ) ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; return AVGSplitter ( { Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] } ) ; } auto FindAddLike = [ & ] ( SDValue V , SDValue & Op0 , SDValue & Op1 ) { if ( <STR_LIT> == V . getOpcode ( ) ) { Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } if ( <STR_LIT> != V . getOpcode ( ) ) return false ; V = V . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) != VT || <STR_LIT> != V . getOpcode ( ) || ! DAG . haveNoCommonBitsSet ( V . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) ) ) return false ; Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } ; SDValue Op0 , Op1 ; if ( FindAddLike ( Operands [ <NUM_LIT> ] , Op0 , Op1 ) ) std :: swap ( Operands [ <NUM_LIT>


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex (


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) ,


<s> C &= ( ( uint64_t ) - <NUM_LIT> ) >> ( <NUM_LIT> - VT . getSizeInBits ( ) ) ; if ( C == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( C == <NUM_LIT> ) return X ; if ( isPowerOf2_64 ( C ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( Log2_64 ( C ) , DL , ShiftTy ) ) ; unsigned Log2Ceil = Log2_64_Ceil ( C ) ; uint64_t Floor = <NUM_LIT> << Log2_64 ( C ) ; uint64_t Ceil = Log2Ceil == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << Log2Ceil ; if ( C - Floor <= Ceil - C ) { SDValue Op0 = genConstMult ( X , Floor , DL , VT ,


<s> return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT>


<s> if ( ( cl == MODE_FLOAT || cl == MODE_VECTOR_INT ) && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return <NUM_LIT> ; return UNITS_PER_WORD


<s> const MCOperand & ImmOp = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegOp , Fixups , STI ) << <NUM_LIT> ) ; Bits |= ( unsigned ) ImmOp . getImm ( ) &


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_es ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Z ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm


<s> return false ; default : break ; } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = <NUM_LIT> ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = <NUM_LIT> ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return false


<s> if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Kind = MCFixupKind ( SExpr -> getFixupKind ( ) ) ; } else { bool IsPic = Ctx . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; Kind = IsPic ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind ) ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: ExpandBITCAST ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) const { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return MoveToHPR ( SDLoc ( N ) , DAG , <STR_LIT> , DstVT . getSimpleVT ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; if ( ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , MoveFromHPR ( SDLoc ( N ) , DAG , <STR_LIT> , SrcVT . getSimpleVT ( ) , Op ) ) ; if ( ! ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return SDValue ( ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { if ( SDValue Val = CombineVMOVDRRCandidateWithVecOp ( N , DAG ) ) return Val ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ,


<s> if ( B . succ_empty ( ) ) return nullptr ; auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeWeight ( & B , Dst0 ) < Prob . getEdgeWeight ( & B , Dst1 ) ; } ) ; return S -> isEHPad ( ) ? nullptr :


<s> rtx x = delegitimize_mem_from_attrs ( orig_x ) ; if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_DLTIND14R ) return gen_const_mem ( Pmode , XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ; return x


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) , FPReg ( - <NUM_LIT> ) { MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( )


<s> vmvn_u8 ( uint8x8_t __a ) { return ~


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( SrcVal . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; SDLoc Loc ( Op ) ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , CallOptions , Loc , Chain ) ; return IsStrict ? DAG . getMergeValues ( { Result , Chain } , Loc )


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = Start ; Op -> EndLoc = Start ; return Op


<s> static bool definesCPSR ( MachineInstr * MI ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( )

== <STR_LIT> && ! MO . isDead ( ) ) return true ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg )

. addReg ( SrcReg ) . addReg ( <STR_LIT> ) ;


<s> static bool CC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo

LocInfo , <STR_LIT> ArgFlags , CCState & State ) {


<s> DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI . eraseFromParent ( ) ; return BB


<s> case CallingConv :: Fast : case CallingConv :: PreserveMost : case CallingConv :: CXX_FAST_TLS : if ( ! Subtarget -> isTargetDarwin


<s> unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( )


<s> bool <ISA_LIT>AsmParser :: parseSetNoReorderDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setNoreorder


<s> unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) ==


<s> <ISA_LIT>AddressTypePromotion ( ) : FunctionPass ( ID ) ,

Func ( nullptr ) , ConsideredSExtType ( nullptr ) {


<s> bool isABI_N64 ( ) const { return ABI .


<s> registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; if ( m_direct_overloads || force_direct_overloads ) { char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name )


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr


<s> MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; }


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasXMMInt ( ) ) { PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint =


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case


<s> SpillGPRRegs . LowGPR = Low ; SpillGPRRegs . HighGPR =


<s> if ( ! isSingleSpacedVectorList ( ) ) return false ; return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList . RegNum )


<s> if ( darwin_emit_branch_islands && GET_CODE ( operands [ dest_operand_number ] ) == SYMBOL_REF && ( INTVAL ( operands [ cookie_operand_number ] ) & CALL_LONG ) ) { tree labelname ; tree funname = get_identifier ( XSTR ( operands [ dest_operand_number ] , <NUM_LIT> ) ) ; if ( no_previous_def ( funname ) ) { rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , <STR_LIT> , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ <NUM_LIT> ] == '*' ? temp_buf + <NUM_LIT> : temp_buf ; labelname = get_identifier ( label_buf ) ; add_compiler_branch_island ( labelname , funname , insn_line ( insn ) ) ; } else labelname = get_prev_label ( funname ) ; sprintf ( buf , <STR_LIT> , dest_operand_number , IDENTIFIER_POINTER ( labelname ) ) ; } else sprintf ( buf , <STR_LIT> ,


<s> if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand


<s> case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSADDSUBSAT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPredicateLoad ( Op , DAG )


<s> if ( ! ia64_dconst_0_5_rtx ) { REAL_VALUE_TYPE rv ; real_from_string ( & rv , <STR_LIT> ) ; ia64_dconst_0_5_rtx = const_double_from_real_value ( rv


<s> const unsigned LASize = FL -> getLinkageSize ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return LASize + <NUM_LIT> * ( Reg - <STR_LIT> ) ; } if ( <STR_LIT> . contains


<s> load_got_register ( ) ; return global_offset_table_rtx ; } return copy_to_reg ( sparc_got (


<s> bool isOffsetOf ( ) const { return OffsetOfLoc . getPointer


<s> if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , getZeroVector ( <STR_LIT> , Subtarget , DAG , DL ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ; } MinPos = DAG . getBitcast ( <STR_LIT> , MinPos ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MinPos ) ; MinPos = DAG . getBitcast ( SrcVT , MinPos ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; return DAG . getNode ( <STR_LIT> , DL , ExtractVT , MinPos , DAG

. getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> return ( __m64 ) __builtin_arm_wmulsmr ( ( __v4hi )


<s> <ISA_LIT>_32GNULDBackend :: ~ <ISA_LIT>_32GNULDBackend ( )


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; unsigned RegSize = MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) ; bool Is32Bit = ( RegSize == <NUM_LIT> ) ; const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ) { if ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) { auto TstMI = MIRBuilder . buildInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { ZReg } , { LHS } ) ; TstMI . addImm ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) ; constrainSelectedInstRegOperands ( * TstMI , TII , TRI , RBI ) ; return & * TstMI ; } } if ( auto Fns = selectLogicalShiftedRegister ( RHS ) ) return emitInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { ZReg } , { LHS


<s> x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x


<s> case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , const1_rtx ) ) ; code = NE ; } break ; case LE : case UNLE : if ( code == LE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = LTU ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case EQ : case UNEQ : if ( code == EQ && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case NE : case LTGT : if ( code == NE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } break ; case UNORDERED : emit_insn ( gen_testqi_ext_ccno_0 ( scratch ,


<s> void <ISA_LIT>WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; MCWinCOFFStreamer :: finishImpl


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : LLVM_FALLTHROUGH ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false


<s> if ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && Mask [ <NUM_LIT> ] != - <NUM_LIT> && ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) != ( Mask [ <NUM_LIT> ] <


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) )


<s> std :: string <ISA_LIT>ArchFeature ; <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( )


<s> assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file


<s> bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( )


<s> uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> :


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { if ( <STR_LIT> ( GO ) && ! GO -> hasSection ( ) && Kind . isReadOnly


<s> } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 ,


<s> if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; return MCDisassembler ::


<s> Value * <ISA_LIT>IREmitter :: visitMEMBARRIER ( const SDNode *


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> Reg2 = temp ; } EmitInstrRegReg ( STI , MovOpc , Reg1 , FPReg1 ) ; EmitInstrRegReg ( STI , MovOpc


<s> assert ( ( Kind == k_Register ) && <STR_LIT> ) ; return Reg


<s> FOR_EACH_INSN_USE ( ref , insn ) if ( DF_REF_REGNO ( ref ) == REGNO ( * op ) ) { gcc_assert ( ! DF_REF_CHAIN ( ref ) ) ; break ; } * op = gen_rtx_SUBREG ( V2DImode , * op , <NUM_LIT> ) ; } else if ( CONST_INT_P ( * op ) ) { rtx vec_cst ; rtx tmp = gen_rtx_SUBREG ( V2DImode , gen_reg_rtx ( DImode ) , <NUM_LIT> ) ; if ( constm1_operand ( * op , GET_MODE ( * op ) ) ) vec_cst = CONSTM1_RTX ( V2DImode ) ; else vec_cst = gen_rtx_CONST_VECTOR ( V2DImode , gen_rtvec ( <NUM_LIT> , * op , const0_rtx ) ) ; if ( ! standard_sse_constant_p (


<s> SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> SDValue RHS = SVN -> getOperand ( <NUM_LIT> ) ; auto Mask = SVN -> getMask ( ) ; int NumElts = LHS . getValueType ( ) . getVectorNumElements ( ) ; SDValue Res ( SVN , <NUM_LIT> ) ; SDLoc dl ( SVN ) ; if ( ! Subtarget . isLittleEndian ( ) ) return Res ; if ( Mask [ <NUM_LIT> ] >= NumElts && LHS . getOpcode ( ) != <STR_LIT> && RHS . getOpcode ( ) != <STR_LIT> ) { std :: swap ( LHS , RHS ) ; Res = DAG . getCommutedVectorShuffle ( * SVN ) ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } SmallVector < int , <NUM_LIT> > ShuffV ( Mask . begin ( ) , Mask . end ( ) ) ; SDValue SToVLHS = isScalarToVec ( LHS ) ; SDValue SToVRHS = isScalarToVec ( RHS ) ; if ( SToVLHS || SToVRHS ) { int NumEltsIn = SToVLHS ? SToVLHS . getValueType ( ) . getVectorNumElements ( ) : SToVRHS . getValueType ( ) . getVectorNumElements ( ) ; int NumEltsOut = ShuffV . size ( ) ; int LHSMaxIdx = - <NUM_LIT> ; int RHSMinIdx = - <NUM_LIT> ; int RHSMaxIdx = - <NUM_LIT> ; int HalfVec = LHS . getValueType ( ) . getVectorNumElements ( ) / <NUM_LIT> ; if ( SToVLHS ) { LHSMaxIdx = NumEltsOut / NumEltsIn ; SToVLHS = getSToVPermuted ( SToVLHS , DAG ) ; if ( SToVLHS . getValueType ( ) != LHS . getValueType ( ) ) SToVLHS = DAG . getBitcast ( LHS . getValueType ( ) , SToVLHS ) ; LHS = SToVLHS ; } if ( SToVRHS ) { RHSMinIdx = NumEltsOut ; RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx ; SToVRHS = getSToVPermuted ( SToVRHS , DAG ) ; if ( SToVRHS . getValueType ( ) != RHS . getValueType ( ) ) SToVRHS = DAG . getBitcast ( RHS . getValueType ( ) , SToVRHS ) ; RHS = SToVRHS ; } fixupShuffleMaskForPermutedSToV ( ShuffV , LHSMaxIdx , RHSMinIdx , RHSMaxIdx , HalfVec ) ; Res = DAG . getVectorShuffle ( SVN -> getValueType ( <NUM_LIT> ) , dl , LHS , RHS , ShuffV ) ; if ( ! isa < ShuffleVectorSDNode > ( Res ) ) return Res ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } if ( ! isSplatBV ( RHS ) ) return Res ; if ( ! isAlternatingShuffMask ( Mask , NumElts ) ) return


<s> if ( clean_p ) { sc -> cached_can_issue_more = <NUM_LIT> ; sc -> last_scheduled_insn = NULL ; sc -> load_store_pendulum = <NUM_LIT> ; sc -> divide_cnt = <NUM_LIT> ; sc -> vec_pairing = <NUM_LIT> ; } else { sc -> cached_can_issue_more = cached_can_issue_more ; sc -> last_scheduled_insn


<s> if ( Header != TheLoop -> getLoopLatch ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } Function & F = * Header -> getParent ( ) ; M = F . getParent ( ) ; DL = & M -> getDataLayout ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LoopAccessInfo LAI ( L , SE , TLI , AA , DT , LI ) ; bool Changes = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changes = MatchSMLAD (


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandISELPass ( ) { return new <ISA_LIT>ExpandISEL (


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> isNullValue ( ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> isOne ( ) && cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand (


<s> return false ; } bool Gatscat = true ; for ( User * U : I -> users ( ) ) { if ( ! isa < Instruction > ( U ) ) return false ; if ( isa < GetElementPtrInst > ( U ) || isGatherScatter ( dyn_cast < IntrinsicInst > ( U ) ) ) { return Gatscat ; } else { unsigned OpCode = cast < Instruction > ( U )


<s> DCRegisterSema * create<ISA_LIT>DCRegisterSema ( StringRef TT , const MCRegisterInfo & MRI , const MCInstrInfo & MII ) { return new <ISA_LIT>RegisterSema ( MRI , MII


<s> void printlea64_32mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printLeaMemReference ( MI , OpNo , O


<s> StringRef Name = getIndexedValueName ( BaseName ) ; Instruction * Res = dyn_cast < Instruction > ( IRB -> CreateSub ( Op0 , Op1 , Name ) ) ; Res -> setDebugLoc ( N -> getDebugLoc ( ) ) ; VisitMap [ N ] = Res ; return Res


<s> int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { KnownUndef . setBit ( i ) ; continue ; } if ( ( M >= <NUM_LIT> && M < Size && V1IsZero ) || ( M >= Size && V2IsZero ) ) { KnownZero . setBit ( i ) ; continue ; } SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) KnownUndef . setBit ( i ) ; if ( <STR_LIT> ( Op ) ) KnownZero . setBit ( i ) ; else if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { APInt Val = Cst -> getAPIntValue ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } else if ( ConstantFPSDNode * Cst = dyn_cast < ConstantFPSDNode > ( Op ) ) { APInt Val = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } continue ; } if ( ( V . getNumOperands ( ) % Size ) == <NUM_LIT> ) { int Scale = V -> getNumOperands ( ) / Size ; bool AllUndef = true ; bool AllZero = true ; for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) { SDValue Op = V . getOperand ( ( M * Scale ) + j ) ; AllUndef &= Op . isUndef ( ) ; AllZero &= <STR_LIT> ( Op


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; return RegBits


<s> return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasFPUDelaySlot ( I ) ;

} , [ this ] ( auto & IInSlot , auto & I ) -> bool {


<s> else if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << PC_REGNUM


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Value >>= <NUM_LIT> ; case <STR_LIT> : unsigned Hi4 = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; unsigned Lo12 = Value & <NUM_LIT> ; Value = ( Hi4 << <NUM_LIT> ) | ( Lo12 ) ; return Value ; } return


<s> if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else return true ; switch ( Mode ) { default : return true ; case 'x' : Reg = <STR_LIT> + Index ; break ; case 't' : Reg = <STR_LIT> + Index ; break ; case 'g' : Reg = <STR_LIT> + Index ; break ; } if ( EmitPercent ) O << '%' ; O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return false


<s> if ( csky_tls_symbol_p ( x ) ) return csky_legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( is_csky_address_register_rtx_p ( xop0 , <NUM_LIT> ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset > CSKY_LD16_MAX_OFFSET ( mode ) && offset <= ( CSKY_ADDI16_MAX_IMM + CSKY_LD16_MAX_OFFSET ( mode ) ) ) { HOST_WIDE_INT new_ld_offset = offset & CSKY_LD16_OFFSET_MASK ( mode ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - new_ld_offset ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , new_ld_offset ) ; } else if ( offset < <NUM_LIT> && offset >= ( - CSKY_SUBI16_MAX_IMM ) ) x = force_operand ( x , NULL_RTX ) ; else if ( offset > CSKY_LD16_MAX_OFFSET ( mode ) || offset < <NUM_LIT> ) { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } if ( is_csky_address_register_rtx_p ( xop1 , <NUM_LIT> ) && ! is_csky_address_register_rtx_p ( xop0 , <NUM_LIT> ) ) { xop0 = force_operand ( xop0


<s> if ( TT . isOSFuchsia ( ) ) return llvm :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return llvm :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return llvm :: make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable ( <STR_LIT>


<s> return __builtin_aarch64_suqaddv8hi_ssu ( __a ,


<s> if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved


<s> emit_insn ( gen_trap ( ) ) ; return ; } if ( current_function_limit_stack ) { if ( REG_P ( stack_limit_rtx ) && REGNO ( stack_limit_rtx ) > <NUM_LIT> && REGNO ( stack_limit_rtx ) <= <NUM_LIT> ) { emit_insn ( TARGET_32BIT ? gen_addsi3 ( tmp_reg , stack_limit_rtx , GEN_INT ( size ) ) : gen_adddi3 ( tmp_reg , stack_limit_rtx , GEN_INT ( size ) ) ) ; emit_insn ( gen_cond_trap ( LTU , stack_reg , tmp_reg , const0_rtx ) ) ; } else if ( GET_CODE ( stack_limit_rtx ) == SYMBOL_REF && TARGET_32BIT && DEFAULT_ABI == ABI_V4 ) { rtx toload = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , stack_limit_rtx , GEN_INT ( size ) ) ) ; emit_insn ( gen_elf_high ( tmp_reg , toload ) ) ; emit_insn ( gen_elf_low ( tmp_reg , tmp_reg , toload ) ) ; emit_insn ( gen_cond_trap ( LTU , stack_reg , tmp_reg , const0_rtx ) ) ; } else warning ( <NUM_LIT> , <STR_LIT> ) ; } if ( copy_r12 || ! TARGET_UPDATE ) emit_move_insn ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , stack_reg ) ; if ( TARGET_UPDATE ) { if ( size > <NUM_LIT> ) { if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , todec ) ; try_split ( PATTERN ( insn ) , insn , <NUM_LIT>


<s> if ( ! ST -> hasMVEFloatOps ( ) ) return SDValue ( ) ; SDLoc dl ( BV ) ; EVT VT = BV . getValueType ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( BV . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( BV . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Op0 = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Op1 = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> || Op1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ;


<s> OS << <STR_LIT> ; if ( LPAC :: isPreOp ( AluCode ) ) OS << <STR_LIT> ; OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( RegOp . getReg ( ) ) ; if ( LPAC :: isPostOp ( AluCode ) )


<s> MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( EltVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > (


<s> bool <ISA_LIT>InstPrinter :: isV9 ( const MCSubtargetInfo & STI ) const { return ( STI . getFeatureBits ( )


<s> if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < <NUM_LIT>


<s> bool <ISA_LIT>Subtarget :: isAAPCS_ABI ( ) const { assert ( TM . TargetABI

!= <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_UNKNOWN ) ;


<s> const MCSection * FindAssociatedSection ( ) const override { return getSubExpr ( ) -> FindAssociatedSection


<s> assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t (


<s> SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false


<s> unsigned VaListSize = Subtarget -> isTargetDarwin ( ) ? <NUM_LIT> : <NUM_LIT> ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( VaListSize , <STR_LIT> ) , <NUM_LIT> , false

, false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned FIOperandNo = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return <NUM_LIT> ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return <NUM_LIT> ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return <NUM_LIT>


<s> if ( <STR_LIT> ( N0 . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( Opcode == <STR_LIT> && ( ShiftVal + <NUM_LIT> ) == NumBitsPerElt && N0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( Opcode == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N1 == N0 . getOperand ( <NUM_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( N00 ) ; if ( ShiftVal . ult ( NumSignBits ) ) return N00 ; } if ( LogicalShift && ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , true , DAG , Subtarget ) ) return Res ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned ShiftImm = ShiftVal . getZExtValue ( ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt <<= ShiftImm ; else if ( <STR_LIT> == Opcode ) Elt . ashrInPlace ( ShiftImm ) ; else Elt . lshrInPlace ( ShiftImm ) ; } return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) , DAG , SDLoc ( N ) ) ; } return SDValue


<s> if ( load ) { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 !=


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem , align ) ; if ( align < <NUM_LIT> ) { rtx unspec = gen_rtx_UNSPEC ( V4SFmode , gen_rtvec ( <NUM_LIT> , mem ) , UNSPEC_LOADU ) ; emit_insn ( gen_rtx_SET ( reg , unspec


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI ) ; MBBI =


<s> static bool isShiftedMask ( uint64_t Mask , EVT VT ) { assert ( VT == <STR_LIT> || VT == <STR_LIT>


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { std :: vector < EVT > VTs ; VTs . push_back ( <STR_LIT> ) ; VTs . push_back ( <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC