<s> if ( ! isUndefUpperHalf ( Mask ) ) return false ; int Len = HalfSize ; for ( ; Len > <NUM_LIT> ; -- Len ) if ( ! Zeroable [ Len - <NUM_LIT> ] ) break ; assert ( Len > <NUM_LIT> && <STR_LIT> ) ; SDValue Src ; int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( i > M || M


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) )

, TII ( * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> return ( __m128 ) __builtin_ia32_cmpunordps ( ( __v4sf )


<s> void <ISA_LIT>_64Relocator :: applyDebugStringOffset ( Relocation & pReloc , uint32_t pOffset ) { pReloc . target ( )


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( ! is128BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) return - <NUM_LIT> ; int Rotation = matchShuffleAsElementRotate ( V1 , V2


<s> DomainValue * SSEDomainFixPass :: Alloc ( int domain ) { DomainValue * dv = Avail . empty ( ) ? new (

Allocator . Allocate ( ) ) DomainValue :


<s> return GV != <NUM_LIT> || CP != <NUM_LIT> || ES !=

<NUM_LIT> || JT != - <NUM_LIT> || BlockAddr != <NUM_LIT> ;


<s> void setBytesToPopOnReturn ( unsigned bytes ) { BytesToPopOnReturn = bytes


<s> if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return true ; } else { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumedToken ) ) ; if ( <ISA_LIT>Operand * Op = ParseOperand ( ) ) { Operands . push_back ( Op ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || getLexer ( ) . getTok ( ) . getIdentifier ( ) != <STR_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc (


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask (


<s> static unsigned computeBytesPoppedByCallee ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , ImmutableCallSite * CS ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC

|| CC == CallingConv :: HiPE ) return <NUM_LIT> ;


<s> if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; } if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) ==


<s> if ( MBBI == MBB . begin ( ) ) return false ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; MachineBasicBlock :: iterator PrevInst = std :: prev ( MBBI ) ; if ( PrevInst -> isBundledWithSucc ( ) ) return false ; const TargetInstrInfo * TII = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; switch ( PrevInst -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return combineRestoreADD ( MBBI , PrevInst , TII ) ; break ; case <STR_LIT> : case <STR_LIT> : return combineRestoreOR ( MBBI , PrevInst , TII ) ; break ; case <STR_LIT> : return combineRestoreSETHIi ( MBBI , PrevInst , TII ) ; break ; } return


<s> break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList


<s> return isRegIdx ( ) && RegIdx . Kind & RegKind_FGR &&


<s> const DebugLoc & DbgLoc = I . getDebugLoc ( ) ; unsigned Opc = getLoadStoreOp ( DstTy , RegBank , TargetOpcode :: G_LOAD , Alignment ) ; const ConstantFP * CFP = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; unsigned CPI = MF . getConstantPool ( ) -> getConstantPoolIndex ( CFP , Alignment . value ( ) ) ; MachineInstr * LoadInst = nullptr ; unsigned char OpFlag = STI . classifyLocalReference ( nullptr ) ; if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { Register AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Alignment ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit ( ) ) { unsigned PICBase = <NUM_LIT> ; if ( OpFlag == <STR_LIT> || OpFlag == <STR_LIT> ) { return false ; } else if ( STI . is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; LoadInst = addConstantPoolReference ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , CPI , PICBase , OpFlag ) ; } else return false ; constrainSelectedInstRegOperands ( * LoadInst , TII


<s> Parser . eatToEndOfStatement ( ) ; return false ; } const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: Create ( Parser . getTok ( ) . getIdentifier ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ , getContext ( ) ) ; Lex (


<s> unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT>


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: FP_TO_SINTHelper ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getValueType ( ) . getSimpleVT ( ) <= <STR_LIT> && Op . getValueType ( ) . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && Op . getValueType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; switch ( Op . getValueType ( ) . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; Chain = Value .


<s> bool isFCCAsmReg ( ) const { if ( ! ( isRegIdx ( ) && RegIdx . Kind & RegKind_FCC ) )


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned ImmReg = DstReg ; if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg = ATReg ; } if ( loadImmediate ( ImmValue , ImmReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out , STI ) ) return true ; TOut . emitRRR ( OpRegCode , DstReg , ImmReg , SrcReg ,


<s> } if ( size <= <NUM_LIT> * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i <= size ; i += probe_interval ) { rtx insn = pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - probe_interval ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_stack_probe ( stack_pointer_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } HOST_WIDE_INT residual = ( i - probe_interval - size ) ; if ( residual ) { pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( residual ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; if ( protection_area ) emit_stack_probe ( stack_pointer_rtx ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; if ( sr . saved ) size -= UNITS_PER_WORD ; HOST_WIDE_INT rounded_size = size & - probe_interval ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ; rtx insn ; if ( address_no_seg_operand ( addr , Pmode ) ) insn = emit_insn ( gen_rtx_SET ( sr . reg , addr ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; insn = emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , sr . reg , m -> fs . cfa_offset + rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx size_rtx = GEN_INT ( rounded_size ) ; insn = emit_insn ( gen_adjust_stack_and_probe ( Pmode , sr . reg , sr . reg , size_rtx ) ) ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) { m -> fs . cfa_offset += rounded_size ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . cfa_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } m -> fs . sp_offset += rounded_size ; emit_insn ( gen_blockage ( ) ) ; if ( size != rounded_size ) { pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( rounded_size - size ) , - <NUM_LIT> , m -> fs


<s> return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; bool OffsetFitsMnemonic = ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ? isUInt < <NUM_LIT> > ( Offset ) : isInt < <NUM_LIT> > ( Offset ) ; if ( ! noImmForm && ( ( OffsetFitsMnemonic && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC


<s> MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> ,


<s> if ( Opcode == <STR_LIT> ) { SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Val -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; bool isInteger = LHS . getValueType ( ) . isInteger ( ) ; if ( Negate ) CC = getSetCCInverse ( CC , isInteger ) ; SDLoc DL ( Val ) ; if ( isInteger ) { OutCC = changeIntCCTo<ISA_LIT>CC ( CC ) ; } else { assert ( LHS . getValueType ( ) . isFloatingPoint ( ) ) ; <STR_LIT> ExtraCC ; changeFPCCToAND<ISA_LIT>CC ( CC , OutCC , ExtraCC ) ; if ( ExtraCC != <STR_LIT> ) { SDValue ExtraCmp ; if ( ! CCOp . getNode ( ) ) ExtraCmp = emitComparison ( LHS , RHS , CC , DL , DAG ) ; else ExtraCmp = emitConditionalComparison ( LHS , RHS , CC , CCOp , Predicate , ExtraCC , DL , DAG ) ; CCOp = ExtraCmp ; Predicate = ExtraCC ; } } if ( ! CCOp ) return emitComparison ( LHS , RHS , CC , DL , DAG ) ; return emitConditionalComparison ( LHS , RHS , CC , CCOp , Predicate , OutCC , DL , DAG ) ; } assert ( Val -> hasOneUse ( ) && <STR_LIT> ) ; bool IsOR = Opcode == <STR_LIT> ; SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; bool MustBeFirstL ; bool ValidL = canEmitConjunction ( LHS , CanNegateL , MustBeFirstL , IsOR ) ; assert ( ValidL && <STR_LIT> ) ; ( void ) ValidL ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateR ; bool MustBeFirstR ; bool ValidR = canEmitConjunction ( RHS , CanNegateR , MustBeFirstR , IsOR ) ; assert ( ValidR && <STR_LIT> ) ; ( void ) ValidR ; if ( MustBeFirstL ) { assert ( ! MustBeFirstR && <STR_LIT> ) ; std :: swap ( LHS , RHS ) ; std :: swap ( CanNegateL , CanNegateR ) ; std :: swap ( MustBeFirstL , MustBeFirstR ) ; } bool NegateR ; bool NegateAfterR ; bool NegateL ; bool NegateAfterAll ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL ) { assert ( CanNegateR && <STR_LIT> ) ; assert ( ! MustBeFirstR && <STR_LIT> ) ; assert ( ! Negate ) ; std :: swap ( LHS , RHS ) ; NegateR = false ; NegateAfterR = true ; } else { NegateR = CanNegateR ; NegateAfterR = !


<s> { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext *


<s> if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > ( V ) -> getOpcode ( ) ; return Opc == Instruction :: AShr || Opc == Instruction :: SDiv


<s> return ( GET_CODE ( x ) == CONST_INT ? <NUM_LIT> : GET_CODE

( x ) == PLUS ? <NUM_LIT> : <NUM_LIT> ) ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i

) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i ) ) return false ;


<s> static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE41 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE41CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE2 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE1 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE1CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; unsigned CmpOpcode ; if ( Ty -> isFPOrFPVectorTy ( ) ) { CmpOpcode = Instruction :: FCmp ; } else


<s> getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t ReservedCPU64Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : if ( current_function_is_leaf ) offset = - current_frame_info . total_size ; else offset = - ( current_frame_info . total_size - current_function_outgoing_args_size - <NUM_LIT> ) ; break ; case STACK_POINTER_REGNUM : if ( current_function_is_leaf ) offset = <NUM_LIT> ; else offset = <NUM_LIT> + current_function_outgoing_args_size ; break ; default : gcc_unreachable (


<s> rtx set = PATTERN ( insn ) ; rtx concat = XEXP ( set , <NUM_LIT> ) ; rtx src0 = XEXP ( concat , <NUM_LIT> ) ; XEXP ( concat , <NUM_LIT> ) = XEXP ( concat , <NUM_LIT> ) ; XEXP ( concat , <NUM_LIT> ) = src0 ; INSN_CODE ( insn ) = -


<s> if ( VT == <STR_LIT> ) return Subtarget . hasDSP


<s> else if ( IDVal . startswith ( <STR_LIT> ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setParsingInlineAsm ( false ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; getParser ( ) . setParsingInlineAsm ( true ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; return true


<s> static int unspec_cond_fcmla ( int rot ) { switch ( rot ) { case <NUM_LIT> :


<s> unsigned Opcode = PrevMI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI . getOperand ( PrevMI . getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> )

|| Opcode == <STR_LIT> ) && <STR_LIT> ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return false ; } R1 =


<s> for ( auto * BB : MBB -> successors ( ) )

if ( BB -> isLiveIn ( <STR_LIT> ) ) return true ;


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLoadStore ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const TargetInstrInfo * TII , bool & Advance , MachineBasicBlock :: iterator & I ) { MachineInstr * MI = MBBI ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; int Opcode = MI -> getOpcode ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isAM5 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool isAM2 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isAM2 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isAM5 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isT2i32Load ( Opcode ) || isT2i32Store ( Opcode ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; bool isLd = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isLd && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base ) return false ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; bool DoMerge = false ; <STR_LIT> AddSub = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode ) ; MBB . erase ( PrevMBBI ) ; } } if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode


<s> emit_insn ( set_func ( target , target , val , GEN_INT ( elt ) ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == <NUM_LIT> ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( mask , <NUM_LIT> , i ) = GEN_INT ( i ) ; for ( i = <NUM_LIT> ; i < width ; ++ i ) XVECEXP ( mask , <NUM_LIT> , elt * width + i ) = GEN_INT ( i + <NUM_LIT> ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , <NUM_LIT> ) ) ; if ( BYTES_BIG_ENDIAN ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; else { rtx notx = gen_rtx_NOT ( V16QImode , force_reg (


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GV -> getValueType (


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) && ( MI . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> )


<s> return DecodeMem ( Inst , insn , Address , Decoder , false ,


<s> unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( LoadedVT == <STR_LIT> && isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match =


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; return nullptr ; } for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isDeadDef ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return & * I ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumLiveDstRejs ; return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return & * I ; } PhysRegInfo PRI = AnalyzePhysRegInBundle ( * I , <STR_LIT> , TRI


<s> if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type


<s> EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> ) ; uint64_t nextOffset = FPROffset


<s> case VectorElem : OriginalMCID = & TII -> get ( <STR_LIT> ) ; ReplInstrMCID . push_back ( & TII -> get ( <STR_LIT> ) ) ; ReplInstrMCID . push_back ( & TII -> get ( <STR_LIT> ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) return false ; break ; case Interleave : std :: string Subtarget = SchedModel . getSubtargetInfo ( ) -> getCPU ( ) ; if ( InterlEarlyExit . find ( Subtarget ) != InterlEarlyExit . end ( ) ) return InterlEarlyExit [ Subtarget ] ; for ( auto & I : IRT ) { OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) { InterlEarlyExit [ Subtarget ] = false ; return false ; } ReplInstrMCID . clear ( )


<s> if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result

, DAG . getConstant ( Offset , getPointerTy ( ) ) ) ;


<s> SDValue EXTRACT_VECTOR_ELT ( SDValue Vec , unsigned Idx ) { return EXTRACT_VECTOR_ELT ( Vec , Constant


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) return SDValue ( ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue ZeroVec = DAG . getUNDEF ( <STR_LIT> ) ; SDValue VecVal ; if ( VT == <STR_LIT> ) { VecVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; VecVal = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , ZeroVec , VecVal ) ; } else { VecVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; } SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecVal ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG

. getConstant ( <STR_LIT> , <STR_LIT> ) , CtPop ) ;


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC ) ) return false ; updateValueMap ( I , ResultReg ) ; return


<s> if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table


<s> return ( __m128i ) __builtin_ia32_pminuw128 ( ( __v8hi ) __X ,


<s> else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn


<s> Inst . addOperand ( MCOperand :: CreateReg ( RegOrOffset ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> )


<s> if ( VT != <STR_LIT> ) { BuildMI ( mainMBB , DL , TII -> get ( CMOVOpc ) , t1 ) . addReg ( SrcReg ) . addReg ( AccReg ) ; } else { const TargetRegisterClass * RC32 = getRegClassFor ( <STR_LIT> ) ; unsigned SrcReg32 = MRI . createVirtualRegister ( RC32 ) ; unsigned AccReg32 = MRI . createVirtualRegister ( RC32 ) ; unsigned t2 = MRI . createVirtualRegister ( RC32 ) ; unsigned Undef = MRI . createVirtualRegister ( RC32 ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Undef ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , SrcReg32 ) . addReg ( Undef ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , AccReg32 ) . addReg ( Undef ) . addReg ( AccReg ) . addImm ( <STR_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( CMOVOpc ) , t2 ) . addReg ( SrcReg32 ) . addReg ( AccReg32 ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: COPY ) , t1 ) . addReg ( t2 , <NUM_LIT> , <STR_LIT> ) ; } } else { assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned SelOpc = getPseudoCMOVOpc ( VT ) ; <STR_LIT> CC = <STR_LIT> ( CMOVOpc ) ; assert ( CC != <STR_LIT> && <STR_LIT> ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( SelOpc ) , t1 ) . addReg ( SrcReg ) . addReg ( AccReg ) . addImm ( CC ) ; mainMBB = EmitLoweredSelect ( MIB , mainMBB ) ; } break ; } } BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: COPY ) , AccPhyReg ) . addReg ( AccReg ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( LCMPXCHGOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; MIB . addReg ( t1 ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> )


<s> MCInst prefix ; prefix . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( prefix ) ; } MCSymbolRefExpr :: VariantKind SRVK ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLD ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MCSymbol * sym = MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) ; const MCSymbolRefExpr * symRef = MCSymbolRefExpr :: Create ( sym , SRVK , context ) ; MCInst LEA ; if ( is64Bits ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> )


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand &


<s> if ( ResVT == <STR_LIT> || ! Subtarget . hasP8Vector ( ) || cast < StoreSDNode > ( N ) -> isTruncatingStore ( ) || ! ValidTypeForStoreFltAsInt ) return SDValue ( ) ; if ( ResVT . getScalarSizeInBits ( ) == <NUM_LIT> ) { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; } unsigned ConvOpcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( ConvOpcode , dl , ResVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; unsigned ByteSize = Op1VT . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Val , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( ByteSize , dl , false ) , DAG . getValueType ( Op1VT ) } ; Val = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , cast < StoreSDNode > ( N ) -> getMemoryVT ( ) , cast < StoreSDNode > ( N ) -> getMemOperand ( ) ) ; DCI . AddToWorklist ( Val . getNode


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQQDecoderTable [


<s> if ( MBBI == MBB . end ( ) ) return false ; } Register PredReg ; return getITInstrPredicate ( * MBBI ,


<s> MachineInstr * setRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT>


<s> EVT ResVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) ; SDValue Cmp ; if ( IsStrict ) { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> , Chain , true ) ; Chain = Cmp . getValue ( <NUM_LIT> ) ; } else { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> ) ; } Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue FltOfs = DAG . getSelect ( DL , TheVT , Cmp , DAG . getConstantFP ( <NUM_LIT> , DL , TheVT ) , ThreshVal ) ; if ( IsStrict ) { Value = DAG . getNode ( <STR_LIT> , DL , { TheVT , <STR_LIT> } , { Chain , Value , FltOfs } ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } else Value = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , FltOfs ) ; } MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MPI ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; unsigned FLDSize = TheVT . getStoreSize ( ) ; assert ( FLDSize <= MemSize && <STR_LIT> ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , FLDSize , FLDSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , TheVT , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , MemSize ,


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function *


<s> for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first ) ) ; cast < MCSymbolXCOFF > ( I . second ) -> setContainingCsect ( TCEntry ) ; OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> EmitLabel ( I . second ) ; TS . emitTCEntry ( * I .


<s> return ( int8x16_t ) __builtin_neon_vld1v16qi ( ( const __builtin_neon_qi


<s> if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val == INT32_MIN ) || ( Val > -


<s> selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu ->


<s> static inline uint64_t decodeAdvSIMDModImmType2 ( uint8_t Imm ) { uint64_t EncVal =


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return <NUM_LIT> ; case


<s> tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; Instructions . push_back ( tmpInst )


<s> rtx set_src ( void ) const { return set_rtx == NULL_RTX ? NULL_RTX : XEXP ( set_rtx ,


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom )


<s> void ELF<ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind


<s> unsigned FixedObject = getFixedObjectSize ( MF , AFI , IsWin64 , false ) ; unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF . getFrameInfo (


<s> int _U_Qfuneq ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD |


<s> if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] * <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( ( Mask [ <NUM_LIT> ] * <NUM_LIT> ) + <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] * <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( ( Mask [ <NUM_LIT> ] * <NUM_LIT> ) + <NUM_LIT> ) } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; } if ( IsBlendSupported ) return lowerShuffleAsDecomposedShuffleBlend ( DL , <STR_LIT> , V1 , V2 , Mask ,


<s> static void iq2000_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; for ( auto & MBB : MF ) if ( processMachineBasicBlock ( MBB ) ) Changed = true ; return


<s> MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugValue ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; std :: sort ( Candidates . begin ( ) , Candidates . end ( ) , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti ||


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return true ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ; if ( ! VT . isPow2VectorType ( ) ) return false ; return true


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , Subtarget . isABI_O32 ( ) , Subtarget . isFP64bit ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ]


<s> Node = emitIntrinsicWithCCAndChain ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , <NUM_LIT> ) ; case <STR_LIT> : Node = emitIntrinsicWithCC ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , Node -> getNumValues ( ) - <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG

. getConstant ( C . ICmpType , DL , <STR_LIT> ) ) ;


<s> static bool isFPR64 ( unsigned Reg , unsigned SubReg , const MachineRegisterInfo * MRI ) { if ( Register :: isVirtualRegister ( Reg ) ) return ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <NUM_LIT> ) || ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <STR_LIT> ) ; return ( <STR_LIT> . contains ( Reg ) && SubReg == <NUM_LIT> ) ||

( <STR_LIT> . contains ( Reg ) && SubReg == <STR_LIT> ) ;


<s> debug_rtx ( x ) ; if ( reg_class_subset_p ( rclass , CR_REGS ) ) rv = mep_secondary_copro_reload_class ( rclass , x ) ; else if ( MEP_NONGENERAL_CLASS ( rclass ) && ( mep_nonregister ( x ) || mep_nongeneral_reg


<s> ELFFileFormat * file_format = getTarget ( ) . getOutputFormat ( ) ; if ( ResolveInfo :: ThreadLocal == pSym . type ( ) ) bss_sect_hdr = & file_format -> getTBSS ( ) ; else bss_sect_hdr = & file_format -> getBSS ( ) ; SectionData * bss_data = NULL ; if ( bss_sect_hdr -> hasSectionData ( ) ) bss_data = bss_sect_hdr -> getSectionData ( ) ; else bss_data = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_data , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size


<s> if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; if ( TT . getEnvironment ( ) == llvm :: Triple :: GNUABIN32 ) return <ISA_LIT>ABIInfo :: N32 ( ) ; assert ( Options . getABIName ( ) . empty ( ) && <STR_LIT> ) ; if ( TT . isMIPS64 ( ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; return <ISA_LIT>ABIInfo :: O32 (


<s> auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; const GlobalObject * GO = cast < GlobalObject > ( G -> getGlobal ( ) ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( GO -> getName ( ) ) ) ) ; if ( GO && GO -> isDeclaration ( ) && ! S -> hasContainingCsect ( ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( S -> getName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; S -> setContainingCsect ( Sec ) ; } EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) return DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , UsePlt


<s> if ( ( VT == <STR_LIT> && OpVT == <STR_LIT> ) || ( VT == <STR_LIT> && OpVT == <STR_LIT> ) ) { if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( OpVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( OpVT , dl , Op , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2


<s> if ( * pinsn && reg_referenced_p ( x , * pinsn ) )


<s> static __inline __m128d __attribute__ ( ( __always_inline__ ) ) _mm_load_pd ( double const * __P ) { return * ( __m128d *


<s> bool isRegInClass ( unsigned Reg , const TargetRegisterClass * RC ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return RC -> hasSubClassEq ( MRI


<s> status = DecodeI64RegisterClass ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( sy ) ) ) ; } MI . addOperand ( MCOperand :: createImm ( simm32 ) ) ; return MCDisassembler


<s> emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x_lo , y_lo ) ) ; rtx x_hi = operand_subword ( x , <NUM_LIT> , <NUM_LIT> , TImode ) ; rtx y_hi = operand_subword ( y , <NUM_LIT> , <NUM_LIT> , TImode ) ; emit_insn ( gen_ccmpccdi ( cc_reg , cc_reg , x_hi , y_hi , gen_rtx_EQ ( cc_mode , cc_reg , const0_rtx ) , GEN_INT ( AARCH64_EQ ) ) ) ; } else { cc_mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x , y ) ) ; } return cc_reg


<s> if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; } c_mask = ( TARGET_64BIT_MS_ABI ? ( <NUM_LIT> << <NUM_LIT> ) : TARGET_64BIT ? ( <NUM_LIT> << <NUM_LIT> ) : ( <NUM_LIT> << <NUM_LIT> ) ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > <NUM_LIT> ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs


<s> if ( FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned SrcReg ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SrcReg = GPR32ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : SrcReg = GPR64ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : LLVM_FALLTHROUGH ; case <STR_LIT> : SrcReg = XMMArgRegs [ FPRIdx ++ ] ; break ; } Register DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & Arg


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , IE = MBB . end ( ) ; I != IE ; ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = false ; else if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = true ; ++ I ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned OutReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First =


<s> I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) && MMI . usePreciseUnwindInfo ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( ! MMI . usePreciseUnwindInfo ( ) ) CFAOffset += InternalAmt ; CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } return ; } if ( isDestroy &&


<s> SDValue Ext = Store -> getValue ( ) ; auto ExtOpCode = Ext . getOpcode ( ) ; if ( ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> ) return SDValue ( ) ; SDValue Orig = Ext -> getOperand ( <NUM_LIT> ) ; if ( Store -> getMemoryVT ( ) != Orig -> getValueType ( <NUM_LIT> ) ) return SDValue ( ) ; return DAG . getStore ( Store -> getChain ( ) , SDLoc ( Store ) , Orig , Store -> getBasePtr ( ) , Store -> getPointerInfo ( ) , Store -> getAlign ( ) ) ; } return SDValue (


<s> Align = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> selected_tune = NULL ; if ( aarch64_branch_protection_string ) aarch64_validate_mbranch_protection ( aarch64_branch_protection_string ) ; if ( aarch64_cpu_string ) valid_cpu = aarch64_validate_mcpu ( aarch64_cpu_string , & selected_cpu , & cpu_isa ) ; if ( aarch64_arch_string ) valid_arch = aarch64_validate_march ( aarch64_arch_string , & selected_arch , & arch_isa ) ; if ( aarch64_tune_string ) valid_tune = aarch64_validate_mtune ( aarch64_tune_string , & selected_tune ) ; SUBTARGET_OVERRIDE_OPTIONS ; if ( ! selected_cpu ) { if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( aarch64_enable_bti == <NUM_LIT> ) { aarch64_enable_bti = <NUM_LIT>


<s> unsigned getCacheLineSize ( ) { return <NUM_LIT>


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; <ISA_LIT>_MC :: initLLVMToCVRegMapping (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; int Shift = MI . getOperand ( <NUM_LIT> ) . getImm


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; assert ( ! isVarArg && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT


<s> unsigned ByValAlign = Flags . getByValAlign ( ) ; if ( RemainingSize == <NUM_LIT> ) return ; SDValue Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; LastFI = MFI -> CreateFixedObject ( RemainingSize , LocMemOffset , true ) ; SDValue Dst = DAG . getFrameIndex ( LastFI , PtrType ) ; ByValChain = DAG . getMemcpy ( ByValChain , dl , Dst , Src , DAG . getConstant ( RemainingSize , <STR_LIT> ) , std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) , false , false , MachinePointerInfo (

<NUM_LIT> ) , MachinePointerInfo ( <NUM_LIT> ) ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; auto & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI ->


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; else GVSym = getSymbol ( GV ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$'


<s> SDValue <ISA_LIT>TargetLowering :: LowerNaClTargetArch ( SDValue Op , SelectionDAG & DAG


<s> bool selectMVIAddr12Pair ( SDValue Addr , SDValue & Base , SDValue & Disp ) const { return selectMVIAddr ( <STR_LIT> , Addr ,


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDValue Glue ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOT , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOTOffset , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getTargetGlobalAddress ( Node -> getGlobal ( ) , DL , Node -> getValueType ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const TargetRegisterInfo * TRI = Subtarget .


<s> bool IsKnownRegister ; auto Mapper = <STR_LIT> ( getSysRegFeatureBits ( ) ) ; Mapper . fromString ( getSysReg (


<s> NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) . value ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; emitSPAdjustment ( MF , MBB , MBBI , - NumBytes ) ; emitSPExtend ( MF , MBB , MBBI , - NumBytes ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) )


<s> static __inline vec_double2 spu_mul ( vec_double2 a , vec_double2 b ) { return ( ( vec_double2 ) ( si_dfm ( ( qword ) ( a ) ,


<s> PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this


<s> IC . pushOperator ( IC_PLUS ) ; break ; case IES_INIT : assert ( ! BracCount && <STR_LIT> ) ; State = IES_LBRAC ; break ; } MemExpr =


<s> if ( code == 'V' ) { if ( GENERAL_REGNO_P ( regno ) ) msize = GET_MODE_SIZE ( word_mode ) ; else error ( <STR_LIT> ) ; } duplicated = code == 'd' && TARGET_AVX ; switch ( msize ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( GENERAL_REGNO_P ( regno ) && msize > GET_MODE_SIZE ( word_mode ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; case <NUM_LIT> : if ( LEGACY_INT_REGNO_P ( regno ) ) putc ( msize > <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; if ( ! ANY_QI_REGNO_P ( regno ) ) error ( <STR_LIT> ) ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : case <NUM_LIT> : if ( SSE_REGNO_P ( regno ) ) { gcc_assert ( ! duplicated ) ; putc ( msize == <NUM_LIT> ? 'y' : 'z' , file


<s> void setVariadicFPRIdx ( int Idx ) { VariadicFPRIdx =


<s> const MachineOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = <NUM_LIT> ; unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT>


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI )


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } ResultReg = createResultReg ( RC


<s> if ( ! TARGET_SH5 && PASS_IN_REG_P ( * cum , mode , type ) && ! ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && ( ROUND_REG ( * cum , mode ) + ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - ROUND_REG ( * cum , mode ) ; else if ( ! TARGET_SHCOMPACT && SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) words = NPARM_REGS ( SImode ) - cum -> arg_count [ SH_ARG_INT ] ; return words * UNITS_PER_WORD


<s> unsigned <ISA_LIT>AsmBackend :: getFixupKindContainereSizeInBytes ( unsigned Kind ) const { if ( IsLittleEndian ) return <NUM_LIT> ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case


<s> bool IsABICalls = Subtarget -> isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( *


<s> if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ; if ( val & <NUM_LIT> ) return IN_RANGE ( val , <NUM_LIT> , <NUM_LIT> ) ; return IN_RANGE ( val , <NUM_LIT> , <NUM_LIT>


<s> return __builtin_mve_vandq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ?

<NUM_LIT> : <NUM_LIT> , LROffset , true ) ;


<s> static bool isIntraBin ( const MachineInstr & MI ,


<s> if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg ,


<s> APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize >= Size || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ; else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( - SarConst , DL , CVT ) ) ; else return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( SarConst , DL , CVT ) ) ; } return SDValue (


<s> case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT>


<s>
unsigned
PairedReg
=
<STR_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
producePairRegisters
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
if
(
MF
.
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
&&
!
Subtarget
.
isTargetWindows
(
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
}
unsigned
CSStackSize
=
<NUM_LIT>
;
unsigned
SVECSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
{
auto
RegSize
=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
SVECSStackSize
+=
RegSize
;
else
CSStackSize
+=
RegSize
;
}
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
uint64_t
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
int64_t
SVEStackSize
=
alignTo
(
SVECSStackSize
+
estimateSVEStackObjectOffsets
(
MFI
)
,
<NUM_LIT>
)
;
bool
CanEliminateFrame
=
(
SavedRegs
.
count
(
)
==
<NUM_LIT>
)
&&
!
SVEStackSize
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
SVEStackSize
||
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR


<s> if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> ,


<s> Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I


<s> enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static void LowerSTACKMAP ( MCStreamer & OS , StackMaps & SM , const MachineInstr & MI , bool Is64Bit , const MCSubtargetInfo & STI ) { unsigned NumBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SM . recordStackMap ( MI )


<s> } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg


<s> if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( )


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF


<s> if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 + msize !=


<s> if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_SIMD && aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> for ( MachineFunction :: iterator B = MF -> begin ( ) , E = MF -> end ( ) ; B != E ; ++ B ) { for ( MachineBasicBlock :: instr_iterator I = B -> instr_begin ( ) , EB = B -> instr_end ( ) ; I != EB ; ++ I ) { switch ( I -> getDesc ( ) . getOpcode ( ) ) { case <STR_LIT> : { DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; J = I -> getNumOperands ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << J << <STR_LIT> ) ; MachineOperand & Literal = I -> getOperand ( <NUM_LIT> ) ; if ( Literal . isImm ( ) ) { int64_t V = Literal . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF >


<s> STClobbers |= ( <NUM_LIT> << STReg ) ; break ; default : break ; } } if ( STUses && ! isMask_32 ( STUses ) ) MI -> emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI -> emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI -> emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI -> emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I < E ; ++ I ) if ( FRegIdx . count ( I ) ) { assert ( ( <NUM_LIT> << getFPReg ( MI -> getOperand ( I ) ) & STDefs ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned FPKills = ( ( <NUM_LIT> << NumFPRegs ) - <NUM_LIT> ) & ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( Op . isUse ( ) && Op . isKill ( ) ) FPKills |= <NUM_LIT> << FPReg ; } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( FRegIdx . count ( i ) ) Op . setReg ( getSTReg ( FPReg ) ) ; else Op . setReg ( <STR_LIT> + FPReg ) ; } StackTop -= NumSTPopped ; for ( unsigned i = <NUM_LIT> ; i < NumSTDefs ; ++ i ) pushReg


<s> const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; if ( MCID . isTerminator ( ) || MCID . isCall ( ) || MCID . isReturn ( ) || MCID . isBranch ( ) || MCID . isIndirectBranch ( ) ) return true ; for ( unsigned OpIdx = <NUM_LIT> ; OpIdx < MCID . getNumDefs ( ) ; ++ OpIdx ) { MCOperand & Op = Inst . getOperand ( OpIdx ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return true ; } if ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> , MRI ) ) return true ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( listContainsReg ( Inst , <NUM_LIT> , <STR_LIT> ) ) return true ; break ; case


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> static enum mips_symbol_type mips_classify_symbolic_expression ( rtx x , enum mips_symbol_context context ) { rtx offset


<s> DAG . getContext ( ) -> diagnose ( DiagnosticInfoUnsupported ( MF . getFunction ( )


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask


<s> const LLT v2s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto BinOp : { G_ADD , G_SUB , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s32 , s64 , v2s32 , v4s32 , v2s64 } ) setAction ( BinOp , Ty , Legal ) ; for ( auto MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { s32 , s64 } ) setAction ( MemOp , Ty , Legal ) ; setAction ( G_BR , LLT :: unsized ( ) , Legal ) ; computeTables ( )


<s> return ( OptLevel >= CodeGenOpt :: Aggressive ) && ! VT


<s> selected_cpu = NULL ; selected_arch = NULL ; selected_tune = NULL ; if ( aarch64_cpu_string ) valid_cpu = aarch64_validate_mcpu ( aarch64_cpu_string , & selected_cpu , & cpu_isa ) ; if ( aarch64_arch_string ) valid_arch = aarch64_validate_march ( aarch64_arch_string , & selected_arch , & arch_isa ) ; if ( aarch64_tune_string ) valid_tune = aarch64_validate_mtune ( aarch64_tune_string , & selected_tune ) ; if ( ! selected_cpu ) { if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( TARGET_ILP32 ) error ( <STR_LIT> ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32 ) sorry (


<s> rtx op1 = XEXP ( src , <NUM_LIT> ) ; gcc_assert ( op0 == dest && GET_CODE ( op1 ) == CONST_INT ) ; if ( INTVAL ( op1 ) < <NUM_LIT> ) { gcc_assert ( ! frame_pointer_needed ) ; if ( unwind ) fprintf ( asm_out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , - INTVAL ( op1 ) ) ; } else process_epilogue ( asm_out_file , insn , unwind , frame ) ; } else { gcc_assert ( src == hard_frame_pointer_rtx ) ; process_epilogue ( asm_out_file , insn , unwind , frame ) ; } } else if ( dest == hard_frame_pointer_rtx ) { gcc_assert ( src == stack_pointer_rtx ) ; gcc_assert ( frame_pointer_needed


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > && AB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , std :: move ( OW ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return S


<s> return ( __m64 ) __builtin_ia32_psrad ( (


<s> SDValue Cst = DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; if ( VT . is256BitVector ( ) ) { SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) , Vec , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( InsV , Vec , DAG . getConstant ( <NUM_LIT> , <STR_LIT> )


<s> if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 =


<s> for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> if ( TT . isOSBinFormatMachO ( ) ) return new TargetLoweringObjectFileMachO ( ) ; if ( TT . isOSWindows ( ) ) return new TargetLoweringObjectFileCOFF ( ) ; return new <ISA_LIT>ElfTargetObjectFile


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI


<s> static unsigned int aarch64_sve_container_bits ( machine_mode mode ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; poly_uint64 vector_bits = ( vec_flags & ( VEC_PARTIAL | VEC_SVE_PRED ) ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE


<s> int32x4_t result = vcombine_s32 ( a , vcreate_s32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b )