<s> int consecutive_zeros = <NUM_LIT> ; if ( ! ( val & ( <NUM_LIT> << i ) ) ) { while ( ( i < <NUM_LIT> ) && ! ( val & ( <NUM_LIT> << i ) ) ) { consecutive_zeros += <NUM_LIT> ; i += <NUM_LIT> ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= <NUM_LIT> ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != <NUM_LIT> && ( ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , <NUM_LIT> ) ; if ( insns2 <=


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFNEGorFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op ,


<s> if ( ! isConjunctionDisjunctionTree ( Op , CanNegate ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue CCVal


<s> if ( FirstLdSt -> getOpcode ( ) != SecondLdSt -> getOpcode ( ) ) return false ; unsigned Ofs1 = FirstLdSt -> getOperand ( <NUM_LIT> )


<s> const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ?


<s> for ( auto & I : BB ) { if ( I . getOpcode ( ) == <STR_LIT> ) { ReTags . push_back ( & I ) ; int FI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; TaggedSlots . insert ( FI ) ; assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; } } } if ( ReTags . empty ( ) )


<s> void <ISA_LIT>FrameLowering :: restoreWinEHStackPointersInParent ( MachineFunction & MF ) const { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ) ; for ( MachineBasicBlock & MBB : MF ) { bool NeedsRestore = MBB . isEHPad ( ) && ! MBB .


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx


<s> SDValue FirstInput = N -> getOperand ( <NUM_LIT> ) ; bool IsRoundOfExtLoad = false ; if ( FirstInput . getOpcode ( ) == <STR_LIT> && FirstInput . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = dyn_cast < LoadSDNode > ( FirstInput . getOperand ( <NUM_LIT> ) ) ; IsRoundOfExtLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } if ( ( ! IsRoundOfExtLoad && FirstInput . getOpcode ( ) != <STR_LIT> ) || N -> getNumOperands ( ) == <NUM_LIT> ) return SDValue ( ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { if ( IsRoundOfExtLoad && N -> getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NextInput = IsRoundOfExtLoad ? N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i ) ; if ( NextInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue PreviousInput = IsRoundOfExtLoad ? N -> getOperand ( i - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( PreviousInput ) ; LoadSDNode * LD2 = dyn_cast < LoadSDNode > ( NextInput ) ; if ( IsRoundOfExtLoad && LD2 -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isConsecutiveLS ( LD2 , LD1 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreConsecutiveLoads = false ; if ( ! isConsecutiveLS ( LD1 , LD2 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreReverseConsecutive = false ; if ( ! InputsAreConsecutiveLoads && ! InputsAreReverseConsecutive ) return SDValue ( ) ; } assert ( ! ( InputsAreConsecutiveLoads && InputsAreReverseConsecutive ) && <STR_LIT> ) ; SDValue FirstLoadOp = IsRoundOfExtLoad ? FirstInput . getOperand ( <NUM_LIT> ) : FirstInput ; SDValue LastLoadOp = IsRoundOfExtLoad ? N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( FirstLoadOp ) ; LoadSDNode * LDL = dyn_cast < LoadSDNode > ( LastLoadOp ) ; if ( InputsAreConsecutiveLoads


<s> return new <ISA_LIT>SETargetLowering ( TM , STI


<s> switch ( Triple ( TT ) . getOS ( ) ) { case Triple :: Darwin : return new Darwin<ISA_LIT>AsmBackend ( T ) ; default : return <NUM_LIT>


<s> MachineInstr * PrevMI = std :: prev ( MBBI ) ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> ) && <STR_LIT> ) ; PrevMI -> setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; PrevMI -> copyImplicitOps ( * MBB . getParent ( ) , & * MBBI ) ; MBB . erase ( MBBI ) ; return true ; } } return


<s> SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , getZeroVector ( <STR_LIT> , Subtarget , DAG , DL ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ; } MinPos = DAG . getBitcast ( <STR_LIT> , MinPos ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MinPos ) ; MinPos = DAG . getBitcast ( SrcVT


<s> return __builtin_neon_vcmla90v4sf ( __r ,


<s> return ( __m128 ) __builtin_ia32_cmpltps ( ( __v4sf ) __A , (


<s> bool isCmseNSCallFunction ( ) const { return IsCmseNSCall


<s> default : return <NUM_LIT> ; } if ( in ) return MAX ( ix86_cost -> mmx_load [ index ] , ix86_cost -> mmx_store [ index ] ) ; return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : if ( Q_CLASS_P ( regclass ) || TARGET_64BIT ) { if ( ! in ) return ix86_cost -> int_store [ <NUM_LIT> ] ; if ( TARGET_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p ( cfun ) ) cost = ix86_cost -> movzbl_load ; else cost = ix86_cost -> int_load [ <NUM_LIT> ] ; if ( in == <NUM_LIT> ) return MAX ( cost , ix86_cost -> int_store [ <NUM_LIT> ] ) ; return cost ; } else { if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> movzbl_load , ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ) ; if ( in ) return ix86_cost -> movzbl_load ; else return ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ; } break ; case <NUM_LIT> : if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> int_load [ <NUM_LIT> ] , ix86_cost -> int_store [ <NUM_LIT> ] ) ; return in ? ix86_cost -> int_load [ <NUM_LIT>

] : ix86_cost -> int_store [ <NUM_LIT> ] ;


<s> } else regno = - <NUM_LIT> ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= <NUM_LIT> && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - <NUM_LIT> || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - <NUM_LIT> || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= <NUM_LIT> && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS


<s> static std :: unique_ptr < <ISA_LIT>Operand > MorphToMEMri ( unsigned Base , std :: unique_ptr < <ISA_LIT>Operand > Op ) { const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = k_MemoryRegImm ; Op -> Mem . Base = Base ; Op -> Mem . IndexReg = <NUM_LIT> ; Op -> Mem . Index


<s> unsigned BaseReg = Base . getReg ( ) ; unsigned IndexReg = Index . getReg ( ) ; if ( STI . hasFeature ( <STR_LIT> ) && BaseReg == <NUM_LIT> && IndexReg == <NUM_LIT> ) return true ; if ( ( BaseReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) || ( IndexReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) ) return true ; return false


<s> switch ( VK ) { default : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT10 ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 : <ISA_LIT>MCExpr


<s> bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto * Regs = Subtarget -> getSpecialRegisters ( ) ; bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue NewSP = Op . getOperand ( <NUM_LIT> ) ; SDValue Backchain ; SDLoc DL ( Op ) ; if ( StoreBackchain ) { SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , Regs -> getStackPointerRegister ( ) , <STR_LIT> ) ; Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , Regs -> getStackPointerRegister ( ) , NewSP ) ; if ( StoreBackchain ) Chain = DAG . getStore ( Chain , DL , Backchain , getBackchainAddress ( NewSP , DAG ) , MachinePointerInfo ( ) ) ; return


<s> bool <ISA_LIT>InstPrinter :: showRegistersWithPrefix ( ) const { return FullRegNamesWithPercent


<s> rtx nth_rtx = extract_nth_access_rtx ( insn , n ) ; if ( nth_rtx == NULL_RTX ) return NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : return SET_DEST ( nth_rtx ) ; case TYPE_STORE_MULTIPLE


<s> bool hasDomain ( unsigned domain ) const { return AvailableDomains & (


<s> len = ( regno == BP_REG || regno == R13_REG ) ; } else if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( Op1 == N -> getOperand ( <NUM_LIT> ) ) return Op1 ; EVT VT = Op1 . getValueType ( ) ; unsigned ElemBytes = VT . getVectorElementType ( ) . getStoreSize ( ) ; if ( ElemBytes <= <NUM_LIT> ) { Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , Op1 ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op ) ; } } } if ( Opcode == <STR_LIT> ) { auto * SN = cast < StoreSDNode > ( N ) ; EVT MemVT = SN -> getMemoryVT ( ) ; if ( MemVT . isInteger ( ) ) { if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } } if ( Opcode == <STR_LIT> ) { if ( auto * IndexN = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDValue Op0 = N -> getOperand ( <NUM_LIT>


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) && hasAtomicRMW ) ? AtomicExpansionKind


<s> uint32_t getAddrMode2OffsetOpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return <NUM_LIT>


<s> size_t <ISA_LIT>ELFDynamic :: getGotSym ( const ELFFileFormat & pFormat ) const { if ( ! pFormat . hasGOT ( ) ) return <NUM_LIT> ; return getSymTabNum ( pFormat ) - m_pParent . getGOT ( ) . getGlobalNum (


<s> Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc


<s> int n = aggregate_value_p ( TREE_TYPE ( type ) , type ) != <NUM_LIT> ; return gen_rtx_REG ( DImode , x86_64_int_parameter_registers [ n ] ) ; } if ( ix86_function_regparm ( type , function ) > <NUM_LIT> ) { tree parm ; parm = TYPE_ARG_TYPES ( type ) ; for ( ; parm ; parm = TREE_CHAIN ( parm ) ) if

( TREE_VALUE ( parm ) == void_type_node ) break ;


<s> if ( Alignment >= <NUM_LIT> && NumRegs == <NUM_LIT> ) Alignment = <NUM_LIT> ; else if ( Alignment >= <NUM_LIT> && ( NumRegs == <NUM_LIT> || NumRegs == <NUM_LIT> ) )


<s> Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode ( )


<s> SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getScalarType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF


<s> case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned ,


<s> uint64_t THMTo<ISA_LIT>Stub :: initSymValue ( ) const { return <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printPrefetchOp ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned prfop = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( prfop , Valid ) ; if ( Valid ) O


<s> inline <STR_LIT> getVPTInstrPredicate ( const MachineInstr & MI ) { Register PredReg


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; TrueOp = <NUM_LIT> ; FalseOp =


<s> static Register createDTuple ( ArrayRef < Register > Regs , MachineIRBuilder & MIB ) { static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> if ( auto * GV = dyn_cast < GlobalValue > ( V ) ) { MovI -> addOperand ( MF , MachineOperand :: CreateGA ( GV , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } else { MovI -> addOperand ( MF , MachineOperand :: CreateBA ( cast < BlockAddress > ( V ) , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } MovI -> addOperand ( MF , MachineOperand :: CreateImm ( Offset ) ) ; constrainSelectedInstRegOperands ( * MovI , TII , TRI , RBI ) ; return DstReg ; } ; Register DstReg = BuildMovK ( MovZ . getReg ( <NUM_LIT> ) , <STR_LIT> | <STR_LIT> ,


<s> return ( uint32x4_t ) ( vabsq_f32 ( __a ) < vabsq_f32 ( __b ) ) ; return ( uint32x4_t ) __builtin_neon_vcagtv4sf (


<s> return SomeVT . getVectorNumElements ( )


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg


<s> emit_insn ( gen_rtx_SET ( target , x ) ) ; return true ; } return false ; case E_V8QImode : case E_V4QImode : if ( ! mmx_ok ) return false ; goto widen ; case E_V8HImode : case E_V8HFmode : case E_V8BFmode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) { struct expand_vec_perm_d dperm ; rtx tmp1 , tmp2 ; permute : memset ( & dperm , <NUM_LIT> , sizeof ( dperm ) ) ; dperm . target = target ; dperm . vmode = mode ; dperm . nelt = GET_MODE_NUNITS ( mode ) ; dperm . op0 = dperm . op1 = gen_reg_rtx ( mode ) ; dperm . one_operand_p = true ; if ( mode == V8HFmode || mode == V8BFmode ) { tmp1 = force_reg ( GET_MODE_INNER ( mode ) , val ) ; tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( maybe_gen_vec_set_0 ( mode , tmp2 , CONST0_RTX ( mode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } else { tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } emit_move_insn ( dperm . op0 , tmp1 ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case E_V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; if ( smode == QImode && ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( wsmode , val , val ) ) ; else { x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case E_V16HImode : case E_V16HFmode : case


<s> bool has<ISA_LIT>32r6 ( ) const { return <ISA_LIT>ArchVersion


<s> auto PosOpt = getAVLPos ( Op -> getOpcode ( ) ) ; return PosOpt ? Op -> getOperand ( * PosOpt ) : SDValue (


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass (


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> return new <ISA_LIT>SEDAGToDAGISel ( TM , OptLevel


<s> break ; case <STR_LIT> : Op = emitIntrinsicWithGlue ( DAG , C . Op0 , C . Opcode ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return SDValue ( Op . getNode ( ) , Op -> getNumValues ( ) - <NUM_LIT> ) ; } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( C . ICmpType , DL , <STR_LIT> ) ) ; if ( C . Opcode == <STR_LIT> ) { bool RegisterOnly = ( bool ( C . CCMask & <STR_LIT> ) != bool ( C . CCMask & <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: MatchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { SDValue Address = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isTargetNaCl ( ) ) { return true ; } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == <NUM_LIT> && Subtarget -> isTargetLinux ( ) ) switch ( N -> getPointerInfo (


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned IntVal = Tok . getIntVal ( ) ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT>


<s> static bool isLD ( InsnType insn ) { return ( getBit ( insn , <NUM_LIT> )


<s> assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setImm ( MIB -> getOperand ( <NUM_LIT> )


<s> return RegNo == <STR_LIT> || RegNo ==


<s> bool <ISA_LIT>BaseRegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering (


<s> int VecSize = VT . getSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; int Len = EltVT . getSizeInBits ( ) ; auto GetShift = [ & ] ( unsigned OpCode , SDValue V , int Shifter ) { MVT VT = V . getSimpleValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Shifters ( VT . getVectorNumElements ( ) , DAG . getConstant ( Shifter , DL , VT . getVectorElementType ( ) ) ) ; return DAG . getNode ( OpCode , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , Shifters ) ) ; } ; auto GetMask = [ & ] ( SDValue V , APInt Mask ) { MVT VT = V . getSimpleValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Masks ( VT . getVectorNumElements ( ) , DAG . getConstant ( Mask , DL , VT . getVectorElementType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , Masks ) ) ; } ; MVT SrlVT = Len > <NUM_LIT> ? VT : <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; SDValue V = Op ; SDValue Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast (


<s> SDValue <ISA_LIT>TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG .


<s> return <NUM_LIT> - MI . getOperand ( Op )


<s> switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler ::


<s> sve_switcher :: ~ sve_switcher ( ) { memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof ( have_regs_of_mode


<s> if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { bool HasCall = false ; InstructionCost NumStores = <NUM_LIT> ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , <NUM_LIT> , TTI :: TCK_RecipThroughput ) ; } } unsigned const NumStoresVal = * NumStores . getValue ( ) ; unsigned const Max = ( NumStoresVal ? ( <NUM_LIT> / NumStoresVal ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = <NUM_LIT> ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= <NUM_LIT> ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = <NUM_LIT> ; UP . DefaultUnrollRuntimeCount = <NUM_LIT>


<s> mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_LINK ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( ( reg_mask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , regno ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset )


<s> return ShiftVal == <NUM_LIT> || ( <STR_LIT> ( Imm ) == <STR_LIT> && ShiftVal == <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ShiftVal = <STR_LIT> ( Imm ) ; return ShiftVal == <NUM_LIT> || ( <STR_LIT> ( Imm ) == <STR_LIT> && ShiftVal == <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; switch ( <STR_LIT> ( Imm ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) == <NUM_LIT> ; } } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned InitialOffset = <NUM_LIT> ; if ( Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) . isELFv2ABI ( ) && ! Fn . getRegInfo ( ) . use_empty ( <STR_LIT> ) ) InitialOffset = <NUM_LIT> ; return InitialOffset


<s> bool Changed = false ; Changed |= trySADReplacement ( BO -> getOperand ( <NUM_LIT> ) , BO ) ; Changed |= trySADReplacement ( BO -> getOperand ( <NUM_LIT> ) , BO ) ; return Changed


<s> if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> indirect_branch_type = ix86_indirect_branch ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep && ( flag_cf_protection & CF_RETURN ) ) error ( <STR_LIT> <STR_LIT> ) ; } if ( cfun -> machine -> function_return_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; int64_t Flags = <NUM_LIT> ; if ( Parser . parseAbsoluteExpression ( Flags ) ) return TokError


<s> } else { RC = Opc != <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; } Register SrcReg = Src . getReg ( ) ; isKill = MI . killsRegister ( SrcReg ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; if ( NewSrc . isVirtual ( ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( SrcReg . isPhysical ( ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc ,

RegState :: Define | RegState :: Undef , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> void printDstIdx64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT>


<s> int EltIdx = MaskVals [ i ] ; EltIdx = ( EltIdx < <NUM_LIT> ) ? <NUM_LIT> : EltIdx - <NUM_LIT> ; pshufbMask . push_back ( DAG . getConstant ( EltIdx , <STR_LIT> ) ) ; } V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , V2 ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) ; SDValue NewV = V1 ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int Elt0 = MaskVals [ i * <NUM_LIT> ] ; int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 /


<s> return ( __m64 ) __builtin_arm_waddsubhx ( ( __v4hi ) a , (


<s> bool <ISA_LIT>TargetLowering :: lowerAtomicStoreAsStoreSDNode ( const StoreInst & SI )


<s> if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthFPExtendToSVE ( Op , DAG ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return SDValue ( )


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT>


<s> static int rs6000_use_sched_lookahead (


<s> int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( imm32 ) ) ; return MCDisassembler ::


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( ShAmtOp ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( EltVT ) && ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMachO ( ) ) ; <ISA_LIT>FrameLowering :: emitStackProbeCall ( * BB -> getParent ( ) , * BB , MI , DL ) ; MI -> eraseFromParent ( ) ; return BB


<s> Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( ! isUInt < <NUM_LIT> > ( Offset ) && ( MemAccessTy ->

isFloatingPointTy ( ) || MemAccessTy -> isVectorTy ( ) ) ) return false ;


<s> assert ( ShlAmount < <NUM_LIT> && <STR_LIT> ) ; int ShrAmount = - ShlAmount ; ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , SDLoc ( Op ) , VT , Op , CurDAG -> getTargetConstant ( ShrAmount , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , VT ) ) ; } return SDValue ( ShiftNode


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( ) ,


<s> const struct cpu_regmove_cost * regmove_cost = aarch64_tune_params . regmove_cost ; if ( to == TAILCALL_ADDR_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == TAILCALL_ADDR_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG ) ) return regmove_cost -> GP2GP ; if ( to == STACK_REG || from == STACK_REG ) return aarch64_register_move_cost ( mode , from , GENERAL_REGS ) + aarch64_register_move_cost ( mode , GENERAL_REGS , to ) ; if ( known_eq ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) { if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP * <NUM_LIT> ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP * <NUM_LIT> ; else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP * <NUM_LIT> ; if ( ! TARGET_SIMD ) return regmove_cost -> GP2FP + regmove_cost -> FP2GP + regmove_cost -> FP2FP ; return regmove_cost -> FP2FP ; } if ( from == GENERAL_REGS && to == GENERAL_REGS


<s> bool <ISA_LIT>16DAGToDAGISel :: selectAddr16 ( SDValue Addr , SDValue & Base , SDValue & Offset ) { return selectAddr ( false , Addr , Base , Offset


<s> } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( BaseReg == <STR_LIT> || ( Is64BitMode && DispForReloc ) ) { assert ( IndexReg . getReg ( ) == <NUM_LIT> && Is64BitMode && <STR_LIT> ) ; MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } bool IsPCRel = MCE . earlyResolveAddresses ( ) ? true : false ; unsigned BaseRegNo = - <NUM_LIT> ; if ( BaseReg != <NUM_LIT> && BaseReg != <STR_LIT> ) BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! Is64BitMode || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; return ; } if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; return ; } MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , IsPCRel ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 =


<s> static MCDisassembler * create<ISA_LIT>elDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ,


<s> static bool isSequentialOrUndefInRange ( const SmallVectorImpl < int > & Mask , int Pos , int Size , int Low ) { for ( int i = Pos , e = Pos + Size ; i != e ; ++ i , ++ Low ) if ( ! isUndefOrEqual ( Mask [ i ] , Low ) ) return false ; return true


<s> if ( isZero ( Elt ) ) return true ; if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Elt ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; return false


<s> if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags (


<s> const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ; return true


<s> if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < <ISA_LIT>FunctionInfo >

( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ;


<s> } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getTargetConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsLowZero ) && ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsHighZero ) && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 =


<s> if ( const PseudoSourceValue * PSV = MMO . getPseudoValue ( ) ) { if ( ! PSV -> isAliased ( MFI ) ) return false ; Objects . push_back ( PSV ) ; return true ; } if ( const Value * V = MMO . getValue ( ) ) { SmallVector < const Value * , <NUM_LIT> > Objs ; GetUnderlyingObjects ( V , Objs , DL ) ; for ( const Value * UValue


<s> bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end


<s> if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) ,

MemTmp , MachinePointerInfo ( ) , MemVT ) ;


<s> DebugLoc dl = N -> getDebugLoc ( ) ; SDValue MemAddr , Align ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; if ( ! SelectAddrMode6 ( N , N -> getOperand ( AddrOpIdx ) , MemAddr , Align ) ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain


<s> return ( __m512i ) __builtin_ia32_pmovsxwq512_mask ( ( __v8hi ) __A , ( __v8di ) _mm512_undefined_epi32 ( ) ,


<s> MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT ) ; SDValue ParentFrameOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , OffsetSymVal ) ; const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ; SDValue RegNodeBase = DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , DAG . getConstant ( RegNodeSize , dl , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl

, PtrVT , RegNodeBase , ParentFrameOffset ) ;


<s> int fp_reg_size = <NUM_LIT> ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < <NUM_LIT> ; regno ++ ) { if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == <NUM_LIT> && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < <NUM_LIT> ; regno


<s> if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction


<s> unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % <NUM_LIT> == <NUM_LIT>


<s> DebugLoc DL = LD -> getDebugLoc ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; SDValue Result = DCI . CombineTo (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( )


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != <NUM_LIT> || Alignment <=

<NUM_LIT> || Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add (

Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI ->


<s> if ( ! CE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) Val = INT32_MIN ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , E ) ) ; return MatchOperand_Success ; } bool haveEaten = false ; bool isAdd = true ; if ( Tok . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; haveEaten = true ; } else if ( Tok . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; isAdd = false ; haveEaten =


<s> for ( auto & B : Buckets ) { const SCEV * Diff = SE -> getMinusSCEV ( LSCEV , B . BaseSCEV ) ; if ( const auto * CDiff = dyn_cast < SCEVConstant > ( Diff ) ) { B . Elements . push_back ( BucketElement ( CDiff


<s> SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode ,


<s> MachineOperand MOpSHSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpMBSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpSHMI = MI . getOperand ( <NUM_LIT> ) ; MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHSrc . isImm ( ) && MOpMBSrc . isImm ( ) && MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHSrc = MOpSHSrc . getImm ( ) ; uint64_t MBSrc = MOpMBSrc . getImm ( ) ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; uint64_t NewSH = SHSrc + SHMI ; uint64_t NewMB = MBSrc - SHMI ; if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++ ; if ( MRI -> use_nodbg_empty


<s> bool <ISA_LIT>TargetLowering :: isFPExtFree ( EVT DestVT , EVT SrcVT ) const { assert ( DestVT . isFloatingPoint ( ) && SrcVT . isFloatingPoint ( ) && <STR_LIT> ) ; if ( DestVT == <STR_LIT> ) return false ; return


<s> void <ISA_LIT>AIXAsmPrinter :: EmitEndOfAsmFile ( Module & M ) { if ( M . empty ( ) ) return ; MCSectionXCOFF * TOCBaseSection = OutStreamer -> getContext ( ) . getXCOFFSection ( StringRef ( <STR_LIT> ) , XCOFF :: XMC_TC0 , XCOFF :: XTY_SD , XCOFF :: C_HIDEXT , SectionKind :: getData ( ) ) ; TOCBaseSection -> setAlignment ( Align ( <NUM_LIT> ) ) ; OutStreamer -> SwitchSection ( TOCBaseSection ) ; <ISA_LIT>TargetStreamer & TS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer ->


<s> else alloc_offset = MIN ( seh -> cfa_offset + <NUM_LIT> , seh -> sp_offset ) ; offset = alloc_offset - INCOMING_FRAME_SP_OFFSET ; if ( offset > <NUM_LIT> ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; for ( int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( seh -> reg_offset [ regno ] > <NUM_LIT> && seh -> reg_offset [ regno ] <= alloc_offset ) { if ( SSE_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else if ( GENERAL_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else gcc_unreachable ( ) ; print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } if ( alloc_offset != seh -> sp_offset ) { offset = seh -> sp_offset - alloc_offset ; if ( offset > <NUM_LIT> && offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; for ( int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( seh -> reg_offset [ regno ] > alloc_offset ) { if ( SSE_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else if ( GENERAL_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else gcc_unreachable ( ) ; print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , seh -> sp_offset - seh -> reg_offset [ regno ] ) ; } } fputs ( <STR_LIT> , f


<s> initGlobalBaseReg ( ) ; } return GlobalBaseReg


<s> } if ( ST . hasV5TOps ( ) ) { getActionDefinitionsBuilder ( G_CTLZ ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_CTLZ_ZERO_UNDEF ) . lowerFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; } else { getActionDefinitionsBuilder ( G_CTLZ_ZERO_UNDEF ) . libcallFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_CTLZ ) . lowerFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; } getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { s32 , p0 } , { s1 } ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s1 } , { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalFor ( { { s64 , p0 } } ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } ,


<s> bool assignArg ( unsigned ValNo , EVT OrigVT , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , const CallLowering :: ArgInfo & Info , <STR_LIT> Flags , CCState & State_ ) override { <ISA_LIT>CCState & State = static_cast < <ISA_LIT>CCState & > ( State_ ) ; if ( IsReturn ) State . PreAnalyzeCallResult ( Info .


<s> const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_UADDE ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> ,


<s> SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; IsTailCall = false ; switch ( CallConv ) { case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , IsVarArg , IsTailCall ,

Outs , OutVals , Ins , DL , DAG , InVals ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ RegNo ]


<s> SDValue V = insert256BitVector ( DAG . getUNDEF ( VT ) , V1 ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> ; if ( Available . size ( ) == <NUM_LIT> ) dbgs ( ) << <STR_LIT> ; Candidate c ( SU , * HazardRec ) ; c . dumpCosts ( ) ; dbgs ( ) << <STR_LIT> ;


<s> const <ISA_LIT>RegisterInfo & RI = TII . getRegisterInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ <STR_LIT> ] ; if ( SaveS2 ) MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; if ( hasFP ( MF ) ) MF . getRegInfo ( ) .


<s> scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode , & int_mode ) ) return false ; if ( aarch64_bitmask_imm ( val_in , int_mode ) ) return false ; if ( aarch64_move_imm ( val_in , int_mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ; return aarch64_bitmask_imm ( imm2 , int_mode


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . AddressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . getOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) .


<s> O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << <STR_LIT> ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> <<

( char ) <STR_LIT> ( MO3 . getImm ( ) ) << ImmOffs ;


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem


<s> <ISA_LIT>_64GOTEntry * got = <NUM_LIT> ; unsigned int EntrySize = <STR_LIT> ; uint64_t RegionSize = <NUM_LIT> ; for ( <ISA_LIT>_64GOTPLT :: iterator it = m_pGOTPLT -> begin ( ) , ie = m_pGOTPLT -> end ( ) ; it != ie ; ++ it , ++


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE


<s> if ( ! canInstrSubstituteCmpInstr ( MI , & CmpInstr , TRI ) ) return false ; MI -> setDesc ( get ( NewOpc ) ) ; CmpInstr . eraseFromParent ( ) ; bool succeeded = UpdateOperandRegClass ( * MI ) ; ( void


<s> void <ISA_LIT>TargetLowering :: computeMaskedBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; case <STR_LIT> : { DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; if ( KnownZero == <NUM_LIT> && KnownOne == <NUM_LIT> ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZeroRHS , KnownOneRHS , Depth


<s> int shift_adv ; int shift = <NUM_LIT> ; int nelem ; switch ( GET_MODE ( op ) ) { case E_V2HImode : mask = <NUM_LIT> ; shift_adv = <NUM_LIT> ; nelem = <NUM_LIT> ; break ; case E_V4QImode : mask = <NUM_LIT> ; shift_adv = <NUM_LIT> ; nelem = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_BIG_ENDIAN ) { for ( i = <NUM_LIT> ; i < nelem ; ++ i ) { HOST_WIDE_INT val = XINT ( XVECEXP ( op , <NUM_LIT> , nelem - i - <NUM_LIT> ) , <NUM_LIT> ) ; hwint |= ( val & mask ) << shift ; shift = shift


<s> BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , LimitReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( ThreadEnvironmentStackLimit ) . addReg ( <STR_LIT> ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( FinalReg ) . addReg ( LimitReg ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( ContinueMBB ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT> ) , RoundedReg ) . addReg ( FinalReg ) . addImm ( PageMask ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( LoopMBB ) ; if ( ! InProlog ) { BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , JoinReg ) . addReg ( LimitReg ) . addMBB ( RoundMBB ) . addReg ( ProbeReg ) . addMBB ( LoopMBB ) ; } addRegOffset ( BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , ProbeReg ) , JoinReg , false , - PageSize ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ProbeReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( RoundedReg ) . addReg ( ProbeReg ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( LoopMBB ) ; MachineBasicBlock :: iterator ContinueMBBI = ContinueMBB -> getFirstNonPHI ( ) ; if ( InProlog ) { addRegOffset ( BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , false , RCXShadowSlot ) ; addRegOffset ( BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , false , RDXShadowSlot ) ; } BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( SizeReg ) ; MBB . addSuccessor ( ContinueMBB ) ; MBB . addSuccessor (


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( Reg0 ) || ! is<ISA_LIT>LowRegister ( Reg1 ) || ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; if ( Reg0 != Reg2 ) { if ( Reg1 != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI ) ; if ( ! CommutedMI ) return false ; } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 = <NUM_LIT> ; unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead


<s> unsigned <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( <STR_LIT> ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { if ( ID == <STR_LIT> && ST -> hasP9Vector ( ) ) return TLI -> getTypeLegalizationCost ( DL , RetTy ) . first ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys ,


<s> return ( __m256i ) __builtin_ia32_cvtps2qq256_mask ( ( __v4sf ) __A , ( __v4di )


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE1 ( ) { if ( ! Subtarget . hasSSE1 ( ) ) return ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) LegacyInfo . setAction (

{ BinOp , Ty } , LegacyLegalizeActions :: Legal ) ;


<s> rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; for ( i = <NUM_LIT> ; i < n_elt ; ++ i , arglist = TREE_CHAIN ( arglist ) ) { rtx x = expand_expr ( TREE_VALUE ( arglist ) , NULL_RTX , VOIDmode , <NUM_LIT> ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target


<s> in_section = NULL ; output_section_asm_op ( data


<s> emit_move_insn ( scratch_r , tmp ) ; emit_move_insn ( scratch_b , scratch_r ) ; if ( ! addr_dead_p ) tmp = gen_rtx_POST_DEC ( Pmode , addr ) ; else tmp = addr ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( pic_offset_table_rtx , tmp ) ; is_desc = true ; addr = scratch_b ; } if ( sibcall_p ) insn = gen_sibcall_nogp ( addr ) ; else if ( retval ) insn = gen_call_value_nogp ( retval , addr


<s> SAVErr = <STR_LIT> ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SAVErr ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) .


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( <STR_LIT> == Addr ) && <STR_LIT> ) ; Out . EmitBundleLock ( false


<s> void <ISA_LIT>AsmPrinter :: LowerFAULTING_OP ( const MachineInstr & FaultingMI , <ISA_LIT>MCInstLower & MCIL ) { NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; Register DefRegister = FaultingMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; FaultMaps :: FaultKind FK = static_cast < FaultMaps :: FaultKind > ( FaultingMI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MCSymbol * HandlerLabel = FaultingMI . getOperand ( <NUM_LIT> ) . getMBB ( ) -> getSymbol ( ) ; unsigned Opcode = FaultingMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned OperandsBeginIdx =


<s> void <ISA_LIT>AnalyzeImmediate :: ReplaceADDiuSLLWithLUi ( InstSeq & Seq ) { if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SLL ) || ( Seq [ <NUM_LIT> ] . ImmOpnd < <NUM_LIT> ) ) return ; int64_t Imm = SignExtend64 < <NUM_LIT> > ( Seq [ <NUM_LIT> ] . ImmOpnd ) ; int64_t ShiftedImm = ( uint64_t ) Imm << ( Seq [ <NUM_LIT> ] . ImmOpnd - <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc = LUi ; Seq [ <NUM_LIT> ] . ImmOpnd = ( unsigned )


<s> return new <ISA_LIT>Disassembler ( STI , Ctx


<s> unsigned ExtraStepsF = <NUM_LIT> , ExtraStepsD = ExtraStepsF + <NUM_LIT> ; bool UseRsqrt = ST . useRSqrt ( ) ; TM . Options . Reciprocals . setDefaults ( <STR_LIT> , UseRsqrt , ExtraStepsF ) ; TM . Options . Reciprocals . setDefaults (


<s> const unsigned DiviserReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT RegTy = MRI . getType ( DstReg ) ; assert ( RegTy == MRI . getType ( DividentReg ) && RegTy == MRI . getType ( DiviserReg ) && <STR_LIT> ) ; const RegisterBank & RegRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const static struct SDivEntry { unsigned SizeInBits ; unsigned QuotientReg ; unsigned DividentRegUpper ; unsigned DividentRegLower ; unsigned OpSignExtend ; unsigned OpCopy ; unsigned OpDiv ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } } ; if ( RegRB . getID ( ) != <STR_LIT> ) return false ; auto SDivEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ RegTy ] ( const SDivEntry & El ) { return El . SizeInBits == RegTy . getSizeInBits ( ) ; } ) ; if ( SDivEntryIt == std :: end ( OpTable ) ) return false ; const TargetRegisterClass * RegRC = getRegClass ( RegTy , RegRB ) ; if ( ! RBI . constrainGenericRegister ( DividentReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DiviserReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * RegRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpCopy ) , SDivEntryIt -> DividentRegLower ) . addReg ( DividentReg ) ; if ( SDivEntryIt -> DividentRegUpper != <STR_LIT> ) BuildMI ( * I . getParent ( ) , I

, I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpSignExtend ) ) ;


<s> static DecodeStatus DecodeModImmTiedInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeFPR128RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm


<s> ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> void <ISA_LIT>GOT :: applyGOT0 ( uint64_t pAddress ) { llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin (


<s> Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy ,


<s> SDValue Result ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Result ) ; } else if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( const auto & A : F -> args ( ) ) { if ( A . hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Size ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setHasWinAlloca ( true ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Align ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg ,


<s> case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder


<s> bool IsInteresting = AI . getAllocatedType ( ) -> isSized ( ) && AI . isStaticAlloca ( ) && AI . getAllocationSizeInBits ( * DL ) . getValue ( ) > <NUM_LIT> && ! AI . isUsedWithInAlloca (

) && ! AI . isSwiftError ( ) && ! AI . getMetadata ( <STR_LIT> ) ;


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && ! Subtarget . hasV6Ops ( ) ) { if ( ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand (

MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallConv ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt


<s> SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( PtrMemVT , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , Align ( PtrMemVT . getSizeInBits ( ) / <NUM_LIT> ) , MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; FuncTLVGet = DAG . getZExtOrTrunc ( FuncTLVGet , DL , PtrVT ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getTLSCallPreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ,


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; if ( isSVEDataVectorRegister ( lowerCase ) ) return - <NUM_LIT> ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( RegNum == <NUM_LIT> ) return


<s> unsigned Flag = ELF :: EF_CPU0_NOREORDER ; Flag |= ELF


<s> static inline bool isAdvSIMDModImmType2 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( (


<s> if ( ! SVOp -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) ) return false ; if ( isVectorShiftLeft ( SVOp , DAG , isLeft , ShVal , ShAmt ) || isVectorShiftRight ( SVOp , DAG , isLeft , ShVal , ShAmt ) ) return true ; return false


<s> if ( F . getKind ( ) == MCFragment :: FT_Data || F . getKind ( ) == MCFragment :: FT_CompactEncodedInst ) continue ; if ( F . getKind ( ) == MCFragment :: FT_Relaxable ) { auto & RF = cast < MCRelaxableFragment > ( * I ) ; Relaxable . push_back ( & RF ) ; continue ; } auto canHandle = [ ] ( MCFragment & F ) -> bool { switch ( F . getKind ( ) ) { default : return false ; case MCFragment :: FT_Align : return <ISA_LIT>PadForAlign ; case MCFragment :: FT_BoundaryAlign : return <ISA_LIT>PadForBranchAlign ; } } ; if ( ! canHandle ( F ) ) { Relaxable . clear ( ) ; continue ; } const uint64_t OrigOffset = Layout . getFragmentOffset ( & F ) ; const uint64_t OrigSize = Asm . computeFragmentSize ( Layout , F ) ; MCFragment * FirstChangedFragment = nullptr ; unsigned RemainingSize = OrigSize ; while ( ! Relaxable . empty ( ) && RemainingSize != <NUM_LIT> ) { auto & RF = * Relaxable . pop_back_val ( ) ; if ( padInstructionEncoding ( RF , Asm . getEmitter ( ) , RemainingSize ) ) FirstChangedFragment = & RF ; if ( ! isFullyRelaxed ( RF ) ) break ; } Relaxable . clear ( ) ; if ( FirstChangedFragment ) { Layout . invalidateFragmentsFrom ( FirstChangedFragment


<s> DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( hasBP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> unsigned DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg


<s> PM . add ( create<ISA_LIT>BundlingPass ( * this ) ) ; return true


<s> POPCNTDKind hasPOPCNTD ( ) const { return HasPOPCNTD


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand


<s> machine_mode mode ; gcc_assert ( TARGET_SSE ) ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) { switch ( get_attr_mode ( insn ) ) { case MODE_XI : return <STR_LIT> ; case MODE_OI : return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; case MODE_TI : return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; case MODE_V8DF : return ( TARGET_AVX512DQ ? <STR_LIT> : <STR_LIT> ) ; case MODE_V4DF : return <STR_LIT> ; case MODE_V2DF : return <STR_LIT> ; case MODE_V16SF : return ( TARGET_AVX512DQ ? <STR_LIT> : <STR_LIT> ) ; case MODE_V8SF : return <STR_LIT> ; case MODE_V4SF : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } else if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) ) { enum attr_mode insn_mode = get_attr_mode ( insn ) ; switch ( insn_mode ) { case MODE_XI : case MODE_V8DF


<s> if ( ! printAliasInstr ( MI , Address , STI , O )

) printInstruction ( MI , Address , STI , O ) ;


<s> case SImode : return TARGET_AVX512F ? V16SImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V8SImode : V4SImode ; case DImode : return TARGET_AVX512F ? V8DImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V4DImode : V2DImode ; case SFmode : if ( TARGET_AVX512F ) return V16SFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V8SFmode ; else return V4SFmode ; case DFmode : if ( TARGET_AVX512F ) return V8DFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V4DFmode ; else if ( TARGET_SSE2 ) return


<s> reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetOddSPReg ( ) ; return


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true


<s> const <ISA_LIT>GNULDBackend & getTarget ( ) const { return m_Target


<s> return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) ,


<s> Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } if ( Need0FPrefix ) EmitByte ( <NUM_LIT> ,


<s> for ( const MCInst & Inst : PendingConditionalInsts ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = <NUM_LIT> ; ITState . CurPosition = ~


<s> return DecodeMem ( Inst , insn , Address , Decoder ,


<s> void \ init_section ( ) \ { \ if ( in_section != in_init ) \ { \ in_section = in_init

; \ fprintf ( asm_out_file , <STR_LIT> , INIT_SECTION_ASM_OP ) ; \ } \ }


<s> if ( TARGET_ARM ) emit_insn ( gen_pic_add_dot_plus_eight ( reg , reg , labelno ) ) ; else emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , <NUM_LIT> , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns


<s> case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) return


<s> Offset += getOffsetOfLocalArea ( ) ; } if ( IsWin64Prologue ) { assert ( ! MFI . hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return StackOffset :: getFixed ( - SEHFrameOffset ) ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( FrameReg == TRI -> getFramePtr ( ) ) { Offset += SlotSize ; Offset += FPDelta ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) Offset -= TailCallReturnAddrDelta ; return StackOffset :: getFixed (


<s> DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ; return


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { assert ( ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; MVT NewVT = <STR_LIT> ( EltVT , <NUM_LIT> / VT . getScalarSizeInBits ( ) ) ; SDValue Vec512 = DAG . getNode ( <STR_LIT> , dl , NewVT , DAG . getUNDEF ( NewVT ) , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Vec512 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( <NUM_LIT> < NumElems ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op . getOperand ( <NUM_LIT> ) , dl ) ; MVT OutVT = <STR_LIT> ( EltVT , NumElems


<s> return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( )

== <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ;


<s> else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ishtmcr = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ismma = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isquad = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ispair = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ismmaint = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isno32bit = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> is32bit = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> iscpu = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isldstmask = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> islxvrse = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> islxvrze = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isendian = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isibmld = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isibm128 = <NUM_LIT> ; else { diag ( oldpos ,


<s> unsigned char e = d . perm [ i ] ; gcc_assert ( e < <NUM_LIT> * nelt ) ; which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( which == <NUM_LIT> ) for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_vector_p = ( which != <NUM_LIT>