<s> static void register_svpattern ( ) { auto_vec < string_int_pair , <NUM_LIT> > values ; values . quick_push ( string_int_pair ( <STR_LIT> # UPPER , VALUE ) ) ; AARCH64_FOR_SVPATTERN ( PUSH ) acle_svpattern = lang_hooks . types . simulate_enum_decl ( input_location


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const


<s> break ; case Function :: ExternalLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; EmitAlignment ( F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> , F ) ; O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , IE = I -> end ( ) ; II != IE ; ++


<s> addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID )


<s> unsigned shift_c = <NUM_LIT> / n_elts ; unsigned i ; int hi_val = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( const_vec , i ) ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) & ( ( <NUM_LIT> << el_prec ) - <NUM_LIT> ) ; unsigned index = BYTES_BIG_ENDIAN ? n_elts - i


<s> auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; Optional < unsigned > MaxNumVScale = getMaxVScale ( ) ; assert ( MaxNumVScale && <STR_LIT> ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; unsigned MaxNumElementsPerGather = MaxNumVScale . getValue ( ) * LegalVF . getKnownMinValue ( ) ; return LT . first * MaxNumElementsPerGather


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) HiddenGVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) FnStubs [ Name ] = Mang -> getMangledName ( GV ) ; if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; printOffset ( MO . getOffset ( ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { FnStubs [ Name + <STR_LIT> ] = Name ; Name += <STR_LIT> ; } if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; PrintPICBaseSymbol ( ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ; PrintPICBaseSymbol ( ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; SrcReg = ANDReg ; } const MCInstrDesc & II = TII . get ( Opc ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg ) ; addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOStore


<s> if ( CPUString == <STR_LIT> ) { if ( FullFS . empty ( ) ) FullFS = <STR_LIT> ; else FullFS = <STR_LIT> + FullFS ; } ParseSubtargetFeatures ( CPU , FullFS ) ; switch ( Align ) { case


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; return Opcode ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( Bitcast -> getType ( ) ) ; Value * Row = II -> getOperand ( <NUM_LIT>


<s> case CmpInst :: FCMP_ULT : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULT : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGT : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLT : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLE : SwapArgs = false ; BranchOpc = <STR_LIT> ; break ; default : return false ; } Value * Op0 = CI -> getOperand ( <NUM_LIT> ) , * Op1 = CI -> getOperand ( <NUM_LIT> ) ; if ( SwapArgs ) std :: swap ( Op0 , Op1 ) ; if ( ! <ISA_LIT>FastEmitCompare ( Op0 , Op1 , VT ) ) return false ; BuildMI ( MBB , DL , TII . get ( BranchOpc ) ) . addMBB ( TrueMBB ) ; if ( Predicate == CmpInst :: FCMP_UNE ) { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; } FastEmitBranch ( FalseMBB ) ; MBB -> addSuccessor ( TrueMBB ) ; return true ; } } else if ( ExtractValueInst * EI = dyn_cast < ExtractValueInst > ( BI -> getCondition ( ) ) ) { if ( IntrinsicInst * CI = dyn_cast < IntrinsicInst > ( EI -> getAggregateOperand ( ) ) ) { if ( CI -> getIntrinsicID ( ) == <STR_LIT> || CI -> getIntrinsicID ( ) == <STR_LIT> ) { const MachineInstr * SetMI = <NUM_LIT> ; unsigned Reg = lookUpRegForValue ( EI ) ; for ( MachineBasicBlock :: const_reverse_iterator RI = MBB -> rbegin ( ) , RE = MBB -> rend ( ) ; RI != RE ; ++ RI ) { const MachineInstr & MI = * RI ; if ( MI . modifiesRegister ( Reg ) ) { unsigned Src , Dst , SrcSR , DstSR ; if ( getInstrInfo ( ) -> isMoveInstr ( MI , Src , Dst , SrcSR , DstSR ) ) { Reg = Src ; continue ; } SetMI = & MI ; break ; } const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . hasUnmodeledSideEffects ( ) || TID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) break ; } if ( SetMI


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , <STR_LIT> , NumBytes


<s> return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) && ( MemKind

== BDLMem ) == ( Mem . Length != <NUM_LIT> ) ) ;


<s> const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( *


<s> SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SmallVector < SDValue , <NUM_LIT> > LoMaskElts , HiMaskElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { LoMaskElts . push_back ( DAG . getConstant ( LoLUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; HiMaskElts . push_back ( DAG . getConstant ( HiLUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; } SDValue LoMask = DAG . getBuildVector ( VT , DL , LoMaskElts ) ; SDValue HiMask = DAG . getBuildVector ( VT , DL , HiMaskElts ) ; Lo = DAG . getNode ( <STR_LIT> , DL ,


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isNullConstant ( RHS ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isOneConstant ( LHS . getOperand ( <NUM_LIT> ) ) && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; LHS = CMPCC . getOperand ( <NUM_LIT> ) ; RHS = CMPCC . getOperand


<s> unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) .

addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) ) ;


<s> __builtin_loongarch_iocsrwr_h ( ( unsigned short ) _1 ,


<s> <STR_LIT> CC1 = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; const SDValue Op2 = isa < ConstantSDNode > ( TrueVal1 ) ? FalseVal1 : TrueVal1 ; if ( Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue K2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue TrueVal2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FalseVal2 = Op2 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue V1Tmp = V1 ; SDValue V2Tmp = V2 ; if ( V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 || K2 != FalseVal2 || ! ( ( isGTorGE ( CC1 )

&& isLTorLE ( CC2 ) ) || ( isLTorLE ( CC1 ) && isGTorGE ( CC2 ) ) ) ) return SDValue ( ) ;


<s> void <ISA_LIT>Operand :: print ( raw_ostream & OS


<s> if ( aligned_p && size == <NUM_LIT> && GET_CODE ( x ) != CONST_INT ) { if ( TARGET_V9 ) { assemble_integer_with_op ( <STR_LIT> ,


<s> if ( isInt < <NUM_LIT> > ( Offset - StackSize ) ) Offset -= StackSize ; else StoreInstr = & * MBBI ; MBBI -> getOperand ( Operand ) . setImm ( Offset ) ; ++ MBBI ; } else llvm_unreachable ( <STR_LIT> ) ; } if ( StackSize ) { MachineBasicBlock :: iterator InsertPt = StoreInstr ? StoreInstr : MBBI ; int64_t Delta = - int64_t ( StackSize ) ; if ( StoreInstr && HasFP ) { BuildMI ( MBB , InsertPt , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; } emitIncrement ( MBB , InsertPt , DL , Regs . getStackPointerRegister (


<s> unsigned OffsetScaled = <NUM_LIT> ; while ( OffsetScaled < ObjSizeScaled ) { if ( ObjSizeScaled - OffsetScaled >= <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode2 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> * <NUM_LIT> ) ) ; OffsetScaled += <NUM_LIT> ; OutChains . push_back ( St ) ; continue ; } if ( ObjSizeScaled - OffsetScaled > <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode1 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> ) ) ; OffsetScaled += <NUM_LIT>


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return ( cfun -> has_nonlocal_label || SUBTARGET_FRAME_POINTER_REQUIRED || ( TARGET_ARM &&

TARGET_APCS_FRAME && ! leaf_function_p ( ) ) ) ;


<s> for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( TARGET_SHMEDIA && epilogue_p < <NUM_LIT> ) for ( i = FIRST_TARGET_REG ; i <= LAST_TARGET_REG ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , * live_regs_mask ) ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> ) { rtx adj_reg , tmp_reg , mem ; gcc_assert ( ! TARGET_SHMEDIA && epilogue_p ) ; gcc_assert ( ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] ) ; adj_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; tmp_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; emit_move_insn ( gen_tmp_stack_mem ( Pmode , reg ) , adj_reg ) ; emit_insn ( GEN_MOV ( adj_reg , GEN_INT ( size ) ) ) ; emit_insn ( GEN_ADD3 ( adj_reg , adj_reg , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( tmp_reg , gen_tmp_stack_mem ( Pmode , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( reg , adj_reg ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( adj_reg , mem ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( tmp_reg , mem ) ; emit_use ( tmp_reg )


<s> rtx sh_get_pr_initial_val ( void ) { rtx val = get_hard_reg_initial_val ( Pmode , PR_REG ) ; return gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> ,


<s> OutStreamer . EmitLabel ( StubLabel ) ; OutStreamer . EmitValue ( StubInfo . Pointer


<s> hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const

MachineInstr * UseMI , unsigned UseIdx ) const {


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT>


<s> Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) CPSRDef


<s> SDLoc dl ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; if ( Op . getValueType ( ) == <STR_LIT> && hasHardQuad ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: SINTTOFP_I32_F128 ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ! Desc . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; default : const <ISA_LIT>InstrFMA3Group * FMA3Group = <ISA_LIT>InstrFMA3Info :: getFMA3Group ( MI . getOpcode ( ) ) ; if ( FMA3Group ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return DW_EH_PE_pcrel | ( Model == CodeModel :: Small ?


<s> int n ; int mask ; int max ; max = MAX_INSN_PER_IT_BLOCK ; if ( arm_condexec_count ) arm_condexec_count -- ; if ( arm_condexec_count ) return ; if ( GET_CODE ( body ) != COND_EXEC ) return ; if ( JUMP_P ( insn ) ) return ; predicate = COND_EXEC_TEST ( body ) ; arm_current_cc = get_arm_condition_code ( predicate ) ; n = get_attr_ce_count ( insn ) ; arm_condexec_count = <NUM_LIT> ; arm_condexec_mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; arm_condexec_masklen = n ; for ( ; ; ) { insn = next_nonnote_insn ( insn ) ; if ( ! NONJUMP_INSN_P ( insn ) && ! JUMP_P ( insn ) ) break ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == USE || GET_CODE ( body ) == CLOBBER ) continue ; if ( GET_CODE ( body ) != COND_EXEC ) break ; n = get_attr_ce_count ( insn ) ; if ( arm_condexec_masklen + n > max ) break ; predicate = COND_EXEC_TEST ( body ) ; code = get_arm_condition_code ( predicate ) ; mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; if ( arm_current_cc == code ) arm_condexec_mask |= ( mask << arm_condexec_masklen ) ; else if ( arm_current_cc != ARM_INVERSE_CONDITION_CODE ( code ) ) break ; arm_condexec_count ++


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; unsigned RCSize = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; RCSize =


<s> static void pop ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode


<s> return ( ( reg_addr [ mode ] . addr_mask

[ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != <NUM_LIT> ) ;


<s> return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size (


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment )


<s> PICStyles :: Style getPICStyle ( ) const { return PICStyle


<s> MachineInstr * MI = & * MII ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) { Modified =


<s> static bool canWidenShuffleElements ( ArrayRef <


<s> split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op


<s> return ( __m64 ) __builtin_ia32_psrad ( ( __v2si ) __m , ( __v2si )


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc Result = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; return Result


<s> return SDValue ( ) ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && ( N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; return DAG . getZExtOrTrunc ( V , DL , VT ) ; } if ( SExtVT == <STR_LIT> ) { assert ( <NUM_LIT> == DAG . ComputeNumSignBits ( V ) && <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getUNDEF ( <STR_LIT> ) ) ; } else assert ( SExtVT . getScalarType ( ) != <STR_LIT>


<s> const MCRegisterInfo * getRegInfo ( )


<s> TokError ( <STR_LIT> ) ; return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT>


<s> const BlockAddress * <ISA_LIT>ConstantPoolConstant :: getBlockAddress ( ) const { assert ( isa < BlockAddress > (


<s> return new <ISA_LIT>LoopInstrFormPrep


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , true


<s> if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) ,

Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> case IES_RSHIFT : case IES_PLUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true


<s> Type = ELF :: R_LANAI_25 ; break ; case <STR_LIT> : case FK_Data_4 : Type = ELF :: R_LANAI_32 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_LO16 ; break ; case <STR_LIT>


<s> <ISA_LIT>_32ATTAsmParser ( const Target & T , MCAsmParser & _Parser , TargetMachine & TM ) : <ISA_LIT>ATTAsmParser ( T , _Parser


<s> if ( GET_CODE ( * loc ) == LO_SUM ) return - <NUM_LIT> ; return <NUM_LIT>


<s> return ( uint32x2_t ) __builtin_neon_vpaddv2si ( ( int32x2_t


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>leTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>beTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstPrinter


<s> MachineBasicBlock :: iterator I = slot ; while ( ! done ) { done = ( I == MBB . begin ( ) ) ; if ( ! done ) -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || I -> hasDelaySlot ( ) || isDelayFiller ( MBB , I ) ) break ; if ( delayHasHazard ( I , sawLoad , sawStore , RegDefs , RegUses ) ) { insertDefsUses ( I , RegDefs , RegUses ) ; continue ; } return


<s> const uint64_t Mask = <NUM_LIT> ; int StartIdx = NotSet ; int EndIdx = NotSet ; for ( int Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { int64_t Chunk = getChunk ( UImm , Idx ) ; Chunk = ( Chunk << <NUM_LIT> ) >> <NUM_LIT> ; if ( isStartChunk ( Chunk ) ) StartIdx = Idx ; else if ( isEndChunk ( Chunk ) ) EndIdx = Idx ; } if ( StartIdx == NotSet || EndIdx == NotSet ) return false ; uint64_t Outside = <NUM_LIT> ; uint64_t Inside = Mask ; if ( StartIdx > EndIdx ) { std :: swap ( StartIdx , EndIdx ) ; std :: swap ( Outside , Inside ) ; } uint64_t OrrImm = UImm ; int FirstMovkIdx = NotSet ; int SecondMovkIdx = NotSet ; for ( int Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { const uint64_t Chunk = getChunk ( UImm , Idx ) ; if ( ( Idx < StartIdx || EndIdx < Idx ) && Chunk != Outside ) { OrrImm = updateImm ( OrrImm , Idx , Outside == <NUM_LIT> ) ; if ( FirstMovkIdx == NotSet ) FirstMovkIdx = Idx ; else SecondMovkIdx = Idx ; } else if ( Idx > StartIdx && Idx < EndIdx && Chunk != Inside ) { OrrImm = updateImm ( OrrImm , Idx , Inside != Mask ) ; if ( FirstMovkIdx == NotSet ) FirstMovkIdx = Idx ; else SecondMovkIdx = Idx ; } } assert ( FirstMovkIdx != NotSet && <STR_LIT> ) ; uint64_t Encoding = <NUM_LIT> ; <STR_LIT> ( OrrImm , <NUM_LIT> , Encoding ) ; Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; const bool SingleMovk = SecondMovkIdx == NotSet ; Insn . push_back ( { <STR_LIT> , getChunk ( UImm , FirstMovkIdx ) , <STR_LIT> ( <STR_LIT> , FirstMovkIdx * <NUM_LIT> ) } ) ; if ( SingleMovk ) return true ; Insn . push_back ( { <STR_LIT> , getChunk ( UImm , SecondMovkIdx ) , <STR_LIT> ( <STR_LIT> ,


<s> return ( poly128_t ) __builtin_arm_crypto_vmullp64 ( ( uint64_t )


<s> bool has<ISA_LIT>64 ( ) const { return ( STI . getFeatureBits ( )


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElemBitSize , true ) && SplatBitSize == ElemBitSize ) { SDValue Shift = DAG . getConstant ( SplatBits . getZExtValue ( ) & <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( ByScalar , DL , VT , Op0 , Shift ) ; } BitVector UndefElements ; SDValue Splat = BVN -> getSplatValue ( & UndefElements ) ; if ( Splat ) { SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Splat ) ; return DAG . getNode ( ByScalar , DL , VT , Op0 ,


<s> return ( int32x4_t ) __builtin_neon_vabsv4si


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm ( ) ; else printOperand ( MI , OpNum , O


<s> } if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; if ( ! rs6000_inner_target_options ( args , false ) || ! rs6000_option_override_internal ( false ) || ( cur_tree = build_target_option_node ( & global_options , & global_options_set ) ) == NULL_TREE ) { if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> ) ; return false ; } } target_option_current_node = cur_tree ; rs6000_activate_target_options ( target_option_current_node ) ; if ( rs6000_target_modify_macros_ptr ) { prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; prev_flags = prev_opt -> x_rs6000_isa_flags ; cur_opt = TREE_TARGET_OPTION ( cur_tree ) ; cur_flags = cur_opt -> x_rs6000_isa_flags ; diff_flags = ( prev_flags


<s> unsigned Imm = MI -> getOperand ( opNum ) . getImm ( ) ; if ( Imm > <NUM_LIT> ) { O << Imm ; return ; } bool First = true ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( TagNames ) / sizeof


<s> SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , VT , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Zero , Zero , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast <

AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> bool <ISA_LIT>16TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool *


<s> return ( __m128 ) __builtin_ia32_rsqrt14ss ( ( __v4sf )


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; int32_t SImm = MO1 . getImm ( ) ; bool isAdd = true


<s> default : break ; case <STR_LIT> : return combineZERO_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineMERGE ( N , DCI ) ; case <STR_LIT> : return combineLOAD ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineVECTOR_SHUFFLE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineFP_ROUND ( N ,


<s> static inline bool isDef32 ( const SDNode & N ) { unsigned Opc = N . getOpcode ( ) ; return Opc != <STR_LIT> && Opc != TargetOpcode :: EXTRACT_SUBREG && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc !=

<STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveReg ( SMLoc Loc ) { unsigned Reg = <NUM_LIT> ; int64_t Off ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken ::

Comma ) ) return TokError ( <STR_LIT> ) ;


<s> static const <ISA_LIT>RegisterBankInfo :: ValueMapping * getFprbMapping


<s> * __carry_out = ( __builtin_arm_get_fpscr_nzcvqc ( ) >> <NUM_LIT> ) & <NUM_LIT> ; return


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> ,


<s> SDValue HiPart ; DebugLoc dl = Op . getDebugLoc ( ) ; bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; unsigned char OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << <STR_LIT> ; printAbsAddrOperand ( MI , OpNo


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return MatchOperand_Success ; return MatchOperand_NoMatch ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; Parser . Lex


<s> if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == <NUM_LIT> && Ty -> getStructElementType ( <NUM_LIT> ) -> isFP128Ty ( ) ) return true ; return ( Func && Ty -> isIntegerTy ( <NUM_LIT> ) && isF128SoftLibCall (


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( ! isAM5 && Offset == Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( Offset == - Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( ! isAM5 && Offset == - Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else return false ; } MBB . erase ( MergeInstr ) ; <STR_LIT> AddSub = Offset < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; bool isLd = isLoadSingle ( Opcode ) ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) . cloneMemRefs ( * MI ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . cloneMemRefs ( * MI ) ; } else { int Imm = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Imm ) . add ( predOps ( Pred , PredReg ) ) . cloneMemRefs ( * MI ) ; } } else


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getReg ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = getGR32FromGR64 ( RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! IsShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N ->


<s> return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> if ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , dl ) ; if ( ! OpVT . is128BitVector ( ) ) { unsigned SizeFactor = OpVT . getSizeInBits ( ) / <NUM_LIT> ; MVT VT128 = <STR_LIT> ( OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / SizeFactor ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand


<s> inline bool legitimate_indirect_address_p ( rtx x ,


<s> Target & llvm :: getThe<ISA_LIT>beTarget ( ) { static Target The<ISA_LIT>beTarget


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , IntPtrTy , DAG . getTargetExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move


<s> if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_SET_GOT ) return true ; else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false


<s> isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified


<s> GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , TargetFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , TargetFlags ) ; } else { Result = getAddr ( GN , DAG , TargetFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo

:: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> return ( __m128i ) __builtin_ia32_pbroadcastw128 ( (


<s> rtx sp = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx limit = gen_reg_rtx ( Pmode ) ; rtx requested = gen_reg_rtx ( Pmode ) ; rtx cmp = gen_reg_rtx ( CCUNSmode ) ; rtx jump ; emit_insn ( gen_load_split_stack_limit ( limit ) ) ; if ( CONST_INT_P ( size ) ) emit_insn ( gen_add3_insn ( requested , sp , GEN_INT ( - INTVAL ( size ) ) ) ) ; else { size = force_reg ( Pmode , size ) ; emit_move_insn ( requested , gen_rtx_MINUS ( Pmode , sp , size ) ) ; } emit_insn ( gen_rtx_SET ( cmp , gen_rtx_COMPARE ( CCUNSmode , requested , limit ) ) ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cmp , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump )


<s> unsigned A15SDOptimizer :: createDupLane ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned Reg , unsigned Lane , bool QPR ) { Register Out = MRI -> createVirtualRegister ( QPR ?


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering

( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) {


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false ,


<s> __o = __builtin_aarch64_ld3rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregciv4hi ( __o , <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> O << formatImm ( ( int64_t ) Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print (


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) .

addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector


<s> } else { unsigned ScratchReg = TM . getSubtargetImpl ( ) -> isDarwinABI ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , ScratchReg ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned ShiftBits = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { unsigned Reg = <NUM_LIT> ; if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; return StoreRegToStackSlot ( MF , Reg , isKill


<s> return new TargetLoweringObjectFileMachO ( ) ; } if ( Subtarget -> isTargetLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetWindows ( ) ) return new


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return false ; getParser ( ) . getStreamer ( ) . EmitValue ( Value


<s> } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec (


<s> DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { return selectAddrRegImm ( Addr , Base , Offset ) || selectAddrDefault ( Addr ,


<s> return ELF :: R_<ISA_LIT>_REFLONG ; case FK_PCRel_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PC_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PC_LO32 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_2 : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_REFLONG ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REFLONG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO32 ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_LO32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOTOFF_HI32 ; case <STR_LIT>


<s> if ( elt_size > <NUM_LIT> ) return false ; scalar_int_mode elt_int_mode = int_mode_for_mode ( elt_mode ) . require ( ) ; auto_vec < unsigned char , <NUM_LIT> > bytes ; bytes . reserve ( n_elts * elt_size ) ; for ( unsigned int i = <NUM_LIT> ; i < n_elts ; i ++ ) { bool swap_p = ( ( vec_flags & VEC_ADVSIMD ) != <NUM_LIT> && BYTES_BIG_ENDIAN ) ; rtx elt = CONST_VECTOR_ELT ( op , swap_p ? ( n_elts - <NUM_LIT> - i ) : i ) ; if ( elt_mode != elt_int_mode ) elt = gen_lowpart ( elt_int_mode , elt ) ; if ( ! CONST_INT_P ( elt ) ) return false ; unsigned HOST_WIDE_INT elt_val = INTVAL ( elt ) ; for ( unsigned int byte = <NUM_LIT> ; byte < elt_size ; byte ++ ) { bytes . quick_push ( elt_val & <NUM_LIT> ) ; elt_val >>= BITS_PER_UNIT ; } } unsigned int nbytes = bytes . length ( ) ; for ( unsigned i = <NUM_LIT> ; i < nbytes ; ++ i ) if ( bytes [ i ] != bytes [ i - <NUM_LIT> ] ) return false ; unsigned HOST_WIDE_INT val64 = <NUM_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) val64 |= ( ( unsigned HOST_WIDE_INT ) bytes [ i % nbytes ] << ( i * BITS_PER_UNIT ) ) ; if ( vec_flags & VEC_SVE_DATA ) return aarch64_sve_valid_immediate ( val64 , info ) ; else return aarch64_advsimd_valid_immediate ( val64 , info


<s> bool has_cxx17_empty_base = false ; return ( mips_fpr_return_fields ( valtype , fields , & has_cxx_zero_width_bf , & has_cxx17_empty_base ) == <NUM_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned imm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > (


<s> uint64_t <ISA_LIT>FrameLowering :: calculateMaxStackAlign ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Align MaxAlign = MFI . getMaxAlign ( ) ; Align StackAlign = getStackAlign ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( MFI . hasCalls ( ) ) MaxAlign = ( StackAlign >


<s> if ( TARGET_ARCH64 && type != <NUM_LIT> && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const DataLayout * DL = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand ::


<s> unsigned CC = cast < ConstantSDNode > ( CCVal ) -> getZExtValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpc = Cmp . getOpcode ( ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) || ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) && <STR_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isNullConstant ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDValue BR ; if ( CC == <STR_LIT> ) BR = DAG . getNode ( <STR_LIT> , SDLoc ( N


<s> void <ISA_LIT>InstPrinter :: printImmPlusOneOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNum )


<s> SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && ( ( VT == <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) { SDValue BaseShAmt ; EVT EltVT = VT . getVectorElementType ( ) ; if ( Amt . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned i , j ; for ( i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( Amt . getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; break ; } for ( j = i ; j != NumElts ; ++ j ) { SDValue Arg = Amt . getOperand ( j ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; if ( Arg != Amt . getOperand ( i ) ) break ; } if ( i != NumElts && j == NumElts ) BaseShAmt = Amt . getOperand ( i ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; if ( Amt . getOpcode ( ) == <STR_LIT> && cast < ShuffleVectorSDNode > ( Amt ) -> isSplat ( ) ) { SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( Amt ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , Amt , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } } if ( BaseShAmt . getNode ( ) ) { if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; switch ( Op . getOpcode ( )


<s> opts -> x_unaligned_access = ( TARGET_32BIT_P ( opts -> x_target_flags ) && arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ; } else if ( opts -> x_unaligned_access == <NUM_LIT> && ! ( arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; opts -> x_unaligned_access = <NUM_LIT> ; } if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_schedule_insns = <NUM_LIT> ; else opts -> x_flag_schedule_insns = to -> x_flag_schedule_insns ; if ( optimize_function_for_size_p ( cfun ) && TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_flag_shrink_wrap = false ; else opts -> x_flag_shrink_wrap = to -> x_flag_shrink_wrap ; if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_ipa_ra = <NUM_LIT> ; else opts -> x_flag_ipa_ra = to -> x_flag_ipa_ra ; if ( TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_inline_asm_unified = true ; if ( arm_stack_protector_guard == SSP_GLOBAL && opts -> x_arm_stack_protector_guard_offset_str ) { error ( <STR_LIT> <STR_LIT> , arm_stack_protector_guard_offset_str ) ; } if ( opts -> x_arm_stack_protector_guard_offset_str ) { char * end ; const char * str = arm_stack_protector_guard_offset_str ; errno = <NUM_LIT> ; long offs = strtol ( arm_stack_protector_guard_offset_str , & end , <NUM_LIT> ) ; if ( ! * str || * end || errno ) error ( <STR_LIT> , str , <STR_LIT> ) ; arm_stack_protector_guard_offset = offs


<s> EmitAlignment ( <NUM_LIT> , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; NumberForBB . clear ( ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ;


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute (


<s> bool <ISA_LIT>AdvSIMDScalar :: runOnMachineFunction ( MachineFunction & mf ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget (


<s> auto * BV2 = dyn_cast < BuildVectorSDNode > ( V2 ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { assert ( Mask [ i ] >= - <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != ExpectedMask [ i ] ) { auto * MaskBV = Mask [ i ] < Size ? BV1 : BV2 ; auto * ExpectedBV = ExpectedMask [ i ] < Size ? BV1 : BV2 ; if ( ! MaskBV || ! ExpectedBV || MaskBV -> getOperand ( Mask [ i ] % Size ) != ExpectedBV -> getOperand ( ExpectedMask [ i ] % Size ) ) return false ; } } return


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExtraToken , Loc ) ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { return true ; } while ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { return true ; } } } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; tryConvertingToTwoOperandForm ( Mnemonic , CarrySetting , Operands ) ; if ( ! CarrySetting && shouldOmitCCOutOperand ( Mnemonic , Operands ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( PredicationCode == <STR_LIT> && shouldOmitPredicateOperand ( Mnemonic , Operands ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( ! isThumb ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isImm ( ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( ! isThumb ( ) && Operands . size ( ) > <NUM_LIT> && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) { bool isLoad = ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ; unsigned Idx = isLoad ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>Operand & Op1 = static_cast < <ISA_LIT>Operand & > ( * Operands [ Idx ] ) ; <ISA_LIT>Operand & Op2 = static_cast < <ISA_LIT>Operand & > ( * Operands [ Idx + <NUM_LIT> ] ) ; const MCRegisterClass & MRC = MRI -> getRegClass ( <STR_LIT> ) ; if ( Op1 . isReg ( ) && Op2 . isReg ( ) && MRC . contains ( Op1 . getReg ( ) ) && MRC . contains ( Op2 . getReg ( ) ) ) { unsigned Reg1 = Op1 . getReg ( ) ; unsigned Reg2 = Op2 . getReg ( ) ; unsigned Rt = MRI -> getEncodingValue ( Reg1 ) ; unsigned Rt2 = MRI -> getEncodingValue ( Reg2 ) ; if ( Rt + <NUM_LIT> != Rt2 || ( Rt & <NUM_LIT> ) ) { return Error ( Op2 . getStartLoc ( ) , isLoad ? <STR_LIT> : <STR_LIT> ) ; } unsigned NewReg = MRI -> getMatchingSuperReg ( Reg1 , <STR_LIT> , & ( MRI -> getRegClass ( <STR_LIT> ) ) ) ; Operands [ Idx ] = <ISA_LIT>Operand :: CreateReg ( NewReg , Op1 . getStartLoc ( ) , Op2 . getEndLoc ( ) ) ; Operands . erase ( Operands . begin ( ) + Idx


<s> CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; assert ( ! IsTailCall && <STR_LIT> ) ; passByValArg ( Chain , DL , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , <ISA_LIT>CCInfo , FirstByValReg , LastByValReg , Flags , Subtarget . isLittle ( ) , VA ) ; CCInfo . nextInRegsParam ( ) ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; continue ; } } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( )


<s> LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( DL ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true


<s> setLibcallName ( RTLIB :: SINTTOFP_I32_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UINTTOFP_I32_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UINTTOFP_I32_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OEQ_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OEQ_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UNE_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UNE_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OGE_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OGE_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OLT_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OLT_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB ::


<s> } if ( Cand . BranchBlock -> mayHaveInlineAsmBr ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Cand . BranchTargetBlock || FalseMBB || ! Cand . BranchBlock -> isSuccessor ( Cand . BranchTargetBlock ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Cand . BranchBlock -> succ_size ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } assert ( Cand . BranchBlock -> canFallThrough ( ) && <STR_LIT> ) ; MachineBasicBlock * Succ = ( * Cand . BranchBlock -> succ_begin ( ) == Cand . BranchTargetBlock ) ? * Cand . BranchBlock -> succ_rbegin ( ) : * Cand . BranchBlock -> succ_begin ( ) ; assert ( Succ && <STR_LIT> ) ; if ( ! Succ -> empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Succ -> isSuccessor ( Cand . BranchTargetBlock ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) { if ( SDValue V = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue V = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } if ( VT == <STR_LIT> ) { V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT>


<s> Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue >


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getDarwinCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { assert ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) && <STR_LIT> ) ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_Darwin_<ISA_LIT>_CXX_TLS_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_Darwin_<ISA_LIT>_AAVPCS_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) report_fatal_error ( <STR_LIT> ) ; if ( CC == CallingConv :: CFGuard_Check ) report_fatal_error ( <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF .


<s> if ( ( Op . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOpcode ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( )


<s> void <ISA_LIT>InstPrinter :: printS5ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; Value = SignExtend32 < <NUM_LIT> > ( Value


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) || CPU == <STR_LIT> ) { if ( TargetTriple . getArch ( ) == Triple :: ppc64le ) CPUName = <STR_LIT> ; else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned =


<s> case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2


<s> return __builtin_ia32_vec_ext_v8hi ( ( __v8hi ) __A ,


<s> bool isMSRMask ( ) const { return Kind ==


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> )


<s> rtx op1 = operands [ <NUM_LIT> ] ; rtx sel = operands [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; unsigned int elt = <NUM_LIT> - ( INTVAL ( e ) & <NUM_LIT> ) ; perm [ i ] = GEN_INT ( elt ) ; } if ( ! REG_P ( op0 ) ) op0 = force_reg ( V16QImode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( V16QImode ,


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; BPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex (


<s> void Filler :: insertDefsUses ( MachineBasicBlock :: iterator MI , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { MCInstrDesc MCID = MI -> getDesc ( ) ; unsigned e = MCID . isCall ( ) || MCID . isReturn ( ) ? MCID . getNumOperands ( ) : MI -> getNumOperands ( ) ; if ( MCID . isCall ( ) ) RegDefs . insert ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; unsigned


<s> switch ( addrtype ) { case CRX_REG_REL : fprintf ( file , <STR_LIT> , offset , reg_names [ REGNO ( address . base ) ] ) ; return ; case CRX_POST_INC : switch ( GET_CODE ( address . side_effect ) ) { case PLUS : break ; case MINUS : offset = - offset ; break ; case POST_INC : offset = GET_MODE_SIZE ( output_memory_reference_mode ) ; break ; case POST_DEC : offset = - GET_MODE_SIZE ( output_memory_reference_mode ) ; break ; default : abort ( ) ; } fprintf ( file , <STR_LIT> , offset , reg_names [ REGNO ( address . base ) ] ) ; return ; case CRX_SCALED_INDX : fprintf ( file , <STR_LIT> , offset , reg_names [ REGNO ( address . base ) ] , reg_names [ REGNO ( address . index ) ] , address . scale ) ; return ; case CRX_ABSOLUTE


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == <STR_LIT> ) return <NUM_LIT> ; return <ISA_LIT>TargetLowering :: getNumRegisters ( Context , VT


<s> if ( ! SubIdx ) return MIB . addReg ( Reg , State ) ; if ( Register :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ; return MIB . addReg ( Reg , State , SubIdx


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Width = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLT Ty = MRI . getType ( Src ) ; assert ( ( Ty == LLT :: scalar ( <NUM_LIT> ) || Ty == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; Register ShiftSrc ; int64_t ShiftImm ; if ( ! mi_match ( Src , MRI , m_OneNonDBGUse ( m_any_of ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) , m_GLShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) ) ) ) ) return false ; if ( ShiftImm < <NUM_LIT> || ShiftImm + Width > Ty . getSizeInBits ( ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder & B ) { auto Cst1 = B . buildConstant (


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT>


<s> assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; if ( NumElts < <NUM_LIT> ) StoredVal = DAG . getZeroExtendInReg ( StoredVal , dl , EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) || ( ( StoreVT == <STR_LIT> || StoreVT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( TLI . getTypeAction ( * DAG . getContext ( ) , StoreVT ) == TargetLowering :: TypeWidenVector && <STR_LIT> ) ; EVT WideVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , StoreVT ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT , <NUM_LIT> ) ; StoredVal = DAG . getBitcast ( CastVT , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , StVT , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_64 ; case FK_Data_8 : return RT64_64 ; case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_None && ! IsPCRel )


<s> static bool mmix_pass_by_reference ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || ! argsp ->


<s> else Kind = k_SPRRegisterList ; } if ( Kind == k_RegisterList && Regs . back ( ) . second == <STR_LIT> ) Kind = k_RegisterListWithAPSR ; assert ( llvm :: is_sorted ( Regs ) && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( const auto & P : Regs ) Op -> Registers . push_back ( P . second ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return Op


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo (


<s> unsigned Opcode ; static const uint16_t SCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , } ; static const uint16_t UCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_802 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_805 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_807 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_810 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_860 ; else EFlags |= ELF :: EF_<ISA_LIT>_810 ; if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_FLOAT ; EFlags |= ELF :: EF_<ISA_LIT>_EFV1


<s> MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch =


<s> MI . setOpcode ( <STR_LIT> ) ; HasRt = true ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; HasRt = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: SDiv : return SelectSDiv ( I ) ; case Instruction :: SRem : return SelectSRem ( I ) ; case Instruction :: Call : return SelectCall ( I ) ; case Instruction :: Select : return SelectSelect ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; default : break ; } return


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > (


<s> return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv8hi


<s> case xgene1 : return <NUM_LIT> ; case cortexa15 : case cortexa57 : case exynosm1 : return <NUM_LIT> ; case cortexm7 : case cortexr4 : case cortexr4f


<s> vmlsl_s8 ( int16x8_t a , int8x8_t b , int8x8_t c ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> return ( uint32x4_t ) __builtin_neon_vcgeuv4si ( ( int32x4_t )


<s> MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr , *


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> static rtx gen_frame_load ( rtx reg , rtx frame_reg , int offset ) { return gen_frame_set ( reg , frame_reg , offset , false


<s> unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; case


<s> Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare . getOpcode ( ) , Type , & Compare ) ; if ( ! FusedOpcode ) return false ; Register SrcReg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode


<s> if ( auto * VTy = dyn_cast < ScalableVectorType > ( Ty ) ) if ( VTy -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; if ( CostKind == TTI :: TCK_CodeSize || CostKind == TTI :: TCK_SizeAndLatency ) return LT . first ; if ( CostKind != TTI :: TCK_RecipThroughput ) return <NUM_LIT> ; if ( ST -> isMisaligned128StoreSlow ( ) && Opcode == Instruction :: Store && LT . second . is128BitVector ( ) &&

( ! Alignment || * Alignment < Align ( <NUM_LIT> ) ) ) {


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { emitA64MappingSymbol (


<s> if ( code == PLUS ) { rtx xop0 = XEXP ( addr , <NUM_LIT> ) ; rtx xop1 = XEXP ( addr , <NUM_LIT> ) ; return ( ( is_csky_address_register_rtx_p ( xop0 , strict_p ) && csky_legitimate_index_p ( mode , xop1 , strict_p ) ) || ( is_csky_address_register_rtx_p ( xop1 , strict_p ) && csky_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } return <NUM_LIT>


<s> static MCStreamer * createELFStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && TAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( TAB ) , std :: move ( OW

) , std :: move ( Emitter ) , RelaxAll ) ;


<s> case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return <NUM_LIT> ; case AND


<s> if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> )


<s> SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <NUM_LIT> , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; return cpOut


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset + info


<s> static bool DisassembleThumb1LdSt ( unsigned opA , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; bool Imm5 = ( opA != <NUM_LIT> ) ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( Imm5 ? getT1Imm5 ( insn ) : <NUM_LIT> ) ) ; ++ OpIdx


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> static bool isV256I32Ty ( Type * Ty ) { if ( auto * FVT = dyn_cast < FixedVectorType > ( Ty ) ) return FVT -> getNumElements ( ) == <NUM_LIT> && FVT -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ; return


<s> static void i386_solaris_elf_named_section ( const char * name , unsigned int flags , tree decl ) { if ( TARGET_64BIT && strcmp ( name , <STR_LIT> ) ==


<s> OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( CurSled ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( Ret , getSubtargetInfo (


<s> if ( MEM_P ( operands [ <NUM_LIT> ] ) && MEM_P ( operands [ <NUM_LIT> ] ) ) return TARGET_SSE3 && rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return


<s> bool B = TII -> AnalyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != MF -> begin ( ) && ! TII -> AnalyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; assert ( isThumb2 &&


<s> } if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return


<s> bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot (


<s> if ( new_type == NUM_TYPE_SUFFIXES ) return false ; if ( type != new_type ) { error_at ( location , <STR_LIT> <STR_LIT> , get_vector_type ( new_type ) , argno + <NUM_LIT>


<s> RefFlags |= <ISA_LIT>MCExpr :: VK_TPREL ; break ; case TLSModel :: LocalDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_DTPREL ; break ; case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else if ( PlatformFlag == <STR_LIT> ) { RefFlags |= <ISA_LIT>MCExpr :: VK_SEC ; } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_HI12 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( PlatformFlag == <STR_LIT>


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , mii ) , InstInfo ( nullptr ) , Code16GCC ( false ) { Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( )


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> const DataLayout * getDataLayout ( ) const override { return &


<s> void <ISA_LIT>MCCodeEmitter :: EmitOpcodePrefix ( uint64_t TSFlags , unsigned & CurByte , int MemOperand , const MCInst & MI , const MCInstrDesc & Desc , const MCSubtargetInfo & STI , raw_ostream & OS ) const { unsigned char OpSize = ( TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( OpSize == ( is16BitMode ( STI ) ? <STR_LIT> : <STR_LIT> ) ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS