<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && MI -> isCompare ( ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> removeFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; CompleteCCUsers = true ; continue ; } Reference CCRefs ( getRegReferences ( MI , <STR_LIT> ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = ! CCRefs .


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getCastInstrCost ( Opcode , Dst , Src


<s> Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; MachineBasicBlock :: instr_iterator LI = LastITMI ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , llvm :: next ( LI ) ) ; Modified = true ; ++


<s> m2 = GET_MODE_INNER ( m2 ) ; } msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = <NUM_LIT> ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = <NUM_LIT> ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 )

&& ! complex_p && ( m != E_DFmode || ! TARGET_VSX ) && ( m != E_SFmode || ! TARGET_P8_VECTOR ) && ! small_int_vsx_p ) {


<s> int64_t Value ; if ( ! SOExpr -> EvaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= INT32_MIN && Value <= INT32_MAX ) && <STR_LIT> ) ; } break ; case MCK_GPRPair : if ( Op -> isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op -> getReg (


<s> return BuildMI ( MF , MI . getDebugLoc ( ) , MI . getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI . getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg1 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg2IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; return &


<s> bool isFBits16 ( ) const { return isImmediate < <NUM_LIT> , <NUM_LIT>


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue G = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , G ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG .


<s> Base = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N . getNode ( ) ) , N . getValueType ( ) , Base , OffImm ) ; return


<s> unsigned Opc = <NUM_LIT> , ZeroReg = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( ZeroReg ) ; if ( SrcReg ) MIB . addReg ( SrcReg


<s> for ( i = <NUM_LIT> ; i < nunits ; i ++ ) for ( j = <NUM_LIT> ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + <NUM_LIT> ) * usize - <NUM_LIT> - j ) ; mask = gen_rtx_CONST_VECTOR ( V16QImode ,


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MI . eraseFromParent (


<s> assemble_name ( asm_out_file , thunk_name ) ; putc ( '\n' , asm_out_file ) ; if ( ( ix86_harden_sls & harden_sls_indirect_jmp ) ) fputs ( <STR_LIT> , asm_out_file ) ; } else output_indirect_thunk ( regno


<s> return ( __m256 ) __builtin_ia32_broadcastss256_mask ( ( __v4sf ) __A , ( __v8sf )


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_GD_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_GD_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPOFF_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPOFF_LO32 ; break ; default : return nullptr ; } return MCSymbolRefExpr :: create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = extractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return nullptr ; return MCUnaryExpr :: create ( UE -> getOpcode ( ) ,


<s> if ( findMaskedBFI ( N -> getOperand ( <NUM_LIT> ) , BFI , ExistingMask , Extended ) ) PossExtraMask = N -> getOperand ( <NUM_LIT> ) ; else if ( findMaskedBFI ( N -> getOperand ( <NUM_LIT> ) , BFI , ExistingMask , Extended ) ) PossExtraMask = N -> getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; if ( PossExtraMask . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( PossExtraMask . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t ExtraMask = PossExtraMask -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ExtraMask & ExistingMask ) return SDValue ( ) ; SDValue OldBFIVal = BFI . getOperand ( <NUM_LIT> ) ; SDValue NewBFIVal = BFI . getOperand ( <NUM_LIT> ) ; if ( Extended ) { assert ( VT == <STR_LIT> && BFI . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; OldBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal ) ; NewBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , NewBFIVal ) ; } if ( PossExtraMask . getOperand ( <NUM_LIT> ) != OldBFIVal ) return SDValue ( ) ; BFI = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal , NewBFIVal , BFI . getOperand ( <NUM_LIT> ) , BFI . getOperand ( <NUM_LIT> ) ) ; if ( ( ExtraMask | ExistingMask ) == ( - <NUM_LIT> >> ( <NUM_LIT> - VT . getSizeInBits ( ) ) ) )


<s> static reg_class_t arm_preferred_rename_class ( reg_class_t rclass ) { if ( TARGET_THUMB2 && rclass == GENERAL_REGS ) return LO_REGS ; else return


<s> case CPOP : OS << * getConstpoolOp ( ) ; break ; case Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case RegisterSeq : OS << <STR_LIT> ; OS << RegName ( getRegSeq ( ) . first ) << <STR_LIT> << RegName ( getRegSeq ( ) . second ) << <STR_LIT> ; break ; case RegisterList : OS << <STR_LIT> ; OS << RegName ( getRegList ( ) . List1From ) << <STR_LIT> << RegName ( getRegList ( ) . List1To ) << <STR_LIT> ; OS << RegName ( getRegList ( ) . List2From ) << <STR_LIT> << RegName ( getRegList ( ) . List2To ) << <STR_LIT> ; OS << RegName ( getRegList ( ) . List3From ) << <STR_LIT> << RegName ( getRegList ( ) . List3To


<s> __builtin_ia32_scatterpfqpd ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , (

long long const * ) addr , scale , hint ) ;


<s> } if ( InConstantPool && MI -> getOpcode ( ) != <STR_LIT> ) { OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Pic =


<s> if ( Opcode == Instruction :: And ) { if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) return <NUM_LIT> ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue


<s> void <ISA_LIT>TargetELFStreamer :: emitTextAttribute ( unsigned


<s> return getSTI ( ) . getFeatureBits (


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream &


<s> O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O <<


<s> unsigned Alignment = LI -> getAlignment ( ) ; unsigned ABIAlignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; if ( Alignment == <NUM_LIT> ) Alignment = ABIAlignment ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg , Alignment ) ) return false ; updateValueMap ( I


<s> bool isValidEndState ( ) { return State ==


<s> if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) { OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( i + <NUM_LIT> < RVLocs . size ( ) && RVLocs [ i + <NUM_LIT> ] . getLocReg ( ) == VA . getLocReg ( ) ) { SDValue NV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVals [ i + <NUM_LIT> ] ) ; OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , NV ) ; ++ i ; } } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVal , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 , rtx reg3 ) { if ( flag_stack_clash_protection ) return output_probe_stack_range_stack_clash ( reg1 , reg2


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; LL = <STR_LIT> ; SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB =


<s> if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } if ( F . hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; unsigned RetReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( Reg ) ; RetRegs . push_back ( RetReg ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ; return


<s> unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( CPTy ) ; if ( Align == <NUM_LIT> ) Align = MF . getDataLayout ( ) . getTypeAllocSize ( CPTy ) ; MachineConstantPool * MCP = MF . getConstantPool ( ) ; return MCP -> getConstantPoolIndex ( CPVal , Align


<s> static bool MorphToF128Reg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT>


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond . back ( ) . getImm ( ) ) ; Cond . back ( ) = MachineOperand ::

CreateImm ( Opposite<ISA_LIT>CC ( CC ) ) ;


<s> } else if ( Offset > <NUM_LIT> * Chunk ) { assert ( Is64Bit && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Rax , RegState :: Kill ) . setMIFlag ( Flag ) ; if ( isSub ) Offset = - ( Offset - SlotSize ) ; else Offset = Offset + SlotSize ; BuildMI ( MBB , MBBI , DL , TII . get ( MovRIOpc ) , Rax ) . addImm ( Offset ) . setMIFlag ( Flag ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Rax ) . addReg ( Rax ) . addReg ( StackPtr ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Rax ) . addReg ( Rax ) , StackPtr , false , <NUM_LIT> ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , StackPtr ) , StackPtr , false , <NUM_LIT> ) ; return ; } } while ( Offset ) { uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == SlotSize ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : TRI ->


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } for ( auto & Block : VPTBlocks ) { if ( Block . IsPredicatedOn ( VCTP ) ) continue ; if ( ! Block . HasNonUniformPredicate ( ) || ! isVCTP ( Block . getDivergent ( ) -> MI ) ) { CannotTailPredicate = true ; return ; } SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ; ) ; CannotTailPredicate = true ; return ; } } Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA -> getReachingDef ( VCTP , NumElements ) >= <NUM_LIT> ) { CannotTailPredicate = true ; return ; } MachineBasicBlock * InsertBB = InsertPt -> getParent ( ) ; if ( ! RDA -> isReachingDefLiveOut ( InsertPt , NumElements ) ) { if ( auto * ElemDef = RDA -> getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( IsSafeToMove < MachineBasicBlock :: reverse_iterator > (


<s> if ( style >= <NUM_LIT> ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( style < <NUM_LIT> ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S2 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr ) { if ( ! isSupportedType ( Val -> getType ( ) ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; ArgInfo ArgRetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM ==


<s> void <ISA_LIT>AsmPrinter :: printCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> if ( ! Subtarget -> useConstIslands ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; } unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error


<s> static bool isALUArithLoOpcode ( unsigned Opcode ) { return false


<s> FunctionPass * llvm :: create<ISA_LIT>FixupLEAs ( ) { return new FixupLEAPass (


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I ->


<s> return ( ( vec_double2 ) ( si_shufb ( ( qword ) ( a ) , (

qword ) ( b ) , ( qword ) ( pattern ) ) ) ) ;


<s> if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) == Load2 -> getOperand ( <NUM_LIT> ) && Load1 -> getOperand ( <NUM_LIT> ) == Load2 -> getOperand ( <NUM_LIT> ) ) { if ( cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op2 = Load1 -> getOperand ( <NUM_LIT> ) ; if ( ! isa < RegisterSDNode > ( Op2 ) || cast < RegisterSDNode > ( Op2 ) -> getReg ( ) != <NUM_LIT> ) return <NUM_LIT> ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand (


<s> for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { User * First = dyn_cast < User > ( Pair . first ) ; User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U


<s> void <ISA_LIT>CodeEmitter :: emitGlobalAddress ( GlobalValue * GV , unsigned Reloc , bool NeedStub


<s> if ( IsTailCall ) return ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> )

) . addReg ( <STR_LIT> , RegState :: Undef ) ;


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT (


<s> void addLiveInAttr ( unsigned VReg , <STR_LIT> Flags ) { LiveInAttrs . push_back ( std :: make_pair (


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ? <STR_LIT> (


<s> if ( llvm :: all_of ( Mask , [ ] ( int Idx ) { return Idx < <NUM_LIT> ; } ) ) { DCI . CombineTo ( Root . getNode ( ) , getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ) ; return true ; } int MaskSize = Mask . size ( ) ; bool UseInput0 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return <NUM_LIT> <= Idx && Idx < MaskSize ; } ) ; bool UseInput1 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return MaskSize <= Idx ; } ) ; if ( UseInput0 && UseInput1 ) return false ; else if ( UseInput1 ) { std :: swap ( Input0 , Input1 ) ; ShuffleVectorSDNode :: commuteMask ( Mask ) ; } assert ( Input0 && <STR_LIT> ) ; HasPSHUFB |= ( Op . getOpcode ( ) == <STR_LIT> ) ; if ( Op -> isOnlyUserOf ( Input0 . getNode ( ) ) && combine<ISA_LIT>ShufflesRecursively ( Input0 , Root , Mask , Depth + <NUM_LIT> , HasPSHUFB , DAG , DCI , Subtarget ) ) return true ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { Mask = std :: move ( WidenedMask ) ; WidenedMask . clear ( ) ; } return combine<ISA_LIT>ShuffleChain ( Input0 , Root , Mask , Depth , HasPSHUFB ,


<s> assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = <STR_LIT> ( Shifter . Val ) ; return ( Val == <NUM_LIT> || Val == <NUM_LIT>


<s> const <ISA_LIT>Subtarget * getSubtargetImpl (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isShiftedImm ( ) ) { addExpr ( Inst , getShiftedImmVal ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( getShiftedImmShift ( ) ) ) ; } else { addExpr ( Inst , getImm (


<s> Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( ! FirstElt ) return false ; EVT VT = Bvec -> getValueType ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) if ( dyn_cast < ConstantSDNode > ( Bvec -> getOperand ( i ) ) != FirstElt ) return false ; ConstVal = FirstElt -> getZExtValue ( ) ; return true


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > <NUM_LIT> ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg .


<s> SDValue Value , Overflow ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; unsigned BaseOp = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } if ( BaseOp ) { SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; Value = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; Overflow = Value . getValue ( <NUM_LIT> ) ; } return std :: make_pair (


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } instantiateCondBranch ( MBB , DL , TBB , Cond ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded =


<s> const TargetRegisterClass * QPRs = TRI . getRegClass ( <STR_LIT> ) ; SetVector < MachineInstr * > FalseLanesUnknown ; SmallPtrSet < MachineInstr * , <NUM_LIT> > FalseLanesZero ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Predicated ; MachineBasicBlock * Header = ML . getHeader ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto & MI : * Header ) { if ( ! shouldInspect ( MI ) ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; bool isPredicated = isVectorPredicated ( & MI ) ; bool retainsOrReduces = retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ; if ( isPredicated ) Predicated . insert ( & MI ) ; if ( producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) FalseLanesZero . insert ( & MI ) ; else if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; else if ( ! isPredicated && retainsOrReduces ) { LLVM_DEBUG ( dbgs ( ) <<


<s> int Len = HalfSize ; for ( ; Len > <NUM_LIT> ; -- Len ) if ( ! Zeroable [ Len - <NUM_LIT> ] ) break ; assert ( Len > <NUM_LIT> && <STR_LIT> ) ; SDValue Src ; int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( i > M || M >= HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask ,


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; } else { return false ; } } if ( VT == <STR_LIT> ) return false ; if ( Fast ) * Fast = true ; return


<s> bool InstrUsesReg ( const MbbIterator & Instr , const MachineOperand * Reg ) { for ( MachineInstr :: const_mop_iterator Mop = Instr -> operands_begin ( ) ; Mop != Instr -> operands_end ( ) ; ++ Mop ) { if ( isSameOperand ( * Mop ,


<s> if ( ( ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) || GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC ) ) && GET_CODE ( PATTERN ( NEXT_INSN ( PREV_INSN ( insn ) ) ) ) != SEQUENCE && get_attr_needs_delay_slot ( insn ) == NEEDS_DELAY_SLOT_YES ) return <NUM_LIT> ; if ( sh_cpu == CPU_SH2E && GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && get_attr_type ( insn ) == TYPE_CBRANCH && GET_CODE ( PATTERN ( NEXT_INSN ( PREV_INSN ( insn ) ) ) ) != SEQUENCE ) return <NUM_LIT> ; if ( GET_CODE ( insn ) == INSN ) { int sum = <NUM_LIT> ; rtx body = PATTERN ( insn ) ; const char * template ; char c ; int maybe_label = <NUM_LIT> ; if ( GET_CODE ( body ) == ASM_INPUT ) template = XSTR ( body , <NUM_LIT> ) ; else if ( asm_noperands ( body ) >= <NUM_LIT> ) template = decode_asm_operands ( body , NULL , NULL , NULL , NULL ) ; else return <NUM_LIT> ; do { int ppi_adjust = <NUM_LIT> ; do c = *


<s> const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned CarryOutReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT>


<s> return ( int16_t ) __builtin_aarch64_sqabshi


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) )


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = N0 . getValueType ( ) ; SDLoc DL ( N ) ; if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG


<s> } if ( ! OneUseConstantOp && ! HasVariableMask ) return SDValue ( ) ; SDLoc DL ( Root ) ; APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT> ) ; APInt ConstantElts ( NumMaskElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > ConstantBitData ( NumMaskElts , APInt :: getZero ( MaskSizeInBits ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { UndefElts . setBit ( i ) ; continue ; } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL ( const Target


<s> return ( __mmask8 ) __builtin_ia32_ucmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue N , SDValue & Base , SDValue & Disp ) { <ISA_LIT>ISelAddressMode AM ; if ( MatchAddress ( N , AM ) ) return false ; EVT VT = N . getValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM .


<s> return ( __m128d ) __builtin_ia32_cmpeqsd ( ( __v2df ) __A , ( __v2df )


<s> SmallVector < StringRef , <NUM_LIT> > Fields ; RegString . split ( Fields , <STR_LIT> ) ; if ( Fields . size ( ) == <NUM_LIT> ) return - <NUM_LIT> ; assert ( Fields . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Ops ; bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned


<s> auto NextBB = std :: next ( MBBI ) ; if ( NextBB == MBB . getParent ( ) -> end ( ) ) return false ; return MBB . isSuccessor (


<s> if ( TII -> AnalyzeBranch ( * HBB , TBB , FBB , HeadCond ) ) { continue ; } if ( ! TBB || TBB == HBB ) { continue ; } SmallVector < MachineOperand , <NUM_LIT> > TrueCond ; MachineBasicBlock * TBB_TBB = nullptr , * TBB_FBB = nullptr ; if ( TII -> AnalyzeBranch ( * TBB , TBB_TBB , TBB_FBB , TrueCond ) ) { continue ; } MachineInstr * HeadCmpMI = findSuitableCompare ( HBB ) ; if ( ! HeadCmpMI ) { continue ; } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm


<s> bool <ISA_LIT>AsmParser :: parseDirectiveRegSave ( SMLoc L , bool IsVector ) { if ( ! UC . hasFnStart ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } struct CleanupObject { SmallVector < MCParsedAsmOperand * , <NUM_LIT> > Operands ; ~ CleanupObject ( ) { for ( unsigned I = <NUM_LIT> , E = Operands . size ( ) ; I != E ; ++ I ) delete Operands [ I ] ; } } CO ; if ( parseRegisterList ( CO . Operands ) ) return false ; <ISA_LIT>Operand * Op = ( <ISA_LIT>Operand * ) CO . Operands [


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return Op ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; unsigned SubVecNumElems = SubVecVT . getVectorNumElements ( ) ; assert ( IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT MinVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; MVT WideOpVT = OpVT ; if ( OpVT . getSizeInBits ( ) < MinVT . getStoreSizeInBits ( ) ) WideOpVT = MinVT ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( WideOpVT ) ; SDValue WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; auto ExtractSubVec = [ & ] ( SDValue V ) { return ( WideOpVT == OpVT ) ? V : DAG . getNode ( <STR_LIT> , dl , OpVT , V , ZeroIdx ) ; } ; if ( Vec . isUndef ( ) ) { if ( IdxVal != <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ; WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , ShiftBits ) ; } return ExtractSubVec ( WideSubVec ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; Vec = ShiftRight ? DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) : Vec ; return ExtractSubVec ( Vec ) ; } if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef


<s> if ( MemAccess -> getAlignment ( ) < StoreSize || ! MemAccess -> getOffset ( ) . isUndef ( ) ) return false ; if ( MMO -> getOffset ( ) % StoreSize != <NUM_LIT> ) return false ; if ( const PseudoSourceValue * PSV = MMO -> getPseudoValue ( ) ) if ( ( PSV -> isGOT ( ) || PSV -> isConstantPool ( ) ) ) return true ; if ( BasePtr . getNumOperands ( ) ) if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( BasePtr . getOperand ( <NUM_LIT> ) ) ) { if ( GA -> getOffset ( ) % StoreSize != <NUM_LIT> ) return false ; const GlobalValue * GV = GA -> getGlobal ( ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> getPointerAlignment ( DL ) . value ( ) < StoreSize ) return false ; } return true


<s> FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return


<s> for ( const auto & Op : x86OperandSets [ insn -> spec -> operands ] ) { switch ( Op . encoding ) { case ENCODING_NONE : case ENCODING_SI : case ENCODING_DI : break ; CASE_ENCODING_VSIB : if ( needVVVV ) needVVVV = hasVVVV & ( ( insn -> vvvv & <NUM_LIT> ) != <NUM_LIT> ) ; if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( fixupReg ( insn , & Op ) ) return - <NUM_LIT> ; if ( Op . encoding != ENCODING_REG && insn -> eaDisplacement == EA_DISP_8 ) insn -> displacement *= <NUM_LIT> << ( Op . encoding - ENCODING_VSIB ) ; break ; case ENCODING_REG : CASE_ENCODING_RM : if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( fixupReg ( insn , & Op ) ) return - <NUM_LIT> ; if ( Op . encoding != ENCODING_REG && insn -> eaDisplacement == EA_DISP_8 ) insn -> displacement *= <NUM_LIT> << ( Op . encoding - ENCODING_RM ) ; break ; case ENCODING_IB : if ( sawRegImm ) { insn -> immediates [ insn -> numImmediatesConsumed ] = insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] & <NUM_LIT> ; ++ insn -> numImmediatesConsumed ; break ; } if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( Op . type == TYPE_XMM || Op . type == TYPE_YMM ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case ENCODING_RB : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RW


<s> MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> emitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: emitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> emitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> emitValue ( TOCDeltaExpr


<s> if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG .


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) || check ( ! hasThumb ( ) , L , <STR_LIT> ) ) return true ; if ( ! isThumb ( ) ) SwitchMode (


<s> unsigned Idx = <NUM_LIT> ; bool isThumb = false ; if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { isThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer == '8' ) { <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '7' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ]


<s> unsigned FirstReg = <NUM_LIT> ; unsigned NumRegs = <NUM_LIT> ; if ( State -> getCallingConv ( ) != CallingConv :: Fast ) { unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; const ArrayRef < MCPhysReg > IntArgRegs = ABI . GetByValArgRegs ( ) ; const MCPhysReg * ShadowRegs = ABI . IsO32 ( ) ? IntArgRegs . data ( ) : <ISA_LIT>64DPRegs ; assert ( ! ( Align % RegSizeInBytes ) && <STR_LIT> <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs ) ; if ( ( Align > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg


<s> case CCValAssign :: AExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; ( void ) Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address


<s> ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( SubRegIdx != <STR_LIT> && SubRegIdx != <STR_LIT> ) continue ; SDValue Move = N -> getOperand ( <NUM_LIT> ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; bool NeedsStackRealignment = RegInfo . needsStackRealignment ( MF ) ; DebugLoc DL ; if ( ! NeedsStackRealignment && MFI . getMaxAlign ( ) > getStackAlign ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; uint64_t NumBytes = MFI . getStackSize ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { NumBytes = STI . getAdjustedFrameSize ( NumBytes ) ; } NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; if ( ! FuncInfo -> isLeafProc ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; assert ( ( RuntimeAlign == None || ! FuncInfo -> isLeafProc ( ) ) && <STR_LIT> ) ; emitSPAdjustment ( MF , MBB , MBBI , - ( int64_t ) NumBytes , RuntimeAlign ) ; if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm (


<s> unsigned PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; const int64_t SSPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const unsigned MemOpndSlot = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( MemOpndSlot + i ) , SSPOffset ) ; else MIB . add ( MI . getOperand ( MemOpndSlot + i ) ) ; } MIB . addReg ( SSPCopyReg ) ; MIB . setMemRefs (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getIConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value . getSExtValue ( ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; MachineInstr * Extract = emitExtractVectorElt ( DstReg , DstRB , NarrowTy , SrcReg , LaneIdx


<s> if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getTargetConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , SubVec , ZeroIdx ) ; Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; if ( Vec . isUndef ( ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; if ( ShiftRight != <NUM_LIT> ) SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftRight , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( IdxVal + SubVecNumElems == NumElems ) { SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( SubVecNumElems * <NUM_LIT> == NumElems ) { Vec = DAG . getNode ( <STR_LIT> , dl , SubVecVT , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , Vec , ZeroIdx ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef ,


<s> bool ISASupported = ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> inMicro<ISA_LIT>Mode ( ) && Subtarget -> has<ISA_LIT>32 ( ) ; TargetSupported = ISASupported && TM . isPositionIndependent ( ) && ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . IsO32


<s> pTarget &= <NUM_LIT> ; pTarget |= pImm & <NUM_LIT> ; pTarget |= ( pImm & <NUM_LIT> ) << <NUM_LIT> ; return pTarget


<s> void startExplicitITBlock ( <STR_LIT> Cond , unsigned Mask ) { assert ( ! inITBlock ( ) ) ; ITState . Cond


<s> LowerFormalArguments_64 ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>64 ) ; const unsigned ArgArea = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA .


<s> assert ( WidenNumElts > InNumElts && WidenNumElts % InNumElts == <NUM_LIT> && <STR_LIT> ) ; EVT EltVT = NVT . getVectorElementType ( ) ; SDLoc dl ( InOp ) ; if ( InOp . getOpcode ( ) == <STR_LIT> && InOp . getNumOperands ( ) == <NUM_LIT> ) { SDValue N1 = InOp . getOperand ( <NUM_LIT> ) ; if ( ( <STR_LIT> ( N1 . getNode ( ) ) && FillWithZeroes ) || N1 . isUndef ( ) ) { InOp = InOp . getOperand ( <NUM_LIT> ) ; InVT = InOp . getSimpleValueType ( ) ; InNumElts = InVT . getVectorNumElements ( ) ; } } if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> (


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ) { BuildCondBr ( MBB , TBB , DL , Cond ) ; BuildMI ( & MBB , DL , get (


<s> const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Subtarget . is<ISA_LIT>64 ( ) ) return & <STR_LIT> ; return &


<s> ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT (


<s> unsigned SABIAlignment = DL . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ; bool Aligned = S -> getAlignment ( ) == <NUM_LIT> || S -> getAlignment ( ) >= SABIAlignment ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) ,


<s> const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; if ( ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> <NUM_LIT>


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg


<s> bool isDstIdx8 ( ) const { return isMem8 ( ) &&


<s> unsigned Register = QPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> __i1 = __i1 << <NUM_LIT> | ( unsigned char ) __b4 ; __i0 = ( unsigned char ) __b3 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b2 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b1 ; __i0 = __i0 << <NUM_LIT> | (


<s> bool RegDefsUses :: isRegInSet ( const BitVector & RegSet , unsigned Reg ) const { for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . test ( * AI ) ) return true ; return


<s> uint64_t Value = CE -> getValue ( ) ; return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <=


<STR_LIT> ( __res ) , <STR_LIT> ( __dtmp ) : ) ;


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( Subtarget . isV9 ( ) ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else llvm_unreachable ( <STR_LIT>


<s> float64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) <<

<STR_LIT> << getRegisterName ( Reg1 ) << <STR_LIT> ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr ; return


<s> <ISA_LIT>MCAsmInfoELF :: <ISA_LIT>MCAsmInfoELF ( const Triple & T ) { if ( T . getArch ( ) == Triple :: aarch64_be ) IsLittleEndian = false ; AssemblerDialect = AsmWriterVariant == Default ? Generic : AsmWriterVariant ; CodePointerSize = <NUM_LIT> ; AlignmentIsInBytes = false


<s> static void GetMemOperands ( const MachineInstr * MI , unsigned long & baseReg , unsigned long & indexReg ) { if ( ! MI -> memoperands_empty ( ) && ! ( ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) || ( MI -> getFlags ( ) & MachineInstr :: FrameDestroy ) ) ) { int index = getMemLocation ( MI ) ; baseReg = MI -> getOperand ( index ) . getReg ( ) ; indexReg = MI -> getOperand ( index + <NUM_LIT> ) . getReg ( ) ; } else { baseReg = <STR_LIT> ; indexReg = <STR_LIT>


<s> case Match_rGPR : return hasV8Ops ( ) ? <STR_LIT> : <STR_LIT> ; case Match_DPR : return hasD32 ( ) ? <STR_LIT> : <STR_LIT> ; case Match_DPR_RegList : return hasD32 ( ) ?


<s> unsigned VF = cast < VectorType > ( SrcTy ) -> getNumElements ( ) ; for ( unsigned P = <NUM_LIT> ; P < Log2Diff ; ++ P ) { if ( NumParts > <NUM_LIT> ) NumParts /= <NUM_LIT> ; Cost += NumParts ; } if ( VF == <NUM_LIT> && SrcTy -> getScalarSizeInBits ( ) == <NUM_LIT> && DstTy -> getScalarSizeInBits ( )


<s> if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_LD ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { rtx lhs = SET_DEST ( body ) ; if ( GET_CODE ( lhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn


<s> void <ISA_LIT>InstPrinter :: printVectorListOneAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (


<s> for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg ,


<s> if ( <STR_LIT> ( In . getOperand ( <NUM_LIT> ) . getNode ( ) , C , false ) ) { return C . isMask ( VT . getScalarSizeInBits ( ) ) ? In . getOperand ( <NUM_LIT> ) : SDValue ( ) ; } return SDValue


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleSoftFloat (


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) ,


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasAVX2 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; if ( NumElts == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = l * NumLaneElts ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i +


<s> unsigned ShiftVal = <STR_LIT> ( MO1 . getImm ( ) ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) | ( ShiftVal == <NUM_LIT> ? <NUM_LIT> : ( <NUM_LIT> << ShiftVal ) ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind (


<s> bool ix86_memtag_can_tag_addresses ( ) { return ix86_lam_type !=


<s> emit_move_insn ( src_addr , plus_constant ( src_addr , <NUM_LIT> ) ) ; emit_move_insn ( to , temp ) ; copied += <NUM_LIT> ; } if ( copied < bytes ) move_by_pieces ( adjust_address ( dest , BLKmode , copied ) , adjust_automodify_address ( src , BLKmode , src_addr , copied ) , bytes - copied , align , <NUM_LIT> ) ; return <NUM_LIT> ; } if ( align < <NUM_LIT> || ( bytes % <NUM_LIT> != <NUM_LIT> ) ) return <NUM_LIT> ; if ( TARGET_HARD_SH4 ) { if ( bytes < <NUM_LIT> ) return <NUM_LIT> ; else if ( bytes == <NUM_LIT> ) { rtx func_addr_rtx = gen_reg_rtx ( Pmode ) ; rtx r4 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; rtx r5 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; function_symbol ( func_addr_rtx , <STR_LIT> , SFUNC_STATIC ) ; force_into ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , r4 ) ; force_into ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , r5 ) ; emit_insn ( gen_block_move_real_i4 ( func_addr_rtx ) ) ; return <NUM_LIT> ; } else if ( ! TARGET_SMALLCODE ) { const char * entry_name ; rtx func_addr_rtx = gen_reg_rtx ( Pmode ) ; int dwords ; rtx r4 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; rtx r5 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; rtx r6 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; entry_name = ( bytes & <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; function_symbol ( func_addr_rtx , entry_name , SFUNC_STATIC ) ; force_into ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , r4 ) ; force_into ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , r5 ) ; dwords = bytes >> <NUM_LIT> ; emit_insn ( gen_move_insn ( r6 , GEN_INT ( dwords - <NUM_LIT> ) ) ) ; emit_insn ( gen_block_lump_real_i4 ( func_addr_rtx ) ) ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( bytes < <NUM_LIT> ) { char entry [ <NUM_LIT> ] ; rtx func_addr_rtx = gen_reg_rtx ( Pmode


<s> rtx sh_gen_truncate ( machine_mode mode , rtx x , int need_sign_ext ) { enum rtx_code code = TRUNCATE ; if ( GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) { rtx inner = XEXP ( x , <NUM_LIT> ) ; machine_mode inner_mode = GET_MODE ( inner ) ; if ( inner_mode == mode ) return inner ; else if ( GET_MODE_SIZE ( inner_mode ) >= GET_MODE_SIZE ( mode ) )


<s> return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg = DAG . getConstant ( ~ <NUM_LIT> , MaskVT ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , MaskInReg ,


<s> Inst . addOperand ( MCOperand :: createImm ( - ( uint32_t )


<s> ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo (

<ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , JITInfo ( ) {


<s> const char * output_call_mem ( rtx * operands ) { if ( TARGET_INTERWORK && ! arm_arch5 ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else if ( regno_use_in ( LR_REGNUM , operands [ <NUM_LIT> ] )


<s> if ( <ISA_LIT>16HardFloat ) set<ISA_LIT>16HardFloatLibCalls ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> bool useFPForScavengingIndex ( const MachineFunction & MF ) const


<s> return ( __m512i ) __builtin_ia32_vpopcountq_v8di_mask ( ( __v8di ) __A , ( __v8di )


<s> if ( Revert ) return ; auto ValidateRanges = [ ] ( MachineInstr * Start , MachineInstr * End , <ISA_LIT>BasicBlockUtils * BBUtils , MachineLoop & ML ) { MachineBasicBlock * TgtBB = End -> getOpcode ( ) == <STR_LIT> ? End -> getOperand ( <NUM_LIT> ) . getMBB ( ) : End -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( TgtBB != ML . getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML . getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML . getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( isWhileLoopStart ( * Start ) ) { MachineBasicBlock * TargetBB = getWhileLoopStartTargetBB ( * Start ) ; if ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( TargetBB ) || ! BBUtils -> isBBInRange ( Start , TargetBB , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> static void addOperands ( MachineInstrBuilder & MIB , ArrayRef < MachineOperand > MOs , int PtrOffset = <NUM_LIT> ) { unsigned NumAddrOps = MOs . size ( ) ; if ( NumAddrOps < <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; addOffset ( MIB , PtrOffset ) ; } else { assert ( MOs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) { const MachineOperand & MO = MOs [ i ] ; if ( i == <NUM_LIT> && PtrOffset != <NUM_LIT> ) { assert ( ( MO . isImm ( ) || MO . isGlobal ( ) ) && <STR_LIT> ) ; if ( MO . isImm


<s> loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; } else { loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; } } rtx_insn * insn = ( rtx_insn * ) insn_ ; struct loongarch_address_info addr = { } ; if ( insn ) { rtx_insn * next = next_nonnote_nondebug_insn_bb ( insn ) ; if ( next ) { rtx set = single_set ( next ) ; if ( set && SET_SRC ( set ) ==


<s> default : return false ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( <STR_LIT> ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! <STR_LIT> ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned NewOpc ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT>


<s> inline static int64_t LO32 ( int64_t imm ) { return ( int32_t )


<s> bool <ISA_LIT>TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasDQI ( ) && BitcastVT == <STR_LIT> ) return false ; return TargetLowering :: isLoadBitCastBeneficial ( LoadVT ,


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst


<s> void <ISA_LIT>InstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr

* > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const {


<s> if ( producesDoubleWidthResult ( MI ) ) return true ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; int NumElements = VT . getVectorNumElements ( ) ; SDLoc DL ( Op ) ; bool Is1BitVector = ( VT . getVectorElementType ( ) == <STR_LIT> ) ; assert ( ( VT . getSizeInBits ( ) != <NUM_LIT> || Is1BitVector ) && <STR_LIT> ) ; bool V1IsUndef = V1 . isUndef ( ) ; bool V2IsUndef = V2 . isUndef ( ) ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , DL , V1 , V2 , NewMask ) ; } int MaskUpperLimit = Mask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; APInt Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . isAllOnesValue ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( Mask , WidenedMask ) ) { MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT

. getScalarSizeInBits ( ) * <NUM_LIT> ) ;


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t


<s> for ( int i = <NUM_LIT> ; i != ( int ) Index ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != ( int ) Length ; ++ i ) ShuffleMask . push_back ( i + <NUM_LIT> ) ; for ( int i = Index + Length ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( - <NUM_LIT> ) ; Value * SV = Builder . CreateShuffleVector ( Builder . CreateBitCast ( Op0 , ShufTy ) , Builder . CreateBitCast ( Op1 , ShufTy ) , ShuffleMask ) ; return Builder . CreateBitCast ( SV , II . getType ( ) ) ; } Constant * C0 = dyn_cast < Constant > ( Op0 ) ; Constant * C1 = dyn_cast < Constant > ( Op1 ) ; ConstantInt * CI00 = C0 ? dyn_cast_or_null < ConstantInt > ( C0 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; ConstantInt * CI10 = C1 ? dyn_cast_or_null < ConstantInt > ( C1 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; if ( CI00 && CI10 ) { APInt V00 = CI00 -> getValue ( ) ; APInt V10 = CI10 -> getValue ( ) ; APInt Mask = APInt :: getLowBitsSet ( <NUM_LIT> , Length ) . shl ( Index ) ; V00 = V00 & ~ Mask ; V10 = V10 . zextOrTrunc ( Length ) . zextOrTrunc ( <NUM_LIT> ) . shl ( Index ) ; APInt Val = V00 | V10 ; Type * IntTy64 = Type :: getInt64Ty ( II . getContext ( ) ) ; Constant * Args [ ] = { ConstantInt :: get ( IntTy64 , Val . getZExtValue ( ) ) , UndefValue :: get ( IntTy64 ) } ; return ConstantVector :: get ( Args ) ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) { Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; Constant * CILength = ConstantInt :: get ( IntTy8 , Length , false ) ; Constant * CIIndex = ConstantInt :: get ( IntTy8 , Index , false ) ; Value * Args [ ] = { Op0 , Op1 , CILength , CIIndex } ; Module * M = II . getModule (


<s> SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , true , SuffixLoc , getContext ( ) ) ) ; } bool condCodeFourthOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeSecondOperand = ( Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeThirdOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , false , false ) ) { return true ; } unsigned N = <NUM_LIT> ; while ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( parseOperand ( Operands , ( N == <NUM_LIT> && condCodeFourthOperand ) || ( N == <NUM_LIT> && condCodeThirdOperand ) || ( N == <NUM_LIT> && condCodeSecondOperand ) , condCodeSecondOperand || condCodeThirdOperand ) ) { return true ; } SMLoc RLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseOptionalToken ( AsmToken :: RBrac ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , RLoc , getContext ( ) ) ) ; SMLoc ELoc = Parser . getTok ( )


<s> <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM


<s> } if ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Chain , Src } ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Src ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = {


<s> ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node


<s> if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; width = ( width + div - <NUM_LIT> )


<s> MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine


<s> LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) ; MIB . addOperand ( New ) ; MIB . addOperand ( Addr ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState


<s> sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; if ( isFPCmp ) { BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; } else { BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; } BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent (


<s> if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; Register Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP ->


<s> mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_andc ( vec_sr ( ( vec_uint4 ) (


<s> unsigned FixupSFBPass :: getRegSizeInBytes ( MachineInstr * LoadInst ) { auto TRC = TII -> getRegClass ( TII -> get ( LoadInst -> getOpcode ( ) ) , <NUM_LIT> , TRI , * LoadInst -> getParent ( ) -> getParent ( ) ) ; return TRI -> getRegSizeInBits ( * TRC )


<s> Changed |= optimizePTrueIntrinsicCalls ( Functions ) ; return


<s> void <ISA_LIT>InstrInfo :: insertSelect ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DstReg , ArrayRef < MachineOperand > Pred , unsigned TrueReg , unsigned FalseReg ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasLoadStoreOnCond2 ( ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT> ; MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg (

TrueReg ) . addImm ( CCValid ) . addImm ( CCMask ) ;


<s> static SDValue getVFPCmp ( SDValue LHS , SDValue RHS , SelectionDAG & DAG , DebugLoc dl ) { SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> ,


<s> if ( Cond . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Cond -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Cond , DAG , <ISA_LIT>cc ) ; <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> static DecodeStatus DecodeMemMMSPImm5Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Offset = Insn & <NUM_LIT> ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT>