<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! <STR_LIT> ( * MI ) ) continue ; if ( ! ( MI -> mayRaiseFPException ( ) || MI -> mayLoadOrStore ( ) ) || isX87ControlInstruction ( * MI ) ) continue ; MachineBasicBlock :: iterator AfterMI = std :: next ( MI ) ; if ( AfterMI != MBB . end ( ) && <STR_LIT> ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ MI ; Changed =


<s> Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Memory


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start = I ; BasicBlock :: const_iterator End = II ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return false ; const auto * EVI = cast < ExtractValueInst > ( Itr ) ; if ( EVI -> getAggregateOperand ( ) != II ) return false ; } CC = TmpCC


<s> void <ISA_LIT>InstPrinter :: printNeonUImm0Operand ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> } case TYPE_DIV : { if ( ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return get_attr_size ( dep_insn ) == SIZE_32 ? <NUM_LIT> : <NUM_LIT> ; break ; } default : break ; } } break ; case TYPE_LOAD : if ( ( rs6000_tune == PROCESSOR_POWER6 ) && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= <NUM_LIT> ) ) { switch ( get_attr_type ( dep_insn ) ) { case TYPE_LOAD : case TYPE_CNTLZ : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_sign_extend ( dep_insn ) == SIGN_EXTEND_YES ? <NUM_LIT> : <NUM_LIT> ; break ; } case TYPE_SHIFT : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_var_shift ( dep_insn ) == VAR_SHIFT_YES ? <NUM_LIT> : <NUM_LIT> ; break ; } case TYPE_INTEGER : case TYPE_ADD : case TYPE_LOGICAL : case TYPE_EXTS : case TYPE_INSERT : { if ( set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : { if ( get_attr_update ( dep_insn ) == UPDATE_YES && set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_MUL : { if ( set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_DIV : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_size ( dep_insn ) == SIZE_32 ? <NUM_LIT> : <NUM_LIT> ; break ; } default : break ; } } break ; case TYPE_FPLOAD : if ( ( rs6000_tune == PROCESSOR_POWER6 ) && get_attr_update ( insn ) == UPDATE_NO && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= <NUM_LIT> ) && ( get_attr_type ( dep_insn ) == TYPE_MFFGPR ) ) return <NUM_LIT> ; default : break ; } } break ; case REG_DEP_OUTPUT : if ( ( rs6000_tune == PROCESSOR_POWER6 ) && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= <NUM_LIT> ) ) { attr_type = get_attr_type ( insn ) ; switch ( attr_type ) { case TYPE_FP : case TYPE_FPSIMPLE : if ( get_attr_type ( dep_insn ) == TYPE_FP || get_attr_type (


<s> static void restoreCRs ( bool is<ISA_LIT>64 , bool is31 , bool CR2Spilled , bool CR3Spilled , bool CR4Spilled , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned CSIIndex ) { MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL ; unsigned RestoreOp , MoveReg ; if ( is<ISA_LIT>64


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel


<s> <ISA_LIT>ELFTargetAsmInfo :: <ISA_LIT>ELFTargetAsmInfo ( const Triple & Triple ) { AsmTransCBE = x86_asm_table ; AssemblerDialect = AsmWriterFlavor ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets =


<s> DebugLoc DL = Op . getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( SmallVectorImpl < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++

I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ;


<s> unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG ,


<s> recordSled ( CurSled , MI , SledKind :: TAIL_CALL , <NUM_LIT> ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst TC ; TC . setOpcode ( OpCode ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( TC , getSubtargetInfo


<s> vmvn_p8 ( poly8x8_t __a ) { return ( poly8x8_t ) ~ ( ( int8x8_t )


<s> MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( Assembler . isBundlingEnabled ( ) && Sec -> isBundleLocked ( ) ) return false ; if ( ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] || STI .

getFeatureBits ( ) [ <STR_LIT> ] ) ) return false ;


<s> unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int register_mask ; unsigned int regs_size ; unsigned int reg ; unsigned HOST_WIDE_INT total_size ; if ( is_naked_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_naked_return ( ) ) ; return ; } rx_get_stack_layout ( & low , & high , & register_mask , & frame_size , & stack_size ) ; total_size = frame_size + stack_size ; regs_size = ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ; if ( is_sibcall || is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || register_mask ) { if ( total_size ) gen_safe_add ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( total_size ) , false ) ; if ( MUST_SAVE_ACC_REGISTER ) { unsigned int acc_low , acc_high ; if ( register_mask ) { acc_low = acc_high = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( register_mask & ( <NUM_LIT> << reg ) ) { if ( acc_low == <NUM_LIT> ) acc_low = reg ; else { acc_high = reg ; break ; } } emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_high ) ) ) ; emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_low ) ) ) ; } else { acc_low = low ; acc_high = low + <NUM_LIT> ; emit_insn ( gen_stack_popm ( GEN_INT ( <NUM_LIT> * UNITS_PER_WORD ) , gen_rx_popm_vector ( acc_low , acc_high ) ) ) ; } emit_insn ( gen_ashlsi3 ( gen_rtx_REG ( SImode , acc_low ) , gen_rtx_REG ( SImode , acc_low ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_mvtaclo ( gen_rtx_REG ( SImode , acc_low ) ) ) ; emit_insn ( gen_mvtachi ( gen_rtx_REG ( SImode , acc_high ) ) ) ; } if ( register_mask ) { for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( register_mask & ( <NUM_LIT> << reg ) ) emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , reg ) ) ) ; } else if ( low ) { if ( high == low ) emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , low ) ) ) ; else emit_insn ( gen_stack_popm ( GEN_INT ( regs_size ) , gen_rx_popm_vector ( low , high ) ) ) ; } if ( is_fast_interrupt_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_fast_interrupt_return ( ) ) ; } else if ( is_interrupt_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_exception_return ( ) ) ; } else if ( ! is_sibcall ) emit_jump_insn ( gen_simple_return ( ) ) ; return ; } if ( total_size )


<s> bool isMemImm0_1020s4Offset ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> && ( Val


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize

( ) > DefaultSafeSPDisplacement ) return true ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList (


<s> if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( llvm :: any_of ( ArgLocs ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N .


<s> if ( type == <NUM_LIT> && ( align & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst , Insn , Address


<s> if ( can_create_pseudo_p ( ) ) return force_reg ( mode , value ) ; else { x = aarch64_emit_move ( x , value ) ; return x


<s> NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> + slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; if ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; } else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm6 ( insn ) * <NUM_LIT>


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ; OS . write_zeros ( Count %


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( )


<s> x = vec_and ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , (

vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> CriticalPathRCs . clear ( ) ; if ( is<ISA_LIT>64 ( ) ) CriticalPathRCs . push_back ( & <STR_LIT> ) ; else CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( &


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = Parser . getTok ( ) . getString ( ) ; Sym = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( Identifier ) , Kind , Ctx ) ; Parser . Lex ( ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( AllowTLS ) Operands . push_back ( <ISA_LIT>Operand :: createImmTLS ( Expr , Sym , StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr


<s> unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( Ctx . getRegisterInfo ( ) && FrameReg != <STR_LIT> ) { RestoreReg ( Out , LocalFrameReg ) ; Out . EmitCFIRestoreState ( ) ; if ( FrameReg == <STR_LIT> ) Out . EmitCFIAdjustCfaOffset


<s> ++ FilledSlots ; Changed = true ; MachineBasicBlock :: iterator D ; if ( EnableDelaySlotFiller && findDelayInstr ( MBB , I , D ) ) { MBB . splice ( llvm :: next ( I ) , & MBB , D ) ; ++ UsefulSlots ; } else BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LastFiller = ++


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = select<ISA_LIT>CPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! TM . Options . UseSoftFloat )


<s> static DecodeStatus DecodeGR128BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> bool <ISA_LIT>FixupSetCCPass :: impUsesFlags ( MachineInstr * MI ) { for ( auto & Op : MI -> implicit_operands ( ) ) if ( Op . isReg ( ) && ( Op . getReg ( ) == <STR_LIT> )


<s> if ( VT == <STR_LIT> && C ) return Op ; if ( Subtarget . isISA3_1 ( ) ) { if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; } if ( ! C ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue Mtvsrz = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned InsertAtElement = C -> getZExtValue ( ) ; unsigned InsertAtByte = InsertAtElement * BytesInEachElement ; if ( Subtarget .


<s> switch ( config ( ) . options ( ) . getStripSymbolMode ( ) ) { case GeneralOptions :: StripSymbolMode :: StripAllSymbols : case GeneralOptions :: StripSymbolMode :: StripLocals : break ; default : { assert ( stub -> symInfo ( ) != NULL && stub -> symInfo ( ) -> isLocal ( ) ) ; LDSection & symtab = file_format -> getSymTab ( ) ; LDSection & strtab = file_format -> getStrTab ( ) ; symtab . setSize ( symtab . size ( ) + sizeof ( llvm :: ELF :: Elf32_Sym ) ) ; symtab . setInfo ( symtab . getInfo ( ) + <NUM_LIT> ) ; strtab . setSize ( strtab . size ( ) + stub -> symInfo ( ) -> nameSize ( ) + <NUM_LIT> ) ; } } isRelaxed = true ; } break ; } case llvm :: ELF :: R_<ISA_LIT>_V4BX : break ; default : break ; } } } } std :: vector < Fragment * > invalid_frags ; pFinished = true ; for ( BranchIslandFactory :: iterator island = getBRIslandFactory ( ) -> begin ( ) , island_end = getBRIslandFactory ( ) -> end ( ) ; island != island_end ; ++ island ) { if ( ( * island ) . size ( ) > stubGroupSize ( ) ) { error ( diag :: err_no_space_to_place_stubs ) << stubGroupSize ( ) ; return false ; } if ( ( * island ) . numOfStubs ( ) == <NUM_LIT> ) { continue ; } Fragment * exit = & * ( * island ) . end ( ) ; if ( exit == & * ( * island ) . begin ( ) -> getParent ( ) -> end ( ) ) { continue ; } if ( ( ( * island ) . offset ( ) + ( * island ) . size ( ) ) > exit -> getOffset ( ) ) { if ( invalid_frags . empty ( ) || ( invalid_frags . back ( ) -> getParent ( ) != ( * island ) . getParent ( ) ) ) { invalid_frags . push_back ( exit ) ; pFinished = false ; } continue ; } } for ( auto it = invalid_frags . begin ( ) , ie = invalid_frags . end ( ) ; it != ie ; ++ it ) { Fragment * invalid = * it ; while ( invalid != NULL ) { invalid -> setOffset ( invalid -> getPrevNode ( ) -> getOffset ( ) + invalid -> getPrevNode ( ) -> size ( ) ) ; invalid = invalid ->


<s> Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( )


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( llvm :: GlobalValue * GV )


<s> if ( GET_CODE ( op ) == CONST_INT && SMALL_INT ( op ) ) return <NUM_LIT> ; return register_operand ( op


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T ) : Darwin<ISA_LIT>AsmBackend ( T ) { HasReliableSymbolDifference = true


<s> insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , mips_unspec_address ( loc , SYMBOL_DTPREL ) ) ; break ; case TLS_MODEL_INITIAL_EXEC


<s> static_assert ( std :: is_same < T , <STR_LIT> > :: value || std :: is_same < T , <STR_LIT> > :: value , <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return false ; if ( Args . empty ( ) )


<s> bool <ISA_LIT>MachObjectWriter :: get<ISA_LIT>FixupKindMachOInfo ( const MCFixup & Fixup , unsigned & RelocType , const MCSymbolRefExpr * Sym , unsigned & Log2Size , const MCAssembler & Asm ) { RelocType = unsigned ( MachO :: ARM64_RELOC_UNSIGNED ) ; Log2Size = ~ <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case FK_Data_1 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_2 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_4 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case FK_Data_8 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is512BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i ) ) return false ; return true


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , DL , TII -> get (


<s> const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; unsigned RegNo = RegOp . getReg ( ) ; const MCSymbolRefExpr * Symbol = cast < MCSymbolRefExpr > ( SymOp . getExpr ( ) ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , getContext ( ) ) ; if ( isGP64bit ( ) ) { const MCSymbolRefExpr * HighestExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST , getContext ( ) ) ; const MCSymbolRefExpr * HigherExpr = MCSymbolRefExpr :: Create ( Symbol -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER , getContext ( ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateExpr ( HighestExpr ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < false > ( MCOperand :: CreateExpr ( HigherExpr ) , RegNo , SMLoc ( ) , Instructions ) ; createShiftOr < true > ( MCOperand :: CreateExpr ( HiExpr ) , RegNo , SMLoc ( ) , Instructions ) ; createShiftOr < true > ( MCOperand :: CreateExpr ( LoExpr ) , RegNo , SMLoc ( ) , Instructions ) ; } else { tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < false > ( MCOperand :: CreateExpr ( LoExpr ) , RegNo ,


<s> CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; machine_mode mode = arg . mode == VOIDmode ? DImode : arg . mode ; if ( arg . end_marker_p ( ) ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( arg ) && ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> || argsp -> lib || TARGET_LIBFUNC

) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ;


<s> HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) { SDValue Cond = Op . getOperand ( SplatIdx ) ; assert ( Cond . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue Select = DAG . getSelect ( dl , <STR_LIT> , Cond , DAG . getAllOnesConstant ( dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Select = DAG . getBitcast ( <STR_LIT> , Select ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Select , Select ) ; } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Select = DAG . getSelect ( dl , ImmVT , Cond , DAG . getAllOnesConstant ( dl , ImmVT ) , DAG . getConstant ( <NUM_LIT> , dl , ImmVT ) ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; Select = DAG . getBitcast ( VecVT , Select ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Select , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast ( <STR_LIT> , ImmL ) ; ImmH = DAG . getBitcast ( <STR_LIT> , ImmH ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ImmL , ImmH ) ; } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; DstVec = DAG . getBitcast ( VecVT , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , DstVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } else DstVec = DAG . getUNDEF ( VT ) ; for ( unsigned i = <NUM_LIT> , e = NonConstIdx . size ( ) ; i != e ; ++ i ) { unsigned InsertIdx = NonConstIdx [ i ]


<s> if ( is<ISA_LIT>LowRegister ( Reg ) ) return <STR_LIT> ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; } return TargetRegisterInfo :: getPhysicalRegisterRegClass ( Reg , VT


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> )


<s> AddValueSymbols_ ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : Asm -> getOrCreateSymbolData ( cast < MCSymbolRefExpr > ( Value ) -> getSymbol ( ) ) ; break ; case MCExpr ::


<s> bool <ISA_LIT>TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level


<s> HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF |


<s> return <NUM_LIT> ; default : return <NUM_LIT> ; } return


<s> return nullptr ; } ; MachineInstr * Start = nullptr ; MachineInstr * Dec = nullptr ; MachineInstr * End = nullptr ; bool Revert = false ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) { Start = SearchForStart ( Preheader ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; MachineBasicBlock * Pred = nullptr ; for ( auto * MBB : ML -> getHeader ( ) -> predecessors ( ) ) { if ( ! ML -> contains ( MBB ) ) { if ( Pred ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Start = nullptr ; break ; } Pred = MBB ; Start = SearchForStart ( MBB ) ; } } } for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( IsLoopStart ( MI ) ) Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } LLVM_DEBUG ( if ( Start ) dbgs ( ) << <STR_LIT> << * Start ; if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; ) ; if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } else if ( ! ( Start && Dec && End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader


<s> if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode

|| GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ;


<s> Value * <ISA_LIT>IREmitter :: visitVCGE ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( ! isShiftedImm ( ) && ! isImm ( ) ) return false ; if ( auto ShiftedVal = getShiftedVal < <NUM_LIT> > ( ) ) return ShiftedVal -> first < <NUM_LIT> && - ShiftedVal -> first <= <NUM_LIT> ; return false


<s> bool <ISA_LIT>MCInstrAnalysis :: evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { if ( Inst . getNumOperands ( ) == <NUM_LIT> || Info -> get ( Inst . getOpcode

( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ;


<s> if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Val ) ) { unsigned Opc = <NUM_LIT> ; bool Signed = true ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc

) ) , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) :


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseProcIFlagsOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodedVal > <NUM_LIT> ) return MCDisassembler :: Fail ; break ; } Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val


<s> return ( int16x8_t ) __builtin_neon_vpaddlsv16qi (


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( canUseRedZone ( MF ) ) return


<s> switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token


<s> bool <ISA_LIT>ConstantIslands :: fixupConditionalBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true


<s> static tree make_attribute ( const char * name , const char * arg_name , tree chain ) { tree attr_name ; tree attr_arg_name ; tree attr_args ; tree attr ; attr_name = get_identifier ( name ) ; attr_arg_name = build_string ( strlen ( arg_name ) , arg_name ) ; attr_args = tree_cons ( NULL_TREE ,


<s> if ( auto PreHeader = L -> getLoopPreheader ( ) ) if ( ! VisitedBlocks . count ( PreHeader ) ) Worklist . push_back ( PreHeader ) ; while ( ! Worklist . empty ( ) ) { auto BB = Worklist . pop_back_val ( ) ; LoopOptimized |= Optimize_PreWhileConversion ( BB ) ; LoopOptimized |= Optimize_PostWhileConversion ( BB ) ; LoopOptimized |= Transform_StructAddressing ( BB ) ; VisitedBlocks . insert ( BB ) ; } ++ NumVisited ; if ( LoopOptimized ) ++


<s> static inline void desc_spill_sprel_p ( unsigned char qp , unw_word t , unsigned char abreg , unw_word spoff , struct unw_state_record * sr ) { struct unw_reg_info * r ; if ( ! desc_is_active ( qp , t , sr ) ) return ; r = sr -> curr . reg + decode_abreg


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Flag ; EVT SPTy = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain


<s> return ( Subtarget . hasDQI ( ) && ( SizeInBits == <NUM_LIT> || SizeInBits == <NUM_LIT> ) ) || ( Subtarget . hasBWI ( ) && ( SizeInBits == <NUM_LIT> || SizeInBits == <NUM_LIT> ) ) ; } ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) . getSimpleVT ( ) ; if ( Op0VT . isVector ( ) && Op0VT . getVectorElementType ( ) == <STR_LIT> && hasKTEST ( Op0VT ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op0VT , Op0 , Op0 ) ; } return SDValue (


<s> } count = <NUM_LIT> ; } else if ( TARGET_SSSE3 ) count = <NUM_LIT> ; return ix86_vec_cost ( mode , cost -> sse_op * count , true ) ; } else return ix86_vec_cost ( mode , cost -> sse_op , true ) ; } if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) { if ( constant_op1 ) { if ( op1_val > <NUM_LIT> ) return cost -> shift_const + COSTS_N_INSNS ( <NUM_LIT> ) ; else return cost -> shift_const * <NUM_LIT> ; } else { if ( and_in_op1 ) return cost -> shift_var * <NUM_LIT> ; else return cost -> shift_var * <NUM_LIT> + COSTS_N_INSNS ( <NUM_LIT> ) ; } } else { if ( constant_op1 ) return cost -> shift_const ; else if ( shift_and_truncate ) { if ( skip_op0 ) * skip_op0 = * skip_op1 = true ; return cost ->


<s> fputs ( <STR_LIT> , asm_out_file ) ; return ; } gcc_assert ( CALL_P ( call_insn ) ) ; for ( link = CALL_INSN_FUNCTION_USAGE ( call_insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( use , <NUM_LIT> ) ) ; if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) { arg_regs [ <NUM_LIT> - regno ] = <STR_LIT> ; if ( arg_mode == DImode ) arg_regs [ <NUM_LIT> - regno ] = <STR_LIT> ; } else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) { if ( arg_mode == SFmode ) arg_regs [ ( regno - <NUM_LIT> ) / <NUM_LIT> ] = <STR_LIT> ; else { arg_regs [ ( regno - <NUM_LIT> ) / <NUM_LIT> ] = <STR_LIT> ; arg_regs [ ( regno - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitFMSUB ( const SDNode * N


<s> return SDValue ( CurDAG -> getMachineNode ( InVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , InVT , InputOp , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } else if ( isLogicOp ( OperandOpcode ) ) return computeLogicOpInGPR ( Operand ) ; return SDValue ( ) ; } ; LHS = getLogicOperand ( LogicOp . getOperand ( <NUM_LIT> ) ) ; RHS = getLogicOperand ( LogicOp . getOperand ( <NUM_LIT> ) ) ; if ( ! LHS || ( ! RHS && ! IsBitwiseNegation ) ) return SDValue ( ) ; NumLogicOpsOnComparison ++ ; if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = addExtOrTrunc ( LHS , ExtOrTruncConversion :: Ext ) ; if ( ! IsBitwiseNegation && RHS . getValueType ( ) == <STR_LIT> ) RHS =

addExtOrTrunc ( RHS , ExtOrTruncConversion :: Ext ) ;


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , DebugLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT>


<s> return ( uint16x4_t ) __builtin_neon_vqmovunv4si


<s> output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftLeftImm64 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ,


<s> return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange0_32 ; return Match_Success ; } case


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb ) : MCELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter


<s> Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize -


<s> } if ( UndefLower && isSequentialOrUndefInRange ( Mask , HalfNumElts , HalfNumElts , <NUM_LIT> ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; } int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( HalfNumElts ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) ) return SDValue ( ) ; assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; int NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; int NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; if ( UndefLower && NumUpperHalves != <NUM_LIT> ) return SDValue ( ) ; if ( ! UndefLower && NumUpperHalves == <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX2 ( ) && ( UndefLower || NumUpperHalves != <NUM_LIT> ) ) { if ( VT == <STR_LIT> || VT ==


<s> return ( __m512d ) __builtin_ia32_loadapd512_mask ( ( const __v8df * ) __P ,


<s> VT = <STR_LIT> ; } bool RV ; unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV == true && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV == true && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; Dest . Offset +=


<s> v . finalize ( ) ; if ( nelts < <NUM_LIT> || ! aarch64_sve_expand_vector_init ( target , v , nelts , nelts )


<s> void printDstIdx8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printDstIdx ( MI , OpNo , O


<s> if ( Parent && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> ) { unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( matchAddress ( N , AM ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM .

IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> if ( ! TARGET_SH5 && PASS_IN_REG_P ( * cum , mode , type ) && ! ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && ( ROUND_REG ( * cum , mode ) + ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - ROUND_REG ( * cum , mode ) ; else if ( ! TARGET_SHCOMPACT && SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) words = NPARM_REGS ( SImode ) - cum -> arg_count [ SH_ARG_INT ] ; return words


<s> bool <ISA_LIT>RegisterInfo :: isFixedRegister ( const MachineFunction & MF , MCRegister PhysReg ) const { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST . getRegisterInfo ( ) ; if ( TRI . isSuperOrSubRegisterEq ( <STR_LIT> , PhysReg ) ) return true ; const <ISA_LIT>FrameLowering & TFI = * getFrameLowering ( MF ) ; if ( TFI . hasFP ( MF ) && TRI . isSuperOrSubRegisterEq


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; Mask . push_back ( isa < ConstantSDNode > ( CondElt ) ? i + (

isZero ( CondElt ) ? Size : <NUM_LIT> ) : - <NUM_LIT> ) ;


<s> if ( ! BasePtr ) return nullptr ; if ( ExtendInput ) Input = Builder . CreateZExt ( Input , InputTy ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) } , { BasePtr , Offsets , Input , Builder

. getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) } ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> i != values . end ( ) ; ++ i ) if ( i -> value == NULL_RTX || ! rtx_equal_p ( last_value , i -> value ) ) return false ; return


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT>


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op


<s> } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> )


<s> MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ResWidth ) ; SDLoc DL ( Extract ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , ResVT ) ; SDValue Ones = DAG . getAllOnesConstant ( DL


<s> const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; assert ( RC && <STR_LIT> ) ; bool Is64Bit = <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ; assert ( ( Is64Bit || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; unsigned OpCode = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SelectPred = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned SubIdx ; bool SwapOps ; switch ( SelectPred ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = true ; break ; } unsigned FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg = SwapOps ? TrueReg : FalseReg ; if ( MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) || MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) ) { const TargetRegisterClass * FirstRC = MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT>


<s> static DecodeStatus DecodeHPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeSPRRegisterClass ( Inst , RegNo , Address ,


<s> const char * suffix = <STR_LIT> ; switch ( ( sz << <NUM_LIT> ) | ( regi % <NUM_LIT> ) ) { case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; default : continue ; } sprintf ( & canon_reg_names [ speci ] [ regi ] [ <NUM_LIT> ] , <STR_LIT> , regi / <NUM_LIT> , suffix ) ; } } switch ( GET_MODE_SIZE ( GET_MODE ( op ) ) ) { case <NUM_LIT> : speci = <NUM_LIT>


<s> unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Constant * C = ConstantInt :: get ( * DAG . getContext ( ) , APInt :: getAllOnesValue ( ExtVT . getScalarType ( ) . getSizeInBits ( ) ) ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) ->


<s> unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned VReg = BasePtr ; if ( Offset ) { VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; if ( Offset > <NUM_LIT> ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , VReg ) . addReg ( BasePtr )


<s> return VT . isVector ( ) && VT . getScalarSizeInBits ( ) %


<s> Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , & Args , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ; return DAG . getNode ( <STR_LIT> , dl , Tys , LoadSin . getValue ( <NUM_LIT> ) , LoadCos . getValue


<s> int i = <NUM_LIT> ; classes [ i ++ ] = GENERAL_REGS ; classes [ i ++ ] = FP_REGS ; classes [ i ++


<s> Value * <ISA_LIT>IREmitter :: visitFST ( const SDNode


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) temp .


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> return wi :: umin ( wi :: to_wide ( TYPE_SIZE ( type ) )


<s> static int readVVVV ( struct InternalInstruction * insn ) { dbgprintf ( insn , <STR_LIT> ) ; int vvvv ; if ( insn -> vectorExtensionType == TYPE_EVEX ) vvvv = vvvvFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv =

vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( const MCSymbolRefExpr * Expr = dyn_cast < MCSymbolRefExpr > ( MO . getExpr ( ) ) ) { MCFixupKind


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SVT = VT . getScalarType ( ) ; EVT InVT = N0 . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT InVT = N . getValueType ( ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , Size / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT


<s> const TargetRegisterClass * <ISA_LIT>SERegisterInfo :: intRegClass ( unsigned


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetFp ( <STR_LIT> Value ) { StringRef ModuleValue ; OS <<


<s> __arm_ldc2 ( const unsigned int __coproc , const unsigned int __CRd , const void * __p ) { return __builtin_arm_ldc2 ( __coproc , __CRd ,


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI -> hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI -> getLocalFrameSize ( ) <


<s> static bool IsCCallConvention ( CallingConv :: ID


<s> case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx


<s> else NewAVL = RawAVL ; NewAVL = getNode ( <STR_LIT> , <STR_LIT> , { NewAVL , OneV } ) ; NewAVL = annotateLegalAVL ( NewAVL ) ; SDValue NewMask ; if ( ! RawMask ) NewMask = getConstantMask ( Packing :: Normal , true ) ; else NewMask = getUnpack ( <STR_LIT> , RawMask , Part , NewAVL ) ; return <ISA_LIT>TargetMasks ( NewMask


<s> int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> + <NUM_LIT> ; if ( RegNo % <NUM_LIT> ) ++ UseCycle ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { UseCycle = RegNo ; bool isSStore = false ; switch ( UseMCID .


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , STI ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS


<s> <ISA_LIT>AsmLexer ( const Target & T , const MCRegisterInfo & MRI , const MCAsmInfo & MAI


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; return MIN ( align , <NUM_LIT>


<s> bool SelectAddrModeIndexed16 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexed ( N , <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitJumpTableTBInst ( const MachineInstr * MI , unsigned OffsetWidth ) { assert ( ( OffsetWidth == <NUM_LIT> || OffsetWidth == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; if ( Subtarget -> isThumb1Only ( ) ) EmitAlignment ( Align ( <NUM_LIT> ) ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel ( JTI ) ; OutStreamer -> EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; OutStreamer -> EmitDataRegion ( OffsetWidth == <NUM_LIT> ? MCDR_DataRegionJT8 : MCDR_DataRegionJT16 ) ; for ( auto MBB : JTBBs ) { const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; MCSymbol * TBInstPC = GetCPISymbol ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; const MCExpr * Expr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( TBInstPC , OutContext ) , MCConstantExpr :: create (

<NUM_LIT> , OutContext ) , OutContext ) ;


<s> static void MoveBelowTokenFactor ( SelectionDAG * CurDAG , SDValue Load , SDValue Store , SDValue TF ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = TF . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) if ( Load . getNode ( ) ==

TF . getOperand ( i ) . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , TLI -> getPointerTy ( ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN ->


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; if ( Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Real ) ) Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; else if ( IntVal != <NUM_LIT> || isNegative ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; return false ; } const MCExpr * ImmVal ; if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal : { SMLoc Loc = getLoc ( ) ; if ( Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; if ( Operands . size ( ) < <NUM_LIT> || ! static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isScalarReg ( ) ) return Error ( Loc , <STR_LIT> ) ; bool IsXReg = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ; MCContext & Ctx = getContext ( ) ; E = SMLoc :: getFromPointer ( Loc . getPointer ( ) - <NUM_LIT> ) ; if ( isa < MCConstantExpr > ( SubExprVal ) ) { uint64_t Imm = ( cast < MCConstantExpr > ( SubExprVal ) ) -> getValue ( ) ; uint32_t ShiftAmt = <NUM_LIT> , MaxShiftAmt = IsXReg ? <NUM_LIT> : <NUM_LIT> ; while ( Imm > <NUM_LIT> && countTrailingZeros ( Imm ) >= <NUM_LIT> ) { ShiftAmt += <NUM_LIT> ; Imm >>= <NUM_LIT> ; } if ( ShiftAmt <= MaxShiftAmt && Imm


<s> return DAG . getConstant ( Imm , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && SrcVT . isFloatingPoint ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == EVT ( SrcVT ) . changeVectorElementTypeToInteger ( ) ) Src = Src . getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; KnownBits Known ; APInt DemandedMask ( APInt :: getSignMask ( SrcVT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Src , DemandedMask , Known , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; return SDValue ( N , <NUM_LIT> ) ; } APInt SplatVal ; if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == Src . getValueType ( ) && Src . getValueType ( ) . getScalarSizeInBits ( ) >= <NUM_LIT> && cast < CondCodeSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ->

get ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; RetAddrOffset = <NUM_LIT> ; } RetOps [ <NUM_LIT> ] = Chain ; RetOps [ <NUM_LIT> ] = DAG . getConstant


<s> if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; computeBlockSize ( OrigBB


<s> short Val = MCE -> getValue ( ) ; Res = MCConstantExpr :: Create ( Val , getContext ( ) ) ; } else if ( RelocStr == <STR_LIT> ) { int Val = MCE -> getValue ( ) ; int LoSign = Val & <NUM_LIT> ; Val = ( Val & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoSign ) Val ++ ; Res = MCConstantExpr :: Create ( Val , getContext ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } return Res ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: Create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res ; } if ( const MCUnaryExpr * UN = dyn_cast < MCUnaryExpr > ( Expr ) ) { const MCExpr * UnExp = evaluateRelocExpr ( UN -> getSubExpr ( ) , RelocStr ) ; Res = MCUnaryExpr :: Create ( UN -> getOpcode ( )


<s> getAddrMode2OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx + <NUM_LIT> , Fixups ) ; Binary |= Rn << <NUM_LIT> ; return


<s> assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRI5S1 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base , Offset ,


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR5 ( ( v8qi ) mm , (


<s> if ( SrcVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) ) { if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is256BitVector ( ) ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is512BitVector ( ) ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } return false


<s> case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : break ; } const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Val < <NUM_LIT> || Val > <NUM_LIT>


<s> if ( ! Subtarget . isTargetWindows ( ) ) return false ; const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; return ( StackSizeInBytes >= StackProbeSize ) && ! F . hasFnAttribute ( <STR_LIT>


<s> char * attr_str , * assembler_name ; if ( DECL_DECLARED_INLINE_P ( decl ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> <STR_LIT> ) ; if ( DECL_VIRTUAL_P ( decl ) || DECL_VINDEX ( decl ) ) sorry ( <STR_LIT> ) ; version_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( version_attr != NULL_TREE ) ; orig_name = IDENTIFIER_POINTER ( id ) ; version_string = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( version_attr ) ) ) ; if ( strcmp ( version_string , <STR_LIT> ) == <NUM_LIT> ) return id ; attr_str = sorted_attr_string ( TREE_VALUE ( version_attr ) ) ; assembler_name = XNEWVEC ( char , strlen ( orig_name ) + strlen ( attr_str ) + <NUM_LIT> ) ; sprintf ( assembler_name , <STR_LIT> , orig_name


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr (


<s> SDValue GprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , VAListPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = GprIndex . getValue ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue GprAnd = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CC64 = DAG . getSetCC ( dl , <STR_LIT> , GprAnd , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue GprIndexPlusOne = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; GprIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CC64 , GprIndexPlusOne , GprIndex ) ; } SDValue FprPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue FprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( )


<s> if ( any_of ( Mask , [ ] ( int M ) { return M == SM_SentinelZero ; } ) ) return - <NUM_LIT> ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( ! is128BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) return - <NUM_LIT> ; int Rotation = matchVectorShuffleAsRotate ( V1


<s> static bool canCombineWithMUL ( MachineBasicBlock & MBB , MachineOperand & MO ,


<s> if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; translateInstruction ( instr , internalInstr ) ; return true


<s> ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , ST . use<ISA_LIT>PreRASchedStrategy ( ) ? llvm :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) : llvm :: make_unique < GenericScheduler > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII


<s> MachineOperand & Dest = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( ! IsADDIInstRequired && ! IsORIInstRequired ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumRemoved ++ ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL . erase ( MI ) ; continue ; } if ( useSameRegister ( TrueValue , FalseValue ) && ( BIL . size ( ) == <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * MI ) , dl , TII -> get ( isISEL8 ( * * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL .


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor ( BB


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base ,


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t MulAmt = C -> getZExtValue ( ) ; unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt


<s> case MachO :: <ISA_LIT>_RELOC_BR24 : if ( ! S . isTemporary ( ) ) return true ; Value -= <NUM_LIT> ; Range = <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } Value += Writer -> getSectionAddress ( & S . getSection ( ) ) ; Value -= Writer -> getSectionAddress ( Fragment . getParent ( ) ) ; if ( Value > Range || Value < - ( Range + <NUM_LIT> ) )


<s> Subtarget . SetJITMode ( ) ; PM . add ( create<ISA_LIT>JITCodeEmitterPass ( *


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( UseFSRMForMemcpy && Subtarget . hasFSRM ( ) ) return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , Size , <STR_LIT> ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( )


<s> } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && InputVector . getOpcode ( ) == <STR_LIT> && dyn_cast < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; uint64_t InputValue = cast < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; uint64_t Res = ( InputValue >> ExtractedElt ) & <NUM_LIT> ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; } if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl ,


<s> return _semctl ( semid , semnum , cmd , arg << SHIFT_BITS


<s> return lowerV2F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case


<s> Imm = CurDAG -> getTargetConstant ( Val , DL , <STR_LIT> ) ; return true ; } if ( Val <= <NUM_LIT> && Val % <NUM_LIT> == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( Val >> <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; default : break ; } return false


<s> bool isMemPlaceholder ( const MCInstrDesc & Desc )


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT>


<s> if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) return <NUM_LIT> ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return <NUM_LIT> ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && ( XEXP ( x , <NUM_LIT> ) == virtual_stack_vars_rtx || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return <NUM_LIT> ; if ( ! FLOAT128_2REG_P ( mode ) && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , <NUM_LIT> ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_lo_sum_address_p ( mode ,


<s> vmovl_high_u16 ( uint16x8_t a ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) :


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE


<s> if ( mode == VOIDmode ) return choose_hard_reg_mode


<s> bool <ISA_LIT>AsmParser :: ParseOperand ( OwningPtr < <ISA_LIT>Operand > & Op ) { SMLoc S , E ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Identifier : if ( ! MaybeParseRegister ( Op , true ) ) return false ; const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand :: CreateImm ( Op , IdVal , S , E ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op )


<s> Inst . addOperand ( MCOperand :: CreateImm ( unsigned (


<s> } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) return ; if ( n_var == <NUM_LIT> ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , <NUM_LIT> , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target ,


<s> } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; address_regnum = REGNO ( XEXP ( address , <NUM_LIT> ) ) ; if ( address_regnum < R0_REGNUM + NUM_ARG_REGS ) bitmap_clear_bit ( to_clear_bitmap , address_regnum ) ; set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( ) ; emit_insn ( gen_blockage ( ) ) ; fntype = TREE_TYPE ( MEM_EXPR ( address ) ) ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , NULL_TREE ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; uint64_t to_clear_args_mask ; machine_mode arg_mode = TYPE_MODE ( arg_type ) ; if ( VOID_TYPE_P ( arg_type ) ) continue ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg_mode , arg_type , true ) ; arg_rtx = arm_function_arg ( args_so_far , arg_mode , arg_type , true ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } first_param = false ; } clearing_reg = XEXP ( address , <NUM_LIT> ) ; shift = gen_rtx_LSHIFTRT ( SImode , clearing_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( clearing_reg , shift ) ) ; shift = gen_rtx_ASHIFT ( SImode , clearing_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( clearing_reg , shift ) ) ; ip_reg = gen_rtx_REG ( SImode , IP_REGNUM ) ; cmse_clear_registers ( to_clear_bitmap , padding_bits_to_clear ,


<s> unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CC ) ; updateValueMap ( I , ResultReg ) ; return


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue (


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( CC ) { default : break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } SDValue Neg = NegateFCC ( LHS , RHS , CC ) ? DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getConstant ( CC , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( )


<s> } unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op


<s> return ( __mmask8 ) __builtin_ia32_pcmpeqw128_mask ( ( __v8hi ) __A ,


<s> printPCRelImm ( MI , Address , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI

, OS ) ) printInstruction ( MI , Address , OS ) ;


<s> static tree aarch64_add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) ,


<s> regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 )


<s> static void mips_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( TARGET_MIPS16 ) sorry ( <STR_LIT> ) ; if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <=


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ,


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { for ( MCRegAliasIterator AI ( Reg , TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if (


<s> void <ISA_LIT>AsmParser :: printWarningWithFixIt ( const Twine & Msg , const Twine & FixMsg , SMRange Range , bool ShowColors ) { getSourceManager ( ) . PrintMessage ( Range . Start , SourceMgr :: DK_Warning , Msg , Range

, SMFixIt ( Range , FixMsg ) , ShowColors ) ;


<s> bool <ISA_LIT>FastISel :: TryToFoldLoad ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( LI -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = TD . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI ->


<s> Function * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ; return CallInst :: Create ( Intr -> getFunctionType ( ) ,


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op00 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op00 . getOpcode ( ) == <STR_LIT> ) Tmp1 = LowerVectorIntExtend ( Op00 , Subtarget , DAG ) ; if ( Tmp1 . getNode ( ) ) { SDValue Tmp1Op0 = Tmp1 . getOperand ( <NUM_LIT> ) ; assert ( Tmp1Op0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Tmp1Op0 . getOperand ( <NUM_LIT> ) ) ; } Tmp1 = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , Op0 , BitsDiff , DAG ) ; return getTargetVShiftByConstNode ( <STR_LIT> , dl , VT ,