<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT CmpVT = LHS . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp2 . getNode (


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits ( )


<s> bool useOddSPReg ( ) const { return ! ( STI . getFeatureBits ( ) [ <STR_LIT> ]


<s> if ( insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [ prefix ] == location ) return true ; else return false


_mm_setzero_ph ( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType ( ) ; SDValue Node = DAG . getNode ( <STR_LIT> , DL , WideTy , WideVec , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return NarrowVector ( Node , DAG


<s> SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( ! Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> ) ; SDValue GprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , VAListPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = GprIndex . getValue ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue GprAnd = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CC64 = DAG . getSetCC ( dl , <STR_LIT> , GprAnd , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue GprIndexPlusOne = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; GprIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CC64 , GprIndexPlusOne , GprIndex ) ; } SDValue FprPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue FprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; InChain = OverflowArea .


<s> int64_t Bytes , NumPredicateVectors , NumDataVectors ; Offset . getForFrameOffset ( Bytes , NumPredicateVectors , NumDataVectors ) ; if ( Bytes || ( ! Offset && SrcReg != DestReg ) ) { assert ( ( DestReg != <STR_LIT> || Bytes % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; if ( Bytes < <NUM_LIT> ) { Bytes = - Bytes ; Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; } emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , Bytes , Opc , TII , Flag , NeedsWinCFI , HasWinCFI ) ; SrcReg = DestReg ; } assert ( ! ( SetNZCV && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr ) ; SrcReg = DestReg ; } if ( NumPredicateVectors ) { assert ( DestReg != <STR_LIT> &&


<s> switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case


<s> int UncondBr = <STR_LIT> ; auto * NewMI = BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . getInstr ( ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( * NewMI ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } const Align Align = MF -> getAlignment ( ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << Log2 ( Align ) << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI


<s> std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) || TT . isOSWindows ( ) || TT . isOSNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( )


<s> static bool isZeroImm ( const MachineOperand & op


<s> void setExceptionsType ( ExceptionHandling ::


<s> const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( SExpr && SExpr -> getSubExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef && <STR_LIT> ) ; const MCSymbolRefExpr * SymExpr = cast < MCSymbolRefExpr > ( SExpr -> getSubExpr ( ) ) ; assert ( SymExpr -> getSymbol ( ) . getName ( ) == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> static DecodeStatus readInstruction16 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn , bool IsBigEndian ) { if ( Bytes . size ( )


<s> Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) )


<s> StoreSDNode * StNode = cast < StoreSDNode > ( Op . getNode ( ) ) ; assert ( StNode && StNode -> getOffset ( ) . isUndef ( ) && <STR_LIT> ) ; EVT MemVT = StNode -> getMemoryVT (


<s> unsigned Offset = ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) + ( Uses64BitFramePtr ? <NUM_LIT> : <NUM_LIT> ) ; BuildCFI ( MBB , MBBI , DebugLoc { } , MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - Offset ) ) ; emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc {


<s> ptr -> x_ix86_dump_tunes = opts -> x_ix86_dump_tunes ; ptr -> x_ix86_force_align_arg_pointer = opts -> x_ix86_force_align_arg_pointer ; ptr -> x_ix86_force_drap = opts -> x_ix86_force_drap ; ptr -> x_ix86_incoming_stack_boundary_arg = opts -> x_ix86_incoming_stack_boundary_arg ; ptr -> x_ix86_pmode = opts -> x_ix86_pmode ; ptr -> x_ix86_preferred_stack_boundary_arg = opts -> x_ix86_preferred_stack_boundary_arg ; ptr -> x_ix86_recip_name = opts -> x_ix86_recip_name ; ptr -> x_ix86_regparm = opts -> x_ix86_regparm ; ptr -> x_ix86_section_threshold = opts -> x_ix86_section_threshold ; ptr -> x_ix86_sse2avx = opts -> x_ix86_sse2avx ; ptr -> x_ix86_stack_protector_guard = opts -> x_ix86_stack_protector_guard ; ptr -> x_ix86_stringop_alg = opts -> x_ix86_stringop_alg ; ptr -> x_ix86_tls_dialect = opts -> x_ix86_tls_dialect ; ptr -> x_ix86_tune_ctrl_string = opts -> x_ix86_tune_ctrl_string ; ptr -> x_ix86_tune_memcpy_strategy = opts -> x_ix86_tune_memcpy_strategy ; ptr -> x_ix86_tune_memset_strategy = opts -> x_ix86_tune_memset_strategy ; ptr -> x_ix86_tune_no_default = opts -> x_ix86_tune_no_default ; ptr -> x_ix86_veclibabi_type = opts -> x_ix86_veclibabi_type ; gcc_assert ( ptr -> arch == ix86_arch ) ; gcc_assert ( ptr -> schedule ==


<s> MCInst TmpInst ; uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS )


<s> static bool isZeroImm ( const MachineOperand


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) DF . getContents ( ) [ Fixup . getOffset

( ) + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass (


<s> if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( In . getScalarValueSizeInBits ( ) > VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; APInt C


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( ! VT . is64BitVector ( ) && ! VT . is128BitVector ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { for ( int j = <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { SDValue O0 = N0 -> getOperand ( i ) ; SDValue O1 = N1 -> getOperand ( j ) ; SDValue Sub , Add , SubSibling , AddSibling ; if ( O0 . getOpcode ( ) == <STR_LIT> && O1 . getOpcode ( ) == <STR_LIT> ) { Sub = O0 ; Add = O1 ; SubSibling = N0 -> getOperand ( <NUM_LIT> - i ) ; AddSibling = N1 -> getOperand ( <NUM_LIT> - j ) ; } else if ( O0 . getOpcode ( ) == <STR_LIT> && O1 . getOpcode ( ) == <STR_LIT> ) { Add = O0 ; Sub = O1 ; AddSibling = N0 -> getOperand ( <NUM_LIT> - i ) ; SubSibling = N1 -> getOperand ( <NUM_LIT> - j ) ; } else continue ; if ( ! <STR_LIT> ( Sub . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) continue ; if ( ! <STR_LIT> ( Add . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) continue ; if ( Sub . getOperand ( <NUM_LIT> ) != Add . getOperand ( <NUM_LIT> ) ) continue ; return DAG . getNode ( <STR_LIT> , DL , VT , Sub , SubSibling , AddSibling ) ; } } unsigned Bits = VT . getScalarSizeInBits ( ) ; uint64_t BitMask = Bits == <NUM_LIT> ? - <NUM_LIT> : ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) for ( int j = <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( i ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( j ) ) ; if ( ! BVN0 || ! BVN1 ) continue ; bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT


<s> void i386_pe_record_stub ( const char * name ) { struct stub_list * p ; if ( ! name || * name == <NUM_LIT> ) return ; p = stub_head ; while ( p != NULL


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ShiftedImmediate ) ; Op -> RegShiftedImm . ShiftTy = ShTy ; Op -> RegShiftedImm . SrcReg = SrcReg ; Op -> RegShiftedImm . ShiftImm =


<s> for ( unsigned int i = <NUM_LIT> ; i < builder . encoded_nelts ( ) ; ++ i ) if ( ( i & ( elt_size - <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( builder . elt ( i ) ) == <NUM_LIT> ) inv_builder . quick_push ( const1_rtx ) ; else inv_builder . quick_push ( const0_rtx ) ; inv_builder . finalize ( ) ; rtx inv = aarch64_expand_sve_const_pred_1 ( NULL_RTX , inv_builder , false ) ; if ( ! inv ) return NULL_RTX ; rtx mask = aarch64_ptrue_all ( elt_size ) ; mask = force_reg ( VNx16BImode , mask ) ; inv = gen_lowpart ( VNx16BImode , inv ) ; target = aarch64_target_reg ( target , VNx16BImode


<s> break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset += MFI . getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI . getLocalFrameMaxAlign

( ) > StackAlign ) && canRealignStack ( MF ) ) ) {


<s> return __builtin_mve_vqrshlq_n_sv4si ( __a ,


<s> StringRef CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) : ( StringRef ) CPU ; StringRef FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; Attribute PreferVecWidthAttr = F . getFnAttribute ( <STR_LIT> ) ; if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( <STR_LIT> ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += <STR_LIT> ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get


<s> } Insn = IsLittleEndian ? ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) : ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> const TargetRegisterClass * RC = & <STR_LIT> ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; return materialize32BitInt ( CI -> getZExtValue


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS1Operand ( const MachineInstr * MI , int Op ) { printThumbAddrModeRI5Operand ( MI ,


<s> DEBUG ( BB -> dump ( ) ) ; SelectRoot ( *


<s> static inline unsigned getAM6Opc ( bool WB =


<s> if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp ,


<s> const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( ) ) { printOperand ( P , MI , Op + <NUM_LIT> , O , Modifier ) ; O << ':'


<s> if ( TARGET_ARCH32 ) { const int size = GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) return UNITS_PER_WORD ; } else { if ( arg . aggregate_type_p ( ) ) { const int size = int_size_in_bytes ( arg . type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> || slotno == SPARC_FP_ARG_MAX - <NUM_LIT> ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_INT || ( ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT || ( arg . type && VECTOR_TYPE_P ( arg . type ) ) ) && ! ( TARGET_FPU && arg . named ) ) ) { const int size = ( arg . type && VECTOR_FLOAT_TYPE_P ( arg . type ) ) ? int_size_in_bytes ( arg . type ) : GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno ==


<s> const Value * V = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue VAList = DAG . getLoad ( getPointerTy ( ) , DL , Chain , Addr , MachinePointerInfo ( V ) , false , false , false , <NUM_LIT> ) ; Chain = VAList . getValue ( <NUM_LIT> ) ; if ( Align > <NUM_LIT> ) { assert ( ( ( Align & ( Align - <NUM_LIT> ) ) == <NUM_LIT> ) && <STR_LIT> ) ; VAList = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( Align - <NUM_LIT> , getPointerTy ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align , getPointerTy ( ) ) ) ; } Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint64_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = <NUM_LIT> ; bool NeedFPTrunc


<s> const TargetRegisterClass & RC = * MRI -> getRegClass ( VirtReg ) ; TII -> storeRegToStackSlot ( * MBB , Before , VirtReg , Kill , FI , & RC , TRI ) ; ++ NumStores


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_set_ps ( const float __Z , const float __Y , const float __X , const float __W ) { return __extension__ ( __m128 ) ( __v4sf ) {


<s> if ( ! Name . startswith ( <STR_LIT> ) ) return - <NUM_LIT> ; int Result = - <NUM_LIT> ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; Reg ++ ) { StringRef RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; if ( RegName . startswith ( <STR_LIT> ) && Name == RegName ) { Result = Reg -


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O , const char * Modifier ) { printOperand ( MI , opNum , O ) ; if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; return ; } const MCOperand & MO = MI -> getOperand


<s> SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> NewOpcode = IsAdd ? <STR_LIT> : <STR_LIT> ; break ; } SDLoc dl ( Op ) ; SDValue Add = DAG . getNode ( NewOpcode , dl , <STR_LIT> , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const BitMode32CalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRC ; else return


<s> else if ( rval >= <NUM_LIT> ) { context -> ireg [ regno - UNW_REG_R2 ] . nat = context -> ireg [ rval - <NUM_LIT> ] . nat ; } else if ( rval == <NUM_LIT> ) { context -> ireg [ regno - UNW_REG_R2 ] . nat . type = UNW_NAT_NONE ; context -> ireg [ regno - UNW_REG_R2 ] . nat . off = <NUM_LIT> ; } else abort ( ) ; break ; case UNW_WHERE_FR : context -> ireg [ regno - UNW_REG_R2 ] . nat . type = UNW_NAT_VAL ; context -> ireg [ regno - UNW_REG_R2 ] . nat . off = <NUM_LIT> ; break ; case UNW_WHERE_BR : context -> ireg [ regno - UNW_REG_R2 ] . nat . type = UNW_NAT_NONE ; context -> ireg [ regno - UNW_REG_R2 ] . nat . off = <NUM_LIT> ; break ; case UNW_WHERE_PSPREL : case UNW_WHERE_SPREL : context -> ireg [ regno - UNW_REG_R2 ] . nat . type = UNW_NAT_MEMSTK ; context -> ireg [ regno - UNW_REG_R2 ] . nat . off = context -> pri_unat_loc - ( unsigned long * ) addr ; break ; default : abort ( ) ; } break ; case UNW_REG_F2 ... UNW_REG_F31 : context -> fr_loc [ regno - UNW_REG_F2 ] = addr ; break ; case UNW_REG_B1 ... UNW_REG_B5 : context -> br_loc [ regno - UNW_REG_B0 ] = addr ; break ; case UNW_REG_BSP : context -> bsp_loc = addr ; break ; case UNW_REG_BSPSTORE : context -> bspstore_loc = addr ; break ; case UNW_REG_PFS : context -> pfs_loc = addr ; break ; case UNW_REG_RP : context -> rp = * ( unsigned long * ) addr ; break ; case UNW_REG_UNAT : context -> unat_loc = addr ; break ; case UNW_REG_PR : context -> pr = * ( unsigned long * ) addr ; break ; case UNW_REG_LC : context -> lc_loc = addr ; break ; case UNW_REG_FPSR : context -> fpsr_loc = addr ; break ; case UNW_REG_PSP : context -> psp = * (


<s> else return false ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( Target ) ; if ( BRCT != <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState ::


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> SuperDestReg = get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ; const auto SubRegIdx = TRI -> getSubRegIndex ( SuperDestReg , OrigDestReg ) ; if ( SubRegIdx == <STR_LIT> ) return false ; if ( ! LiveRegs . contains ( SuperDestReg ) ) { if ( SubRegIdx != <STR_LIT> ) return true ; if ( ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ) && ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( SuperDestReg , <NUM_LIT> , true ) ) ) return true ; } unsigned Opc = OrigMI -> getOpcode ( ) ; ( void ) Opc ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; if ( MO . isDef ( ) && TRI -> isSuperRegisterEq ( OrigDestReg , MO . getReg ( ) ) ) IsDefined = true ; if ( MO . isUse ( ) && ! TRI -> isSubRegisterEq ( OrigDestReg , MO . getReg ( ) ) && TRI -> regsOverlap (

SuperDestReg , MO . getReg ( ) ) ) return false ;


<s> inline int vec_any_lt ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgtfp_p ( __CR6_EQ_REV ,


<s> assert ( ( Subtarget -> hasSSE42 ( ) || Subtarget -> hasAVX ( ) ) && <STR_LIT> ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned Opc ; if ( ! Subtarget -> hasAVX ( ) ) { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> ; i < numArgs ;


<s> SDLoc DL ( Op ) ; AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceScope == CrossThread ) { return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , bool Is64Bit , int FPDiff , DebugLoc dl ) { if ( ! IsTailCall || FPDiff == <NUM_LIT> ) return Chain ; MVT VT =


<s> struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , strict_p ,


<s> MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] <<


<s> CurDAG -> RepositionNode ( N . getNode ( ) , M . getNode ( ) ) ; CurDAG -> ReplaceAllUsesWith ( N ,


<s> return Reg == <STR_LIT> ? Reg : get<ISA_LIT>SubSuperRegister ( Reg


<s> __builtin_altivec_stvehx ( ( vector signed short ) a1 , a2 , ( void * )


<s> bool IsCmpNE ; if ( ( Predicate == CmpInst :: ICMP_EQ ) || ( Predicate == CmpInst :: ICMP_NE ) ) { if ( const auto * C = dyn_cast < ConstantInt > ( LHS ) ) if ( C -> isNullValue ( ) ) std :: swap ( LHS , RHS ) ; if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( ! cast < ConstantInt > ( RHS ) -> isNullValue ( ) ) return false ; if ( const auto * AI = dyn_cast < BinaryOperator > ( LHS ) ) if ( AI -> getOpcode ( ) == Instruction :: And ) { const Value * AndLHS = AI -> getOperand ( <NUM_LIT> ) ; const Value * AndRHS = AI -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( AndLHS , AndRHS ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndRHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) { TestBit = C -> getValue ( ) . logBase2 ( ) ; LHS = AndLHS ; } } IsCmpNE = Predicate == CmpInst :: ICMP_NE ; } else if ( Predicate == CmpInst :: ICMP_SLT ) { if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( ! cast < ConstantInt > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = true ; } else if ( Predicate == CmpInst :: ICMP_SGT ) { if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != - <NUM_LIT> ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = false ; } else return false ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill (


<s> } else { reg [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; } for ( num_reg = ( mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; num_reg > <NUM_LIT> ; num_reg -- ) { sub_reg = gen_lowpart ( QImode , reg [ <NUM_LIT> ] ) ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( mem [ <NUM_LIT> ] , sub_reg ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_insn ( gen_lshrsi3 ( temp_reg , reg [ <NUM_LIT> ] , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_move_insn ( mem [ <NUM_LIT> ] , temp_sub_reg ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ; shift = <NUM_LIT> ; width = GET_MODE_SIZE ( SImode ) - <NUM_LIT> ; offset = offset +


<s> <ISA_LIT>TargetELFStreamer * S = new <ISA_LIT>TargetELFStreamer ( ) ; return createELFStreamer ( Context , S , MAB , OS


<s> SDValue RV = performIntegerAbsCombine ( N , DAG ) ; if ( RV . getNode ( ) ) return RV ; } if ( ! Subtarget -> hasBMI ( ) ) return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; assert ( Subtarget -> hasBMI ( ) && <STR_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; Predicates . insert ( Predicate ) ; IRBuilder < > Builder ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( cast < Instruction > ( Predicate ) ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } SRE -> getSymbol ( ) . print ( OS , MAI ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS <<


<s> FnStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; if ( GV -> hasExternalWeakLinkage ( ) ) ExtWeakSymbols . insert ( GV ) ; return ; } } if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; FnStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; return ; } } printOp ( MI -> getOperand


<s> need_barrier_p = false ; rtx adjust = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; if ( ! IMM12_OPERAND ( INTVAL ( adjust ) ) ) { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = LARCH_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx minus_offset = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , minus_offset ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = loongarch_first_stack_step ( frame ) ; step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { loongarch_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! IMM12_OPERAND ( step1 ) ) { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = LARCH_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX


<s> if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT ==


<s> return ( __m256i ) __builtin_ia32_cvtps2dq256_mask ( ( __v8sf ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if ( deadCPSR ) { assert ( ! MI -> getOperand ( ccOutIdx ) . getReg ( )


<s> case CRYPTO_BUILTIN_VPMSUMD : case CRYPTO_BUILTIN_VPMSUM : case MISC_BUILTIN_ADDG6S : case MISC_BUILTIN_DIVWEU : case MISC_BUILTIN_DIVDEU : case VSX_BUILTIN_UDIV_V2DI : case ALTIVEC_BUILTIN_VMAXUB : case ALTIVEC_BUILTIN_VMINUB : case ALTIVEC_BUILTIN_VMAXUH : case ALTIVEC_BUILTIN_VMINUH : case ALTIVEC_BUILTIN_VMAXUW : case ALTIVEC_BUILTIN_VMINUW : case P8V_BUILTIN_VMAXUD : case P8V_BUILTIN_VMINUD : case ALTIVEC_BUILTIN_VAND_V16QI_UNS : case ALTIVEC_BUILTIN_VAND_V8HI_UNS : case ALTIVEC_BUILTIN_VAND_V4SI_UNS : case ALTIVEC_BUILTIN_VAND_V2DI_UNS : case ALTIVEC_BUILTIN_VANDC_V16QI_UNS : case ALTIVEC_BUILTIN_VANDC_V8HI_UNS : case ALTIVEC_BUILTIN_VANDC_V4SI_UNS : case ALTIVEC_BUILTIN_VANDC_V2DI_UNS : case ALTIVEC_BUILTIN_VNOR_V16QI_UNS : case ALTIVEC_BUILTIN_VNOR_V8HI_UNS : case ALTIVEC_BUILTIN_VNOR_V4SI_UNS : case ALTIVEC_BUILTIN_VNOR_V2DI_UNS : case ALTIVEC_BUILTIN_VOR_V16QI_UNS : case ALTIVEC_BUILTIN_VOR_V8HI_UNS : case ALTIVEC_BUILTIN_VOR_V4SI_UNS : case ALTIVEC_BUILTIN_VOR_V2DI_UNS : case ALTIVEC_BUILTIN_VXOR_V16QI_UNS : case ALTIVEC_BUILTIN_VXOR_V8HI_UNS : case ALTIVEC_BUILTIN_VXOR_V4SI_UNS : case ALTIVEC_BUILTIN_VXOR_V2DI_UNS : case P8V_BUILTIN_EQV_V16QI_UNS : case P8V_BUILTIN_EQV_V8HI_UNS : case P8V_BUILTIN_EQV_V4SI_UNS : case P8V_BUILTIN_EQV_V2DI_UNS : case P8V_BUILTIN_EQV_V1TI_UNS : case P8V_BUILTIN_NAND_V16QI_UNS : case P8V_BUILTIN_NAND_V8HI_UNS : case P8V_BUILTIN_NAND_V4SI_UNS : case P8V_BUILTIN_NAND_V2DI_UNS : case P8V_BUILTIN_NAND_V1TI_UNS : case P8V_BUILTIN_ORC_V16QI_UNS : case P8V_BUILTIN_ORC_V8HI_UNS : case P8V_BUILTIN_ORC_V4SI_UNS : case P8V_BUILTIN_ORC_V2DI_UNS : case P8V_BUILTIN_ORC_V1TI_UNS : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI_UNS : case ALTIVEC_BUILTIN_VPERM_8HI_UNS : case ALTIVEC_BUILTIN_VPERM_4SI_UNS : case ALTIVEC_BUILTIN_VPERM_2DI_UNS : case ALTIVEC_BUILTIN_VSEL_16QI_UNS : case ALTIVEC_BUILTIN_VSEL_8HI_UNS : case ALTIVEC_BUILTIN_VSEL_4SI_UNS : case ALTIVEC_BUILTIN_VSEL_2DI_UNS : case VSX_BUILTIN_VPERM_16QI_UNS : case VSX_BUILTIN_VPERM_8HI_UNS : case VSX_BUILTIN_VPERM_4SI_UNS : case VSX_BUILTIN_VPERM_2DI_UNS : case VSX_BUILTIN_XXSEL_16QI_UNS : case VSX_BUILTIN_XXSEL_8HI_UNS : case VSX_BUILTIN_XXSEL_4SI_UNS : case VSX_BUILTIN_XXSEL_2DI_UNS : case CRYPTO_BUILTIN_VPERMXOR : case CRYPTO_BUILTIN_VPERMXOR_V2DI : case CRYPTO_BUILTIN_VPERMXOR_V4SI : case CRYPTO_BUILTIN_VPERMXOR_V8HI : case CRYPTO_BUILTIN_VPERMXOR_V16QI : case CRYPTO_BUILTIN_VSHASIGMAW : case CRYPTO_BUILTIN_VSHASIGMAD : case CRYPTO_BUILTIN_VSHASIGMA : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI : case ALTIVEC_BUILTIN_VPERM_8HI : case ALTIVEC_BUILTIN_VPERM_4SI : case ALTIVEC_BUILTIN_VPERM_4SF : case ALTIVEC_BUILTIN_VPERM_2DI : case ALTIVEC_BUILTIN_VPERM_2DF : case VSX_BUILTIN_VPERM_16QI : case VSX_BUILTIN_VPERM_8HI : case VSX_BUILTIN_VPERM_4SI : case VSX_BUILTIN_VPERM_4SF : case VSX_BUILTIN_VPERM_2DI : case VSX_BUILTIN_VPERM_2DF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVUXDSP : case VSX_BUILTIN_XVCVUXDDP_UNS : case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVDPUXDS_UNS : case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI : case MISC_BUILTIN_UNPACK_TD : case MISC_BUILTIN_UNPACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VCMPEQUB : case ALTIVEC_BUILTIN_VCMPEQUH : case ALTIVEC_BUILTIN_VCMPEQUW : case P8V_BUILTIN_VCMPEQUD : case VSX_BUILTIN_CMPGE_U16QI : case VSX_BUILTIN_CMPGE_U8HI : case VSX_BUILTIN_CMPGE_U4SI : case VSX_BUILTIN_CMPGE_U2DI : case ALTIVEC_BUILTIN_VCMPGTUB : case ALTIVEC_BUILTIN_VCMPGTUH : case ALTIVEC_BUILTIN_VCMPGTUW : case P8V_BUILTIN_VCMPGTUD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case MISC_BUILTIN_PACK_TD : case MISC_BUILTIN_PACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VSRB


emit<ISA_LIT>WinCFIPrologEnd ( Fragment ) ;


<s> if ( size % UNITS_PER_WORD != <NUM_LIT> ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . require ( ) ; } } return arm_libcall_value_1 (


<s> vec_uint4 mask ; bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) , <NUM_LIT> ) ; mask = ( vec_uint4 ) vec_sra ( vec_sl ( bv , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_andc ( vec_sl ( ( vec_uint4 ) ( a ) ,


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; mode = GET_MODE ( x ) ; if ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( mode ) ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( X87_FLOAT_MODE_P (


<s> if ( flags & MASK_UNALIGNED_DOUBLES ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_V8PLUS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS2 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS3 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS4 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_CBCOND ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_DEPRECATED_V8_INSNS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_SPARCLET ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_SPARCLITE )


<s> static <ISA_LIT>Operand * CreateShiftExtend ( <STR_LIT> ShiftTyp , unsigned Amount , bool ImplicitAmount , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftExtend ,


<s> if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes , NULL ) == - <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb232 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONDataInsn = insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } Size = <NUM_LIT> ; return MCDisassembler


<s> static DecodeStatus decodeU12ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address


<s> else return false ; nelt = d -> nelt ; if ( d -> perm [ <NUM_LIT> ] != <NUM_LIT> && d -> perm [ <NUM_LIT> ] != nelt / <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) if ( d -> perm [ i ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> || d -> perm [ i + <NUM_LIT> ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V32QImode : if ( d -> perm [ <NUM_LIT> ] ) gen = gen_vec_interleave_highv32qi ; else gen = gen_vec_interleave_lowv32qi ; break ; case


<s> __v4sf temp , rounded ; __vector unsigned long long result ; temp = ( __v4sf ) vec_splat ( ( __vector long long ) __A ,


<s> continue ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> || ! VA . isRegLoc ( ) || ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } else { switch ( static_cast < EVT > ( ArgVT ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT ,


<s> RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn


<s> UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) { assert ( ! SVEStackSize && <STR_LIT> ) ; UseFP = true ; } } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; StackOffset FPOffset = { ObjectOffset ,


<s> const DataLayout * DL = TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix

( ) << <STR_LIT> << getFunctionNumber ( ) ;


<s> bif_order = ( int * ) malloc ( ( curr_bif + <NUM_LIT> ) * sizeof ( int ) ) ; rbt_inorder_callback ( & bifo_rbt , bifo_rbt . rbt_root


<s> if ( CPEBB -> empty ( ) ) { if ( BBSizes [ CPEBB -> getNumber ( ) ] != <NUM_LIT> ) { Size += BBSizes [ CPEBB -> getNumber ( ) ] ; BBSizes [ CPEBB -> getNumber ( ) ] = <NUM_LIT> ; } } AdjustBBOffsetsAfter ( CPEBB ,


<s> if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> ) { std :: swap ( ValVT , LocVT ) ; MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ValVReg = MIRBuilder . buildTrunc ( RegTy , ValVReg ) . getReg ( <NUM_LIT> ) ; } else { MemSize = VA . getValVT ( ) .


V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue VAList = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue Stack = DAG . getFrameIndex ( FuncInfo -> getVariadicStackIdx ( ) , getPointerTy ( ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ) ; int GPRSize = FuncInfo -> getVariadicGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVariadicGPRIdx ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr

, MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = IntRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; EmitWindowsUnwindTables (


<s> gcc_assert ( reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX ) ; fprintf ( stderr , <STR_LIT> , line , store_p ? <STR_LIT> : <STR_LIT> ) ; if ( store_p ) set = gen_rtx_SET ( VOIDmode , mem , reg ) ; else set = gen_rtx_SET ( VOIDmode , reg , mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode ,


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++


<s> SmallVector < <ISA_LIT>SpeculativeLoadHardeningPass :: BlockCondInfo , <NUM_LIT> > <ISA_LIT>SpeculativeLoadHardeningPass :: collectBlockCondInfo ( MachineFunction & MF ) { SmallVector < BlockCondInfo , <NUM_LIT> > Infos ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . succ_size ( ) <= <NUM_LIT> ) continue ; BlockCondInfo Info = { & MBB , { } , nullptr } ; for ( MachineInstr & MI : llvm :: reverse ( MBB ) ) { if ( ! MI . isTerminator ( ) ) break ; if ( ! MI . isBranch ( ) ) { Info . CondBrs . clear ( ) ; break ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Info . CondBrs . clear ( ) ; Info . UncondBr = & MI ; continue ; } if ( <STR_LIT> ( MI ) == <STR_LIT> ) { Info . CondBrs . clear ( ) ; Info . UncondBr = & MI ; continue ; } Info . CondBrs . push_back ( & MI ) ; } if ( Info . CondBrs . empty ( ) ) { ++


<s> __o = __builtin_aarch64_ld4rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; return ret


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const

SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> rtx rmask [ MAX_VECT_LEN ] , mask ; gcc_checking_assert ( ! BYTES_BIG_ENDIAN ) ; mask = GEN_INT ( one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rmask [ i ] = mask ; mask = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rmask ) ) ; sel = expand_simple_binop ( vmode , AND , sel , mask ,


<s> EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , Op1 ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N )


<s> SDValue SatValue ; uint64_t SatConstant ; if ( isSaturatingConditional ( Op , SatValue , SatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg


<s> BaseType = RegBase ; Base . Reg = Reg


<s> unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI .


<s> static void rs6000_option_override ( void ) { ( void ) rs6000_option_override_internal ( true


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( ( uint64_t ) Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return true ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> - MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return true ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI . getOperand ( <NUM_LIT>

) . getImm ( ) <= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return true ;


<s> bool count_reg = false ; df_ref ref ; for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { df_ref use ; for ( use = DF_REG_USE_CHAIN ( regno ) ; use ; use = DF_REF_NEXT_REG ( use ) ) if ( bitmap_bit_p ( insns , DF_REF_INSN_UID ( use ) ) ) { rtx_insn * insn = DF_REF_INSN ( use ) ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set ) ; rtx src = SET_SRC ( def_set ) ; if ( ( GET_CODE ( src ) == ASHIFT || GET_CODE ( src ) == ASHIFTRT || GET_CODE ( src ) == LSHIFTRT ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && reg_or_subregno ( XEXP ( src , <NUM_LIT> ) ) == regno ) count_reg = true ; } start_sequence ( ) ; if ( count_reg ) { rtx qreg = gen_lowpart ( QImode , reg ) ; rtx tmp = gen_reg_rtx ( SImode ) ; if ( TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p ( cfun ) ) { emit_move_insn ( tmp , const0_rtx ) ; emit_insn ( gen_movstrictqi ( gen_lowpart ( QImode , tmp ) , qreg ) ) ; } else emit_insn ( gen_rtx_SET ( tmp , gen_rtx_ZERO_EXTEND ( SImode , qreg ) ) ) ; if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx slot = assign_386_stack_local ( SImode , SLOT_STV_TEMP ) ; emit_move_insn ( slot , tmp ) ; tmp = copy_rtx ( slot ) ; } emit_insn ( gen_zero_extendsidi2 ( vreg , tmp ) ) ; } else if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg


<s> if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx r0 = gen_rtx_REG (


<s> if ( Opcode == <STR_LIT> ) AddrMode = <STR_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; do MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; while ( MI . getNumOperands ( ) > FrameRegIdx + <NUM_LIT> ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , & MI ) ; AddDefaultPred ( MIB ) ; return true ; } bool HasCCOut = Opcode != <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; Offset = <NUM_LIT> ; return true ; } if ( Offset < <NUM_LIT> && ( ! HasCCOut || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ) { unsigned NewOpc = isSub ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( NewOpc ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( HasCCOut ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = countLeadingZeros < unsigned > ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false


<s> MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) ,


<s> const Value * RHS = II -> getArgOperand ( <NUM_LIT> ) ; if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) && II -> isCommutative ( ) ) std :: swap ( LHS , RHS ) ; <STR_LIT> IID = II -> getIntrinsicID ( ) ; switch ( IID ) { default : break ; case <STR_LIT> : if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) if ( C -> getValue ( ) == <NUM_LIT> ) IID = <STR_LIT> ; break ; case <STR_LIT> : if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) if ( C -> getValue ( ) == <NUM_LIT> ) IID = <STR_LIT> ; break ; } <STR_LIT> TmpCC ; switch ( IID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = getCombinedIndex ( CPEMI ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT>


<s> for ( const SDNode * User : Flags -> uses ( ) ) { unsigned CCOpNo ; switch ( User -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; case <STR_LIT> : CCOpNo = <NUM_LIT> ; break ; } <STR_LIT> CC = ( <STR_LIT> ) User -> getConstantOperandVal ( CCOpNo


<s> else if ( strcmp ( rs6000_tls_size_string , <STR_LIT> ) == <NUM_LIT> ) rs6000_tls_size = <NUM_LIT> ; else if ( strcmp ( rs6000_tls_size_string , <STR_LIT> ) == <NUM_LIT> ) rs6000_tls_size = <NUM_LIT> ; else if ( strcmp ( rs6000_tls_size_string , <STR_LIT> ) ==


<s> return aarch64_sve_emit_int_cmp ( target , mode , NE , src_mode , src ,


<s> return <STR_LIT> ; default : return <STR_LIT> ; } } if ( Opc == TargetOpcode :: G_ZEXT || Opc == TargetOpcode :: G_ANYEXT ) { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( Size != <NUM_LIT> && <STR_LIT> ) ; switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } } if ( Opc != TargetOpcode :: G_AND ) return <STR_LIT> ; Optional < uint64_t > MaybeAndMask = getImmedFromMO ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! MaybeAndMask ) return <STR_LIT> ; uint64_t AndMask = * MaybeAndMask ; switch ( AndMask ) { default : return <STR_LIT> ; case <NUM_LIT> : return ! IsLoadStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return ! IsLoadStore ? <STR_LIT>


<s> static SDValue LowerEXTRACT_SUBVECTOR ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT ResVT = Op . getSimpleValueType ( ) ; assert ( ResVT == <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT EltVT = ResVT . getVectorElementType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT LegalVT = ( TLI . getTypeToTransformTo ( * DAG . getContext ( ) , EltVT ) ) . getSimpleVT ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> ,


<s> static inline unsigned getAM3Opc ( AddrOpc Opc , unsigned char Offset , unsigned IdxMode = <NUM_LIT> ) { bool isSub = Opc == sub ; return ( ( int ) isSub << <NUM_LIT> ) | Offset | ( IdxMode


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent


<s> if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return std :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSSolaris ( ) ) return std :: make_unique < <ISA_LIT>SolarisTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return std :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return std :: make_unique <


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT>


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const


<s> if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Tilde : case AsmToken :: String : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; return ResTy != MatchOperand_Success ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal


<s> void emitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { emitByte ( Val & <NUM_LIT> , OS ) ; Val >>= <NUM_LIT>


<s> Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( CC ) ; updateValueMap ( I ,


<s> } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { if ( ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( ( unsigned short ) Imm >> <NUM_LIT> , getPointerTy ( ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr >> <NUM_LIT> , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } } Disp = DAG . getTargetConstant ( <NUM_LIT> ,


<s> static void sparc_dwarf_handle_frame_unspec ( const char * label , rtx pattern ATTRIBUTE_UNUSED , int


<s> if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return <NUM_LIT> ; if ( ! FLOAT128_2REG_P ( mode ) && ( TARGET_HARD_FLOAT || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , <NUM_LIT> ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict )


<s> for ( auto & P : PermuteForms ) if ( matchPermute ( Bytes , P , OpNo0 , OpNo1 ) ) return & P ; return nullptr


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr


<s> if ( AlignBoundary == Align :: None ( ) || AlignBranchType == <STR_LIT> ) return false ; MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( Assembler . isBundlingEnabled ( ) && Sec -> isBundleLocked ( ) )


<s> void <ISA_LIT>ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind ,


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv16qi ( (


<s> static bool isMOVSHDUPMask ( ArrayRef < int > Mask , MVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is512BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i + <NUM_LIT> ) ) return false ; return true


<s> Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB

:: MEMSET ) , TLI . getPointerTy ( ) ) , & Args , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> const char * output_64bit_and ( rtx * operands ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) { unsigned HOST_WIDE_INT mask = INTVAL ( operands [ <NUM_LIT> ] ) ; int ls0 , ls1 , ms0 , p , len ; for ( ls0 = <NUM_LIT> ; ls0 < HOST_BITS_PER_WIDE_INT ; ls0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ls0 ) ) == <NUM_LIT> ) break ; for ( ls1 = ls0 ; ls1 < HOST_BITS_PER_WIDE_INT ; ls1 ++ ) if ( ( mask

& ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ls1 ) ) != <NUM_LIT> ) break ;


<s> FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return true ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return true ; return false


<s> break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE (


<s> else if ( REG_P ( op0 ) && MEM_P ( op1 ) ) ret = ( quad_int_reg_operand ( op0 , GET_MODE ( op0 ) ) && quad_memory_operand ( op1 , GET_MODE ( op1 ) ) && ! reg_overlap_mentioned_p ( op0 , op1 ) ) ; else if ( MEM_P ( op0 ) && REG_P ( op1 ) ) ret = ( quad_memory_operand ( op0 , GET_MODE ( op0 ) ) && quad_int_reg_operand ( op1 , GET_MODE ( op1 ) ) ) ; else ret = false ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( gen_rtx_SET ( op0 , op1 )


<s> } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true )


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { CurrGroupSize =


<s> return BaseType == FrameIndexBase || IndexReg . getNode ( ) != <NUM_LIT> || Base_Reg


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SyntaxUnified


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitSRA_FLAG ( const SDNode


<s> void <ISA_LIT>LongBranch :: initMBBInfo ( ) { for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ) splitMBB ( I ++ ) ; MF -> RenumberBlocks ( ) ; MBBInfos . clear ( ) ; MBBInfos . resize ( MF -> size ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( ! getTargetMachine ( ) . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return false ; return Subtarget -> ClassifyGlobalReference ( GA -> getGlobal (

) , getTargetMachine ( ) ) == <STR_LIT> ;


<s> const uint64_t StackSize = MFI -> getStackSize ( ) ; { assert ( ! TRI -> hasBasePointer ( MF ) && <STR_LIT> ) ; int TailCallReturnAddrDelta = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) ; assert ( ! ( TailCallReturnAddrDelta < <NUM_LIT> ) && <STR_LIT> ) ; } FrameReg = TRI -> getStackRegister ( ) ; int Offset = MFI -> getObjectOffset ( FI ) -


<s> bool <ISA_LIT>TTIImpl :: supportsEfficientVectorElementLoadStore ( ) const { return


<s> if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg


<s> if ( ! DECL_ARTIFICIAL ( decl ) ) warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , decl ) ; return false ; } else if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_INLINE ( decl ) ) { if ( extra_warnings ) warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , decl ) ; return false ; } else if ( TREE_CODE ( decl ) == VAR_DECL && TREE_STATIC ( decl ) && TREE_PUBLIC ( decl ) && ! DECL_EXTERNAL ( decl ) ) { if ( ! DECL_VIRTUAL_P ( decl ) ) error ( <STR_LIT> , decl ) ; return false ; } else if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE && ( DECL_VIRTUAL_P ( decl ) || DECL_ARTIFICIAL ( decl ) ) ) return false ; return


<s> for ( first_reg = <NUM_LIT> + <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if (


<s> for ( auto & I : * BB ) { LoadInst * LoadI = dyn_cast < LoadInst > ( & I ) ; if ( ! LoadI ) continue ; Value * PtrValue = LoadI -> getPointerOperand ( ) ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE . getSCEV ( PtrValue ) ; const SCEVAddRecExpr * LSCEVAddRec = dyn_cast


<s> break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( TARGET_SVE ) { int bits ; if ( ! BITS_PER_SVE_VECTOR . is_constant ( & bits ) ) bits = <NUM_LIT> ; builtin_define_with_int_value ( <STR_LIT> , bits ) ; } aarch64_def_or_undef ( TARGET_LSE , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_AES , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; builtin_define_with_int_value ( <STR_LIT> , c_flt_eval_method ( true ) ) ; cpp_undef ( pfile , <STR_LIT> ) ; builtin_define_with_int_value ( <STR_LIT> , c_flt_eval_method ( false


<s> obstack_blank ( & opts_obstack , <NUM_LIT> ) ; obstack_grow ( & opts_obstack , ( const void * ) ( S ) , \ sizeof ( ( S ) ) / sizeof ( char ) - <NUM_LIT> ) obstack_grow ( & opts_obstack , ( const void * ) ( S ) , strlen ( ( S ) ) ) APPEND_LTR ( <STR_LIT> OPTSTR_ ## NAME <STR_LIT> \ <STR_LIT> OPTSTR_ ## NAME <STR_LIT> ) for ( int i = <NUM_LIT> ; i < N_SWITCH_TYPES ; i ++ ) { APPEND_LTR ( <STR_LIT> ) ; APPEND_VAL ( loongarch_switch_strings [ i ]


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setReorder


<s> return ( __m128i ) __builtin_ia32_pmovusdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8


<s> if ( TT . isOSBinFormatELF ( ) ) return create<ISA_LIT>ObjectTargetELFStreamer ( S ) ; if ( TT . isOSBinFormatCOFF ( )


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,


<s> return mips_split_move_p ( dest , src , mips_insn_split_type ( insn


<s> case ENCODING_RM : return translateRM ( mcInst , operand , insn ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [


<s> assert ( ( Kind == k_MemoryReg || Kind == k_MemoryImm ) && <STR_LIT> ) ; return Mem . Base


<s> const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_IMPLICIT_DEF , s64 } , Legal ) ; setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset ,


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; const static MCFixupKindInfo InfosBE [


<s> return ( __m512i ) __builtin_ia32_vcvtph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 ) - <NUM_LIT> ,


<s> return ( int32x2_t ) __builtin_aarch64_sqrshrn_nv2di (


<s> MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII -> getRegisterInfo ( ) ) ; MI -> eraseFromParent


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return <NUM_LIT>


<s> if ( Subtarget . hasSSE41 ( ) ) { if ( Offset && Scale == <NUM_LIT> && VT . is128BitVector ( ) ) return SDValue ( ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( EltBits * Scale ) , NumElements / Scale ) ; InputV = ShuffleOffset ( InputV ) ; InputV = getExtendInVec ( <STR_LIT> , DL , ExtVT , InputV , DAG ) ; return DAG . getBitcast ( VT , InputV ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( AnyExt && EltBits == <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { Offset , - <NUM_LIT> , SafeOffset ( Offset + <NUM_LIT> ) ? Offset + <NUM_LIT> : - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { Offset / <NUM_LIT> , - <NUM_LIT> , SafeOffset ( Offset + <NUM_LIT> ) ? ( Offset + <NUM_LIT> ) / <NUM_LIT> : - <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ; int PSHUFWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; unsigned OddEvenOp = ( Offset & <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getBitcast ( VT , DAG . getNode ( OddEvenOp , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFWMask , DL , DAG ) ) ) ; } if ( ( Scale * EltBits ) == <NUM_LIT> && EltBits < <NUM_LIT> && Subtarget . hasSSE4A ( ) ) { assert ( NumElements == ( int ) Mask . size ( ) && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; int LoIdx = Offset * EltBits ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , InputV , DAG . getConstant ( EltBits , DL , <STR_LIT> ) , DAG . getConstant ( LoIdx , DL , <STR_LIT> ) ) ) ; if ( isUndefUpperHalf ( Mask ) || ! SafeOffset ( Offset + <NUM_LIT> ) ) return DAG . getBitcast ( VT , Lo ) ; int HiIdx = ( Offset + <NUM_LIT> ) * EltBits ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , InputV , DAG . getConstant ( EltBits , DL , <STR_LIT> ) , DAG . getConstant (


<s> if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ]


<s> auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>LegalizerInfo * LI = static_cast < const <ISA_LIT>LegalizerInfo * > ( ST . getLegalizerInfo ( ) ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; <ISA_LIT>PostLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , LI ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr >