<s> return Error ( NameLoc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc , * this ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) && ParseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( ParseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && ParseParenSuffix ( Name , Operands ) ) return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_GOTENT ; llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PLT : assert ( IsPCRel && <STR_LIT> ) ; return getPLTReloc ( Kind )


<s> } } vector_type_index base_vector_type ; if ( type == NUM_TYPE_SUFFIXES ) { base_vector_type = infer_vector_base_type ( argno ) ; if ( base_vector_type == NUM_VECTOR_TYPES ) return MODE_none ; } else { type_suffix_index base_type = infer_vector_type ( argno ) ; if ( base_type == NUM_TYPE_SUFFIXES ) return MODE_none ; unsigned int required_bits = type_suffixes [ type ] . element_bits ; gcc_assert ( required_bits == <NUM_LIT> || required_bits == <NUM_LIT> ) ; type_suffix_index required_type = ( required_bits == <NUM_LIT> ? TYPE_SUFFIX_u32 : TYPE_SUFFIX_u64 ) ; if ( required_type != base_type ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , get_vector_type ( required_type ) ) ; return MODE_none


<s> LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , LN -> getPointerInfo ( ) , LN -> getAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> )


<s> void Emitter < CodeEmitter > :: emitMachineBasicBlock ( MachineBasicBlock * BB


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res >> <NUM_LIT> ; } assert ( MO . isExpr (


<s> static bool isVREVMask ( const SmallVectorImpl < int > & M , EVT VT , unsigned BlockSize ) { assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ; if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts -

<NUM_LIT> - i % BlockElts ) ) return false ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> rtx in_down = code == ASHIFT ? in_high : in_low ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; gcc_assert ( out && ( REG_P ( out ) || GET_CODE ( out ) == SUBREG ) && GET_MODE ( out ) == DImode ) ; gcc_assert ( in && ( REG_P ( in ) || GET_CODE ( in ) == SUBREG ) && GET_MODE ( in ) == DImode ) ; gcc_assert ( amount && ( ( ( REG_P ( amount ) || GET_CODE ( amount ) == SUBREG ) && GET_MODE ( amount ) == SImode ) || CONST_INT_P ( amount ) ) ) ; gcc_assert ( scratch1 == NULL || ( GET_CODE ( scratch1 ) == SCRATCH ) || ( GET_MODE ( scratch1 ) == SImode && REG_P ( scratch1 ) ) ) ; gcc_assert ( scratch2 == NULL || ( GET_CODE ( scratch2 ) == SCRATCH ) || ( GET_MODE ( scratch2 ) == SImode && REG_P ( scratch2 ) ) ) ; gcc_assert ( ! REG_P ( out ) || ! REG_P ( amount ) || ! HARD_REGISTER_P ( out ) || ( REGNO ( out ) != REGNO ( amount ) && REGNO ( out ) + <NUM_LIT> != REGNO ( amount ) ) ) ; gen_addsi3 ( ( DEST ) , ( SRC ) , GEN_INT ( - <NUM_LIT> ) ) gen_subsi3 ( ( DEST ) , GEN_INT ( <NUM_LIT> ) , ( SRC ) ) gen_addsi3_compare0 ( ( DEST ) , ( SRC ) , \ GEN_INT ( - <NUM_LIT> ) ) gen_rtx_SET ( ( DEST ) , ( SRC ) ) gen_rtx_fmt_ee ( ( CODE ) , SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_fmt_ee ( ( CODE ) == ASHIFT ? ASHIFT : LSHIFTRT , \ SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_fmt_ee ( ( CODE ) == ASHIFT ? LSHIFTRT : ASHIFT , \ SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_IOR ( SImode , ( A ) , ( B ) ) gen_arm_cond_branch ( ( LABEL ) , \ gen_rtx_ ## COND ( CCmode , cc_reg , \ const0_rtx ) , \ cc_reg ) if ( CONST_INT_P ( amount ) ) { if ( INTVAL ( amount ) <= <NUM_LIT> ) emit_insn (


<s> Result = DAG . getNode ( getGlobalWrapperKind ( GV ) , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , DAG . getConstant ( Offset , dl , PtrVT ) ) ; return Result


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value


<s> unsigned rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool hasAsi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned asi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeRD ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: createImm ( simm13 ) ) ; else { status = DecodeIntRegsRegisterClass ( MI , rs2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } if ( hasAsi ) MI . addOperand ( MCOperand :: createImm ( asi ) ) ; if ( !


<s> SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ( <NUM_LIT> ) ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } RetOps [ <NUM_LIT> ] =


<s> bool isMemoryRegisterOffset16 ( ) const { return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal == <NUM_LIT> || Mem


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeVR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> x . s [ <NUM_LIT> ] = s ; return ( x . q


<s> II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I


<s> if ( mode == V2DFmode ) emit_insn ( gen_vsx_concat_v2df ( target , op0 , op1 ) ) ; else emit_insn ( gen_vsx_concat_v2di ( target , op0 , op1 ) ) ; } return ; } if ( mode == V4SFmode && VECTOR_MEM_VSX_P ( mode ) ) { if ( all_same ) { rtx freg = gen_reg_rtx ( V4SFmode ) ; rtx sreg = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx cvt = ( ( TARGET_XSCVDPSPN ) ? gen_vsx_xscvdpspn_scalar ( freg , sreg ) : gen_vsx_xscvdpsp_scalar ( freg , sreg ) ) ; emit_insn ( cvt ) ; emit_insn ( gen_vsx_xxspltw_v4sf_direct ( target , freg , const0_rtx ) ) ; } else { rtx dbl_even = gen_reg_rtx ( V2DFmode ) ; rtx dbl_odd = gen_reg_rtx ( V2DFmode ) ; rtx flt_even = gen_reg_rtx ( V4SFmode ) ; rtx flt_odd = gen_reg_rtx ( V4SFmode ) ; rtx op0 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op1 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op2 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op3 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_even , op0 , op1 ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_odd , op2 , op3 ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_even , dbl_even ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_odd , dbl_odd ) ) ; rs6000_expand_extract_even ( target , flt_even , flt_odd


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked (


<s> if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) SplitArgs . back ( ) . Flags [ <NUM_LIT> ] . setZExt ( ) ; } bool IsSibCall = Info . IsTailCall && isEligibleForTailCallOptimization ( MIRBuilder , Info ) ; if ( IsSibCall ) MF . getFrameInfo ( ) . setHasTailCall ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( Info . CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( Info . CallConv , true ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( F , Info . Callee . isReg ( ) , IsSibCall ) ; if ( Opc == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; if ( IsSibCall ) MIB . addImm ( <NUM_LIT> ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> >


<s> SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Z = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Op0 ,


<s> MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym -> print ( O , P . MAI ) ; else { O << '(' ; GVSym -> print ( O , P . MAI ) ; O << ')' ; } P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable (


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleNoCRC ( ) { OS <<


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind (


<s> switch ( MI . getOpcode ( ) ) { default : return


<s> MachineBasicBlock * NextBB = & * std :: next ( MBBI ) ; if ( std :: find ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) , NextBB ) == MBB -> succ_end (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> for ( unsigned i = NumElts / <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , NumElts / <NUM_LIT> ) ) return false ; return


<s> type = TYPE_MAIN_VARIANT ( type ) ; align = TYPE_ALIGN ( type ) ; } else align = GET_MODE_ALIGNMENT ( mode ) ; if ( align < PARM_BOUNDARY ) align = PARM_BOUNDARY ; else { static bool warned ; unsigned int saved_align = align ; if ( ! TARGET_64BIT ) { if ( ! type ) { if ( mode == XFmode || mode == XCmode ) align = PARM_BOUNDARY ; } else if ( ! ix86_contains_aligned_value_p ( type ) ) align = PARM_BOUNDARY ; if ( align < <NUM_LIT> ) align = PARM_BOUNDARY ; } if ( warn_psabi && ! warned && align != ix86_compat_function_arg_boundary ( mode , type , saved_align ) ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT ) ; } } return align


<s> if ( isGPRAsmReg ( ) && RegIdx . Index == <NUM_LIT> ) return true ; return Kind == k_PhysRegister


<s> } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex (


<s> static void mips_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx addr , end_addr , high , low , opcode , mem ; rtx trampoline [ <NUM_LIT> ] ; unsigned int i , j ; HOST_WIDE_INT end_addr_offset , static_chain_offset , target_function_offset ; end_addr_offset = mips_trampoline_code_size ( ) ; static_chain_offset = end_addr_offset ; target_function_offset = static_chain_offset + GET_MODE_SIZE ( ptr_mode ) ; addr = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; end_addr = mips_force_binary ( Pmode , PLUS , addr , GEN_INT ( end_addr_offset ) ) ; i = <NUM_LIT> ; if ( TARGET_USE_PIC_FN_ADDR_REG ) { trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( AT_REGNUM , target_function_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( STATIC_CHAIN_REGNUM , static_chain_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_JR ( AT_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_MOVE ( PIC_FUNCTION_ADDR_REGNUM , AT_REGNUM ) ) ; } else if ( ptr_mode == DImode ) { trampoline [ i ++ ] = OP ( MIPS_MOVE ( AT_REGNUM , RETURN_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_BAL ( <NUM_LIT> ) ) ; trampoline [ i ++ ] = OP ( MIPS_NOP ) ; trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( PIC_FUNCTION_ADDR_REGNUM , target_function_offset - <NUM_LIT> , RETURN_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( STATIC_CHAIN_REGNUM , static_chain_offset - <NUM_LIT> , RETURN_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_JR ( PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_MOVE ( RETURN_ADDR_REGNUM , AT_REGNUM ) ) ; } else { high = expand_simple_binop ( SImode , PLUS , end_addr , GEN_INT ( <NUM_LIT> ) , NULL , false , OPTAB_WIDEN ) ; high = expand_simple_binop ( SImode , LSHIFTRT , high , GEN_INT ( <NUM_LIT>


<s> if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; } else return false ; MachineInstr * BI = & * MBB . getFirstInstrTerminator ( ) ; MachineInstr * CMPI = MRI -> getVRegDef ( BI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( int I = <NUM_LIT> ; I <= <NUM_LIT> ; I ++ ) if

( CMPI -> getOperand ( I ) . isReg ( ) ) {


<s> SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op .


<s> const MCSection * DefaultSection = TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ; if ( DefaultSection != ReadOnlySection ) return DefaultSection ; const GlobalVariable * GVar = dyn_cast


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : case TFmode : case KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true


<s> if ( Op . getOpcode ( ) == <STR_LIT> && Op . getSimpleValueType ( ) == <STR_LIT> ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; bool


<s> const unsigned DstSz = Op . getValueType ( ) . getSizeInBits ( ) ; const unsigned SrcSz = SrcVal . getValueType ( ) . getSizeInBits ( ) ; assert ( DstSz > SrcSz && DstSz <= <NUM_LIT> && SrcSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ; assert ( ! ( DstSz == <NUM_LIT> && Subtarget -> hasFP16 ( ) ) && <STR_LIT> ) ; SDLoc Loc ( Op ) ; RTLIB :: Libcall LC ; MakeLibCallOptions CallOptions ; if ( SrcSz == <NUM_LIT> ) { if ( Subtarget -> hasFP16 ( ) ) SrcVal = DAG . getNode ( <STR_LIT> , Loc , <STR_LIT> , SrcVal ) ; else { LC = RTLIB :: getFPEXT ( <STR_LIT> , <STR_LIT> ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SrcVal = makeLibCall ( DAG , LC , <STR_LIT> , SrcVal , CallOptions , Loc ) . first ; } } if ( DstSz != <NUM_LIT> ) return SrcVal ; if ( Subtarget -> hasFP64 ( ) ) return DAG . getNode ( <STR_LIT> , Loc , <STR_LIT> , SrcVal ) ; LC = RTLIB :: getFPEXT ( <STR_LIT>


<s> MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; BuildMI ( TrueBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfTrueReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; TrueBB -> addSuccessor ( EndBB ) ; if ( ! NZCVKilled ) EndBB -> addLiveIn ( <STR_LIT> ) ; MachineInstr * StartOfEnd = EndBB -> begin ( ) ; BuildMI ( * EndBB , StartOfEnd , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addFrameIndex (


<s> static void nds32_expand_to_rtl_hook ( void


<s> unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = Fn . CreateMachineBasicBlock ( ) ; Fn . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . CPEMI = BuildMI ( NewIsland , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; NumCPEs


<s> Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Q = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd ,

Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static DecodeStatus DecodeLongShiftOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) Val = <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return S


<s> vabaq_s32 ( int32x4_t a , int32x4_t b , int32x4_t c ) { int32x4_t result


<s> bool <ISA_LIT>DAGToDAGISel :: SelectTLSADDRAddr ( SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { assert ( N . getOpcode ( ) == <STR_LIT> ) ; const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( N ) ; <ISA_LIT>ISelAddressMode AM ; AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , N . getValueType ( ) ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> && ! Subtarget -> isTargetNaCl64 ( ) ) { AM . Scale =


<s> bool isMemVY64 ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) &&

getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> const TargetInstrInfo * TII = STI -> getInstrInfo ( ) ; const DebugLoc & DL = VAStartPseudoInstr -> getDebugLoc ( ) ; Register CountReg = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LivePhysRegs LiveRegs ( * STI -> getRegisterInfo ( ) ) ; SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . addLiveIns ( * EntryBlk ) ; for ( MachineInstr & MI : EntryBlk -> instrs ( ) ) { if ( MI . getOpcode ( ) == VAStartPseudoInstr -> getOpcode ( ) ) break ; LiveRegs . stepForward ( MI , Clobbers ) ; } const BasicBlock * LLVMBlk = EntryBlk -> getBasicBlock ( ) ; MachineFunction :: iterator EntryBlkIter = ++ EntryBlk -> getIterator ( ) ; MachineBasicBlock * GuardedRegsBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; MachineBasicBlock * TailBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; Func -> insert ( EntryBlkIter , GuardedRegsBlk ) ; Func -> insert ( EntryBlkIter , TailBlk ) ; TailBlk -> splice ( TailBlk -> begin ( ) , EntryBlk , std :: next ( MachineBasicBlock :: iterator ( VAStartPseudoInstr ) ) , EntryBlk -> end ( ) ) ; TailBlk -> transferSuccessorsAndUpdatePHIs ( EntryBlk ) ; uint64_t FrameOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t VarArgsRegsOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MOVOpc = STI -> hasAVX ( ) ? <STR_LIT>


<s> AttributeList A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: NoInline ) ; FunctionCallee F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( ! TM . isPositionIndependent ( )


<s> * Residue = Displacement ; return <STR_LIT> ( Op . getMemModeSize ( ) , Op . getMemSegReg ( ) , Op . getMemDisp ( ) , Op . getMemBaseReg ( ) , Op . getMemIndexReg ( ) , Op . getMemScale ( ) , SMLoc ( ) , SMLoc ( ) ) ; } int64_t OrigDisplacement = static_cast < const MCConstantExpr * > ( Op . getMemDisp ( ) ) -> getValue ( ) ; CheckDisplacementBounds ( OrigDisplacement


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue (


<s> unsigned UpdReg = ( Opcode ? MRI . createVirtualRegister ( ValueRC ) : Rs2Reg ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , ValReg ) . addReg ( Val0Reg ) . addMBB ( MBB ) . addReg ( DestReg ) . addMBB ( LoopMBB ) ; if ( CondCode ) { BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ValReg ) . addReg ( Rs2Reg ) ; BuildMI ( LoopMBB , DL , TII . get ( Opcode ) , UpdReg ) . addReg ( ValReg ) . addReg ( Rs2Reg ) . addImm ( CondCode ) ; } else if ( Opcode ) { BuildMI ( LoopMBB , DL , TII . get ( Opcode ) , UpdReg ) . addReg ( ValReg ) . addReg ( Rs2Reg ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned TmpReg = UpdReg ; UpdReg = MRI . createVirtualRegister ( ValueRC ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , UpdReg ) . addReg ( TmpReg ) . addImm ( - <NUM_LIT> ) ; } BuildMI ( LoopMBB , DL , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( AddrReg ) . addReg ( ValReg ) . addReg ( UpdReg ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ValReg ) . addReg ( DestReg ) ; BuildMI ( LoopMBB , DL , TII . get ( is64Bit ? <STR_LIT> :

<STR_LIT> ) ) . addMBB ( LoopMBB ) . addImm ( <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , TargetFS , * this ) { initAsmInfo (


<s> } if ( TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI ) { set_optab_libfunc ( add_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , SFmode , SImode , <STR_LIT> ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , DFmode ,


<s> if ( isMicro<ISA_LIT> ( STI ) && hasShortDelaySlot ) { Opc = is<ISA_LIT>32r6 ( STI ) ? <STR_LIT> : <STR_LIT> ; emitRR ( Opc , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; return ; } if ( isMicro<ISA_LIT> ( STI ) ) Opc = is<ISA_LIT>32r6 ( STI ) ? <STR_LIT> : <STR_LIT> ; emitRRI ( Opc , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc ,


<s> else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) RC = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; else return Error ( RegLoc , <STR_LIT> ) ; EReg = MRI -> getEncodingValue ( Reg ) ; Registers . push_back ( std :: pair < unsigned , unsigned > ( EReg , Reg ) ) ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc AfterMinusLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) return Error ( AfterMinusLoc , <STR_LIT> ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! RC -> contains ( EndReg ) ) return Error ( AfterMinusLoc , <STR_LIT> ) ; if ( MRI -> getEncodingValue ( Reg ) > MRI -> getEncodingValue ( EndReg ) ) return Error ( AfterMinusLoc , <STR_LIT> ) ; while ( Reg != EndReg ) { Reg = getNextRegister ( Reg ) ; EReg = MRI -> getEncodingValue ( Reg ) ; Registers . push_back ( std :: pair < unsigned , unsigned > ( EReg , Reg ) ) ; } continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg =


<s> if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { ++ Idx ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : ++ GPRCnt ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasSSE1 ( ) ) return false ; ++ FPRCnt ; break ; } if ( GPRCnt > <NUM_LIT> ) return false ; if ( FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( Arg . getType ( ) ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned SrcReg ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SrcReg = GPR32ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : SrcReg = GPR64ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : case <STR_LIT> : SrcReg = XMMArgRegs [ FPRIdx


<s> if ( TLI . supportSplitCSR ( FuncInfo . MF ) ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: Tail && CC != CallingConv :: SwiftTail && CC != CallingConv :: <ISA_LIT>_FastCall && CC != CallingConv :: <ISA_LIT>_StdCall && CC != CallingConv :: <ISA_LIT>_ThisCall && CC != CallingConv :: <ISA_LIT>_64_SysV && CC != CallingConv :: Win64 ) return false ; if ( ! isUInt < <NUM_LIT> > ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) ) ) return false ; if ( ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) || CC == CallingConv :: Tail || CC == CallingConv :: SwiftTail ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; Register Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return


<s> static SDValue LowerSDIV ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG


<s> unsigned IndexReg = Inst -> getOperand ( IndexOpPosition ) . getReg ( ) ; if ( UseZeroBasedSandbox ) { Inst -> getOperand ( IndexOpPosition ) . setReg ( DemoteRegTo32_ ( IndexReg ) ) ; } else { EmitRegTruncate ( IndexReg , Out


<s> void llvm :: addPredicatedMveVpredNOp ( MachineInstrBuilder & MIB , unsigned Cond ) { MIB . addImm (


<s> StringRef getPassName ( ) const override { return


<s> if ( FP_REG_CLASS_P ( rclass ) || rclass == GENERAL_OR_FP_REGS || rclass == GENERAL_OR_EXTRA_FP_REGS || ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && ! TARGET_FPU ) || ( mode == TFmode && ! const_zero_operand ( x , mode ) ) ) return NO_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_INT )


<s> unsigned getATRegIndex ( ) const { return ATReg


<s> SmallVector < MachineInstr * , <NUM_LIT> > Phis ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( MI . getOpcode ( ) == TargetOpcode :: G_PHI ) Phis . emplace_back ( & MI ) ; } } for ( auto * MI : Phis ) { bool HasGPROp = false , HasFPROp = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) { if ( ! MO . isReg ( ) ) continue ; const LLT & Ty = MRI . getType ( MO . getReg ( ) ) ; if ( ! Ty . isValid ( ) || ! Ty .


<s> case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ <NUM_LIT> ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ <NUM_LIT> ] , two31r , val , tmp [ <NUM_LIT> ] ) ) ; tmp [ <NUM_LIT> ] = expand_simple_binop ( mode , AND , tmp [ <NUM_LIT> ] , two31r , tmp [ <NUM_LIT> ] , <NUM_LIT> , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ <NUM_LIT> ] ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> <<


<s> return ( loongarch_classify_address ( & addr , x , mode , false ) && ( ( addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && LARCH_12BIT_OFFSET_P ( INTVAL ( addr . offset )

) ) || addr . type == ADDRESS_LO_SUM ) ) ;


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo >

( ) -> isCmseNSEntryFunction ( ) ) return false ;


<s> SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . is ( AsmToken :: EndOfStatement ) ) Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return false ; } SMLoc E = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( E ,


<s> OutStreamer -> emitLabel ( CurSled ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( Ret ,


<s> return MCSymbolRefExpr :: Create ( Context . GetOrCreateSymbol ( Name ) , MCSymbolRefExpr ::


<s> static_assert ( ( <STR_LIT> + <NUM_LIT> == <STR_LIT> ) && ( <STR_LIT> + <NUM_LIT> == <STR_LIT> ) , <STR_LIT> ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; if ( ShiftImm >= RetVT . getSizeInBits ( ) ) return <NUM_LIT> ; const TargetRegisterClass * RC ; unsigned Opc ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; } Register ResultReg = fastEmitInst_rri ( Opc , RC , LHSReg , RHSReg , <STR_LIT> ( <STR_LIT> , ShiftImm ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ?


<s> MCStreamer * S = llvm :: createNullStreamer ( Ctx ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S


<s> assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { SDValue GotAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG

. getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ;


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( bool is64Bit , const Triple & T ) { if ( is64Bit ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = false ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ! is64Bit ) Data64bitsDirective =


<s> unsigned CstSizeInBits = CstTy -> getPrimitiveSizeInBits ( ) ; unsigned CstEltSizeInBits = CstTy -> getScalarSizeInBits ( ) ; unsigned NumCstElts = CstTy -> getNumElements ( ) ; assert ( ( CstSizeInBits % MaskEltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumMaskElts = CstSizeInBits / MaskEltSizeInBits ; UndefElts = APInt ( NumMaskElts , <NUM_LIT> ) ; RawMask . resize ( NumMaskElts , <NUM_LIT> ) ; if ( MaskEltSizeInBits == CstEltSizeInBits ) { assert ( NumCstElts == NumMaskElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; if ( isa < UndefValue > ( COp ) ) { UndefElts . setBit ( i ) ; RawMask [ i ] = <NUM_LIT> ; continue ; } auto * Elt = cast < ConstantInt > ( COp ) ; RawMask [ i ] = Elt -> getValue ( ) . getZExtValue ( ) ; } return true ; } APInt UndefBits ( CstSizeInBits , <NUM_LIT> ) ; APInt MaskBits ( CstSizeInBits , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; unsigned BitOffset = i *


<s> if ( ! hasBasePointer ( MF ) ) return getFrameRegister ( MF ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) return <STR_LIT> ; if ( Subtarget . isSVR4ABI ( ) && MF . getTarget ( ) . getRelocationModel (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned <ISA_LIT>FastISel :: getRegForGEPIndex ( const Value * Idx ) { unsigned IdxN = getRegForValue ( Idx ) ; if ( IdxN == <NUM_LIT> ) return <NUM_LIT> ; MVT PtrVT = TLI . getPointerTy ( DL ) ; EVT IdxVT = EVT :: getEVT ( Idx -> getType ( ) , false ) ; if ( IdxVT . bitsLT ( PtrVT ) ) { IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false ) ; } else if ( IdxVT . bitsGT ( PtrVT )


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNo , raw_ostream & O , const char * Modifier ) { O << <STR_LIT> ; printOperand ( MI , OpNo , O , NULL ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O , NULL ) ; O << <STR_LIT>


<s> } if ( GO -> isDeclaration ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForExternalReference ( GO , TM ) ) -> getQualNameSymbol ( ) ; } SectionKind GOKind = getObjFileLowering ( ) . getKindForGlobal ( GO , TM ) ; if ( GOKind . isText ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( cast < const Function > ( GO ) , TM ) ) -> getQualNameSymbol ( ) ; } else if ( GOKind . isCommon ( ) || GOKind . isBSSLocal ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GO , GOKind , TM )


<s> } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } } } if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) ) ) { int ShiftAmt = matchShuffleAsShift ( ShuffleVT , Shuffle , MaskScalarSizeInBits , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( <NUM_LIT> < ShiftAmt ) { PermuteImm = (


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return false ; auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg


<s> unsigned Opc , ZReg ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RetVT = <STR_LIT> ; Opc = <STR_LIT> ; ZReg = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ZReg = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; return fastEmitInst_rrr ( Opc , RC , Op0 ,


<s> return <NUM_LIT> - MI . getOperand ( Op ) .


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } else { unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAllActivePredicate ( SDValue N ) { const <ISA_LIT>TargetLowering * TLI = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; return TLI -> isAllActivePredicate (


<s> int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( - Value ) != -


<s> void addCallTargetOperands ( MCInst & Inst , unsigned N )


<s> OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective ( Symbol , true ) ; for ( auto & Symbol : DLLExportedFns ) GenerateExportDirective ( Symbol , false ) ; } } if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parsePKHImm ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Op , int Low , int High ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , Op + <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef ShiftName = Tok . getString ( ) ; std :: string LowerOp = Op . lower ( ) ; std :: string UpperOp = Op . upper ( ) ; if ( ShiftName != LowerOp && ShiftName != UpperOp ) { Error ( Parser . getTok ( ) . getLoc ( ) , Op + <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex


<s> if ( regno1 != LR_REGNUM && ( live_regs & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) regno = LR_REGNUM ; else { unsigned int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( regno1 != i && ( live_regs & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) { regno = i ; break ; } if ( regno < <NUM_LIT> ) { if ( regno1 == IP_REGNUM && IS_NESTED ( arm_current_func_type


<s> assert ( getStreamer ( ) . Contents . empty ( ) && <STR_LIT> ) ; CurrentVendor = Vendor


<s> Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return


<s> if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == <STR_LIT> ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false ,

& is<ISA_LIT>Area1Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ;


<s> static void EmitIndirectGuardJmp ( const MCSubtargetInfo & STI , int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT>


<s> static __inline unsigned long long sh_media_MSHFLO_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MSHFLO_W ( ( v4hi )


<s> Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode =


<s> static const int8_t NoopsInSledCount = <NUM_LIT> ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol


<s> assert ( ( Opc == TargetOpcode :: G_STORE || Opc == TargetOpcode :: G_LOAD ) && <STR_LIT> ) ; const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; auto & MemOp = * * I . memoperands_begin ( ) ; if ( MemOp . getOrdering ( ) != AtomicOrdering :: NotAtomic ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else


<s> for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( Opcode != <NUM_LIT> ) { SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue New = DAG . getNode ( Opcode , dl , VTs , & Ops [ <NUM_LIT> ] , NumOperands ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , Op . getValueType (


<s> switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , true , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> ,


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return AsmPrinter :: GetCPISymbol ( CPID


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) ) setOperationAction ( <STR_LIT> ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY )

, ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName


<s> break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , const Instruction * I ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT>


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; }


<s> std :: unique_ptr < DCInstruction > <ISA_LIT>DCTranslator :: createDCInstruction ( DCBasicBlock


<s> if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; switch ( idx ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case


<s> void <ISA_LIT>InstructionSelector :: renderVFPF64Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) ->


<s> auto FindDef = [ & ] ( Register VReg ) { MachineInstr * Def = MRI . getVRegDef ( VReg ) ; while ( Def ) { if ( Def -> getOpcode ( ) != TargetOpcode :: COPY ) break ; if ( TargetRegisterInfo :: isPhysicalRegister ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; Def = MRI . getVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } return Def ; } ; auto IsCMN = [ & ] ( MachineInstr * DefMI , const <STR_LIT> & CC ) { if ( ! DefMI || DefMI -> getOpcode ( ) != TargetOpcode :: G_SUB ) return false ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return false ; if ( DefMI -> getOpcode ( ) != TargetOpcode :: G_SUB ) return false ; auto ValAndVReg = getConstantVRegValWithLookThrough ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> ) return false ; return true ; } ; MachineInstr * LHSDef = FindDef ( LHS . getReg ( ) ) ; MachineInstr * RHSDef = FindDef ( RHS . getReg ( ) ) ; CmpInst :: Predicate P = ( CmpInst :: Predicate


<s> target_flags |= MASK_EXPLICIT_RELOCS ; targetm . min_anchor_offset = <NUM_LIT> ; targetm . max_anchor_offset = <NUM_LIT> ; targetm . const_anchor = <NUM_LIT> ; target_flags &= ~ MASK_RELAX_PIC_CALLS ; target_flags &= ~ MASK_FIX_R4000 ; if ( flag_pic && ! TARGET_OLDABI ) sorry ( <STR_LIT> ) ; if ( TARGET_XGOT ) sorry ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT_ABI && ! TARGET_OLDABI ) sorry ( <STR_LIT> ) ; } else { if ( TARGET_MICROMIPS ) target_flags &= ~ MASK_BRANCHLIKELY ; if ( TARGET_64BIT ) { if ( align_loops == <NUM_LIT> ) align_loops = <NUM_LIT> ; if ( align_jumps == <NUM_LIT> ) align_jumps = <NUM_LIT> ; if ( align_functions == <NUM_LIT> ) align_functions = <NUM_LIT> ; } targetm . min_anchor_offset = - <NUM_LIT>


<s> } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore ,


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes -


<s> void <ISA_LIT>MCExpr :: AddValueSymbols ( MCAssembler * Asm ) const { AddValueSymbols_ ( getSubExpr ( )


<s> static bool jumpTableFollowsTB ( MachineInstr * JTMI , MachineInstr * CPEMI ) { MachineFunction :: iterator MBB = JTMI -> getParent ( ) -> getIterator ( ) ; MachineFunction * MF = MBB -> getParent (


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return true


<s> return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_<ISA_LIT>64_R2_Altivec_SaveList : CSR_<ISA_LIT>64_Altivec_SaveList ; return SaveR2 ? CSR_<ISA_LIT>64_R2_SaveList : CSR_<ISA_LIT>64_SaveList ; } if ( Subtarget . isAIXABI ( ) ) return CSR_AIX32_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_SVR432_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; return CSR_SVR432_SaveList


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O <<


<s> emitRX ( <STR_LIT> , TmpReg , HiOperand , IDLoc , STI ) ; if ( BaseReg != <STR_LIT> ) emitRRR ( <STR_LIT> , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; emitRRX ( Opcode , DstReg , TmpReg ,


<s> bool isRegList16 ( ) const { if ( ! isRegList ( ) ) return false ; int Size = RegList . List -> size ( ) ; if ( Size < <NUM_LIT> || Size > <NUM_LIT> || * RegList . List -> begin ( ) != <STR_LIT> || RegList . List -> back ( ) != <STR_LIT> ) return false ; int PrevReg = * RegList . List -> begin ( ) ; for ( int i = <NUM_LIT> ; i < Size - <NUM_LIT> ; i ++ ) { int Reg = ( * ( RegList . List ) ) [ i ] ; if ( Reg != PrevReg + <NUM_LIT> ) return false ; PrevReg = Reg


<s> static DecodeStatus DecodeLogicalImmOperand ( llvm :: MCInst & Inst , unsigned Bits , uint64_t Address , const void * Decoder ) { uint64_t Imm


<s> DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg


<s> static bool ix86_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '*' || code == '+' || code == '&' || code == ';' || code == '~' || code


<s> if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT>


<s> bool isLiveIn ( int FI ) { for ( unsigned i = <NUM_LIT> , e = LiveInFI . size ( ) ; i < e ; ++ i ) if ( FI == LiveInFI [ i ] ) return true ; return false


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT>


<s> if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; if ( imm != INT32_MIN ) imm *= (


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG (


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs * Scale ; O <<


<s> if ( ! UseUnscaled ) { int64_t Offset = Addr . getOffset ( ) ; if ( Offset & ( ScaleFactor - <NUM_LIT> ) ) return EmitStore ( VT , SrcReg , Addr , true ) ; Addr . setOffset ( Offset / ScaleFactor ) ; } if ( ! SimplifyAddress ( Addr , VT , UseUnscaled ? <NUM_LIT> : ScaleFactor , UseUnscaled ) ) return false ; if ( VTIsi1 ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; unsigned ANDReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ANDReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ) ; SrcReg = ANDReg ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( StrOpc ) ) . addReg


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF


<s> const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return static_cast < uint64_t > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) { unsigned ByteOffs = Fixups . size ( ) == <NUM_LIT> ? <NUM_LIT> :


<s> MCSymbol * FnSym = Ctx . GetOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: Create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> )


<s> LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ,

DAG . getConstant ( FPCondCCodeToFCC ( CC ) , <STR_LIT> ) ) ;


<s> <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) -> getCallingConv (

) ) ) return LowerWin64_VASTART ( Op , DAG ) ;


<s> const uint32_t * RegMask = Subtarget . is64Bit ( ) ? Subtarget . getRegisterInfo ( ) -> getDarwinTLSCallPreservedMask ( ) : Subtarget . getRegisterInfo ( ) -> getCallPreservedMask ( * F , CallingConv :: C ) ; if ( Subtarget . is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI ,


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> return Subtarget -> isTargetDarwin ( ) ? LowerGlobalAddressDarwin ( Op , DAG ) : LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP (


<s> return ( __m128d ) __builtin_ia32_minsd ( ( __v2df


<s> } Defs . clear ( ) ; Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = llvm :: getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) ; void EmitInstrWithMacroNoAT ( const MachineInstr * MI ) ; private : bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI ,


<s> case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) &&


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites ->

push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ;


<s> fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; return _URC_NO_REASON ; } return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( ( context -> rp & - <NUM_LIT> ) - context -> region_start ) / <NUM_LIT> * <NUM_LIT> + ( context -> rp & <NUM_LIT> ) ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw + length + <NUM_LIT> ; } insn = ( unsigned char * ) ( unw + <NUM_LIT> ) ; insn_end = ( unsigned char * ) ( unw + <NUM_LIT> + length ) ; while ( ! fs -> done && insn < insn_end ) insn = unw_decode ( insn , fs -> in_body , fs ) ; free_label_states ( fs -> labeled_states ) ; free_state_stack ( & fs ->


<s> enum calling_abi abi = ix86_abi ; if ( abi == SYSV_ABI ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { if ( TARGET_X32 ) { static bool warned = false ; if ( ! warned ) { error ( <STR_LIT> ) ; warned = true ; } } abi = MS_ABI


<s> MachineOperand & Base = getBaseOperand ( MI ) ; MachineOperand & Disp = getDispOperand ( MI ) ; MachineOperand & Scale = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Index = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Segment = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( ! ( ( Base . isReg ( ) && Base . getReg ( ) != <STR_LIT>


<s> const TargetLowering * TLI = TM . getTargetLowering ( ) ; O << * static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ->


<s> case E_V8QImode : emit_insn ( gen_loongson_vec_init1_v8qi ( t1 , elt ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_vec_init1_v4hi ( t1 , elt ) ) ; break ; default : gcc_unreachable ( ) ; } memset ( & d , <NUM_LIT> , sizeof ( d ) ) ; d . target = target ; d . op0 =


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr ,


<s> if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; if ( FP_REG_RTX_P ( dest ) && mips_const_vector_same_int_p ( src , GET_MODE ( src ) , - <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( FP_REG_RTX_P ( dest ) && src == CONST0_RTX


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( const Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , ( const Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol (

<STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemArgument ( SDValue Chain , CallingConv :: ID CallConv , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , const CCValAssign & VA , MachineFrameInfo * MFI , unsigned i ) const { <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = FuncIsMadeTailCallSafe ( CallConv ) ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , isImmutable ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; return DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) ,


<s> return ( uint8x8_t ) __builtin_neon_vqrshrun_nv8hi ( __a ,


<s> bool shouldExpandReduction ( const IntrinsicInst * II ) const { switch ( II -> getIntrinsicID ( ) ) { case


<s> DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; OS << V . getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OS << '+' << MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ]


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ; return Changed


<s> getBDXAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> )


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB .


<s> const_tree fntype , fndecl ; unsigned int ccvt ; regno = CX_REG ; if ( TREE_CODE ( fndecl_or_type ) == FUNCTION_DECL ) { fntype = TREE_TYPE ( fndecl_or_type ) ; fndecl = fndecl_or_type ; } else { fntype = fndecl_or_type ; fndecl = NULL ; } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == <NUM_LIT> ) { if (


<s> ElementCount ResEC = VT . getVectorElementCount ( ) ; if ( InVT . getVectorElementCount ( ) . Min != ( ResEC . Min * <NUM_LIT> ) ) return ; auto * CIndex = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CIndex ) return ; unsigned Index = CIndex -> getZExtValue ( ) ; if ( ( Index != <NUM_LIT> ) && ( Index != ResEC . Min ) ) return ; unsigned Opcode = ( Index == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT ExtendedHalfVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; SDValue Half = DAG . getNode ( Opcode , DL , ExtendedHalfVT ,


<s> sorry ( <STR_LIT> <STR_LIT> ) ; return ; } if ( morestack_ref == NULL_RTX ) { morestack_ref = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( morestack_ref ) |= ( SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_FUNCTION ) ; } r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; r1 = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_load_split_stack_limit ( r0 ) ) ; alloc_hi = ( - allocate + <NUM_LIT> ) & ~ <NUM_LIT> ; alloc_lo = - allocate - alloc_hi ; if ( alloc_hi != <NUM_LIT> ) { emit_insn ( gen_add3_const ( r12 , r1 , alloc_hi ) ) ; if ( alloc_lo != <NUM_LIT> ) emit_insn ( gen_add3_const ( r12 , r12 , alloc_lo ) ) ; else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( insn ) = ok_label ; add_reg_br_prob_note ( insn , profile_probability :: very_likely ( ) ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( r0 , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_frame_store ( r0 , r1 , info -> lr_save_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_call_insn ( gen_call ( gen_rtx_MEM ( SImode , morestack_ref ) , const0_rtx , const0_rtx ) ) ; call_fusage = NULL_RTX ; use_reg ( & call_fusage , r12 ) ; use_reg ( & call_fusage , r0 ) ; add_function_usage_to ( insn