<s> output_asm_insn ( <STR_LIT> , xoperands ) ; } output_asm_insn ( <STR_LIT> , xoperands ) ; } } if ( seq_length == <NUM_LIT> ) output_asm_insn ( <STR_LIT> , xoperands ) ; if ( seq_length == <NUM_LIT> || GET_CODE ( NEXT_INSN ( insn ) ) != JUMP_INSN ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = XEXP ( PATTERN ( NEXT_INSN ( insn ) ) , <NUM_LIT> ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { seq_insn = NEXT_INSN ( PREV_INSN ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ; distance = ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( NEXT_INSN ( insn ) ) ) ) - INSN_ADDRESSES ( INSN_UID ( seq_insn ) ) - <NUM_LIT> ) ; if ( VAL_14_BITS_P ( distance ) ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; } else output_asm_insn ( <STR_LIT> , xoperands ) ; } else output_asm_insn ( <STR_LIT> , xoperands


<s> for ( int i = HalfSize ; i < NumElems ; ++ i ) { int Elt = SVOp -> getMaskElt ( i ) ; if ( SVOp -> getMaskElt ( i ) < <NUM_LIT> ) continue ; SndVecOpNum = Elt / NumElems ; SndVecExtractIdx = Elt % NumElems < HalfSize ? <NUM_LIT> : HalfSize ; break ; } SDValue V1 = Extract128BitVector ( SVOp -> getOperand ( FstVecOpNum ) , DAG . getConstant ( FstVecExtractIdx , <STR_LIT> ) , DAG , dl ) ; SDValue V2 = Extract128BitVector ( SVOp -> getOperand ( SndVecOpNum ) , DAG . getConstant ( SndVecExtractIdx , <STR_LIT> ) , DAG , dl ) ; SmallVector < int , <NUM_LIT> > MaskV1 , MaskV2 ; for ( int i = <NUM_LIT> ; i < HalfSize ; ++ i ) { int Elt = SVOp -> getMaskElt ( i ) ; MaskV1 . push_back ( Elt < <NUM_LIT> ? Elt : Elt % HalfSize ) ; } for ( int i = HalfSize ; i <


<s> return <NUM_LIT> ; case PROCESSOR_V9 : return <NUM_LIT> ; case PROCESSOR_SUPERSPARC : return


<s> static void nds32_emit_load_store ( rtx reg , rtx mem , enum machine_mode mode , int offset , bool load_p ) { rtx new_mem ; new_mem = adjust_address ( mem , mode , offset ) ; if ( load_p ) emit_move_insn ( reg , new_mem ) ; else emit_move_insn ( new_mem , reg


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo


<s> MCSymbol * <ISA_LIT>64_MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI


<s> if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( )

, GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> case 'h' : case 's' : case 'd' : case 'q' : break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MI -> getOperand ( OpNum )


<s> } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == <NUM_LIT>


<s> if ( RM == Reloc :: Default || RM == Reloc :: DynamicNoPIC ) { RM = Reloc :: Static ; } if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return


<s> HasELFModifier = true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_PAGE_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case (


<s> unsigned <ISA_LIT>FastISel :: MaterializeGV ( const GlobalValue * GV , MVT VT ) { if ( VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal (


<s> continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else


<s> <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSWindows (


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , unsigned OpNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { O << MO . getImm ( ) ; break ; } case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; break ; } case MachineOperand :: MO_BlockAddress


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize (


<s> if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return SDValue (


<s> APInt Val = SplatValue . extractBits ( ScalarSize , ScalarSize * i ) ; Constant * Const ; if ( VT . isFloatingPoint ( ) ) { if ( ScalarSize == <NUM_LIT> ) { Const = ConstantFP :: get ( C , APFloat ( APFloat :: IEEEsingle ( ) , Val ) ) ; } else { assert ( ScalarSize == <NUM_LIT> && <STR_LIT> ) ; Const = ConstantFP :: get ( C , APFloat ( APFloat :: IEEEdouble ( ) , Val ) ) ; } } else Const = Constant :: getIntegerValue ( Type :: getIntNTy ( C , ScalarSize ) , Val ) ; ConstantVec . push_back (


<s> assert ( ! TRI -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = TRI -> getStackRegister (


<s> int hi_val = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( const_vec , i ) ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) ; for ( int j = <NUM_LIT> ; j < repeat ; j ++ ) hi_val |= elpart << ( i * repeat + j ) ; } return gen_int_mode ( hi_val


<s> toc_initialized = <NUM_LIT> ; } fprintf ( asm_out_file , <STR_LIT> , (


<s> HasShuffleIntoBitcast = true ; } if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , VT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return


<s> void EmitBytes ( StringRef Data ) override { EmitDataMappingSymbol (


<s> V16QImode , V8QImode , V4HImode , V2SImode } ; unsigned int sve_i = TARGET_SVE ? <NUM_LIT> : ARRAY_SIZE ( sve_modes ) ; unsigned int advsimd_i = <NUM_LIT> ; while ( advsimd_i < ARRAY_SIZE ( advsimd_modes ) ) { if ( sve_i < ARRAY_SIZE ( sve_modes ) && maybe_gt ( GET_MODE_NUNITS ( sve_modes [ sve_i ] ) , GET_MODE_NUNITS ( advsimd_modes [ advsimd_i ] ) ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; else modes -> safe_push ( advsimd_modes [ advsimd_i ++ ] ) ; } while ( sve_i < ARRAY_SIZE ( sve_modes ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; unsigned int flags


<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N )


<s> static MCDisassembler * createThumbDisassembler ( const Target & T


<s> int Addend ; switch ( getMnemonicFromOpcode ( MI . getOpcode ( ) ) ) { case FlagArithMnemonic :: ADC : case FlagArithMnemonic :: ADCX : case FlagArithMnemonic :: RCL : case FlagArithMnemonic :: RCR : case FlagArithMnemonic :: SBB : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; case FlagArithMnemonic :: ADOX : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; } unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; DEBUG ( dbgs ( ) << <STR_LIT> ; AddI ->


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( LHS ) && ! DAG . isConstantIntBuildVectorOrConstantInt ( RHS ) ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , RHS , LHS ) ; if ( <STR_LIT> ( RHS . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnes ( <NUM_LIT> ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LHS . hasOneUse ( ) && ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N ) ; LHS = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; LHS = DAG . getBitcast ( <STR_LIT> , LHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , LHS , RHS ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && RHS . hasOneUse ( ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N )


<s> CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C > <NUM_LIT> && isLegalCmpImmediate ( C - <NUM_LIT> , isThumb1Only ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalCmpImmediate ( C + <NUM_LIT> , isThumb1Only ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C < <NUM_LIT> && isLegalCmpImmediate ( C + <NUM_LIT> , isThumb1Only ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; } <ISA_LIT>CC = DAG . getConstant ( CondCode ,


<s> void <ISA_LIT>AsmPrinter :: printPICLabel ( const MachineInstr * MI , unsigned Op , raw_ostream & O ) { PrintPICBaseSymbol ( O ) ; O << '\n'


<s> SDLoc DL ( Regs [ <NUM_LIT> ] ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( CurDAG -> getTargetConstant ( RegClassIDs [ Regs . size ( ) - <NUM_LIT> ] , DL , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Regs . size ( ) ; ++ i ) { Ops . push_back ( Regs [ i


<s> MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . add ( predOps ( <STR_LIT> ) ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) ,


<s> if ( Stride < std :: numeric_limits < int32_t > :: min ( ) || Stride > std :: numeric_limits < int32_t > :: max ( ) ) return Changed ; const auto & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxVScale = Subtarget . getMaxSVEVectorSizeInBits ( ) / <STR_LIT> ; int64_t LastElementOffset = IndexVT . getVectorMinNumElements ( ) * Stride * MaxVScale ; if ( LastElementOffset < std :: numeric_limits < int32_t > :: min ( ) || LastElementOffset > std :: numeric_limits < int32_t > :: max ( ) ) return Changed ; EVT NewIndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NewIndexVT , DAG . getTargetConstant (


<s> if ( Lane != <NUM_LIT> ) return false ; auto * InsMI = getOpcodeDef ( TargetOpcode :: G_INSERT_VECTOR_ELT , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! InsMI ) return false ; if ( ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return false ; int64_t Index = <NUM_LIT> ; if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Index ) ) || Index ) return false ; MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , { InsMI ->

getOperand ( <NUM_LIT> ) . getReg ( ) } ) ;


<s> if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC , is64BitReg ? <STR_LIT> : <STR_LIT> ) ; CC = matchFPURegisterName (


<s> bool <ISA_LIT>DAGToDAGISel :: canUseBlockOperation ( StoreSDNode * Store , LoadSDNode * Load ) const { if ( Load -> getMemoryVT ( ) != Store -> getMemoryVT ( ) ) return false ; if ( Load -> isVolatile ( ) || Store -> isVolatile ( ) ) return false ; if ( Load -> isInvariant ( ) ) return true ; const Value * V1 = Load -> getSrcValue ( ) ; const Value * V2 = Store -> getSrcValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( ) + Size ; if ( V1 == V2 && End1 == End2 ) return false ; return ! AA -> alias ( AliasAnalysis :: Location ( V1 , End1 , Load -> getTBAAInfo ( ) ) , AliasAnalysis :: Location ( V2


<s> bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO , RegState :: Kill ) .

addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ;


<s> AllowHashAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; DotIsPC = ( AssemblerDialect == AD_ATT ) ; StarIsPC = ( AssemblerDialect == AD_HLASM ) ; EmitGNUAsmStartIndentationMarker = ( AssemblerDialect == AD_ATT ) ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> :


<s> rtx_jump_table_data * tmp ; int new_cost ; gcc_assert ( ! BARRIER_P ( from ) ) ; if ( LABEL_P ( from ) ) count += get_label_padding ( from ) ; else count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & tmp ) ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) =


<s> ( * lang_hooks . types . register_builtin_type ) ( intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node ,


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> void emitByte ( uint8_t C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ; ++ CurByte


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { unsigned TempReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; DestReg = TempReg


<s> unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; if ( MO . isUse ( ) ) LocalUses . push_back ( Reg ) ; else LocalDefs . push_back ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalUses . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalUses [ i ] ; for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) Uses . insert ( * Subreg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalDefs . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalDefs [ i ] ; for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) Defs . insert ( * Subreg ) ; if ( Reg == <STR_LIT> )


<s> APInt ShiftAmt ; if ( ! <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) , ShiftAmt ) || ShiftAmt != <NUM_LIT> ) return SDValue ( ) ; SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = LHS . getOpcode ( ) ; if ( ( ExtOpc != <STR_LIT> && ExtOpc != <STR_LIT> ) || RHS . getOpcode ( ) != ExtOpc ) return SDValue ( ) ; LHS = LHS . getOperand ( <NUM_LIT> ) ; RHS = RHS . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT || RHS . getValueType ( ) != VT ) return SDValue ( ) ; unsigned Opc = ExtOpc == <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back ( MIB


<s> ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; EVT VT = N0 . getValueType ( ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && N1C && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; APInt Mask = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; APInt ShAmt = N1C -> getAPIntValue ( ) ; Mask = Mask . shl ( ShAmt ) ; bool MaskOK = false ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( N00 . getOpcode ( ) == <STR_LIT> && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) .


<s> unsigned getOffsetOf ( MachineBasicBlock * MBB ) const


<s> __builtin_mve_vstrbq_sv8hi ( ( __builtin_neon_qi *


<s> bool <ISA_LIT>TargetLowering :: CallRequiresGOTPtrInReg ( bool


<s> const APInt * CV = & C -> getAPIntValue ( ) ; return CV -> isPowerOf2 ( ) ? CV


<s> MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset ,


<s> return V -> getType ( ) -> getScalarSizeInBits ( )


<s> break ; } switch ( fcode ) { case SPE_BUILTIN_EVSPLATFI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplatfi , arglist , target ) ; case SPE_BUILTIN_EVSPLATI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplati , arglist , target ) ; default : break ; } d = ( struct builtin_description * ) bdesc_2arg_spe ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_2arg_spe ) ; ++ i , ++ d ) if ( d -> code == fcode ) return rs6000_expand_binop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_spe_predicates ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_predicates ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_predicate_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_spe_evsel ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_evsel ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_evsel_builtin ( d -> icode , arglist , target ) ; switch ( fcode ) { case SPE_BUILTIN_EVSTDDX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstddx , arglist ) ; case SPE_BUILTIN_EVSTDHX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdhx , arglist ) ; case SPE_BUILTIN_EVSTDWX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdwx , arglist ) ; case SPE_BUILTIN_EVSTWHEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhex , arglist ) ; case SPE_BUILTIN_EVSTWHOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhox , arglist ) ; case SPE_BUILTIN_EVSTWWEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwex , arglist ) ; case SPE_BUILTIN_EVSTWWOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwox , arglist ) ; case


<s> code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_GENERAL ; return add_builtin_function ( name , type , code , BUILT_IN_MD , NULL ,


<s> OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) , STI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; OutStreamer -> emitInstruction ( TmpInst , STI ) ; }


<s> __builtin_ia32_pmovwb256mem_mask ( ( __v16qi * ) __P , ( __v16hi )


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand ::


<s> unsigned <ISA_LIT>ABIInfo :: GetGlobalPtr ( ) const { return ArePtrs64bit ( ) ? <STR_LIT>


<s> } else if ( frame_off != <NUM_LIT> || REGNO ( frame_reg_rtx ) != <NUM_LIT> ) { rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( frame_off == <NUM_LIT> ) emit_move_insn ( r12 , frame_reg_rtx ) ; else emit_insn ( gen_add3_insn ( r12 , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; } if ( info -> push_p ) { rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx r29 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx cr7 = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; rtx not_more =


<s> std :: list < std :: string > * getStrList ( ) const { return const_cast < std :: list < std :: string > * > (


<s> } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize )

<= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ;


<s> assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; StackOffset DeallocateBefore = { } , DeallocateAfter = SVEStackSize ; MachineBasicBlock :: iterator RestoreBegin = LastPopI , RestoreEnd = LastPopI ; if ( int64_t CalleeSavedSize = AFI -> getSVECalleeSavedStackSize ( ) ) { RestoreBegin = std :: prev ( RestoreEnd ) ; ; while ( IsSVECalleeSave ( RestoreBegin ) && RestoreBegin != MBB . begin ( ) ) -- RestoreBegin ; ++ RestoreBegin ; assert ( IsSVECalleeSave ( RestoreBegin ) && IsSVECalleeSave ( std :: prev ( RestoreEnd ) ) && <STR_LIT> ) ; StackOffset CalleeSavedSizeAsOffset = { CalleeSavedSize , <STR_LIT> } ; DeallocateBefore = SVEStackSize - CalleeSavedSizeAsOffset ; DeallocateAfter = CalleeSavedSizeAsOffset ; } if ( SVEStackSize ) { if ( AFI -> isStackRealigned ( ) ) { if ( int64_t CalleeSavedSize = AFI -> getSVECalleeSavedStackSize ( ) ) emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , { - CalleeSavedSize , <STR_LIT> } , TII , MachineInstr :: FrameDestroy ) ; } else { if ( AFI -> getSVECalleeSavedStackSize ( ) ) { emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , { NumBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy ) ; NumBytes = <NUM_LIT> ; } emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , DeallocateBefore , TII , MachineInstr :: FrameDestroy ) ; emitFrameOffset ( MBB , RestoreEnd , DL , <STR_LIT> , <STR_LIT> , DeallocateAfter , TII , MachineInstr :: FrameDestroy ) ; } } if ( ! hasFP ( MF ) ) { bool RedZone = canUseRedZone ( MF ) ; if ( RedZone && AfterCSRPopSize == <NUM_LIT> ) return ; bool NoCalleeSaveRestore = PrologueSaveSize == <NUM_LIT> ; int64_t StackRestoreBytes = RedZone ? <NUM_LIT> : NumBytes ; if ( NoCalleeSaveRestore ) StackRestoreBytes += AfterCSRPopSize ; bool Done = NoCalleeSaveRestore || AfterCSRPopSize == <NUM_LIT> ; if ( Done ) adaptForLdStOpt ( MBB , MBB . getFirstTerminator ( ) , LastPopI ) ; emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , { StackRestoreBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ; if ( Done ) { if ( NeedsWinCFI ) { HasWinCFI = true ; BuildMI ( MBB , MBB . getFirstTerminator ( ) , DL , TII -> get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return ; } NumBytes = <NUM_LIT> ; } if ( ! IsFunclet && ( MFI . hasVarSizedObjects ( ) || AFI -> isStackRealigned ( ) ) ) { int64_t OffsetToFrameRecord = isTargetDarwin ( MF ) ? ( - ( int64_t ) AFI -> getCalleeSavedStackSize ( ) + <NUM_LIT> ) : <NUM_LIT> ; emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , { OffsetToFrameRecord , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI ) ; } else if ( NumBytes ) emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , {

NumBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI ) ;


<s> } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; bool IsPICCall = ( Subtarget . isABI_N64 ( ) || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false , IsCallReloc = false ; SDValue CalleeLo ; EVT Ty = Callee . getValueType ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { const GlobalValue * Val = G -> getGlobal ( ) ; InternalLinkage = Val -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( G , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ; else if ( LargeGOT ) { Callee = getAddrGlobalLargeGOT ( G , Ty , DAG , <STR_LIT> , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Val ) ) ; IsCallReloc = true ; } else { Callee = getAddrGlobal ( G , Ty , DAG , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Val ) ) ; IsCallReloc = true ; } } else Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( ) , <NUM_LIT> , <STR_LIT> ) ; GlobalOrExternal = true ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * Sym = S -> getSymbol ( ) ; if ( ! Subtarget . isABI_N64 ( ) && ! IsPIC ) Callee = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , <STR_LIT> ) ; else if ( LargeGOT ) { Callee = getAddrGlobalLargeGOT ( S , Ty , DAG , <STR_LIT> , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Sym ) ) ; IsCallReloc = true


<s> static void mips_multi_add_label ( const char * label ) { struct mips_multi_member * member ; member = mips_multi_add ( ) ; member -> is_label_p = true ; member -> format


<s> else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT>


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LastFiller = MBB . instr_end ( ) ; for ( InstrIter I = MBB . instr_begin ( ) ; I != MBB . instr_end ( ) ; ++ I ) if ( I -> hasDelaySlot ( ) ) { ++ FilledSlots ; Changed = true ; InstrIter D ; if ( EnableDelaySlotFiller && findDelayInstr ( MBB , I , D ) ) { MBB . splice ( llvm :: next ( I ) , & MBB , D ) ; ++ UsefulSlots ; } else BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LastFiller = ++


<s> MachineInstr & MI = * I ; int Opcode = MI . getOpcode ( ) ; if ( ! isLEA ( Opcode ) ) return false ; if ( isLEASimpleIncOrDec ( MI ) && TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) { int NewOpcode ; bool isINC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; switch ( Opcode ) { case <STR_LIT> : NewOpcode = isINC ? <STR_LIT> : <STR_LIT> ; break ; case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> )


<s> switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl ,


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) ,


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode ,


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> void loongarch_emit_binary ( enum rtx_code code , rtx target , rtx op0


<s> MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest


<s> int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex = RegNodeEscapeIndex ; calculateWinCXXEHStateNumbers ( & F , FuncInfo


<s> rtl_opt_pass * make_pass_constant_pool_broadcast ( gcc :: context * ctxt ) { return new pass_constant_pool_broadcast ( ctxt


<s> int <ISA_LIT>TTIImpl :: getVectorInstrCost ( unsigned Opcode , Type * Val , unsigned Index ) { assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; if ( ST -> hasVSX ( ) && Val ->


<s> auto & MRI = * MIB . getMRI ( ) ; LLT OpTy = MRI . getType ( LHS ) ; assert ( OpTy . getSizeInBits ( ) == <NUM_LIT> || OpTy . getSizeInBits ( ) == <NUM_LIT> ) ; unsigned CCmpOpc ; if ( CmpInst :: isIntPredicate ( CC ) ) { CCmpOpc = OpTy . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { switch ( OpTy . getSizeInBits ( ) ) { case <NUM_LIT> : CCmpOpc =


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot =


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA )


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( Subtarget -> is32BitELFABI ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue =


<s> else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) =


<s> const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> Cond = Cond -> getOperand ( <NUM_LIT> ) ; } isAnd = false ; SDValue SetCC0 , SetCC1 ; switch ( Cond -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : isAnd = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : SetCC0 = Cond -> getOperand ( <NUM_LIT> ) ; SetCC1 = Cond -> getOperand ( <NUM_LIT> ) ; break ; } ; if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1 -> getConstantOperandVal ( <NUM_LIT>


<s> switch ( CallConv ) { case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , IsVarArg ,


<s> Inst . addOperand ( MCOperand :: CreateReg ( Register + <NUM_LIT> ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler ::


<s> else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary


, subreg_lowpart_offset ( QImode , DImode ) ) ;


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; int CondNo = getCondSrcNoFromDesc ( MCID ) ; if ( CondNo < <NUM_LIT> ) return <STR_LIT> ; CondNo += MCID . getNumDefs ( ) ; return static_cast < <STR_LIT> > ( MI . getOperand ( CondNo ) . getImm (


<s> return ( __m128i ) __builtin_ia32_pabsd128_mask ( ( __v4si ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8


<s> gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return


<s> return parseRegister ( Operands , CR64Reg


<s> if ( Flags . isSExt ( ) ) ArgVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal , DAG . getValueType ( ObjectVT ) ) ; else if ( Flags . isZExt ( ) ) ArgVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal ,


<s> static bool HasNestArgument ( const MachineFunction * MF ) { const Function & F = MF -> getFunction ( ) ; for ( Function :: const_arg_iterator I = F . arg_begin ( ) , E = F . arg_end ( ) ; I != E ; I ++ ) { if ( I -> hasNestAttr ( ) && ! I -> use_empty ( )


<s> bool isSelectSupported ( SelectSupportKind Kind ) const override { return ( Kind != ScalarCondVectorVal


<s> void <ISA_LIT>SEFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize (


<s> case RecurrenceDescriptor :: RK_IntegerAnd : case RecurrenceDescriptor :: RK_IntegerOr : case RecurrenceDescriptor :: RK_IntegerXor : case RecurrenceDescriptor :: RK_FloatAdd : return true ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( )


<s> if ( Subtarget -> isCallingConvWin64 ( CallConv ) ) { return None ; } const Function * Fn = MF . getFunction ( ) ; bool NoImplicitFloatOps = Fn -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; assert ( ! ( MF . getTarget ( ) . Options . UseSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( MF . getTarget ( ) . Options . UseSoftFloat || NoImplicitFloatOps || ! Subtarget -> hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> static bool isVectorPredicate ( MachineInstr


<s> if ( ST -> hasNEON ( ) && Src -> isVectorTy ( ) && ( Alignment && * Alignment != Align ( <NUM_LIT> ) ) && cast < VectorType > ( Src ) -> getElementType ( ) -> isDoubleTy ( ) ) { return LT . first


<s> vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; int cnt ; vec_uchar16 mask ; x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = ( <NUM_LIT> - x . i [ <NUM_LIT> ] ) << <NUM_LIT> ; x . v = vec_splat ( x . v , <NUM_LIT> ) ; mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_sro ( ( vec_uchar16 ) ( a ) , x . v ) , mask


<s> const GlobalValue * getGlobalValue ( ) { return


<s> getTargetStreamer ( ) . EmitARM64WinCFIContext ( ) ; return false


<s> bool hasThumb2DSP ( ) const { return STI . getFeatureBits (


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups , STI ) ; uint32_t Binary = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT> ) ; return


<s> return std :: make_unique < <ISA_LIT>MachObjectWriter > ( CPUType ,


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : if ( Reg == <STR_LIT> ) D8SpillFI = FI ; if ( Reg < <STR_LIT> || Reg >= <STR_LIT> + AFI -> getNumAlignedDPRCS2Regs ( ) ) { AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getNumAlignedDPRCS2Regs ( ) > <NUM_LIT> ) { MBBI = skipAlignedDPRCS2Spills ( MBBI , AFI -> getNumAlignedDPRCS2Regs ( ) ) ; NumBytes += MFI -> getObjectOffset ( D8SpillFI ) ; } else NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr ::


<s> const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) return EmitMOPS ( <STR_LIT> , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; return SDValue (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT>


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; return BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) . addImm (

<NUM_LIT> - Size ) . addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> static tree aarch64_preferred_else_value ( unsigned , tree , unsigned int nops , tree * ops ) { return nops == <NUM_LIT> ? ops [ <NUM_LIT> ] :


<s> return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , Op , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) , <NUM_LIT> , false , true

, false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> const <ISA_LIT>TargetMachine & getTargetMachine (


<s> return ( __m128 ) __builtin_ia32_vfmaddss3_round ( ( __v4sf ) __W , - ( __v4sf ) __A , - (


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg (


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } Warning ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement (


<s> insn -> mode = mode ; insn -> numImmediatesConsumed = <NUM_LIT> ; if ( readPrefixes ( insn ) || readOpcode ( insn ) || getID ( insn ) || insn -> instructionID == <NUM_LIT> || readOperands ( insn ) ) return - <NUM_LIT> ; insn -> length = insn -> readerCursor -


<s> off_t i ; for ( i = <NUM_LIT> ; ; i ++ ) { if ( orig [ i ] == '\0' && equiv [ i ] == '\0' ) return TRUE ; if ( orig [ i ] == '\0' || equiv [ i ] == '\0' ) return FALSE ; if ( orig [ i ] != equiv [ i ] ) { if ( ( orig [ i ] == 'W' || orig [ i ] == 'L' ) && equiv [ i ] == 'Q' ) continue ; if ( ( orig [ i ] == '1' || orig [ i ] == '3' ) && equiv [ i ] == '6' ) continue ; if ( ( orig [ i ] == '6' || orig [ i ] == '2'


<s> Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary ) ; return ; } Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( TID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT>


<s> bool <ISA_LIT>RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( Reg == FramePtr && TFI


<s> case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexA710 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming =


<s> MVT ScalarType ; int ShftAmt = <NUM_LIT> ; switch ( Clamp -> getSExtValue ( ) ) { case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; default : return SDValue ( ) ; } if ( Shft . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * N1 = isConstOrConstSplat ( Shft . getOperand ( <NUM_LIT> ) ) ; if ( ! N1 || N1 -> getSExtValue ( ) != ShftAmt ) return SDValue ( ) ; SDValue Mul = Shft . getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ext0 = Mul . getOperand ( <NUM_LIT> ) ; SDValue Ext1 = Mul . getOperand ( <NUM_LIT> ) ; if ( Ext0 . getOpcode ( ) != <STR_LIT> || Ext1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Mul


<s> case <STR_LIT> : assert ( cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node ) -> getAlignment ( ) && <STR_LIT> ) ; break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; return


<s> HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasADX = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false


<s> bool <ISA_LIT>A57FPLoadBalancing :: runOnBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: vector < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { auto * Ld = cast < LoadSDNode > ( In ) ; if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT>


<s> <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; TD = getDataLayout (


<s> if ( insn_is_load_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_lvx_pattern


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0


<s> case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT>


<s> unsigned Opcode = VA . getLocInfo ( ) == CCValAssign :: ZExtUpper ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( Opcode , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; break ; } } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExtUpper : case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; case CCValAssign :: SExtUpper : case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val , DAG . getValueType ( ValVT ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; case CCValAssign :: ZExtUpper : case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ,


<s> else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) || DEFAULT_ABI == ABI_ELFv2 ) && type && TYPE_ALIGN ( type ) > <NUM_LIT> ) { bool aggregate_p = ( AGGREGATE_TYPE_P ( type ) && ! SCALAR_FLOAT_MODE_P ( elt_mode ) ) ; if ( aggregate_p != ( mode == BLKmode ) ) { static bool warned ; if ( ! warned && warn_psabi ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , ( int

) TYPE_ALIGN ( type ) / BITS_PER_UNIT ) ;


<s> if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; } return ( bool ) ( clock2


<s> unsigned MadeChange = false ; for ( std :: vector < CPEntry > & CPEs : CPEntries ) { for ( CPEntry & CPE : CPEs ) { if ( CPE . RefCount == <NUM_LIT> && CPE . CPEMI ) { removeDeadCPEMI ( CPE . CPEMI ) ; CPE . CPEMI = nullptr ; MadeChange =


<s> return ( ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass

( ) ) ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ;


<s> default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , mips_mdebug_abi_name ( ) ) ; if ( mips_abi == ABI_EABI || mips_abi == ABI_O64 ) fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , TARGET_LONG64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT ) fprintf ( asm_out_file , <STR_LIT> , mips_nan == MIPS_IEEE_754_2008 ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_NO_FLOAT ) fputs ( <STR_LIT> , asm_out_file ) ; ; else if ( ! TARGET_HARD_FLOAT_ABI ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ! TARGET_DOUBLE_FLOAT ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_FLOATXX ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_FLOAT64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_ODD_SPREG ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , mips_arch_info -> name ) ; if ( TARGET_DSPR2 ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_DSP ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_EVA ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_MCU ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_MDMX ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_MIPS3D ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_MT ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_SMARTMIPS ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_VIRT ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_MSA ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_XPA ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_CRC ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_GINV ) fputs ( <STR_LIT> ,


<s> if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount


<s> AddressSpace = <NUM_LIT> ; } return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo


<s> static DecodeStatus DecodeZPR4RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZZZZDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> static bool isLDSTSIMDSPI ( InsnType insn )


<s> break ; default : return SDValue ( ) ; } MVT NarrowTy = N . getSimpleValueType ( ) ; if ( ! NarrowTy . is64BitVector ( ) ) return SDValue ( ) ; MVT ElementTy = NarrowTy . getVectorElementType ( ) ; unsigned NumElems = NarrowTy . getVectorNumElements ( ) ; MVT NewVT = <STR_LIT> ( ElementTy , NumElems * <NUM_LIT> ) ; SDLoc dl ( N ) ; return DAG . getNode ( <STR_LIT> , dl , NarrowTy , DAG . getNode ( N -> getOpcode ( ) , dl , NewVT , N -> ops ( )

) , DAG . getConstant ( NumElems , dl , <STR_LIT> ) ) ;


<s> vld1_dup_p64 ( const poly64_t * __a ) { return ( poly64x1_t ) __builtin_neon_vld1_dupdi ( ( const __builtin_neon_di


<s> bool <ISA_LIT>InstrInfo :: isStridedAccess ( const MachineInstr & MI ) const { return llvm :: any_of ( MI . memoperands ( ) , [


<s> case <STR_LIT> : return expandTrunc ( Inst , true , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUsh ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : return expandUxw ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : return expandRotation ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : return expandRotationImm ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : return expandDRotation ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : return expandDRotationImm ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandAbs ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT>


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( ~ Value ) ; Inst . addOperand ( MCOperand :: createImm ( Value )


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ; return


<s> int SoImmVal ; if ( offset == INT32_MIN ) { Val = <NUM_LIT> ; SoImmVal = <NUM_LIT> ; } else if ( offset < <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; if ( SoImmVal == - <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; } }


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = nullptr ; if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; RHSReg = constrainOperandRegClass ( II , RHSReg , II . getNumDefs ( ) + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( LHSReg , getKillRegState ( LHSIsKill ) ) . addReg ( RHSReg , getKillRegState ( RHSIsKill ) ) . addImm ( getArithExtendImm ( ExtType , ShiftImm ) ) ; return


<s> for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF .


<s> unsigned NewWidth = ( NumElems == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT NewVT ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; } int Scale = NumElems / NewWidth ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i +=


<s> unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) && <STR_LIT> ) ; assert ( MI . definesRegister ( DReg , TRI ) && <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DReg ) .

addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { MadeChange |= convertToCTRLoop ( * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } if ( MadeChange ) return MadeChange ; int Limit = CTRLoopLimit ; if ( Limit >= <NUM_LIT> ) { if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TM -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask


<s> rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= <NUM_LIT> ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / <NUM_LIT> ; if ( ninsns == <NUM_LIT> ) return ; if ( * hilo_delay < <NUM_LIT> && reg_set_p ( lo_reg , pattern ) ) nops = <NUM_LIT> - * hilo_delay ; else if ( * delayed_reg != <NUM_LIT> && reg_referenced_p ( * delayed_reg , pattern ) ) nops = <NUM_LIT> ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < <NUM_LIT> ) nops = <NUM_LIT> ; else nops


<s> return ( __m128d ) __builtin_ia32_unpckhpd128_mask ( ( __v2df ) __A , ( __v2df )


<s> DOP_ENTRY_SD ( ps , inst , ty ) { <STR_LIT> ## _B , { <STR_LIT> ## _B , <STR_LIT>


<s> unsigned RegNum ; StringRef Layout ; SMLoc RegEndLoc , LayoutLoc ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( ! IdentifyRegister ( RegNum , RegEndLoc , Layout , LayoutLoc ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , S , RegEndLoc ) ) ; if ( Layout . size ( ) != <NUM_LIT> ) { unsigned long long TmpLanes = <NUM_LIT> ; llvm :: getAsUnsignedInteger ( Layout . substr ( <NUM_LIT> ) , <NUM_LIT> , TmpLanes ) ; if ( TmpLanes != <NUM_LIT> ) { NumLanes = TmpLanes ; } else { switch ( Layout . back ( )


<s> __v8hu rshift ; __v8hi result ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; rshift = vec_min ( rshift , rshmax ) ; result = vec_sra ( ( __v8hi ) __A , rshift ) ; return ( __m128i


<s> MVT OpVT = <STR_LIT> ( OpSVT , VT . getSizeInBits ( ) / OpSVT . getSizeInBits ( ) ) ; SDValue A = DAG . getBitcast ( OpVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( OpVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( OpVT , N1 . getOperand ( <NUM_LIT> ) ) ; SDValue Imm = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Res = getAVX512Node ( <STR_LIT> , DL , OpVT , { A , B , C , Imm } , DAG , Subtarget ) ; return DAG . getBitcast ( VT , Res ) ; } SDValue X = N -> getOperand ( <NUM_LIT> ) ; SDValue Y = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( VT , N0 . getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( VT , N1 . getOperand ( <NUM_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> static bool arm_cxx_guard_mask_bit ( void ) { return TARGET_AAPCS_BASED


<s> Mask . push_back ( i ) ; for ( unsigned j = <NUM_LIT> ; j != Scale ; j ++ ) Mask . push_back ( IsAnyExtend ?


<s> static bool is_load_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( GET_CODE ( insn ) == CALL_INSN ) return


<s> CPUDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasEFPU2 = false ; HasFPU = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasMMA = false ; HasROPProtect = false ; HasPrivileged = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasQuadwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasStoreFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion = false


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; float FPImm = MO . isDFPImm ( ) ? bit_cast < double > ( MO . getDFPImm ( ) ) : <STR_LIT> ( MO . getImm ( ) ) ; O << format ( <STR_LIT> ,


<s> static void csky_add_gc_roots ( void ) { gcc_obstack_init ( & minipool_obstack ) ; minipool_startobj = ( char * ) obstack_alloc ( & minipool_obstack


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack =


<s> Instr ( unsigned Opcode , unsigned Def , unsigned LHS , unsigned RHS ) : Opcode ( Opcode ) , Def ( Def ) , LHS


<s> return ( __m512 ) __builtin_ia32_rndscaleps_mask ( ( __v16sf ) __A , __imm , ( __v16sf ) _mm512_undefined_ps ( ) ,


<s> targetm . target_option . pragma_parse =


<s> static DecodeStatus DecodeHI32DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> return <ISA_LIT>MaterializeGV ( GV , TLI . getValueType ( GV ->


<s> RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ; unsigned Reg = VA . getLocReg ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , Reg , RetValue , Glue ) ; Glue = Chain . getValue ( <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_pmovwb128_mask ( ( __v8hi ) __A , (

__v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Reg ,


) _mm256_undefined_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget .


<s> MIB . addReg ( DestReg , RegState :: Undef


<s> EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { UpdateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg )


<s> unsigned get<ISA_LIT>BLXTargetOpValue ( const MachineInstr & MI ,


<s> if ( SubRegIdx == <STR_LIT> ) return true ; if ( SubRegIdx == <STR_LIT> ) { const MCInstrDesc & MCID = MII . get ( CurrentInst -> Inst . getOpcode ( ) ) ; if ( ( MCID . TSFlags >> <STR_LIT> ) & <STR_LIT> )


<s> return __builtin_ia32_vtestnzcpd ( ( __v2df ) __M , ( __v2df )


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRotImm ( unsigned Imm , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand >


<s> if ( MBB . getParent ( ) -> getFrameInfo ( ) -> isReturnAddressTaken ( ) && MBB . getParent ( ) -> getRegInfo ( ) . isLiveIn ( Reg ) ) return false ; } MBB . addLiveIn ( Reg


<s> static SDValue PerformADDECombine ( SDNode * N , TargetLowering ::

DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) {


<s> Value * Src = ZExt -> getOperand ( <NUM_LIT> ) ; if ( ZExt -> getSrcTy ( ) == ZExt -> getDestTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ZExt << <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Src ) ; continue ; } if ( NewInsts . count ( Src ) && isa < TruncInst > ( Src ) && Src -> getType ( ) == OrigTy ) { auto * Trunc = cast < TruncInst > ( Src ) ; assert ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) == ExtTy && <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Trunc -> getOperand ( <NUM_LIT> ) ) ; } } for ( auto * I : InstsToRemove


<s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand ::


<s> return ( __m128 ) __builtin_ia32_mulss ( ( __v4sf ) __A , ( __v4sf )


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . padShortFunctions ( ) ) return false ; TSM . init ( & MF . getSubtarget ( ) ) ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( & MF . front ( ) ) ; bool MadeChange = false ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MachineBasicBlock * MBB = I -> first ; unsigned Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugInstr ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange =


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> static bool isCCallConvention ( CallingConv :: ID


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitAdjDynAlloc ( MI ) ; return


<s> auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT>


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectExtractValue ( const Instruction * I ) { const ExtractValueInst * EI = cast < ExtractValueInst > ( I ) ; const Value * Agg = EI -> getAggregateOperand ( ) ; if ( const IntrinsicInst * CI = dyn_cast < IntrinsicInst > ( Agg ) ) { switch ( CI -> getIntrinsicID ( ) ) { default : break


<s> asm_fprintf ( f , <STR_LIT> , STATIC_CHAIN_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , PC_REGNUM , PC_REGNUM ) ; } else { ASM_OUTPUT_ALIGN ( f , <NUM_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT>


<s> return ( __m128i ) __builtin_ia32_extracti64x2_512_mask ( ( __v8di ) __A , __imm , (

__v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( CostKind == TargetTransformInfo :: TCK_CodeSize ) return <NUM_LIT> ; return


<s> rtx neg_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; neg_src = gen_rtx_NEG ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , neg_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } case PLUS : ldop_code = AARCH64_LDOP_PLUS ; break ; case IOR : ldop_code = AARCH64_LDOP_OR ; break ; case XOR : ldop_code = AARCH64_LDOP_XOR ; break ; case AND : { rtx not_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; not_src = gen_rtx_NOT ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , not_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } ldop_code = AARCH64_LDOP_BIC ; break ; default : gcc_unreachable ( ) ; } aarch64_emit_atomic_load_op ( ldop_code , mode , out_data , src , mem , model_rtx ) ; if ( ! out_result ) return ; if ( short_mode ) { src = gen_lowpart ( wmode , src ) ; out_data = gen_lowpart ( wmode , out_data ) ; out_result = gen_lowpart ( wmode , out_result ) ; } x = NULL_RTX ; switch ( code ) { case MINUS : case PLUS : x = gen_rtx_PLUS ( wmode , out_data , src ) ; break ; case IOR : x = gen_rtx_IOR ( wmode , out_data , src ) ; break ; case XOR : x = gen_rtx_XOR ( wmode , out_data , src ) ; break ; case AND : aarch64_emit_bic ( wmode , out_result , out_data , src , <NUM_LIT> ) ; return ; default : gcc_unreachable (


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; } return