<s> const AsmToken & Tok = Parser . getTok ( ) ; <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return true ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ; if ( ! Hash && getLexer ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; if ( Hash ) Parser . Lex ( ) ; SMLoc ExprLoc = getLoc ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; if ( ( MCE -> getValue ( ) & <NUM_LIT> ) != MCE -> getValue ( ) ) return Error ( ExprLoc


<s> unsigned HalfLaneElts = NumLaneElts / <NUM_LIT> ; SDValue A , B ; SmallVector < int , <NUM_LIT> > LMask ( NumElts ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { if ( LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) A = LHS . getOperand ( <NUM_LIT> ) ; if ( LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) B = LHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( LHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , LMask . begin ( ) ) ; } else { if ( LHS . getOpcode ( ) != <STR_LIT> ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) CommuteVectorShuffleMask ( RMask , NumElts ) ; for ( unsigned l = <NUM_LIT> ; l


<s> } if ( isPatchPoint ) { needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI ) { SDValue LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; if ( LDChain . getValueType ( ) == <STR_LIT> ) LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; auto MMOFlags = Subtarget . hasInvariantFunctionDescriptors ( ) ? ( MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) : MachineMemOperand :: MONone ; MachinePointerInfo MPI ( CS ? CS -> getCalledValue ( ) : nullptr ) ; SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddTOC , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; setUsesTOCBasePtr ( DAG ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , InFlag ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; InFlag = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; } MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O


<s> rtx set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; return set


<s> parseDirectiveReq ( Name , NameLoc ) ; return true ; } size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) return parseSysAlias ( Head , NameLoc , Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( ( Head == <STR_LIT> || Head == <STR_LIT> ) && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; std :: string Suggestion ; <STR_LIT> CC = parseCondCodeString ( Head , Suggestion ) ; if ( CC == <STR_LIT> ) { std :: string Msg = <STR_LIT> ; if ( ! Suggestion . empty ( ) ) Msg += <STR_LIT> + Suggestion + <STR_LIT> ; return Error ( SuffixLoc , Msg ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , SuffixLoc , getContext ( ) , true ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , NameLoc , NameLoc , getContext ( ) ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , SuffixLoc , getContext ( ) , true ) ) ; } bool condCodeFourthOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeSecondOperand = ( Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeThirdOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; if ( getLexer ( ) . isNot (


<s> if ( ( perm & <NUM_LIT> ) == ( <NUM_LIT> << <NUM_LIT> ) ) continue ; if ( ( perm & <NUM_LIT> ) == <NUM_LIT> ) continue ; if ( ( perm & <NUM_LIT> ) == ( <NUM_LIT> << <NUM_LIT> ) ) continue ; } for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { j = d -> perm [ i ] / nelt2 ; if ( j == ( ( perm >> ( <NUM_LIT> * ( i >= nelt2 ) ) ) & <NUM_LIT> ) ) dsecond . perm [ i ] = nelt + ( i & nelt2 ) + ( d -> perm [ i ] & ( nelt2 - <NUM_LIT> ) ) ; else if ( j == ( unsigned ) ( i >= nelt2 ) + <NUM_LIT> * ( perm >= <NUM_LIT> ) ) dsecond . perm [ i ] = d -> perm [ i ] & ( nelt - <NUM_LIT> ) ; else break ; } if ( i == nelt ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dsecond ) ; end_sequence ( ) ; } else ok = false ; if ( ok ) { if ( d -> testing_p ) return true ; dsecond . testing_p = false ; dfirst = * d ; dfirst . target = gen_reg_rtx ( d -> vmode ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) dfirst . perm [ i ] = ( i & ( nelt2 - <NUM_LIT> ) ) + ( ( perm >> ( <NUM_LIT> * ( i >= nelt2 ) ) ) & <NUM_LIT> ) * nelt2 ; canonicalize_perm ( & dfirst ) ; ok = expand_vec_perm_1 ( & dfirst ) ; gcc_assert ( ok ) ; if ( perm >= <NUM_LIT> ) dsecond . op0 = dsecond . op1 ; dsecond . op1 = dfirst


<s> else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode


<s> __builtin_arm_set_fpscr_nzcvqc ( ( __builtin_arm_get_fpscr_nzcvqc ( ) & ~ <NUM_LIT> ) | ( * __carry << <NUM_LIT> ) ) ; uint32x4_t __res = __builtin_mve_vadcq_uv4si ( __a , __b ) ; * __carry = ( __builtin_arm_get_fpscr_nzcvqc (


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocNumOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) . lower ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! isValidCoprocessorNumber ( Num , getSTI ( ) . getFeatureBits ( ) ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num ,


<s> if ( TARGET_64BIT ) { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + cum -> words ; if ( arg_size > <NUM_LIT> || mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> , ub = arg_size ; gpr_reg_base -= alignment ; ub = MIN ( ub , max_arg_words - cum -> words - alignment ) ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , GEN_INT ( offset ) ) ; gpr_reg_base -= <NUM_LIT> ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( ub , loc ) ) ; } } else { if ( arg_size > <NUM_LIT> ) { if ( cum -> words ) { gpr_reg_base =


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StringRef LayoutSpec ; SMLoc RegEndLoc , LayoutLoc


<s> static bool virt_or_elim_regno_p ( unsigned regno ) { return ( ( regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_POINTER_REGISTER ) || regno == FRAME_POINTER_REGNUM || regno


<s> t = build3 ( COND_EXPR , void_type_node , t , u , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; t = sav ; if ( sav_ofs ) t = build2 ( PLUS_EXPR , ptr_type_node , sav , size_int ( sav_ofs ) ) ; u = build2 ( POSTINCREMENT_EXPR , TREE_TYPE ( reg ) , reg , size_int ( n_reg ) ) ; u = build1 ( CONVERT_EXPR , integer_type_node , u ) ; u = build2 ( MULT_EXPR , integer_type_node , u , size_int ( sav_scale ) ) ; t = build2 ( PLUS_EXPR , ptr_type_node , t , u ) ; t = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_false ) ; append_to_statement_list ( t , pre_p ) ; if ( n_reg > <NUM_LIT> ) { t = build ( MODIFY_EXPR , TREE_TYPE ( reg ) , reg , size_int ( <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; } } t = ovf ; if ( align != <NUM_LIT> ) { t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( align - <NUM_LIT> ) ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( NULL_TREE , - align ) ) ; } gimplify_expr ( & t , pre_p , NULL , is_gimple_val , fb_rvalue ) ; u = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( u , pre_p ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( size ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; gimplify_and_add ( t , pre_p ) ; if ( lab_over ) { t = build1 ( LABEL_EXPR , void_type_node


<s> rtx address ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; tree arg_type , fntype ; bool first_param = true ; function_args_iterator args_iter ; uint32_t padding_bits_to_clear [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( ! CALL_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , <NUM_LIT> ) > <NUM_LIT> ) ; call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; unspec = XEXP ( call , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) != UNSPEC || XINT ( unspec , <NUM_LIT> ) != UNSPEC_NONSECURE_MEM ) continue ; bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , NUM_ARG_REGS ) ; if ( TARGET_HARD_FLOAT_ABI ) { auto_sbitmap float_bitmap ( maxregno + <NUM_LIT> ) ; bitmap_clear ( float_bitmap ) ; bitmap_set_range ( float_bitmap , FIRST_VFP_REGNUM , D7_VFP_REGNUM - FIRST_VFP_REGNUM + <NUM_LIT> ) ; bitmap_ior ( to_clear_bitmap , to_clear_bitmap , float_bitmap ) ; } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; address_regnum = REGNO ( XEXP ( address , <NUM_LIT> )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm9 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> ) |


<s> void SwitchMode ( ) { unsigned FB = ComputeAvailableFeatures ( STI . ToggleFeature ( <STR_LIT> ) ) ; setAvailableFeatures ( FB


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>64R5 ( ) { OS <<


<s> if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) .

getImm ( ) * Scale ) == Bytes && getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ;


<s> ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> )


<s> } if ( ! HasPads ) return false ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality ::


<s> FPOStateMachine FSM ( FPO ) ; FSM . emitFrameDataRecord ( OS , FPO -> Begin ) ; for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM . CurOffset ; break ; case FPOInstruction :: StackAlign : FSM . StackOffsetBeforeAlign = FSM . CurOffset ; FSM . StackAlign = Inst .


<s> else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment =


<s> static bool scaleOffset ( unsigned Opc , int64_t & Offset ) { int Scale = <ISA_LIT>InstrInfo :: getMemScale ( Opc


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS


<s> } if ( ! TARGET_FPU ) { int regno ; for ( regno = <NUM_LIT> ; regno < SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = <NUM_LIT> ; } if ( fixed_regs [ <NUM_LIT> ] == <NUM_LIT> ) fixed_regs [ <NUM_LIT> ] = ! TARGET_APP_REGS ; if ( fixed_regs [ <NUM_LIT> ] == <NUM_LIT> ) fixed_regs [ <NUM_LIT> ] = ! TARGET_APP_REGS ; if ( TARGET_ARCH32 && fixed_regs [ <NUM_LIT> ] == <NUM_LIT> ) fixed_regs [ <NUM_LIT> ] = ! TARGET_APP_REGS ; else if ( TARGET_CM_EMBMEDANY ) fixed_regs [


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCapFloat64Store ( MachineInstr & MI , MachineBasicBlock * BB ) const { return emitCapFloatStore < <STR_LIT> , <STR_LIT> > ( Subtarget


<s> unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb2 ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ; return


<s> if ( N -> getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> || N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) continue ; SDValue ISR = N -> getOperand ( <NUM_LIT> ) ; if ( ! ISR . isMachineOpcode ( ) || ISR . getMachineOpcode ( ) != TargetOpcode :: INSERT_SUBREG ) continue ; if ( ! ISR . hasOneUse ( ) ) continue ; if ( ISR . getConstantOperandVal ( <NUM_LIT> ) != <STR_LIT> ) continue ; SDValue IDef = ISR . getOperand ( <NUM_LIT> ) ; if ( ! IDef . isMachineOpcode ( ) || IDef . getMachineOpcode ( ) != TargetOpcode :: IMPLICIT_DEF ) continue ; SDValue Op32 = ISR -> getOperand ( <NUM_LIT> ) ; if ( ! Op32 . isMachineOpcode ( ) ) continue ; SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 , ToPromote ) ) continue ; bool OutsideUse = false ; for ( SDNode * PN : ToPromote ) { for ( SDNode * UN : PN -> uses ( ) ) { if ( ! ToPromote . count ( UN ) && UN != ISR . getNode ( ) ) { OutsideUse = true ; break ; } } if ( OutsideUse ) break ; } if ( OutsideUse ) continue ; MadeChange = true ; for ( SDNode * PN : ToPromote ) { unsigned NewOpcode ; switch ( PN -> getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT>


<s> bool <ISA_LIT>InstructionSelector :: selectCopy ( MachineInstr & I , MachineRegisterInfo & MRI ) const { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( Register :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; if ( DstSize > SrcSize && SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> ) { const TargetRegisterClass * SrcRC = getRegClass ( MRI . getType ( SrcReg ) , SrcRegBank ) ; const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { Register ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! Register :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( Register :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && Register :: isPhysicalRegister ( SrcReg ) ) { const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg ( SrcReg


<s> const MCExpr * EVal ; Op = nullptr ; switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( RegNo ) { default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Minus : case AsmToken :: Integer


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) { this -> TLOF = std :: make_unique < <ISA_LIT>TargetObjectFile >


<s> unsigned Op2Val = Op2 . getImm ( ) ; if ( CnVal == <NUM_LIT> ) { switch ( CmVal ) { default : break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; else if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; else if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; else if ( Op1Val == <NUM_LIT> && Op2Val == <NUM_LIT> ) Asm = <STR_LIT> ; break ; case <NUM_LIT> : switch ( Op1Val ) { default : break ; case <NUM_LIT> : switch ( Op2Val ) { default : break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Op2Val ) { default : break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Op2Val ) { default : break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; case <NUM_LIT> : Asm = <STR_LIT> ; break ; } break ; } break ; } } else if ( CnVal == <NUM_LIT> ) { switch ( CmVal ) { default : break ; case <NUM_LIT> : switch ( Op1Val


<s> MachineOperand MO = MI . getOperand ( OpNo ) ; emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI , MO ) ) ; return <NUM_LIT>


<s> std :: list < fma_node * > * fma_node :: get_children (


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: Create ( Mang -> getSymbol ( GV ) , ( Subtarget ->

isTargetDarwin ( ) ? MCSymbolRefExpr :: VK_None : MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv ::


<s> int regno ; int tr0_used ; if ( ! current_function_is_leaf ) return - <NUM_LIT> ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM


<s> std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; static const <ISA_LIT>CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST . hasAVX2 ( ) ) { int Idx = FindInTable ( AVX2CostTbl , array_lengthof ( AVX2CostTbl ) , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX2CostTbl


<s> static MCTargetStreamer * createAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; bool LHSSeenZero = false ; bool LHSOk = canChangeToInt ( LHS , LHSSeenZero , Subtarget ) ; bool RHSSeenZero = false ; bool RHSOk = canChangeToInt ( RHS , RHSSeenZero , Subtarget ) ; if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) )


<s> int64_t Dummy1 , Dummy2 ; if ( ! getMemOpInfo ( LdSt . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ; } else { assert ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg


<s> if ( LastEMS == EMS_A64 ) return ; emitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> return ( float32x2_t ) __builtin_neon_vdup_nv2sf ( ( __builtin_neon_sf


<s> raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << getFunctionNumber ( ) << '_' << uid << '_' << uid2 << <STR_LIT> << MBB -> getNumber ( ) ; return OutContext . GetOrCreateSymbol ( Name . str


<s> bool hasFuseAES ( ) const { return HasFuseAES


<s> } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call || ! isStateStoreNeeded ( Personality , * Call ) ) continue ; int State = getStateForCall ( BlockColors , FuncInfo , * Call ) ; if ( State != PrevState ) insertStateNumberStore ( & I , State ) ; PrevState = State ; } auto EndState = FinalStates . find ( BB ) ; if ( EndState != FinalStates . end ( ) ) if ( EndState -> second != PrevState ) insertStateNumberStore ( BB -> getTerminator ( ) , EndState -> second ) ; } SmallVector < CallBase * , <NUM_LIT> > SetJmp3Calls ; for ( BasicBlock * BB : RPOT ) { for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call ) continue ; if ( Call -> getCalledOperand ( ) -> stripPointerCasts ( ) != SetJmp3 . getCallee ( ) -> stripPointerCasts ( ) ) continue ; SetJmp3Calls . push_back ( Call ) ; } } for ( CallBase * Call


<s> return SelectionDAGISel :: runOnFunction


<s> bool Hash = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; Hash = true ; } APFloat RealVal ( <NUM_LIT> ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Real ) ) { if ( Parser . getTok ( ) . getString ( ) != <STR_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else if ( Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { if ( ! Hash ) return MatchOperand_NoMatch ; Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT ,


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> if ( OpNo == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return


<s> MCInst LEASLInst ; LEASLInst . setOpcode ( <STR_LIT> ) ; LEASLInst . addOperand ( RD ) ; LEASLInst . addOperand (


<s> cfun -> machine -> call_abi = ix86_function_abi (


<s> static void loongarch_option_override ( void )


<s> unsigned getRegOpcode ( ) const { return I


<s> int <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( <STR_LIT> IID , Type * RetTy , ArrayRef < Value * > Args , FastMathFlags FMF , unsigned


<s> if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( create<ISA_LIT>ConstantIslandPass ( )


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo ,


<s> EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; bool IsAligned = Alignment == <NUM_LIT> || Alignment >= MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && Subtarget -> isUnalignedMem32Slow ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , TLI . getPointerTy ( ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr ,


<s> unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) { if ( align == <NUM_LIT> ) return MCDisassembler :: Fail ; align = <NUM_LIT> ; } else { if ( size == <NUM_LIT> ) { align *= <NUM_LIT> ; } else { size = <NUM_LIT> << size ; align *= <NUM_LIT> * size ; } } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) )


<s> isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; if ( Tok . is ( AsmToken :: Real ) && isVmovf ) { APFloat RealVal ( APFloat :: IEEEsingle , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( IntVal , getContext ( ) ) , S , Parser . getTok ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) && isFconst ) { int64_t Val = Tok . getIntVal ( ) ; Parser . Lex ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } float RealVal = <STR_LIT> (


<s> static unsigned getBasePointerSaveOffset ( bool is<ISA_LIT>64 , bool isDarwinABI , bool isPIC ) { if ( isDarwinABI ) return is<ISA_LIT>64 ? - <NUM_LIT> : - <NUM_LIT> ; return is<ISA_LIT>64 ? - <NUM_LIT> : isPIC


<s> if ( ( REG_N_SETS ( <NUM_LIT> ) - REG_N_DEATHS ( <NUM_LIT> ) ) >= R0_MAX_LIFE_REGIONS && REG_LIVE_LENGTH ( <NUM_LIT> ) >= R0_MAX_LIVE_LENGTH ) return <NUM_LIT> ; if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT


<s> unsigned <ISA_LIT>SEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { <ISA_LIT>AnalyzeImmediate AnalyzeImm ; const <ISA_LIT>Subtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; }


<s> if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) Bits = countTrailingZeros ( Size ) ; return Bits


<s> vqmovn_high_u16 ( uint8x8_t a , uint16x8_t b ) { uint8x16_t result = vcombine_u8 ( a , vcreate_u8


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr >


<s> MachineFunction * F = BB -> getParent ( ) ; assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = getTargetMachine ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB ,


<s> else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP ) Mode = <STR_LIT> ; else if ( Offset != <NUM_LIT> ) { if ( ! getLoadStoreMultipleOpcode ( Opcode , Mode ) ) return false ; if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) )

. addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } )


<s> MCOp = GetSymbolRef ( MO , AP . Mang -> getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_FPImmediate : APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; bool ignored ; Val . convert ( APFloat :: IEEEdouble , APFloat :: rmTowardZero , & ignored ) ; MCOp = MCOperand :: CreateFPImm ( Val . convertToDouble ( ) ) ; break ; } OutMI . addOperand (


<s> if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; if ( TARGET_32BIT && TARGET_POWERPC64 ) return rs6000_mixed_function_arg ( mode , type , align_words ) ; part_mode = mode ; n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG ) part_mode = DImode ; return gen_rtx_REG ( part_mode , GP_ARG_MIN_REG + align_words ) ; } } else if ( abi == ABI_V4 ) { if ( abi_v4_pass_in_fpr ( mode , named ) ) { if ( mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( cum -> fregno + ( FLOAT128_2REG_P ( mode ) ? <NUM_LIT> : <NUM_LIT> ) <= FP_ARG_V4_MAX_REG ) return gen_rtx_REG ( mode , cum -> fregno ) ; else return NULL_RTX ; } else { int n_words = rs6000_arg_size ( mode , type ) ; int gregno = cum -> sysv_gregno ; if ( n_words == <NUM_LIT> ) gregno += ( <NUM_LIT> - gregno ) & <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> > GP_ARG_MAX_REG ) return NULL_RTX ; if ( TARGET_32BIT && TARGET_POWERPC64 ) return rs6000_mixed_function_arg ( mode , type , gregno - GP_ARG_MIN_REG ) ; return gen_rtx_REG ( mode , gregno ) ; } } else { int align_words = rs6000_parm_start ( mode , type , cum -> words ) ; if ( elt_mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( USE_FP_FOR_ARG_P ( cum , elt_mode ) && ! ( TARGET_AIX && ! TARGET_ELF && type != NULL && AGGREGATE_TYPE_P ( type ) ) ) { rtx rvec [ GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + <NUM_LIT> ] ; rtx r , off ; int i , k = <NUM_LIT> ; unsigned long n_fpreg = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; int fpr_words ; if ( type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) k = rs6000_psave_function_arg ( mode , type , align_words , rvec ) ; for ( i = <NUM_LIT> ; i < n_elts && cum -> fregno

+ i * n_fpreg <= FP_ARG_MAX_REG ; i ++ ) {


<s> assert ( isReg ( ) && <STR_LIT> ) ; return Reg . RegNum


<s> bool isLegalMaskedStore ( Type * DataTy , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataTy ,


<s> unsigned UseIdx ; for ( UseIdx = <NUM_LIT> ; UseIdx < UseMI . getNumOperands ( ) ; ++ UseIdx ) if ( UseMI . getOperand ( UseIdx ) . isReg ( ) && UseMI . getOperand ( UseIdx ) . getReg ( ) == Reg ) break ; assert ( UseIdx < UseMI . getNumOperands ( ) && <STR_LIT> ) ; assert ( UseIdx < UseMCID . getNumOperands ( ) && <STR_LIT> ) ; const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; }


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool Verbose , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ; return false


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; if ( InVT . isVector ( ) && InVT . getScalarSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( DAG . SignBitIsZero ( Op0 ) ) return DAG . getNode ( <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; if ( isVarArg ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT


<s> return :: isPSHUFHWMask ( M , N -> getValueType


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; } assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm (


<s> return ( poly64x1_t ) __builtin_neon_vget_highv2di ( ( int64x2_t


<s> static bool isSimpleBD12Move ( const MachineInstr * MI , unsigned Flag ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; return ( ( MCID . TSFlags & Flag ) && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) && MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . addOperand ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addOperand ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if ( isZBranch ) { bool isNZ = CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ; BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( isNZ ? <STR_LIT> : <STR_LIT> ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; } CmpMI -> eraseFromParent ( ) ; Head -> updateTerminator ( ) ; RemovedBlocks . push_back ( CmpBB ) ; CmpBB -> eraseFromParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Head ) ; ++


<s> unsigned SrcReg = MI . getOperand ( OpNum ) . getReg ( ) ; unsigned SrcRegNum = Get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) ) ; if ( ( SrcReg >= <STR_LIT> && SrcReg <= <STR_LIT> ) || ( SrcReg >= <STR_LIT> && SrcReg <= <STR_LIT> ) ) SrcRegNum += <NUM_LIT> ; return ( ~ SrcRegNum ) &


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS


<s> if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx += <NUM_LIT> ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MO . setImplicit ( true ) ; MIB . add ( MO


<s> if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = <NUM_LIT> ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; } if ( info . save_lr ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_LINK ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( ( reg_mask & ( <NUM_LIT> << regno )


<s> const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create (

<NUM_LIT> , OutContext ) , OutContext ) ;


<s> bool HasNoMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool softFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU


<s> for ( floater = anchor ; floater ; floater = NEXT_INSN ( floater ) ) { if ( NOTE_P ( floater ) || ( NONJUMP_INSN_P ( floater ) && ( GET_CODE ( PATTERN ( floater ) ) == USE || GET_CODE ( PATTERN ( floater ) ) == CLOBBER ) ) ) continue ; if ( ! NONJUMP_INSN_P ( floater ) ) { floater = NULL ; break ; } floater_attr = get_attr_pa_combine_type ( floater ) ; if ( ( anchor_attr == PA_COMBINE_TYPE_FMPY && floater_attr == PA_COMBINE_TYPE_FADDSUB ) || ( anchor_attr == PA_COMBINE_TYPE_FADDSUB && floater_attr == PA_COMBINE_TYPE_FMPY ) ) { if ( pa_can_combine_p ( new_rtx , anchor , floater , <NUM_LIT> , SET_DEST ( PATTERN ( floater ) ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) ) ) break ; } } } if ( floater && ( anchor_attr == PA_COMBINE_TYPE_FADDSUB || anchor_attr == PA_COMBINE_TYPE_FMPY ) ) { rtvec vtemp = gen_rtvec ( <NUM_LIT> , copy_rtx ( PATTERN ( anchor ) ) , copy_rtx ( PATTERN ( floater ) ) ) ; rtx temp = gen_rtx_PARALLEL ( VOIDmode , vtemp ) ; emit_insn_before ( temp , anchor ) ; SET_INSN_DELETED ( anchor ) ; temp = copy_rtx ( PATTERN ( floater ) ) ; emit_insn_before ( gen_rtx_USE ( VOIDmode , temp ) , floater ) ; delete_insn ( floater ) ; continue ; } else if ( floater && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH ) { rtvec vtemp = gen_rtvec ( <NUM_LIT> , copy_rtx ( PATTERN ( anchor ) ) , copy_rtx ( PATTERN ( floater ) ) ) ; rtx temp = gen_rtx_PARALLEL ( VOIDmode , vtemp ) ; temp = emit_jump_insn_before ( temp


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getInfo <


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_T8I816_ins ( unsigned BtOpc , unsigned CmpOpc , MachineInstr & MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI . getOperand ( <NUM_LIT> ) .


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ]


<s> WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != i + WhichResult ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != i + WhichResult ) ) return false ; } return true


<s> unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; unsigned SetCCOpc ; bool SwapArgs ; switch ( CI -> getPredicate ( ) ) { case CmpInst :: FCMP_OEQ : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned EReg = createResultReg ( & <STR_LIT> ) ; unsigned NPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , EReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , NPReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( NPReg ) . addReg ( EReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_UNE : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned NEReg = createResultReg ( & <STR_LIT> ) ; unsigned PReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , NEReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , PReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( PReg ) . addReg ( NEReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_OGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs =


<s> Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Y ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; Y = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> __arm_vld1q_z_u32 ( uint32_t const *


<s> return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? <STR_LIT> :: read32le ( Bytes . data ( ) ) : <STR_LIT> :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address


<s> static bool hasSpills ( const MachineFunction & MF ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return FuncInfo -> hasSpills ( )


<s> return ( int32x2_t ) __builtin_neon_vcvtsv2sf (


<s> if ( ! Op . isImm ( ) ) return printOperand ( MI , OpNo , STI , O ) ; if ( PrintBranchImmAsAddress ) O << formatHex ( Op . getImm ( ) ) ; else O << formatImm ( Op . getImm ( )


<s> else if ( NumBits == <NUM_LIT> ) { if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ; else if ( SignedValue == - <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ; else return ; } } else if ( Load -> getExtensionType ( ) == <STR_LIT> ) { if ( Value > Mask ) return ; IsUnsigned = true ; } else return ; <STR_LIT> ExtType = IsUnsigned ? <STR_LIT> : <STR_LIT> ; if ( CmpOp0 . getValueType ( ) != <STR_LIT> || Load -> getExtensionType ( ) != ExtType ) CmpOp0 = DAG . getExtLoad ( ExtType , SDLoc ( Load ) , <STR_LIT> , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getMemoryVT ( ) , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ; if ( CmpOp1 . getValueType ( ) != <STR_LIT> || Value != Constant -> getZExtValue

( ) ) CmpOp1 = DAG . getConstant ( Value , <STR_LIT> ) ;


<s> if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) . addMemOperand (


<s> void emitFill ( const MCExpr & NumBytes ,

uint64_t FillValue , SMLoc Loc ) override {


<s> if ( VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : case 'f' : if ( Subtarget . hasSPE ( ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT . isVector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , &


<s> return ( vector signed int ) __builtin_altivec_vsubsws ( ( vector signed int ) a1 , ( vector signed int )


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; if ( cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) != i ) return false ; } for ( unsigned i = <NUM_LIT> ; i !=


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } return MCConstantExpr :: Create ( Val , getContext ( ) ) ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: Create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr


<s> Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; SplatBits |= <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; SplatBits |= <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ; ImmMask <<=


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; printRegister ( MO ,


<s> mips_va_start ( valist , nextarg ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ if ( ! TARGET_NEWABI ) \ { \ fprintf ( FILE , \ <STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names

[ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ } \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> if ( kind == scalar_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) return <NUM_LIT> ; return stmt_cost


<s> slots = buf ; break ; } } if ( GET_CODE ( PATTERN ( insn ) ) == USE ) slots = <STR_LIT> ; code = INSN_CODE ( insn ) ; if ( code >= <NUM_LIT> ) name = get_insn_name ( code ) ; if ( ! name ) name = <STR_LIT> ; fprintf ( dump , <STR_LIT> , code , INSN_UID ( insn ) , name , slots


<s> } } if ( ! Subtarget . useSoftFloat ( ) && Subtarget . hasX87 ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( Subtarget . hasDQI ( ) && VT != <STR_LIT> ) return SDValue ( ) ; if ( Ld -> isSimple ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue ( <NUM_LIT> ) ) ; return FILDChain


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( * CM != CodeModel :: Small && * CM != CodeModel :: Tiny && * CM != CodeModel :: Large ) { report_fatal_error ( <STR_LIT> ) ; } else if ( * CM == CodeModel :: Tiny && ! TT . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; return * CM


<s> return __builtin_mve_vqrshlq_m_n_uv4si ( __a ,


<s> Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , <STR_LIT> ) ; Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ; Value * Lo = Builder . CreateExtractValue (


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , NULL ) : ( Type * )

VectorType :: get ( ArgTy , <NUM_LIT> ) ;


<s> <ISA_LIT>BasicMCBuilder ( <ISA_LIT>BasicMCBuilder & B ) : Opcode ( B . Opcode ) , Format ( B . Format ) , NumOps ( B . NumOps ) , Disasm ( B . Disasm ) , SP ( B . SP ) { Err =


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> getBaseObject


<s> unsigned I = <NUM_LIT> ; for ( ; I < <STR_LIT> ; ++ I ) { uint64_t Byte = IntBits . lshr ( I * <NUM_LIT> ) . trunc ( <NUM_LIT> ) . getZExtValue ( ) ; if ( Byte == <NUM_LIT> ) Mask |= <NUM_LIT> << I ; else if ( Byte != <NUM_LIT> ) break ; } if ( I == <STR_LIT> ) { Opcode = <STR_LIT> ; OpVals . push_back ( Mask ) ; VecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> ) , <NUM_LIT> ) ; return true ; } if ( SplatBitSize > <NUM_LIT> ) return false ; auto tryValue = [ & ] ( uint64_t Value ) -> bool { int64_t SignedValue = SignExtend64 ( Value , SplatBitSize ) ; if ( isInt < <NUM_LIT> > ( SignedValue ) ) { OpVals . push_back ( ( ( unsigned ) SignedValue ) ) ; Opcode = <STR_LIT> ; VecVT = <STR_LIT> ( <STR_LIT> ( SplatBitSize ) , <STR_LIT> / SplatBitSize ) ; return true ; } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , SplatBitSize , Start , End ) ) { OpVals . push_back ( Start - ( <NUM_LIT> - SplatBitSize ) ) ; OpVals . push_back ( End - ( <NUM_LIT> - SplatBitSize ) ) ; Opcode = <STR_LIT> ; VecVT = <STR_LIT> ( <STR_LIT> ( SplatBitSize ) , <STR_LIT> / SplatBitSize ) ; return true


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemRIEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { SDNode * N = Op . getNode ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned BaseOp = <NUM_LIT> ; unsigned Cond = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isOneConstant ( RHS ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : if ( isOneConstant ( RHS ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ?


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( )


<s> } else if ( Op . isImm ( ) ) { O << ( uint32_t ) Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O ,


<s> void LLVMInitialize<ISA_LIT>AsmParser ( )


<s> return ( __m128h ) __builtin_ia32_vfmulcsh_mask_round ( ( __v8hf ) __C , ( __v8hf ) __D , (


<s> unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm ::


<s> bool isMRSSystemRegister ( ) const { if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister


<s> MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugValue ( ) ) { ++ I ; continue ; } if ( ! getAnalyzableBrOpc ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent ( ) ; I = MBB . rbegin


<s> return Create ( VK_AARCH64_GOTTPREL , Expr ,


<s> static void emitLEAzzi ( MCStreamer & OutStreamer , MCOperand & Imm , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand ( RD ) ; LEAInst . addOperand (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; assert ( ! RegInfo -> hasBasePointer (


<s> void SwitchMode ( ) { unsigned FB = ComputeAvailableFeatures ( STI . ToggleFeature ( <STR_LIT> ) ) ; setAvailableFeatures (


<s> int32_t Exp = ( Imm . lshr ( <NUM_LIT> ) . getSExtValue ( ) & <NUM_LIT> ) - <NUM_LIT> ; int64_t Mantissa = Imm . getZExtValue ( ) & <NUM_LIT> ; if ( Mantissa & <NUM_LIT> ) return - <NUM_LIT> ; Mantissa >>= <NUM_LIT> ; if ( ( Mantissa & <NUM_LIT> ) != Mantissa


<s> assert ( * Args [ i ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != * Args [


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) -


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVecShiftL8OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const


<s> if ( ( flags & ( ISA_3_0_MASKS_SERVER & ~ ISA_2_7_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_7_MASKS_SERVER & ~ ISA_2_6_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_6_MASKS_SERVER & ~ ISA_2_5_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_5_MASKS_SERVER & ~ ISA_2_4_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_4_MASKS & ~ ISA_2_1_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ISA_2_1_MASKS ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & OPTION_MASK_POWERPC64 )


<s> unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( FrameLabel , - NumBytes ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } else if ( NumBytes ) { ++ NumRedZoneFunctions ; } return ; } int FPOffset = <NUM_LIT> ; if ( HasFP ) FPOffset = getFPOffsetInPrologue ( MBBI ) ; while ( isCSSave ( MBBI ) ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; const unsigned Alignment = MFI -> getMaxAlignment ( ) ; const bool NeedsRealignment = RegInfo -> needsStackRealignment ( MF ) ; unsigned scratchSPReg = <STR_LIT> ; if ( NumBytes && NeedsRealignment ) { scratchSPReg = <STR_LIT> ; MF . getRegInfo ( ) . setPhysRegUsed ( scratchSPReg ) ; } if ( NumBytes && ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , scratchSPReg , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; if ( NumBytes && NeedsRealignment ) { const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( NrBitsToZero > <NUM_LIT> ) ; assert ( scratchSPReg != <STR_LIT> ) ; uint32_t andMaskEncoded = ( <NUM_LIT> << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero ) << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero - <NUM_LIT> ) << <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( scratchSPReg , RegState :: Kill ) . addImm ( andMaskEncoded ) ; } if ( RegInfo -> hasBasePointer (


<s> SDValue FPSCR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> const auto & MO = I . getOperand ( <NUM_LIT> ) ; auto VRegAndVal = getConstantVRegVal ( MO . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; const LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DstTy . isVector ( ) ) return false ; bool Is64Bit = DstTy . getSizeInBits ( ) == <NUM_LIT> ; auto Imm1Fn = Is64Bit ? selectShiftA_64 ( MO ) : selectShiftA_32 ( MO ) ; auto Imm2Fn = Is64Bit ? selectShiftB_64 ( MO ) : selectShiftB_32 ( MO ) ; MachineIRBuilder MIB ( I ) ; if ( ! Imm1Fn || ! Imm2Fn ) return false ; auto NewI = MIB . buildInstr ( Is64Bit ? <STR_LIT> : <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; for ( auto & RenderFn : * Imm1Fn ) RenderFn ( NewI ) ; for ( auto & RenderFn : * Imm2Fn ) RenderFn ( NewI ) ; I . eraseFromParent (


<s> if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else gcc_unreachable


<s> <STR_LIT> ET = getShiftExtendType ( ) ; if ( ET == <STR_LIT>


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) (


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; O << <STR_LIT> << markup


<s> static __inline__ float __fnabsf ( float x ) { float


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym


<s> if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto Rz = Operands . back ( ) -> getReg ( ) ; Operands . pop_back ( ) ; reglist . push_back ( Ry ) ; reglist . push_back ( Rz ) ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) getLexer ( ) . Lex ( ) ; else if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; } else if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { reglist . push_back ( Ry ) ; reglist . push_back ( Ry ) ; getLexer ( ) . Lex ( ) ; } else if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { reglist . push_back ( Ry ) ; reglist . push_back ( Ry ) ; break ; } else { Error ( getLoc ( ) , <STR_LIT> ) ; return


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } return


<s> const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT>


<s> return ( int8x8_t ) __builtin_neon_vhsubsv8qi


<s> rtx expand ( function_expander & e ) const override { int unspec = ( e . type_suffix ( <NUM_LIT> ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( <NUM_LIT> ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( <NUM_LIT> ) ) ; return e . use_exact_insn ( code_for_while ( unspec ,


<s> int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( LookForWater ( U , UserOffset , IP ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . count ( WaterBB ) ) { NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; CreateNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U .


<s> MVT EltVT = VT . getScalarType ( ) ; int NumEltBits = EltVT . getSizeInBits ( ) ; MVT IntEltVT = <STR_LIT> ( NumEltBits ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , IntEltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , IntEltVT ) ; if ( EltVT . isFloatingPoint ( ) ) { Zero = DAG . getNode ( <STR_LIT> , DL , EltVT , Zero ) ; AllOnes = DAG . getNode ( <STR_LIT> , DL , EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ]


<s> Op -> Mem . BaseReg = <NUM_LIT> ; Op -> Mem . AluOp = LPAC :: ADD ; Op -> Mem . OffsetReg = <NUM_LIT> ; Op -> Mem . Offset = Imm ; return Op


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; SDValue Elt = DAG . getConstant ( Val


<s> if ( ! lra_in_progress && ! reload_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= <NUM_LIT> ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ (


<s> while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin


<s> bool hasEnhancedCounterVirtualization (


<s> static bool isFloatingPointZero ( SDValue Op ) { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; } } else if ( Op -> getOpcode ( ) == <STR_LIT> && Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue BitcastOp = Op -> getOperand ( <NUM_LIT> ) ; if ( BitcastOp -> getOpcode ( ) == <STR_LIT> ) { SDValue MoveOp = BitcastOp -> getOperand ( <NUM_LIT> ) ; if ( MoveOp -> getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( MoveOp ) -> getZExtValue ( ) == <NUM_LIT> ) { return true


<s> if ( out_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( arm_regs_in_sequence , <NUM_LIT> , dst , TRUE , dstbase , & dstoffset ) ) ; else if ( out_words_to_go != <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( arm_regs_in_sequence , out_words_to_go , dst , ( last_bytes == <NUM_LIT> ? FALSE : TRUE ) , dstbase , & dstoffset ) ) ; else { mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , R0_REGNUM ) ) ; if ( last_bytes != <NUM_LIT> ) { emit_insn ( gen_addsi3 ( dst , dst , GEN_INT ( <NUM_LIT> ) ) ) ; dstoffset += <NUM_LIT> ; } } } in_words_to_go -= in_words_to_go < <NUM_LIT> ? in_words_to_go : <NUM_LIT> ; out_words_to_go -= out_words_to_go < <NUM_LIT> ? out_words_to_go : <NUM_LIT> ; } if ( out_words_to_go ) { rtx sreg ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; sreg = copy_to_reg ( mem ) ; mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , sreg ) ; in_words_to_go -- ; gcc_assert ( ! in_words_to_go ) ; } if ( in_words_to_go ) { gcc_assert ( in_words_to_go > <NUM_LIT> ) ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; part_bytes_reg = copy_to_mode_reg ( SImode , mem ) ; } gcc_assert ( ! last_bytes || part_bytes_reg ) ; if ( BYTES_BIG_ENDIAN && last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> * ( <NUM_LIT> - last_bytes ) ) ) ) ; part_bytes_reg = tmp ; while ( last_bytes ) { mem = adjust_automodify_address ( dstbase , QImode , plus_constant ( Pmode , dst , last_bytes - <NUM_LIT> ) , dstoffset + last_bytes - <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( QImode , part_bytes_reg ) ) ; if ( -- last_bytes ) { tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> ) ) ) ; part_bytes_reg = tmp ; } } } else { if ( last_bytes > <NUM_LIT> ) { mem = adjust_automodify_address ( dstbase , HImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_lowpart ( HImode , part_bytes_reg ) ) ; last_bytes -= <NUM_LIT>


<s> SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } bool AllContants = true ; uint64_t Immediate = <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) { AllContants = false ; break ; } if ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) ) Immediate |= ( <NUM_LIT> << idx ) ; } if ( AllContants ) { SDValue FullMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Immediate , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FullMask , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } SDValue In = Op . getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { if ( Op . getOperand ( i ) != In && Op . getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; } SDValue EFLAGS , <ISA_LIT>CC ; if ( In . getOpcode ( )


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpTargetOpValueMM ( const MachineInstr & MI


<s> unsigned A15SDOptimizer :: createVExt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned Ssub0 , unsigned Ssub1 ) { unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm

( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> uint64_t EncVal = Imm ; return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT>


<s> } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) && ! Function . isDeclaration ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) && ! Global . isDeclaration ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective ( Symbol , true ) ; for ( auto & Symbol : DLLExportedFns ) GenerateExportDirective ( Symbol , false ) ; } } if ( TT . isOSBinFormatELF ( )


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VF ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; int MaskUnpackCost = <NUM_LIT> ; if ( VariableMask ) { VectorType * MaskTy = VectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } int MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; int InsertExtractCost = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost

+= getVectorInstrCost ( Instruction :: InsertElement , SrcVTy , i ) ;


<s> OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( ATOMIC_CMP_SWAP ) ; OPCODE ( ATOMIC_LOAD_128 ) ; OPCODE ( ATOMIC_STORE_128 ) ; OPCODE ( ATOMIC_CMP_SWAP_128 ) ; OPCODE ( LRV ) ; OPCODE ( STRV


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; O <<


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > C (


<s> int ImmSize = <STR_LIT> ( TSFlags ) ? <STR_LIT> ( TSFlags ) : <NUM_LIT> ; EmitImmediate ( Disp , <NUM_LIT> , MCFixupKind ( FixupKind ) , CurByte , OS , Fixups , - ImmSize ) ; return ; } unsigned BaseRegNo = BaseReg ? Get<ISA_LIT>RegNum ( Base ) : - <NUM_LIT> ; if ( IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! Is64BitMode || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_4 , CurByte , OS , Fixups ) ; return ; } if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; return ; } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_4 , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg


<s> if ( VT . is128BitVector ( ) ) { if ( Subtarget . hasSSE2 ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else { SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . is256BitVector ( ) ) { if ( Subtarget . hasInt256 ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst ,


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return <NUM_LIT> ; return Subtarget -> isThumb ( )