<s> for ( i = <NUM_LIT> * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_insn ( gen_rtx_SET ( g1 , plus_constant ( Pmode , g1 , - PROBE_INTERVAL ) ) ) ; emit_stack_probe ( g1 ) ; } emit_stack_probe ( plus_constant ( Pmode , g1 , ( i - PROBE_INTERVAL ) - size ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx g4 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( g1 , GEN_INT ( first ) ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( g4 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_insn ( gen_rtx_SET ( g4 , gen_rtx_MINUS ( Pmode , g1 , g4 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , g1


_mm512_setzero_hi ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> if ( ! isTRNMask ( ShuffleMask , NumElts , WhichResult ) ) return false ; unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register V1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register V2 = MI . getOperand ( <NUM_LIT>


<s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( CP_READ_MEMORY | CP_WRITE_MEMORY ) ) return true ; return


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower MCInstLowering ( OutContext


<s> bool <ISA_LIT>ConstantIslands :: FixUpUnconditionalBr ( MachineFunction & MF , ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 ) llvm_unreachable ( <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT>


<s> int SPDiff = ( int ) CallerMinReservedArea - ( int ) ParamSize ; if ( SPDiff < FI -> getTailCallSPDelta ( ) ) FI -> setTailCallSPDelta (


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


<s> EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT .


<s> getStubFactory ( ) -> addPrototype ( new THMToTHMStub ( config ( ) . isCodeIndep ( ) , m_pAttrData -> usingThumb2 ( ) ) ) ; getStubFactory ( ) -> addPrototype ( new THMTo<ISA_LIT>Stub ( config ( ) . isCodeIndep ( ) , m_pAttrData -> usingThumb2 ( ) ) ) ; return


<s> bool LSRWithInstrQueries ( ) { return true


<s> dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedOpcodeModifier ) return <NUM_LIT> ; insn -> consumedOpcodeModifier = TRUE ; switch ( insn -> spec -> modifierType ) { default : debug ( <STR_LIT> ) ; return -


<s> const auto & Mid = Indices . begin ( ) + Indices . size ( ) / <NUM_LIT> ; const auto & End = Indices . end ( ) ; if ( fitsRegularPattern < int > ( Begin , <NUM_LIT> , Mid , <NUM_LIT> , <NUM_LIT> ) ) Wt = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Begin , <NUM_LIT> , Mid , Indices . size ( ) + <NUM_LIT> , <NUM_LIT> ) ) Wt = Op -> getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; if ( fitsRegularPattern < int > ( Mid , <NUM_LIT> , End , <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Mid , <NUM_LIT> , End , Indices . size ( ) + <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else return SDValue


<s> int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , &

num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) .


<s> } else return false ; if ( isLoad && usePartialVectorLoads ( N ) ) { return false ; } if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base ,


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case


<s> switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasMVEIntegerOps ( ) ) return Super ; break ; } Super = * I ++ ; } while ( Super ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDNode * Node = Op . getNode ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , dl ) ; Chain = LowerWindowsDYNAMIC_STACKALLOC ( Op , Chain , Size , DAG ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; Chain = SP . getValue ( <NUM_LIT> ) ; SP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= <NUM_LIT> && nelems <= <NUM_LIT> ) ) return true ; if ( TARGET_HAVE_MVE && ! BYTES_BIG_ENDIAN && VALID_MVE_MODE ( mode ) && ( nelems ==

<NUM_LIT> || nelems == <NUM_LIT> ) ) return true ;


<s> int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ; return IsAddressingMode5 ( N , Base , Offset


<s> bool IsFMA3 = ( ( TSFlags & <STR_LIT> ) == <STR_LIT> || ( TSFlags & <STR_LIT> ) == <STR_LIT> ) && ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) ) ; if ( ! IsFMA3 ) return nullptr ; verifyTables ( ) ; ArrayRef < <ISA_LIT>InstrFMA3Group > Table ; if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( RoundGroups ) ; else if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( BroadcastGroups ) ; else Table = makeArrayRef ( Groups ) ; unsigned FormIndex = ( ( BaseOpcode - <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; auto I = llvm :: bsearch ( Table , [ = ] ( const <ISA_LIT>InstrFMA3Group & Group ) { return Opcode <= Group . Opcodes [ FormIndex ] ; } ) ; assert ( I != Table . end ( ) && I -> Opcodes [ FormIndex ] == Opcode && <STR_LIT> ) ; return I


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VSrc = Node -> getOperand ( <NUM_LIT> ) ; SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue VIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue VMask = Node -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return false ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDLoc DL ( Node ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode


<s> return false ; } for ( const MachineOperand & Op : FPUMI . defs ( ) ) { if ( ! Op . isReg ( ) ) continue ; bool Reads , Writes ; std :: tie ( Reads , Writes ) = MIInSlot . readsWritesVirtualRegister


<s> return ( __m512i ) __builtin_ia32_expandloadqi512_maskz ( ( const __v64qi * ) __B , ( __v64qi ) _mm512_setzero_si512


<s> case <STR_LIT> : { MachineOperand & Op = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op . isUse ( ) && Op . isReg ( ) && Op . getReg ( ) >= <STR_LIT> && Op . getReg ( ) <= <STR_LIT> ) ; unsigned FPReg = getFPReg ( Op ) ; if ( Op . isKill ( ) ) moveToTop ( FPReg , Inst ) ; else duplicateToTop ( FPReg , FPReg , Inst ) ; BuildMI ( * MBB , Inst , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: ImplicitKill ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; -- StackTop ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && ( Op . isKill ( ) || getFPReg ( Op ) == FirstFPRegOp || MI -> killsRegister ( Op . getReg ( ) ) ) && <STR_LIT> ) ; if ( FirstFPRegOp == ~ <NUM_LIT> ) FirstFPRegOp = getFPReg ( Op ) ; else { assert ( SecondFPRegOp == ~ <NUM_LIT> && <STR_LIT> ) ; SecondFPRegOp = getFPReg ( Op ) ; } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI -> RemoveOperand ( i ) ; -- i , -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ScratchFPReg ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp && <STR_LIT> ) ; StackTop = <NUM_LIT>


<s> void <ISA_LIT>BaseInstrInfo :: emitCFIForLRRestoreFromReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , DwarfLR ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags


<s> static <ISA_LIT>Operand * CreateToken ( StringRef Str , SMLoc S , bool Is<ISA_LIT>64 ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> EmitLabel ( Stub ) ; assert ( ! isPositionIndependent ( ) && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig , LE ,


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const


<s> static std :: string computeDataLayout ( bool isLittle , <ISA_LIT>ABIInfo & ABI ) { std :: string Ret = <STR_LIT> ; if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( mnemonic , false , Op -> getStartLoc ( ) , Context ) ; const MCExpr * NewImm = MCConstantExpr :: Create ( imm >> shift , Context ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateImm ( NewImm , Op2 -> getStartLoc ( ) , Op2 -> getEndLoc ( ) , Context ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShifter ( <STR_LIT> , shift , Op2 -> getStartLoc ( ) , Op2 -> getEndLoc ( )


<s> x = strip_salt ( x ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; return SYMBOL_REF_TLS_MODEL ( x )


<s> ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; MVT AmtTy = ShAmt . getSimpleValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , AmtTy , ShAmt ) ; if ( Subtarget . hasSSE41 ( ) ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else { SDValue ByteShift = DAG . getTargetConstant ( ( <NUM_LIT> - AmtTy . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast ( <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; } } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; } else { SDValue ShOps [ <NUM_LIT> ] = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG . getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ; ShAmt = DAG . getBuildVector ( <STR_LIT> , dl


<s> return ( ( optimize_size || arm_ld_sched )


<s> bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } else { FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo (


<s> if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; else operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT>


<s> for ( const auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ; return false


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return std :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return std :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSBinFormatCOFF ( ) ) return std :: make_unique < TargetLoweringObjectFileCOFF


<s> __builtin_aarch64_st1v16qi ( ( __builtin_aarch64_simd_qi *


<s> HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return <NUM_LIT> ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ALTIVEC && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else if ( TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) clear_step = <NUM_LIT> ; else if ( TARGET_SPE && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_SPE && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V2SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest


<s> OpBegins . push_back ( OpBegins . back (


<s> continue ; } TBB = Branch . Target -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = Branch . Target -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch . CCValid ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch . CCMask ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> && TBB && <STR_LIT> ) ; if ( TBB != Branch . Target -> getMBB ( ) ) return true ; unsigned OldCCValid = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned OldCCMask = Cond [ <NUM_LIT> ] .


<s> if ( ( size_t ) p < sz ) { if ( ftruncate ( fd , sz ) == - <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; } base = mmap ( NULL , sz , PROT_READ | PROT_WRITE , MAP_PRIVATE , fd , <NUM_LIT> ) ; if ( base == MAP_FAILED ) base = NULL ; else munmap ( base , sz ) ; if ( lseek ( fd , p , SEEK_SET ) == ( off_t ) - <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; return


<s> __rv . __o = __builtin_neon_vld3_dupv4hi ( ( const


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( mips_expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) perm2 [ i ] = ( d -> perm [ i ] + nelt ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; if ( mips_expand_vselect_vconcat ( d -> target , d -> op1 , d -> op0 , perm2 , nelt ) ) return true ; } if ( mips_expand_vpc_loongson_even_odd ( d ) ) return true ; if ( mips_expand_vpc_loongson_pshufh ( d ) ) return true ; if ( mips_expand_vpc_loongson_bcast ( d ) ) return true ; return false


<s> DebugLoc dl = I == MBB -> end ( ) ? DebugLoc ( ) : I -> getDebugLoc ( ) ; unsigned STReg = getSTReg


<s> Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , LaneLen ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! isLegalInterleavedAccessType ( SubVecTy , DL ) ) return false ; unsigned NumStores = getNumInterleavedAccesses ( SubVecTy , DL ) ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo (


<s> vgetq_lane_u8 ( uint8x16_t __a , const int __b ) { return ( uint8_t ) __builtin_neon_vget_laneuv16qi ( (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getShifter


<s> new GOTPLTEntry ( <NUM_LIT> , m_SectionData ) ; new GOTPLTEntry ( <NUM_LIT>


<s> NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else { return SDValue ( ) ; } unsigned VLDLaneNo = cast < ConstantSDNode > ( VLD -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return SDValue ( ) ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( )


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI (


<s> void <ISA_LIT>InstPrinter :: printSImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed char ) Op . getImm ( ) ) ; else if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed short


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) && Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return TokError (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( )


<s> unsigned llvm :: getMatchingCondBranchOpcode ( unsigned Opc ) { if ( Opc == <STR_LIT> ) return <STR_LIT> ; if ( Opc == <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( e + i ) ,


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand


<s> int modrm = ix86_get_modrm_for_rop ( insn , recog_data . operand , recog_data . n_operands , & opno0 , & opno1 ) ; if ( modrm < <NUM_LIT> || ! ix86_rop_should_change_byte_p ( modrm ) || opno0 == opno1 ) continue ; rtx oldreg = recog_data . operand [ opno1 ] ; preprocess_constraints ( insn ) ; const operand_alternative * alt = which_op_alt ( ) ; int i ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( i != opno1 && alt [ i ] . earlyclobber && reg_overlap_mentioned_p ( recog_data . operand [ i ] , oldreg ) ) break ; if ( i < recog_data . n_operands ) continue ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , REGNO ( oldreg ) , reg_class_names [ alt [ opno1 ] . cl ] ) ; HARD_REG_SET unavailable ; REG_SET_TO_HARD_REG_SET ( unavailable , & live ) ; SET_HARD_REG_BIT ( unavailable , REGNO ( oldreg ) ) ; IOR_COMPL_HARD_REG_SET ( unavailable , call_used_reg_set ) ; IOR_HARD_REG_SET ( unavailable , fixed_reg_set ) ; IOR_HARD_REG_SET ( unavailable , output_risky ) ; IOR_COMPL_HARD_REG_SET ( unavailable , reg_class_contents [ alt [ opno1 ] . cl ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! TEST_HARD_REG_BIT


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ,


<s> unsigned getCSRFirstUseCost ( ) const override { return


<s> rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) ) ; } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P


<s> void <ISA_LIT>AsmPrinter :: printPCLabel ( const MachineInstr * MI , int opNum ) { int Id = ( int ) MI -> getOperand ( opNum ) .


<s> if ( optab_handler ( movmisalign_optab , mode ) == CODE_FOR_nothing ) return false ; if ( misalignment == - <NUM_LIT> ) { if ( rs6000_vector_alignment_reachable ( type ,


<s> unsigned getReg ( ) const { assert ( isRegNumber ( ) && <STR_LIT> ) ; return ( unsigned ) Imm .


<s> static inline uint64_t decodeAdvSIMDModImmType1 ( uint8_t Imm ) { uint64_t EncVal


<s> if ( ! getTargetStreamer ( ) . isModuleDirectiveAllowed ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } StringRef Option ; if ( Parser . parseIdentifier ( Option ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( true , isABI_O32 ( ) ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option


<s> continue ; } SDValue Elt = DAG . getShuffleScalarElt ( SVOp , Index ) ; if ( Elt . getNode ( ) && isZeroNode ( Elt ) ) ++ NumZeros ; else break ; } return


<s> } else if ( RC -> contains ( Reg ) ) { return true ; } return


<s> case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return <NUM_LIT> ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : return <NUM_LIT> ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_GENERIC


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; unsigned CopyOpc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg )


<s> EVT VT = Op . getValueType ( ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; SDValue RC = Op . getOperand ( <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , LoVT , Lo


<s> assert ( ML -> isUnindexed ( ) && <STR_LIT> ) ; SDValue Addr , VecIndex ; Align Alignment ; unsigned Offset ; if ( ! getParamsForOneTrueMaskedElt ( ML , DAG , Addr , VecIndex , Alignment , Offset ) ) return SDValue ( ) ; SDLoc DL ( ML ) ; EVT VT = ML -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VT . getVectorElementType ( ) ; EVT CastVT = VT ; if ( EltVT == <STR_LIT> && ! Subtarget .


<s> NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; } BuildMI ( BB , DL , TII -> get ( SC ) , Success )

. addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> Func . enqueueExitBlock ( ) ; return true


<s> if ( next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = next ( MBBI


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) && Name


<s> void printHex64ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream &


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) &&


<s> static bool isBaseAlignmentOfN ( unsigned N , SDNode * Base , const TargetLowering & TLI ) { GlobalValue *


<s> return ( __m128i ) __builtin_ia32_cvttpd2qq128_mask ( ( __v2df ) __A , ( __v2di )

_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool Changed = false


<s> static bool aarch64_is_reduction ( stmt_vec_info


<s> fprintf ( stderr , <STR_LIT> ) ; } if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; if ( ! rs6000_inner_target_options ( args , false ) || ! rs6000_option_override_internal ( false ) || ( cur_tree = build_target_option_node ( & global_options ) ) == NULL_TREE ) { if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> ) ; return false ; } } target_option_current_node = cur_tree ; if ( rs6000_target_modify_macros_ptr ) { prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; prev_bumask = prev_opt -> x_rs6000_builtin_mask ; prev_flags = prev_opt


<s> return ( __mmask64 ) __builtin_ia32_ucmpb512_mask ( ( __v64qi ) __A , ( __v64qi )


<s> SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true


<s> auto SelectB = N -> getOperand ( <NUM_LIT> ) ; auto NTy = N -> getValueType ( <NUM_LIT> ) ; if ( ! NTy . isScalableVector ( ) ) return SDValue ( ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> || ! SetCC . hasOneUse ( ) ) return SDValue ( ) ; switch ( SelectB . getOpcode ( )


<s> if ( VT . getSizeInBits ( ) >= RegisterVT . getSizeInBits ( ) ) return CCValAssign :: LocInfo :: Full ; if ( Flags . isSExt ( ) ) return


<s> if ( dump_file && ( dump_flags & TDF_DETAILS ) ) fprintf (


<s> Inst . addOperand ( MCOperand :: CreateReg (


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , NumMaskElts ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; if ( CCVT . getSizeInBits ( ) != ResVT . getSizeInBits ( ) ) return SDValue ( ) ; assert ( DCI . isBeforeLegalize ( ) || DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT>


<s> int64_t Value = - CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> )

&& Value > <NUM_LIT> && Value <= <NUM_LIT> ;


<s> return __builtin_mve_vhcaddq_rot270_sv4si ( __a ,


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG


<s> void addExactFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( bool ( isExactFPImm < ImmIs0 , ImmIs1 > ( ) )


<s> return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && Subtarget . is64Bit ( ) ) { return Op ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction


<s> if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Subtarget -> is32Bit ( ) && Subtarget -> isTargetWindowsMSVC ( ) && ( Subtarget -> getCPU ( ) . empty ( ) || Subtarget -> getCPU ( ) == <STR_LIT> ) ) { OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) , * Subtarget ) ; } else if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT> ) { MCI . setOpcode ( <STR_LIT> )


<s> const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } if ( Inst . getOpcode ( ) != <STR_LIT> ) { unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) { if ( Rt == <NUM_LIT> || Rt == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } else Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } if ( featureBits [ <STR_LIT> ] ) { Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { unsigned pred = fieldFromInstruction ( Val , <NUM_LIT>


<s> if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( <STR_LIT> , Extract ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MFI -> erase ( MBI ) ; MachineBasicBlock :: iterator J = static_cast < MachineBasicBlock :: iterator > ( NewMI ) ; processInstruction ( J ,


<s> if ( ! BucketChain . Elements [ j ] . Offset ) RemainderOffsetInfo [ <NUM_LIT> ] = std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ; else { unsigned Remainder = cast < SCEVConstant > ( BucketChain . Elements [ j ] . Offset ) -> getAPInt ( ) . urem ( Form ) ; if ( RemainderOffsetInfo . find ( Remainder ) == RemainderOffsetInfo . end ( ) ) RemainderOffsetInfo [ Remainder ] = std :: make_pair ( j , <NUM_LIT> ) ; else RemainderOffsetInfo [ Remainder ] . second ++ ; } } unsigned MaxCountRemainder = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end (

) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo [ MaxCountRemainder ] . second ) MaxCountRemainder = j ;


<s> if ( CannotTailPredicate ) return false ; if ( isVCTP ( MI ) && VCTP ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( isVCTP ( MI ) ) VCTP = MI ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) return false ; bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( IsDef && ! IsUse && VCTP && ! isVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return


<s> int <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * SrcTy , unsigned Alignment , unsigned AddressSpace ) { bool IsLoad = ( Instruction :: Load == Opcode ) ; bool IsStore = ( Instruction :: Store == Opcode ) ; VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , MaybeAlign ( Alignment ) , AddressSpace ) ; unsigned NumElem = SrcVTy -> getVectorNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second .


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm ,

CodeGenOpt :: Level OptLevel , bool verbose ) {


<s> } else { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; } report_fatal_error (


<s> static <ISA_LIT>Operand * CreateToken ( StringRef Str , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token ) ; Op -> Tok . Data = Str .


<s> SDValue <ISA_LIT>TargetLowering :: getRsqrtEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & ExtraSteps , bool & UseOneConst ) const { UseOneConst = true ; return getEstimate ( * Subtarget , DCI , <STR_LIT> , Operand


<s> if ( Imm . isNonNegative ( ) && Imm . getLimitedValue ( ) <


<s> AlignmentIsInBytes = false ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: <ISA_LIT> ; UseParensForSymbolVariant = true


<s> rtx fn = mips16_stub_function ( stub -> get_name ( ) ) ; SYMBOL_REF_FLAGS ( fn ) |= SYMBOL_FLAG_LOCAL ; if ( ! call_insn_operand ( fn , VOIDmode ) ) fn = force_reg ( Pmode , fn ) ; return


<s> if ( CFn . hasFnAttribute ( <STR_LIT> ) ) F . addFnAttr ( CFn . getFnAttribute ( <STR_LIT> ) ) ; <ISA_LIT>GenInstrInfo :: mergeOutliningCandidateAttributes ( F , Candidates


<s> SDValue <ISA_LIT>TargetLowering :: combineBR_CCMASK ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; auto * CCValid = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * CCMask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValid || ! CCMask


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> :


<s> SDLoc DL ( Op ) ; const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { SDValue GotAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags | <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , LoFlags ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) << <STR_LIT> <<


<s> auto * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) continue ; if ( L -> getNumBackEdges ( ) != <NUM_LIT> ) continue ; auto * Header = L -> getHeader ( ) ; auto PI = pred_begin ( Header ) , PE = pred_end ( Header ) ; while ( ( PI != PE ) && ( * PI == Preheader ) ) ++ PI ; assert ( PI != PE ) ; auto BackBB = * PI ; for ( auto & I : BB ) { if ( ! isa < GetElementPtrInst > ( I ) ) continue ; auto & GEP = cast < GetElementPtrInst > ( I ) ; if ( GEP . getType ( ) != GEP . getOperand ( <NUM_LIT> ) -> getType ( ) ) continue ; if ( auto * I = dyn_cast < Instruction > ( GEP . getOperand ( <NUM_LIT> ) ) ) if ( ! DT . dominates ( I , Preheader -> getTerminator ( ) ) ) continue ; if ( GEP . getNumOperands ( ) > <NUM_LIT> ) continue ; if ( GEP . getPointerAddressSpace ( ) != <NUM_LIT> ) continue ; if ( ! DT . dominates ( & GEP , BackBB ) ) continue ; auto * Idx = GEP . getOperand ( <NUM_LIT> ) ; auto * S = SE . getSCEV ( Idx ) ; if ( isa < SCEVIntegralCastExpr > ( S ) ) S = cast < SCEVIntegralCastExpr > ( S ) -> getOperand ( ) ; if ( auto * SA = dyn_cast < SCEVAddRecExpr > ( S ) ) { auto * Start = SA -> getStart ( ) ; if ( ! Start ) continue ; auto * StartValue = SCEVs [ Start ] ; if ( ! StartValue ) continue ; if ( auto * I = dyn_cast < Instruction > ( StartValue ) ) if ( ! DT . dominates ( I , Preheader -> getTerminator ( ) ) ) continue ; auto Rec = SA ->


<s> int64_t imm = static_cast < int64_t > ( ( helper_get_page_address ( pDest ) - helper_get_page_address (


<s> return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & <NUM_LIT> ) == <NUM_LIT> ) && IN_RANGE ( INTVAL ( addr ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) ; gcc_assert ( CONST_INT_P ( XEXP ( addr ,


<s> Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return false ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; return true


<s> if ( matchVectorShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchVectorShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ; return


<s> void setFeatureBits ( unsigned Feature , StringRef FeatureString ) { if ( ! ( STI . getFeatureBits ( ) & Feature ) ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString


<s> Register DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; updateValueMap ( I ,


<s> return ( __m128 ) __builtin_ia32_vcvtneeph2ps128 ( ( const


<s> break ; case <STR_LIT> : Val = performORCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N ,


<s> Value * IntrVec1Low = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ; Value * IntrVec2Low = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1Low , IntrVec2Low , MaskLowWord ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1Low , IntrVec2Low ,


<s> if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } unsigned ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , InputReg , false , <STR_LIT> ) ; if ( ! ResultReg ) return


<s> return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( )


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return SDValue ( ) ; } ShuffleVectorSDNode * Op0 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; ShuffleVectorSDNode * Op1 = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 || ! Op0 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || ! Op1 -> getOperand ( <NUM_LIT> ) . isUndef ( ) || Op0 -> getMask ( ) != Op1 -> getMask ( ) || Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; ArrayRef < int > NMask = N -> getMask ( ) ; ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size


<s> MachineOperand PushOp = MOV -> getOperand ( <STR_LIT> ) ; if ( MOV -> getOpcode ( ) == <STR_LIT> ) { unsigned PushOpcode = <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = <STR_LIT> ; } BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addOperand ( PushOp ) ; } else { unsigned int Reg = PushOp . getReg ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool SlowPUSHrmm = ST . isAtom ( ) || ST . isSLM ( ) ; MachineInstr * DefMov


<s> for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { return Subtarget -> isTargetDarwin ( ) ? LowerDarwin_VASTART ( Op , DAG ) : LowerAAPCS_VASTART ( Op ,


<s> if ( has<ISA_LIT>32r2 ( ) ) { if ( DReg == SReg ) { TmpReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! TmpReg ) return true ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , TmpReg , <STR_LIT> , TReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( <STR_LIT> , DReg , SReg , TmpReg , Inst . getLoc ( ) , STI ) ; return false ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , DReg , SReg , TReg , Inst . getLoc ( ) , STI ) ; return false ; } return true ; } if ( has<ISA_LIT>32 ( ) ) { switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; } ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; TOut . emitRRR ( <STR_LIT> , ATReg , <STR_LIT> , TReg , Inst . getLoc


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr * DefMI ,


<s> * cum += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) & ~ <NUM_LIT> : ( int_size_in_bytes ( type


<s> if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering


<s> unsigned getNumFixupKinds ( ) const { return


( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> return ( ( Value >>= <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( ( Value + ( ( <ISA_LIT>TextSectOffset - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) << <NUM_LIT> ; case MCFixupKind :: FK_Data_2 : return Value << <NUM_LIT> ; case MCFixupKind ::


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; return std :: make_pair ( Lo , Hi


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const

MachineFunction & MF , unsigned Kind ) const {


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) ||

cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) return <NUM_LIT> ;


<s> NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) !=


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ) return false ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg


<s> EXECUTE_IF_SET_IN_BITMAP ( defs , <NUM_LIT> , id , bi ) convert_reg (


<s> ( void ) Parser . parseOptionalToken ( AsmToken :: Plus ) ; std :: unique_ptr < <ISA_LIT>Operand > RHS ; if ( parse<ISA_LIT>AsmOperand ( RHS ) != MatchOperand_Success ) return MatchOperand_NoMatch ; if ( RHS -> isReg ( ) && ! RHS -> isIntReg ( ) ) { Error ( RHS -> getStartLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( RHS -> isImm ( ) ? <STR_LIT> ( LHS -> getReg ( ) , std :: move ( RHS ) ) : <STR_LIT> ( LHS -> getReg ( ) , std :: move ( RHS ) ) ) ; return MatchOperand_Success ; } Operands . push_back ( <STR_LIT> ( LHS -> getReg ( ) , S , E ) ) ; return MatchOperand_Success


<s> if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out ) ; } else { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV8 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32


<s> for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , <STR_LIT> ) ; emitInst ( TargetOpcode :: COPY , <STR_LIT> ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg


<s> if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 ( insn )


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; bool IsKnown ; auto MRSMapper = <STR_LIT> ( ) ; uint32_t MRSReg = MRSMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) &&


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> static SDValue getScatterNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Src , SDValue Mask , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( Op ) ; auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG .


<s> StringRef OptStr = Tok . getString ( ) ; if ( OptStr . equals_insensitive ( <STR_LIT> ) ) Opt = <STR_LIT> ; else return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Opt = <STR_LIT> + Val ; } else return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: CreateInstSyncBarrierOpt ( ( <STR_LIT> ) Opt , S ) ) ; return


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { real_from_string ( & ext_80387_constants_table [ i ] , cst [ i


<s> int getIntImmCost ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty


<s> else return <NUM_LIT> ; case PLUS : case MINUS : return ( constant_pool_expr_1 ( XEXP ( op , <NUM_LIT> ) , have_sym , have_toc ) && constant_pool_expr_1 ( XEXP ( op , <NUM_LIT> ) , have_sym , have_toc ) ) ; case CONST : return constant_pool_expr_1 ( XEXP ( op , <NUM_LIT> ) , have_sym , have_toc ) ; case


<s> poly_int64 value ; return poly_int_rtx_p ( x , & value )

&& aarch64_sve_cnt_immediate_p ( value ) ;


<s> RegDefs . insert ( <STR_LIT> ) ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & Operand1 = MI -> getOperand


<s> unsigned Imm2 ; if ( Val . getOpcode ( ) != <STR_LIT> || ! isInt32Immediate ( Val . getOperand ( <NUM_LIT> ) , Imm2 ) ) return false ; unsigned MB , ME ; if ( isRunOfOnes ( ~ ( Imm ^ Imm2 ) , MB , ME ) && ! ( ~ Imm & Imm2 ) ) { SDLoc dl ( N


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) ++ NumMovwMovt ; unsigned Wrapper = RelocM == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo

:: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ;


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( )


<s> case CONST : case SYMBOL_REF : if ( sparc_tls_referenced_p ( x ) ) return false ; break ; case CONST_DOUBLE : if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( mode ) && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , MRI . getRegClass (


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand ::


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM .


<s> void insert ( unsigned BBNum , BasicBlockInfo


<s> break ; case EA_BASE_BX_SI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_DI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_SI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_DI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; default : indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; switch ( insn . eaBase ) { default : debug ( <STR_LIT> ) ; return true ; case EA_BASE_ ## x : \ baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; ALL_EA_BASES ALL_REGS debug ( <STR_LIT> <STR_LIT> ) ; return true ; } } scaleAmount = MCOperand :: CreateImm ( <NUM_LIT> ) ; } displacement = MCOperand :: CreateImm ( insn


<s> } if ( regno == cfun -> machine -> global_pointer && ! mips_must_initialize_gp_p ( ) ) { if ( TARGET_64BIT ) emit_insn ( gen_move_gpdi ( dest , src ) ) ; else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthisi_di ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp ,

gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ;


<s> static unsigned <ISA_LIT>16WhichOp8uOr16simm ( unsigned shortOp , unsigned longOp , int64_t Imm ) { if ( isUInt < <NUM_LIT> > ( Imm ) )


<s> } } else { unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) || ( OffReg && TRI -> regsOverlap ( EvenReg , OffReg ) ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) && ( ! OffReg || ! TRI -> regsOverlap ( OddReg , OffReg ) ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } else { InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } if ( isLd ) ++ NumLDRD2LDR ; else ++ NumSTRD2STR ; } MBBI = prior ( MBBI ) ; MBB . erase


<s> } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + i + <NUM_LIT> ) ; } } else { nregs = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i += <NUM_LIT> ) if ( TARGET_BIG_ENDIAN ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i - <NUM_LIT> ) ; parts [ i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno


<s> else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT>


<s> if ( ! CheckXWPInstr ( MI2 , ReduceToLwp , Entry ) ) return false ; Register Reg1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg1 != Reg2 ) return false ; bool ConsecutiveForward = ConsecutiveInstr ( MI1 , MI2 ) ; bool ConsecutiveBackward = ConsecutiveInstr ( MI2 , MI1 ) ; if ( ! ( ConsecutiveForward || ConsecutiveBackward ) ) return false ; NextMII = std :: next ( NextMII ) ; return ReplaceInstruction ( MI1 , Entry , MI2


<s> assert ( TT . isOSBinFormatELF ( ) &&


<s> case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFABS ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op ,


<s> errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } errs ( ) << <STR_LIT> << Disp << '\n' ; if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ; } else if ( ES ) { errs ( ) << <STR_LIT> ; errs ( ) << ES << '\n' ; } else if ( JT != - <NUM_LIT> ) errs ( ) << <STR_LIT> << JT << <STR_LIT> << Align


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } MCSection * ELFSection = getContext ( ) . getELFSection ( Section , Type , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; getParser ( ) . getStreamer ( ) .


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S , E ; OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { bool ExpectLabel = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ; if ( ! ExpectLabel ) { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) . equals_insensitive ( <STR_LIT> ) ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } LLVM_FALLTHROUGH ; } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S ,


<s> } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REG_P ( XEXP ( x , <NUM_LIT> ) ) ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT>


<s> unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( )


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo


<s> inline unsigned createVMOVModImm ( unsigned OpCmode


<s> return ( __m128i ) __builtin_ia32_pabsd128 ( (


<s> if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; MVT VT = ArgVT . getSimpleVT ( ) . SimpleTy ; if ( VT . isFloatingPoint ( ) && ! Subtarget -> hasFPARMv8 ( ) ) return false ; if ( VT . isVector ( ) && ( ! Subtarget -> hasNEON ( ) || ! Subtarget -> isLittleEndian ( ) ) ) return false ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ]


<s> if ( L == <NUM_LIT> ) { if ( imm6 >> <NUM_LIT> == <NUM_LIT> ) esize = ESize8 ; else if ( imm6 >> <NUM_LIT> == <NUM_LIT> ) esize = ESize16 ; else if ( imm6 >> <NUM_LIT> == <NUM_LIT> )


<s> O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MO2 . getImm ( ) * <NUM_LIT> ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> <<


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateSysReg ( StringRef Str , SMLoc S , uint32_t MRSReg , uint32_t MSRReg , uint32_t PStateField , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_SysReg , Ctx ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . MRSReg = MRSReg ; Op -> SysReg . MSRReg


<s> const SCEVAddRecExpr * BasePtrSCEV = cast < SCEVAddRecExpr > ( BucketChain . BaseSCEV ) ; if ( ! BasePtrSCEV -> isAffine ( ) ) return MadeChange ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrSCEV << <STR_LIT> ) ; assert ( BasePtrSCEV -> getLoop ( ) == L && <STR_LIT> ) ; Instruction * MemI = BucketChain . Elements . begin ( ) -> Instr ; Value * BasePtr = GetPointerOperand ( MemI ) ; assert ( BasePtr && <STR_LIT> ) ; Type * I8Ty = Type :: getInt8Ty ( MemI -> getParent ( ) -> getContext ( ) ) ; Type * I8PtrTy = Type :: getInt8PtrTy ( MemI -> getParent ( ) -> getContext ( ) , BasePtr -> getType ( ) -> getPointerAddressSpace ( ) ) ; if ( ! SE -> isLoopInvariant ( BasePtrSCEV -> getStart ( ) , L ) ) return MadeChange ; const SCEVConstant * BasePtrIncSCEV = dyn_cast < SCEVConstant > ( BasePtrSCEV -> getStepRecurrence ( * SE ) ) ; if ( ! BasePtrIncSCEV ) return MadeChange ; bool CanPreInc = ( Form == UpdateForm || ( ( Form == DSForm ) && ! BasePtrIncSCEV -> getAPInt ( ) . urem ( <NUM_LIT> ) && PreferUpdateForm ) ) ; const SCEV * BasePtrStartSCEV = nullptr ; if ( CanPreInc ) BasePtrStartSCEV = SE -> getMinusSCEV ( BasePtrSCEV -> getStart ( ) , BasePtrIncSCEV ) ; else BasePtrStartSCEV = BasePtrSCEV -> getStart ( ) ; if ( ! isSafeToExpand ( BasePtrStartSCEV , * SE ) ) return MadeChange ; if ( alreadyPrepared ( L , MemI , BasePtrStartSCEV , BasePtrIncSCEV , Form ) ) return MadeChange ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrStartSCEV << <STR_LIT> ) ; BasicBlock * Header = L -> getHeader ( ) ; unsigned HeaderLoopPredCount = pred_size ( Header ) ; BasicBlock * LoopPredecessor = L -> getLoopPredecessor ( ) ; PHINode * NewPHI = PHINode :: Create ( I8PtrTy , HeaderLoopPredCount , getInstrName ( MemI , PHINodeNameSuffix ) , Header -> getFirstNonPHI ( ) ) ; SCEVExpander SCEVE ( * SE , Header -> getModule ( ) -> getDataLayout ( ) , <STR_LIT> ) ; Value * BasePtrStart = SCEVE . expandCodeFor ( BasePtrStartSCEV , I8PtrTy , LoopPredecessor -> getTerminator ( ) ) ; for ( const auto & PI : predecessors ( Header


<s> return ( __m512i ) __builtin_ia32_vcvtph2uw512_mask_round ( __B , ( __v32hi )

_mm512_setzero_si512 ( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) { SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ; if ( NewOp . getNode ( )


<s> if ( Name == <STR_LIT> ) return <STR_LIT> ; if ( Name == <STR_LIT> ) return <STR_LIT> ; if ( Name == <STR_LIT> ) return <STR_LIT> ; return None


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst , Is16BitMode ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str


<s> int Cost = getVectorIntrinsicInstrCost ( ID , RetTy ) ; if ( Cost != - <NUM_LIT> ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I


<s> Decrement ? -- First : ++ First ; if ( First -> isDebugValue ( ) ) continue ; if ( isSuitableAluInstr ( IsSpls , First , * Base , * Offset ) ) { return First ; } if ( First != Last ) { if ( InstrUsesReg ( First , Base ) ) break ; if ( Offset -> isReg ( ) && InstrUsesReg


<s> if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDLoc dl ( N ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc ,


<s> if ( ! <ISA_LIT>SelectAddress ( LI -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { std :: cout