<s> rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) && get_attr_length ( insn )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> const auto * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GOLHS || ! GVRHS ) return nullptr ; if ( GVRHS -> isThreadLocal ( ) || GVRHS -> getName ( ) != <STR_LIT> || ! GVRHS -> hasExternalLinkage ( ) || GVRHS -> hasInitializer ( ) || GVRHS -> hasSection ( ) ) return nullptr ; if ( GOLHS -> isThreadLocal


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT> ) LastMI = <NUM_LIT> ; ScoreboardHazardRecognizer :: AdvanceCycle


<s> if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { int x = <NUM_LIT> << i ; bool ok ; real_from_integer ( & s , mode , x , SIGNED ) ; if ( real_equal ( r , & s ) ) return true ; ok = exact_real_inverse ( mode


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU


<s> fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( <STR_LIT> , file )


) ) return aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_UNOPU_bswapv4hi ] ;


<s> MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . emitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext (


<s> } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( isAfterLegalize && ! DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDValue NewLd = SDValue ( ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd ; } if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && ( EltVT . getSizeInBits ( ) == <NUM_LIT> ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , LDBase -> getPointerInfo ( ) ,

LDBase -> getAlignment ( ) , false , true , false ) ;


<s> return ( ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode


<s> } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - <NUM_LIT> && vcall_offset < <NUM_LIT> * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function )


<s> return new <ISA_LIT>Disassembler ( STI ,


<s> MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start ,


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . getIntVal ( ) >= NumLanes ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * Lane = MCConstantExpr :: Create ( Parser . getTok ( ) . getIntVal ( ) , getContext ( ) ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok (


<s> assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false ) ; return getTargetVShiftByConstNode ( <ISA_LIT>Opc , SDLoc ( N ) , VT . getSimpleVT ( ) , N0 , EltBits [ <NUM_LIT> ] . getZExtValue ( ) , DAG ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo (


<s> return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI ,


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return


<s> if ( DoDump ) { DOUT << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << UserOffset << <STR_LIT> << CPEOffset << <STR_LIT> <<

int ( CPEOffset - UserOffset ) << <STR_LIT> << * MI ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; bool Changed = false ; SmallVector < int , <NUM_LIT> > MaskVec ; SVOp -> getMask ( MaskVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++


<s> Offset &= <NUM_LIT> ; Reg = <STR_LIT> ; MCInsts . resize ( <NUM_LIT> ) ; MCInsts [ <NUM_LIT> ] . setOpcode ( <STR_LIT> ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateImm ( Hi ) ) ; MCInsts [ <NUM_LIT> ] . setOpcode ( <STR_LIT> ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } Sw . setOpcode ( <STR_LIT> ) ; Sw . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Sw . addOperand ( MCOperand :: CreateReg ( Reg


<s> static MCStreamer * create<ISA_LIT>NullStreamer ( MCContext & Ctx ) { MCStreamer * S = llvm :: createNullStreamer ( Ctx ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std


<s> auto * Exp = new <STR_LIT> ( S . getContext ( ) , std :: move ( RegInfo ) , std :: move ( InstInfo ) ) ; S . setNaClExpander


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP (

tocrel_base , <NUM_LIT> , <NUM_LIT> ) , INTVAL ( tocrel_offset ) , mode ) ) ) ;


<s> return __builtin_aarch64_uqshl_nv8hi_uus ( __a ,


<s> void arm_pr_long_calls ( struct cpp_reader * pfile ATTRIBUTE_UNUSED


<s> static DecodeStatus DecodeHI32DSPRegisterClass ( MCInst & Inst , unsigned RegNo ,

uint64_t Address , const void * Decoder ) {


<s> if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken


<s> if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MI . setDesc ( TII ->


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>elTarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackendEB32 ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>AsmBackendEL32


<s> void addUImm3Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue


<s> ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; return


<s> return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return


<s> MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count ) ; if ( ! IsDo ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; if ( InsertPt != Start ) LoLoop . ToRemove . insert ( InsertPt ) ; LoLoop . ToRemove . insert ( Start ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op


<s> __v2di mask = __extension__ ( __v2di ) { ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m128i ) __builtin_ia32_gathersiv2di ( src , base , ( __v4si ) index , mask ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ]


<s> int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getBitcast ( FpVT , V1 ) ; V2 = DAG . getBitcast ( FpVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I32VectorShuffle ( Op , V1 , V2 , Subtarget


<s> return ( int32x2_t ) __builtin_neon_vaddhnv2di ( __a ,


<s> while ( * isa_bits != isa_nobit ) bitmap_set_bit ( isa


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ; if ( Result . getNode ( ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits0 ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits1 ; if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) <STR_LIT> :: write < uint32_t > (


<s> GlobalBaseReg = <NUM_LIT> ; <ISA_LIT>SubTarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget


<s> static inline unsigned getShiftValue ( unsigned Imm ) { return Imm &


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) ==


<s> static __inline__ double __fnabs ( double x ) { double r


<s> for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( NElts + i ) ; for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back


<s> rtx arm_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode ,


<s> return parseAddress ( Operands , BDMem ,


<s> return by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + <NUM_LIT> , op ) < ( ! speed_p ? <NUM_LIT> : ( align >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; case STORE_BY_PIECES : case SET_BY_PIECES : return by_pieces_ninsns ( size , align , STORE_MAX_PIECES + <NUM_LIT> , op ) < ( !


<s> case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR


<s> return __builtin_mve_vbrsrq_n_sv16qi ( __a ,


<s> op0 = sparc_compare_op0 ; op1 = sparc_compare_op1 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT && op1 == const0_rtx && v9_regcmp_p ( compare_code ) ) { if ( compare_code == NE && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && rtx_equal_p ( op0 , operands [ <NUM_LIT> ] ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , operands [ <NUM_LIT> ] ) ) ) ; return <NUM_LIT> ; } if ( reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( sparc_compare_op0 ) ) ; emit_move_insn ( op0 , sparc_compare_op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ <NUM_LIT> ] ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , operands [ <NUM_LIT> ] ) ) ) ; return <NUM_LIT> ; } else { operands [ <NUM_LIT> ] = gen_compare_reg ( compare_code , op0 , op1 ) ; switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case CCmode : case CCXmode : case CCFPEmode : case CCFPmode : break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ]


<s> pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && sparc_pic_register_p ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) return orig ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset


<s> void setMaxDisp ( unsigned Val ) { MaxDisp =


<s> case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass *


<s> OS << markup ( <STR_LIT> ) << getRegisterName ( RegNo ) <<


<s> bool <ISA_LIT>InstructionSelector :: validOpRegPair ( MachineRegisterInfo & MRI , unsigned LHSReg

, unsigned RHSReg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const {


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi (


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; Register Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset (


<s> NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } else if ( ! isSub && BaseReg == <STR_LIT> ) { if ( ! isMul4 ) { Bytes &= ~ <NUM_LIT> ; ExtraOpc = <STR_LIT> ; } NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = <STR_LIT> ; } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( MRI . isLowRegister ( DestReg ) && MRI . isLowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; BuildMI ( MBB , MBBI , dl , TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg =


<s> return DecodeSPRRegisterClass ( Inst , RegNo ,


<s> static void def_or_undef_macro ( struct cpp_reader * pfile , const char *


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Vec . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) < <NUM_LIT> ) { DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ,


<s> <ISA_LIT>64ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( VRM && VRM -> hasPhys ( MO . getReg ( ) ) ) { Register PhysReg = VRM -> getPhys ( MO . getReg ( ) ) ; if ( <STR_LIT> . contains ( PhysReg ) ) return & <STR_LIT> ; assert ( <STR_LIT> . contains ( PhysReg ) && <STR_LIT> ) ; return &


<s> return new <ISA_LIT>OptimizePICCall (


<s> return ( __m256i ) __builtin_ia32_psubsb256_mask ( ( __v32qi ) __A , ( __v32qi )


<s> static DecodeStatus DecodeCacheOp ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Hint = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTPOP ( SDValue Op , SelectionDAG & DAG ) const { if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) return SDValue ( ) ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL (


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > (


<s> MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return EmitF128CSEL ( MI , BB ) ; case TargetOpcode :: STACKMAP : case TargetOpcode :: PATCHPOINT : return emitPatchPoint ( MI ,


<s> CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; for ( Function :: const_arg_iterator i = CallerF -> arg_begin ( ) , e = CallerF -> arg_end ( ) ; i != e ; ++ i ) if ( i -> hasByValAttr ( ) ) return false ; if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CCMatch ) return true ; return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc (


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_2 ; else EFlags |= ELF :: EF_MIPS_ARCH_1 ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_MACH_OCTEON ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_NAN2008 ; MCA . setELFHeaderEFlags


<s> return ( __m64 ) __builtin_ia32_punpckhbw ( ( __v8qi )


<s> for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ) splitMBB ( I ++ ) ; MF -> RenumberBlocks ( ) ; MBBInfos . clear ( ) ; MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const { return Subtarget -> isTargetNaCl


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; auto & TD = DAG . getDataLayout ( ) ; EVT PTy = getPointerTy ( TD ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( isPositionIndependent ( ) || ABI . IsN64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static bool aarch64_use_blocks_for_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , const_rtx x ATTRIBUTE_UNUSED ) { return


<s> if ( KillsOp0 ) { moveToTop ( Op0 , I ) ; TOS = Op0 ; } else if ( KillsOp1 ) { moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable


<s> case MI : return <STR_LIT> ; case PL : return <STR_LIT> ; case VS : return <STR_LIT> ; case VC : return <STR_LIT> ; case HI : return <STR_LIT> ; case LS : return <STR_LIT> ; case GE : return <STR_LIT> ; case LT : return <STR_LIT> ; case GT : return <STR_LIT> ; case LE : return <STR_LIT> ; case AL : return <STR_LIT> ; case NV : return <STR_LIT>


<s> for ( const MachineInstr & MI : MBB . terminators ( ) ) { bool BreakNext = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( )


<s> return const0_rtx ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate )


<s> MVT getPointerRangeTy ( const DataLayout & DL , uint32_t AS = <NUM_LIT> ) const override { return <STR_LIT> ( <NUM_LIT>


<s> rtx addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; if ( ! REG_P ( addr_rtx


<s> return THM2_MAX_FWD_BRANCH_OFFSET ; } else { return THM_MAX_FWD_BRANCH_OFFSET


<s> return ( __m64 ) __builtin_ia32_phaddsw ( ( __v4hi


<s> if ( Subtarget . hasVBMI2 ( ) && EltSizeInBits > <NUM_LIT> ) { if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( IsCstSplat ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( EltSizeInBits ) ; SDValue Imm = DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ; return getAVX512Node ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , { Op0 , Op1 , Imm } , DAG , Subtarget ) ; } return getAVX512Node ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , { Op0 , Op1 , Amt } , DAG , Subtarget ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( IsCstSplat ) return SDValue ( ) ; SDValue AmtMask = DAG . getConstant ( EltSizeInBits - <NUM_LIT> , DL , VT ) ; SDValue AmtMod = DAG . getNode ( <STR_LIT> , DL , VT , Amt , AmtMask ) ; bool IsCst = <STR_LIT> ( AmtMod . getNode ( ) ) ; if ( IsCst && EltSizeInBits == <NUM_LIT> ) return SDValue ( ) ; unsigned ShiftOpc = IsFSHR ? <STR_LIT> : <STR_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ExtSVT = <STR_LIT> ( <NUM_LIT> * EltSizeInBits ) ; MVT ExtVT = <STR_LIT> ( ExtSVT , NumElts / <NUM_LIT> ) ; if ( ( VT . is256BitVector ( ) && ( ( Subtarget . hasXOP ( ) && EltSizeInBits < <NUM_LIT> ) || ! Subtarget . hasAVX2 ( ) ) ) || ( VT . is512BitVector ( ) && ! Subtarget . useBWIRegs ( ) && EltSizeInBits < <NUM_LIT> ) ) { Op = DAG . getNode ( Op . getOpcode ( ) , DL , VT , Op0 , Op1 , AmtMod ) ; return splitVectorOp ( Op , DAG ) ; } if ( supportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , ShiftOpc ) ) { int ScalarAmtIdx = - <NUM_LIT> ; if ( SDValue ScalarAmt = DAG . getSplatSourceVector ( AmtMod , ScalarAmtIdx ) ) { if ( EltSizeInBits == <NUM_LIT> ) return SDValue ( ) ; SDValue Lo = DAG . getBitcast ( ExtVT , getUnpackl ( DAG , DL , VT , Op1 , Op0 ) ) ; SDValue Hi = DAG . getBitcast ( ExtVT , getUnpackh ( DAG , DL , VT , Op1 , Op0 ) ) ; Lo = getTargetVShiftNode ( ShiftOpc , DL , ExtVT , Lo , ScalarAmt , ScalarAmtIdx , Subtarget ,


create<ISA_LIT>RetpolineThunksPass ( ) {


<s> uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; assert ( DestEncoding % NumRegs == <NUM_LIT> && SrcEncoding % NumRegs == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned SubReg = <NUM_LIT> ; SubReg != NumRegs ; ++ SubReg ) { const MachineInstrBuilder MIB = BuildMI ( MBB , I ,


<s> const <ISA_LIT>AnalyzeImmediate :: InstSeq & <ISA_LIT>AnalyzeImmediate :: Analyze ( uint64_t Imm , unsigned Size , bool LastInstrIsADDiu ) { this -> Size = Size ; if ( Size == <NUM_LIT> ) { ADDiu = <STR_LIT> ; ORi = <STR_LIT> ; SLL = <STR_LIT> ; LUi = <STR_LIT> ; } else { ADDiu = <STR_LIT> ; ORi = <STR_LIT> ; SLL =


<s> static __inline__ double __fmul ( double a , double b ) { double d


<s> type = mep_pragma_lex ( & val ) ; switch ( type ) { case CPP_NUMBER : if ( ! tree_fits_uhwi_p ( val ) ) break ; i = tree_to_uhwi ( val ) ; if ( i == <NUM_LIT> ) target_flags &= ~ MASK_64BIT_CR_REGS ; else if ( i == <NUM_LIT> ) target_flags |= MASK_64BIT_CR_REGS ; else break ; targetm . init_builtins ( ) ; if ( i != <NUM_LIT> && i != <NUM_LIT> ) break ; type = mep_pragma_lex ( & val ) ; if ( type != CPP_PRAGMA_EOL ) warning ( <NUM_LIT>


<s> assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> (


<s> MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> || ArgVT == <STR_LIT> || ! VA . isRegLoc ( ) || VA . needsCustom ( ) ) return false ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) return false ; } NumBytes = CCInfo . getNextStackOffset ( ) ; NumBytes = std :: max ( NumBytes , LinkageSize + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameSetupOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; unsigned NextGPR = <STR_LIT> ; unsigned NextFPR = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt : { llvm_unreachable ( <STR_LIT> ) ; break ; } } unsigned ArgReg ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { ArgReg = NextFPR ++ ; if ( CC != CallingConv :: Fast ) ++ NextGPR ; } else ArgReg = NextGPR ++ ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ArgReg ) . addReg ( Arg ) ; RegArgs . push_back ( ArgReg


<s> return ( __m256i ) __builtin_ia32_loaddqudi256_mask ( ( const long long * ) __P , ( __v4di ) __W , ( __mmask8


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ,


<s> if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , ThreshVal ) ; Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Value = DAG . getSelect ( DL , TheVT , Cmp , Value , Sub ) ; } MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MPI ) ; SDVTList Tys = DAG . getVTList ( TheVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; unsigned FLDSize = TheVT . getStoreSize ( ) ; assert ( FLDSize <= MemSize && <STR_LIT> ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , FLDSize ,


<s> else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> ,


<s> bool <ISA_LIT>TargetLowering :: DoesCalleeRestoreStack ( CallingConv :: ID CallCC


<s> static void emit_cfa_restores ( rtx cfa_restores ) { rtx_insn * insn = get_last_insn ( ) ; rtx * loc = & REG_NOTES ( insn ) ; while ( * loc ) loc = & XEXP ( * loc , <NUM_LIT> ) ; * loc = cfa_restores


<s> int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( Mask . size ( ) / <NUM_LIT> ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) || ( HalfIdx1 % <NUM_LIT> == <NUM_LIT> ) || ( HalfIdx2

% <NUM_LIT> == <NUM_LIT> ) ) return SDValue ( ) ;


<s> Opc = getTargetVShiftUniformOpcode ( Opc , true ) ; if ( SVT == <STR_LIT> ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else if ( ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ( ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> || ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) ) { ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; MVT AmtTy = ShAmt . getSimpleValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , AmtTy , ShAmt ) ; if ( Subtarget . hasSSE41 ( ) ) ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; else { SDValue ByteShift = DAG . getConstant ( ( <NUM_LIT> - AmtTy . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast (


<s> unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; SPAdj -= MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI -> isCall ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> naked_p = <NUM_LIT> ; machine -> fp_as_gp_p = <NUM_LIT> ; return machine


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( create<ISA_LIT>BranchTargetsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass (


<s> MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case RIT_<ISA_LIT>_64_Subtractor : { RelocationRef RelNext ; Obj -> getRelocationNext ( Rel . getRawDataRefImpl ( ) , RelNext ) ; RelocationEntry RENext = Obj -> getRelocation ( RelNext . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != RIT_<ISA_LIT>_64_Unsigned ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = RelNext . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( RSym -> isVariable ( ) == false ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ; const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; break ; } default : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; } return


<s> reportParseError ( <STR_LIT> ) ; return false ; } if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setNoMacro ( ) ; getTargetStreamer ( ) . emitDirectiveSetNoMacro ( ) ; Parser . Lex ( ) ; return


<s> void addRegQFRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( AddOpcode ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( - <NUM_LIT> ) ; MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII -> getRegisterInfo ( ) ) ; MI -> eraseFromParent (


<s> ~ <ISA_LIT>AsmBackend ( ) override { delete STI


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { SDValue SrcOp = Ops [ i ] ; OneUseConstantOp |= SrcOp . hasOneUse ( ) ; if ( ! getTargetConstantBitsFromNode ( SrcOp , MaskSizeInBits , UndefEltsOps [ i ] , RawBitsOps [ i ] ) ) return SDValue ( ) ; } if ( ! OneUseConstantOp && ! HasVariableMask ) return SDValue ( ) ; APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT> ) ; APInt ConstantElts ( NumMaskElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > ConstantBitData ( NumMaskElts , APInt :: getNullValue ( MaskSizeInBits ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { UndefElts . setBit ( i ) ; continue ; } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits ) { ZeroElts . setBit ( i ) ; continue ; } ConstantElts . setBit ( i ) ; ConstantBitData [ i ] = Bits ; } assert ( ( UndefElts | ZeroElts | ConstantElts ) . isAllOnesValue ( ) ) ; MVT MaskSVT ; if ( VT . isFloatingPoint ( ) && ( MaskSizeInBits == <NUM_LIT> || MaskSizeInBits == <NUM_LIT> ) ) MaskSVT = <STR_LIT> ( MaskSizeInBits ) ; else MaskSVT = <STR_LIT> ( MaskSizeInBits ) ; MVT MaskVT = <STR_LIT> ( MaskSVT , NumMaskElts ) ; SDLoc DL ( Root )


<s> CommentString = <STR_LIT> ; PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; UseDataRegionDirectives = true


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > <NUM_LIT> && ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; } if ( ISA_HAS_MSA ) { if ( all_same ) { rtx same = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; rtx temp , temp2 ; if ( CONST_INT_P ( same ) && nvar == <NUM_LIT> && mips_signed_immediate_p ( INTVAL ( same ) , <NUM_LIT> , <NUM_LIT> ) ) { switch ( vmode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : temp = gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , <NUM_LIT> ) ) ; emit_move_insn ( target , temp ) ; return ; default : gcc_unreachable ( ) ; } } temp = gen_reg_rtx ( imode ) ; if ( imode == GET_MODE ( same ) ) temp2 = same ; else if ( GET_MODE_SIZE ( imode ) >= UNITS_PER_WORD ) temp2 = simplify_gen_subreg ( imode , same , GET_MODE ( same ) , <NUM_LIT> ) ; else temp2 = lowpart_subreg ( imode , same , GET_MODE ( same ) ) ; emit_move_insn ( temp , temp2 ) ; switch ( vmode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : mips_emit_move ( target , gen_rtx_VEC_DUPLICATE ( vmode , temp ) ) ; break ; case V4SFmode : emit_insn ( gen_msa_splati_w_f_scalar ( target , temp ) ) ; break ; case V2DFmode : emit_insn ( gen_msa_splati_d_f_scalar ( target , temp ) ) ; break ; default : gcc_unreachable ( ) ; } } else { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) RTVEC_ELT ( vec , i ) = CONST0_RTX ( imode ) ; emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx temp = gen_reg_rtx ( imode ) ; emit_move_insn ( temp , XVECEXP ( vals , <NUM_LIT> , i ) ) ; switch ( vmode )


<s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister (


<s> const <ISA_LIT>Subtarget & SubtargetA = a . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>Subtarget & SubtargetB = b . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SubtargetA . hasV8_3aOps ( ) == SubtargetB . hasV8_3aOps


<s> if ( incoming ) fputs ( <STR_LIT> , stderr ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , tree_code_name [ ( int )


<s> case <STR_LIT> : case <STR_LIT> : UseOp = MI -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI -> getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT> ,


<s> if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( VT . is128BitVector ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl


<s> return false ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Offset . getValueType ( ) ) ) return SDValue ( ) ; EVT HwSrcVt = getSVEContainerType ( SrcVT ) ; SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) ,


<s> rtx patt = PATTERN ( last ) ; if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt ,


<s> static rtx strip_offset_and_salt ( rtx addr , poly_int64 *


<s> SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) , Mask ) ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> :


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering


<s> void Emitter < CodeEmitter > :: emitMiscInstruction ( const MachineInstr & MI ) { unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; emitWordLE (


<s> DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old


<s> MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; LastWasBL8_ELF = ( Opcode == <STR_LIT> ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) HasCTRSet = true ; if ( isStore && NumStores < <NUM_LIT> && !


<s> static StringRef computeDataLayout ( const Triple & TT ) { return <STR_LIT>


<s> return ( __m512d ) __builtin_ia32_sqrtpd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( )


<s> static DecodeStatus DecodeGR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printMemOperandEA ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> void <ISA_LIT>CodeEmitter :: expandACCInstr ( MachineBasicBlock :: instr_iterator MI , MachineBasicBlock & MBB , unsigned Opc ) const { BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , II -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg

( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> memset ( cum , <NUM_LIT> , sizeof ( * cum ) ) ; cum -> prototype = ( fntype && prototype_p ( fntype )


<s> Value * Op1 = II . getArgOperand ( <NUM_LIT> ) ; Value * Op2 = II . getArgOperand ( <NUM_LIT> ) ; Type * RetTy = II . getType ( ) ; Type * OpTy = Op1 -> getType ( ) ; assert ( RetTy -> getStructElementType ( <NUM_LIT> ) -> isIntegerTy ( <NUM_LIT> ) && RetTy -> getStructElementType ( <NUM_LIT> ) == OpTy && OpTy == Op2 -> getType ( ) && <STR_LIT> ) ; if ( match ( CarryIn , PatternMatch :: m_ZeroInt ( ) ) ) { Value * UAdd = Builder . CreateIntrinsic ( <STR_LIT> , OpTy , { Op1 , Op2 } ) ; Value * UAddResult = Builder . CreateExtractValue ( UAdd , <NUM_LIT> ) ; Value * UAddOV = Builder . CreateZExt ( Builder . CreateExtractValue ( UAdd , <NUM_LIT> ) , Builder . getInt8Ty ( ) ) ; Value * Res = UndefValue :: get ( RetTy ) ; Res = Builder . CreateInsertValue ( Res , UAddOV


<s> long l ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; return UNSIGNED_INT_FITS_N_BITS ( l , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } return ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_LOW ( op ) , <NUM_LIT> ) && UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_HIGH ( op ) ,


<s> return ( __m256i ) __builtin_ia32_broadcasti32x4_256_mask ( ( __v4si ) __A , ( __v8si )

_mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! TARGET_64BIT ) return va_list_type_node ; gcc_assert ( fndecl != NULL_TREE ) ; if ( ix86_function_abi ( ( const_tree ) fndecl ) == MS_ABI ) return ms_va_list_type_node ; else return


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { TargetTransformInfo :: getAnalysisUsage


<s> if ( Idx == SM_SentinelUndef ) return DAG . getUNDEF ( EltVT ) ; assert ( <NUM_LIT> <= Idx && Idx < ( int ) ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; unsigned AllowedUses = ( ShuffleOps . size ( ) > <NUM_LIT> && ShuffleOps [ <NUM_LIT> ] == ShuffleOps [ <NUM_LIT> ] ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI =


<s> return ( __m128 ) __builtin_ia32_minss ( ( __v4sf ) __A ,


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I


<s> OutStreamer -> EmitRawText ( <STR_LIT> ) ; taint_flag ^= <NUM_LIT> ; OutStreamer -> EmitRawText ( <STR_LIT> + std :: to_string ( taint_flag ) ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; AsmPrinter :: EmitFunctionEntryLabel ( ) ; std :: string fname = MF -> getName ( ) . str ( ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> + fname + <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( INS ( <STR_LIT> ) ) ; shadow_stack_push_count =


<s> if ( V -> getType ( ) -> isIntegerTy ( ) ) return V ; if ( VectorType * VecTy = dyn_cast < VectorType > ( V -> getType ( ) ) ) { LLVMContext & Ctx = IRB . getContext ( ) ; Type * EltTy = VecTy -> getElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) { uint32_t EltSize = DL ->


<s> FunctionPass * llvm :: create<ISA_LIT>InsertPrefetchPass (


<s> static void lowerMUL_LOHI32 ( SelectionDAG & DAG , SDLoc DL , unsigned Extend , SDValue Op0 , SDValue Op1 , SDValue & Hi , SDValue & Lo ) { Op0 = DAG . getNode ( Extend , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT>


<s> if ( auto ShiftedVal = getShiftedVal < Shift > ( ) ) { Inst . addOperand ( MCOperand :: createImm ( - ShiftedVal -> first ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) && Subtarget -> hasFP64 ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( FP ) ) ; updateValueMap ( I , ResultReg ) ; return true


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printBDRAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { unsigned Base = MI -> getOperand ( OpNum ) . getReg ( ) ; uint64_t Disp = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; unsigned Length = MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) ; O << Disp << <STR_LIT> << getRegisterName ( Length ) ; if ( Base ) O << <STR_LIT> << getRegisterName (


<s> unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; case


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const override { poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> )


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , - <STR_LIT> , Align ( <NUM_LIT> ) , false ) { RegSpillOffsets . grow ( <STR_LIT>


<s> return __builtin_mve_vcreateq_sv8hi ( __a ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT>


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . Num = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc , <STR_LIT> ) ; case Match_MRS : return Error ( Loc , <STR_LIT> ) ; case Match_MSR : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationEven : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationOdd : return Error ( Loc , <STR_LIT> ) ; case Match_MnemonicFail : { std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , ComputeAvailableFeatures ( STI -> getFeatureBits ( ) ) ) ; return Error ( Loc , <STR_LIT> + Suggestion ) ; } case Match_InvalidSVEPattern : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEPredicateAnyReg : case Match_InvalidSVEPredicateBReg : case Match_InvalidSVEPredicateHReg : case Match_InvalidSVEPredicateSReg : case Match_InvalidSVEPredicateDReg : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEPredicate3bAnyReg : case Match_InvalidSVEPredicate3bBReg : case


<s> switch ( Type ) { case FrameHelperType :: Prolog : RegStream << <STR_LIT> ; break ; case FrameHelperType :: PrologFrame : RegStream << <STR_LIT> << FpOffset << <STR_LIT> ; break ; case FrameHelperType :: Epilog : RegStream << <STR_LIT> ; break ; case FrameHelperType :: EpilogTail : RegStream << <STR_LIT> ; break ; } for ( auto Reg : Regs ) RegStream << <ISA_LIT>InstPrinter :: getRegisterName


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo


<s> int factor ; unsigned int nelts_per_vq ; if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ; if ( factor < <NUM_LIT> ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , operands , -


<s> if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand


<s> MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; if ( PrevI == MBB -> begin ( ) ) continue ; MachineInstr * AddrMI = -- PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; MachineInstr * LeaMI = -- PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk )


<s> static void aarch64_conditional_register_usage ( void ) { int i ; if ( ! TARGET_FLOAT ) { for ( i = V0_REGNUM ; i <= V31_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ]


<s> else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } return


<s> bool isLd = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base ) return false ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool DoMerge = false ; <STR_LIT> AddSub = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , AddSub ) ; MBB . erase ( PrevMBBI ) ; } } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , AddSub ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; } } if ( ! DoMerge ) return false ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { int Offset = AddSub == <STR_LIT> ? -


<s> static bool isStartChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == std :: numeric_limits < uint64_t > ::


<s> rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: STACKMAP : NumBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NumBytes = <NUM_LIT>


<s> assert ( ArgLocs . size ( ) == Args . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MIRBuilder . getMBB ( ) . addLiveIn ( VA . getLocReg ( ) ) ; MIRBuilder . buildInstr ( TargetOpcode :: COPY , VRegs [ i ] , VA . getLocReg ( ) ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; } } return


<s> cost += MAX ( MEMORY_MOVE_COST ( mode , class1 , <NUM_LIT> ) , MEMORY_MOVE_COST ( mode , class1 , <NUM_LIT> ) ) ; cost += MAX ( MEMORY_MOVE_COST ( mode , class2 , <NUM_LIT> ) , MEMORY_MOVE_COST ( mode , class2 , <NUM_LIT> ) ) ; if ( CLASS_MAX_NREGS ( class1 , mode ) > CLASS_MAX_NREGS ( class2 , mode ) ) cost += <NUM_LIT> ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += <NUM_LIT> ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ix86_cost -> mmxsse_to_integer ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) return ix86_cost -> sse_move ; if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> mmx_move ; return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB


<s> return ( ( vec_double2 ) ( si_dfms ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c


<s> ScheduleHazardRecognizer * <ISA_LIT>BaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new <ISA_LIT>HazardRecognizer ( II


<s> MCDataFragment * DF = getOrCreateDataFragment ( ) ; DF -> getFixups ( ) . push_back ( MCFixup :: Create ( DF -> getContents ( ) . size ( ) , PersonalityRef , MCFixup

:: getKindForSize ( <NUM_LIT> , false ) ) ) ;


<s> void EmitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg

) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , <NUM_LIT> ) ; switch ( unspec_val ) { case UNSPEC_PACISP : return


<s> } if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_splat_v2di ( tmp_altivec , tmp_gpr ) ) ; else if ( can_create_pseudo_p ( ) ) emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_gpr , tmp_gpr ) ) ; else { rtx tmp_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; emit_move_insn ( tmp_di , tmp_gpr ) ; emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_di , tmp_di ) ) ; } switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_vslo_v2df ( dest , src , tmp_altivec ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_vslo_v2di ( dest , src , tmp_altivec ) ) ; return ; case E_V4SFmode : { rtx tmp_altivec_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; rtx tmp_altivec_v4sf = gen_rtx_REG ( V4SFmode , REGNO ( tmp_altivec ) ) ; rtx src_v2di = gen_rtx_REG ( V2DImode , REGNO ( src ) ) ; emit_insn ( gen_vsx_vslo_v2di ( tmp_altivec_di , src_v2di , tmp_altivec ) ) ; emit_insn ( gen_vsx_xscvspdp_scalar2 ( dest , tmp_altivec_v4sf ) ) ; return ; } case E_V4SImode : case E_V8HImode : case E_V16QImode : { rtx tmp_altivec_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; rtx src_v2di = gen_rtx_REG ( V2DImode , REGNO ( src ) ) ; rtx tmp_gpr_di = gen_rtx_REG ( DImode , REGNO ( dest ) ) ; emit_insn ( gen_vsx_vslo_v2di ( tmp_altivec_di , src_v2di , tmp_altivec ) ) ; emit_move_insn ( tmp_gpr_di , tmp_altivec_di ) ; emit_insn ( gen_lshrdi3 ( tmp_gpr_di , tmp_gpr_di , GEN_INT ( <NUM_LIT> - bits_in_element ) ) ) ; return ; } default : gcc_unreachable ( ) ; } return ; } else gcc_unreachable


<s> static bool isFPCopy ( MachineInstr * MI ) { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> )


<s> Inst . addOperand ( MCOperand :: CreateImm ( getFPImm ( ) )


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_storeu_si32 ( void * __P , __m128i __B ) { * ( __m32_u * ) __P = ( __m32 ) ( (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindReg , StartLoc , EndLoc ) ; Op -> Reg . Kind =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddr ( P , N . getOperand ( <NUM_LIT> ) , Base , Scale , Index , Disp , Segment ) ; return false


<s> bool aarch64_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type ? ( INTEGRAL_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) || POINTER_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || SCALAR_FLOAT_MODE_P ( mode ) ) ) return false ; return


<s> InfixCalculatorTok StackOp = InfixOperatorStack . pop_back_val ( ) ; if ( StackOp != IC_LPAREN && StackOp != IC_RPAREN ) PostfixStack . push_back ( std :: make_pair ( StackOp , <NUM_LIT> ) ) ; } if ( PostfixStack . empty ( ) ) return <NUM_LIT> ; SmallVector < ICToken , <NUM_LIT> > OperandStack ; for ( unsigned i = <NUM_LIT> , e = PostfixStack . size ( ) ; i != e ; ++ i ) { ICToken Op = PostfixStack [ i ] ; if ( Op . first == IC_IMM || Op . first == IC_REGISTER ) { OperandStack . push_back ( Op ) ; } else { assert ( OperandStack . size ( ) > <NUM_LIT> && <STR_LIT> ) ; int64_t Val ; ICToken Op2 = OperandStack . pop_back_val ( ) ; ICToken Op1 = OperandStack . pop_back_val ( ) ; switch ( Op . first ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case IC_PLUS : Val = Op1 . second + Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_MINUS : Val = Op1 . second - Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_MULTIPLY : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM &&


<s> BSICInst . setOpcode ( <STR_LIT> ) ; BSICInst . addOperand ( R1 ) ; BSICInst . addOperand ( R2 ) ; MCOperand czero = MCOperand :: createImm ( <NUM_LIT> ) ; BSICInst . addOperand ( czero ) ; BSICInst . addOperand ( czero ) ; OutStreamer . emitInstruction ( BSICInst


<s> if ( VT . isVector ( ) && ST -> hasNEON ( ) ) { SDValue X = N -> getOperand ( <NUM_LIT> ) ; SDValue NX = DAG . getNode ( <STR_LIT> , dl , VT , getZeroVector ( VT , DAG , dl ) , X ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , dl , VT , X , NX ) ; EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; SDValue Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Bits ) ; } if ( ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) && ( N -> getOpcode ( ) == <STR_LIT> ) ) { unsigned NumBits = ElemTy . getSizeInBits ( ) ; SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl ,


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) return true ; return false


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c )


<s> bool llvm :: HasLowerConstantMaterializationCost ( unsigned Val1 , unsigned Val2 , const <ISA_LIT>Subtarget * Subtarget , bool ForCodesize ) { unsigned Cost1 = ConstantMaterializationCost ( Val1 , Subtarget , ForCodesize ) ; unsigned Cost2 = ConstantMaterializationCost ( Val2 , Subtarget , ForCodesize


<s> ShAmt = getShuffleVectorZeroOrUndef ( Op0 , <NUM_LIT> , true , Subtarget , DAG ) ; } else { SmallVector < SDValue , <NUM_LIT> > ShOps ; ShOps . push_back ( ShAmt ) ; if ( SVT == <STR_LIT> ) { ShOps . push_back ( DAG . getConstant ( <NUM_LIT> , dl , SVT ) ) ; ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; } ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; MVT BVT = SVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getBuildVector ( BVT , dl , ShOps ) ; } MVT EltVT = VT . getVectorElementType ( ) ; MVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits ( ) ) ; ShAmt = DAG . getBitcast ( ShVT , ShAmt


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + DecVal + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand (

MCOperand :: createImm ( isNeg ? - DecVal : DecVal ) ) ;


<s> inline bool isThumbImm16ShiftedVal ( unsigned V ) { V = ( ~ <NUM_LIT> << getThumbImm16ValShift ( V ) ) & V ; return V == <NUM_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm


<s> static __inline unsigned long long sh_media_MCMPEQ_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode


<s> if ( ! x || ! INSN_P ( x ) ) return false ; rtx pat = PATTERN ( x ) ; if ( GET_CODE ( pat ) == SET ) { rtx tmp = XEXP ( pat , <NUM_LIT> ) ; if ( tmp && ( ( GET_CODE ( tmp ) == UNSPEC && XINT ( tmp , <NUM_LIT> ) == UNSPEC_PAC_NOP ) || ( GET_CODE ( tmp ) == UNSPEC_VOLATILE && XINT ( tmp , <NUM_LIT> ) == VUNSPEC_PACBTI_NOP ) ) ) return true ; } return false


<s> SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> SDValue Elt = DAG . getConstant ( Val , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , &


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr


<s> SDLoc DL ( Op ) ; SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true


<s> MCRegister <ISA_LIT>ElfTargetObjectFile :: getStaticBase


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; return


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! Generated . parseCommandLineOption ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned SHDOp = ( IsFSHR


_mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = ExpandVectorExtension ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG ,


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const <ISA_LIT>InstrInfo * AAII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII )


<s> auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++


<s> <STR_LIT> llvm :: getInstrPredicate ( const MachineInstr * MI , unsigned & PredReg ) { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI -> getOperand ( PIdx +


<s> const auto * GV = GlobalOp . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return true ; auto & TM = ST -> getTargetLowering ( ) -> getTargetMachine ( ) ; unsigned OpFlags = ST -> ClassifyGlobalReference ( GV , TM ) ; if ( OpFlags & <STR_LIT> ) return true ; auto Offset = GlobalOp . getOffset ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { } ) . addGlobalAddress ( GV , Offset , OpFlags | <STR_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { assert ( ! Offset && <STR_LIT> ) ; ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; } MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { ADRP } ) . addGlobalAddress ( GV , Offset , OpFlags | <STR_LIT> | <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true


<s> if ( auto * MS = dyn_cast < MemSetInst > ( II ) ) SetVal = Builder . CreateVectorSplat ( ValTy -> getElementCount ( ) , MS -> getValue ( ) ) ; Value * Zero = ConstantInt :: get ( IdxTy , <NUM_LIT> , false ) ; auto * PredTy = VectorType :: get ( Builder . getInt1Ty ( ) , <NUM_LIT> , true ) ; auto * PredPH = CreateWhile ( <STR_LIT> , PredTy , Zero , Length ) ; Builder . Insert ( PredPH ) ; Builder . SetInsertPoint ( LoopBlock -> getTerminator ( ) ) ; auto * Pred = Builder . CreatePHI ( PredTy , <NUM_LIT> ) ; Pred -> addIncoming ( PredPH , PHBlock ) ; auto * Ind = Builder . CreatePHI ( IdxTy , <NUM_LIT> ) ; Ind -> addIncoming ( Zero , PHBlock ) ; SmallVector < Value * , <NUM_LIT> > Indices = { Ind } ; if ( auto * MC = dyn_cast < MemCpyInst > ( II ) ) { auto SrcAddr = Builder . CreateGEP ( MC -> getRawSource ( ) , Indices ) ; SrcAddr = Builder . CreateBitCast ( SrcAddr , ValTy -> getPointerTo ( ) ) ; SetVal = Builder . CreateMaskedLoad ( SrcAddr , II -> getAlignment ( ) , Pred ) ; } assert ( SetVal && <STR_LIT> ) ; auto * Addr = Builder . CreateGEP ( II -> getRawDest ( ) , Indices ) ; Addr = Builder . CreateBitCast ( Addr , ValTy -> getPointerTo ( ) ) ; Builder . CreateMaskedStore ( SetVal , Addr , II -> getAlignment ( ) , Pred ) ; Value * NextInd = nullptr ; if ( IndexMayOverflow ) { Value * CntVPop = Builder . CreateCntVPop ( Pred , <STR_LIT> ) ; CntVPop = Builder . CreateZExtOrTrunc ( CntVPop , IdxTy ) ; NextInd = Builder . CreateNUWAdd ( Ind , CntVPop ) ; } else { Value * EC = Builder . CreateElementCount ( IdxTy , UndefValue :: get ( ValTy ) ) ; NextInd = Builder . CreateNUWAdd ( Ind , EC ) ; } Ind -> addIncoming ( NextInd , LoopBlock ) ; auto * NextPred = CreateWhile ( <STR_LIT> , PredTy , NextInd , Length ) ; Builder . Insert ( NextPred ) ; Pred -> addIncoming ( NextPred , LoopBlock ) ; Value * Continue = Builder . CreateTest ( TestInst :: FIRST_TRUE , NextPred ) ; Builder . CreateCondBr ( Continue , LoopBlock , ResumeBlock ) ; LoopBlock -> getTerminator ( )


<s> ArrayRef < Node > nodes ( ) const { return makeArrayRef ( Nodes . get ( )