<s> return <ISA_LIT>SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: SExt : return <ISA_LIT>SelectSExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: UIToFP : return <ISA_LIT>SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; Register Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == <STR_LIT> || DstVT . getVectorElementType ( ) ==


<s> unsigned End = KillInst ? KillInstIdx : LastInstIdx ; unsigned OtherEnd = Other -> KillInst ? Other -> KillInstIdx : Other -> LastInstIdx ; return StartInstIdx <= OtherEnd &&


<s> bool ExpandPseudo :: expand ( ) { bool Expanded = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BBEnd = MF


<s> virtual void EmitCFIEndProcImpl ( MCDwarfFrameInfo & Frame ) { Frame . End = ( MCSymbol


<s> while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . isNot ( AsmToken :: Comma ) ) Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex


<s> if ( DisableBackwardSearch ) return false ; RegDefsUses RegDU ( TM ) ; MemDefsUses MemDU ( MBB . getParent ( ) -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot , <NUM_LIT> ) ) ; ++ UsefulSlots ; return true


<s> __builtin_neon_vst1v4si ( ( __builtin_neon_si *


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( VT . SimpleTy , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT>


<s> if ( ! ( getLexer ( ) . is ( AsmToken :: Identifier ) && ( getLexer ( ) . getTok ( ) . getIdentifier ( ) == <STR_LIT> ) ) ) return false ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Z = <STR_LIT> ( <STR_LIT> , StartLoc ) ; return


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment ( )


<s> static rtx mips_expand_builtin_movtf ( enum mips_builtin_type type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree arglist ) { rtx cmp_result , op0 , op1 ; cmp_result = mips_prepare_builtin_target ( icode , <NUM_LIT> , <NUM_LIT> ) ; op0 = mips_prepare_builtin_arg ( icode , <NUM_LIT> , & arglist ) ; op1 = mips_prepare_builtin_arg ( icode , <NUM_LIT> , & arglist ) ; emit_insn ( GEN_FCN ( icode ) ( cmp_result , op0 , op1 ,


<s> getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { s32 , p0 } , { s1 } ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s1 } , { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalFor ( { { s64 , p0 } } ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } , Lower ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . customFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . customForCartesianProduct ( { s1 } , { s32 , s64 } ) ; if ( AEABI ( ST ) ) setFCmpLibcallsAEABI ( ) ; else setFCmpLibcallsGNU ( ) ; getActionDefinitionsBuilder ( G_FPEXT ) . libcallFor ( { { s64


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> return ( vector unsigned int ) __builtin_altivec_vaddcuw ( ( vector signed


<s> bool HasDef = false ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; if ( MO . getReg ( ) != <STR_LIT> ) continue ; if ( ! MO . isDead ( ) ) HasDef = true ; } return HasDef ||


<s> } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( LdSize ) ) ; } else { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn

) . addReg ( <NUM_LIT> ) . addImm ( LdSize ) ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target (


<s> void addMem32Operands ( MCInst & Inst ,


<s> tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type


<s> if ( Base . Reg . getNode ( ) != <NUM_LIT> ) Base . Reg . getNode ( ) -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> << Base . FrameIndex << '\n' ; cerr << <STR_LIT> << Scale << '\n' ; cerr << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> << Disp << '\n' ; cerr << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else cerr << <STR_LIT> ; cerr <<


<s> bool isLeafProc ( ) const { return IsLeafProc


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasE2 ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI ,


<s> while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name


<s> unsigned <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { return <NUM_LIT>


<s> return new <ISA_LIT>FastISel ( funcInfo , libInfo


<s> assert ( isRegBase ( ) && <STR_LIT> ) ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return


<s> bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ; return new ELF<ISA_LIT>AsmBackend ( T , IsLittleEndian ,


<s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , * Subtarget


<s> TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MF -> dump ( )


<s> if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue


<s> DebugLoc dl = Op . getDebugLoc ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Val ) , DAG

. getValueType ( Val . getValueType ( ) ) ) ;


<s> case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_WB : switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ; case PRE_DEC


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg (

<STR_LIT> ) . addImm ( StackSize - <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> patternp = pattern ; encode_pattern_1 (


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> if ( Reg != <STR_LIT> ) return getKillRegState ( true ) ; bool LRLiveIn = MF . getRegInfo ( ) . isLiveIn ( <STR_LIT> ) ; bool LRKill = ! ( LRLiveIn && MF . getFrameInfo (


<s> if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget -> isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 ) ; return SDValue ( Sub . getNode ( ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op


<s> for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( ExperimentalVectorWideningLegalization || NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi


<s> if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return true


<s> if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) return false ; bool IsEVEX_V128 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) ; bool IsEVEX_V256 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ( Desc . TSFlags & <STR_LIT> ) ) ; unsigned NewOpc = <NUM_LIT> ; if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ; if ( usesExtendedRegister ( MI


<s> EVT VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; assert ( VecTy . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SelectBaseMVE_VMLLDAV ( N , Predicated , OpcodesS ,


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M ,


<s> Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg


<s> assert ( Kind == k_Register && <STR_LIT> ) ; return Reg


<s> return ( int32x2_t ) __builtin_aarch64_srshlv2si ( __a ,


<s> if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( Opcode == TargetOpcode :: LOAD_STACK_GUARD ) return false ; if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , CoverageInfo ) ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI , MF ) ; case TargetOpcode :: G_GEP : case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndexOrGep ( I , MRI , MF ) ; case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I ,


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseInstSyncBarrierOptOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; unsigned Opt ; if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; if ( OptStr . equals_lower ( <STR_LIT> ) ) Opt = <STR_LIT> ; else return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return


<s> return ( uint32x2_t ) __builtin_aarch64_umaxpv2si ( ( int32x2_t ) a , ( int32x2_t )


<s> RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM , false ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align ==


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex


<s> MachineSDNode * NewNode = nullptr ; auto Type0 = N -> getValueType ( <NUM_LIT> ) ; auto Type1 = N -> getValueType ( <NUM_LIT> ) ; auto Op0 = N -> getOperand ( <NUM_LIT> ) ; auto Op1 = N -> getOperand ( <NUM_LIT> ) ; auto Op2 = N -> getOperand ( <NUM_LIT> ) ; SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , Op2 } ) ; } ReplaceNode ( N , NewNode


<s> CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment (


<s> static __inline__ double __frsqrte ( double x ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_load_epi32 ( void const * __P ) { return ( __m128i ) ( * ( __v4si * )


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT> ) ; FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize )


<s> static inline bool isThumbImmShiftedVal ( unsigned V ) { V = ( ~ <NUM_LIT> << getThumbImmValShift ( V )


<s> extern __inline __m512i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_loadu_epi32 ( void const * __P ) { return * ( __m512i_u * )


<s> if ( Ty -> isVectorTy ( ) && IsComplex )


<s> return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) | (


<s> bool function_resolver :: require_integer_immediate ( unsigned int argno ) { if ( ! scalar_argument_p (


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI


<s> unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; if ( SrcRegBank != DstRegBank && ( DstSize == <NUM_LIT> && SrcSize == <NUM_LIT> ) ) SrcSize = DstSize = <NUM_LIT> ; return { getMinClassForRegBank ( SrcRegBank , SrcSize , true ) , getMinClassForRegBank ( DstRegBank , DstSize ,


<s> return ( __m128d ) __builtin_ia32_mulsd_mask_round ( ( __v2df ) __A , ( __v2df ) __B , (


<s> virtual const char * getPassName ( ) const { return


<s> case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FMA : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCEIL : case TargetOpcode :: G_FFLOOR : case TargetOpcode :: G_FNEARBYINT : case TargetOpcode :: G_FNEG : case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2 : case TargetOpcode :: G_FSQRT : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FEXP : case TargetOpcode :: G_FRINT : case TargetOpcode :: G_INTRINSIC_TRUNC : case TargetOpcode :: G_INTRINSIC_ROUND : case TargetOpcode :: G_FMAXNUM : case TargetOpcode


<s> __builtin_ia32_storedqu256 ( ( char * ) __P , ( __v32qi )


<s> Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load ,


<s> unsigned ExtOp = <NUM_LIT> ; switch ( LD -> getExtensionType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : ExtOp = <STR_LIT> ; break ; case <STR_LIT> : ExtOp = <STR_LIT> ; break ; } <STR_LIT> MemType = LD -> getMemoryVT ( ) . getSimpleVT (


<s> auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT OpVT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OpVT , Ops ) ; } ; auto BuildPMADDWD = [ & ] ( SDValue Mul ) { SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Madd , DAG . getConstant ( <NUM_LIT> , DL , MAddVT ) ) ; } ; Op0 = BuildPMADDWD ( Op0 ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && canReduceVMulWidth ( Op1 . getNode ( ) , DAG , Mode ) && Mode != MULU16 ) { Op1 = BuildPMADDWD ( Op1 ) ; } return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = Extract -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) . getSizeInBits ( ) > <NUM_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; unsigned BinOp = <NUM_LIT> ; SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD ,


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue ReturnAddress ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } SDNode * St ; if ( Subtarget -> hasV8_3aOps ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else { SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ; St = DAG . getMachineNode ( <STR_LIT> , DL , VT , Chain ) ; } return SDValue ( St ,


<s> const char * arm_gen_far_branch ( rtx * operands , int pos_label , const char * dest , const char * branch_format ) { rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ <NUM_LIT> ] ; char buffer [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , \ CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = arm_strip_name_encoding ( label_buf ) ; rtx dest_label = operands [ pos_label ] ; operands [ pos_label ] = tmp_label ; snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , branch_format , label_ptr ) ; output_asm_insn ( buffer , operands ) ; snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , pos_label , label_ptr ) ; operands [ pos_label ] =


<s> assert ( ( Kind == k_MImmOp ) && <STR_LIT> ) ; return MImm .


<s> if ( ! A ) return nullptr ; } return <ISA_LIT>GenRegisterInfo :: getMatchingSuperRegClass ( A , B


<s> addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> const Constant * C = dyn_cast < Constant > ( V ) ; if ( C && C -> getSplatValue ( ) ) return Optional < int64_t > { C -> getUniqueInteger ( ) . getSExtValue ( ) } ; if ( ! isa < Instruction > ( V ) ) return Optional < int64_t > { } ; const Instruction * I = cast < Instruction > ( V ) ; if ( I -> getOpcode ( ) == Instruction :: Add || I -> getOpcode ( ) == Instruction :: Or || I -> getOpcode ( ) == Instruction :: Mul || I -> getOpcode ( ) == Instruction :: Shl ) { Optional < int64_t > Op0 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; Optional < int64_t > Op1 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 ) return Optional < int64_t > { } ; if ( I -> getOpcode ( ) == Instruction :: Add ) return Optional < int64_t > { Op0 . getValue ( ) + Op1 . getValue ( ) } ; if ( I -> getOpcode ( ) == Instruction :: Mul ) return Optional < int64_t > { Op0 . getValue ( ) * Op1 .


<s> raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str (


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return <NUM_LIT>


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } assert ( ( DestReg != <STR_LIT> || BaseReg == <STR_LIT> ) && <STR_LIT> ) ; if ( ( DestReg == <STR_LIT> ) && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; break ; } bool HasCCOut = true ; int ImmIsT2SO = <STR_LIT> ( ThisVal ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( ImmIsT2SO != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; }


<s> } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; } return


<s> void <ISA_LIT>ELFStreamer :: EmitCFIStartProcImpl ( MCDwarfFrameInfo & Frame ) { Frame . Begin = getContext (


<s> else MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MAI -> addInitialFrameState ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ) ; return MAI


<s> MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB


<s> return ( __m256 ) __builtin_ia32_movshdup256 ( ( __v8sf


<s> } for ( df_ref ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) { if ( NONDEBUG_INSN_P ( DF_REF_INSN ( ref ) ) && ! bitmap_bit_p ( candidates , DF_REF_INSN_UID ( ref ) ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , DF_REF_INSN_UID ( ref ) ) ; bitmap_set_bit ( regs , regno


<s> Inst . addOperand ( MCOperand :: createReg ( CRRegs [ getCRBitMask ( )


<s> unsigned char TargetFlags = <STR_LIT> ; if ( GV -> getValueID ( ) == Value :: FunctionVal ) TargetFlags = <STR_LIT> ; SDValue TargetGlobalAddr = CurDAG -> getTargetGlobalAddress ( GV , SDLoc ( N ) , <STR_LIT> , GA -> getOffset ( ) , TargetFlags ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , TargetGlobalAddr , CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ) ; SDValue op2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( op2 . getOpcode ( ) == <STR_LIT> ) { op2 = CurDAG -> getTargetConstant ( cast < ConstantSDNode > ( op2 . getNode ( ) ) -> getZExtValue (


<s> void sparc_emit_fixunsdi ( rtx * operands , enum machine_mode mode ) { rtx neglab , donelab , i0 , i1 , f0 , in , out , limit ; out = operands [ <NUM_LIT> ] ; in = force_reg ( mode , operands [ <NUM_LIT> ] ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode )


<s> CodeModel :: Model CModel = TM . getCodeModel ( ) ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get

( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ;


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_add_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 =


<s> if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ; GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , is64Bit ( )


<s> bool V1IsUndef = V1 . getOpcode ( ) == <STR_LIT> ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . all ( ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; MVT NewVT = <STR_LIT> ( NewEltVT , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , WidenedMask ) ) ; } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices


<s> if ( Res . getNode ( ) ) return Res ; } if ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) return SDValue ( ) ; assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> ,


<s> virtual unsigned getRelocationInfo ( ) const { return <NUM_LIT>


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Result = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = emitSETCC ( DAG , DL , Result . getValue ( <NUM_LIT> ) , CCValid , CCMask ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( )


<s> assert ( getSubtarget ( ) . isTargetDarwin ( ) && <STR_LIT>


<s> static void moxie_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size


<s> case <NUM_LIT> : insn -> regBase = MODRM_REG_AX ; insn -> eaRegBase = EA_REG_AX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_EAX ; insn -> eaRegBase = EA_REG_EAX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_RAX ; insn -> eaRegBase = EA_REG_RAX ; break ; } reg |= rFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; rm |= bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; if ( insn -> vectorExtensionType == TYPE_EVEX ) { reg |= r2FromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; rm |= xFromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; } insn -> reg = ( Reg ) ( insn -> regBase + reg ) ; switch ( insn -> addressSize ) { case <NUM_LIT> : insn -> eaBaseBase = EA_BASE_BX_SI ; switch ( mod ) { case <NUM_LIT> : if ( rm == <NUM_LIT> ) { insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; } else { insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_NONE ; } break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_8 ; insn -> displacementSize = <NUM_LIT> ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; case <NUM_LIT> : case <NUM_LIT> : insn -> eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> : insn -> displacementSize = <NUM_LIT> ; case <NUM_LIT> : insn -> eaDisplacement = ( mod ==


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister (


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B


<s> if ( SelectAddressRegReg ( N , Disp , Base , DAG ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Aligned || ( imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( imm , N . getValueType ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Convert ; } if ( MI -> isCall ( ) || MI -> mayStore ( ) ) return Exit ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( ! RegInfo . isPhysicalRegister ( Reg ) ) continue ; if ( RegInfo . regsOverlap ( Reg , RegInfo .


<s> int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; if ( ! Memory . OffsetRegNum ) { <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val =


<s> SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; unsigned Pad = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; if ( MO . isUndef ( ) ) { assert ( RegList . empty ( ) && <STR_LIT> ) ; unsigned Width = TargetRegInfo -> getRegSizeInBits ( MO . getReg ( ) , MachineRegInfo ) / <NUM_LIT> ; Pad += Width ; continue ; } unsigned Reg = MO . getReg ( ) ; if ( unsigned RemappedReg = AFI -> EHPrologueRemappedRegs . lookup ( Reg ) ) Reg = RemappedReg ; RegList . push_back ( Reg ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) { ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; if ( Pad ) ATS . emitPad ( Pad


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( VT == <STR_LIT> && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) &&

CC != CallingConv :: <ISA_LIT>_RegCall ) return <NUM_LIT> ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand


<s> return * getDigitalTargetMachine ( )


<s> Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSGD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSLD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL_HI : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL_HA : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_HA ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>64_ADDR16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Type = ELF :: R_<ISA_LIT>64_ADDR16_LO_DS ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>64_GOT16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO : Type = ELF :: R_<ISA_LIT>64_GOT16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC : Type = ELF :: R_<ISA_LIT>64_TOC16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL : Type = ELF :: R_<ISA_LIT>64_TPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : Type = ELF :: R_<ISA_LIT>64_TPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL : Type = ELF :: R_<ISA_LIT>64_DTPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_LO_DS ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable (


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty )


<s> unsigned Q = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue Scc = DAG . getNode ( <STR_LIT> , dl , VT , Clz , DAG . getConstant ( Log2b , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scc ) ; } if ( C -> isAllOnesValue ( ) || C -> isNullValue ( ) ) return SDValue ( ) ; } EVT LHSVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( LHSVT . isInteger ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { EVT VT = Op . getValueType ( ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , LHSVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( dl , VT , Sub , DAG . getConstant ( <NUM_LIT> , LHSVT ) , CC ) ; } return SDValue (


<s> unsigned NumLaneElts = NumElts / NumLanes ; Imm = AlignDirection ? Imm : ( NumLaneElts - Imm ) ; unsigned Offset = Imm * ( VT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Base = i +


<s> enum rtx_code rs6000_reverse_condition ( enum machine_mode mode , enum rtx_code code ) { if ( mode == CCFPmode && ( ! flag_finite_math_only || code == UNLT || code == UNLE || code == UNGT || code == UNGE || code == UNEQ || code == LTGT ) ) return reverse_condition_maybe_unordered ( code ) ; else return reverse_condition ( code


<s> for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ++ I ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & * I ) ; if ( ! II ) continue ; if ( ! isAMXIntrinsic ( II ) ) continue ; assert ( onlyTileDef ( II ) && <STR_LIT> ) ; I = getShapesAndConfigPosEnd ( I , PosAndShapes [ & * I ] ) ; Find =


<s> case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : return false ; } const MachineOperand & MO = I -> getOperand ( structSizeOpNum ) ; if ( ! MO . isImm (


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget


<s> InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable (


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i


<s> OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT> ) . getMBB

( ) , <ISA_LIT>MCExpr :: CEK_ABS_HI ) ) ;


<s> if ( sign_extend ) { rtx discratch = gen_reg_rtx ( DImode ) ; rtx tiscratch = gen_reg_rtx ( TImode ) ; pat = GEN_FCN ( icode ) ( tiscratch , addr ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; rtx scratch = gen_lowpart ( smode , tiscratch ) ; if ( icode == CODE_FOR_vsx_lxvrbx ) emit_insn ( gen_extendqidi2 ( discratch , scratch ) ) ; else if ( icode == CODE_FOR_vsx_lxvrhx ) emit_insn ( gen_extendhidi2 ( discratch , scratch ) ) ; else if ( icode == CODE_FOR_vsx_lxvrwx ) emit_insn ( gen_extendsidi2 ( discratch , scratch ) ) ; if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = scratch ; emit_insn ( gen_extendditi2 ( target , discratch ) ) ; return target ; } else { pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ; } return <NUM_LIT>


<s> default : break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump (


<s> if ( GET_MODE ( x ) == QImode && ( op == EQ || op == NE ) ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) || rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) ) ) return CC_Cmode ; if ( GET_MODE ( x ) == DImode && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND && CONST_INT_P ( y ) && UINTVAL ( y ) == <NUM_LIT> && ( op == GEU || op == LTU ) ) return CC_ADCmode ; if ( GET_MODE ( x ) == DImode && ( op == GE || op == LT ) && GET_CODE ( x ) == SIGN_EXTEND && ( ( GET_CODE ( y ) == PLUS && arm_borrow_operation ( XEXP ( y , <NUM_LIT> ) , DImode ) ) || arm_borrow_operation ( y , DImode ) ) ) return CC_NVmode ; if ( GET_MODE ( x ) == DImode && ( op == GEU || op == LTU ) && GET_CODE ( x ) == ZERO_EXTEND && ( ( GET_CODE ( y ) == PLUS && arm_borrow_operation ( XEXP ( y , <NUM_LIT> ) , DImode ) ) || arm_borrow_operation ( y , DImode ) ) ) return CC_Bmode ; if ( GET_MODE ( x ) == DImode && ( op == EQ || op == NE ) && ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) && GET_CODE ( y ) == SIGN_EXTEND && GET_CODE ( XEXP ( y , <NUM_LIT> ) ) == GET_CODE ( x ) ) return CC_Vmode ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC


<s> EVT VT = Op . getValueType ( ) ; unsigned DivOp = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Div = DAG . getNode ( DivOp , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , VT , Div , Op . getOperand


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT>


<s> rtx op0 = XEXP ( comparison , <NUM_LIT> ) ; rtx op1 = XEXP ( comparison , <NUM_LIT> ) ; rtx_insn * seq , * last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 ) ; seq = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT> , false ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( MaxMaxAlign >= <NUM_LIT> && VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> ) MaxAlign = <NUM_LIT> ; else if ( VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> && MaxAlign < <NUM_LIT> ) MaxAlign = <NUM_LIT> ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign , MaxMaxAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( auto * EltTy : STy -> elements ( ) ) { unsigned EltAlign = <NUM_LIT>


<s> load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc ->


<s> MCInstLowering . Initialize ( Mang , & MF -> getContext (


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( isa < ConstantPointerNull > ( Val ) ) Val = Constant :: getNullValue ( TD . getIntPtrType ( Val -> getContext ( ) ) ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Val ) ) { unsigned Opc = <NUM_LIT> ; bool Signed = true ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( )


<s> if ( ObjSize % <NUM_LIT> != <NUM_LIT> ) { SDNode * St1 = DAG . getMachineNode ( ZeroData ? <STR_LIT> : <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Addr , Addr , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Chain } ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( St1 ) , { BaseMemOperand } ) ; ObjSize -= <NUM_LIT> ; Addr = SDValue ( St1 , <NUM_LIT> ) ; Chain = SDValue ( St1 , <NUM_LIT> ) ; } const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; std :: pair < Value * , int64_t > Add = getVarAndConst ( Offsets , TypeScale ) ; if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , OffsetsIncoming , Builder . CreateVectorSplat ( Ty -> getNumElements ( ) , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , I ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( Ty -> getNumElements ( ) , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , I ) ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) return tryCreateMaskedGatherBase ( I ,

OffsetsIncoming , Builder , Immediate ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> void setMustSaveLR ( bool U ) { MustSaveLR = U


<s> rtvec r = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( r , <NUM_LIT> ) = reg ; RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } else for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode ,


<s> DRECTVE_SECTION_FUNCTION \ SWITCH_TO_SECTION_FUNCTION void \ drectve_section ( void ) \ { \ if ( in_section != in_drectve ) \ { \ fprintf ( asm_out_file , <STR_LIT> , <STR_LIT>


<s> assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back


<s> return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case V64QImode : case V32QImode : case V16QImode : case V32HImode : case V16HImode : case V8HImode : case V16SImode : case V8SImode : case V4SImode : case V8DImode : case V4DImode : case V2DImode : gcc_assert ( vect ) ; case V16SFmode : case V8SFmode : case V4SFmode : case V8DFmode : case V4DFmode : case V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = value ; for ( i = <NUM_LIT> ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig


<s> llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . add ( MO ) ; else DefMI . add


<s> } for ( unsigned j = <NUM_LIT> ; j < VecElems / <NUM_LIT> ; j ++ ) for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i + j * <NUM_LIT>

] = Builder . CreateShuffleVector ( InVec [ j * <NUM_LIT> + i ] , InVec [ j * <NUM_LIT> + i + <NUM_LIT> ] , makeArrayRef ( Concat , <NUM_LIT> ) ) ;


<s> if ( Subtarget . has<ISA_LIT>64r2 ( ) ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Subtarget . has<ISA_LIT>64 ( ) ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Subtarget . has<ISA_LIT>32r2 ( ) ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else EFlags |= ELF :: EF_MIPS_ARCH_32 ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) EFlags |= ELF :: EF_MIPS_MICROMIPS ; if ( Subtarget . isABI_O32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; Reloc :: Model RM = Subtarget . getRelocationModel


<s> if ( SetNZCV ) Opc = isSub ? <STR_LIT> : <STR_LIT> ; else Opc = isSub ? <STR_LIT> : <STR_LIT> ; const unsigned MaxEncoding = <NUM_LIT> ; const unsigned ShiftSize = <NUM_LIT> ; const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; while ( ( ( unsigned ) Offset ) >= ( <NUM_LIT> << ShiftSize ) ) { unsigned ThisVal ; if ( ( ( unsigned ) Offset ) > MaxEncodableValue ) { ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI && SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ThisVal ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( Offset ) . addImm

( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlag ( Flag ) ;


<s> auto InitOutVal = Builder . CreateVectorSplat ( EC , Builder . getIntN ( ScalarTy -> getPrimitiveSizeInBits ( ) , <NUM_LIT> ) ) ; InitOutVal = Builder . CreateBitCast ( InitOutVal , VecTy ) ; Builder . SetInsertPoint ( LoopBlock -> getTerminator ( ) ) ; auto GP = Builder . CreatePHI ( PredTy , <NUM_LIT> , <STR_LIT> ) ; GP -> addIncoming ( InitGP , PHBlock ) ; auto OutVal = Builder . CreatePHI ( VecTy , <NUM_LIT> , <STR_LIT> ) ; OutVal -> addIncoming ( InitOutVal , PHBlock ) ; DEBUG ( dbgs ( ) << <STR_LIT> << II -> getCalledFunction ( ) << <STR_LIT> ) ; SmallVector < Value * , <NUM_LIT> > ScalarArgs ; unsigned ArgIdx = IsPredicated ? <NUM_LIT> : <NUM_LIT> ; for ( ; ArgIdx < II -> getNumArgOperands ( ) ; ++ ArgIdx ) { auto Param = II -> getOperand ( ArgIdx ) ; Value * SplatVal ; Value * LastArg ; if ( ! Param -> getType ( ) -> isVectorTy ( ) ) { LastArg = Param ; } else if ( match ( Param , m_SplatVector ( m_Value ( SplatVal ) ) ) ) LastArg = SplatVal ; else { LastArg = CreateLastB ( GP , Param ) ; Builder . Insert ( cast < Instruction > ( LastArg ) ) ; } ScalarArgs . push_back ( LastArg ) ; } <STR_LIT> IID = II -> getIntrinsicID ( ) ; if ( IsPredicated ) IID = getUnmaskedIntrinsic ( IID ) ; auto NewCall = CreateCall ( IID , ScalarTy , ScalarArgs ) ; NewCall -> setName ( <STR_LIT> ) ; Builder . Insert ( NewCall ) ; auto MergeCpy = CreateMergeCpy ( OutVal , GP , NewCall ) ; OutVal -> addIncoming ( MergeCpy , LoopBlock ) ; Builder . Insert ( MergeCpy ) ; auto GPNext = CreatePNext ( PredTy , Predicate , GP ) ; GP -> addIncoming ( GPNext , LoopBlock ) ; Builder . Insert ( GPNext ) ; auto Test = Builder . CreateTest ( TestInst :: ANY_TRUE , GPNext ) ; Builder . CreateCondBr ( Test , LoopBlock , ResumeBlock ) ; LoopBlock -> getTerminator ( ) -> eraseFromParent ( ) ; Builder . SetInsertPoint ( & ResumeBlock ->


<s> const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( *


<s> ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT Type = N -> getValueType (


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isFloatTy ( ) || ! V -> getType ( ) -> isDoubleTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (

<STR_LIT> ) , ResultReg ) . addReg ( Op ) ;


<s> USItype udivmodsi4 ( USItype num , USItype den , word_type modwanted ) { USItype bit = <NUM_LIT> ; USItype res = <NUM_LIT> ; while ( den < num && bit && ! ( den & ( <NUM_LIT> << <NUM_LIT> ) ) ) { den <<= <NUM_LIT> ; bit <<= <NUM_LIT> ; } while ( bit ) { if ( num >= den ) { num -= den ; res |= bit ; } bit >>= <NUM_LIT> ; den >>= <NUM_LIT>


<s> bool <ISA_LIT>FastISel :: SelectIntrinsicCall ( const IntrinsicInst & I ) { switch ( I . getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : { MachineFrameInfo * MFI = FuncInfo . MF -> getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; unsigned LdrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( )


<s> return MI -> hasDelaySlot ( ) && ! MI ->


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int FIOffset ; Register BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! hasStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) . getFixed ( ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) . getFixed ( ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } Register MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; if ( Offset != <NUM_LIT> || ! tryOptimizeLEAtoMOV ( II ) ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand

( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ;


<s> } if ( Imm1 & ~ <NUM_LIT> ) { Error ( Sx1 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc Sx2 , Ex2 ; Sx2 = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) Parser . Lex ( ) ; const MCExpr * Imm2Exp ; if ( getParser ( ) . parseExpression ( Imm2Exp , Ex2 ) ) { Error ( Sx2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( Imm2Exp ) ; if ( CE ) { Imm2 = CE -> getValue ( ) ; if ( ! ( Imm2 & ~ <NUM_LIT> ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateModImm ( Imm1 , Imm2 , S , Ex2 ) ) ; return MatchOperand_Success ; } Error ( Sx2 , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) ParseDirectiveWord ( <NUM_LIT> , DirectiveID ) ; else if ( IDVal == <STR_LIT> ) ParseDirectiveWord (


<s> SDValue <ISA_LIT>TargetLowering :: LowerCCCCallTo ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl ,


<s> return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , fast


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU


<s> Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT>

|| AM . IndexReg != <NUM_LIT> ) ) return false ;


<s> MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg


<s> BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , dl , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return Sum


<s> void <ISA_LIT>InstrInfo :: fixupPostOutline ( MachineBasicBlock & MBB ) const { for ( MachineInstr & MI : MBB ) { unsigned Base , Width ; int64_t Offset ; if ( ! MI . mayLoadOrStore ( ) || ! getMemOpBaseRegImmOfsWidth ( MI , Base , Offset , Width , & RI ) || Base != <STR_LIT> ) continue ; unsigned


<s> O << <STR_LIT> ; printMemReference ( MI ,


<s> DECL_FIELD_CONTEXT ( f_2 ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_1 ; TREE_CHAIN ( f_1 ) = f_2 ; layout_type ( record ) ; return


<s> SDValue MultHi = SUBENode -> getOperand ( <NUM_LIT> ) ; SDValue MultLo = SUBCNode -> getOperand ( <NUM_LIT> ) ; SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) )


<s> if ( CmpInstr . definesRegister ( <STR_LIT> ) || CmpInstr . definesRegister ( <STR_LIT> ) ) { CmpInstr . eraseFromParent ( ) ; return true ; } unsigned Opc = CmpInstr . getOpcode ( ) ; unsigned NewOpc = convertToNonFlagSettingOpc ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr . setDesc ( MCID ) ; CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( & CmpInstr , SrcReg , SrcReg2


<s> if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT>


<s> static bool isPALIGNRMask ( ArrayRef < int > Mask , MVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ( VT . is128BitVector ( ) && ! Subtarget -> hasSSSE3 ( ) ) || ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) || VT . is512BitVector ( ) ) return false ; return isAlignrMask ( Mask , VT ,


<s> return __builtin_mve_vshlq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) ,


<s> if ( Op2 . isImm ( ) ) { if ( AluIter -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Offset . isReg ( ) && Offset . getReg ( ) == <STR_LIT> ) return true ; if ( Offset . isImm ( ) && ( ( Offset . getImm ( ) == <NUM_LIT> && ( ( IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) || ( ! IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) ) ) || Offset . getImm ( ) == Op2 . getImm ( ) ) ) return true ; } else if ( Op2 . isReg ( ) ) { if ( Offset . isReg ( ) && Op2 . getReg ( ) == Offset . getReg (


<s> if ( Align == <NUM_LIT> ) Align = MF . getDataLayout ( ) . getTypeAllocSize ( CPTy ) ; MachineConstantPool * MCP = MF . getConstantPool ( ) ; return MCP -> getConstantPoolIndex ( CPVal


<s> I = std :: find_if ( B , E , isdigit ) ; Prefix = StringRef ( B , I - B ) ; if ( I == E ) return std :: make_pair ( true , false ) ; return std :: make_pair ( ! getAsUnsignedInteger ( StringRef ( I , E


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : Val = performORCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this , Subtarget ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) { DEBUG ( dbgs ( ) <<


<s> __attribute__ ( ( __always_inline__ ) )


<s> MachineInstr * MI = I ; unsigned Flags = MI -> getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI -> getOpcode ( ) == TargetInstrInfo :: INLINEASM ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = <NUM_LIT> ; if ( I != BB . begin ( ) ) PrevMI = prior ( I ) ; ++ NumFP ; DEBUG ( errs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { cerr << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && prior ( Start ) != PrevI


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( - Value ) !=


<s> case TYPE_R64 : case TYPE_Rv : case TYPE_MM : case TYPE_MM32 : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M16INT : case TYPE_M32INT : case TYPE_M64INT


<s> MCContext & Ctx = Asm . getContext ( ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; Value = adjustFixupValue ( Fixup , Target , Value , Ctx , TheTriple , IsResolved ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes -


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> )

, DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ;


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int opNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm


<s> if ( ! isDoubleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count


<s> void <ISA_LIT>ELFStreamer :: emitFnEnd ( ) { assert ( FnStart && <STR_LIT> ) ; if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else


<s> O << '#' << formatImm ( Scale * MI -> getOperand ( OpNum