<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } UsedInBetween . accumulate ( MI ) ; FoundDef = IsDef ; if ( FoundDef ) { for ( auto & MOP : MI . operands ( ) ) { if ( ! MOP . isReg ( ) || ! MOP . isDef ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) continue ; if ( ! canRenameMOP ( MOP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MOP << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } RequiredClasses . insert ( TRI -> getMinimalPhysRegClass ( MOP . getReg ( ) ) ) ; } return true ; } else { for ( auto & MOP : MI . operands ( ) ) { if ( ! MOP . isReg ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) continue ; if ( ! canRenameMOP ( MOP


<s> return ( __m128i ) __builtin_ia32_loaddqusi128_mask ( ( const int * ) __P ,


<s> rtx result = NULL_RTX ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) { if ( base_term_p && MEM_P ( orig_x ) ) return orig_x ; rtx x2 = XVECEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , x2 ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOTPCREL || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) && ( MEM_P ( orig_x ) || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) ) { x = XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_MODE ( orig_x ) != GET_MODE ( x ) && MEM_P ( orig_x ) ) { x = lowpart_subreg ( GET_MODE ( orig_x ) , x , GET_MODE ( x ) ) ; if ( x == NULL_RTX ) return orig_x ; } return x ; } if ( ix86_cmodel != CM_MEDIUM_PIC && ix86_cmodel != CM_LARGE_PIC ) return ix86_delegitimize_tls_address ( orig_x ) ; } if ( GET_CODE ( x ) != PLUS || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST ) return ix86_delegitimize_tls_address ( orig_x ) ; if ( ix86_pic_register_p ( XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { reg_addend = XEXP ( x , <NUM_LIT> ) ; if ( ix86_pic_register_p ( XEXP ( reg_addend , <NUM_LIT> ) ) ) reg_addend = XEXP ( reg_addend , <NUM_LIT> ) ; else if ( ix86_pic_register_p ( XEXP ( reg_addend , <NUM_LIT> ) ) ) reg_addend = XEXP ( reg_addend , <NUM_LIT> ) ; else { reg_addend = NULL_RTX ; addend = XEXP ( x , <NUM_LIT> ) ; } } else addend = XEXP ( x , <NUM_LIT>


<s> } if ( fcode == ARM_BUILTIN_sel ) { if ( cfun && cfun -> decl ) DECL_ATTRIBUTES ( cfun -> decl ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , DECL_ATTRIBUTES ( cfun -> decl ) ) ; } return


<s> if ( ! unaligned_p && ( length & <NUM_LIT> ) != <NUM_LIT> ) num ++ ; if ( ! unaligned_p && mode == V16QImode ) num -- ; return ( num <=


<s> static SDValue combineVectorSignBitsTruncation ( SDNode * N , const SDLoc & DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX512 ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros (


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool DestCPU = <STR_LIT> . contains ( DestReg ) ; bool SrcCPU = <STR_LIT> . contains ( SrcReg ) ; if ( DestCPU && SrcCPU ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestCPU ) { if ( <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; else if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; } if ( SrcCPU ) { if ( <STR_LIT> . contains ( DestReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( DestReg


<s> Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] )


<s> unsigned getSRetReturnReg ( ) const { return


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op , DAG


<s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) .


<s> if ( STI -> isTargetDarwin ( ) && ( ! MF . getLandingPads ( ) . empty ( ) || ( MF . getFunction ( ) . needsUnwindTableEntry ( ) && ! TFL -> hasFP ( MF ) ) ) ) return false ; if ( STI -> isTargetWin64 ( ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode


<s> inline void RevertDoLoopStart ( MachineInstr * MI , const TargetInstrInfo * TII ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI ->

getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreatePrefetch ( unsigned Val , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand


<s> if ( ( ( isThumb ( ) && Mnemonic == <STR_LIT> ) || ( isThumbTwo ( ) && Mnemonic == <STR_LIT> ) ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( ) && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( ) && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getReg ( ) == <STR_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getReg ( ) == <NUM_LIT> && ( ( Mnemonic == <STR_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( ) ) || static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isImm0_1020s4 ( ) ) ) return true ; if ( isThumbTwo ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( ) && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( ) && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isImm ( ) ) { if ( inITBlock ( ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getReg ( ) ) && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isImm0_7 ( ) ) return false ; if ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getReg ( ) != <STR_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isT2SOImm


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; cond = gen_reg_rtx ( CCmode ) ; if ( mode != TImode ) x = gen_rtx_COMPARE ( CCmode , x , oldval ) ; else { rtx xor1_result = gen_reg_rtx ( DImode ) ; rtx xor2_result = gen_reg_rtx ( DImode ) ; rtx or_result = gen_reg_rtx ( DImode ) ; rtx new_word0 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx new_word1 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx old_word0 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; rtx old_word1 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; emit_insn ( gen_xordi3 ( xor1_result , new_word0 , old_word0 ) ) ; emit_insn ( gen_xordi3 ( xor2_result , new_word1 , old_word1 ) ) ; emit_insn ( gen_iordi3 ( or_result , xor1_result , xor2_result ) ) ; x = gen_rtx_COMPARE ( CCmode , or_result , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; x = newval ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , newval , mask ) ; emit_store_conditional ( orig_mode , cond , mem , x


<s> report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand :: MO_GlobalAddress : return LowerSymbolOperand ( MI , MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO .


<s> return ( __m64 ) __builtin_ia32_psubd ( ( __v2si )


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isTerminator ( ) )

return MachineOutlinerInfo ( <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ;


<s> void printqwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: tryFoldLoad ( SDNode * Root , SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( ! <STR_LIT> ( N . getNode ( ) ) || ! IsProfitableToFold ( N , P , Root )

|| ! IsLegalToFold ( N , P , Root , OptLevel ) ) return false ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectBitfieldExtractOp ( SDNode * N ) { unsigned Opc , LSB , MSB ; SDValue Opd0 ; if ( ! isBitfieldExtractOp ( CurDAG , N , Opc , Opd0 , LSB , MSB ) ) return nullptr ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , SDLoc


<s> bool nds32_use_load_post_increment ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext &


<s> return ( __m128i ) __builtin_ia32_pandn128 ( ( __v2di )


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOT_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PIC_BASE_OFFSET , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_GOTTPOFF , <STR_LIT> } , { MO_INDNTPOFF , <STR_LIT> } ,

{ MO_TPOFF , <STR_LIT> } , { MO_DTPOFF , <STR_LIT> } , { MO_NTPOFF , <STR_LIT> } , { MO_GOTNTPOFF , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_DARWIN_NONLAZY , <STR_LIT> } , { MO_DARWIN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_TLVP , <STR_LIT> } , { MO_TLVP_PIC_BASE , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_COFFSTUB , <STR_LIT> } } ;


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ; if ( ST -> hasPOPCNTD ( ) != <ISA_LIT>Subtarget :: POPCNTD_Unavailable && TyWidth <= <NUM_LIT> ) return ST -> hasPOPCNTD ( ) == <ISA_LIT>Subtarget :: POPCNTD_Slow ? TTI :: PSK_SlowHardware : TTI :: PSK_FastHardware ; return TTI :: PSK_Software


<s> Map [ GRH32Regs [ I ] ] = I ; Map [ GR64Regs [ I ] ] = I ; Map [ GR128Regs [ I ] ] = I ; Map [ FP128Regs [ I ] ] = I ; Map [ AR32Regs [ I ] ] = I ; } for ( unsigned I = <NUM_LIT> ; I <


<s> FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( MachineBasicBlock * BB : depth_first_ext ( Entry , Processed ) )

Changed |= processBasicBlock ( MF , * BB ) ;


<s> static SDValue LowerIntVSETCC_AVX512 ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( Op0 . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) >= <NUM_LIT> && Op . getValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; bool Unsigned = false ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ;


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedScatterOffset ( IntrinsicInst * I , Value * Ptr , IRBuilder < > Builder ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Type * InputTy = Input -> getType ( ) ; Type * MemoryTy = InputTy ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( TruncInst * Trunc = dyn_cast < TruncInst > ( Input ) ) { Value * PreTrunc = Trunc -> getOperand ( <NUM_LIT> ) ; Type * PreTruncTy = PreTrunc -> getType ( ) ; if ( PreTruncTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { Input = PreTrunc ; InputTy = PreTruncTy


<s> for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( mask & ( <NUM_LIT> << reg ) ) { if ( acc_low == <NUM_LIT> ) acc_low = reg ; else { acc_high = reg ; break ; } } gcc_assert ( acc_high != <NUM_LIT> ) ; emit_insn ( gen_mvfacmi ( gen_rtx_REG ( SImode , acc_low ) ) ) ; emit_insn ( gen_mvfachi ( gen_rtx_REG ( SImode , acc_high ) ) ) ; emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , acc_low ) ) ) ; emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , acc_high ) ) ) ; } else { acc_low = low ; acc_high = low + <NUM_LIT> ; gcc_assert ( acc_high <= high ) ; emit_insn ( gen_mvfacmi ( gen_rtx_REG ( SImode , acc_low ) ) ) ; emit_insn ( gen_mvfachi ( gen_rtx_REG ( SImode , acc_high ) ) ) ; emit_insn ( gen_stack_pushm ( GEN_INT ( <NUM_LIT> * UNITS_PER_WORD ) , gen_rx_store_vector ( acc_low , acc_high ) ) ) ; } } if ( frame_pointer_needed ) gen_safe_add ( frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( - ( HOST_WIDE_INT ) frame_size ) , true ) ; if (


<s> if ( ! II ) Row = Col = nullptr ; else { switch ( II -> getIntrinsicID ( ) ) { default : Row = Col = nullptr ; break ; case <STR_LIT> : case <STR_LIT> : { Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } } } if ( ! Row ) { splitST ( Inst ) ; continue ; } IRBuilder < > Builder ( Inst ) ; LLVMContext & Ctx = Builder . getContext


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode


<s> case EQ : case NE : case GT : case GE : case LT : case LE : case GTU : case GEU : case LTU


<s> bool disablePostRAScheduler ( ) const { return DisablePostRAScheduler


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> static SDValue combine<ISA_LIT>INT_TO_FP ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt KnownUndef , KnownZero ; APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) &&


<s> inline const type_suffix_info & function_instance :: type_suffix ( unsigned int i ) const { return type_suffixes [ type_suffix_ids [ i ]


<s> static bool isCallOrRealInstruction ( MachineInstr & MI ) { return MI . isCall ( ) || ( ! MI . isPseudo ( )


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> DebugLoc DL = MIItBegin -> getDebugLoc ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; MIIt = skipDebugInstructionsForward ( ++ MIIt , MIItEnd ) ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable [ FalseReg ] . second ; BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg

) . addMBB ( TrueMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ;


<s> static void EmitNops ( MCStreamer & OS , unsigned NumBytes , bool Is64Bit , const MCSubtargetInfo & STI ) { unsigned NopsToEmit = NumBytes ; ( void ) NopsToEmit ; while ( NumBytes ) { NumBytes -= EmitNop ( OS , NumBytes


<s> gcc_assert ( get_attr_type ( out_insn ) == TYPE_FMADD ) ; extract_insn ( in_insn ) ; dst_reg = REG_P ( recog_data . operand [ <NUM_LIT> ] ) ; extract_insn ( out_insn ) ; src_reg = REG_P ( recog_data . operand [ <NUM_LIT> ] ) ; if ( dst_reg == src_reg ) return true ; return false


<s> bool isMicro<ISA_LIT>Enabled ( ) const { return


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> return * get<ISA_LIT>TargetMachine ( ) .


<s> static DecodeStatus DecodeRestrictedUPredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( ( Val & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT>


<s> if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId ( ) >


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> void <ISA_LIT>InstrInfo :: expandLOCPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned HighOpcode ) const { Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode = isHighReg ( Reg ) ? HighOpcode : LowOpcode ; MI . setDesc ( get ( Opcode )


<s> SmallSet < unsigned , <NUM_LIT> > AddedRegPressure ; while ( ++ I != E ) { if ( I -> isDebugInstr ( ) || MemOps . count ( & * I ) ) continue ; if ( I -> isCall ( ) || I -> isTerminator ( ) || I -> hasUnmodeledSideEffects ( ) ) return false ; if ( I -> mayStore ( ) || ( ! isLd && I -> mayLoad ( ) ) ) for ( MachineInstr * MemOp :

MemOps ) if ( I -> mayAlias ( AA , * MemOp , false ) ) return false ;


<s> output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } output_asm_insn ( <STR_LIT> , xoperands ) ; } } if ( seq_length == <NUM_LIT> ) output_asm_insn ( <STR_LIT> , xoperands ) ; if ( seq_length == <NUM_LIT> || GET_CODE ( NEXT_INSN ( insn ) ) != JUMP_INSN ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = XEXP ( PATTERN ( NEXT_INSN ( insn ) ) , <NUM_LIT> ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { seq_insn = NEXT_INSN ( PREV_INSN ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ; distance = ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( NEXT_INSN ( insn ) ) ) ) - INSN_ADDRESSES ( INSN_UID ( seq_insn ) ) - <NUM_LIT> ) ; if ( VAL_14_BITS_P ( distance ) ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; } else output_asm_insn ( <STR_LIT> , xoperands ) ; } else output_asm_insn ( <STR_LIT> , xoperands ) ; PUT_CODE ( NEXT_INSN ( insn ) , NOTE ) ; NOTE_LINE_NUMBER ( NEXT_INSN ( insn ) ) = NOTE_INSN_DELETED ; NOTE_SOURCE_FILE ( NEXT_INSN ( insn ) ) = <NUM_LIT> ; return


<s> } dbgs ( ) << <STR_LIT> << <STR_LIT> ; for ( MachineInstr * MI : Instrs ) { dbgs ( ) << <STR_LIT> ; MI -> print ( dbgs ( ) ) ; } dbgs ( ) << <STR_LIT>


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * MergeMI ) ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent ( ) ; return


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo (


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { int Offset = <NUM_LIT> ; if ( ExtraCode


<s> MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool is64Bit = STI . is64Bit ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( is64Bit ? & <STR_LIT> : & <STR_LIT> ) ; MachineInstr * Next = I . getNextNode


<s> case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addExpr ( Lower . getExpr ( MI -> getOperand ( <NUM_LIT> ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> ## <NUM_LIT> : LoweredMI = lowerRILow ( MI , <STR_LIT> ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( TMLL ) ; LOWER_LOW ( TMLH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW (


<s> ParallelMAC ( Instruction * I , ValueList & V ) : Mul ( I ) , VL (


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( N00 . getOpcode ( ) == <STR_LIT> && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) ; } if ( MaskOK && Mask != <NUM_LIT> ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Mask , DL , VT ) ) ; } } if ( auto * N1BV = dyn_cast < BuildVectorSDNode > ( N1 ) ) if ( auto * N1SplatC = N1BV -> getConstantSplatNode ( ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( N1SplatC -> isOne ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; } return SDValue


<s> return ConstantPools -> addEntry ( Streamer , Expr , <NUM_LIT>


<s> } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate


<s> auto * SubVecTy = FixedVectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; int BaseCost = ST -> hasMVEIntegerOps ( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( Factor , SubVecTy , DL ) ) return Factor * BaseCost * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; if ( ST -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> && NumElts / Factor > <NUM_LIT> && VecTy -> isIntOrIntVectorTy ( ) && DL . getTypeSizeInBits ( SubVecTy ) <= <NUM_LIT> ) return <NUM_LIT> * BaseCost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind


<s> return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; }


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions (


<s> if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) { PSHUFBMask [ <NUM_LIT> * i ] = PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } int M = i < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> ; assert ( M >= <NUM_LIT> && M < <NUM_LIT> && <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i ] = DAG . getConstant ( <NUM_LIT> * M , <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> * M + <NUM_LIT> , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsBitShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) )


<s> ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregoidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregoidi_pss ( __o , <NUM_LIT> ) ; return ret


<s> for ( MachineFunction :: iterator FI = F . begin ( )


<s> static DecodeStatus DecodeCRBITRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> void SetMemoryLocations ( ) { const auto Size = MemoryLocation :: UnknownSize ; for ( auto * V : AllValues ) { if ( auto * I = dyn_cast < Instruction > ( V ) ) { if ( I -> mayWriteToMemory ( ) ) ReadOnly = false ; if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) MemLocs . push_back (

MemoryLocation ( Ld -> getPointerOperand ( ) , Size ) ) ;


<s> unsigned numRegs = info -> getNumRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numRegs ; ++ i ) { const char * regName = info -> getName ( i


<s> case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return <NUM_LIT> ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return <NUM_LIT> ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return <NUM_LIT> ; case CPU_POWER8


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI


<s> SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( CS . arg_size ( ) ) ; ArgRegs . reserve ( CS . arg_size ( ) ) ; ArgVTs . reserve ( CS . arg_size ( ) ) ; ArgFlags . reserve ( CS . arg_size ( ) ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( GV ) ; if ( isThumb2 ) { MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII .


<s> Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset = MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , Ctx ) ; if ( Offset ) { const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: CreateAdd ( Expr , OffsetExpr , Ctx ) ; } return MCOperand :: CreateExpr ( Expr )


<s> const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst >

( B -> getTerminator ( ) ) ) return false ;


<s> SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( GV -> isDeclaration ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT


<s> case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , false , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG


<s> void emitARM64WinCFISaveReg ( unsigned Reg , int Offset )


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsi_u64 ( unsigned long long __X ) { return __blsi_u64 (


<s> return ( __m128i ) __builtin_ia32_pmaxsq128_mask ( ( __v2di ) __A , ( __v2di )


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF &


<s> if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 ,

DAG . getConstant ( Size , DL , PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ;


<s> static machine_mode mips_get_reg_raw_mode ( int regno ) { if ( TARGET_FLOATXX && FP_REG_P ( regno


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr


<s> void addFGRH32AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp


<s> EVT Evt = TLI . getValueType ( Ty , true ) ; if ( Evt == <STR_LIT> || ! Evt . isSimple ( ) ) return false ; VT = Evt .


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { unsigned NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ,


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( - ValueofRHS ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , LHS , DAG . getValueType (


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } } return true


<s> bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBlockInRange ( MI , NewDest , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand ,


<s> unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) . addImm ( <NUM_LIT>


<s> HOST_WIDE_INT val_broadcast ; scalar_int_mode broadcast_mode ; if ( TARGET_AVX2 && ix86_broadcast ( val , GET_MODE_BITSIZE ( QImode ) , val_broadcast ) ) broadcast_mode = QImode ; else if ( TARGET_AVX2 && ix86_broadcast ( val , GET_MODE_BITSIZE ( HImode ) , val_broadcast ) ) broadcast_mode = HImode ; else if ( ix86_broadcast ( val , GET_MODE_BITSIZE ( SImode ) , val_broadcast ) ) broadcast_mode = SImode ; else if ( TARGET_64BIT && ix86_broadcast ( val , GET_MODE_BITSIZE ( DImode ) , val_broadcast ) ) broadcast_mode = DImode ; else return nullptr ; for ( int i = <NUM_LIT> ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) if ( val != CONST_WIDE_INT_ELT ( op , i ) ) return nullptr ; unsigned int nunits = ( GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( broadcast_mode ) ) ; machine_mode vector_mode


<s> if ( NumUpperHalves == <NUM_LIT> ) return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) ) { if ( EltWidth == <NUM_LIT> && NumLowerHalves && HalfVT . is128BitVector ( ) && ! is128BitUnpackShuffleMask ( HalfMask ) && ( ! isSingleSHUFPSMask ( HalfMask ) || Subtarget . hasFastVariableShuffle ( ) ) ) return SDValue ( ) ; if ( EltWidth == <NUM_LIT> && V2 . isUndef ( ) ) return SDValue ( ) ; } if ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) return SDValue ( ) ; return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; } assert ( NumUpperHalves == <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) && EltWidth == <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) return SDValue ( ) ; return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; case <STR_LIT> : return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , <NUM_LIT> ) ; case <STR_LIT> : return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , <NUM_LIT> ) ; case <STR_LIT> : return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , <NUM_LIT> ) ; default : break ; } if ( Opcode != <STR_LIT> ) return EVT ( ) ; const unsigned IntNo = cast < ConstantSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) ->


<s> Res = tryParseOptionalShiftExtend ( ExtOpnd ) ; if ( Res != MatchOperand_Success ) return Res ; auto Ext = static_cast < <ISA_LIT>Operand * > ( ExtOpnd . back ( ) . get ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , Ext -> getEndLoc ( ) , getContext ( ) , Ext -> getShiftExtendType ( ) ,

Ext -> getShiftExtendAmount ( ) , Ext -> hasShiftExtendAmount ( ) ) ) ;


<s> if ( ( VT == <STR_LIT> && Subtarget . hasFRES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) ) { TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; std :: string RecipOp = getRecipOp ( <STR_LIT> , VT ) ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue


<s> bool <ISA_LIT>BaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , const MachineOperand * & Destination , const MachineOperand * & Source , int64_t & Offset ) const { int Sign = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return false ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm


<s> bool WorthOptLoop = false ; if ( Diff [ <NUM_LIT> ] == Diff [ <NUM_LIT> ] ) WorthOptLoop = Diff [ <NUM_LIT> ] * <NUM_LIT> >= LoopDepth [ <NUM_LIT> ] . Depth ; else if ( Diff [ <NUM_LIT> ] > Diff [ <NUM_LIT> ] ) WorthOptLoop = ( Diff [ <NUM_LIT> ] - Diff [ <NUM_LIT> ] ) * <NUM_LIT> >= ( LoopDepth [ <NUM_LIT> ] . Depth - LoopDepth [ <NUM_LIT> ] . Depth ) && ( Diff [ <NUM_LIT> ] * <NUM_LIT> >= LoopDepth [ <NUM_LIT> ] . Depth ) ; if ( ! WorthOptLoop ) return false ; ++ NumOfLoopCandidate ; unsigned MispredictPenalty = TSchedModel . getMCSchedModel ( ) -> MispredictPenalty ; CmovGroups TempGroups ; std :: swap ( TempGroups , CmovInstGroups ) ; for ( auto & Group : TempGroups ) { bool WorthOpGroup = true ; for ( auto * MI : Group ) { auto UIs = MRI -> use_instructions ( MI -> defs ( ) . begin ( ) -> getReg ( ) ) ; if ( UIs . begin ( ) != UIs . end ( ) && ++ UIs . begin ( ) == UIs . end ( ) ) { unsigned Op = UIs . begin ( ) -> getOpcode ( ) ; if ( Op == <STR_LIT> || Op == <STR_LIT> ) { WorthOpGroup = false ; break ; } } unsigned CondCost = DepthMap [ OperandToDefMap . lookup ( & MI -> getOperand ( <NUM_LIT> ) ) ] . Depth ; unsigned ValCost = getDepthOfOptCmov ( DepthMap [ OperandToDefMap . lookup ( & MI -> getOperand ( <NUM_LIT> ) ) ] . Depth , DepthMap [ OperandToDefMap . lookup ( & MI -> getOperand ( <NUM_LIT> ) ) ] . Depth ) ; if ( ValCost > CondCost || ( CondCost - ValCost ) * <NUM_LIT> < MispredictPenalty ) { WorthOpGroup = false ; break ; } } if ( WorthOpGroup ) CmovInstGroups . push_back ( Group


<s> return ( __m512i ) __builtin_ia32_expandloadqi512_maskz ( ( const __v64qi * ) __B , ( __v64qi ) _mm512_setzero_si512 ( ) , ( __mmask64


<s> else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = <NUM_LIT> ; if ( nregs <= <NUM_LIT>


<s> return ( ( vec_int4 ) ( si_andi ( ( qword ) ( a ) ,


<s> return __builtin_mve_veorq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> EVT IndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index ) ; SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Trunc ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { SDValue Index = N -> getOperand ( <NUM_LIT> ) ; if ( Index . getScalarValueSizeInBits ( ) == <NUM_LIT> && Index . getOpcode ( ) == <STR_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Index . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( Index . getNode ( ) ) ; DCI . AddToWorklist ( N ) ; return SDValue ( N


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , ( Is64Bit ) ? true : false ) ; return createELFObjectWriter ( MOTW ,


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode


<s> unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( ScalarType -> isFloatingPointTy ( ) && Index == <NUM_LIT> ) return <NUM_LIT> ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ST -> isSLM ( ) ) if ( auto * Entry = CostTableLookup ( SLMCostTbl

, ISD , MScalarTy ) ) return LT . first * Entry -> Cost ;


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; SExpr * load1 = ctx -> load ( <NUM_LIT> , TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; SExpr * load2 = ctx -> load ( <NUM_LIT> , TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; SExpr * andexpr = ctx -> and_ ( <NUM_LIT> , load1


<s> static __inline unsigned long long sh_media_MPERM_W ( unsigned long long mm , unsigned int mn


<s> unsigned <ISA_LIT>ELFWriterInfo :: getAbsoluteLabelMachineRelTy ( ) const { return <STR_LIT>


<s> MachineInstrBuilder ( MF , EarlierMI ) . addReg ( Reg128 , Reg128UndefImpl ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg128 , ( Reg128UndefImpl | Reg128Killed ) ) ; } MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; if ( EarlierMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && EarlierMI -> getOperand ( <NUM_LIT> ) . isUse ( ) ) EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm


<s> assemble_integer ( GEN_INT ( bits ) , <NUM_LIT> , BITS_PER_WORD , <NUM_LIT> ) ; if ( ! WORDS_BIG_ENDIAN ) assemble_zeros


<s> MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . GetOrCreateTemporarySymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MCInstLowering . GetPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> )


<s> FuseKind = FuseCmp ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseTest ; break ; } switch ( First -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; if ( getParser ( ) . ParseExpression ( WidthExpr ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( WidthExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT>


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o


<s> if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SUBREG ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case CONST : case


<s> static bool GetCpuIDAndInfo ( unsigned value , unsigned * rEAX , unsigned * rEBX , unsigned * rECX , unsigned * rEDX ) { asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; int registers [ <NUM_LIT> ] ; __cpuid ( registers , value ) ; * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT>


<s> if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) )


<s> SDValue Opnd0 , Opnd1 ; unsigned NumExtracts ; bool IsSubAdd ; if ( ! isAddSubOrSubAdd ( BV , Subtarget , DAG , Opnd0 , Opnd1 , NumExtracts , IsSubAdd ) ) return SDValue ( ) ; MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( BV


<s> if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ,


<s> inline void EmitPersonalityIndex ( unsigned PI ) { assert ( PI < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ; EmitByte ( <STR_LIT> ::


<s> static void ix86_output_indirect_branch ( rtx call_op , const char *


<s> APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue (


<s> ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; return ret


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl


<s> static std :: pair < StackMaps :: Location , MachineInstr :: const_mop_iterator > parseMemoryOperand ( StackMaps :: Location :: LocationType LocTy , unsigned Size , MachineInstr :: const_mop_iterator MOI , MachineInstr :: const_mop_iterator MOE ) { typedef StackMaps :: Location Location ; assert ( std :: distance ( MOI , MOE ) >= <NUM_LIT> && <STR_LIT> ) ; const MachineOperand & Base = * MOI ; const MachineOperand & Scale = * ( ++ MOI ) ; const MachineOperand & Index = * ( ++ MOI ) ; const MachineOperand & Disp = * ( ++ MOI ) ; const MachineOperand & ZeroReg = * (


<s> AU . addRequired < AAResultsWrapperPass >


<s> if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return MatchOperand_Success ; return MatchOperand_NoMatch ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , false ) ) { <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; op -> setRegKind ( <STR_LIT> )


<s> static int mt_arg_partial_bytes ( CUMULATIVE_ARGS * pcum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int cum = * pcum ; int words ; if ( mode == BLKmode ) words = ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; else words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( ! targetm . calls . pass_by_reference ( & cum , mode , type , named ) && cum < MT_NUM_ARG_REGS &&


<s> case <STR_LIT> : if ( ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) || ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; break ; case <STR_LIT> : if ( ! Subtarget . hasVBMI ( ) ) return SDValue ( ) ; break ; case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) || ! Subtarget . hasVBMI ( ) ) return SDValue ( ) ; break ; } SDValue SrcVec , IndicesVec ; for ( unsigned Idx = <NUM_LIT> , E = V . getNumOperands ( ) ; Idx != E ; ++ Idx ) { SDValue Op = V . getOperand ( Idx ) ; if ( Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! SrcVec ) SrcVec = Op . getOperand ( <NUM_LIT> ) ; else if ( SrcVec != Op . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue ExtractedIndex = Op -> getOperand ( <NUM_LIT> ) ; if ( ExtractedIndex . getOpcode ( ) == <STR_LIT> || ExtractedIndex . getOpcode

( ) == <STR_LIT> ) ExtractedIndex = ExtractedIndex . getOperand ( <NUM_LIT> ) ;


<s> case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; default : return false ; } const Value * Op0 = CI -> getOperand ( <NUM_LIT> ) , * Op1 = CI -> getOperand ( <NUM_LIT> ) ; if ( SwapArgs ) std :: swap ( Op0 , Op1 ) ; if ( ! <ISA_LIT>FastEmitCompare ( Op0 , Op1


<s> else if ( XINT ( operands [ <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) { if ( TARGET_CMODEL != CMODEL_SMALL ) output_asm_insn ( <STR_LIT> <STR_LIT> , op ) ; else output_asm_insn ( <STR_LIT> , op ) ; } else gcc_unreachable (


<s> return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , APInt :: getAllOnesValue ( N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT>


<s> SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl ,


<s> if ( BracCount -- != <NUM_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } State = IES_RBRAC ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_clflush ( void const *


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; return _TEXASRU_ABORT (


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( unsigned ( getCondCode ( ) ) ) ) ; unsigned RegNum = getCondCode ( ) == <STR_LIT> ? <NUM_LIT> : <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( RegNum )


<s> SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; } if ( IsSEXT0 && IsVZero1 )


<s> unsigned CPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; unsigned i = <NUM_LIT> , e = CSI . size ( ) ; for ( ; i != e ; ++ i ) { unsigned Reg = CSI [ i ]


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>32 ( ) { OS << <STR_LIT>


<s> unsigned Opc ; bool useAM3 = false ; TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Ops [ ] = { Base , NewOffset , CurDAG -> getTargetConstant ( Pred , SDLoc ( N ) , <STR_LIT> ) , PredReg , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Ops ) ; transferMemOperands ( N , New ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> return ( __m256 ) __builtin_ia32_expandloadsf256_maskz ( ( __v8sf * ) __P , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 )


<s> MachineOperand RegOp1 = getLdStRegOp ( * Rt2MI ) ; if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { unsigned Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg (

DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> auto_vec < rtx > and_ops ; bool is_any_def_and = find_alignment_op ( insn , base_reg , & and_insns , & and_ops ) ; if ( is_any_def_and ) { gcc_assert ( and_insns . length ( ) == and_ops . length ( ) ) ; df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx new_reg = <NUM_LIT> ; rtx and_mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < and_insns . length ( ) ; i ++ ) { rtx_insn * and_insn = and_insns [ i ] ; rtx and_op = and_ops [ i ] ; rtx and_base = XEXP ( and_op , <NUM_LIT> ) ; if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn


<s> if ( pType == llvm :: ELF :: R_AARCH64_RELATIVE || pSym == NULL ) rel_entry . setSymInfo ( NULL ) ; else rel_entry . setSymInfo ( pSym ) ; return rel_entry


<s> void addT2SOImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> SDValue Scale = GorS -> getScale ( ) ; if ( DCI . isBeforeLegalize ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits ( ) ; if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Index ) ) { if ( BV -> isConstant ( ) && IndexWidth > <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits (


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT>


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , DAG . getNode ( <STR_LIT> , DL


<s> Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr . getValueType ( ) ) ; return true


<s> return ( __m256 ) __builtin_ia32_getexpps256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 )


<s> const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( <NUM_LIT> ) ; unsigned VR = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; TII . loadRegFromStack ( MBB , I , VR , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , Dst )


<s> const InstructionSelector * getInstructionSelector ( )


<s> if ( ! Op . isExpr ( ) ) return false ; const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; return Ref && Ref -> getKind (


<s> static void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx )

, gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> const FeatureBitset ArchCheck ; const FeatureBitset Features ; } Extensions [ ] = { { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> } } , { ( <STR_LIT> | <STR_LIT> ) , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV6KBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_2aBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_1MMainlineBit } , { <STR_LIT> } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , } ; MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Name = Parser . getTok ( ) . getString ( ) ; SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) return Error


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C ) { Ctx =


<s> return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; auto IsUnitDup = [ ] ( auto * I ) { auto * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; auto * SplatValue = IntrI -> getOperand ( <NUM_LIT> ) ; return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; if ( IsUnitDup ( OpMultiplicand ) || IsUnitDupX ( OpMultiplicand ) ) std ::

swap ( OpMultiplier , OpMultiplicand ) ;


<s> static void aarch64_destroy_cost_data ( void * data ) { delete static_cast < aarch64_vector_costs * > (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue (


<s> unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI -> getOperand ( <NUM_LIT> ) .


<s> raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid << '_' << uid2 ; return OutContext . GetOrCreateSymbol ( Name . str


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( ! MCID ) { return ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> return __builtin_mve_vmulq_sv8hi ( __a ,


<s> void LLVMInitializePowerPCAsmPrinter ( ) { TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>AsmPrinterPass ) ; TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>AsmPrinterPass


<s> Lex ( ) ; const MCExpr * Value ; if ( Parser . parseExpression ( Value ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo &


<s> else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL


<s> if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return true


<s> return ( ( ( ( short ) ( ( __signed__ char * ) p ) [ <NUM_LIT> ] ) << <NUM_LIT> ) |

( ( unsigned char * ) p ) [ <NUM_LIT> ] ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; assert ( ( unsigned ) NumBytes >= ArgRegsSaveSize && <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; Register FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize , <STR_LIT> , MachineInstr :: NoFlags ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister =


<s> bool <ISA_LIT>FastISel :: FastLowerArguments ( ) { return false


<s> Addr . BaseType = Address :: RegBase ; } if ( ! UseOffset ) { IntegerType * OffsetTy = ( ( VT == <STR_LIT> ) ? Type :: getInt32Ty ( * Context ) : Type :: getInt64Ty ( * Context ) ) ; const ConstantInt * Offset = ConstantInt :: getSigned ( OffsetTy , ( int64_t ) ( Addr .


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( <STR_LIT> ( M , <STR_LIT> )


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { auto I = MI -> getIterator ( ) ; auto E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( & * I ++ ) ; } while ( ( I != E )


<s> if ( TM . getOptLevel ( ) == CodeGenOpt


<s> vpmaxnms_f32 ( float32x2_t a ) { return __builtin_aarch64_reduc_smax_scal_v2sf ( a


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; default : llvm_unreachable (


<s> rtx mask = gen_reg_rtx ( mode ) ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse ; emit_insn ( insn ( mask , op0 , op1 , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return


<s> switch ( MatchResult ) { default : break ; case Match_Success : { if ( needsExpansion ( Inst ) ) { SmallVector < MCInst , <NUM_LIT> > Instructions ; expandInstruction ( Inst , IDLoc , Instructions ) ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) { Out . EmitInstruction ( Instructions [ i ] , getSTI ( ) ) ; } } else { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( <NUM_LIT>

- i - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> void <ISA_LIT>FrameLowering :: emitSPExtend ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int NumBytes ) const { DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( )


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; } return MO . getImm ( )


<s> bool isBDAddr64Disp12 ( ) const { return isMemDisp12 ( BDMem , GR64Reg


<s> EVT InVT = <STR_LIT> ( <STR_LIT> ( InBits ) , <STR_LIT> / InBits ) ; SDValue PackedOp = DAG . getNode ( <STR_LIT> , DL , InVT , Op ) ; unsigned OutBits =


<s> case MachineOperand :: MO_GlobalAddress : return lowerSymbolOperand ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_ExternalSymbol : { StringRef Name = MO . getSymbolName ( ) ; return lowerSymbolOperand ( MO , AsmPrinter . GetExternalSymbolSymbol ( Name ) , MO . getOffset ( ) ) ; } case MachineOperand :: MO_JumpTableIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) , <NUM_LIT> ) ; case MachineOperand :: MO_ConstantPoolIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_BlockAddress


<s> CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC .


<s> case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; std :: swap ( LHS


<s> V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) &&


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand

( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> void <ISA_LIT>Relocator :: addCopyReloc ( ResolveInfo & pSym ) { Relocation & rel_entry = * getTarget ( ) . getRelaDyn ( ) . create ( ) ; rel_entry . setType ( llvm


<s> return isMemRegImm ( ) || isMemRegReg (


<s> OperandMatchResultTy parsePKHASRImm ( OperandVector & O ) { return parsePKHImm ( O , <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> if ( EmitFPOData ) { <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : XTS -> emitFPOPushReg ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : XTS -> emitFPOStackAlloc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; XTS -> emitFPOSetFrame ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : XTS -> emitFPOEndPrologue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ; } switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : OutStreamer -> EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFIAllocStack ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISetFrame ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT>


<s> static recpe_type get_recpe_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return ( gen_aarch64_frecpesf ) ; case E_V2SFmode : return ( gen_aarch64_frecpev2sf ) ; case E_V4SFmode : return ( gen_aarch64_frecpev4sf ) ; case E_DFmode : return ( gen_aarch64_frecpedf ) ; case E_V2DFmode : return ( gen_aarch64_frecpev2df


<s> bool Dcpu16PassConfig :: addPreEmitPass (


<s> if ( ! * name ) { int res = snprintf ( name , STUB_NAME_MAX_LEN , <STR_LIT> , ( have_avx ? <STR_LIT> : <STR_LIT> ) , STUB_BASE_NAMES [ stub ] ,