<s> SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0


<s> } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = VectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; } for ( unsigned i = <NUM_LIT> ; i < NumLoads ; i ++ ) { Value * NewBasePtr = Builder . CreateGEP ( VecBaseTy , VecBasePtr , Builder . getInt32 ( i ) ) ; Instruction * NewLoad = Builder . CreateAlignedLoad ( VecBaseTy , NewBasePtr , LI -> getAlign ( ) ) ; DecomposedVectors . push_back ( NewLoad


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode ::

COPY ) , DestReg ) . addReg ( SrcReg ) ;


<s> return ( int16x8_t ) __builtin_neon_vdup_nv8hi ( ( __builtin_neon_hi )


<s> if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES


<s> return ( __m128i ) __builtin_ia32_vprotw ( ( __v8hi ) __A ,


<s> if ( LinkerConfig :: DynObj == config ( ) . codeGenType ( )

|| m_pGOTPLT -> hasGOT1 ( ) || m_pGOTSymbol != NULL ) {


<s> bool isImm7s4 ( ) const { return isImmediateS4 < - <NUM_LIT> ,


<s> getTargetStreamer ( ) . emit<ISA_LIT>WinCFISaveLR ( Offset ) ; return false


<s> return __builtin_mve_vbicq_n_uv4si ( __a ,


<s> if ( ! Subtarget . hasAVX512 ( ) ) return false ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) ) return false ; if ( ! VT . isVector ( ) ) return false ; return


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Tmp = DAG . getConstantFP ( APF , dl , <STR_LIT> ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Tmp ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSelectCC ( dl , Op . getOperand ( <NUM_LIT> ) , Tmp , True , False , <STR_LIT> ) ; } } return SDValue ( ) ; } if ( Subtarget . hasDirectMove ( ) && Subtarget . is<ISA_LIT>64 ( ) ) return LowerFP_TO_INTDirectMove ( Op


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MF . getInfo <

<ISA_LIT>MachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ;


<s> unsigned SCIdx = TII -> get ( <STR_LIT> ) . getSchedClass ( ) ; const MCSchedClassDesc * SCDesc = SchedModel . getMCSchedModel ( ) -> getSchedClassDesc ( SCIdx ) ; if ( SCDesc -> isValid ( ) && ! SCDesc -> isVariant ( ) ) { unsigned ResLenWithSTP = BBTrace . getResourceLength ( ArrayRef < const MachineBasicBlock * > ( ) , SCDesc ) ; if ( ResLenWithSTP >


<s> for ( auto I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : if ( TLSBaseAddrReg ) I = ReplaceTLSCall ( & * I , TLSBaseAddrReg ) ; else I = SetRegister ( & *


<s> args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; prev_arg_type = arg_type ; if ( VOID_TYPE_P ( arg_type ) ) continue ; function_arg_info arg ( arg_type , true ) ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg ) ; arg_rtx = arm_function_arg ( args_so_far , arg ) ; if ( ! arg_rtx || arm_arg_partial_bytes ( args_so_far ,


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { SDValue RelAddr ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( )

, CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { if ( DefRelocModel == Reloc :: Default && ( ! Subtarget . isTargetDarwin ( ) || ! Subtarget . is64Bit ( ) ) ) { setRelocationModel ( Reloc :: Static ) ; Subtarget . setPICStyle ( PICStyles :: None ) ; } PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return


<s> return FullVT -> getNumElements ( ) == <NUM_LIT> * HalfVT -> getNumElements ( ) ; } ; ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_ShuffleVector ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_ShuffleVector ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ; int M1Start = - <NUM_LIT> ; int M2Start = - <NUM_LIT> ; int NumElements = cast < VectorType > ( Op1 -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ; if ( ! ShuffleVectorInst :: isExtractSubvectorMask ( M1 , NumElements , M1Start ) || ! ShuffleVectorInst :: isExtractSubvectorMask ( M2 , NumElements , M2Start ) || M1Start

!= M2Start || ( M1Start != <NUM_LIT> && M2Start != ( NumElements / <NUM_LIT> ) ) ) return false ;


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass (


<s> if ( ! SomeVT . isVector ( ) ) return false ; return SomeVT . getVectorElementType ( ) ==


<s> MI . removeOperand ( std :: min ( Op1 , Op2 ) ) ; if ( MaxOp - MinOp == <NUM_LIT> && MI . getNumOperands ( ) == MinOp ) { MI . addOperand ( MOp2 ) ; MI . addOperand ( MOp1 ) ; } else { SmallVector < MachineOperand , <NUM_LIT> > MOps ; unsigned TotalOps = MI . getNumOperands ( ) + <NUM_LIT> ; for ( unsigned i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= MinOp ; i -- ) { MOps . push_back ( MI .


<s> if ( ( old_flags ^ target_flags ) & ( MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH4 ) ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_HITACHI ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_LITTLE_ENDIAN ) return _ ( <STR_LIT> ) ; return


<s> static bool nds32_use_blocks_for_constant_p ( machine_mode mode , const_rtx x ATTRIBUTE_UNUSED ) { if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && ( mode

== DFmode || mode == SFmode ) ) return true ;


<s> mips_adjust_block_mem ( dest , MAX_MOVE_BYTES , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; mips_block_move_straight ( dest , src , MAX_MOVE_BYTES ) ; emit_move_insn ( src_reg , plus_constant ( src_reg , MAX_MOVE_BYTES ) ) ; emit_move_insn ( dest_reg , plus_constant ( dest_reg , MAX_MOVE_BYTES ) ) ; if ( Pmode == DImode ) emit_insn ( gen_cmpdi ( src_reg , final_src ) ) ; else emit_insn ( gen_cmpsi ( src_reg , final_src ) ) ; emit_jump_insn ( gen_bne (


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { if ( DarwinDirective == <STR_LIT> ) return false ; Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( is<ISA_LIT>64 ( ) ) CriticalPathRCs . push_back (


<s> else if ( XINT ( operands [ funop + <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) sprintf ( arg , <STR_LIT> ) ; } char z [ <NUM_LIT> ] ; sprintf ( z , <STR_LIT> , funop , ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; static char str [ <NUM_LIT> ] ; if ( rs6000_pcrel_p ( ) ) sprintf ( str , <STR_LIT> , sibcall ? <STR_LIT> : <STR_LIT> , z , arg ) ; else if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) sprintf ( str , <STR_LIT> , sibcall ? <STR_LIT> : <STR_LIT> , z , arg , sibcall ? <STR_LIT> : <STR_LIT> ) ; else if ( DEFAULT_ABI == ABI_V4 ) sprintf ( str , <STR_LIT> , sibcall ? <STR_LIT> : <STR_LIT> , z , arg , flag_pic ? <STR_LIT> : <STR_LIT> ) ; else if ( DEFAULT_ABI == ABI_DARWIN ) { gcc_checking_assert ( GET_CODE ( operands [ funop + <NUM_LIT> ] ) == CONST_INT ) ; int cookie = INTVAL ( operands [ funop + <NUM_LIT> ] ) ; if ( cookie & CALL_LONG ) { tree funname = get_identifier ( XSTR ( operands [ funop ] , <NUM_LIT> ) ) ; tree labelname = get_prev_label ( funname ) ; gcc_checking_assert ( labelname && ! sibcall ) ; sprintf ( str , <STR_LIT> , funop , IDENTIFIER_POINTER ( labelname


<s> case TargetOpcode :: DBG_VALUE : { if ( ! isVerbose ( ) || ! OutStreamer . hasRawTextSupport ( ) ) return ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; unsigned NOps = MI -> getNumOperands ( ) ; assert ( NOps == <NUM_LIT> ) ; O << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static unsigned HOST_WIDE_INT ix86_memmodel_check ( unsigned HOST_WIDE_INT val ) { enum memmodel model = memmodel_from_int ( val ) ; bool strong ; if ( val & ~ ( unsigned HOST_WIDE_INT ) ( IX86_HLE_ACQUIRE | IX86_HLE_RELEASE | MEMMODEL_MASK ) || ( ( val & IX86_HLE_ACQUIRE ) && ( val & IX86_HLE_RELEASE ) ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST ; } strong = ( is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) ; if ( val & IX86_HLE_ACQUIRE && ! ( is_mm_acquire ( model ) ||


( ) , ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; bool has_dyn_rel = ( dyn_rel != NULL ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( <NUM_LIT> == ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) ) { pReloc . target ( ) = S + A ; return Relocator :: OK ; } if ( rsym -> isLocal ( ) && has_dyn_rel ) { dyn_rel -> setAddend ( S + A ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_AARCH64_ABS64 == pReloc . type ( ) && llvm :: ELF :: R_AARCH64_RELATIVE == dyn_rel -> type ( ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator :: OK


<s> InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT>


<s> return new <ISA_LIT>WinCOFFAsmTargetStreamer ( S , OS , * InstPrinter


<s> unsigned <ISA_LIT>FastISel :: emitIntExt ( MVT SrcVT , unsigned SrcReg , MVT DestVT , bool isZExt ) { unsigned DestReg = createResultReg (


<s> if ( ConditionVT . getSizeInBits ( ) < <NUM_LIT> ) return <STR_LIT> ; return TargetLoweringBase :: getPreferredSwitchConditionType ( Context ,


<s> static bool ck803_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case SET : if ( MEM_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct csky_address op1 ; bool address_valid = decompose_csky_address ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , & op1 ) ; if ( op1 . index ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( address_valid ) { * total = COSTS_N_INSNS ( <NUM_LIT> )


<s> unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; assert ( CCMask > <NUM_LIT> && CCMask < <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) ) { if ( unsigned CondOpcode = getConditionalMove ( Opcode ) ) { MI . setDesc ( get ( CondOpcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } } if ( Opcode == <STR_LIT> ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true


<s> if ( Inst . startswith ( <STR_LIT> ) || Inst . startswith ( <STR_LIT> ) ) { StringRef AddressingMode = Inst . substr ( <NUM_LIT> , <NUM_LIT> ) ; if ( AddressingMode == <STR_LIT> || AddressingMode == <STR_LIT> || AddressingMode == <STR_LIT> ||


<s> if ( isTypeSupported ( ZE -> getType ( ) , RetVT ) ) IntExtVal = ZE ; else RetVT = VT ; } else if ( const auto * SE = dyn_cast < SExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( SE -> getType ( ) , RetVT ) ) IntExtVal = SE ; else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { unsigned Reg = lookUpRegForValue ( IntExtVal ) ; auto * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) { if ( RetVT == <STR_LIT> && VT <= <STR_LIT> ) { if ( WantZExt ) { std :: prev ( FuncInfo . InsertPt ) -> eraseFromParent ( ) ; ResultReg = std :: prev ( FuncInfo . InsertPt ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , ResultReg , true , <STR_LIT> ) ; } updateValueMap ( I , ResultReg ) ; return true ; } while ( MI ) { Reg = <NUM_LIT> ; for ( auto & Opnd : MI -> uses ( ) ) { if ( Opnd . isReg ( ) ) { Reg = Opnd . getReg ( ) ; break ; } } MI -> eraseFromParent ( ) ; MI = nullptr ; if ( Reg ) MI = MRI


<s> bool useWideStrideVFP ( ) const { return UseWideStrideVFP


<s> while ( true ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: Integer : case AsmToken ::


<s> EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX512 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL , Subtarget , DAG ) ; return SDValue (


<s> } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getBuildVector ( <STR_LIT> , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DAG . getBuildVector ( <STR_LIT> , DL , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; else V = V1InUse ? V1 : V2 ; return DAG . getBitcast ( VT ,


<s> return ( __m512d ) __builtin_ia32_rsqrt14pd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_undefined_pd ( )


<s> vpadalq_s32 ( int64x2_t a , int32x4_t b ) { int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> return __builtin_aarch64_lflooruhfsi_us (


<s> return llvm :: create<ISA_LIT>SEFrameLowering


<s> if ( OverrideVectorInsertExtractBaseCost . getNumOccurrences ( ) > <NUM_LIT> ) return OverrideVectorInsertExtractBaseCost ; return VectorInsertExtractBaseCost


<s> Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != Width ) return false ; } else { Shift = <NUM_LIT> ; Expr = getImm ( ) ; } <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ||

ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ;


<s> return ( int16x4_t ) __builtin_neon_vpaddlsv8qi


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; bool CanFoldLoad = false ; if ( MayFoldVectorLoad ( V2 ) ) CanFoldLoad = true ; else if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( CanFoldLoad ) { if ( HasSSE2 && NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; if ( NumElems == <NUM_LIT> ) if ( SVOp -> getMaskElt ( <NUM_LIT> ) != - <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT>


<s> if ( Subtarget . isThumb1Only ( ) ) return false ; assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / <NUM_LIT> > <NUM_LIT> ) return false ; if ( ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) && ! ( ( Load1 -> getMachineOpcode ( ) == <STR_LIT> && Load2 -> getMachineOpcode ( ) == <STR_LIT> ) || ( Load1 -> getMachineOpcode (

) == <STR_LIT> && Load2 -> getMachineOpcode ( ) == <STR_LIT> ) ) ) return false ;


<s> Function * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ; return CallInst :: Create ( Intr -> getFunctionType ( ) , Intr , Args


<s> return ( poly8x8_t ) __builtin_neon_vset_lanev8qi ( ( __builtin_neon_qi ) __a , ( int8x8_t )


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler


<s> bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( ! IsPIC && ! IsN64 ) { JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; HiPart = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI ) ; JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; } else { unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OfstFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , GOTFlag ) ; JTI = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI ) ; HiPart = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return getSubtargetImpl ( ) -> getFrameLowering


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> mcld :: RegisterTarget < llvm :: Triple :: thumb


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == <STR_LIT> ) return <NUM_LIT> ; return <ISA_LIT>TargetLowering :: getNumRegisters (


<s> return isPromotableZeroStoreOpcode ( MI . getOpcode


<s> fprintf ( stream , <STR_LIT> ) ; OUTPUT_QUOTED_STRING ( stream , name ) ; fprintf ( stream


<s> Chain = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Result , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops1 [ ] = { Chain , DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , DAG . getRegister ( <STR_LIT> , PtrVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops1 , <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ,


<s> for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define )

. addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> } else { if ( regno_base == SP_REGNUM ) sprintf ( pattern , <STR_LIT> , conditional ) ; if ( update ) sprintf ( pattern , <STR_LIT> , conditional ) ; else sprintf ( pattern , <STR_LIT> , conditional ) ; strcat ( pattern , reg_names [ regno_base ] ) ; if ( update ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern , <STR_LIT> ) ; } strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , offset ) , <NUM_LIT> ) ) ] ) ; for ( i = offset + <NUM_LIT> ; i < num_saves ; i ++ ) { strcat ( pattern , <STR_LIT> ) ; strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , i ) , <NUM_LIT> ) ) ] ) ; } strcat ( pattern , <STR_LIT> ) ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) && return_pc ) strcat ( pattern , <STR_LIT> ) ; output_asm_insn ( pattern ,


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter (


<s> RegisterTargetMachine < ThumbTargetMachine >


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget .


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return const_cast < <ISA_LIT>TargetLowering * > (


<s> inline machine_mode function_instance :: gp_mode ( unsigned int i ) const { return aarch64_sve_pred_mode ( type_suffix ( i ) . element_bytes ) . require


<s> bool csky_legitimate_pic_operand_p ( rtx x ) { if ( tls_unspec_mentioned_p ( x ) ) return true ; if ( csky_symbol_mentioned_p ( x ) || csky_label_mentioned_p ( x ) ) return false ; return true


<s> case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16BFmode : extract = gen_avx_vextractf128v16bf ; mode = V8BFmode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case E_V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , <NUM_LIT> ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , <NUM_LIT> ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ; addExpr ( Inst


<s> } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind =


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return I -> getFlag ( MachineInstr :: FrameSetup ) || I -> getFlag ( MachineInstr


<s> MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> GetInstSizeInBytes ( & * MI ) ; ReverseIter End = MBB ->


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; static const unsigned FirstRegs [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ,


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return ( <STR_LIT> ) N -> getConstantOperandVal ( <NUM_LIT> ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) return ( <STR_LIT> ) N -> getConstantOperandVal ( <NUM_LIT> ) ; else llvm_unreachable (


<s> break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address

, Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static DecodeStatus decodeS8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void


<s> if ( isAllActivePredicate ( Pg ) ) { if ( UnpredOp ) return DAG . getNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; else return DAG . getNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Pg , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>


<s> if ( ( uint32_t ) Fixup . getKind ( )


<s> State = EMS_None ; MCELFStreamer :: reset ( )


<s> extern long long _U_Qfcnvfxt_quad_to_dbl ( long double


<s> static bool rs6000_is_opaque_type ( tree type ) { return ( type == opaque_V2SI_type_node || type == opaque_V2SF_type_node || type == opaque_p_V2SI_type_node || type ==


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset +

i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( CE ) { Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; return ; } const MCSymbolRefExpr * SR = dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ; assert ( SR && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( SR ) ) ; return ; } assert ( isMem ( )


<s> int32_t max = ( <NUM_LIT> << ( bits - <NUM_LIT> ) ) - <NUM_LIT> ; int32_t min = - ( <NUM_LIT> << ( bits


<s> uint16x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = (


<s> return ( __m128 ) __builtin_ia32_maxps ( ( __v4sf ) __A , (


<s> if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; switch ( FlagUI -> getMachineOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( __m128i ) __builtin_ia32_expandqi128_mask ( ( __v16qi ) __C , ( __v16qi )


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn ,

Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) )


<s> ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o , <NUM_LIT> ) ; return


<s> cfun -> machine -> force_align_arg_pointer = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; return copy_to_reg ( cfun -> machine -> force_align_arg_pointer


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( )


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm )


<s> return Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> :


<s> bool hasNEON ( ) const { return <ISA_LIT>FPUType >=


<s> return ( float32x2_t ) __builtin_neon_vrintmv2sf (


<s> if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2


<s> return __builtin_loongson_pcmpeqw_u ( s


<s> } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; SmallVector < MachineOperand , <NUM_LIT> > MOs ; if ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) { unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const VectorType * Ty = VectorType :: get (


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( )


<s> void <ISA_LIT>AsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> unsigned Op0Opc = Op0 . getOpcode ( ) ; unsigned Op1Opc = Op1 . getOpcode ( ) ; unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { APInt MKZ , MKO ; CurDAG -> ComputeMaskedBits ( Op1 . getOperand ( <NUM_LIT> ) , MKZ , MKO ) ; bool CanFoldMask = InsertMask == MKO . getZExtValue


<s> assert ( User && <STR_LIT> ) ; if ( User -> getOpcode ( ) != Instruction :: FSub && User -> getOpcode ( ) != Instruction :: FAdd ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F ->


<s> case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( RegName ) ; if ( RegKind == <STR_LIT> ) RegNum /= <NUM_LIT> ; else if ( RegKind == <STR_LIT> && ! isFP64 ( ) ) if ( RegNum != - <NUM_LIT> && RegNum % <NUM_LIT> != <NUM_LIT> ) Warning ( S , <STR_LIT> ) ; break ; case <STR_LIT> : RegNum = matchFCCRegisterName ( RegName ) ; break ; case <STR_LIT> : RegNum = matchACRegisterName ( RegName ) ; break ; default : break ; } if ( RegNum < <NUM_LIT> ) return MatchOperand_NoMatch ; int RegVal = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; if ( RegVal == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( RegVal , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; hasConsumedDollar = false ; Parser . Lex ( ) ; return MatchOperand_Success ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; if ( Kind == <STR_LIT> ) { if ( RegNum != <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = <NUM_LIT> ; } int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( Kind ) ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; hasConsumedDollar = false ; Parser . Lex ( ) ; if ( ( RegKind == <STR_LIT> ) && ( getLexer ( ) . is ( AsmToken :: LParen ) ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( parseRegs ( Operands , RegKind ) != MatchOperand_Success ) return MatchOperand_NoMatch ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return MatchOperand_NoMatch ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return MatchOperand_Success ; } return MatchOperand_NoMatch


<s> for ( j = i + <NUM_LIT> ; j < nops ; j ++ ) if ( regs [ i ] == regs [ j ] ) { rtx t = peep2_find_free_register ( <NUM_LIT> , nops * <NUM_LIT> , TARGET_THUMB1 ? <STR_LIT> : <STR_LIT> , SImode , & allocated ) ; if ( t == NULL_RTX ) return false ; reg_rtxs [ i ] = t ; regs [ i ] = REGNO ( t ) ; } } reg_order [ <NUM_LIT> ] = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) if ( regs [ i ] < regs [ reg_order [ <NUM_LIT> ] ] ) reg_order [ <NUM_LIT> ] = i ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) { int this_order = reg_order [ i - <NUM_LIT> ] ; for ( j = <NUM_LIT> ; j < nops ; j ++ ) if ( regs [ j ] > regs [ reg_order [ i - <NUM_LIT> ] ] && ( this_order == reg_order [ i - <NUM_LIT> ] || regs [ j ] < regs [ this_order ] ) ) this_order = j ; reg_order [ i ] = this_order ; } for ( i = <NUM_LIT> ; i < nops ; i ++ ) { int this_order = reg_order [ i ] ; if ( ( this_order != mem_order [ i ] || orig_reg_rtxs [ this_order ] != reg_rtxs [ this_order ] ) && ! peep2_reg_dead_p ( nops * <NUM_LIT> , orig_reg_rtxs [ this_order ] ) ) return false ; } for ( i = <NUM_LIT> ; i < nops ; i ++ ) { rtx op = operands [ <NUM_LIT> * nops + mem_order [ i ] ] ; sorted_regs [ i ] = regs [ reg_order [ i ] ] ; emit_move_insn ( reg_rtxs [ reg_order [ i ] ] ,


<s> bool SelectAddrImmOffs ( SDValue Op , SDValue N , SDValue & Out ) const { Out =


<s> static bool isPrecededByMatchingHi ( const MCAssembler & Asm , uint32_t Index , std :: vector < <ISA_LIT>RelocationEntry > & <ISA_LIT>Relocs ) { return Index < <ISA_LIT>Relocs . size ( ) - <NUM_LIT> && areMatchingHiAndLo ( Asm , <ISA_LIT>Relocs [ Index + <NUM_LIT>

] . R , <ISA_LIT>Relocs [ Index ] . R ) ;


<s> bool isLegalMaskedStore ( Type * DataType ,


<s> getImm ( ) -> print ( OS ) ; break ; case MemBarrierOpt : OS << <STR_LIT> << MemBOptToString ( getMemBarrierOpt ( ) ) << <STR_LIT> ; break ; case Memory : OS << <STR_LIT> << <STR_LIT> << getMemBaseRegNum ( ) ; if ( getMemOffsetIsReg ( ) ) { OS << <STR_LIT> << getMemOffsetRegNum ( ) ; if ( getMemOffsetRegShifted ( ) ) { OS << <STR_LIT> << getMemShiftType ( ) ; OS << <STR_LIT> << * getMemShiftAmount ( ) ; } } else { OS << <STR_LIT> << * getMemOffset ( ) ; } if ( getMemOffsetIsReg ( ) ) OS << <STR_LIT> ; if ( getMemPreindexed ( ) ) OS << <STR_LIT> ; if ( getMemPostindexed ( ) ) OS << <STR_LIT> ; if ( getMemNegative ( ) ) OS << <STR_LIT> ; if ( getMemWriteback ( ) ) OS << <STR_LIT> ; OS << <STR_LIT> ; break ; case ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case RegisterList : case DPRRegisterList : case SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT>


<s> case 'H' : { if ( OpNo == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return


long long __B , long long __C , long long __D ) {


<s> addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) )


<s> bool <ISA_LIT>PostLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { CombinerHelper Helper ( Observer , B , KB , nullptr , LInfo ) ; <ISA_LIT>GenPostLegalizerCombinerHelper Generated ( GeneratedRuleCfg ,


<s> MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx ) { MachineOperand & MO = Instr -> getOperand ( OpIdx ) ; const TargetRegisterClass * OpRegCstraints = Instr -> getRegClassConstraint ( OpIdx , TII , TRI ) ; if ( ! OpRegCstraints ) continue ; if ( MO . isFI ( ) ) continue ; assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) { if ( ! OpRegCstraints -> contains ( Reg ) ) return false ; } else if ( ! OpRegCstraints -> hasSubClassEq ( MRI -> getRegClass ( Reg ) ) && ! MRI -> constrainRegClass ( Reg , OpRegCstraints ) ) return false ; } return true


<s> if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI .


<s> } if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> && CondTy ) { static const TypeConversionCostTblEntry NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT .


<s> return ( int16x8_t ) __builtin_neon_vabsv8hi (


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) ,


<s> const LDSymbol * getGOTSymbol ( ) const


<s> OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; for ( <ISA_LIT>COFFMachineModuleInfo :: stub_iterator I = COFFMMI . stub_begin ( ) , E = COFFMMI . stub_end ( ) ; I != E ; ++ I ) { O << <STR_LIT> << I -> getKeyData ( ) << <STR_LIT> << COFF :: C_EXT << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ; } if ( Subtarget -> isTargetCygMing ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getCOFFSection ( <STR_LIT> , true , SectionKind :: getMetadata ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) O << <STR_LIT> << * DLLExportedGlobals [ i ] << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = DLLExportedFns . size ( ) ; i != e ; ++ i ) O << <STR_LIT> << * DLLExportedFns [ i ] << <STR_LIT> ; } } } if ( Subtarget -> isTargetELF ( ) ) { TargetLoweringObjectFileELF & TLOFELF = static_cast < TargetLoweringObjectFileELF & >


<s> } if ( MI -> mayStore ( ) ) { if ( SawStore ) return true ; SawStore = true ; if ( SawLoad ) return true ; } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef (


<s> MCSubtargetInfo & STI = copySTI ( ) ; uint64_t FB = ComputeAvailableFeatures ( STI . ToggleFeature ( <STR_LIT> ) ) ; setAvailableFeatures (


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << <STR_LIT> ; return false ; } case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum


<s> FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return


<s> if ( OptLevel != CodeGenOpt :: None && Subtarget .


<s> MI . addOperand ( MCOperand :: CreateReg ( B -> InITBlock ( ) ? <NUM_LIT> : <STR_LIT> ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; } else


<s> aarch64_cmodel = AARCH64_CMODEL_SMALL_PIC ; } break ; case AARCH64_CMODEL_LARGE : if ( opts -> x_flag_pic ) sorry ( <STR_LIT> , <STR_LIT> , opts -> x_flag_pic > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( opts -> x_aarch64_abi == AARCH64_ABI_ILP32 ) sorry ( <STR_LIT> , <STR_LIT> ) ; break ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL_SPIC : gcc_unreachable (


<s> if ( VT != <STR_LIT> && ( ! HasAVX2 || VT != <STR_LIT> ) ) return false ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT>


<s> unsigned Reg ; const <ISA_LIT>Subtarget & Subtarget = State . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetELF ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else if ( Subtarget . isTargetXPLINK64 ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Offset = Reg ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( Offset ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { int ISDOpcode = TLI -> InstructionOpcodeToISD ( Opcode ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < <STR_LIT> > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx = - <NUM_LIT> ; if ( ST -> hasNEON ( ) ) Idx = CostTableLookup (


<s> static DecodeStatus DecodeShiftRight32Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler :: Success


<s> unsigned getMaximumUnrollFactor ( ) const override { if ( ST -> isCortexA15 ( ) || ST -> isSwift ( ) ) return <NUM_LIT> ; return


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame (


<s> Value * <ISA_LIT>IREmitter :: visitVZEXT_MOVL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS ; if ( from == dregs ) return mips_move_from_gpr_cost ( to ) ; if ( to == dregs ) return mips_move_to_gpr_cost ( from ) ; cost1 = mips_move_to_gpr_cost ( from


<s> unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasNoRedZoneAttr ( ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize


<s> State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Op , DAG ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: combineINT_TO_FP ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( DCI . Level != BeforeLegalizeTypes ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; LLVMContext & Ctx = * DAG . getContext ( ) ; unsigned Opcode = N -> getOpcode ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; Type * OutLLVMTy = OutVT . getTypeForEVT ( Ctx ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OutScalarBits = OutLLVMTy -> getScalarSizeInBits ( ) ; unsigned InScalarBits = Op -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; if ( OutLLVMTy -> isVectorTy ( ) && OutScalarBits > InScalarBits && OutScalarBits <=


<s> case <STR_LIT> : return lowerV16I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : if ( Subtarget -> hasBWI ( ) ) return lowerV32I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; break ; case <STR_LIT> : if ( Subtarget -> hasBWI ( ) ) return lowerV64I8VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { assert ( GISel && <STR_LIT> ) ; return GISel -> getRegBankInfo (


<s> bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( Rt == Rt2 ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2AddrModeImm8s4 ( Inst , addr , Address , Decoder ) )


<s> } if ( Subtarget . hasSPE ( ) ) FlagSet |= <STR_LIT> ; if ( const LSBaseSDNode * LSB = dyn_cast < LSBaseSDNode > ( Parent ) ) if ( LSB -> isIndexed ( ) ) return <STR_LIT> ; const MemSDNode * MN = dyn_cast < MemSDNode > ( Parent ) ; assert ( MN && <STR_LIT> ) ; EVT MemVT = MN -> getMemoryVT ( ) ; unsigned Size = MemVT . getSizeInBits ( ) ; if ( MemVT . isScalarInteger ( ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; if ( Size < <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else FlagSet |= <STR_LIT> ; } else if ( MemVT . isVector ( ) && ! MemVT . isFloatingPoint ( ) ) { if ( Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } else { if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( MemVT == <STR_LIT> || MemVT . isVector ( ) ) FlagSet |= <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } computeFlagsForAddressComputation ( N , FlagSet , DAG ) ; if ( const LoadSDNode * LN = dyn_cast < LoadSDNode > ( Parent ) ) { switch ( LN -> getExtensionType ( ) ) { case <STR_LIT> : FlagSet |= <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : FlagSet |= <STR_LIT> ; break ; case <STR_LIT> : FlagSet |= <STR_LIT> ; break ; } } else FlagSet |=


<s> MachineFunction * MF = C . getMF ( ) ; const <ISA_LIT>RegisterInfo * ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! ARI -> isReservedReg ( * MF , Reg ) && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && C . LRU . available ( Reg ) && C . UsedInSequence . available ( Reg ) ) return Reg ; } return


<s> MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , ImpDef , N , SubReg ) ; return SDValue ( Node ,


<s> if ( get<ISA_LIT>Subtarget ( ) . useConstIslands ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( create<ISA_LIT>NaClRewritePass ( )


<s> EVT ResVT = TLI -> getValueType ( DL , ResTy ) ; if ( ST -> hasMVEIntegerOps ( ) && ValVT . isSimple ( ) && ResVT . isSimple ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= <NUM_LIT> ) || ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= ( IsMLA ? <NUM_LIT> : <NUM_LIT> ) ) || ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= <NUM_LIT> ) ) return ST -> getMVEVectorCostFactor


<s> static void setCallTargetReg ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I ) { MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg


<s> break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: Alloca : { const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> )


<s> if ( DestRC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( SrcReg ) ; else BuildMI ( MBB , MI , DL , get ( <STR_LIT>


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) .


<s> bool convertSelectOfConstantsToMath ( ) const


<s> rtx_insn * i = emit_insn ( gen_rtx_SET ( VOIDmode , m_ccreg , gen_rtx_fmt_ee ( XOR , GET_MODE ( m_ccreg ) , m_ccreg , const1_rtx ) ) ) ; end_sequence ( ) ; return i


<s> int k ; bool neon = false ; bool mve = false ; if ( IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - <NUM_LIT> ) ) neon = true ; if ( IN_RANGE ( fcode , ARM_BUILTIN_MVE_BASE , ARM_BUILTIN_MAX - <NUM_LIT> ) ) mve = true ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = ARG_BUILTIN_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_pair_index ) args


<s> Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; It = MBB . insert ( It , CallMIB ) ; return It


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ; if ( isSVR4ABI ( ) && is64BitMode ( ) ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; else Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO


<s> unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( Reg , true ) + <NUM_LIT> ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT>


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out


<s> assert ( From < <NUM_LIT> && To < <NUM_LIT> && From >= To ) ; uint32_t Mask = ( ( <NUM_LIT> << ( From - To + <NUM_LIT> ) ) - <NUM_LIT> ) ; Bits &= ~ ( Mask <<


<s> in = ( vec_ushort8 ) ( a ) ; mask = ( vec_char16 ) ( vec_perm ( in , in , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( )


<s> __builtin_neon_vst3v8hi ( ( __builtin_neon_hi * ) __a ,


<s> return ( __m512i ) __builtin_ia32_vcvttph2dq512_mask_round ( __A , ( __v16si ) _mm512_setzero_si512 ( )

, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitAtomicLoadMinMax ( MachineInstr * MI , MachineBasicBlock * MBB , unsigned CompareOpcode , unsigned KeepOldMask , unsigned BitSize ) const { MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool IsSubWord = ( BitSize < <NUM_LIT> ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; unsigned NegBitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = MRI . createVirtualRegister ( RC ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return Lower256IntUnary ( Op ,


<s> bool always_inline = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( callee ) ) ; if ( always_inline ) return true ; if ( caller_opts -> x_aarch64_cmodel_var != callee_opts -> x_aarch64_cmodel_var ) return false ; if ( caller_opts -> x_aarch64_tls_dialect != callee_opts -> x_aarch64_tls_dialect ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err835769 , callee_opts -> x_aarch64_fix_a53_err835769 , <NUM_LIT> , TARGET_FIX_ERR_A53_835769_DEFAULT ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err843419 , callee_opts

-> x_aarch64_fix_a53_err843419 , <NUM_LIT> , TARGET_FIX_ERR_A53_843419 ) ) return false ;


<s> Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . isFPOnlySP ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst


<s> extern __inline float __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _m_to_float ( __m64 __A ) { union { __v2sf v ; float a [ <NUM_LIT> ] ; } __tmp ; __tmp . v = ( __v2sf ) __A ; return __tmp . a [ <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) || N -> getConstantOperandVal ( FirstOp ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG )


<s> static bool iq2000_return_in_memory ( tree type , tree


<s> SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) ; unsigned Opc = Cmp . getOpcode ( ) ; if ( is<ISA_LIT>LogicalCmp ( Cmp ) || Opc == <STR_LIT> ) { Cond = Cmp ; addTest = false ; } else { switch ( cast < ConstantSDNode > ( CC ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Cond = Cond . getNode ( ) -> getOperand ( <NUM_LIT> ) ; addTest = false ; break ; } } } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; addTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; SDValue User = SDValue ( * Op . getNode ( ) -> use_begin ( ) , <NUM_LIT> ) ; if ( User . getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User . getOperand ( <NUM_LIT> ) ; SDValue NewBR = DAG . UpdateNodeOperands ( User , User . getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR


<s> } APInt UsersUsefulBits ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; for ( SDNode * Node : Op . getNode ( ) -> uses ( ) ) { APInt UsefulBitsForUse = APInt ( UsefulBits ) ; getUsefulBitsForUse ( Node , UsefulBitsForUse , Op , Depth ) ; UsersUsefulBits |= UsefulBitsForUse ; } UsefulBits &=


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( VecWidth != <NUM_LIT> && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == <NUM_LIT> && Alignment >= <NUM_LIT> ) || ( EltWidth == <NUM_LIT> && Alignment

>= <NUM_LIT> ) || ( EltWidth == <NUM_LIT> ) ;


<s> return ( __m128 ) __builtin_ia32_cmpngeps ( ( __v4sf ) __A ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O )


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - <NUM_LIT> ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if (


<s> auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT OpVT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OpVT , Ops ) ; } ; auto BuildPMADDWD = [ & ] ( SDValue Mul ) { SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Madd ,

DAG . getConstant ( <NUM_LIT> , DL , MAddVT ) ) ;


<s> ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII .

get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) ) ;


<s> OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( LowerOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand (

<NUM_LIT> ) . getMBB ( ) , <ISA_LIT>MCExpr :: MEK_HI ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC


<s> ArrayRef < MCPhysReg > RegList ; if ( LocVT . SimpleTy == <STR_LIT> || ( IsDarwinILP32 && LocVT . SimpleTy == <STR_LIT> ) ) RegList = XRegList ; else if ( LocVT . SimpleTy == <STR_LIT> ) RegList = HRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is32BitVector ( ) ) RegList = SRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is64BitVector ( ) ) RegList = DRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is128BitVector ( ) ) RegList = QRegList ; else if ( LocVT . isScalableVector ( ) ) RegList = ZRegList ; else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned EltsPerReg = ( IsDarwinILP32 && LocVT . SimpleTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned RegResult = State . AllocateRegBlock ( RegList , alignTo ( PendingMembers . size ( ) , EltsPerReg ) / EltsPerReg ) ; if ( RegResult && EltsPerReg == <NUM_LIT> ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } else if ( RegResult ) { assert ( EltsPerReg == <NUM_LIT> && <STR_LIT> ) ; bool UseHigh = false ; CCValAssign :: LocInfo Info ; for ( auto & It : PendingMembers ) { Info = UseHigh ? CCValAssign :: AExtUpper : CCValAssign :: ZExt ; State . addLoc ( CCValAssign :: getReg ( It . getValNo ( ) , <STR_LIT> , RegResult , <STR_LIT> , Info ) ) ; UseHigh = ! UseHigh ; if ( ! UseHigh ) ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } if ( ! LocVT . isScalableVector ( ) ) { for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; } const Align StackAlign = State . getMachineFunction ( ) . getDataLayout ( ) . getStackAlignment ( ) ; const Align MemAlign = ArgFlags .


<s> void EmitCallAsanReport ( unsigned AccessSize , bool IsWrite , MCContext & Ctx , MCStreamer & Out , const RegisterContext & RegCtx ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; if ( RegCtx . AddressReg ( <STR_LIT> ) != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . AddressReg ( <STR_LIT> ) ) ) ; } MCSymbol * FnSym = Ctx . getOrCreateSymbol ( llvm :: Twine ( <STR_LIT> ) + ( IsWrite ? <STR_LIT> : <STR_LIT> ) + llvm :: Twine


<s> if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return <NUM_LIT> ; list = SH_ATTRIBUTES ( t ) ; while ( list


<s> machine_mode mode = ( regno1 <= R30_REGNUM ) ? DImode : DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode ,


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass (


<s> const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv )


base == const0_rtx && aarch64_sve_index_immediate_p ( step ) ) return step ;


<s> if ( getStubFactory ( ) == NULL ) return false ; getStubFactory ( ) -> addPrototype ( new


<s> if ( ! OPTION_SET_P ( flag_web ) ) flag_web = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_unroll_loops ||

flag_peel_loops || optimize >= <NUM_LIT> ;


<s> assert ( ImmMO . getImm ( ) >= <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegMO , Fixups , STI ) << <NUM_LIT> ) ; Bits |= ( unsigned ) ImmMO . getImm ( ) & <NUM_LIT> ; return Bits


<s> if ( Ptr . getOpcode ( ) == <STR_LIT> ) { PtrOffsetC = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } GlobalAddressSDNode * PtrN = cast < GlobalAddressSDNode > ( Ptr . getNode ( ) ) ; SDValue TPtr = DAG . getTargetGlobalAddress ( PtrN -> getGlobal ( ) , DL , VT , <NUM_LIT> , <NUM_LIT> ) ; PtrOffsetC += PtrN -> getOffset ( ) ; assert ( PtrN -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Ld = LowerPtrAuthGlobalAddressViaGOT ( Wrapper , ( <STR_LIT> ) KeyC , HasAddrDiversity , PtrN , DAG ) ) return Ld ; if ( HasAddrDiversity ) { SDValue BlendIntID = DAG . getTargetConstant ( <STR_LIT> , DL , VT ) ; AddrDiscriminator = DAG . getNode ( <STR_LIT> , DL , VT , BlendIntID , AddrDiscriminator , Discriminator ) ; DiscriminatorC = <NUM_LIT> ; } SDValue PtrOffset = DAG . getTargetConstant ( PtrOffsetC , DL , <STR_LIT> ) ; SDValue Key = DAG . getTargetConstant ( KeyC , DL , <STR_LIT> ) ; Discriminator = DAG . getTargetConstant ( DiscriminatorC , DL , VT ) ; SDValue X16Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , SDValue ( ) ) ; SDValue X17Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , X16Copy . getValue ( <NUM_LIT> ) ) ; SDNode * MOV = DAG . getMachineNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { TPtr , PtrOffset , Key , AddrDiscriminator

, Discriminator , X17Copy . getValue ( <NUM_LIT> ) } ) ;


<s> bool isVecListTwoDHWordIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT>

&& VectorList . LaneIndex <= <NUM_LIT> ;


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> isThreadLocal ( ) ? MMIMachO . getThreadLocalGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; SmallString < <NUM_LIT>


<s> return <ISA_LIT>Lowering -> SelectForceXFormMode ( N , Disp ,


<s> if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( GA -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( <NUM_LIT> ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> static bool or1k_function_value_regno_p ( const unsigned int regno


) return CSR_<ISA_LIT>_AAVPCS_SaveList ;


<s> break ; default : gcc_unreachable ( ) ; } break ; case ARG_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = <NUM_LIT> - crtl -> args . pretend_args_size ; break ; case STACK_POINTER_REGNUM : offset = ( current_frame_info . total_size + <NUM_LIT> - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset


<s> MCTargetStreamer & TS = * getTargetStreamer ( ) ; <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ; ATS . reset ( ) ; MappingSymbolCounter = <NUM_LIT>


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) )


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl


<s> void PadShortFunc :: addPadding ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator & MBBI , unsigned int NOOPsToAdd ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; while ( NOOPsToAdd -- > <NUM_LIT> ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * MBB , MBBI , DL , TII -> get