<s> getLexer ( ) . Lex ( ) ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) Error ( ExtLoc , <STR_LIT> + Name ) ; for ( const auto & Extension : Extensions ) { if ( Extension . Kind != FeatureKind ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; if ( ( getAvailableFeatures ( ) & Extension .

ArchCheck ) != Extension . ArchCheck ) {


<s> unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE41CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> isSLM ( ) ) if ( const auto * Entry = CostTableLookup ( SLMCostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTbl , ISD , MTy ) ) return LT . first * ( ExtraCost + Entry -> Cost ) ; if ( ST -> hasSSE41 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE41CostTbl , ISD , MTy ) ) return LT . first


<s> HOST_WIDE_INT val0 = <NUM_LIT> , val1 = <NUM_LIT> ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ; val0 = INTVAL ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg0 = XEXP ( a , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ; val1 = INTVAL ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg1 = XEXP ( b , <NUM_LIT> ) ; if ( ! const_ok_for_op ( val0 , PLUS ) || ! const_ok_for_op ( val1 , PLUS ) ) return <NUM_LIT> ; if ( arm_eliminable_register ( reg0 ) ) return <NUM_LIT> ; val_diff = val1 - val0


, ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO . getReg (


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return false ; const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; if ( ! Section ) { getStreamer ( ) . initSections ( false , getSTI ( ) ) ; Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT>


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcSubIdx = MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; DstSubIdx = MI . getOperand ( <NUM_LIT> ) . getSubReg


<s> if ( d -> perm [ <NUM_LIT> ] == high ) ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * <NUM_LIT> ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * <NUM_LIT> + <NUM_LIT> ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4HFmode : gen = gen_aarch64_zip2v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip2v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi


<s> if ( SkipDelaySlotFiller ) return false ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock


<s> static TargetLoweringObjectFile * createTLOF ( TargetMachine & TM ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin (

) ) return new <ISA_LIT>MachOTargetObjectFile ( ) ;


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , <STR_LIT> Flags ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal (


<s> else gcc_unreachable ( ) ; } else if ( REG_P ( dest ) && REGNO ( dest ) == MD_REG_FIRST ) { low_dest = mips_subword ( dest , false ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( dest , mips_subword ( src , true ) , low_dest ) ) ; else emit_insn ( gen_mthisi_di ( dest , mips_subword ( src , true ) , low_dest ) ) ; } else if ( REG_P ( src ) && REGNO ( src ) == MD_REG_FIRST ) { mips_emit_move ( mips_subword ( dest , false ) , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( mips_subword ( dest , true ) , src ) ) ; else emit_insn ( gen_mfhisi_di ( mips_subword ( dest , true ) , src ) ) ; } else { low_dest = mips_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; } else { mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; } } rtx_insn * insn = ( rtx_insn * ) insn_ ; struct mips_address_info addr = { } ; if ( insn ) { rtx_insn * next = next_nonnote_nondebug_insn_bb ( insn ) ; if ( next ) { rtx set = single_set ( next ) ; if ( set && SET_SRC ( set ) == dest ) { if ( MEM_P ( src ) ) { rtx tmp = XEXP ( src


<s> void <ISA_LIT>InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo


<s> assert ( VT != <STR_LIT> && <STR_LIT> ) ; if ( HasSSE2 && VT == <STR_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( Size == <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } } else if ( NumRegs == <NUM_LIT> ) { if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } } return false


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue (


<s> static DecodeStatus DecodeThumbCmpBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( Val << <NUM_LIT> ) ) ; return MCDisassembler :: Success


<s> break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_SaveList ; return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return


<s> SDValue <ISA_LIT>TargetLowering :: getReturnAddressFrameIndex ( SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> )


<s> if ( NumOperands != <NUM_LIT> || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) llvm_unreachable ( <STR_LIT> ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , isFP ) , <NUM_LIT> ) ; return getInstructionMapping ( DefaultMappingID , <NUM_LIT> ,


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBaseNum ( )


<s> rtx_insn * insn ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn )


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( ) { AlignmentIsInBytes = false ; Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective =


<s> emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } else emit_move_insn ( dst , copy_rtx ( tmp ) ) ; } else if ( ! TARGET_64BIT && smode == DImode ) { if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , src , <NUM_LIT> ) , tmp ) ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , src , <NUM_LIT> ) , tmp ) ) ) ; } else { rtx vcopy = gen_reg_rtx ( V2DImode ) ; emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode ,


<s> EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , <STR_LIT> | Flags ) ; return DAG . getNode ( <STR_LIT> , DL , Ty


<s> } if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ; int PSHUFHWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFHWMask , DAG ) ) ) ; } if ( Scale > <NUM_LIT> && EltBits == <NUM_LIT> && Subtarget -> hasSSSE3 ( ) ) { assert ( NumElements == <NUM_LIT> && <STR_LIT> ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) PSHUFBMask [ i ] = DAG . getConstant ( ( i % Scale == <NUM_LIT> ) ? i / Scale : <NUM_LIT> , <STR_LIT> ) ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ; } do { MVT InputVT = <STR_LIT> ( <STR_LIT> ( EltBits ) , NumElements ) ; SDValue Ext = AnyExt ? DAG . getUNDEF ( InputVT ) : getZeroVector ( InputVT , Subtarget , DAG , DL ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV , Ext ) ; Scale /= <NUM_LIT> ; EltBits *= <NUM_LIT> ; NumElements /= <NUM_LIT> ; } while ( Scale > <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> ,


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM

-> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) {


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return true


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectVSplatUimmInvPow2 ( SDValue N , SDValue & Imm ) const { APInt ImmValue ; EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { int32_t Log2 = ( ~ ImmValue ) . exactLogBase2 ( ) ; if ( Log2 != - <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( Log2 , EltTy ) ; return true ; } } return false


<s> __arm_vldrbq_s8 ( int8_t const * __base ) { return __builtin_mve_vldrbq_sv16qi ( ( __builtin_neon_qi *


<s> assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) { if ( CanUseBFC ) { AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; } } else


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg (


<s> AU . addRequired < AAResultsWrapperPass


<s> bool MadeChange = false ; MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT>


<s> unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UserMBB ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end


<s> InsertPts . insert ( InsertionPoints :: value_type ( NewPt , IPI -> second ) ) ; IPI = InsertPts . find ( OldInstr ) ; InsertPts . erase (


<s> DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts


<s> SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG .

getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( ! Scale ) return <NUM_LIT> ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , VTs , Ops , array_lengthof ( Ops ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT>


<s> return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT>


<s> void addInstruction ( MachineInstr * I ) { Instrs . push_back ( I


<s> } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( BaseReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( IndexReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } Scale = ( unsigned ) ScaleVal


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) { Inst . setOpcode ( <STR_LIT> ) ; } else { if ( ! isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode


<s> const SDValue Dividend = Op -> getOperand ( <NUM_LIT> ) ; const SDValue Divisor = Op -> getOperand ( <NUM_LIT> ) ; SDValue Div = DAG . getNode ( DivOpcode , dl , VT , Dividend , Divisor ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , VT , Div , Divisor ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , dl , VT , Dividend , Mul ) ; SDValue Values [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , Values ) ; } RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) , Subtarget ) ; SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; Type * RetTy = StructType :: get ( Ty , Ty ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , InChain ) ; TargetLowering :: CallLoweringInfo CLI


<s> if ( rest == NULL ) return - <NUM_LIT> ; char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest +


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ; return


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst , Expr


<s> if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ,


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { Expr -> print ( OS , MAI ) ; OS << getVariantKindName ( getKind


<s> PM . add ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine (


<s> else return true ; if ( Parser . getLexer ( ) . peekTokens ( Tokens ) != Tokens . size ( ) ) return true ; if ( Tokens [ Tokens . size ( ) - <NUM_LIT> ] . isNot ( AsmToken :: At ) || Tokens [ Tokens . size ( ) - <NUM_LIT> ] . isNot ( AsmToken :: Identifier ) || Tokens [ Tokens . size ( ) - <NUM_LIT> ] . getIdentifier ( ) != <STR_LIT> ) return true ; if ( Tok . is ( AsmToken :: String ) ) { StringRef SymName ; if ( Parser . parseIdentifier ( SymName ) ) return true ; Res = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( SymName ) , Ctx ) ; } else { if ( Parser . parsePrimaryExpr ( Res , EndLoc , nullptr ) ) return true ; } Parser . Lex ( ) ; Parser . Lex ( ) ; } if ( parseToken ( AsmToken :: LParen , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef KeyStr = Parser . getTok ( ) . getIdentifier ( ) ; auto KeyIDOrNone = <ISA_LIT>StringToPACKeyID ( KeyStr ) ; if ( ! KeyIDOrNone ) return TokError ( <STR_LIT> + KeyStr + <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Discriminator = Parser . getTok ( ) . getIntVal ( ) ; if ( ! isUInt < <NUM_LIT> > ( Discriminator ) ) return TokError ( <STR_LIT> + itostr ( Discriminator ) + <STR_LIT> ) ; Parser . Lex ( ) ; bool UseAddressDiversity = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex


<s> SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , A1 , b . OR ( b . AND ( A1 , b . NOT ( A2 ) ) , b . AND ( A2 , b . SRL < <NUM_LIT> > ( A1 ) ) ) ) ; } llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> return ( __m128d ) __builtin_ia32_scalefpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , (

__v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return ( int32x2_t ) __builtin_neon_vld1_dupv2si ( (


<s> if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; } return true


<s> bool mips_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true


<s> if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; FastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; FastEmitBranch ( Target ,


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer )


<s> return ( __m64 ) __builtin_ia32_psrlq ( ( long long )


<s> fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ebx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ecx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( edx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( esi ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( edi ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ebp ) - new_cfa ; fs -> regs . reg [


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> label_name = ( * targetm . strip_name_encoding ) ( ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , <NUM_LIT> , VOIDmode , <NUM_LIT> , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LINK_REGISTER_REGNUM ; current_function_uses_pic_offset_table = <NUM_LIT> ; if ( MACHOPIC_INDIRECT && current_function_uses_pic_offset_table ) caller_addr_regno


<s> IPI != EndIPI ; ++ IPI ) { BasicBlock * CurBB = IPI -> first -> getParent ( ) ; if ( NewBB == CurBB ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , Use , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB , CurBB ) ; if ( ! CommonDominator ) continue ; if ( CommonDominator != NewBB ) { assert ( CommonDominator != CurBB && <STR_LIT> ) ; NewPt = CommonDominator -> getTerminator ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print


<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT> , false , SDLoc ( Op


<s> int Id = ( int ) MI -> getOperand ( OpNum


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ; return false


<s> const MCOperand & Op = MI . getOperand ( i ) ; if ( & Op == & MO ) return i ; } llvm_unreachable ( <STR_LIT> ) ; return ~ <NUM_LIT>


<s> bool <STR_LIT> ( SDNode * N ) { return isVEXTRACTIndex ( N


<s> O << '#' ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; else if ( TF == <STR_LIT> ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( TF & <STR_LIT> ) O << <STR_LIT> ; else if ( TF & <STR_LIT> ) O << <STR_LIT> ; Get<ISA_LIT>GVSymbol ( GV , TF ) -> print ( O , MAI ) ; printOffset ( MO . getOffset ( ) ,


<s> if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - <NUM_LIT> ) / UNITS_PER_FP_WORD ; if ( TARGET_E500_DOUBLE && mode == DFmode ) return <NUM_LIT> ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_SPE_WORD - <NUM_LIT> ) / UNITS_PER_SPE_WORD ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_ALTIVEC_WORD - <NUM_LIT> )


<s> __ev64_opaque__ v ; uint16_t i [ <NUM_LIT> ] ; } u ; u . v =


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) .


<s> unsigned <ISA_LIT>TTI :: getMaximumUnrollFactor ( ) const { if ( ST -> isAtom ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( )


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MVT NVT = <STR_LIT> ( <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NVT , N0


<s> return ( __m128i ) __builtin_ia32_prolvq128_mask ( ( __v2di ) __A , ( __v2di ) __B , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 )


<s> if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 == <NUM_LIT> && NumBits2 ==


<s> FunctionPass * llvm :: create<ISA_LIT>AtomicExpandPass ( const <ISA_LIT>TargetMachine


<s> if ( ! IO -> isReg ( ) || ! IO -> isDef ( ) ) continue ; unsigned CurReg = IO -> getReg ( ) ; for ( MCRegAliasIterator AI ( CurReg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegToId . find ( * AI ) == RegToId . end ( ) ) { DEBUG ( IdToReg . push_back ( * AI ) ; assert ( IdToReg [ CurRegId ] == * AI && <STR_LIT> ) ) ; RegToId [ * AI ] = CurRegId ++ ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg (


<s> bool isSystemCPSRField ( ) const { if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister ; <STR_LIT> ( ) . fromString ( getSysReg ( ) , IsKnownRegister


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( const auto * Entry = CostTableLookup ( CostTbl , ISDOpcode , LT . second ) ) return LT . first * Entry -> Cost ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( LT . second == <STR_LIT> && Op2Info == TargetTransformInfo :: OK_UniformConstantValue ) Cost += <NUM_LIT> ; return


<s> O << <STR_LIT> << MI -> getOperand ( OpNum


<s> if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC ,


<s> const unsigned Reg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Offset ) . addReg ( Reg ) ; return


<s> SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getStore ( firstStore , dl , ArgFPR , nextPtr , SV , nextOffset ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr


<s> const MCExpr * SubExpr2 = MCBinaryExpr :: createSub ( CurrentLocationExpr , SubExpr , getContext ( ) ) ; MCDataFragment * DF = static_cast < MCDataFragment * > ( LabelSym -> getFragment ( ) ) ; assert ( DF && <STR_LIT> ) ; MCFixupKind FixupKind = static_cast < MCFixupKind > ( FirstLiteralRelocationKind + ELF :: R_<ISA_LIT>64_PCREL_OPT ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( LabelSym -> getOffset (

) - <NUM_LIT> , SubExpr2 , FixupKind , Inst . getLoc ( ) ) ) ;


<s> getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo >


<s> return Value == <NUM_LIT> || isNEONBytesplat ( Value , <NUM_LIT>


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] .


<s> const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return


<s> return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstStore ( Opc , SrcReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; unsigned Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addFrameIndex ( FI ) . addImm ( Offset ) .


<s> void <ISA_LIT>FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) .

hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ;


<s> if ( const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , SDLoc ( N ) , <STR_LIT> ) ; return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return false ; Imm = N ; if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N )

-> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ;


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned MemOpc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI -> getOperand


<s> return ( poly16x4_t ) __builtin_shuffle ( __a , ( uint16x4_t ) {


<s> return DAG . getRegister ( FI -> getGlobalBaseReg ( )


<s> if ( ! isRegInClass ( MO , QPRs ) && AllowScalars ) continue ; if ( auto * OpDef = RDA . getMIOperand ( & MI , MO ) ) if ( FalseLanesZero . count ( OpDef ) ) continue ; return


<s> static bool arm_must_pass_in_stack ( const function_arg_info & arg ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( arg ) ; else return must_pass_in_stack_var_size_or_pad ( arg )


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; assert ( Infos [ Kind - FirstTargetFixupKind ] . Name && <STR_LIT> ) ; return Infos [ Kind


<s> static char prid_str [ <NUM_LIT> ] ; sprintf ( prid_str , <STR_LIT> , cpucfg_cache [


<s> MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel ( JTI ) ; OutStreamer -> EmitLabel ( JTISymbol ) ; OutStreamer -> EmitDataRegion ( MCDR_DataRegionJT32 ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( Expr


<s> bool enableClusterStores ( ) const override { return true


<s> const char * rs6000_indirect_call_template ( rtx * operands , unsigned int funop ) { return rs6000_indirect_call_template_1 ( operands , funop ,


<s> tree s = build_string ( strlen ( reg_names [ CA_REGNO ] ) , reg_names [ CA_REGNO ] ) ; return tree_cons ( NULL_TREE , s , clobbers


<s> nextMBB -> splice ( nextMBB -> begin ( ) , thisMBB , llvm :: next ( MachineBasicBlock :: iterator ( bInstr ) ) , thisMBB -> end ( ) ) ; nextMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; assert ( bInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; MachineOperand & destOper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; int numArgs = bInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; int valArgIndx = lastAddrIndx + <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned tt = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( invSrc


<s> } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , N , <STR_LIT> ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , ConstLo ) ; if (


<s> return <STR_LIT> ; } if ( Subtarget . hasAltivec ( ) && Size >= <NUM_LIT> && ( ( ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT>


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym ->


<s> return _mm512_insertf64x4 ( _mm512_setzero_pd ( ) ,


<s> MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * RegSeq , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * TBL2 , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true


<s> static tree pru_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { switch ( code ) { case PRU_BUILTIN_DELAY_CYCLES


<s> emitRX ( Opcode , DstReg , MCOperand :: createImm


<s> return ( uint64x1_t ) ( __a == __AARCH64_INT64_C ( <NUM_LIT> )


<s> if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= countTrailingZeros ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , DL , <STR_LIT> ) , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( ) ; } } else if ( N1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * N11C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! N11C ) return SDValue ( ) ; unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && ( Mask == ~ Mask2 ) ) { if ( Subtarget -> hasDSP ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned amt = countTrailingZeros ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( amt , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , Res , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( ) ; } else if ( <STR_LIT> ( ~ Mask ) && ( ~ Mask == Mask2 ) ) { if ( Subtarget -> hasDSP ( ) && ( Mask2 == <NUM_LIT> || Mask2 == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = countTrailingZeros ( Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( lsb , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask2 , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( ) ; } } if ( DAG . MaskedValueIsZero ( N1 , MaskC -> getAPIntValue ( ) ) && N00 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode

> ( N00 . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( ~ Mask ) ) {


<s> if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM , false ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( <ISA_LIT>FastEmitLoad ( VT , AM , ResultReg )


<s> if ( PreOp ) return LPAC :: makePreOp ( AluCode ) ; if ( PostOp ) return LPAC :: makePostOp ( AluCode ) ; return AluCode


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> assert ( ByteVecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( EltVT != <STR_LIT> && <STR_LIT> ) ; unsigned VecSize = VT . getSizeInBits ( ) ; assert ( ByteVecVT . getSizeInBits ( ) == VecSize && <STR_LIT> ) ; if ( EltVT == <STR_LIT> ) { SDValue Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , SadVecVT , V , Zeros ) ; return DAG . getBitcast ( VT , V ) ; } if ( EltVT == <STR_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize


<s> MIB . addReg ( AddrIn ) . addImm ( StSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) ) ; } else { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg (

Data ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( StSize ) ) ;


<s> static bool isT1i32Store ( unsigned Opc ) { return Opc == <STR_LIT> || Opc ==


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst *


<s> if ( ! AtStart ) -- BeforeI ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( *


<s> Value * <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , <NUM_LIT> ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB


<s> unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned NumRegs = LastReg - FirstReg ; unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> (


<s> return ( __mmask8 ) __builtin_ia32_pcmpeqw128_mask ( ( __v8hi ) __A ,


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return


<s> ReplaceNode ( N , createDRegPairNode ( VT , N -> getOperand ( <NUM_LIT> ) , N ->


<s> nds32_split_shiftrtdi3 ( dst , src , shiftamount ,


<s> static DecodeStatus DecodeStoreFP ( MCInst & Inst , unsigned insn

, uint64_t Address , const void * Decoder ) {


<s> if ( DstTy . isVector ( ) ) return false ; bool Is64Bit = DstTy . getSizeInBits ( ) == <NUM_LIT> ; auto Imm1Fn = Is64Bit ? selectShiftA_64 ( MO ) : selectShiftA_32 ( MO ) ; auto Imm2Fn = Is64Bit ? selectShiftB_64 ( MO ) : selectShiftB_32 ( MO ) ; MachineIRBuilder MIB ( I ) ; if ( ! Imm1Fn || ! Imm2Fn ) return false ; auto NewI = MIB . buildInstr ( Is64Bit ? <STR_LIT> : <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; for ( auto & RenderFn : * Imm1Fn ) RenderFn ( NewI ) ; for ( auto & RenderFn : * Imm2Fn )


<s> assert ( ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; AsmParser . warnIfRegIndexIsAT ( RegNo , StartLoc ) ; Inst . addOperand ( MCOperand :: createReg ( RegIdx . RegInfo -> getRegClass ( AsmParser . getABI ( ) . AreGprs64bit ( ) ? <STR_LIT> : <STR_LIT>


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo (


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; const MCSymbolRefExpr * RefExp = nullptr ; const MCConstantExpr * ConstExp = nullptr ; if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Op . getExpr ( ) ) ) { RefExp = cast < MCSymbolRefExpr > ( BinExpr -> getLHS ( ) ) ; ConstExp = cast < MCConstantExpr > ( BinExpr -> getRHS ( ) ) ; } else RefExp = cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; O << RefExp -> getSymbol ( ) . getName ( ) ; O << '(' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; O << ')' ; if ( RefExp -> getKind ( ) != MCSymbolRefExpr :: VK_None ) O << '@' << MCSymbolRefExpr :: getVariantKindName ( RefExp -> getKind ( ) ) ; if ( ConstExp != nullptr ) O << '+' << ConstExp -> getValue


<s> int regs = <NUM_LIT> - * cum ; * pretend_size = regs < <NUM_LIT> ? <NUM_LIT> : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < <NUM_LIT> ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( <NUM_LIT> + ( regno - <NUM_LIT> ) ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) ,


<s> bool hasVAES ( ) const { return HasVAES


<s> return I -> getOpcode ( ) == Instruction :: Or && haveNoCommonBitsSet ( I -> getOperand ( <NUM_LIT> ) , I ->


<s> REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = CONST_DOUBLE_FROM_REAL_VALUE ( r_pow , DFmode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt ,


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { const uint16_t t = <NUM_LIT>


<s> Parser . Lex ( ) ; StringRef Arch ; if ( Parser . parseIdentifier ( Arch ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case (

<STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> if ( name [ len - <NUM_LIT> ] == ']' ) return ggc_alloc_string ( name , len - <NUM_LIT> ) ; else return


<s> if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load ) { if ( const auto * Entry = CostTableLookup ( AVX2InterleavedLoadTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } else { assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; if ( const auto * Entry = CostTableLookup ( AVX2InterleavedStoreTbl , Factor , ETy


<s> if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) || isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ) return SDValue ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT ==


<s> else if ( Opc == <STR_LIT> ) CC = static_cast < <STR_LIT> > ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; else if ( Opc == <STR_LIT> ) CC = static_cast < <STR_LIT> > ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) CC = static_cast < <STR_LIT> > ( N ->


<s> if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (


<s> bool aarch64_const_vec_all_same_in_range_p ( rtx x , HOST_WIDE_INT minval , HOST_WIDE_INT maxval ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && IN_RANGE ( INTVAL ( elt ) , minval ,


<s> MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackPtr ) . addReg ( physSPReg ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB ) ; BuildMI ( tailMBB , DL , TII -> get ( TargetOpcode :: COPY ) , MI

. getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FinalStackPtr ) ;


<s> RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAdjustCodeGenOptsFn Y ( * T , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T ,


<s> unsigned Size = TRI -> getSpillSize ( RC ) ; Align Alignment = TRI -> getSpillAlign ( RC ) ; int FrameIdx = MFI -> CreateSpillStackObject


<s> unsigned <ISA_LIT>FastISel :: emitIntExt ( MVT SrcVT , unsigned SrcReg , MVT DestVT , bool isZExt ) { unsigned DestReg = createResultReg ( & <STR_LIT> ) ; return emitIntExt ( SrcVT , SrcReg , DestVT , DestReg


<s> rtx div , mod ; rtx_insn * insn ; rtx scratch , tmp0 , tmp1 , tmp2 ; rtx ( * gen_divmod4_1 ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode ) { if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode ) gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_1 : gen_divmodsi4_1 ; else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_2 : gen_divmodsi4_zext_2 ; } else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_1 : gen_divmodsi4_zext_1 ; break ; case E_DImode : gen_divmod4_1 = unsigned_p ? gen_udivmoddi4_1 : gen_divmoddi4_1 ; break ; default : gcc_unreachable ( ) ; } end_label = gen_label_rtx ( ) ; qimode_label = gen_label_rtx ( ) ; scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; scratch = expand_simple_binop ( mode , IOR , scratch , operands [ <NUM_LIT> ] , scratch , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_test_ccno_1 ( mode , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp0 = gen_rtx_EQ ( VOIDmode , tmp0 , const0_rtx ) ; tmp0 = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp0 , gen_rtx_LABEL_REF ( VOIDmode , qimode_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp0 ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = qimode_label ; emit_insn ( gen_divmod4_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_jump_insn ( gen_jump ( end_label ) ) ; emit_barrier ( ) ; emit_label ( qimode_label ) ; tmp0 = lowpart_subreg ( HImode , scratch , mode ) ; tmp1 = lowpart_subreg ( HImode , operands [ <NUM_LIT> ] , mode ) ; tmp2 = lowpart_subreg ( QImode , operands [ <NUM_LIT> ] , mode


<s> SmallVector < int , <NUM_LIT> > CommutedMask ( Mask . begin ( ) , Mask . end ( ) ) ; ShuffleVectorSDNode :: commuteMask ( CommutedMask ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SmallVector < int , <NUM_LIT> > UnpackMask ; createUnpackShuffleMask ( VT , UnpackMask , ( i >> <NUM_LIT> ) % <NUM_LIT> , i % <NUM_LIT> ) ; if ( isTargetShuffleEquivalent ( VT , Mask , UnpackMask ) || isTargetShuffleEquivalent ( VT , CommutedMask , UnpackMask ) )


<s> Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { End , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Glue } ; VTs = DAG . getVTList (


<s> const unsigned ScratchReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addDef ( ResultReg1 ) . addDef ( ScratchReg ) . addUse ( AddrReg ) . addUse ( DesiredReg ) . addUse ( NewReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addDef ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addUse ( ResultReg1 ) . addUse ( DesiredReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResultReg2 ) .

addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ;


<s> auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds .


<s> if ( ! ST -> vectorsUseTwoUnits ( ) || ! Ty1 -> isVectorTy ( ) ) return InstructionCost ( <NUM_LIT> ) ; std :: pair < InstructionCost , MVT > LT1 = TLI -> getTypeLegalizationCost ( DL , Ty1 ) ; if ( LT1 . first != <NUM_LIT> || ! LT1 . second . isVector ( ) ) return InstructionCost ( <NUM_LIT> ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( TLI -> isOperationExpand ( ISD , LT1 . second ) ) return InstructionCost ( <NUM_LIT> ) ; if ( Ty2 ) { std :: pair < InstructionCost , MVT > LT2 = TLI -> getTypeLegalizationCost ( DL , Ty2 ) ; if ( LT2 . first != <NUM_LIT> || ! LT2 . second


<s> return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64


<s> CommentStream = & cs ; uint8_t bytes [ <NUM_LIT> ] ; Size = <NUM_LIT> ; if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes ) == - <NUM_LIT> ) return Fail ; Size = <NUM_LIT> ; uint32_t insn = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address ,


<s> return ( uint16x8_t ) __builtin_neon_vceqv8hi ( ( int16x8_t ) __a , (


<s> if ( VT == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( Opcode , DL , { LoadVT , <STR_LIT> } , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( VT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load , LoadChain } , DL


<s> const TargetInstrInfo * TII ; const <ISA_LIT>Subtarget * STI ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; int returnEmitted = <NUM_LIT> ; MachineFunction :: iterator noSuccessorBlock ; int noSuccessorFound = <NUM_LIT> ; for ( MachineFunction :: iterator BBi = MF . begin ( ) ; BBi != MF . end ( ) ; BBi ++ ) { if ( BBi -> succ_empty ( ) ) { noSuccessorBlock = BBi ; noSuccessorFound = <NUM_LIT> ; } for ( MachineBasicBlock :: iterator MCi = BBi -> begin ( ) ; MCi != BBi -> end ( ) ; MCi ++ ) { if ( MCi -> isReturn ( ) ) { returnEmitted = <NUM_LIT> ; break ; } } } if ( ! returnEmitted ) { errs ( ) << <STR_LIT> << MF . getName ( ) . str ( ) << <STR_LIT> ; if ( noSuccessorFound ) { MachineBasicBlock :: iterator lastMI = noSuccessorBlock -> begin ( ) ; BuildMI ( * noSuccessorBlock , noSuccessorBlock -> end ( ) , ( * lastMI ) . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } else


<s> Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } SDValue Res , Chain ; unsigned Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; if ( IsStrict ) { Res = DAG . getNode ( Opc , dl , { ResVT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( Opc , dl , { ResVT , <STR_LIT> } , { DAG . getEntryNode ( ) , Src } ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && SrcVT == <STR_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ; unsigned Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( Opc , dl , { VT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , Tmp } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; return DAG . getMergeValues ( { Res , Chain } , dl ) ; } return DAG . getNode ( Opc , dl , { VT , <STR_LIT> } , { DAG . getEntryNode ( ) , Tmp } ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && UseSSEReg ) { if ( Subtarget . hasAVX512 ( ) ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Res , Chain ; if ( IsStrict )


<s> static void extractParts ( Register Reg , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder ,

LLT Ty , int NumParts , SmallVectorImpl < Register > & VRegs ) {


<s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { assert ( MBB . getParent ( ) && <STR_LIT> ) ; if ( STI . isTargetWin64 ( ) && ! MBB . succ_empty ( ) && ! MBB . isReturnBlock ( ) ) return false ; if ( canUseLEAForSPInEpilogue ( * MBB . getParent ( ) ) )


<s> InConstantPool = false ; OutStreamer -> emitDataRegion (


<s> EVT VecVT = <STR_LIT> ; EVT CmpVT = PreferKOT ? <STR_LIT> : VecVT ; if ( OpSize == <NUM_LIT> ) { VecVT = <STR_LIT> ; CmpVT = PreferKOT ? <STR_LIT> : VecVT ; } EVT CastVT = VecVT ; bool NeedsAVX512FCast = false ; if ( OpSize == <NUM_LIT> || NeedZExt ) { if ( Subtarget . hasBWI ( ) ) { VecVT = <STR_LIT> ; CmpVT = <STR_LIT> ; if ( OpSize == <NUM_LIT> ) CastVT = VecVT ; } else { VecVT = <STR_LIT> ; CmpVT = <STR_LIT> ; CastVT = OpSize == <NUM_LIT> ? VecVT : OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; NeedsAVX512FCast = true ; } } auto ScalarToVector = [ & ] ( SDValue X ) -> SDValue { bool TmpZext = false ; EVT TmpCastVT = CastVT ; if ( X . getOpcode ( ) == <STR_LIT> ) { SDValue OrigX = X . getOperand ( <NUM_LIT> ) ; unsigned OrigSize = OrigX . getScalarValueSizeInBits ( ) ; if ( OrigSize < OpSize ) { if ( OrigSize == <NUM_LIT> ) { TmpCastVT = NeedsAVX512FCast ? <STR_LIT> : <STR_LIT> ; X = OrigX ; TmpZext = true ; } else if ( OrigSize == <NUM_LIT> ) { TmpCastVT = NeedsAVX512FCast ? <STR_LIT> : <STR_LIT> ; X = OrigX ; TmpZext = true ; } } } X = DAG . getBitcast ( TmpCastVT , X ) ; if ( ! NeedZExt && ! TmpZext ) return X ; return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( <NUM_LIT> , DL , VecVT ) , X , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; } ; SDValue Cmp ; if ( IsOrXorXorTreeCCZero ) { Cmp = emitOrXorXorTree ( X , DL , DAG , VecVT , CmpVT , HasPT , ScalarToVector ) ; } else { SDValue VecX = ScalarToVector ( X ) ; SDValue VecY = ScalarToVector ( Y ) ; if ( VecVT != CmpVT ) { Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } else if ( HasPT ) { Cmp = DAG . getNode ( <STR_LIT> , DL , VecVT , VecX , VecY ) ; } else { Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY ,


<s> unsigned <ISA_LIT>BaseInstrInfo :: getOutputLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * DepMI ) const { unsigned Reg = DefMI -> getOperand ( DefIdx ) . getReg ( ) ; if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) ||

! isPredicated ( DepMI ) ) return <NUM_LIT> ;


<s> if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ?


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal


<s> Info . MI0 = & MI ; Info . MI1 = nullptr ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Info . Type = MCLOH_AdrpAdd ; Info . IsCandidate = true ; Info . MI0 = & MI ; } else if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( )

== <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) {


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . approx_modes ->

recip_sqrt & AARCH64_APPROX_MODE ( mode ) ) || flag_mrecip_low_precision_sqrt ) ) ;


<s> break ; case <STR_LIT> : SHLIntrinsicsID = <STR_LIT> ; SRAIntrinsicsID = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasAVX2 ( ) ) { int NumElems = VT . getVectorNumElements ( ) ; SDValue Idx0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Idx1 = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , Idx0 , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , Idx1 , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; int ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; ; } if ( VT == <STR_LIT> ) { SHLIntrinsicsID = <STR_LIT> ; SRAIntrinsicsID = <STR_LIT> ; } else { SHLIntrinsicsID =


<s> } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && ( matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) ) { AsmPieces . clear ( ) ; StringRef ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) { AsmPieces . clear ( ) ; StringRef ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { InlineAsm :: ConstraintInfoVector Constraints = IA -> ParseConstraints ( ) ; if ( Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } } break ; } return false


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address +=

I -> Size , ++ I ) I -> Address = Address ;


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCOPY_FD ( MachineInstr * MI , MachineBasicBlock * BB ) const { return BB


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T

, computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) {


<s> bool isTargetCygMing ( ) const { return ( TargetType == isMingw || TargetType == isCygwin


<s> MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext ( ) ; TargetSupported = ( ( Subtarget -> getRelocationModel ( ) == Reloc :: PIC_ ) && ( Subtarget -> has<ISA_LIT>32r2 ( ) && ( Subtarget -> isABI_O32


<s> else { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; const MCSymbolRefExpr * Dot = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; OutStreamer . EmitLabel ( DotSym ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addExpr ( Dot ) , STI ) ; return


<s> return Subtarget -> useSoftFloat ( )


<s> pa_asm_output_aligned_local ( FILE , NAME , SIZE , ALIGN ) { rtx addr = ADDR ; \ switch ( GET_CODE ( addr ) ) \ { \ case REG : \ fprintf ( FILE , <STR_LIT> , reg_names [ REGNO ( addr ) ] ) ; \ break ; \ case PLUS : \ gcc_assert ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) ; \ fprintf ( FILE , <STR_LIT> , ( int ) INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , \ reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; \ break ; \ case LO_SUM : \ if ( ! symbolic_operand ( XEXP ( addr , <NUM_LIT> ) , VOIDmode ) ) \ fputs ( <STR_LIT> , FILE ) ; \ else if ( flag_pic == <NUM_LIT> )

\ fputs ( <STR_LIT> , FILE ) ; \ else \ fputs ( <STR_LIT> , FILE ) ; \ pa_output_global_address ( FILE , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ output_operand ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ break ; \ case CONST_INT : \ fprintf ( FILE , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( addr ) ) ; \ break ; \ default : \ output_addr_const ( FILE , addr ) ; \ } }


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: mips || TT . getArch ( ) ==


<s> mips_multi_start ( ) ; switch ( mips_abi ) { case ABI_N32 : mips_multi_add_insn ( <STR_LIT> , target , <NUM_LIT> ) ; mips_multi_add_insn ( <STR_LIT> , target , <NUM_LIT> ) ; break ; case ABI_64 : mips_multi_add_insn ( <STR_LIT> , target , <NUM_LIT> ) ; mips_multi_add_insn ( <STR_LIT> , target , <NUM_LIT> ) ; break ; default : gp = pic_offset_table_rtx ; if ( mips_cfun_has_cprestore_slot_p ( ) ) { gp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; mips_get_cprestore_base_and_offset ( & base , & offset , true ) ; if ( ! SMALL_OPERAND ( offset ) ) { intop = GEN_INT ( CONST_HIGH_PART ( offset ) ) ; mips_multi_add_insn ( <STR_LIT> , gp , intop , <NUM_LIT> ) ; mips_multi_add_insn ( <STR_LIT> , gp , base , <NUM_LIT> ) ; base = gp


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs (


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( GV -> isWeakForLinker ( ) && GV -> isDeclaration ( ) && RelocM == Reloc :: Static ) { SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup =


<s> bool isREXExtendedReg ( const MCInst & MI , unsigned OpNum ) const { return ( get<ISA_LIT>RegEncoding ( MI , OpNum ) >> <NUM_LIT>


<s> if ( Subtarget -> getProcFamily ( ) == <ISA_LIT>Subtarget :: Falkor && I . getMetadata ( FALKOR_STRIDED_ACCESS_MD ) != nullptr ) return MOStridedAccess ; return MachineMemOperand


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant ,

const char * ExtraCode , raw_ostream & O ) {


<s> const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { unsigned ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg


<s> if ( Subtarget . isTargetWindowsMSVC ( ) && ! Subtarget . is64Bit ( ) && Arg . getSimpleValueType ( ) != <STR_LIT> ) Alignment = MaybeAlign ( <NUM_LIT> ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset )


<s> vec_double2 vd ; } out ; union { float f [ <NUM_LIT> ] ; vec_float4 vf ; } in ; in . vf = ( vec_float4


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case