<s> while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT> ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedStore ( Type


<s> return ( int32x4_t ) __builtin_neon_vmls_nv4si ( __a , __b , (


<s> if ( GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE ( SUBREG_REG ( op ) ) == DFmode ) return true ; if ( GET_CODE ( op ) == SUBREG && mode == DFmode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE

( SUBREG_REG ( op ) ) == DImode ) return true ;


<s> brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2BROperand ( Inst , brtarget , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred ,


<s> if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back


<s> DenseMap < unsigned , unsigned > :: const_iterator I = MLxEntryMap . find ( Opcode ) ; if ( I == MLxEntryMap . end ( ) ) return false ; const <ISA_LIT>_MLxEntry & Entry = <ISA_LIT>_MLxTable [ I


<s> return __builtin_loongson_pasubub ( s


<s> rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , const_double_from_real_value ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , <NUM_LIT> ) , XEXP ( test , <NUM_LIT> ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> )


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo


<s> default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( RM . hasValue ( ) ) return * RM ; if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) return


<s> t = __ev_mwhsmi ( a , b ) ; return __ev_addsmiaaw ( t )


<s> break ; } } } } if ( ! YmmOrZmmUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) processBasicBlock ( MBB ) ; if ( FnHasLiveInYmmOrZmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock * Succ : MBB . successors ( ) ) addDirtySuccessor ( * Succ ) ; } } BlockStates . clear ( ) ; return


<s> vmlsq_s32 ( int32x4_t a , int32x4_t b , int32x4_t c ) { int32x4_t result


<s> const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std ::


<s> if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> &&

RHSC < ( <NUM_LIT> << Log2_32 ( Size ) ) ) return false ;


<s> MSRReg = SysReg -> Writeable ? SysReg -> Encoding : - <NUM_LIT> ; } else MRSReg = MSRReg = <STR_LIT> ( Tok . getString ( ) ) ; auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateImm , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; for ( const auto & Info : CSI ) { if ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID :: ScalableVector ) continue ; assert ( ! Info . isSpilledToReg ( ) && <STR_LIT> ) ; unsigned DwarfReg = TRI . getDwarfRegNum ( Info . getReg ( ) , true ) ; int64_t Offset = MFI . getObjectOffset ( Info . getFrameIdx


<s> Opcode = <STR_LIT> ; break ; case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineSDNode * CmpSwap = DAG . getMachineNode ( Opcode , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; DAG . setNodeMemRefs ( CmpSwap , { MemOp } ) ; unsigned SubReg1 = <STR_LIT> , SubReg2 = <STR_LIT> ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( SubReg1 , SubReg2 ) ; SDValue Lo = DAG . getTargetExtractSubreg ( SubReg1 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( SubReg2 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Lo , Hi ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; return ; } auto Desired = splitInt128 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; auto New = splitInt128 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Desired . first , Desired . second , New . first , New . second , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ,


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF

. getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ;


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( MCInst & Inst , const MCSubtargetInfo &


<s> static DecodeStatus DecodeBranchTarget21 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _aor_i32 ( int * __A , int __B ) { __builtin_ia32_aor32 ( ( int * ) __A


<s> return ( uint8_t ) __builtin_neon_vget_laneuv16qi ( ( int8x16_t ) __a ,


<s> } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false


<s> __arm_vldrhq_z_s16 ( int16_t const *


<s> SDValue <ISA_LIT>CC ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>CC , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl ,


<s> return ; } int64_t Residue ; std :: unique_ptr < <ISA_LIT>Operand > NewOp = AddDisplacement ( Op , Displacement , Ctx , & Residue ) ; EmitLEA ( * NewOp , VT , Reg , Out ) ; while ( Residue != <NUM_LIT> ) { const MCConstantExpr * Disp = MCConstantExpr :: Create ( ApplyDisplacementBounds ( Residue ) , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > DispOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Reg , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ; EmitLEA ( * DispOp , VT , Reg


<s> for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const


<s> return { nullptr , <ISA_LIT>MCExpr ::


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint64_t > ( OS ,


<s> ud4 = c & <NUM_LIT> ; if ( ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ud2 == <NUM_LIT> && ( ud1 & <NUM_LIT> ) ) || ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ud2 == <NUM_LIT> && ! ( ud1 & <NUM_LIT> ) ) ) emit_move_insn ( dest , GEN_INT ( ( ud1 ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; else if ( ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ( ud2 & <NUM_LIT> ) ) || ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ! ( ud2 & <NUM_LIT> ) ) ) { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , GEN_INT ( ( ( ud2 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud1 ) ) ) ; } else if ( ud3 == <NUM_LIT> && ud4 == <NUM_LIT> ) { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; gcc_assert ( ud2 & <NUM_LIT> ) ; emit_move_insn ( copy_rtx ( temp ) , GEN_INT ( ( ( ud2 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( copy_rtx ( temp ) , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud1 ) ) ) ; emit_move_insn ( dest , gen_rtx_ZERO_EXTEND ( DImode , gen_lowpart ( SImode , copy_rtx ( temp ) ) ) ) ; } else if ( ( ud4 == <NUM_LIT> && ( ud3 & <NUM_LIT> ) ) || ( ud4 == <NUM_LIT> && ! ( ud3 & <NUM_LIT> ) ) ) { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx


<s> bool isPostIdxImm8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t > ::


<s> case V8SFmode : case V4DFmode : case V4DImode : if ( TARGET_AVX512VL ) return true ; break ; case V16HImode : if ( TARGET_AVX2 ) return true ; break ; case V32QImode : if ( TARGET_AVX2 ) return true ; break ; case V4SImode : case V4SFmode : case V8HImode : case V16QImode : if ( TARGET_XOP ) return true ; if ( TARGET_SSSE3 ) return true ; break ; case V2DImode : case V2DFmode : return true ; default : return false ; } memcpy ( d . perm , sel , nelt ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < <NUM_LIT> * nelt ) ; which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( which == <NUM_LIT> ) for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which !=


<s> return ( __mmask8 ) __builtin_ia32_cmpq128_mask ( ( __v2di ) __X , ( __v2di )


<s> static DecodeStatus decodePC24DBLBranchOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm


<s> if ( isMul ( MI ) ) { for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << * MI ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else if ( isMla ( MI ) ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AccumReg , TRI ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ActiveChains [ AccumReg ] -> add ( MI , Idx , getColor ( DestReg ) ) ; if ( DestReg != AccumReg ) { ActiveChains [ DestReg ] = ActiveChains [ AccumReg ] ; ActiveChains . erase (


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = <STR_LIT> ( MO1 . getImm ( ) ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) | ( ShiftVal == <NUM_LIT> ? <NUM_LIT> : ( <NUM_LIT> << ShiftVal ) ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) ShiftVal


<s> AFI . addLOHDirective ( MCLOH_AdrpAdd , { & MI , Info . MI0 } ) ; ++ NumADRSimpleCandidate ; break ; } case MCLOH_AdrpLdr : if ( supportLoadFromLiteral ( * Info . MI0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdr , { & MI , Info . MI0 } ) ; ++ NumADRPToLDR ; } break ; case MCLOH_AdrpAddLdr : { MachineInstr * AddMI = const_cast < MachineInstr * > ( Info . MI1 ) ; const MachineInstr * LdrMI = Info . MI0 ; auto AddIt = MachineBasicBlock :: iterator ( AddMI ) ; auto EndIt = AddMI -> getParent ( ) -> end ( ) ; if ( AddMI -> getIterator ( ) == EndIt || LdrMI != & * next_nodbg ( AddIt , EndIt ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; } case MCLOH_AdrpAddStr : if ( Info . MI1 != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 <<


<s> printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream &


<s> FunctionPass * llvm :: create<ISA_LIT>LowOverheadLoopsPass ( ) { return new <ISA_LIT>LowOverheadLoops (


<s> assert ( isToken ( ) && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok


<s> ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm )


<s> SMLoc getOffsetLoc ( ) const { return


<s> unsigned Latency = SchedModel . computeOperandLatency ( & DefMI , DefIdx , & UseMI , UseIdx ) ; if ( Latency <= <NUM_LIT> ) return false ; return DDomain == <STR_LIT> || DDomain == <STR_LIT> || UDomain ==


<s> } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) { if ( tryOptSelectConjunction ( I , * CondDef ) ) return true ; return false ; } <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } emitSelect ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> )


<s> unsigned getVariadicGPRSize ( ) const { return


<s> MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst )


<s> int last = <NUM_LIT> ; const int buf_size = <NUM_LIT> ; if ( feof ( f ) ) return std :: string ( ) ; do { size += buf_size ; buf = ( char * ) xrealloc ( buf , size ) ; gcc_assert ( buf ) ; if ( ! fgets ( buf + last , buf_size , f ) ) return std :: string ( ) ; last = strnlen ( buf , size


<s> -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI == MI ) return nullptr ; NewOpcode = VCMPOpcodeToVPT ( CmpMI -> getOpcode ( ) ) ; if ( NewOpcode == <NUM_LIT> )


<s> DiagnosticPredicate isSVEPattern ( ) const { if ( ! isImm ( ) ) return DiagnosticPredicateTy :: NoMatch ; auto * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return DiagnosticPredicateTy ::


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( const Type * Ty1 , const Type * Ty2 )


<s> SMLoc BracLoc = Tok . getLoc ( ) , End = Tok . getEndLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( BracLoc , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc StartInBrac = Tok . getLoc ( ) ; IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return <NUM_LIT> ; const MCExpr * Disp = <NUM_LIT> ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: Create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: CreateAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return <NUM_LIT> ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( Disp , Start , End , Size ) ; else return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End ,


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; SDValue MulOp = N -> getOperand ( <NUM_LIT> ) ; SDValue Phi = N -> getOperand ( <NUM_LIT> ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( MulOp , Phi ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( MulOp . getNode ( ) , DAG , Mode ) || Mode == MULU16 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasDQI ( ) ) { SDLoc dl ( N ) ; MVT IntScalar = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT IntVT = <STR_LIT> ( IntScalar , VT . getVectorNumElements ( ) ) ; SDValue Op0 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT>


<s> return shift_insns [ INTVAL ( count ) ] > <NUM_LIT>


<s> const char * name = i386_pe_strip_name_encoding ( str ) ; if ( * name == '@' ) name ++ ; p = strchr ( name


<s> x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( target , gen_vec_duplicate ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; rtx merge_mask = GEN_INT ( <NUM_LIT> << one_var ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; neon_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , one_var ) ) ; emit_insn ( gen_vec_set_internal ( mode , target , x , merge_mask , target


<s> for ( MCRegAliasIterator AI ( Reg , TM . getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; if ( RI -> needsStackRealignment ( MF ) && MFI . hasVarSizedObjects ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION


<s> void <ISA_LIT>AsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; getSymbol ( GV ) -> print (


<s> if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A ==


<s> return __builtin_aarch64_popcountv8qi (


<s> vmode = vmode_ ; chain_id = ++ max_id ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain_id ) ; bitmap_obstack_initialize ( NULL ) ; insns = BITMAP_ALLOC ( NULL ) ; defs = BITMAP_ALLOC ( NULL ) ; defs_conv = BITMAP_ALLOC ( NULL ) ; queue =


<s> rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return <NUM_LIT> ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return <NUM_LIT> ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode ,


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ; const MCExpr * Expr


<s> return ( __m128i ) __builtin_ia32_pcmpistrm128 ( ( __v16qi )


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK

== <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( <STR_LIT> ( V1 ) ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI )


<s> unsigned Opc = I . getOpcode ( ) ; assert ( ( Opc == TargetOpcode :: G_STORE || Opc == TargetOpcode :: G_LOAD ) && <STR_LIT> ) ; const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; assert ( I . hasOneMemOperand ( ) ) ; auto & MemOp = * * I . memoperands_begin ( ) ; if ( MemOp . isAtomic ( ) ) { if ( ! MemOp . isUnordered ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlignment ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else { I . RemoveOperand ( <NUM_LIT> ) ; I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) . addUse ( DefReg ) ; } return constrainSelectedInstRegOperands ( I , TII


<s> const MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( Kind


<s> MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand ::


<s> return __builtin_mve_sqshl_si ( value , shift


<s> TargetTransformInfo <ISA_LIT>BaseTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID )


<s> if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloatPass


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( )


<s> EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2 ) ImmOffset


<s> bool Code = false ; StringRef CodeID ; if ( getLexer ( ) . is ( AsmToken :: At ) ) { SMLoc startLoc = getLexer ( ) . getLoc ( ) ; getParser ( ) . Lex ( ) ; if ( ! getParser ( ) . parseIdentifier ( CodeID ) ) { if ( CodeID != <STR_LIT> ) return Error ( startLoc , <STR_LIT> ) ; Code = true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) .


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CC ) ; updateValueMap ( I , ResultReg


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_PLT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCHI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCLO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFHI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFLO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: Create (


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = loongarch_force_temporary ( temp , high ) ; if ( loongarch_symbol_extreme_p ( symbol_type ) && can_create_pseudo_p ( ) ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; temp1 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp1 , gen_rtx_LO_SUM ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) , addr ) ) ; emit_insn ( gen_lui_h_lo20 ( temp1 , temp1 , addr ) ) ; emit_insn ( gen_lui_h_hi12 ( temp1 , temp1 , addr )


<s> SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Zext ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , VT , Clz , DAG . getConstant ( Log2b , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scc ) ; } if ( C -> isAllOnesValue ( ) || C -> isNullValue ( ) ) return SDValue ( ) ; } EVT LHSVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( LHSVT . isInteger ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { EVT VT = Op . getValueType ( ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , LHSVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( dl , VT , Sub , DAG . getConstant ( <NUM_LIT> , LHSVT ) , CC ) ; } return SDValue


<s> unsigned <ISA_LIT>FastISel :: emitAdd_ri_ ( MVT VT , unsigned Op0 , int64_t Imm ) { unsigned ResultReg ; if ( Imm < <NUM_LIT> ) ResultReg = emitAddSub_ri ( false , VT , Op0 , - Imm ) ; else ResultReg = emitAddSub_ri ( true , VT , Op0 , Imm ) ; if ( ResultReg ) return ResultReg ; unsigned CReg = fastEmit_i ( VT , VT , <STR_LIT> , Imm ) ; if ( ! CReg ) return


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addPostIdxRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) return false ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ->


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; MadeChange = true ; } } return


<s> FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo ->


<s> assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return false ; if ( ! performCustomAdjustments ( MI , NewOpc , ST ) ) return false ; MI . setDesc ( TII -> get ( NewOpc


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V2 ) . addReg ( V0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg (


<s> return new <ISA_LIT>SpeculationHardening (


<s> for ( auto & MI : MBB ) FnSize += TII . getInstSizeInBytes ( MI ) ; } return


<s> MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; if ( ! LoopCount ) return <NUM_LIT> ; if ( LoopCount -> getOpcode ( ) == <STR_LIT> || LoopCount -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) { LoopCount -> eraseFromParent ( ) ; Loop -> eraseFromParent ( ) ; return <NUM_LIT> ; } LoopCount -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , true ) ) ; return


<s> OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second


<s> sri -> icode = CODE_FOR_nothing ; sri -> t_icode = CODE_FOR_nothing ; sri -> extra_cost = <NUM_LIT> ; icode = ( ( in_p ) ? reg_addr [ mode ] . reload_load : reg_addr [ mode ] . reload_store ) ; if ( REG_P ( x ) || register_operand ( x , mode ) ) { enum rs6000_reg_type to_type = reg_class_to_reg_type [ ( int ) rclass ] ; bool altivec_p = ( rclass == ALTIVEC_REGS ) ; enum rs6000_reg_type from_type = register_to_reg_type ( x , & altivec_p ) ; if ( ! in_p ) std :: swap ( to_type , from_type ) ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , sri , altivec_p ) ) { icode = ( enum insn_code ) sri -> icode ; default_p = false ; done_p = true ; ret = NO_REGS ; } } if ( x == CONST0_RTX ( mode ) && VSX_REG_CLASS_P ( rclass ) ) { ret = NO_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && reg_addr [ mode ] . scalar_in_vmx_p && ! mode_supports_vmx_dform ( mode ) && ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( memory_p || ( GET_CODE ( x ) == CONST_DOUBLE ) ) ) { ret = FLOAT_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && icode != CODE_FOR_nothing && memory_p ) { int extra_cost = rs6000_secondary_reload_memory ( XEXP ( x , <NUM_LIT> ) , rclass , mode ) ; if ( extra_cost >= <NUM_LIT> ) { done_p = true ; ret = NO_REGS ; if ( extra_cost > <NUM_LIT> ) { sri -> extra_cost = extra_cost ; sri -> icode = icode ; } } } if ( ! done_p && TARGET_POWERPC64 && reg_class_to_reg_type [ ( int ) rclass ] == GPR_REG_TYPE && memory_p && GET_MODE_SIZE ( GET_MODE ( x ) ) >= UNITS_PER_WORD ) { rtx addr = XEXP ( x , <NUM_LIT> ) ; rtx off = address_offset ( addr ) ; if ( off != NULL_RTX ) { unsigned int extra = GET_MODE_SIZE ( GET_MODE ( x ) ) - UNITS_PER_WORD ; unsigned HOST_WIDE_INT offset = INTVAL ( off ) ; if ( GET_CODE ( addr ) == LO_SUM ? ( <NUM_LIT> && ( ( offset & <NUM_LIT> ) != <NUM_LIT> || ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) >= <NUM_LIT> - extra ) ) : ( offset + <NUM_LIT> <

<NUM_LIT> - extra && ( offset & <NUM_LIT> ) != <NUM_LIT> ) ) {


<s> TripCountPattern ( Instruction * P , Value * TC , FixedVectorType * VT ) : Predicate

( P ) , TripCount ( TC ) , VecTy ( VT ) { }


<s> Value * Src = ZExt -> getOperand ( <NUM_LIT> ) ; if ( ZExt -> getSrcTy ( ) == ZExt -> getDestTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ZExt << <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Src ) ; continue ; } if ( NewInsts . count ( Src ) && isa < TruncInst > ( Src ) && Src -> getType ( ) == OrigTy ) { auto * Trunc = cast < TruncInst >


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> unsigned int i ; for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS ( REGNO ( reg ) , GET_MODE ( reg ) ) ; i ++ ) if ( state -> last_set [ REGNO ( reg ) + i ] . insn != <NUM_LIT> ) { unsigned int t ; t = state -> last_set [ REGNO ( reg


<s> MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT ) ) return false ; unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT>


<s> return __builtin_mve_vhcaddq_rot90_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> void <ISA_LIT>InstPrinter :: printAddrMode4Operand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM ) ; } else O << <STR_LIT> (


<s> if ( ! mep_interrupt_p ( ) ) return false ; if ( r == REGSAVE_CONTROL_TEMP || ( TARGET_64BIT_CR_REGS && TARGET_COP && r == REGSAVE_CONTROL_TEMP + <NUM_LIT> ) ) return true ; if ( mep_asm_without_operands_p ( ) && ( ! fixed_regs [ r ] || ( r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO ) || IVC2_ISAVED_REG ( r ) ) ) return true ; if ( ! crtl -> is_leaf ) if ( r == LP_REGNO || IVC2_ISAVED_REG ( r ) ) return true ; if ( ! crtl -> is_leaf || cfun -> machine -> doloop_tags > <NUM_LIT> ) if ( r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO ) return true ; if ( crtl -> is_leaf && call_used_regs [ r ] && ! df_regs_ever_live_p ( r ) ) return false ; if ( call_used_regs [ r ] && ! fixed_regs [ r ] ) return true ; if ( IVC2_ISAVED_REG ( r ) ) return true ; return false


<s> ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return <NUM_LIT> ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ;


<s> void <ISA_LIT>ConditionalCompares :: invalidateTraces ( ) { Traces -> invalidate ( CmpConv . Head ) ; Traces -> invalidate ( CmpConv . CmpBB


<s> bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectNegArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectArithExtendedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS


<s> static bool FuncIsMadeTailCallSafe ( CallingConv :: ID


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new NaCl<ISA_LIT>_32AsmBackend ( T , OSABI , CPU


<s> return ( <NUM_LIT> - i / <NUM_LIT> ) * <NUM_LIT>


_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel (


<s> for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( ML ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } if ( ! LoLoop . Dec || LoLoop . End || LoLoop . Revert ) continue ; for ( auto & MO : MI . operands ( ) ) { if ( MI . getOpcode ( ) != <STR_LIT> && MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; LoLoop . Revert =


<s> SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = DAG . getDataLayout ( ) . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , DL , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I , DL ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) ->


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! ( VECTOR_MODE_P ( GET_MODE ( dst ) ) ? standard_sse_constant_p ( src , GET_MODE ( dst ) ) :

x86_64_immediate_operand ( src , GET_MODE ( dst ) ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ;


<s> if ( NegVal . getValueType ( ) != VT ) return SDValue ( ) ; unsigned NewOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand (


<s> case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) )


<s> AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> bool hasSVE2AES ( ) const { return HasSVE2AES


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None &&


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; bool IsZeroV1 = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsZeroV2 = <STR_LIT> ( V2 . getNode ( ) ) ; if ( IsZeroV1 && IsZeroV2 ) return getZeroVector ( ResVT , Subtarget , DAG , dl ) ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Undef = DAG . getUNDEF ( ResVT ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; V2 = DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , V2 , ZeroIdx ) ; V2 = DAG . getNode ( <STR_LIT> , dl , ResVT , V2 , ShiftBits ) ; if ( IsZeroV1 ) return V2 ; V1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , V1 , ZeroIdx ) ; V1 = DAG . getNode ( <STR_LIT> , dl , ResVT , V1 , ShiftBits ) ; V1 = DAG . getNode ( <STR_LIT> , dl ,


<s> return MI -> getOpcode ( ) == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! usesIXAddr ( * MI ) || ( Offset & <NUM_LIT>


<s> MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( <NUM_LIT> ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> EmitIntValue ( ELF :: ODK_REGINFO , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gprmask , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( MTS -> getABI ( ) . IsN32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> EmitIntValue ( ri_gprmask , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ]


<s> Instruction * User = dyn_cast < Instruction > ( Use . getUser ( ) ) ; if ( ! User ) continue ; if ( ! shouldConvertUse ( Val , User , Use . getOperandNo ( ) ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << Use . getOperandNo ( ) << <STR_LIT> ) ; DEBUG ( User -> print ( dbgs


<s> } } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc


<s> return TargetType == isMingw || TargetType ==


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) ==


<s> assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { MovePCtoLROffset = <NUM_LIT> ; MCE . startFunction ( MF )


<s> DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; assert ( DW && <STR_LIT> ) ; DW -> BeginModule ( & M , MMI , O , this , TAI ) ; if ( Subtarget -> isTargetDarwin ( ) ) Mang -> setUseQuotes ( true ) ; return


<s> return ( __m512i ) __builtin_ia32_pmovsxbq512_mask ( ( __v16qi ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8


<s> if ( ! Is32BitAddress && ! has<ISA_LIT>3 ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } if ( ! Offset . isImm ( ) ) return loadAndAddSymbolAddress ( Offset . getExpr ( ) , DstReg , BaseReg , Is32BitAddress , IDLoc , Out , STI ) ; if ( ! ABI . ArePtrs64bit ( )


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo


<s> assert ( NarrowTy . isScalar ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value ; MachineIRBuilder MIRBuilder ( I ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; MachineInstr * Extract = emitExtractVectorElt ( DstReg , DstRB , NarrowTy ,


<s> static rtx safe_vector_operand ( rtx x , enum machine_mode


<s> static SDValue foldXorTruncShiftIntoCmp ( SDNode * N , SelectionDAG & DAG ) { EVT ResultType = N -> getValueType ( <NUM_LIT> ) ; if ( ResultType != <STR_LIT> && ResultType != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; if ( ! isOneConstant ( N1 ) ) return SDValue ( ) ; SDValue Shift = N0 . getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> || ! Shift . hasOneUse ( ) ) return SDValue ( ) ; EVT ShiftTy = Shift . getValueType ( ) ; if ( ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) || Shift . getConstantOperandVal ( <NUM_LIT> ) != ShiftTy . getSizeInBits ( ) - <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue ShiftOp = Shift . getOperand ( <NUM_LIT> ) ; EVT ShiftOpTy = ShiftOp . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) ,


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getTargetData ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case


<s> bool isTargetLinux ( ) const { return TargetTriple . getOS ( ) == Triple


<s> return new Darwin<ISA_LIT>_32AsmBackend ( T ) ; case Triple :: MinGW32 : case Triple :: Cygwin : case Triple :: Win32 : if ( Triple ( TT ) . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_32AsmBackend ( T ) ; else return new Windows<ISA_LIT>AsmBackend ( T , false ) ; default : return new ELF<ISA_LIT>_32AsmBackend ( T , Triple ( TT ) .


<s> return new <ISA_LIT>MCCodeEmitter ( TM ,


<s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; bool IsLittleEndian = ( Endian == <STR_LIT> ) ; bool IsInstFixup = ( Kind >= FirstTargetFixupKind ) ; if ( IsLittleEndian && IsInstFixup && ( NumBytes == <NUM_LIT> ) ) { Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( Value & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; } else { for ( unsigned I = <NUM_LIT> ; I


<s> return ! is_fast_interrupt_func ( decl ) && ! is_interrupt_func ( decl ) && ! is_naked_func (


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return


<s> void setVarArgsSaveSize ( int Size ) { VarArgsSaveSize = Size


<s> if ( ( mangle = arm_mangle_builtin_vector_type ( type ) ) || ( mangle = arm_mangle_builtin_scalar_type (


<s> return ( __m256d ) __builtin_ia32_blendvpd256 ( ( __v4df ) __X , (


<s> if ( ! ST . hasLOB ( ) ) return false ; MF = & mf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; MF -> getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( * MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF -> front ( ) ) ; bool Changed = false ; for ( auto ML : * MLI ) { if ( ! ML -> getParentLoop ( ) ) Changed


<s> if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI . setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo (


<s> rtx flag = gen_int_mode ( known_ptrue_p , SImode ) ; rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( pred ) , gen_rtvec ( <NUM_LIT> , pred , flag , op0 , op1

) , aarch64_unspec_cond_code ( code ) ) ;


<s> Op = DAG . getVectorShuffle ( <STR_LIT> , DL , Op , DAG . getUNDEF ( <STR_LIT> ) , Mask ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> bool has<ISA_LIT>32 ( ) const { return ( <ISA_LIT>ArchVersion >= <ISA_LIT>32 && <ISA_LIT>ArchVersion

< <ISA_LIT>32Max ) || has<ISA_LIT>64 ( ) ;


<s> if ( ! GetLane ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewToVT = EVT :: getIntegerVT ( C , VT .


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 ,


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { OS << <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT>


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , const BranchProbability & Probability ) const { if ( ! TCycles || ! FCycles ) return false ; unsigned TUnpredCost = Probability . scale ( TCycles ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles ) ; unsigned UnpredCost =


<s> obstack_free ( & argv_obstack , NULL ) ; size_t symbol_name_len = strlen ( target_so_filename ) ; char * symbol_name = XALLOCAVEC ( char , symbol_name_len + <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < symbol_name_len ; i ++ ) { char c = target_so_filename [ i ] ; if ( ! ISALNUM ( c ) ) c = '_' ; symbol_name [ i ] = c ; } symbol_name [ symbol_name_len ] = '\0' ; char * opt_for_objcopy [ <NUM_LIT> ] ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ]


<s> for ( offset = <NUM_LIT> , chainp = & aof_pic_chain ; * chainp ; offset += <NUM_LIT> , chainp = & ( * chainp ) -> next ) if ( ( * chainp ) -> symname == XSTR ( x , <NUM_LIT> ) ) return plus_constant ( aof_pic_label , offset ) ; * chainp = ( struct pic_chain * ) xmalloc ( sizeof ( struct pic_chain ) ) ; ( * chainp ) -> next = NULL ; ( * chainp ) -> symname = XSTR ( x , <NUM_LIT> ) ; return plus_constant ( aof_pic_label ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> static const char * getName ( ) { return


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { int64_t Offset = Op . getImm ( ) * <NUM_LIT> ; if ( PrintBranchImmAsAddress ) O << formatHex ( Address + Offset ) ; else O << <STR_LIT> << formatImm ( Offset ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) .


<s> return NULL ; } switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT PtrTy = TLI . getPointerTy ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , PtrTy , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ) ; } case <STR_LIT> : { ConstantPoolSDNode * CN = cast < ConstantPoolSDNode > ( Node ) ; const Constant * C = CN -> getConstVal ( ) ; SDValue CP = CurDAG -> getTargetConstantPool ( C , CN -> getValueType ( <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , CP ) ; return NULL ; } case <STR_LIT> : { SDNode * ResNode = <NUM_LIT> ; if ( cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) == <NUM_LIT> ) { EVT Ty = Node -> getValueType ( <NUM_LIT> ) ; assert ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && <STR_LIT> ) ; uint16_t Register = Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ResNode = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , Node -> getDebugLoc ( ) , Register , Ty ) . getNode ( ) ; } if ( ! ResNode ) { ResNode = TrySelectToMoveImm ( Node ) ; } if ( ResNode ) return ResNode ; ResNode = SelectToLitPool ( Node ) ; assert ( ResNode && <STR_LIT> ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; Node = ResNode ; break ; } case <STR_LIT> : { if ( A64Imms :: isFPImm ( cast < ConstantFPSDNode > (


<s> } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) == & <STR_LIT> ) Worklist . push_back ( OtherReg ) ; } else if ( Use . getOpcode ( ) == <STR_LIT> || Use . getOpcode ( ) == <STR_LIT> ) { if ( Use . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { bool OnlyLMuxes = true ; for ( MachineInstr & DefMI : MRI -> def_instructions ( VirtReg ) ) if ( DefMI . getOpcode ( ) != <STR_LIT> ) OnlyLMuxes = false ; if ( OnlyLMuxes ) { addHints ( Order , Hints , & <STR_LIT> , MRI ) ; return false ; } } } } } } if ( VRM == nullptr ) return BaseImplRetVal ; SmallSet < unsigned , <NUM_LIT> > TwoAddrHints ; for ( auto & Use : MRI -> reg_nodbg_instructions ( VirtReg ) ) if ( <STR_LIT> ( Use . getOpcode ( ) ) != - <NUM_LIT> ) { const MachineOperand * VRRegMO = nullptr ; const MachineOperand * OtherMO = nullptr ; const MachineOperand * CommuMO = nullptr ; if ( VirtReg == Use . getOperand ( <NUM_LIT> ) . getReg ( ) ) { VRRegMO = & Use . getOperand ( <NUM_LIT> ) ; OtherMO = & Use . getOperand ( <NUM_LIT> ) ; if ( Use . isCommutable ( ) ) CommuMO = & Use . getOperand ( <NUM_LIT> ) ; } else if ( VirtReg == Use . getOperand ( <NUM_LIT> ) . getReg ( ) ) { VRRegMO = & Use .


<s> BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( SmallVector < MBBInfo , <NUM_LIT> > :: iterator BI = MBBs . begin ( ) , BE = MBBs . end ( ) ; BI != BE ;


<s> } ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; int ParitySrc [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned Size = Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( M % Size ) != i ) return false ; int Src = M / Size ; if ( ParitySrc [ i % <NUM_LIT> ] >= <NUM_LIT> && ParitySrc [ i % <NUM_LIT> ] != Src ) return false ; ParitySrc [ i % <NUM_LIT> ] = Src ; } if ( ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] == ParitySrc [ <NUM_LIT> ] ) return false ; IsSubAdd = ParitySrc [ <NUM_LIT> ] == <NUM_LIT> ? V1 -> getOpcode (

) == <STR_LIT> : V2 -> getOpcode ( ) == <STR_LIT> ;


<s> unsigned TmpReg2 ; if ( Imm ) { TmpReg2 = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addReg ( TmpReg1 ) . addImm ( Shift ) . addImm ( <NUM_LIT> - Shift ) ; } else TmpReg2 = TmpReg1 ; unsigned TmpReg3 , Hi , Lo ; if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { TmpReg3 = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg3 ) . addReg ( TmpReg2 )


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { PointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; CommentString =


<s> EVT VT = Op . getValueType ( ) ; unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ]


<s> bool <ISA_LIT>AsmParser :: searchSymbolAlias ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; if ( Sym ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * Expr ; if ( Sym -> isVariable ( ) ) Expr = Sym -> getVariableValue ( ) ; else return false ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar ( Operands , DefSymbol . substr ( <NUM_LIT> ) , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; return


<s> uint32_t Bits = <STR_LIT> ( ) . fromString ( getSysReg ( ) , Valid ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> Value * <ISA_LIT>IREmitter :: visitATOMXOR64_DAG ( const SDNode *


<s> if ( ! Hash && getLexer ( ) . isNot ( AsmToken :: Integer ) ) { if ( ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShiftExtend ( ShOp , <NUM_LIT> , false , S , E , getContext ( ) ) ) ; return MatchOperand_Success ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Integer ) && ! Parser . getTok ( ) . is ( AsmToken :: LParen )

&& ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) {


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT>


<s> bool ret = rs6000_can_change_mode_class ( from , to , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( from ) , GET_MODE_NAME ( to ) , reg_class_names [ rclass ] ) ; return ret


<s> if ( MI -> mayStore ( ) ) return false ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( Reg , TRI ) ; return false


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , Is64Bit , IsLittleEndian ) ; return createELFObjectWriter ( MOTW , OS ,


<s> if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else assert ( <NUM_LIT> )


<s> unsigned NopSize ; unsigned Opc , BaseReg , ScaleVal , IndexReg , Displacement , SegmentReg ; Opc = IndexReg = Displacement = SegmentReg = <NUM_LIT> ; BaseReg = <STR_LIT> ; ScaleVal = <NUM_LIT> ; switch ( NumBytes ) { case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . EmitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : OS . EmitInstruction ( MCInstBuilder ( Opc ) , STI


<s> return __builtin_neon_vaddv4hf ( __a ,


<s> if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( UNSPEC_ADDRESS ( base ) , offset ) ; fputs ( relocs [ symbol_type ] , file ) ; output_addr_const ( file , op ) ; for ( p = relocs [ symbol_type ] ; * p != <NUM_LIT> ; p


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple (


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel


<s> if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2


<s> case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; Register Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( <ISA_LIT>InstrInfo :: isVRRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; else if ( <ISA_LIT>InstrInfo :: isVFRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; const char * RegName ; RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; RegName = <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return new <ISA_LIT>MCAsmInfoDarwin (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) Inst .

addOperand ( MCOperand :: createImm ( ConstExpr -> getValue ( ) & <NUM_LIT> ) ) ;


<s> if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasAVX ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL


<s> emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( - <NUM_LIT> * UNITS_PER_WORD ) ) ) ; mem = change_address ( regbuf , DFmode , fpregs ) ; emit_move_insn ( mem , gen_rtx_REG ( DFmode , BASE_ARG_REG ( DFmode ) + regno ) ) ; } regno = first_floatreg ; if ( regno & <NUM_LIT> ) { emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( - UNITS_PER_WORD ) ) ) ; mem = change_address ( regbuf , SFmode , fpregs ) ; emit_move_insn ( mem , gen_rtx_REG ( SFmode , BASE_ARG_REG ( SFmode ) + regno - SH_REG_MSW_OFFSET ) ) ; } } else for ( regno = NPARM_REGS ( SFmode ) - <NUM_LIT> ; regno >= first_floatreg ; regno -- ) { rtx mem ; emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( - UNITS_PER_WORD ) ) ) ; mem = change_address ( regbuf , SFmode , fpregs ) ; emit_move_insn ( mem , gen_rtx_REG ( SFmode , BASE_ARG_REG ( SFmode ) + regno ) ) ; } return XEXP ( regbuf


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( DstVT . isVector ( ) && <STR_LIT> ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT SrcVT = In . getValueType ( ) ; if ( SrcVT == DstVT ) return In ; unsigned DstSizeInBits = DstVT . getSizeInBits ( ) ; unsigned SrcSizeInBits = SrcVT . getSizeInBits ( ) ; if ( ( DstSizeInBits % <NUM_LIT> ) != <NUM_LIT> || ( SrcSizeInBits % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; unsigned NumElems = SrcVT . getVectorNumElements ( ) ; if ( ! isPowerOf2_32 ( NumElems ) ) return SDValue ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; assert ( DstVT . getVectorNumElements ( ) == NumElems && <STR_LIT> ) ; assert ( SrcSizeInBits > DstSizeInBits && <STR_LIT> ) ; EVT PackedSVT = EVT :: getIntegerVT ( Ctx , SrcVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; EVT InVT = <STR_LIT> , OutVT = <STR_LIT> ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Opcode == <STR_LIT> || Subtarget . hasSSE41 ( ) ) ) { InVT = <STR_LIT> ; OutVT = <STR_LIT> ; } if ( SrcVT . is128BitVector ( ) ) { InVT = EVT :: getVectorVT ( Ctx , InVT , <NUM_LIT> / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , <NUM_LIT> / OutVT . getSizeInBits ( ) ) ; In = DAG . getBitcast ( InVT , In ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , In , DAG . getUNDEF ( InVT ) ) ; Res = extractSubVector ( Res , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; return DAG . getBitcast ( DstVT , Res ) ; } unsigned NumSubElts = NumElems


<s> MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N ->


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm (


<s> int Threshold = <NUM_LIT> + Adj ; return Latency <= Threshold ? <NUM_LIT> : Latency - Adj ; } const MCInstrDesc & UseMCID = get ( UseNode -> getMachineOpcode ( ) ) ; auto * DefMN = cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; auto * UseMN = cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isLikeA9 ( ) || Subtarget . isCortexA7 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } else if ( DefIdx == <NUM_LIT> && Latency > <NUM_LIT> && Subtarget . isSwift ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ( ShImm == <NUM_LIT> || ShImm == <NUM_LIT> || ShImm == <NUM_LIT> ) && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) Latency -= <NUM_LIT> ; else if ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Latency -= <NUM_LIT> ; break ; } } if ( DefAlign < <NUM_LIT> && Subtarget . checkVLDnAccessAlignment ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue Reg = Is64Bit ? DAG . getRegister ( <STR_LIT> , VT ) : DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Ops [ ] = { GA , Reg


<s> if ( ! lookup_attribute ( <STR_LIT> , attrs ) && ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( node ) ) ) { if ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , attrs ) ; else if ( lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) ) { tree * tail ; for ( tail = attributes ; attrs ; attrs = TREE_CHAIN ( attrs ) ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) ) warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( TREE_PURPOSE ( attrs ) ) ) ; else { * tail = tree_cons ( TREE_PURPOSE ( attrs ) , NULL_TREE


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm ==

<NUM_LIT> ) S = MCDisassembler :: SoftFail ;


<s> ElementCount EC = VT . getVectorElementCount ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumVecs ; ++ I ) assert ( VT == EVT :: getEVT ( CI . getArgOperand ( I ) -> getType ( ) ) && <STR_LIT> ) ; Info . memVT = EVT :: getVectorVT ( CI . getType ( ) -> getContext ( ) , VT . getScalarType ( ) , EC * NumVecs ) ; Info . ptrVal = CI . getArgOperand ( CI . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return


<s> } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return lower128BitVectorShuffle ( Op , V1 , V2 , VT , Subtarget , DAG ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return lower256BitVectorShuffle ( Op , V1 , V2 ,


<s> Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret +=


<s> if ( OPTION_GLIBC && ! BYTES_BIG_ENDIAN && ( ( TARGET_GLIBC_MAJOR * <NUM_LIT> ) + TARGET_GLIBC_MINOR ) >= <NUM_LIT> )


<s> if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ; return