<s> if ( ! matchShuffleWithSHUFPD ( VT , V1 , V2 , ForceV1Zero , ForceV2Zero , Immediate , Mask , Zeroable ) ) return SDValue ( ) ; if ( ForceV1Zero ) V1 = getZeroVector ( VT , Subtarget , DAG , DL ) ; if ( ForceV2Zero ) V2 = getZeroVector ( VT , Subtarget , DAG , DL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG .

getTargetConstant ( Immediate , DL , <STR_LIT> ) ) ;


<s> static SDValue getGatherNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; SDValue Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) . getVectorNumElements


<s> if ( ! matchAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && ! AM . Base_Reg . getNode ( ) && ! AM . IndexReg . getNode ( ) ) { N = Handle . getValue ( ) ; AM . Base_Reg = N . getOperand ( <NUM_LIT> ) ; AM . IndexReg = N . getOperand ( <NUM_LIT> ) ; AM . Scale = <NUM_LIT>


<s> assert ( ( ( ! Subtarget -> hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( ( Op0 . getValueType ( ) == <STR_LIT> ) && ( Op1 . getOpcode ( ) == <STR_LIT> ) && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , NewCC ) ; } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1


<s> CurrGroupSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx ] <=

ProcResCostLim ) ) CriticalResourceIdx = UINT_MAX ;


<s> if ( VectorIndex . Val >= Min && VectorIndex . Val <= Max ) return DiagnosticPredicateTy


<s> if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlign ( ) >= Align ( <NUM_LIT> ) ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills =


<s> unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) { MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * CmpMI << <STR_LIT> << * Br . MI ) ; MachineInstr * NewBR = BuildMI ( * MBB , CmpMI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg ) . addMBB ( DestBB , Br

. MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( MRI . isLowRegister ( DestReg ) && MRI . isLowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; BuildMI ( MBB , MBBI , dl , TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; while ( Bytes ) { unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; ThisVal /=


<s> void fpscr_set_from_mem ( int mode , HARD_REG_SET regs_live ) { enum attr_fp_mode fp_mode = mode


<s> SDValue LO , HI ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , SDValue ( N1 , <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , SDValue ( N1 , <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } Chain = HI . getValue ( <NUM_LIT> ) ; Glue = HI . getValue ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO , Tmp ) ) ; Results . push_back ( Chain ) ; return Glue


<s> Value * <ISA_LIT>IREmitter :: visitPINSRB ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else { llvm_unreachable ( <STR_LIT>


<s> warnIfNoMacro ( IDLoc ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : OpRegCode = <STR_LIT> ; OpImmCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpRegCode = <STR_LIT> ; OpImmCode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( OpImmCode , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; } else { unsigned ImmReg = DstReg ; if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg =


<s> CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > <NUM_LIT> ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) accessible_reg_set &= ~ reg_class_contents [ MMX_REGS ] ; if ( ! TARGET_SSE ) accessible_reg_set &= ~ reg_class_contents [ ALL_SSE_REGS ] ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) accessible_reg_set &= ~ reg_class_contents [ FLOAT_REGS ] ; if ( ! TARGET_AVX512F


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount < <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImmWithLSL ( Imm , ShiftAmount , false , S , E ) ) ; return MatchOperand_Success


<s> setAction ( { G_PTR_ADD , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } setAction ( { G_ANYEXT , s128 } , Legal ) ; getActionDefinitionsBuilder ( G_SEXT_INREG ) . lower ( ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; for ( const auto & Ty : { s16 , s32 , s64 } ) { setAction ( { G_MERGE_VALUES , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { s8 , s16 , s32 } ) { setAction ( { G_MERGE_VALUES , <NUM_LIT> ,


<s> int Size = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) Size = - Size ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Size ) ; } MBB . erase (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI


<s> getThumbBCCTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return ( MO . getImm ( )


<s> static __inline unsigned int _MM_GET_EXCEPTION_MASK ( void ) { return _mm_getcsr ( ) &


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return Ctx . GetOrCreateSymbol ( Name . str


<s> unsigned IsPCRel = <NUM_LIT> ; const MCSymbolData * SD_A = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; unsigned Index = SD_A -> getIndex ( ) ; if ( Target . getSymB ( ) ) { uint32_t FixupAddress = Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) ; const MCSymbolData * SD_B = & Asm . getSymbolData ( Target . getSymB ( ) -> getSymbol ( ) ) ; IsPCRel = <NUM_LIT> ; FixedValue = ( FixupAddress - Writer -> getSymbolAddress ( SD_B , Layout ) + Target . getConstant ( ) ) ; FixedValue += <NUM_LIT> << Log2Size ; } else { FixedValue = <NUM_LIT>


<s> return CONST_INT_P ( val ) && INTVAL ( val ) == trunc_int_for_mode (

HOST_WIDE_INT_C ( <NUM_LIT> ) , mode ) ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const <ISA_LIT>FrameLowering * AFI = static_cast < const <ISA_LIT>FrameLowering * > ( TFI ) ; return AFI -> useFPForAddressing ( MF


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo (


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _mm_sfence ( void ) { __builtin_ia32_sfence (


<s> SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits ( ) ) return SDValue ( ) ; SDValue Res = DAG . getSetCC ( dl , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int fromindex ; int endfrom ; char * frompc ; int toindex ; struct rawarc rawarc ; char * profdir ; const char * proffile ; char * progname ; char buf [ PATH_MAX ] ; extern char * * ___Argv ; moncontrol ( <NUM_LIT> ) ; if ( ( profdir = getenv ( <STR_LIT> ) ) != NULL ) { if ( * profdir == '\0' ) { return ; } progname = strrchr ( ___Argv [ <NUM_LIT> ] , '/' ) ; if ( progname == NULL ) progname = ___Argv [ <NUM_LIT> ] ; else progname ++ ; sprintf ( buf , <STR_LIT> , profdir , ( long ) getpid ( ) , progname ) ; proffile = buf ; } else { proffile = <STR_LIT> ; } fd = creat (


<s> std :: getline ( ss , tokens . back ( ) , ',' ) ; } if ( tokens . empty ( ) ) err_ret ( <STR_LIT> ) ; { for ( size_t i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) if ( tokens . front ( ) == model_names [ i ] ) { ret . type = ( <STR_LIT> ) i ; ret . name = model_names [ i ] ; ret . cdef_name = model_cdef_names [ i ] ; goto got_mode_name ; } err_ret ( <STR_LIT> , tokens . front ( ) . c_str ( ) ) ; got_mode_name : ; } for ( size_t i = <NUM_LIT> ; i < tokens . size ( ) ; ++ i ) { if ( tokens [ i ] == <STR_LIT> ) ret . strict = true ; else if ( tokens [ i ] . find ( <STR_LIT> ) == <NUM_LIT> ) { std :: string offset_str = tokens [ i ] . substr ( strlen ( <STR_LIT> ) ) ; ret . tcb_gbr_offset = integral_argument ( offset_str . c_str ( ) ) ; if ( offset_str . empty ( ) || ret . tcb_gbr_offset == - <NUM_LIT>


<s> for ( auto & MI : MBB ) { if ( ! MI . isCall ( ) ) continue ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( const auto & LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI ) ; incStackMBB -> addLiveIn ( LI ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; SPLimitOffset = getHiPELiteral ( HiPELiteralsMD , <STR_LIT> ) ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ; CALLop = <STR_LIT>


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCNaClExpander ( The<ISA_LIT>_32Target , create<ISA_LIT>_32MCNaClExpander ) ; TargetRegistry :: RegisterMCNaClExpander ( The<ISA_LIT>_64Target ,


<s> EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , DCI , Subtarget ) ) return FPLogic ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue R = combineAndNotIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> &&

isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) {


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> ||


<s> if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ; static const TypeConversionCostTblEntry < MVT > AVXConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) ) { int Idx = ConvertCostTableLookup < MVT > ( AVXConversionTbl , array_lengthof ( AVXConversionTbl ) , ISD , DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return


<s> assert ( ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; return lowerAddSubToHorizontalOp ( Op ,


<s> break ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> ) return false ; unsigned Arg2 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg2 == <NUM_LIT> ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( Arg1 ) . addReg ( Arg2 ) ) ; if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) .


<s> return ( __mmask16 ) __builtin_ia32_ptestnmw256 ( ( __v16hi )


<s> if ( ! LogAlign ) return <NUM_LIT> ; unsigned AlignAmt = <NUM_LIT> << LogAlign ; unsigned ParentLogAlign = MBB . getParent ( ) -> getLogAlignment ( ) ; if ( LogAlign <= ParentLogAlign ) return OffsetToAlignment ( Offset , AlignAmt ) ; if ( FirstImpreciseBlock < <NUM_LIT> ) FirstImpreciseBlock = MBB . getNumber (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( *

this ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) {


<s> static void EmitBranchToAt ( uint64_t At , uint64_t To , bool isCall , bool is64Bit ) { intptr_t Offset = ( ( intptr_t ) To - ( intptr_t ) At ) >> <NUM_LIT> ; unsigned * AtI = ( unsigned * ) ( intptr_t ) At ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset < ( <NUM_LIT> << <NUM_LIT> ) ) { AtI [ <NUM_LIT> ] = BUILD_B ( Offset , isCall ) ; } else if ( ! is64Bit ) { AtI [ <NUM_LIT> ] = BUILD_LIS ( <NUM_LIT> , To >> <NUM_LIT> ) ; AtI [ <NUM_LIT> ] = BUILD_ORI ( <NUM_LIT> , <NUM_LIT> , To ) ; AtI [ <NUM_LIT> ] = BUILD_MTCTR ( <NUM_LIT> ) ; AtI [ <NUM_LIT> ] = BUILD_BCTR ( isCall ) ; }


<s> int <ISA_LIT>TTIImpl :: getVectorInstrCost ( unsigned Opcode , Type * Val , unsigned


<s> uint64_t Mask = ( <NUM_LIT> << Num1s ) - <NUM_LIT> ; uint64_t WidthMask = Width == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << Width ) - <NUM_LIT> ; if ( Rotation != <NUM_LIT> && Rotation != <NUM_LIT> ) Mask = ( Mask >> Rotation ) | ( ( Mask << ( Width - Rotation ) ) & WidthMask ) ; Imm = Mask ; for ( unsigned i = <NUM_LIT> ; i < RegWidth / Width ; ++ i ) { Mask <<= Width ; Imm |= Mask ; } return


<s> if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; SDValue Ins128Idx = DAG . getConstant ( Upper ? NumElems / <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) ; SDValue V = Extract128BitVector ( N0 , Ins128Idx , DAG , dl ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , Upper ? DAG . getConstant ( IdxVal - NumElems / <NUM_LIT> , <STR_LIT> ) : N2 ) ; return Insert128BitVector ( N0 , V , Ins128Idx , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode (


<s> return new MandarinPassConfig ( this


<s> if ( flag_pic ) switch ( ptr -> x_ix86_cmodel ) { case CM_SMALL : ptr -> x_ix86_cmodel = CM_SMALL_PIC ; break ; case CM_MEDIUM : ptr -> x_ix86_cmodel = CM_MEDIUM_PIC ; break ; case CM_LARGE : ptr -> x_ix86_cmodel = CM_LARGE_PIC ; break ; case CM_KERNEL : error ( <STR_LIT> , <STR_LIT> ) ; break ; default : break ; } else switch ( ptr -> x_ix86_cmodel ) { case CM_SMALL_PIC : ptr -> x_ix86_cmodel = CM_SMALL ; break ; case CM_MEDIUM_PIC


<s> static bool isConstantOrUndefBUILD_VECTOR ( const BuildVectorSDNode * Op ) { for ( unsigned i = <NUM_LIT> ; i < Op -> getNumOperands ( ) ; ++ i ) if ( isConstantOrUndef ( Op -> getOperand ( i ) ) ) return true ; return false


<s> SDLoc DL ( Op ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : if ( Subtarget . hasBWI ( ) ) return lowerV32I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; break ; case <STR_LIT> : if ( Subtarget . hasBWI ( ) ) return lowerV64I8VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return splitAndLowerVectorShuffle ( DL , VT , V1


<s> unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register ) ; return true


<s> MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( Subtarget -> hasSPE ( ) ) { unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; Register DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return true ; } if ( ! IsSigned && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { Register TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; unsigned


<s> Qn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Qm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> const char * name ; size_t nlen , plen ; char * string ; plen = strlen ( prefix ) ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; nlen = strlen ( name ) ; string = alloca ( nlen + plen + <NUM_LIT> ) ; memcpy ( string , prefix , plen ) ; memcpy ( string + plen , name , nlen + <NUM_LIT>


<s> unsigned Size = <NUM_LIT> << ( AccessInfo & <NUM_LIT> ) ; if ( Size != <NUM_LIT> ) OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Size - <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( HandleMismatchSym , OutContext ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( ReturnSym , OutContext ) ) , * STI ) ; OutStreamer -> EmitLabel ( HandleMismatchSym ) ; } OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; if ( Reg != <STR_LIT> ) OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> )


<s> Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ; if ( isa < InsertElementInst > ( LoadUser ) ) IsVectorAccess = true ; } if ( ! isUInt < <NUM_LIT> > ( Offset ) && ( IsFPAccess || IsVectorAccess ) ) return false ; return


<s> FunctionPass * llvm :: create<ISA_LIT>TOCRegDepsPass ( ) { return new <ISA_LIT>TOCRegDeps (


<s> if ( isa < Constant > ( Op ) && ComputeNumSignBits ( Op , * DL , <NUM_LIT> , nullptr , BO ) > <NUM_LIT> ) return true ; if ( auto * Cast = dyn_cast < CastInst > ( Op ) ) { if ( Cast -> getParent ( ) == BB && ( Cast -> getOpcode ( ) == Instruction :: SExt || Cast -> getOpcode ( ) == Instruction :: ZExt ) && ComputeNumSignBits ( Op , * DL , <NUM_LIT> , nullptr , BO ) > <NUM_LIT> ) return true ; } return false ; } ; if ( ! canShrinkOp ( LHS ) && ! canShrinkOp ( RHS ) ) return false ; IRBuilder < > Builder ( Add ) ; Type * MulTy = Op -> getType ( ) ; unsigned NumElts = MulTy -> getVectorNumElements ( ) ; SmallVector < uint32_t , <NUM_LIT> > EvenMask ( NumElts / <NUM_LIT> ) ; SmallVector < uint32_t , <NUM_LIT> > OddMask ( NumElts / <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i != e ; ++ i ) { EvenMask [ i ] = i * <NUM_LIT> ; OddMask [ i ] = i * <NUM_LIT> + <NUM_LIT> ; } Value * EvenElts = Builder . CreateShuffleVector ( BO , BO , EvenMask ) ; Value * OddElts = Builder . CreateShuffleVector ( BO , BO , OddMask ) ; Value * MAdd = Builder . CreateAdd ( EvenElts , OddElts ) ; SmallVector < uint32_t , <NUM_LIT> > ConcatMask ( NumElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end


<s> static bool isReachableFromPHI ( PHINode * Phi , BinaryOperator * BO ) { if ( ! Phi -> hasOneUse ( ) ) return false ; Instruction * U = cast < Instruction >


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ( RegNo & <NUM_LIT> ) ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = IntPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair


<s> if ( ! last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < <NUM_LIT> ) ) return ; if ( mode == SImode || mode == HImode || mode == QImode || mode == DImode ) { if ( l <= <NUM_LIT> ) cum


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __t1mskc_u32 ( unsigned int


<s> static short find_set_regmode_weight ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == CLOBBER && register_operand ( SET_DEST ( x ) , mode ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == SET && register_operand ( SET_DEST ( x ) , mode ) ) { if ( REG_P ( SET_DEST ( x ) ) ) { if ( ! reg_mentioned_p ( SET_DEST ( x ) , SET_SRC ( x ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } return


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = <NUM_LIT> * HOST_BITS_PER_WIDE_INT - <NUM_LIT> ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return


<s> if ( flag_vect_cost_model ) { int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options ,

RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle ) , DataLayout ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> :


<s> assert ( RC -> contains ( PReg ) && <STR_LIT> ) ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister (


<s> Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements || ! L -> isLoopInvariant ( BECount ) ) return false ; return


<s> break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . emitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OS . emitInstruction ( MCInstBuilder ( Opc ) , * Subtarget ) ; break ; case <STR_LIT> : OS . emitInstruction ( MCInstBuilder ( Opc ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) , * Subtarget ) ; break ; case <STR_LIT> : case


<s> EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , NULL , <NUM_LIT> , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , NULL , <NUM_LIT> , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> )


<s> return Kind == Memory && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size ||


<s> return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) &&

getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> return ( int8x8_t ) __builtin_aarch64_shaddv8qi (


<s> if ( ArgFlags . isHva ( ) ) return true ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } if ( ! ValVT . isFloatingPoint ( ) ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; ArgFlags . setInReg


<s> continue ; } if ( ! MI -> hasDelaySlot ( ) ) continue ; MachineBasicBlock :: iterator D = MBB . end ( ) ; if ( ! DisableDelaySlotFiller ) D = findDelayInstr ( MBB , MI ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( I , & MBB , D ) ; unsigned structSize = <NUM_LIT> ; if ( needsUnimp ( MI , structSize ) ) { MachineBasicBlock :: iterator J = MI ; ++ J ; assert ( J != MBB . end ( ) && <STR_LIT> ) ; BuildMI ( MBB , ++ J , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( structSize ) ; MIBundleBuilder ( MBB , MachineBasicBlock :: iterator ( MI ) , J ) ; } else { MIBundleBuilder ( MBB , MachineBasicBlock :: iterator ( MI


<s> ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> (


<s> SDValue <ISA_LIT>TargetLowering :: LowerAsSplatVectorLoad ( SDValue SrcOp , EVT VT , DebugLoc dl , SelectionDAG & DAG ) const { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( SrcOp ) ) { SDValue Ptr = LD -> getBasePtr ( ) ; if ( ! <STR_LIT> ( LD ) || LD -> isVolatile ( ) ) return SDValue ( ) ; EVT PVT = LD -> getValueType ( <NUM_LIT> ) ; if ( PVT != <STR_LIT> && PVT != <STR_LIT> ) return SDValue ( ) ; int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm8 = MO1 . getImm ( ) ; return ( Reg << <NUM_LIT> )


<s> SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasInt256 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero


index , __m128d mask , const int scale ) {


<s> if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; Mask = DAG . getBitcast ( MaskVT , Mask ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ; return DAG . getMergeValues ( { Res , Res .


<s> return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case FK_Data_4 : return <NUM_LIT> ; case


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { unsigned Offset = <NUM_LIT> ; Offset += SlotSize ; Offset += MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; Offset += getWinEHFuncletFrameSize ( MF


<s> SmallVector < const User * , <NUM_LIT> > Worklist ; for ( auto * U : V -> users ( ) ) Worklist . push_back ( U ) ; while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > (


<s> static enum cpp_ttype mep_pragma_lex ( tree * valp ) { enum cpp_ttype t = pragma_lex


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset += MFI . getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI . getLocalFrameMaxAlign ( ) > TFI -> getStackAlign ( ) ) && canRealignStack (


<s> void changeAndComment ( bool b ) { if ( b == OS .


<s> ++ NumInstsInserted ; ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { Register ActualRetAddrReg = MRI -> createVirtualRegister (


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( Subtarget -> getABI ( ) . GetEnumValue ( ) ) { case <ISA_LIT>ABIInfo :: ABI :: O32 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: N32 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: N64 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: EABI : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFRegX ( SMLoc L ) { unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFRegX ( Reg , Offset


<s> TargetLoweringBase :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( SI ) ) return AtomicExpansionKind


<s> Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { unsigned ResultReg = createResultReg ( &


<s> const bool NonPCrelGEPRequired = ! Subtarget -> isUsingPCRelativeCalls ( ) && Subtarget -> isELFv2ABI ( ) && UsesX2OrR2 ; if ( NonPCrelGEPRequired || PCrelGEPRequired ) { MCSymbol * GlobalEntryLabel = <ISA_LIT>FI -> getGlobalEPSymbol ( * MF ) ; OutStreamer -> emitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = <ISA_LIT>FI ->


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant (

<ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ;


<s> return false ; } bool WasThumb = isThumb ( ) ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON ( MVT VT ) { addRegisterClass ( VT , & <STR_LIT> )


<s> if ( SDValue HOp = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return HOp ; if ( SDValue COp = combineFaddCFmul ( N , DAG , Subtarget ) ) return COp ; return SDValue ( )


<s> bool isSingleFloat ( ) const { return


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel (


<s> else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode


<s> } if ( NeedSplit ) { splitBlockBeforeInstr ( * MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addMBB ( NextBB ) ; } Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( * MI ) ; MI -> eraseFromParent (


<s> void <ISA_LIT>TargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { setAttributeItem ( Attribute , Value


<s> bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; if ( Flags . isByVal ( ) ) return FIN ; return DAG . getLoad ( ValVT , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI )


<s> return ( __m128i ) __builtin_ia32_cvttpd2dq256_mask ( ( __v4df ) __A , ( __v4si ) _mm_setzero_si128 ( )


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWindowsUnwindTables ( WinEH


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc Loc = MI . getDebugLoc ( ) ; auto InsertPt = MI


<s> printPCRelImm ( MI , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI


<s> return BaseT :: getShuffleCost ( Kind , Tp , Index


<s> } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) . addReg ( Op0Reg ) . addReg ( Op0Reg ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1Reg ) . addReg ( Op2Reg ) ; UpdateValueMap ( I , ResultReg ) ; return true


<s> if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = TYPE_ARG_TYPES ( fntype ) ? TRUE : FALSE ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == <NUM_LIT> && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > <NUM_LIT> && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = <NUM_LIT> ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode


<s> assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( unsigned LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn (


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; int e = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) ,


<s> static SDValue lowerV2X128Shuffle ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , Zeroable , WidenedMask ) ) return SDValue ( ) ; bool IsLowZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; bool IsHighZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; if ( WidenedMask [ <NUM_LIT> ] == <NUM_LIT> && IsHighZero ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX (


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ; if ( Subtarget -> isTargetELF ( ) && ! Subtarget -> isThumb1Only ( ) && TM -> Options . EnableFastISel )

addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ;


<s> return ( unsigned char ) __builtin_ia32_kortestcdi (


<s> if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex (


<s> unsigned <ISA_LIT>ABIInfo :: GetStackPtr ( ) const { return IsCheriPureCap ( ) ? <STR_LIT> : ( ArePtrs64bit ( ) ? <STR_LIT>


<s> OperandMatchResultTy parsePCRel12 ( OperandVector & Operands ) { return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) ,

( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , false ) ;


<s> if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { Rb = gen_rtx_REG ( SImode , cfun -> machine -> va_args_first_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> va_args_last_regno ) ; nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( <NUM_LIT> ) , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> naked_p ) return ; Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = <NUM_LIT> ; if ( cfun -> machine -> fp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> gp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> lp_size ) en4_const += <NUM_LIT> ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == <NUM_LIT> ) ) { nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( en4_const ) , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; RTX_FRAME_RELATED_P ( fp_adjust_insn ) = <NUM_LIT> ; } sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun ->

machine -> callee_saved_area_gpr_padding_bytes ;


<s> MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent (


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass

( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ;


<s> SDValue Hi64 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg128 ) ; SDValue Lo64 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg128 ) ; if ( isV9 ) Hi64 = DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Hi64 ) ; else Hi64 = LowerF64Op ( Op , DAG ) ; SDValue DstReg128 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF ,


<s> Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Register , StartLoc , EndLoc ) ) ; } else { if ( isParsingHLASM ( ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg ) ) return MatchOperand_ParseFail ; if ( Reg . Num > <NUM_LIT> ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegisterKind Kind ; unsigned RegNo ; if ( Reg . Group == RegGR ) { Kind = GR64Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegFP ) { Kind = FP64Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegV ) { Kind = VR128Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegAR ) { Kind = AR32Reg


<s> MachineOperand & DestLo = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & DestHi = MI . getOperand ( <NUM_LIT> ) ; Register StatusReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool StatusDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DesiredLoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DesiredHiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewLoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewHiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( AddrReg ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addReg ( DesiredLoReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addReg ( DesiredHiReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( StatusReg , RegState :: Kill ) . addUse ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [


<s> bool <ISA_LIT>AsmParser :: ParseOperand ( OperandVector & Operands ) { switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: LParen : case AsmToken :: RParen : Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) , getLexer ( ) . getTok ( ) . getLoc ( ) ) ) ; getLexer ( ) . Lex ( ) ; return false ; default : break ; } unsigned RegNo ; if ( ! ParseRegister ( RegNo , Operands ) ) return false ; SMLoc S = getLexer ( ) . getTok ( ) . getLoc ( ) ; if ( ! ParseImmediate ( Operands ) || ! ParseSymbolReference ( Operands ) ) { return false ; } return Error ( S


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent


<s> static SDValue PerformMSTORECombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { MaskedStoreSDNode * Mst = cast < MaskedStoreSDNode > ( N ) ; if ( ! Mst -> isTruncatingStore ( ) ) return SDValue ( ) ; EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++

i ) ShuffleVec [ i ] = NumElems * SizeRatio ;


<s> vld3_s64 ( const int64_t * __a ) { int64x1x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; return ret


<s> } else if ( ! TARGET_AVX512F ) str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , <NUM_LIT> ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl


<s> enum attr_mode insn_mode = get_attr_mode ( insn ) ; switch ( insn_mode ) { case MODE_XI : case MODE_V8DF : case MODE_V16SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_OI : case MODE_V4DF : case MODE_V8SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_TI : case MODE_V2DF : case MODE_V4SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_DI : if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) { if ( HAVE_AS_IX86_INTERUNIT_MOVQ ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) { if ( HAVE_AS_IX86_INTERUNIT_MOVQ ) return <STR_LIT> ; else return <STR_LIT> ; } else return <STR_LIT> ; case MODE_SI : if ( GENERAL_REG_P ( operands [


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; LiveRegs . init ( TII -> getRegisterInfo ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF


<s> mode = SPARC_INT_REG_P ( i ) ? DImode : DFmode ; regno = i ; } else if ( reg0 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i ; } else if ( reg1 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i + <NUM_LIT> ; offset += <NUM_LIT> ; } else { if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; continue ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 ) = <NUM_LIT> ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) ; set2 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode


<s> static inline unsigned getNEONModImmVal ( unsigned ModImm ) { return ModImm


<s> SelectionDAG & DAG = DCI . DAG ; DebugLoc DL = N -> getDebugLoc ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t ExtraSignBits = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t BitsOnLeft = Shift -> getConstantOperandVal (


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) , Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue MaskedShamt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeftLo2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , MaskedShamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo2 , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues (


<s> void i386_pe_record_external_function ( tree decl , const char * name ) { struct extern_list * p


<s> if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand (


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } } ; return makeArrayRef (


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return


<s> } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { KnownBits MKnown ; CurDAG -> computeKnownBits ( Op1 . getOperand ( <NUM_LIT> ) , MKnown ) ; bool CanFoldMask = InsertMask == MKnown . One . getZExtValue ( ) ; unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && CanFoldMask && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } } SH &= <NUM_LIT> ; SDValue Ops [ ] = { Op0 , Op1 , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) , getI32Imm


<s> if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params -> int_reassoc_width ; if ( FLOAT_MODE_P ( mode )

) return aarch64_tune_params -> fp_reassoc_width ;


<s> static unsigned findScratchNonCalleeSaveRegister ( MachineBasicBlock * MBB ) { MachineFunction * MF = MBB -> getParent ( ) ; if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; if ( ! RS . isRegUsed ( <STR_LIT> ) ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget


<s> if ( ! HasFp256 || ! VT . is256BitVector ( ) ) return false ; unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT>


<s> SrcSR = DstSR = <NUM_LIT> ; unsigned oc = MI . getOpcode ( ) ; if ( oc == <STR_LIT> || oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } return false


<s> int regno ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; ++ regno ) { char name [ <NUM_LIT> ] ; if ( ! ( ( pic_labels_used >> regno ) & <NUM_LIT> ) ) continue ; get_pc_thunk_name ( name , regno ) ; if ( USE_HIDDEN_LINKONCE ) { tree decl ; decl = build_decl ( FUNCTION_DECL , get_identifier ( name ) , error_mark_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_ONE_ONLY ( decl ) = <NUM_LIT> ; ( * targetm . asm_out . unique_section ) ( decl , <NUM_LIT> ) ; named_section ( decl , NULL , <NUM_LIT> ) ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file ,


<s> Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . LaneIndex = Index ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc


) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> int regno ; int reg_save_count = <NUM_LIT> ; for ( regno = GP_REG_LAST ; regno >= GP_REG_FIRST ; regno -- ) if ( BITSET_P ( mask , regno - GP_REG_FIRST ) ) reg_save_count += <NUM_LIT> ; base_offset = gp_offset - ( ( reg_save_count - <NUM_LIT> ) * <NUM_LIT> ) ; base_reg_rtx = iq2000_add_large_offset_to_sp ( base_offset ) ; } for ( regno = GP_REG_LAST ; regno >= GP_REG_FIRST ; regno -- ) { if ( BITSET_P ( mask , regno - GP_REG_FIRST ) ) { rtx reg_rtx ; rtx mem_rtx = gen_rtx_MEM ( gpr_mode , gen_rtx_PLUS ( Pmode , base_reg_rtx , GEN_INT ( gp_offset - base_offset ) ) ) ; reg_rtx = gen_rtx_REG ( gpr_mode , regno ) ; if ( store_p ) iq2000_emit_frame_related_store ( mem_rtx , reg_rtx


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR6 ( ( v8qi ) mm , ( v8qi


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int


<s> } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( TARGET_ILP32 ) error ( <STR_LIT>


<s> for ( auto & MI : MBB ) { MachineInstr * CurrInstr = & MI ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( PrevInstr ) { DEBUG ( dbgs ( ) << <STR_LIT> << * PrevInstr << <STR_LIT> << * CurrInstr << <STR_LIT> << isFirstInstructionInSequence ( PrevInstr ) << <STR_LIT> << <STR_LIT> << isSecondInstructionInSequence ( CurrInstr ) << <STR_LIT> ) ; if ( isFirstInstructionInSequence ( PrevInstr ) && isSecondInstructionInSequence ( CurrInstr ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Idx << <STR_LIT> ) ; Sequences . push_back ( CurrInstr ) ; } } if ( ! CurrInstr -> isPseudo ( ) ) PrevInstr = CurrInstr ; ++ Idx


<s> for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>elTarget ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64elTarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; } for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEB ) ; for ( Target * T : { & getThe<ISA_LIT>elTarget ( ) , & getThe<ISA_LIT>64elTarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackendEB32 ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>AsmBackendEL32 ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>64Target


<s> tree attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; tree args ; if ( attr == NULL ) return SHADOW_SET_NO ; args = TREE_VALUE ( attr ) ; if ( args == NULL )


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( VT == N0 . getValueType ( ) && ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . zextOrTrunc ( <NUM_LIT> ) . uge ( NumBitsPerElt ) ) { if ( LogicalShift ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( LogicalShift && ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } SmallBitVector UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned ShiftImm = ShiftVal . getZExtValue ( ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt = Elt . shl ( ShiftImm ) ; else if ( <STR_LIT> == Opcode ) Elt = Elt . ashr ( ShiftImm ) ; else Elt = Elt . lshr ( ShiftImm ) ; } return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) ,


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return false


<s> bool isShiftExtend ( ) const { return Kind


<s> } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= <NUM_LIT> ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; for ( const Argument & Arg : F -> args ( ) ) { unsigned ArgNo = Arg . getArgNo ( ) ; unsigned SrcReg = GPRArgRegs [ ArgNo ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC


<s> assert ( isa < VectorType > ( Ty ) && <STR_LIT> ) ; unsigned ScalarBits = Ty -> getScalarSizeInBits ( ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; switch ( Opcode ) { case Instruction :: FAdd : case Instruction :: FMul : case Instruction :: And : case Instruction ::


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return


<s> Value * <ISA_LIT>IREmitter :: visitLCMPXCHG16_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRRSext ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) { ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || ! NC -> isZero ( ) ) return false ; Base = Offset = N ; return true


<s> m_SymbolOrderMap . clear ( ) ; m_MultipartList . clear ( ) ; m_MultipartList . push_back ( GOTMultipart ( ) ) ; m_MultipartList . back ( ) . m_Inputs . insert ( m_pInput ) ; m_MergedGlobalSymbols . clear ( ) ; m_InputGlobalSymbols . clear ( ) ; m_MergedLocalSymbols . clear ( ) ; m_InputLocalSymbols . clear ( ) ; m_InputTLSGdSymbols . clear (


<s> return __builtin_mve_vldrhq_z_uv4si ( ( __builtin_neon_hi *


<s> MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; bool PostRA = ! MRI -> isSSA ( ) ; if ( ! PostRA ) return false ; unsigned ToBeDeletedReg = <NUM_LIT> ; int64_t OffsetImm = <NUM_LIT> ; unsigned XFormOpcode = <NUM_LIT> ; ImmInstrInfo III ; if ( ! isImmInstrEligibleForFolding ( MI , ToBeDeletedReg , XFormOpcode , OffsetImm , III ) ) return false ; bool OtherIntermediateUse = false ; MachineInstr * ADDMI = getDefMIPostRA ( ToBeDeletedReg , MI , OtherIntermediateUse ) ; if ( OtherIntermediateUse || ! ADDMI ) return false ; if ( ! isADDInstrEligibleForFolding ( * ADDMI ) ) return false ; unsigned ScaleRegIdx = <NUM_LIT> ; int64_t OffsetAddi = <NUM_LIT> ; MachineInstr * ADDIMI = nullptr ; if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else return false ; assert ( ADDIMI && <STR_LIT> ) ; unsigned ToBeChangedReg = ADDIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScaleReg = ADDMI -> getOperand ( ScaleRegIdx ) . getReg ( ) ; auto NewDefFor = [ & ] ( unsigned Reg , MachineBasicBlock :: iterator Start , MachineBasicBlock :: iterator End ) { for ( auto It = ++ Start ; It != End ; It ++ ) if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) return true ; return false ; } ; if ( NewDefFor ( ToBeChangedReg , * ADDMI , MI ) || NewDefFor ( ScaleReg , * ADDMI , MI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; LLVM_DEBUG ( ADDIMI -> dump ( ) ) ; LLVM_DEBUG ( ADDMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; ADDIMI -> getOperand ( <NUM_LIT> ) . setImm ( OffsetAddi + OffsetImm ) ; MI . setDesc ( get ( XFormOpcode ) ) ; MI . getOperand ( III . ImmOpNo ) . ChangeToRegister ( ScaleReg , false , false , ADDMI

-> getOperand ( ScaleRegIdx ) . isKill ( ) ) ;


<s> void setFramePointerSaveIndex ( int Idx ) { FramePointerSaveIndex =


<s> return __builtin_aarch64_sqrtv4sf ( a


<s> for ( const MachineOperand & MO : MI . uses ( ) ) if ( MO . isFI ( ) ) return true ; return false


<s> bool isMachineVerifierClean ( ) const override { return false


<s> fprintf ( file , <STR_LIT> , reg_names [ PIC_OFFSET_TABLE_REGNUM ] , reg_names [ PIC_OFFSET_TABLE_REGNUM ] ) ; } } if ( delta != <NUM_LIT> ) { if ( satisfies_constraint_Is15 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , this_regno , this_regno , delta ) ; } else if ( satisfies_constraint_Is20 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } else { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } } if ( flag_pic ) { fprintf ( file , <STR_LIT> ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> )


<s> rtx end_label = gen_label_rtx ( ) ; value = force_reg ( QImode , value ) ; if ( need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( size , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , end_label ) ; if ( ! need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_label ( byte_mode_label ) ; nds32_emit_post_inc_load_store ( value , itr , QImode , false ) ; emit_cmp_and_jump_insns ( end , itr , NE , NULL , Pmode , <NUM_LIT> , byte_mode_label ) ; emit_label (


<s> else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == <NUM_LIT> ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = <NUM_LIT> ; i < ( size - rounded_size ) ; i += <NUM_LIT> ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - <NUM_LIT> ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - ( size - rounded_size - i + <NUM_LIT> ) ) ; emit_stack_probe ( r1


<s> vmlsl_high_n_u32 ( uint64x2_t a , uint32x4_t b , uint32_t c ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_PCS_RegMask


<s> bool isModImm ( ) const { return Kind ==