<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering


<s> static bool isConsecutiveLS ( SDNode * N , LSBaseSDNode * Base , unsigned Bytes , int Dist , SelectionDAG & DAG ) { if ( LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( N ) ) { EVT VT = LS -> getMemoryVT ( ) ; SDValue Loc = LS -> getBasePtr ( ) ; return isConsecutiveLSLoc ( Loc , VT , Base , Bytes , Dist , DAG ) ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { EVT VT ; switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; } return isConsecutiveLSLoc ( N -> getOperand ( <NUM_LIT> ) , VT , Base , Bytes , Dist , DAG ) ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { EVT VT ; switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case


<s> SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > ( - <NUM_LIT> ) & <NUM_LIT> , } ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size ; Align Alignment ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo ::


<s> return __builtin_mve_vcmpltq_m_fv8hf ( __a ,


<s> MVT EltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( EltVT == Src . getSimpleValueType ( ) . getVectorElementType ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo = extractSubVector ( Src , <NUM_LIT> , DAG ,


<s> } } if ( isContactVector ) { int offset = NumElts / <NUM_LIT> ; for ( int I = NumElts / <NUM_LIT> , E = NumElts ; I != E ; I ++ ) { if ( Mask [ I ] != I + splitV0 * offset ) { isContactVector = false ; break ; } } } if ( isContactVector ) { EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts / <NUM_LIT> ) ; if ( splitV0 ) { V0 = DAG . getNode ( <STR_LIT> , DL , CastVT , V0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( V1 . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { V1 = DAG . getNode ( <STR_LIT> , DL , CastVT , V1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } Res = DAG . getNode ( <STR_LIT> , DL , VT , V0 , V1 ) ; return


<s> if ( CmpInstr . getOpcode ( ) != <STR_LIT> ) return false ; assert ( ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) == CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) && <STR_LIT> <STR_LIT> ) ; assert ( ( MRI -> getVRegDef ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) == & CmpValDefInstr ) && <STR_LIT> ) ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; MachineInstr * VregDefInstr = MRI -> getVRegDef ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( VregDefInstr && <STR_LIT> ) ; if ( VregDefInstr -> getParent ( ) != CmpValDefInstr . getParent ( ) ) return false ; if ( <STR_LIT> ( VregDefInstr ->


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsi_u32 ( unsigned int __X ) { return ( __X &


<s> assert ( ! STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; bool ListContainsPC = false , ListContainsLR = false ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg (


<s> for ( i = <NUM_LIT> ; i < XVECLEN ( in_pat , <NUM_LIT> ) ; i ++ ) { in_exp = XVECEXP ( in_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = <NUM_LIT> ; j < XVECLEN ( out_pat , <NUM_LIT> ) ; j ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE )


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return


<s> const TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc


<s> for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; if ( NumAddrOps < <NUM_LIT> ) MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return MIB . addImm ( <NUM_LIT>


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( )

, CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_punpcklwd128 ( ( __v8hi ) __A , ( __v8hi )


<s> if ( ! sh_fsca_df2int_rtx ) { REAL_VALUE_TYPE rv ; real_from_string ( & rv , <STR_LIT> ) ; sh_fsca_df2int_rtx = const_double_from_real_value ( rv , DFmode ) ; } return sh_fsca_df2int_rtx


<s> <ISA_LIT>_64ATTAsmParser ( const Target & T , MCAsmParser & _Parser ) : <ISA_LIT>ATTAsmParser ( T , _Parser ) { Is64Bit =


<s> valist = arm_extract_valist_ptr ( valist ) ; std_expand_builtin_va_start ( valist , nextarg


<s> int fp_sethi_p ( rtx op ) { if ( GET_CODE ( op


<s> if ( CD8_Scale == <NUM_LIT> ) { CValue = Value ; return isDisp8 ( Value ) ; } unsigned Mask = CD8_Scale - <NUM_LIT> ; assert ( ( CD8_Scale & Mask ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value & Mask ) return false ; Value /= ( int ) CD8_Scale ; bool Ret = ( Value == ( int8_t ) Value ) ; if ( Ret ) CValue = Value ; return Ret


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> return ( __m128i ) __builtin_ia32_pabsq128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( ) ,


<s> return ( int ) __builtin_loongarch_crc_w_h_w ( ( short ) _1 ,


<s> NaCl<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>_64AsmBackend ( T , OSABI , CPU ) { State . PrefixSaved = <NUM_LIT> ; State . PrefixPass


<s> rtx element_offset ; rtx new_addr ; bool valid_addr_p ; gcc_assert ( GET_RTX_CLASS ( GET_CODE ( addr ) ) != RTX_AUTOINC ) ; if ( CONST_INT_P ( element ) ) element_offset = GEN_INT ( INTVAL ( element ) * scalar_size ) ; else { int byte_shift = exact_log2 ( scalar_size ) ; gcc_assert ( byte_shift >= <NUM_LIT> ) ; if ( byte_shift == <NUM_LIT> ) element_offset = element ; else { if ( TARGET_POWERPC64 ) emit_insn ( gen_ashldi3 ( base_tmp , element , GEN_INT ( byte_shift ) ) ) ; else emit_insn ( gen_ashlsi3 ( base_tmp , element , GEN_INT ( byte_shift ) ) ) ; element_offset = base_tmp ; } } if ( element_offset == const0_rtx ) new_addr = addr ; else if ( REG_P ( addr ) || SUBREG_P ( addr ) ) new_addr = gen_rtx_PLUS ( Pmode , addr , element_offset ) ; else if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) ; rtx op1 = XEXP ( addr , <NUM_LIT> ) ; rtx insn ; gcc_assert ( REG_P ( op0 ) || SUBREG_P ( op0 ) ) ; if ( CONST_INT_P ( op1 ) && CONST_INT_P ( element_offset ) ) { HOST_WIDE_INT offset = INTVAL ( op1 ) + INTVAL ( element_offset ) ; rtx offset_rtx = GEN_INT ( offset ) ; if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && ( scalar_size < <NUM_LIT> || ( offset & <NUM_LIT> ) == <NUM_LIT> ) ) new_addr = gen_rtx_PLUS ( Pmode , op0 , offset_rtx ) ; else { emit_move_insn ( base_tmp , offset_rtx ) ; new_addr = gen_rtx_PLUS ( Pmode , op0 , base_tmp ) ; } } else { bool op1_reg_p = ( REG_P ( op1 ) || SUBREG_P ( op1 ) ) ; bool ele_reg_p = ( REG_P ( element_offset ) || SUBREG_P ( element_offset ) ) ; if ( op1_reg_p && ( ele_reg_p || reg_or_subregno ( op1 ) != FIRST_GPR_REGNO ) ) { insn = gen_add3_insn ( base_tmp , op1 , element_offset ) ; gcc_assert ( insn != NULL_RTX ) ; emit_insn ( insn ) ; } else if ( ele_reg_p && reg_or_subregno ( element_offset ) != FIRST_GPR_REGNO ) { insn = gen_add3_insn ( base_tmp , element_offset , op1 ) ; gcc_assert ( insn != NULL_RTX ) ; emit_insn ( insn ) ; } else { emit_move_insn ( base_tmp , op1 ) ; emit_insn ( gen_add2_insn ( base_tmp , element_offset ) ) ; } new_addr = gen_rtx_PLUS ( Pmode , op0 ,


<s> return __builtin_aarch64_smaxv16qi ( __a ,


<s> if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movt ( result , get_t_reg_rtx ( ) ) ) ; else if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movnegt ( result , get_t_reg_rtx ( ) ) ) ; else if ( code == EQ || code == NE ) emit_insn ( gen_move_insn ( result , GEN_INT ( code == NE ) ) ) ; else return false


<s> bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; } MI . getOperand ( i ) . ChangeToRegister ( ScratchReg , false , false , true ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) MI . setDesc ( TII . get


<s> void getAnalysisUsage ( AnalysisUsage & AU


<s> case IES_NE : case IES_LT : case IES_LE : case IES_GT : case IES_GE : case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : case IES_OFFSET : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC || CurrState == IES_OFFSET ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned CRm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: Colon , <STR_LIT> ) ) return true ; } if ( getParser ( ) . parseExpression ( ImmVal ) ) return


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , int64_t offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy ,


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Cost = LT . first * <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> &&

! ST . hasAVX2 ( ) ) Cost *= <NUM_LIT> ;


<s> enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < <NUM_LIT> ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode ==


<s> unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d ->


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> unsigned Unsigned = <NUM_LIT> ; auto * Extend = Root ; if ( OriginalTy -> getPrimitiveSizeInBits ( ) < <NUM_LIT> ) { if ( ! I -> hasOneUse ( ) ) return nullptr ; Extend = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; if ( isa < SExtInst > ( Extend ) ) { Unsigned = <NUM_LIT> ; } else if ( ! isa < ZExtInst > ( Extend ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ResultTy = Extend -> getType ( ) ; if ( ResultTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } } GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , cast < FixedVectorType > ( ResultTy ) , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; Value * Load = tryCreateIncrementingGatScat ( I , BasePtr , Offsets , GEP , Builder ) ; if ( Load ) return Load ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , OriginalTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; Root = Extend


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & )


<s> static SDValue PerformVQMOVNCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; unsigned IsTop = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned NumElts = N -> getValueType ( <NUM_LIT> ) .


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( )


<s> Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] )


<s> BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( !


<s> } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Val )


<s> LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; if ( IsTailCall ) { assert ( ! Flags . isByVal ( ) && <STR_LIT> ) ; Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( <NUM_LIT> ) ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) . getReg ( <NUM_LIT> ) ; auto OffsetReg = MIRBuilder . buildConstant (


<s> CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; Data64bitsDirective = Is64Bit ? <STR_LIT> : nullptr ; SupportsDebugInformation =


<s> Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets

( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE


<s> static bool nds32_rtx_costs ( rtx x , int code , int outer_code ,


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ! flag_unwind_tables && ( !

flag_exceptions || USING_SJLJ_EXCEPTIONS ) ) return ;


<s> size_t i ; rs6000_file_start ( ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_select ) ; i ++ ) if ( rs6000_select [ i ] . set_arch_p && rs6000_select [ i ] . string && rs6000_select [ i ] . string [ <NUM_LIT> ] != '\0' ) cpu_id = rs6000_select [ i ] . string ; i = <NUM_LIT> ; while ( mapping [ i ] . arg != NULL && strcmp ( mapping [ i ] . arg , cpu_id ) != <NUM_LIT> && ( mapping [ i ] . if_set & target_flags ) == <NUM_LIT> ) i ++ ; fprintf ( asm_out_file , <STR_LIT> , mapping [ i ]


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getConstant ( getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = Outs [ i ] . Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { EVT ValVT = ValToCopy . getValueType ( ) ; if ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) == <NUM_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr


<s> __builtin_ia32_scatterpfqps ( mask , ( __v8di ) index , ( int const * ) addr ,


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Loc . getPointer ( ) + Str . size ( ) ) ; <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Token , Loc , EndLoc ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ; return Res


<s> if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT>


<s> int Offset = ArgOffset + SPDiff ; uint32_t OpSize = ( Arg . getValueType ( ) . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( OpSize , Offset , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FIN = DAG . getFrameIndex ( FI , VT ) ; TailCallArgumentInfo Info


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned FirstRegOp = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SecondRegOp = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; TOut . emitRI ( <STR_LIT> , SecondRegOp , <NUM_LIT> , IDLoc , STI ) ; if ( FirstRegOp != SecondRegOp ) TOut . emitRRR ( <STR_LIT> , FirstRegOp , SecondRegOp , <STR_LIT> , IDLoc , STI ) ; else TOut . emitEmptyDelaySlot ( false


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI

, SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ;


<s> Instrumentation -> SetInitialFrameRegister ( RegNo


<s> enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return <NUM_LIT> ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) ) return arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && GET_CODE ( addend ) == REG ) return <NUM_LIT> ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) return <NUM_LIT> ; else if ( mode == TImode ) return <NUM_LIT> ; else if ( code ==


<s> Zero1 &= isUndefOrZero ( M1 ) ; Zero2 &= isUndefOrZero ( M2 ) ; } assert ( ! ( ( Undef1 || Zero1 ) && ( Undef2 || Zero2 ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createUnpackShuffleMask ( VT , Unpckl , true , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } createUnpackShuffleMask ( VT , Unpckh , false , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true


<s> gcc_assert ( result != DOESNT_MATTER ) ; return result == IS_PST


<s> const <ISA_LIT>BaseTargetMachine & <ISA_LIT>_TM = static_cast < const <ISA_LIT>BaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = <ISA_LIT>_TM . TargetABI == <ISA_LIT>BaseTargetMachine :: <STR_LIT> ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM


<s> return ! MF . getTarget ( ) . getMCAsmInfo ( ) ->


<s> static bool isAllActivePredicate ( SelectionDAG & DAG , SDValue N ) { unsigned NumElts = N . getValueType ( ) . getVectorMinNumElements ( ) ; while ( N . getOpcode ( ) == <STR_LIT> ) { N = N . getOperand ( <NUM_LIT> ) ; if ( N . getValueType ( ) . getVectorMinNumElements ( ) < NumElts ) return false ; } if ( <STR_LIT> ( N . getNode ( ) ) ) return true ; if ( N . getOpcode ( ) == <STR_LIT> && N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return N . getValueType ( ) . getVectorMinNumElements ( ) >= NumElts ; if ( N . getOpcode ( ) == <STR_LIT> ) { const auto & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MinSVESize = Subtarget . getMinSVEVectorSizeInBits ( ) ; unsigned MaxSVESize = Subtarget . getMaxSVEVectorSizeInBits ( ) ; if ( MaxSVESize && MinSVESize == MaxSVESize ) { unsigned VScale = MaxSVESize / <STR_LIT> ; unsigned PatNumElts = getNumElementsFromSVEPredPattern ( N . getConstantOperandVal ( <NUM_LIT> ) ) ; return PatNumElts == ( NumElts * VScale ) ; } } return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT>


<s> unsigned CSSize = MF . getInfo < <ISA_LIT>FunctionInfo


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) ==


<s> SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , <NUM_LIT> ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumNOPBytes ; ++ i )

OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) ) ;


<s> for ( MCSuperRegIterator Supers ( Reg , RI ) ; Supers . isValid ( ) ; ++ Supers ) if ( <STR_LIT> .

contains ( * Supers ) ) return RI -> getSubReg ( * Supers , Odd ? <STR_LIT> : <STR_LIT> ) ;


<s> bitmap_clear_bit ( candidates , insn_uid ) ; if ( ! add_insn ( candidates , insn_uid , disallowed ) ) { bitmap_ior_into ( disallowed , insns ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain_id ) ; BITMAP_FREE ( queue ) ; return false ; } } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , chain_id ) ; fprintf ( dump_file , <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , const SDLoc & dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr ,


<s> bool hasVectorPackedDecimalEnhancement ( ) const { return HasVectorPackedDecimalEnhancement


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned long long __Y ) { return ( ( __X << ( <NUM_LIT> - __Y ) )


<s> if ( aarch64_bitmask_imm ( val_in , mode ) ) return false ; if ( aarch64_move_imm ( val_in , mode )


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>1 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ; const unsigned * SubSet = TRI -> getSubRegisters ( DestReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SubSet [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SubSet [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } else llvm_unreachable ( <STR_LIT>


<s> void addAlignedMemoryOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory .


<s> return ( mode1 == mode2 || ( ! loongarch_mode_ok_for_mov_fmt_p ( mode1 )

&& ! loongarch_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ;


<s> for ( const unsigned * Regs = MCID . ImplicitDefs ; * Regs ;

++ Regs ) if ( * Regs == <STR_LIT> ) return true ;


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned ATReg = <STR_LIT> ; unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TmpReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TOut . emitRR ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , SrcReg , TmpReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , ATReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , DstReg


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_

&& ! IsN64 ) return getAddrNonPIC ( Op , DAG ) ;


<s> static DecodeStatus DecodeCPU64RegsRegisterClass ( MCInst & Inst , unsigned RegNo ,

uint64_t Address , const void * Decoder ) {


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor ( ) { unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive ==


<s> return isInt64Immediate ( N . getNode ( ) , Imm


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( Mask == - <NUM_LIT> ) return - <NUM_LIT> ; return Mask << <NUM_LIT> ; } if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { return - <NUM_LIT> ; } if ( Flags . empty ( ) || Flags == <STR_LIT> ) return Mask | <NUM_LIT> ; for ( char Flag : Flags ) { int FlagVal ; switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal = <NUM_LIT> ; } if ( ! FlagVal || ( Mask & FlagVal ) ) return - <NUM_LIT> ; Mask |= FlagVal ; } if ( Reg == <STR_LIT> ) Mask |= <NUM_LIT> ; return


<s> switch ( Reg ) { default : return get<ISA_LIT>SubSuperRegister_ ( Reg , <STR_LIT> , false ) ; case <STR_LIT>


<s> int lane0 = INTVAL ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ; int lane1 = INTVAL ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ; int new_lane0 = <NUM_LIT> - lane1 ; int new_lane1 = <NUM_LIT> - lane0 ; XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( new_lane0 ) ; XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( new_lane1 ) ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ,


<s> return isMem ( ) && isConstantMemOff ( ) && isInt < Bits > ( getConstantMemOff

( ) ) && getMemBase ( ) -> isGPRAsmReg ( ) ;


<s> if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( bit


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> std :: string Name = GV ? Mang -> getValueName ( GV ) : TAI -> getGlobalPrefix ( ) ; if ( ! GV ) Name += ACPV -> getSymbol ( ) ; if ( ACPV -> isNonLazyPointer ( ) ) { if ( GV -> hasHiddenVisibility ( ) ) HiddenGVNonLazyPtrs . insert ( Name ) ; else GVNonLazyPtrs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; } else if ( ACPV -> isStub ( ) ) { FnStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; } else O << Name ; if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment (


<s> void Thumb1InstrInfo :: getNoop ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> )


<s> const <ISA_LIT>TargetMachine & getTargetMachine


<s> unsigned int save_reg_mask = <NUM_LIT> ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = <NUM_LIT> ; else max_reg = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; } else { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( <NUM_LIT> << reg ) ; if ( ! TARGET_APCS_FRAME && ! frame_pointer_needed && regs_ever_live [ HARD_FRAME_POINTER_REGNUM ] && ! call_used_regs


<s> gcc_assert ( to == STACK_POINTER_REGNUM ) ; if ( from == ARG_POINTER_REGNUM ) return frame . stack_pointer_offset ; gcc_assert ( from == FRAME_POINTER_REGNUM ) ; return frame . stack_pointer_offset


<s> DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; break ; } } return DAG . getNode ( <STR_LIT> , DL


<s> void <ISA_LIT>BranchTargets :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( )


<s> SDValue OneVec = Node -> getOperand ( <NUM_LIT> ) ; APInt SplatVal ; if ( ! <STR_LIT> ( OneVec , SplatVal ) || ! SplatVal . isOneValue ( ) ) return false ; SDLoc DL ( Node ) ; SDValue AllOnesVec ; APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; AllOnesVec = CurDAG -> getConstant ( Ones , DL , <STR_LIT> ( <STR_LIT> , NumElts ) ) ; insertDAGNode ( * CurDAG ,


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <NUM_LIT> ) || ( MRI -> getRegClass ( Reg )

-> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <STR_LIT> ) ;


<s> if ( isTileLoad ( * II ) ) { KeyMI = & * II ; continue ; } if ( isTileStore ( * II ) ) { assert ( KeyMI && <STR_LIT> ) ; break ; } if ( isAMXInstr ( * II ) ) { assert ( ( KeyAMXNum == <NUM_LIT> ) &&


<s> unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT>


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return


<s> ReverseIter Filler ; RegDU . init ( Slot ) ; MachineBasicBlock :: iterator SlotI = Slot ; if ( ! searchRange ( MBB , ++ SlotI . getReverse ( ) , MBB . rend ( ) , RegDU , MemDU ,


<s> assert ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasMSA ( ) && <STR_LIT> ) ; return & <STR_LIT> [


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return true ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return false ; return true


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ResTy ) ; SDValue Bit = DAG . getNode ( <STR_LIT> , DL , ResTy , One , Op -> getOperand


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel (


<s> rtx group_id ; bool valid ; def_record = DF_INSN_DEFS ( sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( sethi ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! ( recog_memoized ( use_insn ) == CODE_FOR_lo_sum || nds32_symbol_load_store_p ( use_insn ) || ( nds32_reg_base_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) ) ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id ( ) ) ; emit_insn_before ( gen_relax_group ( group_id ) , sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link


<s> static void __attribute__ ( ( format ( printf , <NUM_LIT> , <NUM_LIT> ) ) ) ovld_diag ( int diagpos , const char * fmt , ... ) { va_list args ; int real_line , real_pos ; real_line_pos ( diagpos , & real_line , & real_pos ) ; fprintf ( stderr , <STR_LIT> , ovld_path , real_line , real_pos ) ; va_start ( args , fmt


<s> if ( ! MDT -> dominates ( Def , Instr ) ) return false ; if ( UseToDefs . find ( Def ) == UseToDefs . end ( ) || UseToDefs . find ( Def ) -> second . empty ( ) ) return false ; Instr =


<s> case TargetTransformInfo :: CacheLevel :: L1D : LLVM_FALLTHROUGH ; case TargetTransformInfo :: CacheLevel :: L2D : return <NUM_LIT> ; } llvm_unreachable (


<s> static void sparc_va_start ( tree valist ,


<s> } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , true ) ; -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get (


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( ! <ISA_LIT>SubTarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl ,


<s> assert ( Kind == k_SysReg && <STR_LIT> ) ; return SysReg .


<s> FunctionPass * create<ISA_LIT>PreLegalizeCombiner ( ) { return new <ISA_LIT>PreLegalizerCombiner


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , IntReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( IntReg , getKillRegState ( true ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( FI , Subtarget . getCapAlignment ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( FI , Subtarget . getCapAlignment ( ) ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) . addReg ( <STR_LIT> ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC )


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target (


<s> enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT>


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( )


<s> tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < n_elts / <NUM_LIT> ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , <NUM_LIT> * i + use_odd ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , <NUM_LIT> * i + use_odd + n_elts ) ) ; } tree permute = elts . build (


<s> assert ( FnStart && <STR_LIT> ) ; if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; uint64_t Intval = Opcodes [ <NUM_LIT> ] | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> ; EmitIntValue ( Intval , Opcodes . size ( ) ) ; } SwitchSection ( & FnStart -> getSection ( ) ) ; EHReset ( )


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup )


<s> LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; Align OrigAlign = ArgFlags . getNonZeroOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == Align ( <NUM_LIT> ) ) ; bool isVectorFloat = <ISA_LIT>State -> WasOriginalArgVectorFloat ( ValNo ) ; if ( ValVT == <STR_LIT> && isVectorFloat ) { if ( ArgFlags . isSplit ( ) ) { Reg = State . AllocateReg ( FloatVectorIntRegs ) ; if ( Reg == <STR_LIT> ) State . AllocateReg ( <STR_LIT> ) ; else if ( Reg == <NUM_LIT> ) State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( IntRegs ) ; } } else if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg


<s> bool <ISA_LIT>TTIImpl :: prefersVectorizedAddressing ( ) const { return supportsGather (


<s> } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg > EndReg ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += EndReg - Reg ; Reg = EndReg ; continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { if ( ! Spacing ) Spacing = <NUM_LIT> ; else if ( Spacing == <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Reg = getDRegFromQReg ( Reg ) ; if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc LaneLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( LaneLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } continue ; } if ( ! Spacing ) Spacing = <NUM_LIT> + ( Reg == OldReg + <NUM_LIT> ) ; if ( Reg != OldReg + Spacing ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Count ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( )


<s> uint64_t op1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; Inst . addOperand ( MCOperand :: CreateImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( crm ) ) ; bool ValidNamed ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; ( void ) <STR_LIT> ( ) . toString ( pstate_field , Dis

-> getSubtargetInfo ( ) . getFeatureBits ( ) , ValidNamed ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> SDValue rd = DAG . getNode ( <STR_LIT> , dl , Tys , & TheChain , <NUM_LIT> ) ; SDValue rax = DAG . getCopyFromReg ( rd , dl , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; SDValue rdx = DAG . getCopyFromReg ( rax . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , rax . getValue


return function_section ( current_function_decl ) ;


<s> Parser . Lex ( ) ; StringRef Arch ; if ( Parser . parseIdentifier ( Arch ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ArchFeatureName . empty ( ) ) return reportParseError ( <STR_LIT> ) ; if ( ArchFeatureName == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) return reportParseError ( <STR_LIT> ) ; selectArch ( ArchFeatureName


<s> if ( insn -> consumedDisplacement ) return <NUM_LIT> ; insn -> consumedDisplacement = TRUE ; insn -> displacementOffset = insn -> readerCursor - insn -> startLocation ; switch ( insn -> eaDisplacement ) { case EA_DISP_NONE : insn -> consumedDisplacement = FALSE ; break ; case EA_DISP_8 : if ( consumeInt8 ( insn , & d8 ) ) return - <NUM_LIT> ; insn -> displacement = d8 ; break ; case EA_DISP_16 : if ( consumeInt16 ( insn , & d16 ) ) return - <NUM_LIT> ; insn -> displacement = d16 ; break ; case EA_DISP_32 : if ( consumeInt32 ( insn , & d32 ) ) return - <NUM_LIT> ; insn -> displacement =


<s> void addLogicalImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm (


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return *


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y


<s> AU . setPreservesAll ( ) ; AU . addRequired < MachineLoopInfo >


<s> return ( __m128h ) __builtin_ia32_getexpph128_mask ( ( __v8hf ) __A , ( __v8hf )


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div4si ( (


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackUp ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg


<s> HOST_WIDE_INT src , dest ; loongarch_compute_frame_info ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { assert ( NumOps == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { assert ( NumOps == <NUM_LIT> && getIBit ( insn ) == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; getImmShiftSE ( ShOp , ShImm ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( AddrOpcode , ShImm , ShOp ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx = <NUM_LIT> ; return true


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc ::


<s> unsigned getRegSpillOffset ( unsigned Reg ) const { return RegSpillOffsets [ Reg ]


<s> Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ,


<s> return ( uint8x16_t ) __builtin_neon_vqshl_u_nv16qi ( ( int8x16_t


<s> return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return MI && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) .


<s> unsigned VisitedIndex = <NUM_LIT> ; while ( VisitedIndex < PHIs . size ( ) ) { MachineInstr * VisitedPHI = PHIs [ VisitedIndex ] ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = VisitedPHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register RegOp = VisitedPHI -> getOperand ( PHIOp ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( RegOp ) ) return


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , TargetMachine & TM , unsigned SyntaxVariant , const MCAsmInfo & MAI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( TM , MAI ) ; return <NUM_LIT>


<s> return ( __m128 ) __builtin_ia32_loadaps128_mask ( ( __v4sf * ) __P , (


<s> rtx t0 , t1 , x , merge , rmerge [ <NUM_LIT> ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & <NUM_LIT> ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( <NUM_LIT> , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge


<s> unsigned getRsaSize ( ) const { return <NUM_LIT>


<s> MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createMem ( MemoryKind MemKind , RegisterKind RegKind , unsigned Base , const MCExpr * Disp , unsigned Index , const MCExpr * LengthImm , unsigned LengthReg , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindMem , StartLoc , EndLoc ) ; Op -> Mem . MemKind = MemKind ; Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; if ( MemKind == BDLMem ) Op -> Mem . Length . Imm = LengthImm ; if ( MemKind == BDRMem ) Op -> Mem . Length . Reg = LengthReg ; return Op


<s> StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( *


<s> if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction (


<s> if ( DefRelocModel == Reloc :: Default ) setRelocationModel ( Reloc :: Static ) ; PM . add ( create<ISA_LIT>ObjectCodeEmitterPass ( *


<s> static void rs6000_xcoff_asm_globalize_label ( FILE * stream , const char * name ) { fputs ( GLOBAL_ASM_OP ,


<s> bool is<ISA_LIT>_64ExtendedReg ( const MCInst & MI ,


<s> static void AliasCandidates ( BasicBlock * Header , Instructions & Reads , Instructions & Writes ) { for ( auto & I


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned PredicationCode ; unsigned ProcessorIMod ; bool CarrySetting ; Head = SplitMnemonic ( Head , PredicationCode , CarrySetting , ProcessorIMod ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , NameLoc ) ) ; bool CanAcceptCarrySet , CanAcceptPredicationCode ; GetMnemonicAcceptInfo ( Head , CanAcceptCarrySet , CanAcceptPredicationCode ) ; if ( CanAcceptCarrySet ) { Operands . push_back ( <ISA_LIT>Operand :: CreateCCOut ( CarrySetting ? <STR_LIT> : <NUM_LIT> , NameLoc ) ) ; } else { } if ( CanAcceptPredicationCode ) { Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( <STR_LIT> ( PredicationCode ) , NameLoc ) ) ; } else { } if ( ProcessorIMod ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( ProcessorIMod , getContext ( ) ) , NameLoc , NameLoc ) ) ; } else { } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start +


<s> bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; break ; } case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Mode != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry


<s> uint64_t Offset = ( ( InstDesc . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( InstDesc . getOpcode ( )


<s> Chain = CWD . getValue ( <NUM_LIT> ) ; } SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; RetVal = DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ; return DAG . getMergeValues ( { RetVal , Chain } ,


<s> BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> )


<s> break ; case E_V8HImode : gen_load_even = gen_vec_setv8hi ; gen_interleave_first_low = gen_vec_interleave_lowv4si ; gen_interleave_second_low = gen_vec_interleave_lowv2di ; inner_mode = HImode ; first_imode = V4SImode ; second_imode = V2DImode ; third_imode = VOIDmode ; break ; case E_V16QImode : gen_load_even = gen_vec_setv16qi ; gen_interleave_first_low = gen_vec_interleave_lowv8hi ; gen_interleave_second_low = gen_vec_interleave_lowv4si ; inner_mode = QImode ; first_imode = V8HImode ; second_imode = V4SImode ; third_imode = V2DImode ; break ; default : gcc_unreachable ( ) ; } for ( i = <NUM_LIT> ; i < n ; i ++ ) { op = ops [ i + i ] ; if ( inner_mode == HFmode || inner_mode == BFmode ) { rtx even , odd ; machine_mode vec_mode = ( inner_mode == HFmode ) ? V8HFmode : V8BFmode ; op0 = gen_reg_rtx ( vec_mode ) ; even = lowpart_subreg ( vec_mode , force_reg ( inner_mode , op ) , inner_mode ) ; odd = lowpart_subreg ( vec_mode , force_reg ( inner_mode , ops [ i + i + <NUM_LIT> ] ) , inner_mode ) ; emit_insn ( gen_load_even ( op0 , even , odd ) ) ; } else { op0 = gen_reg_rtx ( SImode ) ; emit_move_insn ( op0 , gen_lowpart ( SImode , op ) ) ; op1 = gen_reg_rtx ( V4SImode ) ; op0 = gen_rtx_VEC_MERGE ( V4SImode , gen_rtx_VEC_DUPLICATE ( V4SImode , op0 ) , CONST0_RTX ( V4SImode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( op1 , op0 ) ) ; op0 = gen_reg_rtx ( mode ) ; emit_move_insn ( op0 , gen_lowpart ( mode , op1 ) ) ; emit_insn ( gen_load_even ( op0 , force_reg ( inner_mode , ops [ i + i + <NUM_LIT> ] ) , const1_rtx ) ) ; } ops [ i ] = gen_reg_rtx ( first_imode ) ; emit_move_insn ( ops [ i ] , gen_lowpart ( first_imode , op0 ) ) ; } for ( i = j = <NUM_LIT> ; i < n ; i += <NUM_LIT> , j ++ ) { op0 = gen_reg_rtx (


<s> isStoreToStackSlot ( const MachineInstr * MI , int


<s> for ( auto & MO : MI -> operands ( ) ) { const MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp .


<s> SDValue <ISA_LIT>TargetLowering :: joinRegisterPartsIntoValue ( SelectionDAG & DAG , const SDLoc & DL , const SDValue * Parts , unsigned NumParts , MVT PartVT , EVT ValueVT , Optional < CallingConv :: ID > CC ) const { assert ( ( ValueVT != <STR_LIT> || ( ( NumParts == <NUM_LIT> && PartVT == <STR_LIT> ) || ( NumParts == <NUM_LIT> && PartVT


<s> machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , res ,


<s> if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ; } return MaxAlign


<s> static unsigned computeBytesPoppedByCalleeForSRet ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , ImmutableCallSite * CS ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv

:: GHC || CC == CallingConv :: HiPE ) return <NUM_LIT> ;


<s> bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ; auto & CMovRC = * MRI -> getRegClass ( CMovI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CMovI . setDesc ( TII -> get ( <STR_LIT> ( Inverted ? <STR_LIT> : <STR_LIT> , TRI -> getRegSizeInBits ( CMovRC ) / <NUM_LIT> , ! CMovI . memoperands_empty ( ) ) ) ) ; FlagUse . setIsKill ( true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> uint64_t bit = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; bit |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t dst = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( bit ) ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , dst * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst .

addOperand ( MCOperand :: createImm ( dst ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoMt ( ) { OS << <STR_LIT>


<s> EmitFrames ( nullptr ) ; MCWinCOFFStreamer :: FinishImpl (


<s> unsigned <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type *


<s> const char * <ISA_LIT>_64Relocator :: getName ( Relocation :: Type pType ) const { return <ISA_LIT>_64ApplyFunctions [ pType ] .


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel


<s> __cpuid ( <NUM_LIT> , eax , ebx , ecx , edx ) ; level1 . sizekb = ( ecx >> <NUM_LIT> ) & <NUM_LIT> ; level1 . assoc = ( ecx >>


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget & STI ) { return llvm :: create<ISA_LIT>SEInstrInfo (


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input ,


<s> SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ; if ( ! Subtarget -> isLittle ( ) ) std ::


<s> } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) , ABI . StackAddrSpace ( ) ) ) ; if ( ABI . IsCheriPureCap ( ) ) { unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( CapType ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SV = SV -> stripPointerCasts ( ) ; assert ( isCheriPointer ( SV -> getType ( ) , & DAG . getDataLayout ( ) ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue CapAddr = Op . getOperand ( <NUM_LIT> ) ; FI = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , CapType ) ; return DAG . getStore ( Chain , DL , FI , CapAddr , MachinePointerInfo (


<s> size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size > <NUM_LIT> *


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( ) ; clearRegisterClasses ( ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( <ISA_LIT>16HardFloat ) set<ISA_LIT>16HardFloatLibCalls ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> static <STR_LIT> getPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> )


<s> if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef


<s> if ( Sym -> isVariable ( ) ) { auto V = Sym -> getVariableValue ( false ) ; return isa < <ISA_LIT>MCExpr > ( V ) ; } } return false ; } ; if ( ! Disp ) { if ( ! isAtMemOperand ( ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( Disp , EndLoc ) ) return true ; assert ( ! isa < <ISA_LIT>MCExpr > ( Disp ) && <STR_LIT> ) ; } else { Disp = MCConstantExpr :: create ( <NUM_LIT> , Parser . getContext ( ) ) ; } } if ( ! parseOptionalToken ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , StartLoc , EndLoc ) ) ; else Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , StartLoc , EndLoc ) ) ; return false ; } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc BaseLoc = getLexer ( ) . getLoc ( ) ; const MCExpr * E ; StringRef ErrMsg ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) && getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseExpression ( E , EndLoc ) || check ( ! isa < <ISA_LIT>MCExpr > ( E ) , BaseLoc , <STR_LIT> ) ) return true ; BaseReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return Error ( BaseLoc , <STR_LIT> , SMRange ( BaseLoc , EndLoc ) ) ; } if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( E , EndLoc ) ) return true ; if ( ! isa < <ISA_LIT>MCExpr > ( E ) ) { int64_t ScaleVal ; if ( ! E -> evaluateAsAbsolute ( ScaleVal , getStreamer ( ) . getAssemblerPtr ( ) ) ) return Error ( Loc , <STR_LIT> ) ; if ( ScaleVal != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } else { IndexReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> ) return Error


<s> getParser ( ) . parseStringToEndOfStatement ( ) ; return


<s> const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned BROpcode ; unsigned CC ; DebugLoc dl = MI -> getDebugLoc ( ) ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; } CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB =


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getCrossCopyRegClass (

const TargetRegisterClass * RC ) const {


<s> } else { switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = fastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc


<s> return __builtin_mve_vbrsrq_n_uv8hi ( __a ,


<s> bool Unpckl = true ; bool Unpckh = true ; bool UnpcklSwapped = true ; bool UnpckhSwapped = true ; int NumEltsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned LaneStart = ( i / NumEltsInLane ) * NumEltsInLane ; int LoPos = ( i % NumEltsInLane ) / <NUM_LIT> + LaneStart + NumElts * ( i % <NUM_LIT> ) ; int HiPos = LoPos + NumEltsInLane / <NUM_LIT> ; int LoPosSwapped = ( LoPos + NumElts ) % ( NumElts * <NUM_LIT> ) ; int HiPosSwapped = ( HiPos + NumElts ) % ( NumElts * <NUM_LIT> ) ; if ( Mask [ i ] ==


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask


<s> unsigned high_part_offset = subreg_highpart_offset ( SImode , DImode ) ; return simplify_gen_subreg ( SImode , reg , DImode , high_part_offset


<s> const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset


<s> return ( uint32x4_t ) __builtin_neon_vtstv4si ( ( int32x4_t ) __a , ( int32x4_t )


<s> OperandMatchResultTy parseADDR128 ( OperandVector &


<s> if ( Subtarget -> hasNEON ( ) ) { if ( VT == <STR_LIT> ) return <STR_LIT> ; else if ( VT == <STR_LIT> ) return <STR_LIT> ; } return TargetLowering :: getRegClassFor (


<s> DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst (


<s> const std :: vector < MachineBasicBlock * > & MBBs = I . MBBs ; for ( MachineBasicBlock * MBB : MBBs ) MBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } } for ( auto & MBB : MF


<s> if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( ) && ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>_64AsmBackend ( T , OSABI , CPU


<s> static rtx rx_expand_int_builtin_0_arg ( rtx target , rtx (


<s> return ( uint16x4_t ) __builtin_aarch64_sqmovunv4si (