<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return


<s> return __builtin_mve_vmulhq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> >


<s> O << <STR_LIT> ; printMemOffset ( MI , OpNo , O


<s> unsigned InitialOffset = <NUM_LIT> ; if ( Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) . isELFv2ABI ( ) && ! Fn . getRegInfo ( ) . use_empty ( <STR_LIT>


<s> static EVT getVectorTyFromPredicateVector ( EVT VT ) { switch ( VT . getSimpleVT (


<s> assert ( Kind == k_Barrier && <STR_LIT> ) ; return Barrier .


<s> if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = <NUM_LIT>


<s> translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_RM : return translateRM ( mcInst , operand , insn ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_I : return translateFPRegister ( mcInst , insn . opcodeModifier ) ; case ENCODING_Rv


<s> return Variant == <ISA_LIT>MCExpr :: VK_AARCH64_None || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOT || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC ; } return isLabel < <NUM_LIT> , <NUM_LIT> >


__I , int __J , int __K , int __L , int __M , int __N , int __O , int __P ) {


<s> unsigned getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const override { return


<s> return __builtin_aarch64_reduc_plus_scal_v2sf ( __a )


<s> unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> EmitInstruction ( Ret , getSubtargetInfo ( ) ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; recordSled ( CurSled , MI , SledKind


<s> inline SDValue getI8Imm ( uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_i ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB

, FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> void <ISA_LIT>TargetStreamer :: emitObjectArch ( unsigned Arch ) { llvm_unreachable ( <STR_LIT>


<s> const GlobalObject * GO = nullptr ; if ( MO . getType ( ) != MachineOperand :: MO_GlobalAddress || ! ( GO = dyn_cast < const GlobalObject > ( MO . getGlobal ( ) ) ) ) return <ISA_LIT>AsmPrinter :: getMCSymbolForTOCPseudoMO ( MO ) ; const auto * GV = dyn_cast < const GlobalVariable > ( GO ) ; if ( GV ) { ValidateGV ( GV ) ; } MCSymbolXCOFF * XSym = cast < MCSymbolXCOFF > ( getSymbol ( GO ) ) ; if ( GO -> isDeclaration ( ) ) { if ( ! XSym -> hasContainingCsect ( ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; XSym -> setStorageClass ( SC


<s> } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; if ( cast < AtomicSDNode > ( N ) -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Res = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Res ) , <NUM_LIT> ) ; Results . push_back ( Res ) ; break ; } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; SDValue Success = emitSETCC ( DAG , DL , Res . getValue ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; Success = DAG . getZExtOrTrunc ( Success , DL , N -> getValueType ( <NUM_LIT> ) ) ; Results . push_back ( lowerGR128ToI128 ( DAG , Res ) ) ; Results . push_back ( Success ) ; Results . push_back ( Res . getValue (


<s> unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getTarget ( ) . getRegisterInfo ( ) -> getAllocatableSet ( MF ) . test ( R ) && <STR_LIT> <STR_LIT> ) ; if ( ! MBB . isLiveIn ( R ) ) MBB .


<s> void <ISA_LIT>ELFStreamer :: emitCantUnwind ( )


<s> return ( __m64 ) __builtin_arm_wsubaddhx ( ( __v4hi ) a


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( CanTailCallOpt ) return lowerTailCall ( MIRBuilder , Info , OutArgs ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed ,


<s> int64_t ParamsSize ; if ( Parser . parseIdentifier ( ProcName ) ) return Parser . TokError ( <STR_LIT> ) ; if ( Parser . parseIntToken ( ParamsSize , <STR_LIT> ) ) return true ; if ( ! isUIntN ( <NUM_LIT> , ParamsSize ) ) return Parser . TokError ( <STR_LIT> ) ; if ( Parser . parseEOL ( <STR_LIT> ) )


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & TheTriple ) { if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( ) == Triple :: thumbeb ) ) IsLittleEndian = false ; AlignmentIsInBytes = false ; Data64bitsDirective =


<s> DebugLoc dl = MI . getDebugLoc ( ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAreaOffset ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerPrepareProbedAlloca ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; bool OffsetFitsMnemonic = ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ? isUInt < <NUM_LIT> > ( Offset ) : isInt < <NUM_LIT> > ( Offset ) ; if ( ! noImmForm && ( ( OffsetFitsMnemonic && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset


<s> unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; return getNumJTEntries ( JT , JTI ) * <NUM_LIT> + ( MI -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } default : return <NUM_LIT> ; } } } return


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_ARCH_ASE_M16 ; MCA . setELFHeaderEFlags ( Flags ) ; forbidModuleDirective ( )


<s> if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( CONST_INT_P ( x ) && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; vmode = aarch64_simd_container_mode ( imode , width


<s> SmallVector < MachineInstr * , <NUM_LIT> > Decs ; SmallVector < MachineInstr * , <NUM_LIT> > Ends ; for ( auto & I : MBB ) { if ( isLoopStart ( I ) ) Starts . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Decs . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Ends . push_back ( & I ) ; } if ( Starts . empty ( ) && Decs . empty ( ) && Ends . empty ( ) ) continue ; Changed = true ; for ( auto * Start : Starts ) { if ( Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( Start ) ; else Start -> eraseFromParent ( ) ; } for ( auto * Dec : Decs ) RevertLoopDec ( Dec ) ; for ( auto * End : Ends ) RevertLoopEnd (


<s> if ( ST -> hasMVEFloatOps ( ) ) continue ; break ; default : break ; } if ( IsMasked ( & I ) ) { auto * VecTy = getVectorType ( Int ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; continue ; } for ( const Use & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) ) return false ; } } } if ( !


<s> MachineInstr * NewInst = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opc ) ) . addDef ( Dest ) . add ( BaseAddr ) . addImm ( Offset ) . addUse ( TiedDest ) . addMemOperand ( * I . memoperands_begin ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * NewInst , TII , TRI , RBI ) ) return false ; return true


<s> static rtx gen_safe_SET64 ( rtx dest , HOST_WIDE_INT val


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; } } else if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT>


<s> bool hasFRInt3264 ( ) const { return HasFRInt3264


<s> const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList


<s> MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment =


<s> IRBuilder < > Builder { Ctx } ; auto InsertTrunc = [ & ] ( Value * V ) -> Instruction * { if ( ! isa < Instruction > ( V ) || ! isa < IntegerType > ( V -> getType ( ) ) ) return nullptr ; if ( ( ! Promoted . count ( V ) && ! NewInsts . count ( V ) ) || ! TruncTysMap . count ( V ) || Sources . count ( V ) ) return nullptr ; Type * TruncTy = TruncTysMap [ V ] ; if ( TruncTy == ExtTy ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * TruncTy << <STR_LIT> << * V << <STR_LIT> ) ; Builder . SetInsertPoint ( cast < Instruction > ( V ) ) ; auto * Trunc = dyn_cast < Instruction > ( Builder . CreateTrunc ( V , TruncTy ) ) ; if ( Trunc ) NewInsts . insert ( Trunc ) ; return Trunc ; } ; for ( auto I : Sinks ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; if ( auto * Call = dyn_cast < CallInst > ( I ) ) { for ( unsigned i = <NUM_LIT> ; i < Call -> getNumArgOperands ( ) ; ++ i ) { Value * Arg = Call -> getArgOperand ( i ) ; if ( Instruction * Trunc = InsertTrunc ( Arg ) ) { Trunc -> moveBefore ( Call ) ; Call -> setArgOperand ( i , Trunc ) ; } } continue ; } for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { if ( Instruction * Trunc = InsertTrunc ( I -> getOperand ( i ) ) ) { Trunc -> moveBefore ( I


<s> Op = DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Op ) ; SDValue TruncNode = DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode ) ; SDValue Delta = DAG . getConstant ( <NUM_LIT> - EltVT . getSizeInBits ( ) , dl


<s> return ( __m512i ) __builtin_ia32_pmovzxdq512_mask ( ( __v8si ) __X , (


<s> return __builtin_loongson_pandn_sd ( s , t )


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT>


<s> bool isMemDisp12Len4 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange ( Mem . Length . Imm ,


<s> static DecodeStatus DecodeQQQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQQQDecoderTable


__v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> static InstrUID decode ( OpcodeType type , InstructionContext insnContext , uint8_t opcode , uint8_t modRM ) { struct ModRMDecision * dec ; switch ( type ) { default : unreachable ( <STR_LIT> ) ; case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : unreachable ( <STR_LIT> ) ; case MODRM_ONEENTRY


<s> void addGR32orGR64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getReg


<s> if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getStoreSize ( ) ; Align Alignment ( Size ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI ,


<s> if ( J . isReg ( ) && J . isDef ( ) ) { MCRegAliasIterator AI ( J . getReg ( ) , TRI , true ) ; if ( J . isDead ( ) ) for ( ; AI . isValid ( ) ; ++ AI ) AvailableRegs . reset ( * AI ) ; else for ( ; AI . isValid ( ) ; ++ AI ) assert ( ! AvailableRegs [ * AI ] && <STR_LIT> ) ; } } } auto Ord = RCI . getOrder ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto Reg : Ord ) { if ( ! AvailableRegs [ Reg ] ) continue ; if ( C == getColor ( Reg ) ) return Reg ; } return - <NUM_LIT>


<s> if ( RelocOp -> isGlobal ( ) ) { FinalSize += sizeGlobalAddress ( false ) ; } else if ( RelocOp -> isCPI ( ) ) { FinalSize += sizeConstPoolAddress ( false ) ; } else if ( RelocOp -> isJTI (


<s> case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI


<s> static bool rs6000_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE


<s> int regalign = <NUM_LIT> ; gimple * stmt ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { t = rs6000_gimplify_va_arg ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( t ) ; } if ( ( ( TARGET_MACHO && rs6000_darwin64_abi ) || DEFAULT_ABI == ABI_ELFv2 || ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) ) && integer_zerop ( TYPE_SIZE ( type ) ) ) { unsigned HOST_WIDE_INT align , boundary ; tree valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = rs6000_function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; if ( boundary > align ) { tree t ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; t = fold_convert ( sizetype , valist_tmp ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_convert ( TREE_TYPE ( valist ) , fold_build2 ( BIT_AND_EXPR , sizetype , t , size_int ( - boundary ) ) ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; } valist_tmp = fold_convert ( build_pointer_type ( type ) , valist_tmp ) ; return build_va_arg_indirect_ref ( valist_tmp ) ; } if ( DEFAULT_ABI != ABI_V4 ) { if ( targetm . calls . split_complex_arg && TREE_CODE ( type ) == COMPLEX_TYPE ) { tree elem_type = TREE_TYPE ( type ) ; machine_mode elem_mode = TYPE_MODE ( elem_type ) ; int elem_size = GET_MODE_SIZE ( elem_mode ) ; if ( elem_size < UNITS_PER_WORD ) { tree real_part , imag_part ; gimple_seq post = NULL ; real_part = rs6000_gimplify_va_arg ( valist , elem_type , pre_p , & post ) ; real_part = get_initialized_tmp_var ( real_part , pre_p , & post ) ; gimple_seq_add_seq ( pre_p , post ) ; imag_part = rs6000_gimplify_va_arg ( valist , elem_type , pre_p , post_p ) ; return build2 ( COMPLEX_EXPR , type , real_part , imag_part ) ; } } return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ; f_ovf = DECL_CHAIN ( f_res )


<s> tree target = TREE_TYPE ( actual ) ; type_suffix_index type = find_type_suffix_for_scalar_type ( target ) ; if ( type == NUM_TYPE_SUFFIXES ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , build_qualified_type ( target , <NUM_LIT> ) ) ; return NUM_TYPE_SUFFIXES ; } unsigned int bits = type_suffixes [ type ] . element_bits ; if ( gather_scatter_p && bits != <NUM_LIT> && bits != <NUM_LIT> ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl ) ; return


<s> if ( isa < MCTargetExpr > ( getMemOff ( ) ) || ( isConstantMemOff ( ) && isIntN ( PtrBits , getConstantMemOff ( ) ) ) ) return true ; MCValue Res ; bool IsReloc = getMemOff ( ) -> evaluateAsRelocatable ( Res ,


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL

, <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ;


<s> void printMemOffs32 ( const MCInst * MI ,


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; uint64_t Features = STI . getFeatureBits ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; unsigned EFlags = <NUM_LIT> ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; if ( T . isArch64Bit ( ) ) { if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ABI2 ; else if ( Features & <STR_LIT> ) { EFlags |= ELF :: EF_MIPS_ABI_O32 ; EFlags |= ELF ::


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; if ( Mnemonic == <STR_LIT> ) Mnemonic = <STR_LIT> ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex


<s> if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) )


<s> std :: tie ( N , Opcode ) = llvm :: find_if ( IntrinsicMap , [ & ] ( auto P ) { return P . first == Intrinsic ; } ) -> second ; assert ( VT . getVectorElementCount ( ) . getKnownMinValue ( ) % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) . divideCoefficientBy ( N ) ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys , LoadOps ) ; SmallVector < SDValue , <NUM_LIT> > PseudoLoadOps ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) PseudoLoadOps

. push_back ( SDValue ( PseudoLoad . getNode ( ) , I ) ) ;


<s> RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ; return x


<s> bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp (


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_int4 ) ( a ) , ( vec_int4 ) (


<s> expand_float ( out , in , <NUM_LIT> ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , <NUM_LIT> , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_PLUS ( mode


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~


<s> inline SDValue getI32Imm ( unsigned Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm ,


<s> if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; Register regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * target = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned CmpOpc ; if ( isUInt < <NUM_LIT> > ( imm ) )


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> if ( STI . is64Bit ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( CatchRetTarget ) . addReg ( <NUM_LIT> ) ; } else


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget .


<s> MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle ( ) && <STR_LIT> ) ; Size += getInstSizeInBytes ( * I


<s> void <ISA_LIT>16InstrInfo :: adjustStackPtrBigUnrestricted ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { assert ( false


<s> rtx_insn * insn ; insn = mips_epilogue_emit_cfa_restores ( ) ; if ( reg != mips_epilogue . cfa_reg || offset != mips_epilogue . cfa_offset ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , plus_constant ( Pmode , reg , offset ) , REG_NOTES ( insn ) ) ; mips_epilogue . cfa_reg = reg


<s> BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else { unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || ( RI . canRealignStack ( MF ) && ! MFI . isFixedObjectIndex ( FrameIdx ) ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( sti ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( sti . getTargetTriple ( ) ) , sti . getCPU ( ) , Options ) ) { MCAsmParserExtension :: Initialize ( parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions >


<s> while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref


<s> return ( Kind != ScalarCondVectorVal


<s> StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) ,


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm ) ) <<


|| DisableTailPredication ) return false ;


<s> rtx mep_return_stackadj_rtx ( void ) { return gen_rtx_REG ( SImode , <NUM_LIT> )


<s> MCSymbol * Start = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD ,


<s> const MachineOperand & MO = MI -> getOperand ( I ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) RegDefs . insert ( Reg ) ; else if ( MO . isUse ( ) ) RegUses .


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ; return


<s> return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegExtendLarge : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed3SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1SImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm10 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT>


<s> } uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this


<s> if ( ! isPredicable ( * MI ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied (


<s> SDValue Ops [ ] = { Val . getOperand ( <NUM_LIT> ) , Val . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ) ; return true ; } return false


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb ) : MCELFStreamer ( Context , std

:: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , IsThumb ( IsThumb ) {


<s> poly8x16x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t )


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( true ) ) ; assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: create ( Get<ISA_LIT>GVSymbol ( GV , <STR_LIT> ) , ( Subtarget -> isTargetELF ( ) ?

MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : MCSymbolRefExpr :: VK_None ) , OutContext ) ;


<s> static DecodeStatus DecodeHWRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address ,


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5S2Operand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI ,


<s> void addHiImm16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( ConstExpr -> getValue ( ) >> <NUM_LIT> ) ) ; else if ( isa < <ISA_LIT>MCExpr > ( getImm ( ) ) ) { const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast <


<s> if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , TT ) ; if ( TT . isOSBinFormatXCOFF ( ) ) return new XCOFF<ISA_LIT>AsmBackend ( T , TT ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT )


<s> SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG )

, CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ;


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case

( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = mi -> getDesc ( ) . getNumDefs ( ) ; i != e ; ++ i ) { MachineOperand & mo = mi -> getOperand ( i ) ; if ( ! mo . isReg ( ) ) continue ; int rx = RegIndex ( mo . getReg


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> : <STR_LIT> ,

Memory . ShiftImm , Memory . ShiftType ) ;


<s> case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand :: MO_GlobalAddress : return LowerSymbolOperand ( MI , MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return LowerSymbolOperand ( MI , MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_MachineBasicBlock : return LowerSymbolOperand ( MI , MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand ( )


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; bool is64Bit = TT . getArch ( ) == Triple :: x86_64 ; if ( RM == Reloc :: Default ) { if ( TT . isOSDarwin ( ) ) { if ( is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: DynamicNoPIC ; } else if ( TT . isOSWindows ( ) && is64Bit ) RM = Reloc


<s> for ( unsigned i = <NUM_LIT> , e = Inst . getNumOperands ( ) ; i != e ; i ++ ) { if ( Desc . OpInfo [ i ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( i ) . getImm ( ) * <NUM_LIT> ; Target = Addr + Imm ; return true ; } } return


<s> ValidCopy = KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ; assert ( ValidCopy && <STR_LIT> ) ; ( void ) KnownValid ; return ValidCopy ; } ; if ( I . isCopy ( ) ) { if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; unsigned SubReg ; if ( getMinSizeForRegBank ( SrcRegBank ) > DstSize ) { const TargetRegisterClass * DstTempRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; getSubRegForClass ( DstRC , TRI , SubReg ) ; MachineIRBuilder MIB ( I ) ; auto Copy = MIB . buildCopy ( { DstTempRC } , { SrcReg } ) ; copySubReg ( I , MRI , RBI , Copy . getReg ( <NUM_LIT> ) , DstRC , SubReg ) ; } else if ( SrcSize > DstSize ) { const TargetRegisterClass * SubRegRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SubRegRC , TRI , SubReg ) ; copySubReg ( I , MRI , RBI , SrcReg , DstRC , SubReg ) ; } else if ( DstSize > SrcSize ) { const TargetRegisterClass * PromotionRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SrcRC , TRI , SubReg ) ; Register PromoteReg = MRI . createVirtualRegister ( PromotionRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , PromoteReg ) . addImm ( <NUM_LIT> ) . addUse ( SrcReg )


<s> return hasAnyDataBarrier ( ) && ( ! isThumb (


<s> SDLoc dl ( Op ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister


<s> BranchSize = BrOffset ; MaxLogAlign = std :: max ( MaxLogAlign , Src -> getLogAlignment ( ) ) ; int DestBlock = Dest -> getNumber ( ) ; BranchSize += BlockSizes [ DestBlock ] . first ; for ( unsigned i = DestBlock + <NUM_LIT> , e = Src -> getNumber ( ) ; i < e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxLogAlign = std :: max ( MaxLogAlign , Fn . getBlockNumbered ( i ) -> getLogAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( DestBlock >= FirstImpreciseBlock ) ; } else { unsigned StartBlock = Src -> getNumber ( ) ; BranchSize = BlockSizes [ StartBlock ] . first - BrOffset ; MaxLogAlign = std :: max ( MaxLogAlign , Dest -> getLogAlignment ( ) ) ; for ( unsigned i = StartBlock + <NUM_LIT> , e = Dest -> getNumber ( ) ; i != e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxLogAlign = std :: max ( MaxLogAlign , Fn . getBlockNumbered ( i ) -> getLogAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( Src -> getNumber ( ) >= FirstImpreciseBlock ) ; } if ( NeedExtraAdjustment ) BranchSize += ( <NUM_LIT> <<


<s> if ( ! STy || ( STy -> getNumElements ( ) == <NUM_LIT> ) ) return false ; auto ElemTy = dyn_cast < VectorType > ( STy -> getElementType ( <NUM_LIT> ) ) ; if ( ! ElemTy || ! ElemTy -> isScalable ( ) ) return false ; return std :: equal ( STy -> element_begin ( ) , STy -> element_end ( ) ,


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumRegs = sizeof ( RegList ) / sizeof ( RegList [ <NUM_LIT> ] ) ; SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ArgFlags . isSplit ( ) || ! PendingMembers . empty ( ) ) { PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; } if ( PendingMembers . empty ( ) ) { if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } return


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , vec_splat (

( vec_uchar16 ) ( si_from_uchar ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand ::


<s> } else { Result = ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ; } return APInt ( N


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI , bool isLittle ) : ELF<ISA_LIT>AsmBackend ( T , TT , _OSABI , isLittle ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( TT , <STR_LIT> , <STR_LIT> ) ) { assert ( isLittle && <STR_LIT> ) ; State . SaveCount = <NUM_LIT> ; State . I =


<s> static void aarch64_add_cfa_expression ( rtx_insn * insn , rtx reg , rtx base , poly_int64 offset ) { rtx mem = gen_frame_mem ( GET_MODE ( reg ) , plus_constant ( Pmode , base , offset


<s> static DecodeStatus DecodeThumbBROperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const


<s> static int ix86_avx_u128_mode_exit ( void ) { rtx reg = crtl -> return_rtx ; if ( reg && ix86_check_avx_upper_register ( reg ) ) return AVX_U128_DIRTY ; return ix86_avx_u128_mode_entry ( )


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC , Subtarget -> isLittle ( ) ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ) emitInstruction ( * I ++ , * MBB ) ; } } while ( MCE . finishFunction


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( <NUM_LIT> ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget


<s> case <STR_LIT> : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case <STR_LIT> : return PerformVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSignExtendCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : return CombineVLDDUP ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool isImmSExti64i32 ( ) const { if ( ! isImm (


<s> if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Op0 , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts = <NUM_LIT> ; SVT = <STR_LIT> ; } Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getBuildVector ( NewVT , dl , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) && Subtarget . hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector


<s> return ( uint64x2_t ) __builtin_neon_vbslv2di ( ( int64x2_t ) __a , ( int64x2_t )


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU )


<s> return Kind == k_Register && Reg . Kind == RegKind :: SVEPredicate && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg


<s> unsigned TargetMask = LKZ . getZExtValue ( ) ; unsigned InsertMask = RKZ . getZExtValue ( ) ; if ( ( TargetMask | InsertMask ) == <NUM_LIT> ) { unsigned Op0Opc = Op0 . getOpcode ( ) ; unsigned Op1Opc = Op1 . getOpcode ( ) ; unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1


<s> unsigned Size = TD . getTypePaddedSize ( CPs [ i ] . getType ( ) ) ; assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back (


<s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT (


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , IsLittleEndian


<s> insn = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == PARALLEL ) insn = XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( insn ) != SET ) return false ; dst = SET_DEST (


<s> if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return ; if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlign ( ) >= Align ( <NUM_LIT> ) ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! SavedRegs . test ( <STR_LIT> + NumSpills ) ) break ; if ( NumSpills < <NUM_LIT> )


<s> mips_multi_members . truncate ( <NUM_LIT>


<s> if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( !


<s> MCSymbol * Label = S . emitCFILabel ( ) ; CurFrame -> PrologEnd = Label ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End ,


<s> ) ; return false ; } } Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA -> getReachingDef ( VCTP , NumElements ) >= <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = InsertPt -> getParent ( ) ; if ( ! RDA -> isReachingDefLiveOut ( InsertPt , NumElements ) ) { if ( auto * ElemDef = RDA -> getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( IsSafeToMove < MachineBasicBlock :: reverse_iterator > ( ElemDef , InsertPt , RDA ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( InsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( IsSafeToMove < MachineBasicBlock :: iterator > ( InsertPt , ElemDef , RDA ) ) { InsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , InsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else return false ; } } auto CannotProvideElements = [ & RDA ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA -> getReachingDef ( & MBB -> back ( ) , NumElements ) >= <NUM_LIT> ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = MLI -> findLoopPreheader ( ML , true ) ; if ( ! MBB ) return false ; while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements )


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT = <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( ( VT == <STR_LIT> ) || VT . is64BitVector ( ) ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = &


<s> assert ( Scale > <NUM_LIT> && <STR_LIT> ) ; const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Node ) ; if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ; ScaledConstant /= Scale ; return ScaledConstant >= RangeMin && ScaledConstant <


<s> break ; case <STR_LIT> : Scale = <NUM_LIT> ; break ; } if ( ( V & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; return isUInt < <NUM_LIT> >


<s> SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfan ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhsmf ( a , b ) ; return __ev_mwsmian ( t , ( ( __ev64_s32__ )


<s> bool stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) ; bool dimode_p = GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; static char buf [ <NUM_LIT> ] ; const char * p ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( <STR_LIT> , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( MEM_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( GET_MODE ( operands [ <NUM_LIT> ] ) != TFmode ) ; if ( fisttp ) return <STR_LIT> ; strcpy ( buf , <STR_LIT> ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ; p = <STR_LIT> ; strcat ( buf , p + ! ( stack_top_dies || dimode_p ) ) ; output_asm_insn ( buf , operands


<s> else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( )

, TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeInt ( const Constant * C , MVT VT ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> )


<s> if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineInstr & MI : SinglePredMBB -> terminators ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; bool TakenBranch = ( MI . isBranch ( ) && ( TII -> getBranchInfo ( MI ) . isIndirect ( ) || TII -> getBranchInfo ( MI ) . getMBBTarget ( ) == MBB ) ) ; HazardRec -> emitInstruction ( & MI , TakenBranch ) ; if ( TakenBranch ) break


<s> static bool RetCC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { return RetCC_<ISA_LIT>_APCS_Custom_f64 ( ValNo , ValVT , LocVT , LocInfo ,


<s> call_target_mcop = MCOperand :: CreateImm ( call_target . getImm ( ) ) ; call_opcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : call_target_mcop = MCOperand :: CreateReg ( call_target . getReg ( ) ) ; call_opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst call_inst ; call_inst . setOpcode ( call_opcode ) ; call_inst . addOperand (


<s> } if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; return ; } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , MCFixupKind ( <STR_LIT> ) , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField ,


<s> int i = <NUM_LIT> ; while ( PredefinedFuncs [ i ] . Name ) { name_ = PredefinedFuncs [ i ]


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; ArgumentPopSize = StackAdjust . getImm


<s> return ; } const MCInstrDesc * MCID = & MI . getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI . setDesc ( * MCID ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI . hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI . RemoveOperand ( i ) ; break ; } } if ( !


<s> CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetMsa (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getAFGR64Reg


<s> if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) { bool IsError = parseSysAlias ( Head , NameLoc , Operands ) ; if ( IsError && getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) Parser . eatToEndOfStatement ( ) ; return IsError ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , true , SuffixLoc , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , NameLoc , NameLoc , getContext ( ) ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head ,


<s> if ( GET_MODE ( XEXP ( rvec [ <NUM_LIT> ] , <NUM_LIT> ) ) == mode

) return XEXP ( rvec [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> if ( parseVectorLane ( LaneKind , LaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( ! Spacing ) Spacing = <NUM_LIT> ; else if ( Spacing == <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc AfterMinusLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg > EndReg ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += EndReg - Reg ; Reg = EndReg ; continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { if ( ! Spacing ) Spacing = <NUM_LIT> ; else if ( Spacing == <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Reg = getDRegFromQReg ( Reg ) ; if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc LaneLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( LaneLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } continue ; } if ( ! Spacing ) Spacing = <NUM_LIT> + ( Reg == OldReg + <NUM_LIT> ) ; if ( Reg != OldReg + Spacing ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Count ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex


<s> unsigned Register = DPairDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register )


<s> DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg ( ScratchReg ) ; if ( LdI . IsPrePost ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ScratchReg ) ; BuildMI ( * MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , DL , TII -> get ( <STR_LIT> ) , LdI . BaseReg ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } for ( int I = <NUM_LIT> , E = OldCollisions . size ( ) ; I != E ; ++ I ) if ( OldCollisions [ I ] == & MI ) { std :: swap ( OldCollisions [ I ] , OldCollisions [ E - <NUM_LIT> ] ) ; OldCollisions . pop_back ( ) ; break ; } TagMap [ NewTag ] . push_back ( & MI ) ; ++ NumCollisionsAvoided ; Fixed = true ; Modified = true


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseGPROperand ( OperandVector & Operands ) { SMLoc StartLoc = getLoc ( ) ; unsigned RegNum ; OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) , EqTy ) ) ; return MatchOperand_Success ; } getParser ( ) . Lex ( ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > ExtOpnd ; Res = tryParseOptionalShiftExtend ( ExtOpnd ) ; if ( Res != MatchOperand_Success ) return Res ; auto Ext = static_cast < <ISA_LIT>Operand * > ( ExtOpnd . back ( ) . get ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , Ext -> getEndLoc ( ) , getContext ( ) , EqTy , Ext

-> getShiftExtendType ( ) , Ext -> getShiftExtendAmount ( ) , Ext -> hasShiftExtendAmount ( ) ) ) ;


<s> if ( ! supportsGather ( ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) return false ; if ( ST -> hasAVX512 ( ) && ( NumElts == <NUM_LIT> || ( NumElts == <NUM_LIT> && ! ST -> hasVLX


<s> bool inline noCost ( ) { return ( GroupingCost <= <NUM_LIT> && !


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; return false


<s> } assert ( OpVT . is128BitVector ( ) && OpVT . isInteger ( ) && OpVT != <STR_LIT> && <STR_LIT> ) ; if ( OpVT == <STR_LIT> ) return Op ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( OpVT , DAG . getNode ( <STR_LIT> ,


<s> if ( Subtarget -> hasSSE41 ( ) ) { unsigned ZMask = <NUM_LIT> ; if ( <STR_LIT> ( V1 . getNode ( ) ) ) { ZMask = <NUM_LIT> ^ ( <NUM_LIT> << V2Index ) ; } else if ( V1 . getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int M = Mask [ i ] ; if ( M >= <NUM_LIT> ) continue ; if ( M > - <NUM_LIT> ) { SDValue Input = V1 . getOperand ( M ) ; if ( Input . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Input ) ) { ZMask = <NUM_LIT> ; break ; } } ZMask |= <NUM_LIT> << i ; } } int InsertShuffleMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( i != V2Index && ( ZMask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) InsertShuffleMask [ i ] = Mask [ i ] ; if ( isNoopShuffleMask ( InsertShuffleMask ) ) { if ( ( ZMask | <NUM_LIT> << V2Index ) == <NUM_LIT> ) V1 = DAG . getUNDEF ( <STR_LIT> ) ; unsigned InsertPSMask = ( Mask [ V2Index ] - <NUM_LIT> ) << <NUM_LIT> | V2Index << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( InsertPSMask , <STR_LIT> ) ) ; } } int V2AdjIndex = V2Index ^ <NUM_LIT> ; if ( Mask [ V2AdjIndex ] == - <NUM_LIT> ) { if ( V2Index < <NUM_LIT> ) std :: swap ( LowV , HighV ) ; NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index


<s> <ISA_LIT>XPLINKFrameLowering :: <ISA_LIT>XPLINKFrameLowering ( ) : <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , false ) , RegSpillOffsets ( - <NUM_LIT> ) { RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( XPLINKSpillOffsetTable ) ; I != E ; ++ I )

RegSpillOffsets [ XPLINKSpillOffsetTable [ I ] . Reg ] = XPLINKSpillOffsetTable [ I ] . Offset ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } } } } if ( ! DCI . isBeforeLegalize ( ) && ! DCI . isBeforeLegalizeOps ( ) ) { ConstantSDNode * CmpAgainst = <NUM_LIT> ; if ( ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) && ( CmpAgainst = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) && dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) == <NUM_LIT> ) { if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( FalseOp ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( TrueOp )


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( <NUM_LIT> ) ,


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return true ; return TARGET_ELF && tls_referenced_p


<s> if ( ! NDS32_EXT_DSP_P ( ) ) return word_mode ; switch ( mode ) { case E_QImode : return V4QImode ; case


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>V9Target ( )


<s> void Thumb1FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; assert ( ( unsigned ) NumBytes >= ArgRegsSaveSize && <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ; } else


<s> if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , <STR_LIT> , & <STR_LIT> ) , & <STR_LIT> ) ; if ( ! R . second && StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { R . first


<s> if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead =


<s> int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( ! HARD_REGISTER_NUM_P ( regno0 ) || ! HARD_REGISTER_NUM_P ( regno1 ) ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return


<s> static const uint16_t CalleeSavedRegs [ ] = {


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) return true ; return


<s> Inst . addOperand ( MCOperand :: createImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Imm & <NUM_LIT> ) ) ; return


<s> else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) )


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = getDataLayout ( ) -> getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , Align ( isThumb ? <NUM_LIT> : <NUM_LIT> ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , LRSpilledForFarJump ( false ) , R3IsLiveIn ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , SpilledCSRegs ( MF . getTarget

( ) . getRegisterInfo ( ) -> getNumRegs ( ) ) , JumpTableUId ( <NUM_LIT> ) , ConstPoolEntryUId ( <NUM_LIT> ) {


<s> auto Ty = MRI . getType ( Reg ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; if ( Ty . getSizeInBits ( ) == TRI . getRegSizeInBits ( RC


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; AFI -> setVarArgsFrameIndex (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( TARGET_CLD || cfun -> machine -> func_type != TYPE_NORMAL ) return X86_DIRFLAG_ANY ; return X86_DIRFLAG_RESET


<s> bool isN0ZExt = isZeroExtended ( N0 , DAG ) ; bool isN1ZExt = isZeroExtended ( N1 , DAG ) ; if ( isN0ZExt && isN1ZExt ) NewOpc = <STR_LIT> ; else if ( isN1SExt || isN1ZExt ) { if ( isN1SExt && isAddSubSExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN1ZExt && isAddSubZExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN0ZExt && isAddSubZExt ( N1 , DAG ) ) { std :: swap ( N0 , N1 ) ; NewOpc = <STR_LIT> ; isMLA = true ; } } if ( ! NewOpc ) { if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; } } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 ; SDValue Op1 = SkipExtensionForVMULL ( N1 , DAG ) ; if ( ! isMLA


<s> bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = <NUM_LIT> ; else if ( TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode =


<s> void addArithmeticShifterOperands ( MCInst & Inst ,


<s> void addVectorRegLoOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> const unsigned SI = Use64BitRegs ? <STR_LIT> : <STR_LIT> ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , CX , Size , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , DI , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , SI , Src


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC0 = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> CC1 = cast < CondCodeSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ! Subtarget . hasAVX ( ) && ! ( cheap<ISA_LIT>FSETCC_SSE ( CC0 ) && cheap<ISA_LIT>FSETCC_SSE ( CC1 ) ) ) return SDValue ( ) ; unsigned NumElts = <NUM_LIT> / N00Type .


<s> unsigned QueryMemSize = Query . MMODescrs [ <NUM_LIT> ] . MemoryTy . getSizeInBits ( ) ; if ( ! isPowerOf2_64 ( QueryMemSize ) ) return false ; for ( auto & Val : SupportedValues ) { if ( Val . ValTy != Query . Types [ <NUM_LIT>


<s> HOST_WIDE_INT offset = <NUM_LIT> * UNITS_PER_WORD ; HOST_WIDE_INT size = SPARC_STACK_ALIGN ( offset + <NUM_LIT> * UNITS_PER_WORD ) ; rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , SPARC_STACK_BIAS + offset ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - size ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( slot , word_mode ,


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) return false ; Imm = M [ <NUM_LIT> ] ; unsigned ExpectedElt = Imm ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { ++ ExpectedElt ; if ( ExpectedElt == NumElts ) ExpectedElt


<s> if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister


<s> virtual bool gate ( function * ) { return ( TARGET_PCREL && TARGET_PCREL_OPT &&


<s> MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( IsVSReg ( DstMO . getReg ( ) , MRI ) && ! IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( <STR_LIT> ) ; SrcMO . setReg (


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , <NUM_LIT> ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , <NUM_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return