<s> if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) { SmallVector < SDValue > ConcatOps ; if ( VT . getSizeInBits ( ) > <NUM_LIT> || ! collectConcatOps ( In . getNode ( ) , ConcatOps ) ) return SDValue ( ) ; } unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL


<s> break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Value ) ; AddValueSymbols_ ( BE -> getLHS ( ) , Asm ) ; AddValueSymbols_ ( BE -> getRHS


<s> inline SDValue getImm ( const SDNode * Node , unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node ->


<s> addMSAFloatType ( <STR_LIT> Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; if ( Ty != <STR_LIT> ) { setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFP<ISA_LIT>v8Base ( ) && ! ST -> hasVFP2Base ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ST -> hasMVEIntegerOps ( ) ; case <STR_LIT> : case


<s> a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmpeq ( a


<s> DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL (


) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> for ( unsigned Reg : RegList ) Inst . addOperand


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case


<s> return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( )

&& Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) {


<s> AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage


<s> AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo > <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! AssemblerOptions . back ( ) -> setATReg ( AtRegNo ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false


<s> Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Index , CurDAG -> getTargetConstant


<s> const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineInstr * AMI = ASU -> getInstr ( ) ; if ( ! AMI || AMI -> isPseudo ( ) || AMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , nullptr , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , nullptr ) ) ) return false ; for ( SDep & BDep : APreds ) { if ( BDep . isWeak ( ) ) continue ; SUnit * BSU = BDep . getSUnit ( ) ; const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( !

Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ;


<s> } if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPROddRegisterClass ( Inst , RdaHi , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPROddRegisterClass ( Inst , RdaHi , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Saturate = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Saturate ) ) ; } return


<s> if ( OpcA == OpcB ) return true ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned )


<s> static __inline qword si_rotqmbii ( qword a , int count ) { return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 )

( si_from_int ( <NUM_LIT> - count ) ) , <NUM_LIT> ) ) ) ) ;


<s> void printU6ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { unsigned char value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> Condition = <STR_LIT> ( ExtraCC ) ; OutCC = <STR_LIT> ( OutCC ) ; } } if ( ! CCOp . getNode ( ) ) return emitComparison ( LHS , RHS , CC , DL , DAG ) ; SDValue ConditionOp = DAG . getConstant ( Condition , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC ) ; unsigned NZCV = <STR_LIT> ( InvOutCC ) ; return emitConditionalComparison ( LHS , RHS , CC , CCOp , ConditionOp , NZCV , DL , DAG ) ; } SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool isOr = Val -> getOpcode ( ) == <STR_LIT> ; assert ( ( isOr || Val -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Negate ^= isOr ; <STR_LIT> RHSCC ; SDValue CmpR = emitConjunctionDisjunctionTree ( DAG , RHS , RHSCC , isOr , CCOp , Condition ) ; SDValue CmpL = emitConjunctionDisjunctionTree ( DAG , LHS , OutCC , isOr


<s> } } } else { for ( i = low ; i < high ; i += <NUM_LIT> ) { bool reg0 = regs_ever_live [ i ] && ! call_used_regs [ i ] ; bool reg1 = regs_ever_live [ i + <NUM_LIT> ] && ! call_used_regs [ i + <NUM_LIT> ] ; enum machine_mode mode ; int regno ; if ( reg0 && reg1 ) { mode = i < <NUM_LIT> ? DImode : DFmode ; regno = i ; } else if ( reg0 ) { mode = i < <NUM_LIT> ? SImode : SFmode ; regno = i ; } else if ( reg1 ) { mode = i < <NUM_LIT> ? SImode : SFmode ; regno = i + <NUM_LIT>


<s> return ( int32x4_t ) __builtin_neon_vqshlsv4si ( __a ,


<s> bool <ISA_LIT>AsmParser :: expandInstruction ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return expandLoadImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadImm ( Inst , false , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandBranchImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> ExtraG0 = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . isV9 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { subRegIdx = DFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . isV9 ( ) ) { if ( Subtarget . hasHardQuad ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { subRegIdx = QFP_DFP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else { subRegIdx = QFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( numSubRegs == <NUM_LIT> || subRegIdx == nullptr || movOpc == <NUM_LIT> ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * MovMI = nullptr ; for ( unsigned i = <NUM_LIT> ; i != numSubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , subRegIdx [ i ] ) ; unsigned Src = TRI -> getSubReg ( SrcReg , subRegIdx [ i ] ) ; assert ( Dst && Src && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( movOpc ) , Dst ) ; if ( ExtraG0 ) MIB .


<s> rtx first_push ; gcc_assert ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) ; last_reg = ( INTVAL ( operands [ <NUM_LIT> ] ) / UNITS_PER_WORD ) - <NUM_LIT> ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == PARALLEL ) ; first_push = XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( SET_P ( first_push ) ) ; first_push = SET_SRC ( first_push ) ; gcc_assert ( REG_P ( first_push )


<s> emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; unsigned regFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( FrameLabel , regFP ) ) ; MMI . addFrameInst ( MCCFIInstruction ::


<s> rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 = GET_CODE ( xplus0 ) ; enum rtx_code code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; code0 = GET_CODE ( xplus0 ) ; code1 = GET_CODE


<s> if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ; return tls_get_addr_libfunc


<s> if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) ||

( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ;


<s> return APIntToHexString ( CI -> getValue ( ) ) ; } else { unsigned NumElements ; if ( isa < VectorType > ( Ty ) ) NumElements = Ty -> getVectorNumElements ( ) ; else NumElements = Ty -> getArrayNumElements ( ) ; std :: string HexString ; for ( int I = NumElements - <NUM_LIT> , E = - <NUM_LIT> ; I != E ; -- I ) HexString += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ; return HexString


<s> uint64_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = <NUM_LIT> ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) , false , false , <NUM_LIT> ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue NarrowFP = DAG . getNode ( <STR_LIT> , DL , VT , WideFP . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Ops [ ] = { NarrowFP , WideFP . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return


<s> static bool csky_can_eliminate ( const int from ATTRIBUTE_UNUSED ,


<s> if ( Subtarget . isDarwinABI ( ) ) return Subtarget

. is<ISA_LIT>64 ( ) ? CSR_Darwin64_SaveList :


<s> static bool hasFallthrough ( const MachineBasicBlock & MBB ) { MachineFunction :: const_iterator MBBI (


<s> BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size = <NUM_LIT> ; BBI . Unalign = <NUM_LIT> ; BBI . PostAlign = <NUM_LIT> ; for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siti ( (


<s> if ( TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p ( x ) ) return false ; if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && ( NDS32_SYMBOL_REF_RODATA_P ( x ) || CONSTANT_POOL_ADDRESS_P ( x ) ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; case CONST : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( x , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == SYMBOL_REF && CONST_INT_P ( op1 ) ) { if ( flag_pic || SYMBOL_REF_TLS_MODEL ( op0 ) ) return false ; if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && NDS32_SYMBOL_REF_RODATA_P ( op0 ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; } } return false ; case POST_MODIFY : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( x , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op , <NUM_LIT> ) ; if ( nds32_address_register_rtx_p ( op0 , strict ) && nds32_legitimate_index_p ( mode , op1 , strict ) ) return true ; else return false ; } return false ; case POST_INC : case POST_DEC : if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else return false ; case PLUS : if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else return false ; case LO_SUM : { rtx sym = NULL_RTX ; if ( flag_pic )


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand ::


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn


<s> if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT (


<s> static SDValue lowerV8I64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_pshufhw512_mask ( ( __v32hi ) __A , __imm , ( __v32hi ) _mm512_setzero_hi ( ) , ( __mmask32 )


( Mask [ i ] >= <NUM_LIT> && Mask [ i ] < Size ) {


<s> SDValue In2 = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = In2 . getValueType ( ) ; if ( VT . isScalableVector ( ) ) { if ( VT != SrcVT ) return SDValue ( ) ; EVT IntVT = getPackedSVEVectorVT ( VT . getVectorElementType ( ) . changeTypeToInteger ( ) ) ; unsigned NumBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstant ( APInt :: getSignMask ( NumBits ) , DL , IntVT ) ; SDValue InvSignMask = DAG . getNOT ( DL , SignMask , IntVT ) ; SDValue Sign = DAG . getNode ( <STR_LIT> , DL , IntVT , SignMask , getSVESafeBitCast ( IntVT , In2 , DAG ) ) ; SDValue Magnitude = DAG . getNode ( <STR_LIT> , DL , IntVT , InvSignMask , getSVESafeBitCast ( IntVT , In1 , DAG ) ) ; SDValue IntResult = DAG . getNode ( <STR_LIT> , DL , IntVT , Sign , Magnitude ) ; return getSVESafeBitCast ( VT , IntResult , DAG ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; if ( SrcVT . bitsLT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 ) ; else if ( SrcVT . bitsGT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; EVT VecVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; auto setVecVal = [ & ] ( int


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) res . as_char [ i ] = ( ( unsigned char ) m1 . as_char [ i ] > ( unsigned char ) m2 . as_char [ i ] ) ? m1 .


<s> } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockAlignment = NextBlock -> getAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size ; if ( CPEEnd > NextBlockOffset ) { Growth = CPEEnd - NextBlockOffset ; Growth += OffsetToAlignment ( CPEEnd , <NUM_LIT> << NextBlockAlignment ) ; if ( CPEOffset < UserOffset ) UserOffset += Growth ; } else Growth


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <=


<s> if ( isAM2 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isAM5 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isT2i32Load ( Opcode ) || isT2i32Store ( Opcode ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; bool isLd = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isLd && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base ) return false ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; bool DoMerge = false ; <STR_LIT> AddSub = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode ) ; MBB . erase ( PrevMBBI ) ; } } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode (


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; bool hasFramePointer = hasFP ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; if ( RI -> needsStackRealignment ( MF ) && MFI . hasVarSizedObjects ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( hasFramePointer ) StackSize ++ ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , -


<s> return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : return setRTypes ( ELF :: R_MIPS_GPREL16 , ELF :: R_MIPS_SUB , ELF :: R_MIPS_HI16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MICROMIPS_GPREL16 , ELF :: R_MICROMIPS_SUB , ELF :: R_MICROMIPS_HI16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MIPS_GPREL16 , ELF :: R_MIPS_SUB , ELF :: R_MIPS_LO16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MICROMIPS_GPREL16 , ELF :: R_MICROMIPS_SUB , ELF :: R_MICROMIPS_LO16 ) ; case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_SUB ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_DISP ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_TPREL_LO16 ; case


<s> if ( ! AddOp1 ) return SDValue ( ) ; bool HasLEAPotential = false ; for ( auto * User : Sext -> uses ( ) ) { if ( User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> ) { HasLEAPotential = true ; break ; } } if ( ! HasLEAPotential ) return SDValue ( ) ; int64_t AddConstant = AddOp1 -> getSExtValue ( ) ; SDValue AddOp0 = Add . getOperand ( <NUM_LIT> ) ; SDValue NewSext = DAG . getNode ( <STR_LIT> , SDLoc ( Sext ) , VT , AddOp0 ) ; SDValue NewConstant = DAG . getConstant ( AddConstant , SDLoc ( Add ) , VT ) ; SDNodeFlags


<s> if ( ! STI . getTargetTriple ( ) . isOSBinFormatCOFF ( ) ) return nullptr ; return new <ISA_LIT>WinCOFFTargetStreamer (


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / <NUM_LIT> ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , Vec -> op_begin ( ) + NormalizedIdxVal , ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant (


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>_64Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR


<s> assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( <NUM_LIT> ) ; unsigned VR = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> )


<s> unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; MCA . setELFHeaderEFlags (


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) { DebugLoc dl = N -> getDebugLoc ( ) ; MVT DstVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue I = DAG . getNode ( <STR_LIT> , dl , DstVT , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , I ) ; } return SDValue


<s> void DecodeEXTRQIMask ( int Len , int Idx , SmallVectorImpl < int > & ShuffleMask ) { Len &= <NUM_LIT> ; Idx &= <NUM_LIT> ; if ( <NUM_LIT> != ( Len % <NUM_LIT> ) || <NUM_LIT> != ( Idx % <NUM_LIT> ) ) return ; if ( Len == <NUM_LIT> ) Len = <NUM_LIT> ; if ( ( Len + Idx ) > <NUM_LIT> ) { ShuffleMask . append ( <NUM_LIT> , SM_SentinelUndef


<s> bool isS16Imm ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base


<s> SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root ,


<s> return getAddr < JumpTableSDNode , false > (


<s> return false ; } if ( valid_perm_using_mode_p ( V16SImode , d ) ) vmode = V16SImode ; } else if ( d -> vmode == V16SFmode ) vmode = V16SImode ; if ( vmode == V64QImode ) { for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( ( d -> perm [ i ] ^ i ) & ( nelt / <NUM_LIT> ) ) return false ; } } else return false ; } if ( d -> testing_p ) return true ; if ( vmode == V8SImode ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = GEN_INT ( ( d -> perm [ i * nelt / <NUM_LIT> ] * <NUM_LIT> / nelt ) & <NUM_LIT> ) ; else if ( vmode == V16SImode ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = GEN_INT ( ( d -> perm [ i * nelt / <NUM_LIT> ] * <NUM_LIT> / nelt ) & <NUM_LIT> ) ; else { eltsz = GET_MODE_UNIT_SIZE ( d -> vmode ) ; if ( ! d -> one_operand_p ) mask = <NUM_LIT> * nelt - <NUM_LIT> ; else if ( vmode == V16QImode ) mask = nelt - <NUM_LIT> ; else if ( vmode == V64QImode ) mask = nelt / <NUM_LIT> - <NUM_LIT> ; else mask = nelt / <NUM_LIT> - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & mask ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) rperm [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; } } vperm = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( GET_MODE_NUNITS ( vmode ) , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; target = d -> target ; if ( d -> vmode != vmode ) target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , d -> op0 ) ; if ( d -> one_operand_p ) { if ( vmode == V16QImode ) emit_insn ( gen_ssse3_pshufbv16qi3 ( target , op0 , vperm ) ) ; else if ( vmode == V32QImode ) emit_insn ( gen_avx2_pshufbv32qi3 ( target , op0 , vperm ) ) ; else if ( vmode == V64QImode ) emit_insn ( gen_avx512bw_pshufbv64qi3 ( target , op0 , vperm ) ) ; else if ( vmode == V8SFmode ) emit_insn ( gen_avx2_permvarv8sf (


<s> unsigned HOST_WIDE_INT df_mantissa = value & ( ( HOST_WIDE_INT_1U << <NUM_LIT> ) - HOST_WIDE_INT_1U ) ; if ( df_exponent == <NUM_LIT> && df_mantissa != <NUM_LIT> ) return <NUM_LIT> ; if ( df_exponent == <NUM_LIT> && df_mantissa != <NUM_LIT> ) return <NUM_LIT> ; } long df_words [ <NUM_LIT> ] = { vsx_const -> words [ <NUM_LIT> ] , vsx_const -> words [ <NUM_LIT> ] } ; if ( ! BYTES_BIG_ENDIAN ) std :: swap ( df_words [ <NUM_LIT> ] , df_words [ <NUM_LIT> ] ) ; REAL_VALUE_TYPE rv_type ; real_from_target ( & rv_type , df_words , DFmode ) ; const REAL_VALUE_TYPE * rv = & rv_type ; if ( ! exact_real_truncate ( SFmode , rv ) ) return <NUM_LIT> ; long sf_value


<s> bool always_inline = ( DECL_DISREGARD_INLINE_LIMITS ( callee ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( callee ) ) ) ; if ( TARGET_GENERAL_REGS_ONLY_P ( callee_opts -> x_ix86_target_flags ) ) always_inline_safe_mask |= MASK_80387 ; cgraph_node * callee_node = cgraph_node :: get ( callee ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( ( ! always_inline && caller_opts -> x_target_flags != callee_opts -> x_target_flags ) || ( caller_opts -> x_target_flags & ~ always_inline_safe_mask ) != ( callee_opts -> x_target_flags & ~ always_inline_safe_mask ) ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( ! always_inline && caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath && ( ! ipa_fn_summaries || ipa_fn_summaries -> get ( callee_node ) == NULL || ipa_fn_summaries -> get ( callee_node ) -> fp_expressions ) ) ret = false ; else if ( ! always_inline && caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; return ret


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( )


<s> bool shouldRestoreSPFromFP ( ) const { return


<s> O << <ISA_LIT>InstPrinter :: getRegisterName ( * SR ) << ( Lane0 ? <STR_LIT> : <STR_LIT> ) ; return false ; } } return true ; case 'B' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ~ ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ( MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ) ; return false ; case 'M' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned RegBegin = MO . getReg ( ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( RegBegin ) ; unsigned RegOps = OpNum + <NUM_LIT> ; while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; } O << <STR_LIT> ; return false ; } case 'R' : case 'Q' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = ExtraCode [ <NUM_LIT> ] == 'Q' ? OpNum : OpNum + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } case 'e'


<s> unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; updateValueMap ( I , Result ) ; return


<s> EVT InSVT = InVT . getScalarType ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || ( InSVT == <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT>

) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ;


<s> if ( MO . isKill ( ) && ActiveChains . find ( MO . getReg ( ) ) != ActiveChains . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( MO . getReg ( ) ) << <STR_LIT> ) ; ActiveChains [ MO . getReg ( ) ] -> setKill ( MI , Idx ,


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; align *= <NUM_LIT> * size ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } return S


<s> bool isVecListFourQHWordIndexed ( ) const { if ( ! isDoubleSpacedVectorIndexed (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return


<s> unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , FSetCC ) ; return FSetCC ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast (


<s> if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) ) return true ; } } unsigned Opcode = candidate -> getOpcode ( ) ; if ( Subtarget -> insertNOPLoad ( ) && Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) return true ; if ( Subtarget -> fixAllFDIVSQRT ( ) && Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) return true ; return


<s> auto TestI = BuildMI ( MBB , Pos , Loc , TII -> get ( <STR_LIT> )

) . addReg ( Reg ) . addImm ( - <NUM_LIT> ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } if ( VT != <STR_LIT> ) { SDValue Hi16 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Hi16 ) ; } else { X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; } SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT>


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) std :: swap ( op0 , op1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target


<s> } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( ! STI . isTargetWin32


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( false && <STR_LIT>


<s> CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return


<s> return ! <ISA_LIT>ScalarSSEf64 || VT


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister


<s> if ( Val & ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler ::


<s> ASM_OUTPUT_LABEL ( file , XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( regs_ever_live [ <NUM_LIT> ] ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ; if ( gr_saved ) fprintf ( file , <STR_LIT> , gr_saved + <NUM_LIT> ) ; if ( fr_saved ) fprintf ( file , <STR_LIT> , fr_saved + <NUM_LIT> ) ; fputs ( <STR_LIT> , file


<s> FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT>

) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ;


<s> } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN ,


<s> enum machine_mode mode ; mode = insn_data [ icode ] . operand [ op ] . mode ; if ( target == <NUM_LIT> || ! insn_data [ icode ] . operand [ op ] . predicate ( target

, mode ) ) target = gen_reg_rtx ( mode ) ;


<s> Range = <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Value += Writer -> getSectionAddress ( & SymSD ) ; Value -= Writer -> getSectionAddress ( Fragment


<s> FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF


<s> SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , <STR_LIT> ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , VT ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Cond , IsSRA ? Ext : DAG . getConstant ( <NUM_LIT> , VT ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] =


<s> MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( i == <STR_LIT> ) MIB . addDisp ( MO , LabelOffset ) ; else if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOs ) ; BuildMI ( * thisMBB , MI , DL , TII -> get ( IJmpOpc ) ) .


<s> tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( func ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; int flags = callee_opts


<s> } } } for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } if ( ! ( Start && Dec && End ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! BBUtils -> isBBInRange ( End , ML ->


<s> if ( FrameIdx < <NUM_LIT> ) return ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; if ( Align >= <NUM_LIT> ) return ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasNonRISpills (


<s> unsigned Odd ; switch ( Hint . first ) { case <STR_LIT> : Odd = <NUM_LIT> ; break ; case <STR_LIT> : Odd = <NUM_LIT> ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == <NUM_LIT> ) return false ; unsigned PairedPhys = <NUM_LIT> ; if ( Register :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false


<s> static void add_libcall ( libcall_table_type * htab


<s> bool HighFPRsUsed = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( HighFPRs ) ; i != e ; ++ i ) HighFPRsUsed |= MRI . isPhysRegUsed ( HighFPRs [ i ] ) ; if ( FFI -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; if ( HighFPRsUsed || FFI -> hasCalls ( ) || FFI -> getObjectIndexEnd ( ) != <NUM_LIT> || FFI -> hasVarSizedObjects ( ) ) MRI


<s> return __builtin_mve_vcmphiq_v16qi ( __a ,


<s> for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , srcmem ) ; } } else { rtx tmpreg [ <NUM_LIT> ] ; gcc_assert ( unroll <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { tmpreg [ i ] = gen_reg_rtx ( mode ) ; if ( i ) srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( tmpreg [ i ] , srcmem ) ; } for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , tmpreg [ i ] ) ; } } } else for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , value ) ; } tmp = expand_simple_binop ( iter_mode , PLUS , iter , piece_size , iter , true , OPTAB_LIB_WIDEN ) ; if ( tmp != iter ) emit_move_insn ( iter , tmp ) ; emit_cmp_and_jump_insns ( iter , size , LT , NULL_RTX ,


<s> DiagnosticPredicate isUImmScaled ( ) const { return isImmScaled < Bits , Scale > ( false


<s> void setMemOffset ( const MCExpr * off ) { assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ; Mem . Offset =


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FI = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain


<s> case IES_RSHIFT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State = IES_LPAREN ; IC . pushOperator ( IC_LPAREN ) ; break ; } PrevState = CurrState


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_i32scatter_ps ( void *


<s> static unsigned getOpcodeForFMAIntrinsic ( unsigned IntNo ) { switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; unsigned BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg


<s> return FixedVectorType :: get ( ArgTy -> getScalarType ( ) , cast < VectorType > ( DstTy ) -> getNumElements ( ) ) ; } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction :: Sub : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second .


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return createWinCOFFStreamer ( Ctx , MAB , * _Emitter , _OS , RelaxAll ) ; return createELFStreamer ( Ctx , MAB , _OS ,


<s> return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF ,


<s> if ( isGPRAsmReg ( ) && RegIdx . Index ==


<s> unsigned PredOpcode = Signed ? <STR_LIT> : <STR_LIT> ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode , true ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT FixedWidenedVT = HalfVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; EVT ScalableWidenedVT = getContainerForFixedLengthVector ( DAG , FixedWidenedVT ) ; EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Div ) ; } SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ?


<s> inline unsigned getPredicateHint ( Predicate Opcode


<s> int MaxUInt = ( <NUM_LIT> << width ) ; if ( ExtType == <STR_LIT> ) AddConstant -= ( <NUM_LIT> << ( width - <NUM_LIT> ) ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant == <NUM_LIT> ) || ( CompConstant == MaxUInt - <NUM_LIT> && AddConstant < <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant < AddConstant ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant == <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant <= <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant <= AddConstant ) ) return true ; break ; case <STR_LIT> : case


<s> if ( ! insn . spec ) { debug ( <STR_LIT> ) ; return true ; } mcInst . setOpcode ( insn . instructionID ) ; int index ; insn . numImmediatesTranslated = <NUM_LIT> ; for ( index = <NUM_LIT> ; index < <ISA_LIT>_MAX_OPERANDS ; ++ index ) { if ( insn . operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . operands [ index ] , insn , Dis ) ) { return true ; } } } return


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> Tok . IsSuffix = IsSuffix ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; unsigned ZMask = Imm & <NUM_LIT> ; unsigned CountD = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned CountS = ( Imm >> <NUM_LIT> ) &


<s> RegNo = <STR_LIT> ; RegKind = <STR_LIT> ; return true ; } if ( name . equals ( <STR_LIT> ) ) { RegNo = <STR_LIT> ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = <STR_LIT> + intVal ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true


<s> return ; } Len /= <NUM_LIT> ; Idx /= <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Idx ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> llvm_unreachable ( <STR_LIT> ) ; break ; CASE_VSHUF_COMMON ( <NUM_LIT> , Z , m ) HasMemOp = true ; CASE_VSHUF_COMMON ( <NUM_LIT> , Z , r ) VT = <STR_LIT> ; break ; CASE_VSHUF_COMMON ( <NUM_LIT> , Z256 , m ) HasMemOp = true ; CASE_VSHUF_COMMON ( <NUM_LIT> , Z256 , r ) VT = <STR_LIT> ; break ; CASE_VSHUF_COMMON ( <NUM_LIT> , Z , m ) HasMemOp


<s> unsigned NumElts = VecTy -> getVectorNumElements ( ) ; auto * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace


<s> MCFragment * findAssociatedFragment ( ) const


<s> XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * <NUM_LIT> ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) =


<s> assert ( VT . getVectorElementCount ( ) . getKnownMinValue ( ) % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / N ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys , LoadOps ) ; SmallVector < SDValue , <NUM_LIT> > PseudoLoadOps ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) PseudoLoadOps . push_back ( SDValue (


<s> static void CalculateTailCallArgDest ( SelectionDAG & DAG , MachineFunction & MF , bool is<ISA_LIT>64 , SDValue Arg , int SPDiff , unsigned ArgOffset , SmallVectorImpl < TailCallArgumentInfo > & TailCallArguments ) { int Offset = ArgOffset + SPDiff ; uint32_t OpSize = ( Arg . getValueType ( ) . getSizeInBits (


<s> return ( int64x1_t ) __builtin_neon_vrshlsdi ( __a ,


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; for ( size_t i = <NUM_LIT> ; i < RegList . size ( ) ; ++ i ) { unsigned Reg = MRI -> getEncodingValue ( RegList [ i ] ) ; assert ( Reg < ( IsVector ? <NUM_LIT> : <NUM_LIT> ) && <STR_LIT> ) ; unsigned Bit = ( <NUM_LIT> << Reg ) ; if ( ( Mask & Bit ) == <NUM_LIT> ) { Mask |= Bit ; ++ Count ; } } SPOffset -= Count * ( IsVector ? <NUM_LIT>


<s> return gen_rtx_REG ( Pmode , CRX_STRUCT_VALUE_REGNUM


<s> else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode !=


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFPOStackAlloc ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; int64_t


<s> MachineBasicBlock :: iterator I = UserMI ; ++ I ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) , PredReg = <NUM_LIT> ; I -> getOpcode ( ) != <STR_LIT> && getITInstrPredicate ( * I , PredReg ) != <STR_LIT> ; Offset += TII -> getInstSizeInBytes ( * I ) , I = std :: next ( I ) ) { BaseInsertOffset = std :: max ( BaseInsertOffset , Offset + TII -> getInstSizeInBytes ( * I ) + <NUM_LIT> ) ; assert ( I != UserMBB -> end ( ) && <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = & * MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getITInstrPredicate ( * MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; } if ( STI -> isTargetWindows ( ) && isThumb && MI -> getOpcode ( ) == <STR_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> )


<s> if ( EltTy -> isIntegerTy ( <NUM_LIT> ) || EltTy -> isIntegerTy ( <NUM_LIT> ) ) return HasBW ; return false ; } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor ,


<s> OpIdx = <NUM_LIT> ; unsigned Rn = decodeNEONRn ( insn ) ; unsigned Len = slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRd ( insn ) ) ) ) ; ++ OpIdx ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } for ( unsigned i = <NUM_LIT> ; i < Len ; ++ i ) { assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn +


<s> int <ISA_LIT>Subtarget :: getAdjustedFrameSize ( int frameSize ) const { frameSize += <NUM_LIT> ; frameSize = alignTo ( frameSize , <NUM_LIT> ) ; return frameSize


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return


<s> unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg


<s> bool arm_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS


<s> Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ; return


<s> bool HasR6 = ABI . IsN64 ( ) ? STI -> has<ISA_LIT>64r6 ( ) : STI -> has<ISA_LIT>32r6 ( ) ; bool AddImm = HasR6 && ! STI -> useIndirectJumpsHazard ( ) ; unsigned JR = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned JIC = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned JR_HB = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned JR_HB_R6 = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned JumpOp ; if ( STI -> useIndirectJumpsHazard ( ) ) JumpOp = HasR6 ? JR_HB_R6 : JR_HB ; else JumpOp = HasR6 ? JIC


<s> dc = vec_sel ( vec_sub ( bc , ac ) , vec_sub ( ac , bc ) , vec_cmpgt ( ac , bc ) ) ; return ( ( qword )


<s> if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex ( ) ; return MFI . isFixedObjectIndex ( Idx ) && MFI


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ) ) return true ; } else if ( MO . isRegMask ( ) ) { if ( MO . clobbersPhysReg ( <STR_LIT> ) || MO . clobbersPhysReg ( <STR_LIT> ) ) return true ; } } return false


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { LPCC :: CondCode CC = static_cast < LPCC :: CondCode > ( MI -> getOperand (


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerRET ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op ,


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> >


<s> assert ( Kind == KindReg && <STR_LIT> ) ; return Reg .


<s> std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; MatchSizeInBits = Match . getValueSizeInBits ( ) ; } MVT MaskSrcVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskSrcVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskSrcVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; Movmsk = getPMOVMSKB ( DL , BitcastLogicOp , DAG , Subtarget ) ; NumElts = MaskSrcVT . getVectorNumElements ( ) ; } assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; if ( BinOp == <STR_LIT> ) { SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Movmsk ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , Mask ) ; return DAG . getZExtOrTrunc ( Result , DL , ExtractVT ) ; } SDValue CmpC ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CmpC = DAG . getConstant ( ( <NUM_LIT> << NumElts ) - <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETEQ ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetccVT = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Movmsk ,


<s> static void checkIs64 ( MCContext & Ctx

, SMLoc Loc , <ISA_LIT>_64RelType Type ) {


<s> return MI . getOperand ( Op ) . getImm (


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; auto Keyword = Tok . getString ( ) ; Keyword = StringSwitch < StringRef > ( Keyword . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Keyword ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Keyword , Tok . getLoc ( ) , getContext ( ) ) ) ; Lex ( )


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != i + WhichResult ) || ( M [ i +

<NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != i + WhichResult ) ) return false ;


<s> int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = <NUM_LIT> ; if ( type && TREE_ADDRESSABLE ( type ) ) return - <NUM_LIT> ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != <NUM_LIT> ) return - <NUM_LIT> ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= <NUM_LIT> && ( slotno & <NUM_LIT> ) != <NUM_LIT> ) slotno ++ , * ppadding = <NUM_LIT> ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - <NUM_LIT> ; regno = SPARC_FP_ARG_FIRST + slotno * <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - <NUM_LIT> ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) == UNION_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; } else { int intregs_p = <NUM_LIT> , fpregs_p = <NUM_LIT> , packed_p = <NUM_LIT> ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = <NUM_LIT> ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = <NUM_LIT> ,


<s> case MCK__HASH_0 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return


<s> Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ; if ( IdVal -> EvaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; else if ( BE -> getLHS ( ) -> getKind ( ) != MCExpr :: SymbolRef ) IdVal = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , BE -> getRHS ( ) , BE ->


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; IterationCountDCE ( LoLoop ) ; MachineBasicBlock :: iterator InsertPt = LoLoop . StartInsertPt ; MachineInstr * Start = LoLoop . Start ; MachineBasicBlock * MBB = LoLoop . StartInsertBB ; unsigned Opc = LoLoop . getStartOpcode ( ) ; MachineOperand & Count = LoLoop . getLoopStartOperand ( ) ; MachineInstr * NewStart ; if ( Opc == <STR_LIT> && Count . isReg ( ) && Count . getReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; NewStart =


<s> const MachineOperand & Scale = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Index = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Offset = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Segment = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; if ( ! ( TII -> isThreeOperandsLEA ( MI ) || hasInefficientLEABaseReg ( Base , Index ) ) || ! TII -> isSafeToClobberEFLAGS ( MBB , MI ) || Segment . getReg ( ) != <STR_LIT> ) return nullptr ; Register DstR = Dst . getReg ( ) ; Register BaseR = Base . getReg ( ) ; Register IndexR = Index . getReg ( ) ; Register SSDstR = ( LEAOpcode == <STR_LIT> ) ? Register ( get<ISA_LIT>SubSuperRegister ( DstR , <NUM_LIT> ) ) : DstR ; bool IsScale1 = Scale . getImm ( ) == <NUM_LIT> ; bool IsInefficientBase = isInefficientLEAReg ( BaseR ) ; bool IsInefficientIndex = isInefficientLEAReg ( IndexR ) ; if ( IsInefficientBase && SSDstR == BaseR && ! IsScale1 ) return nullptr ; if ( LEAOpcode == <STR_LIT> && IsInefficientBase && ( IsInefficientIndex || ! IsScale1 ) ) return nullptr ; const DebugLoc DL = MI . getDebugLoc ( ) ; const MCInstrDesc & ADDrr = TII -> get ( getADDrrFromLEA ( LEAOpcode ) ) ; const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( LEAOpcode , Offset ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( IsScale1 && ( DstR == BaseR || DstR == IndexR ) ) { const MachineOperand & Src = DstR == BaseR ? Index : Base ; MachineInstr * NewMI = BuildMI ( MBB , MI , DL , ADDrr , DstR ) . addReg


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp ->


<s> if ( ExtractedIndex . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! IndicesVec ) IndicesVec = ExtractedIndex . getOperand ( <NUM_LIT> ) ; else if ( IndicesVec != ExtractedIndex . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; auto * PermIdx = dyn_cast < ConstantSDNode > ( ExtractedIndex . getOperand ( <NUM_LIT> ) ) ; if ( ! PermIdx || PermIdx -> getZExtValue ( ) != Idx ) return SDValue ( ) ; } MVT VT = V . getSimpleValueType ( ) ; MVT ShuffleVT = VT ; unsigned Opcode = LegalPermuteOpcode ( VT , ShuffleVT ) ; if ( ! Opcode ) return SDValue ( ) ; assert ( VT . getScalarSizeInBits ( ) == ShuffleVT . getScalarSizeInBits ( ) && VT . getVectorNumElements ( ) == ShuffleVT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( IndicesVec . getValueType ( ) . getVectorNumElements ( ) < NumElts ) return SDValue ( ) ; else if ( IndicesVec . getValueType ( ) . getVectorNumElements ( ) > NumElts ) { IndicesVec = extractSubVector ( IndicesVec , <NUM_LIT> , DAG , SDLoc ( IndicesVec ) , NumElts * VT . getScalarSizeInBits ( ) ) ; } MVT IndicesVT = EVT ( VT ) . changeVectorElementTypeToInteger ( ) . getSimpleVT ( ) ; IndicesVec = DAG . getZExtOrTrunc ( IndicesVec , SDLoc ( IndicesVec ) , IndicesVT ) ; if ( SrcVec . getValueSizeInBits ( ) > VT . getSizeInBits ( ) ) return SDValue ( ) ; else if ( SrcVec . getValueSizeInBits ( ) < VT . getSizeInBits ( ) ) { SrcVec = DAG . getNode ( <STR_LIT> , SDLoc ( SrcVec ) , VT , DAG . getUNDEF ( VT ) , SrcVec , DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( SrcVec ) ) ) ; } SrcVec = DAG . getBitcast ( ShuffleVT , SrcVec ) ; SDValue Res = Opcode == <STR_LIT> ? DAG . getNode ( Opcode , SDLoc ( V ) , ShuffleVT , IndicesVec , SrcVec ) : DAG . getNode ( Opcode , SDLoc (

V ) , ShuffleVT , SrcVec , IndicesVec ) ;


<s> return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_LoadStoreUImm12_2 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_LoadStoreUImm12_4 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_LoadStoreUImm12_8 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_LoadStoreUImm12_16 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_MOVWUImm16 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_MRS : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_MSR : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_at : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_dbarrier : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_dc : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_ic : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_isb : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_prefetch : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_NamedImm_tlbi : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_UImm16 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_UImm3 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) , <STR_LIT> ) ; case Match_UImm4 : return Error ( ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize ) .


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else { I . RemoveOperand ( <NUM_LIT> ) ; I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) . addUse (


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ; } else


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> else if ( ! DC -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( DC -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( DC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( DC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * AT = <STR_LIT> ( Op ) ; if ( ! AT ) return TokError ( <STR_LIT> ) ; else if ( ! AT -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( AT -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( AT -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI ->


<s> assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG ( Opc ) ; if ( InVT == <STR_LIT> ) { if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF


<s> Scale = <NUM_LIT> ; isT2 = true ; } else { return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isAtomic ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function & Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func . getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } FirstReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SecondReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstReg == SecondReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * Op0 , PredReg ) ; dl = Op0 -> getDebugLoc ( )


<s> MFI -> setHasCalls ( true ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : return makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ; case CodeModel :: Medium : { SDValue H44 = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , DAG ) ; H44 = DAG . getNode ( <STR_LIT> , DL , VT , H44 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue L44 = withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , DAG ) ; L44 = DAG . getNode ( <STR_LIT> , DL , VT , L44 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , H44 , L44 ) ; } case CodeModel :: Large : { SDValue Hi = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , DAG ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Lo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ,


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; else { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes , MachineInstr :: FrameDestroy ) ; if ( MBBI != MBB . end ( ) && AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) , MachineInstr :: FrameDestroy ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) )


<s> if ( Ext == <STR_LIT> ) IsLSL = true ; else if ( Ext != <STR_LIT> ) return MCDisassembler :: Fail ; if ( ( ! IsLSL || ( IsLSL && IsHalf ) ) && ShiftAmount != <NUM_LIT> && ShiftAmount != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( IsLSL && ShiftAmount > <NUM_LIT>


<s> static unsigned int pa_hard_regno_nregs ( unsigned int regno

ATTRIBUTE_UNUSED , machine_mode mode ) {


<s> MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A1 ) ; SDValue TmpAns = b . OR ( b . AND ( Tmp , A2 ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND ( Tmp , A2 ) ) , b . OR ( Tmp , A2 ) ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , TmpAns , b . SRL < <NUM_LIT>


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget


<s> return parseRegister ( Operands , RegGR ,


<s> x = gen_rtx_COMPARE ( CCmode , retval , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( scratch , newval ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; emit_insn ( gen_isync ( ) ) ; emit_label ( XEXP ( label2


<s> return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc ( dst ,