<s> tree t0 = TREE_TYPE ( ( * params ) [ <NUM_LIT> ] ) ; if ( t0 == error_mark_node || TREE_CODE ( t0 ) != POINTER_TYPE ) { TREE_TYPE ( fndecl ) = inittype ; return NULL_TREE ; } if ( TYPE_MODE ( t0 ) != DImode ) warning_at ( loc , <NUM_LIT> , <STR_LIT> , ( int ) tree_to_shwi ( DECL_SIZE ( ( * params ) [ <NUM_LIT> ] ) ) ) ; switch ( fcode ) { case AARCH64_MEMTAG_BUILTIN_IRG : retype = build_function_type_list ( t0 , t0 , uint64_type_node , NULL ) ; break ; case AARCH64_MEMTAG_BUILTIN_GMI : retype = build_function_type_list ( uint64_type_node , t0 , uint64_type_node , NULL ) ; break ; case AARCH64_MEMTAG_BUILTIN_INC_TAG : retype = build_function_type_list ( t0 , t0 , unsigned_type_node , NULL ) ; break ; case AARCH64_MEMTAG_BUILTIN_SET_TAG : retype = build_function_type_list ( void_type_node , t0 , NULL ) ; break ; case


<s> MF -> RenumberBlocks ( ) ; unsigned NumBlocks = MF -> size ( ) ; MBBs . clear ( ) ; MBBs . resize ( NumBlocks ) ; Terminators . clear ( ) ; Terminators . reserve ( NumBlocks ) ; BlockPosition Position ( MF -> getLogAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . LogAlignment = MBB -> getLogAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && !


<s> return ( __m128d ) __builtin_ia32_addsd ( ( __v2df )


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) ) { <ISA_LIT>MachineFunctionInfo * MFI = CurDAG -> getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Base = CurDAG -> getRegister ( MFI -> getGlobalBaseReg ( ) , <STR_LIT> ) ; Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand (


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SMLoc ExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> )


<s> paddh_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_paddh_s ( s , t )


<s> void <ISA_LIT>MCAsmStreamer :: addExplicitComment ( const Twine & T ) { StringRef c = T . getSingleStringRef ( ) ; if ( c . startswith ( StringRef ( MAI -> getCommentString ( ) ) ) ) { ExplicitCommentToEmit . append ( c . str ( ) ) ; }


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT , SelectionDAG & ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> bool isS17Imm ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > (


<s> OS << <STR_LIT> << S -> getSymbol ( ) . getName ( )


<s> case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val ,


<s> if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM


<s> enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm )


<s> SDValue V1 = Ops [ <NUM_LIT> ] ; SDValue V2 = IsUnary ? V1 : Ops [ <NUM_LIT> ] ; V1 = peekThroughBitcasts ( V1 ) ; V2 = peekThroughBitcasts ( V2 ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) Mask [ i ] = SM_SentinelUndef ; else if ( <STR_LIT> ( Op ) ) Mask [ i ] = SM_SentinelZero ; continue ; } if ( ( V . getNumOperands ( )


<s> return CustomExpandInstNaCl<ISA_LIT> ( * STI ,


<s> return R . getValue ( <NUM_LIT> ) ; } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( VT . isVector ( ) && VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ; if ( R . getNode ( ) ) return R ; } return SDValue (


<s> const TargetRegisterClass * RC = & <STR_LIT> ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; int64_t Imm ; if ( ( VT != <STR_LIT> ) && CI -> isNegative ( )


<s> ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregoidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregoidf ( __o ,


<s> static <ISA_LIT>Operand * CreateExtend ( <STR_LIT> ExtOp , unsigned Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Extend , Ctx ) ; Op -> Extend . Val = <STR_LIT> ( ExtOp , Val ) ; Op -> StartLoc


<s> storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC


<s> return ( isGTorGE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == RHS && K == TrueVal ) || ( K == LHS


<s> b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmple ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> static bool arm_fdpic_local_funcdesc_p ( rtx fnx ) { tree fn ; enum symbol_visibility vis ; bool ret ; if ( ! TARGET_FDPIC ) return true ; if ( ! SYMBOL_REF_LOCAL_P ( fnx


<s> function_instance ( const char * base_name_in , const function_base * base_in , const function_shape * shape_in , mode_suffix_index mode_suffix_id_in , const type_suffix_pair & type_suffix_ids_in , predication_index pred_in ) : base_name ( base_name_in ) , base ( base_in ) , shape ( shape_in ) , mode_suffix_id ( mode_suffix_id_in ) , pred ( pred_in ) { memcpy ( type_suffix_ids , type_suffix_ids_in , sizeof (


<s> switch ( ValLow ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; LLVM_FALLTHROUGH ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )

+ <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> return __builtin_mve_vmaxnmaq_fv8hf ( __a ,


<s> UCB_FORCED_STOP_ARG ( ucbp ) = ( _uw ) stop_arg ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ; return unwind_phase2_forced ( ucbp , entry_vrs , <NUM_LIT>


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( )


<s> Streamer . SwitchSection ( AttributeSection ) ; Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ; Streamer . emitBytes ( CurrentVendor ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; Streamer . emitInt8 ( ELFAttrs :: File ) ; Streamer . emitInt32 (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX20Reserved ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> <ISA_LIT>MCExpr :: VariantKind Variant ; const MCExpr * E = extractModifierFromExpr ( EVal , Variant ) ; if ( E ) EVal = <ISA_LIT>MCExpr :: create ( Variant , E , getParser ( ) . getContext


<s> bool <ISA_LIT>AsmParser :: parseDirectiveWord ( unsigned Size , SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( )


<s> case LO : return HS ; case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return VS ; case HI : return LS ; case LS : return HI ; case GE : return LT ; case LT : return GE ; case GT : return LE


<s> MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI ->


<s> MachineBasicBlock :: LivenessQueryResult LQR = MI . getParent ( ) -> computeRegisterLiveness ( TRI , ImplicitSReg , MI ) ; if ( LQR == MachineBasicBlock :: LQR_Live ) return true ; else if ( LQR == MachineBasicBlock :: LQR_Unknown ) return false ; ImplicitSReg = <NUM_LIT> ; return


<s> static MachineInstr * genFusedMultiply ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , unsigned IdxMulOpd , unsigned MaddOpc , const TargetRegisterClass * RC , FMAInstKind kind = FMAInstKind :: Default , const unsigned * ReplacedAddend = nullptr ) { assert ( IdxMulOpd == <NUM_LIT> || IdxMulOpd == <NUM_LIT> ) ; unsigned IdxOtherOpd = IdxMulOpd == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MachineInstr * MUL = MRI . getUniqueVRegDef ( Root . getOperand ( IdxMulOpd ) . getReg ( ) ) ; unsigned ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg2 ; bool Src2IsKill ; if ( ReplacedAddend ) { SrcReg2 = * ReplacedAddend ; Src2IsKill = true ; } else { SrcReg2 = Root . getOperand ( IdxOtherOpd ) . getReg ( ) ; Src2IsKill = Root . getOperand ( IdxOtherOpd ) . isKill ( ) ; } if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg2 ) ) MRI . constrainRegClass ( SrcReg2 , RC ) ; MachineInstrBuilder MIB ; if ( kind == FMAInstKind :: Default ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) .

addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) ;


<s> return ( ( qword ) ( vec_mule ( ( vec_short8 ) ( a ) , ( vec_short8 ) (


<s> unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value &


<s> ++ EmittedInsts ; int Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : if ( ! InCPMode && AFI -> isThumbFunction ( ) ) { EmitAlignment ( <NUM_LIT> ) ; InCPMode = true ; } break ; default : { if ( InCPMode && AFI -> isThumbFunction ( ) ) InCPMode = false ; } } printInstruction ( MI


<s> if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp )


<s> case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) ) return false ; break ; case SMAX : case SMIN : case UMAX : case UMIN : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSE4_1 ) ) return false ; case AND : case IOR : case XOR : case PLUS : case MINUS : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != mode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT ) break ; src = XEXP ( src , <NUM_LIT> ) ; case NOT


<s> default : llvm_unreachable ( <STR_LIT> ) ; \ VPTESTM_CASE ( v4i32 , DZ128 ## SUFFIX ) \ VPTESTM_CASE ( v2i64 , QZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i32 , DZ256 ## SUFFIX ) \ VPTESTM_CASE ( v4i64 , QZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i32 , DZ ## SUFFIX ) \ VPTESTM_CASE ( v8i64 , QZ ## SUFFIX ) VPTESTM_BROADCAST_CASES ( SUFFIX ) \ VPTESTM_CASE ( v16i8 , BZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i16 , WZ128 ## SUFFIX ) \ VPTESTM_CASE ( v32i8 , BZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i16 , WZ256 ## SUFFIX ) \ VPTESTM_CASE ( v64i8 , BZ ## SUFFIX ) \ VPTESTM_CASE ( v32i16 , WZ ## SUFFIX ) if ( FoldedLoad ) { switch ( TestVT . SimpleTy ) { VPTESTM_FULL_CASES (


<s> } } if ( ! returnEmitted ) { errs ( ) << <STR_LIT> << MF . getName ( ) . str ( ) << <STR_LIT> ; if ( noSuccessorFound ) { MachineBasicBlock :: iterator lastMI = noSuccessorBlock -> begin ( ) ; BuildMI ( * noSuccessorBlock , noSuccessorBlock -> end ( ) , ( * lastMI ) . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } else { errs ( )


<s> static bool darwin_local_data_pic ( rtx disp ) { return ( GET_CODE ( disp ) == UNSPEC && XINT ( disp , <NUM_LIT> ) ==


<s> bool <ISA_LIT>CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TFL = STI -> getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI -> getRegisterInfo ( ) ) ; SlotSize = RegInfo . getSlotSize ( ) ; assert ( isPowerOf2_32 ( SlotSize ) && <STR_LIT> ) ; Log2SlotSize = Log2_32 ( SlotSize ) ; if ( skipFunction ( MF . getFunction ( ) ) || ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( MI . getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , MBB , MI , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( const auto & CC : CallSeqVector ) { if ( CC . UsePush ) { adjustCallSequence ( MF , CC ) ; Changed =


<s> bool rs6000_split_128bit_ok_p ( rtx operands [ ] ) { if ( ! reload_completed ) return false ; if ( ! gpr_or_gpr_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return false ; if ( quad_load_store_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return false ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X (


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) .


<s> <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first , TM ) ) ; OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel (


<s> static DecodeStatus DecodeADDR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo ,

uint64_t Address , const void * Decoder ) {


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return * RM


<s> FunctionPass * llvm :: createAnnotationsInferencePass ( ) { return new AnnotationsInference ( )


<s> if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal


<s> bool Modified = false ; ( void ) std :: initializer_list < int > { Modified |= std :: get < ThunkInserterT > ( ThunkInserters ) . run ( MMI , MF


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) return VLdLn ; SuperReg = SDValue ( VLdLn ,


<s> else if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTPC ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res


<s> FineIBTHashesSection ( ) : ModulePass ( ID ) { initializeFineIBTHashesSectionPass ( * PassRegistry ::


<s> dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << unsigned ( BBI

. PostAlign ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Convert ; } if ( MI -> isCall ( ) || MI -> mayStore ( ) ) return Exit ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Register :: isPhysicalRegister ( Reg ) ) continue ; if ( RegInfo . regsOverlap ( Reg , RegInfo . getStackRegister ( ) ) ) return Exit ; if ( MO .


<s> case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * RegNo ; } } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } llvm_unreachable (


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> Write32 ( <NUM_LIT> ) ; return true


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { assert ( ConstraintCode == 'm' && <STR_LIT> ) ; OutOps . push_back ( Op ) ; return


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinUnwindCode ( unsigned UnwindCode , int Reg , int Offset ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S .


<s> bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ; if ( ! isSPVFP ) Binary |= RegD


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_I386_REL32 ; case


<s> return getFromCapTable ( N , DL , Ty , DAG , Chain , PtrInfo , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask = false ; if ( Mask [ i ] < CommutVal || Mask [ i ] > CommutVal + <NUM_LIT> ) CommutableMask = false ; ShuffleImm |= ( Mask [ i ] % <NUM_LIT> ) << i ; } if ( ShufpdMask ) return true ; if ( CommutableMask ) { std :: swap ( V1 , V2 ) ; return


<s> SDValue Reg = Is64Bit ? DAG . getRegister ( <STR_LIT> , VT ) : DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Ops [ ] = { GA ,


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { if ( IsILP32 ) return create<ISA_LIT>MachObjectWriter ( MachO :: CPU_TYPE_ARM64_32 , MachO ::


<s> return ( __m128 ) __builtin_ia32_cmpgtps ( ( __v4sf ) __A ,


<s> arm_init_bf16_types ( ) ; if ( TARGET_MAYBE_HARD_FLOAT ) { tree lane_check_fpr = build_function_type_list ( void_type_node , intSI_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_SIMD_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , ARM_BUILTIN_SIMD_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( TARGET_HAVE_MVE ) arm_init_mve_builtins ( ) ; else arm_init_neon_builtins ( ) ; arm_init_vfp_builtins ( ) ; arm_init_crypto_builtins ( ) ; } if ( TARGET_CDE ) arm_init_cde_builtins ( ) ; arm_init_acle_builtins ( ) ; if ( TARGET_MAYBE_HARD_FLOAT ) { tree ftype_set_fpscr = build_function_type_list ( void_type_node ,


<s> unsigned maximum_regs , maximum_bytes , start_regno , regno ; rtx value4word ; rtx dst_base_reg , new_base_reg ; unsigned HOST_WIDE_INT remain_bytes , remain_words , prepare_regs , fill_per_smw ; unsigned HOST_WIDE_INT real_size ; if ( TARGET_REDUCED_REGS ) { maximum_regs = <NUM_LIT> ; maximum_bytes = <NUM_LIT> ; start_regno = <NUM_LIT> ; } else { maximum_regs = <NUM_LIT> ; maximum_bytes = <NUM_LIT> ; start_regno = <NUM_LIT> ; } real_size = UINTVAL ( size ) & GET_MODE_MASK ( SImode ) ; if ( ! ( CONST_INT_P ( size ) && real_size <= maximum_bytes ) ) return false ; remain_bytes = real_size ; gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; value4word = nds32_gen_dup_4_byte_to_word_value ( value ) ; prepare_regs = remain_bytes / UNITS_PER_WORD ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; if ( prepare_regs > maximum_regs ) prepare_regs = maximum_regs ; fill_per_smw = prepare_regs * UNITS_PER_WORD ; regno = start_regno ; switch ( prepare_regs ) { case <NUM_LIT> : default : { rtx reg0 = gen_rtx_REG ( SImode , regno ) ; rtx reg1 = gen_rtx_REG ( SImode , regno + <NUM_LIT> ) ; unsigned last_regno = start_regno + prepare_regs - <NUM_LIT> ; emit_move_insn ( reg0 , value4word ) ; emit_move_insn ( reg1 , value4word ) ; rtx regd = gen_rtx_REG ( DImode , regno ) ; regno += <NUM_LIT> ; while ( regno <= last_regno ) { if ( ( regno + <NUM_LIT> ) <= last_regno ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; emit_move_insn ( reg , regd ) ; regno += <NUM_LIT> ; } else { rtx reg = gen_rtx_REG ( SImode , regno ) ; emit_move_insn ( reg , reg0 ) ; regno += <NUM_LIT> ; } } break ; } case <NUM_LIT> : { rtx reg = gen_rtx_REG ( SImode , regno ++ ) ; emit_move_insn ( reg , value4word ) ; } break ; case <NUM_LIT> : break ; } if ( fill_per_smw ) for ( ; remain_bytes >= fill_per_smw ; remain_bytes -= fill_per_smw ) { emit_insn ( nds32_expand_store_multiple ( start_regno , prepare_regs , dst_base_reg , dstmem , true , & new_base_reg ) ) ; dst_base_reg = new_base_reg ; dstmem = gen_rtx_MEM ( SImode , dst_base_reg ) ; } remain_words = remain_bytes / UNITS_PER_WORD ; if ( remain_words ) { emit_insn ( nds32_expand_store_multiple ( start_regno , remain_words , dst_base_reg , dstmem , true , & new_base_reg ) ) ; dst_base_reg = new_base_reg ; dstmem = gen_rtx_MEM ( SImode


<s> } static const CostTblEntry < <STR_LIT> > SSE2CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , } ; if ( ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup ( SSE2CostTable , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2CostTable [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > AVX1CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) && ! ST -> hasAVX2 ( ) ) { EVT VT = LT . second ; if ( ISD == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) && Op2Info == TargetTransformInfo :: OK_NonUniformConstantValue ) ISD = <STR_LIT> ; int Idx = CostTableLookup ( AVX1CostTable , ISD , VT ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> >


<s> Inst . addOperand ( MCOperand :: createImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Imm


<s> static inline bool is<ISA_LIT>LowRegister ( unsigned Reg ) { using namespace <ISA_LIT> ; switch ( Reg ) { case R0 : case R1 : case R2 : case R3 : case R4 : case R5 : case R6 : case R7 : return true ; default : return


<s> SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getAlign ( )

, LN -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubReg1 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned SubReg2 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg (


<s> MCAsmParser & Parser = getParser ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { const SMLoc consumedToken = consumeToken ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr &


<s> if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return false


<s> <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction (


<s> } break ; } case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( ShiftImm -> getAPIntValue ( ) . uge ( BitWidth ) ) break ; unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; APInt DemandedMask = OriginalDemandedBits << ShAmt ; if ( OriginalDemandedBits . isSignMask ( ) ) return TLO . CombineTo ( Op , Op0 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 == Op0 . getOperand ( <NUM_LIT> ) ) { SDValue Op00 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned NumSignBits = TLO . DAG . ComputeNumSignBits ( Op00 , OriginalDemandedElts ) ; if ( ShAmt < NumSignBits ) return TLO . CombineTo ( Op , Op00 ) ; } if ( OriginalDemandedBits . countLeadingZeros ( ) < ShAmt ) DemandedMask . setSignBit ( ) ; if ( SimplifyDemandedBits ( Op0 , DemandedMask , OriginalDemandedElts , Known , TLO , Depth + <NUM_LIT> ) ) return true ; assert ( ! Known . hasConflict ( ) && <STR_LIT> ) ; Known . Zero . lshrInPlace ( ShAmt ) ; Known . One . lshrInPlace ( ShAmt ) ; if ( Known . Zero [ BitWidth - ShAmt - <NUM_LIT> ] || OriginalDemandedBits . countLeadingZeros ( ) >= ShAmt ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op0 , Op1 ) ) ; if ( Known . One [ BitWidth - ShAmt - <NUM_LIT> ] ) Known . One . setHighBits ( ShAmt ) ; } break ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; unsigned SrcBits = SrcVT . getScalarSizeInBits ( ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; if ( OriginalDemandedBits . countTrailingZeros ( ) >= NumElts ) return TLO . CombineTo ( Op , TLO . DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , VT ) ) ; APInt KnownUndef , KnownZero ; APInt DemandedElts = OriginalDemandedBits . zextOrTrunc ( NumElts ) ; if ( SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , TLO , Depth


<s> if ( isa < SExtInst > ( V ) ) return false ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V


<s> return ( const_vec_duplicate_p ( x , & elt ) && GET_CODE ( elt ) == CONST_DOUBLE && real_equal

( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) ) ;


<s> const auto * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF

. getSubtarget ( ) . getRegisterInfo ( ) ) ;


<s> else if ( MEP_NONGENERAL_CLASS ( rclass ) && ( mep_nonregister ( x ) || mep_nongeneral_reg ( x ) ) ) rv = GENERAL_REGS ; fprintf ( stderr , <STR_LIT> , reg_class_names [ rv ] ) ; return ( enum reg_class )


<s> } else LaneA = LaneB ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( ViaVecTy != ResVecTy ) Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , Result ) ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> unsigned RegD = decodeVFPRd ( insn , isSPVFP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , RegD ) ) ) ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn )


<s> assert ( Kind == k_Immediate && <STR_LIT>


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { unsigned Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ; unsigned SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> && ! ST -> hasAVX2 ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs ,


<s> rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ <NUM_LIT> ] ) ) ) ; int index ; static const char * const patterns [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; index = exact_log2 ( GET_MODE_SIZE ( GET_MODE ( diff_vec ) ) ) ; gcc_assert ( index >= <NUM_LIT> && index


<s> unsigned MB = <NUM_LIT> - countTrailingOnes ( Imm64 ) ; unsigned SH = <NUM_LIT> ; unsigned Imm ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) { auto Op0 = Val . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Op0 . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { auto ResultType = Val . getNode ( ) -> getValueType ( <NUM_LIT> ) ; auto ImDef = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType ) ; SDValue IDVal ( ImDef , <NUM_LIT> ) ; Val = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType , IDVal , Op0 . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } } if ( Val . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Val . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { assert ( Imm < <NUM_LIT> && <STR_LIT> ) ; Val = Val . getOperand ( <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } SDValue Ops [ ] = { Val , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true


<s> if ( ! isHomogeneousAggregate ( ST -> getElementType ( i ) , Base , SubMembers ) ) return false ; Members += SubMembers ; } } else if ( auto * AT = dyn_cast < ArrayType > ( Ty ) ) { uint64_t SubMembers = <NUM_LIT> ; if ( ! isHomogeneousAggregate ( AT -> getElementType ( ) , Base , SubMembers ) ) return false ; Members += SubMembers * AT -> getNumElements ( ) ; } else if ( Ty -> isFloatTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_FLOAT ) return false ; Members = <NUM_LIT> ; Base = HA_FLOAT ; } else if ( Ty -> isDoubleTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_DOUBLE ) return false ; Members =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Subtarget -> isABI_N64 ( )


<s> default : break ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget


<s> int Reg2 = OffsetRegTok . is ( AsmToken :: Identifier ) ? tryParseRegister ( ) : - <NUM_LIT> ; if ( Reg2 != - <NUM_LIT> ) { <STR_LIT> ExtOp = <STR_LIT> ; int64_t ShiftVal = <NUM_LIT> ; bool ExplicitShift = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; SMLoc ExtLoc = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; ExtOp = StringSwitch < <STR_LIT> > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ExtOp == <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> ) ; Parser . Lex ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg2 ) ) { if ( ExtOp != <STR_LIT> && ExtOp != <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> <STR_LIT> ) ; } else if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg2 ) ) return Error ( OffsetLoc , <STR_LIT> ) ; bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ; if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) { if ( ExtOp == <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> ) ; } else if ( Hash || getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; SMLoc ExprLoc = getLoc ( ) ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; ExplicitShift = true ; ShiftVal = MCE -> getValue ( ) ; if ( ShiftVal < <NUM_LIT> || ShiftVal > <NUM_LIT> ) return Error ( ExprLoc , <STR_LIT> ) ; } else return Error ( getLoc ( ) , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc E = getLoc (


<s> gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs ) ; density_pct = ( vec_cost * <NUM_LIT> ) / ( vec_cost + not_vec_cost


<s> uint64_t <ISA_LIT>InstrInfo :: getElementSizeForOpcode ( unsigned


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) { return false


<s> if ( MI -> getOperand ( OpNo ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O


<s> AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L =

df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> auto & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) { ArgInfo & OutArg = OutArgs . back ( ) ; assert ( OutArg . Regs . size ( ) == <NUM_LIT> && MRI . getType ( OutArg . Regs [ <NUM_LIT> ] ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OutArg . Regs [ <NUM_LIT> ] = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , OutArg . Regs [ <NUM_LIT> ] ) . getReg ( <NUM_LIT> ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; OutArg . Ty = Type :: getInt8Ty ( Ctx ) ; } } SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; bool CanTailCallOpt = isEligibleForTailCallOptimization ( MIRBuilder , Info , InArgs , OutArgs ) ; if ( Info . IsMustTailCall && ! CanTailCallOpt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Info . IsTailCall = CanTailCallOpt ; if ( CanTailCallOpt ) return lowerTailCall ( MIRBuilder , Info , OutArgs ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opc = <NUM_LIT> ; if ( Info . CB && objcarc :: hasAttachedCallOpBundle ( Info . CB ) ) Opc = <STR_LIT> ; else if ( Info . CB && Info . CB -> getAttributes ( ) . hasFnAttr ( Attribute :: ReturnsTwice ) && ! Subtarget . noBTIAtReturnTwice ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) Opc = <STR_LIT> ; else Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; unsigned CalleeOpNo = <NUM_LIT> ; if ( Opc == <STR_LIT> ) { Function * ARCFn = * objcarc :: getAttachedARCFunction ( Info . CB ) ; MIB . addGlobalAddress ( ARCFn ) ; ++ CalleeOpNo ; } MIB . add ( Info . Callee ) ; const uint32_t * Mask ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( AssignFnFixed , AssignFnVarArg


<s> else { HOST_WIDE_INT rounded_size ; rtx g4 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( g1 , GEN_INT ( first ) ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( g4 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_insn ( gen_rtx_SET ( g4 , gen_rtx_MINUS ( Pmode , g1 , g4 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , g1 , g1 , g4 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , g4 , rounded_size - size ) ) ; } emit_insn ( gen_blockage ( )


<s> if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_PAIRED ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_SPE ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> )


<s> static void ReplaceREADCYCLECOUNTER ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc DL ( N ) ; SDValue Cycles32 , OutChain ; if ( Subtarget -> hasPerfMon ( ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) } ; Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Ops [ <NUM_LIT> ] , array_lengthof ( Ops ) ) ; OutChain = Cycles32 . getValue ( <NUM_LIT> ) ; } else { Cycles32 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; OutChain = DAG . getEntryNode ( ) ; } SDValue Cycles64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Results . push_back (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { auto Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDLoc DL ( Op ) ; SDValue Chain = Node -> getChain ( ) ; SDValue Dst = Op . getOperand ( <NUM_LIT> ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; Val = DAG . getAnyExtOrTrunc ( Val , DL , <STR_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; auto Alignment = Node -> getMemOperand ( ) -> getAlign ( ) ; bool IsVol = Node -> isVolatile ( ) ; auto DstPtrInfo = Node


<s> rtx chr2 = gen_reg_rtx ( SImode ) ; rtx chr1_di = simplify_gen_subreg ( DImode , chr1 , SImode , <NUM_LIT> ) ; rtx chr2_di = simplify_gen_subreg ( DImode , chr2 , SImode , <NUM_LIT> ) ; emit_insn ( gen_vclzlsbb_v16qi ( diffix , vec_result ) ) ; emit_insn ( gen_vextublx ( chr1 , diffix , str1 ) ) ; emit_insn ( gen_vextublx ( chr2 , diffix , str2 ) ) ; do_sub3 ( result , chr1_di , chr2_di ) ; } else { gcc_assert ( TARGET_P8_VECTOR ) ; rtx diffix = gen_reg_rtx ( DImode ) ; rtx result_gbbd = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_p8v_vgbbd ( result_gbbd , vec_result ) ) ; rtx result_shifted = gen_reg_rtx ( V16QImode ) ; int shift_amt = ( BYTES_BIG_ENDIAN ) ? <NUM_LIT> : <NUM_LIT> ; emit_insn ( gen_altivec_vsldoi_v16qi ( result_shifted , result_gbbd , result_gbbd , GEN_INT ( shift_amt ) ) ) ; rtx diffix_df = simplify_gen_subreg ( DFmode , diffix , DImode , <NUM_LIT> ) ; emit_insn ( gen_p8_mfvsrd_3_v16qi ( diffix_df , result_shifted ) ) ; rtx count = gen_reg_rtx ( DImode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_clzdi2 ( count , diffix ) ) ; else emit_insn ( gen_ctzdi2 ( count , diffix ) ) ; do_add3 ( off_reg , off_reg , count ) ; rtx chr1 = gen_reg_rtx ( QImode ) ; rtx chr2 = gen_reg_rtx ( QImode ) ; rtx addr1 = gen_rtx_PLUS ( Pmode , s1addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr1 , addr1 , orig_src1 ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , s2addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr2 , addr2 , orig_src2 ) ; machine_mode rmode = GET_MODE ( result ) ; rtx chr1_rm = simplify_gen_subreg ( rmode , chr1 , QImode , <NUM_LIT> ) ; rtx chr2_rm = simplify_gen_subreg ( rmode , chr2 , QImode ,


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ResTy ) ; SDValue Bit = DAG . getNode ( <STR_LIT> , DL , ResTy ,


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( )

. isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) PSHUFBMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ; } if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ; return lowerVectorShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 ,


<s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: COPY ) , Out ) . addReg ( DReg , <NUM_LIT> , Lane ) ; return Out


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSet<ISA_LIT>16 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF ::


<s> ConstantSDNode * ConstVal = cast < ConstantSDNode > ( N ) ; uint64_t ImmVal = ConstVal -> getZExtValue ( ) ; uint64_t SupportedMask = <NUM_LIT> ; if ( ( ImmVal & SupportedMask ) != ImmVal ) { return SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , N , <STR_LIT> ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT>


<s> FunctionPass * llvm :: createCleanupLocalDynamicTLSPass ( ) { return new LDTLSCleanup (


<s> return GET_CODE ( x ) == REG && INT_REG_OK_FOR_BASE_P ( x


<s> return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < <ISA_LIT>Subtarget


<s> unsigned i , elt ; rtx t0 , t1 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( V8QImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_loongson_punpcklbh ( t0 , d -> op0 , d -> op0 ) ) ; else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= <NUM_LIT> ; elt *= <NUM_LIT> ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ; return


<s> unsigned getVarArgsFPRSize ( ) const { return VarArgsFPRSize


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { if ( ! hasFP ( MF ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI ->


<s> Value * <ISA_LIT>IREmitter :: visitVSRAI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N


<s> isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) ,

GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , SpilledCSRegs ( MF . getTarget ( ) . getRegisterInfo ( ) -> getNumRegs ( ) ) , JumpTableUId ( <NUM_LIT> ) , ConstPoolEntryUId ( <NUM_LIT> ) {


<s> void addLogicalImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( Imm . Val ) ; uint32_t Bits ; A64Imms :: isLogicalImm ( RegWidth , CE -> getValue (


<s> rtx body = PATTERN ( insn ) ; rtx src_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx copy = gen_rtx_SET ( SET_DEST ( body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( insn ) ) ; df_insn_rescan ( new_insn


<s> const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg

( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;


<s> if ( GOTOFF_P ( address ) ) { address = XEXP ( address , <NUM_LIT> ) ; if ( GET_CODE ( address ) == PLUS ) address = XEXP (


<s> if ( PTR_IN ( emergency_labeled_state , ls ) )

atomic_free ( & emergency_labeled_state_free , emergency_labeled_state - ls ) ;


<s> } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == <NUM_LIT> ) { if ( incoming_p ) { if ( fndecl == current_function_decl && ! ix86_static_chain_on_stack ) { gcc_assert ( ! reload_completed ) ; ix86_static_chain_on_stack = true ; } return gen_frame_mem ( SImode , plus_constant ( Pmode , arg_pointer_rtx , -


<s> if ( ! matchVectorAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; N = Handle . getValue


<s> assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case TargetOpcode ::


<s> const TargetSubtargetInfo * ST = & MFunc . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>FI = MFunc . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool Change = false ; for ( MachineBasicBlock & MBB : MFunc ) Change |= configBasicBlock (


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; if ( BaseReg . getReg ( ) == <STR_LIT> ) { assert ( IndexReg . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; return true


<s> if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getSelect ( dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl ,


<s> setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; setAction ( { extOp , <NUM_LIT> , s32 } ,


<s> Value * <ISA_LIT>IREmitter :: visitMOVSLDUP ( const SDNode *


<s> bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; unsigned Offset ; if ( TII -> getLdStBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( & MI ) ; } PrevBaseReg =


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI


<s> if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( create<ISA_LIT>CondBrTuning


<s> if ( ST -> hasSSE1 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( ST -> is64Bit ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> case PLUS : if ( CONST_OK_FOR_I ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_J ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : if ( CONST_OK_FOR_K ( INTVAL ( x ) ) || CONST_OK_FOR_L ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true


<s> void <ISA_LIT>XPLINKFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; MFFrame . setOffsetAdjustment ( Regs . getStackPointerBias (


<s> void <ISA_LIT>ConstantIslands :: createNewWater ( unsigned CPUserIndex , unsigned UserOffset , MachineBasicBlock * & NewMBB ) { CPUser & U = CPUsers [ CPUserIndex ] ; MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; unsigned CPELogAlign = getCPELogAlign ( * CPEMI ) ; MachineBasicBlock * UserMBB = UserMI -> getParent ( ) ; const BasicBlockInfo & UserBBI = BBInfo [ UserMBB -> getNumber ( ) ] ; if ( BBHasFallthrough ( UserMBB ) ) { unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UserMBB ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } } NewMBB = splitBlockBeforeInstr (


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( NonMpxChecks ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } return Reserved


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Cond == <STR_LIT> && isOneConstant ( RHS ) && LHS -> getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS -> getOperand ( <NUM_LIT> ) ) && isOneConstant ( LHS -> getOperand ( <NUM_LIT> ) ) && LHS -> hasOneUse ( ) ) { auto * OpCC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; auto OldCond = static_cast < <STR_LIT> > ( OpCC -> getZExtValue ( ) ) ; auto NewCond = getInvertedCondCode ( OldCond ) ; SDValue CSEL = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( NewCond , DL , <STR_LIT> ) , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( CSEL , DL , VT ) ; } if ( Cond == <STR_LIT> && isNullConstant ( RHS ) && LHS -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) && LHS -> hasOneUse ( ) ) { EVT TstVT = LHS -> getValueType ( <NUM_LIT> ) ; if ( TstVT . isScalarInteger ( ) && TstVT . getFixedSizeInBits ( ) <= <NUM_LIT> ) { uint64_t TstImm = - <NUM_LIT> << LHS -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue TST = DAG . getNode ( <STR_LIT> , DL , TstVT , LHS -> getOperand

( <NUM_LIT> ) , DAG . getConstant ( TstImm , DL , TstVT ) ) ;


<s> bool macho_lo_sum_memory_operand ( rtx x , machine_mode mode ) { if ( ! TARGET_MACHO || ! flag_pic || mode != SImode ||


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc_copysign : case LibFunc_copysignf : continue ; case LibFunc_copysignl : return true ; case LibFunc_fabs : case LibFunc_fabsf : case LibFunc_fabsl : continue ; case LibFunc_sqrt : case LibFunc_sqrtf : case LibFunc_sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc_floor : case LibFunc_floorf : case LibFunc_floorl : Opcode = <STR_LIT> ; break ; case LibFunc_nearbyint : case LibFunc_nearbyintf : case LibFunc_nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc_ceil : case LibFunc_ceilf : case LibFunc_ceill : Opcode = <STR_LIT> ; break ; case LibFunc_rint : case LibFunc_rintf : case LibFunc_rintl : Opcode = <STR_LIT> ; break ; case LibFunc_round : case LibFunc_roundf : case LibFunc_roundl : Opcode = <STR_LIT> ; break ; case LibFunc_trunc : case LibFunc_truncf : case LibFunc_truncl : Opcode = <STR_LIT> ; break ; case LibFunc_fmin : case LibFunc_fminf : case LibFunc_fminl : Opcode = <STR_LIT> ; break ; case LibFunc_fmax : case LibFunc_fmaxf : case LibFunc_fmaxl : Opcode = <STR_LIT> ; break ; } } if ( Opcode ) { EVT EVTy = TLI -> getValueType ( DL , CI -> getArgOperand ( <NUM_LIT> ) ->


<s> bool isMSA128DAsm ( ) const { return Kind == k_Register && Reg . Kind


<s> HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; if ( size >= ( <NUM_LIT> << ( HOST_BITS_PER_INT - <NUM_LIT> ) ) ) size


<s> MachineInstrBuilder MIB ; if ( AddrReg == <STR_LIT> || AddrReg == <STR_LIT> ) { Register AddrTmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , AddrTmp ) ; MIB . addReg ( AddrReg ) ; MIB . addImm ( <NUM_LIT> ) ; AddrReg = AddrTmp ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( AddrTmp , false , false , true ) ; } MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MIB . addReg ( PC , RegState :: Define ) ; MIB . addReg ( AddrReg ) ; MIB . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( StackReg ,


<s> <ISA_LIT>ElfTargetObjectFile ( ) : TargetLoweringObjectFileELF ( ) { PLTRelativeVariantKind = MCSymbolRefExpr ::


<s> unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |= <STR_LIT> ( AM2Opc ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO2 . getReg ( ) ) ) ; Binary |= II -> getRegisterInfo ( ) . getEncodingValue ( MO2


<s> bool IsLeafFunction = true ; auto IsNonTailCall = [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; IsLeafFunction = false ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> needsDwarfUnwindInfo ( ) ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset (


<s> O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : { Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin ( ) ) ; TmpInst . setOpcode ( <STR_LIT> ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isGlobal ( ) ) ; MCSymbol * & TOCEntry = TOC [ Mang -> getSymbol ( MO . getGlobal ( ) ) ] ; if ( TOCEntry == <NUM_LIT> ) TOCEntry = GetTempSymbol ( <STR_LIT> , TOCLabelID ++ ) ; const MCExpr * Exp = MCSymbolRefExpr :: Create ( TOCEntry , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateExpr ( Exp


<s> MI = Temp ; MBB . erase ( II ) ; break ; } case <STR_LIT> : { Register NewReg ; if ( STI . hasE2 ( ) ) { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , RegState :: Define ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NewReg ) . addImm ( <NUM_LIT> ) ; } MI = BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , getKillRegState ( true ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . getInstr ( ) ; MBB . erase ( II ) ; break ; } } int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) report_fatal_error ( <STR_LIT> ) ; bool FrameRegIsKill = false ; MachineBasicBlock :: iterator NewII ( MI ) ; if ( ! IsLegalOffset ( TII , MI , Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; assert ( Offset >= <NUM_LIT> ) ; Register ScratchReg = TII -> movImm ( MBB , NewII , DL , Offset ) ; BuildMI ( MBB , NewII , DL , TII -> get ( STI . hasE2 ( ) ? <STR_LIT> : <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( FrameReg ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill =


<s> if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case ENCODING_IRC : insn -> RC = ( l2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | lFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; break ; case ENCODING_RB : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RW : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RD : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RO : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Rv : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_CC : insn -> immediates [ <NUM_LIT> ] = insn -> opcode & <NUM_LIT> ; break ; case ENCODING_FP : break ; case ENCODING_VVVV : needVVVV = <NUM_LIT> ; if ( ! hasVVVV ) return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) insn -> vvvv = static_cast < Reg > ( insn -> vvvv & <NUM_LIT> ) ; if ( fixupReg ( insn , & Op ) ) return - <NUM_LIT> ; break ; case ENCODING_WRITEMASK : if ( readMaskRegister ( insn ) ) return - <NUM_LIT> ; break ; case ENCODING_DUP : break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( needVVVV ) return


<s> return ( __m512i ) __builtin_ia32_vpopcountd_v16si_mask ( ( __v16si ) __A , ( __v16si ) _mm512_setzero_si512 ( )


<s> for ( unsigned int i = <NUM_LIT> ; i < elt_size ; ++

i ) builder . quick_push ( const0_rtx ) ;


<s> static const <ISA_LIT>MCExpr * CreateLo12 ( const MCExpr * Expr , MCContext


<s> if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size )

+ ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { std :: cout << <STR_LIT>


<s> return ( __m128d ) vec_mergeh ( ( __v2df )


<s> int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , SPOffsetFromCFA + Delta ) ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MCSymbol * SetFPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( SetFPLabel ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( SetFPLabel , HardFP ) ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } MCSymbol * FPRSaveLabel = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; if ( ! FPRSaveLabel ) FPRSaveLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; unsigned Reg = MRI -> getDwarfRegNum ( I -> getReg ( )


<s> Relocator :: Result adr_got_page ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { if ( ! ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) { return Relocator :: BadReloc ; } Relocator :: Address GOT_S = helper_get_GOT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: Address P = pReloc . place ( ) ; Relocator :: DWord X = helper_get_page_address ( GOT_S + A ) - helper_get_page_address ( P ) ; pReloc . target ( ) = helper_reencode_adr_imm ( pReloc . target ( ) , ( X >> <NUM_LIT> ) ) ; <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ; if ( got_entry != NULL && <ISA_LIT>Relocator :: SymVal == got_entry -> getValue ( ) ) got_entry -> setValue ( pReloc . symValue ( ) ) ; Relocation * dyn_rela = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; if ( ( dyn_rela != NULL ) && ( <ISA_LIT>Relocator :: SymVal == dyn_rela -> addend ( )


<s> SDValue <ISA_LIT>TargetLowering :: lowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = false ; ShiftLeft = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = true ; ShiftLeft = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = true ; ShiftLeft = true ; break ; } assert ( ( LogicalShift || ! ShiftLeft ) && <STR_LIT> ) ; Value * Vec = II . getArgOperand ( <NUM_LIT> ) ; Value * Amt = II . getArgOperand ( <NUM_LIT> ) ; auto * VT = cast < FixedVectorType > ( II . getType ( ) ) ; Type * SVT = VT -> getElementType ( ) ; int NumElts = VT -> getNumElements ( ) ; int BitWidth = SVT -> getIntegerBitWidth ( ) ; APInt UpperBits = APInt :: getHighBitsSet ( BitWidth , BitWidth - Log2_32 ( BitWidth ) ) ; if ( llvm :: MaskedValueIsZero ( Amt , UpperBits , II . getModule ( ) -> getDataLayout ( ) ) ) { return ( LogicalShift ? ( ShiftLeft ? Builder . CreateShl ( Vec , Amt ) : Builder . CreateLShr ( Vec , Amt ) ) : Builder . CreateAShr ( Vec , Amt ) ) ; } auto * CShift = dyn_cast < Constant > ( Amt ) ; if ( ! CShift ) return nullptr ; bool AnyOutOfRange = false ; SmallVector < int , <NUM_LIT>


<s> const <ISA_LIT>InstrInfo & <ISA_LIT>II = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified =


<s> for ( auto * I : MaskedInsts ) { unsigned PredOp = I -> getIntrinsicID ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * Predicate = dyn_cast < Instruction > ( I -> getArgOperand ( PredOp ) ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; ActiveLaneMask = dyn_cast < IntrinsicInst > ( Predicate ) ; if ( ! ActiveLaneMask || ActiveLaneMask -> getIntrinsicID ( ) != <STR_LIT>


<s> bool <ISA_LIT>MachObjectWriter :: recordScatteredRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , unsigned Log2Size , uint64_t & FixedValue ) { const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; const MCFixupKind FK = Fixup . getKind ( ) ; const unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , FK ) ; const unsigned Type = getRelocType ( Target , FK , IsPCRel ) ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; if ( ! A -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + SB -> getName ( ) + <STR_LIT> ) ; Value2 = Writer -> getSymbolAddress ( * SB , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return false ; } uint32_t other_half = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : other_half = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF : other_half = FixedValue


<s> return mips_function_value_1 ( NULL_TREE ,


<s> bool <ISA_LIT>TargetLowering :: isConstantUnsignedBitfieldExtractLegal ( unsigned Opc , LLT Ty1 , LLT


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { Op = Op -> getOperand ( <NUM_LIT> ) ; VT = Op -> getValueType ( <NUM_LIT> ) ; BitWidth = VT . getSizeInBits ( ) ; } uint64_t ShiftImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShiftImm ) && ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShiftImm ) ) return false ; unsigned Width = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; if ( ShiftImm + Width > BitWidth ) return false ; Opc = ( VT == <STR_LIT> ) ? <STR_LIT> :


<s> SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG