<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( SK_<ISA_LIT>ELFStreamer , Context , TAB , OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) { Reset (


<s> uint64_t Val ; if ( ! isa < ConstantSDNode > ( N ) ) return SDValue ( ) ; Val = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( ST -> isThumb1Only ( ) ) { if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction


<s> bool isMemNegImm8Offset ( ) const { if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory .


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtvec vec = gen_rtvec ( <NUM_LIT> , pred , op0 , op1 ) ; return gen_rtx_UNSPEC ( pred_mode , vec , aarch64_unspec_cond_code ( code


<s> if ( TARGET_64BIT || TARGET_VXWORKS_RTP ) fprintf ( file , <STR_LIT> , directive , LPREFIX , value , LPREFIX , rel ) ; else if ( HAVE_AS_GOTOFF_IN_DATA ) fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; else if ( TARGET_MACHO ) { fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; machopic_output_function_base_name ( file ) ; putc ( '\n' , file ) ; } else asm_fprintf ( file , ASM_LONG <STR_LIT> , GOT_SYMBOL_NAME , LPREFIX


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> } if ( SPReg == <STR_LIT> || SPReg == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; Error ( SPRegLoc , <STR_LIT> ) ; return false ; } int64_t Offset = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc OffsetLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) ) { Parser . eatToEndOfStatement ( ) ; Error ( OffsetLoc , <STR_LIT> )


<s> CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = <STR_LIT> ; } else if ( el_mode == SFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = <STR_LIT> ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name )


<s> return ( uint8x8_t ) __builtin_neon_vqshlu_nv8qi ( __a ,


<s> } else { Result = getAddr ( GN , DAG , OpFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( OpFlags & ( <STR_LIT> | <STR_LIT> ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result


<s> bool <ISA_LIT>FastISel :: optimizeIntExtLoad ( const Instruction * I , MVT RetVT , MVT SrcVT ) { const auto * LI = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! LI || ! LI -> hasOneUse ( ) ) return false ; unsigned Reg = lookUpRegForValue ( LI ) ; if ( ! Reg ) return false ; MachineInstr * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) return false ; bool IsZExt = isa < ZExtInst > ( I ) ; const auto * LoadMI = MI ; if ( LoadMI -> getOpcode ( ) == TargetOpcode :: COPY && LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { unsigned LoadReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LoadMI = MRI . getUniqueVRegDef ( LoadReg ) ; assert ( LoadMI && <STR_LIT> ) ; } if ( ! ( IsZExt && isZExtLoad ( LoadMI ) ) && ! ( ! IsZExt && isSExtLoad ( LoadMI ) ) ) return false ; if ( RetVT != <STR_LIT> || SrcVT > <STR_LIT> ) { updateValueMap ( I , Reg ) ; return true ; } if ( IsZExt ) { unsigned Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg = Reg64


<s> return ( __m256bh ) __builtin_ia32_cvtneps2bf16_v16sf (


<s> StringRef getPassName ( ) const override { return


<s> unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return


<s> if ( MIOpc == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; } else if ( MIOpc == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; } else { return false ; } <STR_LIT> MICC = findCondCodeUsedByInstr ( MI ) ; if ( MICC == <STR_LIT> ) return false ; if ( MI . findRegisterDefOperandIdx ( <STR_LIT> , true ) != - <NUM_LIT> ) return false ; const unsigned CmpOpcode = CmpInstr . getOpcode ( ) ; bool IsSubsRegImm = isSUBSRegImm ( CmpOpcode ) ; if ( CmpValue && ! IsSubsRegImm ) return false ; if ( ! CmpValue && ! IsSubsRegImm && ! isADDSRegImm ( CmpOpcode ) ) return false ; UsedNZCV MIUsedNZCV = getUsedNZCV ( MICC ) ; if ( MIUsedNZCV . C || MIUsedNZCV . V ) return false ; Optional < UsedNZCV > NZCVUsedAfterCmp = examineCFlagsUse ( MI , CmpInstr , TRI , & CCUseInstrs ) ; if ( ! NZCVUsedAfterCmp ) return false ; if ( ( MIUsedNZCV . Z && NZCVUsedAfterCmp -> N ) || ( MIUsedNZCV . N && NZCVUsedAfterCmp -> Z ) ) return false ; if ( MIUsedNZCV . N && ! CmpValue )


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( ) { return std :: make_unique <


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI


<s> output_asm_insn ( <STR_LIT> , operands ) ; } else output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT


<s> int num_pushes = ARM_NUM_INTS ( crtl -> args . pretend_args_size ) ; unsigned long mask ; mask = <NUM_LIT> << ( LAST_ARG_REGNUM + <NUM_LIT> ) ; mask -= <NUM_LIT> << ( LAST_ARG_REGNUM + <NUM_LIT> - num_pushes ) ; insn = thumb1_emit_multi_reg_push ( mask , <NUM_LIT> ) ; } else { insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , x ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_BACKTRACE ) { HOST_WIDE_INT offset = <NUM_LIT> ; unsigned work_register ; rtx work_reg , x , arm_hfp_rtx ; work_register = thumb_find_work_register ( live_regs_mask ) ; work_reg = gen_rtx_REG ( SImode , work_register ) ; arm_hfp_rtx = gen_rtx_REG ( SImode , ARM_HARD_FRAME_POINTER_REGNUM ) ; insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( l_mask ) { insn = thumb1_emit_multi_reg_push ( l_mask , l_mask ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; offset = bit_count ( l_mask ) * UNITS_PER_WORD ; } x = GEN_INT ( offset + <NUM_LIT> + crtl -> args . pretend_args_size ) ; emit_insn ( gen_addsi3 ( work_reg , stack_pointer_rtx , x ) ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; if ( l_mask ) { x = gen_rtx_REG ( SImode , PC_REGNUM ) ; emit_move_insn ( work_reg , x ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; emit_move_insn ( work_reg , arm_hfp_rtx ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; } else { emit_move_insn ( work_reg , arm_hfp_rtx ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; x = gen_rtx_REG ( SImode , PC_REGNUM ) ; emit_move_insn ( work_reg , x ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; } x = gen_rtx_REG (


<s> unsigned Directive = ST -> getCPUDirective ( ) ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return reasonForFixupRelaxation ( Fixup


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType ( ) ; SDValue Node = DAG . getNode ( <STR_LIT> , DL , WideTy , WideVec , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return NarrowVector ( Node ,


<s> const TargetRegisterClass * RC = RegInfo . intRegClass ( VRegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I


<s> static SDValue lowerVectorShuffleAsShift ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; auto CheckZeros = [ & ] ( int Shift , int Scale , bool Left ) { for ( int i = <NUM_LIT> ; i < Size ; i += Scale ) for ( int j = <NUM_LIT> ; j < Shift ; ++ j ) if ( ! Zeroable [ i + j + ( Left ? <NUM_LIT> : ( Scale - Shift ) ) ] ) return false ; return true ; } ; auto MatchShift = [ & ] ( int Shift , int Scale , bool Left , SDValue V ) { for ( int i = <NUM_LIT> ; i != Size ; i += Scale ) { unsigned Pos = Left ? i + Shift : i ; unsigned Low = Left ? i : i + Shift ; unsigned Len = Scale - Shift ; if ( ! isSequentialOrUndefInRange ( Mask , Pos , Len , Low + ( V == V1 ? <NUM_LIT> : Size ) ) ) return SDValue ( ) ; } int ShiftEltBits = VT . getScalarSizeInBits ( ) * Scale ; bool ByteShift = ShiftEltBits > <NUM_LIT> ; unsigned OpCode = Left ? ( ByteShift ? <STR_LIT> : <STR_LIT> ) : ( ByteShift ? <STR_LIT> : <STR_LIT> ) ; int ShiftAmt = Shift * VT . getScalarSizeInBits ( ) / ( ByteShift ? <NUM_LIT> : <NUM_LIT> ) ; Scale = ByteShift ? Scale / <NUM_LIT> : Scale ; MVT ShiftSVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) * Scale ) ; MVT ShiftVT = ByteShift ? <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) : <STR_LIT> ( ShiftSVT , Size / Scale ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ShiftVT ) && <STR_LIT> ) ; V = DAG . getBitcast ( ShiftVT , V ) ; V = DAG . getNode ( OpCode , DL , ShiftVT , V , DAG . getConstant ( ShiftAmt , DL ,


<s> ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsAMD ) { IsSHLDSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) ) ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } else if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelSLM ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT> ) { <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasLZCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPRFCHW = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsAMD ) { if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasSSE4A =


<s> else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( insn ) = ok_label ; add_reg_br_prob_note ( insn , profile_probability :: very_likely ( ) ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( r0 , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_frame_store ( r0 , r1 , info -> lr_save_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_call_insn ( gen_call ( gen_rtx_MEM ( SImode , morestack_ref ) , const0_rtx , const0_rtx


<s>
if
(
!
TAI
->
getSetDirective
(
)
)
return
;
if
(
Subtarget
->
isPICStyleGOT
(
)
)
return
;
O
<<
TAI
->
getSetDirective
(
)
<<
' '
<<
TAI
->
getPrivateGlobalPrefix
(
)
<<
getFunctionNumber
(
)
<<
'_'
<<
uid
<<
<STR_LIT>
<<
MBB
->
getNumber
(
)
<<
','
;
printBasicBlockLabel
(
MBB
,
false
,
false
,
false
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
'-'
<<
TAI
->
getPrivateGlobalPrefix
(
)
<<
<STR_LIT>
<<
getFunctionNumber
(
)
<<
'_'
<<
uid
<<
'\n'
;
else
{
O
<<
'-'
;
PrintPICBaseSymbol
(


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( *


<s> break ; } case 'Q' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'R' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : if ( ! Subtarget -> hasMMX ( ) ) break ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'Y' : if ( ! Subtarget -> hasSSE2 ( ) ) break ; case 'x' : if ( ! Subtarget -> hasSSE1 ( ) ) break ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; } } std :: pair < unsigned , const TargetRegisterClass * >


<s> return isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) &&


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret


<s> if ( TARGET_MACHO ) flag_errno_math = <NUM_LIT> ; if ( optimize >= <NUM_LIT> ) flag_omit_frame_pointer = <NUM_LIT> ; flag_pcc_struct_return =


<s> if ( VOp0 . getOpcode ( ) == <STR_LIT> && V . getValueSizeInBits ( ) == cast < VTSDNode > ( VOp0 . getOperand ( <NUM_LIT> )

) -> getVT ( ) . getSizeInBits ( ) ) return VOp0 . getOperand ( <NUM_LIT> ) ;


<s> valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , <NUM_LIT> , true ) ; if ( valret ) return false ; } if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; warned_for_return_big_vectors = true ; } return true ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE ( type ) ==


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( ( I == <NUM_LIT> ) && ( SaveCount == <NUM_LIT> ) ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; } } if ( I < SaveCount ) { assert ( I < MaxSaved && <STR_LIT> ) ; Saved [ I ++ ] = Inst ; if ( I < SaveCount ) return true ; } assert ( I == SaveCount && SaveCount > <NUM_LIT> && <STR_LIT> ) ; RecurseGuard = true ; switch ( Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( I , Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardJmp ( I , Saved , Out ) ; break ; case <STR_LIT>


<s> SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , P } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = <STR_LIT> ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; if ( DCI . isBeforeLegalize ( ) || TruncVT != <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , Trunc } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc


<s> } unsigned MIPredReg ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg || getInstrPredicate ( MI , MIPredReg ) != Pred || MIPredReg != PredReg ) return <NUM_LIT> ; if ( CheckCPSRDef && definesCPSR ( MI ) ) return <NUM_LIT> ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) *


<s> } if ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF && MEM_P ( fnaddr ) && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF && ! local_symbolic_operand ( XEXP ( fnaddr , <NUM_LIT> ) , VOIDmode ) ) fnaddr = gen_rtx_MEM ( QImode , construct_plt_address ( XEXP ( fnaddr , <NUM_LIT> ) ) ) ; else if ( sibcall ? ! sibcall_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) : ! call_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) ) { fnaddr = convert_to_mode ( word_mode , XEXP ( fnaddr , <NUM_LIT> ) , <NUM_LIT> ) ; fnaddr = gen_rtx_MEM ( QImode , copy_to_mode_reg ( word_mode , fnaddr ) ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) { if ( TARGET_MPX && SCALAR_INT_MODE_P ( GET_MODE ( retval ) ) ) { rtx b0 = gen_rtx_REG ( BND64mode , FIRST_BND_REG ) ; rtx b1 = gen_rtx_REG ( BND64mode , FIRST_BND_REG + <NUM_LIT> ) ; if ( GET_CODE ( retval ) == PARALLEL ) { b0 = gen_rtx_EXPR_LIST ( VOIDmode , b0 , const0_rtx ) ; b1 = gen_rtx_EXPR_LIST ( VOIDmode , b1 , const0_rtx ) ; rtx par = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , b0 , b1 ) ) ; retval = chkp_join_splitted_slot ( retval , par ) ; } else { retval = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , retval , b0 , b1 ) ) ; chkp_put_regs_to_expr_list ( retval ) ; } } call = gen_rtx_SET ( VOIDmode , retval , call ) ; } vec [ vec_len ++ ] = call ; if ( pop ) { pop = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , pop ) ; pop = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , pop ) ; vec [ vec_len ++


<s> return __builtin_loongson_psadbh ( s ,


<s> } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] )


<s> if ( NumElems != <NUM_LIT> ) return false ; int QuarterSize = NumElems / <NUM_LIT> ; int HalfSize = QuarterSize * <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < QuarterSize ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , HalfSize ) ) return false ; for ( int i = QuarterSize ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems , NumElems + HalfSize ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , HalfSize , NumElems ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems + HalfSize , NumElems * <NUM_LIT> ) ) return false ; return true


<s> bool isSystemPStateFieldWithImm0_1 ( ) const { if ( ! isSysReg ( )


<s> bool <ISA_LIT>InstrInfo :: useMachineCombiner ( ) const { return


<s> static void appendVGScaledOffsetExpr ( SmallVectorImpl < char > & Expr , int NumBytes , int NumVGScaledBytes , unsigned VG , llvm :: raw_string_ostream & Comment ) { uint8_t buffer [ <NUM_LIT> ] ; if ( NumBytes ) { Expr . push_back ( dwarf :: DW_OP_consts ) ; Expr . append ( buffer , buffer + encodeSLEB128 ( NumBytes , buffer ) ) ; Expr . push_back ( ( uint8_t ) dwarf :: DW_OP_plus ) ; Comment << ( NumBytes < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) << std :: abs ( NumBytes ) ; } if ( NumVGScaledBytes ) { Expr . push_back ( ( uint8_t ) dwarf :: DW_OP_consts


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == -


<s> unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor (


<s> Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT>


<s> BB -> setAlignment ( AlignConstantIslands ? MaxAlign : Align ( <NUM_LIT> ) ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( Log2 ( MaxAlign ) + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= Log2 ( MaxAlign ) ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } LLVM_DEBUG ( BB ->


<s> <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = ( CallConv == CallingConv :: Fast ) && PerformTailCallOpt ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( )


<s> Register getStackRegister ( ) const { return StackPtr


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> return ( uint64x1_t ) __builtin_neon_vld1di ( ( const __builtin_neon_di


<s> if ( ! isSingleSpacedVectorList ( ) ) return


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const { assert ( isFrameInstr ( I


<s> void <ISA_LIT>InstrInfo :: suppressLdStPair ( MachineInstr * MI ) const { if ( MI -> memoperands_empty ( ) ) return ; static_assert ( MOSuppressPair < ( <NUM_LIT> << MachineMemOperand :: MOTargetNumBits )


<s> const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Ws1 = RegInfo . createVirtualRegister ( RC ) ; unsigned Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2


<s> ix86_prefetch_sse = ptr -> prefetch_sse ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch !=


<s> static DecodeStatus DecodeVCVTQ ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool hasFullFP16 = featureBits [ <STR_LIT> ] ; unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT>


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false ,

MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS <<


<s> return ( n <= MAX_REG_FOR_PASSING_ARGS && n >= MIN_REG_FOR_PASSING_ARGS


<s> else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ; for ( auto & Obj : SortingObjects ) { if ( ! Obj .


<s> void RegDefsUses :: init ( const MachineInstr & MI ) { update ( MI , <NUM_LIT> , MI . getDesc ( ) . getNumOperands ( ) ) ; if ( MI . isCall ( ) ) Defs . set


<s> } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) || ( VT . isVector ( ) && TLI . isTypeLegal ( VT ) ) ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op1 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op0 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r0 , x0 ) ; for ( i = <NUM_LIT> ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { xi = CONST_VECTOR_ELT ( x , i ) ; if ( ! CONST_DOUBLE_P ( xi ) ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( ri , xi


<s> default : RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } unsigned RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand :: createReg ( Regs [ i ] ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( code == LTGT || code == GE || code == UNGT ) cond [ n ++ ] = gen_rtx_fmt_ee ( GT , mode , x , const0_rtx ) ; if ( code == LE || code == GE || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( EQ , mode , x , const0_rtx ) ; if ( code == UNLT || code == UNGT || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( UNORDERED , mode , x , const0_rtx ) ; gcc_assert ( n == <NUM_LIT> ) ; rtx cc = gen_reg_rtx


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs


<s> return ! ( MI -> mayLoad ( ) || MI -> mayStore ( ) || MI -> hasUnmodeledSideEffects ( ) ||

MI -> isCall ( ) || MI -> isReturn ( ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitMMX_PINSRW ( const


<s> return std :: all_of ( MBB . succ_begin ( ) , MBB . succ_end ( ) , [ ] ( const MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) ; } ) && std :: all_of ( MBBI , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . isMetaInstruction ( ) ; } )


<s> static void rs6000_elf_asm_out_destructor ( rtx symbol , int priority ) { const char * section = <STR_LIT> ; char buf [ <NUM_LIT> ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file


<s> constv = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , perm ) ) ; constv = force_reg ( V16QImode , constv ) ; unspec = gen_rtx_UNSPEC ( V16QImode , gen_rtvec ( <NUM_LIT> , op1 , op0 , constv ) , UNSPEC_VPERM ) ; if ( ! REG_P ( target ) ) { rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_move_insn ( tmp ,


<s> else if ( AM . BaseType == <STR_LIT> ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity += <NUM_LIT> ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Disp && ( AM . Base . Reg . getNode ( ) || AM . IndexReg .

getNode ( ) ) ) Complexity += <NUM_LIT> ;


<s> MCE . addRelocation ( MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( )

, Reloc , JTIndex , <NUM_LIT> , true ) ) ;


<s> static tree pa_d_handle_target_float_abi ( void ) { const char *


<s> machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ <NUM_LIT> ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ <NUM_LIT> ] , code , op0 , op1 , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , code , op0 , op1 , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ix86_expand_sse_movcc ( operands [ <NUM_LIT> ] , tmp , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx


<s> return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : { <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_ABS && <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_SABS ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( ! IsResolved ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3


<s> for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool RestrictR15 = FlagRestrictR15 ; assert ( FlagUseZeroBasedSandbox || RestrictR15 ) ; if ( Subtarget . isTargetNaCl64 ( ) ) { if ( RestrictR15 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; const bool RestrictR11 = FlagHideSandboxBase && ! FlagUseZeroBasedSandbox ; if ( RestrictR11 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> static SDValue LowerToTLSGeneralDynamicModelX32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const EVT PtrVT ) { return GetTLSADDR ( DAG , DAG . getEntryNode ( ) , GA , nullptr , PtrVT , <STR_LIT> ,


<s> return new <ISA_LIT>ExpandHardenedPseudos


<s> Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; } return


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction


<s> SDValue CC = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = CC -> getOpcode ( ) ; SDValue Int ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( CC -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) ) { assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; Int = CC -> getOperand ( <NUM_LIT> ) ; } else if ( CC -> getOpcode ( ) == <STR_LIT> ) Int = CC ; else return SDValue ( ) ; unsigned IntOp = cast < ConstantSDNode > ( Int . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; SDValue ExitBlock = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , Elements , ExitBlock


<s> bool isUImm4 ( ) const { return isUImm < <NUM_LIT> > (


<s> MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; const SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , In2L , In2H , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs (


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new <ISA_LIT>HazardRecognizer (


<s> const MCInstrDesc & MCID = TII . get ( UnfoldedOpc ) ; return TII . getRegClass ( MCID , Index , & TII


<s> if ( sp_offset + frame_size < <NUM_LIT> ) sp_offset += frame_size ; add_constant ( SP_REGNO , SP_REGNO , - sp_offset , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( mep_call_saves_register ( i ) ) { rtx mem ; bool maybe_dead_p ; machine_mode rmode ; rss = cfun -> machine -> reg_save_slot [ i ] ; if ( ( i == TP_REGNO || i == GP_REGNO || i == LP_REGNO ) && ( ! mep_reg_set_in_function ( i ) && ! mep_interrupt_p ( ) ) ) continue ; if ( mep_reg_size ( i ) == <NUM_LIT> ) rmode = DImode ; else rmode = SImode ; mem = gen_rtx_MEM ( rmode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss ) ) ; maybe_dead_p = rtx_equal_p ( mem , has_hard_reg_initial_val ( rmode , i ) ) ; if ( GR_REGNO_P ( i ) || LOADABLE_CR_REGNO_P ( i ) ) F ( maybe_dead_move ( mem , gen_rtx_REG ( rmode , i ) , maybe_dead_p ) ) ; else if ( rmode == DImode ) { rtx_insn * insn ; int be = TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss + be ) ) ; maybe_dead_move ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , i ) , maybe_dead_p ) ; maybe_dead_move ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP + <NUM_LIT> ) , gen_rtx_ZERO_EXTRACT ( SImode , gen_rtx_REG ( DImode , i ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , maybe_dead_p ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , maybe_dead_p ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , copy_rtx ( mem ) , gen_rtx_REG ( rmode , i ) ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss + ( <NUM_LIT> - be ) ) ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP + <NUM_LIT> ) , maybe_dead_p ) ; } else { rtx_insn * insn ; maybe_dead_move ( gen_rtx_REG ( rmode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( rmode , i ) , maybe_dead_p ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( rmode , REGSAVE_CONTROL_TEMP ) , maybe_dead_p ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , copy_rtx ( mem ) , gen_rtx_REG ( rmode , i ) ) ) ; } } if ( frame_pointer_needed ) { add_constant ( FP_REGNO , SP_REGNO , sp_offset - reg_save_size , <NUM_LIT> ) ; } add_constant ( SP_REGNO , SP_REGNO , sp_offset - ( reg_save_size + frame_size


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; DebugLoc DL ; using RegAndKill = std :: pair < unsigned , bool > ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( const RegAndKill


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Type * Ty = Input -> getType ( ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getVectorNumElements ( ) , Ty -> getScalarSizeInBits ( ) ,


<s> bool hasLoadStoreOnCond ( ) const { return HasLoadStoreOnCond


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; EVT ResVT = Op . getValueType ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ; assert ( ResVT == <STR_LIT> || ResVT == <STR_LIT> || ResVT == <STR_LIT> || ResVT == <STR_LIT> ) ; int Mask [ <NUM_LIT> ] ; SDValue InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue VecOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; InVec = Op . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT


<s> PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCatchPad ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const Constant * PerFn = MF -> getFunction ( ) ->


<s> MBB -> addSuccessor ( TrueMBB ) ; return true ; } } else if ( ExtractValueInst * EI = dyn_cast < ExtractValueInst > ( BI -> getCondition ( ) ) ) { if ( const IntrinsicInst * CI = dyn_cast < IntrinsicInst > ( EI -> getAggregateOperand ( ) ) ) { if ( CI -> getIntrinsicID ( ) == <STR_LIT> || CI -> getIntrinsicID ( ) == <STR_LIT> ) { const MachineInstr * SetMI = <NUM_LIT> ; unsigned Reg = lookUpRegForValue ( EI ) ; for ( MachineBasicBlock :: const_reverse_iterator RI = MBB -> rbegin ( ) , RE = MBB -> rend ( ) ; RI != RE ; ++ RI ) { const MachineInstr & MI = * RI ; if ( MI . modifiesRegister ( Reg ) ) { unsigned Src , Dst , SrcSR , DstSR ; if ( getInstrInfo ( ) -> isMoveInstr ( MI , Src , Dst , SrcSR , DstSR ) ) { Reg = Src ; continue ; } SetMI = & MI ; break ; } const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . hasUnmodeledSideEffects ( ) || TID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) break ; } if ( SetMI ) { unsigned OpCode = SetMI -> getOpcode ( ) ; if ( OpCode == <STR_LIT> || OpCode == <STR_LIT> ) { BuildMI ( MBB , DL , TII . get ( OpCode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( TrueMBB ) ; FastEmitBranch ( FalseMBB ) ; MBB -> addSuccessor ( TrueMBB ) ; return true ; } } } } } unsigned OpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( OpReg ) . addReg ( OpReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; FastEmitBranch (


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT>


<s> if ( tok -> type == CPP_NAME ) { cpp_hashnode * ident = tok -> val . node . node ; if ( ident == C_CPP_HASHNODE ( vector_keyword ) ) return C_CPP_HASHNODE ( __vector_keyword ) ; if ( ident == C_CPP_HASHNODE ( pixel_keyword ) ) return C_CPP_HASHNODE ( __pixel_keyword ) ; if ( ident == C_CPP_HASHNODE ( bool_keyword ) ) return C_CPP_HASHNODE ( __bool_keyword ) ; if ( ident == C_CPP_HASHNODE ( _Bool_keyword ) ) return C_CPP_HASHNODE ( __bool_keyword ) ; return ident ; } return <NUM_LIT>


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const


<s> void <ISA_LIT>MIPeephole :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo


<s> if ( MachineInstOpcode == <STR_LIT> ) MRI . setRegClass ( Op0 , & <STR_LIT> ) ; else if ( MachineInstOpcode == <STR_LIT> ) MRI . setRegClass ( Op0 , & <STR_LIT> ) ; const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? &


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo &

STI ) : MCELFStreamer ( Context , MAB , OS , Emitter ) {


<s> if ( get_attr_may_clobber_hilo ( insn ) ) mips_macc_chains_last_hilo


<s> default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; if ( ! OpInfo ) return false ; bool SP = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool fixed_point = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned RegClassID = SP ? <STR_LIT> : <STR_LIT> ; if ( fixed_point ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int size = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int fbits = size - ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , decodeVFPRd ( insn , SP ) ) ) ) ; assert ( TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; assert ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( fbits ) ) ; NumOpsAdded = <NUM_LIT> ; } else { unsigned d , m ; if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { d = decodeVFPRd ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , d ) ) ) ; m = decodeVFPRm ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , m ) ) ) ; } else { d = decodeVFPRd ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID ,


<s> return STI . getFeatureBits ( ) [ <STR_LIT>


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <NUM_LIT> : return imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> ; case <NUM_LIT> : return imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 << <NUM_LIT> | imm8 ; } } else { unsigned Val = <NUM_LIT> << <NUM_LIT> | slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ; unsigned Amt = slice ( imm12 , <NUM_LIT> , <NUM_LIT> ) ; return <STR_LIT> ( Val ,


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG


<s> } bool RV ; unsigned ResultReg ; RV = emitLoad ( VT , ResultReg , Src ) ; if ( ! RV ) return false ; RV = emitStore ( VT , ResultReg , Dest ) ; if ( ! RV ) return false ; int64_t Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; UnscaledOffset += Size ; Dest . setOffset ( OrigDest . getOffset ( ) +


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> if ( ! isa < MemSDNode > ( * UI ) ) return false ; } if ( isa < ConstantSDNode > ( RHS ) ) { int64_t ImmOff = ( int64_t ) cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( ImmOff % Size == <NUM_LIT> && ImmOff >= <NUM_LIT> && ImmOff < ( <NUM_LIT> << Scale ) ) || isPreferredADD ( ImmOff ) || isPreferredADD ( - ImmOff ) ) return false ; SDValue Ops [ ] = { RHS } ; SDNode * MOVI = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; SDValue MOVIV = SDValue ( MOVI , <NUM_LIT> ) ; N = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , MOVIV ) ; } bool IsExtendedRegisterWorthFolding = isWorthFolding ( N ) ; if ( IsExtendedRegisterWorthFolding && RHS . getOpcode ( ) == <STR_LIT> && SelectExtendedSHL ( RHS , Size ,


<s> EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ( ImmValue & ~ ( ImmValue + <NUM_LIT>


<s> if ( ! IsARPop && ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC && ListContainsLR ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( inITBlock ( ) && ! lastInITBlock ( ) && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; return false


<s> Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = F . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask

( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> if ( Reg == FramePtr && TFI -> hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin (


<s> MCAsmParser & getParser ( ) const { return Parser


<s> void setReg ( unsigned Val ) { Contents . RegNum =


<s> gcc_assert ( GET_MODE ( src ) != DFmode ) ; src_template = <STR_LIT> ; } else if ( MEM_P ( src ) && rx_small_data_operand ( XEXP ( src , <NUM_LIT> ) ) ) { gcc_assert ( GET_MODE ( src ) != DImode ) ; gcc_assert ( GET_MODE ( src ) != DFmode ) ; src_template = <STR_LIT> ; } else src_template = <STR_LIT> ; if ( MEM_P ( dest ) && rx_small_data_operand ( XEXP ( dest , <NUM_LIT> ) ) ) { gcc_assert ( GET_MODE ( dest ) != DImode ) ; gcc_assert ( GET_MODE ( dest ) != DFmode ) ; dst_template = <STR_LIT> ; } else dst_template = <STR_LIT> ; if ( GET_MODE ( dest ) == DImode || GET_MODE ( dest ) == DFmode ) { gcc_assert ( ! is_movu ) ; if ( REG_P ( src ) && REG_P ( dest ) && ( REGNO ( dest ) == REGNO ( src ) + <NUM_LIT> ) ) sprintf ( out_template , <STR_LIT> ) ; else sprintf ( out_template , <STR_LIT> ) ; } else sprintf ( out_template , <STR_LIT> , is_movu ? <STR_LIT> : <STR_LIT>

, extension , src_template , dst_template ) ;


<s>
}
unsigned
BasePointerReg
=
<STR_LIT>
;
if
(
RegInfo
->
hasBasePointer
(
MF
)
)
BasePointerReg
=
RegInfo
->
getBaseRegister
(
)
;
bool
ExtraCSSpill
=
false
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
++
i
)
{
const
unsigned
Reg
=
CSRegs
[
i
]
;
if
(
Reg
==
BasePointerReg
)
SavedRegs
.
set
(
Reg
)
;
bool
RegUsed
=
SavedRegs
.
test
(
Reg
)
;
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
true
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
int
Reg
=
SavedRegs
.
find_first
(
)
;
Reg
!=
<NUM_LIT>
;
Reg
=
SavedRegs
.
find_next
(
Reg
)
)
dbgs
(
)
<<
' '
<<
PrintReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
bool
CanEliminateFrame
=
NumRegsSpilled
==
<NUM_LIT>
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
MFI
.
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
NumRegsSpilled
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
&&
!
ExtraCSSpill
)
{
if
(
UnspilledCSGPR
!=
<STR_LIT>
)
{
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
PrintReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
true
;
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
}
if
(
!
ExtraCSSpill
)
{
const
TargetRegisterClass
*
RC


<s> getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; if ( ! SetCCI . mayStore ( ) ) { assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MRI -> replaceRegWith ( SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB .


<s> SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp ) ; return false ; } return true


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return NULL ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI


<s> pattern = copy_insn ( pattern ) ; ix86_rewrite_tls_address_1 ( & pattern ) ; return


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ Idx ] , Regs , Offsets ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI


<s> unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , VR ) . addReg ( Src , getKillRegState ( I -> getOperand ( <NUM_LIT>


<s> void Thumb1InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI .


<s> return ( __m256 ) __builtin_ia32_sqrtps256 ( ( __v8sf


<s> return ( R0 . Offset > R1 . Offset ) ? <NUM_LIT> : ( ( R0 . Offset == R1 . Offset


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: Fast ) { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_Fast ) ; } else { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg )


<s> Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = isSVR4ABI ? <STR_LIT> : <STR_LIT> ; Callee . setNode ( <NUM_LIT> ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , PtrVT ) ) ; } if ( Callee . getNode ( ) ) { Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back (

DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


<s> EQ = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , UNORD , EQ ) ; } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> && ! Subtarget -> hasAVX2 ( ) ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; FlipSigns = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; FlipSigns = true ; Invert


<s> case MCExpr :: Constant : return nullptr ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_None : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_REFLONG ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PC_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PC_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF_HI32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF_LO32 : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_LO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT_HI32 : Variant = <ISA_LIT>MCExpr ::


<s> if ( ! ST . hasLOB ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; MF . RenumberBlocks


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; this -> TM = & static_cast < const <ISA_LIT>TargetMachine


<s> const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return <NUM_LIT> ; switch ( MBBI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg


<s> unsigned char value = MI -> getOperand ( Op ) . getImm ( ) ; assert ( value <= <NUM_LIT> && <STR_LIT> ) ; switch ( value ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div2di ( ( int64x2_t )


<s> JITCompilerFunction = Fn ; return is64Bit ? <ISA_LIT>64CompilationCallback :


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranch16TargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Name ) ) { return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } } Parser . Lex (


<s> unsigned Idx = isPairedLdSt ( MI ) || <ISA_LIT>InstrInfo :: isPreLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ; return MI . getOperand


<s> initialize<ISA_LIT>CondBrTuningPass ( * PassRegistry :: getPassRegistry (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> if ( ! I -> isCopy ( ) || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; Context . SPCopy = I ++ ; StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MaxAdjust > <NUM_LIT> ) Context . MovVector . resize ( MaxAdjust , nullptr ) ; do { int Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) break ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp % <NUM_LIT> ) return ; StackDisp /= <NUM_LIT> ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp ] != nullptr ) return ; Context . MovVector [ StackDisp ] = I ; ++ I ; } while ( I != MBB . end ( ) ) ; if ( I == MBB . end ( ) ) return ; if ( I -> isCopy ( ) ) { if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getGlobalBaseReg ( ) ) ++ I ; else return ; } if ( ! I -> isCall ( ) ) return ; Context . Call


<s> return ( int32x4x2_t ) { vtrn1q_s32 ( a , b ) , vtrn2q_s32 ( a ,


<s> case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> ,


<s> assert ( LdOpc != <NUM_LIT> && <STR_LIT> ) ; if ( LdSize >= <NUM_LIT> ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState ::

Define ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x )


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ case TYPE_MM32 : \ case TYPE_MM

: \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _MM0 + index ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _CR0 + index ; \ } \ }


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5SOperand ( const MCInst * MI , unsigned Op , raw_ostream & O , unsigned Scale ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = MO2 . getImm ( ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( ImmOffs * Scale ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT>


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand

( OpNum ) . getImm ( ) << markup ( <STR_LIT> ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> static AsmPrinter * create<ISA_LIT>AsmPrinterPass ( formatted_raw_ostream & o , TargetMachine & tm , MCContext & Ctx ,

MCStreamer & Streamer , const MCAsmInfo * tai ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = std :: make_unique < <ISA_LIT>Operand > ( Immediate , StartLoc , EndLoc ) ; Res -> Imm .


<s> bool getManipulatesSP ( ) const { return ManipulatesSP


<s> for ( tail = attributes ; attrs ; attrs = TREE_CHAIN ( attrs ) ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) ) warning ( OPT_Wattributes , <STR_LIT> , TREE_PURPOSE ( attrs ) ) ; else { * tail = tree_cons ( TREE_PURPOSE ( attrs ) , NULL_TREE , NULL_TREE ) ; tail = & TREE_CHAIN ( * tail ) ; } } attrs = * attributes ; } } * attributes = attrs ; sh_deferred_function_attributes = NULL_TREE ; sh_deferred_function_attributes_tail = &


<s> if ( isThumb2 ( ) ) { EncodedValue |=


<s> MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestHi . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredHi . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addOperand ( DesiredLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addOperand ( DesiredHi ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( NewLo . getReg ( ) ) ; StoreBB -> addLiveIn ( NewHi . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addOperand ( NewLo ) . addOperand ( NewHi ) . addOperand ( Addr ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg ,

RegState :: Kill ) . addMBB ( LoadCmpBB ) ;


<s> PROMOTE_MODE ( mode , * punsignedp , type ) ; return


<s> Lea . setOpcode ( <STR_LIT> ) ; Lea . addOperand ( MCOperand :: CreateReg ( getReg64 ( Op . getReg ( ) ) ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( getReg64 ( Op


<s> const GlobalValue * <ISA_LIT>ConstantPoolValue :: getGV ( ) const { return dyn_cast_or_null < GlobalValue > ( CVal


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . setOffset


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) != <STR_LIT> ) Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; } SDLoc dl ( Op ) ; MVT VT = <STR_LIT> ( std :: max ( ( int ) Op . getValueType ( ) . getSizeInBits (


<s> bool has<ISA_LIT>3 ( ) const { return STI . getFeatureBits ( )


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , IsLittle ( little ) , TM ( _TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies

( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) {


<s> PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira


<s> for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO

) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> InLastByte += MFI -> getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , Chain . getDebugLoc ( ) , <STR_LIT> , & ArgChains [ <NUM_LIT> ]


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ScalarTy ) ; SDValue StepVector = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , One ) ; SDValue Step = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Op2 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , N ->

getValueType ( <NUM_LIT> ) , StepVector , Step ) ;


<s> unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) . getImm ( ) ; return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == TargetOpcode :: STACKMAP || MI -> getOpcode ( ) == TargetOpcode ::

PATCHPOINT || ( isInt < <NUM_LIT> > ( Offset ) && ( Offset % offsetMinAlign ( * MI ) ) == <NUM_LIT> ) ;