<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> .

hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) ) return getRegBank ( <STR_LIT> ) ;


<s> return true ; } ; if ( Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( SDValue U = PerformVQDMULHCombine ( Trunc . getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ) { DAG . ReplaceAllUsesWith ( Trunc . getOperand ( <NUM_LIT> ) , U ) ; return SDValue ( ) ; } } if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc -> getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNOriginalMask ( Shuffle -> getMask ( ) , false ) || isVMOVNOriginalMask ( Shuffle -> getMask ( ) , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = i * NumElements * ToEltVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , NewFromVT , Trunc . getOperand ( <NUM_LIT> ) , DAG . getConstant ( i * NumElements , DL , <STR_LIT> ) ) ; if ( ToEltVT == <STR_LIT> ) { SDValue FPTrunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPTrunc ) ; } SDValue Store = DAG . getTruncStore ( Ch , DL , Extract , NewPtr , St -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewToVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Stores . push_back


<s> OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear (


<s> void clearUsedRegisterList ( ) { UsedRegisters . clear


<s> static MCAsmInfo * create<ISA_LIT>V9MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg ,


<s> if ( Suffix == 's' || Suffix == 'd' ) O << '.' << Suffix ; else assert ( Suffix == <NUM_LIT> && <STR_LIT> ) ; bool DoShift = ExtWidth != <NUM_LIT> ; if ( SignExtend || DoShift || SrcRegKind == 'w' ) { O << <STR_LIT> ; printMemExtendImpl ( SignExtend , DoShift , ExtWidth , SrcRegKind


<s> if ( ArchID != <STR_LIT> && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT>


<s> tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != <NUM_LIT> ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( tree_fits_uhwi_p ( bit_position ( field ) ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ; machine_mode mode = DECL_MODE (


<s> if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF


<s> S = Parser . getTok ( ) . getLoc ( ) ; if ( parseMemOffset ( IdVal ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( )


<s> FunctionPass * llvm :: create<ISA_LIT>CmovConverterPass ( ) { return new <ISA_LIT>CmovConverterPass (


<s>
}
return
;
}
std
::
string
name
=
Mang
->
getValueName
(
GVar
)
;
Constant
*
C
=
GVar
->
getInitializer
(
)
;
const
Type
*
Type
=
C
->
getType
(
)
;
unsigned
Size
=
TD
->
getTypeAllocSize
(
Type
)
;
unsigned
Align
=
TD
->
getPreferredAlignmentLog
(
GVar
)
;
printVisibility
(
name
,
GVar
->
getVisibility
(
)
)
;
if
(
Subtarget
->
isTargetELF
(
)
)
O
<<
<STR_LIT>
<<
name
<<
<STR_LIT>
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
GVar
)
)
;
if
(
C
->
isNullValue
(
)
&&
!
GVar
->
hasSection
(
)
&&
!
(
Subtarget
->
isTargetDarwin
(
)
&&
TAI
->
SectionKindForGlobal
(
GVar
)
==
SectionKind
::
RODataMergeStr
)
)
{
if
(
GVar
->
hasExternalLinkage
(
)
)
{
if
(
const
char
*
Directive
=
TAI
->
getZeroFillDirective
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
O
<<
Directive
<<
<STR_LIT>
<<
name
<<
<STR_LIT>
<<
Size
<<
<STR_LIT>
<<
Align
<<
'\n'
;
return
;
}
}
if
(
!
GVar
->
isThreadLocal
(
)
&&
(
GVar
->
hasLocalLinkage
(
)
||
GVar
->
isWeakForLinker
(
)
)
)
{
if
(
Size
==
<NUM_LIT>
)
Size
=
<NUM_LIT>
;
if
(
TAI
->
getLCOMMDirective
(
)
!=
)
{
if
(
GVar
->
hasLocalLinkage
(
)
)
{
O
<<
TAI
->
getLCOMMDirective
(
)
<<
name
<<
','
<<
Size
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
O
<<
','
<<
Align
;
}
else
if
(
Subtarget
->
isTargetDarwin
(
)
&&
!
GVar
->
hasCommonLinkage
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
<<
TAI
->
getWeakDefDirective
(
)
<<
name
<<
'\n'
;
EmitAlignment
(
Align
,
GVar
)
;
O
<<
name
<<
<STR_LIT>
;
if
(
VerboseAsm
)
{
O
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;
PrintUnmangledNameSafely
(
GVar
,
O
)
;
}
O
<<
'\n'
;
EmitGlobalConstant
(
C
)
;
return
;
}
else
{
O
<<
TAI
->
getCOMMDirective
(
)
<<
name
<<
','
<<
Size
;
if
(
TAI
->
getCOMMDirectiveTakesAlignment
(
)
)
O
<<
','
<<
(
TAI
->
getAlignmentIsInBytes
(
)
(
<NUM_LIT>
<<
Align
)
:
Align
)
;
}
}
else
{
if
(
!
Subtarget
->
isTargetCygMing
(
)
)
{
if
(
GVar
->
hasLocalLinkage
(
)
)
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
}
O
<<
TAI
->
getCOMMDirective
(
)
<<
name
<<
','
<<
Size
;
if
(
TAI
->
getCOMMDirectiveTakesAlignment
(
)
)
O
<<
','
<<
(
TAI
->
getAlignmentIsInBytes
(
)
(
<NUM_LIT>
<<
Align
)
:
Align
)
;
}
if
(
VerboseAsm
)
{
O
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;
PrintUnmangledNameSafely
(
GVar
,
O
)
;
}
O
<<
'\n'


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = I64RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; MadeChange = true ; } } return


<s> if ( ParseIntelExpression ( SM , End ) ) return true ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( ! PtrInOperand ) Size = SM . getElementSize ( ) << <NUM_LIT> ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return Error ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( ) , ErrMsg ) ) return Error ( Start , ErrMsg ) ; if ( isParsingMSInlineAsm ( ) ) return CreateMemForMSInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) , Operands ) ; if ( Parser . isParsingMasm (


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; } ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addFullAddress ( MIB , AM ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return


<s> void <ISA_LIT>AsmPrinter :: EmitXXStructor ( const Constant * CV ) { uint64_t Size = TM . getTargetData ( ) -> getTypeAllocSize ( CV -> getType ( ) ) ; assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ; assert ( GV


<s> case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG


<s> return ( ( vec_double2 ) ( si_shlqbi ( ( qword ) ( a ) , si_from_uint ( count )


<s> std :: vector < LiveRange * > getLiveRangesFor ( MachineInstr * MI ) { std :: vector < LiveRange * > ranges ; for ( auto & LR : interferenceGraph ) { if ( LR -> contains ( MI ) ) { ranges . push_back ( LR ) ; } } return


<s> case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case


<s> PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead =


<s> bool <ISA_LIT>InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo


<s> case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLDOReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSLDM : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLDMReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSGD : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSGDReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_GOTENT ; llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PLT : assert ( IsPCRel && <STR_LIT> ) ; return getPLTReloc (


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName


<s> if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII ->


<s> Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; ExtraSteps = <NUM_LIT> ; return Estimate


<s> else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . add ( predOps ( <STR_LIT> ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( MF , UserMBB , BBInfo [ UserMBB -> getNumber ( ) ] ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset


<s> static DecodeStatus DecodePOOL16BEncodedField ( MCInst & Inst , unsigned Value , uint64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Value == <NUM_LIT> ? <NUM_LIT> : Value ) ) ; return MCDisassembler


<s> if ( TT . isOSBinFormatMachO ( ) ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer (


<s> unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , <NUM_LIT> , TRI , * ( MBB -> getParent ( ) ) ) ) ; BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LoadDisp ) . addReg ( <STR_LIT> ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; DEBUG ( LoadInst -> getPrevNode ( ) -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst )


<s> break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case


<s> int <ISA_LIT>BaseInstrInfo :: getVSTMUseCycle ( const InstrItineraryData * ItinData , const TargetInstrDesc & UseTID , unsigned UseClass , unsigned UseIdx , unsigned UseAlign ) const { int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseTID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( )


<s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; IsMasked = true ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( Alignment < Align ( <NUM_LIT> ) ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return true ; } bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Op , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return false ; return


<s> static void mips_emit_loadgp ( void ) { rtx addr , offset , incoming_address , base , index , pic_reg ; pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx ; switch ( mips_current_loadgp_style ( ) ) { case LOADGP_ABSOLUTE : if ( mips_gnu_local_gp == NULL ) { mips_gnu_local_gp = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( mips_gnu_local_gp ) |= SYMBOL_FLAG_LOCAL ; } emit_insn ( PMODE_INSN ( gen_loadgp_absolute , ( pic_reg , mips_gnu_local_gp ) ) ) ; break ; case LOADGP_OLDABI : break ; case LOADGP_NEWABI : addr = XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) ; offset = mips_unspec_address ( addr , SYMBOL_GOTOFF_LOADGP ) ; incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( PMODE_INSN ( gen_loadgp_newabi , ( pic_reg , offset , incoming_address ) ) ) ; break ; case LOADGP_RTP : base = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( VXWORKS_GOTT_BASE ) ) ; index = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup


<ISA_LIT>ConstantPoolValue :: equals ( A ) ;


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetNaCl ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT>


<s> LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , WidenScalar } , { <NUM_LIT> , Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , Unsupported } ) ; return result


<s> void addSImm9Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> )


<s> ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file


<s> if ( a >= - ( SFtype ) ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) return ( SItype ) ( a + ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << (


<s> switch ( TI . getOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : TargetReg = TI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( llvm :: any_of ( MBB . terminators ( ) , [ & ] ( MachineInstr & OtherTI ) { return ! OtherTI . isDebugInstr ( ) && & OtherTI != & TI ; } ) ) { LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> <STR_LIT> ; for ( MachineInstr & MI : MBB . terminators ( ) ) { MI . dump ( ) ; dbgs ( ) << '\n' ; } } ) ; report_fatal_error ( <STR_LIT> ) ; } TargetAddrSSA . AddAvailableValue ( & MBB , TargetReg ) ; IndirectTerminatedMBBs . insert ( & MBB ) ; for ( MachineBasicBlock * Succ : MBB . successors ( ) ) IndirectTargetMBBs . insert ( Succ ) ; } SmallVector < MachineInstr * , <NUM_LIT> > CMovs ; if ( IndirectTargetMBBs . empty ( ) ) return CMovs ; for ( MachineBasicBlock & MBB : MF ) { if ( ! IndirectTargetMBBs . count ( & MBB ) ) continue ; assert ( ! MBB . isEHPad ( ) && <STR_LIT> ) ; assert ( ! MBB . isLiveIn ( <STR_LIT> ) && <STR_LIT> ) ; for ( MachineBasicBlock * Pred : MBB . predecessors ( ) ) { if ( IndirectTerminatedMBBs . count ( Pred ) ) continue ; if ( ! llvm :: all_of ( Pred -> successors ( ) , [ & ] ( MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) || Succ == & MBB ; } ) ) { LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> <STR_LIT> ; Pred -> dump ( ) ; MBB . dump ( ) ; } ) ; report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } auto InsertPt = Pred -> getFirstTerminator ( ) ; Register TargetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { auto AddrI = BuildMI ( * Pred , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , TargetReg ) . addMBB ( & MBB ) ; ++


<s> else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; return Inst -> getType ( ) ->

getPrimitiveSizeInBits ( ) <= <NUM_LIT> ;


<s> const TargetFrameLowering * getFrameLowering


<s> static SDValue lowerVectorShuffleAsTruncBroadcast ( SDLoc DL , MVT VT , SDValue V0 , int BroadcastIdx , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; EVT EltVT = VT . getVectorElementType ( ) ; EVT V0VT = V0 . getValueType ( ) ; assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; EVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx /


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MFI -> hasVarSizedObjects ( ) && TRI -> needsStackRealignment (


<s> to = mips_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && mips_mode_ok_for_mov_fmt_p ( mode ) ) return <NUM_LIT> ; } dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS ; if ( from == dregs ) return mips_move_from_gpr_cost


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement


<s> Br . MaxDisp = ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI


<s> temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! isMachO ) { Name = Parser . getTok ( ) . getIdentifier ( ) ; } MCSymbol * Func = getParser ( ) . getContext


<s> SDValue <ISA_LIT>TargetLowering :: ReconstructShuffle ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; struct ShuffleSourceInfo { SDValue Vec ; unsigned MinElt = std :: numeric_limits < unsigned > :: max ( ) ; unsigned MaxElt = <NUM_LIT> ; SDValue ShuffleVec ; int WindowBase = <NUM_LIT> ; int WindowScale = <NUM_LIT> ; ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , ShuffleVec ( Vec ) { } bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = llvm :: find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) ,


<s> unsigned int i , nelt , which ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = ! target ; gcc_assert ( sel . length ( ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned int ei = sel [ i ] & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; d . perm [ i ] = ei ; perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) { d . one_operand_p = false ; break ; } for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d . perm [ i ] >= nelt ) d . perm [ i ] -= nelt ; case <NUM_LIT> : d . op1 = d . op0 ; d . one_operand_p = true ; break ; case <NUM_LIT> : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . op0 = d . op1 ; d . one_operand_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER +


<s> bool <ISA_LIT>FrameInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_WrappedRegister , S , E ) ; Op -> Reg . RegNum = RegNum ; return


<s> return ( uint8x16_t ) __builtin_aarch64_uhsubv16qi ( ( int8x16_t ) __a , ( int8x16_t )


<s> InstrToInstrs * ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , true , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs ADRPToReachingDefs ; reachedUsesToDefs ( ADRPToReachingDefs , ColorOpToReachedUses , RegToId , true ) ; computeADRP ( ADRPToReachingDefs , * <ISA_LIT>FI , MDT ) ; delete [ ] ColorOpToReachedUses ; ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , false , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs UsesToReachingDefs ; reachedUsesToDefs ( UsesToReachingDefs , ColorOpToReachedUses , RegToId , false ) ; computeOthers ( UsesToReachingDefs , ColorOpToReachedUses , * <ISA_LIT>FI , RegToId , MDT ) ; delete [ ] ColorOpToReachedUses ; if ( BasicBlockScopeOnly ) MF .


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) ->


<s> uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT>


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseEOL ( <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; return getTargetStreamer ( ) . emitFPOEndProc ( L


<s> MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New )


<s> if ( ST -> isROPI ( ) || ST -> isRWPI (


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr =


<s> for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ]


<s> SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue HiSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits


<s> } xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) xa = ix86_expand_sse_fabs ( xa , NULL ) ; ix86_sse_copysign_to_positive ( res , xa ,


<s> const char * s ; s = division ; if ( TARGET_CHECK_ZERO_DIV ) { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } return s


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { std :: string IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; if ( IDVal == <STR_LIT> ) return parseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return parseLiteralValues ( <NUM_LIT> , DirectiveID .


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> isStrongDefinitionForLinker ( ) ; return


<s> SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( VT == <STR_LIT> && InputVector . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t InputValue = InputVector . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t Res = ( InputValue >> ExtractedElt ) & <NUM_LIT> ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << Extract -> getConstantOperandVal


<s> OperandMatchResultTy parseFP32 ( SmallVectorImpl < MCParsedAsmOperand


<s> } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , LHS . getValueType ( ) ) ; } } if ( LHS . getNode ( ) ) { bool Invert = false ; if ( LHS . getOpcode ( ) == <STR_LIT> && isAllOnes ( LHS . getOperand ( <NUM_LIT> ) ) ) { Invert = true ; LHS = LHS . getOperand ( <NUM_LIT> ) ; } if ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; if ( LHS . getValueType ( ) != RHS . getValueType ( ) ) RHS = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , RHS ) ; SDValue BT = DAG . getNode ( <STR_LIT> , dl ,


<s> return MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || needsStackRealignment (


<s> if ( ST -> hasAltivec ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( ST -> is<ISA_LIT>64 ( ) )


<s> static bool ix86_additional_allocno_class_p (


<s> unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_PCS_RegMask


<s> UseSubVector = true ; } bool IsUnary ; SmallVector < SDValue , <NUM_LIT> > SrcOps ; SmallVector < int , <NUM_LIT> > SrcShuffleMask ; SDValue BC = peekThroughBitcasts ( Op ) ; if ( isTargetShuffle ( BC . getOpcode ( ) ) && getTargetShuffleMask ( BC . getNode ( ) , BC . getSimpleValueType ( ) , false , SrcOps , SrcShuffleMask , IsUnary ) ) { if ( ! UseSubVector && SrcShuffleMask . size ( ) == NumElts && SrcOps . size ( ) <= <NUM_LIT> ) { N0 = SrcOps . size ( ) > <NUM_LIT> ? SrcOps [ <NUM_LIT> ] : SDValue ( ) ; N1 = SrcOps . size ( ) > <NUM_LIT> ? SrcOps [ <NUM_LIT> ] : SDValue ( ) ; ShuffleMask . append ( SrcShuffleMask . begin ( ) , SrcShuffleMask . end ( ) ) ; } if ( UseSubVector && ( SrcShuffleMask . size ( ) == ( NumElts * <NUM_LIT> ) ) && SrcOps . size ( ) == <NUM_LIT> ) { N0 = extract128BitVector ( SrcOps [ <NUM_LIT> ] , <NUM_LIT> , DAG , SDLoc ( Op ) ) ; N1 = extract128BitVector ( SrcOps [ <NUM_LIT> ] , NumElts , DAG , SDLoc ( Op ) ) ; ArrayRef < int > Mask = ArrayRef < int > ( SrcShuffleMask ) . slice ( <NUM_LIT> , NumElts ) ; ShuffleMask . append ( Mask . begin ( ) , Mask . end ( ) ) ; } } } ; SDValue A , B ; SmallVector < int , <NUM_LIT> > LMask ; GetShuffle ( LHS , A , B , LMask ) ; SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ; GetShuffle ( RHS , C , D , RMask ) ; unsigned NumShuffles = ( LMask . empty ( ) ? <NUM_LIT> : <NUM_LIT> ) + ( RMask . empty ( ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( NumShuffles == <NUM_LIT> ) return false ; if ( LMask . empty ( ) ) { A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask . push_back ( i ) ; } if ( RMask . empty ( ) ) { C =


<s> unsigned LDiL = <STR_LIT> ; unsigned T = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { if ( isUInt < <NUM_LIT> > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( Amount ) ; } else { BuildMI ( MBB , I , DL , get ( LDi4 ) , T ) . addImm ( Amount ) ; } BuildMI ( MBB , I , DL , get ( ADDR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } else if ( isUInt < <NUM_LIT> > ( - Amount ) ) { if ( isUInt < <NUM_LIT> > ( - Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( - Amount ) ; } else


<s> int getMaxSVECSFrameIndex ( ) const { return MaxSVECSFrameIndex


<s> void <ISA_LIT>MCExpr :: PrintImpl ( raw_ostream & OS


<s> void <ISA_LIT>ExpandPseudo :: CMSERestoreFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , SmallVectorImpl < unsigned > & AvailableRegs ) { if ( STI -> hasV8_1MMainlineOps ( ) ) CMSERestoreFPRegsV81 ( MBB , MBBI , DL


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) <


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> static bool applyEXT ( MachineInstr & MI , ShuffleVectorPseudo & MatchInfo ) { MachineIRBuilder MIRBuilder ( MI ) ; auto Cst = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , MatchInfo .


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; Imm = SplatValue ; return


<s> void <ISA_LIT>AsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( ! TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return ; unsigned Flags = <NUM_LIT> ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( <STR_LIT> ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( <STR_LIT> ) ) ) if ( Sign -> getZExtValue

( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ;


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; int RegisterFileMoveCost = <NUM_LIT> ; if ( Index == - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { assert ( isa < FixedVectorType > ( Val ) && <STR_LIT> ) ; Align VecAlign = DL . getPrefTypeAlign ( Val ) ; Align SclAlign = DL . getPrefTypeAlign ( ScalarType ) ; if ( Opcode == Instruction :: ExtractElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { if ( Opcode == Instruction :: ExtractElement && ScalarType -> getScalarSizeInBits ( ) == <NUM_LIT> && cast < FixedVectorType > ( Val ) -> getNumElements ( ) > <NUM_LIT> ) return <NUM_LIT> ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned SizeInBits = LT . second . getSizeInBits ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index %


<s> unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ; SDValue Ops1 [ <NUM_LIT> ] = { Chain . getValue ( <NUM_LIT> ) , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> ,


<s> auto_vec < rtx_insn * > control_flow_insns ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( TARGET_AVX512F ) replace_constant_pool_with_broadcast ( insn ) ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( get_attr_avx_partial_xmm_update ( insn ) != AVX_PARTIAL_XMM_UPDATE_TRUE ) continue ; if ( ! v4sf_const0 ) v4sf_const0 = gen_reg_rtx ( V4SFmode ) ; rtx src = SET_SRC ( set ) ; rtx dest = SET_DEST ( set ) ; machine_mode dest_mode = GET_MODE ( dest ) ; rtx zero ; machine_mode dest_vecmode ; if ( dest_mode == E_SFmode ) { dest_vecmode = V4SFmode ; zero = v4sf_const0 ; } else { dest_vecmode = V2DFmode ; zero = gen_rtx_SUBREG ( V2DFmode , v4sf_const0 , <NUM_LIT> ) ; } src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx ( dest_vecmode ) ; set = gen_rtx_SET ( vec , src ) ; set_insn = emit_insn_before ( set , insn ) ; df_insn_rescan ( set_insn ) ; if ( cfun -> can_throw_non_call_exceptions ) { rtx note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) { control_flow_insns . safe_push ( set_insn ) ; add_reg_note ( set_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } } src = gen_rtx_SUBREG ( dest_mode , vec , <NUM_LIT> ) ; set = gen_rtx_SET ( dest , src ) ; PATTERN ( insn ) = set ; INSN_CODE ( insn ) = - <NUM_LIT> ; recog_memoized ( insn ) ; df_insn_rescan ( insn ) ; bitmap_set_bit ( convert_bbs , bb -> index ) ; } } if ( v4sf_const0 ) { calculate_dominance_info ( CDI_DOMINATORS ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; bb = nearest_common_dominator_for_set ( CDI_DOMINATORS , convert_bbs ) ; while ( bb -> loop_father -> latch != EXIT_BLOCK_PTR_FOR_FN ( cfun ) ) bb = get_immediate_dominator ( CDI_DOMINATORS , bb -> loop_father -> header ) ; set = gen_rtx_SET ( v4sf_const0 , CONST0_RTX ( V4SFmode ) ) ; insn = BB_HEAD ( bb ) ; while ( insn && ! NONDEBUG_INSN_P ( insn ) ) { if ( insn == BB_END ( bb ) ) { insn = NULL ; break ; } insn = NEXT_INSN ( insn ) ; } if ( insn == BB_HEAD ( bb ) ) set_insn = emit_insn_before ( set , insn ) ; else set_insn = emit_insn_after ( set , insn ? PREV_INSN ( insn ) : BB_END ( bb ) ) ; df_insn_rescan ( set_insn ) ; loop_optimizer_finalize ( ) ; if ( ! control_flow_insns . is_empty ( ) ) { free_dominance_info ( CDI_DOMINATORS ) ; unsigned int i ; FOR_EACH_VEC_ELT ( control_flow_insns , i , insn ) if ( control_flow_insn_p ( insn ) ) { bb = BLOCK_FOR_INSN ( insn ) ; split_block ( bb , insn )


<s> const MCOperand & M0 = MI . getOperand ( OpIdx ) ; const MCOperand & M1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( M0 . getReg ( ) ) ; unsigned Qm = CTX . getRegisterInfo ( ) -> getEncodingValue ( M1 . getReg ( ) ) ; assert ( Qm < <NUM_LIT> &&


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> else if ( ( thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && thumb_legitimate_offset_p ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == STACK_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) + GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == FRAME_POINTER_REGNUM || REGNO ( XEXP ( x , <NUM_LIT> ) ) == ARG_POINTER_REGNUM || ( REGNO ( XEXP ( x , <NUM_LIT> ) ) >= FIRST_VIRTUAL_REGISTER && REGNO ( XEXP ( x , <NUM_LIT> ) ) <= LAST_VIRTUAL_POINTER_REGISTER ) ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_SIZE ( mode ) == <NUM_LIT> && SYMBOL_REF_P ( x ) && CONSTANT_POOL_ADDRESS_P ( x ) && ! arm_disable_literal_pool && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( ! GVA ) return TM . getCodeModel ( ) == CodeModel :: Small ; if ( GVA -> getSection ( ) . startswith ( <STR_LIT> ) ) return false ; if ( TM . getCodeModel ( ) == CodeModel :: Small ) return true ; if ( GVA -> hasLocalLinkage ( ) ) return


<s> if ( ! isSplatVector ( V . getNode ( ) ) ) return SDValue ( ) ; Ld = V . getOperand ( <NUM_LIT> ) ; if ( ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Ld = Sc . getOperand ( <NUM_LIT> ) ; if ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) return SDValue ( ) ; break ; } } if ( ! <STR_LIT> ( Ld . getNode ( ) ) ) return SDValue ( ) ; bool Is256 = VT . getSizeInBits ( ) == <NUM_LIT> ; bool Is128 = VT . getSizeInBits ( ) == <NUM_LIT> ; unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; if ( Is256 && ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) ) return Ld ; if ( Is128 && ( ScalarSize == <NUM_LIT> ) ) return Ld ; if ( Subtarget -> hasAVX2 ( ) && Ld . getValueType ( ) .


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> Cond = ( <STR_LIT> ) cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( N ) ; if ( isZeroVector ( Op1 ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT

, Op0 , N -> getOperand ( <NUM_LIT> ) ) ;


<s> rs6000_gen_section_name ( & xcoff_tbss_section_name , main_input_filename , <STR_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_quoted_string ( asm_out_file , main_input_filename ) ; fputc ( '\n' , asm_out_file ) ; if ( write_symbols != NO_DEBUG ) switch_to_section ( private_data_section ) ; switch_to_section ( toc_section ) ; switch_to_section ( text_section ) ; if ( profile_flag ) fprintf ( asm_out_file


<s> unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ( Rt & <NUM_LIT> ) || Rt == <NUM_LIT> || Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx


<s> return ( ( qword ) ( vec_msum ( vec_and ( ( vec_short8 ) ( a ) , ( ( vec_short8 ) { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , -

<NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ) , ( vec_short8 ) ( b ) , ( vec_int4 ) ( c ) ) ) ) ;


<s> bool isCheapToSpeculateCtlz ( ) const


<s> MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; return


<s> MCStreamer :: EmitWinEHHandlerData ( ) ; MCWin64EHUnwindEmitter :: EmitUnwindInfo ( * this


<s> unsigned ElementWidth = StringSwitch < unsigned > ( Kind . lower ( ) ) . Case ( <STR_LIT> , - <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! ElementWidth ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEPredicateVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; return


<s> void addImmShiftOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> if ( AI -> getOperation ( ) != AtomicRMWInst :: Min && AI -> getOperation ( ) != AtomicRMWInst :: Max && AI -> getOperation ( ) != AtomicRMWInst :: UMin && AI -> getOperation ( ) != AtomicRMWInst :: UMax ) { return AtomicExpansionKind :: None ; } } } if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt ::

None ) return AtomicExpansionKind :: CmpXChg ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT>

, & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ;


<s> static SDValue combinePMULH ( SDValue Src , EVT VT , const SDLoc & DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Src . getOpcode ( ) != <STR_LIT> || Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT InVT = Src . getValueType ( ) ; if ( InVT . getVectorElementType ( ) . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; APInt ShiftAmt ; if ( ! <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) , ShiftAmt ) || ShiftAmt != <NUM_LIT> ) return SDValue ( ) ; SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand


PM . add ( createThumb2ITBlockPass ( ) ) ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( )


<s> const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; for ( const auto & I : CSI ) { unsigned Reg = I . getReg ( ) ; unsigned RegNum = TRI ->


<s> MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( <NUM_LIT> ) ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) . getReg ( <NUM_LIT> ) ; auto OffsetReg = MIRBuilder . buildConstant ( s64 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack (


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT>


<s> __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v2di ( ( __builtin_aarch64_simd_di * )


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) ,


<s> inline bool isV8EligibleForIT ( InstrType * Instr ) { switch ( Instr -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsCPSRDead ( Instr ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBUtils -> clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; JumpTableEntryIndices . clear ( ) ; JumpTableUserIndices . clear ( ) ; ImmBranches . clear ( ) ; PushPopMIs . clear


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT>


<s> vrev32q_s16 ( int16x8_t a ) { return __builtin_shuffle ( a , ( uint16x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> return dword ? <NUM_LIT> : <NUM_LIT>


<s> case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx


<s> return ( __m512d ) __builtin_ia32_sqrtpd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8


<s> if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ! isFloatingPointZero ( RHS ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap


<s> return ( __mmask8 ) __builtin_ia32_fpclassps256_mask ( ( __v8sf


<s> static unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ; for ( unsigned LI : MBB -> liveins ( ) ) { if ( LI < <STR_LIT> || LI >


<s> if ( CommentStream && ( Op . getImm ( ) > <NUM_LIT> || Op . getImm ( ) < - <NUM_LIT> ) ) * CommentStream << format ( <STR_LIT> PRIX64 <STR_LIT> , ( uint64_t ) Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT>


<s> <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs


<s> if ( GET_MODE ( cr ) == CCmode ) emit_insn ( gen_isel_signed ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; else emit_insn ( gen_isel_unsigned ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return


<s> if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) { SDLoc DL ( N


<s> assert ( Zeros < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CRRegs [ <NUM_LIT> - Zeros ] ) ) ; return MCDisassembler ::


<s> APInt UndefBits ( CstSizeInBits , <NUM_LIT> ) ; APInt MaskBits ( CstSizeInBits , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; unsigned BitOffset = i * CstEltSizeInBits ; if ( isa < UndefValue > ( COp ) ) { UndefBits . setBits ( BitOffset , BitOffset + CstEltSizeInBits ) ; continue ; } MaskBits . insertBits ( cast < ConstantInt > ( COp ) -> getValue ( ) , BitOffset ) ; } for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { unsigned BitOffset = i


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL


<s> static unsigned getFixupKindNumBytes ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : case FK_SecRel_2 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const MachineFrameInfo * MFI = MF . getFrameInfo


<s> SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; unsigned StoreAddrReg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false


<s> unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno -- > <NUM_LIT> ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ,


<s> static void printRegs ( formatted_raw_ostream & OS , ListSeparator & LS , int First ,


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO .


<s> if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) )


<s> static bool isTransformable ( const MachineInstr * MI


<s> else if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) )


<s> MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , <NUM_LIT> ) ) ; int GPRSize = FuncInfo -> getVarArgsGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , PtrVT ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , GRTop , DAG . getConstant ( GPRSize , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , <NUM_LIT> ) ) ; } int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop , VRTopAddr ; VRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; VRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsFPRIndex ( ) , PtrVT ) ; VRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , VRTop , DAG . getConstant ( FPRSize , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , VRTop , VRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , <NUM_LIT> ) ) ; } SDValue GROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - GPRSize , DL , <STR_LIT> ) , GROffsAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , <NUM_LIT> ) ) ; SDValue VROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - FPRSize , DL

, <STR_LIT> ) , VROffsAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> static SDValue PerformXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( Subtarget -> hasCMov ( ) ) { SDValue RV = performIntegerAbsCombine ( N , DAG ) ; if ( RV . getNode ( ) ) return RV ; } if ( ! Subtarget -> hasBMI ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; assert ( Subtarget -> hasBMI ( ) && <STR_LIT> ) ; SDValue N0 = N ->


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == <STR_LIT> || VT == <STR_LIT> || VT ==


<s> if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> return vabsq_f32 ( __a ) <= vabsq_f32 (


<s> return ; } if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val ) ; if ( Reg && Reg -> Readable && Reg -> haveFeatures (

STI . getFeatureBits ( ) ) ) O << Reg -> Name ;


<s> static void AnalyzeRetResult ( CCState & State , const SmallVectorImpl <


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( Subtarget . hasCDI ( ) ) return LowerVectorCTLZ_AVX512CDI ( Op , DAG ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; return LowerVectorCTLZInRegLUT ( Op , DL , Subtarget , DAG


<s> inline const MachineInstrBuilder & addRegReg ( const MachineInstrBuilder & MIB , unsigned Reg1 , bool isKill1 , unsigned Reg2 , bool isKill2 ) { return MIB . addReg ( Reg1 , false , false , isKill1 ) . addImm ( <NUM_LIT> ) . addReg ( Reg2 , false

, false , isKill2 ) . addImm ( <NUM_LIT> ) ;


<s> MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB ( MBBOpnd ) ; if ( Br -> hasDelaySlot ( ) ) { assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II (


<s> static unsigned GetScratchRegister ( bool Is64Bit , const MachineFunction & MF ) { if ( Is64Bit ) { return <STR_LIT> ; } else { CallingConv :: ID CallingConvention = MF . getFunction ( ) -> getCallingConv ( ) ; bool IsNested = HasNestArgument ( & MF ) ; if ( CallingConvention == CallingConv :: <ISA_LIT>_FastCall ) { if ( IsNested ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return - <NUM_LIT> ; } else { return <STR_LIT> ; } } else { if ( IsNested ) return


<s> ArrayRef < int > StubMask = Mask . slice ( ZeroLo , Len ) ; if ( ! isUndefOrInRange ( StubMask , <NUM_LIT> , NumElts ) && ! isUndefOrInRange ( StubMask , NumElts , <NUM_LIT> * NumElts ) ) return SDValue ( ) ; SDValue Res = Mask [ ZeroLo ] < ( int ) NumElts ? V1 : V2 ; Res = DAG . getBitcast ( <STR_LIT> , Res ) ; if ( ZeroLo == <NUM_LIT> ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * ZeroHi , DL , <STR_LIT> ) ) ; } else if ( ZeroHi == <NUM_LIT> ) { unsigned Shift = Mask [ ZeroLo ] % NumElts ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * ZeroLo , DL , <STR_LIT> ) ) ; } else if ( ! Subtarget . hasSSSE3 ( ) ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Shift += Mask [ ZeroLo ] % NumElts ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * ZeroLo , DL , <STR_LIT> ) ) ; } else return SDValue ( ) ; return DAG . getBitcast (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRrr ( SDValue Addr , SDValue & R1 , SDValue & R2 ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 =


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg

) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) )


<s> CCInfo . AnalyzeReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold ) ? RetCC_<ISA_LIT>_Cold : RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister (


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info

, TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) {


<s> if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | !


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == std :: numeric_limits <


<s> return ( __m512i ) __builtin_ia32_vcvttph2uw512_mask_round ( __B , ( __v32hi ) _mm512_setzero_si512 ( ) ,


<s> void addModImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode


<s> if ( IN_REGNO_P ( regno ) ) return <NUM_LIT> + regno - IN_REG ( <NUM_LIT> ) ; else if ( LOC_REGNO_P ( regno ) ) return <NUM_LIT> + current_frame_info . n_input_regs +


<s> return __builtin_aarch64_floatv4siv4sf (


<s> return ( __m64 ) __builtin_ia32_pavgb ( ( __v8qi


<s> SMLoc getStartLoc ( ) const { return StartLoc


<s> switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else


<s> const char * getPassName ( ) const override { return


<s> bool <ISA_LIT>TargetLowering :: isFPExtFree ( EVT DestVT , EVT SrcVT ) const { assert ( DestVT . isFloatingPoint ( ) && SrcVT . isFloatingPoint (


<s> xops [ <NUM_LIT> ] = reg2 ; xops [ <NUM_LIT> ] = GEN_INT ( - probe_interval ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> static MachineInstr * FuseTwoAddrInst ( MachineFunction & MF , unsigned Opcode , ArrayRef < MachineOperand > MOs , MachineBasicBlock :: iterator InsertPt , MachineInstr & MI , const TargetInstrInfo & TII ) { MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI . getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; addOperands ( MIB , MOs ) ; unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . addOperand ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand (


<s> rtx fnaddr , mem , a_tramp ; const int tramp_code_sz = <NUM_LIT> ; rtx temp = convert_memory_address ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; emit_block_move ( gen_rtx_MEM ( BLKmode , temp ) , assemble_trampoline_template ( ) , GEN_INT ( tramp_code_sz ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode ,


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) mask |= <NUM_LIT> << regno ; fprintf ( file , <STR_LIT> , mask ) ; if ( dwarf2out_do_frame ( ) ) { const char * label = dwarf2out_cfi_label ( ) ; int offset = <NUM_LIT> ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; -- regno ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) dwarf2out_reg_save ( label , regno , offset -= <NUM_LIT> ) ; dwarf2out_reg_save ( label , PC_REGNUM , offset -= <NUM_LIT> ) ; dwarf2out_reg_save ( label , FRAME_POINTER_REGNUM , offset -= <NUM_LIT> ) ; dwarf2out_reg_save ( label , ARG_POINTER_REGNUM , offset -= <NUM_LIT> ) ; dwarf2out_def_cfa ( label , FRAME_POINTER_REGNUM , - ( offset


<s> __cpuid ( registers , value ) ; * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; __asm { mov eax , value cpuid mov esi , rEAX mov dword ptr [ esi ] , eax mov esi , rEBX mov dword ptr [ esi ] , ebx mov esi , rECX mov

dword ptr [ esi ] , ecx mov esi , rEDX mov dword ptr [ esi ] , edx }


<s> uint64_t EncVal = Imm ; return ( EncVal << <NUM_LIT> ) | (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFP<ISA_LIT>v8Base ( ) && ! ST -> hasVFP2Base ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ST -> hasMVEIntegerOps (


<s> return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src )


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return


<s> return new <ISA_LIT>AsmBackend ( T , MRI , TT , CPU , Options .


<s> if ( isTargetDarwin ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false


<s> } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; else return RegNum ; if ( is<ISA_LIT>64 ( ) && RegNum


<s> static DecodeStatus DecodeQPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; RegNo >>= <NUM_LIT> ; unsigned Register = QPRDecoderTable


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit )


<s> MCAsmParser & Parser = getParser ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SMLoc S = getLexer ( ) . getLoc ( ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = parseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success


<s> Zero = DAG . getNode ( <STR_LIT> , DL , EltVT , Zero ) ; AllOnes = DAG . getNode ( <STR_LIT> , DL , EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ]


<s> if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; return outliner ::


<s> SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( getPointerTy ( ) ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; ( void )