<s> int sh_contains_memref_p ( rtx insn ) { return for_each_rtx ( & PATTERN ( insn ) , & sh_contains_memref_p_1


<s> virtRegs . insert ( LR -> virtRegs . begin ( )


<s> bool isUnsignedOffset ( ) const { if ( ! isImm ( ) ) return false ; if ( isa < MCSymbolRefExpr > ( Imm . Val ) ) return true ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val )


<s> bool isHWRegsAsm ( ) const { assert ( ( Kind == k_Register ) && <STR_LIT>


<s> static void do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched (


<s> BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg =


<s> static bool isIntrinsicInline ( Function * F ) { return std :: binary_search ( std :: begin ( IntrinsicInline ) , std :: end ( IntrinsicInline ) , F ->


<s> SmallVector < int , <NUM_LIT> > MaskHigh ; SmallVector < int , <NUM_LIT> > MaskLow ; SmallVector < int , <NUM_LIT> > LowHighMask [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > MaskHighTemp ; SmallVector < int , <NUM_LIT> > MaskLowTemp ; createUnpackShuffleMask ( VT , MaskLow , true , false ) ; createUnpackShuffleMask ( VT , MaskHigh , false , false ) ; createUnpackShuffleMask ( HalfVT , MaskLowTemp , true , false ) ; createUnpackShuffleMask ( HalfVT , MaskHighTemp , false , false ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskLowTemp , LowHighMask [ <NUM_LIT> ] ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskHighTemp , LowHighMask [ <NUM_LIT> ] ) ; Value * IntrVec [ <NUM_LIT> ] ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [


<s> vld1q_f64 ( const float64_t * a ) { return __builtin_aarch64_ld1v2df ( ( const __builtin_aarch64_simd_df * ) a


<s> for ( i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && GET_CODE ( SET_DEST ( part ) ) == REG ) ? SET_SRC ( part ) : part ) ) ) return <NUM_LIT> ; } return reg


<s> v [ <NUM_LIT> ] = * op ; vec_cst = gen_rtx_CONST_VECTOR ( V1TImode , gen_rtvec_v ( <NUM_LIT> , v ) ) ; } if ( ! standard_sse_constant_p ( vec_cst , V1TImode ) ) { start_sequence ( ) ; vec_cst = validize_mem ( force_const_mem ( V1TImode , vec_cst ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } emit_insn_before ( gen_move_insn ( tmp , vec_cst ) , insn ) ; * op = tmp ; } else { gcc_assert ( SUBREG_P ( * op )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( i - <NUM_LIT>


<s> SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VTs , TrueV ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands (


<s> MCELFStreamer :: EmitValueImpl ( Value , Size ,


<s> bool <ISA_LIT>ElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |=


<s> switch ( qimode ) { case E_V16QImode : himode = V8HImode ; gen_il = gen_vec_interleave_lowv16qi ; gen_ih = gen_vec_interleave_highv16qi ; break ; case E_V32QImode : himode = V16HImode ; gen_il = gen_avx2_interleave_lowv32qi ; gen_ih = gen_avx2_interleave_highv32qi ; break ; case E_V64QImode : himode = V32HImode ; gen_il = gen_avx512bw_interleave_lowv64qi ; gen_ih = gen_avx512bw_interleave_highv64qi ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case MULT : op2_l = gen_reg_rtx ( qimode ) ; op2_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op2_l , op2 , op2 ) ) ; emit_insn ( gen_ih ( op2_h , op2 , op2 ) ) ; op1_l = gen_reg_rtx ( qimode ) ; op1_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op1_l , op1 , op1 ) ) ; emit_insn ( gen_ih ( op1_h , op1 , op1 ) ) ; full_interleave = qimode == V16QImode ; break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; if ( GET_MODE_CLASS ( GET_MODE ( op2 ) ) == MODE_VECTOR_INT ) { rtx tmp = force_reg ( qimode ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; MF -> getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( * MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF ->


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa (


<s> uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT> ) | ( ( Disp & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Disp


<s> dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = <NUM_LIT> ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true )


<s> void EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const override { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; if ( Opcode == TargetOpcode :: COPY_TO_REGCLASS ) return ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { case <NUM_LIT> : if ( IsLittleEndian ) { OS << ( char ) ( Bits ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; } else { OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits ) ; } break ; case <NUM_LIT> : if ( IsLittleEndian ) { OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char ) ( Bits >> <NUM_LIT> ) ; OS << ( char )


<s> static DecodeStatus DecodeVCVTImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler :: Success


<s> __inline__ static void sh_media_NOP (


<s> else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( i + <NUM_LIT> )


<s> __builtin_ia32_scatterpfdpd ( ( __mmask8 ) <NUM_LIT> , ( __v8si ) index ,

( long long const * ) addr , scale , hint ) ;


<s> if ( CP -> isMachineConstantPoolEntry ( ) ) Result = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlign ( ) ) ; else Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlign ( )


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl ,


<s> <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) : CurDAG -> getTargetConstant (


<s> assert ( TID . getNumDefs ( ) == <NUM_LIT> && NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; ElemSize esize = Opcode == <STR_LIT> ? ESize8 : ( Opcode == <STR_LIT> ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd (


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment = <NUM_LIT> ; MaxInlineSizeThreshold = <NUM_LIT>


<s> bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; int64_t Offset ; if ( TII -> getMemOpBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( & MI ) ; } PrevBaseReg = BaseReg ; } else PrevBaseReg = <NUM_LIT> ; } } return


<s> scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode ,


<s> Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT>


<s> unsigned BlockCount = <NUM_LIT> ; const unsigned InspectionLimit = <ISA_LIT>AvoidSFBInspectionLimit ; for ( auto PBInst = std :: next ( MachineBasicBlock :: reverse_iterator ( LoadInst ) ) , E = LoadInst -> getParent ( ) -> rend ( ) ; PBInst != E ; ++ PBInst ) { BlockCount ++ ; if ( BlockCount >= InspectionLimit ) break ; MachineInstr & MI = * PBInst ; if ( MI . getDesc ( ) . isCall ( ) ) return PotentialBlockers ; PotentialBlockers . push_back ( & MI ) ; } if ( BlockCount < InspectionLimit ) { MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; int LimitLeft = InspectionLimit - BlockCount ; for ( MachineBasicBlock :: pred_iterator PB = MBB -> pred_begin ( ) , PE = MBB -> pred_end ( ) ; PB != PE ; ++ PB ) { MachineBasicBlock * PMBB = * PB ; int PredCount


<s> unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> ( EncodedImm ,


<s> static inline unsigned getAM4ModeImm ( AMSubMode SubMode ) { return ( int )


<s> SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; bool CanMergeOpc = Opc == MI -> getOpcode ( ) ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( ! CanMergeOpc ) { bool IsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( Opc , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) Opc ? <NUM_LIT> : <NUM_LIT> ) ; CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode ( MI -> getOpcode ( ) ) ; } if ( CanMergeOpc && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI -> mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool MIIsUnscaled = isUnscaledLdSt ( MI ) ; if ( ! inBoundsForPair ( MIIsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] && ! ( MI -> mayLoad ( ) && UsedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) && ! mayAlias ( MI , MemInsns , TII ) ) { Flags . setMergeForward ( false ) ; return MBBI ; } if ( ! ModifiedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] && ! ( MayLoad && UsedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] ) && ! mayAlias ( FirstMI , MemInsns , TII ) ) { Flags . setMergeForward ( true ) ; return MBBI ; } } } if ( MI -> isCall ( ) ) return E ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return


<s> if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT>


<s> return Kind == Memory && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size ||


<< <NUM_LIT> ) | __C , _MM_FROUND_CUR_DIRECTION ) ;


<s> size = ( size + UNITS_PER_WORD - <NUM_LIT> ) & ~ ( UNITS_PER_WORD - <NUM_LIT> ) ; if ( size || frame_pointer_needed ) size += STARTING_FRAME_OFFSET ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; ++ i ) continue ; size += i * UNITS_PER_WORD ; } for ( i = <NUM_LIT> , j = frame_pointer_needed ? <NUM_LIT> : <NUM_LIT> ; i >= j ; i -- ) if ( df_regs_ever_live_p ( i ) ) size += UNITS_PER_WORD ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { freg_saved = <NUM_LIT> ; size += <NUM_LIT> ; } if ( freg_saved ) { size = ( size + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( fregs_live ) * fregs_live = <NUM_LIT> ; } size += crtl


<s> int InputIdx0 = - <NUM_LIT> , InputIdx1 = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Ops . size ( ) ; i < e ; ++ i ) { SDValue BC = peekThroughBitcasts ( Ops [ i ] ) ; if ( Input0 && BC == peekThroughBitcasts ( Input0 ) ) InputIdx0 = i ; if ( Input1 && BC == peekThroughBitcasts ( Input1 ) ) InputIdx1 = i ; } if ( Input0 && InputIdx0 < <NUM_LIT> ) { InputIdx0 = SrcOpIndex ; Ops [ SrcOpIndex ] = Input0 ; } if ( Input1 && InputIdx1 < <NUM_LIT> ) { InputIdx1 = Ops . size ( ) ; Ops . push_back ( Input1 ) ; } assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpMask . size ( ) ) && <STR_LIT> ) ; unsigned RootMaskSizeLog2 = countTrailingZeros ( RootMask . size ( ) ) ; unsigned OpMaskSizeLog2 = countTrailingZeros ( OpMask . size ( ) ) ; unsigned MaskWidth = std :: max < unsigned > ( OpMask . size ( ) , RootMask . size ( ) ) ; unsigned RootRatio = std :: max < unsigned > ( <NUM_LIT> , OpMask . size ( ) >> RootMaskSizeLog2 ) ; unsigned OpRatio = std :: max < unsigned > ( <NUM_LIT> , RootMask . size ( ) >> OpMaskSizeLog2 ) ; assert ( ( RootRatio == <NUM_LIT> || OpRatio == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( MaskWidth ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootRatio ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpRatio ) && <STR_LIT> ) ; unsigned RootRatioLog2 = countTrailingZeros ( RootRatio ) ; unsigned OpRatioLog2 = countTrailingZeros ( OpRatio ) ; SmallVector < int , <NUM_LIT> > Mask ( MaskWidth , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i


<s> auto * Exp = new <STR_LIT> ( S . getContext ( ) , std :: move ( RegInfo ) , std :: move ( InstInfo )


<s> static <ISA_LIT>Operand * CreateShiftedImmediate ( <STR_LIT> ShTy , unsigned SrcReg , unsigned ShiftImm , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftedImmediate ) ; Op -> RegShiftedImm . ShiftTy = ShTy ; Op -> RegShiftedImm . SrcReg = SrcReg ; Op -> RegShiftedImm . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getScatterVecOpcode ( IsScaled , IsSigned ,


<s> x = strip_offset_and_salt ( x , & offset


<s> if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return


<s> if ( ! isa < ConstantSDNode > ( K1 ) || ! isa < ConstantSDNode > ( K2 ) ) return SDValue ( ) ; int64_t Val1 = cast < ConstantSDNode > ( K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; int64_t NegVal = std :: min ( Val1 , Val2 ) ; if ( ! ( ( Val1 > Val2 && isLTorLE ( CC1 ) ) || ( Val1 < Val2 && isLTorLE ( CC2 ) ) ) || ! isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) return SDValue ( ) ; uint64_t K = PosVal ; SDLoc dl ( Op ) ; if ( Val1 == ~ Val2 ) return DAG . getNode ( <STR_LIT> , dl , VT , V2Tmp , DAG . getConstant ( countTrailingOnes ( K ) , dl , VT ) ) ; if ( NegVal == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V2Tmp , DAG . getConstant (


<s> return parseAddress ( Operands , BDVMem


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( EVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset )

, MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES (

) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ;


<s> if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; } case CallingConv :: C : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS :


<s> return __builtin_loongson_psllw_u ( s


<s> } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) .

addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ;


<s> assert ( ( VCI . Opcode == <STR_LIT> || VCI . Opcode == <STR_LIT> || VCI . Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( VCI . VecVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned OpVal : VCI . OpVals ) Ops . push_back ( CurDAG -> getTargetConstant ( OpVal , DL , <STR_LIT> ) ) ; SDValue Op = CurDAG -> getNode ( VCI . Opcode , DL , VCI . VecVT , Ops ) ; if ( VCI . VecVT == VT . getSimpleVT ( ) ) ReplaceNode ( Node , Op . getNode ( ) ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue BitCast = CurDAG -> getNode ( <STR_LIT> ,


<s> if ( ReplacedSplat != SDValue ( ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getIntPtrConstant ( NumElts ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG

. getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { s64 ,


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> bool NoImplicitFloatOps = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget . hasSSE2 ( ) ) { SDValue SclToVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Node -> getChain ( ) , SclToVec , Node -> getBasePtr ( ) } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , Node -> getMemOperand ( ) ) ; if ( IsSeqCst ) Chain = emitLockedStackOp ( DAG , Subtarget , Chain , dl ) ; return Chain ; } } SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , Node -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getMemOperand ( ) ) ; return Swap . getValue


<s> alias_set_type get_TOC_alias_set ( void ) { if ( set == - <NUM_LIT> ) set = new_alias_set (


<s> bool <ISA_LIT>SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF


<s> SDValue <ISA_LIT>TargetLowering :: withTargetFlags ( SDValue Op , unsigned TF , SelectionDAG & DAG ) const { if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( GA ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , TF ) ; if ( const ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( CP -> getConstVal ( ) , CP -> getValueType ( <NUM_LIT> ) , CP -> getAlign ( ) , CP -> getOffset ( ) , TF ) ; if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ; llvm_unreachable ( <STR_LIT>


<s> rtx mem = load_p ? operands [ <NUM_LIT> ] : operands [ <NUM_LIT> ] ; if ( optimize == <NUM_LIT> || ! flag_schedule_insns_after_reload ) return ! satisfies_constraint_Da (


<s> OffsetRegNum = TryParseRegister ( ) ; if ( OffsetRegNum != - <NUM_LIT> ) { OffsetIsReg = true ; E = CurLoc ; } } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount , E ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted = true ; } } else { const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( Offset


<s> static unsigned computeReturnSaveOffset ( const <ISA_LIT>Subtarget & STI ) { if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64 ( ) ? <NUM_LIT>


<s> if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode =


<s> } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS ->


<s> if ( ! isNullConstant ( N1 ) ) return SDValue ( ) ; EVT VTy = N0 . getValueType ( ) ; if ( ! VTy . isVector ( ) ) return SDValue ( ) ; EVT EltTy = VTy . getVectorElementType ( ) ; if ( EltTy != <STR_LIT> && EltTy != <STR_LIT> && EltTy != <STR_LIT>


<s> else if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( addr , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op


<s> assert ( Op . getValueType ( ) . isScalableVector ( ) && isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ; if ( isTypeLegal ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { unsigned NumOperands = Op -> getNumOperands ( ) ; assert ( NumOperands > <NUM_LIT> && isPowerOf2_32 ( NumOperands ) && <STR_LIT> ) ; if ( NumOperands == <NUM_LIT> ) return Op ; SmallVector < SDValue > ConcatOps ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; while ( ConcatOps . size ( ) > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> , E = ConcatOps . size ( ) ; I != E ; I += <NUM_LIT> ) { SDValue V1 = ConcatOps [ I ] ; SDValue V2 = ConcatOps [ I + <NUM_LIT> ] ; EVT SubVT = V1 . getValueType ( ) ; EVT PairVT = SubVT . getDoubleNumVectorElementsVT ( * DAG . getContext ( ) ) ; ConcatOps [ I / <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , PairVT , V1 , V2 ) ; } ConcatOps . resize ( ConcatOps . size ( ) / <NUM_LIT>


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSWindows ( ) ) { MAI = new <ISA_LIT>MCAsmInfoCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; MachineLocation Dst ( MachineLocation ::


<s> Streamer . EmitCodeAlignment ( <NUM_LIT> ) ; Streamer . EmitDataRegion ( MCDR_DataRegion ) ; for ( EntryVecTy :: const_iterator I = Entries . begin ( ) , E = Entries . end ( ) ; I != E ; ++ I ) { Streamer . EmitLabel ( I -> first ) ; Streamer . EmitValue ( I ->


<s> assert ( MF && <STR_LIT> ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isDarwinABI ( ) ) return nullptr ; if ( ! TM . is<ISA_LIT>64 ( ) ) return nullptr ; if ( MF -> getFunction ( ) -> getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) .


<s> bool Is256 = VT . getSizeInBits ( ) == <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) == <NUM_LIT> || Is256 ) && <STR_LIT> ) ; SDValue V = Op ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( Is256 && ! ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) return false ; if ( Is256 ) V = V . getOperand ( <NUM_LIT> ) ; if ( ! V . hasOneUse ( ) ) return false ; if ( V . getOpcode ( ) != <STR_LIT> ) return false ; unsigned ScalarSize = V . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; if ( ScalarSize != <NUM_LIT> && ScalarSize != <NUM_LIT> ) return false ; if ( ! Is256 && ScalarSize == <NUM_LIT> ) return false ; V = V . getOperand ( <NUM_LIT> ) ; if ( ! MayFoldLoad ( V ) ) return false ; Op = V ; return true


<s> else EmitGlobalConstant ( MF -> getDataLayout ( ) , MCPE . Val . ConstVal ) ; return ; } switch ( Opc ) { case <STR_LIT> : LowerPATCHABLE_FUNCTION_ENTER ( * MI ) ; return ; case <STR_LIT> : LowerPATCHABLE_FUNCTION_EXIT ( * MI ) ; return ; case <STR_LIT> : LowerPATCHABLE_TAIL_CALL ( * MI ) ; return ; } if ( EmitJalrReloc && ( MI -> isReturn ( ) || MI -> isCall ( ) || MI -> isIndirectBranch ( ) ) ) { emitDirectiveRelocJalr ( * MI , OutContext , TM , * OutStreamer , * Subtarget ) ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isBundle ( )


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( const GlobalVariable * GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( false ) ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = <NUM_LIT> ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; } } return false


<s> Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( )

. emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) ) ;


<s> static DecodeStatus DecodeVLDST4Instruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT>


<s> __v2df c ; c = vec_sqrt ( ( __v2df ) _mm_set1_pd ( __B [ <NUM_LIT> ] ) ) ; return ( __m128d ) _mm_setr_pd ( c [ <NUM_LIT> ] ,


<s> case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op ,


<s> llvm :: next ( MachineBasicBlock :: instr_iterator ( I . Br ) ) -> setIsInsideBundle ( false ) ; I . Br -> eraseFromParent ( ) ; return ; } assert ( I . Br -> isConditionalBranch ( ) && <STR_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MF -> insert ( llvm :: next ( MachineFunction :: iterator ( MBB ) ) , NewMBB ) ; MBB -> removeSuccessor ( Tgt ) ; MBB -> addSuccessor ( NewMBB ) ; NewMBB -> addSuccessor


<s> m2 . as_m64 = __B ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) res . as_char [ i ] = ( ( unsigned char ) m1 . as_char [ i ] < ( unsigned char ) m2 . as_char [

i ] ) ? m1 . as_char [ i ] : m2 . as_char [ i ] ;


<s> add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , SImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , SImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , DImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , DImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , DImode , SFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , DImode , SFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( add_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( sdiv_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( smul_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( neg_optab


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * A << <STR_LIT> << * B << <STR_LIT> ) ; Value * Ptr = BasePtr ; if ( Offset ) Ptr = IRB . CreateConstGEP1_32 ( Ptr , Offset ) ; IRB . CreateCall ( StgpFn , { Ptr , A


<s> return ( __m256i ) __builtin_ia32_vpmadd52huq256 ( ( __v4di ) __X ,


<s> return PO + UnknownPadding ( LogAlign


<s> ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask


<s> for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_<ISA_LIT>_AIX_TLSGDM ) { SmallString < <NUM_LIT> > Name ; StringRef Prefix = <STR_LIT> ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else


<s> if ( mode == HFmode ) return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ; else if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; else return default_scalar_mode_supported_p


<s> static int nds32_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == HIGH_REGS || to == HIGH_REGS ) return <NUM_LIT> ; return


<s> rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG (


<s> } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Ld = Sc . getOperand ( <NUM_LIT> ) ; if ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) return SDValue ( ) ; break ; } } if ( ! <STR_LIT> ( Ld . getNode ( ) ) ) return SDValue ( ) ; bool Is256 = VT .


<s> LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) )

MadeChange |= optimizeThumb2Branches ( ) ;


<s> bool UndefLower = isUndefLowerHalf ( Mask ) ; if ( ! UndefLower && ! isUndefUpperHalf ( Mask ) ) return SDValue ( ) ; assert ( ( ! UndefLower || ! isUndefUpperHalf ( Mask ) ) && <STR_LIT> ) ; if ( ! UndefLower && isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfNumElts , HalfNumElts ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( UndefLower && isSequentialOrUndefInRange ( Mask , HalfNumElts , HalfNumElts , <NUM_LIT> ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; } int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( HalfNumElts ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) ) return SDValue ( ) ; assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; int NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; int NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; if ( UndefLower && NumUpperHalves != <NUM_LIT> ) return SDValue ( ) ; if ( ! UndefLower && NumUpperHalves == <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX2 ( ) && ( UndefLower || NumUpperHalves != <NUM_LIT> ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ! UndefLower && NumLowerHalves != <NUM_LIT> && NumUpperHalves != <NUM_LIT> ) return SDValue ( ) ; } } if ( VT . is512BitVector ( ) && ( UndefLower || NumUpperHalves != <NUM_LIT> )


<s> LiveRange * makeNewLiveRangeFor ( unsigned _physicalReg ) { LiveRange * LR = new LiveRange ( ) ; interferenceGraph . insert ( LR ) ; LR -> physicalReg = _physicalReg ; LR -> usesPhysicalReg = true ; return LR


<s> return __builtin_ia32_vcvtw2ph128_mask ( ( __v8hi ) __A , _mm_setzero_ph ( ) , ( __mmask8


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned I = <NUM_LIT> ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue


<s> unsigned getRegSpillOffset ( unsigned


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const unsigned SlotSize = TM . getRegisterInfo ( ) -> getSlotSize ( ) ; const bool Is64Bit = STI . is64Bit ( ) ; DebugLoc DL ; const unsigned HipeLeafWords = <NUM_LIT> ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI -> getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock & prologueMBB = MF . front ( ) ; MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( MachineBasicBlock :: livein_iterator I = prologueMBB . livein_begin ( ) , E = prologueMBB . livein_end ( ) ; I != E ; I ++ ) { stackCheckMBB -> addLiveIn ( * I ) ; incStackMBB -> addLiveIn ( *


<s> int Size ; switch ( ( TSFlags & <STR_LIT> ) >> <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Size = <NUM_LIT> ; break ; case <STR_LIT> : Size = <NUM_LIT> ; break ; } uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; if ( Subtarget . isThumb ( ) && Size == <NUM_LIT> ) { EmitConstant ( Binary >> <NUM_LIT> , <NUM_LIT> , OS ) ; EmitConstant ( Binary & <NUM_LIT> , <NUM_LIT> , OS ) ; } else EmitConstant ( Binary ,


<s> if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , (


<s> parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num , Reg . StartLoc


<s> SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue CompareOps [ ] = {


<s> assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> <<


<s> InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ; } Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . Label . Decl ) ) ; return false ; } unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info .


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return


<s> if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , SDLoc ( BASDN ) , GA ) ; } if ( Subtarget . is32BitELFABI ( ) && isPositionIndependent ( ) ) return getTOCEntry ( DAG , SDLoc ( BASDN ) , DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ) ; unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA ,


<s> temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT>


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( ST -> hasNEON ( ) && Src -> isVectorTy ( ) && ( Alignment && * Alignment != Align ( <NUM_LIT> ) ) && cast < VectorType > ( Src ) -> getElementType ( ) -> isDoubleTy ( ) ) { return LT . first


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString


<s> int <ISA_LIT>ConstantIslands :: findInRangeCPEntry ( CPUser & U , unsigned UserOffset ) { MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getMaxDisp ( ) , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries


<s> EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { VT = VT . changeVectorElementTypeToInteger ( ) ; ElementCount EC = VT . getVectorElementCount ( ) ; auto ScalarIntVT = <STR_LIT> ( <STR_LIT> / EC . getKnownMinValue ( ) ) ; PassThru = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ScalarIntVT , EC ) , PassThru ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru . getSimpleValueType ( ) , <STR_LIT>


<s> if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = <NUM_LIT> ; cost += inline_memory_move_cost ( mode , class1 , <NUM_LIT> ) ; cost += inline_memory_move_cost ( mode , class2 , <NUM_LIT> ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += <NUM_LIT> ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += <NUM_LIT> ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return MAX ( <NUM_LIT> , MMX_CLASS_P ( class1 ) || MMX_CLASS_P ( class2 ) ? ix86_cost -> mmxsse_to_integer : ix86_cost -> ssemmx_to_integer ) ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops


<s> const auto & STI = DAG . getMachineFunction ( ) . getSubtarget <


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv16qi (


<s> MVT RetVT ; if ( ! isTypeSupported ( I -> getType ( ) , RetVT , true ) ) return false ; if ( RetVT . isVector ( ) ) return selectOperator ( I , I -> getOpcode ( ) ) ; if ( const auto * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = <NUM_LIT> ; uint64_t ShiftVal = C -> getZExtValue ( ) ; MVT SrcVT = RetVT ; bool IsZExt = ( I -> getOpcode ( ) == Instruction :: AShr ) ? false : true ; const Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { if ( ! isIntExtFree ( ZExt ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { if ( ! isIntExtFree ( SExt ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> return __builtin_mve_vhcaddq_rot270_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V1DFmode ) ) return true ; return


<s> static int aarch64_sched_issue_rate ( void )


<s> if ( PreExtendType != <STR_LIT> && PreExtendType != <STR_LIT> && PreExtendType != <STR_LIT> ) return SDValue ( ) ; EVT PreExtendVT = TargetType . changeVectorElementType ( PreExtendType ) ; if ( PreExtendVT . getVectorElementCount ( ) != TargetType . getVectorElementCount ( ) ) return SDValue ( ) ; if ( TargetType . getScalarSizeInBits ( ) != PreExtendVT . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( VectorShuffle ) ; SDValue InsertVectorNode = DAG . getNode ( InsertVectorElt . getOpcode ( ) , DL , PreExtendVT , DAG . getUNDEF ( PreExtendVT ) , DAG . getAnyExtOrTrunc ( Extend . getOperand ( <NUM_LIT> ) , DL , PreExtendType ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; std :: vector < int > ShuffleMask ( TargetType . getVectorElementCount ( ) . getValue ( ) ) ; SDValue VectorShuffleNode = DAG . getVectorShuffle ( PreExtendVT , DL , InsertVectorNode , DAG . getUNDEF


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum =


<s> const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( AddrReg ) ; for ( unsigned i = <NUM_LIT> , e = BI -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo . MBB -> addSuccessor ( FuncInfo

. MBBMap [ BI -> getSuccessor ( i ) ] ) ;


<s> static void ix86_check_avx256_stores ( rtx dest , const_rtx , void * data ) { if ( ix86_check_avx256_register ( dest ) ) { bool * used = ( bool *


<s> for ( i = n_replacements - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx from = replacements [ i * <NUM_LIT> ] ; rtx to = replacements [ i * <NUM_LIT> + <NUM_LIT> ] ; unsigned from_regno , from_nregs , to_regno , new_regno ; if ( GET_CODE ( from ) != REG ) continue ; from_regno = REGNO ( from ) ; from_nregs = ( from_regno < FIRST_PSEUDO_REGISTER ? HARD_REGNO_NREGS ( from_regno , GET_MODE ( from ) ) : <NUM_LIT> ) ; if ( regno < from_regno + from_nregs && regno + nregs > from_regno ) { if ( regno < from_regno || regno + nregs > from_regno + nregs || GET_CODE ( to ) != REG || result ) return NULL_RTX ; to_regno = REGNO ( to ) ; if ( to_regno < FIRST_PSEUDO_REGISTER ) { new_regno = regno + to_regno - from_regno ; if ( ( unsigned ) HARD_REGNO_NREGS ( new_regno , GET_MODE ( x ) ) != nregs ) return NULL_RTX ; result = gen_rtx_REG ( GET_MODE ( x ) , new_regno ) ; } else if ( GET_MODE ( x ) <= GET_MODE ( to ) ) result = gen_lowpart_common ( GET_MODE ( x ) , to ) ; else result = gen_lowpart_SUBREG ( GET_MODE ( x ) , to ) ; } } return result ? result : x ; } else if ( GET_CODE ( x ) == ZERO_EXTEND ) { rtx new = replace_n_hard_rtx ( XEXP ( x , <NUM_LIT> ) , replacements , n_replacements , modify ) ; if ( GET_CODE ( new ) == CONST_INT ) { x = simplify_unary_operation ( ZERO_EXTEND , GET_MODE ( x ) , new , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( ! x ) abort ( ) ; } else if ( modify ) XEXP ( x , <NUM_LIT> ) = new ; return x ; } fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx new ; if ( fmt [ i ] == 'e' ) { new = replace_n_hard_rtx ( XEXP ( x , i ) , replacements , n_replacements , modify ) ; if ( ! new ) return NULL_RTX ; if ( modify ) XEXP ( x , i ) = new ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { new = replace_n_hard_rtx ( XVECEXP ( x , i , j ) , replacements , n_replacements , modify ) ; if ( ! new ) return NULL_RTX ; if ( modify ) XVECEXP ( x , i ,


<s> bool FoundLoad = false ; SmallVector < SDValue , <NUM_LIT> > ChainOps ; SmallVector < const SDNode * , <NUM_LIT> > LoopWorklist ; SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { FoundLoad = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } LoopWorklist . push_back ( Op . getNode ( ) ) ; ChainOps . push_back ( Op ) ; } if ( ! FoundLoad ) return false ; if ( ! LoopWorklist . empty ( ) ) { const unsigned int Max = <NUM_LIT> ; if ( SDNode :: hasPredecessorHelper ( Load . getNode ( ) , Visited , LoopWorklist , Max , true ) ) return false ; } InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> , ChainOps ) ; return true


<s> if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( ArrayRef < EVT > ( Tys , NumVecs + <NUM_LIT> ) ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( ) , ResNo ) ) ; } std :: vector < SDValue > VLDDupResults ; for ( unsigned n = <NUM_LIT> ; n < NumVecs ; ++ n ) VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , n ) ) ; VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , NumVecs ) ) ; DCI . CombineTo ( VLD ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII ,

const MCRegisterInfo & MRI , MCContext & Ctx ) {


<s> OperandMatchResultTy parseADDR32 ( OperandVector & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> ,


<s> switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> bool isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRd ( insn , isSP ) ) ) ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; RegClass = OpInfo [ OpIdx ] . RegClass ; assert ( ( RegClass == <STR_LIT> || RegClass == <STR_LIT> ) && <STR_LIT> ) ; isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRm ( insn , isSP ) ) ) ) ; ++ OpIdx ; return


<s> static int d30v_issue_rate ( ) { return <NUM_LIT>


<s> SDValue NotOp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , NotOp1 ) ; case


<s> MachineInstrBuilder EmitInstLoad ( unsigned Opc , unsigned DstReg , unsigned MemReg ,


<s> if ( ! TARGET_SOM ) fputs ( <STR_LIT> , asm_out_file ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( <STR_LIT> , asm_out_file ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT>


<s> return false ; } else if ( which_group == previous_group ) { if ( is_dispatch_slot_restricted ( insn ) ) return true ; return false ; } return


<s> real_from_string ( & rv , <STR_LIT> ) ; sh_fsca_int2sf_rtx = const_double_from_real_value ( rv ,


<s> } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( LocVT , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( VA


<s> const <ISA_LIT>Subtarget & getSubtarget (


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG

. getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ;


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CPN = dyn_cast < ConstantPointerNull > ( C ) ) { ( void ) CPN ; assert ( CPN -> getType ( ) -> getPointerAddressSpace ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return materializeInt ( ConstantInt :: get ( Type :: getInt64Ty ( * Context ) , <NUM_LIT> ) , VT ) ; } if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP >

( C ) ) return materializeFP ( CFP , VT ) ;


<s> case <STR_LIT> : return emitBPOSGE32 ( MI , BB ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitCOPY_FW ( MI , BB ) ; case <STR_LIT> : return emitCOPY_FD ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FW ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FD ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : return emitFILL_FW ( MI , BB ) ; case <STR_LIT> : return emitFILL_FD ( MI , BB ) ; case <STR_LIT> : return emitFEXP2_W_1 ( MI , BB ) ; case <STR_LIT> : return emitFEXP2_D_1 ( MI , BB ) ; case <STR_LIT> : return emitST_F16_PSEUDO ( MI , BB ) ; case <STR_LIT> : return emitLD_F16_PSEUDO ( MI , BB ) ; case <STR_LIT>


<s> void <ISA_LIT>PostRewrite :: selectSELRMux ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned LowOpcode , unsigned HighOpcode ) { Register DestReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DestIsHigh = <STR_LIT> ( DestReg ) ; bool Src1IsHigh = <STR_LIT> ( Src1Reg ) ; bool Src2IsHigh = <STR_LIT> ( Src2Reg ) ; if ( DestReg != Src1Reg && DestReg != Src2Reg ) { if ( DestIsHigh != Src1IsHigh ) { BuildMI ( * MBBI -> getParent ( ) , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MBBI -> getOperand ( <NUM_LIT> ) ) ) ; MBBI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Src1Reg = DestReg ; Src1IsHigh = DestIsHigh ; } else if ( DestIsHigh != Src2IsHigh ) { BuildMI ( * MBBI -> getParent ( ) , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MBBI -> getOperand ( <NUM_LIT> ) ) ) ; MBBI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Src2Reg =


<s> APInt MinC , MaxC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; if ( ! <STR_LIT> ( Max -> getOperand ( <NUM_LIT> ) . getNode ( ) , MaxC ) || MaxC != ~ SaturateC ) return false ; return true ; } ; if ( IsSignedSaturate ( N , N0 . getNode ( ) ) ) { SDLoc DL ( N ) ; MVT ExtVT , HalfVT ; if ( VT == <STR_LIT> ) { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } else { HalfVT = <STR_LIT> ; ExtVT = <STR_LIT> ; } SDValue VQMOVN = DAG . getNode ( <STR_LIT> , DL , HalfVT , DAG . getUNDEF ( HalfVT ) , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT , VQMOVN ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Bitcast , DAG . getValueType ( ExtVT ) ) ; } auto IsUnsignedSaturate = [ & ] ( SDNode * Min ) { if ( Min -> getOpcode ( ) != <STR_LIT> ) return false ; APInt SaturateC ; if ( VT == <STR_LIT> ) SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; else SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; APInt MinC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; return true ; } ; if ( IsUnsignedSaturate ( N ) ) { SDLoc DL ( N ) ; MVT HalfVT ; unsigned ExtConst ; if ( VT == <STR_LIT> ) { HalfVT = <STR_LIT> ; ExtConst = <NUM_LIT> ; } else


<s> if ( VT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT>


<s> else if ( isa < UndefValue > ( C ) ) { unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf32 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf64 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return <NUM_LIT>


<s> return new <ISA_LIT>Disassembler ( STI , T . createMCRegInfo (


<s> static const MCSymbol * GetAnonSym ( const MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym ->


<s> bool NZCVKilled = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; TrueBB -> addSuccessor ( EndBB ) ; if ( !


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( __A ) , <STR_LIT> ( __B ) : ) ; return ( __m128i ) result ; return ( __m128i ) vec_mule ( ( __v4su ) __A , ( __v4su ) __B ) ; return ( __m128i ) vec_mulo ( ( __v4su )


<s> void EmitByte ( uint8_t elem ) { Vec [ Pos ] =


<s> if ( STI . hasV5TOps ( ) ) return <STR_LIT> ; if ( STI . hasV4TOps ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType


<s> for ( unsigned l = <NUM_LIT> ; l != <NUM_LIT> ; ++ l ) { unsigned HalfMask = Imm >> ( l * <NUM_LIT> ) ; unsigned HalfBegin = ( HalfMask & <NUM_LIT> ) * HalfSize ; for ( unsigned i = HalfBegin , e = HalfBegin + HalfSize ; i != e ; ++ i ) ShuffleMask . push_back

( HalfMask & <NUM_LIT> ? SM_SentinelZero : ( int ) i ) ;


<s> int adjacent_mem_locations ( rtx a , rtx b ) { if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return <NUM_LIT> ; if ( ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == REG || ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) && ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == REG || ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) { HOST_WIDE_INT val0 = <NUM_LIT> , val1 = <NUM_LIT> ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ; val0 = INTVAL ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg0 = XEXP ( a , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ; val1 = INTVAL ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg1 = XEXP ( b , <NUM_LIT> ) ; if ( ! const_ok_for_op ( PLUS , val0 ) || ! const_ok_for_op (


<s> bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed =


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - <NUM_LIT> ; Parser . Lex


<s> MCOperand segmentReg ; uint64_t pcrel = <NUM_LIT> ; if ( insn . eaBase == EA_BASE_sib || insn . eaBase == EA_BASE_sib64 ) { if ( insn . sibBase != SIB_BASE_NONE ) { switch ( insn . sibBase ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_BASE_ ## x : \ baseReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; ALL_SIB_BASES } } else { baseReg = MCOperand :: createReg ( <STR_LIT> ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM } } else { if ( ! ForceSIB && ( insn . sibScale != <NUM_LIT> || ( insn . sibBase == SIB_BASE_NONE && insn . mode != MODE_64BIT ) || ( insn . sibBase != SIB_BASE_NONE && insn . sibBase != SIB_BASE_ESP && insn . sibBase != SIB_BASE_RSP && insn . sibBase != SIB_BASE_R12D && insn . sibBase != SIB_BASE_R12 ) ) ) { indexReg = MCOperand :: createReg ( insn . addressSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else indexReg = MCOperand :: createReg ( <STR_LIT> ) ; } scaleAmount = MCOperand :: createImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) { pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: createReg ( insn . addressSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; default : indexReg = MCOperand :: createReg ( <STR_LIT> ) ; switch ( insn . eaBase


<s> inline unsigned getAM2Opc ( AddrOpc Opc , unsigned Imm12 , ShiftOpc SO , unsigned IdxMode = <NUM_LIT> ) { assert ( Imm12 < ( <NUM_LIT> << <NUM_LIT>


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV )


<s> if ( V . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( V . getValueType ( ) . isFloatingPoint ( ) ) { if ( Subtarget . hasSSE1 ( ) && ! isa < ConstantFPSDNode > ( V ) ) { V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; V = DAG . getBitcast ( <STR_LIT> , V ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } V = DAG . getBitcast ( <STR_LIT> , V ) ; } else { V = DAG . getAnyExtOrTrunc ( V , DL , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( Splat ) { if ( Splat . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; Splat = CreateMMXElement ( Splat ) ; if ( Subtarget . hasSSE1 ( ) ) { if ( NumElts == <NUM_LIT> ) Splat = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , Splat ) ; unsigned ShufMask = ( NumElts > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , DAG . getConstant ( ShufMask , DL , <STR_LIT> ) ) ; } Ops . append ( NumElts , Splat ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Ops . push_back ( CreateMMXElement ( N . getOperand ( i ) ) ) ; } while ( Ops . size ( ) > <NUM_LIT> ) { unsigned NumOps = Ops . size ( ) ; unsigned IntrinOp = ( NumOps == <NUM_LIT> ? <STR_LIT> : ( NumOps == <NUM_LIT> ? <STR_LIT> : <STR_LIT>


<s> assert ( isMem ( ) && <STR_LIT> ) ; return Mem .


<s> return ( int8x8x2_t ) { vtrn1_s8 ( a , b )


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return false ; return true


<s> Info = & FunctionInfoMap [ F ] ; } else { Info = & info_item -> second ; } const FunctionType * FT = F -> getFunctionType ( ) ; switch ( Info -> getDecorationStyle ( ) ) { case None : break ; case StdCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; break ; case FastCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; if ( Name [ <NUM_LIT> ] == '_' ) { Name [ <NUM_LIT> ] = '@' ; } else { Name = '@' + Name ; } break ; default : assert ( <NUM_LIT> &&


<s> static __inline qword si_from_float ( float f ) { union { qword q


<s> } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits (


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasLoadStoreOnCond2 ( ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT>


<s> static tree rs6000_vector_type ( const char * name , tree elt_type , unsigned num_elts ) { tree result = build_vector_type ( elt_type , num_elts ) ; result = build_variant_type_copy ( result ) ; add_builtin_type ( name , result ) ; return


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm ,


<s> void TagStoreEdit :: emitUnrolled ( MachineBasicBlock :: iterator InsertI ) { const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const int64_t kMinOffset = - <NUM_LIT> * <NUM_LIT> ; const int64_t kMaxOffset = <NUM_LIT> * <NUM_LIT> ; Register BaseReg = FrameReg ; int64_t BaseRegOffsetBytes = FrameRegOffset . getBytes ( ) ; if ( BaseRegOffsetBytes < kMinOffset || BaseRegOffsetBytes + ( Size - Size % <NUM_LIT> ) > kMaxOffset ) { Register ScratchReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( * MBB , InsertI , DL , ScratchReg , BaseReg , { BaseRegOffsetBytes , <STR_LIT> } , TII ) ; BaseReg = ScratchReg ; BaseRegOffsetBytes = <NUM_LIT> ; } MachineInstr * LastI = nullptr ; while ( Size ) { int64_t InstrSize = ( Size > <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Opcode = InstrSize == <NUM_LIT> ? ( ZeroData ? <STR_LIT> : <STR_LIT> ) : ( ZeroData


<s> if ( index != - <NUM_LIT> ) { auto * CPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( CP ->

getConstants ( ) [ index ] . Val . MachineCPVal ) ;


<s> if ( rx_gp_base_regnum_val == INVALID_REGNUM )


<s> return ( uint8x16_t ) __builtin_neon_vcgtv16qi (


<s> unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = Subtarget -> isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i =


, CurSlots ( <NUM_LIT> ) , CurBranches ( <NUM_LIT> ) {


<s> static bool isCompareEqualsImm ( const MachineInstr * MI , bool & SignedCmp ) { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { SignedCmp =


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHEpilogEnd ( SMLoc L ) { getTargetStreamer ( ) . emit<ISA_LIT>WinCFIEpilogEnd ( ) ; return


<s> Function * Ldrex = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ?


<s> rtx_insn * thumb1_md_asm_adjust ( vec < rtx > & outputs , vec < rtx > & , vec < machine_mode > & , vec < const char * > & constraints , vec < rtx > & , HARD_REG_SET & , location_t ) { for ( unsigned i = <NUM_LIT> , n = outputs . length ( ) ; i < n ; ++ i ) if ( startswith ( constraints [ i ] , <STR_LIT> ) ) { sorry ( <STR_LIT> )


<s> MachineFunction * F = MBB -> getParent ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> )


<s> static DecodeStatus DecodeZPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success