<s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( &


<s> SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDVTList ResultVTs = DAG . getVTList ( XLenVT , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL ,

ResultVTs , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static void riscv_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( riscv_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) riscv_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! riscv_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == <NUM_LIT> ) { rtx inv_target = riscv_force_binary ( GET_MODE ( target )


<s> const DataLayout & DL = getDataLayout ( ) ; return <STR_LIT> ( Imm , DL . getTypeSizeInBits ( Ty ) , getST ( )


<s> case CASE_VFMA_SPLATS ( FNMSUB ) : case CASE_VFMA_OPCODE_LMULS ( FMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( MADD , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSUB , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMACC , FMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMADD , FMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSAC , FMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSUB , FMSAC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMACC , FNMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMADD , FNMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSAC , FNMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSUB , FNMSAC ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMACC , FMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMSAC , FMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMACC , FNMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMSAC , FNMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MADD , MACC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSUB , NMSAC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ; WorkingMI . setDesc ( get


<s> const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra


<s> uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler :: Success


<s> static bool riscv_use_save_libcall ( const struct riscv_frame_info * frame


<s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall ) { MachineBasicBlock :: iterator NewMI = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( RestoreLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( MI != MBB . end ( ) && MI


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ; assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; if ( STI . getFeatureBits (


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg


<s> unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size


<s> if ( isa < FixedVectorType > ( DataType ) &&

ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;


<s> const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , CPU , FS , <STR_LIT> , RTM ) ; RTS . emitTargetAttributes ( STI


<s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands (


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; rtx_insn * tmp = NEXT_INSN ( prologue ) ; if ( ! NOTE_P ( tmp ) || NOTE_KIND ( tmp ) != NOTE_INSN_PROLOGUE_END ) return ; do { tmp = NEXT_INSN ( tmp ) ; } while ( tmp != NULL && NOTE_P ( tmp ) ) ; if ( tmp == NULL || ! INSN_P ( tmp ) ) return ; bool noreturn_p = find_reg_note ( tmp ,


<s> SDLoc DL ( Op ) ; SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; SDVTList VTs = DAG . getVTList ( XLenVT , <STR_LIT> ) ; SDValue RM = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , SysRegNo ) ; static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT>

* <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> SmallVector < MachineInstr * , <NUM_LIT> > MIs ; Register NewReg = analyzeCompressibleUses ( MI , RegImm , MIs ) ; if ( ! NewReg ) continue ; if ( <STR_LIT> . contains ( RegImm . Reg ) ) { assert ( isInt < <NUM_LIT> > ( RegImm . Imm ) ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , NewReg ) . addReg ( RegImm . Reg ) . addImm ( RegImm . Imm ) ; } else { assert ( RegImm . Imm == <NUM_LIT> ) ; unsigned Opcode = <STR_LIT> . contains ( RegImm . Reg ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( Opcode ) , NewReg ) . addReg ( RegImm . Reg ) . addReg ( RegImm . Reg ) ; } for ( MachineInstr * UpdateMI : MIs ) updateOperands ( * UpdateMI , RegImm , NewReg ) ; } } return true


<s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; count ++ ; return count ; } return InsertBranchAtInst ( MBB , MBB . end ( ) , TBB ,


<s> if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) result = expand_simple_unop ( mode , code , op1 , NULL_RTX , false ) ; else result = expand_simple_binop ( mode , code , op1 , op2 , NULL_RTX , false , OPTAB_DIRECT ) ; riscv_emit_move ( op0 , result ) ; } else { rtx pat ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) pat = gen_rtx_fmt_e ( code , mode , op1 ) ; else pat = gen_rtx_fmt_ee ( code ,


<s> break ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getRegister ( <STR_LIT> , PtrVT ) ; } case <STR_LIT> : { SDValue scalar = Op . getOperand ( <NUM_LIT> ) ; if ( scalar . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Promote = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Promote , Op . getOperand ( <NUM_LIT> ) } ) ; } break ; } } if ( const <STR_LIT> * EII = <STR_LIT> ( IntNo ) ) { if ( EII -> ExtendedOperand ) { assert ( EII -> ExtendedOperand < Op . getNumOperands ( ) ) ; std :: vector < SDValue > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ EII -> ExtendedOperand ] ; if ( ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp


<s> return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) !=


<s> const unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode ==

<STR_LIT> ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; unsigned Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ,


<s> return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> break ; case RVV_VXSAT : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VXRM : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT>


<s> I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout

( ) , CurDAG -> getDataLayout ( ) . getAllocaAddrSpace ( ) ) ) ;


<s> for ( int i = <NUM_LIT> ; op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) if ( FLOAT_MODE_P ( TYPE_MODE ( get_arg_type ( i ) ) ) ) return true ; return false


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg =


<s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK


<s> case CONST_DOUBLE : case CONST_VECTOR : return x == CONST0_RTX ( GET_MODE ( x ) ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : if ( riscv_symbolic_constant_p ( x , & symbol_type ) ) return riscv_symbol_insns ( symbol_type ) ; split_const ( x , & x , & offset ) ; if ( offset != <NUM_LIT>


<s> const GlobalValue * GV = N -> getGlobal ( ) ; int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , Ty


<s> if ( cfun -> machine -> naked_p ) return ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -=


<s> static bool ge_sew_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_LMUL ) && ! info2 . demand_p ( DEMAND_RATIO ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return true


<s> if ( RegNo > sizeof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode ,


<s> if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; bool Fractional = false ; if ( Name . consume_front ( <STR_LIT> ) ) { Fractional = true ; } APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; bool TailAgnostic ; if ( Name . consume_front ( <STR_LIT> ) )


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler


<s> bool needsRelocateWithSymbol ( const MCSymbol & Sym


<s> bool <ISA_LIT>AsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == <NUM_LIT> ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> ,


<s> Target & getThe<ISA_LIT>32Target ( ) { static Target The<ISA_LIT>32Target ; return


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > array_lengthof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; Register Reg = FPR64DecoderTable


<s> return lookup_attribute ( <STR_LIT> ,


<s> MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> AnalyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch


<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment


<s> if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO ,


<s> Op -> VType . Val = VTypeI ; Op -> StartLoc = S ; Op -> EndLoc =


<s> add_input_operand ( CONSTM1_RTX ( mode )


<s> mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ; } memset ( & args , <NUM_LIT> , sizeof args ) ; return riscv_get_arg_info ( & info , & args , mode , type ,


<s> return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > (


<s> Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = true ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRelax (


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return true


<s> if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount >


<s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT>


<s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType


<s> void th_mempair_save_restore_regs ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) { gcc_assert ( th_mempair_operands_p ( operands , load_p , mode )


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm (


<s> return VLen == <NUM_LIT> ? getMinVLen ( ) :


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands (


<s> return TFI -> hasFP ( MF ) ? TFI -> getFPReg ( ) :


<s> else if ( info2 . demand_p ( DEMAND_MASK_POLICY ) ) { set_ma ( info2 . get_ma ( ) ) ; demand ( DEMAND_MASK_POLICY ) ; } else set_ma ( get_default_ma


<s> void <ISA_LIT>MCAsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { unsigned Opcode = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; assert ( Opcode && <STR_LIT> )


<s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) compute_local_backward_infos ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) emit_local_forward_vsetvls ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf ( dump_file


<s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; else VL = N


<s> int NumOp = MI . getNumExplicitOperands ( ) ; return MI . getOperand ( NumOp - <NUM_LIT>


<s> BBInfo . InQueue = false ; VSETVLIInfo InInfo ; if ( MBB . pred_empty ( ) ) { InInfo . setUnknown ( ) ; } else { for ( MachineBasicBlock * P : MBB . predecessors ( ) ) InInfo = InInfo . intersect ( BlockInfo [ P -> getNumber ( ) ] . Exit ) ; } if ( ! InInfo . isValid


<s> static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getSTI ( ) . getFeatureBits ( )


<s> static void addUses ( const MachineInstr & MI , SmallVectorImpl < const MachineInstr * > & Worklist , MachineRegisterInfo & MRI ) { for ( auto & UserOp : MRI . reg_operands ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { const auto * User = UserOp


<s> static rtx riscv_emit_set ( rtx target


<s> return MCDisassembler :: Fail ; } Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ; return createELFObjectWriter ( MOTW , OS , true


<s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) const { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( argno ) ; return false ; } return require_immediate_range ( argno , min ,


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile

, bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return


<s> if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getCondCode ( CCVal ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getCondCode ( <STR_LIT> ) ; SDValue Ops [ ] = { CondV , Zero , SetNE ,


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * LoopMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , LoopMBB ) ; MachineBasicBlock * DoneMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopMBB ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; Register ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode ; <ISA_LIT>MCExpr :: VariantKind VKHi ; if ( getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) { SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; VKHi = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; } else { SecondOpcode = <STR_LIT> ; VKHi = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; } emitAuipcInstPair ( DestReg , DestReg , Symbol , VKHi ,


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK


<s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( )


<s> SDValue Add ; unsigned AddBaseIdx ; if ( Base . getMachineOpcode ( ) == <STR_LIT> && Base . hasOneUse ( ) ) { Add = Base ; SDValue Op0 = Base . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Base . getOperand ( <NUM_LIT> ) ; if ( Op0 . isMachineOpcode ( ) && Op0 . getMachineOpcode ( ) == <STR_LIT> && ! isa < FrameIndexSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { AddBaseIdx = <NUM_LIT> ; Base = Op0 ; } else if ( Op1 . isMachineOpcode ( ) && Op1 . getMachineOpcode ( ) == <STR_LIT> && ! isa < FrameIndexSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { AddBaseIdx = <NUM_LIT> ; Base = Op1 ; } else if ( Op1 . isMachineOpcode ( ) && Op1 . getMachineOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . getOperand ( <NUM_LIT> ) . isMachineOpcode ( ) && Op1 . getOperand ( <NUM_LIT> ) . getMachineOpcode ( ) == <STR_LIT> ) { uint64_t Imm = Op1 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; Imm <<= <NUM_LIT> ; Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; uint64_t LoImm = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Imm += LoImm ; if ( ! isInt < <NUM_LIT> > ( Imm ) ) return false ; AddBaseIdx = <NUM_LIT> ; Base = Op1 ; } else return false ; } else if ( Base . getMachineOpcode (


<s> if ( prop . has_avl_reg ( ) && ! vlmax_avl_p ( prop . get_avl ( ) ) ) { hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( ) , true , true , true ) ; set_info * set = get_same_bb_set ( sets , e -> src ) ; if ( set ) block_info . reaching_out . set_avl_info ( avl_info ( prop . get_avl ( ) , set ) ) ; } block_info . local_dem = block_info . reaching_out ; block_info . probability = curr_block_info . probability ; changed_p = true ; } else if ( block_info . reaching_out . dirty_p ( ) ) { vector_insn_info new_info ; if ( block_info . reaching_out . compatible_p ( prop ) ) { if ( block_info . reaching_out . available_p ( prop ) ) continue ; new_info = block_info . reaching_out . merge ( prop , GLOBAL_MERGE ) ; new_info . set_dirty ( block_info . reaching_out . dirty_with_killed_avl_p ( ) ) ; block_info . probability += curr_block_info . probability ; } else { if ( curr_block_info . probability > block_info . probability ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; new_info = prop ; new_info . set_dirty ( type ) ; block_info . probability = curr_block_info . probability ; } else continue ; } if ( propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) { rtx reg = new_info . get_avl_reg_rtx ( ) ; if ( find_reg_killed_by ( crtl -> ssa -> bb ( e -> src ) , reg ) ) new_info . set_dirty ( true ) ; } block_info . local_dem = new_info ; block_info . reaching_out = new_info ; changed_p = true ; } else { gcc_assert ( block_info . reaching_out . valid_p ( ) ) ; hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( )


<s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp0 , NewOp1


<s> unsigned getIncomingArgSize ( ) const


<s> assert ( Kind == KindReg && <STR_LIT>


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm

) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> bool isPseudoJumpSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT>


<s> if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ; return


<s> Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 ,


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR


<s> switch ( Opcode ) { case <STR_LIT> : { SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; unsigned Opc = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , DL , VT , TFI , imm ) ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == NULL || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump ( CurDAG ) ; errs ( ) <<


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; } TargetABI = <STR_LIT> ( TT , getFeatureBits (


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtP ( ) && Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT ,


<s> SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node , Store )


<s> uint64_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 < <NUM_LIT> && VC1 == ( ( uint64_t ) <NUM_LIT> << VC2 ) ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC2 , SDLoc ( N ) , Shl . getOperand ( <NUM_LIT>


<s> case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } return getIntImmCost ( Imm , Ty


<s> struct riscv_address_info addr ; return riscv_classify_address ( & addr , x , mode


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT>


<s> int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA ,


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( DataTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( DataTy , Align ( Alignment ) ) ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ! isa < FixedVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VTy = cast < FixedVectorType > ( DataTy ) ; unsigned NumLoads = VTy -> getNumElements ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VTy -> getElementType ( ) , Alignment ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) || C -> getSExtValue ( ) == <STR_LIT> ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; else VL = N ; return true


<s> } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ) ) ; return


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL


<s> return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_F8 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_1 : return createM1Tuple ( CurDAG , Regs ,


<s> case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT>


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned FP = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) SavedRegs . set ( FP ) ; if ( <ISA_LIT>FI -> getCallsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) +


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) ,


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> static bool has_vtype_op ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_has_vtype_op ( rinsn


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget .


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT


<s> return std :: make_pair ( <NUM_LIT> << static_cast < unsigned > ( VLMUL ) , false ) ; case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F8 : return std :: make_pair ( <NUM_LIT> << ( <NUM_LIT> - static_cast


<s> if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection (


<s> emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand


<s> if ( CM ) return * CM ; return CodeModel


<s> FunctionPass * llvm :: create<ISA_LIT>RI5CYIRPass ( ) { return new <ISA_LIT>RI5CYIR (


<s> case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent : return parseOperandWithModifier ( Operands ) ; } Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res ,


<s> SavedRegs . set ( <STR_LIT> ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( const GlobalValue * gv , <STR_LIT> modifier ) : MachineConstantPoolValue ( gv -> getType ( ) ) ,


<s> auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; bool IsMaskOp = VT . getVectorElementType ( ) == <STR_LIT> ; SDValue IntID = DAG . getTargetConstant ( IsMaskOp ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsMaskOp ) Ops . push_back ( DAG . getUNDEF (


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState

( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F


<s> } else if ( FP_REG_P ( regno ) ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_or_fixed_reg_p ( regno ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else if ( V_REG_P ( regno ) ) { if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return false ; if ( ! V_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; int lmul = <NUM_LIT> ; if ( known_gt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) lmul = exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; if ( lmul != <NUM_LIT> ) return ( ( regno % lmul ) == <NUM_LIT> ) ; } else if ( regno == VL_REGNUM || regno == VTYPE_REGNUM ) return true ; else return false ; for ( unsigned i = <NUM_LIT> ; i < nregs ; i ++ ) if ( call_used_or_fixed_reg_p ( regno ) != call_used_or_fixed_reg_p ( regno + i ) ) return false ; if ( ! TARGET_64BIT && TARGET_ZDINX ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_UNIT_SIZE ( mode ) == GET_MODE_SIZE ( DFmode ) ) return ! ( regno & <NUM_LIT> ) ; } return


<s> if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success


<s> SDValue Promote = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Promote , Op . getOperand ( <NUM_LIT> ) } ) ; } break ; } } if ( const <STR_LIT> * EII = <STR_LIT> ( IntNo ) ) { if ( EII -> ExtendedOperand ) { assert ( EII -> ExtendedOperand < Op . getNumOperands ( ) ) ; std :: vector < SDValue > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [


<s> if ( ! flag_pic ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( riscv_call_tls_get_addr ( loc , tmp ) , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp = riscv_unspec_offset_high ( NULL , loc , SYMBOL_TLS_LE ) ; dest = gen_reg_rtx (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo &


<s> if ( DL . isFatPointer ( PointerTy ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) && ( isa < AtomicRMWInst > ( AI )

|| isa < AtomicCmpXchgInst > ( AI ) ) ) return false ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( OSABI , TT .


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> Kind = o . Kind ; IsRV64 = o . IsRV64 ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token


<s> void <ISA_LIT>InstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned * Reg , int64_t Value ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned Opcode ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = STI . isRV64 ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; * Reg = RegInfo . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Value ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , * Reg ) .


<s> if ( vsetvl_insn_p ( rinsn ) || vlmax_avl_p ( info . get_avl ( ) ) ) { rtx dest = get_vl ( rinsn ) ; new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , new_info , dest ) ; } else if ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_vtype_change_only ) new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , new_info , NULL_RTX ) ; else new_pat = gen_vsetvl_pat ( VSETVL_DISCARD_RESULT


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> function_instance instance = get_read_vl_instance ( ) ; hashval_t hash = instance . hash ( ) ; registered_function * rfn = function_table -> find_with_hash (


<s> MCSymbol * TmpLabel = Ctx . createNamedTempSymbol ( <STR_LIT> ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx )

, <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;


<s> MCInst Inst ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ; Register VReg = RegInfo . createVirtualRegister


<s> flag_pcc_struct_return = <NUM_LIT> ; if ( flag_pic ) g_switch_value = <NUM_LIT> ; if ( TARGET_MUL && ( target_flags_explicit & MASK_DIV ) == <NUM_LIT> ) target_flags |= MASK_DIV ; else if ( ! TARGET_MUL && TARGET_DIV ) error ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT && ( target_flags_explicit & MASK_FDIV ) == <NUM_LIT> ) target_flags |= MASK_FDIV ; cpu = riscv_parse_cpu ( riscv_tune_string ? riscv_tune_string : RISCV_TUNE_STRING_DEFAULT ) ; tune_info = optimize_size ? & optimize_size_tune_info : cpu -> tune_info ; riscv_slow_unaligned_access_p = ( cpu -> tune_info -> slow_unaligned_access || TARGET_STRICT_ALIGN ) ; if ( ( target_flags_explicit & MASK_STRICT_ALIGN ) == <NUM_LIT> && cpu -> tune_info -> slow_unaligned_access ) target_flags |= MASK_STRICT_ALIGN ; if ( riscv_branch_cost == <NUM_LIT> ) riscv_branch_cost = tune_info -> branch_cost ; init_machine_status = & riscv_init_machine_status ; if ( flag_pic ) riscv_cmodel = CM_PIC ; if ( ( target_flags_explicit & MASK_EXPLICIT_RELOCS ) == <NUM_LIT> ) if ( riscv_cmodel == CM_MEDLOW ) target_flags |= MASK_EXPLICIT_RELOCS ; if ( UNITS_PER_FP_ARG > ( TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : <NUM_LIT> ) ) error ( <STR_LIT> , UNITS_PER_FP_ARG > <NUM_LIT> ? 'Q' : ( UNITS_PER_FP_ARG > <NUM_LIT> ? 'D' : 'F' ) ) ; if ( BITS_PER_WORD != POINTER_SIZE ) error ( <STR_LIT> , POINTER_SIZE ) ; riscv_stack_boundary = ABI_STACK_BOUNDARY ; if ( riscv_preferred_stack_boundary_arg ) { int min = ctz_hwi ( STACK_BOUNDARY / <NUM_LIT> ) ; int max = <NUM_LIT> ; if ( ! IN_RANGE ( riscv_preferred_stack_boundary_arg , min , max ) ) error (

<STR_LIT> , riscv_preferred_stack_boundary_arg , min , max ) ;


<s> auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT ,


<s> bool hasStdExtZbr ( ) const { return


<s> if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind ,


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; assert ( TFI -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT>


<s> if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT

( ) , DL , Chain , Value , MachinePointerInfo ( ) ) ;


<s> if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits )


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success


<s> auto TargetABI = StringSwitch < ABI > ( ABIName ) . Case ( <STR_LIT> , ABI_ILP32 ) . Case ( <STR_LIT> , ABI_ILP32F ) . Case ( <STR_LIT> , ABI_ILP32D ) . Case ( <STR_LIT> , ABI_ILP32E ) . Case ( <STR_LIT> , ABI_IL32PC64 ) . Case ( <STR_LIT> , ABI_IL32PC64F ) . Case ( <STR_LIT> , ABI_IL32PC64D ) . Case ( <STR_LIT> , ABI_IL32PC64E ) . Case ( <STR_LIT> , ABI_LP64 ) . Case ( <STR_LIT> , ABI_LP64F ) . Case ( <STR_LIT> , ABI_LP64D ) . Case ( <STR_LIT> , ABI_L64PC128 ) . Case ( <STR_LIT> , ABI_L64PC128F ) . Case ( <STR_LIT> , ABI_L64PC128D ) . Default ( ABI_Unknown ) ; return


<s> return <ISA_LIT>MaxBuildIntsCost == <NUM_LIT> ? getSchedModel ( ) . LoadLatency + <NUM_LIT> : std :: max

< unsigned > ( <NUM_LIT> , <ISA_LIT>MaxBuildIntsCost ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <STR_LIT>


<s> sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; function_abi_aggregator callee_abis ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; return components


<s> void <ISA_LIT>InstrInfo :: movImm32 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) .


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT>


<s> if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVL = true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVTYPE = true ; if ( ! isVectorConfigInstr ( MI ) ) continue ; if ( PrevMI ) { if ( ! UsedVL && ! UsedVTYPE ) { ToDelete . push_back ( PrevMI ) ; } else if ( ! UsedVTYPE && isVLPreservingConfig ( MI ) ) { PrevMI -> getOperand ( <NUM_LIT> ) . setImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; ToDelete . push_back ( & MI ) ; continue ; } } PrevMI = & MI ; UsedVL = false ; UsedVTYPE = false ; Register VRegDef = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( VRegDef != <STR_LIT> && ! ( VRegDef . isVirtual ( ) && MRI -> use_nodbg_empty ( VRegDef ) )


<s> if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p


<s> <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> ) && ! WritesElement0 ) TailAgnostic = false ; MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( Multiplier , ElementWidth , TailAgnostic , false ) ) ; MI . getOperand ( SEWIndex ) . setImm ( - <NUM_LIT> ) ; if ( VLIndex >= <NUM_LIT> ) { MI . getOperand ( VLIndex ) . setReg


<s> mem2 = copy_rtx ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode ) format = <STR_LIT> ; else format = <STR_LIT> ; } split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; gcc_assert ( rtx_equal_p ( base1 , base2 ) ) ; auto size1 = MEM_SIZE ( mem1 ) ; auto size2 = MEM_SIZE ( mem2 ) ; gcc_assert ( known_eq ( size1 , size2 ) ) ; gcc_assert ( known_eq ( offset1 + size1 , offset2 ) ) ; HOST_WIDE_INT imm2 = offset1 >> shamt ; gcc_assert ( imm2 >= <NUM_LIT> && imm2 < <NUM_LIT> ) ; gcc_assert ( ( imm2 << shamt ) == offset1 ) ; gcc_assert ( REG_P ( reg1 ) ) ; gcc_assert ( REG_P ( reg2 ) ) ; gcc_assert ( REG_P ( base1 ) ) ; if ( load_p ) { gcc_assert ( REGNO ( reg1 ) != REGNO ( reg2 ) ) ; gcc_assert ( REGNO ( reg1 ) != REGNO ( base1 ) ) ; gcc_assert ( REGNO ( reg2 ) != REGNO ( base1 ) ) ; } output_operands [ <NUM_LIT> ] = copy_rtx ( reg1 ) ; output_operands [ <NUM_LIT> ] = copy_rtx (


<s> } if ( ! good_use ) return ; if ( epilogue_count != <NUM_LIT> ) return ; if ( call_count > <NUM_LIT> ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; return ; } rtx_insn * epilogue_begin_note = PREV_INSN ( epilogue_matched ) ; gcc_assert ( NOTE_P ( epilogue_begin_note ) && NOTE_KIND ( epilogue_begin_note ) == NOTE_INSN_EPILOGUE_BEG ) ; df_finish_pass ( false ) ; rtx_insn * insn_before_epilogue ; for ( insn_before_epilogue = PREV_INSN ( epilogue_begin_note ) ; NOTE_P ( insn_before_epilogue ) ; insn_before_epilogue = PREV_INSN ( insn_before_epilogue ) ) ; if ( GET_CODE ( insn_before_epilogue ) != CALL_INSN ) return ; rtx_insn * call = insn_before_epilogue ; rtx callpat = PATTERN ( call ) ; gcc_assert ( GET_CODE ( callpat ) == PARALLEL ) ; rtx target_call = NULL ; rtx tmp_rtx = XVECEXP ( callpat , <NUM_LIT> , <NUM_LIT> ) ; rtx set_target = NULL ; switch ( GET_CODE ( tmp_rtx ) ) { case CALL : target_call = tmp_rtx ; break ; case SET : { set_target = XEXP ( tmp_rtx , <NUM_LIT> ) ; tmp_rtx = XEXP ( tmp_rtx , <NUM_LIT> ) ; if ( GET_CODE ( tmp_rtx ) != CALL ) return ; target_call = tmp_rtx ; break ; } default : return ; } rtx target_mem = XEXP ( target_call , <NUM_LIT> ) ; if ( GET_CODE ( target_mem ) != MEM ) return ; rtx target = XEXP ( target_mem , <NUM_LIT> ) ; if ( GET_CODE ( target ) != SYMBOL_REF && GET_CODE ( target ) != REG ) return ; if ( GET_CODE ( target ) == REG && ! SIBCALL_REG_P ( REGNO


<s> unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc ,


<s> if ( reg_class_subset_p ( rclass , GR_REGS ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ; if ( reg_class_subset_p ( rclass , V_REGS ) ) return riscv_hard_regno_nregs ( V_REG_FIRST


<s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ; assert ( Expr && Expr -> getKind ( )


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ,


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , enum machine_mode mode ) { if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) )


<s> return ! riscv_naked_function_p ( decl )


<s> const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ; SDValue Ops [ ] = { CondV , Zero ,


<s> poly_int64 riscv_v_adjust_precision ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode )


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo

-> getSpillAlignment ( * RC ) , false ) ;


<s> const <ISA_LIT>Subtarget & ST = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; unsigned Opcode ; bool IsScalableVector = true ; bool IsZvlsseg = true ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode =


<s> int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) return <NUM_LIT> ; if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE (

mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> void pass_vsetvl :: prune_expressions ( void ) { for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . local_dem . valid_or_dirty_p ( ) ) m_vector_manager -> create_expr ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . local_dem ) ; if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out . valid_or_dirty_p ( ) ) m_vector_manager -> create_expr ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out ) ; } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , m_vector_manager ->


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMaskReg ( OperandVector & Operands ) { switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; if ( RegNo != <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } return


<s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( IsUnmasked ) Ops . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; else Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex ,


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op


<s> if ( VT . getFixedSizeInBits ( ) > <NUM_LIT> * <NUM_LIT> ) return false ; unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; switch ( EltVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT>


<s> Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand (


<s> } if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - <NUM_LIT> ; return


<s> reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; default : output_operand_lossage ( <STR_LIT> , hi_reloc ? 'h' : 'R' ) ; return ; } fprintf ( file , <STR_LIT> , reloc ) ; output_addr_const ( file , riscv_strip_unspec_address ( op ) ) ; fputc ( ')' ,


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target


<s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , <NUM_LIT> , <NUM_LIT>


<s> return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM


<s> if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ; AsmPrinter :: EmitToStreamer ( * OutStreamer , Res


<s> static vector_insn_info get_hard_empty ( ) { vector_insn_info info


<s> bool writesElement0 ( ) const { return WritesElement0


<s> MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success


<s> unsigned <ISA_LIT>TTIImpl :: getRegUsageForType ( Type * Ty ) { TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) { if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getKnownMinValue ( ) , <STR_LIT> ) ; if ( ST -> useRVVForFixedLengthVectors ( ) ) return divideCeil ( Size , ST ->


<s> bool hasStdExtB ( ) const { return HasStdExtB


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> bool enableUnalignedScalarMem ( ) const { return EnableUnalignedScalarMem


<s> const <ISA_LIT>Subtarget * getST ( ) const { return ST


<s> return parseRegister ( Operands , 'p' ,


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp


<s> offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; if ( bitmap_bit_p ( components , regno ) ) riscv_save_restore_reg


<s> if ( vector_kill == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_kill [ cfg_bb -> index ] ) ; } fprintf ( file , <STR_LIT> ) ; FOR_ALL_BB_FN ( cfg_bb , cfun ) { fprintf ( file , <STR_LIT> , cfg_bb -> index ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_avin == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_avin [ cfg_bb -> index ] ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_avout == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_avout [ cfg_bb -> index ] ) ; fprintf ( file , <STR_LIT> ) ; if ( vector_del == nullptr ) fprintf ( file , <STR_LIT> ) ; else dump_bitmap_file ( file , vector_del [ cfg_bb -> index ] ) ; } fprintf ( file , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( )


<s> if ( Vec . getValueType ( ) != VT ) return SDValue ( ) ; SDValue Idx = SplatVal . getOperand ( <NUM_LIT> ) ; if ( Idx . getValueType ( ) != Subtarget . getXLenVT ( ) ) return SDValue ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( DAG , VT


<s> SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi ,


<s> if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime


<s> auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal


<s> switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token


<s> } if ( Opcode == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; unsigned Op0Code = Op0 -> getOpcode ( ) ; unsigned Op1Code = Op1 -> getOpcode ( ) ; if ( Op0Code == <STR_LIT> ) return expandOffset ( AM , IsBase , Op1 , cast < ConstantSDNode > ( Op0 ) ) ; if ( Op1Code == <STR_LIT> ) return expandOffset ( AM , IsBase , Op0 , cast < ConstantSDNode > (


<s> Mask = Op . getConstantOperandVal ( <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return None ; bool IsSHL = Op . getOpcode ( ) == <STR_LIT> ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return None ; uint64_t ShAmt = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width || ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ; if ( ! Mask


<s> for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst


<s> for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( ) ; i ++ )

if ( bitmap_bit_p ( bitdata , i ) ) count ++ ;


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> return true ; } ; auto MatchShift = [ & ] ( int Shift ) { for ( int i = <NUM_LIT> ; i != Size - Shift ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != Shift + i ) return false ; return true ; } ; for ( int Shift = <NUM_LIT> ; Shift != Size ; ++ Shift ) if ( CheckUndefs ( Shift ) && MatchShift ( Shift ) ) return Shift ; return - <NUM_LIT>


<s> void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! ( TARGET_HARD_FLOAT || TARGET_ZFINX ) ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags

, <NUM_LIT> ) , NULL_TREE , NULL_TREE ) ;


<s> int get_ma ( rtx ma ) { if ( INTVAL ( ma )

== MASK_ANY ) return INVALID_ATTRIBUTE ;


<s> if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx (


<s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg


<s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( )


<s> } if ( known_ge ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) { if ( MEM_P ( dest ) && ! REG_P ( src ) ) src = force_reg ( mode , src ) ; return false ; } if ( register_operand ( src , mode ) && register_operand ( dest , mode ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_pred_mov ( mode ) , tmp , src , mask_mode ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } if ( satisfies_constraint_vu ( src ) ) return false ; emit_vlmax_op ( code_for_pred_mov ( mode ) , dest , src , mask_mode ) ; return true


<s> if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> void print ( raw_ostream & OS ) const override { auto RegName = [ ] ( unsigned Reg ) { if ( Reg ) return <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; else return <STR_LIT> ; } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy


<s> bool isLegalToVectorizeReduction ( const RecurrenceDescriptor & RdxDesc , ElementCount VF ) const { if ( ! ST -> hasStdExtV ( ) ) return false ; if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; Register SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; emitAuipcInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI


<s> else return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , DstVT , Src ) ; SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , DL , DstVT ) ; return DAG . getSelectCC ( DL , Src , Src , ZeroInt , FpToInt , <STR_LIT>


<s> assert ( ! OuterLoopSetup && <STR_LIT> ) ; if ( LoopSetup ) { OuterLoopSetup = LoopSetup ; } LoopSetup = & MI ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( LoopSetup && <STR_LIT> ) ; Setups . push_back ( LoopSetup ) ; Branches . push_back ( & MI ) ; LoopNums . push_back ( OuterLoopSetup ? <NUM_LIT> : <NUM_LIT>


<s> return new <ISA_LIT>MCInstrAnalysis ( Info


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & )


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize


<s> TailPaddingAmount <ISA_LIT>TargetLowering :: getTailPaddingForPreciseBounds ( uint64_t Size ) const { if ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return TailPaddingAmount :: None ; return <STR_LIT> ( Size , Subtarget .


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> if ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) { MCSubtargetInfo & STI = copySTI (


<s> struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; cum -> num_fprs = info . fpr_offset


<s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( llvm :: any_of ( Regs , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext (

) . diagnose ( DiagnosticInfoUnsupported {