<s> RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back


<s> if ( I -> isCall ( ) || I -> isTerminator ( ) || I -> hasUnmodeledSideEffects ( ) ) return false ; if ( I -> mayStore ( ) || ( ! isLd && I -> mayLoad ( ) ) ) for ( MachineInstr * MemOp : MemOps ) if ( I -> mayAlias ( AA , * MemOp , false ) ) return false ; for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure . insert ( Reg ) ; } } if ( MemRegs . size ( ) <= <NUM_LIT> ) return true ; return AddedRegPressure . size ( ) <= MemRegs . size ( ) *


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy ( )


<s> if ( isSource ( V ) ) return true ; auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I )


<s> unsigned Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . addImm ( ( unsigned ) Pred ) . addReg

( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> SelectionDAG & DAG = CLI . DAG ; const char * <ISA_LIT>16HelperFunction = <NUM_LIT> ; bool Need<ISA_LIT>16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { S -> getSymbol ( ) , <STR_LIT> } ; if ( std :: binary_search ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) { const <ISA_LIT>16IntrinsicHelperType * h = ( std :: find ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) ; <ISA_LIT>16HelperFunction = h -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . Args , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper


<s> void or1k_expand_atomic_compare_and_swap ( rtx operands [ ] ) { rtx boolval , retval , mem , oldval , newval ; rtx label1 , label2 ; machine_mode mode ; bool is_weak ; boolval = operands [ <NUM_LIT> ] ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_compare ( EQ , retval , oldval ) ; emit_unlikely_jump ( EQ , label2 ) ; emit_store_conditional ( mode , mem , newval ) ; if ( ! is_weak ) emit_unlikely_jump ( EQ


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef Cpu , StringRef FeatureString , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CodeModel , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , computeDataLayout ( ) , TT , Cpu , FeatureString , Options , getEffectiveRelocModel ( RM ) , CodeModel , OptLevel ) , Subtarget ( TT , Cpu , FeatureString , * this

, Options , CodeModel , OptLevel ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) {


<s> if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget


<s> int i386_pe_dllimport_name_p ( const char * symbol ) { return ( strncmp ( DLL_IMPORT_PREFIX , symbol , strlen

( DLL_IMPORT_PREFIX ) ) == <NUM_LIT> ) ;


<s> static SDValue ConcatVectors ( SDValue Lower , SDValue Upper , SelectionDAG & DAG ) { DebugLoc dl = Lower . getDebugLoc ( ) ; assert ( Lower . getValueType ( ) == Upper . getValueType ( ) && <STR_LIT> ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , Lower . getValueType ( ) . getVectorElementType ( ) , Lower . getValueType ( ) . getVectorNumElements ( ) * <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Vec = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , Upper , DAG . getConstant ( Lower . getValueType ( ) . getVectorNumElements ( ) , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( Vec , Lower , DAG . getConstant ( <NUM_LIT>


<s> Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , <STR_LIT> ) ; Register DestLoReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestHiReg ) ; Offset += <NUM_LIT> ; } replaceFI ( MF , II , MI , dl , FIOperandNum


<s> unsigned getNumLocalDynamicTLSAccesses ( ) const { return NumLocalDynamics


<s> int negate = - <NUM_LIT> ; unsigned int encoded_nelts = const_vector_encoded_nelts ( value ) ; for ( unsigned int i = <NUM_LIT> ; i < encoded_nelts ; ++ i ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( value , i ) ; if ( ! CONST_SCALAR_INT_P ( elt ) ) return NULL_RTX ; rtx_mode_t val ( elt , int_mode ) ; wide_int pow2 = wi :: neg ( val ) ; if ( val != pow2 ) { if ( negate == ! wi :: neg_p ( val ) ) return NULL_RTX ; negate = wi :: neg_p ( val ) ; if ( ! negate ) pow2 = val ; } int shift = wi :: exact_log2 ( pow2 ) ; if ( shift < <NUM_LIT> ) return NULL_RTX ; builder . quick_push ( gen_int_mode ( shift , int_mode ) ) ; } if ( negate == - <NUM_LIT> ) code = PLUS ; else if ( negate == <NUM_LIT> ) code = code == PLUS ?


<s> switch ( CC ) { case FCOND_F : case FCOND_T : return <STR_LIT> ; case FCOND_UN : case FCOND_OR : return <STR_LIT> ; case FCOND_OEQ : case FCOND_UNE : return <STR_LIT> ; case FCOND_UEQ : case FCOND_ONE : return <STR_LIT> ; case FCOND_OLT : case FCOND_UGE : return <STR_LIT> ; case FCOND_ULT : case FCOND_OGE :


<s> OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitRawText ( <STR_LIT>


<s> MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( Subtarget -> hasAVX ( ) ) MIB . addReg ( OpReg ) ; MIB . addReg ( OpReg ) ; updateValueMap ( I


<s> for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable


<s> if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getValueType ( ) . getSimpleVT ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , <ISA_LIT>CC , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> )


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Op = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Op ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ?


<s> insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp


<s> return TM . getRelocationModel ( ) ==


<s> bool isDarwinABI ( ) const { return isTargetMachO ( ) ||


<s> SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Clz = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Clz , getI64Imm ( <NUM_LIT> , dl ) , getI64Imm (


<s> if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i


<s> MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned UsedRegMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( MRI . isPhysRegModified ( VRRegNo [ i ] ) ) UsedRegMask |= <NUM_LIT> << ( <NUM_LIT> - i ) ; for ( std :: pair < unsigned , unsigned > LI : MF -> getRegInfo ( ) . liveins ( ) ) { unsigned RegNo = TRI -> getEncodingValue ( LI . first ) ; if ( VRRegNo [ RegNo ] == LI . first ) UsedRegMask &= ~ ( <NUM_LIT> << ( <NUM_LIT> - RegNo ) ) ; } for ( MachineFunction :: const_iterator BI = MF -> begin ( ) , BE = MF -> end ( ) ; UsedRegMask != <NUM_LIT> && BI != BE ; ++ BI ) { const MachineBasicBlock & MBB = * BI ; if ( ! MBB . isReturnBlock ( ) ) continue ; const MachineInstr & Ret = MBB . back ( ) ; for ( unsigned I = <NUM_LIT> , E = Ret . getNumOperands ( ) ; I != E ; ++


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> if ( MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) MI = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ; if ( ! MI || MI -> getParent ( ) != & MBB || ( unsigned ) MI -> getOpcode ( ) != MulOpc ) return false ; assert ( MI -> getNumOperands ( ) >= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin (


<s> con += <NUM_LIT> ; if ( strchr ( con , ',' ) != NULL ) { error_at ( loc , <STR_LIT> ) ; continue ; } bool invert = false ; if ( con [ <NUM_LIT> ] == 'n' ) invert = true , con ++ ; machine_mode mode = CCmode ; rtx_code code = UNKNOWN ; switch ( con [ <NUM_LIT> ] ) { case 'a' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = NE ; break ; case 'b' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = NE ; break ; case 'c' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; break ; case 'e' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; case 'g' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GE ; break ; case 'l' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LE ; break ; case 'o' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCOmode , code = EQ ; break ; case 'p' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCPmode , code = EQ ; break ; case 's' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCSmode , code = EQ ; break ; case 'z' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; } if ( code == UNKNOWN ) { error_at ( loc , <STR_LIT> , constraints [ i ] ) ; continue ; } if ( invert ) code = reverse_condition ( code ) ; rtx dest = outputs [ i ] ; if ( ! saw_asm_flag


<s> if ( I != BB . begin ( ) ) PrevMI = prior ( I ) ; ++ NumFP ; DEBUG ( errs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { cerr << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start


<s> const MachineOperand * Op1 = & MI1 . getOperand ( N1 + <STR_LIT> ) ; const MachineOperand * Op2 = & MI2 . getOperand ( N2 + <STR_LIT> ) ; if ( ! isIdenticalOp ( * Op1 , * Op2 ) ) { if ( Op1 -> isImm ( ) && Op2 -> isImm ( ) ) AddrDispShift = Op1 -> getImm ( ) - Op2 -> getImm ( ) ; else if ( Op1 -> isGlobal ( ) && Op2 -> isGlobal ( ) && Op1 -> getGlobal ( ) == Op2 -> getGlobal ( ) ) AddrDispShift = Op1 -> getOffset ( ) - Op2 -> getOffset ( ) ; else return


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >= <STR_LIT> && RegIdx .


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> std :: vector < Type * > AsmArgTypes ; std :: vector < Value * > AsmArgs ; FunctionType * AsmFTy = FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes


<s> static void aof_globalize_label ( FILE * stream , const char * name ) { default_globalize_label ( stream


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Size ) ) ) ; return MCDisassembler ::


<s> if ( ! Subtarget . hasAVX ( ) || ( Factor != <NUM_LIT> && Factor != <NUM_LIT> ) ) return false ; if ( isa < LoadInst > ( Inst ) ) { WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; if ( cast < LoadInst > ( Inst ) -> getPointerAddressSpace ( ) ) return false ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> && Factor == <NUM_LIT> ) return true ; if ( ShuffleElemSize == <NUM_LIT> && isa < StoreInst > ( Inst ) && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; if ( ShuffleElemSize == <NUM_LIT> && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> )


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) { Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = TheTriple . getArch ( ) ==


<s> } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> ,


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> Optional < MCFixupKind > ELF<ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . is<ISA_LIT>64 (


<s> VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } if ( PassThru . isUndef ( ) ) PassThru = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ; SDValue NewGather = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , N -> getMemoryVT ( ) ,


<s> switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> initialize<ISA_LIT>LongBranchPass ( PR ) ; initialize<ISA_LIT>LDCleanupPass ( PR ) ; initialize<ISA_LIT>ShortenInstPass ( PR ) ; initialize<ISA_LIT>PostRewritePass ( PR )


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo )


<s> unsigned long off ; int i ; for ( i = <NUM_LIT> ; i < ( int ) sizeof ( save_order ) ; ++ i ) { reg = sr -> curr . reg + save_order [ i ] ; if ( reg -> where == UNW_WHERE_GR_SAVE ) { reg -> where = UNW_WHERE_GR ; reg -> val = sr -> gr_save_loc ++ ; } } if ( sr -> imask ) { static unsigned char const limit [ <NUM_LIT> ] = { UNW_REG_F31 , UNW_REG_R7 , UNW_REG_B5 } ; unsigned char kind , mask = <NUM_LIT> , * cp = sr -> imask ; int t ; struct unw_reg_info * ( regs [ <NUM_LIT> ] ) ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_F2 ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_R4 ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_B1 ; for ( t = <NUM_LIT> ; t < sr -> region_len ; ++ t ) { if ( ( t & <NUM_LIT> ) == <NUM_LIT> ) mask = * cp ++ ; kind = ( mask >> <NUM_LIT> * ( <NUM_LIT> - ( t & <NUM_LIT> ) ) ) & <NUM_LIT> ; if ( kind > <NUM_LIT> ) spill_next_when ( & regs [ kind - <NUM_LIT> ] , sr -> curr . reg + limit [ kind - <NUM_LIT> ] , sr -> region_start + t ) ; } } if ( sr -> any_spills ) { off = sr -> spill_offset ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_F2 , sr -> curr . reg + UNW_REG_F31 ) ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_B1 , sr -> curr . reg


<s> break ; case <STR_LIT> : assert ( Root . getOperand ( <NUM_LIT> ) . isReg ( ) && Root . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDWI_OP1 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ,


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return <NUM_LIT> ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P (


<s> if ( MI . getDesc ( ) . isCall ( ) ) break ; PotentialBlockers . push_back ( & MI ) ; } if ( BlockLimit < LIMIT ) { MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; int LimitLeft = LIMIT - BlockLimit ; for ( MachineBasicBlock :: pred_iterator PB = MBB -> pred_begin ( ) , PE = MBB -> pred_end ( ) ; PB != PE ; ++ PB ) { MachineBasicBlock * PMBB = * PB


<s> SDValue <ISA_LIT>TargetLowering :: LowerVECREDUCE ( SDValue Op , SelectionDAG & DAG ) const { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; bool OverrideNEON = Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || ( Op . getOpcode ( ) != <STR_LIT> && SrcVT . getVectorElementType ( ) == <STR_LIT> ) ; if ( SrcVT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( SrcVT , OverrideNEON && Subtarget -> useSVEForFixedLengthVectors ( ) ) ) { if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) return LowerPredReductionToSVE ( Op , DAG ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op


<s> if ( Dist < <NUM_LIT> ) { DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate


<s> static bool isSource ( Value * V ) { if ( ! isa < IntegerType > ( V -> getType ( ) ) ) return false ; if ( isa < Argument > ( V ) ) return true ; else if ( isa < LoadInst > ( V


<s> MachineBasicBlock :: iterator CallPt ; MachineInstr * Save ; MachineInstr * Restore ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; Save = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Restore = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) ; } else { Save = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; Restore = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } It = MBB . insert ( It , Save ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; It = MBB . insert ( It , Restore ) ; return CallPt


<s> SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( Upper ? IdxVal - NumElems / <NUM_LIT> : IdxVal , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast <

ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ;


<s> uint64_t MaxVal = ( ( uint64_t ( <NUM_LIT> ) << Bits ) - <NUM_LIT> ) * Scale ; return Val <= MaxVal && ( Val %


<s> O << '[' ; printOperand ( MI , Op , O ) ; O <<


<s> PrintDebugValueComment ( MI , OS ) ; return ; } if ( InConstantPool && MI -> getOpcode ( ) != <STR_LIT> ) { OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId )


<s> TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target (


<s> if ( LoadSDNode * ChainLD = dyn_cast < LoadSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: op_iterator O = ChainNext -> op_begin ( ) , OE = ChainNext -> op_end ( ) ; O != OE ; ++ O ) if ( ! Visited . count ( O -> getNode ( ) ) ) Queue . push_back ( O -> getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ; Queue . clear


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt

( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ;


<s> bool n13_consumed_by_e2_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_rt_dep_reg_p ( consumer , def_reg ) ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , <NUM_LIT> ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; default : gcc_unreachable ( )


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( )


<s> const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) / <NUM_LIT> ; unsigned FGR32RegSize = <STR_LIT> . getSize ( ) / <NUM_LIT> ; unsigned AFGR64RegSize = <STR_LIT> . getSize ( ) / <NUM_LIT> ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; unsigned i , e = CSI . size ( ) ; for ( i = <NUM_LIT> ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) break ; unsigned RegNum = get<ISA_LIT>RegisterNumbering ( Reg ) ; if ( <STR_LIT> . contains (


<s> return <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectAddrModeXRO ( MachineOperand & Root , unsigned SizeInBytes ) const { MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; if ( isBaseWithConstantOffset ( Root , MRI ) ) return None ; auto AddrModeFns = selectAddrModeShiftedExtendXReg ( Root , SizeInBytes ) ; if ( AddrModeFns )


<s> if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! ( Subtarget . hasAVX512 ( ) && InSVT == <STR_LIT> ) && ! ( Subtarget . hasBWI ( ) && InSVT == <STR_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL


<s> } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsWin64 ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> >


<s> return ( uint32x2_t ) __builtin_neon_vqshrun_nv2di ( __a ,


<s> return ( ( qword ) ( vec_xor ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) ( si_from_uint ( b


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I


<s> static const <ISA_LIT>MCExpr * CreateABS_G1_NC ( const MCExpr * Expr , MCContext


<s> RestoreGPRRegs . LowGPR = Low ; RestoreGPRRegs . HighGPR = High


<s> if ( Mask == - <NUM_LIT> ) return - <NUM_LIT> ; return Mask << <NUM_LIT> ; } if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { return - <NUM_LIT> ; } if ( Flags . empty ( ) || Flags == <STR_LIT> ) return Mask | <NUM_LIT> ; for ( char Flag : Flags ) { int FlagVal ; switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal =


<s> NumIssued = <NUM_LIT> ; HasCTRSet = false ; NumStores =


<s> bool isMem ( RegisterKind RegKind , MemoryKind MemKind ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) &&

( MemKind == BDLMem ) == ( Mem . Length != <NUM_LIT> ) ) ;


<s> if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) return <NUM_LIT> ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE )


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( )


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( DestRC == <STR_LIT> &&


<s> GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer .

getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF )


<s> int xstormy16_legitimate_address_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x , int strict ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( ( GET_CODE ( x ) == PRE_MODIFY && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == REG && REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) && ( ! strict || REGNO (

x ) < FIRST_PSEUDO_REGISTER ) ) return <NUM_LIT> ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( )


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc


<s> for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; ++ i ) { if ( ix86_tune_no_default ) ix86_tune_features [ i ] = <NUM_LIT> ; else ix86_tune_features [ i ] = ! ! (

initial_ix86_tune_features [ i ] & ix86_tune_mask ) ;


<s> this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true )


<s> Register Reg = Op . getReg ( ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; return false


<s> else if ( orig_tune_defaulted ) opts -> x_ix86_tune_string = NULL ; if ( enum_opts_set . x_ix86_fpmath ) opts_set -> x_ix86_fpmath = ( enum fpmath_unit ) <NUM_LIT> ; if ( enum_opts_set . x_prefer_vector_width_type ) opts_set -> x_prefer_vector_width_type = ( enum prefer_vector_width ) <NUM_LIT> ; bool r = ix86_option_override_internal ( false , opts , opts_set ) ; if ( ! r ) { release_options_strings ( option_strings ) ; return error_mark_node ; } ix86_add_new_builtins ( opts -> x_ix86_isa_flags , opts -> x_ix86_isa_flags2 ) ; enum excess_precision orig_ix86_excess_precision = opts -> x_ix86_excess_precision ; bool orig_ix86_unsafe_math_optimizations = opts -> x_ix86_unsafe_math_optimizations ; opts -> x_ix86_excess_precision = opts -> x_flag_excess_precision ; opts -> x_ix86_unsafe_math_optimizations = opts -> x_flag_unsafe_math_optimizations ; t = build_target_option_node ( opts , opts_set ) ; opts -> x_ix86_arch_string = orig_arch_string ; opts -> x_ix86_tune_string = orig_tune_string ; opts_set -> x_ix86_fpmath = orig_fpmath_set ; opts_set -> x_prefer_vector_width_type = orig_pvw_set ; opts -> x_ix86_excess_precision = orig_ix86_excess_precision ; opts -> x_ix86_unsafe_math_optimizations = orig_ix86_unsafe_math_optimizations ; release_options_strings (


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( ! <STR_LIT> ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || isPositionIndependent ( ) ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return false


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode


<s> ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) )


<s> return std :: pair < unsigned , unsigned > ( RegSeq


<s> virtual void finalizePass ( ) { popTTIStack ( )


<s> case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Call : return selectCall (


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( GP0Regs [ Base ] )


<s> RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) { RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; result = ( uint8x8_t ) __builtin_aarch64_tbx4v8qi ( ( int8x8_t ) __r , __o , ( int8x8_t ) __idx ) ; return


<s> static SDValue lowerV8I64VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , const SmallBitVector & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 ,

Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: findReloadPosition ( MachineInstr * MI )


<s> } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; int64_t Cnt ; unsigned VShiftOpc = <NUM_LIT> ; switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { VShiftOpc = <STR_LIT> ; break ; } if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) { VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : if ( Cnt == VT . getVectorElementType ( ) . getSizeInBits ( ) ) VShiftOpc = <STR_LIT> ; else VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ;


<s> if ( N0 . hasOneUse ( ) && N0 . getOpcode ( ) == <STR_LIT> ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( EVT == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDLoc DL ( N0 ) ; SDValue Ops [ ] = { N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 . getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } return SDValue ( )


<s> set = single_set ( out_insn ) ; if ( ! set ) return <NUM_LIT> ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) == GET_MODE_SIZE ( other_mode


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned add = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( add ) ) ; return S


<s> assert ( isWhileLoopStart ( MI ) && <STR_LIT> ) ; unsigned Op = MI . getOpcode ( )


<s> if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo ,


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } SDValue ThreadPointer = DAG . getNode (


<s> SDValue <ISA_LIT>TargetLowering :: LowerTLSDescCall ( SDValue SymAddr , SDValue DescAddr , SDLoc DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; SDValue Func , Chain ; Func = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getEntryNode ( ) , DescAddr ) ; SDValue Glue ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * A64RI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = A64RI -> getTLSDescCallPreservedMask ( ) ; std :: vector < SDValue > Ops ; Ops . push_back


<s> for ( arg = DECL_ARGUMENTS ( current_function_decl ) ; arg ; arg = TREE_CHAIN ( arg ) ) { rtx incoming = DECL_INCOMING_RTL ( arg ) ; if ( incoming && ix86_check_avx256_register ( incoming ) ) return AVX_U128_DIRTY ; } return AVX_U128_CLEAN


<s> const char * getPassName ( ) const override


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) ||


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> enum rtx_code rs6000_reverse_condition ( machine_mode mode , enum rtx_code code ) { if ( mode == CCFPmode && ( ! flag_finite_math_only || code == UNLT || code == UNLE || code ==

UNGT || code == UNGE || code == UNEQ || code == LTGT ) ) return reverse_condition_maybe_unordered ( code ) ;


<s> WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI

-> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ;


<s> if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , [ this ] ( const


<s> static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } } return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind ,


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return ( int


<s> Opcode = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; assert ( Subtarget -> hasAVX ( ) && <STR_LIT> ) ; unsigned ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , true , OpReg , false ) ; updateValueMap ( I , ResultReg


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return


<s> if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Ctx , Fixup . getLoc ( ) , Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ; return getRelocType32 ( Modifier , getType32 (


<s> if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getScalarSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType (


<s> static DecodeStatus DecodeT2AddrModeImm7s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7S4 ( Inst , imm , Address , Decoder


<s> union { __ev64_opaque__ v ; uint32_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] =


<s> PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode


<s> if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , false ) ) return false ; for ( APInt Elt : EltBits ) RawMask . push_back ( Elt . getZExtValue ( ) ) ; return


<s> static const MCInstrDesc * UpdateOp ( MachineInstr & MI , const <ISA_LIT>InstrInfo * II , unsigned Opcode ) { const MCInstrDesc * Desc = & II -> get ( Opcode ) ; MI . setDesc ( * Desc ) ; return Desc


<s> SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( )


<s> assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , NewBB . begin ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; const MachineJumpTableInfo & MJTI = * MF -> getJumpTableInfo ( ) ; const MachineJumpTableEntry & JTE = MJTI . getJumpTables ( ) [ JTI ] ; for ( const MachineBasicBlock * MBB : JTE . MBBs ) { if ( MBB != & OldBB ) continue ; -- BlockJumpTableRefCount [ MBB ] ; ++ BlockJumpTableRefCount [ & NewBB


<s> static void addAndInterleaveWithUnsupported ( LegalizerInfo :: SizeAndActionsVec & result , const LegalizerInfo :: SizeAndActionsVec & v ) { for ( unsigned i = <NUM_LIT> ; i < v . size ( )


<s> case 'n' : if ( ! TARGET_SIMD ) return - <NUM_LIT> ; return <NUM_LIT> ; default : gcc_unreachable ( )


<s> NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , false , false , true ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addReg ( LdReg , false , false , true ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , LdReg , NumBytes , <STR_LIT> , <NUM_LIT> , & TII , true , dl ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , false , false , true ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , false ,


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask

[ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ;


<s> if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes (

) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> str += <NUM_LIT> ; } parse_res = aarch64_parse_extension ( str , & isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { aarch64_isa_flags = isa_flags ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr , str


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Op1 || Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType


<s> return MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) &&


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args


<s> if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> ) return false ; return ( AllowI1 && VT == <STR_LIT> ) ||


<s> void getAnalysisUsage ( AnalysisUsage &


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c


<s> return ( vector unsigned int ) __builtin_altivec_vsubuwm ( ( vector signed int ) a1 ,


<s> offset = par_index * <NUM_LIT> ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET (


<s> BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs )

; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ;


<s> int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; assert ( isSingleInputShuffleMask ( Mask ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ]

% Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ;


<s> if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int NumElems = VT . getVectorNumElements ( ) ; EVT CanonVT = VT . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> ; i < NumElems ; ++ i ) Mask . push_back ( EltNo ) ; V1 = DAG . getNode ( <STR_LIT> , dl , CanonVT , V1 ) ; return DAG . getNode ( <STR_LIT> , dl , NVT , DAG . getVectorShuffle ( CanonVT , dl , V1 , DAG . getUNDEF

( CanonVT ) , & Mask [ <NUM_LIT> ] ) ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc =

getZeroVector ( VT , Subtarget , DAG , dl ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'b' : case 'r' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> ,


<s> int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber ( ) ; if ( DTNumber < JTNumber ) { MachineBasicBlock * NewBB = adjustJTTargetBlockForward ( MBB , MI -> getParent ( ) ) ; if ( NewBB ) MJTI -> ReplaceMBBInJumpTable ( JTI , JTBBs [ j ] , NewBB ) ; MadeChange = true


<s> if ( ! hasMVE ( ) || Operands . size ( ) < <NUM_LIT> ) return true ; for ( auto & Operand : Operands ) { if ( static_cast < <ISA_LIT>Operand & > ( * Operand ) . isVectorIndex ( ) || ( Operand -> isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operand -> getReg ( ) ) ) ) ) return false ; } return true


<s> const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy == LLT :: scalar ( <NUM_LIT> ) ) { unsigned AndOpc ; if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return


<s> } ; LoadInst * DomLoad = DT -> dominates ( Base , Offset ) ? Base : Offset ; IRBuilder < NoFolder > IRB ( DomLoad -> getParent ( ) , ++ BasicBlock :: iterator ( DomLoad ) ) ; const unsigned AddrSpace = DomLoad -> getPointerAddressSpace ( ) ; Value * VecPtr = IRB . CreateBitCast ( Base -> getPointerOperand ( ) , LoadTy -> getPointerTo ( AddrSpace ) ) ; LoadInst * WideLoad = IRB . CreateAlignedLoad ( LoadTy , VecPtr , Base -> getAlign ( ) ) ; MoveBefore ( Base -> getPointerOperand ( ) , VecPtr ) ; MoveBefore ( VecPtr , WideLoad ) ; Value * Bottom = IRB . CreateTrunc ( WideLoad , Base -> getType ( ) ) ; Value * NewBaseSExt = IRB . CreateSExt ( Bottom , BaseSExt -> getType ( ) ) ; BaseSExt -> replaceAllUsesWith ( NewBaseSExt ) ; IntegerType * OffsetTy = cast < IntegerType > ( Offset -> getType ( ) ) ; Value * ShiftVal = ConstantInt :: get ( LoadTy , OffsetTy -> getBitWidth (


<s> SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , DL ,


<s> Out . EmitInstruction ( Inst ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return InstrInfo . get


<s> PM . add ( createUnpackMachineBundlesPass ( ) ) ; } PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return true


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return ParseMemOperand ( <NUM_LIT> , Parser . getTok ( ) . getLoc ( ) ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return <NUM_LIT> ; if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) { Error ( Start , <STR_LIT> ) ; return <NUM_LIT> ; } if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) . Lex


<s> const struct cpu_regmove_cost * regmove_cost = aarch64_tune_params . regmove_cost ; if ( to == TAILCALL_ADDR_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == TAILCALL_ADDR_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && hard_reg_set_subset_p ( reg_class_contents [ from_i ] , reg_class_contents [ FFR_REGS ] ) ) return <NUM_LIT> ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG ) ) return regmove_cost -> GP2GP ; if ( to == STACK_REG || from == STACK_REG ) return aarch64_register_move_cost ( mode , from , GENERAL_REGS ) + aarch64_register_move_cost ( mode , GENERAL_REGS , to ) ; if ( known_eq ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) { if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP * <NUM_LIT> ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP * <NUM_LIT> ; else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP * <NUM_LIT> ; if ( ! TARGET_SIMD ) return regmove_cost -> GP2FP + regmove_cost -> FP2GP + regmove_cost -> FP2FP ; return regmove_cost -> FP2FP ; } if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP ; else if ( to == GENERAL_REGS ) return regmove_cost ->


<s> if ( IMM12_OPERAND ( - rhs ) ) { * op0 = loongarch_force_binary ( GET_MODE ( * op0 ) , PLUS , * op0 , GEN_INT ( - rhs ) ) ; * op1 = const0_rtx ; } } else { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; bool decrement = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; if ( ! increment && ! decrement ) continue ; new_rhs = rhs + ( increment ? <NUM_LIT> : - <NUM_LIT> ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) && ( rhs < <NUM_LIT> ) == ( new_rhs < <NUM_LIT> ) ) { * op1 = GEN_INT (


<s> Out . EmitCFIAdjustCfaOffset ( <NUM_LIT> ) ; Out . EmitCFIRelOffset ( MRI -> getDwarfRegNum ( LocalFrameReg , true ) , <NUM_LIT> ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( LocalFrameReg ) . addReg ( FrameReg ) ) ; Out . EmitCFIRememberState ( ) ; Out . EmitCFIDefCfaRegister ( MRI -> getDwarfRegNum ( LocalFrameReg , true ) ) ; } EmitAdjustRSP ( Ctx , Out , - <NUM_LIT> ) ; SpillReg ( Out , RegCtx . ShadowReg ( <NUM_LIT> ) ) ; SpillReg ( Out , RegCtx . AddressReg ( <NUM_LIT> ) ) ; if ( RegCtx . ScratchReg ( <NUM_LIT> ) != <STR_LIT> ) SpillReg ( Out , RegCtx . ScratchReg


<s> SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT


<s> gen_vec_shr = vmode == E_V16QImode ? gen_vec_shr_v16qi : gen_vec_shr_v8hi ; gen_vec_shl = vmode == E_V16QImode ? gen_vec_shl_v16qi : gen_vec_shl_v8hi ; imode = GET_MODE_INNER ( vmode ) ; inner_size = GET_MODE_BITSIZE ( imode ) ; op0 = gen_reg_rtx ( vmode ) ; op1 = gen_reg_rtx ( vmode ) ; if ( start1 ) emit_insn ( gen_vec_shr ( op0 , d -> op0 , GEN_INT ( start1 * inner_size ) ) ) ; else emit_move_insn ( op0 , d -> op0 ) ; dop1 = d -> op1 ; if ( d -> one_operand_p ) dop1 = d -> op0 ; int shl_offset = end1 - start1 + <NUM_LIT> - start2 % nelt ; if ( shl_offset ) emit_insn ( gen_vec_shl ( op1 , dop1 , GEN_INT ( shl_offset * inner_size ) ) ) ; else emit_move_insn ( op1 , dop1 ) ; if ( clear_op0 || clear_op1 ) { rtx vec [ <NUM_LIT> ] ; rtx const_vec ; rtx clear ; for ( i = <NUM_LIT> ; i != nelt ; i ++ ) { if ( i < ( end1 - start1 + <NUM_LIT> ) ) vec [ i ] = gen_int_mode ( ( HOST_WIDE_INT_1U << inner_size ) - <NUM_LIT> , imode ) ; else vec [ i ] =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> MVT NVT = <STR_LIT> ( <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NVT , N0 ) ) ; } case <STR_LIT> : case <STR_LIT> : return lowerUINT_TO_FP_vXi32 ( Op , DAG , * Subtarget ) ; case <STR_LIT> : case <STR_LIT>


<s> c = ( __v2du ) vec_cmpeq ( __A , __A ) ; d = ( __v2du ) vec_cmpeq ( __B , __B ) ; __v2du a , b ; __v2du c , d ; const __v2du double_exp_mask = { <NUM_LIT> , <NUM_LIT> } ; a = ( __v2du ) vec_abs ( ( __v2df ) __A ) ; b = ( __v2du ) vec_abs ( ( __v2df ) __B ) ; c = ( __v2du ) vec_cmpgt ( double_exp_mask , a ) ; d = ( __v2du ) vec_cmpgt ( double_exp_mask , b ) ; return ( ( __m128d ) vec_and


<s> break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) || ( isTargetMachO ( ) && ! HasV6Ops ) ) ReservedGPRegisters . set ( <NUM_LIT> ) ; const int restFP = ( useR7AsFramePointer ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( isGPRegisterReserved ( restFP ) ) report_fatal_error ( <STR_LIT> + std :: to_string ( restFP ) + <STR_LIT> ) ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance =


<s> Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; auto * CByte = dyn_cast < ConstantSDNode > (


<s> unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) { EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * I ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB =


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> void Emitter < CodeEmitter > :: emitGlobalAddress ( GlobalValue * GV , unsigned Reloc , bool NeedStub ,


<s> void addGPR32as64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p (


<s> if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align


<s> if ( isInt < <NUM_LIT> > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg ( ) ; if ( ! ATReg ) return ; unsigned LoOffset = Offset


<s> int mmix_eh_return_data_regno ( int n ) { if ( n >= <NUM_LIT> && n < <NUM_LIT> ) return MMIX_EH_RETURN_DATA_REGNO_START + n ; return INVALID_REGNUM


<s> case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static __inline void si_stqx ( qword a , qword b , qword c ) { vec_st ( ( vec_uchar16 ) ( a ) , si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( b ) , (

vec_uint4 ) ( c ) ) ) ) , ( vector unsigned char * ) ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , MachineInstr :: mmo_iterator MMOBegin , MachineInstr :: mmo_iterator MMOEnd , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get


<s> CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags


<s> bool <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo .


<s> bool isReg ( ) const { return Kind ==


<s> IsV9 ( false ) , V8DeprecatedInsts ( false ) , IsVIS ( false ) , Is64Bit ( is64Bit ) { const char * CPU = <STR_LIT> ; if (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getHiLo16ImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; const MCExpr * E = MO . getExpr ( ) ; MCFixupKind Kind ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( E ) ) { const int64_t Value = MCE -> getValue ( ) ; if ( Value > UINT32_MAX ) report_fatal_error ( <STR_LIT> ) ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : return ( int32_t ( Value ) & <NUM_LIT> ) >> <NUM_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << C << <STR_LIT> << ( IsLegal ? <STR_LIT> : <STR_LIT> ) ) ; return IsLegal


<s> if ( stack_realign_fp ) return ( ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM )

|| ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ) ;


<s> static DecodeStatus DecodeCall ( MCInst & Inst , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , true


<s> void <ISA_LIT>InstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern :: MC_PATTERN Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstIdxForVirtReg ) const { MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * Prev = nullptr ; switch ( Pattern ) { case MachineCombinerPattern :: MC_REASSOC_AX_BY : case MachineCombinerPattern :: MC_REASSOC_XA_BY : Prev = MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg


<s> return ( cost + set_src_cost ( XEXP ( x , <NUM_LIT> ) , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , GET_CODE ( x ) ,


<s> else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * this , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * this , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) ; emitSPUpdate ( MBB , MBBI , TII , dl , * this , VARegSaveSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MBB . erase ( MBBI


<s> if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && SecondOpcode == <STR_LIT> ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> )


<s> FCmp32Libcalls . resize ( CmpInst :: LAST_FCMP_PREDICATE + <NUM_LIT> ) ; FCmp32Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: O_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SGT } , { RTLIB :: OLT_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: ICMP_EQ } , { RTLIB :: UO_F32 , CmpInst :: ICMP_NE } } ; FCmp64Libcalls . resize ( CmpInst :: LAST_FCMP_PREDICATE + <NUM_LIT> ) ; FCmp64Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F64 , CmpInst :: ICMP_SGE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F64 , CmpInst :: ICMP_SGT } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F64 , CmpInst :: ICMP_SLE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F64 , CmpInst :: ICMP_SLT } } ; FCmp64Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: O_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F64 ,


<s> static bool DisassembleStFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { return DisassembleLdStFrm ( MI , Opcode , insn , NumOps , NumOpsAdded


<s> int <ISA_LIT>AsmParser :: getATReg ( )


<s> assert ( m_CurrentGOTPart < m_MultipartList . size ( ) && <STR_LIT> ) ; if ( m_MultipartList [ m_CurrentGOTPart ] . isConsumed (


<s> gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1


<s> bool Changed = false ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed


<s> SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT>


<s> int m16_simm8_8 ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return m16_check_op ( op , ( - <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ,


<s> int iq2000_adjust_insn_length ( rtx insn , int length ) { if ( simplejump_p ( insn ) || ( ( GET_CODE ( insn ) == JUMP_INSN || GET_CODE ( insn

) == CALL_INSN ) ) ) length += <NUM_LIT> ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectNegArithImmed ( MachineOperand & Root ) const { if ( ! Root . isReg ( ) ) return None ; auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None ) return None ; uint64_t Immed = * MaybeImmed ; if ( Immed == <NUM_LIT> ) return None ; MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; if ( MRI . getType ( Root . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) Immed = ~ ( ( uint32_t ) Immed ) + <NUM_LIT> ; else Immed = ~ Immed + <NUM_LIT> ; if ( Immed & <NUM_LIT> ) return None ; Immed &=


<s> char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ]