<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O


<s> if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode


<s> InstructionCost Cost = getVectorIntrinsicInstrCost ( ICA . getID ( ) , ICA . getReturnType ( ) ) ; if ( Cost != - <NUM_LIT> ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA ,


<s> static SDValue PromoteSplat ( ShuffleVectorSDNode * SV , SelectionDAG & DAG ) { EVT SrcVT = SV -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SV -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SV -> getDebugLoc ( ) ; int EltNo = SV -> getSplatIndex ( ) ; int NumElems = SrcVT . getVectorNumElements


<s> static inline unsigned getThumbImmNonShiftedVal ( unsigned V ) { return V >> getThumbImmValShift ( V


<s> insertCall ( Op1 ) ; return true ; } default : break ; } errs ( ) << <STR_LIT> + utostr ( Opcode )


<s> SDValue EltCond = BuildVector -> getOperand ( i ) ; SDValue SndLaneEltCond = ( NumLanes == <NUM_LIT> ) ? BuildVector -> getOperand ( i + NumElemsInLane ) : EltCond ; int Lane1Cond = - <NUM_LIT> , Lane2Cond = - <NUM_LIT> ; if ( isa < ConstantSDNode > ( EltCond ) ) Lane1Cond = ! isZero ( EltCond ) ; if ( isa < ConstantSDNode > ( SndLaneEltCond ) ) Lane2Cond = ! isZero ( SndLaneEltCond ) ; if ( Lane1Cond == Lane2Cond || Lane2Cond < <NUM_LIT> ) MaskValue |= ! Lane1Cond << i ; else if ( Lane1Cond < <NUM_LIT> ) MaskValue |= ! Lane2Cond << i ; else return false ; } return true


<s> <ISA_LIT>TTI :: PopcntSupportKind <ISA_LIT>TTI :: getPopcntSupport ( unsigned TyWidth )


<s> return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg

( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> virtual const <ISA_LIT>FrameInfo * getFrameInfo (


<s> case NAME ## rri : \ case NAME ## rzi : \ case NAME ## iri : \ case NAME ## izi : \ case NAME ## rri_nt : \ case NAME ## rzi_nt : \ case NAME ## iri_nt : \ case NAME ## izi_nt : \ case NAME ## rri_t : \ case NAME ## rzi_t : \ case NAME ## iri_t : \ case NAME ## izi_t : case NAME ## rr : \ case NAME ## ir : \ case NAME ## rr_nt : \ case NAME ## ir_nt : \ case NAME ## rr_t : \ case NAME ## ir_t : { using namespace llvm ::


<s> cmp_bytes = bytes_to_compare ; if ( extra_bytes < offset ) { offset -= extra_bytes ; cmp_bytes = load_mode_size ; bytes_to_compare = cmp_bytes ; } } else cmp_bytes = bytes_to_compare ; rtx offset_rtx ; if ( BYTES_BIG_ENDIAN || TARGET_AVOID_XFORM ) offset_rtx = GEN_INT ( offset ) ; else { offset_rtx = gen_reg_rtx ( Pmode ) ; emit_move_insn ( offset_rtx , GEN_INT ( offset ) ) ; } rtx addr1 = gen_rtx_PLUS ( Pmode , src1_addr , offset_rtx ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , src2_addr , offset_rtx ) ; do_load_for_compare_from_addr ( load_mode , tmp_reg_src1 , addr1 , orig_src1 ) ; do_load_for_compare_from_addr ( load_mode , tmp_reg_src2 , addr2 , orig_src2 ) ; unsigned HOST_WIDE_INT remain = bytes_to_compare - cmp_bytes ; if ( load_mode_size != <NUM_LIT> ) { if ( load_mode_size < word_mode_size ) { rtx sh = GEN_INT ( BITS_PER_UNIT * ( word_mode_size - load_mode_size ) ) ; do_rotl3 ( tmp_reg_src1 , tmp_reg_src1 , sh ) ; do_rotl3 ( tmp_reg_src2 , tmp_reg_src2 , sh ) ; } if ( cmp_bytes < word_mode_size ) { HOST_WIDE_INT mb = BITS_PER_UNIT * ( word_mode_size - cmp_bytes ) ; rtx mask = GEN_INT ( HOST_WIDE_INT_M1U << mb ) ; do_and3 ( tmp_reg_src1 , tmp_reg_src1 , mask ) ; do_and3 ( tmp_reg_src2 , tmp_reg_src2 , mask ) ; } } rtx dst_label ; if ( remain > <NUM_LIT> || equality_compare_rest ) { if ( ! cleanup_label ) cleanup_label = gen_label_rtx ( ) ; dst_label = cleanup_label ; } else dst_label = final_move_label ; if ( load_mode_size == <NUM_LIT> ) { if ( equality_compare_rest ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , final_move_label ) ; rtx cond = gen_reg_rtx


<s> vmovn_high_u64 ( uint32x2_t a , uint64x2_t b ) { uint32x4_t result = vcombine_u32 ( a , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i32gather_ps ( __m512i index , __mmask16 mask , void * addr , int scale , int hint ) { __builtin_ia32_gatherpfdps ( mask , ( __v16si ) index , ( int const * ) addr , scale


<s> rtx_insn * next ; found_barrier = from ; if ( barrier_align ( from ) > <NUM_LIT> ) good_barrier = from ; next = NEXT_INSN ( from ) ; if ( next && NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) break ; } if ( broken_move ( from ) ) { rtx pat , src , dst ; machine_mode mode ; pat = PATTERN ( from ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; src = SET_SRC ( pat ) ; dst = SET_DEST ( pat ) ; mode = GET_MODE ( dst ) ; if ( GET_CODE ( src ) == UNSPEC && PIC_ADDR_P ( XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) ) ) last_got = last_got ? NULL : from ; else if ( PIC_ADDR_P ( src ) ) last_got = last_got ? NULL : from ; if ( mode == HImode || ( mode == SImode && satisfies_constraint_I16 ( src ) && REGNO ( dst ) != FPUL_REG ) ) { found_hi += <NUM_LIT> ; si_limit -= <NUM_LIT> ; } else { while ( si_align > <NUM_LIT> && found_si + si_align - <NUM_LIT> > count_si ) si_align >>= <NUM_LIT> ; if ( found_si > count_si ) count_si = found_si ; found_si += GET_MODE_SIZE ( mode ) ; if ( num_mova ) si_limit -= GET_MODE_SIZE ( mode ) ; } } if ( mova_p ( from ) ) { switch ( untangle_mova ( & num_mova , & mova , from ) ) { case <NUM_LIT> : if ( flag_pic ) { rtx src = SET_SRC ( PATTERN ( from ) ) ; if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_SYMOFF ) last_symoff = from ; } break ; case <NUM_LIT> : return find_barrier ( <NUM_LIT> , <NUM_LIT> , mova ) ; case <NUM_LIT> : { leading_mova = <NUM_LIT> ; barrier_before_mova = good_barrier ? good_barrier : found_barrier ; } default : break ; } if ( found_si > count_si ) count_si = found_si ; } else if ( JUMP_TABLE_DATA_P ( from ) && GET_CODE ( PATTERN ( from ) ) == ADDR_DIFF_VEC ) { if ( ( num_mova > <NUM_LIT> && GET_MODE ( prev_nonnote_insn ( from ) ) == VOIDmode ) || ( num_mova && ( prev_nonnote_insn

( from ) == XEXP ( MOVA_LABELREF ( mova ) , <NUM_LIT> ) ) ) ) num_mova -- ;


<s> machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( <NUM_LIT> , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + <NUM_LIT> ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( <NUM_LIT> , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: getCapGlobalReg ( SelectionDAG & DAG , EVT Ty ) const { assert ( Ty . isFatPointer


<s> bool isAlignedMemory32 ( ) const { if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false , <NUM_LIT>


<s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( Subtarget -> isSingleFloat ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasSEInReg ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> bool isUImm12Offset ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm (


<s> static bool sparc_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '#' || code == '*' || code == '(' || code == ')' || code == '_' ||


<s> return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Aligned || ( imm & <NUM_LIT> ) == <NUM_LIT> ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } Disp = DAG . getTargetConstant ( imm , dl , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! Aligned || ( Imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , dl , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) && ( ! Aligned || ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , dl , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , dl , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else Base =


<s> else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Index , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } return


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Src -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , Call , <STR_LIT> , Ops , CallOptions , dl , Chain ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp


<s> Val = <NUM_LIT> ; StringRef LineBuf ( Identifier . data ( ) ) ; SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; const char * EndPtr = Tok . getLoc ( ) .


<s> putc ( '\n' , stream ) ; } else if ( write_symbols == DBX_DEBUG ) return ; else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ; fprintf ( stream , <STR_LIT> , num_source_filenames ) ; output_quoted_string ( stream , name


<s> static rtx_insn * emit_frame_insn ( rtx x ) { rtx_insn * insn = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return


<s> switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : if ( opts -> x_flag_pic ) aarch64_cmodel = AARCH64_CMODEL_TINY_PIC ; break ; case AARCH64_CMODEL_SMALL : if ( opts -> x_flag_pic ) { aarch64_cmodel = ( flag_pic == <NUM_LIT> ?


<s> } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC )


<s> case VK_CALL : return <STR_LIT> ; case VK_LO12 : return <STR_LIT> ; case VK_ABS_G3 : return <STR_LIT> ; case VK_ABS_G2 : return <STR_LIT> ; case VK_ABS_G2_S : return <STR_LIT> ; case VK_ABS_G2_NC : return <STR_LIT> ; case VK_ABS_G1 : return <STR_LIT> ; case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_PREL_G3 : return <STR_LIT> ; case VK_PREL_G2 : return <STR_LIT> ; case VK_PREL_G2_NC : return <STR_LIT> ; case VK_PREL_G1 : return <STR_LIT> ; case VK_PREL_G1_NC : return <STR_LIT> ; case VK_PREL_G0 : return <STR_LIT> ; case VK_PREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return <STR_LIT> ; case VK_TPREL_LO12_NC : return <STR_LIT> ; case VK_TLSDESC_LO12 : return <STR_LIT> ; case VK_ABS_PAGE : return <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange0_32 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> >= ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeUImm6 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } case <STR_LIT> :


<s> if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) return Reg - <STR_LIT> ; if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) return Reg - <STR_LIT> ; if ( Reg == <STR_LIT> ) return <NUM_LIT> ; if ( Reg == <STR_LIT> ) return


<s> return TM . getRelocationModel ( ) == Reloc :: RWPI ||

TM . getRelocationModel ( ) == Reloc :: ROPI_RWPI ;


<s> void <ISA_LIT>FastTileConfig :: getTileShapesCfg ( MachineInstr * CfgMI , SmallVector < MachineOperand * > & ShapedTiles ) { MachineInstr * KeyMI = getKeyAMXInstr ( CfgMI ) ; SmallVector < MachineOperand * > DefTiles ; for ( MachineOperand & MO : KeyMI -> operands ( ) ) { if ( ! isTilePhysReg ( MO ) ) continue ; if ( MO . isDef ( ) ) DefTiles . push_back (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getShifter ( )


<s> MVT castType ; if ( VT . is32BitVector ( ) ) castType = <STR_LIT> ; else if ( VT . is64BitVector ( ) )


<s> State = IES_ERROR ; break ; case IES_PLUS : case IES_NOT : State =


<s> return true ; } return false ; } ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { const SDValue & Src = Op . getOperand ( i ) ; unsigned BitOffset = i * SrcEltSizeInBits ; if ( Src . isUndef ( ) ) { UndefBits . setBits ( BitOffset , BitOffset + SrcEltSizeInBits ) ; continue ; } auto * Cst = cast < ConstantSDNode > ( Src ) ; APInt Bits = Cst -> getAPIntValue ( ) . zextOrTrunc ( SrcEltSizeInBits ) ; MaskBits |= Bits . zext ( SizeInBits ) . shl ( BitOffset ) ; } return SplitBitData ( ) ; } if ( auto * Cst = getTargetConstantFromNode ( Op ) ) { Type * CstTy = Cst -> getType ( ) ; if ( ! CstTy -> isVectorTy ( ) || ( SizeInBits != CstTy -> getPrimitiveSizeInBits ( ) ) ) return false ; unsigned CstEltSizeInBits = CstTy -> getScalarSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> , e = CstTy -> getVectorNumElements ( ) ; i != e ; ++ i ) if ( ! CollectConstantBits ( Cst -> getAggregateElement ( i ) , MaskBits , UndefBits , i * CstEltSizeInBits ) ) return false ; return SplitBitData ( ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && EltSizeInBits <= SrcEltSizeInBits ) { if ( auto * Broadcast = getTargetConstantFromNode ( Op . getOperand ( <NUM_LIT> ) ) ) { APInt Bits ( SizeInBits , <NUM_LIT> ) ; APInt Undefs ( SizeInBits , <NUM_LIT> ) ; if ( CollectConstantBits ( Broadcast , Bits , Undefs , <NUM_LIT> ) ) { for ( unsigned i = <NUM_LIT> ; i != NumSrcElts ; ++ i ) { MaskBits |= Bits . shl ( i


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Comments


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; return


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getDarwinDirective ( ) == <STR_LIT> ) return true ; return


<s> return ( __m128i ) __builtin_ia32_packsswb128 ( ( __v8hi )


<s> void <ISA_LIT>16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return canBeExpandedToORR ( MI


<s> static bool CallIsStructReturn ( CallSDNode * TheCall ) { unsigned NumOps = TheCall ->


<s> case EXTRACT_LAST_REDUCTION : return sve_costs -> clast_cost ; case FOLD_LEFT_REDUCTION : switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_HFmode : case E_BFmode : return sve_costs ->


<s> void <ISA_LIT>GNULDBackend :: defineGOTSymbol ( IRBuilder & pBuilder ) { if ( m_pGOTSymbol != NULL ) { pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOTPLT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ; } else { m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOTPLT -> begin ( ) ) , <NUM_LIT> )


<s> static unsigned HOST_WIDE_INT arm_shift_truncation_mask ( enum


<s> void <ISA_LIT>MCAsmStreamer :: EmitIntValue ( uint64_t


<s> return DecodeVecShiftRImm ( Inst , Imm , <NUM_LIT>


<s> CurrGroupSize = <NUM_LIT> ; CurrGroupHas4RegOps = false ; clearProcResCounters ( ) ; GrpCount = <NUM_LIT> ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI =


<s> unsigned Val = Shifter . Val ; return <STR_LIT> ( Val ) == <STR_LIT> && ( <STR_LIT> ( Val ) == <NUM_LIT> || <STR_LIT> (


<s> assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( OS ,


<s> SDValue BasePtr = MGS -> getBasePtr ( ) ; <STR_LIT> IndexType = MGS -> getIndexType ( ) ; EVT IdxVT = Index . getValueType ( ) ; if ( DCI . isBeforeLegalize ( ) ) { if ( ( IdxVT . getVectorElementType ( ) == <STR_LIT> ) || ( IdxVT . getVectorElementType ( ) == <STR_LIT> ) ) { EVT NewIdxVT = IdxVT . changeVectorElementType ( <STR_LIT> ) ; if ( MGS -> isIndexSigned ( ) ) Index = DAG . getNode ( <STR_LIT> , DL , NewIdxVT , Index ) ; else Index = DAG . getNode ( <STR_LIT> , DL , NewIdxVT , Index ) ; if ( auto * MGT = dyn_cast < MaskedGatherSDNode > ( MGS ) ) { SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Ops [ ] = { Chain , PassThru , Mask , BasePtr , Index , Scale } ; return DAG . getMaskedGather ( DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) , PassThru . getValueType ( ) , DL , Ops , MGT -> getMemOperand ( ) , MGT -> getIndexType ( ) , MGT -> getExtensionType ( ) ) ; } else { auto * MSC = cast < MaskedScatterSDNode > ( MGS ) ; SDValue Data = MSC -> getValue ( ) ; SDValue Ops [ ] = { Chain , Data , Mask , BasePtr ,


<s> static void signOutlinedFunction ( MachineFunction & MF , MachineBasicBlock & MBB , bool ShouldSignReturnAddr , bool ShouldSignReturnAddrWithAKey ) { if ( ShouldSignReturnAddr ) { MachineBasicBlock :: iterator MBBPAC = MBB . begin ( ) ; MachineBasicBlock :: iterator MBBAUT = MBB . getFirstTerminator ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL ; if ( MBBAUT != MBB . end ( ) ) DL = MBBAUT -> getDebugLoc ( ) ; unsigned PACI ; if ( ShouldSignReturnAddrWithAKey ) { PACI = Subtarget . hasPAuth ( ) ? <STR_LIT> : <STR_LIT> ; } else { BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; PACI = Subtarget . hasPAuth ( ) ? <STR_LIT> : <STR_LIT> ; } auto MI = BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( PACI ) ) ; if ( Subtarget . hasPAuth ( ) ) MI . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: InternalRead ) ; MI . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createNegateRAState ( nullptr ) ) ; BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; if ( Subtarget . hasPAuth ( ) && MBBAUT != MBB . end ( ) && MBBAUT -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBAUT , DL , TII -> get ( ShouldSignReturnAddrWithAKey ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBAUT ) ; MBB . erase ( MBBAUT


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case V2SImode : case V2SFmode : perm2 [ <NUM_LIT> ] = elt ; perm2 [ <NUM_LIT> ] = elt + <NUM_LIT> ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( HasAVX2 ) return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( HasAVX2 ) return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div16qi (


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> static DecodeStatus DecodeCoprocessor ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) return MCDisassembler


<s> if ( BranchRelaxation ) addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( )

) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> if ( ! canWidenShuffleElements ( Mask , Zeroable , WidenedMask ) ) return SDValue ( ) ; bool IsLowZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; bool IsHighZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; if ( WidenedMask [ <NUM_LIT> ] == <NUM_LIT> && IsHighZero ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 ,


<s> if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++


<s> if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == std :: numeric_limits < int32_t > :: min ( ) ; } return false


<s> bool SelectAddrModeIndexed32 ( SDValue N , SDValue & Base


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : break ; default : return false ; } if ( isa < MCBinaryExpr > ( BE -> getLHS ( ) ) ) { if ( ! isa < MCConstantExpr > ( BE -> getRHS ( ) ) ) return


<s> bool is64Bit ( ) const { return Root -> getType ( ) -> isIntegerTy


<s> <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } MFI -> setAdjustsStack


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> ) !=


<s> return __builtin_aarch64_uqrshlqi_uus ( __a ,


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> void MLxExpansion :: clearStack ( ) { std :: fill ( LastMIs , LastMIs + <NUM_LIT> , ( MachineInstr * ) <NUM_LIT>


<s> if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT (


<s> } output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_INTERWORK || arm_arch4t ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> ,


<s> static bool isBlockingStore ( int64_t LoadDispImm , unsigned LoadSize , int64_t StoreDispImm , unsigned


<s> MVT VMVT = TLI . getValueType ( V -> getType ( ) , true ) . getSimpleVT ( ) ; if ( ( VMVT == <STR_LIT> ) || ( VMVT == <STR_LIT> ) ) { unsigned TempReg = createResultReg ( &


<s> unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << * MI ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else if ( isMla ( MI ) ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AccumReg , TRI ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ActiveChains [ AccumReg ] -> add ( MI , Idx , getColor ( DestReg ) ) ; if ( DestReg != AccumReg ) { ActiveChains [ DestReg ] = ActiveChains [ AccumReg ] ; ActiveChains . erase (


<s> SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2


<s> else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && current_function_calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_load == <NUM_LIT> && local_fsize == <NUM_LIT> && VAL_14_BITS_P ( - actual_fsize ) ) merge_sp_adjust_with_load = regno ; else load_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) { if ( merge_sp_adjust_with_load == <NUM_LIT> && local_fsize == <NUM_LIT> && VAL_14_BITS_P ( - actual_fsize ) ) merge_sp_adjust_with_load = i ; else load_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { if ( frame_pointer_needed ) set_reg_plus_d ( <NUM_LIT> , FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; else set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( regs_ever_live [ i ] || ( ! TARGET_64BIT && regs_ever_live [ i + <NUM_LIT> ] ) ) { rtx src = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( DFmode , tmpreg ) ) ; rtx dest = gen_rtx_REG ( DFmode ,


<s> default : return true ; case ELF :: R_<ISA_LIT>_PREL31 : case ELF :: R_<ISA_LIT>_ABS32 : return


<s> void function_expander :: rotate_inputs_left ( unsigned int start , unsigned int end ) { rtx new_last = args [ start ] ; for ( unsigned int i = start ; i < end - <NUM_LIT> ; ++ i ) args [ i ]


<s> bool isMemOffs64_16 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return false


<s> assert ( Kind == k_MSRMask && <STR_LIT> ) ; return MMask


<s> for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i , ++ Low ) if ( ! isUndefOrZero ( Mask [ i ] ) && Mask [ i ] != Low ) return false ; return


<s> return getSubtargetImpl ( ) -> getFrameLowering (


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) return true ; return ( RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI


<s> return genFusedMultiply ( MF , MRI , TII , Root , InsInstrs , IdxMulOpd ,

MaddOpc , RC , FMAInstKind :: Indexed ) ;


<s> } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlign ( ) . value ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J


<s> SDLoc DL ( Op ) ; EVT InVT = Op . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; ( void ) TLI ; assert ( VT . isScalableVector ( ) && TLI . isTypeLegal ( VT ) && InVT . isScalableVector ( ) && TLI . isTypeLegal ( InVT ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> ) == ( InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == VT ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; EVT PackedVT = getPackedSVEVectorVT ( VT . getVectorElementType ( ) ) ; EVT PackedInVT = getPackedSVEVectorVT ( InVT . getVectorElementType ( ) ) ; assert ( ( VT == PackedVT || InVT == PackedInVT ) && <STR_LIT> ) ; if ( InVT != PackedInVT ) Op = DAG . getNode ( <STR_LIT> , DL ,


<s> void OutgoingValueHandler :: assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , <NUM_LIT> ) ; MIRBuilder . buildStore ( ValVReg ,


<s> } if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; unsigned FixupKind ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_LO


<s> break ; case <ISA_LIT>_64_RELOC_SIGNED_2 : Expr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( Sym , Ctx ) , MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_SIGNED_1 : Expr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( Sym , Ctx ) , MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_GOT_LOAD : Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_GOT : Expr = MCSymbolRefExpr :: Create ( Sym , isPCRel ? MCSymbolRefExpr :: VK_GOTPCREL : MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_SUBTRACTOR : { Rel . moveNext ( ) ; any_relocation_info RENext = Obj -> getRelocation ( Rel . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != <ISA_LIT>_64_RELOC_UNSIGNED ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = Rel . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol (


<s> const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && STI . hasSym32 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName ,


<s> switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - <NUM_LIT> ; if ( ! TARGET_AVX ) return <NUM_LIT> ; return TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; case 'c' : if ( ! TARGET_AVX ) return - <NUM_LIT> ; return TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - <NUM_LIT> ; return <NUM_LIT> ; case 'e' : if ( ! TARGET_AVX512F ) return - <NUM_LIT> ; return


<s> SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue Src0 = N -> getValue ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { if ( NumElts == <NUM_LIT> ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ; DAG . UpdateNodeOperands ( N , Ops ) ; return Op ; } NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , NumElts ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; if ( IndexVT . getScalarType ( ) == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; MVT MaskBitVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; assert ( MaskVT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , NumElts ) ; Mask = ExtendToType ( Mask , ExtMaskVT , DAG , true ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskBitVT , Mask ) ; MVT NewVT = <STR_LIT> ( VT . getScalarType ( ) ,


<s> MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskState = getRegState ( MIB -> getOperand ( <NUM_LIT> ) ) ; unsigned Opc = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . RemoveOperand ( <NUM_LIT> ) ; MIB -> setDesc ( get ( Opc ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( MaskReg , MaskState ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : return expandNOVLXLoad ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXLoad ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXLoad ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXLoad ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXStore ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXStore ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXStore ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return expandNOVLXStore ( MIB , & getRegisterInfo ( ) , get ( <STR_LIT> ) , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT>


<s> unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | <NUM_LIT> ; unsigned flags = fieldFromInstruction ( Insn ,


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask ,


<s> __arm_stcl ( const unsigned int __coproc , const unsigned


<s> case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useLoc , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint

, MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseLO32DSP ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL ,


<s> rtx tmp_reg ; rtx tp_reg = gen_rtx_REG ( Pmode , TP_REGNUM ) ; rtx pat , insns , reg0 ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC ) pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSGD ) ; else pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSLD ) ; pat = gen_rtx_CONST ( SImode , pat ) ; reg0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; insns = emit_call_insn ( gen_tls_desc ( pat , GEN_INT ( relax_group_id ) ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insns ) , pic_offset_table_rtx ) ; RTL_CONST_CALL_P ( insns ) = <NUM_LIT> ; tmp_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp_reg , reg0 ) ; x = tmp_reg ; break ; case TLS_MODEL_INITIAL_EXEC : pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSIE ) ; tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_ie ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; if ( flag_pic ) emit_use ( pic_offset_table_rtx ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSLE ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; default : gcc_unreachable ( ) ; } else if ( GET_CODE ( x ) == CONST ) { rtx base , addend ; split_const ( x , & base , & addend ) ; if ( SYMBOL_REF_TLS_MODEL ( base ) == TLS_MODEL_LOCAL_EXEC ) { tmp_reg = gen_reg_rtx (


<s> Subtarget -> getMReginfo ( ) . emit<ISA_LIT>ReginfoSectionCG ( OutStreamer , getObjFileLowering ( ) , *


<s> } } MVT VT ; if ( ! isTypeLegal ( LI -> getType ( ) , VT , true ) ) return false ; const Value * Ptr = LI -> getPointerOperand ( ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg , LI -> getAlign ( ) .


) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ;


<s> for ( MachineInstr & MI : MBB ) if ( MI . definesRegister ( <STR_LIT> ) || MI

. definesRegister ( <STR_LIT> ) ) return true ;


<s> Mask <<= N1C -> getAPIntValue ( ) ; bool MaskOK = false ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( N00 . getOpcode ( ) == <STR_LIT> && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) ; } if ( MaskOK && Mask != <NUM_LIT>


<s> MCSymbol * <ISA_LIT>_64MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , Mangler * Mang


<s> return gen_rtx_SET ( VOIDmode , gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , gen_rtx_fmt_ee ( code


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegList ( SmallVectorImpl < unsigned > & Regs , SMLoc StartLoc , SMLoc EndLoc , <ISA_LIT>AsmParser & Parser ) { assert ( Regs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; auto Op = make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ; Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( ) ; for ( auto Reg : Regs ) Op -> RegList . List -> push_back ( Reg ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc =


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ; else TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer . EmitLabel (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateProcIFlags ( <STR_LIT> IFlags , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ProcIFlags ) ; Op -> IFlags . Val = IFlags ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ; ArgSize = ( ( ArgSize + PtrByteSize - <NUM_LIT> ) /


<s> rtx rperm [ <NUM_LIT> ] [ <NUM_LIT> ] , vperm , l , h , op , m128 ; unsigned int i , nelt , eltsz ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( ! TARGET_SSSE3 || ( GET_MODE_SIZE ( d -> vmode ) != <NUM_LIT> && GET_MODE_SIZE ( d -> vmode ) != <NUM_LIT> && GET_MODE_SIZE ( d -> vmode ) != <NUM_LIT> ) ) return false ; gcc_assert ( ! d -> one_operand_p ) ; if ( d -> testing_p ) return true ; switch ( GET_MODE_SIZE ( d -> vmode ) ) { case <NUM_LIT> : mode = V4QImode ; gen = gen_mmx_pshufbv4qi3 ; break ; case <NUM_LIT> : mode = V8QImode ; gen = gen_mmx_pshufbv8qi3 ; break ; case <NUM_LIT> : mode = V16QImode ; gen = gen_ssse3_pshufbv16qi3 ; break ; default : gcc_unreachable ( ) ; } nelt = d -> nelt ; eltsz = GET_MODE_UNIT_SIZE ( d -> vmode ) ; m128 = GEN_INT ( - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , k , e = d -> perm [ i ] ; unsigned which = ( e >= nelt ) ; if ( e >= nelt ) e -= nelt ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ i * eltsz + j ] = m128 ; } for ( k = i * eltsz + j ; k < <NUM_LIT> ; ++ k ) rperm [

<NUM_LIT> ] [ k ] = rperm [ <NUM_LIT> ] [ k ] = m128 ;


<s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup


<s> int GetRegIndexForOperand ( MachineInstr & MI , int OperandIndex ) ; void clearUsedRegisterList ( ) { UsedRegisters . clear ( ) ; } void markRegisterUsed ( int registerIndex ) { UsedRegisters . push_back ( registerIndex ) ; } int getUnusedFPRegister ( MachineRegisterInfo &


<s> if ( ! isDoubleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> &&


<s> unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid ; StringRef Name = MapperClass ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; assert ( Valid && <STR_LIT> ) ; if ( Valid ) O


<s> __builtin_ia32_pmovqw256mem_mask ( ( unsigned long long * ) __P , ( __v4di ) __A


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVESpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT>


<s> SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , Load . getDebugLoc ( ) , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = CallSeqStart . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( CallSeqStart . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( CallSeqStart , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT>


<s> if ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getToken ( ) == <STR_LIT> || static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getToken ( ) == <STR_LIT> ) ) { if ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isToken ( ) && ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getToken ( ) == <STR_LIT> || static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . getToken ( ) == <STR_LIT> ) ) RegIdx = <NUM_LIT> ; if ( static_cast < <ISA_LIT>Operand & > ( * Operands [ RegIdx ] ) . isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( static_cast < <ISA_LIT>Operand & > ( * Operands [ RegIdx ] ) . getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( static_cast < <ISA_LIT>Operand & > ( * Operands [ RegIdx ] ) . getReg ( ) ) ) ) return true ; } return


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; unsigned Op0Opcode = Op0 -> getOpcode ( ) ; if ( Op0Opcode == <STR_LIT> || Op0Opcode == <STR_LIT> ) { ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ! Mask ) return SDValue ( ) ; int32_t Log2IfPositive = ( Mask -> getAPIntValue ( ) + <NUM_LIT> ) . exactLogBase2 ( ) ; if ( Log2IfPositive <= <NUM_LIT> ) return SDValue (


<s> const TargetRegisterClass * RC ; std :: string Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; assert ( Prefix == <STR_LIT> ) ; RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) + Reg ) ,


<s> unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ; } return true


<s> int64_t Val = CE -> getValue ( ) ; return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ; } return false


<s> if ( I -> isDebugValue ( ) ) continue ; std :: bitset < <NUM_LIT> > Defs ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; MachineInstr & MI = * I ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) - <STR_LIT> ; if ( Reg >= <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) { Defs . set ( Reg ) ; if ( ! LPR . contains ( MO . getReg ( ) ) )


<s> static const char * sparc_mangle_fundamental_type ( tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return <STR_LIT> ; return


<s> const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) -


<s> StringRef Name = Tok . getString ( ) ; if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; return false ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; return false ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = <STR_LIT> ; IntVal = <NUM_LIT> ; return false ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = is<ISA_LIT>64 ( ) ? XRegs [ IntVal ] : RRegs [ IntVal ] ; return false ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = FRegs [ IntVal ] ; return false ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VRegs [ IntVal ] ; return false ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = CRRegs


<s> assert ( Last . getParent ( ) == First . getParent ( ) && <STR_LIT> ) ; assert ( InstrPos . find ( & First ) != InstrPos . end ( ) && InstrPos . find ( & Last ) != InstrPos . end ( ) && <STR_LIT> ) ; return InstrPos [ & Last ]


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) |


<s> EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT


<s> OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) ,


<s> MCInst BICInst ; const int32_t EncodedMask = <STR_LIT> ( Mask ) ; assert ( EncodedMask != - <NUM_LIT> ) ; BICInst . setOpcode ( <STR_LIT> ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( EncodedMask


<s> vtrn_u8 ( uint8x8_t a , uint8x8_t b ) { return ( uint8x8x2_t ) { vtrn1_u8 ( a , b ) , vtrn2_u8 (


<s> bool IsKnown ; auto MRSMapper = <STR_LIT> ( ) ; uint32_t MRSReg = MRSMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto MSRMapper = <STR_LIT> ( ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> rtx set , clobber ; gcc_assert ( reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX ) ; fprintf ( stderr , <STR_LIT> , line , store_p ? <STR_LIT>


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer (

) . getTargetStreamer ( ) && <STR_LIT> ) ;


<s> static DecodeStatus DecodeVLDST4Instruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned size = fieldFromInstruction ( Insn


<s> <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const TargetInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( MBB , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> )


<s> SDValue V1Mask [ <NUM_LIT> ] ; SDValue V2Mask [ <NUM_LIT> ] ; V1InUse = false ; V2InUse = false ; int Size = Mask . size ( ) ; int Scale = <NUM_LIT> / Size ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i / Scale ] == - <NUM_LIT> ) { V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; else V = V1InUse ? V1 : V2 ; return DAG . getNode ( <STR_LIT> , DL ,


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG .


<s> __inline__ static void sh_media_FPUTSCR ( float fg ) { __asm__ ( <STR_LIT> : : <STR_LIT> ( fg )


<s> if ( Op . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> )


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Reg , Imm8 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind (


<s> if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine (


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HADDBuilder ) ; } if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL (


<s> bool FixupLEAPass :: runOnMachineFunction ( MachineFunction & Func ) { MF = & Func ; const <ISA_LIT>Subtarget & ST = Func . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = ST . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) <<


<s> switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( IsVarArg ) { report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs


<s> if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc ==


<s> Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> )


<s> bool isBrTarget ( ) { return isBrImm ( )


<s> void addBranchTargetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : PN -> ops ( ) ) { if ( ! ToPromote . count ( V . getNode ( ) ) && V . getValueType ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V ) ) { SDValue ReplOpOps [ ] = { ISR . getOperand ( <NUM_LIT> ) , V , ISR . getOperand ( <NUM_LIT> ) } ; SDNode * ReplOp = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( V ) , ISR . getNode ( ) -> getVTList ( ) , ReplOpOps ) ; Ops . push_back ( SDValue ( ReplOp , <NUM_LIT> ) ) ; } else { Ops . push_back ( V ) ; } } SmallVector < EVT , <NUM_LIT> > NewVTs ; SDVTList VTs = PN -> getVTList ( ) ; for ( unsigned i = <NUM_LIT> , ie = VTs . NumVTs ; i != ie ; ++ i ) if ( VTs . VTs [ i ] == <STR_LIT> ) NewVTs . push_back ( <STR_LIT> ) ; else NewVTs . push_back ( VTs . VTs [ i ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; CurDAG -> SelectNodeTo ( PN , NewOpcode , CurDAG -> getVTList ( NewVTs ) , Ops ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; if ( foldOffsetIntoAddress ( G -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; if ( foldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; if ( foldOffsetIntoAddress ( BA -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || M == CodeModel :: Small || M == CodeModel :: Kernel ) { assert ( N . getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset (


<s> if ( cum -> aapcs_stack_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode


<s> const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) )


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; } return true


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++


<s> static void AnalyzeVarArgs ( CCState & State , const SmallVectorImpl <


<s> const MCInstrDesc & <ISA_LIT>16InstrInfo :: AddiuSpImm ( int64_t Imm ) const { if ( validSpImm8 ( Imm ) ) return get ( <STR_LIT> ) ; else return get ( <STR_LIT>


<s> uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT>


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR (


<s> int64_t Imm = MI -> getOperand ( Op ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> SDValue Flag ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF


<s> SDLoc DL ( N ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOneValue ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isNullValue ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getAnyExtOrTrunc ( Src . getOperand ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; return SDValue ( )


<s> return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ; } return SDValue (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) { if ( Rt == <NUM_LIT> || Rt == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } else Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder


<s> unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == <NUM_LIT> ) return ~ <NUM_LIT> ; switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case


<s> static inline unsigned char getBaseOpcodeFor (


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ? <NUM_LIT> : <NUM_LIT> ) ; if ( builtin_sha1cpm_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 , op3 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat


<s> void <ISA_LIT>CodeEmitter :: emitNEONDupInstruction ( const MachineInstr & MI ) { unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= ( IsThumb ? <STR_LIT> : II -> getPredicate ( & MI ) ) << <STR_LIT> ; unsigned RegT = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; RegT = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT>


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand ( OpNum ) . getImm


<s> assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem .


<s> virtual const InstrItineraryData getInstrItineraryData ( )


<s> static bool mips_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { if ( TARGET_OLDABI ) return ( VECTOR_FLOAT_TYPE_P ( type ) || TYPE_MODE ( type ) == BLKmode ) ; return ( ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT> , <NUM_LIT>


<s> else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } else { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } } if ( dstreg == basereg ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + <NUM_LIT> , operands + <NUM_LIT> ) ; if ( CSKY_CONST_OK_FOR_I ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Uc ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Ub ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; if ( CSKY_CONST_OK_FOR_I ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Uc ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Ub ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else gcc_unreachable ( ) ; } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , <NUM_LIT> ) ; int srcreg = REGNO ( src ) ; int basereg = - <NUM_LIT> ; struct csky_address op0 ; decompose_csky_address ( XEXP ( dst , <NUM_LIT> ) , & op0 ) ; if ( GET_CODE ( memexp ) == REG ) basereg = REGNO ( memexp ) ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else gcc_unreachable ( ) ; } else gcc_unreachable ( ) ; if ( CSKY_VREG_P ( srcreg ) ) { if ( op0 . index ) { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } else { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } } if ( srcreg == basereg ) return <STR_LIT> ; else return <STR_LIT> ; } else gcc_unreachable


<s> static DecodeStatus DecodeVCVTQ ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - imm ) ) ; return


<s> if ( <STR_LIT> ( N1 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( SDValue Not = IsNOT ( N0 , DAG ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( VT , Not ) , N1 ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; auto GetDemandedMasks = [ & ] ( SDValue Op , bool Invert = false ) { APInt UndefElts ; SmallVector < APInt > EltBits ; int NumElts = VT . getVectorNumElements ( ) ; int EltSizeInBits = VT . getScalarSizeInBits ( ) ; APInt DemandedBits = APInt :: getAllOnes ( EltSizeInBits ) ; APInt DemandedElts = APInt :: getAllOnes ( NumElts ) ; if ( getTargetConstantBitsFromNode ( Op , EltSizeInBits , UndefElts , EltBits ) ) { DemandedBits . clearAllBits ( ) ; DemandedElts . clearAllBits ( ) ; for ( int I = <NUM_LIT> ; I != NumElts ; ++ I ) if ( ( Invert && ! EltBits [ I ] . isAllOnes ( ) ) || ( ! Invert && ! EltBits [ I ] . isZero ( ) ) ) { DemandedBits |= Invert ? ~ EltBits [ I ] : EltBits [ I ] ; DemandedElts . setBit ( I ) ; } } return std :: make_pair ( DemandedBits , DemandedElts ) ; } ; std :: pair < APInt , APInt > Demand0 = GetDemandedMasks ( N1 ) ; std :: pair < APInt , APInt > Demand1 = GetDemandedMasks (