<s> SDValue <ISA_LIT>TargetLowering :: expandIndirectJTBranch ( const SDLoc & dl , SDValue Value , SDValue Addr , SelectionDAG & DAG ) const { const Module * M = DAG . getMachineFunction ( ) . getMMI ( ) . getModule ( ) ; Metadata * IsCFProtectionSupported = M -> getModuleFlag ( <STR_LIT> ) ; if ( IsCFProtectionSupported ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , Addr ) ; } return TargetLowering :: expandIndirectJTBranch ( dl , Value


<s> const MCExpr * Val ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) { return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else if ( SM . onIdentifierExpr ( Val , Identifier , Info , false , ErrMsg ) ) { return Error ( IdentLoc , ErrMsg ) ; } else break ; } if ( unsigned OpKind = IdentifyIntelInlineAsmOperator ( Identifier ) ) { if ( OpKind == IOK_OFFSET ) return Error ( IdentLoc , <STR_LIT> <STR_LIT> ) ; if ( int64_t Val = ParseIntelInlineAsmOperator ( OpKind ) ) { if ( SM . onInteger ( Val , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; } else return true ; break ; } if ( Identifier . count ( '.' ) && PrevTK == AsmToken :: RBrac ) { if ( ParseIntelDotOperator ( SM , End ) ) return true ; break ; } if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return true ; else if ( SM . onIdentifierExpr ( Val , Identifier , Info , true , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; break ; } case AsmToken :: Integer : { SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef IDVal = getTok ( ) . getString ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { MCSymbol * Sym = getContext ( ) . getDirectionalLocalSymbol ( IntVal , IDVal == <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; const MCExpr * Val = MCSymbolRefExpr :: create ( Sym , Variant , getContext ( ) ) ; if ( IDVal == <STR_LIT> && Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> ) ; StringRef Identifier = Sym -> getName ( ) ; InlineAsmIdentifierInfo Info ; if ( SM . onIdentifierExpr ( Val , Identifier , Info , isParsingInlineAsm ( ) , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; End = consumeToken ( ) ; } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } break ; } case AsmToken :: Plus


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter (


<s> bool hasFPRegs64 ( ) const { return HasFPRegs64


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SType , <STR_LIT>


<s> return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal == <NUM_LIT> || Mem


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; else return LowerToTLSExecModels ( GA , DAG


<s> unsigned int src1 = REGNO ( operands [ <NUM_LIT> ] ) ; unsigned int src2 = REGNO ( operands [ <NUM_LIT> ] ) ; machine_mode halfmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; unsigned int halfregs = REG_NREGS ( operands [ <NUM_LIT> ] ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest , <NUM_LIT> ) ; desthi = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>LoopDataPrefetchPass


<s> void <ISA_LIT>16DAGToDAGISel :: initGlobalBaseReg ( MachineFunction & MF ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * )


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return hasFP ( MF ) ? <STR_LIT> :


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> unsigned IsData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool IsStream = ! Locality ; if ( Locality ) { assert ( Locality <= <NUM_LIT> && <STR_LIT> ) ; Locality = <NUM_LIT> - Locality ; } unsigned PrfOp = ( IsWrite << <NUM_LIT> ) | ( ! IsData << <NUM_LIT> ) | ( Locality << <NUM_LIT> ) | ( unsigned ) IsStream ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant (

PrfOp , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; assert ( ( KnownZero & KnownOne )


<s> machine_mode mode ; if ( crtl -> return_rtx != <NUM_LIT> ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE (


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; ++ NumUBrFixed


<s> if ( * insn_ptr && r10k_needs_protection_p_1 ( x , * insn_ptr )


<s> int FirstInputOp = Predicated ? <NUM_LIT> : <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( FirstInputOp ) ) ; Ops . push_back ( N -> getOperand ( FirstInputOp + <NUM_LIT> ) ) ; uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( FirstInputOp + <NUM_LIT> ) , N -> getOperand ( FirstInputOp - <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc , VT ) ; uint16_t Opcode = SelectFPOpcode ( VT ,


<s> int hppa_can_use_return_insn_p ( void ) { return ( reload_completed && ( compute_frame_size ( get_frame_size ( ) , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) && ! regs_ever_live [ <NUM_LIT> ]


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( - CE


<s> AssemblerDialect = AsmWriterVariant == Default ? <NUM_LIT> : AsmWriterVariant ; PointerSize = <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; Code32Directive = <STR_LIT> ; Data16bitsDirective =


<s> Relocator :: Result unsupported ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { return Relocator ::


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di (


<s> if ( ! MCE ) return isSymbolicUImm12Offset ( getImm ( ) , Scale ) ; int64_t Val = MCE -> getValue ( ) ; return ( Val % Scale ) == <NUM_LIT> && Val >= <NUM_LIT> && (


<s> int words = <NUM_LIT> ; if ( ! TARGET_SH5 && sh_pass_in_reg_p ( * cum , mode , type ) && ! ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && ( sh_round_reg ( * cum , mode ) + ( mode != BLKmode ? CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) : CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - sh_round_reg ( * cum , mode ) ; else if ( ! TARGET_SHCOMPACT && SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) words = NPARM_REGS ( SImode ) - cum -> arg_count [ SH_ARG_INT ] ; return words


<s> bool ix86_modes_tieable_p ( enum machine_mode mode1 , enum machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) >= <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ; return


<s> unsigned get<ISA_LIT>BranchTargetOpValue ( const MachineInstr &


<s> static DecodeStatus DecodeVecShiftR16Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm , <NUM_LIT>


<s> int64_t Imm = Op . getImm ( ) ; O << markup ( <STR_LIT> ) << '$' << formatImm ( Imm ) << markup ( <STR_LIT> ) ; if ( CommentStream && ! HasCustomInstComment && ( Imm > <NUM_LIT> || Imm < - <NUM_LIT> ) ) { if ( Imm == ( int16_t ) ( Imm ) ) * CommentStream << format ( <STR_LIT> PRIX16 <STR_LIT> , ( uint16_t ) Imm ) ; else if ( Imm == ( int32_t ) ( Imm ) ) * CommentStream << format ( <STR_LIT> PRIX32 <STR_LIT> , ( uint32_t ) Imm ) ; else * CommentStream << format ( <STR_LIT> PRIX64 <STR_LIT> , ( uint64_t ) Imm ) ; } } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << markup ( <STR_LIT> )


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) ,

FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> return ( vector signed int ) __builtin_altivec_vcmpequw ( ( vector signed int ) a1 , (


<s> return __builtin_mve_vsubq_n_uv8hi ( __a ,


<s> unsigned Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , Value >>= <NUM_LIT> ) { Imm |= ( Value & <NUM_LIT> ) << i ; } Inst . addOperand ( MCOperand :: createImm ( Imm | <NUM_LIT>


<s> static DecodeStatus DecodeShiftRight64Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler


<s> Constant * Int = <STR_LIT> ( M , <STR_LIT> , Tys , <NUM_LIT> ) ; Value * Op = CI -> getOperand ( <NUM_LIT> ) ; Op = CallInst :: Create ( Int , Op , CI -> getName ( ) , CI ) ; CI -> replaceAllUsesWith ( Op ) ; CI -> eraseFromParent ( ) ; return true


<s> DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getBitcast ( VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleHigh128VectorInsertLow ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getUNDEF ( VT ) , V , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleLow128VectorInsertHigh ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , <NUM_LIT> , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getUNDEF ( VT ) , V , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo (


<s> if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return


<s> if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { unsigned TempReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; DestReg =


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Comma : case AsmToken :: RBrac : case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( BaseReg , nullptr , S , E ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Parser . Lex ( ) ; break ; case AsmToken :: Minus : break ; } <ISA_LIT>Operand * Offset = nullptr ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand


<s> if ( Value > UINT32_MAX ) report_fatal_error ( <STR_LIT> ) ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : return ( int32_t ( Value ) & <NUM_LIT> ) >> <NUM_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } llvm_unreachable (


<s> } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) { Op2Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op2Reg , <NUM_LIT> ) ; Op1Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op1Reg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; }


<s> bool IsZero = false ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) == <NUM_LIT> ; else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; if ( ! IsZero ) return false ; Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; return


<s> static DecodeStatus DecodeInsSize ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Pos += <NUM_LIT> ; int Size ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Size = ( int ) Insn - Pos + <NUM_LIT> ; else Size = ( int ) Insn - Pos


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> I . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Symbol , OutContext )


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT>


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn

( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> s = division ; if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } if ( TARGET_CHECK_ZERO_DIV ) { if ( TARGET_MIPS16 ) { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } else if ( GENERATE_DIVIDE_TRAPS ) { if ( TUNE_74K ) output_asm_insn ( <STR_LIT> , operands ) ; else { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } } else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( s , operands ) ; s =


<s> machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; bool collisionparts [ <NUM_LIT> ] ; if ( TARGET_64BIT && GET_MODE_SIZE ( GET_MODE ( operands [ <NUM_LIT> ] ) ) == <NUM_LIT> ) { if ( MEM_P ( operands [ <NUM_LIT> ] ) && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) operands [ <NUM_LIT> ] = get_pool_constant ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( push_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { operands [ <NUM_LIT> ] = copy_rtx ( operands [ <NUM_LIT> ] ) ; PUT_MODE ( operands [ <NUM_LIT> ] , word_mode ) ; } else operands [ <NUM_LIT> ] = gen_lowpart ( DImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_lowpart ( DImode , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } if ( push_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) push = <NUM_LIT> ; else gcc_assert ( ! MEM_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ; nparts = ix86_split_to_parts ( operands [ <NUM_LIT> ] , part [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) ) ; ix86_split_to_parts ( operands [ <NUM_LIT> ] , part [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) ) ; if ( push && MEM_P ( operands [ <NUM_LIT> ] ) && reg_overlap_mentioned_p ( stack_pointer_rtx , operands [ <NUM_LIT> ] ) ) { rtx src_base = XEXP ( part [ <NUM_LIT> ] [ nparts - <NUM_LIT> ] , <NUM_LIT> ) ; if ( ! TARGET_64BIT && nparts == <NUM_LIT> && mode == XFmode && TARGET_128BIT_LONG_DOUBLE ) src_base = plus_constant ( Pmode , src_base , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nparts ; i ++ ) part [ <NUM_LIT> ] [ i ] = change_address ( part [ <NUM_LIT> ] [ i ] , GET_MODE ( part [ <NUM_LIT> ] [ i ] ) , src_base ) ; } if ( REG_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) && MEM_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) { rtx tmp ; for ( i = <NUM_LIT> ; i < nparts ; i ++ ) { collisionparts [ i ] = reg_overlap_mentioned_p ( part [ <NUM_LIT> ] [ i ] , XEXP ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( collisionparts [ i ] ) collisions


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction (


<s> unsigned Directive = <STR_LIT> ; for ( const Function & F : M ) { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; unsigned FDir = STI . getDarwinDirective ( ) ; Directive = Directive > FDir ? FDir : STI . getDarwinDirective ( ) ; if ( STI . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; } assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> if ( RLAmt [ i ] != VRI . RLAmt ) continue ; Mask |= ( <NUM_LIT> << i ) ; } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; SDValue TotalVal ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; if ( ! Res ) Res = TotalVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , TotalVal ) , <NUM_LIT> ) ; eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt ; } )


<s> bool Res = compressInst ( CInst , TmpInst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; EmitToStreamer ( * OutStreamer , Res ? CInst : TmpInst


<s> return PA_HARD_REGNO_MODE_OK ( regno , mode )


<s> break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , <STR_LIT> , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , <STR_LIT> , reg_names [ true_regnum ( XEXP ( x , <NUM_LIT> ) ) ] ) ; break ; case POST_INC : fprintf ( stream , <STR_LIT> , reg_names [ true_regnum ( XEXP


<s> SDValue VHi = DAG . getAnyExtOrTrunc ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , dl , <STR_LIT> ) ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( VLo , VHi ) ; SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> ,


<s> uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD ; EncVal <<= <NUM_LIT> ; EncVal |= BitE ; EncVal <<= <NUM_LIT> ; EncVal |= BitF ; EncVal <<= <NUM_LIT> ; EncVal |=


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSizeInBytes ) ; else VaArgOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std

:: numeric_limits < int32_t > :: min ( ) ) ;


<s> const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs ,


<s> void <ISA_LIT>WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( )


<s> bool isMemUImm12Offset ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> ||

Memory . Alignment != <NUM_LIT> ) return false ;


<s> return ( int64x1_t ) { __builtin_aarch64_sqsubdi ( __a [ <NUM_LIT> ] ,


<s> RepeatedMask . assign ( LaneSize , - <NUM_LIT> ) ; int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + LaneSize ; if ( RepeatedMask [ i % LaneSize ] < <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = LocalM ; else if ( RepeatedMask [ i % LaneSize ] != LocalM ) return false ; } return true


<s> RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } unsigned RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand :: createReg ( Regs [ i ] ) ) ; Inst . addOperand ( MCOperand ::


<s> return ( __m128i ) __builtin_ia32_pmovqb256_mask ( ( __v4di ) __A , ( __v16qi ) _mm_undefined_si128 ( )


<s> case MachineOperand :: MO_GlobalAddress : Symbol = AP . getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AP . GetCPISymbol ( MO . getIndex ( ) ) ; break ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create (


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . isUndef ( ) ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl ,

ResultVT , makeArrayRef ( Vec -> op_begin ( ) + IdxVal , ElemsPerChunk ) ) ;


<s> Opcode = <STR_LIT> ; break ; case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineSDNode * CmpSwap = DAG . getMachineNode ( Opcode , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; DAG . setNodeMemRefs ( CmpSwap , { MemOp } ) ; unsigned SubReg1 = <STR_LIT> , SubReg2 = <STR_LIT> ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( SubReg1 , SubReg2 ) ; SDValue Lo = DAG . getTargetExtractSubreg ( SubReg1 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( SubReg2 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Lo , Hi ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; return ; } unsigned Opcode ; switch ( MemOp -> getMergedOrdering ( ) ) { case AtomicOrdering :: Monotonic : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: Acquire : Opcode =


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Token , Loc , Loc ) ; Res -> Tok . Data = Str . data (


<s> USItype c = <NUM_LIT> ; while ( a != <NUM_LIT> ) { if ( a & <NUM_LIT>


<s> return <STR_LIT> ; case VK_<ISA_LIT>_LO32 : return <STR_LIT> ; case VK_<ISA_LIT>_PC_HI32 : return <STR_LIT> ; case VK_<ISA_LIT>_PC_LO32 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_HI32 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_LO32 : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF_HI32 : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF_LO32 : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_HI32 : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_LO32 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI32 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_LO32 : return <STR_LIT>


<s> MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insertAfter ( MachineBasicBlock :: iterator ( MI ) , CallseqEnd ) ; return BB


<s> EVT PtrVT = Src . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( Loop , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , DL , PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> ,


<s> if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; if ( ! named ) return ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int slot = aapcs_select_call_coproc ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = slot ; if ( slot >= <NUM_LIT> ) { if ( ! pcum -> aapcs_cprc_failed [ slot ] ) { if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [ slot ] = true ; pcum -> can_split = false ; } gcc_assert ( pcum -> can_split == false ) ; return ; } } ncrn = pcum -> aapcs_ncrn ; if ( ncrn & <NUM_LIT> ) { int res = arm_needs_doubleword_align ( mode , type


<s> return __builtin_mve_vcmpcsq_uv8hi ( __a ,


<s> bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false


<s> EVT EltVT = VT ; if ( VT . isVector ( ) ) EltVT = VT . getVectorElementType ( ) ; std :: vector < Constant * > CV ; if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C )


<s> if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents (


<s> bool <ISA_LIT>ShortenInst :: shortenFPConv ( MachineInstr & MI , unsigned Opcode ) { if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MachineOperand Dest ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Src ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Suppress ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Mode ( MI . getOperand ( <NUM_LIT> ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . add ( Dest ) . add

( Mode ) . add ( Src ) . add ( Suppress ) ;


<s> bool useFPVFMx64 ( ) const { return useFPVFMx ( ) && hasFP64


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ <STR_LIT> ] ; MachineInstrBuilder MIB ; unsigned Opc = ( ( FrameSize <= <NUM_LIT> ) && ! SaveS2 ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MBB , I , DL ,


<s> if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) { if ( MaxMaxAlign >= <NUM_LIT> && VTy -> getBitWidth ( ) >= <NUM_LIT> ) MaxAlign = <NUM_LIT> ; else if ( VTy -> getBitWidth ( ) >= <NUM_LIT> && MaxAlign < <NUM_LIT> ) MaxAlign = <NUM_LIT> ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign , MaxMaxAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; ++ i ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( STy -> getElementType ( i ) , EltAlign , MaxMaxAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; if ( MaxAlign == MaxMaxAlign


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( <NUM_LIT> ) . addReg ( Rs ) . addImm ( <STR_LIT> ) ; Rs = Tmp ; } BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Rs ) . addReg ( Rt ) . addImm ( Imm ) . addMemOperand ( BB -> getParent ( ) -> getMachineMemOperand ( & MMO , MMO . getOffset ( ) , MMO . getSize ( ) ) ) ; MI . eraseFromParent (


<s> return __builtin_aarch64_btruncv2sf (


<s> SDValue <ISA_LIT>TargetLowering :: LowerNaClTpTlsOffset ( SDValue Op , SelectionDAG & DAG ) const { return DAG . getConstant ( <NUM_LIT> , Op . getValueType


<s> CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CosVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDVTList Tys = DAG . getVTList


<s> __inline__ static double sh_media_FMOV_QD ( long long mm ) { double res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) ) ; return res


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl (


<s> while ( TmpReg <= RegNo ) { if ( ( ( ( TmpReg < <STR_LIT> ) || ( TmpReg > <STR_LIT> ) ) && ! isGP64bit ( ) ) || ( ( ( TmpReg < <STR_LIT> ) || ( TmpReg > <STR_LIT> ) ) && isGP64bit ( ) ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } PrevReg = TmpReg ; Regs . push_back ( TmpReg ++ ) ; } } RegRange = false ; } else { if ( ( PrevReg == <STR_LIT> ) && ( ( isGP64bit ( ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) || ( ! isGP64bit ( ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ! ( ( ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) && ! isGP64bit ( ) ) || ( ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) && isGP64bit ( ) ) ) ) { Error ( E , <STR_LIT>


<s> assert ( NumVec > <NUM_LIT> && NumVec < <NUM_LIT> && <STR_LIT> ) ; if ( ! PredVT . isScalableVector ( ) || PredVT . getVectorElementType ( ) != <STR_LIT> ) return EVT ( ) ; if ( PredVT != <STR_LIT> && PredVT != <STR_LIT> && PredVT != <STR_LIT> && PredVT != <STR_LIT> ) return EVT ( ) ; ElementCount EC = PredVT . getVectorElementCount ( ) ; EVT ScalarVT = EVT :: getIntegerVT ( Ctx , <STR_LIT> / EC . getKnownMinValue ( ) ) ; EVT MemVT = EVT :: getVectorVT ( Ctx , ScalarVT ,


<s> switch ( MemMI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( RegSaveFrameIndex ) , MachineMemOperand :: MOStore , Offset , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( <STR_LIT> ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI -> eraseFromParent


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) { if ( arr [ <NUM_LIT> ] != INVALID_CORE ) { if ( arr [ <NUM_LIT> ] == core )


<s> if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2


<s> if ( ! NewMul ) { assert ( C -> getZExtValue ( ) != <NUM_LIT> && C -> getZExtValue ( ) != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; if ( isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , NewMul ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( SignMulAmt >= <NUM_LIT> && isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( SignMulAmt >= <NUM_LIT> && isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT


<s> rtx vec_lab , pat , prevpat , x , braf_label ; rtx_insn * prev ; if ( ! JUMP_TABLE_DATA_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC ) continue ; pat = PATTERN ( insn ) ; vec_lab = XEXP ( XEXP ( pat , <NUM_LIT> ) , <NUM_LIT> ) ; for ( prev = as_a < rtx_insn * > ( vec_lab ) ; ; prev = PREV_INSN ( prev ) ) { if ( ! JUMP_P ( prev ) ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , <NUM_LIT> ) != <NUM_LIT> ) continue ; x = XVECEXP ( prevpat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x


<s> if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT || GET_MODE_CLASS ( d -> vmode ) != MODE_VECTOR_INT || GET_MODE_SIZE ( vmode ) != GET_MODE_SIZE ( d -> vmode ) ) return false ; if ( GET_MODE_NUNITS ( vmode ) >= d -> nelt ) return true ; chunk = d -> nelt / GET_MODE_NUNITS ( vmode ) ; for ( i = <NUM_LIT> ; i < d -> nelt ; i += chunk ) if ( d -> perm [ i ] & ( chunk - <NUM_LIT> ) ) return false ; else for ( j = <NUM_LIT> ; j < chunk ; ++ j ) if ( d -> perm [ i ] + j != d -> perm [ i + j ] ) return false ; return true


<s> dist_use = distance_agu_use ( regno0 , insn ) ; if ( dist_define < <NUM_LIT> || dist_define >= LEA_MAX_STALL ) { if ( dist_use < <NUM_LIT> && split_cost == <NUM_LIT> ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost +


<s> return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; int64_t Imm = UseSExt ? CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg (


<s> const MCOperand & Operand = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) ; assert ( Operand . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Operand . getExpr ( ) ; const MCSymbolRefExpr * SymExpr = static_cast < const MCSymbolRefExpr * > ( Expr ) ; assert ( SymExpr -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT && <STR_LIT> ) ; MCSymbol * LabelSym = getContext ( ) . getOrCreateSymbol ( SymExpr -> getSymbol ( ) . getName ( ) ) ; emitLabel ( LabelSym , Inst .


<s> if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Idx = <NUM_LIT> ; const TargetRegisterClass * RC32 = TLI . getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx ] :


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; bool isPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex


<s> CallingConv :: ID CC = CLI . CallConv ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameDestroyOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT>64_ELF_FIS ) ; CCValAssign & VA = RVLocs [ <NUM_LIT> ] ; assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MVT DestVT = VA . getValVT ( ) ; MVT CopyVT = DestVT ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned SourcePhysReg = VA . getLocReg ( ) ; unsigned ResultReg = <NUM_LIT> ; if ( RetVT == CopyVT ) { const TargetRegisterClass * CpyRC = TLI . getRegClassFor ( CopyVT ) ; ResultReg = copyRegToRegClass ( CpyRC , SourcePhysReg ) ; } else if ( CopyVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) { SourcePhysReg -= <STR_LIT> - <STR_LIT> ; ResultReg = copyRegToRegClass ( & <STR_LIT>


<s> SmallPtrSet < Value * , <NUM_LIT> > NewPtrs ; NewPtrs . insert ( Base . first ) ; for ( unsigned Idx = BaseElemIdx + <NUM_LIT> ; Idx < BaseElemIdx + Bucket . ChainSize ; ++ Idx ) { BucketElement & I = Bucket . Elements [ Idx ] ; Value * Ptr = getPointerOperandAndType ( I . Instr ) ; assert ( Ptr && <STR_LIT> ) ; if ( NewPtrs . count ( Ptr ) ) continue ; const SCEV * OffsetSCEV = BaseElemIdx ? SE -> getMinusSCEV ( Bucket . Elements [ Idx ] . Offset , Bucket . Elements [ BaseElemIdx ] . Offset ) : Bucket . Elements [ Idx ] . Offset ; if ( ! BaseElemIdx ) if ( ! isSafeToExpand ( OffsetSCEV , * SE ) ) return false ; Value * OffsetValue = SCEVE . expandCodeFor ( OffsetSCEV , OffsetSCEV -> getType ( ) , LoopPredecessor -> getTerminator ( ) ) ; Instruction * NewPtr = rewriteForBucketElement ( Base , Bucket . Elements [


<s> expand_operand ops [ <NUM_LIT> ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ <NUM_LIT> ] , dest , mode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ <NUM_LIT> ] , src , mode ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) ,


<s> if ( & A == & <STR_LIT> && & B == & <STR_LIT> ) return <NUM_LIT> ; if ( & A == & <STR_LIT> && & B


<s> else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( CallTarget ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getMetaOper ( PatchPointOpers :: NBytesPos ) . getImm ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ; EmitNops ( OutStreamer , NumBytes - EncodedBytes , Subtarget -> is64Bit ( ) , getSubtargetInfo


<s> bool isBTIHint ( ) const { return Kind


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMovePRegSingleOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( ( ( OpNo == <NUM_LIT> ) || ( OpNo == <NUM_LIT> ) ) && <STR_LIT> ) ; MCOperand Op = MI . getOperand ( OpNo ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; switch ( Op . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitWIN_ALLOCA ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE


<s> unsigned <ISA_LIT>ABIInfo :: GetFramePtr


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrRegImm11 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { if ( selectAddrFrameIndex ( Addr , Base


<s> unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , SupReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * ( NextReg - R4BaseReg ) ) ) ; std :: prev ( MI ) ->


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; T -> dump ( ) ) ; return false ; } if ( isa < StoreInst > ( I ) || isa < LoadInst > ( I ) ) { Value * Ptr = getLoadStorePointerOperand ( & I ) ; Type * AccessTy = getLoadStoreType ( & I ) ; int64_t NextStride = getPtrStride ( PSE , AccessTy , Ptr , L ) ; if ( NextStride == <NUM_LIT> ) { continue ; } else if ( NextStride == - <NUM_LIT> || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } else if ( EnableMaskedGatherScatters ) { const SCEV * PtrScev = PSE . getSE ( ) -> getSCEV ( Ptr ) ; if ( auto AR = dyn_cast < SCEVAddRecExpr > ( PtrScev ) ) { const SCEV * Step = AR -> getStepRecurrence ( * PSE . getSE ( ) ) ; if ( PSE . getSE ( ) -> isLoopInvariant ( Step , L ) ) continue ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } } LLVM_DEBUG ( dbgs ( ) <<


<s> case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; } if ( Shift == <STR_LIT> && imm == <NUM_LIT> ) Shift = <STR_LIT> ; unsigned Op = Shift | ( imm << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Op ) ) ; return S


<s> static <STR_LIT> isUseDefConvertible ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printBarrierOption ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; bool


<s> switch ( this -> Subtarget . getDarwinDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false ,


<s> RxSBGOperands RxSBG [ ] = { RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) , RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) } ; unsigned Count [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) while ( expandRxSBG ( RxSBG [ I ] ) ) if ( RxSBG [ I ] . Input . getOpcode ( ) != <STR_LIT> ) Count [ I ] += <NUM_LIT> ; if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return false ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return false ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I


<s> InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { Register Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { Register LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( ShiftOp ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } Register WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg , <NUM_LIT> , SubRegIdx ) ; Register WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } Register LaneTmp2 = RegInfo . createVirtualRegister ( GPRRC


<s> switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT>


<s> emit_insn ( gen_anddi3 ( scratch , scratch , tracker ) ) ; emit_insn ( gen_rtx_SET ( sp , scratch ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence (


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |=


<s> rtx value4word ; rtx value4byte ; rtx dst ; rtx byte_mode_size ; dst = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; value4word = nds32_gen_dup_4_byte_to_word_value ( value ) ; byte_mode_size = emit_setmem_word_loop ( dst , size , value4word ) ; value4byte = simplify_gen_subreg ( QImode , value4word , SImode , subreg_lowpart_offset ( QImode , SImode ) ) ; emit_setmem_byte_loop ( dst , byte_mode_size ,


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } SDLoc dl ( N ) ; SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; unsigned NumLanes = Op . getValueType (


<s> u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [


<s> void setCalleeSaveBaseToFrameRecordOffset ( int


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR (


<s> unsigned getMemDefaultBaseReg ( ) const { assert ( Kind == Memory && <STR_LIT> ) ; return Mem .


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , unsigned StackAlignOverride , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , <ISA_LIT>SSELevel ( NoMMXSSE ) , <ISA_LIT>3DNowLevel ( NoThreeDNow ) , HasCMov ( false ) , Has<ISA_LIT>_64 ( false ) , HasPOPCNT ( false ) , HasSSE4A ( false ) , HasAES ( false ) , HasPCLMUL ( false ) , HasFMA ( false ) , HasFMA4 ( false ) , HasXOP ( false ) , HasMOVBE ( false ) , HasRDRAND ( false ) , HasF16C ( false ) , HasFSGSBase ( false ) , HasLZCNT ( false ) , HasBMI ( false ) , HasBMI2 ( false ) , HasRTM ( false ) , IsBTMemSlow ( false ) , IsUAMemFast ( false ) , HasVectorUAMem ( false ) , HasCmpxchg16b ( false ) , UseLeaForSP ( false ) , HasSlowDivide ( false ) , PostRAScheduler ( false ) , PadShortFunctions ( false ) , stackAlignment ( <NUM_LIT> ) , MaxInlineSizeThreshold ( <NUM_LIT> ) , TargetTriple ( TT ) , In64BitMode ( is64Bit ) { std :: string CPUName = CPU ; if ( ! FS . empty ( ) || ! CPU . empty ( ) ) { if ( CPUName . empty ( ) ) { || defined ( __x86_64__ ) || defined ( _M_AMD64 ) || defined ( _M_X64 ) CPUName = sys :: getHostCPUName ( ) ; CPUName = <STR_LIT> ; } std :: string FullFS = FS ; if ( In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; } else { if ( CPUName . empty ( ) ) { CPUName = sys :: getHostCPUName ( ) ; CPUName = <STR_LIT> ; } AutoDetectSubtargetFeatures ( ) ; if ( In64BitMode ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; HasCMov = true ; ToggleFeature ( <STR_LIT> ) ; if ( <ISA_LIT>SSELevel < SSE2 ) { <ISA_LIT>SSELevel = SSE2 ; ToggleFeature ( <STR_LIT> ) ; ToggleFeature ( <STR_LIT> ) ; } } } InitMCProcessorInfo ( CPUName , FS ) ; if ( <ISA_LIT>ProcFamily == IntelAtom ) PostRAScheduler = true ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64


<s> virtual EVT getSetCCResultType ( LLVMContext &


<s> if ( type1 == NUM_TYPE_SUFFIXES ) return report_no_such_form ( type0 ) ; if ( type0 == type_suffix_ids [ <NUM_LIT> ] ) return report_no_such_form ( type1 ) ; gcc_unreachable ( ) ; } return


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( unsigned short ) MI -> getOperand ( OpNo ) .


<s> if ( regclass == STACK_REG ) { if ( REG_P ( x ) && reg_class_subset_p ( REGNO_REG_CLASS ( REGNO ( x ) ) , POINTER_REGS ) ) return regclass ; return NO_REGS ; } if ( ! reg_class_subset_p ( regclass , GENERAL_REGS ) && GET_CODE ( x ) == PLUS ) { rtx lhs = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( lhs ) == SUBREG ) lhs = SUBREG_REG ( lhs ) ; gcc_assert ( REG_P ( lhs


<s> bool loongarch_check_zero_div_p ( void ) { if ( target_flags_explicit & MASK_CHECK_ZERO_DIV ) return TARGET_CHECK_ZERO_DIV ; return ! optimize ||


<s> MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) ,


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( )


<s> return BranchTargetAlignBLR . getValue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BranchTargetAlignCBZ . getValue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BranchTargetAlignTBZ . getValue ( ) ; break ; case <STR_LIT> : return BranchTargetAlignBcc . getValue ( ) ; break ; default : return false ; break ; } } return true ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { const MCOperand & FirstOperand = Inst . getOperand ( <NUM_LIT> ) ; const MCOperand & SecondOperand = Inst . getOperand ( <NUM_LIT> ) ; const MCOperand & ThirdOperand = Inst . getOperand ( <NUM_LIT> ) ; if ( ! FirstOperand . isExpr ( ) && ! SecondOperand . isExpr ( ) && ! ThirdOperand . isExpr ( ) ) return false ; const MCSymbolRefExpr * RefExpr = nullptr ; if ( FirstOperand . isExpr ( ) ) RefExpr = static_cast < const MCSymbolRefExpr * > ( FirstOperand . getExpr ( ) ) ; else if ( SecondOperand . isExpr ( ) ) RefExpr = static_cast < const MCSymbolRefExpr * > ( SecondOperand . getExpr ( ) ) ; else if ( ThirdOperand . isExpr ( ) ) RefExpr = static_cast < const MCSymbolRefExpr * > ( ThirdOperand . getExpr ( ) ) ; if ( RefExpr == nullptr ) return false ; uint32_t VK = static_cast < uint32_t > ( RefExpr -> getKind ( ) ) ; if ( VK > MCSymbolRefExpr :: VK_DTPREL ) { if ( const <ISA_LIT>MCExpr * AARefExpr = dyn_cast < const <ISA_LIT>MCExpr > ( RefExpr ) ) { VK = AARefExpr -> getKind ( ) ; } else return false ; } if ( VK == MCSymbolRefExpr :: VK_Invalid || VK == MCSymbolRefExpr :: VK_None || VK >= <ISA_LIT>MCExpr :: VK_INVALID || VK == <ISA_LIT>MCExpr :: VK_NONE ) { switch ( Opcode ) { case <STR_LIT> : return BranchTargetAlignBCond . getValue ( ) ; break ; case <STR_LIT> : return BranchTargetAlignBL . getValue ( ) ; break ; case <STR_LIT> : return BranchTargetAlignBLR . getValue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return __builtin_ia32_vtestnzcps256 ( ( __v8sf ) __M ,


<s> case <STR_LIT> : Invert = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Invert = true ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSPLAT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerDIV ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerDIV ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case


<s> } Amt = DAG . getNode ( <STR_LIT> , DL , VT , Amt , DAG . getConstant ( EltSizeInBits - <NUM_LIT> , DL , VT ) ) ; bool ConstantAmt = <STR_LIT> ( Amt . getNode ( ) ) ; bool LegalVarShifts = SupportedVectorVarShift ( VT , Subtarget , <STR_LIT> ) && SupportedVectorVarShift ( VT , Subtarget , <STR_LIT> ) ; if ( IsSplatAmt || LegalVarShifts || ( Subtarget . hasAVX2 ( ) && ! ConstantAmt ) ) { SDValue AmtR = DAG . getConstant ( EltSizeInBits , DL , VT ) ; AmtR = DAG . getNode ( <STR_LIT> , DL , VT , AmtR , Amt ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , VT , R , Amt ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , VT , R , AmtR ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SHL , SRL ) ; } SDValue Scale = convertShiftLeftToScale ( Amt , DL , Subtarget , DAG ) ; assert ( Scale && <STR_LIT> ) ; if ( EltSizeInBits == <NUM_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , R , Scale ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , R , Scale ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; static const int OddMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue R13 = DAG . getVectorShuffle ( VT , DL , R , R , OddMask ) ; SDValue Scale13 = DAG . getVectorShuffle ( VT , DL , Scale , Scale , OddMask ) ; SDValue Res02 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , R ) , DAG . getBitcast ( <STR_LIT> , Scale ) ) ; SDValue Res13 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , R13 ) , DAG . getBitcast ( <STR_LIT> , Scale13 ) ) ; Res02 = DAG . getBitcast ( VT , Res02 ) ; Res13 = DAG . getBitcast ( VT , Res13 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getVectorShuffle ( VT , DL , Res02 , Res13 , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , DAG . getVectorShuffle ( VT , DL , Res02 , Res13 , { <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ <NUM_LIT> ] ) ) ) ; int index ; static const char * const patterns [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; scalar_int_mode mode = as_a < scalar_int_mode > ( GET_MODE ( diff_vec ) ) ; index = exact_log2 ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( index >= <NUM_LIT> && index <= <NUM_LIT> ) ; output_asm_insn ( patterns [ index ] [ <NUM_LIT> ] , operands ) ; ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , CODE_LABEL_NUMBER ( operands [ <NUM_LIT> ] ) ) ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , targetm . strip_name_encoding ( label ) ) ; output_asm_insn ( buf , operands ) ; output_asm_insn ( patterns [ index ] [ <NUM_LIT> ] , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( aarch64_sls_barrier ( aarch64_harden_sls_retbr_p ( ) ) , operands ) ; assemble_label ( asm_out_file


<s> if ( Op . isImm ( ) ) O << formatImm ( Op . getImm ( ) ) ; else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address


<s> if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_type_node ) return <STR_LIT> ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return <STR_LIT> ; if ( type == ibm128_float_type_node ) return


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check ==

STATIC_BUILTIN_STACK_CHECK ) return false ;


<s> static SDValue PerformFMinFMaxCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! DAG . getTarget ( ) . Options . UnsafeFPMath ) return SDValue ( ) ; unsigned NewOp =


<s> void <ISA_LIT>GOT :: initGOTList ( ) { m_SymbolOrderMap . clear ( ) ; m_MultipartList . clear ( ) ; m_MultipartList . push_back ( GOTMultipart ( ) ) ; m_MultipartList . back ( ) . m_Inputs . insert ( m_pInput ) ; m_MergedGlobalSymbols . clear ( ) ; m_InputGlobalSymbols . clear ( ) ; m_MergedLocalSymbols . clear ( ) ; m_InputLocalSymbols . clear ( ) ; m_InputTLSGdSymbols . clear ( )


<s> expand_insn ( icode , m_ops . length ( ) , m_ops . address (


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) RM = Reloc :: Static ; X -> InitMCCodeGenInfo ( RM , CM


<s> InstructionCost <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , MaybeAlign Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) { if ( auto * SI = dyn_cast_or_null < StoreInst > ( I ) ) { if ( auto * GEP = dyn_cast < GetElementPtrInst > ( SI -> getPointerOperand ( ) ) ) { if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) { return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ; } } return TTI :: TCC_Basic ; } assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( auto * VTy = dyn_cast < FixedVectorType > ( Src ) ) { const unsigned NumElem = VTy -> getNumElements ( ) ; if ( ! isPowerOf2_32 ( NumElem ) ) { InstructionCost Cost = <NUM_LIT> ; unsigned NumElemDone = <NUM_LIT> ; for ( unsigned NumElemLeft = NumElem , Factor ; Factor = PowerOf2Floor ( NumElemLeft ) , NumElemLeft > <NUM_LIT> ; NumElemLeft -= Factor ) { Type * SubTy = FixedVectorType :: get ( VTy -> getScalarType ( ) , Factor ) ; unsigned SubTyBytes = SubTy -> getPrimitiveSizeInBits ( ) / <NUM_LIT> ; Cost += getMemoryOpCost ( Opcode , SubTy , Alignment , AddressSpace , CostKind ) ; std :: pair < InstructionCost , MVT > LST = TLI -> getTypeLegalizationCost ( DL , SubTy ) ; if ( ! LST . second . isVector ( ) ) { APInt DemandedElts = APInt :: getBitsSet ( NumElem , NumElemDone , NumElemDone + Factor ) ; Cost += getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; } NumElemDone += Factor ; Alignment = commonAlignment ( Alignment . valueOrOne ( ) , SubTyBytes ) ; } assert ( NumElemDone == NumElem && <STR_LIT> ) ; return Cost ; } } std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; InstructionCost Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; else { assert ( MO . isImm ( ) && <STR_LIT> ) ; return static_cast < unsigned > (


<s> void <ISA_LIT>TargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { <ISA_LIT>ELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( Type == ELF :: STT_FUNC || Type ==

ELF :: STT_GNU_IFUNC ) Streamer . emitThumbFunc ( Symbol ) ;


<s> gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE


<s> bool <ISA_LIT>ConstantIslands :: CPEIsInRange ( MachineInstr * MI , unsigned UserOffset , MachineInstr * CPEMI , unsigned MaxDisp , bool NegOk , bool DoDump ) { unsigned CPEOffset = GetOffsetOf


<s> else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= <NUM_LIT> ; elt *= <NUM_LIT> ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , IsN64 ? <STR_LIT>


<s> void pa_output_function_label ( FILE * file ) { ASM_OUTPUT_LABEL ( file , XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( crtl -> is_leaf ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( rp_saved ) fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ; if ( gr_saved ) fprintf ( file , <STR_LIT> , gr_saved + <NUM_LIT> ) ; if ( fr_saved ) fprintf ( file , <STR_LIT> , fr_saved + <NUM_LIT> ) ; fputs ( <STR_LIT> ,


<s> if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT == <STR_LIT> && Subtarget -> useCRBits ( ) ) return false ; long Imm = <NUM_LIT> ; bool UseImm = false ; const bool HasSPE = Subtarget -> hasSPE ( ) ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } unsigned CmpOpc ; bool NeedsExt = false ; auto RC1 = MRI . getRegClass ( SrcReg1 ) ; auto RC2 = SrcReg2 != <NUM_LIT> ? MRI . getRegClass ( SrcReg2 ) : nullptr ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else { CmpOpc = <STR_LIT> ; if ( isVSSRCRegClass ( RC1 ) ) SrcReg1 = copyRegToRegClass ( & <STR_LIT> , SrcReg1 ) ; if ( RC2 && isVSSRCRegClass ( RC2 ) ) SrcReg2 = copyRegToRegClass ( & <STR_LIT> , SrcReg2 ) ; } break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT>


<s> bool isFIBase ( ) const { return Kind == FrameIndexBase


<s> warning ( OPT_Wattributes , <STR_LIT> , name ) ; } } else { if ( TREE_CODE ( * node ) == FUNCTION_TYPE || TREE_CODE ( * node ) == METHOD_TYPE ) { if ( arm_isr_value ( args ) == ARM_FT_UNKNOWN ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } } else if ( TREE_CODE ( * node ) == POINTER_TYPE && ( TREE_CODE ( TREE_TYPE ( * node ) ) == FUNCTION_TYPE || TREE_CODE ( TREE_TYPE ( * node ) ) == METHOD_TYPE ) && arm_isr_value ( args ) != ARM_FT_UNKNOWN ) { * node = build_variant_type_copy ( * node ) ; TREE_TYPE ( * node ) = build_type_attribute_variant ( TREE_TYPE ( * node ) , tree_cons ( name , args , TYPE_ATTRIBUTES ( TREE_TYPE ( * node ) ) ) ) ; * no_add_attrs = true ; } else { if ( flags & ( ( int ) ATTR_FLAG_DECL_NEXT | ( int ) ATTR_FLAG_FUNCTION_NEXT | ( int ) ATTR_FLAG_ARRAY_NEXT ) ) { * no_add_attrs = true ; return tree_cons ( name , args , NULL_TREE ) ; } else { warning ( OPT_Wattributes , <STR_LIT> , name


<s> static bool aarch64_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_SIMD && ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) || AARCH64_VALID_SIMD_DREG_MODE ( mode ) ) && ( nelems >= <NUM_LIT> && nelems <= <NUM_LIT> ) ) return true ; return false


<s> const char * getPassName ( ) const override { return


<s> part = gen_lowpart ( SImode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( ! const_ok_for_arm ( INTVAL ( part ) ) ) return false ; return


<s> Info . OneUser = false ; Info . MultiUsers = false


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( The<ISA_LIT>V9Target ) ; RegisterAsmInfo < <ISA_LIT>ELFMCAsmInfo > A ( The<ISA_LIT>Target


<s> static <ISA_LIT>Operand * CreateShiftedImm ( const MCExpr * Val , unsigned ShiftAmount , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftedImm , Ctx ) ; Op -> ShiftedImm . Val = Val ; Op -> ShiftedImm . ShiftAmount = ShiftAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsTestAndBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; IsTestAndBranch = true ; break ; } if ( IsTestAndBranch && MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; assert ( MI . getParent ( ) && <STR_LIT> ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; Register VReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; while ( DefMI -> isCopy ( ) ) { Register CopyVReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( CopyVReg ) ) return false ; if ( ! MRI -> hasOneDef ( CopyVReg ) ) return false ; DefMI = MRI -> getVRegDef ( CopyVReg ) ; } switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { if ( IsTestAndBranch ) return false ; if ( DefMI -> getParent ( ) != MBB ) return false ; if ( ! MRI -> hasOneNonDBGUse ( VReg ) ) return false ; bool Is32Bit = ( DefMI -> getOpcode ( ) == <STR_LIT> ) ; uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; Register NewReg = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MO . setIsKill ( false ) ; if ( ! Is32Bit && Imm < <NUM_LIT> ) NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; MI . eraseFromParent ( )


<s> BB = Inst -> getOperand ( NumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Opc ) ) ; for ( int i = <NUM_LIT> ; i < NumOp - <NUM_LIT> ; i ++ ) Cond . push_back ( Inst


<s> if ( ArgRegs . size ( ) == Idx ) VaArgOffset = RoundUpToAlignment ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else VaArgOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex (


<s> bool isCortexA7 ( ) const { return CPUString


<s> IRBuilder < > Builder ( InsertAtEnd ) ; Value * Idx [ <NUM_LIT> ] ; Idx [ <NUM_LIT> ] = Builder . getInt32 ( <NUM_LIT> ) ; Idx [ <NUM_LIT> ] = Builder . getInt32 ( getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ getTranslator ( ) . getRegSetDesc

( ) . RegLargestSupers [ <STR_LIT> ] ] ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C


<s> } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } SDValue Chain = HI . getValue ( <NUM_LIT> ) ; SDValue TSC ; if ( Subtarget . is64Bit ( ) ) { TSC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TSC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO , TSC ) ; } else { TSC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { LO , HI


<s> return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_vector_value ( size , slotno , named , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming


<s> if ( cast < AtomicSDNode > ( Node ) -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) ) ; return Swap . getValue ( <NUM_LIT> ) ; } return


<s> for ( auto & MO : MI -> operands ( ) ) { const MCOperand MCOp = LowerOperand (


<s> uint64_t Ceil = Log2Ceil == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << Log2Ceil ; if ( C - Floor <= Ceil - C ) { SDValue Op0 = genConstMult ( X , Floor , DL , VT , ShiftTy , DAG ) ; SDValue Op1 = genConstMult ( X , C - Floor , DL , VT , ShiftTy , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; } SDValue Op0 = genConstMult ( X , Ceil , DL , VT , ShiftTy , DAG ) ; SDValue Op1 = genConstMult ( X , Ceil - C , DL , VT , ShiftTy , DAG ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> bool <ISA_LIT>TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttr (


<s> if ( const <ISA_LIT>MCExpr * S1 = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) { if ( const <ISA_LIT>MCExpr * S2 = dyn_cast < const <ISA_LIT>MCExpr > ( S1 -> getSubExpr ( ) ) ) { if ( S1 -> getKind ( ) == MEK_NEG && S2


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned val = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( val != <NUM_LIT>


<s> case OImode : return aarch64_simd_intOI_type_node ; case CImode : return aarch64_simd_intCI_type_node ; case XImode : return aarch64_simd_intXI_type_node ; case HFmode : return aarch64_fp16_type_node ; case SFmode : return float_type_node ; case DFmode : return double_type_node ; default : gcc_unreachable (


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } return VT .


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm ->