<s> if ( WasCandidate ) { MIReplacements . push_back ( std :: make_pair ( MI , NewMI ) ) ; if ( ! NewMI ) CandidateDidntGetTransformed = true ; } LiveRegs . stepBackward ( * MI ) ; } if ( CandidateDidntGetTransformed ) { LiveRegs . clear ( ) ; LiveRegs . addLiveIns ( MBB ) ; auto NextCandidateIter = MIReplacements . begin ( ) ; auto EndCandidateIter = MIReplacements . end ( ) ; for ( auto I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { MachineInstr * MI = & * I ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MI , Clobbers ) ; if ( NextCandidateIter == EndCandidateIter ) break ; if ( NextCandidateIter -> first == MI ) { if ( NextCandidateIter -> second == nullptr ) { MachineInstr * NewMI = tryReplaceInstr ( MI , MBB , WasCandidate ) ; NextCandidateIter -> second = NewMI ; } ++ NextCandidateIter ; } } } while ( ! MIReplacements . empty ( ) ) { MachineInstr * MI = MIReplacements . back ( ) .


<s> if ( ( ImmVal & SupportedMask ) != ImmVal ) { return SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , <STR_LIT> ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , ConstLo ) ; if ( ImmHi ) { SDValue ConstHi = CurDAG -> getTargetConstant ( ImmHi >> <NUM_LIT> , <STR_LIT>


<s> if ( Opcode == <STR_LIT> ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( ImmedOffset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDPR = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isDef = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; Opcode = getLoadStoreMultipleOpcode ( Opcode


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> return ( __m128i ) __builtin_ia32_pminuw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( )


<s> unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( getCPELogAlign ( U . CPEMI ) ) ; if ( CloserWater && MinNoSplitDisp > U . getMaxDisp ( ) / <NUM_LIT> ) return false ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI ->

getParent ( ) ) && Growth < BestGrowth ) {


<s> return StringSwitch < AluCode > ( S ) . Case ( <STR_LIT> , ADD ) . Case ( <STR_LIT> , ADDC ) . Case ( <STR_LIT> , SUB ) . Case ( <STR_LIT> , SUBB ) . Case ( <STR_LIT> , AND ) . Case ( <STR_LIT> , OR ) . Case ( <STR_LIT> , XOR

) . Case ( <STR_LIT> , SHL ) . Case ( <STR_LIT> , SRL ) . Case ( <STR_LIT> , SRA ) . Default ( UNKNOWN ) ;


) ) _mm512_cvt_roundps_ph ( __m512 __A , const int __I ) {


<s> bool <ISA_LIT>BaseInstrInfo :: getExtractSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPairAndIdx & InputReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isExtractSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand & MOReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOReg . isUndef ( ) ) return false ; InputReg . Reg = MOReg . getReg ( ) ; InputReg . SubReg = MOReg . getSubReg ( ) ; InputReg . SubIdx = DefIdx == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , TTI :: TargetCostKind CostKind , const Instruction * I ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( CostKind == TTI :: TCK_CodeSize && ISD == <STR_LIT> && ST -> isThumb ( ) && ! ValTy -> isVectorTy ( ) ) { if ( TLI -> getValueType ( DL , ValTy , true ) == <STR_LIT> ) return TTI :: TCC_Expensive ; int Cost = TLI -> getTypeLegalizationCost ( DL , ValTy ) . first ; ++ Cost ; if ( ValTy -> isIntegerTy ( <NUM_LIT> ) ) ++ Cost ; return Cost


<s> assemble_start_function ( thunk , fnname ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , delta ) ; asm_fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT>


<s> void EmitMappingSymbol ( StringRef Name ) { MCSymbol * Start = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFPLRX ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFPLRX ( Offset ) ; return false


<s> if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( inAbs2008Mode ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; assert ( inAbs2008Mode ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true


<s> auto * DefRC = MRI -> getRegClass ( OldDefReg ) ; Register UnhardenedReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( UnhardenedReg ) ; unsigned HardenedReg = hardenValueInRegister ( UnhardenedReg , MBB , std :: next ( MI . getIterator ( )


<s> uint8_t <STR_LIT> ( ) { if ( FpABI == FpABIKind :: XX ) return ( uint8_t ) AFL_REG_32 ; return ( uint8_t )


<s> MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } auto DbgRange = llvm :: make_range ( MachineBasicBlock :: iterator ( MI ) , MachineBasicBlock :: iterator ( LastCMOV ) ) ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( DbgRange ) ) if ( MI . isDebugInstr ( ) ) SinkMBB -> push_back ( MI . removeFromParent ( ) ) ; SinkMBB -> splice ( SinkMBB -> end ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( ThisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; createPHIsForCMOVsInSinkBB ( MIItBegin , MIItEnd , ThisMBB , FalseMBB


<s> const <ISA_LIT>TargetLowering * getTLI ( )


<s> case CallingConv :: CXX_FAST_TLS : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2Base ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : if ( ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : if ( Return ) report_fatal_error ( <STR_LIT> ) ; else return


<s> static rtx_insn * mips16_emit_constants_1 ( machine_mode mode , rtx value , rtx_insn * insn ) { if ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } if ( SCALAR_FLOAT_MODE_P ( mode ) ) return emit_insn_after

( gen_consttable_float ( value ) , insn ) ;


<s> break ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MI . setOpcode ( <STR_LIT> ) ; InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Pos ) ) ; MI . addOperand ( MCOperand :: createImm


<s> return ( __m64 ) __builtin_ia32_cvtpd2pi ( ( __v2df )


<s> if ( Kind != k_Memory ) return false ; if ( Memory . BaseRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory


<s> if ( ! ATReg ) return true ; FinalDstReg = DstReg ; DstReg = ATReg ; } if ( ! loadImmediate ( ImmValue , DstReg , <STR_LIT> , Is32Bit , false , Inst . getLoc ( ) , Instructions ) ) { switch ( FinalOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; } MCInst tmpInst ; tmpInst . clear ( ) ; tmpInst . setLoc ( Inst . getLoc ( ) ) ; tmpInst . setOpcode ( FinalOpcode ) ; if ( FinalDstReg == <STR_LIT> ) { tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( SrcReg ) ) ; } else { tmpInst . addOperand ( MCOperand :: createReg ( FinalDstReg ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( FinalDstReg ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; } Instructions . push_back ( tmpInst ) ; return


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && SelectMadd ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( )


<s> O << '[' ; bool NeedPlus = false ; if ( BaseReg . getReg ( ) ) { printOperand ( MI , Op ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <NUM_LIT> ) ; NeedPlus = true ; } if ( ! DispSpec .


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Callee , Symbol , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getRegisterMask ( Mask ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setHasCalls ( true ) ; SDValue TGA = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 , DAG ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , TGA ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , withTargetFlags ( Op ,


<s> return ( __m256i ) __builtin_ia32_pmovusqd512_mask ( ( __v8di ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , ( __mmask8


<s> std :: tie ( DstVec , DstLane , SrcVec , SrcLane ) = MatchInfo ; auto SrcCst = Builder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , SrcLane ) ; auto Extract = Builder . buildExtractVectorElement ( ScalarTy , SrcVec , SrcCst ) ; auto DstCst = Builder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , DstLane ) ; Builder . buildInsertVectorElement ( Dst , DstVec ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) * <NUM_LIT> ) ) ; return MCDisassembler :: Success


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned SP = <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; return u .


<s> default : break ; case Instruction :: Alloca : { assert ( false && <STR_LIT> ) ; return false ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( Obj ) ) { ( void ) GV ; return false ; } Reg = getRegForValue ( Obj ) ; if ( Reg == <NUM_LIT> ) return false ; if ( Offset != <NUM_LIT> ) { <STR_LIT> Pred = <STR_LIT> ; unsigned PredReg = <NUM_LIT> ; if ( ! isThumb ) emit<ISA_LIT>RegPlusImmediate ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , Reg , Reg , Offset , Pred , PredReg , static_cast < const <ISA_LIT>BaseInstrInfo & > ( TII ) ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , Reg , Reg , Offset


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber ( ) ; if ( DTNumber < JTNumber ) { MachineBasicBlock * NewBB = AdjustJTTargetBlockForward ( MBB , MI ->


<s> rtx label1 , label2 , x , mask , shift ; machine_mode mode , orig_mode ; enum memmodel mod_s , mod_f ; bool is_weak ; boolval = operands [ <NUM_LIT> ] ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; orig_mode = mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( mode == QImode || mode == HImode ) { oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; if ( ! TARGET_SYNC_HI_QI ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; oldval = expand_simple_binop ( SImode , ASHIFT , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) { x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } cond = gen_reg_rtx ( CCmode ) ; if ( mode != TImode ) x = gen_rtx_COMPARE ( CCmode , x , oldval ) ; else { rtx xor1_result = gen_reg_rtx ( DImode ) ; rtx xor2_result = gen_reg_rtx ( DImode ) ; rtx or_result = gen_reg_rtx ( DImode ) ; rtx new_word0 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx new_word1 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx old_word0 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; rtx old_word1 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; emit_insn ( gen_xordi3 ( xor1_result , new_word0 , old_word0 ) ) ; emit_insn ( gen_xordi3 ( xor2_result , new_word1 , old_word1 ) ) ; emit_insn ( gen_iordi3 ( or_result ,


<s> assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList (


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( )


<s> unsigned getBitfieldInvertedMaskOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Mask ) ; } } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } } else if ( ConstantSDNode * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { ConstantSDNode * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) == Bits ) return DAG . getNode ( Opc , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } return SDValue (


<s> SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } } } } return


<s> static int mvtc_inform_done = <NUM_LIT> ; if ( GET_CODE ( op ) == CONST_INT ) switch ( INTVAL ( op ) ) { case <NUM_LIT> : case 'c' : case 'C' : case <NUM_LIT> : case 'z' :


<s> if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this


<s> PredicateThen = std :: make_unique < PredicatedMI > (


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u16 ( unsigned short __X ) { return __builtin_ctz (


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std


<s> if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( <STR_LIT> ) ) adjustment += RegInfo -> getSlotSize ( ) ; if ( hasFP ( MF ) && MF . protectFramePtr ( ) ) adjustment += RegInfo -> getSlotSize


<s> bool assignArg ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , const CallLowering :: ArgInfo & Info , CCState & State ) override { bool Res = AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info


<s> if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; auto TRI = STI . getRegisterInfo ( ) ; if ( ! STI . isTargetLinux ( ) || ! ( CallConv == CallingConv :: C || CallConv == CallingConv :: <ISA_LIT>_64_SysV ) ) return false ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Reg ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = OrigArgs . empty ( ) ? true : OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , <NUM_LIT> ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > NewRegs ; if ( ! splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { NewRegs . assign ( Regs . begin ( ) , Regs . end ( ) ) ; } ) ) return false ; CallReturnHandler Handler ( MIRBuilder , MRI , RetCC_<ISA_LIT> , MIB ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler


<s> } op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , <NUM_LIT> ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result


<s> assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; unsigned Reg = PMapper -> Encoding ; uint64_t Immed = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned State ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } else { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } ReplaceNode ( N , CurDAG -> getMachineNode ( State , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( Immed , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } auto TheReg = <STR_LIT> ( RegString -> getString ( ) ) ; if ( TheReg && TheReg -> Writeable && TheReg -> haveFeatures ( Subtarget -> getFeatureBits


<s> static DecodeStatus DecodeSPRRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; regrename_init ( true ) ; regrename_analyze ( NULL ) ; this -> analyze ( ) ; this -> rename_fma_trees ( ) ; regrename_finish (


<s> if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ; if ( MF -> getFunction ( ) -> getCallingConv

( ) == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ;


<s> for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> GetInstSizeInBytes ( * MI ) ; ReverseIter End = MBB -> rend (


<s> if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) , MI . getOperand ( OpNo - <NUM_LIT> ) ) ; const Align OffsetAlign ( getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || ! isAligned ( OffsetAlign , Offset ) ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAdduOp ( ) ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg = Reg ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill =


<s> vpaddlq_u32 ( uint32x4_t a ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst =


<s> } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX512 ( ) ) { const TargetRegisterClass * VR128X = & <STR_LIT> ; const TargetRegisterClass * VK1 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , VK1 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned ImplicitDefReg = createResultReg ( VR128X ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned MovOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned MovReg = fastEmitInst_rrrr ( MovOpcode , VR128X , RHSReg , RHSIsKill , CmpReg , true , ImplicitDefReg , true , LHSReg , LHSIsKill ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( MovReg ) ; } else if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill


<s> case GPRwithAPSRRegClassID : case GPRnopcRegClassID : case rGPRRegClassID : case GPRspRegClassID : case tGPR_and_tcGPRRegClassID : case tcGPRRegClassID : case tGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case HPRRegClassID : case SPR_8RegClassID : case SPRRegClassID : case DPR_8RegClassID : case DPRRegClassID : case QPRRegClassID : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . LastADRP ) ; AFI . addLOHDirective ( MCLOH_AdrpAdrp , { & MI , Info . LastADRP } ) ; ++ NumADRPSimpleCandidate ; } if ( Info . IsCandidate ) { switch ( Info . Type ) { case MCLOH_AdrpAdd : { const MachineInstr * AddMI = Info . MI0 ; int DefIdx = mapRegToGPRIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LOHInfo DefInfo = LOHInfos [ OpIdx ] ; if ( DefIdx != OpIdx && ( DefInfo . OneUser || DefInfo . MultiUsers ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAdd , { & MI , Info . MI0 } ) ; ++ NumADRSimpleCandidate ; break ; } case MCLOH_AdrpLdr : if ( supportLoadFromLiteral ( * Info . MI0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdr , { & MI , Info . MI0 } ) ; ++ NumADRPToLDR ; } break ; case MCLOH_AdrpAddLdr : { MachineInstr * AddMI = const_cast < MachineInstr * > ( Info . MI1 ) ; const MachineInstr * LdrMI = Info . MI0 ; auto AddIt = MachineBasicBlock :: iterator ( AddMI ) ; auto EndIt = AddMI -> getParent ( ) -> end ( ) ; if ( AddMI -> getIterator ( ) == EndIt || LdrMI != & * next_nodbg ( AddIt , EndIt ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; } case MCLOH_AdrpAddStr : if ( Info . MI1 != nullptr


<s> HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 =


<s> void <ISA_LIT>InstPrinter :: printInverseCondCode ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( <STR_LIT> (


<s> void aarch64_elf_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { char flagchars [ <NUM_LIT> ] , * f = flagchars ; if ( ! ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) && ( flags & SECTION_DECLARED ) ) { fprintf ( asm_out_file , <STR_LIT> , name ) ; return ; } if ( ! ( flags & SECTION_DEBUG ) ) * f ++ = 'a' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_SMALL ) * f ++ = 's' ; if ( flags & SECTION_MERGE ) * f ++ = 'M' ; if ( flags & SECTION_STRINGS ) * f ++ = 'S' ; if ( flags & SECTION_TLS ) * f ++


<s> if ( Bytes != <NUM_LIT> ) { unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [


<s> bool <ISA_LIT>AsmParser :: MatchInstruction ( const SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCInst & Inst ) { <ISA_LIT>Operand & Op0 = * ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ; assert ( Op0 . Kind == <ISA_LIT>Operand :: Token && <STR_LIT> ) ; const StringRef & Mnemonic = Op0 . getToken ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { Inst = MCInst ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand ::


<s> void setVarArgsFrameIndex ( int Index


<s> if ( Reg . isPhysical ( ) ) return <STR_LIT> . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & <STR_LIT> || TRC == & <STR_LIT> ; } ; return llvm :: any_of ( MI . operands ( )


<s> one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , d ) , UNSPEC_FRES ) ) ) ; if ( passes > <NUM_LIT> ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = <NUM_LIT> , xprev = x1 , eprev = e0 ; i


<s> if ( CI -> getNumOperands ( ) != <NUM_LIT> || CI -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! CI -> getType ( ) -> isIntegerTy ( ) ) return false ; const IntegerType * Ty = dyn_cast < IntegerType > ( CI


<s> unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; if ( ResultReg == <NUM_LIT> ) return false ; if ( DstVT != <STR_LIT> ) { ResultReg = FastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ; if ( ResultReg == <NUM_LIT> ) return false ; } UpdateValueMap ( I , ResultReg ) ; return


<s> case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value


<s> static bool rs6000_real_tls_symbol_ref_p (


<s> const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ; CondCycles = <NUM_LIT>


<s> if ( target -> cpu_native == CPU_NATIVE ) { const char * isa_string = isa_str ( & target -> isa , ',' ) ; APPEND_STRING ( <STR_LIT> ) APPEND_STRING ( get_native_prid_str ( ) ) APPEND_STRING ( <STR_LIT> ) APPEND_STRING ( isa_string ) APPEND1 ( '\0' ) } else APPEND_STRING ( loongarch_cpu_strings [ target -> cpu_native


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , llvm :: next ( llvm :: next ( I ) ) ) ; } return Changed


<s> if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs + <NUM_LIT> ) { if ( pcum -> iwmmxt_nregs <= <NUM_LIT> ) return gen_rtx_REG ( mode , pcum -> iwmmxt_nregs + FIRST_IWMMXT_REGNUM ) ; else { pcum -> can_split =


<s> static SDValue tryCombineShiftImm ( unsigned IID , SDNode * N , SelectionDAG & DAG ) { MVT ElemTy = N -> getSimpleValueType ( <NUM_LIT> ) . getScalarType ( ) ; unsigned ElemBits = ElemTy . getSizeInBits ( ) ; int64_t ShiftAmount ; if ( BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BVN -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , ElemBits ) || SplatBitSize != ElemBits ) return SDValue ( ) ; ShiftAmount = SplatValue . getSExtValue ( ) ; } else if ( ConstantSDNode * CVN = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { ShiftAmount = CVN -> getSExtValue ( ) ; } else return SDValue ( ) ; unsigned Opcode ; bool IsRightShift ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>MachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach


<s> if ( Mnemonic == <STR_LIT> && Operands . size ( ) > <NUM_LIT> && ! isThumb ( ) && ! static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> is<ISA_LIT>SOImm ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm0_65535Expr ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> ) return true ; if ( isThumb ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> ) return true ; if ( ( ( isThumb ( ) && Mnemonic == <STR_LIT> ) || ( isThumbTwo ( ) && Mnemonic == <STR_LIT> ) ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <STR_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && ( ( Mnemonic == <STR_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) ) || static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm0_1020s4 ( ) ) ) return true ; if ( isThumbTwo ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) { if ( inITBlock ( ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm0_7 ( ) ) return false ; if ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != <STR_LIT> && static_cast <

<ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isT2SOImm ( ) ) return false ;


<s> if ( Arg . hasOneUse ( ) && Subtarget . hasAnyFMA ( ) ) { switch ( Arg . getOpcode ( ) ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } if ( NewOpcode ) return DAG . getBitcast ( OrigVT , DAG . getNode ( NewOpcode , DL , VT , Arg . getNode ( ) -> ops ( ) ) ) ; return SDValue (


<s> unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S ->


<s> if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getFunction ( <STR_LIT> ) ; return TargetLowering :: getSSPStackGuardCheck


<s> const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) ; return getAIXFuncEntryPointSymbolSDNode ( F -> getName ( ) , F -> isDeclaration ( ) , SC ) ; } if ( isValidAIXExternalSymSDNode ( SymName ) ) { return getAIXFuncEntryPointSymbolSDNode ( SymName , true , XCOFF :: C_EXT ) ; } report_fatal_error ( <STR_LIT> + Twine


<s> int regnum ; if ( GET_CODE ( op ) == REG ) regnum = REGNO ( op ) ; else if ( GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op

, <NUM_LIT> ) ) == CONST_INT ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ;


<s> return __builtin_mve_vdupq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_EXCEPT_MASK ) |


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , int64_t Offset ) const { assert ( Offset <=


<s> case <NUM_LIT> : if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumOps == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <NUM_LIT> : if ( NumOps == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && ( Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> || Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) && <STR_LIT> ) return <NUM_LIT> ; return


<s> if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return VFP_HI_REGS ; } if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ; if ( IS_IWMMXT_GR_REGNUM ( regno ) )


<s> Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; unsigned Hi16 = getMovi32Value ( MI , MO1 , <STR_LIT> ) >> <NUM_LIT> ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI


<s> APInt Mask = N0 . getConstantOperandAPInt ( <NUM_LIT> ) ; Mask <<= N1C -> getAPIntValue ( ) ; bool MaskOK = false ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( N00 . getOpcode ( ) == <STR_LIT> && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) ; } if ( MaskOK && Mask != <NUM_LIT> ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG .


<s> for ( auto * U : Vec -> uses ( ) ) { if ( U != Op0 . getNode ( ) && U -> hasOneUse ( ) && U -> getOpcode ( ) == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) == Vec && U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue OtherRound = SDValue ( * U -> use_begin ( ) , <NUM_LIT> ) ; if ( OtherRound . getOpcode ( ) == <STR_LIT> && OtherRound . getOperand ( <NUM_LIT> ) == SDValue ( U , <NUM_LIT> ) && OtherRound . getValueType ( ) == <STR_LIT> ) { SDValue VRound = DAG . getNode ( <STR_LIT> , SDLoc ( N ) ,


<s> return false ; } char * str_to_check = ( char * ) alloca ( len + <NUM_LIT> ) ; strcpy ( str_to_check , arg_str ) ; if ( * str_to_check == '+' ) return aarch64_handle_attr_isa_flags ( str_to_check ) ; if ( len > <NUM_LIT> && strncmp ( str_to_check , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { invert = true ; str_to_check += <NUM_LIT> ; } char * arg = strchr ( str_to_check , '=' ) ; if ( arg ) { * arg = '\0' ; arg ++ ; } const struct aarch64_attribute_info * p_attr ; bool found = false ; for ( p_attr = aarch64_attributes ; p_attr -> name ; p_attr ++ ) { if ( strcmp ( str_to_check , p_attr -> name ) != <NUM_LIT> ) continue ; found = true ; bool attr_need_arg_p = p_attr -> attr_type == aarch64_attr_custom || p_attr -> attr_type == aarch64_attr_enum ; if ( attr_need_arg_p ^ ( arg != NULL ) ) { error ( <STR_LIT> , str_to_check ) ; return false ; } if ( invert && ! p_attr -> allow_neg


<s> return ( __m128i ) __builtin_ia32_pmovqb256_mask ( ( __v4di ) __A ,


<s> SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else if ( Subtarget . hasMiscellaneousExtensions2 ( ) ) lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL ,


<s> static __inline vec_double2 spu_madd ( vec_double2 a , vec_double2 b , vec_double2 c ) { return ( ( vec_double2 ) ( si_dfma ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c


<s> int64_t SVal = int64_t ( Value ) ; if ( SVal < Min || SVal > Max ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SVal ) + <STR_LIT> + Twine ( Min ) + <STR_LIT> + Twine ( Max ) + <STR_LIT> ) ; return false ; } return true ; } ; auto handlePCRelFixupValue = [ & ] ( unsigned W ) -> uint64_t { if ( Value % <NUM_LIT> != <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( ! checkFixupInRange ( minIntN ( W ) * <NUM_LIT> , maxIntN ( W ) * <NUM_LIT> ) ) return <NUM_LIT> ; return ( int64_t ) Value / <NUM_LIT> ; } ; switch ( unsigned ( Kind ) ) { case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : if ( ! checkFixupInRange ( <NUM_LIT> , maxUIntN ( <NUM_LIT> ) ) ) return <NUM_LIT> ; return Value ; case <STR_LIT> : { if ( ! checkFixupInRange ( minIntN ( <NUM_LIT> ) , maxIntN ( <NUM_LIT> ) ) ) return <NUM_LIT> ; uint64_t DLo = Value & <NUM_LIT> ; uint64_t DHi = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; return ( DLo << <NUM_LIT> ) | DHi ; } case <STR_LIT>


<s> static SDValue PerformVZEXT_MOVLCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) , OpVT = Op . getValueType ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getVectorElementType ( ) . getSizeInBits ( ) == OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) { return DAG . getNode ( <STR_LIT> , N -> getDebugLoc (


<s> for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <STR_LIT> , false ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool RestrictR15 = FlagRestrictR15 ; assert ( FlagUseZeroBasedSandbox || RestrictR15 ) ; if ( Subtarget . isTargetNaCl64 ( ) ) { if ( RestrictR15 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering *

> ( Subtarget . getFrameLowering ( ) ) ;


<s> if ( ! IsSigned ) return false ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned TempReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitInst ( Opc , TempReg ) . addReg ( SrcReg ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) ; updateValueMap ( I , DestReg ) ; return true


<s> return ( __m512d ) __builtin_ia32_pd512_pd ( (


<s> static Reloc :: Model getEffectiveRelocModel ( CodeModel :: Model CM , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) || CM == CodeModel :: JITDefault ) return Reloc :: Static ; return *


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> +


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget -> hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue S2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue Shuffle = getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , S2F , <NUM_LIT> , DAG ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode (

<STR_LIT> , dl , <STR_LIT> , Shuffle ) , Sub ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: adjustPqBitsSpls ( const MCInst & Inst ,

unsigned Value , const MCSubtargetInfo & STI ) const {


<s> MCAsmParserExtension :: Initialize ( parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( std :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( std :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; ABI . updateCheriInitialFrameStateHack ( * getContext ( ) . getAsmInfo ( ) , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; IsCpRestoreSet = false ; AreCheriSysRegsAccessible = false ; CpRestoreOffset = - <NUM_LIT> ; GPReg = ABI . IsCheriPureCap ( ) ? ( unsigned ) <STR_LIT> : ABI . GetGlobalPtr ( ) ; const Triple & TheTriple = sti . getTargetTriple


<s> if ( Subtarget -> isTargetDarwin ( ) ) OutStreamer . SwitchSection

( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> Target & llvm :: getThe<ISA_LIT>V9Target ( ) { static Target The<ISA_LIT>V9Target


<s> case tGPR_and_tcGPRRegClassID : case tGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case SPR_8RegClassID : case SPRRegClassID : case DPR_8RegClassID : case DPRRegClassID : return getRegBank ( <STR_LIT>


<s> return SelectAddrModeUnscaled ( N , <NUM_LIT> , Base


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; <STR_LIT> Cond ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( Cond , Op , DAG ) ; SDValue SetCC = getSETCC ( Cond , Overflow , DL


<s> SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers Opers ( & MI ) ; int64_t CallTarget = Opers . getCallTarget ( ) . getImm ( ) ; unsigned EncodedBytes = <NUM_LIT> ; if ( CallTarget ) { assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; Register ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) .

addImm ( CallTarget & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ;


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return TargetAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds (


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1


<s> bool <ISA_LIT>SpeculationHardening :: insertCSDB ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL ) { assert ( ! UseControlFlowSpeculationBarrier && <STR_LIT> <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm (


<s> return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost

, C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ;


<s> return tryParseRegister ( RegNo , StartLoc , EndLoc


<s> ME = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) ; return true ; } else { Val = ~ Val ; if ( isShiftedMask_32 ( Val ) ) { ME = countLeadingZeros ( Val ) - <NUM_LIT> ; MB = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) + <NUM_LIT> ; return true ; } } return


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI =


<s> data -> cost [ vect_body ] = <NUM_LIT> ; data -> cost [ vect_epilogue ] = <NUM_LIT> ; rs6000_vect_nonmem =


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi ,


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( ( isHReg ( DestReg ) || isHReg ( SrcReg ) ) && Subtarget . is64Bit ( ) ) { Opc = <STR_LIT> ; assert ( <STR_LIT> . contains ( SrcReg , DestReg ) && <STR_LIT> ) ; } else Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( HasVLX ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else { Opc = <STR_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( HasVLX ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! Opc ) Opc = CopyToFromAsymmetricReg ( DestReg , SrcReg , Subtarget ) ; if ( Opc ) { BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( SrcReg == <STR_LIT> || DestReg == <STR_LIT> ) { report_fatal_error ( <STR_LIT> )


<s> unsigned ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( VR ) ) MRI . constrainRegClass ( VR , RC ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( VR ) ; InsInstrs . push_back ( MIB ) ; return MUL


<s> ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( aarch64_bf16_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type


<s> static SDValue combineExtSetcc ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits ( ) ) return SDValue ( ) ; SDValue Res = DAG . getSetCC ( dl , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , CC ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) Res = DAG . getZeroExtendInReg ( Res , dl , N0 .


<s> } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveNaN ( ) ; if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false


<s> <STR_LIT> CC = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock :: iterator NextMIIt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; if ( isCMOVPseudo ( MI ) ) { while ( NextMIIt != BB -> end ( ) && isCMOVPseudo ( NextMIIt ) && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CC || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) ) { LastCMOV = & * NextMIIt ; ++ NextMIIt ; } } if ( LastCMOV == MI && NextMIIt != BB -> end ( ) && NextMIIt -> getOpcode ( ) == MI -> getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { CascadedCMOV = & * NextMIIt ; } MachineBasicBlock * jcc1MBB = nullptr ; if ( CascadedCMOV ) { jcc1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , jcc1MBB ) ; jcc1MBB -> addLiveIn ( <STR_LIT> ) ; } MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineInstr * LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ; if ( ! LastEFLAGSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastEFLAGSUser , BB


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i + <NUM_LIT> ) ; MIB . addOperand ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; MIB . addOperand ( MO ) ; } MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt ,


( __v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> default : return Op ; case <STR_LIT> : if ( ( C -> getZExtValue ( ) >> Bit ) & <NUM_LIT> ) return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; return Op ; case <STR_LIT> : if ( C -> getZExtValue ( ) <= Bit && ( Bit - C -> getZExtValue ( ) ) < Op -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { Bit = Bit - C -> getZExtValue ( ) ; return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; } return Op ; case <STR_LIT> : Bit = Bit + C -> getZExtValue


<s> <ISA_LIT>FI -> setCallsEhReturn ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg ,

getPointerTy ( ) ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> } ) ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isTerminator ( ) ) return MachineOutlinerInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return MachineOutlinerInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerDefault ,


<s> bool xstormy16_below100_symbol ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != <NUM_LIT> ; if ( CONST_INT_P ( x ) ) { HOST_WIDE_INT i = INTVAL ( x


<s> return ( __mmask8 ) __builtin_ia32_kxorqi ( ( __mmask8 ) __A ,


<s> } const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( )


<s> unsigned getSOImmOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> static Relocator :: DWord getThumbBit ( const Relocation & pReloc ) { Relocator :: DWord thumbBit = ( ( ! pReloc . symInfo ( ) -> isUndef ( ) || pReloc . symInfo ( ) -> isDyn ( ) ) && ( pReloc . symInfo ( ) -> type ( ) == ResolveInfo :: Function ) && ( ( pReloc . symValue ( ) & <NUM_LIT> ) != <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ; return


<s> static SDValue LowerPREFETCH ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; unsigned IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Locality = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool IsStream = ! Locality ; if ( Locality ) { assert ( Locality <= <NUM_LIT>


<s> rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) { rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , <NUM_LIT> , i ) =

gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ;


<s> gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != RECORD_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; } else { if ( slotno >= SPARC_FP_ARG_MAX ) return - <NUM_LIT> ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs && ! data . fp_regs_in_first_word && slotno >= SPARC_FP_ARG_MAX - <NUM_LIT> ) return - <NUM_LIT> ; if ( ! data . fp_regs && data . int_regs &&


<s> return ( __m128 ) __builtin_ia32_vextractf128_ps256 ( ( __v8sf )


<s> } O << '[' ; bool NeedPlus = false ; if ( BaseReg . getReg ( ) ) { printOperand ( MI , Op , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <NUM_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O <<


<s> if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( VT . getScalarSizeInBits ( )


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ; CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT> ; FalseCycles = <NUM_LIT>


<s> unsigned TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; return


<s> return infer_vector_or_tuple_type ( argno ,


<s> uint64x1_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> __rv . __o = __builtin_neon_vld3v8qi ( ( const __builtin_neon_qi * )


<s> void addPostRegAlloc ( ) override { if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) addPass ( createCheriInvalidatePass (


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) . getSimpleVT ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT


<s> static bool outliningCandidatesSigningKeyConsensus ( const outliner :: Candidate & a , const outliner :: Candidate & b ) { const auto & MFIa = a . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & MFIb = b . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return MFIa -> shouldSignWithBKey ( ) == MFIb -> shouldSignWithBKey (


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { if ( NumElts == <NUM_LIT> ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDValue Ops [ ] = { N -> getChain ( ) , Src0 , Mask , N -> getBasePtr ( ) , Index } ; SDValue NewGather = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( DAG . getVTList ( VT , MaskVT , <STR_LIT> ) , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; return DAG . getMergeValues ( { NewGather , NewGather . getValue ( <NUM_LIT> ) } , dl ) ; } NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , NumElts ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; if ( IndexVT . getScalarType ( ) == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; MVT MaskBitVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; assert ( MaskVT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , NumElts ) ; Mask = ExtendToType ( Mask , ExtMaskVT , DAG , true ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskBitVT , Mask ) ; MVT NewVT = <STR_LIT> ( VT . getScalarType ( ) , NumElts ) ; Src0 = ExtendToType ( Src0 , NewVT , DAG ) ; SDValue Ops [ ] = { N -> getChain ( ) , Src0 , Mask , N -> getBasePtr ( ) , Index } ; SDValue NewGather = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( DAG . getVTList ( NewVT , MaskBitVT , <STR_LIT> ) , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , VT , NewGather . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Extract , NewGather . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) { assert ( VT == <STR_LIT> && Src0 . getValueType ( ) ==


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG (


<s> Value * <ISA_LIT>IREmitter :: visitVFPEXT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> VRI . NumGroups += <NUM_LIT> ; VRI . FirstGroupStartIdx = std :: min ( VRI . FirstGroupStartIdx , BG . StartIdx ) ; } ValueRotsVec . clear ( ) ; for ( auto & I : ValueRots ) { ValueRotsVec . push_back ( I . second ) ; } llvm :: sort ( ValueRotsVec . begin ( ) , ValueRotsVec


<s> machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source


<s> unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Op = DAG . getNode ( Opc , dl , <STR_LIT>


<s> case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG


<s> FunctionPass * llvm :: create<ISA_LIT>LDCleanupPass


<s> } bool DoXform = false ; bool InvCC = false ; assert ( ( Opc == <STR_LIT> || ( Opc == <STR_LIT> && Slct == N -> getOperand ( <NUM_LIT> ) ) ) && <STR_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( LHS ) -> isNullValue ( ) ) { DoXform = true ; } else if ( CC != <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( RHS ) -> isNullValue ( ) ) { std :: swap ( LHS , RHS ) ; SDValue Op0 = Slct . getOperand ( <NUM_LIT> ) ; EVT OpVT = isSlctCC ? Op0 . getValueType ( ) : Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool isInt = OpVT . isInteger ( ) ; CC = <STR_LIT> ( CC , isInt ) ; if ( ! TLI . isCondCodeLegal ( CC , OpVT ) ) return SDValue ( ) ; DoXform = true ; InvCC = true ; } if ( DoXform


<s> void mips_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { <STR_LIT> , mips_d_handle_target_float_abi } , { NULL , NULL }


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; SmallVector < MachineMemOperand * , <NUM_LIT> > MMOs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; unsigned DstReg ; unsigned MemOpndSlot = <NUM_LIT> ; unsigned CurOp = <NUM_LIT> ; DstReg = MI . getOperand ( CurOp ++ ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; ( void ) TRI ; Register mainDstReg = MRI . createVirtualRegister ( RC ) ; Register restoreDstReg = MRI . createVirtualRegister ( RC ) ; MemOpndSlot = CurOp ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; restoreMBB -> setHasAddressTaken ( ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next (

MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ;


<s> if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1

, V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( MCPhysReg R : LiveRegs ) RestMBB -> addLiveIn ( R ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( MCPhysReg R : LiveRegs ) MoveMBB -> addLiveIn ( R ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB ) ; MBB . addSuccessor ( MoveMBB ) ; BuildMI ( * MoveMBB , MoveMBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MI . getOperand ( <NUM_LIT> ) ) ) ; MoveMBB -> addSuccessor (


<s> uint64_t THMToTHMStub :: initSymValue


<s> Value * <ISA_LIT>TargetLowering :: getSDagStackGuard ( const


<s> WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { if ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != <NUM_LIT> * j + WhichResult ) return false ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult


<s> __extension__ static __inline void vst3_f64 ( float64_t * __a , float64x1x3_t val ) { __builtin_aarch64_simd_ci __o ; float64x2x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT>


<s> else if ( TREE_CODE ( TREE_VALUE ( args ) ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } return


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( isOneBitExtractOpFromShr ( N , Opc , Opd0 , LSB , MSB ) ) return true ; uint64_t Shl_imm = <NUM_LIT> ; uint64_t Trunc_bits = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Trunc_bits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; assert ( Shl_imm < VT . getSizeInBits ( ) && <STR_LIT> ) ; uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; assert ( Srl_imm > <NUM_LIT> && Srl_imm < VT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Width = VT . getSizeInBits ( ) - Trunc_bits - Srl_imm - <NUM_LIT> ; int sLSB = Srl_imm - Shl_imm ; if ( sLSB < <NUM_LIT> ) return false ; LSB = sLSB ; MSB = LSB + Width ; if ( VT == <STR_LIT> ) Opc = N ->

getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> assert ( ! OldFlagDef1 == ! OldFlagDef2 && <STR_LIT> ) ; if ( ! OldFlagDef1 || ! OldFlagDef2 ) return ; assert ( OldFlagDef1 -> isDead ( ) && OldFlagDef2 -> isDead ( ) && <STR_LIT> ) ; MachineOperand * NewFlagDef1 = NewMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * NewFlagDef2 = NewMI2 . findRegisterDefOperand ( <STR_LIT>


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_fp_cond ( tmp , code , pred , known_ptrue_p , op0 , op1 ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp