<s> tree id = get_identifier ( vector_types [ type ] . name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TREE_TYPE ( decl ) != error_mark_node && TYPE_MAIN_VARIANT ( TREE_TYPE

( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> )


<s> return new yaml :: <ISA_LIT>MachineFunctionInfo (


<s> static bool riscv_save_reg_p ( unsigned int regno ) { bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG


, gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;


<s> case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT>


<s> static rtx gen_no_side_effects_vsetvl_rtx ( machine_mode vmode , rtx vl , rtx avl ) { unsigned int sew = get_sew ( vmode ) ; return gen_vsetvl_no_side_effects ( Pmode , vl , avl , gen_int_mode ( sew , Pmode )

, gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return IsCapMode ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) { rtx base = XEXP ( x , <NUM_LIT> ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr , mode ) ; } return x


<s> gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - <NUM_LIT> ) , build_int_cst ( build_pointer_type ( size_type_node ) , <NUM_LIT> ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ; gsi_insert_after ( f . gsi , assign , GSI_SAME_STMT ) ; gsi_insert_after ( f . gsi , g , GSI_SAME_STMT ) ; return repl


<s> if ( fault_first_load_p ( info1 . get_insn ( ) -> rtl ( ) ) && info2 . demand_p ( DEMAND_AVL ) && info2 . has_avl_reg ( ) && info2 . get_avl_source ( ) && info2 . get_avl_source ( ) ->


<s> unsigned Reg = GPRDecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg (


<s> const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; FlagsHi = <STR_LIT> ; } else { SecondOpcode = <STR_LIT> ; FlagsHi = <STR_LIT> ; } return expandAuipcInstPair ( MBB , MBBI , NextMBBI


<s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL , SDLoc DL , SelectionDAG & DAG ) { MVT MaskVT = getMaskTypeFor ( VecVT


<s> offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) , FALSE


<s> memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof


<s> unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ;


<s> switch ( getKind ( ) ) { default : return ; case VK_<ISA_LIT>_TPREL_HI


<s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreOffset ( )


<s> if ( Kind . isData ( ) && isGlobalInSmallSection ( GO , TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind ,


<s> if ( DisableInsertVSETVLPHIOpt ) return true ; if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber


<s> if ( can_create_pseudo_p ( ) && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode ,


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign (


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this ,


<s> Register <ISA_LIT>FrameLowering :: getFPReg ( ) const { if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) return <STR_LIT> ; else return


<s> unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } RVFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; } if ( ! OutChains . empty ( ) ) { OutChains . push_back ( Chain ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler ::


<s> SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT>


<s> if ( code == EQ || code == NE ) { rtx zie = riscv_zero_if_equal ( op0 , op1 ) ; riscv_emit_binary ( code , target , zie ,


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> bool IsRV64 = TT . isArch64Bit ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( ! ABIName . empty ( ) && TargetABI == ABI_Unknown ) { errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT>


<s> } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; if ( ! IsUnmasked ) { SDValue Policy = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ; Ops . push_back ( Policy ) ; } SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; Result = convertFromScalableVector ( VT , Result , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Chain } , DL ) ; } } return lowerVectorIntrinsicSplats ( Op , DAG ,


<s> static bool vector_config_insn_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type ( rinsn )


<s> if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! <STR_LIT> ( Subtarget .

getTargetABI ( ) ) ) return AtomicExpansionKind :: MaskedIntrinsic ;


<s> return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT>


<s> static inline bool isImmHL ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) ==


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout


<s> if ( parseOperand ( Operands , Name ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ; return


<s> mode = GET_MODE ( dest ) ; num_ops = riscv_build_integer ( codes , value , orig_mode ) ; if ( can_create_pseudo && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { codes [ <NUM_LIT> ] . value = trunc_int_for_mode ( codes [ <NUM_LIT> ] . value , mode ) ; x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value ,


<s> if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return


<s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS


<s> return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK ==


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> bool isVTypeI10 ( ) const { if ( Kind == KindTy :: Immediate


<s> unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF )


<s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT>


<s> bool neg_simm5_p ( rtx x ) { if ( ! CONST_INT_P ( x ) ) return false ; return IN_RANGE ( INTVAL ( x ) , -


<s> static bool get_default_ta ( ) { return ( bool ) ( get_prefer_tail_policy ( ) & <NUM_LIT> || ( get_prefer_tail_policy (


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm (


<s> case TargetStackID :: Default : case TargetStackID :: <ISA_LIT>Vector : case TargetStackID :: NoAlloc


<s> assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; unsigned UseOpIdx ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) && ! WritesElement0 ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI . getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( VLMul , ElementWidth , TailAgnostic , false ) ) ; MI . getOperand ( SEWIndex ) . setImm ( - <NUM_LIT> ) ; if ( VLIndex >= <NUM_LIT> ) { MI . getOperand ( VLIndex ) . setReg


<s> assert ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; Hi = DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo ::


<s> BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; } Register DestReg = <STR_LIT> ; if ( AVLReg == <STR_LIT> ) DestReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg

( AVLReg ) . addImm ( Info . encodeVTYPE ( ) ) ;


<s> return addVSetVL ( MI , BB , VLIndex , SEWIndex , RVV -> VLMul ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return RE -> evaluateAsConstant ( Imm ) ; } if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) { VK = <ISA_LIT>MCExpr


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant (


<s> const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSRE -> findAssociatedFragment ( ) ) ; if ( ! DF ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE


<s> bool isSystemRegister ( ) const { return Kind == KindTy ::


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> if ( <STR_LIT> ( TSFlags ) ) { unsigned NumOperands = MI . getNumExplicitOperands ( ) ; int VLIndex = <STR_LIT> ( TSFlags ) ? NumOperands - <NUM_LIT> : - <NUM_LIT> ; unsigned SEWIndex = NumOperands - <NUM_LIT> ; bool ForceTailAgnostic = <STR_LIT> ( TSFlags ) ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , ForceTailAgnostic ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT>


<s> if ( ! has_vector_insn ( cfun ) ) return <NUM_LIT> ; init ( ) ; if ( ! optimize ) simple_vsetvl ( ) ; else lazy_vsetvl ( ) ; done ( ) ; return


<s> if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl ->

is_leaf && call_used_or_fixed_reg_p ( regno ) ) ) return true ;


<s> if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) { return <NUM_LIT> - getStackAlign ( ) .


<s> if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects


<s> if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) return ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const <ISA_LIT>InstrInfo * TII = STI .


<s> return op_info -> ret . get_tree_type ( type


<s> if ( TARGET_RVC && ! speed && riscv_mshorten_memrefs && mode == SImode && ! riscv_compressed_lw_address_p ( addr ) ) return riscv_address_insns ( addr , mode , false ) + <NUM_LIT> ; return riscv_address_insns ( addr , mode ,


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( IsVarArg ) report_fatal_error ( <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == Subtarget . getXLenVT ( ) && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo


<s> <ISA_LIT>RI5CYIR ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>RI5CYIRPass ( * PassRegistry :: getPassRegistry (


<s> if ( ignore_zero_width_bit_field_p && DECL_BIT_FIELD ( f ) && ( DECL_SIZE ( f ) == NULL_TREE || integer_zerop ( DECL_SIZE ( f ) ) ) ) ; else { HOST_WIDE_INT pos = offset + int_byte_position ( f ) ; n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi (


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex


<s> static SDValue combineGREVI_GORCI ( SDNode * N , SelectionDAG & DAG ) { bool IsGORC = N -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsGORC || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt ; if ( IsGORC ) CombinedShAmt


<s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ; return ST -> hasStdExtZbb ( ) ? TTI :: PSK_FastHardware


<s> bool hasVInstructionsF32 ( ) const { return HasStdExtV && hasStdExtF


<s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , <NUM_LIT> ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set (


<s> return TREE_TYPE ( TREE_TYPE ( fndecl ) ) ==


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO . getReg ( ) ) ; O <<


<s> SDValue ScalarSplat = lowerScalarSplat ( SDValue ( ) , ScalarVal , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , DAG . getUNDEF ( M1VT ) , VectorVal , ScalarSplat , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant (


<s> assert ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == <NUM_LIT> ) Result = Builder . CreateTrunc ( Result ,


<s> static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void )


<s> void <ISA_LIT>InstPrinter :: printBDAddrOperand ( const MCInst * MI , int OpNum , raw_ostream &


<s> bool riscv_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun ->


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ; bool Res = compressInst ( CInst , Inst , * STI , OutStreamer -> getContext ( ) ) ; if ( Res


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter >


[ VECTOR_TYPE_vuint8mf8_t ] . scalar_const_ptr ;


<s> SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) , DL , XLenVT ) : DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue Mask = getAllOnesMask ( ContainerVT , VL , DL , DAG ) ; return { Mask , VL


<s> regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM ||

regno == FRAME_POINTER_REGNUM ) return true ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> )


<s> bool hasStdExtZihintpause ( ) const { return HasStdExtZihintpause


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm )

&& VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch


<s> case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT>


<s> unsigned Size = CI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind ::


<s> int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; int Srcs [ ] = { - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i != Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int Pol = i % <NUM_LIT> ; int Src = Mask [ i ] / Size ; if ( Srcs [ Pol ] < <NUM_LIT> ) Srcs [ Pol ] = Src ; if ( Srcs [ Pol ] != Src ) return false ; int Elt = Mask [ i ] % Size ; if ( Elt != i / <NUM_LIT> ) return false ; } if ( Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] == Srcs [ <NUM_LIT> ] ) return false ; SwapSources = Srcs [ <NUM_LIT> ] > Srcs [ <NUM_LIT>


<s> case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm )


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } else { Operands . push_back ( Node -> getOperand ( <NUM_LIT> +


<s> { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high , in_splitter ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx


<s> case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> return DCI . CombineTo ( N , Lo , Hi ) ; } if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue Lo = NewSplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = NewSplitF64 . getValue ( <NUM_LIT> ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt RHSMask = APInt :: getLowBitsSet ( RHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LHSMask , DCI ) || SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , RHSMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue ShAmt = N -> getOperand ( <NUM_LIT> ) ; APInt OpMask = APInt :: getLowBitsSet ( Op0 . getValueSizeInBits ( ) , <NUM_LIT> ) ; APInt ShAmtMask = APInt :: getLowBitsSet ( ShAmt . getValueSizeInBits ( ) , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( Op0 , OpMask , DCI ) || SimplifyDemandedBits ( Op1 , OpMask , DCI ) || SimplifyDemandedBits ( ShAmt , ShAmtMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const unsigned Reg = RegInfo


<s> if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; auto * CE = dyn_cast < MCConstantExpr > ( Res ) ; if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SpecialCapReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( SpecialCapReg ? SpecialCapReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SpecialCapReg = <STR_LIT> ( Identifier ) ; if ( SpecialCapReg ) { Operands . push_back ( <ISA_LIT>Operand :: createSpecialCapReg ( Identifier , S , SpecialCapReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken ::


<s> if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else { continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( BaseOpIdx == <NUM_LIT> ) CurDAG -> UpdateNodeOperands ( N , Base . getOperand ( <NUM_LIT> ) , ImmOperand , N


<s> case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( )


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> if ( info1 . demand_p ( DEMAND_TAIL_POLICY ) ) { set_ta ( info1 . get_ta ( ) ) ; demand ( DEMAND_TAIL_POLICY ) ; } else if ( info2 . demand_p ( DEMAND_TAIL_POLICY ) ) { set_ta ( info2 . get_ta


<s> gcc_unreachable ( ) ; } for ( const poly_int64 & poly_val : worklist ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , gen_int_mode ( poly_val , mode ) ) ; ASSERT_TRUE ( known_eq ( calculate_x_in_sequence ( dest ) , poly_val ) ) ; end_sequence (


<s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = <STR_LIT>


<s> static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI , MachineBasicBlock * BB ) { assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) .


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ) ; } else


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorFCOPYSIGNToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Mag = Op . getOperand ( <NUM_LIT> ) ; SDValue Sign = Op . getOperand ( <NUM_LIT> ) ; assert ( Mag . getValueType ( ) == Sign . getValueType ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; Mag = convertToScalableVector ( ContainerVT , Mag , DAG , Subtarget ) ; Sign = convertToScalableVector ( ContainerVT , Sign , DAG , Subtarget ) ; SDValue Mask


<s> IdxDiff = <NUM_LIT> ; } if ( ! SeqStepNum ) SeqStepNum = ValDiff ; else if ( ValDiff != SeqStepNum ) return None ; if ( ! SeqStepDenom ) SeqStepDenom = IdxDiff ; else if ( IdxDiff != * SeqStepDenom ) return None ; } if ( ! PrevElt || PrevElt -> first != Val ) PrevElt = std :: make_pair ( Val , Idx ) ; } if ( ! SeqStepNum || ! SeqStepDenom ) return None ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumElts ; Idx ++ ) { if ( Op . getOperand ( Idx ) . isUndef ( ) ) continue ; uint64_t Val = Op . getConstantOperandVal ( Idx ) & maskTrailingOnes < uint64_t > ( EltSizeInBits ) ; uint64_t ExpectedVal = ( int64_t ) ( Idx * ( uint64_t ) * SeqStepNum ) / * SeqStepDenom ; int64_t Addend = SignExtend64 ( Val - ExpectedVal , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( Addend != SeqAddend


<s> static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * <NUM_LIT> ) return COSTS_N_INSNS ( double_insns ) ; return COSTS_N_INSNS ( single_insns )


<s> const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups (


<s> if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size ) ; if ( RVVStackSize && ! hasFP ( MF


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectCC ( MI , MBB ) ; case <STR_LIT>


<s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects (


<s> Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize


<s> if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) RAReg = <STR_LIT> ; else RAReg = <STR_LIT> ; Init<ISA_LIT>MCRegisterInfo ( X


<s> if ( riscv_compressed_reg_p ( regno ) ) return


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = <NUM_LIT> , unsigned Align = <NUM_LIT> , MachineMemOperand :: Flags Flags =

MachineMemOperand :: MONone , bool * Fast = nullptr ) const {


<s> <STR_LIT> rvv_switcher ( ) { memcpy ( have_regs_of_mode , m_old_have_regs_of_mode ,


<s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . getValVT ( ) . isFixedLengthVector ( ) && LocVT . isScalableVector ( ) ) Val = convertToScalableVector ( LocVT , Val , DAG , Subtarget ) ; break ; case CCValAssign :: BCvt : if ( VA . getLocVT ( ) . isInteger ( ) && VA . getValVT ( ) == <STR_LIT> )

Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ;


<s> const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW ==


<s> static bool second_lmul_less_than_first_lmul_p ( const vector_insn_info & info1 , const


<s> static tree riscv_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED ,


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOperandWithModifier ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: getVariantKindForName ( Identifier ) ; if ( VK == <ISA_LIT>MCExpr ::


<s> bool riscv_can_use_return_insn ( void ) { return ( reload_completed && cfun -> machine -> frame . total_size ==

<NUM_LIT> && ! cfun -> machine -> interrupt_handler_p ) ;


<s> } } bool IsSelect = all_of ( enumerate ( SVN -> getMask ( ) ) , [ & ] ( const auto & MaskIdx ) { int MaskIndex = MaskIdx . value ( ) ; return MaskIndex < <NUM_LIT> || MaskIdx . index ( ) == ( unsigned ) MaskIndex % NumElts ; } ) ; assert ( ! V1 . isUndef ( ) && <STR_LIT> ) ; SmallVector < SDValue > MaskVals ; SmallVector < SDValue > GatherIndicesLHS , GatherIndicesRHS ; bool SwapOps = DAG . isSplatValue ( V2 ) && ! DAG . isSplatValue ( V1 ) ; bool InvertMask = IsSelect == SwapOps ; for ( int MaskIndex : SVN -> getMask ( ) ) { bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHS = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( DAG . getConstant ( IsLHS ? std :: max ( MaskIndex , <NUM_LIT> ) : <NUM_LIT> , DL , XLenVT ) ) ; GatherIndicesRHS . push_back ( DAG . getConstant ( IsLHS ? <NUM_LIT> : MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ; IndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; } MVT IndexContainerVT = ContainerVT . changeVectorElementType ( IndexVT . getScalarType ( ) ) ; SDValue Gather ; if ( SDValue SplatValue = DAG . getSplatValue ( V1 , true ) ) { Gather = lowerScalarSplat ( SplatValue , VL , ContainerVT , DL , DAG , Subtarget ) ; } else { SDValue LHSIndices = DAG . getBuildVector ( IndexVT , DL , GatherIndicesLHS ) ; LHSIndices = convertToScalableVector ( IndexContainerVT , LHSIndices , DAG , Subtarget ) ; V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ; } if ( ! V2 . isUndef ( ) ) { MVT MaskContainerVT = ContainerVT . changeVectorElementType


<s> HOST_WIDE_INT offset ; sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; if ( riscv_use_save_libcall ( & cfun -> machine -> frame ) || cfun -> machine -> interrupt_handler_p || ! cfun -> machine -> frame . gp_sp_offset . is_constant ( ) ) return components ; offset = cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if (

BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) {


<s> if ( can_create_pseudo_p ( ) && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode


<s> void <ISA_LIT>InstPrinter :: printMemRegOperand ( const MCInst * MI , int opNum , raw_ostream &


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 , bool IsGPRAsFPR = false ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Register ) ; Op -> Reg . RegNum =


<s> if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL


<s> if ( isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost )


<s> SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL ,


<s> MBB . addLiveIn ( <STR_LIT> ) ; MBB . insert ( MBB . end ( ) , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) )

. addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ;


<s> default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_emit_attribute_p ) riscv_emit_attribute (


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize -


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return


<s> riscv_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL ,


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg


<s> int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false


<s> static int riscv_issue_rate ( void ) { return tune_param -> issue_rate


<s> bool <ISA_LIT>ExpandPseudo :: expandLoadTLSGDAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipcInstPair ( MBB , MBBI , NextMBBI


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) || VecVT . getVectorElementType ( ) != <STR_LIT> ) { if ( isNullConstant ( Idx ) ) return Op ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Vec , Idx ) ; SDValue InsertElt0 = DAG . getNode ( <STR_LIT> , DL , VecVT , Slidedown , Val , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Vec , InsertElt0 , Idx ) ; } SDValue SplattedVal = DAG . getSplatVector ( VecVT , DL , Val ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VecVT , Idx ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VecVT ) ; auto SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VecVT ) ; SDValue Mask = DAG . getSetCC ( DL , SetCCVT ,


<s> TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectBaseAddr ( SDValue Addr , SDValue & Base ) { if ( Addr . getValueType ( ) . isFatPointer ( ) ) return false ; assert ( Addr . getValueType ( ) . isInteger ( ) || Addr . getValueType ( ) == <STR_LIT> ) ; if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; else Base = Addr ; return


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF


<s> } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( )


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > (

Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction &


<s> gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; HOST_WIDE_INT actual = tree_to_uhwi ( arg ) ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( argno , actual , min , max ) ; return false ; } return true


<s> return create<ISA_LIT>ObjectWriter ( OS , OSABI


<s> EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign ::


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> } if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Base == Op -> getOperand ( <NUM_LIT> ) ) { Offset = Op -> getOperand ( <NUM_LIT> ) ; } else


<s> Register HiLuiDestReg = HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ; if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; return true


<s> MVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; unsigned Opc = VT . isFloatingPoint (


<s> return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8


<s> Result += getULEB128Size ( item . IntValue ) ; break ; case AttributeType :: Text : Result += getULEB128Size ( item . Tag ) ; Result += item . StringValue . size ( ) + <NUM_LIT> ; break ; case AttributeType


<s> unsigned Opc ; switch ( N0 . getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getMachineOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( cast < ConstantSDNode > ( N01 ) -> getSExtValue ( ) ) ) break ; SDNode * Result = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N00 , N01 ) ; ReplaceUses ( N , Result ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ReplaceUses ( N , N0 . getNode ( ) ) ; return true


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isUInt < <NUM_LIT> > (


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , VT , VT , CCValAssign ::

Full , ArgFlags , CCInfo , true , true ) ) return false ;


<s> if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ; return


<s> if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( )


<s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { CurInfo = BlockInfo [ MBB . getNumber ( ) ] . Pred ; assert ( CurInfo . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , CurInfo ) ) { if ( needVSETVLIPHI ( NewInfo , MBB ) ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } else { if ( needVSETVLI ( MI , NewInfo , CurInfo ) ) { insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { CurInfo = <STR_LIT> ( ) ; } } if ( ! UseStrictAsserts ) { const VSETVLIInfo & ExitInfo = BlockInfo [ MBB . getNumber ( ) ] . Exit ; if ( CurInfo . isValid ( ) && ExitInfo . isValid ( ) && ! ExitInfo . isUnknown ( ) && CurInfo != ExitInfo ) { auto InsertPt = MBB . getFirstInstrTerminator ( ) ; insertVSETVLI ( MBB , InsertPt , MBB . findDebugLoc ( InsertPt ) , ExitInfo , CurInfo ) ; CurInfo = ExitInfo ; } } if ( UseStrictAsserts && CurInfo . isValid


<s> void pass_vsetvl :: cleanup_insns ( void ) const { for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { rtx_insn * rinsn = insn -> rtl ( ) ; if ( vlmax_avl_insn_p ( rinsn ) ) { eliminate_insn ( rinsn ) ; continue ; } if ( ! has_vl_op ( rinsn ) || ! REG_P ( get_vl ( rinsn ) ) ) continue ; rtx avl = get_vl ( rinsn ) ; if ( count_occurrences ( PATTERN ( rinsn ) , avl , <NUM_LIT> ) == <NUM_LIT> ) { auto attempt = crtl -> ssa -> new_change_attempt ( ) ; insn_change change ( insn ) ; access_array_builder uses_builder ( attempt ) ; uses_builder . reserve ( insn -> num_uses ( ) - <NUM_LIT> ) ; for ( use_info * use : insn -> uses ( ) ) if ( use != find_access ( insn -> uses ( ) , REGNO ( avl ) ) ) uses_builder . quick_push ( use ) ; use_array new_uses = use_array ( uses_builder . finish ( ) ) ; change . new_uses = new_uses ; change . move_range = insn -> ebb ( ) -> insn_range ( ) ; rtx


<s> MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst


<s> if ( F -> getName ( ) . startswith (


<s> if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return

AtomicExpansionKind :: MaskedIntrinsic ;


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt <


<s> for ( unsigned int pred_idx = <NUM_LIT> ; group . preds [ pred_idx ] != NUM_PRED_TYPES ; ++ pred_idx ) for ( unsigned int vec_type_idx


<s> SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; SDValue Chain = CurDAG -> getEntryNode ( ) ; Lo = CurDAG -> getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = CurDAG -> getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = CurDAG -> getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = CurDAG -> getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , Passthru , StackSlot , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; SDValue Result = CurDAG -> getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { return true


<s> static void riscv_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs


<s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType ->


<s> void setRVVStackAlign ( Align StackAlign ) { RVVStackAlign =


<s> if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_SaveList ; else if ( Subtarget . hasF ( )


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B


<s> MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , IsStrided , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsStrided , false , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand


<s> machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size (


<s> if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( )

) return outliner :: InstrType :: Invisible ;


<s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo == <NUM_LIT>


<s> bool isUImm5NonZero ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt <


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( getLexer ( ) . is (


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( The<ISA_LIT>64Target


<s> LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg

) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ;


<s> void <ISA_LIT>TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution &


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero ,


<s> bool <ISA_LIT>RemoveRedundancyVSETVL :: removeRedundancy ( ) { if ( ! redundancyVSETVLI . size ( ) ) return false ; for ( MachineInstr * instr : redundancyVSETVLI


<s> reload_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset !=


<s> OperandMatchResultTy parsePairFP64 ( OperandVector &


<s> BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm


<s> addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; addPass ( create<ISA_LIT>ExpandAtomicPseudoPass (


<s> bool isPairFP128 ( ) const { return isReg ( PairFP128Reg


<s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT>


<s> return Op == Other . Op && ShAmt == Other . ShAmt


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc , SplatZero , <STR_LIT>


<s> const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall )


<s> assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> )


<s> case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG


<s> function_builder :: ~ function_builder ( )


<s> riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 ,


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; uint64_t MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo


<s> if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; EVT VecVT = Vec . getValueType ( ) ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG .


<s> static MVT getMaskTypeFor ( EVT VecVT ) { assert ( VecVT . isVector


<s> uint32_t Inst = <STR_LIT> :: read32le ( Bytes . data ( ) ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer


<s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode


<s> return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp ,


<s> SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI

, Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> const riscv_subset_t * begin ( ) const {


<s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ; else if ( MC . isExpr ( ) ) MC . getExpr ( ) -> print ( O , & MAI , true ) ; else llvm_unreachable (


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; Known . resetAll ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth


<s> memset ( & args , <NUM_LIT> , sizeof args ) ; return riscv_pass_by_reference ( cum , TYPE_MODE ( type ) ,


<s> void <ISA_LIT>FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize


<s> SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ResVT = ! VecVT . isInteger ( ) || VecEltVT . bitsGE ( XLenVT ) ? VecEltVT : XLenVT ; SDValue StartSplat = lowerScalarSplat ( SDValue ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , ResVT , Reduction , DAG . getConstant ( <NUM_LIT>


<s> memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case


<s> bool isLegalMaskedScatter ( Type * DataType , Align Alignment


<s> switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , MaskVT , Op1 , Op2 , Op . getOperand ( <NUM_LIT> ) , Mask , VL ) ; return convertFromScalableVector ( VT , Cmp


<s> static bool has_vsetvl_killed_avl_p ( const bb_info * bb , const vector_insn_info & info ) { if ( info . dirty_with_killed_avl_p ( ) ) { rtx avl = info . get_avl ( ) ; if ( vlmax_avl_p ( avl ) ) return find_reg_killed_by ( bb , info . get_avl_reg_rtx ( ) ) != nullptr ; for ( const insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) { def_info * def = find_access ( insn -> defs ( ) , REGNO ( avl


<s> State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else { State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes )