<s> struct ix86_address parts ; int ok ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; if ( REG_P ( operands [ <NUM_LIT> ] ) || ( SImode_address_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ) return false ; if ( ! ix86_ok_to_clobber_flags ( insn ) ) return false ; ok = ix86_decompose_address ( operands [ <NUM_LIT> ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > <NUM_LIT> ) < <NUM_LIT> ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; split_cost =


<s> static bool canWidenShuffleElements ( ArrayRef < int > Mask ) { for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) if ( ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] % <NUM_LIT> != <NUM_LIT> ) || ( Mask [ i + <NUM_LIT> ] != - <NUM_LIT> && ( Mask [ i + <NUM_LIT> ] % <NUM_LIT> != <NUM_LIT> ||

( Mask [ i ] != - <NUM_LIT> && Mask [ i ] + <NUM_LIT> != Mask [ i + <NUM_LIT> ] ) ) ) ) return false ;


<s> if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch64_bti_j_insn_p ( next ) ) continue ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn


<s> label = gen_label_rtx ( ) ; rtx tmp = gen_rtx_fmt_ee ( UNORDERED , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } if ( GET_MODE ( set_dst ) != mode ) { gcc_assert ( mode == CCAmode || mode == CCCmode || mode == CCOmode || mode == CCPmode || mode == CCSmode || mode == CCZmode ) ; set_dst = gen_rtx_REG ( mode


<s> if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum = VM512Regs [ regIdx / <NUM_LIT> ] ; return


<s> for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == N1Opc && ( N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> ) ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal (


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) )


<s> mips_print_operand_reloc ( file , addr . offset , SYMBOL_CONTEXT_MEM , mips_lo_relocs ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , <STR_LIT> , reg_names [ GP_REG_FIRST ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , mips_strip_unspec_address ( x ) ) ; return ; } gcc_unreachable (


<s> if ( hasInlineStackProbe ( MF ) ) return <STR_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute


<s> if ( ! INSN_P ( insn ) ) continue ; rtx_code code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return <NUM_LIT> ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; bool retval = false ; for ( int i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set


<s> if ( usesGlobalOffsetTable ( ) ) return DAG . getGLOBAL_OFFSET_TABLE ( getPointerTy ( ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table


<s> static __inline__ double __fsqrt ( double x ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) :


<s> static bool isUndefOrEqual ( int Val , int CmpVal ) { return ( Val < <NUM_LIT> ||


<s> bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand TrueReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * FalseClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; const TargetRegisterClass * TrueClass = MRI . getRegClass ( TrueReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , FalseClass ) ) return nullptr ; if ( ! MRI . constrainRegClass ( DestReg , TrueClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit


<s> unsigned RegNum = getVPTPred ( ) == <STR_LIT> ? <NUM_LIT> : <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI ,


<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT>


<s> if ( getOptLevel ( ) != CodeGenOpt ::


<s> for ( unsigned I = MI . getNumExplicitOperands ( ) , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . isDead ( ) && MO . getReg ( ) == <STR_LIT> ) MO . setIsDead ( false ) ; } return & MI ; } bool Is64Bit ; unsigned NewOpc = TII -> convertToFlagSettingOpc ( MI . getOpcode ( ) , Is64Bit ) ; Register NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> hasOneNonDBGUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) NewDestReg =


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return


<s> switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : if ( MemOperand != - <NUM_LIT> ) { switch ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS )


<s> STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vreplace_un_v4si || icode == CODE_FOR_vreplace_un_v4sf ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsldb_v16qi || icode == CODE_FOR_vsldb_v8hi || icode == CODE_FOR_vsldb_v4si || icode == CODE_FOR_vsldb_v2di || icode == CODE_FOR_vsrdb_v16qi || icode == CODE_FOR_vsrdb_v8hi || icode == CODE_FOR_vsrdb_v4si || icode == CODE_FOR_vsrdb_v2di ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger (


<s> RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: FPTOSINT_F128_I64 : RTLIB :: FPTOUINT_F128_I64 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> : { assert ( Subtarget -> hasLeonCycleCounter ( ) ) ; SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getCopyFromReg ( Lo , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Lo , Hi } ; SDValue Pair = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; Results . push_back ( Pair ) ; Results . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: SINTTOFP_I64_F128 : RTLIB :: UINTTOFP_I64_F128 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> : { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; if ( Ld -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Ld -> getMemoryVT ( ) != <STR_LIT> ) return ; SDLoc dl ( N ) ; SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , dl , <STR_LIT> , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , <STR_LIT> , Ld -> getOriginalAlign ( ) , Ld

-> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


<s> if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; hi = gen_rtx_HIGH ( Pmode , lo ) ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , <NUM_LIT> ) ; lo = XEXP ( addr


<s> const char * name = i386_pe_strip_name_encoding ( str ) ; if ( * name == '@' ) name ++ ; p = strchr ( name , '@' ) ; if ( p ) return ggc_alloc_string ( name , p


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector (


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { if ( opNum + <NUM_LIT> >= ( int ) MI -> getNumOperands ( ) ) { printOperand ( MI , opNum , O ) ; return ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : opNum = MI -> getNumOperands ( ) - <NUM_LIT> ; break ; } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) ) OpFlag = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag =


<s> SDValue To ; unsigned DestIndex ; if ( FromV1 == <NUM_LIT> ) { From = V1 ; To = V2 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , FromV1Predicate ) - Mask . begin ( ) ; int FromV2 = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) ; assert ( DestIndex <= INT32_MAX && <STR_LIT> ) ; if ( FromV1 == FromV2 && static_cast < int > ( DestIndex ) == Mask [ DestIndex ] % <NUM_LIT> ) { From = V2 ; To = V1 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) - Mask . begin ( ) ; } } else { assert ( std :: count_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) == <NUM_LIT> && <STR_LIT> <STR_LIT> <STR_LIT> ) ; From = V2 ; To = V1 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) - Mask . begin ( ) ; } unsigned SrcIndex = Mask [ DestIndex ] % <NUM_LIT> ; if ( MayFoldLoad ( From ) ) { SDValue NewLoad = NarrowVectorLoadToElement ( cast < LoadSDNode > ( From ) , SrcIndex , DAG ) ; if ( ! NewLoad . getNode ( ) ) return SDValue ( ) ; if ( EVT == <STR_LIT> ) { SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad ) ; SDValue InsertpsMask = DAG . getIntPtrConstant ( DestIndex << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , To , LoadScalarToVector , InsertpsMask ) ; } else


<s> unsigned <ISA_LIT>FastISel :: getLibcallReg ( const Twine & Name ) { Type * GVTy = Type :: getInt32PtrTy ( * Context , <NUM_LIT> ) ; EVT LCREVT = TLI . getValueType ( GVTy ) ; if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , Name ) ; assert ( GV -> getType ( ) == GVTy && <STR_LIT>


<s> SDLoc dl ( Op ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ; unsigned Val = Cst -> getZExtValue (


<s> unsigned <ISA_LIT>AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( MCID . TSFlags & <STR_LIT> && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; return


<s> bool <ISA_LIT>LegalizerInfo :: legalizeLoadStore ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy .


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; else { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes , MachineInstr :: FrameDestroy ) ; if ( MBBI != MBB . end ( ) && AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> &&


<s> NewMBB -> splice ( NewMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return NewMBB


<s> if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) !=


<s> case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , ZeroVec , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Combo = NewLoad ; if ( ! PassThru . isUndef ( ) && ( PassThru . getOpcode ( ) != <STR_LIT> || ! IsZero ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) Combo = DAG . getNode ( <STR_LIT> , dl , VT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Combo , NewLoad . getValue ( <NUM_LIT> ) } , dl


<s> const TargetRegisterClass * AddrRegClass = getRegClassFor ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned mallocPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , bumpSPPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , tmpSPVReg = MRI . createVirtualRegister ( AddrRegClass ) , SPLimitVReg = MRI . createVirtualRegister ( AddrRegClass ) , sizeVReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , physSPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineFunction :: iterator MBBIter = BB ; ++ MBBIter ; MF -> insert ( MBBIter , bumpMBB ) ; MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) ,

bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ;


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <=


<s> if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return


<s> InstructionCost Cost = <NUM_LIT> ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost +


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & , const MCTargetOptions & ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable (


<s> int first_reg ; for ( first_reg = <NUM_LIT> + <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return


<s> if ( final_sequence ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; if ( final_sequence ) { rtx delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; output_restore ( PATTERN ( delay ) ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) =


<s> return ( STI . isAIXABI ( ) && ! STI . is<ISA_LIT>64 ( )


<s> bool isAdrLabel ( ) const { if ( ! isImm ( ) ) return false ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Min = - ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ; int64_t Max = ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) ; return Val >= Min && Val <= Max ; } return true


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( )


<s> unsigned TF = MO . getTargetFlags ( ) ; if ( TF & <STR_LIT> ) O << <STR_LIT> ; else if ( TF & <STR_LIT> ) O << <STR_LIT> ; Get<ISA_LIT>GVSymbol ( MO . getGlobal ( ) , TF ) -> print ( O


<s> static unsigned long arm_compute_func_type ( ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; if ( TREE_CODE ( current_function_decl ) != FUNCTION_DECL ) abort ( ) ; if ( optimize > <NUM_LIT> && current_function_nothrow && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( current_function_needs_context )


<s> if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineInstr * Ear1MI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , Ear1MI ) ; Ear1MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear1MI ) . addImm ( <NUM_LIT> ) ; MachineInstr * SllgMI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , SllgMI ) ; SllgMI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , SllgMI ) . addReg ( Reg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Ear2MI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , Ear2MI ) ; Ear2MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear2MI ) . addImm ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) .


<s> const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG .

getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue (


<s> switch ( RegName [ <NUM_LIT> ] ) { default : return false ; case 'r' : case 'f'


<s> if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) return CFP -> getValueAPF ( ) . isZero ( ) ; else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) if ( ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isZero ( ) ; } return


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mullo_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats


<s> return ( useR7AsFramePointer ( ) && MF . getTarget ( ) .

Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ;


<s> really_need_stack_frame = frame_size ; really_need_stack_frame |= mep_assign_save_slots ( reg_save_size ) ; sp_offset = reg_save_size ; if ( sp_offset + frame_size < <NUM_LIT> ) sp_offset += frame_size ; add_constant ( SP_REGNO , SP_REGNO , - sp_offset , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( mep_call_saves_register ( i ) ) { rtx mem ; bool maybe_dead_p ; machine_mode rmode ; rss = cfun -> machine -> reg_save_slot [ i ] ; if ( ( i == TP_REGNO || i == GP_REGNO || i == LP_REGNO ) && ( ! mep_reg_set_in_function ( i ) && ! mep_interrupt_p ( ) ) ) continue ; if ( mep_reg_size ( i ) == <NUM_LIT> ) rmode = DImode ; else rmode = SImode ; mem = gen_rtx_MEM ( rmode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss ) ) ; maybe_dead_p = rtx_equal_p ( mem , has_hard_reg_initial_val ( rmode , i ) ) ; if ( GR_REGNO_P ( i ) || LOADABLE_CR_REGNO_P ( i ) ) F ( maybe_dead_move ( mem , gen_rtx_REG ( rmode , i ) , maybe_dead_p ) ) ; else if ( rmode == DImode ) { rtx_insn * insn ; int be = TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss + be ) ) ; maybe_dead_move ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , i ) , maybe_dead_p ) ; maybe_dead_move ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP + <NUM_LIT> ) , gen_rtx_ZERO_EXTRACT ( SImode , gen_rtx_REG ( DImode , i ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , maybe_dead_p ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , maybe_dead_p ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( copy_rtx ( mem ) , gen_rtx_REG ( rmode , i ) ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , sp_offset - rss + ( <NUM_LIT> - be ) ) ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP + <NUM_LIT> ) , maybe_dead_p ) ; } else { rtx_insn * insn ; maybe_dead_move ( gen_rtx_REG ( rmode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( rmode , i ) , maybe_dead_p ) ; insn = maybe_dead_move ( mem , gen_rtx_REG ( rmode , REGSAVE_CONTROL_TEMP ) , maybe_dead_p ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( copy_rtx ( mem ) , gen_rtx_REG ( rmode , i ) ) ) ; } } if ( frame_pointer_needed )


<s> int aarch64_simd_attr_length_rglist ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG )


<s> return LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( MemI ) ) { return SMemI -> getPointerOperand ( ) ; } else if ( IntrinsicInst * IMemI = dyn_cast < IntrinsicInst > ( MemI ) ) { if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI ->


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI


<s> if ( code == LT || code == LE ) return pru_output_ltle_signed_cbranch ( operands , is_near ) ; else if ( code == GT || code == GE ) return pru_output_gtge_signed_cbranch ( operands


<s> else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( IsLoopStart ( MI ) ) Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } LLVM_DEBUG ( if ( Start ) dbgs ( ) << <STR_LIT> << * Start ; if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; ) ; if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } else if ( ! ( Start && Dec && End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB


<s> int64_t FPOffset = getFPOffset ( MF , ObjectOffset ) . getBytes ( ) ; int64_t Offset = getStackOffset ( MF , ObjectOffset ) . getBytes ( ) ; bool isCSR = ! isFixed && ObjectOffset >= - ( ( int ) AFI -> getCalleeSavedStackSize ( MFI ) ) ; const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) && ! isSVE ) { PreferFP &= ! SVEStackSize ; if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( isCSR && RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) { assert ( ! SVEStackSize && <STR_LIT> ) ; UseFP = true ; } } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; StackOffset FPOffset = { ObjectOffset , <STR_LIT> } ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR


<s> unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; for ( unsigned I = <NUM_LIT> ; I < BytesPerElement ; ++ I ) Bytes .


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM


<s> Item -> StringValue = std :: string ( StringValue ) ; return ; } Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue ,


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Element = RawMask [ i ] ; uint64_t Index = Element & <NUM_LIT> ; uint64_t PermuteOp = ( Element >> <NUM_LIT> )


<s> const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return VectorSelectTbl [ Idx ] . Cost ; } } return BaseT :: getCmpSelInstrCost ( Opcode , ValTy ,


<s> need_align = <NUM_LIT> ; for ( ; start != barrier ; start = NEXT_INSN ( start ) ) if ( GET_CODE ( start ) == INSN && recog_memoized ( start ) == CODE_FOR_casesi_worker_2 ) { rtx src = SET_SRC ( XVECEXP ( PATTERN ( start ) , <NUM_LIT> , <NUM_LIT> ) ) ; rtx lab = XEXP ( XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; scan = emit_label_after ( lab , scan ) ; } } if ( TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df ) { rtx align_insn = NULL_RTX ; scan = emit_label_after ( gen_label_rtx ( ) , scan ) ; scan = emit_insn_after ( gen_align_log ( GEN_INT ( <NUM_LIT> ) ) , scan ) ; need_align = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; switch ( p -> mode ) { case HImode : break ; case SImode : case SFmode : if ( align_insn && ! p -> part_of_sequence_p ) { for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) emit_label_before ( lab , align_insn ) ; emit_insn_before ( gen_consttable_4 ( p -> value , const0_rtx ) , align_insn ) ; for ( ref = p -> wend ; ref ; ref = LABEL_NEXTREF ( ref ) ) { lab = XEXP ( ref , <NUM_LIT> ) ; emit_insn_before ( gen_consttable_window_end ( lab ) , align_insn ) ; } delete_insn ( align_insn ) ; align_insn = NULL_RTX ; continue ; } else { for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) scan = emit_label_after ( lab , scan ) ; scan = emit_insn_after ( gen_consttable_4 ( p -> value , const0_rtx ) , scan ) ; need_align = ! need_align ; } break ; case DFmode : if ( need_align ) { scan = emit_insn_after ( gen_align_log ( GEN_INT ( <NUM_LIT> ) ) , scan ) ; align_insn = scan ; need_align = <NUM_LIT> ; } case DImode : for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) scan = emit_label_after ( lab , scan ) ; scan = emit_insn_after ( gen_consttable_8 ( p -> value , const0_rtx ) , scan ) ; break ; default : gcc_unreachable ( ) ; } if ( p -> mode != HImode ) { for ( ref = p -> wend ; ref ; ref = LABEL_NEXTREF ( ref ) ) { lab = XEXP ( ref , <NUM_LIT> ) ; scan = emit_insn_after ( gen_consttable_window_end ( lab ) , scan ) ; } } } pool_size = <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; switch ( p


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg (


<s> unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } ShImm = CurDAG -> getTargetConstant ( ShAmt , <STR_LIT> ) ; return true


<s> switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB .

addReg ( DestReg , RegState :: ImplicitDefine ) ;


<s> unsigned tgt = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; MI . addOperand ( MCOperand ::


<s> return ( __m128i ) __builtin_ia32_pmaxuw128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_si128 ( ) ,


<s> Streamer ( Streamer_ ) , CurrentVendor ( <STR_LIT>


<s> GenericOpcode = Op . getOpcode ( ) ; switch ( GenericOpcode ) { case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; default : return false ; } } SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || ! Op . hasOneUse ( ) ) return false ; if ( j < NumEltsIn64Bits ) { if ( V0 . isUndef ( ) ) V0 = Op0 . getOperand ( <NUM_LIT> ) ; } else { if ( V1 . isUndef ( ) ) V1 = Op0 . getOperand ( <NUM_LIT> ) ; } SDValue SourceVec = ( j < NumEltsIn64Bits ) ? V0 : V1 ; if ( SourceVec != Op0 . getOperand ( <NUM_LIT> ) ) return false ; unsigned ExtIndex0 = Op0 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned ExtIndex1 = Op1 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned ExpectedIndex = i * NumEltsIn128Bits + ( j % NumEltsIn64Bits ) * <NUM_LIT> ; if ( ExpectedIndex == ExtIndex0 && ExtIndex1 == ExtIndex0 + <NUM_LIT> ) continue ; if ( GenericOpcode != <STR_LIT> && GenericOpcode != <STR_LIT> )


<s> if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm ( cop ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( opc1 ) ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( CRm ) ) ; return S


<s> if ( ! TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT ( decl ) ) DECL_VISIBILITY ( decl ) =


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetInfo ( ) { RegisterTarget < Triple :: ppc , true > W ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: ppcle , true > X ( getThe<ISA_LIT>32LETarget ( ) , <STR_LIT> , <STR_LIT>


<s> bool IsTC = TLI . isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) && F -> getReturnType ( ) == LCRTy ; if ( IsTC ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , LCRTy , Callee , std :: move ( Args ) ) . setTailCall ( IsTC ) ; std :: pair < SDValue , SDValue > CI = TLI . LowerCallTo ( CLI ) ; return ! CI . second . getNode ( ) ? DAG . getRoot ( )


<s> if ( ! isMemory ( ) || ! Memory . OffsetRegNum || Memory . Alignment != <NUM_LIT> ) return false ; return


<s> return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; }


<s> if ( Subtarget -> hasAVX ( ) ) { if ( ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) || ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) ) { SDValue ZeroVec = getZeroVector ( OpVT , Subtarget -> hasSSE2 ( ) , Subtarget -> hasAVX2 ( ) , DAG , dl ) ; SDValue OpLo = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; SDValue OpHi = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ; } } return SDValue ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ||


<s> return DecodeCAS ( MI , insn , Address , Decoder , false , false


<s> static SDValue PerformADDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue N0 = N -> getOperand (


<s> if ( CodeModel :: Medium == TM . getCodeModel ( ) || CodeModel :: Large == TM . getCodeModel ( ) ) return TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , G -> getGlobal ( ) ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! GV -> isStrongDefinitionForLinker ( ) ) return false ; if ( TM . getFunctionSections ( ) || GV -> hasComdat ( ) || Caller -> hasComdat ( ) || GV -> getSection ( ) != Caller -> getSection ( ) ) return false ; if ( const auto * F = dyn_cast < Function > ( GV ) ) { if ( F -> getSectionPrefix ( ) != Caller -> getSectionPrefix ( ) )


<s> gcc_assert ( REG_P ( dst ) ) ; if ( src == NULL || ( SSE_REGNO_P ( REGNO ( dst ) ) && standard_sse_constant_p ( src , GET_MODE ( dst ) ) != <NUM_LIT> ) || ( STACK_REGNO_P ( REGNO ( dst ) ) && standard_80387_constant_p ( src ) < <NUM_LIT> ) ) return false ; return


<s> unsigned int fcode , avail ; const struct loongarch_builtin_description * d ; fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; gcc_assert ( fcode < ARRAY_SIZE ( loongarch_builtins ) ) ; d = & loongarch_builtins [ fcode ] ; avail = d -> avail ( ) ; gcc_assert ( avail != <NUM_LIT> ) ; switch ( d -> builtin_type ) { case LARCH_BUILTIN_DIRECT : return loongarch_expand_builtin_direct ( d -> icode , target , exp , true ) ; case LARCH_BUILTIN_DIRECT_NO_TARGET


<s> const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( DstRB . getID ( ) != SrcRB . getID ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRB . getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; if ( ! DstRC ) return false ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! SrcRC ) return false ; unsigned SubIdx ; if ( DstRC == SrcRC ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else { return false ; } SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } I . getOperand ( <NUM_LIT> ) . setSubReg


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF )


<s> for ( Value * Operand : II -> operands ( ) ) if ( Operand -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return false ; return II -> getType ( ) -> is<ISA_LIT>_AMXTy


<s> if ( StackTop == <NUM_LIT> ) report_fatal_error (


<s> if ( Is64Bit && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetKFreeBSD ( ) || isTargetNaCl ( ) || Is64Bit ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit )


<s> uint64_t Value = CE -> getValue ( ) ; unsigned Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , Value >>= <NUM_LIT> ) { Imm |= ( Value &


<s> void addSImm7ScaledOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr


<s> const char * pa_output_ior ( rtx * operands ) { unsigned HOST_WIDE_INT mask = INTVAL ( operands [ <NUM_LIT> ] ) ; int bs0 , bs1 , p , len ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; for ( bs0 = <NUM_LIT> ; bs0 < <NUM_LIT> ; bs0 ++ ) if ( ( mask & ( <NUM_LIT> << bs0 ) ) != <NUM_LIT> ) break ; for ( bs1 = bs0 ; bs1 < <NUM_LIT> ; bs1 ++ ) if ( ( mask & ( <NUM_LIT> << bs1 ) ) == <NUM_LIT> ) break ; gcc_assert ( bs1 == <NUM_LIT> || ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs1 ) > mask ) ; p = <NUM_LIT>


<s> ID . AddPointer ( CVal ) ; for ( const auto * GV : GVars ) ID . AddPointer


<s> } bool FPNeedsSetting = hasFP ( MF ) ; for ( ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( FPNeedsSetting && MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { int64_t X29FrameIdx = MBBI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; FuncInfo -> setFramePointerOffset ( MFI -> getObjectOffset ( X29FrameIdx ) ) ; ++ MBBI ; emitRegUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , <STR_LIT> , <STR_LIT> , NumInitialBytes + MFI -> getObjectOffset ( X29FrameIdx ) , MachineInstr :: FrameSetup ) ; MFI -> setOffsetAdjustment ( - MFI -> getObjectOffset ( X29FrameIdx ) - MFI -> getStackSize ( ) ) ; if ( NeedsFrameMoves ) { unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = MFI -> getObjectOffset ( X29FrameIdx ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } FPNeedsSetting = false ; } if ( ! MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) break ; } assert ( ! FPNeedsSetting && <STR_LIT> ) ; emitSPUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , - NumResidualBytes , MachineInstr :: FrameSetup ) ; if ( ! NeedsFrameMoves ) return ; if ( ! hasFP ( MF ) && NumResidualBytes ) { MachineLocation Dst ( MachineLocation :: VirtualFP ) ; unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = NumResidualBytes + NumInitialBytes


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Expr ,


) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ; if ( LD . getNode ( ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Shuffle = PerformTargetShuffleCombine ( SDValue ( N , <NUM_LIT> ) , DAG , DCI , Subtarget ) ; if ( Shuffle . getNode ( ) ) return Shuffle ; SmallVector < int , <NUM_LIT>


<s> unsigned Reg = VMRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> unsigned getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const override { return MinPrefetchStride


<s> Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( ! isLoadStoreTypeLegal ( Op0 -> getType ( ) , VT ) || cast <

StoreInst > ( I ) -> isAtomic ( ) ) return false ;


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg


<s> RegisterTarget < Triple :: mips64 , true > A ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mips64el , true > B ( getThe<ISA_LIT>64elTarget ( ) , <STR_LIT> ,


<s> else if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Imm , S , E , getContext ( ) ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok (


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC


<s> if ( ! isPositionIndependent ( ) ) return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N


<s> { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = const_double_from_real_value ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ : case IA64_BUILTIN_COPYSIGNQ


<s> DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , PersonalityRef , MCFixup :: getKindForSize (


<s> if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; return aarch64_float_const_representable_p (


<s> memcpy ( & ls -> saved_state , & sr -> curr , sizeof ( ls -> saved_state ) ) ; ls -> saved_state . next = dup_state_stack ( sr -> curr . next ) ; ls -> next = sr


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant


<s> void addRegF4RCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( FRegs


<s> if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) , Mask -> getType ( ) } , { Ptr

, Builder . getInt32 ( <NUM_LIT> ) , Mask } ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved


<s> return Op + <STR_LIT> <= MI . getNumOperands ( ) && MI . getOperand ( Op + <STR_LIT> ) . isReg (


<s> case UNSPEC_CHKACLR : case UNSPEC_CHKS : return may_trap_p_1 ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , flags ) ; } return default_unspec_may_trap_p ( x , flags


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return

G -> getGlobal ( ) -> isStrongDefinitionForLinker ( ) ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDXAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; uint64_t Index = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Index ) ) ; return ( Index << <NUM_LIT> ) |


<s> else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO (


<s> } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_AARCH64_ABS64 == pReloc . type ( ) && llvm :: ELF :: R_AARCH64_RELATIVE == dyn_rel -> type ( ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator :: OK ; } } } pReloc . target ( ) = S + A ; return Relocator


<s> case InlineAsm :: Constraint_X : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 )


<s> static DecodeStatus DecodeCCOperand ( MCInst & MI , uint64_t cf

, uint64_t Address , const void * Decoder ) {


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs ,


<s> switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & <NUM_LIT> ) == <NUM_LIT> ) && IN_RANGE ( INTVAL ( addr ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : return true ; default : return


<s> bool Micro<ISA_LIT>SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicro<ISA_LIT>Mode ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return false ; <ISA_LIT>II = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false


<s> getTargetStreamer ( ) . emitFnEnd ( ) ; UC . reset ( ) ; return false


<s> std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != ExpectedOpcode || V2 . getOpcode ( ) != NextExpectedOpcode ) return false ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return false ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return false ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return false ; Opnd0 =


<s> case 'H' : if ( REG_P ( x ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) + <NUM_LIT> ] ) ; else output_operand_lossage ( <STR_LIT> ) ; break ; case 'd' : if ( REG_P ( x ) ) { if ( GET_MODE ( x ) == DFmode || GET_MODE ( x ) == DImode ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] , reg_names [ REGNO ( operand ) + <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] ) ; } else output_operand_lossage ( <STR_LIT> ) ; break ; case 'h' : print_reloc ( file , x , <NUM_LIT> , RKIND_HI ) ; break ; case 'L' : print_reloc ( file , x , <NUM_LIT> , RKIND_LO ) ; break ; case 'P' : if ( ! flag_pic || SYMBOL_REF_LOCAL_P ( x ) ) output_addr_const ( file , x ) ; else output_addr_reloc ( file , x , <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : switch ( GET_CODE ( operand ) ) { case REG : if ( REGNO ( operand ) > <NUM_LIT> ) internal_error ( <STR_LIT> , REGNO ( operand ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] ) ; break ; case MEM : output_address ( GET_MODE ( XEXP ( operand , <NUM_LIT> ) ) , XEXP ( operand , <NUM_LIT> ) ) ; break ; case CODE_LABEL : case LABEL_REF


<s> auto Converted = PromotionCache . insert ( std :: make_pair (

& C , <ISA_LIT>PromoteConstant :: PromotedConstant ( ) ) ) ;


<s> while ( insn ) { if ( insn == label ) break ; else insn = NEXT_INSN ( insn ) ; } return ( insn ==


<s> return ( __m128i ) __builtin_ia32_packssdw128 ( ( __v4si ) __A , (


<s> else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , isImmutable , false ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset


<s> int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( csky_label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && csky_label_mentioned_p ( XEXP ( x , i ) )


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( i == <NUM_LIT> ) continue ; fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = ( long ) & ( sc -> sc_regs [ i ] ) - new_cfa ; } fs -> regs . reg [ SH_DWARF_FRAME_SR ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SH_DWARF_FRAME_SR ] . loc . offset = ( long ) & ( sc -> sc_sr ) - new_cfa ; r = SH_DWARF_FRAME_BT0 ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ r + i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ r + i ] . loc . offset = ( long ) & ( sc -> sc_tregs [ i ] ) - new_cfa ; } r = SH_DWARF_FRAME_FP0 ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ r + i ] .


<s> ConstantInt * ConstElemCount = nullptr ; if ( ! SE -> isLoopInvariant ( EC , L ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ( ConstElemCount = dyn_cast < ConstantInt > ( ElemCount ) ) ) { ConstantInt * TC = dyn_cast < ConstantInt > ( TripCount ) ; if ( ! TC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } uint64_t TC1 = TC -> getZExtValue ( ) ; uint64_t TC2 = ( ConstElemCount -> getZExtValue ( ) + VectorWidth - <NUM_LIT> ) / VectorWidth ; if ( TC1 != TC2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TC1 << <STR_LIT> << TC2 << <STR_LIT> ) ; return false ; } } else if ( ! ForceTailPredication ) { auto * VW = SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ; auto * ECPlusVWMinus1 = SE -> getAddExpr ( EC , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , VW ) ; ( void ) TC ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; TC -> dump


<s> StructType * ST = cast < StructType > ( T ) ; if ( ST -> getNumElements ( ) != <NUM_LIT> ) break ; if ( ( ST -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) && ( ST -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) )


<s> bool mips_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != <NUM_LIT> ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return false ; if ( mips_abi == ABI_O64 ) if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return


<s> bool runOnMachineFunction ( MachineFunction & F ) { <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && ! hasHardQuad ) return TLI . LowerF128Op ( Op , DAG

, TLI . getLibcallName ( RTLIB :: FPTOSINT_F128_I32 ) , <NUM_LIT> ) ;


<s> if ( ! Visited . insert ( MemAddr ) . second ) return false ; const auto * GV = dyn_cast < GlobalValue > ( MemAddr ) ; if ( ! GV ) { if ( const auto * CV = dyn_cast < Constant > ( MemAddr ) ) for ( const auto & CO : CV -> operands ( ) ) if ( memAddrUsesCTR ( CO , TM , Visited ) ) return true ; return false ; } if ( ! GV -> isThreadLocal ( ) ) return false ; TLSModel :: Model Model = TM . getTLSModel (


<s> SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> :


<s> return MI . modifiesRegister ( <STR_LIT> , TRI


<s> arm_configure_build_target ( & arm_active_target , ptr , opts_set ,


<s> return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) , getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) , getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) .

addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> SDValue Result = DAG . getAtomic ( Node -> getOpcode ( ) , dl , <STR_LIT> , Tys , Ops . data ( ) , Ops . size ( ) , cast < MemSDNode > ( Node ) -> getMemOperand ( ) , AN -> getSuccessOrdering ( ) , AN -> getFailureOrdering ( ) , AN -> getSynchScope ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue


<s> if ( OutUnscaledOp ) * OutUnscaledOp = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = isSVEScaledImmInstruction ( MI . getOpcode ( ) ) ; int64_t Offset = IsMulVL ? ( SOffset . getScalableBytes ( ) ) : ( SOffset . getBytes ( ) ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) * EmittableOffset = NewOffset ; if ( OutUseUnscaledOp ) * OutUseUnscaledOp = useUnscaledOp ; if ( OutUnscaledOp && UnscaledOp ) * OutUnscaledOp = * UnscaledOp ; if ( IsMulVL ) SOffset = StackOffset ( Offset , <STR_LIT> ) + StackOffset ( SOffset . getBytes ( ) , <STR_LIT> ) ; else SOffset = StackOffset ( Offset , <STR_LIT> ) + StackOffset

( SOffset . getScalableBytes ( ) , <STR_LIT> ) ;


<s> F -> insert ( MBBIter , newMBB ) ; F -> insert ( MBBIter , nextMBB ) ; nextMBB -> transferSuccessors ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; assert ( bInstr -> getNumOperands ( ) < <NUM_LIT> && <STR_LIT> ) ; MachineOperand & dest1Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & dest2Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t2 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx - <NUM_LIT> ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MachineOperand newOp3 = * ( argOpers [ <NUM_LIT> ] ) ; if ( newOp3 . isImm ( ) ) newOp3 . setImm ( newOp3 . getImm ( ) + <NUM_LIT> ) ; else newOp3 . setOffset ( newOp3 . getOffset ( ) + <NUM_LIT> ) ; ( * MIB ) . addOperand ( newOp3 ) ; unsigned t3 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned t4 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , dest1Oper . getReg ( ) ) . addReg ( t1 ) . addMBB ( thisMBB ) . addReg ( t3 ) . addMBB ( newMBB ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , dest2Oper . getReg ( ) ) . addReg ( t2 ) . addMBB ( thisMBB ) . addReg ( t4 ) . addMBB ( newMBB ) ; unsigned tt1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned tt2 = F -> getRegInfo ( ) . createVirtualRegister ( RC


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Val ) const { if ( Val < <NUM_LIT> ) Val = - Val ; return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> || (


<s> if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const <ISA_LIT>BaseTargetMachine & <ISA_LIT>_TM = static_cast < const <ISA_LIT>BaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = <ISA_LIT>_TM . TargetABI


<s> unsigned Reg = MRI -> createVirtualRegister ( PromoteRC ) ; auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ( Cond ) ) , Reg ) ; ( void )


<s> const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) ; return getAIXFuncEntryPointSymbolSDNode ( F -> getName ( ) , F -> isDeclaration ( ) , SC ) ; } return getAIXFuncEntryPointSymbolSDNode ( SymName , true


<s> const SymbolListType & getGlobalGOTSyms ( ) const { return m_GlobalGOTSyms


<s> rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( <NUM_LIT> , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 )


<s> if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; else if ( TF == <STR_LIT> ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO


<s> EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; return getTargetShuffleInputs ( Op , DemandedElts , Inputs , Mask ,

KnownUndef , KnownZero , DAG , Depth , ResolveKnownElts ) ;


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall ,

Outs , OutVals , Ins , dl , DAG , InVals ) ;


<s> rtx x = args [ argno ] ; if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ; if ( ! x ) return false ; args [ argno ] = x ; return


<s> JCE . emitWordLE ( ( intptr_t ) Ptr ) ; void * PtrAddr = JCE . finishGVStub ( GV ) ; addIndirectSymAddr ( Ptr , ( intptr_t ) PtrAddr


<s> } } if ( Subtarget . hasVector ( ) && DCI . Level == BeforeLegalizeTypes && isOnlyUsedByStores ( Op1 , DAG ) ) { SDValue Word = SDValue ( ) ; EVT WordVT ; auto FindReplicatedImm = [ & ] ( ConstantSDNode * C , unsigned TotBytes ) { if ( C -> getAPIntValue ( ) . getBitWidth ( ) > <NUM_LIT> || C -> isAllOnes ( ) || isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) || MemVT . getStoreSize ( ) <= <NUM_LIT> ) return ; <ISA_LIT>VectorConstantInfo VCI ( APInt ( TotBytes * <NUM_LIT> , C -> getZExtValue ( ) ) ) ; if ( VCI . isVectorConstantLegal ( Subtarget ) && VCI . Opcode == <STR_LIT> ) { Word = DAG . getConstant ( VCI . OpVals [ <NUM_LIT> ] , SDLoc ( SN ) , <STR_LIT> ) ; WordVT = VCI . VecVT . getScalarType ( ) ; } } ; auto FindReplicatedReg = [ & ] ( SDValue MulOp ) { EVT MulVT = MulOp . getValueType ( ) ; if ( MulOp -> getOpcode ( ) == <STR_LIT> && ( MulVT == <STR_LIT> || MulVT == <STR_LIT> || MulVT == <STR_LIT> ) ) { SDValue LHS = MulOp -> getOperand ( <NUM_LIT> ) ; if ( LHS -> getOpcode ( ) == <STR_LIT> ) WordVT = LHS -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; else if ( LHS -> getOpcode ( ) == <STR_LIT> ) WordVT = cast < VTSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; else return ; if ( auto * C = dyn_cast < ConstantSDNode > ( MulOp -> getOperand ( <NUM_LIT> ) ) ) { <ISA_LIT>VectorConstantInfo VCI ( APInt ( MulVT . getSizeInBits ( ) , C -> getZExtValue ( ) ) ) ; if ( VCI . isVectorConstantLegal ( Subtarget ) && VCI . Opcode == <STR_LIT> && VCI . OpVals [ <NUM_LIT> ] == <NUM_LIT> && WordVT == VCI . VecVT . getScalarType ( ) ) Word = DAG . getZExtOrTrunc ( LHS -> getOperand ( <NUM_LIT> ) , SDLoc ( SN ) , WordVT ) ; } } } ; if ( isa < BuildVectorSDNode > ( Op1 ) && DAG . isSplatValue ( Op1 , true ) ) { SDValue SplatVal = Op1 -> getOperand ( <NUM_LIT> ) ; if ( auto * C = dyn_cast < ConstantSDNode > ( SplatVal ) ) FindReplicatedImm ( C , SplatVal . getValueType ( ) . getStoreSize ( ) ) ; else FindReplicatedReg ( SplatVal ) ; } else { if ( auto * C = dyn_cast < ConstantSDNode > ( Op1 ) ) FindReplicatedImm ( C , MemVT


<s> return TM . getRelocationModel ( ) == Reloc :: RWPI || TM .

getRelocationModel ( ) == Reloc :: ROPI_RWPI ;


<s> EVT Ty = Op . getValueType ( ) ; if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , SDLoc ( Op ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> return ( __m256i ) __builtin_ia32_loaddqudi256_mask ( ( const long long * ) __P , ( __v4di ) __W


<s> if ( <STR_LIT> <= RegNo && RegNo <= <STR_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> <= RegNo && RegNo


<s> dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP8_MAP : dec = & XOP8_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP9_MAP : dec = & XOP9_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOPA_MAP : dec = & XOPA_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : debug ( <STR_LIT> ) ; return <NUM_LIT>


<s> void paired_expand_vector_move ( rtx operands [ ] ) { rtx op0 = operands [ <NUM_LIT> ] , op1 = operands [ <NUM_LIT> ] ; emit_move_insn ( op0 ,


<s> bool mips_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { if ( op == STORE_BY_PIECES ) return mips_store_by_pieces_p ( size , align ) ; if ( op == MOVE_BY_PIECES && HAVE_cpymemsi ) { if ( currently_expanding_to_rtl ) return false ; if ( align < BITS_PER_WORD ) return size < UNITS_PER_WORD ; return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT ; } return default_use_by_pieces_infrastructure_p ( size , align , op


<s> bool NeedSwap ; std :: tie ( CC , NeedSwap ) = <STR_LIT> ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS


<s> static DecodeStatus DecodeThreeAddrSRegInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftHi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftLo = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shift = ( shiftHi << <NUM_LIT> ) | shiftLo ; switch ( Inst . getOpcode ( ) ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; case <STR_LIT> : case


<s> if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode (


) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return <NUM_LIT> ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : return <NUM_LIT> ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return <NUM_LIT> ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy (


<s> if ( Cond != <STR_LIT> || ! isZerosVector ( RHS . getNode ( ) ) || LHS -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Extract = LHS -> getOperand ( <NUM_LIT> ) ; if ( Extract -> getOpcode ( ) != <STR_LIT> || Extract -> getValueType ( <NUM_LIT> ) != N -> getValueType ( <NUM_LIT> ) || Extract -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue InnerSetCC = Extract -> getOperand ( <NUM_LIT> ) ; if ( InnerSetCC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue InnerPred = InnerSetCC . getOperand ( <NUM_LIT>