<s> if ( Subtarget -> isTargetMachO ( ) ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ || RelocM == Reloc :: DynamicNoPIC ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; SetVector < const MCSection * , SmallVector < const MCSection * , <NUM_LIT> > , SmallPtrSet < const MCSection * , <NUM_LIT> > > TextSections ; TextSections . insert ( TLOFMacho . getTextSection ( ) ) ; for ( Module :: iterator F = M . begin ( ) , e = M . end ( ) ; F != e ; ++ F ) if ( ! F -> isDeclaration ( ) && ! F -> hasAvailableExternallyLinkage ( ) ) TextSections . insert ( TLOFMacho . SectionForGlobal ( F , * Mang , TM ) ) ; TextSections . insert ( TLOFMacho . getTextCoalSection ( ) ) ; TextSections . insert ( TLOFMacho . getConstTextCoalSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = TextSections . size ( ) ; i != e ; ++ i ) OutStreamer . SwitchSection ( TextSections [ i ] ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false

, false , MachinePointerInfo ( <NUM_LIT> ) , MachinePointerInfo ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>XPLINKFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; bool HasFP = hasFP ( MF )


<s> } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( DL ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg !=


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> return :: isMOVLMask ( N -> op_begin ( ) , N -> getNumOperands ( )


<s> if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned RegNum = InVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT>


<s> new_list -> window = XNEWVEC ( struct sched_insn_info_s , MAX_INSN + <NUM_LIT>


<s> return ( float32x2_t ) __builtin_neon_vabdfv2sf (


<s> if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) ) return getRegBank ( <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC


<s> Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchACRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128RegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128CtrlRegisterName ( Identifier ) ; if ( Index != -


<s> unsigned Kind = Fixup . getKind ( ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return AdrImmBits ( Value & <NUM_LIT> ) ; case <STR_LIT> : assert ( ! IsResolved ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return AdrImmBits ( Value & <NUM_LIT> ) ; return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup


<s> return ( __m512h ) __builtin_ia32_getmantph512_mask ( ( __v32hf ) __A , ( __C << <NUM_LIT> ) |


<s> <ISA_LIT>AssemblerOptions ( const FeatureBitset & Features_ ) : ATReg ( <NUM_LIT> ) , Reorder ( true ) ,

Macro ( true ) , Features ( Features_ ) {


<s> vld1q_dup_u64 ( const uint64_t * __a ) { return vdupq_n_u64 ( *


<s> MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DOUT << <STR_LIT> << * BMI ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = next ( MachineFunction :: iterator ( MBB ) ) ; DOUT << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBSizes [ MI -> getParent ( ) -> getNumber ( ) ] -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; int delta = TII -> GetInstSizeInBytes ( & MBB ->


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


) __B , ( __vector unsigned long long ) __A ) ;


<s> case Instruction :: Mul : return false ; case Instruction :: Add : return ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ; case Instruction :: ICmp : return ( ScalarBits < <NUM_LIT> ) && ( ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ) ; case Instruction :: FCmp : return Flags . NoNaN ; default : llvm_unreachable ( <STR_LIT> ) ; } return


<s> if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == <NUM_LIT> ) { uint64_t isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags


<s> if ( IsSubWord ) BitSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = MRI . createVirtualRegister ( RC ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB =


<s> DEBUG ( dbgs ( ) << <STR_LIT> << R << <STR_LIT> ) ; unsigned MatchingType = getMatchingLoType ( R ) ; assert ( MatchingType != ELF :: R_MIPS_NONE && <STR_LIT> ) ; auto InsertionPoint = find_best ( Sorted . begin ( ) , Sorted . end ( ) , [ & R , & MatchingType ] ( const <ISA_LIT>RelocationEntry & X ) { return isMatchingReloc ( X , R , MatchingType ) ; } , compareMatchingRelocs ) ; if ( InsertionPoint != Sorted . end ( ) ) InsertionPoint -> Matched = true ; Sorted . insert ( InsertionPoint , R ) -> Matched = true ; } DEBUG ( dumpRelocs ( <STR_LIT> , Sorted )


<s> setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetCC_<ISA_LIT> ) ; <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; } MIRBuilder . insertInstr ( MIB ) ; return


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain ,


<s> LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc ; if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) NewOpc = <STR_LIT> ; else if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) NewOpc = STI . isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; addOffset ( MIB ,


<s> assert ( MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) == ( Is64Bit ? <STR_LIT> : <STR_LIT> ) && <STR_LIT> ) ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; StackAdjust = <NUM_LIT> ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { PrevStackSize = StackSize ; StackSize = std :: abs ( Inst . getOffset ( ) ) / StackDivide ; ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; SavedRegs [ SavedRegIdx ++ ] = Reg ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ( Reg ) ; break ; } } } StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { if ( ( NumDefCFAOffsets == SavedRegIdx + <NUM_LIT> && StackSize - PrevStackSize == <NUM_LIT> ) || ( Instrs . size ( ) == <NUM_LIT> && NumDefCFAOffsets == <NUM_LIT> && StackSize == <NUM_LIT> ) ) return CU :: UNWIND_MODE_DWARF ; SubtractInstrIdx += InstrOffset ; ++ StackAdjust ; if ( ( StackSize & <NUM_LIT> ) == StackSize ) { CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IMMD ; CompactUnwindEncoding |= ( StackSize & <NUM_LIT> ) << <NUM_LIT> ; } else { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IND ; CompactUnwindEncoding |= ( SubtractInstrIdx & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; } std :: reverse ( & SavedRegs [ <NUM_LIT> ] , & SavedRegs [ SavedRegIdx ] ) ; CompactUnwindEncoding |= ( SavedRegIdx &


<s> StringRef Name ( SysReg . Data , SysReg . Length ) ; <STR_LIT> ( ) . fromString


<s> auto * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueSizeInBits ( ) ) return false ; ShiftVal = Amount


<s> __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) val . val [ <NUM_LIT>


<s> warning ( <NUM_LIT> , <STR_LIT> , name ) ; * no_add = true ; } else if ( args == NULL_TREE && TREE_CODE ( * node ) == VAR_DECL ) { if ( ! ( TREE_PUBLIC ( * node ) || TREE_STATIC ( * node ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; * no_add = true ; } if ( TREE_TYPE ( * node ) && TREE_CODE ( TREE_TYPE ( * node ) ) == POINTER_TYPE ) { warning ( <NUM_LIT> , <STR_LIT> ) ; * no_add = true ; } } return NULL_TREE


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { return


<s> const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , DL , GA ) ; } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag , GV ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset (


<s> __rv . __o = __builtin_neon_vld3_dupv4hi ( ( const


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _MM_SET_ROUNDING_MODE ( unsigned int __mode ) { _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_ROUND_MASK


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ) ) ; } if ( SDValue Cmp = foldVectorXorShiftIntoCmp ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue SetCC = foldXor1SetCC ( N , DAG ) ) return SetCC ; if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; return combineFneg ( N , DAG


<s> SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; if ( N00VT == N10 . getValueType ( ) && ( N00VT == <STR_LIT> || N00VT == <STR_LIT> ) && N00VT . getScalarSizeInBits ( ) == <NUM_LIT> * VT . getScalarSizeInBits ( ) ) { MVT MidVT = ( N00VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( MidVT . getVectorNumElements ( ) ) ; for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( )


<s> Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( )


<s> for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j


<s> SUnit * <ISA_LIT>PostRASchedStrategy :: pickNode ( bool & IsTopNode ) { IsTopNode = true ; if ( Available . empty ( ) ) return nullptr ; if ( Available . size ( ) == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec -> dumpSU ( * Available . begin ( ) , dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; ) ; return * Available . begin ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; Available . dump ( * HazardRec ) ; ) ; Candidate Best ; for ( auto * SU : Available ) { Candidate c ( SU , * HazardRec ) ; if ( Best . SU == nullptr || c < Best ) { Best = c ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; } else DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DEBUG ( HazardRec -> dumpSU ( c . SU , dbgs


<s> bool Filler :: needsUnimp ( MachineBasicBlock :: iterator I , unsigned & StructSize ) { if ( ! I -> getDesc ( ) . isCall ( ) ) return false ; unsigned structSizeOpNum = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; } const MachineOperand & MO = I -> getOperand ( structSizeOpNum ) ; if ( ! MO . isImm


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions (


<s> if ( TAI -> hasDotTypeDotSizeDirective ( ) && ! Subtarget -> isLinux ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName


<s> if ( ! rs6000_tls_symbol ) rs6000_tls_symbol


<s> } if ( State . RecursiveCall ) return false ; unsigned Opc = Inst . getOpcode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( ( State . I == <NUM_LIT> ) && ( State . SaveCount == <NUM_LIT> ) ) { switch ( Opc ) { default : State . SaveCount = <NUM_LIT> ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; } } if ( State . I < State . SaveCount ) { State . Saved [ State . I ++ ] = Inst ; if ( State . I < State . SaveCount ) return true ; } if ( State . SaveCount > <NUM_LIT> ) { assert ( State . I == State . SaveCount && <STR_LIT> ) ; State . SaveCount = <NUM_LIT> ; State . RecursiveCall = true ; switch ( State . Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( State . I , State .


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI


<s> SDValue V ( <NUM_LIT> , <NUM_LIT> ) ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , true , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt = LastElt ; if ( ThisElt . getNode ( ) ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , ThisElt , DAG . getIntPtrConstant ( i /


<s> switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress (


<s> return ( poly8x16_t ) __builtin_neon_vset_lanev16qi ( ( __builtin_neon_qi ) __a , ( int8x16_t )


<s> * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode )


<s> if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( CONST_INT_P ( XEXP ( address , <NUM_LIT> ) ) ) ; offset = INTVAL ( XEXP ( address , <NUM_LIT> ) ) ; address = XEXP ( address , <NUM_LIT> ) ; } else offset = <NUM_LIT> ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address =


<s> return __builtin_loongson_pandn_ud ( s


<s> std :: string Suffix ( <STR_LIT> ) ; if ( NumLanes ) Suffix += itostr ( NumLanes )


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState


<s> static bool getTargetShuffleInputs ( SDValue Op , const APInt & DemandedElts , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , APInt & KnownUndef , APInt & KnownZero , const SelectionDAG & DAG , unsigned Depth , bool ResolveKnownElts ) { if ( Depth >= SelectionDAG :: MaxRecursionDepth ) return false ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; if ( getTargetShuffleAndZeroables ( Op , Mask , Inputs , KnownUndef ,


<s> bool allowsUnalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = <NUM_LIT>

, bool * Fast = nullptr ) const override {


<s> if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > &


<s> unsigned Vm = ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CSD = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! CSD ) return false ; ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal > <NUM_LIT> ) return false ; Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else { Ext = getExtendTypeForNode ( N


<s> return ( __m128h ) __builtin_ia32_vfcmaddcph128_maskz ( ( __v8hf ) __B , ( __v8hf )


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( )


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream &


<s> const TargetRegisterClass * RC ; switch ( ExtraCode [ <NUM_LIT> ] ) { case 'b' : RC = & <STR_LIT> ; break ; case 'h' : RC = & <STR_LIT> ; break ; case 's' : RC = & <STR_LIT> ; break ; case 'd' : RC = & <STR_LIT> ; break ; case 'q' : RC = & <STR_LIT> ; break ; case 'z' : RC = & <STR_LIT> ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , <STR_LIT> , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO ,


<s> if ( I . second ) { MIBundleBuilder ( I . second ) . append ( MF -> CloneMachineInstr ( & * Filler ) ) ; ++ UsefulSlots ; } else { I . first -> push_back ( MF -> CloneMachineInstr (


<s> named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > <NUM_LIT> ) * pretend_arg_size = anon_parm_regs *


<s> return ( Kind == k_Register && Reg . Kind == rk_FloatReg


<s> return __builtin_ia32_vec_ext_v4si ( ( __v4si )


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm ( <NUM_LIT> ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1

, RegState :: Kill ) . addImm ( PCLabelId ) ) ;


<s> unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( <STR_LIT> , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return <NUM_LIT> ; SrcReg = TmpReg ; } Address Addr ; Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { if ( ! IsSigned ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( <ISA_LIT>SubTarget -> isLittleEndian ( )


<s> return ( t == float128_type_node || ( t && t == float128t_type_node ) ||

( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t == long_double_type_node ) ) ;


<s> if ( ! O ) return false ; auto Opcode = O -> getOpcode ( ) ; Value * RHS = * std :: prev ( U -> op_end


<s> case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M16INT : case TYPE_M32INT


<s> Inst . addOperand ( MCOperand :: createReg ( getFGR32Reg ( ) ) ) ; if ( ! AsmParser . useOddSPReg ( ) && RegIdx . Index

& <NUM_LIT> ) AsmParser . Error ( StartLoc , <STR_LIT> <STR_LIT> ) ;


<s> assert ( std :: is_sorted ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) && std :: is_sorted ( std :: begin

( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain ) ) && <STR_LIT> ) ;


<s> bool ix86_d_has_stdcall_convention ( unsigned int * link_system , unsigned int * link_windows ) { if ( ix86_abi == MS_ABI ) { * link_system = <NUM_LIT> ; * link_windows = ( ! TARGET_64BIT ) ? <NUM_LIT> : <NUM_LIT> ; } else { * link_system = <NUM_LIT>


<s> return - <NUM_LIT> ; } StringRef Name = Parser . getTok ( ) . getString ( ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchRegisterNameAlias ( Head , true ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > (


<s> case FK_PCRel_1 : return <NUM_LIT> ; case FK_Data_2 : case FK_PCRel_2 : return <NUM_LIT> ; return <NUM_LIT> ; case FK_Data_4 : case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Ctx . GetOrCreateSymbol ( Name . str ( )


<s> bool isMSRMask ( ) const { return Kind ==


<s> I . Size += ( addLongBranch ( * MBB , llvm :: next ( Iter ( I . Br ) ) , Tgt , DL , true ) - <NUM_LIT> ) * <NUM_LIT> ; llvm :: next ( MachineBasicBlock :: instr_iterator ( I . Br ) ) -> setIsInsideBundle ( false ) ; I . Br -> eraseFromParent ( ) ; return ; } assert ( I . Br -> isConditionalBranch ( ) && <STR_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MF -> insert ( llvm :: next ( MachineFunction :: iterator ( MBB ) ) , NewMBB ) ; MBB -> removeSuccessor ( Tgt ) ; MBB -> addSuccessor ( NewMBB ) ; NewMBB -> addSuccessor ( Tgt ) ; I . Size += addLongBranch ( * NewMBB , NewMBB -> begin ( ) , Tgt , DL


<s> if ( LoopCount -> getOpcode ( ) == <STR_LIT> || LoopCount -> getOpcode ( ) == <STR_LIT> ) { int64_t TripCount = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) + TripCountAdjust ; LoopCount -> getOperand ( <NUM_LIT> ) . setImm


<s> void addFGR32AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> bool i386_pe_type_dllimport_p ( tree ) { return false


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS )


<s> Builder . SetInsertPoint ( Trunc ) ; IntegerType * SrcTy = cast < IntegerType > ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; IntegerType * DestTy = cast < IntegerType > ( TruncTysMap [ Trunc ] [ <NUM_LIT> ] ) ; unsigned NumBits = DestTy -> getScalarSizeInBits ( ) ; ConstantInt * Mask = ConstantInt :: get ( SrcTy , APInt :: getMaxValue ( NumBits ) .


<s> default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : { StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , S ,


<s> while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI -> isCall ( ) && MI -> definesRegister ( <STR_LIT> ) ) return true ; return false


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI ->


<s> void <ISA_LIT>InstPrinter :: printAbsBranchOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand


<s> bool Micro<ISA_LIT>SizeReduce :: ReplaceInstruction ( MachineInstr * MI , const ReduceEntry & Entry ) { MI -> setDesc ( <ISA_LIT>II -> get ( Entry . NarrowOpc ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ NumReduced


<s> void <ISA_LIT>InstPrinter :: printSORegRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; printRegName ( O , MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT>


<s> aarch64_tune_flags = selected_tune -> flags ; aarch64_tune = selected_tune -> sched_core ; aarch64_tune_params = * ( selected_tune -> tune ) ; aarch64_architecture_version = selected_arch -> architecture_version ; if ( opts -> x_aarch64_override_tune_string ) aarch64_parse_override_string ( opts -> x_aarch64_override_tune_string , & aarch64_tune_params ) ; if ( opts -> x_flag_strict_volatile_bitfields < <NUM_LIT> && abi_version_at_least ( <NUM_LIT> ) ) opts -> x_flag_strict_volatile_bitfields = <NUM_LIT> ; initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = <NUM_LIT> ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> num_slots > <NUM_LIT> ) maybe_set_param_value ( PARAM_SIMULTANEOUS_PREFETCHES , aarch64_tune_params . prefetch -> num_slots , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_size >= <NUM_LIT> ) maybe_set_param_value ( PARAM_L1_CACHE_SIZE , aarch64_tune_params . prefetch -> l1_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_line_size >= <NUM_LIT> ) maybe_set_param_value ( PARAM_L1_CACHE_LINE_SIZE , aarch64_tune_params . prefetch -> l1_cache_line_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l2_cache_size >= <NUM_LIT> ) maybe_set_param_value ( PARAM_L2_CACHE_SIZE , aarch64_tune_params . prefetch -> l2_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; maybe_set_param_value ( PARAM_SCHED_PRESSURE_ALGORITHM , SCHED_PRESSURE_MODEL , opts -> x_param_values , global_options_set . x_param_values ) ; if ( opts -> x_flag_prefetch_loop_arrays < <NUM_LIT> && ! opts -> x_optimize_size && aarch64_tune_params . prefetch -> default_opt_level >= <NUM_LIT> && opts -> x_optimize >= aarch64_tune_params .

prefetch -> default_opt_level ) opts -> x_flag_prefetch_loop_arrays = <NUM_LIT> ;


<s> MJTEs = nullptr ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF


<s> const RegisterBankInfo * getRegBankInfo ( )


<s> unsigned NumEltsPer128BitChunk = NumElts / Num128BitChunks ; unsigned NumEltsPer64BitChunk = NumEltsPer128BitChunk / <NUM_LIT> ; assert ( ( NumEltsPer128BitChunk % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != NumElts ; j += NumEltsPer128BitChunk ) { for ( unsigned i = <NUM_LIT> ; i != NumEltsPer128BitChunk ; ++ i ) { int LIdx = LMask [ i + j ] , RIdx = RMask [ i + j ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; if ( ! ( ( RIdx & <NUM_LIT> ) == <NUM_LIT> && ( LIdx + <NUM_LIT> ) == RIdx ) && ! ( ( LIdx & <NUM_LIT> ) == <NUM_LIT> && ( RIdx + <NUM_LIT> ) == LIdx && IsCommutative ) ) return false ; int Base = LIdx & ~ <NUM_LIT> ; int Index = ( ( Base % NumEltsPer128BitChunk ) / <NUM_LIT> ) + ( ( Base % NumElts ) & ~ ( NumEltsPer128BitChunk - <NUM_LIT> ) ) ; if ( ( B && Base >= ( int ) NumElts ) || ( ! B && i >= NumEltsPer64BitChunk ) ) Index += NumEltsPer64BitChunk ; PostShuffleMask [ i + j ] = Index ; } } SDValue NewLHS = A . getNode ( ) ? A : B ; SDValue NewRHS = B . getNode ( ) ? B : A ; bool IsIdentityPostShuffle = isSequentialOrUndefInRange ( PostShuffleMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ; if ( IsIdentityPostShuffle ) PostShuffleMask . clear ( ) ; if ( ! IsIdentityPostShuffle && ! Subtarget . hasAVX2 ( ) && VT . isFloatingPoint ( ) && isMultiLaneShuffleMask ( <NUM_LIT> , VT . getScalarSizeInBits ( ) , PostShuffleMask ) ) return false ; if ( ! shouldUseHorizontalOp ( NewLHS == NewRHS && ( NumShuffles < <NUM_LIT> || ! IsIdentityPostShuffle ) , DAG , Subtarget ) ) return false ; LHS = DAG . getBitcast ( VT ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI . getDesc ( ) . TSFlags ) ; if ( FMA3Group ) return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , FMA3Group -> isIntrinsic ( ) ) ; if ( <STR_LIT> ( Desc . TSFlags ) ) { unsigned CommutableOpIdx1 = Desc . getNumDefs ( ) + <NUM_LIT> ; unsigned CommutableOpIdx2 = Desc . getNumDefs ( ) + <NUM_LIT> ; if ( ( MI . getDesc ( ) . getOperandConstraint ( Desc . getNumDefs ( ) , MCOI :: TIED_TO ) != - <NUM_LIT> ) ) { if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } else { -- CommutableOpIdx1 ; } } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , - <STR_LIT> , <NUM_LIT> , false ) { RegSpillOffsets . grow ( <STR_LIT>


<s> Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) { Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> return getSTI ( ) . getFeatureBits (


<s> if ( INSN_CODE ( insn ) < <NUM_LIT> ) return ; byte_len = ix86_min_insn_size ( insn ) ; window_list = dispatch_window_list ; next_list = window_list -> next ; path = get_insn_path ( insn ) ; insn_group = get_insn_group ( insn ) ; if ( next_list ) window_list = dispatch_window_list -> next ; if ( path == path_single ) insn_num_uops = <NUM_LIT> ; else if ( path == path_double ) insn_num_uops = <NUM_LIT> ; else insn_num_uops = ( int ) path ; num_insn = window_list -> num_insn ; num_uops = window_list -> num_uops ; window_num = window_list -> window_num ; insn_fits = fits_dispatch_window ( insn ) ; if ( num_insn >= MAX_INSN || num_uops + insn_num_uops > MAX_INSN || ! ( insn_fits ) ) { window_num = ~ window_num & <NUM_LIT> ; window_list = allocate_next_window ( window_num ) ; } if ( window_num == <NUM_LIT> ) { add_insn_window ( insn , window_list , insn_num_uops ) ; if ( window_list -> num_insn >= MAX_INSN && insn_group == disp_branch ) { process_end_window ( ) ; return ; } } else if ( window_num == <NUM_LIT> ) { window0_list = window_list -> prev ; sum = window0_list -> window_size +


<s> vmls_n_f32 ( float32x2_t a , float32x2_t b , float32_t c ) { float32x2_t result ; float32x2_t t1 ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> void addVecListTwoDOperands ( MCInst & Inst


<s> if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( ) ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs


<s> assert ( ! LHS . getValueType ( ) . isFloatingPoint ( ) && <STR_LIT> ) ; <STR_LIT> TCC = <STR_LIT> ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : TCC = <STR_LIT> ; if ( LHS . getOpcode ( ) == <STR_LIT> ) std :: swap ( LHS , RHS ) ; break ; case <STR_LIT> : TCC = <STR_LIT> ; if ( LHS . getOpcode ( ) == <STR_LIT> ) std :: swap ( LHS , RHS ) ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode


<s> unsigned int t ; t = ( state -> last_set [ regno ] . time + insn_latency ( state -> last_set [ regno ] . insn , insn ) ) ; while ( state -> time < t ) mips_sim_next_cycle ( state


<s> if ( <STR_LIT> ( V2 ) || WillBeConstantPoolLoad ( V2 ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ]


<s> } MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; StringRef Name = Parser . getTok ( ) . getString ( ) ; if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSGD ; else if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSLDM ; else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = Parser . getTok ( ) . getString ( ) ; Sym = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( Identifier ) , Kind , Ctx ) ; Parser . Lex ( )


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( ( Imm & <NUM_LIT> ) ) ; Imm >>= <NUM_LIT> ; } ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back (


<s> return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> ,


<s> return ! ( TARGET_HARD_FLOAT && mode1 != mode2 && ( mode1 == DFmode


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT>


<s> if ( island . size ( ) > stubGroupSize ( ) ) { error ( diag :: err_no_space_to_place_stubs ) << stubGroupSize ( ) ; return false ; } if ( island . numOfStubs ( ) == <NUM_LIT> ) { continue ; } Fragment * exit = & * island . end ( ) ; if ( exit == & * island . begin ( ) -> getParent ( ) -> end ( ) ) { continue ; } if ( ( island . offset ( ) + island . size ( ) ) > exit -> getOffset ( ) ) { if ( invalid_frags . empty ( ) || ( invalid_frags . back ( ) -> getParent ( ) != island . getParent ( ) ) ) { invalid_frags . push_back ( exit ) ; pFinished = false ; } continue ; } } for ( auto it = invalid_frags . begin ( ) , ie = invalid_frags . end ( ) ; it != ie ; ++ it ) { Fragment * invalid = * it ; while ( invalid != NULL ) { invalid -> setOffset ( invalid -> getPrevNode ( ) -> getOffset ( ) + invalid -> getPrevNode


<s> RequiredAligment = Align ( <NUM_LIT> ) ; unsigned NumBits = LoadedType . getSizeInBits ( ) ; return NumBits == <NUM_LIT> || NumBits


<s> static const unsigned IntRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned F32Regs [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = <NUM_LIT> ; unsigned UnallocIntReg = State . getFirstUnallocated ( IntRegs , IntRegsSize ) ; bool IntRegUsed = ( IntRegs [ UnallocIntReg ] != ( unsigned ( <STR_LIT> ) ) ) ; if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign ::


<s> return parseMSARegs ( Operands , ( int )


<s> struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem ,


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; <STR_LIT> ShiftOpc = <STR_LIT> ( OffImm ) ; if ( ShiftOpc == <STR_LIT>


<s> if ( Opt == <STR_LIT> ) { ArchRegNames = true ; return true ; } if ( Opt == <STR_LIT> ) { DebugFlag = true ; return true ; } if ( Opt == <STR_LIT> ) { ABIRegNames =


<s> SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] )


<s> CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) loongarch_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set (


<s> if ( TARGET_SVE2 ) current_tune . extra_tuning_flags &=


<s> const struct processor * arch ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == <NUM_LIT> ) { uint64_t isa_temp = arch -> flags ; if ( ext != NULL


<s> if ( ! isa < Constant > ( RHS ) || ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLT ; break ; case CmpInst :: ICMP_SGT : case CmpInst :: ICMP_SLE : if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != APInt ( BW , - <NUM_LIT> , true ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLE ; break ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; if ( BW == <NUM_LIT> && ! Is64Bit ) SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , <STR_LIT> ) ; if ( ( BW < <NUM_LIT> ) && ! IsBitTest ) SrcReg = emitIntExt ( VT , SrcReg , <STR_LIT> , true ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,

TII . get ( Opc ) ) . addReg ( SrcReg ) ;


<s> return ( uint32_t ) __builtin_neon_vget_laneuv2si ( ( int32x2_t


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>AddressingMode & AM , EVT VT , SDValue & Base

, SDValue & Disp , SDValue & Index ) const {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDNode * Parent , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { <ISA_LIT>ISelAddressMode AM ; if ( Parent && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> &&

Parent -> getOpcode ( ) != <STR_LIT> ) {


<s> if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold = <NUM_LIT> ; if ( Cost < <NUM_LIT> ) UP . Force =


<s> return __builtin_ia32_cvttsd2si64 ( ( __v2df


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) -


<s> CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT !=


<s> bool isTargetWindowsGNU ( ) const { return TargetTriple . isWindowsGNUEnvironment


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static const LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses


<s> if ( Is<ISA_LIT>64 ) { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } else { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } bool UseTraps = useTraps ( ) ; unsigned Opcode = Inst . getOpcode ( ) ; bool isDiv = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isRem = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( RtOp . isImm ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( ImmValue == <NUM_LIT> ) { if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( isRem && ( ImmValue == <NUM_LIT> || ( Signed && ( ImmValue == - <NUM_LIT> ) ) ) ) { TOut . emitRRR ( <STR_LIT> , RdReg , ZeroReg , ZeroReg , IDLoc , STI ) ; return false ; } else if ( isDiv && ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( isDiv && Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps


<s> mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM512 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_REL8 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_REL32 : case TYPE_REL64 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; default : break ; } if ( ! tryAddingSymbolicOperand ( immediate + pcrel , isBranch , insn . startLocation , insn . immediateOffset , insn . immediateSize , mcInst , Dis ) ) mcInst . addOperand ( MCOperand :: CreateImm ( immediate ) ) ; if ( type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || type == TYPE_MOFFS32 || type


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned long long __Y ) { return __builtin_ia32_bzhi_di ( __X ,


<s> if ( INTVAL ( todec ) != - size ) { warning ( <NUM_LIT> , <STR_LIT> ) ; emit_insn ( gen_trap ( ) ) ; return <NUM_LIT> ; } if ( crtl -> limit_stack ) { if ( REG_P ( stack_limit_rtx ) && REGNO ( stack_limit_rtx ) > <NUM_LIT> && REGNO ( stack_limit_rtx ) <= <NUM_LIT> ) { rtx_insn * insn = gen_add3_insn ( tmp_reg , stack_limit_rtx , GEN_INT ( size ) ) ; gcc_assert ( insn ) ; emit_insn ( insn ) ; emit_insn ( gen_cond_trap ( LTU , stack_reg , tmp_reg , const0_rtx ) ) ; } else if ( SYMBOL_REF_P ( stack_limit_rtx ) && TARGET_32BIT && DEFAULT_ABI == ABI_V4 && ! flag_pic ) { rtx toload = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , stack_limit_rtx , GEN_INT ( size ) ) ) ; rtx r11_reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp_reg , r11_reg ) ; emit_insn ( gen_elf_high ( r11_reg , toload


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>InstructionSelector :: renderVFPF32Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> (


<s> if ( Is64BitMode || IsPIC ) { DispForReloc = & Op3 ; } else { DispVal = <NUM_LIT> ; } } else if ( Op3 . isJTI ( ) ) { if ( Is64BitMode || IsPIC ) { DispForReloc = & Op3 ; } else { DispVal = <NUM_LIT> ; } } else { DispVal = <NUM_LIT> ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( ( ! Is64BitMode || DispForReloc || BaseReg != <NUM_LIT> ) && IndexReg . getReg ( ) == <NUM_LIT> && ( BaseReg == <NUM_LIT> || <ISA_LIT>RegisterInfo :: get<ISA_LIT>RegNum ( BaseReg ) != N86 :: ESP ) ) { if ( BaseReg == <NUM_LIT> ) { ++ FinalSize ; FinalSize += getDisplacementFieldSize ( DispForReloc ) ; } else { unsigned BaseRegNo = <ISA_LIT>RegisterInfo :: get<ISA_LIT>RegNum ( BaseReg ) ; if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { ++ FinalSize ; } else { ++ FinalSize ; FinalSize += getDisplacementFieldSize ( DispForReloc ) ; } } } else { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; if ( BaseReg == <NUM_LIT> || DispForReloc ) { ++ FinalSize


<s> case llvm :: ELF :: R_<ISA_LIT>_JUMP24 : case llvm :: ELF :: R_<ISA_LIT>_PLT32 : { uint64_t dest = pTargetSymValue + pReloc . addend ( ) + <NUM_LIT> ; int64_t branch_offset = static_cast < int64_t > ( dest ) - pSource ; if ( ( branch_offset > <ISA_LIT>GNULDBackend :: <ISA_LIT>_MAX_FWD_BRANCH_OFFSET )

|| ( branch_offset < <ISA_LIT>GNULDBackend :: <ISA_LIT>_MAX_BWD_BRANCH_OFFSET ) ) {


<s> if ( IsSigned ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128ToCall ( Op ,


<s> if ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ) return DAG . expandVAArg ( Op . getNode ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode


<s> if ( ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) ) return SDValue ( ) ; if ( ! isNullConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! isNullConstant ( IfTrue . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! isOneConstant ( IfFalse . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return tryMatchAcrossLaneShuffleForReduction ( N , SetCC , Op


<s> poly_int64 size = - <NUM_LIT> ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) size = int_size_in_bytes ( type ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode )

== MODE_VECTOR_FLOAT ) size = GET_MODE_SIZE ( mode ) ;


<s> __builtin_neon_vst1_lanev2di ( ( __builtin_neon_di * ) __a ,


<s> if ( auto C = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return C ->

getSExtValue ( ) < <NUM_LIT> && C -> getSExtValue ( ) >= - <NUM_LIT> ;


<s> TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Lex ( ) ; MCSymbol * Alias = getContext ( ) . GetOrCreateSymbol ( Name ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Value ) ) { MCSymbol * Sym = getContext ( ) . LookupSymbol ( SRE -> getSymbol ( ) . getName ( ) ) ; if ( ! Sym -> isDefined ( ) ) { getStreamer ( ) . EmitSymbolAttribute ( Sym , MCSA_Global ) ; getStreamer ( ) . EmitAssignment ( Alias , Value ) ; return false ; } const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) ->


<s> unsigned <ISA_LIT>16InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned & NewImm ) const { RegScavenger rs ; int32_t lo = Imm & <NUM_LIT> ; int32_t hi = ( ( Imm >> <NUM_LIT> ) + ( lo >> <NUM_LIT> ) ) & <NUM_LIT> ; NewImm = lo ; unsigned Reg = <NUM_LIT> ; unsigned SpReg = <NUM_LIT> ; rs . enterBasicBlock ( & MBB ) ; rs . forward ( II ) ; unsigned FirstRegSaved = <NUM_LIT> , SecondRegSaved = <NUM_LIT> ; unsigned FirstRegSavedTo = <NUM_LIT> , SecondRegSavedTo = <NUM_LIT> ; Reg = rs . FindUnusedReg ( & <STR_LIT> ) ; if ( Reg == <NUM_LIT> ) { FirstRegSaved = Reg = <STR_LIT> ; FirstRegSavedTo = <STR_LIT> ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } else rs . setUsed ( Reg ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( hi ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) ; if ( FrameReg == <STR_LIT> ) { SpReg = rs . FindUnusedReg ( & <STR_LIT> ) ; if ( SpReg == <NUM_LIT> ) { if ( Reg != <STR_LIT> ) { SecondRegSaved = SpReg = <STR_LIT> ; SecondRegSavedTo = <STR_LIT> ; } else { SecondRegSaved = SpReg = <STR_LIT> ; SecondRegSavedTo = <STR_LIT> ; } copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ; } else rs . setUsed ( SpReg ) ; copyPhysReg ( MBB , II , DL , SpReg , <STR_LIT> , false ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( SpReg ) . addReg ( Reg ) ; } else BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; if ( FirstRegSaved || SecondRegSaved


<s> ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; return ret


<s> inline static bool isMImmVal ( uint64_t Val ) { if ( Val == <NUM_LIT> ) { return true ; } if ( isMask_64 ( Val ) ) { return true


<s> inline int vec_all_le ( vector float a1 , vector


<s> if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( TRI -> hasBasePointer ( DAG . getMachineFunction ( ) ) && TRI -> getBaseRegister ( ) == <STR_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType


<s> return llvm :: createMCRelocationInfo (


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( )


<s> OperandMatchResultTy parsePCRelTLS16 ( OperandVector & Operands ) { return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> <<


<s> bool SVEIntrinsicOpts :: optimizeFunctions ( SmallSetVector < Function * , <NUM_LIT> > & Functions ) { bool Changed =


<s> <ISA_LIT>_MachoTargetObjectFile :: <ISA_LIT>_MachoTargetObjectFile ( ) : TargetLoweringObjectFileMachO ( ) { SupportGOTPCRelWithOffset =


<s> void <ISA_LIT>InstPrinter :: printAddrMode7Operand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64Target , create<ISA_LIT>64Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64elTarget ,


<s> rtx_insn * insn = insn_info -> insn ; operand_rr_info * dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; for ( i = <NUM_LIT> ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head


<s> const unsigned * Reg = <ISA_LIT>64IntRegs + <NUM_LIT> ; int FOOffset ; if ( IsRegLoc ) { Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; OutChains . push_back ( Store ) ; } return


<s> SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ; } SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , TLI . getPointerTy ( ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> )


<s> void <ISA_LIT>ConstantPoolValue :: dump ( ) const { errs ( ) << <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateImm ( getShifter (


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { <STR_LIT> Form ; <STR_LIT> DispRange ; SDValue Base , Disp , Index ; switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_Q : Form = <STR_LIT> ; DispRange = <STR_LIT> ; break ; case InlineAsm :: Constraint_R : Form = <STR_LIT> ; DispRange = <STR_LIT> ; break ; case InlineAsm :: Constraint_S : Form = <STR_LIT> ; DispRange = <STR_LIT> ; break ; case InlineAsm


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT != <STR_LIT> || Subtarget . hasP8Altivec ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant (


<s> static DecodeStatus DecodeAddSubERegInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned extend = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shift = extend & <NUM_LIT> ; if ( shift > <NUM_LIT> ) return Fail ; switch ( Inst . getOpcode ( ) ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn ,


<s> addOperands ( MIB , MOs ) ; unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . add ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; MIB . add ( MO ) ; } updateOperandRegConstraints ( MF , * NewMI , TII ) ; if ( MI . getPrototypeHash ( ) ) NewMI -> setPrototypeHash (


<s> compute_bb_for_insn ( ) ; if ( TARGET_SEH && current_function_has_exception_handlers ( ) ) ix86_seh_fixup_eh_fallthru ( ) ; if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_SSE2 ) ix86_split_stlf_stall_load ( ) ; if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS )


<s> ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC =


<s> static void nds32_option_override ( void ) { if ( TARGET_ISA_V2 ) { target_flags &= ~ MASK_V3PUSH ; } if ( TARGET_ISA_V3 ) { if ( nds32_arch_option == ARCH_V3J ) target_flags |= MASK_REDUCED_REGS ; } if ( TARGET_ISA_V3M ) { target_flags |= MASK_REDUCED_REGS ; target_flags &= ~ MASK_EXT_PERF ; target_flags &= ~ MASK_EXT_PERF2 ; target_flags &= ~ MASK_EXT_STRING ; if ( flag_pic ) error ( <STR_LIT> ) ; } if ( TARGET_REDUCED_REGS ) { int r ; for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = call_used_regs [ r ] = <NUM_LIT> ; for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = call_used_regs [ r ] = <NUM_LIT> ; } if ( TARGET_FORCE_FP_AS_GP ) fixed_regs [ FP_REGNUM ] = call_used_regs [ FP_REGNUM ] = <NUM_LIT> ; if ( ! TARGET_16_BIT ) { target_flags &= ~ MASK_V3PUSH ; } if ( TARGET_HARD_FLOAT && ! ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) ) { if ( nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F ) error ( <STR_LIT> <STR_LIT> ) ; else error ( <STR_LIT> <STR_LIT> ) ; } nds32_init_rtx_costs ( )


<s> return ( int8x8_t ) __builtin_neon_vbslv8qi ( ( int8x8_t


<s> gcc_assert ( fix -> forwards || fix -> backwards ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , GET_MODE_NAME ( mode ) , INSN_UID ( insn ) , ( unsigned long ) address , - <NUM_LIT> * ( long ) fix -> backwards , ( long ) fix -> forwards ) ; print_csky_value ( dump_file , fix -> value ) ; fprintf ( dump_file , <STR_LIT> )


<s> static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; bool HasAVX = Subtarget -> hasAVX ( ) ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue (


<s> } } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value = V ; else if ( V != Value ) usesOnlyOneValue = false ; } if ( ! Value . getNode ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( usesOnlyOneValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , & Ops [


<s> static InstrUID decode ( OpcodeType type , InstructionContext insnContext , uint8_t opcode , uint8_t modRM ) { const struct ModRMDecision * dec = <NUM_LIT> ; switch ( type ) { case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP8_MAP : dec = & XOP8_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP9_MAP : dec = & XOP9_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOPA_MAP : dec = & XOPA_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : debug ( <STR_LIT> ) ; return <NUM_LIT> ; case MODRM_ONEENTRY : return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITRM : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITREG : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT>


<s> case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; Result -> sgx_type = Op -> sgx_type ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , EFLAGS ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , EFLAGS . getValue ( <NUM_LIT> ) ) ; return SDValue


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX


<s> if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; HasVectorPackedDecimalEnhancement2 = false ; } return *


<s> void addCOP3AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getCOP3Reg


<s> EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VT , InFlag ) . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } return Chain


<s> if ( LI -> isAtomic ( ) ) return false ; const Value * SV = I -> getOperand ( <NUM_LIT> ) ; if ( TLI . supportSwiftError ( ) ) { if ( const Argument * Arg = dyn_cast < Argument > ( SV ) ) { if ( Arg -> hasSwiftErrorAttr ( ) ) return false ; } if ( const AllocaInst * Alloca = dyn_cast < AllocaInst > ( SV ) ) { if ( Alloca -> isSwiftError ( ) ) return false ; } } MVT VT ; if ( ! isTypeLegal ( LI -> getType ( ) , VT , true ) ) return false ; const Value * Ptr = LI -> getPointerOperand ( ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg = <NUM_LIT>


<s> if ( m -> fs . cfa_reg == stack_pointer_rtx ) { rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; m -> fs . cfa_offset -= UNITS_PER_WORD ; } if ( reg == hard_frame_pointer_rtx ) { m -> fs . fp_valid = false ; if ( m -> fs


<s> if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitCounts ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else


<s> OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq


<s> if ( crtl -> abi -> id ( ) != expr_callee_abi ( exp ) . id


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements


<s> MachineBasicBlock * tailMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB . getIterator ( ) ; MF . insert ( MBBIter , testMBB ) ; MF . insert ( MBBIter , tailMBB ) ; unsigned FinalStackPtr = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FinalStackPtr ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; { const unsigned Opc = getSUBriOpcode ( Uses64BitFramePtr , Offset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , FinalStackPtr ) . addReg ( FinalStackPtr ) . addImm ( Offset / StackProbeSize * StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } { const unsigned Opc = getSUBriOpcode ( Uses64BitFramePtr , StackProbeSize ) ; BuildMI ( testMBB , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } addRegOffset ( BuildMI ( testMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( StackPtr ) . addReg ( FinalStackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( testMBB ) . addImm ( <STR_LIT> ) . setMIFlag


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( )


<s> return ( int16x4_t ) __builtin_neon_vqrshlsv4hi ( __a ,


<s> bool Res ; if ( Info . IsFixed && ! UseVarArgsCCForFixed ) Res = AssignFn ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; else Res = AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; StackOffset = State . getNextStackOffset


<s> static inline <ISA_LIT>TargetStreamer :: SymbolIndex getTombstoneKey ( ) { return { nullptr ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_slli_epi64 ( __m128i __A , int __B ) { __v2du lshift ; __v2di result = { <NUM_LIT> , <NUM_LIT> } ; if ( __B >= <NUM_LIT> && __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) && __B < <NUM_LIT> ) lshift = ( __v2du ) vec_splat_s32 ( __B ) ; else lshift = ( __v2du ) vec_splats ( ( unsigned int ) __B ) ; result = vec_sl ( ( __v2di ) __A , lshift ) ; } return ( __m128i )


<s> return StringRef ( Tok . Data , Tok . Length