<s> const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( ST -> hasNEON ( )


<s> void <ISA_LIT>PassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization (


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> OS << <STR_LIT> ; } else if ( isAcceptableChar ( C ) ) { OS << C ; } else if ( C >= 'A' && C <= 'Z' ) { OS << '\'' << ( char ) (


<s> case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; unsigned dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( AtomicSize == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LoadMnemonic ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( StoreMnemonic ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB =


<s> mp -> value = fix -> value ; mp -> refcount = <NUM_LIT> ; mp -> min_address = - <NUM_LIT> ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_csky_constpool_label ( gen_rtx_CONST_INT ( VOIDmode , constpool_label_no ++ ) ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp =


<s> O << '#' << Scale * MI -> getOperand ( OpNum )


<s> TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; } for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>64Target } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEB ) ; for ( Target * T : { & The<ISA_LIT>elTarget , & The<ISA_LIT>64elTarget } ) TargetRegistry ::

RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEL ) ;


<s> MachineInstr * <ISA_LIT>OptimizeLEAPass :: replaceDebugValue ( MachineInstr & MI , unsigned VReg , int64_t AddrDispShift ) { DIExpression * Expr = const_cast < DIExpression * > ( MI . getDebugExpression ( ) ) ; if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable (


<s> } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB .


<s> WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ; auto it = CurFrame -> Instructions . begin


<s> if ( ! FuncInfo . StaticAllocaMap . count ( C ) ) return <NUM_LIT> ; assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg )


<s> int getReturnAddrSaveIndex ( ) const { return ReturnAddrSaveIndex


<s> } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ; if ( CmpOpTy != nullptr && CmpOpTy -> isFloatingPointTy ( ) ) Cost ++ ; return Cost ; } } else if ( ST -> hasVector ( ) ) { auto * SrcVecTy = cast < FixedVectorType > ( Src ) ; auto * DstVecTy = cast < FixedVectorType > ( Dst ) ; unsigned VF = SrcVecTy -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) , CostKind ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( SrcVecTy , false , NeedsExtracts ) ; TotCost += getScalarizationOverhead ( DstVecTy , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits ==


<s> if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( ( which == <NUM_LIT> && negated ) || ( which == <NUM_LIT> && ! negated ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcpy ( buf , <STR_LIT> ) ; if ( ( which == <NUM_LIT> && negated ) || ( which == <NUM_LIT> && ! negated ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( nullify && negated ) strcat ( buf , <STR_LIT> ) ; else if ( nullify && ! negated ) strcat ( buf , <STR_LIT> ) ; else if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } break ; default : gcc_unreachable ( )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ,

CodeGenOpt :: Level OL , bool isLittle ) :


<s> SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , St )


<s> unsigned FixupKind = Fixup . getKind ( ) ; if ( IsCrossSection ) { if ( FixupKind != FK_Data_4 && FixupKind != FK_Data_8 ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_ARM64_ADDR32 ; } FixupKind = FK_PCRel_4 ; } auto Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; const MCExpr * Expr = Fixup . getValue ( ) ; if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; switch ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_ABS : case <ISA_LIT>MCExpr :: VK_SECREL : break ; default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A64E -> getVariantKindName ( ) + <STR_LIT> ) ; return COFF :: IMAGE_REL_ARM64_ABSOLUTE ; } } switch ( FixupKind ) { default : { if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A64E -> getVariantKindName ( ) + <STR_LIT> ) ; } else { const MCFixupKindInfo & Info = MAB . getFixupKindInfo ( Fixup . getKind ( ) ) ; Ctx . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> ) + Info . Name + <STR_LIT> ) ; } return COFF :: IMAGE_REL_ARM64_ABSOLUTE ; } case FK_PCRel_4 : return COFF :: IMAGE_REL_ARM64_REL32 ; case FK_Data_4 : switch ( Modifier ) { default : return COFF :: IMAGE_REL_ARM64_ADDR32 ; case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_ARM64_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_ARM64_SECREL ; } case FK_Data_8 : return COFF :: IMAGE_REL_ARM64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_ARM64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_ARM64_SECREL ; case


<s> static uint64_t calculateMaxStackAlign ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; uint64_t MaxAlign = MFI -> getMaxAlignment ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; if ( ForceStackAlign ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( )


<s> bool <ISA_LIT>DAGToDAGISel :: tryReadRegister ( SDNode * N ) { const MDNodeSDNode * MD = dyn_cast < MDNodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const MDString * RegString = dyn_cast < MDString > ( MD -> getMD ( ) -> getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } auto TheReg = <STR_LIT> ( RegString -> getString ( ) ) ; if ( TheReg && TheReg -> Readable && TheReg -> haveFeatures ( Subtarget -> getFeatureBits ( ) ) ) Reg = TheReg -> Encoding ; else Reg = <STR_LIT> ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } if ( RegString -> getString ( ) == <STR_LIT>


<s> if ( cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) < <NUM_LIT> ) return false ; if ( ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> &&


<s> DiagnosticPredicate isUImmScaled ( ) const


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t ExtraSignBits = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t BitsOnLeft = Shift -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t Width = VT . getSizeInBits ( ) - ExtraSignBits ; uint64_t LSB = VT . getSizeInBits ( ) - Width -


<s> OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , WordSize ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) )


<s> BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex

) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> unsigned StackAlign = MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pdep_u64 ( unsigned long long __X , unsigned long long __Y ) { return __builtin_ia32_pdep_di ( __X ,


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> switch ( IID ) { default : break ; case <STR_LIT> : case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; break ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> ,


<s> SmallVector < SDValue , <NUM_LIT> > OpInputs ; if ( ! resolveTargetShuffleInputs ( Op , OpInputs , OpMask , DAG ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( SrcOps . begin ( ) , SrcOps . end ( ) ) ; auto AddOp = [ & Ops ] ( SDValue Input , int InsertionPoint ) -> int { SDValue InputBC = peekThroughBitcasts ( Input ) ; for ( int i = <NUM_LIT> , e = Ops . size ( ) ; i < e ; ++ i ) if ( InputBC == peekThroughBitcasts ( Ops [ i ] ) ) return i ; if ( InsertionPoint >= <NUM_LIT> ) { Ops [ InsertionPoint ] = Input ; return InsertionPoint ; } Ops . push_back ( Input ) ; return Ops . size ( ) - <NUM_LIT> ; } ; SmallVector < int , <NUM_LIT> > OpInputIdx ; for ( SDValue OpInput : OpInputs ) OpInputIdx . push_back ( AddOp ( OpInput , OpInputIdx . empty ( ) ? SrcOpIndex : - <NUM_LIT> ) ) ; assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpMask . size ( ) ) && <STR_LIT> ) ; unsigned RootMaskSizeLog2 = countTrailingZeros ( RootMask . size ( ) ) ; unsigned OpMaskSizeLog2 = countTrailingZeros ( OpMask . size ( ) ) ; unsigned MaskWidth = std :: max < unsigned > ( OpMask . size ( ) , RootMask . size ( ) ) ; unsigned RootRatio = std :: max < unsigned > ( <NUM_LIT> , OpMask . size ( ) >> RootMaskSizeLog2 ) ; unsigned OpRatio = std :: max < unsigned > ( <NUM_LIT> , RootMask . size ( ) >> OpMaskSizeLog2 ) ; assert ( ( RootRatio == <NUM_LIT> || OpRatio == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( MaskWidth ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootRatio ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpRatio ) && <STR_LIT> ) ; unsigned RootRatioLog2 = countTrailingZeros ( RootRatio ) ; unsigned OpRatioLog2 = countTrailingZeros ( OpRatio ) ; SmallVector < int , <NUM_LIT> > Mask ( MaskWidth , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { unsigned RootIdx = i >> RootRatioLog2 ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask [ i ] = RootMask


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) .

addReg ( <STR_LIT> ) . addImm ( NumBytes ) ;


<s> Value * <ISA_LIT>IREmitter :: visitMOVSD (


<s> if ( ! CE ) return true ; uint64_t Value = CE -> getValue ( ) ; return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT>


<s> if ( ! Subtarget -> hasVFP2 ( ) || Subtarget -> isFPOnlySP ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) ->


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister (


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm


<s> const MCSymbolRefExpr * A = Target . getSymA ( ) ; const MCSymbol * Sym = A ? & A -> getSymbol ( ) : nullptr ; const unsigned FixupKind = Fixup . getKind ( ) ; if ( FixupKind == FK_Data_4 || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) { if ( Sym ) { if ( Asm . isThumbFunc ( Sym ) ) Value |= <NUM_LIT> ; } } if ( IsResolved && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { assert ( Sym && <STR_LIT> ) ; if ( Sym -> isExternal ( ) || Value


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpScalarSize = Op . getScalarValueSizeInBits ( ) ; unsigned ShiftImm = N -> getConstantOperandVal ( <NUM_LIT> ) ; assert ( OpScalarSize > ShiftImm && <STR_LIT> ) ; APInt ShiftedOutBits = APInt :: getLowBitsSet ( OpScalarSize , ShiftImm ) ; APInt DemandedMask = ~ ShiftedOutBits ; if ( TLI . SimplifyDemandedBits ( Op , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue (


<s> if ( ! ImmInRange ( MI , Entry ) ) return false ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! IsSP ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI


<s> const MachineOperand & PMO = Loc -> getOperand ( <NUM_LIT> ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : <ISA_LIT>RegisterInfo :: getRegisterNumbering ( PReg ) ; for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isAM4 && RegNum > PRegNum ) || RegNum == PRegNum + <NUM_LIT> ) ) { Offset += Size ; PRegNum = RegNum ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch


<s> if ( ! Subtarget . usesFunctionDescriptors ( ) && ! Subtarget . isELFv2ABI ( ) && isBLACompatibleAddress ( Callee , DAG ) ) return false ; return true


<s> addr = SET_SRC ( addr ) ; } else { int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) { addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT>


<s> unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , <NUM_LIT> , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = <NUM_LIT> ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { llvm :: erase_if ( RepeatedSequenceLocs , CantGuaranteeValueAcrossCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs .


<s> return ( __m256h ) __builtin_ia32_vfmaddcph256_mask ( ( __v16hf ) __A , ( __v16hf ) __C , (


<s> case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : if ( TARGET_MMX_WITH_SSE && TARGET_SSE4_1 ) break ; wmode = V4HImode ; goto widen ; case E_V4QImode : if ( TARGET_SSE4_1 ) break ; wmode = V2HImode ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << <NUM_LIT> , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> <NUM_LIT> ) ; emit_move_insn ( target , gen_lowpart ( mode , x )


<s> r = sr -> curr . reg + decode_abreg ( abreg , <NUM_LIT> ) ; r -> where = UNW_WHERE_NONE ; r -> when = sr -> region_start + MIN ( ( int


<s> if ( ! VT . isVector ( ) ) return VT ; return <STR_LIT> ( VT . getVectorElementType


<s> if ( llvm :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = llvm :: next ( MBBI ) ; for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( * I == NextBB ) return true ; return false


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num , Reg . StartLoc , Reg


<s> static SDValue LowerSVEIntrinsicDUP ( SDNode * N , SelectionDAG & DAG ) { SDLoc dl ( N ) ; SDValue Scalar = N -> getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Scalar .


++ ) if ( save_reg_p ( first_reg ) ) break ;


<s> break ; case GT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; case GE : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; case LT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; case LE : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; case ORDERED : case UNORDERED : case UNGT : case UNLT : case UNEQ : case UNGE : case UNLE : case LTGT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_ARCH64 ) { if ( MEM_P ( x ) ) { tree expr = MEM_EXPR ( x ) ; if ( expr ) mark_addressable ( expr ) ; slot0 = x ; } else { slot0 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot0 , x ) ; } if ( MEM_P ( y ) ) { tree expr = MEM_EXPR ( y ) ; if ( expr ) mark_addressable ( expr ) ; slot1 = y ; } else { slot1 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot1 , y ) ; } libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , DImode , <NUM_LIT> , XEXP ( slot0 , <NUM_LIT> ) , Pmode , XEXP ( slot1 , <NUM_LIT> ) , Pmode ) ; mode = DImode ; } else { libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , SImode , <NUM_LIT> , x , TFmode , y , TFmode ) ; mode = SImode ; } result = gen_reg_rtx ( mode ) ; emit_move_insn ( result , hard_libcall_value ( mode , libfunc ) ) ; switch ( comparison )


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { int imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm > <NUM_LIT> ) return


<s> return __builtin_aarch64_usqaddv16qi_uus ( __a ,


<s> else if ( ( fnmask & RS6000_BTM_SPE ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) == ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) error ( <STR_LIT> <STR_LIT>


<s> CONST_SECTION_FUNCTION \ SDATA_SECTION_FUNCTION \ SBSS_SECTION_FUNCTION void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP ) ; \


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState


<s> return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info ,


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( TARGET_HITACHI ) return false ; if ( ! type ) return true ; return ! sh_attr_renesas_p (


__J , float __K , float __L , float __M , float __N , float __O , float __P ) {


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . hasVLX ( ) ) return <STR_LIT> ; DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . hasVLX ( ) ) return <STR_LIT> ; DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && GRRegClassContains ( SrcReg ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; return <STR_LIT> ; } if ( GRRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <NUM_LIT> ) ; return <STR_LIT> ; } return


<s> FunctionPass * llvm :: create<ISA_LIT>FixupLEAs ( ) { return new FixupLEAPass (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; EVT VT = N0 . getValueType ( ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && N1C && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> || ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { APInt Mask = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; APInt ShAmt = N1C -> getAPIntValue ( ) ; Mask = Mask . shl ( ShAmt ) ; if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N

) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ;


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x16_t ) __builtin_aarch64_tbx4v16qi ( ( int8x16_t ) r , __o , (


<s> RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> &&


, BUILT_IN_NORMAL , NULL , fnattr_ms ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; if ( FlagSfiLoad ) Modified |= SandboxLoadsInBlock ( MBB ) ; if ( FlagSfiStore ) Modified |= SandboxStoresInBlock ( MBB ) ; if ( FlagSfiBranch ) Modified |= SandboxBranchesInBlock ( MBB


<s> bool hasSVE2BitPerm ( ) const { return HasSVE2BitPerm


<s> for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) if


<s> void or1k_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , label ; machine_mode mode ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; val = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , val ) ) val =


<s> OS << StringRef ( getRegisterName ( RegNo ) ) . lower


<s> } DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) .

addImm ( isSub ? - ThisVal : ThisVal ) ;


<s> int byte_size ; int args_byte_size ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = <NUM_LIT> ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) cum -> int_regs = cum -> words ; else if ( cum -> prototype


<s> Mask . clear ( ) ; Ops . clear ( ) ; MVT VT = N . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumSizeInBits = VT . getSizeInBits ( ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && ( NumSizeInBits % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = N . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; bool IsAndN = ( <STR_LIT> == Opcode ) ; uint64_t ZeroMask = IsAndN ? <NUM_LIT> : <NUM_LIT> ; if ( ! getTargetConstantBitsFromNode ( IsAndN ? N0 : N1 , <NUM_LIT> , UndefElts , EltBits ) ) return false ; for ( int i = <NUM_LIT> , e = ( int ) EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) { Mask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t ByteBits = EltBits [ i ] . getZExtValue ( ) ; if ( ByteBits != <NUM_LIT> && ByteBits != <NUM_LIT> ) return false ; Mask . push_back ( ByteBits == ZeroMask ? SM_SentinelZero : i ) ; } Ops . push_back ( IsAndN ? N1 : N0 ) ; return true ; } case <STR_LIT> : { SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue SrcExtract ; if ( ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) || ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) || ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) { SrcExtract = N0 ; } if ( ! SrcExtract || ! isa < ConstantSDNode > ( SrcExtract . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue SrcVec = SrcExtract . getOperand ( <NUM_LIT> ) ; EVT SrcVT = SrcVec . getValueType ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; unsigned NumZeros = ( NumBitsPerElt / SrcVT . getScalarSizeInBits ( ) ) - <NUM_LIT> ; unsigned SrcIdx = SrcExtract . getConstantOperandVal ( <NUM_LIT> ) ; if ( NumSrcElts <= SrcIdx ) return false ; Ops . push_back ( SrcVec ) ; Mask . push_back ( SrcIdx ) ; Mask . append ( NumZeros , SM_SentinelZero


<s> for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ;


<s> static int loongarch_sign_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return <NUM_LIT> ; return COSTS_N_INSNS (


<s> return isUImm < <NUM_LIT> , <NUM_LIT> >


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! isReservedReg ( MF , PhysReg


<s> assert ( RegOp . isReg ( ) && <STR_LIT> ) ; OS << <STR_LIT> ; if ( LPAC :: isPreOp ( AluCode )


<s> static rtx ix86_builtin_setjmp_frame_value (


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; return nullptr


<s> static void AnalyzeRetResult ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Outs ) { State . AnalyzeReturn (


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; MCSymbol * Label = S . emitCFILabel ( ) ; CurFrame -> PrologEnd = Label ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ; auto it = CurFrame -> Instructions .


<s> FunctionPass * create<ISA_LIT>NaClRewritePass


<s> if ( ! ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) { return Relocator :: BadReloc ; } <ISA_LIT>_32GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * rsym ) ; assert ( got_entry !=


<s> return ; } } break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex (

FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( Vector && ! ST -> hasAltivec ( ) ) return <NUM_LIT> ; return ST -> hasVSX ( )


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: lowerTLSCall ( SDValue Op , SDLoc dl , SelectionDAG & DAG ) const { Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering ::


<s> if ( TARGET_LS64 ) aarch64_init_ls64_builtins (


<s> case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstLoad ( Opc , ResultReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; int64_t Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI )


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef Triple ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return


<s> static void Passv64i1ArgInRegs ( const SDLoc & Dl , SelectionDAG & DAG , SDValue & Arg , SmallVectorImpl < std :: pair < unsigned , SDValue >> & RegsToPass , CCValAssign & VA , CCValAssign & NextVA , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; assert ( Subtarget . is32Bit ( ) && <STR_LIT> ) ; assert ( Arg . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo ,


<s> BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ;


<s> static DecodeStatus DecodeGPRMM16MovePRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; } break ; } } } return


<s> uint32_t Bits ; return A64Imms :: isLogicalImm ( RegWidth , CE -> getValue ( ) ,


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) || CPU == <STR_LIT> ) { if ( TargetTriple . getArch ( ) == Triple :: ppc64le ) CPUName = <STR_LIT> ; else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment


<s> Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! IsPairedInsn && ( UpdateOffset > <NUM_LIT> || UpdateOffset < - <NUM_LIT> ) ) break ; if ( IsPairedInsn ) { int Scale = getMemScale ( MemMI ) ; if ( UpdateOffset % Scale != <NUM_LIT> ) break ; int ScaledOffset = UpdateOffset / Scale ; if ( ScaledOffset > <NUM_LIT> || ScaledOffset <


<s> case Triple :: COFF : return LowerGlobalAddressWindows ( Op , DAG ) ; case Triple :: ELF : return LowerGlobalAddressELF ( Op , DAG


<s> return __builtin_arm_crc32cb ( __a ,


<s> if ( CONST_DOUBLE_P ( x ) ) x = gen_lowpart ( int_mode_for_mode ( GET_MODE ( x ) ) . require ( ) , x ) ; return


<s> Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( ! hasThumb ( ) ) { Error ( L


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; return ret


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) && N . getOpcode ( ) == <STR_LIT> && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) { if ( AM . hasBaseOrIndexReg ( ) ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( G -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast


<s> lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 <<= <NUM_LIT> - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - shift ) ; out [ <NUM_LIT> ] = GEN_INT ( m1 ) ; out [ <NUM_LIT> ] = GEN_INT ( shift ) ; out [ <NUM_LIT> ] = GEN_INT ( m2 ) ; ( void ) in ; ( void


<s> printMemOperand ( const MCInst * MI , int opNum ,


<s> bool <ISA_LIT>TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits (


<s> unsigned <ISA_LIT>TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , VT


<s> static __inline void _mm_free ( void * __ptr


<s> OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const MCExpr * OffsetExpr ; int64_t OffsetVal ; SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) || ! OffsetExpr -> evaluateAsAbsolute ( OffsetVal ) ) { reportParseError ( ExprLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Save = OffsetVal ; SaveIsReg = false ; } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned CC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent


<s> return Subtarget . isCallingConvWin64


<s> static inline unsigned getT2SOImmValRotate ( unsigned V ) { if ( ( V & ~ <NUM_LIT> )


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize32 : ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeNVLaneOpIndex ( insn , esize ) ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL ,


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= ( Subtarget -> isMClass ( )


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; unsigned ID = StringSwitch < unsigned > ( Arch ) . Case ( NAME , <STR_LIT> ) . Case ( NAME , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ID == <STR_LIT> ) { Error ( ArchLoc , <STR_LIT> + Arch +


<s> if ( TARGET_32BIT ) return ( TARGET_THUMB2 && ! speed_p ) ? <NUM_LIT> : <NUM_LIT> ; else return ( optimize > <NUM_LIT> ) ?


<s> Register ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT == <STR_LIT> ) { Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , Result32 , true , <STR_LIT> ) ; } else if ( DstVT


<s> if ( TII -> isUnscaledLdSt ( MI ) ) ++ NumUnscaledPairCreated ; auto Prev = std :: prev ( MBBI ) ; MBBI = mergePairedInsns ( MBBI , Paired , Flags ) ; for ( auto I = std :: next ( Prev ) ; I != MBBI ; I ++ ) updateDefinedRegisters ( * I , DefinedInBB , TRI ) ; return true ; } return false


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( Inst -> hasAtomicLoad ( ) && isAcquireOrStronger ( Ord ) ) { if ( isa < LoadInst > ( Inst ) && Subtarget . is<ISA_LIT>64 ( ) ) return Builder . CreateCall ( <STR_LIT> ( Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) , <STR_LIT> , { Inst -> getType ( ) } ) , { Inst } ) ; return callIntrinsic ( Builder , <STR_LIT> ) ; } return nullptr


<s> CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ; ReplaceUses ( N , M


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = <NUM_LIT> ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>Lowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return


<s> } else { MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) )


<s> const CCState & getCCInfo ( ) const { return CCInfo


<s> Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , PtrTy , TlsGetAddr , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT ,


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target


<s> nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ] . total_n_vectors = <NUM_LIT> ; strcpy ( nds32_isr_vectors [ i ] . nmi_name ,


<s> for ( const char * C = S . begin ( ) ; C != S . end ( ) ; ++ C ) { GlobalHeap . push_back ( *


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , const Triple

& TT , StringRef CPU , const MCTargetOptions & Options ) {


<s> static __inline __m64 _mm_alignr1_si64 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_walignr1 ( ( __v8qi ) a , (


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is256BitVector ( ) ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is512BitVector ( ) ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } return


<s> unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( FlagsReg ) restoreEFLAGS ( MBB , InsertPt , Loc , FlagsReg ) ; return


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } } return TTI :: TCC_Basic ; } assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; auto * VTy = dyn_cast < FixedVectorType > ( Src ) ; if ( ! VTy || ! LT . second . isVector ( ) ) return LT . first * <NUM_LIT> ; bool IsLoad = Opcode == Instruction :: Load ; Type * EltTy = VTy -> getElementType ( ) ; const int EltTyBits = DL . getTypeSizeInBits ( EltTy ) ; InstructionCost Cost = <NUM_LIT> ; const unsigned SrcNumElt = VTy -> getNumElements ( ) ; int NumEltRemaining = SrcNumElt ; auto NumEltDone = [ & ] ( ) { return SrcNumElt - NumEltRemaining ; } ; const int MaxLegalOpSizeBytes = divideCeil ( LT . second . getSizeInBits ( ) , <NUM_LIT> ) ; const unsigned XMMBits = <NUM_LIT> ; if ( XMMBits % EltTyBits != <NUM_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; const int NumEltPerXMM = XMMBits / EltTyBits ; auto * XMMVecTy = FixedVectorType :: get ( EltTy , NumEltPerXMM ) ; for ( int CurrOpSizeBytes = MaxLegalOpSizeBytes , SubVecEltsLeft = <NUM_LIT> ; NumEltRemaining > <NUM_LIT> ; CurrOpSizeBytes /= <NUM_LIT> ) { if ( ( <NUM_LIT> * CurrOpSizeBytes ) % EltTyBits != <NUM_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; int CurrNumEltPerOp = ( <NUM_LIT> * CurrOpSizeBytes ) / EltTyBits ; assert ( CurrOpSizeBytes > <NUM_LIT> && CurrNumEltPerOp > <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( ( NumEltRemaining * EltTyBits ) < ( <NUM_LIT> * <NUM_LIT> * CurrOpSizeBytes ) ) || ( CurrOpSizeBytes == MaxLegalOpSizeBytes ) ) && <STR_LIT> <STR_LIT> ) ; auto * CurrVecTy = CurrNumEltPerOp > NumEltPerXMM ? FixedVectorType :: get ( EltTy , CurrNumEltPerOp ) : XMMVecTy ; assert ( CurrVecTy -> getNumElements ( ) %


<s> FIN = DAG . getMemBasePlusOffset ( FIN , <NUM_LIT> , DL ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> , DL ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo ->


<s> static bool sh_cannot_modify_jumps_p ( void


<s> static unsigned getShuffleVPERMILPImmediate ( ShuffleVectorSDNode * SVOp ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned LaneSize = NumElts / NumLanes ; unsigned Shift = ( LaneSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int MaskElt = SVOp -> getMaskElt ( i ) ; if ( MaskElt < <NUM_LIT> ) continue ; MaskElt %= LaneSize ; unsigned Shamt = i ; if ( NumElts == <NUM_LIT> ) Shamt


<s> } case SYMBOL_PCREL : reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_GOT_DISP : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_TLS_IE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_TLS_LE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_TLSGD : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; case SYMBOL_TLSLDM : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; default : gcc_unreachable ( )


<s> unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; VLdDup = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , OpsB ) ; } else { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; SDValue SuperReg = SDValue ( VLdA , <NUM_LIT> ) ; Chain = SDValue (


<s> if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) ==


<s> NaCl<ISA_LIT>_32AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>_32AsmBackend ( T , OSABI , CPU ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( <STR_LIT> , CPU , <STR_LIT> ) ) { State . PrefixSaved


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym


<s> static DecodeStatus DecodeThumbBLXOffset ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand

:: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> return Op . getOpcode ( ) == unsigned ( BinOp ) ; } ) ) return SDValue ( ) ; unsigned CandidateBinOp = Op . getOpcode ( ) ; for ( unsigned i = <NUM_LIT> ; i < Stages ; ++ i ) { if ( Op . getOpcode ( ) != CandidateBinOp ) return SDValue ( ) ; ShuffleVectorSDNode * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( Shuffle ) { Op = Op . getOperand ( <NUM_LIT> ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( ! Shuffle || Shuffle -> getOperand ( <NUM_LIT> ) != Op ) return SDValue ( ) ; for ( int Index = <NUM_LIT> , MaskEnd = <NUM_LIT> << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt (

Index ) != MaskEnd + Index ) return SDValue ( ) ;


<s> SDValue FPCR_64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; SDValue FPCR_32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPCR_64 ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPCR_32 , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl ,


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = <NUM_LIT> ; char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( SPARC_STACK_BIAS ) ; output_asm_insn ( <STR_LIT> , xops


<s> auto insnCtx = InstructionContext ( x86DisassemblerContexts [ attrMask ] ) ; const ContextDecision * decision ; switch ( insn -> opcodeType ) { case ONEBYTE : decision = & ONEBYTE_SYM ; break ; case TWOBYTE : decision = & TWOBYTE_SYM ; break ; case THREEBYTE_38 : decision = & THREEBYTE38_SYM ; break ; case THREEBYTE_3A : decision = & THREEBYTE3A_SYM ; break ; case XOP8_MAP : decision =


<s> <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back


<s> if ( SDValue Select = pushAddIntoCmovOfConsts ( N , DAG ) ) return Select ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_3 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op1 . getOperand (


<s> void <ISA_LIT>InstPrinter :: printMemRrOperand ( const MCInst * MI , int OpNo , raw_ostream & OS , const char * ) { const MCOperand & RegOp = MI -> getOperand ( OpNo ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand & AluOp = MI -> getOperand


<s> assert ( getParser ( ) . getStreamer (

) . getTargetStreamer ( ) && <STR_LIT> ) ;


<s> EVT SrcVT = SrcVal . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; const unsigned DstSz = Op . getValueType ( ) . getSizeInBits ( ) ; const unsigned SrcSz = SrcVT . getSizeInBits ( ) ; ( void ) DstSz ; assert ( DstSz < SrcSz && SrcSz <= <NUM_LIT> && DstSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) &&


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return &


<s> if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) ,


<s> if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , <NUM_LIT> ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , <NUM_LIT> ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , <NUM_LIT> ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ <NUM_LIT> ] ) emit_move_insn (


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ;


<s> static bool rs6000_gen_pic_addr_diff_vec


<s> if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; unsigned Opc = invertFPCondCodeUser ( CC ) ? <STR_LIT> : <STR_LIT> ; SDValue BrCode = DAG . getConstant ( Opc , <STR_LIT> ) ; SDValue FCC0 = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( )

, Chain , BrCode , FCC0 , Dest , CondRes ) ;


<s> if ( N1 . hasOneUse ( ) ) { DCI . CombineTo ( N1 . getNode ( ) , AndOp ) ; return SDValue ( N , <NUM_LIT> ) ; } else { SDValue Replace = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AndOp ) ; DCI . AddToWorklist ( Replace . getNode


<s> EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Subtarget . hasAVX ( ) && TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( SrcVT ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; if ( SDValue R = combineConcatVectorOps ( SDLoc ( N ) , VT . getSimpleVT ( ) , Ops , DAG , DCI , Subtarget


<s> void mmix_asm_output_aligned_local ( FILE * stream , const char * name , int size , int align ) { data_section (


<s> case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case FK_Data_4 : return <NUM_LIT> ; case FK_PCRel_8 : case


<s> HOST_WIDE_INT low = ( ( value & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; HOST_WIDE_INT high = value >> <NUM_LIT> ; if ( high == <NUM_LIT> || high == - <NUM_LIT> ) return <NUM_LIT> ; high >>= <NUM_LIT> ; if ( low == <NUM_LIT> ) return num_insns_constant_gpr ( high )


<s> SmallVectorImpl < MachineInstr * > & Insts = Block . getInsts ( ) ; for ( unsigned i = <NUM_LIT> ; i < Insts . size ( ) ; ++ i ) { MachineInstr * Next = Insts [ i ] ; if ( isVectorPredicate ( Next


<s> tree uti_ftype_udi_udi = build_function_type_list ( unsigned_intTI_type_node , unsigned_intDI_type_node , unsigned_intDI_type_node , NULL_TREE ) ; ARM_BUILTIN_CRYPTO_ ## U <STR_LIT> # L R ## _ftype_ ## A R ## _ftype_ ## A1 ## _ ## A2 R ## _ftype_ ## A1 ## _ ## A2 ## _ ## A3 arm_builtin_decls [ C ( U ) ] \ = add_builtin_function ( N ( L ) , FT1 ( R , A ) , \ C ( U ) , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ C ( U ) ] \ = add_builtin_function ( N ( L ) , FT2 ( R , A1 , A2


<s> if ( env && * env == '1' ) add_mingw


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CM , OL ) , isLittle ( isLittle ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( TT , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) { Subtarget = & DefaultSubtarget ; initAsmInfo (


<s> static DecodeStatus DecodeGPRnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) S =


<s> SmallPtrSet < Instruction * , <NUM_LIT> > Sinks ; WorkList . insert ( V ) ; SmallPtrSet < Value * , <NUM_LIT> > CurrentVisited ; CurrentVisited . clear ( ) ; auto AddLegalInst = [ & ] ( Value * V ) { if ( CurrentVisited . count ( V ) ) return true ; if ( isa < GetElementPtrInst > ( V ) ) return true ; if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) return false ; CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Op1 || Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitDTPRel64Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveGpWord ( ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitGPRel32Value ( Value ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return


<s> FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value &


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { return GetRelocTypeInner ( Target , Fixup , IsPCRel , Ctx


<s> if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; return SYSmvalue | Mask <<


<s> unsigned Reg0 = ChangeReg0 ? Reg2 : MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI . getDebugLoc ( ) , MI . getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI . getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg1 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg2IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( ( ME + <NUM_LIT>


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdrand32_step ( unsigned int * __P ) { return __builtin_ia32_rdrand32_step ( __P )


<s> vrev64q_u32 ( uint32x4_t a ) { return __builtin_shuffle ( a , ( uint32x4_t ) { <NUM_LIT> ,


<s> else if ( auto * Load = dyn_cast < LoadInst > ( V ) ) { if ( ! isa < IntegerType > ( Load -> getType ( ) ) ) return false ; if ( Load -> hasOneUse ( ) && isa < ZExtInst > ( * Load -> use_begin (


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>3 (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( FirstMI == nullptr ) return true ; switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> enum machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( mode != SFmode && mode != DFmode ) return <NUM_LIT> ; if ( ! ( mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) ) ) return <NUM_LIT> ; if ( ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands

[ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ) return <NUM_LIT> ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return


<s> return false ; } else if ( gimple_code ( stmt ) == GIMPLE_CALL ) { tree fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl && fndecl_built_in_p ( fndecl , BUILT_IN_MD ) ) { enum rs6000_gen_builtins fcode = ( enum rs6000_gen_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; if ( bif_is_htm ( rs6000_builtin_info [ fcode ] ) ) { info |= RS6000_FN_TARGET_INFO_HTM ; return false ; } } } return true


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { d = decodeVFPRd ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , d ) ) ) ; m = decodeVFPRm ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , m ) ) ) ; } else { d = decodeVFPRd ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , d ) ) ) ; m = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , m ) ) ) ; } NumOpsAdded = <NUM_LIT>


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg =


<s> bool useReductionIntrinsic ( unsigned Opcode , Type * Ty , TTI


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> :


<s> EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> ) return false ; return TLI . isTypeLegal ( VT


<s> Op -> RegShiftedImm . SrcReg = SrcReg ; Op -> RegShiftedImm . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc


<s> MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB =


<s> vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpeq ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc ( ( vec_float4 )


<s> } x ; int cnt ; vec_uchar16 mask ; x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = ( <NUM_LIT> - x . i [ <NUM_LIT> ] ) << <NUM_LIT> ; x . v = vec_splat ( x .


<s> static DecodeStatus DecodeBranch26Target ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) ) ) ; return MCDisassembler :: Success


<s> return ( InstDesc . isConditionalBranch ( ) && ( AlignBranchType & <STR_LIT> ) ) || ( InstDesc . isUnconditionalBranch ( ) && ( AlignBranchType & <STR_LIT> ) ) || ( InstDesc . isCall ( ) && ( AlignBranchType & <STR_LIT> ) ) || ( InstDesc . isReturn ( ) &&

( AlignBranchType & <STR_LIT> ) ) || ( InstDesc . isIndirectBranch ( ) && ( AlignBranchType & <STR_LIT> ) ) ;


<s> return ( uint32x2_t ) __builtin_aarch64_umaxv2si ( ( int32x2_t ) __a , ( int32x2_t )


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_RegMask


<s> const MCExpr * Expr = NULL ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == MCFixupKind ( <STR_LIT> ) ) && StartsWithGlobalOffsetTable ( Expr ) ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; ImmOffset =


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool Res = false ; if ( EnableCompressedInst ) Res = compressInst ( CInst , Inst ,


<s> BitVector <ISA_LIT>BaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( STI . isTargetDarwin ( ) || hasFP (


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get


<s> case <STR_LIT> : if ( TLSBaseAddrReg ) I = ReplaceTLSBaseAddrCall ( * I , TLSBaseAddrReg ) ; else I = SetRegister ( * I , & TLSBaseAddrReg ) ; Changed = true ; break ; default : break ; } } for ( auto I = Node -> begin ( ) , E = Node -> end ( ) ; I != E ; ++ I ) { Changed |= VisitNode ( * I


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ? <STR_LIT> ( MI )


<s> bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; int Offset = MemOps [ SIndex ] . Offset ; int SOffset = Offset ; unsigned insertAfter = SIndex ; MachineBasicBlock :: iterator Loc = MemOps [ SIndex ] . MBBI ; DebugLoc dl = Loc -> getDebugLoc ( ) ; const MachineOperand & PMO = Loc -> getOperand ( <NUM_LIT> ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( PReg ) ; unsigned Count = <NUM_LIT> ; unsigned Limit = ~ <NUM_LIT> ; bool BaseKill = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) )

&& ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) {


<s> static unsigned getCMovFromCond ( <STR_LIT> CC , unsigned RegBytes , bool HasMemoryOperand ) { static const unsigned Opc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; assert ( CC < <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = HasMemoryOperand ? <NUM_LIT> + CC : CC ; switch ( RegBytes )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( ( ( char * ) p )


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; { auto Op = MI . getOpcode ( ) ; if ( Op == <STR_LIT> || Op == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; } if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; const MCInstrDesc & Desc = MI . getDesc


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value


<s> bool <ISA_LIT>TargetObjectFile :: IsConstantInSmallSection ( const DataLayout & DL , const Constant * CN , const


<s> unsigned Reg = DFPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg

( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVZIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> static __inline__ float __fnmsubs ( float x , float y , float z ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r