<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { switch ( cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : return GetNaClThreadPointer ( DAG , Op -> getDebugLoc ( ) ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true


<s> return __builtin_mve_vabdq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; unsigned NumArgs = Ins . size ( ) ; Function :: const_arg_iterator CurOrigArg = MF . getFunction ( ) -> arg_begin ( ) ; unsigned CurArgIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ValVT = Ins [ i ] . VT ; std :: advance ( CurOrigArg , Ins [ i ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ i ] . OrigArgIndex ; EVT ActualVT = getValueType ( CurOrigArg -> getType ( ) , true ) ; MVT ActualMVT = ActualVT . isSimple ( ) ? ActualVT . getSimpleVT ( ) : <STR_LIT> ; if ( ActualMVT == <STR_LIT> || ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; else if ( ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; CCAssignFn * AssignFn = CCAssignFnForCall ( CallConv , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , Ins [ i ] . Flags , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void ) Res ; } assert ( ArgLocs . size ( ) == Ins . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = &


<s> unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM -> getSubtargetImpl ( ) -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 (


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return false


<s> if ( NumNonZero > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue V ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool isNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( isNonZero ) { if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First =


<s> for ( unsigned Idx = <NUM_LIT> , e = Src . getNumOperands ( ) ; Idx < e ; ++ Idx ) { if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && SrcVT . isFloatingPoint ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == EVT ( SrcVT ) . changeVectorElementTypeToInteger ( ) ) Src = Src . getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; APInt


<s> if ( Scope . equals ( <STR_LIT> ) ) return false ; if ( Scope . equals ( <STR_LIT> ) ) return true ; assert ( Scope . equals ( <STR_LIT> ) && <STR_LIT> ) ; for ( const auto & Info : MF . getFrameInfo ( ) . getCalleeSavedInfo ( )

) if ( Info . getReg ( ) == <STR_LIT> ) return true ;


<s> if ( TARGET_IWMMXT ) { rtx_insn * insn ; int lrm_count = ( num_regs % <NUM_LIT> ) ? ( num_regs + <NUM_LIT> ) : ( num_regs + <NUM_LIT> ) ; for ( i = LAST_IWMMXT_REGNUM ; i >= FIRST_IWMMXT_REGNUM ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { rtx addr = gen_frame_mem ( V2SImode , plus_constant ( Pmode , hard_frame_pointer_rtx , - lrm_count * <NUM_LIT> ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( V2SImode , i ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( V2SImode , i ) , NULL_RTX ) ; lrm_count += <NUM_LIT> ; } } gcc_assert ( saved_regs_mask & ( <NUM_LIT> << IP_REGNUM ) ) ; saved_regs_mask &= ~ ( <NUM_LIT> << IP_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << SP_REGNUM ) ; if ( really_return && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> calls_eh_return ) saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; else saved_regs_mask &= ~ ( <NUM_LIT> << PC_REGNUM ) ; num_regs = bit_count ( saved_regs_mask ) ; if ( ( offsets -> outgoing_args != ( <NUM_LIT> + num_regs ) ) || cfun -> calls_alloca ) { rtx_insn * insn ; emit_insn ( gen_blockage ( ) ) ; insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - <NUM_LIT> * num_regs ) ) ) ; arm_add_cfa_adjust_cfa_note ( insn , - <NUM_LIT> * num_regs , stack_pointer_rtx , hard_frame_pointer_rtx ) ; } arm_emit_multi_reg_pop ( saved_regs_mask ) ; if ( IS_INTERRUPT ( func_type ) ) { rtx_insn * insn ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( SImode , IP_REGNUM ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode ,


<s> std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isOSWindows ( ) || ST . isTargetNaCl ( )


<s> case MachineOperand :: MO_Immediate : case MachineOperand :: MO_CImmediate : case MachineOperand :: MO_FPImmediate : return false ; case MachineOperand :: MO_MachineBasicBlock : return true ; case MachineOperand :: MO_FrameIndex : return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand ::


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( REAL_VALUES_EQUAL ( * r ,

values_fp [ i ] ) ) return strings_fp [ i ] ;


<s> unsigned getRelocationInfo ( ) const override


<s> gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( SUBREG_P ( mem ) ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P (


<s> SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > IndirectTargetMBBs ; for ( MachineBasicBlock & MBB : MF ) { auto MII = MBB . instr_rbegin ( ) ; while ( MII != MBB . instr_rend ( ) && MII -> isDebugInstr ( ) ) ++ MII ; if ( MII == MBB . instr_rend ( ) ) continue ; MachineInstr & TI = * MII ; if ( ! TI . isTerminator ( ) || ! TI . isBranch ( ) ) continue ; unsigned TargetReg ; switch ( TI . getOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : TargetReg = TI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( llvm :: any_of ( MBB . terminators ( ) , [ & ] ( MachineInstr & OtherTI ) { return ! OtherTI . isDebugInstr ( ) && & OtherTI != & TI ; } ) ) { LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> <STR_LIT> ; for ( MachineInstr & MI : MBB . terminators ( ) ) { MI . dump ( ) ; dbgs ( ) << '\n' ; } } ) ; report_fatal_error ( <STR_LIT> ) ; } TargetAddrSSA . AddAvailableValue ( & MBB , TargetReg ) ; IndirectTerminatedMBBs . insert ( & MBB ) ; for ( MachineBasicBlock * Succ : MBB . successors ( ) ) IndirectTargetMBBs . insert ( Succ ) ; } SmallVector < MachineInstr * , <NUM_LIT> > CMovs ; if ( IndirectTargetMBBs . empty ( ) ) return CMovs ; for ( MachineBasicBlock & MBB : MF ) { if ( ! IndirectTargetMBBs . count ( & MBB ) ) continue ; assert ( ! MBB . isEHPad ( ) && <STR_LIT> ) ; assert ( ! MBB . isLiveIn ( <STR_LIT> ) && <STR_LIT> ) ; for ( MachineBasicBlock * Pred : MBB . predecessors ( ) ) { if ( IndirectTerminatedMBBs . count ( Pred ) ) continue ; if ( ! llvm :: all_of ( Pred -> successors ( ) , [ & ] ( MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) || Succ


<s> const MCSymbolRefExpr * Sym1 = MCSymbolRefExpr :: create ( BB1 -> getSymbol ( ) , * Ctx ) ; const MCSymbolRefExpr * Sym2 = MCSymbolRefExpr :: create ( BB2 -> getSymbol ( ) , * Ctx ) ; const MCBinaryExpr * Sub = MCBinaryExpr :: createSub


<s> if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated (


<s> AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeThumb2Instruction16 ( MI , insn16 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ITBlock . instrInITBlock ( ) ) result = MCDisassembler :: SoftFail ; Check ( result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; ITBlock . setITState ( Firstcond , Mask ) ; } return result ; } if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes , NULL ) == - <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeThumbInstruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeThumb2Instruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } MI . clear ( ) ; result = decodeVFPInstruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } MI . clear ( ) ; result = decodeNEONDupInstruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction32 ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( )


<s> return TargetIRAnalysis ( [ this ] ( const Function & F


<s> Offset = CurDAG -> getTargetConstant ( ImmOff >> Scale , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Offset } ; SDNode * MI = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; Offset = SDValue ( MI , <NUM_LIT> ) ; return true ; } if ( RHS . getOpcode ( ) != <STR_LIT> ) return false ; const SDValue ShiftRHS = RHS . getOperand ( <NUM_LIT> ) ; if ( auto * C = dyn_cast < ConstantSDNode > ( ShiftRHS ) ) if ( C -> getZExtValue ( ) == Scale ) { Base = LHS ; Offset = RHS . getOperand ( <NUM_LIT> ) ; return


-> safe_push ( sve_modes [ sve_i ++ ] ) ;


<s> return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize64BitInt (


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock :: iterator II ( MI ) ; unsigned Fc = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const auto & FGR64RegClass = TRI -> getRegClass ( <STR_LIT> ) ; unsigned Fc2 = RegInfo . createVirtualRegister ( FGR64RegClass ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , Fc2 ) . addImm ( <NUM_LIT> ) . addReg (


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op .


<s> return ( GET_CODE ( x ) == CONST_INT ? <NUM_LIT> : GET_CODE ( x ) == PLUS ? <NUM_LIT>


<s> MVT splitVectorType ( MVT VT ) { if ( ! VT . isVector


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && magic_milli [ INTVAL ( operands [ <NUM_LIT> ] ) ] ) { rtx ret = gen_rtx_REG ( SImode , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; emit_move_insn ( gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ; emit ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) , gen_rtx_fmt_ee ( unsignedp ? UDIV : DIV , SImode , gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , ret ) ) ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; return


<s> unsigned Flag = ELF :: EF_CPU0_NOREORDER ; Flag |= ELF :: EF_CPU0_ARCH_32R2 ; return Flag


<s> tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( <NUM_LIT> , tmp ) ) ; } return tmp


<s> static bool isSignedCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ||


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; } if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( ! isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) && ! isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) ) if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1

, V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc ( ) ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG


<s> void addRegVSFRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( VSFRegs [ getVSReg ( ) ]


<s> return emitAddSub_rx ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ExtendType , <NUM_LIT> , SetFlags , WantResult ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( MulLHS ) ; ResultReg = emitAddSub_rs ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , <STR_LIT> , ShiftVal , SetFlags , WantResult ) ; if ( ResultReg ) return ResultReg ; } } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) { if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { <STR_LIT> ShiftType = <STR_LIT> ; switch ( SI -> getOpcode ( ) ) { default : break ; case Instruction :: Shl : ShiftType = <STR_LIT> ; break ; case Instruction :: LShr : ShiftType = <STR_LIT> ; break ; case Instruction :: AShr : ShiftType = <STR_LIT> ; break ; } uint64_t ShiftVal = C -> getZExtValue ( ) ; if ( ShiftType != <STR_LIT> ) { unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI


<s> case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RTB ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT


<s> for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> EmitInstruction ( MI


<s> rtx_insn * op ; if ( optimize_size ) return <NUM_LIT> ; if ( lab == NULL ) return <NUM_LIT> ; op = lab ; do { op = next_nonnote_nondebug_insn ( op ) ; } while ( op && ( LABEL_P ( op ) || ( INSN_P ( op ) && GET_CODE ( PATTERN ( op ) ) == USE ) ) ) ; if ( ! op ) return


<s> static inline bool isAdvSIMDModImmType11 ( uint64_t Imm ) { uint64_t BString = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( BString == <NUM_LIT> || BString == <NUM_LIT> ) && ( ( Imm &


<s> unsigned IdxN = getRegForValue ( Idx ) ; if ( IdxN == <NUM_LIT> ) return std :: pair < unsigned , bool > ( <NUM_LIT> , false ) ; bool IdxNIsKill = hasTrivialKill ( Idx ) ; MVT PtrVT = TLI . getPointerTy


<s> return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getTargetConstant

( C . CCMask , DL , <STR_LIT> ) , Dest , CCReg ) ;


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_crc_builtin_data ) ; ++ i ) { aarch64_crc_builtin_datum * d = & aarch64_crc_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_std_type ( d -> mode , qualifier_unsigned ) ; tree ftype = build_function_type_list ( usi_type , usi_type , argtype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_NONE , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d ->


<s> if ( ! common ) return false ; A -> AvailableDomains = common ; A -> Dist = std :: max ( A -> Dist , B -> Dist ) ; A -> Instrs . append ( B -> Instrs . begin ( ) , B -> Instrs . end ( ) ) ; for ( unsigned rx = <NUM_LIT> ; rx != NumRegs ; ++ rx ) if ( LiveRegs [


<s> const MCOperand MO1 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ; if ( MO1 . isImm (


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) { if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant


<s> inline unsigned getSOImmValRotate ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned TZ = countTrailingZeros ( Imm ) ; unsigned RotAmt = TZ & ~ <NUM_LIT> ; if ( ( rotr32 ( Imm , RotAmt ) & ~ <NUM_LIT> ) == <NUM_LIT> )

return ( <NUM_LIT> - RotAmt ) & <NUM_LIT> ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token , Ctx ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> Tok . IsSuffix = IsSuffix ; Op -> StartLoc


<s> bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl


<s> printOperand ( MI , opNum , O ) ; if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; return ; } const MCOperand & MO = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . getReg


<s> SDValue Res1 = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DCI . CombineTo ( N , Res1


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address , false , Decoder


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetMt (


<s> RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegNum - <NUM_LIT> ; i ++ ) Inst . addOperand ( MCOperand :: CreateReg ( Regs [ i ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success


<s> if ( ! isInt < <NUM_LIT> > ( Addr . getOffset ( ) ) ) { unsigned TempReg = materialize32BitInt ( Addr . getOffset ( ) , &


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasSVE ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors (


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return nullptr


<s> bool <ISA_LIT>MCAsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind (


<s> return ( __m64 ) __builtin_ia32_pfadd ( ( __v2sf


<s> return __builtin_neon_vmmlav8bf ( __r ,


<s> static bool isVShiftRImm ( SDValue Op , EVT VT , bool isNarrow , bool isIntrinsic , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt = - Cnt ; return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits /


<s> bool <ISA_LIT>ConditionalCompares :: runOnMachineFunction ( MachineFunction & MF ) { DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( )


<s> bool isAbsMem ( ) const { return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( )

== <NUM_LIT> && isMaybeDirectBranchDest ( ) ;


<s> Register VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII .


<s> if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return ClassifyGlobalReference ( GV


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS =


<s> int Size = ( int ) Insn - Pos + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; ExceptionsType = ExceptionHandling


<s> arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT>


<s> if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB (


<s> StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; RegNo = - <NUM_LIT> ; if ( Operand . isGPRAsmReg ( ) ) { RegNo = isGP64bit ( ) ? Operand . getGPR64Reg ( ) : Operand . getGPR32Reg ( ) ; } else if ( Operand . isCheriAsmReg ( ) ) { RegNo = Operand . getCheriReg ( ) ; } else { llvm_unreachable (


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext


<s> rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_csky_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCAsmInfo ) ; for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer


<s> if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( *

GV -> getParent ( ) , GV ) ) return <STR_LIT> ;


<s> if ( ! isShiftedImm ( ) && ! isImm ( ) ) return false ; if ( auto ShiftedVal = getShiftedVal < <NUM_LIT> > ( ) ) return ShiftedVal -> first < <NUM_LIT> && - ShiftedVal -> first <= <NUM_LIT> ; return


<s> SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } AFI -> setArgRegsSaveSize ( ArgRegsSaveSize + AFI -> getArgRegsSaveSize


<s> if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p = { } ; if ( <STR_LIT> ( type , & p . num_zr , & p . num_pr ) ) { machine_mode mode = TYPE_MODE_RAW ( type ) ; gcc_assert ( VECTOR_MODE_P ( mode ) && ( ! TARGET_SVE || aarch64_sve_mode_p ( mode ) ) ) ; p . mode = p . orig_mode =


<s> if ( ! isFP64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int ) <STR_LIT>


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB


<s> void <ISA_LIT>InstrInfo :: fixupPostOutline ( MachineBasicBlock & MBB ) const { for ( MachineInstr & MI : MBB ) { MachineOperand * Base ; unsigned Width ; int64_t Offset ; if ( ! MI . mayLoadOrStore ( ) || ! getMemOperandWithOffsetWidth ( MI , Base , Offset , Width , & RI ) || ( Base -> isReg ( ) && Base -> getReg ( ) != <STR_LIT> ) ) continue ; unsigned Scale ; int64_t Dummy1 , Dummy2 ; MachineOperand & StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand ( MI ) ; assert ( StackOffsetOperand . isImm ( ) && <STR_LIT> ) ; getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1


<s> if ( ! ST . is<ISA_LIT>64 ( ) || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) || ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) && ! GVKind . isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( isVerbose ( ) ) { if ( GV -> hasInitializer ( ) ) { GV -> printAsOperand ( OutStreamer -> GetCommentOS ( ) , false , GV -> getParent ( ) ) ; OutStreamer -> GetCommentOS ( ) << '\n' ; } } MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> hasCommonLinkage ( ) || GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getValueType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned adjustment = <NUM_LIT> ; if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( <STR_LIT> ) ) adjustment += RegInfo -> getSlotSize ( ) ; if ( hasFP ( MF ) && MF . protectFramePtr ( ) )


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) || TheTriple . isWindowsCoreCLREnvironment ( ) ) { if ( Options . getAssemblyLanguage ( ) . equals_lower ( <STR_LIT> ) ) MAI = new <ISA_LIT>MCAsmInfoMicrosoftMASM ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT>


<s> case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : case MachineOperand :: MO_CImmediate : case MachineOperand :: MO_FPImmediate : return false ; case MachineOperand :: MO_MachineBasicBlock : return true ; case MachineOperand :: MO_FrameIndex : return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true


<s> case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return <NUM_LIT> ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL


<s> ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < ShlOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; Register RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } Register RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; MVT VT = std :: max ( <STR_LIT> , RetVT . SimpleTy ) ; ResultReg = fastEmit_rr ( VT , VT , ISDOpc , LHSReg ,


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) ,

PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { SDNode * N = Op . getNode ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned BaseOp = <NUM_LIT> ; unsigned Cond = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) if ( C -> isOne ( ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) if ( C -> isOne ( ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp =


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( tryRISBGZero ( Node ) ) return ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) { splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getScalarSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } else if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } break ; } case <STR_LIT> : { auto * Store = cast < StoreSDNode > ( Node ) ; unsigned ElemBitSize = Store -> getValue ( ) . getValueSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryScatter ( Store , <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = MCID . getNumOperands ( ) ; i != e ; ++ i ) if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT>


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> } ; const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) <


<s> } for ( i = FIRST_SHADOW_REGISTER ; i <= LAST_SHADOW_REGISTER ; i ++ ) global_regs [ i


<s> unsigned <ISA_LIT>TargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int Scale = BitWidth / <NUM_LIT> ; int NumBytes = NumElts * Scale ; ShuffleMask . reserve ( NumBytes ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue > ( COp ) ) { ShuffleMask . append ( Scale , SM_SentinelUndef ) ; continue ; } APInt APElt = cast < ConstantInt > ( COp ) -> getValue ( ) ; for ( int j = <NUM_LIT> ; j != Scale ;


<s> unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Firstcond = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Firstcond & <NUM_LIT> ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 ) llvm_unreachable ( <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; NumUBrFixed ++ ; DOUT ( llvm :: dbgs ( ) << <STR_LIT>


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; MCContext & Ctx = Asm . getContext ( ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; Value = adjustFixupValue ( Fixup , Target , Value , Ctx , TheTriple , IsResolved ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes ==


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( hasConsumedDollar ) { hasConsumedDollar = false ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken ::


<s> static inline int getMClassRegisterSYSmValueMask ( StringRef RegString ) { return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate (


<s> return __builtin_mve_veorq_uv16qi ( __a ,


<s> return ( __m128i ) __builtin_ia32_pmovsdw128_mask ( ( __v4si ) __A ,


<s> unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( FirstReg

+ getVectorListStart ( ) - <STR_LIT> ) ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token , S , S ) ; Op -> Tok . Data = Str


<s> if ( JIT ) return CodeModel :: Small ; if ( TT . isOSAIX ( ) ) return CodeModel :: Small ; assert ( TT . isOSBinFormatELF ( ) && <STR_LIT> ) ; if ( TT . isArch32Bit ( ) )


<s> StringRef Option ; if ( Parser . parseIdentifier ( Option ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleHardFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken


<s> assert ( Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( Ty == <STR_LIT> || Has<ISA_LIT>64 ) return LowerFCOPYSIGNLargeIntReg


<s> if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; return ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange

( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) {


<s> unsigned ConvOpc = IsSingle ? ( IsSigned ? <STR_LIT> : <STR_LIT> ) : ( IsSigned ? <STR_LIT> : <STR_LIT> ) ; EVT ConvTy = IsSingle ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ConvOpc , dl


<s> Value * <ISA_LIT>IREmitter :: visitSETCC_CARRY ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> void \ sbss_section ( void ) \ { \ if ( in_section != in_sbss ) \ { \ in_section = in_sbss ; \ fprintf (

asm_out_file , <STR_LIT> , SBSS_SECTION_ASM_OP ) ; \ } \ }


<s> void <ISA_LIT>InstPrinter :: printS34ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { long long Value = MI -> getOperand ( OpNo ) . getImm


<s> assert ( ( ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] ) && <STR_LIT> ) ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT>


<s> for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } can_issue_more = issue_rate ; slot = <NUM_LIT> ; insn = get_next_active_insn ( prev_head_insn , tail ) ; group_end = false ; while ( insn != NULL_RTX ) { slot = ( issue_rate - can_issue_more ) ; group_insns [ slot ] = insn ; can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; if ( insn_terminates_group_p ( insn , current_group ) ) can_issue_more = <NUM_LIT> ; next_insn = get_next_active_insn ( insn , tail ) ; if ( next_insn == NULL_RTX ) return group_count + <NUM_LIT> ; group_end = ( can_issue_more == <NUM_LIT> || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; can_issue_more = force_new_group ( sched_verbose , dump , group_insns , next_insn , & group_end ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo (


<s> if ( ! OrigOp . isMem ( ) ) return false ; unsigned OrigReg = OrigOp . Mem . BaseReg ; unsigned FinalReg = FinalOp . Mem . BaseReg ; if ( RegClassID != - <NUM_LIT> && ! <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( OrigReg ) ) { return Error ( OrigOp . getStartLoc ( ) , <STR_LIT> ) ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else return false ; bool IsSI = IsSIReg ( FinalReg ) ; FinalReg = GetSIDIForRegClass ( RegClassID , FinalReg , IsSI ) ; if ( FinalReg != OrigReg ) { std :: string RegName = IsSI ? <STR_LIT> : <STR_LIT> ; Warnings . push_back ( std :: make_pair ( OrigOp . getStartLoc ( ) , <STR_LIT> + RegName + <STR_LIT> ) ) ; } FinalOp . Mem . Size = OrigOp . Mem . Size ; FinalOp . Mem . SegReg = OrigOp . Mem . SegReg ; FinalOp . Mem . BaseReg = FinalReg ; } } for ( auto & WarningMsg : Warnings ) { Warning ( WarningMsg . first , WarningMsg . second ) ; } for ( unsigned int i = <NUM_LIT> ; i < FinalOperands . size ( ) ; ++ i ) OrigOperands . pop_back ( ) ; } for ( unsigned int i = <NUM_LIT> ; i < FinalOperands . size ( ) ; ++ i ) OrigOperands . push_back ( std :: move ( FinalOperands [ i ] ) ) ; return


<s> } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) &


<s> static inline unsigned getADDrrFromLEA ( unsigned LEAOpcode ) { switch ( LEAOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>BaseRegisterInfo * ARI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = ARI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Register Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; SDValue ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , PtrVT ) ; constexpr EVT ResultTys [ ] = { <STR_LIT>


<s> if ( ! HasControlFlow ( MI ) ) return false ; if ( IsDirectBranch ( MI ) ) return false ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( Is64Bit ) { NewMI . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( Is64Bit ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg

( <STR_LIT> ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Qd = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= cmode << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT>


<s> if ( auto Value = combineADDToADDZE ( N ,

DCI . DAG , Subtarget ) ) return Value ;


<s> auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; Optional < unsigned > MaxNumVScale = getMaxVScale ( ) ; assert ( MaxNumVScale && <STR_LIT> ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; unsigned MaxNumElementsPerGather = MaxNumVScale . getValue ( ) * LegalVF . getKnownMinValue ( ) ; return LT . first * MaxNumElementsPerGather *


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; return emitBinOp ( OpcTable , DefReg ,


<s> return getSchedModel ( ) . hasInstrSchedModel


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Result ) . addReg ( <STR_LIT> ) . addReg ( Tmp2 , getKillRegState ( true ) ) . addMBB ( TargetBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp1 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMBB ( TargetBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO32 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp1 , getKillRegState ( true ) ) . addImm ( M0 ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Result ) . addReg ( Tmp2 , getKillRegState ( true ) ) . addImm ( <NUM_LIT> ) . addMBB ( TargetBB ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getGatherNode ( Opc , Op , DAG , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getMGatherNode ( Opc , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand


<s> MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg ,


<s> Value * <ISA_LIT>IREmitter :: visitFSETCC ( const


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( ( Cond . size ( ) && Cond . size ( ) <= <NUM_LIT> ) &&


<s> static bool sparc_function_value_regno_p ( const unsigned int


<s> MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start =


<s> } gcc_assert ( MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_unop ( DImode , NOT , new_reg , NULL_RTX , true ) ; code = AND ; } new_reg = expand_simple_binop ( DImode , code , new_reg , val , NULL_RTX , true , OPTAB_DIRECT ) ; if ( mode != DImode ) new_reg = gen_lowpart ( mode , new_reg ) ; if ( new_dst ) emit_move_insn ( new_dst ,


<s> static bool isGPR ( const TargetRegisterClass * RC ) { return <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC )

|| <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ;


<s> fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( crtl -> is_leaf ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( rp_saved ) fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ; if ( gr_saved ) fprintf ( file ,


<s> __m64 result ; __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ) ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> fputs ( <STR_LIT> , file ) ; switch ( size ) { case <NUM_LIT> : break ; case <NUM_LIT> : fputs ( <STR_LIT> , file


<s> static DecodeStatus DecodeMatrixTile ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { unsigned LastReg = ( <NUM_LIT> << NumBitsForTile ) - <NUM_LIT> ; if ( RegNo > LastReg ) return Fail ; Inst . addOperand ( MCOperand :: createReg ( MatrixZATileDecoderTable [ NumBitsForTile ] [ RegNo ] ) ) ; return Success


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; if ( MMO . isVolatile ( ) ||


<s> } ) != To -> getParent ( ) -> rend ( ) ) ; for ( -- To ; To != From ; -- To ) { const MachineInstr & Instr = * To ; if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read ) && Instr . readsRegister


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: Dwarf ; AbsoluteEHSectionOffsets = false ; if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch

( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , PseudoSourceValue :: getFixedStack ( NewRetAddr ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , PseudoSourceValue :: getFixedStack ( NewFPIdx ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } } return Chain


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT>


<s> unsigned getFramePointerSaveOffset (


<s> MachineInstr * OptimizeLEAPass :: replaceDebugValue ( MachineInstr & MI , unsigned VReg , int64_t AddrDispShift ) { DIExpression * Expr = const_cast < DIExpression * > ( MI . getDebugExpression ( ) ) ; if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: NoDeref , AddrDispShift , DIExpression :: NoDeref , DIExpression :: WithStackValue ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue (


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( i == Idx ? NumElems : i ) ; return DAG . getVectorShuffle ( VT , V2 . getDebugLoc ( ) , V1 ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op


<s> if ( sh_symbian_dllexport_p ( decl ) ) sh_symbian_mark_dllexport ( decl ) ; else if ( sh_symbian_dllimport_p ( decl ) ) sh_symbian_mark_dllimport ( decl ) ; else if ( ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CODE ( decl ) == VAR_DECL ) && DECL_RTL ( decl ) != NULL_RTX && GET_CODE ( DECL_RTL ( decl ) ) == MEM && GET_CODE ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && sh_symbian_dllimport_name_p

( XSTR ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) {


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; SpillsVRS = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg


<s> unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const TargetInstrDesc & TID1 = TII -> get ( MulOpc ) ; const TargetInstrDesc & TID2 = TII -> get ( AddSubOpc ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TID1 . getRegClass ( <NUM_LIT> , TRI ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI -> hasOneNonDBGUse ( AccReg ) ; MIB . addReg ( TmpReg , getKillRegState ( true ) ) . addReg

( AccReg , getKillRegState ( AccKill ) ) ;


<s> Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> static SDValue PerformTruncateCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering

:: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) {


<s> unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift =


<s> if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: CreateImm ( getImm (


<s> case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer . AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer . PushSection ( ) ; const MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( M , <NUM_LIT> ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbol * Stub = OutContext . GetOrCreateSymbol ( StringRef ( x ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer . EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer . EmitLabel ( Stub ) ; if ( Subtarget -> getRelocationModel ( ) == Reloc :: PIC_ ) llvm_unreachable


<s> return ( __m512i ) __builtin_ia32_broadcasti64x4_512 ( ( __v4di ) __A , (


<s> MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) )

FrameReg = RegInfo -> getBaseRegister ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( unsigned (


<s> auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align (


<s> static DecodeStatus DecodeRegisterClassByID ( llvm :: MCInst & Inst , unsigned RegNo , unsigned RegID , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , RegID , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL


<s> const MandarinInstrInfo & TII = * static_cast < const MandarinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( - StackSize ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } if ( StackSize ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize ) ;


<s> return __builtin_ia32_vcvtdq2ph512_mask_round ( ( __v16si ) __B , _mm256_setzero_ph ( ) ,


<s> } else if ( Subtarget -> hasVFP3 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> allowsUnalignedMem ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasFP16 ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasMPExtension ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasDivideIn<ISA_LIT>Mode ( ) && ! Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( MMI ) { if ( const Module * SourceModule = MMI -> getModule ( ) ) { if ( auto WCharWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ) { int WCharWidth = WCharWidthValue -> getZExtValue ( ) ; assert ( ( WCharWidth == <NUM_LIT> || WCharWidth == <NUM_LIT> ) && <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , WCharWidth ) ; } if ( auto EnumWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ) { int EnumWidth = EnumWidthValue -> getZExtValue ( ) ; assert ( ( EnumWidth == <NUM_LIT> || EnumWidth == <NUM_LIT> ) && <STR_LIT> ) ; int EnumBuildAttr = EnumWidth == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; ATS . emitAttribute ( <STR_LIT> , EnumBuildAttr ) ; } } } if ( Subtarget -> isR9Reserved ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res >> <NUM_LIT> ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr


<s>
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
unsigned
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)
)
;
return
true
;
}
if
(
(
Match1
==
Match_MnemonicFail
)
&&
(
Match2
==
Match_MnemonicFail
)

&& ( Match3 == Match_MnemonicFail ) && ( Match4 == Match_MnemonicFail ) ) {


<s> const MCPhysReg * <ISA_LIT>TargetLowering :: getScratchRegisters ( CallingConv ::


<s> void addCCOutOperands ( MCInst & Inst , unsigned


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> static SDValue GetTLSADDR ( SelectionDAG & DAG , SDValue Chain , GlobalAddressSDNode * GA , SDValue * InFlag , const EVT PtrVT , unsigned ReturnReg , unsigned char OperandFlags , bool LocalDynamic = false , unsigned Opcode = <STR_LIT> ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; unsigned CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( Opcode != <STR_LIT> ) CallType = Opcode ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys


<s> static void printExpr ( const MCExpr * Expr , raw_ostream & OS ) { const MCSymbolRefExpr * SRE ; SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; const MCSymbolRefExpr :: VariantKind Kind = SRE


<s> if ( isImmOpnd ) { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; ImmOffset = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; LoOffset = ImmOffset & <NUM_LIT> ; HiOffset = ( ImmOffset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; } else ExprOffset = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; TempInst . setLoc ( IDLoc ) ; const MCInstrDesc & Desc = getInstDesc ( Inst . getOpcode ( ) ) ; int16_t RegClassOp0 = Desc . OpInfo [ <NUM_LIT> ] . RegClass ; unsigned RegClassIDOp0 = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RegClassOp0 ) . getID ( ) ; bool IsGPR = ( RegClassIDOp0 == <STR_LIT> ) || ( RegClassIDOp0 == <STR_LIT> ) ; if ( isLoad && IsGPR && ( BaseRegNum != RegOpNum ) ) TmpRegNum = RegOpNum ; else { TmpRegNum = getATReg ( IDLoc ) ; if ( ! TmpRegNum ) return ; } TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: createReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: createImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; } } Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; if ( BaseRegNum != <STR_LIT> ) { TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: createReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: createReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: createReg ( BaseRegNum ) ) ; Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; } TempInst . setOpcode ( Inst . getOpcode ( ) ) ; TempInst . addOperand ( MCOperand :: createReg ( RegOpNum ) ) ; TempInst . addOperand ( MCOperand :: createReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: createImm ( LoOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO


<s> ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ;


<s> Type * T = Args [ Idx ] . Ty ; if ( T -> isPointerTy ( ) || T -> isIntegerTy ( ) ) if ( MF -> getDataLayout ( ) . getTypeAllocSize ( T ) <= <NUM_LIT> ) { unsigned numRegs = <NUM_LIT> ; if ( MF -> getDataLayout ( ) . getTypeAllocSize (


<s> if ( match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Value ( A ) , m_Value ( B ) ) ) && match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Specific ( A ) , m_Specific ( B ) ) ) ) return IC . replaceInstUsesWith ( II , ( II . getIntrinsicID ( ) == <STR_LIT> ? A : B ) ) ; return None


<s> x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask )


<s> if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { cum -> fpr_offset = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG ( cum -> fpr_offset , mode , type ) - NDS32_FPR_ARG_FIRST_REGNUM + NDS32_NEED_N_REGS_FOR_ARG ( mode , type ) ; } else { cum -> gpr_offset = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) - NDS32_GPR_ARG_FIRST_REGNUM + NDS32_NEED_N_REGS_FOR_ARG ( mode , type ) ; } } else { if ( ! TARGET_HARD_FLOAT ) { cum -> gpr_offset = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) - NDS32_GPR_ARG_FIRST_REGNUM + NDS32_NEED_N_REGS_FOR_ARG ( mode ,


<s> MVT VT ; Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , VT ) ) return false ; RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 :


<s> return ( __m64 ) __builtin_ia32_psubsw ( ( __v4hi ) __m1 , ( __v4hi )


<s> } Insn = IsLittleEndian ? ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) : ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; return DAG


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _MM_SET_FLUSH_ZERO_MODE ( unsigned int


<s> arm_simd_polyDI_type_node = build_distinct_type_copy ( unsigned_intDI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyDI_type_node , <STR_LIT> ) ; arm_simd_polyTI_type_node = build_distinct_type_copy ( unsigned_intTI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyTI_type_node , <STR_LIT> ) ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; TYPE_STRING_FLAG ( arm_simd_polyQI_type_node ) = false ; TYPE_STRING_FLAG ( arm_simd_polyHI_type_node ) = false ; } arm_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; arm_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; arm_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; arm_simd_types [ Bfloat16x2_t ] . eltype = arm_bf16_type_node ; arm_simd_types [ Bfloat16x4_t ] . eltype = arm_bf16_type_node ; arm_simd_types [ Bfloat16x8_t ] . eltype = arm_bf16_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; machine_mode mode = arm_simd_types [ i ] . mode ; if ( eltype == NULL && ( ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) || ! TARGET_HAVE_MVE )


<s> dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == <NUM_LIT> ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > <NUM_LIT> ) return false ; return dalign / BITS_PER_UNIT >= dsize ; } } else { type = TREE_TYPE ( decl ) ; dalign = TYPE_ALIGN ( type ) ; if ( CONSTANT_CLASS_P ( decl ) ) dalign = CONSTANT_ALIGNMENT ( decl , dalign ) ; else dalign = DATA_ALIGNMENT ( decl , dalign ) ; if ( dsize == <NUM_LIT> ) { if ( TREE_CODE ( decl ) == STRING_CST ) dsize = TREE_STRING_LENGTH ( decl ) ; else if ( TYPE_SIZE_UNIT ( type ) && tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) dsize = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) ; else return


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg


<s> return ( __m512i ) __builtin_ia32_vpshld_v16si ( ( __v16si ) __A ,


<s> } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I


<s> MaskUnpackCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } int MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; int InsertExtractCost = <NUM_LIT>


<s> auto Where = llvm :: find_if ( PrologMBB , [ ] ( MachineInstr & MI ) { return MI . getOpcode ( ) == <STR_LIT> ; } ) ; if ( Where != PrologMBB . end ( ) ) { DebugLoc DL = PrologMBB . findDebugLoc ( Where ) ; emitStackProbeInline ( MF , PrologMBB , Where , DL


<s> const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num


<s> return ( __m128d ) __builtin_ia32_cvtps2pd ( (