<s> default : error ( <STR_LIT> ) ; return const0_rtx ; } } } else if ( i == nargs - <NUM_LIT> ) { if ( ! insn_p -> operand [ nargs ] . predicate ( op , SImode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( INTVAL ( op ) == NO_ROUND ) redundant_embed_rnd = <NUM_LIT> ; } else { if ( VECTOR_MODE_P ( mode ) ) op = safe_vector_operand ( op , mode ) ; op = fixup_modeless_constant ( op , mode ) ; if ( GET_MODE ( op ) == mode || GET_MODE ( op ) == VOIDmode ) { if ( optimize || ! match ) op = copy_to_mode_reg ( mode , op ) ; } else { op = copy_to_reg ( op ) ; op = simplify_gen_subreg ( mode , op , GET_MODE ( op ) , <NUM_LIT> ) ; } } args [ i ] . op = op ; args [ i ] . mode = mode ; } switch ( nargs ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return <NUM_LIT> ; if ( redundant_embed_rnd ) pat = ix86_erase_embedded_rounding ( pat ) ; emit_insn ( pat ) ; return target


<s> if ( CALL_P ( insn ) ) return false ; return is_load_insn1 ( PATTERN ( insn ) , load_mem


<s> printRegName ( O , Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << '$' << ( int64_t ) Op . getImm ( ) << markup ( <STR_LIT> ) ; if ( CommentStream && ( Op . getImm ( ) > <NUM_LIT> || Op . getImm ( ) < - <NUM_LIT> ) ) * CommentStream << format ( <STR_LIT> PRIX64 <STR_LIT> , ( uint64_t ) Op . getImm ( ) ) ; } else


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> || strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) flags |= SECTION_BSS ; return flags


<s> for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; i += <NUM_LIT> ) { SDValue Op0L = Op0 -> getOperand ( i ) , Op1L = Op1 -> getOperand ( i ) , Op0H = Op0 -> getOperand ( i + <NUM_LIT> ) , Op1H = Op1 -> getOperand ( i + <NUM_LIT> ) ; if ( Op0L . getOpcode ( ) != <STR_LIT> || Op1L . getOpcode ( ) != <STR_LIT> || Op0H . getOpcode ( ) != <STR_LIT> || Op1H . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * Const0L = dyn_cast < ConstantSDNode > ( Op0L -> getOperand ( <NUM_LIT> ) ) ; auto * Const1L = dyn_cast < ConstantSDNode > ( Op1L -> getOperand ( <NUM_LIT> ) ) ; auto * Const0H = dyn_cast < ConstantSDNode > ( Op0H -> getOperand ( <NUM_LIT> ) ) ; auto * Const1H = dyn_cast < ConstantSDNode > ( Op1H -> getOperand ( <NUM_LIT> ) ) ; if ( ! Const0L || ! Const1L || ! Const0H || ! Const1H ) return SDValue ( ) ; unsigned Idx0L = Const0L -> getZExtValue ( ) , Idx1L = Const1L -> getZExtValue ( ) , Idx0H = Const0H -> getZExtValue ( ) , Idx1H = Const1H -> getZExtValue ( ) ; if ( Idx0L > Idx1L ) std :: swap ( Idx0L , Idx1L ) ; if ( Idx0H > Idx1H ) std :: swap ( Idx0H , Idx1H ) ; if ( Idx0L > Idx0H ) { std :: swap ( Idx0L , Idx0H ) ; std :: swap ( Idx1L , Idx1H ) ; } if ( Idx0L != <NUM_LIT> * i || Idx1L != <NUM_LIT> * i + <NUM_LIT> || Idx0H != <NUM_LIT> * i + <NUM_LIT> || Idx1H != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; if ( ! Mul ) { Mul = Op0L -> getOperand ( <NUM_LIT> ) ; if ( Mul -> getOpcode ( ) != <STR_LIT> || Mul . getValueType ( ) . getVectorNumElements ( ) != <NUM_LIT> * e ) return SDValue ( ) ; } if ( Mul != Op0L -> getOperand ( <NUM_LIT> ) || Mul != Op1L -> getOperand ( <NUM_LIT> ) || Mul != Op0H -> getOperand ( <NUM_LIT> ) || Mul != Op1H -> getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } ShrinkMode Mode ; if ( ! canReduceVMulWidth ( Mul . getNode ( ) , DAG , Mode ) || Mode == MULU16


<s> fprintf ( file , <STR_LIT> , i ) ; fprintf ( file , <STR_LIT> , ( optional_tbtab << <NUM_LIT> ) | ( ( info -> first_fp_reg_save != <NUM_LIT> ) << <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , ( ( optional_tbtab << <NUM_LIT> ) | ( ( optional_tbtab & frame_pointer_needed ) << <NUM_LIT> ) | ( info -> cr_save_p << <NUM_LIT> ) | ( info -> lr_save_p ) ) ) ; fprintf ( file , <STR_LIT> , ( info -> push_p << <NUM_LIT> ) | ( <NUM_LIT> - info -> first_fp_reg_save ) ) ; fprintf ( file , <STR_LIT> , ( <NUM_LIT> - first_reg_to_save ( ) ) ) ; if ( optional_tbtab ) { tree decl ; int next_parm_info_bit = <NUM_LIT> ; for ( decl = DECL_ARGUMENTS ( current_function_decl ) ; decl ; decl = DECL_CHAIN ( decl ) ) { rtx parameter = DECL_INCOMING_RTL ( decl ) ; machine_mode mode = GET_MODE ( parameter ) ; if ( GET_CODE ( parameter ) == REG ) { if ( SCALAR_FLOAT_MODE_P ( mode ) ) { int bits ; float_parms ++ ; switch ( mode ) { case SFmode : case SDmode : bits = <NUM_LIT> ; break ; case DFmode : case DDmode : case TFmode : case TDmode : case IFmode : case KFmode : bits = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( next_parm_info_bit > <NUM_LIT> ) parm_info |= ( bits << ( next_parm_info_bit - <NUM_LIT> ) ) ; next_parm_info_bit -= <NUM_LIT> ; } else { fixed_parms += ( ( GET_MODE_SIZE ( mode ) + ( UNITS_PER_WORD - <NUM_LIT> ) ) / UNITS_PER_WORD ) ; next_parm_info_bit -= <NUM_LIT> ; } } } } fprintf ( file , <STR_LIT> , fixed_parms ) ; fprintf ( file , <STR_LIT> , ( ( float_parms << <NUM_LIT> ) | ( ! optimize ) ) ) ; if ( optional_tbtab ) { if ( fixed_parms || float_parms ) fprintf ( file , <STR_LIT> , parm_info ) ; fputs ( <STR_LIT> , file ) ; ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; RS6000_OUTPUT_BASENAME ( file , fname ) ; putc ( '-' , file ) ; rs6000_output_function_entry ( file , fname ) ; putc ( '\n' , file


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> if ( __count <= <NUM_LIT> ) { m = ( __vector signed short ) vec_splats ( __m ) ; c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; r = vec_sl ( m , ( __vector unsigned short ) c ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) r ,


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetGINV (


<s> NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( std :: prev ( MachineFunction :: iterator ( NewIsland ) ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i )


<s> DebugLoc dl ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ==


<s> return getFP32Imm ( FPImm . bitcastToAPInt (


<s> unsigned short Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned short


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumRegs = sizeof ( RegList ) / sizeof ( RegList [ <NUM_LIT> ] ) ; SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ArgFlags . isSplit ( ) || ! PendingMembers . empty ( ) ) { PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; } if ( PendingMembers . empty ( ) ) { if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } return false


<s> if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG )


<s> virtual bool enableMachineScheduler ( )


<s> unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> ) return Op ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; MVT WideVecVT = VecVT ; if ( ( ! Subtarget . hasDQI ( ) && NumElems == <NUM_LIT> ) || NumElems < <NUM_LIT> ) { WideVecVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , DAG . getUNDEF ( WideVecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( )


<s> mac_op0 = XEXP ( XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; mac_op1 = XEXP ( XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; mac_acc = XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) ; return ( reg_overlap_mentioned_p ( mul_result , mac_acc ) && ! reg_overlap_mentioned_p ( mul_result , mac_op0 ) && ! reg_overlap_mentioned_p ( mul_result ,


<s> static int mips16_rewrite_pool_refs ( rtx * x , void * data ) { struct mips16_constant_pool * pool = data ; if ( GET_CODE ( * x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( * x ) ) * x = gen_rtx_LABEL_REF ( Pmode ,

add_constant ( pool , get_pool_constant ( * x ) , get_pool_mode ( * x ) ) ) ;


<s> return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , DAG . getIntPtrConstant ( Size


<s> assert ( CCR . getOpcode ( ) == <STR_LIT> ) ; <STR_LIT> CCVal = ( <STR_LIT> ) cast < ConstantSDNode > ( CC ) -> getZExtValue ( ) ; if ( ! Subtarget -> isThumb1Only ( ) && VT == <STR_LIT> ) { SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( Subtarget -> isThumb ( ) ) { SDNode * Res = SelectT2CMOVShiftOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = SelectT2CMOVShiftOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVShiftOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVShiftOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } if ( Subtarget -> isThumb ( ) ) { SDNode * Res = SelectT2CMOVSoImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = SelectT2CMOVSoImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } else { SDNode * Res = Select<ISA_LIT>CMOVSoImmOp ( N , FalseVal , TrueVal , CCVal , CCR , InFlag ) ; if ( ! Res ) Res = Select<ISA_LIT>CMOVSoImmOp ( N , TrueVal , FalseVal , <STR_LIT> ( CCVal ) , CCR , InFlag ) ; if ( Res ) return Res ; } } SDValue Tmp2 = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , TrueVal , Tmp2 , CCR , InFlag } ; unsigned Opc = <NUM_LIT> ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; break ; case <STR_LIT> : Opc = Subtarget -> isThumb ( ) ? ( Subtarget -> hasThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> bool allowsUnalignedMem ( ) const { return AllowsUnalignedMem


<s> data -> ifetch_block_n_insns = prev_data -> ifetch_block_n_insns + <NUM_LIT> ; gcc_assert ( data -> ifetch_block_len <= core2i7_ifetch_block_size && data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; if ( ! data -> ready_try_change ) { data -> ready_try_change = sbitmap_alloc ( n_ready ) ; data -> ready_try_change_size = n_ready ; } else if ( data -> ready_try_change_size < n_ready ) { data -> ready_try_change = sbitmap_resize ( data -> ready_try_change , n_ready , <NUM_LIT> ) ; data -> ready_try_change_size = n_ready ; } bitmap_clear ( data -> ready_try_change


<s> CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } if ( ! Subtarget -> is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; unsigned Reg = VA . getLocReg ( ) ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: foldBoolExts ( SDValue & Res , SDNode * & N ) { if ( ! <ISA_LIT>SubTarget -> useCRBits ( ) ) return ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; if ( ! N -> hasOneUse ( ) ) return ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N


<s> if ( context -> br_loc [ <NUM_LIT> ] && * context -> br_loc [ <NUM_LIT> ] != context -> rp ) { fs -> curr . reg [ UNW_REG_RP ] . where = UNW_WHERE_BR ; fs -> curr . reg [ UNW_REG_RP ] . when = - <NUM_LIT> ; fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; goto success ; } return _URC_END_OF_STACK ; success : return _URC_NO_REASON ; return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( context -> rp - context -> region_start ) / <NUM_LIT> * <NUM_LIT> ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw + length + <NUM_LIT> ; } insn = ( unsigned char * ) ( unw + <NUM_LIT> ) ; insn_end = ( unsigned char * ) ( unw + <NUM_LIT> + length ) ; while ( ! fs -> done && insn < insn_end ) insn = unw_decode ( insn , fs -> in_body , fs ) ; free_label_states ( fs -> labeled_states ) ; free_state_stack ( & fs -> curr ) ; if ( reg_state_alloced || labeled_state_alloced ) abort ( ) ; if ( fs -> when_target > fs -> epilogue_start ) { struct unw_reg_info * r ; fs -> curr . reg [ UNW_REG_PSP ] . where = UNW_WHERE_NONE ; fs -> curr . reg [ UNW_REG_PSP ] . val = <NUM_LIT> ; for ( r = fs -> curr . reg ; r < fs -> curr . reg + UNW_NUM_REGS ; ++ r ) if ( ( r -> where == UNW_WHERE_PSPREL && r -> val <= <NUM_LIT> ) || r

-> where == UNW_WHERE_SPREL ) r -> where = UNW_WHERE_NONE ;


<s> wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return - <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ; if ( ( mantissa & mask ) != <NUM_LIT> ) return - <NUM_LIT> ; mantissa >>= point_pos


<s> frame -> var_size = MIPS_STACK_ALIGN ( size ) ; offset += frame -> var_size ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( mips_save_reg_p ( regno ) ) { frame -> num_gp ++ ; frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) ; } if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { frame -> num_gp ++ ; frame -> mask |= <NUM_LIT> << ( EH_RETURN_DATA_REGNO ( i ) - GP_REG_FIRST ) ; } if ( GENERATE_MIPS16E_SAVE_RESTORE ) { mips16e_mask_registers ( & frame -> mask , mips16e_s2_s8_regs , ARRAY_SIZE ( mips16e_s2_s8_regs ) , & frame -> num_gp ) ; mips16e_mask_registers ( & frame -> mask , mips16e_a0_a3_regs , ARRAY_SIZE ( mips16e_a0_a3_regs ) , & frame -> num_gp ) ; } if ( frame -> num_gp > <NUM_LIT> ) { offset += MIPS_STACK_ALIGN ( frame -> num_gp * UNITS_PER_WORD ) ; frame -> gp_sp_offset = offset - UNITS_PER_WORD ; } if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno += MAX_FPRS_PER_FMT ) if ( mips_save_reg_p ( regno ) ) { frame -> num_fp += MAX_FPRS_PER_FMT ; frame -> fmask |= ~ ( ~ <NUM_LIT> << MAX_FPRS_PER_FMT ) << ( regno - FP_REG_FIRST ) ; } if ( frame -> num_fp > <NUM_LIT> ) { offset += MIPS_STACK_ALIGN ( frame -> num_fp * UNITS_PER_FPREG


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT>


<s> assert ( Cond . size ( ) == <NUM_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC


<s> SItype __divsi3 ( SItype a , SItype b ) { word_type neg = <NUM_LIT> ; SItype res ; if ( a < <NUM_LIT> ) { a = - a ; neg = ! neg ; } if ( b < <NUM_LIT> ) { b = - b ; neg = !


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG .

getEntryNode ( ) , Offset , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment


<s> static bool isDataTypeToken ( StringRef Tok ) { return Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> ||

Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> ;


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= <NUM_LIT> && ST -> hasAVX ( )


<s> if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return <NUM_LIT> - CurrGroupSize ; return - <NUM_LIT> ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots (


<s> inline static bool modifiesOp ( unsigned AluOp


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm -> getValue ( ) / <NUM_LIT> ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val )


<s> if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; return


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; bool TryRegParse = getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) ) ; if ( ! TryRegParse || ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Parser . clearPendingErrors ( ) ; Res = <STR_LIT> ( RegNo , Parser .


<s> } if ( mode == SFmode && ( i % <NUM_LIT> ) == <NUM_LIT> && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( TEST_HARD_REG_BIT ( * live_regs_mask , ( i ^ <NUM_LIT> ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == <NUM_LIT> ) != align ) continue ; if ( current_function_interrupt && GENERAL_REGISTER_P ( i ) && tmpx < MAX_TEMPS ) schedule -> temps [ tmpx ++ ] = i ; offset -= GET_MODE_SIZE ( mode ) ; entry -> reg = i ; entry -> mode = mode ; entry -> offset = offset ; entry ++ ; } if ( align && current_function_interrupt ) for ( i = LAST_TARGET_REG ; i >= FIRST_TARGET_REG ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { offset -= GET_MODE_SIZE ( DImode ) ; entry -> reg = i ; entry -> mode = DImode ; entry -> offset = offset ; entry ++ ; } } entry -> reg =


<s> size_type getEdgeIndex ( const Edge & E ) const { return std :: distance ( edges_begin ( ) , &


<s> else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = insn_size_16bit ; else * total = insn_size_32bit ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = insn_size_16bit ; else * total = insn_size_32bit ; } else { * total = insn_size_32bit ; } break ; case CONST_DOUBLE : * total = insn_size_32bit * <NUM_LIT> ; break ; case CONST : case SYMBOL_REF : * total = insn_size_32bit * <NUM_LIT> ; break ; default : * total = insn_size_32bit ; break ; } return true


<s> if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel


<s> int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; ++ MBIter ; while ( MBIter != EndIter && VPTInstCnt < <NUM_LIT> ) { NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred != Pred ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBIter -> dump ( ) ) ; ++ VPTInstCnt ; ++ MBIter ; } ; MachineInstrBuilder MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( <STR_LIT> ) ) ; switch ( VPTInstCnt ) { case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: T ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseConstpoolSymbol ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LBrac ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier )


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) || ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO )


<s> for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; int Offset = getRegSpillOffset ( MF , Reg ) ; if ( Offset ) { if ( <STR_LIT> . contains ( Reg ) && StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } Offset -= <STR_LIT> ; int FrameIdx = MFFrame . CreateFixedSpillStackObject ( <NUM_LIT> , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } ZFI -> setRestoreGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; int Offset = getRegSpillOffset ( MF , Reg ) ; if ( StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } } } ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; int CurrOffset = - <STR_LIT> ; if ( usePackedStack ( MF ) ) CurrOffset += StartSPOffset ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg (


<s> return DAG . getNode ( <STR_LIT> , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( <NUM_LIT>


<s> else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops ,


<s> RegSizes [ <STR_LIT> ] = <NUM_LIT> ; RegSizes [ <STR_LIT> ]


<s> if ( isAnyMOVZMovAlias ( Value , RegWidth ) ) return false ; Value = ~ Value ; if ( RegWidth == <NUM_LIT> ) Value &= <NUM_LIT> ; return isMOVZMovAlias ( Value , Shift , RegWidth


<s> assert ( ( Kind == k_Register || Kind == k_CCOut ) && <STR_LIT> ) ; return Reg .


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_cvtusepi64_storeu_epi8 ( void *


<s> gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; if ( is_frame_related ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( dest , gen_rtx_PLUS ( SImode ,


<s> unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF (


<s> if ( FoldedLoad ) MIB . addReg ( Reg ) ; for ( MachineOperand & AfterOp : AfterOps ) MIB . add ( AfterOp ) ; for ( MachineOperand & ImpOp : ImpOps ) { MIB . addReg ( ImpOp . getReg ( ) , getDefRegState ( ImpOp . isDef ( ) ) | RegState :: Implicit | getKillRegState ( ImpOp . isKill ( ) ) | getDeadRegState ( ImpOp . isDead ( ) ) | getUndefRegState ( ImpOp . isUndef ( ) ) ) ; } switch ( DataMI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand & MO0 = DataMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MO1 = DataMI -> getOperand ( <NUM_LIT> ) ; if ( MO1 . getImm ( ) == <NUM_LIT> ) { unsigned NewOpc ; switch ( DataMI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } DataMI -> setDesc ( get ( NewOpc ) ) ; MO1 . ChangeToRegister ( MO0 . getReg ( ) , false ) ; } } } NewMIs . push_back ( DataMI ) ; if ( UnfoldStore ) { const TargetRegisterClass * DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; auto MMOs = extractStoreMMOs ( MI . memoperands ( ) , MF ) ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * DstRC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlign ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( Reg , DstRC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = AddrOps . size ( ) ; i != e ; ++ i ) MIB . add ( AddrOps [ i ] ) ; MIB . addReg ( Reg , RegState :: Kill


<s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasXMM ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> unsigned <ISA_LIT>BaseRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , FrameIndexValue * Value , RegScavenger * RS ) const { unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( FrameReg != <STR_LIT> ) SPAdj = <NUM_LIT> ; Offset += SPAdj ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Done ) return <NUM_LIT> ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( Value ) { Value -> first = FrameReg ; Value -> second = Offset ; } if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function (


<s> assert ( static_cast < size_t > ( cpu_arch ) < ( sizeof ( generic_cpu_name_table ) / sizeof ( generic_cpu_name_table [ <NUM_LIT> ] ) ) ) ; return generic_cpu_name_table [


<s> if ( GR_REGNO_P ( regno ) ) return mode != XFmode && mode != XCmode && mode != RFmode ; if ( AR_REGNO_P ( regno ) ) return mode == DImode ; if ( BR_REGNO_P ( regno ) ) return mode == DImode ; return false


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle

, RM , this ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> :


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Elt ) ) return CN -> isNullValue ( ) ; if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Elt ) ) return CFP -> getValueAPF ( )


<s> Triple TheTriple ( TT ) ; bool isV9 = ( TheTriple . getArch ( ) == Triple :: sparcv9 ) ; if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 =


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return


<s> return ; } RDA -> collectKilledOperands ( Def , Killed ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > BasicBlocks ; for ( auto * MI : Killed ) BasicBlocks . insert ( MI -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; RDA -> getReachingLocalUses ( & MI , <STR_LIT> , ITBlocks [ & MI ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; for ( auto * MI : Killed ) { if ( MachineOperand * MO = MI -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA -> getMIOperand ( MI , * MO ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( MI ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT


<s> return ( float16x8_t ) __builtin_neon_vcvtuv8hi ( ( int16x8_t


<s> m2 = GET_MODE_INNER ( m2 ) ; } msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = <NUM_LIT> ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = <NUM_LIT> ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode )

&& ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ;


<s> static DecodeStatus decodeRrMemoryValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT>


<s> case UNORDERED : ccode = <STR_LIT> ; break ; case ORDERED : ccode = <STR_LIT> ; break ; case UNGE : ccode = <STR_LIT> ; break ; case UNLE : ccode = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } pred = <STR_LIT> ; note = find_reg_note ( insn , REG_BR_PROB , NULL_RTX ) ; if ( note != NULL_RTX ) { int prob = profile_probability :: from_reg_br_prob_note ( XINT ( note , <NUM_LIT> ) ) . to_reg_br_prob_base ( ) - REG_BR_PROB_BASE / <NUM_LIT> ; if ( rs6000_always_hint || ( abs ( prob ) > REG_BR_PROB_BASE / <NUM_LIT> * <NUM_LIT> && ( profile_status_for_fn ( cfun ) != PROFILE_GUESSED ) && br_prob_note_reliable_p ( note ) ) ) { if ( abs ( prob ) > REG_BR_PROB_BASE / <NUM_LIT> && ( ( prob > <NUM_LIT> ) ^ need_longbranch ) ) pred = <STR_LIT> ; else pred = <STR_LIT> ; } } if ( label == NULL ) s += sprintf ( s , <STR_LIT> , ccode , pred ) ; else s += sprintf ( s , <STR_LIT> , ccode , pred ) ; if ( reg_names [ cc_regno + CR0_REGNO ] [ <NUM_LIT> ] == '%'


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT>


<s> auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> Mem . FrontendSize = FrontendSize ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = false ; return Res


<s> ImmutablePass * llvm :: create<ISA_LIT>TargetTransformInfoPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>TTI (


<s> return ( __m128i ) __builtin_ia32_loaddquhi128_mask ( ( const short * ) __P , ( __v8hi ) _mm_setzero_si128


<s> assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize ,


<s> unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits ==


<s> unsigned A15SDOptimizer :: createVExt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned


( adjust_address ( m_tramp , DImode , <NUM_LIT> ) ) ) ) ;


<s> inline bool Pred_t2_so_imm ( SDNode * inN ) const { ConstantSDNode * N = cast < ConstantSDNode


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getSimpleValueType ( ) ; MVT ShufSVT = ShufVT . getVectorElementType ( ) ; int NumElems = ( int ) ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , true , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt == SM_SentinelZero ) return ShufSVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , ShufSVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , ShufSVT ) ; if ( Elt == SM_SentinelUndef ) return DAG . getUNDEF ( ShufSVT ) ; assert ( <NUM_LIT> <= Elt && Elt < ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue NewV = ( Elt < NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth +


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this


<s> if ( isMacho ) return <NUM_LIT> * ( LP64 ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool <ISA_LIT>PostLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer ,

MachineInstr & MI , MachineIRBuilder & B ) const {


<s> auto GetMask = [ & ] ( SDValue V , APInt Mask ) { MVT VT = V . getSimpleValueType ( ) ; SDValue MaskV = DAG . getConstant ( Mask , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V , MaskV ) ; } ; MVT SrlVT = Len > <NUM_LIT> ? VT : <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; SDValue V = Op ; SDValue Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast ( SrlVT , V ) , <NUM_LIT> ) ) ; SDValue And = GetMask ( Srl , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; V = DAG . getNode ( <STR_LIT> , DL , VT , V , And ) ; SDValue AndLHS = GetMask ( V , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast ( SrlVT , V ) , <NUM_LIT> ) ) ; SDValue AndRHS = GetMask ( Srl , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; V = DAG . getNode ( <STR_LIT> , DL , VT , AndLHS , AndRHS ) ; Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast


<s> static void mips_asm_file_end ( void


<s> if ( LT1 . first != <NUM_LIT> || ! LT1 . second . isVector ( ) ) return Cost ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( TLI -> isOperationExpand ( ISD , LT1 . second ) ) return Cost ; if ( Ty2 ) { std :: pair < InstructionCost , MVT > LT2 = TLI -> getTypeLegalizationCost ( DL , Ty2 ) ; if ( LT2 . first != <NUM_LIT> || ! LT2 . second . isVector ( ) ) return Cost ; } return Cost *


<s> case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF ::


<s> return ( uint32x4_t ) ( __a >= <NUM_LIT>


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsi_u64 ( unsigned long long __X ) { return __blsi_u64 ( __X )


<s> static DecodeStatus DecodeSynciR6 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Immediate = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Immediate )


<s> struct register_pass_info f = { p , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; register_pass ( &


<s> static inline bool isUncondBranchOpcode ( int Opc


<s> } if ( Res ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Res . getNode ( ) -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( )


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < <STR_LIT> > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx = - <NUM_LIT> ; if ( ST -> hasNEON ( ) ) Idx = CostTableLookup ( CostTbl , ISDOpcode ,


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind


<s> return new <ISA_LIT>_64GOTEntry ( <NUM_LIT>


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == <NUM_LIT> ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return


<s> SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget . hasBWI ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) && InVTElt != <STR_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || Subtarget . hasBWI ( ) ) ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return getExtendInVec ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) , DAG ) ; return getExtendInVec ( <STR_LIT> , dl , VT , In , DAG ) ; } if ( InVTElt != <STR_LIT> ) return SDValue ( ) ; MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; } else if ( VTElt == <STR_LIT> || VTElt == <STR_LIT> ) { ExtVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; } SDValue V ; if ( Subtarget . hasDQI ( ) ) { V = getExtendInVec ( <STR_LIT> , dl , ExtVT , In , DAG


<s> if ( VT == <STR_LIT> ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT


<s> return MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ; case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V5 ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ; case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ; case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ; case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ; case <STR_LIT> : case <STR_LIT> : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ; case <STR_LIT>


<s> snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . warm_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . warm_name ) ; nds32_emit_section_tail_template ( symbol_name


<s> section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) { fputs ( <STR_LIT>


<s> if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext (


<s> auto & Args = F . getArgumentList ( ) ; for ( auto & Arg : Args ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; ArgInfos . push_back (


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; }


<s> const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset


<s> return __builtin_ia32_cvtss2si64 ( ( __v4sf )


<s> unsigned getSRetReturnReg ( ) const { return


<s> switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) )


<s> if ( Triple ( tm . getTargetTriple ( ) ) . isMacOSX ( ) ) return new <ISA_LIT>DarwinAsmPrinter ( tm


<s> void <ISA_LIT>InstPrinter :: printAddrModeMemSrc ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op1 = MI ->


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O


<s> bool <ISA_LIT>WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = <NUM_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings )


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> ,


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ( ~ __X &


<s> return usePackedStack ( MF ) ? <STR_LIT> - <NUM_LIT> :


<s> NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = false ; break ; case RestrictedIT : RestrictIT = true ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) HasNEONForFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexA710 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : case CortexX1C : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT>


<s> if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE


<s> SMLoc getStartLoc ( ) const override { return


<s> const SCEVAddRecExpr * LSCEVAddRec = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LSCEVAddRec ) continue ; bool DupPref = false ; for ( SmallVector < std :: pair < Instruction * , const SCEVAddRecExpr * > , <NUM_LIT> > :: iterator K = PrefLoads . begin ( ) , KE = PrefLoads . end ( ) ; K != KE ; ++ K ) { const SCEV * PtrDiff = SE -> getMinusSCEV ( LSCEVAddRec , K -> second ) ; if ( const SCEVConstant * ConstPtrDiff = dyn_cast < SCEVConstant > ( PtrDiff ) ) { int64_t PD = std :: abs ( ConstPtrDiff -> getValue ( ) -> getSExtValue ( ) ) ; if ( PD < ( int64_t ) CacheLineSize ) { DupPref = true ; break ; } } } if ( DupPref ) continue ; const SCEV * NextLSCEV = SE -> getAddExpr ( LSCEVAddRec , SE -> getMulExpr ( SE -> getConstant ( LSCEVAddRec -> getType ( ) , ItersAhead ) , LSCEVAddRec -> getStepRecurrence ( * SE ) ) ) ; if ( ! isSafeToExpand ( NextLSCEV , * SE ) ) continue ; PrefLoads . push_back ( std :: make_pair ( MemI , LSCEVAddRec ) ) ; Type * I8Ptr = Type :: getInt8PtrTy ( ( * I ) -> getContext ( ) , PtrAddrSpace ) ; SCEVExpander SCEVE ( * SE , J -> getModule ( ) -> getDataLayout ( ) , <STR_LIT> ) ; Value * PrefPtrValue = SCEVE . expandCodeFor ( NextLSCEV , I8Ptr , MemI ) ; IRBuilder < > Builder ( MemI ) ; Module * M = ( * I ) -> getParent ( ) -> getParent ( ) ; Type * I32 = Type :: getInt32Ty ( ( * I ) -> getContext ( ) ) ; Value * PrefetchFunc = <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall4 ( PrefetchFunc , PrefPtrValue , ConstantInt :: get ( I32 , MemI -> mayReadFromMemory ( ) ? <NUM_LIT> : <NUM_LIT> ) , ConstantInt :: get ( I32 , <NUM_LIT> ) , ConstantInt :: get ( I32 , <NUM_LIT> ) ) ; MadeChange =


<s> for ( auto & Terminator : MBB -> terminators ( ) ) { if ( Terminator . getOpcode ( ) == <STR_LIT> ) return & Terminator ; } return


<s> Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm


<s> int64_t InstrOffs = <NUM_LIT> ; ; int Scale = <NUM_LIT> ; unsigned ImmIdx = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : InstrOffs = MI -> getOperand ( Idx + <NUM_LIT> ) . getImm ( ) ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { const MachineOperand & OffOp = MI -> getOperand ( Idx + <NUM_LIT> ) ; InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; Scale = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ==


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream &


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T ) { HasScatteredSymbols =


<s> asm_fprintf ( file , <STR_LIT> , r9 ) ; asm_fprintf ( file , <STR_LIT> ) ; asm_fprintf ( file , <STR_LIT> , r9 ) ; } else { asm_fprintf ( file , <STR_LIT> , r8 ) ; asm_fprintf ( file , <STR_LIT> ) ; asm_fprintf ( file , <STR_LIT> , r9


<s> unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup


<s> assert ( Kind == Immediate && <STR_LIT>


<s> return selectAddrRiSpls ( Addr , Base , Offset , AluOp , false


<s> using namespace PatternMatch ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Value * PassThru = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; } Root -> replaceAllUsesWith (


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , <NUM_LIT> , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg

) return rs6000_complex_function_value ( mode ) ;


<s> assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( pos + size ) <= <NUM_LIT>


<s> unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#' << formatImm ( Val ) ; if ( Shift != <NUM_LIT> ) { printShifter ( MI , OpNum + <NUM_LIT> , STI , O ) ; if ( CommentStream ) * CommentStream << '=' << formatImm ( Val << Shift ) << '\n' ; } } else { assert ( MO . isExpr ( ) && <STR_LIT>


<s> IsGroupOfZeros = ! Bits [ LastGroupStartIdx ] . hasValue ( ) ; } if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup ( LastValue , LastRLAmt , LastGroupStartIdx , Bits . size ( ) - <NUM_LIT> ) ) ; if ( BitGroups . empty ( ) ) return ; if ( BitGroups . size ( ) > <NUM_LIT> ) { if ( BitGroups [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . EndIdx == Bits . size ( ) - <NUM_LIT> && BitGroups [ <NUM_LIT> ] . V == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . V && BitGroups [ <NUM_LIT> ] . RLAmt ==

BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . RLAmt ) {


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found = true ; } } return Found


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static unsigned SubRegs [ ] = { <STR_LIT>


<s> BOOL hasModRMExtension ; uint8_t instructionClass ; instructionClass = contextForAttrs ( attrMask ) ; hasModRMExtension = modRMRequired ( insn -> opcodeType , instructionClass , insn -> opcode ) ; if ( hasModRMExtension ) { if ( readModRM ( insn ) )


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode ,


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isNullConstant ( RHS ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isOneConstant ( LHS . getOperand ( <NUM_LIT> ) ) && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> )


<s> if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( )


<s> FunctionPass * llvm :: create<ISA_LIT>LDCleanupPass ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>LDCleanup ( )


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned ,


<s> const <ISA_LIT>TargetMachine & getTargetMachine (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT>


<s> bool is64Bit ( ) const { return STI . getTargetTriple ( ) . startswith (


<s> Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; Register Wtemp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * GPRRC = IsFGR64on<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; unsigned MFC1Opc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : ( IsFGR64on<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ; unsigned FILLOpc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; Register Rtemp = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( MFC1Opc ) , Rtemp ) . addReg ( Fs ) ; BuildMI ( * BB , MI , DL , TII -> get ( FILLOpc ) , Wtemp ) . addReg ( Rtemp ) ; unsigned WPHI = Wtemp ; if ( IsFGR64on<ISA_LIT>32 ) { Register Rtemp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Rtemp2 ) . addReg ( Fs ) ; Register Wtemp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register Wtemp3 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( Wtemp ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp3 ) . addReg ( Wtemp2 ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; WPHI =


<s> dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , <NUM_LIT> ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest


<s> inline void vec_dststt ( void * a1 , int


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != REG ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; return CONSTANT_P (


<s> MachineBasicBlock * SinglePredMBB = getSingleSchedPred ( MBB , MLI -> getLoopFor ( MBB ) ) ; if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; for ( MachineBasicBlock :: iterator I = SinglePredMBB -> getFirstTerminator ( ) ; I != SinglePredMBB -> end ( ) ; I ++ ) { DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; bool TakenBranch = ( I -> isBranch ( ) && ( TII -> getBranchInfo ( * I ) . Target -> isReg ( ) || TII -> getBranchInfo ( * I ) . Target -> getMBB ( ) == MBB ) ) ; HazardRec -> emitInstruction ( & * I , TakenBranch ) ; if ( TakenBranch )


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectShiftB_64 ( const MachineOperand & Root ) const { auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None || * MaybeImmed > <NUM_LIT> ) return None ; uint64_t Enc = <NUM_LIT> - * MaybeImmed ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Enc ) ;


<s> unsigned getArgumentStackToRestore ( ) const { return ArgumentStackToRestore


<s> switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; unsigned VReg = MF . addLiveIn ( <STR_LIT> [ I


<s> Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } else


<s> <ISA_LIT>ExprKind Kind ; return isGpOff (


<s> UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI -> getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT> ,


<s> MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst , CoverageInfo ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get (

TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ;


<s> isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { return false


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( RAOffset ) . addReg


<s> if ( Imm . isNegZero ( ) ) return false ; return Imm .


<s> unsigned LaneWidth = getVectorTyFromPredicateVector ( VecVT ) . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Conv , DAG . getConstant ( Lane * LaneWidth , dl , <STR_LIT> ) ) ; return Shift


<s> auto S = bit_cast < std :: array < int32_t , <NUM_LIT> >> ( Imm ) ; auto H = bit_cast < std :: array < int16_t , <NUM_LIT> >> ( Imm ) ; auto B = bit_cast < std :: array < int8_t , <NUM_LIT> >> ( Imm ) ; if ( isSVEMaskOfIdenticalElements < int32_t > ( Imm ) && isSVECpyImm < int32_t > ( S [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int16_t > ( Imm ) && isSVECpyImm < int16_t > ( H [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int8_t > ( Imm ) && isSVECpyImm < int8_t > ( B [ <NUM_LIT> ] ) ) return false ; return isLogicalImmediate ( Imm


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return false ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > (


<s> return false ; } if ( matchADDRrr ( Addr , LHS , RHS ) ) { if ( matchADDRri ( RHS , Index , Offset ) ) { Base = LHS ; return true ; } if ( matchADDRri ( LHS , Base , Offset ) ) { Index = RHS ; return true ; } Base = LHS ; Index = RHS ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; Inst . addOperand ( MCOperand :: createImm ( (


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI

, raw_ostream & OS , StringRef Annot ) {


<s> case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: AppendingLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: DLLExportLinkage : DLLExportedGVs . insert ( name ) ; case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << <STR_LIT> ; case GlobalValue :: InternalLinkage : SwitchToSection ( TAI -> getDataSection ( ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ! bCustomSegment ) EmitAlignment ( Align , I ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> << I -> getName ( ) ; O << '\n' ; EmitGlobalConstant ( C ) ; if ( bCustomSegment ) O << name << <STR_LIT> ; } if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) ) { SwitchToDataSection ( <STR_LIT> ) ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> ; } for ( StringSet < > :: iterator i = DLLExportedGVs . begin ( ) , e = DLLExportedGVs . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; for ( StringSet < > :: iterator i = DLLExportedFns . begin ( ) , e = DLLExportedFns . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) )


<s> return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( Op , LD -> getBasePtr ( ) , Base , Scale , Index , Disp ) ) return false ; OutChain = LD ->


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBUtils -> adjustBBSize ( CPEBB , - Size ) ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( Align ::


<s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMSA ( ) ) return SDValue ( ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ! Ty . is128BitVector ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> && Op1 -> getOpcode ( ) == <STR_LIT> ) { SDValue Op0Op0 = Op0 -> getOperand ( <NUM_LIT> ) ; SDValue Op0Op1 = Op0 -> getOperand ( <NUM_LIT> ) ; SDValue Op1Op0 = Op1 -> getOperand ( <NUM_LIT> ) ; SDValue Op1Op1 = Op1 -> getOperand ( <NUM_LIT> ) ; bool IsLittleEndian = ! Subtarget -> isLittle ( ) ; SDValue IfSet , IfClr , Cond ; bool IsConstantMask = false ; APInt Mask , InvMask ; if ( isVSplat ( Op0Op0 , Mask , IsLittleEndian ) ) { Cond = Op0Op0 ; IfSet = Op0Op1


<s> MCRelocationInfo * llvm :: create<ISA_LIT>MachORelocationInfo ( MCContext & Ctx ) { return new <ISA_LIT>MachORelocationInfo (


<s> assert ( ( MRI -> getVRegDef ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) == & CmpValDefInstr ) && <STR_LIT> ) ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; MachineInstr * VregDefInstr = MRI -> getVRegDef ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( VregDefInstr && <STR_LIT>


<s> void emitDefCFAOffsets ( MachineModuleInfo & MMI , MachineBasicBlock & MBB , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset -= Info .


<s> if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT>


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != -


<s> SDLoc DL ( Op ) ; if ( SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT . getScalarType ( ) ) ) ; if ( SrcElementWidth < SatWidth || SrcElementVT == <STR_LIT> ) return SDValue ( ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , IntVT , SrcVal , DAG . getValueType ( IntVT . getScalarType ( ) ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sext ( SrcElementWidth ) , DL , IntVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , IntVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sext ( SrcElementWidth ) , DL , IntVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , IntVT , Min ,


<s> unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get


<s> if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetIOS ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( )


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void *


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else { MRI . setPhysRegUnused ( <STR_LIT>


<s> bool <ISA_LIT>ElimCompare :: convertToLoadAndTest ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = TII -> getLoadAndTest ( MI . getOpcode ( ) ) ; if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; auto MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get (


<s> emit_insn ( gen_load_toc_v4_PIC_1 ( lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_3b ( tmp2 , tmp1 , got , lab ) ) ; emit_insn ( gen_load_toc_v4_PIC_3c ( dest , tmp2 , got , lab ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { emit_insn ( gen_load_toc_v4_pic_si ( ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_insn ( gen_load_toc_v4_PIC_1 ( symF ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ; } else { rtx tocsym , lab ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( toc_label_name ) ) ; need_toc_init = <NUM_LIT> ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tocsym , lab ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( dest , dest , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; } emit_insn ( gen_addsi3 ( dest , temp0


<s> } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode >


<s> void <ISA_LIT>AIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor (


<s> if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT> )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarryx_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) { return __builtin_ia32_addcarryx_u64 ( __CF , __X


<s> for ( unsigned I = <NUM_LIT> ; I < NumElts ; I ++ ) { SDValue OpI = Op . getOperand ( I ) ; if ( OpI . getOpcode ( ) != <STR_LIT> || OpI . getOperand ( <NUM_LIT> ) != Op0 || ! isa < ConstantSDNode > ( OpI . getOperand ( <NUM_LIT> ) ) || OpI . getConstantOperandVal ( <NUM_LIT> ) != I * N ) return SDValue ( ) ; } SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op0 , DAG .


<s> int nb , ne ; return rs6000_is_valid_mask ( mask , & nb , & ne , mode ) && nb


<s> bool selectBDAddr12Only ( SDValue Addr , SDValue & Base


<s> return ( uint32x4_t ) __builtin_aarch64_uhaddv4si ( ( int32x4_t )


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT>


<s> bool IsTailPredicationLegal ( ) const { return ! Revert && FoundAllComponents ( ) && VCTP && ! CannotTailPredicate && ML . getNumBlocks ( )


<s> void <ISA_LIT>InstPrinter :: printCPURegs ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> unsigned char OpFlag = Subtarget . classifyLocalReference ( nullptr ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; SDLoc DL ( JT )