<s> if ( MO . isRegMask ( ) ) { const uint32_t * RegMask = MO . getRegMask ( ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; continue ; } if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; int Idx = mapRegToGPRIndex ( MO . getReg ( ) ) ; if ( Idx < <NUM_LIT> ) continue ; handleClobber ( LOHInfos [ Idx ] ) ; } SmallSet < int , <NUM_LIT> > UsesSeen ; for ( const MachineOperand & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . readsReg ( ) ) continue ; int Idx = mapRegToGPRIndex ( MO . getReg ( ) ) ; if ( Idx < <NUM_LIT> ) continue ; if ( ! UsesSeen . count ( Idx ) ) { handleUse ( MI , MO , LOHInfos [


<s> case <NUM_LIT> : if ( A -> getSize ( ) == <NUM_LIT> ) { if ( B == & <STR_LIT> ) return & <STR_LIT> ; assert ( B == & <STR_LIT> && <STR_LIT> ) ; if ( A == & <STR_LIT> ) return A ; return & <STR_LIT> ; } assert ( A -> getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( B == & <STR_LIT> ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : case


<s> if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const LLVM_OVERRIDE { return


<s> unsigned internalKnownBits ( ) const { return Unalign ? Unalign :


<s> const <ISA_LIT>MCExpr * HighestExpr = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST , Symbol , getContext ( ) ) ; const <ISA_LIT>MCExpr * HigherExpr = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER , Symbol , getContext ( ) ) ; if ( UseSrcReg && getContext ( ) . getRegisterInfo ( ) -> isSuperOrSubRegisterEq ( DstReg , SrcReg ) ) { emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , Instructions ) ; emitRRR ( <STR_LIT> , DstReg , ATReg , SrcReg , IDLoc , Instructions ) ; return false ; } emitRX ( <STR_LIT> , DstReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , Instructions ) ; emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , DstReg , DstReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRR ( <STR_LIT> , DstReg , DstReg , ATReg , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg , DstReg , SrcReg , IDLoc , Instructions ) ; return false ; } unsigned TmpReg = DstReg ; if ( UseSrcReg && getContext ( ) . getRegisterInfo ( ) -> isSuperOrSubRegisterEq ( DstReg , SrcReg ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } emitRX ( <STR_LIT> , TmpReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; else assert ( getContext ( ) . getRegisterInfo ( ) ->

isSuperOrSubRegisterEq ( DstReg , TmpReg ) ) ;


<s> static inline __ev64_opaque__ __ev_create_u64 ( uint64_t a ) { union { __ev64_opaque__ v ; uint64_t i ; } u ; u . i = a ; return u .


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> vld1q_p16 ( const poly16_t * a ) { return ( poly16x8_t ) __builtin_aarch64_ld1v8hi ( ( const __builtin_aarch64_simd_hi * )


<s> SMLoc OffsetOfLoc = Start ; Parser . Lex ( ) ; Start = Parser . getTok ( ) . getLoc ( ) ; assert ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; SMLoc


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask ) { SmallBitVector UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , false , false ) ) return false ; for ( APInt Elt : EltBits ) RawMask . push_back ( Elt . getZExtValue


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( ABI . IsN32 ( ) ) { const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg (

V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ;


<s> else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) )


<s> bool <ISA_LIT>FastISel :: SelectSIToFP ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; const Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand (


<s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset (


<s> rtx insns , insn ; if ( current_function_calls_eh_return || current_function_calls_setjmp || current_function_has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ; else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN ,

DAG . getConstant ( - SarConst , DL , CVT ) ) ;


<s> if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL


<s> SDValue ExtendOpA , ExtendOpB ; SDValue ShiftOp0 = Shift . getOperand ( <NUM_LIT> ) ; unsigned ShiftOp0Opc = ShiftOp0 . getOpcode ( ) ; if ( ShiftOp0Opc == <STR_LIT> ) { SDValue Xor = ShiftOp0 . getOperand ( <NUM_LIT> ) ; if ( Xor . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; uint64_t C ; if ( ! isAllConstantBuildVector ( Xor . getOperand ( <NUM_LIT> ) , C ) ) return SDValue ( ) ; unsigned ElemSizeInBits = VT . getScalarSizeInBits ( ) ; APInt CAsAPInt ( ElemSizeInBits , C ) ; if ( CAsAPInt != APInt :: getAllOnes ( ElemSizeInBits ) ) return SDValue ( ) ; ExtendOpA = Xor . getOperand ( <NUM_LIT> ) ; ExtendOpB = ShiftOp0 . getOperand ( <NUM_LIT> ) ; } else if ( ShiftOp0Opc == <STR_LIT> ) { ExtendOpA = ShiftOp0 . getOperand ( <NUM_LIT> ) ; ExtendOpB = ShiftOp0 . getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; unsigned ExtendOpAOpc = ExtendOpA . getOpcode ( ) ; unsigned ExtendOpBOpc = ExtendOpB . getOpcode ( ) ; if ( ! ( ExtendOpAOpc == ExtendOpBOpc && ( ExtendOpAOpc == <STR_LIT> || ExtendOpAOpc == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue OpA = ExtendOpA . getOperand ( <NUM_LIT> ) ; SDValue OpB = ExtendOpB . getOperand ( <NUM_LIT> ) ; EVT OpAVT = OpA . getValueType ( ) ; assert ( ExtendOpA . getValueType ( ) == ExtendOpB . getValueType ( ) ) ; if ( ! ( VT == OpAVT && OpAVT == OpB . getValueType ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; bool IsSignExtend = ExtendOpAOpc == <STR_LIT> ; bool IsRHADD = ShiftOp0Opc == <STR_LIT> ; unsigned HADDOpc = IsSignExtend ? ( IsRHADD ? <STR_LIT> : <STR_LIT> ) : ( IsRHADD ? <STR_LIT> : <STR_LIT> ) ; SDValue ResultHADD = DAG . getNode ( HADDOpc , DL , VT ,


<s> HOST_WIDE_INT no_flag = flags [ i ] . no_flag ; if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) { HOST_WIDE_INT dep_flags = flags [ i ] . dep_flags ; HOST_WIDE_INT set_flags = ( rs6000_isa_flags_explicit & rs6000_isa_flags & dep_flags ) ; if ( set_flags ) { for ( j = <NUM_LIT> ; j < ARRAY_SIZE ( rs6000_opt_masks ) ; j ++ ) if ( ( set_flags & rs6000_opt_masks [ j ] . mask ) != <NUM_LIT> ) { set_flags &= ~ rs6000_opt_masks [ j ] . mask ; error ( <STR_LIT> , flags [ i ] . name , rs6000_opt_masks [ j ] .


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : if ( _system_configuration . version == <NUM_LIT> ) return <STR_LIT> ; else return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> assert ( VT . isFloatingPoint ( ) ) ; return


<s> static inline bool isAdvSIMDModImmType7 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ; MI . getOperand ( OpNo + <NUM_LIT>


<s> __inline__ static unsigned long long sh_media_MCMPEQ_W ( unsigned long long mm , unsigned long long mn ) { unsigned long


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i = interrupt_handler ? LAST_BANKED_REG + <NUM_LIT> : <NUM_LIT> ; int skip_fpscr = <NUM_LIT> ; for ( ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = <NUM_LIT> ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = <NUM_LIT> ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + <NUM_LIT> ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * <NUM_LIT> ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - <NUM_LIT> ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA ,


<s> enum rtx_code code = GET_CODE ( x ) ; if ( code == MULT && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && exact_log2 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) > <NUM_LIT> ) return true ; if ( code == ASHIFT )


<s> MachineInstr :: mmo_iterator MMOBegin = MI . memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI . memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BP = ( PVT == <STR_LIT> ) ? <STR_LIT> : ( Subtarget . isSVR4ABI ( ) && isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT>


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) ,

ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( imm8 ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( imm8 == <NUM_LIT> && pred != <NUM_LIT> && ( ( FeatureBits [ <STR_LIT> ] ) != <NUM_LIT> ) ) S = MCDisassembler


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions (


<s> } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , <NUM_LIT> , <NUM_LIT> ) ; } } unsigned const Max = ( NumStores ? ( <NUM_LIT> / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = <NUM_LIT> ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= <NUM_LIT> ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = <NUM_LIT> ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . AllowExpensiveTripCount = true ; UP . Force =


<s> if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; return ( VT1 . getSizeInBits ( ) > VT2 .


<s> if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << Extract -> getConstantOperandVal ( <NUM_LIT> ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( SrcVT ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) ) ; EVT ElementType = SrcVT . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t Offset = EltSize * i ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue OffsetVal = DAG . getConstant ( Offset , dl , PtrVT ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , OffsetVal ) ; Vals [ i ] = DAG . getLoad ( ElementType , dl , Ch , ScalarAddr , MachinePointerInfo (


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align


<s> static DecodeStatus DecodePOP75GroupBranchMMR6 ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; bool HasRs


<s> bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; bool CallConv = MF . getFunction ( ) .

getCallingConv ( ) != CallingConv :: GHC ;


<s> unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( Rt == Rt2 ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address


<s> return ( __m512i ) __builtin_ia32_pbroadcastq512 ( ( __v2di ) __A , (

__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TM . getFrameLowering


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; int64_t Imm = UseSExt ? CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ; return ImmReg


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; Op2 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 ,

Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ;


<s> void <ISA_LIT>ConstantPoolMBB :: print ( raw_ostream & O ) const { O << <STR_LIT> << MBB -> getNumber ( ) ; <ISA_LIT>ConstantPoolValue :: print (


<s> SDValue True = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * TrueC = dyn_cast < ConstantSDNode > ( True ) ; if ( ! TrueC || ! True . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; if ( True . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; int64_t Diff = TrueC -> getSExtValue ( ) - FalseC -> getSExtValue ( ) ; if ( Diff == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , SetCC . getValueType ( ) , SetCC , False ) ; if ( Diff == - <NUM_LIT> ) { <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , true ) ) ; return DAG . getNode ( <STR_LIT> , DL , SetCC . getValueType


<s> const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( S


<s> error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } if ( lang_GNU_C ( ) && VECTOR_BOOLEAN_TYPE_P ( type ) ) type = build_variant_type_copy ( type ) ; else type = build_distinct_type_copy (


<s> SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( GV -> isDeclaration ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = VT . isFloatingPoint ( ) ; break ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , SVOp -> getMask ( ) ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { if ( SDValue Elt = getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) { Elts . push_back ( Elt ) ; continue ; } Elts . clear ( ) ; break ; } if ( Elts . size ( ) == VT . getVectorNumElements ( ) ) if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , Subtarget , true ) ) return LD ; if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT>


<s> CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else


<s> if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } MCContext & Context = TOut . getStreamer ( ) . getContext ( ) ; MCSymbol * BrTarget ; MCOperand LabelOp ; if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; } else { BrTarget = Context . createTempSymbol ( ) ; LabelOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( BrTarget , Context ) ) ; TOut . emitRRX ( <STR_LIT> , RtReg , ZeroReg , LabelOp , IDLoc , STI ) ; } TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; if ( ! UseTraps ) TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; if ( ! Signed ) { if ( ! UseTraps ) TOut . getStreamer ( ) . EmitLabel ( BrTarget ) ; TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( ! UseTraps ) TOut . getStreamer ( ) . EmitLabel


<s> loongarch_emit_move ( mem , reg ) ; loongarch_set_frame_expr ( loongarch_frame_set ( mem , reg )


<s> case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; } base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_8 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32


<s> return Cand . SU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> || Cand . SU ->

getInstr ( ) -> getOpcode ( ) == <STR_LIT> ;


<s> auto MBBStart = MBB -> instr_rend ( ) ; for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op . isDef ( ) ) ) return & * MI ; return nullptr


<s> if ( ! LiveRegs . contains ( <STR_LIT> ) && shortenOn001 ( MI , Opcode ) ) { MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . addReg ( <STR_LIT> , RegState


<s> if ( MayFoldLoad && N1 -> getOpcode ( ) == <STR_LIT> && N1 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N1 . getNode ( ) , N1 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N1 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( Load . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < LoadSDNode > ( Load ) -> getMemOperand ( ) ; CNode -> setMemRefs ( MemOp , MemOp +


<s> if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm


<s> if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return <STR_LIT> ; assert ( ! isTargetCOFF ( ) ) ; const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) )


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow (


<s> DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; DReg = getCorrespondingDRegAndLane ( TRI , SrcReg , Lane ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB . addReg ( DstReg , RegState :: Define ) . addReg ( DReg , RegState :: Undef ) . addImm ( Lane ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; break ; case <STR_LIT> : { if ( Domain != ExeNEON ) break ; assert ( ! isPredicated ( MI ) && <STR_LIT> ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DReg = getCorrespondingDRegAndLane ( TRI , DstReg , Lane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DReg , Lane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DReg , RegState :: Define ) . addReg ( DReg , getUndefRegState ( ! MI -> readsRegister ( DReg , TRI ) ) ) . addReg ( SrcReg ) . addImm ( Lane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc


<s> SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD ->

isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ;


<s> static SDValue getGeneralPermuteNode ( SelectionDAG & DAG , SDLoc DL , SDValue * Ops , const SmallVectorImpl < int > & Bytes ) { for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) Ops [ I ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ I ] ) ; unsigned StartIndex , OpNo0 , OpNo1 ; if ( isShlDoublePermute ( Bytes , StartIndex , OpNo0 , OpNo1 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ OpNo0 ] , Ops [ OpNo1 ] , DAG . getConstant ( StartIndex , DL , <STR_LIT> ) ) ; SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= <NUM_LIT> )

IndexNodes [ I ] = DAG . getConstant ( Bytes [ I ] , DL , <STR_LIT> ) ;


<s> InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; bool HasRs = false ; bool HasRt = false ; if ( Rt == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs == <NUM_LIT>


<s> case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT>


<s> IntegerCompareEliminator ( SelectionDAG * DAG , <ISA_LIT>DAGToDAGISel * Sel ) : CurDAG ( DAG ) , S ( Sel ) { assert ( CurDAG -> getTargetLoweringInfo ( ) . getPointerTy ( CurDAG -> getDataLayout ( ) ) . getSizeInBits ( ) ==


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeS2Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { printThumbAddrModeRI5Operand ( MI , Op , O ,


<s> bool <ISA_LIT>TargetLowering :: shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const { return ! Subtarget -> optForMinSize ( )


<s> if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size = ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode )


<s> const ImmTLSOp getImmTLS ( ) const { assert ( Kind == KindImmTLS && <STR_LIT> ) ; return


<s> for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) { Parser . Lex ( ) ; } else return true ; } return false


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> MVT InVT = In . getSimpleValueType ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ExtVT = VT ; if ( ! Subtarget . hasBWI ( ) && ( VT . getVectorElementType ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) ExtVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; AttributeSet FnAttrs = MF -> getFunction ( ) -> getAttributes ( ) ; bool <ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool No<ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( <ISA_LIT>16Attr && No<ISA_LIT>16Attr ) && <STR_LIT> ) ; if ( <ISA_LIT>16Attr ) Subtarget


<s> if ( MI . isBundle ( ) ) return <NUM_LIT> ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) { return


<s> void <ISA_LIT>PostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; HazardRec . setDAG ( dag ) ; HazardRec . Reset ( )


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > Killed = { LoLoop . Start , LoLoop . Dec , LoLoop . End } ; if ( ! TryRemove ( Def , * RDA , LoLoop . ToRemove

, Killed ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> static bool IsRegAbsolute ( unsigned Reg ) { const bool RestrictR15 = FlagRestrictR15 ; assert ( FlagUseZeroBasedSandbox || RestrictR15 ) ; return ( Reg == <STR_LIT> || Reg == <STR_LIT> ||


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro


<s> if ( ShiftAmt == <NUM_LIT> && Subtarget . hasSSE42 ( ) ) { assert ( ( VT != <STR_LIT> || Subtarget . hasInt256 ( ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , R ) ; } if ( ShiftAmt >= <NUM_LIT> ) { SDValue Upper = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , <NUM_LIT> , DAG ) ; SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , ShiftAmt - <NUM_LIT> , DAG ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } else { SDValue Upper = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , ShiftAmt , DAG ) ; SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; Lower = DAG . getBitcast ( ExVT , Lower ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return DAG . getBitcast ( VT , Ex ) ; } ; APInt APIntShiftAmt ; if ( ! <STR_LIT> ( Amt , APIntShiftAmt ) ) return SDValue ( ) ; if ( APIntShiftAmt . uge ( VT . getScalarSizeInBits ( ) ) ) return DAG . getUNDEF ( VT ) ; uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; if ( SupportedVectorShiftWithImm ( VT , Subtarget , Op . getOpcode ( ) ) ) return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl , VT , R , ShiftAmt , DAG ) ; if ( ( ( ! Subtarget . hasXOP ( ) && VT == <STR_LIT> ) || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) ) && Op . getOpcode ( ) == <STR_LIT> ) return ArithmeticShiftRight64 ( ShiftAmt ) ; if ( VT == <STR_LIT> || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && VT == <STR_LIT> ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ShiftVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) return

DAG . getNode ( <STR_LIT> , dl , VT , R , R ) ;


<s> case <STR_LIT> : return PerformFNEGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTRUNCATECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return performFMaxNumCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return LowerSymbolOperand ( MI , MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : return LowerSymbolOperand ( MI , MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand


<s> unsigned RegNum ; if ( getVPTPred ( ) == <STR_LIT> ) { RegNum = <NUM_LIT> ; } else { unsigned NextOpIndex = Inst . getNumOperands ( ) ; const MCInstrDesc & MCID = <ISA_LIT>Insts [ Inst . getOpcode ( ) ] ; int TiedOp = MCID . getOperandConstraint ( NextOpIndex , MCOI :: TIED_TO ) ; assert ( TiedOp >= <NUM_LIT>


<s> DebugLoc DL = N -> getDebugLoc ( ) ; if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; SDValue NewMul ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT ,

NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , <STR_LIT> ) ) ;


<s> else emit_insn ( gen_insv_immdi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } mask = <NUM_LIT> ; zero_match = ( ( val & mask ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; one_match = ( ( ~ val & mask ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; if ( zero_match != <NUM_LIT> && one_match != <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> , mask <<= <NUM_LIT> ) { val2 = val & ~ mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val | mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val2 & ~ mask ; val2 = val2 | ( ( ( val2 >> <NUM_LIT> ) | ( val2 << <NUM_LIT> ) ) & mask ) ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; } if ( i != <NUM_LIT> ) { if ( generate ) { emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val2 ) ) ) ; emit_insn ( gen_insv_immdi ( dest , GEN_INT ( i ) , GEN_INT ( ( val >> i ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } } num_insns = <NUM_LIT> ; mask = <NUM_LIT> ; val2 = one_match > zero_match ? ~ val : val ; i = ( val2 & mask ) != <NUM_LIT> ? <NUM_LIT> : ( val2 & ( mask << <NUM_LIT> ) ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( generate ) emit_insn ( gen_rtx_SET ( dest , GEN_INT ( one_match > zero_match ? ( val | ~ ( mask << i ) ) : ( val & ( mask << i ) ) ) ) ) ; for ( i += <NUM_LIT> ; i < <NUM_LIT> ; i


<s> case VK_AARCH64_DTPREL_G1 : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_G1_NC : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_G0 : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_G0_NC : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_HI12 : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_LO12 : OS << <STR_LIT> ; break ; case VK_AARCH64_DTPREL_LO12_NC : OS << <STR_LIT> ; break ; case VK_AARCH64_GOTTPREL_G1 : OS << <STR_LIT> ; break ; case VK_AARCH64_GOTTPREL_G0_NC : OS << <STR_LIT> ; break ; case VK_AARCH64_GOTTPREL : OS << <STR_LIT> ; break ; case VK_AARCH64_GOTTPREL_LO12 : OS << <STR_LIT> ; break ; case VK_AARCH64_TPREL_G2 : OS << <STR_LIT> ; break ; case VK_AARCH64_TPREL_G1 : OS <<


<s> else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG (


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) )


<s> Value * VecOp = II . getOperand ( <NUM_LIT> ) ; Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * PtrOp = II . getOperand ( <NUM_LIT> ) ; Value * VecPtr = Builder . CreateBitCast ( PtrOp , VecOp -> getType ( ) -> getPointerTo ( ) ) ; if ( isAllActivePredicate ( Pred ) ) { StoreInst * Store = Builder . CreateStore ( VecOp ,


<s> N1 = DAG . getNode ( <STR_LIT> , dl , ShufVT , N1 ) ; N1 = getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; return DAG . getBitcast ( VT , N1 ) ; } } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } assert ( N1 . getValueType ( ) != <STR_LIT> && <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , DAG . getTargetConstant ( IdxVal << <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return Op ; } return SDValue


<s> static bool can_avoid_literal_pool_for_label_p ( rtx x ) { if ( arm_disable_literal_pool && SYMBOL_REF_P ( x ) && CONSTANT_POOL_ADDRESS_P ( x


<s> IsEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( GV -> hasLocalLinkage ( ) ) return false ; if ( ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GV -> getType (


<s> DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn ,


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return


<s> if ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ) { unsigned DSub0 = createExtractSubreg ( MBB , InsertPt , DL , Reg , <STR_LIT> , & <STR_LIT> ) ; unsigned DSub1 = createExtractSubreg ( MBB , InsertPt , DL , Reg , <STR_LIT> , & <STR_LIT> ) ; unsigned Out1 = createDupLane ( MBB , InsertPt , DL , DSub0 , <NUM_LIT> ) ; unsigned Out2 = createDupLane ( MBB , InsertPt , DL , DSub0 , <NUM_LIT> ) ; Out = createVExt ( MBB , InsertPt , DL , Out1 , Out2 ) ; unsigned Out3 = createDupLane ( MBB , InsertPt , DL , DSub1 , <NUM_LIT> ) ; unsigned Out4 = createDupLane ( MBB , InsertPt , DL , DSub1 , <NUM_LIT> ) ; Out2 = createVExt ( MBB , InsertPt , DL , Out3 , Out4 ) ; Out = createRegSequence ( MBB , InsertPt , DL , Out , Out2 ) ; } else if ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ) { unsigned Out1 = createDupLane ( MBB , InsertPt , DL , Reg , <NUM_LIT> ) ; unsigned Out2 = createDupLane ( MBB , InsertPt , DL , Reg , <NUM_LIT> ) ; Out = createVExt ( MBB , InsertPt , DL , Out1 , Out2 ) ; } else { assert ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; unsigned PrefLane = getPrefSPRLane ( Reg ) ; unsigned Lane ; switch ( PrefLane ) { case <STR_LIT> : Lane = <NUM_LIT> ; break ; case <STR_LIT> : Lane = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT>


<s> CombinerHelper Helper ( Observer , B ) ; switch ( MI . getOpcode ( ) ) { default : return false ; case TargetOpcode :: COPY : return Helper . tryCombineCopy ( MI ) ; case TargetOpcode :: G_BR : return Helper . tryCombineBr ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode ::


<s> PointerSize = ( is64Bit && ! isX32 && ! isNaCl ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation =


<s> return true ; case <STR_LIT> : case <STR_LIT> : return STI -> isTargetDarwin ( ) || ReserveX18 ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ; case <STR_LIT> : case <STR_LIT> : return hasBasePointer ( MF ) ; } return


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset

, bool MemcpyStrSrc , MachineFunction & MF ) const {


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpins32 ( unsigned int data2 , unsigned int data1 , unsigned int flags ) { return __builtin_ia32_lwpins32 ( data2 , data1 , flags


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective (


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReferencePreferSP ( const MachineFunction & MF , int FI , Register & FrameReg , bool IgnoreSPUpdates ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI .


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn , REG_CFA_WINDOW_SAVE , const0_rtx


<s> case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , false ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , true ) ; case <STR_LIT> : case <STR_LIT> : return ExpandMOVImmSExti8 ( MIB , * this , Subtarget ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskState = getRegState ( MIB -> getOperand ( <NUM_LIT> ) ) ; unsigned Opc = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . RemoveOperand ( <NUM_LIT> ) ; MIB -> setDesc ( get ( Opc ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( MaskReg , MaskState ) . addReg ( Reg , RegState :: Undef ) . addReg (


<s> static DecodeStatus DecodeDEXT ( MCInst & MI , InsnType Insn , uint64_t Address , const void * Decoder ) { unsigned Msbd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Lsb = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Size = <NUM_LIT> ; unsigned Pos = <NUM_LIT> ; bool IsMicro<ISA_LIT> = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : IsMicro<ISA_LIT> = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Pos = Lsb ; Size = Msbd + <NUM_LIT> ; break ; case <STR_LIT> : IsMicro<ISA_LIT> = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Pos = Lsb ; Size = Msbd + <NUM_LIT> + <NUM_LIT> ; break ; case <STR_LIT> : IsMicro<ISA_LIT> = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MI . setOpcode ( IsMicro<ISA_LIT> ? <STR_LIT> :


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT>


<s> setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = getContext ( ) . getObjectFileInfo ( )


<s> if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , & Fast ) && Fast ) ) ) { return


<s> return & InstrInfo . getRegisterInfo ( )


<s> set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != const0_rtx ) ) return false ; break ; case CCmode : if ( req_mode == CCGCmode ) return false ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return false ; case CCGOCmode : if ( req_mode == CCZmode ) return false ; case CCZmode : break ; case CCAmode : case


<s> bool isToken ( ) const { return Kind ==


<s> assert ( MRI ) ; int DeadNZCVIdx = CmpInstr -> findRegisterDefOperandIdx ( <STR_LIT> , true ) ; if ( DeadNZCVIdx != - <NUM_LIT> ) { if ( CmpInstr -> definesRegister ( <STR_LIT> ) || CmpInstr -> definesRegister ( <STR_LIT> ) ) { CmpInstr -> eraseFromParent ( ) ; return true ; } unsigned Opc = CmpInstr -> getOpcode ( ) ; unsigned NewOpc = convertFlagSettingOpcode ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr -> setDesc ( MCID ) ; CmpInstr -> RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( CmpValue != <NUM_LIT> || SrcReg2 != <NUM_LIT> )


<s> for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) != ( Mask [

<NUM_LIT> ] < <NUM_LIT> ) ) return false ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm )


<s> if ( recog_memoized ( insn ) == CODE_FOR_tlscall ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_BASE || XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_UNIFIED ) ) return true ; } rtx set = single_set ( insn ) ; if ( set


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return ; <ISA_LIT>FunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; PFI -> setIsSplitCSR ( true


<s> SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ; ReplaceUses ( SDValue ( N , ChainIdx ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> bool getPreservesR0 ( ) const { return PreservesR0


<s> x = gen_rtx_SET ( VOIDmode , x , src ) ; add_reg_note ( insn , REG_CFA_OFFSET ,


<s> assert ( isVPTPred ( ) && <STR_LIT> ) ; return VCC . Val


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII .


<s> uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; bool ValidNamed


<s> bool isU6Imm ( ) const { return isImm ( <NUM_LIT> , <NUM_LIT>


<s> <STR_LIT> ArgFlags = Ins [ i ] . Flags ; if ( IsRet ) { if ( RetCC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; } } else { if ( CC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign ::


<s> if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget


<s> for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ) { MachineBasicBlock & B = * I ++ ; Changed |= processBlock ( B


<s> const char * aarch64_sls_barrier ( int mitigation_required ) { return mitigation_required ? ( TARGET_SB ?


<s> if ( ! isGPRMem ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . ShiftType != <STR_LIT> || Memory .


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) )


<s> else this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( delta ) emit_insn ( gen_add3_insn ( this_rtx , this_rtx , GEN_INT ( delta ) ) ) ; if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( ( ( unsigned HOST_WIDE_INT ) vcall_offset ) + <NUM_LIT> >= <NUM_LIT> ) { emit_insn ( gen_add3_insn ( tmp , tmp , vcall_offset_rtx ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; } else { rtx loc = gen_rtx_PLUS ( Pmode , tmp , vcall_offset_rtx ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns (


<s> unsigned OperandsBeginIdx = <NUM_LIT> ; assert ( FK < FaultMaps :: FaultKindMax && <STR_LIT> ) ; FM . recordFaultingOp ( FK , HandlerLabel ) ; MCInst MI ; MI . setOpcode ( Opcode ) ; if ( DefRegister != <STR_LIT> ) MI . addOperand ( MCOperand :: createReg ( DefRegister ) ) ; for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand .


<s> SDValue extLoad = DAG . getNode ( Opcode , SDLoc ( newLoad ) , LD -> getValueType ( <NUM_LIT> ) , newLoad ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , extLoad ) ; return newLoad ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getBuildVector ( <STR_LIT> , SDLoc ( N ) , { BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) } ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT .


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( - CE -> getValue (


<s> case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ; ret = <NUM_LIT>


<s> fprintf ( file , <STR_LIT> ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT>


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: Default ) CM = RM == Reloc

:: PIC_ ? CodeModel :: Medium : CodeModel :: Small ;


<s> } ; const auto & Users = P -> users ( ) ; const auto & Operands = P -> operands ( ) ; if ( ! std :: all_of ( Users . begin ( ) , Users . end ( ) , IsValidUser ) || ! std :: all_of ( Operands . begin ( ) , Operands . end ( ) , IsValidOperand ) ) ToRemove . push_back ( P ) ; } auto IsPromotable = [ & Promotable ] ( const Value * V ) -> bool { const PHINode * Phi = dyn_cast < PHINode > ( V ) ; return ! Phi || Promotable . count ( Phi ) ; } ; while ( ! ToRemove . empty


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( GP0Regs [ Base ] ) ) ; break ; case <STR_LIT> : case <STR_LIT>


<s> copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; int br_code ; switch ( Opc ) { case <STR_LIT> : br_code = <STR_LIT> ; break ; case <STR_LIT> : br_code = <STR_LIT> ; break ; default : br_code = <NUM_LIT> ; } BuildMI ( BB , dl , TII . get ( br_code ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> static const EVT VTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; SDValue Elt = DAG . getConstant ( Val , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


Subtarget -> hasAVX512 ( ) ) return false ;


<s> if ( aarch64_simd_call_p ( insn ) ) { for ( int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( FP_SIMD_SAVED_REGNUM_P ( regno ) )

CLEAR_HARD_REG_BIT ( * return_set , regno ) ;


<s> bool <ISA_LIT>AsmParser :: expandLoadAddressReg ( MCInst & Inst , bool Is32BitImm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { if ( loadAndAddSymbolAddress ( ImmOp . getExpr ( ) , DstRegOp . getReg ( ) , SrcRegOp . getReg ( ) , Is32BitImm , IDLoc , Instructions ) ) return true ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , SrcRegOp . getReg ( ) , Is32BitImm , IDLoc , Instructions )


<s> PM -> add ( create<ISA_LIT>ExpandPseudoPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> return parseRegister ( Operands , RegFP , <STR_LIT> ,


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div8hi ( ( int16x8_t


<s> void printlea32mem ( const MCInst * MI


<s> case V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( target , last , fold


<s> bool <ISA_LIT>AsmParser :: parseDataDirective ( unsigned Size , SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { while ( true ) { const MCExpr *


<s> qword q ; unsigned int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] =


<s> SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple ::

Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = nullptr ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> static SDValue lowerV4I32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask (


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddress ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( MatchAddressRecursively ( N , AM , <NUM_LIT> ) ) return true ; if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . Base . Reg = AM . IndexReg ; AM . Scale


<s> void eraseMatchingBitGroups ( function_ref < bool ( const BitGroup & ) > F ) { erase_if ( BitGroups ,


<s> arch = strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ; if ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; if ( arch )


<s> addPass ( create<ISA_LIT>RetpolineThunksPass (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; } } MVT VT = Root -> getValueType ( Root -> getNumValues ( ) - <NUM_LIT> ) ; while ( VT == <STR_LIT>


<s> unsigned Reg = Info . getReg ( ) ; unsigned NewReg ; if ( static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) -> regNeedsCFI ( Reg , NewReg ) ) Reg = NewReg ; else continue ; StackOffset Offset ; if ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID :: SVEVector ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Offset = StackOffset :: getScalable ( MFI . getObjectOffset ( Info . getFrameIdx ( ) ) ) - StackOffset

:: getFixed ( AFI -> getCalleeSavedStackSize ( MFI ) ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg


<s> SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( SrcVal . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; SDLoc Loc ( Op ) ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , CallOptions , Loc , Chain ) ; return IsStrict ? DAG . getMergeValues ( { Result , Chain } , Loc ) : Result ; } if ( IsStrict ) { SDLoc Loc ( Op ) ; SDValue Result = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Loc , Op . getValueType ( ) , SrcVal ) ; return DAG . getMergeValues ( { Result , Op . getOperand ( <NUM_LIT> ) } , Loc ) ; } return


<s> Register RHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; unsigned OpCmp ; LLT Ty = MRI . getType ( LHS ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; } MachineInstr & CmpInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpCmp ) ) . addReg ( LHS ) . addReg ( RHS ) ; MachineInstr & SetInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( CC ) ; constrainSelectedInstRegOperands ( CmpInst , TII , TRI


<s> unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : <NUM_LIT> ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align


<s> return ( __m64 ) __builtin_arm_wabsdiffw ( ( __v2si ) a , (


<s> } else if ( VPTBlock . instrInVPTBlock ( ) ) { VCC = VPTBlock . getVPTPred ( ) ; VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator CCI = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ CCI ) { if ( OpInfo [ i ] . isPredicate ( ) || CCI == MI . end ( ) ) break ; } if ( <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) { CCI = MI . insert ( CCI , MCOperand :: createImm ( CC ) ) ; ++ CCI ; if ( CC == <STR_LIT> ) MI . insert ( CCI , MCOperand :: createReg ( <NUM_LIT> ) ) ; else MI . insert ( CCI , MCOperand :: createReg ( <STR_LIT> ) ) ; } else if ( CC != <STR_LIT> ) { Check ( S , SoftFail ) ; } MCInst :: iterator VCCI = MI . begin ( ) ; unsigned VCCPos ; for ( VCCPos = <NUM_LIT> ; VCCPos < NumOps ; ++ VCCPos , ++ VCCI ) { if ( <STR_LIT> ( OpInfo [ VCCPos ] . OperandType ) || VCCI == MI . end ( ) ) break ; } if ( isVectorPredicable ( MI . getOpcode ( ) ) ) { VCCI = MI . insert ( VCCI , MCOperand :: createImm ( VCC ) ) ; ++ VCCI ; if ( VCC == <STR_LIT> ) VCCI = MI . insert ( VCCI , MCOperand


<s> if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) return <NUM_LIT> ; if ( ( ~ ZImmVal < <NUM_LIT> )

|| <STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ;


<s> int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( OffsetReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; } } }


<s> int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return DataWidth >= <NUM_LIT> && ST ->


<s> case CallingConv :: Cold : return ( Return ? RetCC_<ISA_LIT>_Cold : CC_<ISA_LIT>64_ELF_FIS


<s> SDValue Addr = DAG . getNode ( <STR_LIT> , DL , Ty , { TV , TCPV } ) ; if ( ! IsPIC ) return Addr ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; if ( IsLocal ) return Result ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction


<s> APInt ImmValue ; EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ( ImmValue & ~ ( ImmValue + <NUM_LIT>


<s> assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT> ] , NewRegs [ <NUM_LIT> ] ) ; MIRBuilder . buildSequence ( Arg . Reg , NewRegs , { <NUM_LIT> , <NUM_LIT> } ) ; return


<s> const MCOperand & IndexReg = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <STR_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <STR_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addNEONi8ReplicateOperands ( Inst , true


<s> case AsmToken :: Percent : { const AsmToken & nextToken = lexTentative ( ) ; if ( nextToken . getKind ( ) != AsmToken :: Identifier ) return lexedToken ; if ( unsigned regID = MatchRegisterName ( nextToken . getString ( ) ) ) { lexDefinite ( ) ; StringRef regStr ( lexedToken . getString ( ) . data ( ) , lexedToken . getString ( ) . size ( ) + nextToken . getString ( ) . size ( ) ) ; return AsmToken ( AsmToken :: Register , regStr , static_cast < int64_t > ( regID ) ) ; } if ( nextToken . getString ( ) . size ( ) == <NUM_LIT> && nextToken . getString ( ) . startswith ( <STR_LIT> ) ) { int RegNo = - <NUM_LIT> ; switch ( nextToken . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo =


<s> if ( ! ( ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) ) return SDValue ( ) ; SDValue X , Y , Mask ; if ( ! matchLogicBlend ( N , X , Y , Mask ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , Res ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = VT . is256BitVector ( ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y ) ; Mask = DAG . getBitcast ( BlendVT , Mask ) ; Mask = DAG . getSelect ( DL , BlendVT


<s> LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; return false ; } MBB . splice ( std :: next ( SlotI ) , & MBB , Filler . getReverse ( ) ) ; MIBundleBuilder ( MBB , SlotI , std :: next ( SlotI , <NUM_LIT> ) ) ; ++ UsefulSlots


<s> mthree = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero , mask ; zero = gen_reg_rtx ( mode ) ; mask = gen_reg_rtx ( mode ) ; zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_NE ( mode , zero , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_AND ( mode , x0 , mask ) ) ) ; } } emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MULT ( mode , x0 , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( mode , e0 ,


<s> O << <STR_LIT> << MBB -> getNumber (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> bool hasXOP ( ) const { return HasXOP


<s> unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode (


<s> MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; VRM = & getAnalysis < VirtRegMap > ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; if ( VRM -> isShapeMapEmpty ( ) ) return false ; tileConfig (


<s> case E_V16SImode : case E_V8SImode : return V4SImode ; case E_V32HImode : case E_V16HImode : return V8HImode ; case E_V64QImode : case E_V32QImode : return V16QImode ; case


<s> shift = d -> perm [ <NUM_LIT> ] ; if ( BYTES_BIG_ENDIAN && shift > nelt ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != ( ( shift + i ) & mask ) ) return false ; if ( d -> testing_p ) return true ; hi = shift < nelt ? d -> op1 : d -> op0 ; lo = shift < nelt ? d -> op0 : d -> op1 ; shift %= nelt ; shift *= GET_MODE_UNIT_SIZE ( d -> vmode ) * BITS_PER_UNIT ; gcc_assert ( IN_RANGE ( shift , <NUM_LIT> , <NUM_LIT> ) ) ; if ( BYTES_BIG_ENDIAN ) shift = <NUM_LIT> -


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> const char * getPassName ( ) const override { return


<s> if ( MI . getParent ( ) == nullptr ) return nullptr ; const MachineFunction * MF = MI . getParent ( ) ->


<s> expr = mep_frame_expr ( insn2 ) ; if ( RTX_FRAME_RELATED_P ( insn1 ) ) expr = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( <NUM_LIT> , mep_frame_expr ( insn1 ) , expr ) ) ; set_unique_reg_note ( insn1 , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( insn1 ) = <NUM_LIT> ; } PATTERN ( insn1 ) = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , PATTERN (


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addReg ( SrcReg , false , false , isKill ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case VK_<ISA_LIT>_HI : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGH : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; break ; case VK_<ISA_LIT>_HIGHA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case VK_<ISA_LIT>_HIGHESTA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; } Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol


<s> std :: unique_ptr < <ISA_LIT>Operand > Op ( new ( Mem ) <ISA_LIT>Operand ( Token ) ) ; Op -> Tok . Data = reinterpret_cast < const char * > ( Op . get ( ) + <NUM_LIT> ) ; Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( const_cast < char * > ( Op -> Tok . Data ) , Str .


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjust<ISA_LIT>StackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack


<s> case CallingConv :: PreserveMost : case CallingConv :: CXX_FAST_TLS : case CallingConv :: Swift : if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; if ( ! IsVarArg ) return CC_<ISA_LIT>_DarwinPCS ; return Subtarget -> isTargetILP32 ( ) ? CC_<ISA_LIT>_DarwinPCS_ILP32_VarArg : CC_<ISA_LIT>_DarwinPCS_VarArg ; case CallingConv ::


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const


<s> void rs6000_disqualify_components ( sbitmap components , edge e , sbitmap edge_components , bool ) { if ( bitmap_bit_p ( edge_components , <NUM_LIT> ) && bitmap_bit_p ( DF_LIVE_IN ( e -> dest ) , <NUM_LIT> ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , e -> dest -> index ) ; bitmap_clear_bit ( components , <NUM_LIT>


enum machine_mode mode ATTRIBUTE_UNUSED ) {


<s> MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister


<s> if ( Ext == <STR_LIT> ) IsLSL = true ; else if ( Ext != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; int64_t Imm = MO . getImm ( ) ; if ( ( ! IsLSL || ( IsLSL && isHalf ) ) && Imm != <NUM_LIT> && Imm != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; if ( IsLSL && ( Imm < <NUM_LIT> || Imm > <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; if ( ! IsLSL ) Imm ++ ; Imm *= <NUM_LIT> ; if ( IsLSL ) { if ( Imm == <NUM_LIT> ) return ; O << <STR_LIT> ; } else O << <STR_LIT> ; O << <STR_LIT> << Imm


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; bool IsILP32 = Options . getABIName ( ) == <STR_LIT> ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI