<s> LoadInst * <ISA_LIT>TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; IRBuilder < > Builder ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent


<s> if ( mips_ls2 . alu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu1_core_unit_code ) ) mips_ls2 . alu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; } if ( mips_ls2 . falu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu1_core_unit_code ) ) mips_ls2 . falu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 .


<s> void addFGR32AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getFGR32Reg


<s> assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; SDValue Glue ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( auto * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( IsTailCall ) { Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Callee , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Callee = DAG . getRegister ( <STR_LIT> , Callee . getValueType ( ) ) ; } for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) Ops . push_back ( DAG . getRegister ( RegsToPass [ I ] . first , RegsToPass [ I ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList


<s> MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++


<s> RM = Reloc :: Static ; } if ( CM == CodeModel :: Default ) { CM = CodeModel :: Small ; } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) { report_fatal_error ( <STR_LIT> ) ; } X -> initMCCodeGenInfo ( RM , CM , OL


<s> pat = gen_rtx_CONST ( SImode , gen_rtx_PLUS ( Pmode , pat , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_lo_sum ( pic_offset_table_rtx , pic_offset_table_rtx , pat ) ) ; emit_insn ( gen_add_pc ( pic_offset_table_rtx , pic_offset_table_rtx ) ) ; emit_insn ( gen_blockage (


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> isPICStyleRIPRel ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) , Result ) ; } return Result


<s> if ( Kind != k_VectorIndex ) return false ; return VectorIndex .


<s> if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk , delta , vcall_offset , function


<s> const MCExpr * Value ; SMLoc ExprLoc = getParser ( ) . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> + ID . getIdentifier ( ) + <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue , Size ) ; } else getStreamer ( ) . EmitValue ( Value , Size , ExprLoc ) ; return false ; } ; if ( parseMany ( parseOp ) ) return addErrorSuffix ( <STR_LIT> + ID . getIdentifier ( )


<s> if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT>


<s> assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent (


<s> const ArrayRef < size_t > getPreallocatedArgOffsets ( const size_t Id ) { assert ( ! PreallocatedArgOffsets [ Id ] . empty ( ) && <STR_LIT> ) ; return PreallocatedArgOffsets [ Id


<s> SDValue <ISA_LIT>TargetLowering :: lowerFCOPYSIGN ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . isGP64bit ( ) ) return lowerFCOPYSIGN64 ( Op , DAG , Subtarget . hasExtractInsert ( ) ) ; return lowerFCOPYSIGN32 ( Op , DAG , Subtarget


<s> SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; int FirstFI = - MFI -> getNumFixedObjects ( ) - <NUM_LIT> , LastFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue Arg = OutVals [ i ] ; CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( <STR_LIT> ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; WriteByValArg ( ByValChain , Chain , dl , RegsToPass , MemOpChains , LastFI , MFI , DAG , Arg , VA , Flags , getPointerTy ( ) , Subtarget -> isLittle ( ) ) ; continue ; } if ( VA . isMemLoc ( ) ) { LastFI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue PtrOff = DAG . getFrameIndex ( LastFI , getPointerTy ( ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } } if ( LastFI ) <ISA_LIT>FI -> extendOutArgFIRange ( FirstFI , LastFI ) ; if ( InChain != ByValChain ) DAG . UpdateNodeOperands ( CallSeqStart . getNode ( ) , ByValChain , NextStackOffsetVal ) ; if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest ,


<s> return __builtin_loongson_pmulhh ( s ,


<s> int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + <NUM_LIT> ) >> <NUM_LIT> : <NUM_LIT> ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts ) * n_elts = <NUM_LIT> ; return


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( isCalleeSavedCR ( Reg ) && ! Subtarget . is32BitELFABI ( ) ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . loadRegFromStackSlotNoUpd ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { assert ( Subtarget . is32BitELFABI ( ) && <STR_LIT> ) ; bool is31 = needsFP ( * MF ) ; restoreCRs ( is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; } return true


<s> MCInst Move ; Move . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Move . addOperand ( MCOperand :: CreateReg ( ToReg ) ) ; Move . addOperand ( MCOperand :: CreateReg ( FromReg ) ) ; Out . EmitInstruction (


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , Ops . data ( ) , Ops . size (


<s> if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) . isVector ( ) ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value , DAG . getUNDEF ( <STR_LIT> ) ) ; Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; } else assert ( VA . getLocInfo ( ) == CCValAssign ::


<s> fprintf ( file , <STR_LIT> ) ; break ; case POST_INC : fprintf ( file , <STR_LIT> ) ; rx_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; break ; case PLUS : { rtx arg1 = XEXP ( addr , <NUM_LIT> ) ; rtx arg2 = XEXP ( addr , <NUM_LIT> ) ; rtx base , index ; if ( REG_P ( arg1 ) && RTX_OK_FOR_BASE ( arg1 , true ) ) base = arg1 , index = arg2 ; else if ( REG_P ( arg2 ) && RTX_OK_FOR_BASE ( arg2 , true ) ) base = arg2 , index = arg1 ; else { rx_print_operand ( file , arg1 , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; rx_print_operand ( file , arg2 , <NUM_LIT> ) ; break ; } if ( REG_P ( index ) || GET_CODE ( index ) == MULT ) { fprintf ( file , <STR_LIT> ) ; rx_print_operand ( file , index , 'A' ) ; fprintf ( file , <STR_LIT> ) ; } else { rx_print_operand ( file , index , 'A' ) ; fprintf ( file , <STR_LIT> ) ; } rx_print_operand ( file , base , <NUM_LIT>


<s> assert ( Mem . OffsetIsReg && Mem . OffsetRegShifted && <STR_LIT> ) ; return Mem . ShiftType


<s> if ( ! ( Cmp . getOpcode ( ) == <STR_LIT> || ( Cmp . getOpcode ( ) == <STR_LIT> && ! Cmp -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; if ( ! Cmp . hasOneUse ( ) ) return SDValue ( ) ; SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC ) return SDValue ( ) ; APInt Comparison = CmpRHSC -> getAPIntValue ( ) ; if ( Comparison == - Addend ) { auto * AN = cast < AtomicSDNode > ( CmpLHS . getNode ( ) ) ; auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpLHS . getValueType ( ) , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - Addend , SDLoc ( CmpRHS ) , CmpRHS . getValueType ( ) ) , AN -> getMemOperand ( ) ) ; auto LockOp = lowerAtomicArithWithLOCK ( AtomicSub , DAG , Subtarget ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , DAG . getUNDEF ( CmpLHS . getValueType ( ) ) ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , LockOp . getValue ( <NUM_LIT> ) ) ; return LockOp ; } if ( ! Comparison . isNullValue ( ) ) return SDValue ( ) ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC


<s> static Optional < Instruction * > instCombineSVEZip ( InstCombiner & IC , IntrinsicInst & II ) { Value * A , * B ; if ( match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Value ( A ) , m_Value ( B ) ) ) && match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Specific ( A ) , m_Specific ( B ) ) ) ) return IC . replaceInstUsesWith ( II , ( II . getIntrinsicID ( ) == <STR_LIT> ? A : B ) ) ; return None


<s> UseCapTable = TM . getSubtargetImpl ( ) ->


<s> if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex


<s> void addImmScaledOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> if ( B . succ_empty ( ) ) return NULL ; CmpWeight Cmp ( B , getAnalysis <


<s> SDValue Increment = DAG . getConstant ( SclrLoadTy . getSizeInBits ( ) / <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Res = DAG . getUNDEF ( LoadUnitVecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; Chains . push_back ( ScalarLoad . getValue ( <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; else Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , Res , ScalarLoad , DAG . getIntPtrConstant ( i , dl ) ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chains ) ; SDValue SlicedVec = DAG . getBitcast ( WideVecVT , Res ) ; unsigned SizeRatio = RegSz / MemSz ; if ( Ext == <STR_LIT> ) { if ( Subtarget -> hasSSE41 ( ) ) { SDValue Sext = DAG . getNode ( <STR_LIT> , dl , RegVT , SlicedVec ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , TF ) ; return Sext ; } assert ( TLI . isOperationLegalOrCustom ( <STR_LIT> , RegVT ) && <STR_LIT> ) ; SDValue Shuff = DAG . getSignExtendVectorInReg ( SlicedVec , dl , RegVT ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , TF ) ; return Shuff ; } SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i * SizeRatio ] = i ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , dl , SlicedVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; Shuff = DAG . getBitcast ( RegVT , Shuff ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , TF ) ; return Shuff


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; } virtual const char * getPassName ( ) const { return <STR_LIT> ; } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) LLVM_OVERRIDE { if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( raw_ostream & O ) ; void printHex32 ( unsigned int Value , raw_ostream & O ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ; virtual void EmitFunctionBodyEnd ( ) ; virtual bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int


<s> const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! RI . getCommonSubClass ( RC , MRI . getRegClass ( DstReg ) ) ) return false ; unsigned ExtraCondLat = Cond . size ( ) != <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = <NUM_LIT> ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = <NUM_LIT> ; return true ; } if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getString ( ) . equals_lower ( <STR_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( )

} , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input , Mask } ) ;


<s> const MCExpr * <ISA_LIT>_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym ,

MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I ,


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes =


<s> else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7s : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6t2 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6k : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5te : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v4t : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: NoSubArch : break ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature =


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT>


<s> void <ISA_LIT>GNUInfo :: setElfFlags (


<s> static DecodeStatus DecodeCOP2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand ::


<s> assert ( ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . has<ISA_LIT>64r6 ( ) ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; unsigned Opc = invertFPCondCodeUser ( CC ) ? <STR_LIT> :


<s> <ISA_LIT>RegInfoRecord ( <ISA_LIT>ELFStreamer * S , MCContext & Context ) : Streamer ( S ) , Context ( Context ) { ri_gprmask = <NUM_LIT> ; ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = <NUM_LIT> ; ri_gp_value = <NUM_LIT> ; const MCRegisterInfo * TRI = Context . getRegisterInfo ( ) ; GPR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; AFGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; MSA128BRegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP2RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP3RegClass = & ( TRI ->


<s> <ISA_LIT>XCOFFMCAsmInfo :: <ISA_LIT>XCOFFMCAsmInfo ( bool Is64Bit , const Triple & T ) { assert ( ! IsLittleEndian &&


<s> const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v2s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) { for ( auto Ty : { s32 , s64 , v2s32 , v4s32 , v2s64 } ) setAction ( BinOp , Ty , Legal ) ; for ( auto Ty : { s8 , s16 } ) setAction ( BinOp , Ty , WidenScalar ) ; } for ( auto MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { s32 , s64 } ) setAction ( MemOp


<s> static SDValue MergeInputChains ( SDNode * N1 , SDNode * N2 ) { SDValue Chain1 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue Chain2 = N2 -> getOperand ( <NUM_LIT> ) ; if ( Chain1 == Chain2 ) return


<s> else setRelocationModel ( Reloc :: DynamicNoPIC ) ; } assert ( getRelocationModel ( ) != Reloc :: Default && <STR_LIT> ) ; if ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { if ( is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; else if ( ! Subtarget . isTargetDarwin ( ) ) setRelocationModel ( Reloc :: Static ) ; } if ( getRelocationModel ( ) == Reloc :: Static && Subtarget . isTargetDarwin ( ) && is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle (


<s> void addConstPoolAsmImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONAltShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; return BaseT :: getShuffleCost ( Kind ,


<s> static DecodeStatus DecodeGPR64commonRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void *


<s> if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ; return


<s> assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT>


<s> DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap . find ( Base ) ; if ( BI != Base2LdsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2LdsMap [ Base ] . push_back ( MI ) ; LdBases . push_back ( Base ) ; } } else { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2StsMap . find ( Base ) ; if ( BI != Base2StsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2StsMap [ Base ] . push_back ( MI ) ; StBases . push_back ( Base ) ; } } if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear


<s> if ( ! EnableBasePointer ) return false ; if ( AlwaysBasePointer


<s> insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } } return


<s> unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , MBBI ) ; MBB . erase (


<s> void <ISA_LIT>FlagsCopyLoweringPass :: insertTest ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Pos , const DebugLoc & Loc , unsigned Reg ) { auto TestI = BuildMI ( MBB , Pos , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( Reg ) ; ( void ) TestI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; TestI -> dump ( ) ) ; ++


<s> if ( ( kind == vector_load || kind == unaligned_load || kind == vector_store || kind ==

unaligned_store ) && STMT_VINFO_DATA_REF ( stmt_info ) ) {


<s> return new <ISA_LIT>16HardFloat ( TM


<s> MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += getInstSizeInBytes ( * MI , TII ) ; ++ MI ; } skipNonTerminators ( Position , Block ) ; while ( MI != End ) { if ( ! MI -> isDebugInstr ( ) ) { assert ( MI -> isTerminator ( ) && <STR_LIT> ) ; Terminators . push_back ( describeTerminator ( * MI ) ) ; skipTerminator ( Position , Terminators . back ( ) ,


<s> unsigned contents , i , nelt , nelt2 ; unsigned h0 , h1 , h2 , h3 ; rtx_insn * seq ; bool ok ; if ( d -> one_operand_p ) return false ; nelt = d -> nelt ; nelt2 = nelt / <NUM_LIT> ; contents = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) contents |= <NUM_LIT> << d -> perm [ i ] ; memset ( remap , <NUM_LIT> , sizeof ( remap ) ) ; dremap = * d ; h0 = ( <NUM_LIT> << nelt2 ) - <NUM_LIT> ; h1 = h0 << nelt2 ; h2 = h0 << nelt ; h3 = h0 << ( nelt + nelt2 ) ; if ( ( contents & ( h0 | h2 ) ) == contents ) { for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned which = i / <NUM_LIT> + ( i & <NUM_LIT> ? nelt : <NUM_LIT> ) ; remap [ which ] = i ; dremap . perm [ i ] = which ; } } else if ( ( contents & ( h1 | h3 ) ) == contents ) { for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned which = i / <NUM_LIT> + nelt2 + ( i & <NUM_LIT> ? nelt : <NUM_LIT> ) ; remap [ which ] = i ; dremap . perm [ i ] = which ; } } else if ( ( contents & <NUM_LIT> ) == contents ) { for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned which = ( i & ~ <NUM_LIT> ) + ( i & <NUM_LIT> ? nelt : <NUM_LIT> ) ; remap [ which ] = i ; dremap . perm [ i ] = which ; } } else if ( ( contents & <NUM_LIT> ) == contents ) { for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned which = ( i | <NUM_LIT> ) + ( i & <NUM_LIT> ? nelt : <NUM_LIT> ) ; remap [ which ] = i ; dremap . perm [ i ] = which ; } } else if ( floor_log2 ( contents ) - ctz_hwi ( contents ) < ( int ) nelt ) { unsigned shift = ctz_hwi (


<s> Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { Res = VRI . V ; } eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt ; } ) ; } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue (

MI , OpIdx , <STR_LIT> , Fixups , STI ) ;


<s> assert ( isRegBase ( ) && <STR_LIT> ) ; Base . Reg


<s> if ( DisableBackwardSearch ) return false ; auto * Fn = MBB . getParent ( ) ; RegDefsUses RegDU ( * Fn -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MemDefsUses MemDU ( Fn -> getDataLayout ( ) , Fn -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB ,


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> return Kind == k_PostIndexRegister && PostIdxReg . ShiftTy ==


<s> unsigned <ISA_LIT>TTI :: getMaxInterleaveFactor ( ) const { if ( ST -> isCortexA57 ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> unsigned getVectorIndex ( ) const { assert ( Kind == k_VectorIndex && <STR_LIT> ) ; return VectorIndex .


<s> MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( <NUM_LIT> , Dst


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > (


<s> SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <NUM_LIT> , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL

, Reg , T , Result . getValue ( <NUM_LIT> ) ) ;


<s> return ( __m512d ) __builtin_ia32_cvtudq2pd512_mask ( ( __v8si ) __A , (


<s> static StringRef decIncOperator ( const MCInst * MI ) { if ( MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> if ( Base . Reg . getNode ( ) != <NUM_LIT> ) Base . Reg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Base . FrameIndex << '\n' << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' <<


<s> return arm_gen_constant ( code , SImode , NULL_RTX , INTVAL ( val ) , NULL_RTX , NULL_RTX


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain


<s> default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock


<s> Address ( ) : Kind ( RegBase ) , Offset ( <NUM_LIT> ) , GV ( <NUM_LIT> ) { Base . Reg =


<s> static void aarch64_emit_prologue_components ( sbitmap components ) { aarch64_process_components ( components ,


<s> case <STR_LIT> : if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT>


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI


<s> OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue


<s> memset ( ( char * ) & ultra_pipe , <NUM_LIT> ,


<s> case FK_Data_8 : return ELF :: R_390_PC64 ; case <STR_LIT> : return ELF :: R_390_PC16DBL ; case <STR_LIT> : return ELF


<s> for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <STR_LIT> , false ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set (


<s> if ( TheTriple . isOSWindows ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ,


<s> if ( Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; return MCDisassembler ::


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModeThumbSPOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI .


<s> bool <ISA_LIT>DAGToDAGISel :: selectScalarSSELoad ( SDNode * Root , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment , SDValue & PatternNodeWithChain ) { if ( N . getOpcode ( ) == <STR_LIT> ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && PatternNodeWithChain . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD ,


<s> if ( ! CFP -> isExactlyValue ( <NUM_LIT> ) && ! CFP -> isExactlyValue ( <NUM_LIT> ) ) return false ; if ( CFP -> isExactlyValue ( <NUM_LIT> ) && ! CI -> hasNoSignedZeros ( ) ) return false ; CI -> setCalledFunction ( <STR_LIT> ( & M , <STR_LIT> , CI -> getType ( ) ) ) ; return true


<s> SDValue In = N -> getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , InVT ,


<s> if ( index == <NUM_LIT> ) { insn -> sibIndex = SIB_INDEX_NONE ; } else { insn -> sibIndex = ( SIBIndex ) ( insn -> sibIndexBase + index ) ; } insn -> sibScale = <NUM_LIT> << scaleFromSIB ( insn -> sib ) ; base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement =


<s> return ( uint32x2_t ) __builtin_shuffle ( __a , ( uint32x2_t ) { <NUM_LIT> ,


<s> if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch (


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; auto * GA = dyn_cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! GA ) return false ; Optional < ConstantRange > CR = GA -> getGlobal (


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isExpr (


<s> if ( ST -> isCortexA15 ( ) || ST -> isSwift ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> case TargetOpcode :: DBG_VALUE : { if ( ! isVerbose ( ) || ! OutStreamer . hasRawTextSupport ( ) ) return ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; unsigned NOps = MI -> getNumOperands ( ) ; assert ( NOps == <NUM_LIT> ) ; O << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O


<s> int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = next ( MachineFunction :: iterator ( MBB ) ) ; DOUT << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp (


<s> bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable (


<s> const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx


<s> void <ISA_LIT>ExpandISEL :: expandMergeableISELs ( BlockISELList & BIL ) { MachineBasicBlock * MBB = BIL . back ( ) -> getParent ( ) ; handleSpecialCases ( BIL , MBB ) ; reorganizeBlockLayout ( BIL , MBB


<s> static DecodeStatus DecodeAddiGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { llvm_unreachable ( <STR_LIT>


<s> if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; <STR_LIT> NCC = getInstrPredicate ( NMI , PredReg ) ; if ( ! ( NCC == CC || NCC == OCC ) || NMI -> modifiesRegister ( SrcReg , & TRI ) || NMI -> modifiesRegister ( <STR_LIT> , & TRI ) ) break ; if ( ++ NumInsts == <NUM_LIT> ) return ; } if (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & MCSTI , MCContext &


<s> else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment ) ; Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( Subtarget -> is64Bit ( ) && CM == CodeModel :: Large ) { Register AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addRegReg ( MIB , AddrReg , false , PICBase , false ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , DL . getPointerSize ( ) , Alignment ) ; MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return ResultReg


<s> assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getConstant ( NumBits / <NUM_LIT> , dl , ScalarShiftTy ) ; return DAG . getBitcast ( VT , DAG . getNode ( Opc , dl


<s> gcc_unreachable ( ) ; } return r ; } rt = reg_names [ REGNO ( temp ) ] ; switch ( code ) { case ASHIFT : sprintf ( r , <STR_LIT> , rt , r0 , r0 , ( int ) size , r1 , ( int ) size , rt , ( int ) ( <NUM_LIT> - size ) , r1 , rt ) ; break ; case ASHIFTRT : sprintf ( r , <STR_LIT> , rt , r1 , r1 , ( int ) size , r0 , ( int ) size , rt , ( int ) ( <NUM_LIT> - size ) , r0 , rt ) ; break ; case LSHIFTRT : sprintf ( r , <STR_LIT> , rt , r1 , r1 , ( int ) size , r0 , ( int ) size , rt , ( int ) ( <NUM_LIT> -


<s> Streamer . EmitBytes ( CurrentVendor , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item .


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm &


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; unsigned ATReg = <NUM_LIT> ; bool LoadedOffsetInAT = false ; if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; LoadedOffsetInAT = true ; warnIfNoMacro ( IDLoc ) ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t LeftLoadOffset = <NUM_LIT> , RightLoadOffset = <NUM_LIT> ; if ( isLittle ( ) ) { LeftLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; RightLoadOffset = LoadedOffsetInAT ? <NUM_LIT>


<s> return new Emitter < ObjectCodeEmitter > ( TM , OCE


<s> if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set )


<s> virtual ~ <ISA_LIT>Operand ( ) { switch ( Kind ) { case k_Immediate : break ; case k_Memory : delete Mem . Base ; break ; case


<s> MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; unsigned NumAddrOps = MOs . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; if ( NumAddrOps < <NUM_LIT> ) addOffset ( MIB , <NUM_LIT> ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i + <NUM_LIT> ) ; MIB . addOperand ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; MIB . addOperand ( MO


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( VOIDmode , target , x ) ; rtx_insn * insn =


<s> switch ( AsmInfo . getAssemblerDialect ( ) ) { default : SetError ( SMLoc ( ) , <STR_LIT> ) ; return AsmToken ( AsmToken :: Error , <STR_LIT> ,


<s> if ( cfun -> calls_alloca ) return true ; if ( TARGET_MIPS16 ) { mips_compute_frame_info ( ) ; if ( ! SMALL_OPERAND ( cfun -> machine -> frame . total_size ) ) return true ; } return false


<s> void MLxExpansion :: pushStack ( MachineInstr * MI ) { LastMIs [ MIIdx ] = MI ; if ( ++ MIIdx == <NUM_LIT>


<s> unsigned CC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI , MII , MRI , STI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI , MII


<s> return __builtin_mve_vshlq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> machine_mode mode = GET_MODE ( x ) ; int words , cost ; switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : return ( mode == SImode ) ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : case MINUS : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int const_size = thumb1_size_rtx_costs ( XEXP ( x , <NUM_LIT> ) , CONST_INT , SET ) ; if ( arm_arch6m && arm_m_profile_small_mul ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) + const_size ; } return COSTS_N_INSNS ( <NUM_LIT> ) ; case SET : words = ARM_NUM_INTS ( GET_MODE_SIZE ( GET_MODE ( SET_DEST ( x ) ) ) ) ; cost = COSTS_N_INSNS ( words ) ; if ( satisfies_constraint_J ( SET_SRC ( x ) ) || satisfies_constraint_K ( SET_SRC ( x ) ) || ( CONST_INT_P ( SET_SRC ( x ) ) && UINTVAL ( SET_SRC ( x ) ) >= <NUM_LIT> && TARGET_HAVE_MOVT && satisfies_constraint_j ( SET_SRC ( x ) ) ) || ( ( words > <NUM_LIT> ) && MEM_P ( SET_SRC ( x ) ) ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; return cost ; case CONST_INT : if ( outer == SET ) { if ( UINTVAL ( x ) < <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_HAVE_MOVT && ! ( INTVAL ( x ) & <NUM_LIT> ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) <= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return arm_disable_literal_pool ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_<ISA_LIT>_RegMask


<s> return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ; return SDValue


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo


<s> unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg


<s> case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; case ENCODING_IB : if ( sawRegImm ) { insn -> immediates [ insn -> numImmediatesConsumed ] = insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] & <NUM_LIT> ; ++ insn -> numImmediatesConsumed ; break ; } if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( x86OperandSets [ insn -> spec -> operands ] [ index ] . type == TYPE_IMM3 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( x86OperandSets [ insn -> spec -> operands ] [ index ] . type == TYPE_IMM5 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( x86OperandSets [ insn -> spec -> operands ] [ index ] . type == TYPE_XMM128 || x86OperandSets [ insn -> spec -> operands ] [ index ] . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { IsPIC = isPIC


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ) ) return true ; } else if ( MO . isRegMask ( ) ) { if ( MO . clobbersPhysReg ( <STR_LIT> ) || MO . clobbersPhysReg ( <STR_LIT> )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const

MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> TOut . emitRRX ( <STR_LIT> , ATReg , <STR_LIT> , MCOperand :: createExpr ( GotExpr ) , IDLoc , STI ) ; } else { TOut . emitRRX ( <STR_LIT> , ATReg , <STR_LIT> , MCOperand :: createExpr ( GotExpr ) , IDLoc , STI ) ; } } else { const MCExpr * HiSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , HiSym , getContext ( ) ) ; if ( isABI_O32 ( ) || isABI_N32 ( ) ) { TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ; } else { const MCExpr * HighestSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HighestExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHEST , HighestSym , getContext ( ) ) ; const MCExpr * HigherSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HigherExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHER , HigherSym , getContext ( ) ) ; TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg ,


<s> case MEK_CAPTABLE20 : case MEK_CAPTABLE_HI16 : case MEK_CAPTABLE_LO16 : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_DTPREL : case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_TLSLDM : case MEK_TLSGD : case MEK_GOTTPREL : case MEK_TPREL_HI : case MEK_TPREL_LO : case MEK_CAPTAB_TLSGD_HI16 : case


<s> void <ISA_LIT>MCAsmStreamer :: ChangeSection ( MCSection * Section , const MCExpr * Subsection ) { flushValues (


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { if ( EmitFPOData ) { <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * >

( OutStreamer -> getTargetStreamer ( ) ) ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const


<s> if ( SourceRegion . MustMoveUp && SourceRegion . MustMoveDown ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } if ( ! validateCandidates ( SourceRegion , TargetRegion ) ) return false ; moveAndUpdatePHIs ( SourceRegion . BranchBlock , SourceRegion . BranchTargetBlock ) ; MachineBasicBlock :: iterator firstInstr = SourceRegion . BranchBlock -> getFirstNonPHI ( ) ; MachineBasicBlock :: iterator lastInstr = SourceRegion . BranchBlock -> getFirstTerminator ( ) ; MachineBasicBlock * Source = SourceRegion . MustMoveDown ? SourceRegion . BranchTargetBlock : TargetRegion . BranchBlock ; MachineBasicBlock :: iterator Target = SourceRegion . MustMoveDown ? SourceRegion . BranchTargetBlock -> getFirstNonPHI ( ) : TargetRegion . BranchBlock -> getFirstTerminator ( ) ; Source -> splice ( Target , SourceRegion . BranchBlock , firstInstr , lastInstr ) ; SourceRegion . BranchBlock -> removeSuccessor ( SourceRegion . FallThroughBlock ) ; TargetRegion . BranchBlock -> transferSuccessorsAndUpdatePHIs ( SourceRegion . BranchBlock ) ; TargetRegion . BranchBlock -> ReplaceUsesOfBlockWith ( SourceRegion . BranchBlock , SourceRegion . BranchTargetBlock ) ; MachineBasicBlock :: iterator I = SourceRegion . BranchBlock -> terminators ( ) . begin ( ) ; while ( I != SourceRegion . BranchBlock -> terminators ( ) . end ( ) ) { MachineInstr & CurrInst = * I ; ++ I ; if ( CurrInst . isBranch ( ) ) CurrInst . eraseFromParent ( ) ; } assert ( TargetRegion . FallThroughBlock -> empty ( ) && <STR_LIT> ) ; TargetRegion . FallThroughBlock -> transferSuccessorsAndUpdatePHIs ( SourceRegion . FallThroughBlock ) ; TargetRegion . FallThroughBlock -> removeSuccessor ( SourceRegion . BranchBlock ) ; assert ( SourceRegion . BranchBlock -> empty ( ) && <STR_LIT> ) ; SourceRegion . BranchBlock -> eraseFromParent ( ) ; assert ( SourceRegion . FallThroughBlock -> empty ( ) &&


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i32gather_epi32 ( int const * base , __m128i index , const int scale ) { __v4si src = __extension__ ( __v4si ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4si mask = __extension__ ( __v4si ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~


<s> const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) GlobalBaseReg = <STR_LIT> ; else GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , TempReg ) . addReg ( GlobalBaseReg ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , <ISA_LIT>Lowering ->


<s> if ( Offset <= <NUM_LIT> ) return false ; if ( Offset % SlotSize ) return false ; int NumPops = Offset / SlotSize ; if ( NumPops != <NUM_LIT> && NumPops != <NUM_LIT> ) return false ; if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; auto & RegClass = Is64Bit ? <STR_LIT> : <STR_LIT> ; for ( auto Candidate : RegClass


<s> SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixMulHigh ( const MCInst & MI , unsigned EncodedValue ) const { EncodedValue |= <NUM_LIT> << <NUM_LIT> ; return


<s> return infer_vector_or_tuple_type ( argno


<s> if ( const auto * Entry = CostTableLookup ( NEONDupTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; } if ( Kind == TTI :: SK_Reverse ) { static const CostTblEntry NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; } if ( Kind == TTI :: SK_Select ) { static const CostTblEntry NEONSelShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost (


<s> addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) )


<s> if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm (


<s> SDValue Val = Parts [ <NUM_LIT> ] ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( PartBits ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ValueBits ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , ValueVT


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap =


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; } assert ( Opc && <STR_LIT> ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ; if ( Offset ) MI . addImm (


<s> return ( __m64 ) __builtin_ia32_pabsw ( ( __v4hi )


<s> assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( )


<s> case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getHighBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType


<s> CUMULATIVE_ARGS xstormy16_function_arg_advance ( CUMULATIVE_ARGS cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { if ( cum < NUM_ARGUMENT_REGISTERS && cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) cum = NUM_ARGUMENT_REGISTERS ; cum += XSTORMY16_WORD_SIZE ( type ,


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr )


<s> Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Shift ) ; break ; } case <NUM_LIT> : { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; break ; } case <NUM_LIT> : { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , Tmp ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op , Tmp ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } return Op ; } KnownBits Known = DAG . computeKnownBits ( Op ) ; unsigned NumSignificantBits = ( ~ Known . Zero ) . getActiveBits ( ) ; if ( NumSignificantBits == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> ,


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( IfTrue . getValueType ( ) . isVector ( ) ) return LowerVectorSELECT_CC ( Op , DAG ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , CmpOp , IfTrue , IfFalse , A64cc ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64SELECT_CC = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , SetCC , IfTrue , IfFalse , A64cc ) ; if ( Alternative


<s> return ( __m128i ) __builtin_ia32_pmovqd256_mask ( ( __v4di ) __A , ( __v4si ) _mm_undefined_si128 ( ) , ( __mmask8 ) -


<s> initialize<ISA_LIT>VSXFMAMutatePass ( PR ) ; initialize<ISA_LIT>VSXSwapRemovalPass ( PR ) ; initialize<ISA_LIT>ReduceCRLogicalsPass ( PR ) ; initialize<ISA_LIT>BSelPass ( PR ) ; initialize<ISA_LIT>BranchCoalescingPass ( PR ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR ) ; initialize<ISA_LIT>ExpandISELPass ( PR ) ; initialize<ISA_LIT>PreEmitPeepholePass ( PR ) ; initialize<ISA_LIT>TLSDynamicCallPass ( PR ) ; initialize<ISA_LIT>MIPeepholePass ( PR


<s> unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap . find ( Base ) ; if ( BI != Base2LdsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2LdsMap [ Base ] . push_back ( MI ) ; LdBases . push_back ( Base ) ; } } else { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2StsMap . find ( Base ) ; if ( BI != Base2StsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2StsMap [ Base ] . push_back ( MI ) ; StBases . push_back ( Base ) ; } } if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear ( ) ; LdBases . clear (


<s> if ( sawStore ) return true ; } if ( candidate -> getDesc ( ) . mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) ) return true ; } } return false


<s> const int LUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getNode ( <STR_LIT> , DL , CurrVT , LUTVec ) ; SDValue Op0 = DAG . getBitcast ( CurrVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Zero = getZeroVector ( CurrVT , Subtarget , DAG , DL ) ; SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , CurrVT ) ; SDValue NibbleShift = DAG . getConstant ( <NUM_LIT> , DL , CurrVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , CurrVT


<s> bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> )


<s> isFirst = isSingle = isCracked = isLoad = isStore = false ; return <STR_LIT> ; } Opcode = ~ Opcode ; const TargetInstrDesc & TID = TII . get ( Opcode ) ; isLoad = TID . mayLoad ( ) ; isStore = TID .


<s> static DecodeStatus DecodeInsSize ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; int Size = ( int ) Insn - Pos


<s> return DecodeGPRSeqPairsClassRegisterClass ( Inst , <STR_LIT> , RegNo , Addr ,


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; const bool ArePtrs64bit = ABI . ArePtrs64bit ( ) ; const TargetRegisterClass * RCp = getRegClassFor ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AlignedAddr = RegInfo . createVirtualRegister ( RCp ) ; unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RCp ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AtomicOp = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned Scratch = RegInfo . createVirtualRegister ( RC ) ; unsigned Scratch2 = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator


<s> CPUser ( MachineInstr * mi , MachineInstr * cpemi , unsigned maxdisp , bool neg , bool soimm ) : MI ( mi ) , CPEMI ( cpemi ) , MaxDisp ( maxdisp ) , NegOk

( neg ) , IsSoImm ( soimm ) , KnownAlignment ( false ) {


<s> static MachineInstr * genMadd ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , unsigned IdxMulOpd , unsigned MaddOpc , const TargetRegisterClass * RC ) { assert ( IdxMulOpd == <NUM_LIT> || IdxMulOpd == <NUM_LIT> ) ; unsigned IdxOtherOpd = IdxMulOpd == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MachineInstr * MUL = MRI . getUniqueVRegDef ( Root . getOperand ( IdxMulOpd ) . getReg ( ) ) ; unsigned ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg2 = Root . getOperand (


<s> FunctionPass * llvm :: create<ISA_LIT>DomainReassignmentPass ( ) { return new <ISA_LIT>DomainReassignment (


<s> unsigned Opc = Op . getNode ( ) -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return


<s> } if ( code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR ) { if ( ! address_operand ( op [ arg_count ] , SImode ) ) { op [ arg_count ] = convert_memory_address ( Pmode , op [ arg_count ] ) ; op [ arg_count ] = copy_addr_to_reg ( op [ arg_count ] ) ; } op [ arg_count ] = gen_rtx_MEM ( SImode , op [ arg_count ] ) ; } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ; } switch ( arg_count


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ; return


<s> int Addend = <NUM_LIT> ; switch ( getMnemonicFromOpcode ( MI . getOpcode ( ) ) ) { case FlagArithMnemonic :: ADC : case FlagArithMnemonic :: ADCX : case FlagArithMnemonic :: RCL : case FlagArithMnemonic :: RCR : case FlagArithMnemonic :: SBB : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; case FlagArithMnemonic :: ADOX : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; } unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> bool DPRRegs = llvm :: <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; unsigned Binary = <NUM_LIT> ; if ( SPRRegs || DPRRegs ) { unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg ) ; unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo = get<ISA_LIT>RegisterNumbering ( MI . getOperand ( I ) . getReg ( ) ) ; Binary |= <NUM_LIT> << RegNo ; } } return Binary


<s> Value * <ISA_LIT>IREmitter :: visitADD ( const SDNode * N ) { return IREmitter :: visitADD ( N


<s> MachineBasicBlock :: iterator T = ( MI -> getParent ( ) ) -> instr_end ( ) , E = ( MI -> getParent ( ) ) -> instr_end ( ) ; if ( T != ( MI -> getParent ( ) ) -> instr_begin ( ) ) T -- ; if ( MI != E && MI != T ) NewBB -> splice ( NewBB -> end ( ) , ( MI -> getParent ( ) ) , MI , ( MI -> getParent ( ) ) -> end ( ) ) ; else errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << MI -> getParent ( ) -> getName ( ) << <STR_LIT> << * MI << <STR_LIT> ; return


<s> word_type i ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; for ( i = ( b & <NUM_LIT> ) ; i


<s> bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear


<s> if ( ! isTypeLegal ( I -> getType ( ) , RetVT ) ) return false ; unsigned Opc ; if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else return false ; const TargetRegisterClass * RC = nullptr ; switch ( RetVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ;


<s> unsigned ReturnReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ; Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler ) ; Chain = DAG . getCopyToReg ( Chain , dl , ReturnReg , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , <STR_LIT> ) , DAG . getRegister ( AddrReg , getPointerTy


<s> if ( CSKY_FUNCTION_IS_INTERRUPT ( func_type ) ) return <STR_LIT> ; else return


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) { splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; if ( UpdatedNode != Node ) { ReplaceNode ( Node , UpdatedNode ) ; Node = UpdatedNode ; } } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getScalarSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } else if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } break ; } case <STR_LIT> : { auto * BVN = cast < BuildVectorSDNode > ( Node ) ; <ISA_LIT>VectorConstantInfo VCI ( BVN ) ; if ( VCI . isVectorConstantLegal ( * Subtarget ) ) { loadVectorConstant ( VCI , Node ) ; return ; } break ; } case <STR_LIT> : { APFloat Imm = cast < ConstantFPSDNode > ( Node ) -> getValueAPF ( ) ; if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) break ; <ISA_LIT>VectorConstantInfo VCI ( Imm


<s> int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( ! TARGET_USE_RETURN_INSN || !


<s> if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) return false ; if ( VT == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } return


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm (


<s> if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols ) ; if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack


<s> bool <ISA_LIT>AsmParser :: parseSetNoMsaDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMsa ( ) ; return false


<s> case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; case 'U' : case 'X' : assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false ; } } assert ( MI -> getOperand ( OpNo ) . isReg


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case <STR_LIT> : case <STR_LIT> : { Register Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> slowTwoMemOps ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; Push -> cloneMergedMemRefs ( MF , { & * DefMov , & * Store