<s> static SDValue combineMulToPMULDQ ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || VT . getVectorNumElements ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasSSE41 ( ) && DAG . ComputeNumSignBits ( N0 ) > <NUM_LIT> && DAG . ComputeNumSignBits ( N1 ) > <NUM_LIT> ) { auto PMULDQBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { N0 , N1 } , PMULDQBuilder , false ) ; } APInt Mask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( N0 , Mask ) && DAG . MaskedValueIsZero ( N1 , Mask ) ) { auto PMULUDQBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { N0 , N1 } , PMULUDQBuilder , false ) ; } return SDValue (


<s> rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; else if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; else gcc_unreachable ( ) ; } return get_attr_length ( insn


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF


<s> void storeCheckNAIVE ( MachineFunction & MF , MachineBasicBlock * UnrecoverableERRORBB , MachineBasicBlock * UnrecoverableERRORInter , MachineBasicBlock * RecoverableErrorBB ) { const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , I1 = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I , ++ I1 ) { bool check = true ; if ( I -> mayStore ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ;


<s> size_t <ISA_LIT>CA53ErratumStub :: alignment ( ) const { return


<s> static void arm_set_fixed_conv_libfunc ( convert_optab optable , machine_mode to , machine_mode from , const char * funcname , const char * toname , const char * fromname ) { char buffer [ <NUM_LIT> ] ; const char *


<s> else { return BuildMI ( MBB , MBBI , DL , get ( LowLowOpcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) ; } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; return BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) . addImm ( <NUM_LIT> - Size ) . addImm

( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> )


<s> GetJumpTableSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_'


<s> OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( ATOMIC_CMP_SWAP


<s> if ( VT == <STR_LIT> && Subtarget -> useCRBits ( ) ) { Register ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT ==


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ; <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping


<s> assert ( Ty . isVector ( ) && <STR_LIT> ) ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; auto Cst = get<ISA_LIT>VectorSplatScalar ( *


<s> bool <ISA_LIT>CallLowering :: lowerReturnVal ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < unsigned > VRegs , MachineInstrBuilder & Ret ) const { if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT>


<s> printSymbolLo ( MI , OpNo , O ) ; O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ==


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target


<s> FunctionPass * llvm :: create<ISA_LIT>CTRLoops ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>CTRLoops ( TM


<s> return ( uint32x4_t ) ( __a <= <NUM_LIT>


<s> SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V ) return SDValue ( ) ; SDValue VMask = DAG . getBuildVector ( VT , DL


<s> } if ( ! WidenVMOVS || ! MI -> isCopy ( ) || Subtarget . isCortexA15 ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef


<s> const char * hint = candidates_list_and_hint ( str . c_str ( ) , s , candidates ) ; if ( hint ) inform ( input_location , <STR_LIT> <STR_LIT> , s , hint ) ; else inform ( input_location , <STR_LIT> , s


<s> static rtx expand_mad ( function_expander & e , unsigned int merge_argno = DEFAULT_MERGE_ARGNO ) { if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( <NUM_LIT> ) . integer_p ) icode = code_for_aarch64_pred_fma ( e . vector_mode ( <NUM_LIT> ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLA , e


<s> MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT ,


<s> void EmitInstruction ( MCStreamer & Out , const MCInst & Inst


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; addPass ( create<ISA_LIT>ALFWriterPass ( ) )


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( GET_CODE ( pat ) != SET ) return - <NUM_LIT> ; reg = SET_DEST ( pat ) ; if ( ! REG_P ( reg ) ) return - <NUM_LIT> ; mem = SET_SRC ( pat ) ; if ( GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem


<s> for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++

BB ) Changed |= processBasicBlock ( MF , * BB ) ;


<s> if ( Subtarget -> isTargetDarwin ( ) ) return getPointerTy ( DL


<s> __builtin_ia32_pmovqd128mem_mask ( ( unsigned long long * ) __P


<s> assert ( Kind == k_Extend && <STR_LIT>


<s> assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return IsStrict ? DAG . getMergeValues ( { LHS , Chain } , dl ) : LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , LHS . getValueType ( ) ) , CCVal , DAG , dl ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; return IsStrict ? DAG . getMergeValues ( { Res , Chain } , dl ) : Res ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp ; if ( IsStrict ) Cmp = emitStrictFPComparison ( LHS , RHS , dl , DAG , Chain , IsSignaling ) ; else Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; SDValue Res ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , LHS . getValueType ( ) ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ; } else { SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; SDValue CS1 = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , CC1Val , Cmp ) ; SDValue CC2Val = DAG . getConstant ( CC2 , dl , <STR_LIT> ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , TVal , CS1 ,


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler ::


<s> <ISA_LIT>ELFWriterInfo :: <ISA_LIT>ELFWriterInfo ( TargetMachine & TM )


<s> add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args . last ( ) ) ; add_input_operand ( icode , args [ <NUM_LIT>


<s> SMShadowTracker . emitShadowPadding ( OutStreamer ,


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( Op , DAG , <STR_LIT> , <STR_LIT> ) ; return getAddrGlobal ( Op , DAG , Has<ISA_LIT>64


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true


<s> rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int len = shift_insns [ INTVAL ( XEXP ( set_src , <NUM_LIT> ) ) ] ; rtx op = XEXP ( set_src , <NUM_LIT> ) ; len += shift_insns [ INTVAL ( XEXP ( op , <NUM_LIT> ) ) ] + <NUM_LIT> ; op = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; return len + shift_insns [ INTVAL ( XEXP (


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> void emitDirectiveVariantPCS ( MCSymbol * Symbol


<s> unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back


<s> if ( ! <STR_LIT> ( N ) ) return false ; if ( LD ) * LD = cast


<s> static bool nds32_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( ! TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == <NUM_LIT> ) &&


<s> for ( int i = <NUM_LIT> , e = Ty -> getVectorNumElements ( ) ; i < e ; ++ i ) { if ( Insert ) Cost += getVectorInstrCost (

Instruction :: InsertElement , Ty , i ) ;


<s> if ( totalsize == <NUM_LIT> || elementsize == <NUM_LIT> ) return false ; auto lane = wi :: to_widest ( arg2 ) ; auto high = wi :: udiv_trunc


<s> if ( VT . getScalarSizeInBits ( ) != <NUM_LIT> ) return false ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SignBits [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; bool IsPositive [ <NUM_LIT> ] = { false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Opd = N -> getOperand ( i ) ; if ( Opd . getOpcode ( ) == <STR_LIT> ) { if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) SignBits [ i ] = <NUM_LIT> ; else if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( )


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( BVN -> isConstant ( ) ) { if ( <ISA_LIT>VectorConstantInfo ( BVN ) . isVectorConstantLegal ( Subtarget ) ) return Op ; return SDValue ( ) ; } if ( SDValue Res = tryBuildVectorShuffle ( DAG , BVN ) ) return Res ; if ( isOperationLegal ( <STR_LIT> , VT ) && isScalarToVector ( Op ) ) return buildScalarToVector ( DAG , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned NumElements = Op . getNumOperands ( ) ; SmallVector < SDValue , <STR_LIT> > Ops


<s> return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl )


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , <NUM_LIT> ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , <NUM_LIT> ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP (


<s> int i ; int hfa_size ; int byte_size ; int offset ; hfa_size = GET_MODE_SIZE ( hfa_mode ) ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( valtype ) : GET_MODE_SIZE ( mode ) ) ; offset = <NUM_LIT> ; for ( i = <NUM_LIT> ; offset < byte_size ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( hfa_mode , FR_ARG_FIRST + i ) , GEN_INT ( offset ) ) ; offset += hfa_size ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( FLOAT_TYPE_P ( valtype ) && mode != TFmode && mode != TCmode ) return gen_rtx_REG ( mode , FR_ARG_FIRST ) ; else { bool need_parallel = false ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( valtype && AGGREGATE_TYPE_P ( valtype ) ) ) ) need_parallel = true ; else if ( mode == XFmode || mode == XCmode || mode == RFmode ) need_parallel = true ; if ( need_parallel ) { rtx loc [ <NUM_LIT> ] ; int offset ; int bytesize ; int i ; offset = <NUM_LIT> ; bytesize = int_size_in_bytes ( valtype ) ; if ( bytesize == <NUM_LIT> ) return gen_rtx_REG ( mode , GR_RET_FIRST ) ; for ( i = <NUM_LIT> ; offset < bytesize ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , GR_RET_FIRST + i ) , GEN_INT ( offset ) ) ; offset += UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } return gen_rtx_REG ( mode , GR_RET_FIRST


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { if ( Info . CallConv != CallingConv :: C ) return false ; for ( auto & Arg : Info . OrigArgs ) { if ( ! isSupportedArgumentType ( Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isSRet ( ) && ! Arg . Ty -> isPointerTy ( ) ) return false ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) && ! isSupportedReturnType ( Info . OrigRet . Ty ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; const bool IsCalleeGlobalPIC = Info . Callee . isGlobal ( ) && TM . isPositionIndependent ( ) ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( Info . Callee . isReg ( ) || IsCalleeGlobalPIC ? <STR_LIT> : <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; if ( IsCalleeGlobalPIC ) { Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Info . Callee . getGlobal ( ) ) ; if ( ! Info . Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Info . Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( )


<s> bool IsPositionIndependent = isPositionIndependent ( ) ; if ( Subtarget -> useMovt ( ) && ( Subtarget -> isTargetMachO ( ) || ! IsPositionIndependent ) ) { unsigned Opc ; unsigned char TF = <NUM_LIT> ; if ( Subtarget -> isTargetMachO ( ) ) TF = <STR_LIT> ; if ( IsPositionIndependent ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { Align Alignment = DL . getPrefTypeAlign ( GV -> getType ( ) ) ; if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Alignment . value ( ) ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> :


<s> void <ISA_LIT>_64GNULDBackend :: setRelDynSize ( ) { ELFFileFormat * file_format = getOutputFormat ( ) ; file_format -> getRelaDyn ( ) . setSize ( m_pRelDyn -> numOfRelocs ( ) *


<s> if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const


<s> bool <ISA_LIT>AsmParser :: ParseDirective (


<s> <STR_LIT> , <STR_LIT> } } ; size_t i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( shell_commands ) ; i ++ ) if ( strcmp ( shell_commands [ i ] [ <NUM_LIT> ] , shell_name + <NUM_LIT> ) == <NUM_LIT> ) { fnotice ( stderr , <STR_LIT> , shell_commands [ i ] [ <NUM_LIT> ] ) ; } } if ( global_dc -> abort_on_error ) fancy_abort ( __FILE__ , __LINE__ , __FUNCTION__ ) ; exit ( FATAL_EXIT_CODE ) ; } fprintf ( stderr , <STR_LIT> , uc -> uc_mcontext -> MC_FLD ( es ) . MC_FLD ( dar ) , uc -> uc_mcontext -> MC_FLD ( ss ) . MC_FLD ( srr0 ) ) ; internal_error (


<s> declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , <STR_LIT> ) ; } } addr = convert_memory_address ( Pmode , addr ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( addr_reg , addr ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , addr_reg ) , gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , addr_reg ) , copy_to_reg ( plus_constant ( addr , <NUM_LIT> ) ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , addr_reg ) , fnaddr ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight )


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCFPmode ) ; pat = GEN_FCN ( icode ) (


<s> do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( )


<s> return __builtin_mve_vqmovntq_m_sv4si ( __a ,


<s> return ( unsigned short ) __builtin_ia32_vec_ext_v4hi ( ( __v4hi ) __A


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl <

<STR_LIT> > & Outs , LLVMContext & Context ) const {


<s> virtual unsigned getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { if ( ArgTy -> isVectorTy ( ) ) return std :: min (

DL . getABITypeAlignment ( ArgTy ) , <NUM_LIT> ) ;


<s> asm_fprintf ( asm_out_file , <STR_LIT> , arm_active_target . arch_name ) ; arm_last_printed_arch_string = arm_active_target . arch_name ; if ( ! arch -> common . extensions ) return ; for ( const struct cpu_arch_extension * opt = arch -> common . extensions ; opt -> name


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl (

) ) , TLI ( TM -> getTargetLowering ( ) ) {


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) && ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetKnownWindowsMSVC ( ) ) ) { MachineFunction & MF = DAG . getMachineFunction


<s> if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; MI -> eraseFromParent ( ) ; return true


<s> const std :: string & <ISA_LIT>CA53ErratumStub ::


<s> } aa , bb , cc , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c ) ; dd . d [ <NUM_LIT> ] = - cc . d [ <NUM_LIT> ] - aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = - cc . d [ <NUM_LIT> ] - aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] ; return ( ( qword ) ( dd . v


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } SelectCode ( Node


<s> DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) )


<s> SDValue Highest = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , <STR_LIT> ) ) ; SDValue Higher = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue HigherPart = DAG . getNode ( <STR_LIT> , DL , Ty , Highest , DAG . getNode ( <STR_LIT> , DL , Ty , Higher ) ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , Ty


<s> if ( TuneCPU . empty ( ) ) TuneCPU = <STR_LIT> ; std :: string FullFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple ) ; assert ( ! FullFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetKFreeBSD ( ) || isTargetNaCl ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit ) PreferVectorWidth


<s> case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill

) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( r ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRrAllowed = & G . getNodeMetadata ( node2 ) . getAllowedRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; assert ( edge != G . invalidEdgeId ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRrAllowed ) ; } PBQP :: Matrix costs ( G . getEdgeCosts ( edge ) ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; PBQP :: PBQPNum sameParityMax = std :: numeric_limits < PBQP :: PBQPNum > :: min ( ) ; for ( unsigned j = <NUM_LIT> , je = vRrAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRrAllowed ) [ j ] ; if ( ! haveSameParity ( pRd , pRa ) ) if ( costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] != std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) && costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] > sameParityMax )

sameParityMax = costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; SDValue CCReg = emitCmp ( DAG , DL , C ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getConstant ( C . CCMask , DL , <STR_LIT>


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue ,


<s> case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ;


<s> return ( __m512i ) __builtin_ia32_movdqa32load512_mask ( ( const __v16si * ) __P , ( __v16si ) _mm512_setzero_si512 ( ) ,


<s> static bool mayCombineMisaligned ( const TargetSubtargetInfo & STI , const MachineInstr & MI ) { unsigned Opcode = MI . getOpcode ( ) ; if ( ! isi32Load ( Opcode ) && ! isi32Store ( Opcode ) ) return true ; if ( getLoadStoreBaseOp ( MI ) . getReg ( ) == <STR_LIT> && STI . getFrameLowering ( ) -> getTransientStackAlign ( ) >= Align ( <NUM_LIT> ) ) return true ; return


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX )

) return altivec_builtin_mask_for_load ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasV6T2Ops (


<s> assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_RegisterMask : return


<s> rtl_opt_pass * make_pass_nds32_relax_opt ( gcc :: context *


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList


<s> EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value , Size )


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) ) & <NUM_LIT> )


<s> enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( def_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == def_insn ) { rtx note = find_reg_note ( def_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted (


<s> Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( ATReg ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; Instr3 = Move ; } else { TwoInstructions = true ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; } break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( ATReg ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; Instr3 . setOpcode ( <STR_LIT> ) ; Instr3 . addOperand ( Target ) ; Instr3 . addOperand ( ATReg ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( Base . getReg ( ) != Target . getReg ( ) ) ; TwoInstructions = true ; MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( Name ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( ATReg ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . setOpcode ( <STR_LIT> )


<s> unsigned long long _U_Qfcnvfxt_quad_to_udbl ( long double a ) { extern quad_type _U_Qfcnvfxt_quad_to_quad (


<s> if ( REG_P ( dest ) && REGNO ( dest ) == other_def -> regno ( ) && REG_NREGS ( dest ) == <NUM_LIT> && parallelize_insns

( cc_def , cc_set , other_def , other_set ) ) return ;


<s> if ( MinVScale != MaxVScale || MinVScale == <NUM_LIT> ) return false ; auto * PredType = ScalableVectorType :: get ( Type :: getInt1Ty ( I -> getContext ( ) ) , <NUM_LIT> ) ; auto * FixedPredType = FixedVectorType :: get ( Type :: getInt8Ty ( I -> getContext ( ) ) , MinVScale * <NUM_LIT> ) ; auto * Store = dyn_cast < StoreInst > ( I ) ; if ( ! Store || ! Store -> isSimple ( ) ) return false ; if ( Store -> getOperand ( <NUM_LIT> ) -> getType ( ) != FixedPredType ) return false ; auto * IntrI = dyn_cast < IntrinsicInst > ( Store -> getOperand ( <NUM_LIT> ) ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; if ( ! cast < ConstantInt > ( IntrI -> getOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return false ; auto * BitCast = dyn_cast < BitCastInst > (


<s> bool IsMClass = Subtarget -> isMClass ( ) ; if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT> && ! IsMClass ; } else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT>


<s> bool hasFPExtension ( ) const { return HasFPExtension


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const


<s> else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onOr ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onLShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onRShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onXor ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onAnd ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onMod ( ) ; else return false ; return


<s> void <ISA_LIT>WinCOFFStreamer :: FinishImpl ( ) { EmitFrames ( nullptr )


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case Function :: InternalLinkage : case Function :: PrivateLinkage : case Function :: LinkerPrivateLinkage : break ; case Function :: ExternalLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; break ; case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage


<s> return LPAC :: encode<ISA_LIT>AluCode ( AluCode ) == LPAC :: ADD && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == AddOffset || MI -> getOperand (

<NUM_LIT> ) . getImm ( ) == - AddOffset ) ;


<s> static __inline qword si_ceqh ( qword


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> )


<s> static unsigned computeFramePointerSaveOffset ( const <ISA_LIT>Subtarget &


<s> rtx arm_load_function_descriptor ( rtx funcdesc ) { rtx fnaddr_reg = gen_reg_rtx ( Pmode ) ; rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc


<s> const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v8s16 } , Legal ) ; setAction ( { G_FPEXT , s64 } , Legal ) ; setAction ( { G_FPEXT , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_FPTRUNC , s32 } , Legal ) ; setAction ( { G_FPTRUNC , <NUM_LIT> , s64 } , Legal ) ; setAction ( { TargetOpcode :: G_FCONSTANT , s64 } , Legal ) ; for ( const auto


<s> RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - TRI -> getEncodingValue ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( PFI -> usesPICBase ( ) ) { HasGPSaveArea = true ; int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ]


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) { MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } Register ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT>


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , Reg0 , Offset ) ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , Reg1 , Offset + <NUM_LIT> ) ) ; } else


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb1Only ( ) ? <NUM_LIT>


<s> if ( FirstRegOp != SecondRegOp ) TOut . emitRRR ( <STR_LIT> , FirstRegOp , SecondRegOp , <STR_LIT> , IDLoc , STI ) ; else TOut . emitEmptyDelaySlot ( false , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , FirstRegOp , <STR_LIT> , SecondRegOp , IDLoc , STI ) ; return false


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitStringWrapper ( MachineInstr & MI , MachineBasicBlock * MBB , unsigned Opcode ) const { MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; uint64_t End1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Start1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Start2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t CharReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t This1Reg = MRI . createVirtualRegister ( RC ) ; uint64_t This2Reg = MRI . createVirtualRegister ( RC ) ; uint64_t End2Reg = MRI . createVirtualRegister


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ; DwarfFDESymbolsUseAbsDiff = true


<s> if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get (


<s> if ( Tok . is ( AsmToken :: Identifier ) ) RegNo = matchRegisterName ( Tok . getString ( ) . lower ( ) ) ; else if ( Tok . is ( AsmToken :: Integer ) ) RegNo = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; if ( RegNo == - <NUM_LIT> ) return true ; if ( Operands ) { Operands -> push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex (


<s> int OpNum = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OutStreamer . EmitJumpTable8Region ( ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OutStreamer . EmitJumpTable16Region ( ) ; } else { OutStreamer . EmitJumpTable32Region ( ) ; } MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth == <NUM_LIT> ) { MCInst BrInst ; BrInst . setOpcode ( <STR_LIT> ) ; BrInst . addOperand ( MCOperand :: CreateExpr ( MBBSymbolExpr ) ) ; BrInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; BrInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; OutStreamer . EmitInstruction ( BrInst


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT> && <STR_LIT> ) ; const MachineConstantPoolEntry & CPE = MCP -> getConstants ( ) [ CPI ] ; assert ( ! CPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; Offset = - cast < ConstantInt > ( CPE . Val . ConstVal ) -> getSExtValue ( ) ; break ; } } if ( MAI -> getExceptionHandlingType (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> if ( Reg2 == <STR_LIT> ) return true ; if ( ! NeedsWinCFI ) return false ; if ( Reg2 == Reg1 + <NUM_LIT> ) return false ; return true


<s> if ( DECL_CONTEXT ( decl ) && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL && ! TREE_STATIC ( decl ) ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } if ( DECL_REGISTER ( decl ) ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } if ( ! TARGET_EXPLICIT_RELOCS ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , name , <STR_LIT> ) ; * no_add_attrs = true ; return NULL_TREE ; } arg = TREE_VALUE ( arg ) ; if ( TREE_CODE ( arg ) != STRING_CST ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } const char * model = TREE_STRING_POINTER ( arg ) ; if ( strcmp ( model , <STR_LIT> ) != <NUM_LIT> && strcmp ( model , <STR_LIT> ) != <NUM_LIT> ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE


<s> assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! isLegalInterleavedAccessType ( VecTy , DL ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; Type * EltTy = VecTy -> getVectorElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor -


<s> if ( GET_CODE ( set ) != SET ) return false ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! MEM_P ( mem ) || MEM_VOLATILE_P ( mem ) ) return false ; mips_split_plus ( XEXP ( mem , <NUM_LIT> ) , & this_base , & this_offset ) ; if ( ! REG_P ( this_base ) ) return false ; if ( n == <NUM_LIT> ) { if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; first_base = this_base ; first_offset = this_offset ; } else { if ( REGNO ( this_base ) != REGNO ( first_base ) || this_offset != first_offset + UNITS_PER_WORD * n ) return false ; } reg = save_p ? SET_SRC ( set ) : SET_DEST (


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( <STR_LIT> ( CC ) , S ) ) ; return MatchOperand_Success


<s> const char * getClearCacheBuiltinName ( )


<s> addExpr ( Inst , getImm ( ) ) ; return ; } assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( MCE


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t

& Offset , const TargetRegisterInfo * TRI ) const {


<s> } bool hasUnsigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; bool hasSigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; } } else if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT>


<s> __builtin_aarch64_st1v4si ( ( __builtin_aarch64_simd_si * ) a ,


<s> void addLoImm16AndOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> if ( Disable<ISA_LIT>IntABS ) return NULL ; if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand


<s> if ( ! poly_int_rtx_p ( x , & offset ) ) return - <NUM_LIT> ; return aarch64_offset_temporaries ( true


<s> MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO )


<s> return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; for ( unsigned i = <NUM_LIT> ; i != AllowedModifiers . size (


<s> O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( MO3 . getReg ( ) ) O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO3 . getReg ( ) ) . AsmName ; else if ( unsigned ImmOffs = MO2 . getImm ( ) ) { O << <STR_LIT> << ImmOffs ; if ( Scale > <NUM_LIT> ) O << <STR_LIT> << Scale ; } O <<


<s> } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % <NUM_LIT> ) == <NUM_LIT> ) && FP_REGNO_P ( last_regno ) ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return <NUM_LIT> ; if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return GET_MODE_SIZE ( mode ) <=


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [


<s> } MCSymbol * NLPSym = OutContext . GetOrCreateSymbol ( StringRef ( MAI -> getGlobalPrefix ( ) ) + MO . getSymbolName ( ) + <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( NLPSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , true ) ; O << * NLPSym ; return ; } case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) ,


<s> SmallString < <NUM_LIT> > Str ; Twine ErrorMsg = MF . getName ( ) + <STR_LIT> ; LLVMContext & Context = MF . getMMI ( ) . getModule ( ) -> getContext ( ) ; Context . emitError ( ErrorMsg


<s> if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex


<s> static SDValue emitMemMemImm ( SelectionDAG & DAG , const SDLoc & DL , unsigned Op , SDValue Chain , SDValue Dst , SDValue Src , uint64_t Size , SDValue Byte = SDValue ( ) ) { unsigned Adj = getMemMemLenAdj ( Op ) ; assert ( Size >= Adj && <STR_LIT> ) ; SDValue LenAdj = DAG . getConstant ( Size - Adj , DL , Dst . getValueType (


<s> return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned psbhint = Mapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail


<s> rtx extract_nth_access_rtx ( rtx_insn * insn , int n ) { int n_elems = parallel_elements ( insn ) ; int post_update_rtx_index = find_post_update_rtx ( insn ) ; memory_access_direction direction = determine_access_direction ( insn ) ; gcc_assert ( direction != MEM_ACCESS_DIR_UNKNOWN ) ; if ( direction == MEM_ACCESS_DIR_NEG ) n = - <NUM_LIT> * n


<s> unsigned <ISA_LIT>TTIImpl :: getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const { if ( NumPrefetches > <NUM_LIT> ) return UINT_MAX ; if ( NumStridedMemAccesses > <NUM_LIT> && NumStridedMemAccesses == NumMemAccesses && ! HasCall )


<s> return __builtin_mve_vaddq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a


<s> AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo & <NUM_LIT> ) S = MCDisassembler ::


<s> OS << <STR_LIT> ; OS << * Imm . Val ; OS << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> ; Mem . Base -> print ( OS ) ; OS << <STR_LIT> ; OS << * Mem . Off ; OS << <STR_LIT> ; break ; case


<s> State . AllocateReg ( <STR_LIT> ) ; bool AllocGPR2 = State . AllocateReg ( <STR_LIT> ) ; bool AllocGPR3 = State . AllocateReg ( <STR_LIT> ) ; if ( AllocGPR2 && AllocGPR3 ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , <STR_LIT> , LocVT , LocInfo ) ) ; return true ; } if ( ! AllocGPR2


<s> void addLO32DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr )

. addReg ( StackPtr ) . addImm ( Amount ) ;


<s> int64_t Val = MCE -> getValue ( ) ; if ( Val >> <NUM_LIT> != <NUM_LIT> && Val >> <NUM_LIT> != ~


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && ! isBR_CC ( I -> getOpcode ( ) ) && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent


<s> return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( isHReg ( Reg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT>


<s> } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex =


<s> StringRef getPassName ( ) const override { return


<s> return ( ( vec_int4 ) ( si_sfx ( ( qword ) ( b ) , ( qword ) ( a ) , ( qword ) (


<s> bool <ISA_LIT>FastISel :: SelectIToFP ( const Instruction * I , bool IsSigned ) { MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg (


<s> rtx ops [ <NUM_LIT> ] ; gcc_assert ( arm_reg0 != IP_REGNUM ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , ops ) ; output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { if ( Kind != TTI :: SK_Reverse && Kind != TTI :: SK_Alternate ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; if ( Kind == TTI :: SK_Reverse ) { static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx ] . Cost ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry < <STR_LIT> > NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index


<s> struct csky_address addr ; if ( ! decompose_csky_address ( op , & addr ) ) return false ; if ( addr . disp && GET_CODE ( addr . disp )


<s> return isTargetWatchABI ( ) || ( useWideStrideVFP


<s> assert ( Cond . size ( ) == <NUM_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectFPTrunc ( const Instruction * I ) { if ( <ISA_LIT>ScalarSSEf64 ) { if ( I -> getType ( ) -> isFloatTy ( ) ) { const Value * V = I -> getOperand (


<s> Type * RetType = F . getReturnType ( ) ; return whichFPReturnVariant ( RetType


<s> void emitARM64WinCFISaveFPLR ( int Offset ) override { OS << <STR_LIT> << Offset <<


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> EVT PtrVT = Op . getValueType ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getBlockAddress ( BA , PtrVT


( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( <NUM_LIT> << j ) ) { if ( ( j % <NUM_LIT> == <NUM_LIT> ) && ( saved_regs_mask & ( <NUM_LIT> << ( j + <NUM_LIT> ) ) ) ) { if ( offset < <NUM_LIT> ) { tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; mem = gen_frame_mem ( DImode , tmp ) ; offset = <NUM_LIT> ; } else if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , mem , gen_rtx_REG ( DImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( dwarf_index == <NUM_LIT> ) insn = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else { if ( offset < <NUM_LIT> ) { tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; mem = gen_frame_mem ( SImode , tmp ) ; offset = <NUM_LIT> ; } else if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( dwarf_index == <NUM_LIT> ) insn = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } } else j ++ ; gcc_assert ( insn


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } TypeSize ScaleValue ( <NUM_LIT> , false ) ; unsigned Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = ScaleValue . isScalable ( ) ; unsigned Scale = ScaleValue . getKnownMinSize ( ) ; int64_t Offset = IsMulVL ? SOffset . getScalableBytes ( ) : SOffset . getBytes ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable ( ) && <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) * EmittableOffset =


<s> if ( GV && GV -> isAbsoluteSymbolRef ( ) ) return <STR_LIT> ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) return <STR_LIT> ; if ( OpFlags ==


<s> int nelts = sizeof ( arm_simd_types ) / sizeof ( arm_simd_types [ <NUM_LIT> ] ) ; if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode ) ) return arm_simd_builtin_std_type ( mode , q ) ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) if ( arm_simd_types [ i ] . mode == mode && arm_simd_types [ i ] . q == q ) return arm_simd_types [ i ] . itype ; return NULL_TREE


<s> unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ]


<s> if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) { if ( arm_disable_literal_pool ) sorry ( <STR_LIT> <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == UNSPEC && XINT ( x ,

<NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ;


<s> void <ISA_LIT>MCAsmStreamer :: EmitBundleAlignMode ( unsigned


<s> void addThumbModImmNeg8_255Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE


<s> static void ix86_pad_returns ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR -> preds ) { basic_block bb = e -> src ; rtx ret = BB_END ( bb ) ; rtx prev ; bool replace = false ; if ( GET_CODE ( ret ) != JUMP_INSN || GET_CODE ( PATTERN ( ret ) ) != RETURN || ! maybe_hot_bb_p ( bb ) ) continue ; for ( prev = PREV_INSN ( ret ) ; prev ; prev = PREV_INSN ( prev ) ) if ( active_insn_p ( prev ) || GET_CODE ( prev ) == CODE_LABEL ) break ; if ( prev && GET_CODE ( prev ) == CODE_LABEL ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( EDGE_FREQUENCY ( e ) && e -> src -> index >= <NUM_LIT> && ! ( e -> flags & EDGE_FALLTHRU ) ) replace = true ; } if ( ! replace ) { prev = prev_active_insn ( ret ) ; if ( prev && ( ( GET_CODE ( prev ) == JUMP_INSN && any_condjump_p ( prev ) ) || GET_CODE ( prev ) == CALL_INSN ) ) replace = true ; if ( ! prev && cfun -> function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED ) replace = true ; } if ( replace ) { emit_insn_before ( gen_return_internal_long ( ) , ret


<s> emitRRX ( Opcode , Reg0 , Reg1 , MCOperand :: createReg ( Reg2 ) ,


<s> <STR_LIT> Pred = ( <STR_LIT> ) BI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredCond = <STR_LIT> ( Pred ) ; unsigned PredHint = <STR_LIT> ( Pred ) ; if ( PredCond == <STR_LIT> ) return <STR_LIT> ( <STR_LIT> , PredHint ) ; if ( PredCond == <STR_LIT> ) return <STR_LIT> ( <STR_LIT> , PredHint ) ; return


<s> op = lab ; do { op = next_nonnote_nondebug_insn ( op ) ; } while ( op && ( LABEL_P ( op ) || ( INSN_P ( op ) && GET_CODE ( PATTERN ( op ) ) == USE ) ) ) ; if ( ! op ) return <NUM_LIT> ; opsize = get_attr_length ( op )


<s> Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) && ! Subtarget -> isFPOnlySP ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII

. get ( Opc ) , ResultReg ) . addReg ( FP ) ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT>


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int Off = Offset ; unsigned i = <NUM_LIT>


<s> case RS6000_BIF_RECIP : if ( VECTOR_UNIT_VSX_P ( V2DFmode ) && out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ RS6000_BIF_RECIP_V2DF ] ; break ; default : break ; } machine_mode in_vmode = TYPE_MODE ( type_in ) ; machine_mode out_vmode = TYPE_MODE ( type_out ) ; if ( TARGET_POWER10 && in_vmode == out_vmode && VECTOR_UNIT_ALTIVEC_OR_VSX_P ( in_vmode ) ) { machine_mode exp_mode = DImode ; machine_mode exp_vmode = V2DImode ; enum rs6000_gen_builtins bif ; switch ( fn ) { case RS6000_BIF_DIVWE : case RS6000_BIF_DIVWEU : exp_mode = SImode ; exp_vmode = V4SImode ; if ( fn == RS6000_BIF_DIVWE ) bif = RS6000_BIF_VDIVESW ; else bif = RS6000_BIF_VDIVEUW ; break ; case RS6000_BIF_DIVDE : case RS6000_BIF_DIVDEU : if ( fn == RS6000_BIF_DIVDE ) bif = RS6000_BIF_VDIVESD ; else bif = RS6000_BIF_VDIVEUD ; break ; case RS6000_BIF_CFUGED : bif = RS6000_BIF_VCFUGED ; break ; case RS6000_BIF_CNTLZDM : bif = RS6000_BIF_VCLZDM ; break ; case RS6000_BIF_CNTTZDM : bif = RS6000_BIF_VCTZDM ; break ; case RS6000_BIF_PDEPD : bif = RS6000_BIF_VPDEPD ; break ; case RS6000_BIF_PEXTD : bif = RS6000_BIF_VPEXTD ; break ; default : return NULL_TREE ; } if ( in_mode == exp_mode && in_vmode == exp_vmode ) return rs6000_builtin_decls [ bif


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MF . getFrameInfo ( ) -> setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , TLI . getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , TLI . getPointerTy ( ) )

, DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> void addRegSPERCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> static inline bool isAdvSIMDModImmType8 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm