<s> auto AdjustReg = [ & ] ( unsigned Reg ) { auto & OrigRC = * MRI -> getRegClass ( Reg ) ; if ( & OrigRC == & SetBRC ) return Reg ; unsigned NewReg ; int OrigRegSize = TRI -> getRegSizeInBits ( OrigRC ) / <NUM_LIT> ; int TargetRegSize = TRI -> getRegSizeInBits ( SetBRC ) / <NUM_LIT> ; assert ( OrigRegSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( TargetRegSize <= <NUM_LIT> && <STR_LIT> ) ; int SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( OrigRegSize < TargetRegSize && OrigRegSize < <NUM_LIT> ) { NewReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , NewReg ) . addReg ( Reg ) ; if ( & SetBRC == & <STR_LIT> ) return NewReg ; Reg = NewReg ; OrigRegSize = <NUM_LIT> ; } NewReg = MRI -> createVirtualRegister ( & SetBRC ) ; if ( OrigRegSize < TargetRegSize ) { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewReg ) . addImm ( <NUM_LIT> ) . addReg ( Reg ) . addImm ( SubRegIdx [ OrigRegSize ] ) ; } else if ( OrigRegSize > TargetRegSize ) { if ( TargetRegSize == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { MRI -> constrainRegClass ( Reg , & <STR_LIT> ) ; } BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg , <NUM_LIT> , SubRegIdx [ TargetRegSize ] ) ; } else { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg ) ; } return NewReg


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( const MCExpr * Expr , VariantKind Kind , MCContext


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 ) -


<s> auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op1 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op0 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT ,


<s> void MVEGatherScatterLowering :: lookThroughBitcast ( Value * & Ptr ) { if ( auto * BitCast = dyn_cast < BitCastInst > ( Ptr ) ) { auto * BCTy = cast < FixedVectorType > ( BitCast -> getType ( ) ) ; auto * BCSrcTy = cast < FixedVectorType > ( BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( BCTy -> getNumElements ( ) == BCSrcTy -> getNumElements ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Ptr = BitCast -> getOperand (


<s> return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , vec_sub ( ( ( vec_float4 ) { <NUM_LIT> } ) , (


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static rtx pa_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode


<s> int getIntImmCost ( <STR_LIT> IID , unsigned Idx , const


<s> extract_base_offset_in_addr ( dest , base , offset ) ; } else if ( MEM_P ( src ) && REG_P ( dest ) ) { * is_load = true ; extract_base_offset_in_addr ( src , base , offset ) ; } else return false ; return ( * base != NULL_RTX && *


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> )


<s> return ( int32x2_t ) __builtin_neon_vmlsv2si (


<s> static const char * SerializedPrefetchPrefix = <STR_LIT> ; const ErrorOr < PrefetchHints > T = getPrefetchHints ( TopSamples , MI ) ; if ( ! T ) return false ; int16_t max_index = - <NUM_LIT> ; for ( const auto & S_V : * T ) { StringRef Name = S_V . getKey ( ) ; if ( Name . consume_front ( SerializedPrefetchPrefix ) ) { int64_t D = static_cast < int64_t > ( S_V . second ) ; unsigned IID = <NUM_LIT> ; for ( const auto & HintType : HintTypes ) { if ( Name . startswith ( HintType . first ) ) { Name = Name . drop_front ( HintType . first . size ( ) ) ; IID = HintType . second ; break ; } } if ( IID == <NUM_LIT> ) return false ; uint8_t index = <NUM_LIT> ; Name . consumeInteger ( <NUM_LIT> , index ) ; if ( index >= Prefetches . size ( ) ) Prefetches . resize ( index + <NUM_LIT> ) ; Prefetches [ index ] = { IID , D } ; max_index = std :: max ( max_index , static_cast < int16_t > ( index ) ) ; } } assert ( max_index + <NUM_LIT> >= <NUM_LIT> && <STR_LIT> ) ; assert ( static_cast < size_t > ( max_index + <NUM_LIT> ) ==

Prefetches . size ( ) && <STR_LIT> <STR_LIT> ) ;


<s> SDValue ArgValue ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } else if ( VA . isRegLoc ( ) ) { MVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack

( FI ) , false , false , false , <NUM_LIT> ) ;


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const { return


<s> static char * detect_caches_linux ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) { l1_line = <NUM_LIT> ; if ( platform [ <NUM_LIT> ] == '6' ) l1_sizekb = <NUM_LIT> ; else l1_sizekb = <NUM_LIT> ; } else { l1_line = elf_dcachebsize ( ) ; l1_sizekb = <NUM_LIT> ; } l1_assoc = <NUM_LIT> ; l2_sizekb = <NUM_LIT>


<s> return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isGVInGOT ( GV ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else if ( MF . getTarget ( ) . isPositionIndependent ( )


<s> if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( auto * EltTy : STy -> elements ( ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( EltTy , EltAlign


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; } else if ( auto * Int = dyn_cast < IntrinsicInst > ( & I ) ) { for ( auto & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) )


<s> unsigned <ISA_LIT>DAGToDAGISel :: ConstantMaterializationCost ( unsigned Val ) const { if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; }


<s> bool i386_pe_valid_dllimport_attribute_p ( const_tree decl ) { if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return


<s> static bool iq2000_pass_by_reference ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = *


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return const_cast < <ISA_LIT>TargetLowering * > ( &


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) { this -> TLOF = std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ; initAsmInfo ( )


<s> return InlineAsm :: Constraint_o ; case 'Q' : return InlineAsm :: Constraint_Q ; case 'R' : return InlineAsm :: Constraint_R ; case 'S' : return InlineAsm :: Constraint_S ; case 'T' : return InlineAsm :: Constraint_T ; } } else if ( ConstraintCode . size ( ) == <NUM_LIT>

&& ConstraintCode [ <NUM_LIT> ] == 'Z' ) {


<s> } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) ||

isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ;


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , WordSize ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) Feat00Flags |= <NUM_LIT> ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> EmitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } OutStreamer -> EmitSyntaxDirective


<s> return ( uint8x8_t ) __builtin_neon_vdup_lanev8qi ( ( int8x8_t


<s> HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; UseSqrtEst = false ; stackAlignment = <NUM_LIT>


<s> } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , spill_reg2 , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ; spill_reg2 = gen_rtx_REG ( word_mode , PIC_OFFSET_TABLE_REGNUM ) ; start_sequence ( ) ; load_pic_register ( true ) ; scratch = legitimize_pic_address ( funexp , Pmode , scratch ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_and_preserve ( seq , spill_reg , spill_reg2 ) ; } else if ( TARGET_ARCH32 ) { emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_HIGH ( SImode , funexp ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_LO_SUM ( SImode , scratch , funexp ) ) ) ; } else { switch ( sparc_cmodel ) { case CM_MEDLOW : case CM_MEDMID : sparc_emit_set_symbolic_const64 ( scratch , funexp , scratch ) ; break ; case CM_MEDANY : case CM_EMBMEDANY : spill_reg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; start_sequence ( ) ; sparc_emit_set_symbolic_const64 ( scratch , funexp , spill_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_and_preserve ( seq , spill_reg , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } emit_jump_insn ( gen_indirect_jump ( scratch ) ) ; } emit_barrier ( ) ; insn = get_insns ( ) ; insn_locators_initialize (


<s> typename std :: enable_if < IntrID == <STR_LIT> || IntrID == <STR_LIT> || IntrID == <STR_LIT> || IntrID == <STR_LIT> || IntrID == <STR_LIT> , bool > :: type <ISA_LIT>LowerAMXIntrinsics :: lowerTileDP ( Instruction * TileDP ) { Value * M , * N , * K , * C , * A , * B ; match ( TileDP , m_Intrinsic < IntrID > ( m_Value ( M ) , m_Value ( N ) , m_Value ( K ) , m_Value ( C ) , m_Value ( A ) , m_Value ( B ) ) ) ; Instruction * InsertI = TileDP ; IRBuilder < > PreBuilder ( TileDP ) ; PreBuilder . SetInsertPoint ( TileDP ) ; Value * NDWord = PreBuilder . CreateLShr ( N , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; Value * KDWord = PreBuilder . CreateLShr ( K , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; BasicBlock * Start = InsertI -> getParent ( ) ; BasicBlock * End = SplitBlock ( InsertI -> getParent ( ) , InsertI , & DTU , LI , nullptr , <STR_LIT> ) ; IRBuilder < > Builder ( TileDP ) ; Value * ResVec = createTileDPLoops < IntrID > ( Start , End , Builder , M , NDWord , KDWord , C , A , B ) ; Builder . SetInsertPoint ( End -> getFirstNonPHI ( ) ) ; Value * ResAMX = Builder . CreateBitCast ( ResVec , Type :: get<ISA_LIT>_AMXTy (


<s> EVT InVT = In . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( InVT ) && TLI . isTypeLegal ( VT ) && isSATValidOnAVX512Subtarget ( InVT , VT , Subtarget ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( auto USatVal = detectUSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT


<s> void <ISA_LIT>TargetAsmStreamer :: emitArchExtension ( unsigned ArchExt ) { OS << <STR_LIT> << <STR_LIT> ( ArchExt


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , const TargetOptions & Options , bool isLittle ) { std :: string Ret = <STR_LIT> ; if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret +=


<s> rtx ( * set_func ) ( rtx , rtx , rtx , rtx ) = ( ( mode == V2DFmode ) ? gen_vsx_set_v2df : gen_vsx_set_v2di ) ; emit_insn ( set_func ( target , target , val , GEN_INT ( elt ) ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == <NUM_LIT> ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( mask , <NUM_LIT> , i ) = GEN_INT ( i ) ; for ( i = <NUM_LIT> ; i < width ; ++ i ) XVECEXP ( mask , <NUM_LIT> , elt * width + i ) = GEN_INT ( i + <NUM_LIT> ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , <NUM_LIT> ) ) ; if ( BYTES_BIG_ENDIAN ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; else { rtx notx = gen_rtx_NOT ( V16QImode , force_reg ( V16QImode , x ) ) ; rtx iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_rtx_SET ( tmp , iorx ) ) ; x = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , reg , target , tmp


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return


<s> unsigned NewOpcode = ( ( ( unsigned ) Branch -> getOpcode ( ) ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & NewDesc = TII -> get ( NewOpcode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Branch , DL , NewDesc ) ; MIB . addReg ( Branch -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MIB . addMBB ( Branch -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; Iter tmpIter = Branch ; Branch = std :: prev ( Branch ) ; MBB . erase ( tmpIter ) ; return Branch


<s> assert ( ( isa < ScalableVectorType > ( Ty ) && isa < ScalableVectorType > ( CondTy ) ) && <STR_LIT> ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; InstructionCost LegalizationCost = <NUM_LIT> ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( Ty -> getContext ( ) ) ; unsigned CmpOpcode = Ty -> isFPOrFPVectorTy ( ) ? Instruction :: FCmp : Instruction :: ICmp ; LegalizationCost = getCmpSelInstrCost ( CmpOpcode , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) + getCmpSelInstrCost ( Instruction ::

Select , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ;


<s> void <ISA_LIT>DCBasicBlock :: materializeRegister ( unsigned RegNo


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] = {


<s> <STR_LIT> ExtraCC ; changeFPCCTo<ISA_LIT>CC ( CC , OutCC , ExtraCC ) ; if ( ExtraCC != <STR_LIT> ) { SDValue ExtraCmp ; if ( ! CCOp . getNode ( ) ) ExtraCmp = emitComparison ( LHS , RHS , CC , DL , DAG ) ; else { SDValue ConditionOp = DAG . getConstant ( Condition , DL , MVT_CC ) ; unsigned NZCV = <STR_LIT> ( ExtraCC ) ; ExtraCmp = emitConditionalComparison ( LHS , RHS , CC , CCOp , ConditionOp , NZCV , DL , DAG ) ; } CCOp = ExtraCmp ; Condition = <STR_LIT> ( ExtraCC ) ; OutCC = <STR_LIT> ( OutCC ) ; } } if ( ! CCOp . getNode ( ) ) return emitComparison ( LHS , RHS , CC , DL , DAG ) ; SDValue ConditionOp = DAG . getConstant ( Condition , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC ) ; unsigned NZCV = <STR_LIT> ( InvOutCC ) ; return emitConditionalComparison ( LHS , RHS , CC , CCOp , ConditionOp , NZCV , DL , DAG ) ; } SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool isOr = Val -> getOpcode ( ) == <STR_LIT> ; assert ( ( isOr || Val -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Negate ^= isOr


<s> tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( TARGET_SILVERMONT || TARGET_INTEL ) if ( stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval *


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> switch ( RegClassID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSIReg ? <STR_LIT> :


<s> static inline bool has_func_attr ( const_tree decl , const char * func_attr ) { if ( decl == NULL_TREE ) decl = current_function_decl ; return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl


<s> return ; } assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isFLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isFLDM ) ; } else O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; } O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg


<s> static void arm_run_selftests ( void ) { arm_test_cpu_arch_data (


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ; if ( PhysReg == <STR_LIT> ) return ( getReservedRegs ( MF ) . test


<s> Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) )


<s> return ImplicitItMode == ImplicitItModeTy :: Always || ImplicitItMode ==


<s> createSysAlias ( IC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * DC = <STR_LIT> ( Op ) ; if ( ! DC ) return TokError ( <STR_LIT> ) ; else if ( ! DC -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( DC -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( DC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( DC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * AT = <STR_LIT> ( Op ) ; if ( ! AT ) return TokError ( <STR_LIT> ) ; else if ( ! AT -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( AT -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( AT -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits


<s> SDValue Op0 = CMOV -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = CMOV -> getOperand ( <NUM_LIT> ) ; auto CCNode = cast < ConstantSDNode > ( CMOV -> getOperand ( <NUM_LIT> ) ) ; auto CC = CCNode -> getAPIntValue ( ) . getLimitedValue ( ) ; SDValue CmpZ = CMOV -> getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( CmpZ -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt * AndC = isPowerOf2Constant ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; KnownBits Known ; DAG . computeKnownBits ( Y , Known ) ; if ( ( OrCI & Known . Zero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ; } for ( unsigned BitInY = <NUM_LIT> , NumActiveBits = OrCI . getActiveBits ( ) ; BitInY < NumActiveBits ; ++ BitInY ) { if ( OrCI [ BitInY ] == <NUM_LIT> ) continue ; APInt Mask ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; Mask . setBit ( BitInY )


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst .

addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> return decodeRegisterClass ( Inst , RegNo


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm (

) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> if ( Is64Bit ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT> : <STR_LIT> ; } if ( Is64Bit ) { if ( IsLP64 ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT> : <STR_LIT> ; } bool IsNested = HasNestArgument ( & MF ) ; if ( CallingConvention == CallingConv :: <ISA_LIT>_FastCall || CallingConvention == CallingConv :: Fast ) { if ( IsNested ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return Primary ? <STR_LIT> : <STR_LIT> ; } if ( IsNested ) return


<s> Value * <ISA_LIT>IREmitter :: visitINC ( const SDNode * N ) { Value * Op0 = visit ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Constant * Initializer = Constant :: getAllOnesValue ( Op0 -> getType ( ) ) ; Value * Op1 = Initializer -> stripInBoundsConstantOffsets ( ) ; StringRef BaseName = getInstructionName ( N ) ; if ( BaseName . empty ( ) ) { BaseName = getBaseValueName ( Op0 -> getName ( ) ) ; } if ( BaseName . empty ( ) ) { BaseName = getBaseValueName ( Op1 -> getName ( ) ) ; } StringRef Name = getIndexedValueName ( BaseName


<s> bool IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Code = IsWrite ? <STR_LIT> : <STR_LIT> ; auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Code , DL , <STR_LIT>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , isLittle ( )


<s> const MachineBasicBlock * getMBB ( ) const { return


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( ! tryAddingSymbolicOperand ( tgt + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI

. addOperand ( MCOperand :: createImm ( tgt ) ) ;


<s> if ( MI -> getOperand ( i ) . isMBB ( ) ) { DestBB = MI -> getOperand ( i ) . getMBB ( ) ; break ; } } assert ( DestBB && <STR_LIT> ) ; if ( isBBInRange ( MI , DestBB , Br


<s> SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( SmallVectorImpl < MBBInfo > :: iterator BI = MBBs . begin ( ) , BE = MBBs . end ( ) ; BI != BE ; ++ BI


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB ,


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( )

-> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1


<s> case POST_MODIFY : switch ( GET_CODE ( XEXP ( XEXP ( code , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case REG : case SUBREG : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; case CONST_INT : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; default : abort ( ) ; } break ; case PLUS : switch ( GET_CODE ( XEXP ( code , <NUM_LIT> ) ) ) { case REG : case SUBREG : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; case


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix =


<s> if ( ! I -> isBranch ( ) ) break ; if ( ! getBranchInfo ( * I ) . Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return


<s> if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , Res ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y ) ; Mask = DAG . getBitcast ( BlendVT , Mask ) ; Mask = DAG . getSelect ( DL , BlendVT , Mask


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( <NUM_LIT> - Val , getContext ( ) ) , S , E ) ) ; return


<s> if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm (


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) ,

S -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) return false ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) )


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI .


<s> return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS

&& MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return <NUM_LIT> ; switch ( code ) { case SET : if ( arm_arch_thumb2 && ( i & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & <NUM_LIT> ) == <NUM_LIT> || ( ( - i ) & <NUM_LIT> ) == <NUM_LIT> ) ) return <NUM_LIT> ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED


<s> } <STR_LIT> <ISA_LIT>Pred = getComparePred ( Predicate ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrMode3OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( <STR_LIT> ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; return ( Rn << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; return ( Rn << <NUM_LIT> ) | Imm8 | ( isAdd <<


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; if ( reserve3Registers ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( reserve18Registers ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( reserve22Registers ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> static SDValue performORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT>


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src ,


<s> assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , A64cc , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT> ,


) ) _mm256_permute_pd ( __m256d __X , const int __C ) {


<s> void setHasNonRISpills ( ) { HasNonRISpills = true


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT>


<s> if ( True . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; int64_t Diff = TrueC -> getSExtValue ( ) - FalseC -> getSExtValue ( ) ; if ( Diff == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , SetCC . getValueType ( ) , SetCC , False ) ; if ( Diff == - <NUM_LIT> ) { <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; assert ( True . getValueType ( ) . isInteger ( ) ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , SetCC . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , SetCC . getValueType ( ) , SetCC , True ) ; } return SDValue (


<s> int set_once = <NUM_LIT> ; rtx y = x ; gcc_assert ( GET_CODE ( x ) == REG ) ; if ( GET_MODE ( x ) == DImode ) y = gen_rtx_REG ( SImode , REGNO ( x ) + WORDS_BIG_ENDIAN ) ; if ( flag_expensive_optimizations && df && DF_REG_DEF_COUNT ( REGNO ( y ) ) == <NUM_LIT> ) set_once = <NUM_LIT> ; if ( insn == <NUM_LIT> ) { if ( set_once ) insn = get_last_insn_anywhere ( ) ; else return <NUM_LIT> ; } while ( ( insn = PREV_INSN ( insn ) ) ) { switch ( GET_CODE ( insn ) ) { case JUMP_INSN : case NOTE : break ; case CODE_LABEL : case CALL_INSN : default : if ( ! set_once ) return <NUM_LIT> ; break ; case INSN : { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return <NUM_LIT> ; if ( rtx_equal_p ( x , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( y && rtx_equal_p ( y , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( reg_overlap_mentioned_p ( SET_DEST ( pat ) ,


<s> CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment =


<s> MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst


<s> virtual const <ISA_LIT>Subtarget * getSubtarget ( ) { return Subtarget


<s> auto MovI = MIB . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( SrcReg ) ; if ( auto * GV = dyn_cast < GlobalValue > ( V ) ) { MovI -> addOperand ( MF , MachineOperand :: CreateGA ( GV , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } else { MovI -> addOperand ( MF , MachineOperand :: CreateBA ( cast < BlockAddress > ( V ) , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } MovI -> addOperand ( MF , MachineOperand :: CreateImm ( Offset ) ) ; constrainSelectedInstRegOperands ( * MovI , TII , TRI


<s> static std :: string computeDataLayout ( const Triple & TT , bool LittleEndian ) { if ( TT . isOSBinFormatMachO ( ) ) return <STR_LIT> ; if ( LittleEndian )


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) ) ; nextOffset += FrameOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> return <STR_LIT> ; case SUBB : return <STR_LIT> ; case AND : return <STR_LIT> ; case OR : return <STR_LIT> ; case XOR : return <STR_LIT> ; case SHL : return <STR_LIT> ; case SRL : return <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseDirectiveLtorg ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; getTargetStreamer ( ) . emitCurrentConstantPool


<s> std :: string FullFS = FS ; if ( CPUString == <STR_LIT> ) { if ( FullFS . empty ( ) ) FullFS = <STR_LIT> ; else FullFS =


<s> void <ISA_LIT>TargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue ,


<s> if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; } else { if ( Subtarget -> useMovt ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV


<s> static bool definesCPSR ( MachineInstr * MI ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI ->


<s> unsigned SubReg ; if ( getMinSizeForRegBank ( SrcRegBank ) > DstSize ) { const TargetRegisterClass * DstTempRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; getSubRegForClass ( DstRC , TRI , SubReg ) ; MachineIRBuilder MIB ( I ) ; auto Copy = MIB . buildCopy ( { DstTempRC } , { SrcReg } ) ; copySubReg ( I , MRI , RBI , Copy . getReg ( <NUM_LIT> ) , DstRC , SubReg ) ; } else if ( SrcSize > DstSize ) { const TargetRegisterClass * SubRegRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SubRegRC , TRI , SubReg ) ; copySubReg ( I , MRI , RBI , SrcReg , DstRC , SubReg ) ; } else if ( DstSize > SrcSize ) { const TargetRegisterClass * PromotionRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SrcRC , TRI , SubReg ) ; Register PromoteReg = MRI . createVirtualRegister ( PromotionRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , PromoteReg ) . addImm ( <NUM_LIT> ) . addUse ( SrcReg ) . addImm ( SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( PromoteReg ) ; KnownValid = true ; } if ( Register :: isPhysicalRegister ( DstReg ) ) return CheckCopy ( ) ; } if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) <<


<s> default : return <NUM_LIT> ; case PROCESSOR_NIAGARA4 : case PROCESSOR_V9 : return <NUM_LIT> ; case PROCESSOR_SUPERSPARC : return <NUM_LIT> ; case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : return <NUM_LIT> ; case PROCESSOR_ULTRASPARC : case


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( Subtarget . hasAVX ( ) && VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; return SDValue


<s> return tryReplaceCopy ( MI ) ; case <STR_LIT> : return tryReplaceExtend ( <STR_LIT> , MI ) ; case <STR_LIT> : return tryReplaceExtend ( <STR_LIT> , MI ) ; case <STR_LIT> : return tryReplaceExtend ( <STR_LIT> , MI ) ; case <STR_LIT> : return tryReplaceExtend ( <STR_LIT> , MI ) ; default : break ; } return nullptr


<s> Comparison C ( CmpOp0 , CmpOp1 , Chain ) ; C . CCMask = CCMaskForCondCode ( Cond ) ; if ( C . Op0 . getValueType ( ) . isFloatingPoint ( ) ) { C . CCValid = <STR_LIT> ; if ( ! C . Chain ) C . Opcode = <STR_LIT> ; else if ( ! IsSignaling ) C . Opcode = <STR_LIT> ; else C . Opcode = <STR_LIT> ; adjustForFNeg ( C ) ; } else { assert ( ! C . Chain ) ; C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( C . Op0 ) && DAG . SignBitIsZero ( C . Op1 ) ) ) C . ICmpType = <STR_LIT> ; else if ( C . CCMask & <STR_LIT> ) C . ICmpType = <STR_LIT> ; else C . ICmpType = <STR_LIT> ; C . CCMask &= ~ <STR_LIT> ; adjustForRedundantAnd ( DAG , DL , C ) ; adjustZeroCmp ( DAG , DL , C ) ; adjustSubwordCmp ( DAG , DL


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> static inline void rws_insn_set ( int regno ) { gcc_assert ( ! TEST_HARD_REG_BIT ( rws_insn , regno ) ) ; SET_HARD_REG_BIT ( rws_insn ,


<s> AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ; MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( AddrIn ) . addImm ( LdSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( LdSize ) ) ; } else { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addReg ( <NUM_LIT>


<s> static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = OpLHS .


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast


<s> enum tls_model tls_symbolic_operand ( rtx op

, machine_mode mode ATTRIBUTE_UNUSED ) {


<s> if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg (

) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;


<s> return ( __m64 ) __builtin_arm_waddhus ( ( __v4hi )


<s> static bool isVShiftLImm ( SDValue Op , EVT VT , bool isLong , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getVectorElementType (


<s> if ( GET_CODE ( x ) != TRUNCATE ) return <NUM_LIT> ; reg = XEXP ( x , <NUM_LIT> ) ; if ( GET_MODE_SIZE ( GET_MODE ( reg ) ) > <NUM_LIT> && GET_CODE ( reg ) ==


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; printOffset ( MO . getOffset ( ) , O ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' )


<s> if ( IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC , val ) ; else fprintf ( file , TARGET_AS100_SYNTAX ? <STR_LIT> HOST_WIDE_INT_PRINT

<STR_LIT> : HOST_WIDE_INT_PRINT_HEX , val ) ;


<s> return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( ) ) ; APInt C2Int = C2 -> getAPIntValue ( ) ; APInt C1Int = C1ShlC2 -> getAPIntValue ( ) ; APInt Mask = APInt :: getHighBitsSet ( C2Int . getBitWidth ( ) , C2Int . getBitWidth ( ) - C2 -> getZExtValue ( ) ) ; if ( ( C1Int & Mask ) != C1Int ) return SDValue ( ) ; C1Int . lshrInPlace ( C2Int ) ; unsigned Zeros = C1Int . countLeadingZeros ( ) + C1Int . countTrailingZeros ( ) ; if ( C1Int . getBitWidth ( ) - Zeros > <NUM_LIT> ) return SDValue ( ) ; Zeros = C2Int . countLeadingZeros ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> static const char * aarch64_invalid_unary_op ( int op , const_tree type ) { if ( element_mode ( type ) == BFmode && op != ADDR_EXPR ) return


<s> case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return lowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op


<s> const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & <STR_LIT> ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += <NUM_LIT> ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( <NUM_LIT> ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( )


<s> auto Const = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; auto * NewConst = ConstantInt :: get ( Ctx , Const -> getValue ( ) . abs ( ) ) ; Builder . SetInsertPoint ( I ) ; Value * NewVal = Builder . CreateSub ( I -> getOperand ( <NUM_LIT> ) , NewConst ) ; if ( auto * NewInst = dyn_cast < Instruction > ( NewVal ) ) { NewInst -> copyIRFlags ( I ) ; NewInsts . insert ( NewInst ) ; } InstsToRemove . insert ( I ) ; I -> replaceAllUsesWith ( NewVal


<s> unsigned NumNonZero = <NUM_LIT> ; uint64_t NonZeros = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) { SDValue SubVec = Op . getOperand ( i ) ; if ( SubVec . isUndef ( ) ) continue ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) ++ NumZero ; else { assert ( i < sizeof ( NonZeros ) * CHAR_BIT ) ; NonZeros |= ( uint64_t ) <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero <= <NUM_LIT> ) { SDValue Vec = NumZero ? getZeroVector ( ResVT , Subtarget , DAG , dl ) : DAG . getUNDEF ( ResVT ) ; if ( ! NumNonZero ) return Vec ; unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands


<s> return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 )


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const


<s> if ( index_term_p ( xfoo0 , mode , strict ) && nonindexed_address_p ( xfoo1 , strict ) ) return <NUM_LIT> ; if ( index_term_p ( xfoo1 , mode , strict ) && nonindexed_address_p ( xfoo0 , strict ) ) return <NUM_LIT> ; if ( indirectable_constant_address_p ( xfoo0 ) && ( BASE_REGISTER_P ( xfoo1 , strict ) || reg_plus_index_p ( xfoo1 , mode , strict ) ) ) return <NUM_LIT> ; if ( indirectable_constant_address_p ( xfoo1 ) && ( BASE_REGISTER_P ( xfoo0 , strict )

|| reg_plus_index_p ( xfoo0 , mode , strict ) ) ) return <NUM_LIT> ;


<s> if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget


<s> virtual bool isDeadInstruction ( const MachineInstr * MI


<s> unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx


<s> } } if ( ( ! CCRefs && convertToLoadAndTest ( MI , Compare , CCUsers ) ) || ( ! CCRefs . Def && ( adjustCCMasksForInstr ( MI , Compare , CCUsers ) || convertToLogical ( MI , Compare , CCUsers ) ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; if ( Compare . mayRaiseFPException ( ) && ( MI . isCall ( ) || MI . hasUnmodeledSideEffects ( ) ) ) break ; } auto MIRange = llvm :: make_range ( std :: next ( MachineBasicBlock :: iterator ( & Compare ) ) , MBB . end ( ) ) ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( MIRange ) ) { if ( preservesValueOf ( MI , SrcReg ) ) { if ( convertToLoadAndTest ( MI , Compare , CCUsers ) ) { EliminatedComparisons += <NUM_LIT> ; return


<s> for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const auto * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { auto * First = dyn_cast < User > ( Pair . first ) ; auto * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) && ! isa < Constant > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; auto * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set (


<s> case <STR_LIT> : case <STR_LIT> : return combineSIntToFP ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineVTRUNC ( N , DAG , DCI ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineCVTPH2PS ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineEXTEND_VECTOR_INREG ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorHADDSUB ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; Expr = <ISA_LIT>MCExpr :: create ( Kind ,


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : break ; default : return false ; } if ( isa < MCBinaryExpr > ( BE -> getLHS ( ) ) ) { if ( ! isa < MCConstantExpr > ( BE -> getRHS ( ) ) ) return false ; BE = cast < MCBinaryExpr > ( BE -> getLHS ( ) ) ; } return ( isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) && isa

< MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) ;


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( IdxMode == <STR_LIT> ) { printAM3PostIndexOp ( MI , Op , O ) ; return ; } printAM3PreOrOffsetIndexOp ( MI , Op ,


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , copyMoveD ) ; return NULL


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false


<s> SDValue Ops [ ] = { GA , Reg } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , VT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction (

) ) , <NUM_LIT> , false , true , false , <NUM_LIT> ) ;


<s> inline int getFP32FP16Imm ( const APFloat


<s> return false ; } if ( ! LocalSData && GVA -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; if ( EmbeddedData && GVA -> isConstant ( )


<s> Type * OpTy = IntegerType :: get ( getContext ( ) , OpSize * <NUM_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( getContext ( ) , OldSP -> getType ( ) -> getIntegerBitWidth ( ) ) , OpSize ) ; Value * NewSP = Builder . CreateAdd


<s> bool isCCRegNumber ( ) const { return Kind == Immediate &&


<s> return RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> )

|| RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) ;


<s> } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) LLVM_OVERRIDE { if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( raw_ostream & O ) ; void printHex32 ( unsigned int Value , raw_ostream & O ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ; virtual void EmitFunctionBodyEnd ( ) ; virtual bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = <NUM_LIT> ) ; void EmitStartOfAsmFile ( Module


<s> } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >>


<s> static __inline int __get_cpuid_count ( unsigned int __leaf , unsigned int __subleaf , unsigned int * __eax , unsigned

int * __ebx , unsigned int * __ecx , unsigned int * __edx ) {


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize =

( maxCallFrameSize + AlignMask ) & ~ AlignMask ;


<s> if ( asm_switch -> nesting_level == <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , prefix ,


<s> int Offset = <NUM_LIT> ; if ( ExtraCode ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) )


<s> SDLoc DL ( Op ) ; const unsigned NumFields = <NUM_LIT> ; SDValue Fields [ NumFields ] = { DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , DL , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , DL , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields


<s> CStringSection = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; DwarfRequiresFrameSection = false ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection =


<s> if ( ! Subtarget -> isTargetDarwin ( ) )


<s> unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; return


<s> explicit <ISA_LIT>ScalarTargetTransformImpl ( const TargetLowering * TL ) : ScalarTargetTransformImpl ( TL ) , Subtarget ( & TL -> getTargetMachine ( ) . getSubtarget


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasOpaqueSPAdjustment ( ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned BaseReg = TRI -> getBaseRegister ( ) ; for ( unsigned R : ClobberSet ) if ( BaseReg == R ) return true ; return false


<s> bool <ISA_LIT>TTIImpl :: forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) { unsigned NumElts = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ; return NumElts == <NUM_LIT> || ( ST -> hasAVX512 ( ) && ( NumElts == <NUM_LIT> || ( NumElts


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned RBegin , REnd ; if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; } else { unsigned RBeginIdx = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; RBegin = RBeginIdx == <NUM_LIT> ? ( unsigned ) <STR_LIT> : GPRArgRegs [ RBeginIdx ] ; REnd = <STR_LIT> ; } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd


<s> Parser . Lex ( ) ; const MCExpr * Expr ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( Expr ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocOption ( Val , S , E ) ) ; return MatchOperand_Success


<s> if ( ! Kind . empty ( ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const char * ZM = Pred == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ZM , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( )


<s> MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) ; RegInfo . addLiveIn ( <STR_LIT> ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg


<s> rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; regno +=


<s> * epilogue_cost = costs -> region [ vect_epilogue ] ; if ( costs -> is_loop && costs -> vec_flags && aarch64_use_new_vector_costs_p ( ) ) * body_cost = aarch64_adjust_body_cost (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm -> getValue ( ) / <NUM_LIT> ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType


<s> if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> ; } else if ( arg . type && int_size_in_bytes ( arg . type ) == - <NUM_LIT> ) return true ; } return


<s> else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops , DL


<s> Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler ::


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! IsStore )


<s> if ( ConstantSDNode * StoreOffset = dyn_cast < ConstantSDNode > ( StorePtr1 [ i ] ) ) if ( ConstantSDNode * LoadOffset = dyn_cast < ConstantSDNode > ( Ptr1 ) ) { int StoreOffs = StoreOffset -> getZExtValue ( ) ; int LoadOffs = LoadOffset -> getZExtValue ( ) ; if ( StoreOffs < LoadOffs ) { if ( int ( StoreOffs + StoreSize [ i ]


<s> ~ <ISA_LIT>AsmBackend ( ) { delete STI


<s> break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'r' : case 'v'


) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto =


<s> void printMemOffs8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( Value ) * Value = Offset ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; } MI . getOperand ( i ) . ChangeToRegister ( ScratchReg , false , false , true ) ; if ( ! ReuseFrameIndexVals )


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: Win32 ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: MinGW32 || TheTriple . getOS ( ) == Triple :: Cygwin ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; MachineLocation Dst ( MachineLocation


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFILL_FW ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; printInstruction ( MI ,


<s> SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT>


<s> unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == <NUM_LIT> || DataSize == <NUM_LIT> ) ) return DataSize == <NUM_LIT> ? ST -> hasSSE1


<s> <ISA_LIT>CTRLoopsVerify ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>CTRLoopsVerifyPass ( * PassRegistry :: getPassRegistry (


<s> REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) && ! REAL_VALUE_MINUS_ZERO (


<s> static bool ix86_rop_should_change_byte_p ( int


<s> break ; case ELF :: R_<ISA_LIT>_ABS32 : InNormalSection = StringSwitch < bool > ( Section . getSectionName ( ) ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Default ( true ) ; EmitThisSym = false ; break ; } } else { NonPCRelCount ++ ; InNormalSection = StringSwitch < bool > ( Section . getSectionName ( ) ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Case ( <STR_LIT> , false ) . Default ( true ) ; switch ( RelocType ) { default : EmitThisSym = true ; break ; case ELF :: R_<ISA_LIT>_ABS32 : EmitThisSym = false ; break ; case ELF :: R_<ISA_LIT>_PREL31 : EmitThisSym = false ; break ; } } if ( EmitThisSym ) return


<s> if ( getLexer ( ) . is ( AsmToken :: LBrac ) && parseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && parseParenSuffix ( Name , Operands ) ) return true ; } } if ( getLexer ( ) . isNot ( AsmToken ::


<s> SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ; else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL ,

VT , NN , DAG . getConstant ( - SarConst , DL , CVT ) ) ;