<s> MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_TLSGD : Variant = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case MCSymbolRefExpr :: VK_TLSLD : Variant = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLD ; break ; default : return E ; } return MCSymbolRefExpr :: create ( & SRE -> getSymbol ( ) , Variant , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = FixupVariantKind ( UE -> getSubExpr ( ) ) ; if ( Sub == UE -> getSubExpr ( ) ) return E ; return MCUnaryExpr :: create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; const MCExpr * LHS = FixupVariantKind ( BE -> getLHS ( ) ) ; const MCExpr * RHS = FixupVariantKind (


<s> SDValue Counts16 = lowerCTPOP16BitElements ( Bitcast . getNode ( ) , DAG ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N1 , N1 ) ; if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else


<s> bool CompactUnwind = MF . getMMI ( ) . getContext ( ) . getObjectFileInfo ( ) -> getCompactUnwindSection ( ) != nullptr ; return ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) || ! CompactUnwind ) && MF .

getFunction ( ) . getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ;


<s> bool checkVLDnAccessAlignment ( ) const { return CheckVLDnAlign


<s> SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE


<s> return Create ( VK_<ISA_LIT>_HA16 , Expr ,


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isLikeA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) )


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions &


<s> return isTargetDarwin ( ) || ( ! isTargetWindows ( ) && isThumb (


<s> assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I


<s> unsigned CurOp = <STR_LIT> ( Desc ) ; for ( unsigned i = CurOp ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) UsesHighByteReg = true ; if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI ,


<s> if ( is<ISA_LIT>64 ( ) ) addRegG8RCOperands ( Inst , N ) ; else addRegGPRCOperands ( Inst , N


<s> int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = isSVEScaledImmInstruction ( MI . getOpcode ( ) ) ; int64_t Offset = IsMulVL ? ( SOffset . getScalableBytes ( ) ) : ( SOffset . getBytes ( ) ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) *


<s> } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> ,


<s> unsigned Start = <NUM_LIT> ; unsigned End = NumSectionElts / <NUM_LIT> ; for ( unsigned s = <NUM_LIT> ; s < NumSections ; ++ s ) { for ( unsigned i = Start ; i != End ; ++ i ) { ShuffleMask . push_back ( i ) ; ShuffleMask . push_back ( i + NumSectionElts ) ; } Start += NumSectionElts ; End += NumSectionElts


<s> if ( sign1 != sign2 ) return MCDisassembler :: Fail ; unsigned Val = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= sign1 << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler ::


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB


<s> uint32_t getAddrModeThumbSPOpValue ( const MachineInstr &


<s> uint64_t <ISA_LIT>FrameLowering :: getAllocatedStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFFrame = MF . getFrameInfo


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return


<s> __vector signed int vm1 ; __vector signed short vresult ; vm1 = ( __vector signed int ) __builtin_pack_vector_int128 ( __m2 , __m1 ) ; vresult = vec_vpkswss ( vm1


<s> if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes

&& llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { rtx ( * gen_x86_shift_adj_1 ) ( rtx , rtx , rtx , rtx ) = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1 ; emit_move_insn ( scratch , high [ <NUM_LIT> ] ) ; emit_insn ( gen_ashr3 ( scratch , scratch , GEN_INT ( half_width - <NUM_LIT>


<s> if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> &&


<s> bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg

, isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;


<s> if ( ! Subtarget . hasAltivec ( ) ) return CSR_NoRegs_Altivec_RegMask ; if ( Subtarget . isDarwin ( )


<s> FunctionPass * llvm :: createA15SDOptimizerPass ( ) { return new A15SDOptimizer (


<s> O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) printMachineInstruction ( II ) ; } if ( TAI -> hasDotTypeDotSizeDirective ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << '\n' ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; return false


<s> assert ( Emitted && <STR_LIT> ) ; ( void ) Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset (


<s> static __inline qword si_ceqh ( qword a ,


<s> bool hasMiscellaneousExtensions3 ( ) const


<s> unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment ( Inst ) ; if ( BA ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitCodeAlignment ( BA


<s> if ( I -> getScalarSizeInBits ( ) * cast < FixedVectorType > ( I ) -> getNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) + getMemoryOpCost ( Instruction :: Load , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) ; } return * Cost . getValue (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHPrologEnd ( SMLoc L ) { getTargetStreamer ( ) . EmitARM64WinCFIPrologEnd (


<s> for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( <NUM_LIT> <= Mask [ i ] ) return false ; return


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> if ( Flags . isSExt ( ) ) return CCValAssign :: LocInfo :: SExt ; if ( Flags . isZExt ( ) ) return CCValAssign :: LocInfo :: ZExt ; return CCValAssign ::


<s> bool HasHazard = Candidate . isImplicitDef ( ) ; HasHazard |= IM . hasHazard ( Candidate ) ; HasHazard |= RegDU . update ( Candidate , <NUM_LIT>


<s> return ( int16x8_t ) __builtin_neon_vhaddsv8hi ( __a ,


<s> bool loongarch_global_symbol_p ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return false ; const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x )


<s> Label = CurDAG -> getTargetConstant ( cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } return false


create<ISA_LIT>CompressJumpTablesPass ( ) {


<s> bool isPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI , isPIC ) ; BPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( )


<s> static rtx or1k_legitimize_address ( rtx x , rtx , machine_mode


<s> StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; FFI -> setMaxAlignment ( MaxAlign ) ; return


<s> else return false ; Register DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { Register ImpDefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImpDefReg ) ; DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: INSERT_SUBREG ) , DefReg ) . addReg ( ImpDefReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI ,


<s> void <ISA_LIT>InstPrinter :: printThumbITMask ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned Firstcond = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Firstcond & <NUM_LIT> ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; --


<s> } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) } ; std :: vector < EVT > VTs ; VTs . push_back ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; VTs . push_back ( <STR_LIT> ) ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit


<s> FixupLEAPass ( ) : MachineFunctionPass ( ID ) { initializeFixupLEAPassPass ( * PassRegistry :: getPassRegistry


<s> emitPGORefs ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_<ISA_LIT>_AIX_TLSGDM ) { SmallString < <NUM_LIT> > Name ; StringRef Prefix = <STR_LIT> ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else


<s> std :: vector < <ISA_LIT>FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlign ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF


<s> return isThumb1 ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; case <STR_LIT> : return isThumb1 ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; case <STR_LIT> : return Align ( <NUM_LIT> ) ; case


<s> bool <ISA_LIT>TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < <NUM_LIT> || DataSize > <NUM_LIT> || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == <NUM_LIT> ) return ST -> hasAVX ( ) ; if ( DataSize == <NUM_LIT> ) return ST -> hasSSE1 ( ) ; return true


<s> LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return


<s> return ( __mmask8 ) __builtin_ia32_ucmpq128_mask ( ( __v2di ) __X , ( __v2di )


<s> if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue V = lowerShuffleAsVTRUNC ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue V = lowerShuffleAsByteShiftMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; int NumEvenDrops = canLowerByDroppingEvenElements ( Mask , false ) ; if ( ( NumEvenDrops == <NUM_LIT> || NumEvenDrops == <NUM_LIT> ) && Subtarget . hasSSE41 ( ) && ! Subtarget . hasVLX ( ) ) { SmallVector < SDValue , <NUM_LIT> > DWordClearOps ( <NUM_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> << ( NumEvenDrops - <NUM_LIT> ) ) DWordClearOps [ i ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue DWordClearMask = DAG . getBuildVector ( <STR_LIT> , DL , DWordClearOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DWordClearMask ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DWordClearMask ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1


<s> case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ; return true ; } return false


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return FixUpUnconditionalBr ( Fn , Br ) ; return FixUpConditionalBr ( Fn ,


<s> if ( Op . getType ( ) != MachineOperand :: MO_Immediate ) return std :: string ( ) ; int FirstPredOp = MI . findFirstPredOperandIdx ( ) ; if ( FirstPredOp != ( int ) OpIdx ) return std :: string ( ) ; std :: string CC = <STR_LIT>


, V1 ) , DAG . getBitcast ( <STR_LIT> , V2 ) , Mask ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { VShiftOpc = <STR_LIT> ; break ; } if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) { VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc =


<s> return InsertSubVector ( Result , Vec , IdxVal


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Vcarryin = N -> getOperand ( <NUM_LIT> ) ; SDNodeTreeBuilder b ( & DAG , dl ) ; if ( DCI . isBeforeLegalize ( ) && ( ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) || ( Subtarget -> hasAVX ( ) && VT == <STR_LIT> ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( ) ) ; SDValue Ret = LongStreamAddition ( VT , V1 , V2 ,


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_es ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Z ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Zy ; return TargetLowering :: getInlineAsmMemConstraint (


<s> const MCExpr * getSubExpr ( ) const { return Expr


<s> machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return <NUM_LIT> ; return Subtarget -> isThumb ( ) ? <STR_LIT>


<s> rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr = reg ; } x = replace_equiv_address ( x ,


<s> if ( ResTy != MatchOperand_Success ) return ResTy ; if ( ! getLexer ( ) . is ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } std :: unique_ptr < <ISA_LIT>Operand > Op ; ResTy = parse<ISA_LIT>AsmOperand ( Op , ( Mnemonic == <STR_LIT> ) ) ; if ( ResTy != MatchOperand_Success || ! Op ) return MatchOperand_ParseFail ; Operands . push_back ( std ::


<s> <ISA_LIT>PostRASchedStrategy :: ~ <ISA_LIT>PostRASchedStrategy ( ) { for ( auto I


<s> } ; if ( ! canShrinkOp ( LHS ) && ! canShrinkOp ( RHS ) ) return false ; IRBuilder < > Builder ( Add ) ; auto * MulTy = cast < VectorType > ( Op -> getType ( ) ) ; unsigned NumElts = MulTy -> getNumElements ( ) ; SmallVector < int , <NUM_LIT> > EvenMask ( NumElts / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > OddMask ( NumElts / <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i != e ; ++ i ) { EvenMask [ i ] = i * <NUM_LIT> ; OddMask [ i ] = i * <NUM_LIT> + <NUM_LIT> ; } Value * EvenElts = Builder . CreateShuffleVector ( BO , BO , EvenMask ) ; Value * OddElts = Builder . CreateShuffleVector ( BO , BO , OddMask ) ; Value * MAdd = Builder . CreateAdd ( EvenElts


<s> SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != NULL && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = Subtarget -> isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode


<s> std :: unique_ptr < MCObjectTargetWriter

> create<ISA_LIT>WinCOFFObjectWriter ( ) {


<s> bool isTargetELF ( ) const { return TargetTriple . isOSBinFormatELF (


<s> if ( IsZExt ) { unsigned ResultReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ResultReg && <STR_LIT> ) ; if ( DestVT == <STR_LIT> ) { unsigned Reg64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg ) . addImm ( <STR_LIT> ) ; ResultReg = Reg64 ; } return ResultReg ; } else { if ( DestVT == <STR_LIT> ) { return <NUM_LIT> ; } return fastEmitInst_rii ( <STR_LIT> , & <STR_LIT> , SrcReg , false


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( The<ISA_LIT>_64Target )


<s> return new <ISA_LIT>EncodeLiteralsPass (


<s> int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? Register ( TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> virtual const char * getPassName ( ) const


<s> void setLeafProc ( bool rhs ) { IsLeafProc = rhs


<s> return ( __m128i ) __builtin_ia32_phminposuw128 ( ( __v8hi


<s> int iq2000_can_use_return_insn ( void ) { if ( ! reload_completed ) return <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] ||


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> if ( MI . isDebugInstr ( ) || MI . isKill ( ) ) return Sum ; return Sum + <NUM_LIT> ; } ) ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerTailCall , <NUM_LIT> ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , <NUM_LIT> , MachineOutlinerTailCall ) ; } for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo

( MachineOutlinerDefault , <NUM_LIT> ) ;


<s> unsigned Shift1Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg (


<s> inline vector unsigned char vec_andc ( vector unsigned char a1 , vector unsigned char a2 ) { return ( vector unsigned char ) __builtin_altivec_vandc ( ( vector signed int ) a1 , ( vector


<s> return static_cast < VariantKind > ( Kind &


<s> if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) { Imm = Val


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( !

Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> return getSubtargetImpl ( ) -> getInstrInfo


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register BasePtr ; int64_t Offset = ( TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getDebugOffset ( ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) { if ( OpcodeForOffset == <STR_LIT> && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVector ( ) ) { OpcodeForOffset = <STR_LIT> ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB ,


<s> bool AtStart = I == MBB . begin ( ) ; if ( ! AtStart ) -- BeforeI ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; } return true


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; Lower<ISA_LIT>MachineOperandToMCOperand ( MO ,


<s> void llvm :: Lower<ISA_LIT>MachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , AsmPrinter & AP ) { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp = LowerOperand ( MI , MO , AP ) ; if ( MCOp . isValid ( ) )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Op -> SysCRImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , NULL , <NUM_LIT> ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , getTargetMachine ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MinReservedArea = std :: max ( MinReservedArea , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( false , false ) ) ; unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; MinReservedArea = ( MinReservedArea + AlignMask ) & ~ AlignMask ; FI -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const unsigned GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const unsigned FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; VarArgsNumGPR = CCInfo . getFirstUnallocated ( GPArgRegs , NumGPArgRegs ) ; VarArgsNumFPR = CCInfo . getFirstUnallocated ( FPArgRegs , NumFPArgRegs ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * EVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; VarArgsStackOffset = MFI -> CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) ) ; VarArgsFrameIndex = MFI -> CreateStackObject ( Depth , <NUM_LIT> ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; unsigned GPRIndex = <NUM_LIT> ; for ( ; GPRIndex != VarArgsNumGPR ; ++ GPRIndex


<s> static <STR_LIT> classifySecond ( const MachineInstr & MI ) { <STR_LIT> CC = <STR_LIT> ( MI


<s> if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } if ( NumSubs == <NUM_LIT> ) return Builder ( DAG , DL , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Subs ; for ( unsigned i = <NUM_LIT> ; i != NumSubs ; ++ i ) { SmallVector < SDValue , <NUM_LIT> > SubOps ; for ( SDValue Op : Ops ) { EVT OpVT = Op . getValueType ( ) ; unsigned NumSubElts = OpVT . getVectorNumElements ( ) / NumSubs ; unsigned SizeSub = OpVT . getSizeInBits ( ) / NumSubs ; SubOps . push_back ( extractSubVector ( Op , i * NumSubElts , DAG , DL , SizeSub ) ) ; } Subs . push_back ( Builder ( DAG ,


<s> bool hasThreeDNow ( ) const { return <ISA_LIT>3DNowLevel >=


<s> if ( OptimizationGoals == - <NUM_LIT> ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = <NUM_LIT> ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( TIP . first ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; } ThumbIndirectPads . clear ( ) ; } return false


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ,


<s> void <ISA_LIT>InstPrinter :: printAddSubImmLSL0Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Imm12Op = MI -> getOperand ( OpNum ) ; if ( Imm12Op . isImm ( ) ) { int64_t Imm12 = Imm12Op . getImm ( ) ; assert ( Imm12 >= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << Imm12 ; }


<s> if ( ST -> getDarwinDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount


<s> if ( m_pEXIDX != NULL && m_pEXIDX -> size ( ) != <NUM_LIT> ) { ELFSegment * exidx_seg = elfSegmentTable ( ) . produce ( llvm :: ELF :: PT_<ISA_LIT>_EXIDX , llvm


<s> rtx condition_rtx , cr ; if ( GET_MODE ( rs6000_compare_op0 ) != SImode ) return <NUM_LIT> ; condition_rtx = rs6000_generate_compare ( GET_CODE ( op ) ) ; cr = XEXP ( condition_rtx , <NUM_LIT> ) ; if ( GET_MODE ( cr ) == CCmode ) emit_insn ( gen_isel_signed ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; else emit_insn ( gen_isel_unsigned ( dest , condition_rtx , true_cond


<s> return ( __m128i ) vec_mergel ( ( __vector long long ) __A , ( __vector long


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSizeInsEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup


<s> void i386_pe_adjust_class_at_definition ( tree t ) { tree member ; gcc_assert ( CLASS_TYPE_P ( t ) ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) == NULL_TREE ) return ; for ( member = TYPE_FIELDS ( t ) ; member ; member = TREE_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllimport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = TREE_CHAIN ( member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) maybe_add_dllimport ( member ) ; for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = TREE_CHAIN ( member ) ) if ( TREE_CODE ( member ) ==


<s> bool is16BitMode ( ) const { return STI -> getFeatureBits (


<s> if ( GET_CODE ( clobber ) != CLOBBER ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; rtx scratch = SET_DEST ( clobber ) ; if ( GET_CODE ( src ) != UNSPEC ) return false ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SI_FROM_SF && GET_CODE ( dest ) == MEM && GET_MODE ( dest ) == SImode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == V4SFmode ) return true ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SF_FROM_SI && GET_CODE ( dest ) == REG && GET_MODE ( dest ) == SFmode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == DImode ) return true ; return


<s> switch ( getIntrinsicID ( S . getNode ( ) ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getLoadStoreVecRegBitWidth ( unsigned AddrSpace


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode )


<s> break ; case THREEBYTE_A6 : dec = & THREEBYTEA6_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_A7 : dec = & THREEBYTEA7_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : debug ( <STR_LIT> ) ; return <NUM_LIT> ; case MODRM_ONEENTRY : return dec -> instructionIDs [ <NUM_LIT> ] ; case MODRM_SPLITRM : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return dec -> instructionIDs [ <NUM_LIT> ] ; else return dec -> instructionIDs [ <NUM_LIT> ] ; case MODRM_FULL : return dec -> instructionIDs [


<s> bool is64Bit = is<ISA_LIT>64 && VT == LLT :: scalar ( <NUM_LIT> ) ; if ( ! is64Bit && VT != LLT :: scalar ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , is64Bit ? <STR_LIT> : <STR_LIT> ) . Case ( <STR_LIT> , ( IsDarwinABI || is<ISA_LIT>64 ) ? Register ( ) : <STR_LIT> ) . Case ( <STR_LIT> , ( ! is<ISA_LIT>64 && IsDarwinABI ) ? Register ( ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> return mode == DFmode ? loongarch_cost -> fp_mult_df


<s> RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; RHSSwap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHSSwap ) ; SDValue LoProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; SDValue HiProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHSSwap , Zero , DAG , dl , <STR_LIT> ) ; HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; return BuildIntrinsicOp ( <STR_LIT> , LHS , RHS ,


<s> return __builtin_neon_vrndav4hf ( __a )


<s> } const NEONLdStTableEntry * I = std :: lower_bound ( NEONLdStTable , NEONLdStTable + NumEntries , Opcode ) ; if ( I != NEONLdStTable + NumEntries && I -> PseudoOpc == Opcode ) return


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker


<s> return getSubExpr ( ) -> EvaluateAsRelocatable ( Res


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned getArgumentStackToRestore ( )


<s> rtx op0 = operands [ <NUM_LIT> ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( final_sequence -> insn ( <NUM_LIT> ) ) && get_attr_length ( final_sequence -> insn ( <NUM_LIT> ) ) ) { asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , ASSEMBLER_DIALECT ? <STR_LIT> : <STR_LIT> , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , label ) ; output_asm_insn ( <STR_LIT> , & op0 ) ; fprintf ( asm_out_file , <STR_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , label ) ; return <STR_LIT> ; } case <NUM_LIT> : return logic ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> )


<s> auto * COffs = dyn_cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; if ( ! COffs || COffs -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , getAL ( CurDAG , SDLoc ( N ) ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; SDNode * New = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> ,


<s> if ( Reg != - <NUM_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> PMapper ; bool IsValidSpecialReg ; Reg = PMapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) { assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; uint64_t Immed = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned State ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } else { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } return CurDAG -> getMachineNode ( State , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( Immed , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } <STR_LIT> Mapper


<s> } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( FRegIdx . count ( i ) ) Op . setReg ( getSTReg ( FPReg ) ) ; else Op . setReg ( <STR_LIT> + FPReg ) ; } StackTop -= NumSTPopped ; for ( unsigned i = <NUM_LIT> ; i < NumSTDefs ; ++ i ) pushReg ( NumSTDefs - i - <NUM_LIT> ) ; while ( FPKills ) { unsigned FPReg = countTrailingZeros ( FPKills ) ; if ( isLive ( FPReg ) ) freeStackSlotAfter ( Inst , FPReg ) ; FPKills &= ~ ( <NUM_LIT> << FPReg ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && ( Op . isKill ( ) || getFPReg ( Op ) == FirstFPRegOp || MI -> killsRegister ( Op . getReg ( ) ) ) && <STR_LIT> ) ; if ( FirstFPRegOp == ~ <NUM_LIT> ) FirstFPRegOp = getFPReg ( Op ) ; else { assert ( SecondFPRegOp == ~ <NUM_LIT> && <STR_LIT> ) ; SecondFPRegOp = getFPReg ( Op ) ; } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI -> RemoveOperand ( i ) ; -- i , -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask )


<s> bool <ISA_LIT>BaseRegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI ->


<s> MachO :: CPUSubType<ISA_LIT> CS = getMachOSubTypeFromArch ( TheTriple . getArchName ( ) ) ; return new <ISA_LIT>AsmBackendDarwin ( T , STI , MRI , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>AsmBackendWinCOFF (


<s> void DecodeZeroMoveLowMask ( unsigned NumElts , SmallVectorImpl < int > & ShuffleMask ) { ShuffleMask . push_back ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) ShuffleMask . push_back


<s> Value * <ISA_LIT>IREmitter :: visitFAND ( const SDNode *


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else assert ( false &&


<s> static unsigned char * unw_decode_b2 ( unsigned char * dp , unsigned char code , void * arg ) { unw_word t ; t = unw_decode_uleb128 (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT

|| type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) {


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT>


<s> return ( __m512i ) __builtin_ia32_cvttps2dq512_mask ( ( __v16sf ) __A , ( __v16si )


<s> return CreateReg ( Index , RegKind_ACC , RegInfo , S , E ,


<s> gcc_assert ( mem != NULL_RTX ) ; if ( ! eliminated ) { mem = eliminate_regs ( mem , VOIDmode , NULL_RTX ) ; cfun -> machine -> sdmode_stack_slot = mem ; eliminated = true ; } ret = mem ; } if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( mode ) ) ; if ( ! ret ) fprintf ( stderr , <STR_LIT> ) ; else debug_rtx ( ret


<s> static inline bool save_global_or_fp_reg_p ( unsigned int

regno , int leaf_function ATTRIBUTE_UNUSED ) {


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return <NUM_LIT> ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return <NUM_LIT> ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size ==


<s> static void expand_csky_stack_adjust ( int offset ) { rtx set ; rtx_insn * insn ; int size = ( offset > <NUM_LIT> ? offset : - offset ) ; if ( offset == <NUM_LIT> ) return ; if ( size > CSKY_MAX_SP_ADJUST * <NUM_LIT> ) { rtx tmp , dwarf ; gcc_assert ( cfun -> machine -> reg_size != <NUM_LIT> && ( cfun -> machine -> reg_mask & ( <NUM_LIT> << CSKY_STACKADJUST_REGNUM ) ) ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; tmp = gen_rtx_REG ( SImode , CSKY_STACKADJUST_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( size ) ) ; if ( offset > <NUM_LIT> ) set = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; else set = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; } else while ( size


<s> static bool hasYmmReg ( MachineInstr * MI ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg


<s> unsigned <ISA_LIT>ABIInfo :: GetNullPtr ( ) const { return


<s> int stackGrowth = ( MF . getTarget ( ) . getFrameInfo ( ) -> getStackGrowthDirection ( ) == TargetFrameInfo :: StackGrowsUp ? TD -> getPointerSize ( ) : - TD -> getPointerSize ( ) ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; Offset = MaxOffset - Offset + saveAreaOffset ; if ( HasFP && FramePtr == Reg ) continue ; MachineLocation CSDst ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation CSSrc (


<s> static bool aarch64_evpc_dup ( struct expand_vec_perm_d * d ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; rtx out = d -> target ; rtx in0 ; machine_mode vmode = d -> vmode ; unsigned int i , elt , nelt = d -> nelt ; rtx lane ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { if ( elt != d -> perm [ i


<s> switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> :


<s> if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) { Imm = Val


<s> assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( Update -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) )


<s> unsigned Offset = FirstArgOffset + VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( ) ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , DAG .

getConstant ( <NUM_LIT> , getPointerTy ( ) , true ) , InFlag ) ;


<s> if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ; return CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC ==


<s> unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || CurSlots == <NUM_LIT> ) { CurGroup . clear


<s> unsigned int nelems1 , nelems2 ; if ( prev . orig_mode == p . orig_mode && known_eq ( prev . offset + GET_MODE_SIZE ( prev . mode ) , p . offset ) && constant_multiple_p ( GET_MODE_NUNITS ( prev . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems1 ) && constant_multiple_p ( GET_MODE_NUNITS ( p . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems2 ) && targetm . array_mode ( p . orig_mode , nelems1 + nelems2 ) . exists ( & prev . mode ) ) { prev . num_zr += p . num_zr ; prev . num_pr += p . num_pr ; return ; } } pieces . quick_push


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI ->


<s> if ( num_regs == <NUM_LIT> && ! arm_arch6 ) { if ( first_reg == <NUM_LIT> ) first_reg -- ; num_regs ++ ; } if ( num_regs > <NUM_LIT> ) { arm_emit_vfp_multi_reg_pop ( first_reg , <NUM_LIT> , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + <NUM_LIT> , num_regs - <NUM_LIT> , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp )


<s> void printMRSOperand ( const MCInst * MI , unsigned OpNum


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( )


<s> static SDValue LowerBITCAST ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Op0 , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts =


<s> if ( TARGET_64BIT ) { fprintf ( file , <STR_LIT> , LPREFIX , labelno ) ; if ( ! TARGET_PECOFF && flag_pic ) fprintf ( file , <STR_LIT> , mcount_name ) ; else x86_print_call_or_nop ( file , mcount_name ) ; } else if ( flag_pic ) { fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , mcount_name ) ; } else { fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; x86_print_call_or_nop ( file , mcount_name ) ; } if ( flag_record_mcount ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file , <STR_LIT>


<s> MCInst TmpInst0 ; if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { TmpInst0 . setOpcode ( <STR_LIT> ) ; HasLinkReg = true ; } else { TmpInst0 . setOpcode ( <STR_LIT> ) ; } MCOperand MCOp ; if ( HasLinkReg ) { unsigned ZeroReg = <STR_LIT> ; TmpInst0 . addOperand ( MCOperand :: CreateReg ( ZeroReg ) ) ; } lowerOperand ( MI -> getOperand (


<s> if ( TARGET_FLOATXX && FP_REG_P ( regno )


<s> void addComplexRotationEvenOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE


<s> if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Amt ) ) { BaseShAmt = BV -> getSplatValue ( ) ; if ( BaseShAmt && BaseShAmt . isUndef ( ) ) BaseShAmt = SDValue ( ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = dyn_cast < ShuffleVectorSDNode > ( Amt ) ; if ( SVN && SVN -> isSplat ( ) ) { unsigned SplatIdx = ( unsigned ) SVN -> getSplatIndex ( ) ; SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { assert ( ( SplatIdx < InVec . getSimpleValueType ( ) . getVectorNumElements ( ) ) && <STR_LIT> ) ; BaseShAmt = InVec . getOperand ( SplatIdx ) ; } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( ! BaseShAmt ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , InVec , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; } } if ( BaseShAmt . getNode ( ) ) { assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , DAG ) ; } } if ( ! Subtarget . is64Bit ( ) && VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals (


<s> } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag , GV ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , DL , false , GA ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rdf ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregoidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t )


<s> unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( MRI && FrameReg != <STR_LIT> ) { SpillReg ( Out , <STR_LIT> ) ; if ( FrameReg == <STR_LIT> ) { Out . EmitCFIAdjustCfaOffset ( <NUM_LIT> ) ; Out . EmitCFIRelOffset ( MRI -> getDwarfRegNum ( LocalFrameReg , true ) , <NUM_LIT> ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( LocalFrameReg ) . addReg ( FrameReg ) ) ; Out . EmitCFIRememberState ( ) ; Out . EmitCFIDefCfaRegister ( MRI -> getDwarfRegNum ( LocalFrameReg , true )


<s> case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_ExternalSymbol : { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; return ; } MCSymbol * NLPSym = OutContext . GetOrCreateSymbol ( StringRef ( MAI -> getGlobalPrefix ( ) ) + MO . getSymbolName ( ) + <STR_LIT> ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( NLPSym ) ; if ( StubSym == <NUM_LIT> ) StubSym = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; O << * NLPSym ; return ; } case MachineOperand :: MO_GlobalAddress : { GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym == <NUM_LIT> ) StubSym = GetGlobalValueSymbol ( GV ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( StubSym == <NUM_LIT> ) StubSym = GetGlobalValueSymbol ( GV ) ; } else { SymToPrint = GetGlobalValueSymbol ( GV ) ; } } else { SymToPrint = GetGlobalValueSymbol ( GV


<s> static EVT getExtensionTo64Bits ( const EVT & OrigVT ) { if ( OrigVT . getSizeInBits ( ) >= <NUM_LIT> ) return OrigVT ; assert ( OrigVT . isSimple ( ) && <STR_LIT> ) ; <STR_LIT> OrigSimpleTy = OrigVT . getSimpleVT ( ) . SimpleTy ; switch ( OrigSimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> ML -> getExitBlocks ( Frontier ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited { MI -> getParent ( ) } ; unsigned Idx = <NUM_LIT> ; while ( Idx < Frontier . size ( ) ) { MachineBasicBlock * BB = Frontier [ Idx ] ; bool LookAtSuccessors = true ; for ( auto & I : * BB ) { if ( ! IsStackOp ( & I ) || I . memoperands ( ) . size ( ) == <NUM_LIT> ) continue ; if ( GetFrameIndex ( I . memoperands ( ) . front ( ) ) != FI ) continue ; if ( I . getOpcode ( ) == <STR_LIT> ) { LookAtSuccessors = false ; break ; } if ( I . getOpcode ( ) == <STR_LIT> ) return false ; } if ( LookAtSuccessors ) { for ( auto Succ : BB -> successors ( ) ) { if ( ! Visited . contains ( Succ ) && ! is_contained (

Frontier , Succ ) ) Frontier . push_back ( Succ ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < ArgLocs . size ( ) ; ++ i ) { const CCValAssign & VA = ArgLocs [ i ] ; CCValAssign :: LocInfo LocInfo = determineLocInfo ( Arguments [ i ] . VT , Arguments [ i ] . ArgVT , Arguments [ i ] . Flags ) ; if ( VA . isMemLoc ( ) ) ArgLocs [ i ] = CCValAssign :: getMem ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocMemOffset ( ) , VA . getLocVT ( ) , LocInfo ) ; else ArgLocs [ i ] = CCValAssign :: getReg ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocReg


<s> SmallVector < StringRef , <NUM_LIT> > AsmPieces ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) ) { return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && ( matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) ) { AsmPieces . clear ( ) ; const std :: string & ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) { AsmPieces . clear


<s> switch ( Opc ) { default : break ; } return SDValue


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF


<s> pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_arg_processed = false ; pcum -> aapcs_stack_words = <NUM_LIT> ; pcum -> aapcs_stack_size = <NUM_LIT> ; pcum -> silent_p = silent_p ; if ( ! silent_p && ! TARGET_FLOAT && fntype && fntype != error_mark_node ) { const_tree type = TREE_TYPE ( fntype ) ; machine_mode mode ATTRIBUTE_UNUSED ; int nregs ATTRIBUTE_UNUSED ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & mode , & nregs , NULL , false ) ) aarch64_err_no_fpadvsimd ( TYPE_MODE ( type ) ) ; } if ( ! silent_p && ! TARGET_SVE && pcum -> pcs_variant == ARM_PCS_SVE ) { if ( fndecl ) fatal_error ( input_location , <STR_LIT>


<s> return ( uint64x1_t ) __builtin_neon_vqrshludi ( ( int64x1_t ) __a ,


<s> Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewToVT = EVT :: getVectorVT ( C , ToVT . getVectorElementType ( ) , FromVT . getVectorNumElements ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < Trunc . getNumOperands ( ) ; i ++ ) { unsigned NewOffset = i * FromVT . getVectorNumElements ( ) * ToVT . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue Extract = Trunc . getOperand ( i ) ; SDValue Store = DAG . getTruncStore ( Ch , DL , Extract , NewPtr , St -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewToVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Stores . push_back ( Store )


<s> unsigned LongFormMaxOff = branchMaxOffsets ( LongFormOpcode ) ; if ( isBBInRange ( MI , DestBB , LongFormMaxOff ) ) { Br . MaxDisp = LongFormMaxOff ; MI -> setDesc ( TII -> get ( LongFormOpcode ) ) ; return true ; } MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; unsigned OppositeBranchOpcode = TII -> getOppositeBranchOpc ( Opcode ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> isUnconditionalBranch ( ) ) { unsigned BMITargetOperand = branchTargetOperand ( BMI ) ; MachineBasicBlock * NewDest = BMI -> getOperand ( BMITargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MI -> setDesc ( TII -> get ( OppositeBranchOpcode ) ) ; BMI -> getOperand ( BMITargetOperand ) . setMBB ( DestBB ) ; MI -> getOperand ( TargetOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit


<s> void emitMask ( unsigned AddrReg , unsigned MaskReg , const MCSubtargetInfo & STI ) { MCInst MaskInst ; MaskInst . setOpcode ( <STR_LIT> ) ; MaskInst . addOperand ( MCOperand :: createReg


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemArgument ( SDValue Chain , CallingConv :: ID CallConv , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , const CCValAssign & VA , MachineFrameInfo * MFI , unsigned i ) const { <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = shouldGuaranteeTCO ( CallConv , DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI -> setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy


<s> rtx select0 = XEXP ( concat , <NUM_LIT> ) ; rtx select1 = XEXP ( concat , <NUM_LIT> ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ; rtx reg0 = XEXP ( select0 , <NUM_LIT> ) ; rtx reg1 = XEXP ( select1 , <NUM_LIT> ) ; if ( ! rtx_equal_p ( reg0 , reg1 ) || ! REG_P ( reg0 ) ) return false ; rtx parallel0 = XEXP ( select0


<s> case 'R' : return C_Memory ; } } if ( Constraint == <STR_LIT> ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint


<s> void <ISA_LIT>ELFStreamer :: emitIntValue ( uint64_t Value


<s> SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumByteElts ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , LUTVec ) ; SmallVector < SDValue , <NUM_LIT> > Mask0F ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue M0F = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Mask0F ) ; SmallVector < SDValue , <NUM_LIT> > Four ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FourV = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Four ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ; SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL ,


<s> StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > I = df_ext_begin ( Entry , Processed ) , E = df_ext_end ( Entry , Processed ) ; I != E ; ++ I ) Changed |= processBasicBlock ( MF ,


<s> if ( Imm == <NUM_LIT> ) return false ; for ( RepeatWidth = RegWidth ; RepeatWidth > <NUM_LIT> ; RepeatWidth /= <NUM_LIT> ) { uint64_t RepeatMask = RepeatWidth == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << RepeatWidth ) - <NUM_LIT> ; uint64_t ReplicatedMask = Imm & RepeatMask ; if ( ReplicatedMask == <NUM_LIT> ) continue ; bool IsReplicatedMask = true ; for ( unsigned i = RepeatWidth ; i < RegWidth ; i += RepeatWidth ) { if ( ( ( Imm >> i ) & RepeatMask ) != ReplicatedMask ) { IsReplicatedMask = false ; break ; } } if ( ! IsReplicatedMask ) continue ; Rotation = countTrailingZeros ( Imm ) ; if ( Rotation == <NUM_LIT> ) { Rotation = RegWidth == <NUM_LIT> ? CountLeadingOnes_64 ( Imm ) : CountLeadingOnes_32 ( Imm ) ; Rotation = RepeatWidth - Rotation ; } uint64_t ReplicatedOnes = ReplicatedMask ; if ( Rotation != <NUM_LIT> && Rotation != <NUM_LIT> ) ReplicatedOnes = ( ReplicatedMask >> Rotation ) | ( ( ReplicatedMask << ( RepeatWidth - Rotation ) ) & RepeatMask ) ; if ( ! isMask_64 ( ReplicatedOnes ) ) continue ; Num1s = CountTrailingOnes_64 ( ReplicatedOnes ) ; break ; } if ( RepeatWidth == <NUM_LIT> || Num1s == RepeatWidth ) return false ; uint32_t N = RepeatWidth == <NUM_LIT> ; uint32_t ImmR = RepeatWidth - Rotation ; uint32_t ImmS = Num1s - <NUM_LIT> ; switch ( RepeatWidth


<s> while ( CurrentReg != OrderEnd && ! EnabledRegs . count ( * CurrentReg ) ) ++ CurrentReg ; return


<s> static void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1


<s> unsigned BBNum = BB -> getNumber ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << <STR_LIT> << BB -> getNumber ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << <STR_LIT> << <STR_LIT> << MF . getNumBlockIDs ( ) << <STR_LIT> ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF . getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF . getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset (


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: x86 , true > X ( The<ISA_LIT>_32Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: x86_64 , true > Y ( The<ISA_LIT>_64Target , <STR_LIT> ,


<s> MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext ( ) ; TargetSupported = ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && ( ( Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget -> has<ISA_LIT>32 ( ) ) && ( Subtarget -> isABI_O32 ( ) ) ) ) ; UnsupportedFPMode = Subtarget ->


<s> NewMI2 . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; NewMI2 . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; NewMI2 . clearFlag ( MachineInstr :: MIFlag :: IsExact ) ; MachineOperand * OldFlagDef1 = OldMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * OldFlagDef2 = OldMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( ! OldFlagDef1 == ! OldFlagDef2 && <STR_LIT> ) ; if ( ! OldFlagDef1 || ! OldFlagDef2 ) return ; assert ( OldFlagDef1 -> isDead ( ) && OldFlagDef2 -> isDead ( ) && <STR_LIT> ) ; MachineOperand * NewFlagDef1 = NewMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * NewFlagDef2 = NewMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( NewFlagDef1 && NewFlagDef2 && <STR_LIT> ) ; NewFlagDef1 -> setIsDead (


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return true


<s> return __builtin_mve_vshlq_r_sv4si ( __a ,


<s> if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : BytesInStackArgArea ( <NUM_LIT> ) , ArgumentStackToRestore ( <NUM_LIT> ) , HasStackFrame ( false ) , NumLocalDynamicTLSAccesses ( <NUM_LIT> ) , VarArgsStackIndex ( <NUM_LIT> ) , VarArgsGPRIndex ( <NUM_LIT> ) , VarArgsGPRSize ( <NUM_LIT> ) , VarArgsFPRIndex ( <NUM_LIT> ) , VarArgsFPRSize ( <NUM_LIT> ) { ( void


<s> vmull_u16 ( uint16x4_t a , uint16x4_t b ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> cvtT2LdrdPre ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addMemImm8s4OffsetOperands ( Inst , <NUM_LIT> ) ;


<s> MachineBasicBlock :: const_instr_iterator II = MachineBasicBlock :: const_instr_iterator ( & MI ) ; if ( II != MBB -> instr_begin ( ) && ( -- II ) -> getOpcode ( ) == <STR_LIT> ) { const MachineInstr & CallMI = * ( -- II ) ; if ( CallMI . isCall ( ) && CallMI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) { const Function * CalleeFn = dyn_cast < Function > ( CallMI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; const IntegerType * IntTy = dyn_cast < IntegerType > ( CalleeFn -> getReturnType ( ) ) ; const AttributeSet & Attrs = CalleeFn -> getAttributes ( ) . getRetAttributes ( ) ; if ( IntTy && IntTy -> getBitWidth ( ) <= <NUM_LIT> ) return Attrs . hasAttribute ( SignExt ? Attribute :: SExt : Attribute :: ZExt ) ; } } } } if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { unsigned SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && ! is<ISA_LIT>LowRegister ( SrcReg ) ) break ; NewMI = AddDefaultPred ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { unsigned DstReg = MI -> getOperand (


<s> SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src . getNode ( ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT> ) ; if ( TLI . isOperationLegalOrPromote ( Opcode , VT ) && IsRepeatedOpOrFreeTruncation ( Op0 , Op1 ) ) return TruncateArithmetic ( Op0 , Op1 ) ; break ; } case <STR_LIT> : if ( SrcVT . getScalarType ( ) == <STR_LIT> && TLI . isOperationLegal ( Opcode , VT ) && ! TLI . isOperationLegal ( Opcode , SrcVT ) ) return TruncateArithmetic ( Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue Op0 = Src . getOperand (


<s> static const uint16_t ReservedCPURegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; } const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo


<s> if ( MEM_P ( dest ) && rx_small_data_operand ( XEXP ( dest , <NUM_LIT> ) ) ) { gcc_assert ( GET_MODE ( dest ) != DImode ) ; gcc_assert ( GET_MODE ( dest ) != DFmode ) ; dst_template = <STR_LIT> ; } else dst_template = <STR_LIT> ; if ( GET_MODE ( dest ) == DImode || GET_MODE ( dest ) == DFmode ) { gcc_assert ( ! is_movu ) ; if ( REG_P ( src ) && REG_P ( dest ) && ( REGNO ( dest ) == REGNO ( src ) + <NUM_LIT> ) ) sprintf ( out_template , <STR_LIT> ) ; else sprintf ( out_template , <STR_LIT> ) ; } else sprintf ( out_template , <STR_LIT> , is_movu ? <STR_LIT> : <STR_LIT> , extension ,


<s> static const char * getName ( ) { return DEBUG_TYPE


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return


<s> if ( ! RM . hasValue ( ) ) return TT . isOSBinFormatMachO ( ) ? Reloc :: PIC_ : Reloc :: Static ; if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( )


<s> tree field , member = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE ; member = field


<s> rtx addr_reg = SET_DEST ( addr_set ) ; gcc_assert ( base_reg_operand ( addr_reg , Pmode ) ) ; rtx addr_symbol = SET_SRC ( addr_set ) ; gcc_assert ( pcrel_external_address ( addr_symbol , Pmode ) ) ; rtx load_set = PATTERN ( load_insn ) ; gcc_assert ( GET_CODE ( load_set ) == SET ) ; rtx reg = SET_DEST ( load_set ) ; if ( reg_used_between_p ( reg , addr_insn , load_insn ) || reg_set_between_p ( reg , addr_insn , load_insn ) ) return ; rtx mem = SET_SRC ( load_set ) ; machine_mode reg_mode = GET_MODE ( reg ) ; machine_mode mem_mode = GET_MODE ( mem ) ; rtx mem_inner = mem ; unsigned int reg_regno = reg_or_subregno ( reg ) ; if ( GET_CODE ( mem ) == SIGN_EXTEND && GET_MODE ( XEXP ( mem , <NUM_LIT> ) ) == SImode ) { if ( ! INT_REGNO_P ( reg_regno ) ) return ; mem_inner = XEXP ( mem , <NUM_LIT> ) ; mem_mode = DImode ; } else if ( GET_CODE ( mem ) == SIGN_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND || GET_CODE ( mem ) == FLOAT_EXTEND ) { mem_inner = XEXP ( mem , <NUM_LIT> ) ; mem_mode = GET_MODE ( mem_inner ) ; } if ( ! MEM_P ( mem_inner ) ) return ; if ( ! pcrel_opt_valid_mem_p ( reg , mem_mode , mem_inner ) ) return ; unsigned int addr_regno = reg_or_subregno ( addr_reg ) ; rtx label_num = GEN_INT ( ++ pcrel_opt_next_num ) ; rtx reg_di = gen_rtx_REG ( DImode , reg_regno ) ; rtx addr_pattern ; if ( addr_regno != reg_regno ) addr_pattern = gen_pcrel_opt_ld_addr ( addr_reg , addr_symbol , label_num , reg_di ) ; else addr_pattern = gen_pcrel_opt_ld_addr_same_reg ( addr_reg , addr_symbol , label_num ) ; validate_change ( addr_insn , & PATTERN ( addr_insn ) , addr_pattern , false ) ; rtvec v_load = gen_rtvec ( <NUM_LIT> , mem_inner , reg_di , label_num ) ; rtx new_load = gen_rtx_UNSPEC ( GET_MODE ( mem_inner

) , v_load , UNSPEC_PCREL_OPT_LD_RELOC ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) . getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups ) ; uint32_t Binary = ( Imm8 >> <NUM_LIT> ) &


<s> vld1q_lane_s16 ( const int16_t * __a , int16x8_t __b , const int __c ) { return ( int16x8_t ) __builtin_neon_vld1_lanev8hi ( ( const __builtin_neon_hi * )


<s> Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex


<s> TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified


<s> case AddrModeNone : return <STR_LIT> ; case AddrMode1 : return <STR_LIT> ; case AddrMode2 : return <STR_LIT> ; case AddrMode3 : return <STR_LIT> ; case AddrMode4 : return <STR_LIT> ; case AddrMode5 : return <STR_LIT> ; case AddrMode5FP16 : return <STR_LIT> ; case AddrMode6 : return <STR_LIT> ; case AddrModeT1_1 :


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Memory , Ctx ) ; Op -> Mem . BaseRegNum = BaseReg ; Op -> Mem . OffsetRegNum = OffsetReg ; Op -> Mem . OffsetImm = nullptr ; Op -> Mem . ExtType = ExtType ; Op -> Mem . ShiftVal = ShiftVal ; Op -> Mem . ExplicitShift = ExplicitShift ; Op -> Mem . Mode = RegisterOffset ; Op -> StartLoc = S ; Op -> EndLoc


<s> SDValue <ISA_LIT>TargetLowering :: LowerDarwinGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( ) , false , true , true , <NUM_LIT> ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) .


<s> } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; return DAG . getZExtOrTrunc ( V , DL , VT ) ; } if ( SExtVT ==