<s> CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { const fltSemantics & Sem = APFloat :: IEEEdouble ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { const fltSemantics & Sem = APFloat ::


<s> bool <ISA_LIT>FastISel :: SelectLoad ( const Instruction * I ) { if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : <NUM_LIT> ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> Sign *= - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; int Shift = MI . getOperand ( <NUM_LIT> ) . getImm


<s> const MCDwarfFrameInfo & Frame = Out . getDwarfFrameInfos ( ) . back ( ) ; if ( Frame . End ) return <STR_LIT> ; const MCRegisterInfo * MRI = Ctx . getRegisterInfo ( ) ; if ( ! MRI ) return <STR_LIT> ; if ( InitialFrameReg ) { return InitialFrameReg ; } return MRI -> getLLVMRegNum ( Frame


<s> static StackOffset getStackOffset ( const MachineFunction & MF , int64_t ObjectOffset ) { const auto & MFI = MF . getFrameInfo ( ) ; return { ObjectOffset + ( int64_t ) MFI . getStackSize ( ) ,


<s> if ( ( unsigned ) M [ i ] != <NUM_LIT> * i + WhichResult ) return false ; } if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ; return true


<s> int64_t StDisp1 = StDispImm ; int64_t StDisp2 = <NUM_LIT> ; unsigned Size1 = <NUM_LIT> ; unsigned Size2 = <NUM_LIT> ; int64_t LdStDelta = StDispImm - LdDispImm ; for ( auto DispSizePair : BlockingStoresDispSizeMap ) { LdDisp2 = DispSizePair . first ; StDisp2 = DispSizePair . first + LdStDelta ; Size2 = DispSizePair . second ; if ( LdDisp2 < LdDisp1 ) { int OverlapDelta = LdDisp1 - LdDisp2 ; LdDisp2 += OverlapDelta ; StDisp2 += OverlapDelta ; Size2 -= OverlapDelta ; } Size1 = std :: abs ( std :: abs ( LdDisp2 ) - std :: abs ( LdDisp1 ) ) ; buildCopies ( Size1 , LoadInst , LdDisp1 , StoreInst , StDisp1 , LMMOffset , SMMOffset ) ; buildCopies ( Size2 , LoadInst , LdDisp2 , StoreInst , StDisp2 , LMMOffset + Size1 , SMMOffset + Size1 ) ; LdDisp1 = LdDisp2 + Size2 ; StDisp1 = StDisp2 + Size2 ; LMMOffset += Size1 + Size2 ; SMMOffset += Size1 + Size2 ; } unsigned Size3 = ( LdDispImm + getRegSizeInBytes ( LoadInst ) ) - LdDisp1 ; buildCopies ( Size3 , LoadInst , LdDisp1 , StoreInst , StDisp1 ,


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch (


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; BuildMI ( StoreBB , DL , TII -> get ( StlrOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * DoneBB ) ; computeAndAddLiveIns ( LiveRegs , * StoreBB ) ; computeAndAddLiveIns ( LiveRegs , * LoadCmpBB ) ; StoreBB -> clearLiveIns ( ) ; computeAndAddLiveIns ( LiveRegs , * StoreBB ) ; LoadCmpBB -> clearLiveIns ( ) ; computeAndAddLiveIns ( LiveRegs , * LoadCmpBB ) ; return true


<s> Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , true , SuffixLoc , getContext ( ) ) ) ; } bool condCodeFourthOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeSecondOperand = ( Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeThirdOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { unsigned N = <NUM_LIT> ; do { if ( parseOperand ( Operands , ( N == <NUM_LIT> && condCodeFourthOperand ) || ( N == <NUM_LIT> && condCodeThirdOperand ) || ( N == <NUM_LIT> && condCodeSecondOperand ) , condCodeSecondOperand || condCodeThirdOperand ) ) { return true ; } SMLoc RLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseOptionalToken ( AsmToken :: RBrac ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , RLoc , getContext ( ) ) ) ; SMLoc ELoc = Parser . getTok


<s> const uint32_t * Mask ; if ( ! OutArgs . empty ( ) && OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . isReturned ( ) ) { Mask = TRI . getThisReturnPreservedMask ( MF , Info . CallConv ) ; if ( ! Mask ) { OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . setReturned ( false ) ; Mask = TRI . getCallPreservedMask ( MF , Info .


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; SetVector < const MCSection * , SmallVector < const MCSection * , <NUM_LIT> > , SmallPtrSet < const MCSection * , <NUM_LIT> > > TextSections ; TextSections . insert ( TLOFMacho . getTextSection ( ) ) ; for ( Module :: iterator F = M . begin ( ) , e = M . end ( ) ; F != e ; ++ F ) if ( ! F -> isDeclaration ( ) && ! F -> hasAvailableExternallyLinkage ( ) ) TextSections . insert ( TLOFMacho . SectionForGlobal ( F , * Mang , TM ) ) ; TextSections . insert ( TLOFMacho . getTextCoalSection ( ) ) ; TextSections . insert ( TLOFMacho . getConstTextCoalSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = TextSections . size ( ) ; i != e ; ++ i ) OutStreamer . SwitchSection ( TextSections [ i ] ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } const MCSection * StaticInitSect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR | MachO

:: S_ATTR_PURE_INSTRUCTIONS , SectionKind :: getText ( ) ) ;


<s> __builtin_ia32_storehps ( ( __v2sf * ) __P , ( __v4sf )


<s> std :: string lsl_str = <STR_LIT> ; if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && OpNo == <NUM_LIT> ) lsl_str = <STR_LIT> ; O << lsl_str << <STR_LIT> << <ISA_LIT>_ez_int2hex ( Op . getImm ( )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool little ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPUName =


<s> Result |= UImm16MO . getImm ( ) ; return Result ; } const <ISA_LIT>MCExpr * A64E = cast < <ISA_LIT>MCExpr > ( UImm16MO . getExpr ( ) ) ; <STR_LIT> requestedFixup ; switch ( A64E -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G3 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 : requestedFixup = <STR_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable (


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < <STR_LIT> > & Ins , CCAssignFn Fn ) { PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear


<s> return ( __m256d ) __builtin_ia32_movapd256_mask ( ( __v4df ) __A , ( __v4df ) _mm256_setzero_pd ( )


<s> bool isPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; if ( isPIC ) { HiOpFlags |= <STR_LIT> ; LoOpFlags |= <STR_LIT> ; } if ( GV && Subtarget . hasLazyResolverStub ( GV ) ) { HiOpFlags |= <STR_LIT> ; LoOpFlags |= <STR_LIT> ; if ( GV -> hasHiddenVisibility


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> static void transferMIFlag ( MachineInstr * OldMI , MachineInstr * NewMI , MachineInstr :: MIFlag Flag ) { if ( OldMI -> getFlag ( Flag ) )


<s> bool Revert = false ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) Start = SearchForStart ( Preheader ) ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } if ( Start || Dec || End ) { if ( ! Start || ! Dec || ! End ) report_fatal_error ( <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Start << <STR_LIT>


<s> if ( ! <ISA_LIT>AbiFlags :: fillByElfFlags ( pInput , elfFlags , pElfFlags ) ) return false ; const LDContext * ctx = pInput . context ( ) ; for ( auto it = ctx -> sectBegin ( ) , ie = ctx -> sectEnd ( ) ; it != ie ; ++ it ) if ( ( * it ) -> type ( ) == llvm :: ELF :: SHT_MIPS_ABIFLAGS ) { if ( ! <ISA_LIT>AbiFlags :: fillBySection ( pInput , * * it , pFlags ) ) return false ; if ( ! <ISA_LIT>AbiFlags :: isCompatible ( pInput , pElfFlags


<s> for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . UnrollAndJam =


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res


<s> static bool usesGivenOffset ( const MCInst * MI , int AddOffset ) { unsigned AluCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return LPAC :: encode<ISA_LIT>AluCode ( AluCode ) == LPAC :: ADD && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == AddOffset || MI -> getOperand ( <NUM_LIT> )


<s> else return ( ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) >


<s> static bool isIntraBin ( const MachineInstr & MI , StringRef BinPrefix ) { return MI . getOpcode ( ) == <STR_LIT> && getCallee ( MI )


<s> MCFragment * findAssociatedFragment (


<s> MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg (


<s> const <ISA_LIT>ELFDynamic & <ISA_LIT>GNULDBackend :: dynamic ( ) const { assert ( m_pDynamic != NULL


<s> bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasF128 . clear (


<s> forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2


<s> MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) { if ( ! BB -> empty ( ) && BB -> back ( ) . isReturn ( ) ) { IP = BB -> end ( ) ; -- IP ; MachineBasicBlock :: iterator


<s> debug ( <STR_LIT> ) ; return true ; case TYPE_R8 : case TYPE_R16 : case TYPE_R32 : case TYPE_R64 : case TYPE_Rv : case TYPE_MM64 : case TYPE_XMM : case TYPE_YMM : case TYPE_ZMM : case TYPE_TMM : case TYPE_VK_PAIR : case TYPE_VK : case TYPE_DEBUGREG : case TYPE_CONTROLREG : case TYPE_BNDR : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_MVSIBX : case TYPE_MVSIBY : case TYPE_MVSIBZ : return translateRMMemory ( mcInst , insn


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; if ( ForceStackAlign ) return


<s> return ( __m256i ) __builtin_ia32_pblendw256 ( ( __v16hi ) __X , (


<s> Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) ) ; SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ; return DAG . getNode ( <STR_LIT> , dl , Tys , LoadSin .

getValue ( <NUM_LIT> ) , LoadCos . getValue ( <NUM_LIT> ) ) ;


<s> unsigned getCSRFirstUseCost ( ) const


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { case 'A' : default : return true ; case 'm' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; O << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ; return false ; } } const MachineOperand & MO = MI -> getOperand ( OpNum


<s> void addRegACCRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT>


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitConstant ( Binary , <NUM_LIT> , OS


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TrueBlock , MachineBasicBlock * FalseBlock , ArrayRef < MachineOperand > Condition , const DebugLoc & DL , int * BytesAdded ) const { return <NUM_LIT>


<s> void setMustSaveTOC ( bool U ) { MustSaveTOC =


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getTarget ( ) . getSubtarget < TargetSubtargetInfo > ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo (


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results


<s> unsigned const OP_ENCODING_MASK = <NUM_LIT> ; return AluOp


<s> uf = <NUM_LIT> << ceil_log2 ( uf ) ; if ( LOOP_VINFO_NITERS_KNOWN_P ( loop_vinfo ) ) return uf ; if ( reduc_factor > ( unsigned int ) rs6000_vect_unroll_reduc_threshold || m_gather_load ) return uf ; HOST_WIDE_INT est_niter = get_estimated_loop_iterations_int ( loop ) ; unsigned int vf = vect_vf_for_cost ( loop_vinfo ) ; unsigned int unrolled_vf = vf * uf ; if ( est_niter == - <NUM_LIT> || est_niter < unrolled_vf ) return <NUM_LIT> ; else { unsigned int epil_niter_unr = est_niter % unrolled_vf ; unsigned int epil_niter = est_niter % vf ; if ( LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) &&


<s> if ( max_skip ) { while ( nbytes + max_skip >= <NUM_LIT> ) { start = NEXT_INSN ( start ) ; if ( ( JUMP_P ( start ) && asm_noperands ( PATTERN ( start ) ) < <NUM_LIT> ) || CALL_P ( start ) ) njumps -- , isjump = true ; else isjump = false ; nbytes -= ix86_min_insn_size ( start ) ; } } continue ; } min_size = ix86_min_insn_size ( insn ) ; nbytes += min_size ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) , min_size ) ; if ( ( JUMP_P ( insn ) && asm_noperands ( PATTERN ( insn ) ) < <NUM_LIT> ) || CALL_P ( insn ) ) njumps ++ ; else continue ; while ( njumps > <NUM_LIT> ) { start = NEXT_INSN ( start ) ; if ( ( JUMP_P ( start ) && asm_noperands ( PATTERN ( start ) ) < <NUM_LIT> ) ||


<s> assert ( ! IsLP64 ) ; if ( MO . isImm ( ) && isInt < <NUM_LIT> > ( MO . getImm ( ) )


<s> unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != <NUM_LIT> ; ++ l ) { unsigned HalfBegin = ( ( Imm >> ( l * <NUM_LIT> ) ) & <NUM_LIT> ) * HalfSize ; for ( unsigned i = HalfBegin , e = HalfBegin + HalfSize ; i != e ; ++


<s> return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case TargetOpcode :: LOAD_STACK_GUARD : expandLoadStackGuard ( MIB , * this ) ; return


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( IsLoad && isAcquireOrStronger ( Ord ) ) return callIntrinsic ( Builder , <STR_LIT> ) ; return


<s> DFtype __floatdidf ( DItype u ) { DFtype d ; d = ( SItype ) ( u >> ( sizeof ( SItype ) * <NUM_LIT> ) ) ; d *= <NUM_LIT> * ( ( ( UDItype ) <NUM_LIT> ) << ( ( sizeof ( SItype ) * <NUM_LIT> ) - <NUM_LIT> ) ) ; d += ( USItype ) ( u & ( ( ( ( UDItype ) <NUM_LIT> ) <<

( sizeof ( SItype ) * <NUM_LIT> ) ) - <NUM_LIT> ) ) ;


<s> if ( GET_CODE ( body ) != PARALLEL ) return <NUM_LIT> ; rtx set = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_DEST ( set )


<s> CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( isGP64bit ( ) ? & <STR_LIT> : &


<s> inline vector signed int vec_rl ( vector signed int a1


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( ! shouldAssumeDSOLocal ( RM , TargetTriple , * GV -> getParent


<s> int arm_early_load_addr_dep_ptr ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( ! value || ! addr || ! MEM_P ( SET_SRC ( value ) )


<s> return static_cast < <ISA_LIT>TargetStreamer & > ( *

OutStreamer -> getTargetStreamer ( ) ) ;


<s> static DecodeStatus decodeBDAddr12Operand ( MCInst & Inst , uint64_t Field , const unsigned * Regs ) { uint64_t Base = Field >> <NUM_LIT> ; uint64_t Disp = Field &


<s> if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return <NUM_LIT> ; if ( regno == SPE_ACC_REGNO


<s> return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU


<s> else return false ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { OperandMatchResultTy ResTy = MatchAnyRegisterNameWithoutDollar ( Operands , DefSymbol . substr ( <NUM_LIT> ) , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( )


<s> static bool cmse_func_args_or_return_in_stack ( tree fndecl , tree name , tree fntype ) { function_args_iterator args_iter ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; bool first_param = true ; tree arg_type , prev_arg_type = NULL_TREE , ret_type ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , fndecl ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; prev_arg_type = arg_type ; if ( VOID_TYPE_P ( arg_type ) ) continue ; function_arg_info arg ( arg_type , true ) ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg ) ; arg_rtx = arm_function_arg ( args_so_far , arg ) ; if ( ! arg_rtx || arm_arg_partial_bytes ( args_so_far , arg ) ) { error ( <STR_LIT> <STR_LIT> , name ) ; return true


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op2 = expand_expr ( arg2 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx pat ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] .


<s> if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> ,


<s> MVT VT = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeft1Hi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeft1Hi , Not ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , VT ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Cond , IsSRA ?

Shift31 : DAG . getConstant ( <NUM_LIT> , VT ) , ShiftRightHi ) ;


<s> enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; if ( ! TARGET_ALTIVEC ) return <NUM_LIT> ; mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 ,


<s> infp -> reg_mask = get_csky_live_regs ( & reg_count ) ; infp -> reg_size = reg_count * UNITS_PER_WORD ; infp -> arg_offset = infp -> reg_offset + infp -> reg_size ; infp -> arg_size = crtl -> args . pretend_args_size ; infp -> frame_size = infp -> arg_offset


<s> bool hasFPAO ( ) const { return HasFPAO


<s> static DecodeStatus decodeS8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeSImmOperand < <NUM_LIT> > ( Inst


<s> return DAG . getLoad ( LD -> getMemoryVT ( ) , N -> getDebugLoc ( ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD

-> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , <NUM_LIT> ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Value * TDCFunc = <STR_LIT> ( & M , <STR_LIT> , V -> getType (


<s> static DecodeStatus DecodeFP32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; if ( imm != INT32_MIN ) imm *=


<s> static bool isPSHUFHWMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 ) { if ( VT != <STR_LIT> && ( ! HasInt256 || VT != <STR_LIT> ) ) return false ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [


<s> virtual const <ISA_LIT>FrameInfo * getFrameInfo (


<s> std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F )


<s> Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . ParseAbsoluteExpression ( Value ) ) return <NUM_LIT> ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } SMLoc MemEnd = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex (


<s> return __builtin_mve_vrmlaldavhxq_sv4si ( __a ,


<s> MachineBasicBlock :: iterator FirstEpilogSEH = std :: prev ( MBBI ) ; while ( FirstEpilogSEH -> getFlag ( MachineInstr :: FrameDestroy ) && FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: prev ( FirstEpilogSEH ) ; if ( FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: next ( FirstEpilogSEH ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addMBB ( TargetMBB ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addMBB ( TargetMBB ) . addImm ( <NUM_LIT> ) ; return true ; } Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill

) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> PMACPairList & getMulPairs ( ) { return MulPairs


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler (


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return

make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>RegNum ( const MCOperand &


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum (


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createIndirectBrExpandPass ( )


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> assert ( Kind == k_PSBHint && <STR_LIT> ) ; return PSBHint . Val


<s> bool SelectAddrImm ( SDValue N , SDValue & Disp , SDValue & Base ) { return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base ,


<s> static inline uint64_t encodeLogicalImmediate ( uint64_t imm , unsigned regSize ) { uint64_t encoding = <NUM_LIT> ; bool res = processLogicalImmediate ( imm ,


<s> <ISA_LIT>CollectLOH ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>CollectLOHPass ( * PassRegistry :: getPassRegistry


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParsePSBHint ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail


<s> static const int MaskToOptimizeEven [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static const int MaskToOptimizeOdd [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool MatchEvenMask = true ; bool MatchOddMask = true ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] ) )


<s> unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } if ( ! R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget -> isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_crc32_u64 ( unsigned long long __C , unsigned long long __V ) { return __builtin_ia32_crc32di ( __C , __V


<s> BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Op1 . getNode ( ) ) ; if ( ! BV ) return SDValue ( ) ; MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , dl


<s> if ( checkFnHasLiveInYmm ( MRI ) ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this


<s> CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , Align ( <NUM_LIT> ) ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( MF ) ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( MIB -> getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; MIB . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ; splitToValueTypes ( DL , Info . OrigRet , <NUM_LIT> , ArgInfos , OrigRetIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigRetIndices , Ins ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , TLI . CCAssignFnForReturn ( ) , Info . OrigRet .


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol =


<s> } SmallVector < unsigned , <NUM_LIT> > Match ; uint64_t ErrorInfoMissingFeature = <NUM_LIT> ; if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstructionImpl ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfo ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; SMRange OpRange = UnsizedMemOp -> getLocRange ( ) ; ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges


<s> machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! COMPLEX_MODE_P (

mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ;


<s> State = IES_GT ; IC . pushOperator ( IC_GT ) ; break ; } PrevState =


<s> if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ; if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } if ( ( TheTriple . getArch ( ) == Triple :: mipsel ) || ( TheTriple . getArch ( ) == Triple :: mips ) ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT>


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; buildLoad ( LoadVReg , Addr , Size , <NUM_LIT> , MPO ) ; MIRBuilder . buildTrunc (


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = <NUM_LIT> ; unsigned Inc = DblSpaced ? <NUM_LIT> : <NUM_LIT> ; unsigned Rn = decodeRn ( insn ) ; unsigned Rm = decodeRm ( insn ) ; unsigned Rd = decodeNEONRd ( insn ) ; bool WB = Rm != <NUM_LIT> ; unsigned RmEnum = <NUM_LIT> ; if ( WB && Rm != <NUM_LIT> ) RmEnum = getRegisterEnum ( B , <STR_LIT> , Rm ) ; if ( Store ) { assert ( OpIdx < NumOps && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; ++ OpIdx ; } assert ( ( OpIdx + <NUM_LIT> ) < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx += <NUM_LIT> ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( RmEnum ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> || OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; RegClass = OpInfo [ OpIdx ] . RegClass ; while ( OpIdx < NumOps && ( unsigned ) OpInfo [ OpIdx ] . RegClass == RegClass ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , Rd ) ) ) ; Rd +=


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI


<s> return ( vector signed char ) __builtin_altivec_vcmpequb ( ( vector signed char ) a1 , ( vector


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( ) , false , true , true , <NUM_LIT> ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * ARI = static_cast <

const <ISA_LIT>RegisterInfo * > ( TRI ) ;


<s> if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand ::


<s> CannotTailPredicate = ! ValidateMVEInst ( MI


<s> if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - <NUM_LIT> && val < <NUM_LIT> && ( val & <NUM_LIT> ) == <NUM_LIT> ; } else return <NUM_LIT> ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , <NUM_LIT> ) ; return ( arm_address_register_rtx_p ( XEXP ( index , <NUM_LIT> ) , strict_p ) && CONST_INT_P ( op ) && INTVAL

( op ) > <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ;


<s> unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Expression ) ; Op -> Expr . Val = Val ; Op -> Expr . CRVal = EvaluateCRExpr ( Val ) ; Op -> StartLoc = S ; Op -> EndLoc =


<s> inline SDValue getImm ( const SDNode * Node , unsigned


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= cmode << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( cmode == <NUM_LIT> && Inst . getOpcode ( ) == <STR_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) )


<s> if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc ,


<s> UseDataRegionDirectives = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> int Opc = Lookup ( OpcodeTable , Opcode ) ; assert ( Opc != - <NUM_LIT> && <STR_LIT> ) ; return Opc


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) ) return lowerFCOPYSIGN64 ( Op , DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ; return lowerFCOPYSIGN32 ( Op , DAG , Subtarget -> has<ISA_LIT>32r2


<s> const char * getPassName ( ) const { return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Src1 . isUndef ( ) || Src0 . getOperand ( <NUM_LIT> ) == Src1 . getOperand ( <NUM_LIT> ) ) { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) , Src0 .


<s> static int ia64_issue_rate ( ) { return <NUM_LIT>


<s> int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum ,


<s> auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > <NUM_LIT> ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++


<s> FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return StackOffset :: getFixed ( Offset + StackSize ) ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return StackOffset :: getFixed (


<s> void function_expander :: add_ptrue_hint ( unsigned int argno , machine_mode pred_mode ) { rtx pred = gen_lowpart ( pred_mode , args


<s> const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering


<s> __attribute__ ( ( __always_inline__ ) )


<s> return m16_check_op ( op , - <NUM_LIT> , <NUM_LIT>


<s> I . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Symbol , OutContext ) ) ) ; OutStreamer -> emitInstruction (


<s> } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = next ( MI ) ) { if ( CPUIndex < CPUsers . size ( ) && CPUsers [ CPUIndex ] . MI == MI ) { if ( ! OffsetIsInRange ( Offset , EndInsertOffset , CPUsers [ CPUIndex ] . MaxDisp , ! isThumb ) ) { BaseInsertOffset -= ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb ? <NUM_LIT>


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> if ( CmpOpcode ) F -> insert ( It , loop2MBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; Register TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( AtomicSize == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LoadMnemonic ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; if ( CmpOpcode ) { if ( CmpOpcode == <STR_LIT> && AtomicSize < <NUM_LIT> ) { unsigned ExtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( AtomicSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , ExtReg ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( CmpOpcode ) , <STR_LIT> ) . addReg ( incr ) . addReg ( ExtReg ) ; } else BuildMI ( BB , dl , TII -> get ( CmpOpcode ) , <STR_LIT> ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CmpPred ) . addReg ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB


<s> if ( matchVectorShuffleWithPACK ( VT , PackVT , V1 , V2 , PackOpcode , Mask , DAG , Subtarget ) ) return DAG . getNode ( PackOpcode , DL , VT ,

DAG . getBitcast ( PackVT , V1 ) , DAG . getBitcast ( PackVT , V2 ) ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> if ( brmask & <NUM_LIT> ) set_reg ( sr -> curr . reg + UNW_REG_B1 + i , UNW_WHERE_GR , sr -> region_start + sr -> region_len - <NUM_LIT> , gr ++ ) ; brmask >>=


<s> for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: instr_iterator FI = I . getReverse ( ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I


<s> if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; BeforeOps . insert ( BeforeOps . end ( ) , AfterOps . begin ( ) , AfterOps . end ( ) ) ; SDNode * NewNode = DAG . getMachineNode ( Opc , dl , VTs , BeforeOps ) ; NewNodes . push_back ( NewNode ) ; if ( FoldedStore ) { AddrOps . pop_back ( ) ; AddrOps . push_back ( SDValue ( NewNode , <NUM_LIT> ) ) ; AddrOps . push_back ( Chain ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractStoreMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC


<s> SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; unsigned NumArgs = Ins . size ( ) ; Function :: const_arg_iterator CurOrigArg = MF . getFunction ( ) -> arg_begin ( ) ; unsigned CurArgIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ValVT = Ins [ i ] . VT ; std :: advance ( CurOrigArg , Ins [ i ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ i ] . OrigArgIndex ; EVT ActualVT = getValueType ( CurOrigArg -> getType ( ) , true ) ; MVT ActualMVT = ActualVT . isSimple ( ) ? ActualVT . getSimpleVT ( ) : <STR_LIT> ; if ( ActualMVT == <STR_LIT> || ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; else if ( ActualMVT == <STR_LIT> ) ValVT = <STR_LIT> ; CCAssignFn * AssignFn = CCAssignFnForCall ( CallConv , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , Ins [ i ] . Flags , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void ) Res ; } assert ( ArgLocs . size ( ) == Ins . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC =


<s> void printS32ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream &


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op ,


<s> } } ; assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( ScalarType -> isFloatingPointTy ( ) && Index ==


<s> if ( ADDCNode -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue MultHi = ADDENode -> getOperand ( <NUM_LIT> ) ; SDValue MultLo = ADDCNode -> getOperand ( <NUM_LIT> ) ; SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDValue Chain = CurDAG -> getEntryNode ( ) ; DebugLoc dl = ADDENode -> getDebugLoc ( ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , dl , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; SDValue CopyFromLo = CurDAG -> getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> , MAdd ) ; SDValue CopyFromHi = CurDAG -> getCopyFromReg ( CopyFromLo . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , CopyFromLo . getValue ( <NUM_LIT> ) ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) CurDAG

-> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT> ) , CopyFromLo ) ;


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys ,


<s> } else { rtx cond = gen_rtx_GT ( VOIDmode , e , zero ) ; rs6000_emit_vector_cond_expr ( e , e , zero , cond , src , zero ) ; } } emit_insn ( gen_mul ( g , e , src ) ) ; emit_insn ( gen_mul ( h , e , mhalf ) ) ; if ( recip ) { if ( passes == <NUM_LIT> ) { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h , mhalf ) ; rs6000_emit_madd ( dst , e , t , e ) ; } else { for ( i = <NUM_LIT> ; i < passes ; i ++ ) { rtx t1 = gen_reg_rtx ( mode ) ; rtx g1 = gen_reg_rtx ( mode ) ; rtx h1 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t1 , g , h , mhalf ) ; rs6000_emit_madd ( g1 , g , t1 , g ) ; rs6000_emit_madd ( h1 , h , t1 , h ) ; g = g1 ; h = h1 ; } emit_insn ( gen_add3_insn ( dst , h , h ) ) ; } } else { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF


<s> Type * Ty = arg . getType ( ) ; if ( auto * STy = dyn_cast < StructType > ( Ty ) ) Ty = STy -> getTypeAtIndex ( ( uint32_t ) <NUM_LIT> ) ; if ( auto * VT = dyn_cast < VectorType > ( Ty ) ) if ( VT -> isScalable ( ) ) return true ; } Type * Ty = MF . getFunction ( ) -> getReturnType ( ) ; if ( auto * STy = dyn_cast < StructType > ( Ty ) ) Ty = STy -> getTypeAtIndex ( (


<s> inline static bool isPreOp ( unsigned AluOp ) { return AluOp &


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsFlagSetting = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefMI . print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; NewCmp = convertToFlagSetting ( DefMI , IsFlagSetting ) ; NewBr = convertToCondBr ( MI ) ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsFlagSetting = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } DEBUG ( dbgs ( ) << <STR_LIT>


<s> unsigned getFPImm ( ) const { assert ( Kind ==


<s> if ( GET_CODE ( insn ) != JUMP_INSN ) return <NUM_LIT> ; if ( PREV_INSN ( insn ) && PREV_INSN ( PREV_INSN ( insn ) ) && GET_CODE ( next_real_insn ( PREV_INSN ( PREV_INSN ( insn ) ) ) ) == INSN ) { rtx test_insn = next_real_insn ( PREV_INSN ( PREV_INSN ( insn ) ) ) ; return ( GET_CODE ( PATTERN ( test_insn ) ) == SEQUENCE && XVECEXP ( PATTERN ( test_insn ) , <NUM_LIT> , <NUM_LIT> ) == insn ) ; } else return


<s> UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } } return


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = LHS . getValueType ( ) ; SDLoc DL ( N ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> )


<s> return ! IS_NAKED ( arm_current_func_type


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> static bool isHorizontalReduction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t Flags =


<s> if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; if ( ! IsLegal && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) IsLegal = <STR_LIT>

( ImmInt . getZExtValue ( ) , VT . getSizeInBits ( ) ) ;


<s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , isDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool isThumb = STI . isThumb ( ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! isDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = isThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; if ( ! SplitRegs . empty (


<s> break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , <NUM_LIT> ) ) ) return NULL_RTX ; plus_rtx = XEXP ( mem_rtx , <NUM_LIT> ) ; switch ( GET_CODE ( plus_rtx ) ) { case SYMBOL_REF : case CONST : case POST_INC : case POST_DEC : return NULL_RTX ; case PLUS : if ( REG_P ( XEXP ( plus_rtx , <NUM_LIT> ) )

) offset_rtx = XEXP ( plus_rtx , <NUM_LIT> ) ;


<s> ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si


<s> bool hasTOCLoReloc ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) return true ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> )


<s> return Op + <STR_LIT> <= MI . getNumOperands ( ) && MI . getOperand ( Op + <STR_LIT> ) . isReg ( ) && isScale ( MI . getOperand ( Op + <STR_LIT> ) ) && MI . getOperand ( Op + <STR_LIT> ) . isReg ( ) && ( MI . getOperand ( Op + <STR_LIT> ) . isImm ( )

|| MI . getOperand ( Op + <STR_LIT> ) . isGlobal ( ) || MI . getOperand ( Op + <STR_LIT> ) . isCPI ( ) || MI . getOperand ( Op + <STR_LIT> ) . isJTI ( ) ) ;


<s> static const Constant * getConstantFromPool ( const MachineInstr & MI , const MachineOperand & Op ) { if ( ! Op . isCPI ( ) ) return nullptr ; ArrayRef < MachineConstantPoolEntry > Constants = MI . getParent ( ) -> getParent ( ) -> getConstantPool ( ) -> getConstants ( ) ; const MachineConstantPoolEntry & ConstantEntry = Constants [ Op


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool has<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS


<s> CDE . insert ( Mnemonic ) ; CDEWithVPTSuffix . insert ( Mnemonic ) ; CDEWithVPTSuffix . insert ( std :: string ( Mnemonic ) + <STR_LIT> ) ; CDEWithVPTSuffix . insert ( std :: string (


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SDValue SignMask2x64 ( SDValue A ) { assert ( A . getSimpleValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( A . getSimpleValueType ( ) != <STR_LIT>


<s> return DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , ThreadPointer , MachinePointerInfo ( ) , false , false ,


<s> AsmPrinter :: EmitBasicBlockEnd ( MBB ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( MBB . empty ( ) ) TS . emitDirectiveInsn


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_SJLJ_SETJMP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op


<s> Iter Filler :: replaceWithCompactJump ( MachineBasicBlock & MBB , Iter Jump , DebugLoc DL ) { const <ISA_LIT>InstrInfo * TII = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> if ( auto USatVal = detectUSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( ( VT . getScalarType ( ) == <STR_LIT> && InVT . getScalarType ( ) == <STR_LIT> ) || ( VT . getScalarType ( ) == <STR_LIT> && InVT . getScalarType ( ) == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( Subtarget . hasSSE41 ( ) || VT . getScalarType ( ) == <STR_LIT> ) if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL


<s> parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , <NUM_LIT> ) )


<s> DiagnosticPredicate isSVEPreferredLogicalImm ( ) const { if ( isLogicalImm < T > ( ) && ! isSVECpyImm < T > ( ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy


<s> if ( ! ImmToIdxMap . count ( ImmOpcode )


<s> inline int vec_any_ge ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgefp_p ( __CR6_EQ_REV , a1 ,


<s> if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> ; else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> + <NUM_LIT> ; else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> + <NUM_LIT> ; else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> + <NUM_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> )


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return &


<s> bool setATRegIndex ( unsigned Reg ) { if ( Reg > <NUM_LIT> ) return false ; ATReg =


<s> SDValue <ISA_LIT>TargetLowering :: combineVReverseMemOP ( ShuffleVectorSDNode * SVN , LSBaseSDNode * LSBase , DAGCombinerInfo & DCI ) const { assert ( ( <STR_LIT> ( LSBase ) || <STR_LIT> ( LSBase ) ) && <STR_LIT> ) ; auto IsElementReverse = [ ] ( const ShuffleVectorSDNode * SVN ) -> bool { auto Mask = SVN -> getMask ( ) ; int i = <NUM_LIT> ; auto I = Mask . rbegin ( ) ; auto E = Mask . rend ( ) ; for ( ; I != E ; ++ I ) { if ( * I != i ) return false ; i ++ ; } return true ; } ; SelectionDAG & DAG = DCI . DAG ; EVT VT = SVN -> getValueType ( <NUM_LIT> ) ; if ( ! isTypeLegal ( VT ) || ! Subtarget . isLittleEndian ( ) || ! Subtarget . hasVSX ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasP9Vector ( ) ) return SDValue ( ) ; if ( ! IsElementReverse ( SVN ) ) return SDValue ( ) ; if ( LSBase -> getOpcode ( ) == <STR_LIT> ) { SDLoc dl ( SVN ) ; SDValue LoadOps [ ] = { LSBase -> getChain ( ) , LSBase -> getBasePtr ( ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , LoadOps , LSBase -> getMemoryVT ( ) , LSBase -> getMemOperand ( ) ) ; } if ( LSBase -> getOpcode ( ) == <STR_LIT>


<s> unsigned numElts = regSize / size ; unsigned mask = ( <NUM_LIT> << size ) - <NUM_LIT> ; uint64_t lowestEltVal = imm & mask ; bool allMatched = true ; for ( unsigned i = <NUM_LIT> ; i < numElts ; ++ i ) { uint64_t currEltVal = ( imm >> ( i * size ) ) & mask ; if ( currEltVal != lowestEltVal ) { allMatched = false ; break ; } } if ( allMatched ) { eltVal = lowestEltVal ; break ; } size *= <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> ; i < size ; ++ i ) { eltVal = ror ( eltVal , size ) ; uint32_t clz = countLeadingZeros ( eltVal ) - ( <NUM_LIT> - size ) ; uint32_t cto = CountTrailingOnes_64 ( eltVal ) ; if ( clz + cto == size ) { unsigned immr = size - ( i + <NUM_LIT> ) ; uint64_t nimms = ~ ( size - <NUM_LIT> ) << <NUM_LIT> ; nimms |= ( cto - <NUM_LIT> ) ; unsigned N = ( ( nimms >> <NUM_LIT> ) & <NUM_LIT> )


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <NUM_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + <NUM_LIT> ) . isReg ( ) &&


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; unsigned Alignment = LD -> getOriginalAlignment ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo ( ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; SDValue NewLoad2 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( NewLoad1 . getNode ( ) , <NUM_LIT>

) , SDValue ( NewLoad2 . getNode ( ) , <NUM_LIT> ) ) ;


<s> MachineBasicBlock & MBB = * Root . getParent ( ) ; bool Found = false ; auto Match = [ & ] ( unsigned Opcode , int Operand , MachineCombinerPattern Pattern ) -> bool { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineOperand & MO = Root . getOperand ( Operand ) ; MachineInstr * MI = nullptr ; if ( MO . isReg ( ) && Register :: isVirtualRegister ( MO . getReg ( ) ) ) MI = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ; if ( MI && MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) MI = MRI . getUniqueVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( MI && MI -> getOpcode ( )


<s> Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; return DAG . getConstant ( Imm , DL


<s> enum machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) { enum machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type )


<s> return ( N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) ) ; } ; if ( ! N -> hasOneUse ( ) || ! N -> getSimpleValueType ( <NUM_LIT> ) . bitsGE ( <STR_LIT> ) || ! isORCandidate ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto isSetCCCandidate = [ ] ( SDValue N ) { return N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) && <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isNullConstant ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . bitsGE ( <STR_LIT> ) ; } ; SDNode * OR = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue LHS = OR -> getOperand ( <NUM_LIT> ) ; SDValue RHS = OR -> getOperand ( <NUM_LIT> ) ; SmallVector < SDNode * , <NUM_LIT> > ORNodes ; while ( ( ( isORCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ( isORCandidate ( RHS ) && isSetCCCandidate ( LHS ) ) ) ) { ORNodes . push_back ( OR ) ; OR = ( LHS -> getOpcode ( ) == <STR_LIT> ) ? LHS . getNode ( ) : RHS . getNode ( ) ; LHS = OR -> getOperand ( <NUM_LIT> ) ; RHS = OR -> getOperand ( <NUM_LIT> ) ; } if ( ! ( isSetCCCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ! isORCandidate ( SDValue ( OR , <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = OR -> getValueType ( <NUM_LIT> ) ; SDValue NewLHS = lower<ISA_LIT>CmpEqZeroToCtlzSrl ( LHS , VT , DAG ) ; SDValue Ret , NewRHS


<s> void <ISA_LIT>InstPrinter :: printBankedRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint32_t Banked = MI -> getOperand ( OpNum ) . getImm ( ) ; uint32_t R = ( Banked & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t SysM = Banked & <NUM_LIT> ; if ( R ) { O << <STR_LIT> ; switch ( SysM ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( ! R && <STR_LIT> ) ; const char * RegNames [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name =


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { MVT XORVT = VT . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , XORVT , DAG . getNode ( <STR_LIT> , dl , XORVT , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , XORVT , Mask ) ) ) ; } else { return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT>


<s> bool enableMachineScheduler ( ) const override


<s> SDValue Result = DAG . getBuildVector ( ViaVecTy , DL , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( ViaVecTy != ResVecTy ) { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ViaVecTy ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Result , One ) ) ; } return Result


<s> else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> if ( ! MI ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned NewOpc = sForm ( * MI ) ; if ( NewOpc == <STR_LIT> ) return false ; if ( ! canInstrSubstituteCmpInstr ( MI , CmpInstr ,


<s> SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , SDValue ( BFM , <NUM_LIT> ) , SubReg ) ; return Node ; } SDValue Ops [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , dl , VT ) , CurDAG -> getTargetConstant ( MSB , dl ,


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isThumb ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isThumb ) , FrameInfo ( Subtarget ) , JITInfo

( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> void <ISA_LIT>ConstantPoolValue :: AddSelectionDAGCSEId ( FoldingSetNodeID & ID ) { ID . AddPointer ( GV ) ; ID . AddPointer ( S ) ; ID . AddInteger (


<s> return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT>


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_BankedReg ) ; Op -> BankedReg . Val = Reg ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT> ) ; return ; } assert ( pos < <NUM_LIT> && <STR_LIT> ) ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( size - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT>


<s> for ( auto DispSizePair = std :: next ( BlockingStoresDispSizeMap . begin ( ) ) ; DispSizePair != BlockingStoresDispSizeMap . end ( ) ; ++ DispSizePair ) { int64_t CurrDisp = DispSizePair -> first ; unsigned CurrSize = DispSizePair -> second ; if ( CurrDisp + CurrSize <= PrevDisp + PrevSize ) { ForRemoval . push_back ( PrevDisp


<s> unsigned OpC = MI . getOpcode ( ) ; return offsetMinAlignForOpcode ( OpC


<s> if ( recog_memoized ( in_insn ) < <NUM_LIT> || ( get_attr_type ( in_insn ) != TYPE_FPSTORE && get_attr_type ( in_insn ) != TYPE_FPSTORE_LOAD ) || recog_memoized ( out_insn ) < <NUM_LIT> ) return <NUM_LIT> ; store_mode = GET_MODE ( SET_SRC ( PATTERN ( in_insn ) ) ) ; set = single_set ( out_insn ) ; if ( ! set ) return <NUM_LIT> ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) == GET_MODE_SIZE ( other_mode


<s> void EmitARM64WinCFISaveFRegX ( unsigned Reg , int Offset


<s> if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) ,


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> return ( __m64 ) __builtin_ia32_paddsb ( ( __v8qi ) __m1 ,


<s> return pParent . getTarget ( ) . getGOT ( ) . addr


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) return

ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ;


<s> unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm