<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return


<s> else if ( local_symbolic_operand64 ( src , VOIDmode ) ) { emit_insn ( gen_load_gprel64 ( dest , src ) ) ; } else { HOST_WIDE_INT addend = <NUM_LIT> ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; lo = ( ( hi & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; hi = hi - lo ; if ( lo != <NUM_LIT> ) { addend = lo ; src = plus_constant ( Pmode , XEXP ( XEXP ( src ,


<s> PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0


<s> Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { Parser . EatToEndOfStatement ( ) ; return false


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; SrcReg = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC


<s> if ( MI . modifiesRegister ( BaseReg , TRI ) ) return false ; if ( isLdStPairSuppressed ( MI ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo , STI ,


<s> bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) MI -> eraseFromParent ( ) ; MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT>


== BLKmode && TREE_ADDRESSABLE ( ret_type ) && lang_GNU_CXX ( ) ) ;


<s> static bool arm_warn_func_return ( tree


<s> FinalStates . insert ( { BB , FinalState } ) ; } while ( ! Worklist . empty ( ) ) { BasicBlock * BB = Worklist . front ( ) ; Worklist . pop_front ( ) ; if ( InitialStates . count ( BB ) != <NUM_LIT> ) continue ; int PredState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; if ( PredState == OverdefinedState ) continue ; InitialStates . insert ( { BB , PredState } ) ; FinalStates . insert ( { BB , PredState } ) ; for ( BasicBlock * SuccBB : successors ( BB ) ) Worklist . push_back ( SuccBB ) ; } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! isStateStoreNeeded ( Personality , CS ) ) continue ; int State = getStateForCallSite ( BlockColors ,


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; BBUtils -> adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; computeBlockSize ( MF , OrigBB , BBInfo [ OrigBB -> getNumber ( ) ] ) ; computeBlockSize ( MF , NewBB , BBInfo [ NewBB -> getNumber ( ) ] ) ; adjustBBOffsetsAfter ( OrigBB )


<s> if ( Subtarget . is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( ! isPositionIndependent ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> )


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < NumElts ; ++ Idx ) { SDValue V = N -> getOperand ( Idx ) ; if ( V . isUndef ( ) ) continue ; if ( V . getOpcode ( ) == <STR_LIT> && V -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; else { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , <STR_LIT> , V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } SDValue LaneIdx = DAG . getConstant ( Idx , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , V , LaneIdx ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ; DCI . AddToWorklist ( Vec .


<s> for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v4s32 , v2s64

} ) setAction ( { MemOp , Ty } , Legal ) ;


<s> MCSymbolData & Data = getOrCreateSymbolData ( Sym ) ; MCELF :: setOther ( Data , Val >>


<s> bool <ISA_LIT>PreLegalizerCombinerInfo :: combine ( CombinerChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { CombinerHelper Helper ( Observer , B ) ; switch ( MI . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD


<s> if ( INSN_CODE ( insn ) != CODE_FOR_move_di && INSN_CODE ( insn ) != CODE_FOR_move_df


<s> auto * LoadA = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( <NUM_LIT> - I ) ) ; auto * LoadB = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( I ) ) ; return ! LoadA -> isVolatile ( ) && LoadA -> getMemoryVT ( ) == LoadB -> getMemoryVT

( ) && canUseBlockOperation ( StoreA , LoadB ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> )


<s> unsigned int i ; cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) rx_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mint_register_ : switch ( opt -> value ) { case <NUM_LIT> : fixed_regs [ <NUM_LIT> ] = call_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; case <NUM_LIT> : fixed_regs [ <NUM_LIT> ] = call_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; case <NUM_LIT> : fixed_regs [ <NUM_LIT> ] = call_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; case <NUM_LIT> : fixed_regs [ <NUM_LIT> ] = call_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; case <NUM_LIT> : rx_num_interrupt_regs = opt ->


<s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return expandLoadImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadImm ( Inst , false , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandBranchImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry ( )


<s> void <ISA_LIT>TTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ST -> getDarwinDirective ( ) == <STR_LIT>


<s> HOST_WIDE_INT odd ; poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > <NUM_LIT> ) return false ; if ( ! d -> perm [ <NUM_LIT> ] . is_constant ( & odd ) || ( odd != <NUM_LIT> && odd != <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , odd , <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , nelt + odd , <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1


<s> } Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; return MCDisassembler ::


<s> if ( ResVT . getVectorElementType ( ) == <STR_LIT> ) return Index == <NUM_LIT> || ( ( ResVT . getSizeInBits ( ) == SrcVT . getSizeInBits ( ) *

<NUM_LIT> ) && ( Index == ResVT . getVectorNumElements ( ) ) ) ;


<s> case <STR_LIT> : { unsigned FCVTMOpcs [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; Opc = FCVTMOpcs [ FpConVariant ] [ InTyVariant ] [ OutTyVariant ] ; break ; } case <STR_LIT> : { unsigned FCVTZOpcs [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; Opc = FCVTZOpcs [ FpConVariant ] [ InTyVariant ] [ OutTyVariant ] ; break ; } case <STR_LIT> : { unsigned FCVTAOpcs [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; Opc = FCVTAOpcs [ FpConVariant ] [ InTyVariant ] [ OutTyVariant ] ; break ; } } SDLoc DL ( N ) ; SDValue In = Op0 -> getOperand ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( In


<s> static MCSymbol * GetAnonSym ( MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) ) ; TmpStr +=


<s> V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) { EVT PackVT = V1Pack . getValueType ( ) ; if ( PackVT == V2Pack . getValueType ( ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , PackVT , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask ,


<s> return ( IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind

. isCommon ( ) || Kind . isReadOnly ( ) ) ) ;


<s> return ( int64x1_t ) { __builtin_aarch64_ashldi ( __a [ <NUM_LIT> ] ,


<s> return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( has<ISA_LIT>32r6 ( ) && isFP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r6FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler ::


<s> if ( ! isOperationLegalOrCustom ( <STR_LIT> , ResVT ) ) return false ; return ( Index == <NUM_LIT> || Index == ResVT . getVectorMinNumElements (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , LHS , RHS ) ; return SDValue ( )


<s> MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return VT1 == <STR_LIT> && VT2 == <STR_LIT> && Subtarget . is64Bit


<s> bool <ISA_LIT>AsmParser :: validatetLDMRegList ( const MCInst & Inst , const OperandVector & Operands , unsigned ListNo , bool IsARPop ) { const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst


<s> bool aarch64_sve_ld1rq_operand_p ( rtx op ) { return aarch64_sve_ld1rq_ld1ro_operand_p ( op , TImode , GET_MODE_INNER ( GET_MODE ( op )


<s> Value * <ISA_LIT>IREmitter :: visitWrapperJT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; unsigned NumPackedBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; KnownBits Known ; DAG . computeKnownBits ( In , Known ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; NumPackedBits = Subtarget . hasSSE41 ( ) ? NumPackedBits :


<s> static bool validSpImm8 ( int offset ) { return ( ( offset & <NUM_LIT> ) == <NUM_LIT> )


<s> const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment (


<s> void i386_djgpp_asm_lto_end ( void ) { debug_info_level =


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { assert ( <NUM_LIT> &&


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t Imm ) { if ( MachineInstOpcode == <STR_LIT> ) MRI .


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) addExpr ( Inst , getImm ( ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat ( ) const { return Subtarget . useSoftFloat (


<s> Value * <ISA_LIT>IREmitter :: visitVCLTZ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> return hasUnscaledLdStOffset ( MI . getOpcode (


<s> insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + <NUM_LIT> ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn


<s> int FIOffset ; if ( AfterFPPop ) { const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI . getOffsetOfLocalArea ( ) ; } else FIOffset = getFrameIndexOffset ( MF , FrameIndex ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = FIOffset + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else


<s> SDValue CCReg = N -> getOperand ( <NUM_LIT> ) ; if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Chain , DAG . getConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getConstant ( CCMaskVal , SDLoc ( N ) , <STR_LIT> ) , N ->


<s> Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = CurDAG -> getRegister ( GPReg , ValTy ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr .


<s> if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != const0_rtx ) ) return false ; break ; case CCmode : if ( req_mode == CCGCmode ) return false ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return false ; case CCGOCmode : if ( req_mode == CCZmode ) return false ; case CCZmode : break ; case CCAmode : case CCCmode : case CCOmode


<s> break ; case MULT : gcc_assert ( * amountp != - <NUM_LIT> ) ; * amountp = int_log2 ( * amountp ) ; return <STR_LIT> ; default : gcc_unreachable ( ) ; } if ( * amountp != - <NUM_LIT> ) { if ( code == ROTATERT ) * amountp &= <NUM_LIT> ; else if ( * amountp != ( * amountp & <NUM_LIT> ) ) { if ( code == ASHIFT ) mnem = <STR_LIT> ; * amountp = <NUM_LIT> ; } if ( * amountp ==


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT>


<s> if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && PatternNodeWithChain . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD , <NUM_LIT> ) ; return true ; } return


<s> bool add_note = false ; if ( ! NONJUMP_INSN_P ( insn ) || NEXT_INSN ( insn ) ) add_note = true ; else { rtx set = single_set ( insn ) ; if ( set == NULL_RTX || SET_DEST ( set ) != end_addr || GET_CODE ( SET_SRC ( set ) ) != PLUS || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != stack_pointer_rtx || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != rs ) add_note = true ; } insn = emit_insn ( insn ) ; if ( add_note ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( end_addr , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , rs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) retval = emit_insn ( gen_probe_stack_rangedi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; else retval = emit_insn ( gen_probe_stack_rangesi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; RTX_FRAME_RELATED_P ( retval ) = <NUM_LIT> ; add_reg_note ( retval , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , end_addr ) ) ; emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , rounded_size


<s> return ShiftExtend . Amount == <NUM_LIT> || ShiftExtend


<s> __builtin_ia32_pmovwb128mem_mask ( ( unsigned long long * ) __P , ( __v8hi ) __A ,


<s> } else { DebugLoc dl = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue BAGOTOffset = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALOOffset = DAG . getBlockAddress ( BA


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] .


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S4 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base , Offset ,


<s> SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) ,


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addr |= Rn << <NUM_LIT> ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! load


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , L ) ; return false ; } ; if ( parseMany ( parseOp ) ) return true ; return false


<s> if ( ( format == <NUM_LIT> && write_symbols != DWARF2_DEBUG ) || format == <NUM_LIT> ) return regno ; if ( regno <= <NUM_LIT> ) return regno ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm (


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY )

, ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> { <STR_LIT> , aarch64_d_handle_target_float_abi } , {


<s> return __builtin_mve_vldrhq_fv8hf ( ( __builtin_neon_hi * ) __base


<s> bool SelectAddrIdxOffs ( SDValue N , SDValue & Out ) const { if ( isa < ConstantSDNode > ( N ) || N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) return false ; Out = N ; return


<s> break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitAdjDynAlloc ( MI )


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getTheARM64Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getTheARM64Target ( )


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCatchPad ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const Constant * PerFn = MF -> getFunction ( ) . getPersonalityFn ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( PerFn ) ) ; if ( IsSEH && Subtarget . is32Bit ( ) ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; } MI . eraseFromParent ( )


<s> if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; const Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; auto * IndexVTy = FixedVectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL ,


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT>


<s> } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { assert ( VT . getSizeInBits ( ) >= SrcSVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned OpCode = ( SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( OpCode , dl , <STR_LIT> , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; return DAG . getZExtOrTrunc ( ExtOp , dl , VT ) ; } return SDValue ( )


<s> for ( int i = <NUM_LIT> ; CopyOpcodes [ i ] != - <NUM_LIT> ; i ++ ) if ( Opcode == CopyOpcodes [ i ] ) return true ; return false


<s> getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( )


<s> emit ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( gen_rtx_REG ( SImode , <NUM_LIT> ) , gen_rtx_fmt_ee ( unsignedp ? UDIV : DIV , SImode , gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode ,

<NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , ret ) ) ) ) ;


<s> if ( auto FMLA = instCombineSVEVectorFMLA ( IC , II ) ) return FMLA ; return instCombineSVEVectorBinOp ( IC


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; const TargetRegisterClass * RC = is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned PtrReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Shift1Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) .


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFILL_FW ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get


<s> SDLoc dl ( NatWidthRes ) ; if ( Conv == ExtOrTruncConversion :: Ext ) { SDValue ImDef ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ) , <NUM_LIT> ) ; SDValue SubRegIdx = CurDAG -> getTargetConstant ( <STR_LIT> , dl ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> return ( __builtin_sh_media_LDHI_L ( ( char * ) p + <NUM_LIT> ) | __builtin_sh_media_LDLO_L


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( HasAVX2 ) return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return <NUM_LIT>


<s> bool <ISA_LIT>GOT :: dynSymOrderCompare ( const LDSymbol * pX , const LDSymbol * pY ) const { SymbolOrderMapType :: const_iterator itX = m_SymbolOrderMap


<s> if ( get<ISA_LIT>Subtarget ( ) . hasNEON ( ) ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) )


<s> HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE1 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc =


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( Rt ) ) ; } Inst . addOperand ( MCOperand :: createReg ( Rt ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand ::


<s> const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; auto & MemOp = * * I . memoperands_begin ( ) ; if ( MemOp . getOrdering ( ) != AtomicOrdering :: NotAtomic ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . optForSize ( ) ; Subtarget = & MF . getSubtarget


<s> exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AllOnes ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( AllOnes ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StoreVal ) . addReg ( Ptr


<s> DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm


<s> return i ( ) . enable | get_enable ( args ...


<s> static SDValue PerformADCCombine ( SDNode * N , SelectionDAG & DAG , <ISA_LIT>TargetLowering :: DAGCombinerInfo & DCI ) { if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { DebugLoc DL = N -> getDebugLoc ( ) ; EVT VT = N -> getValueType


<s> assert ( ( Cond . size ( ) && Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] .


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger (


<s> void <ISA_LIT>BaseInstrInfo :: copyToCPSR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool KillSrc , const <ISA_LIT>Subtarget & Subtarget ) const { unsigned Opc = Subtarget . isThumb ( ) ? ( Subtarget . isMClass ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get (


<s> RS6000_OUTPUT_BASENAME ( stream , name ) ; putc ( '\n' ,


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N ->


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) { addExpr ( Inst , Imm . Val ) ; return ; } int64_t Val = CE -> getValue ( ) ; assert ( Val % scale == <NUM_LIT> && <STR_LIT> ) ; Val /=


<s> static inline void desc_spill_psprel_p ( unsigned char qp , unw_word t , unsigned char abreg , unw_word pspoff , struct unw_state_record * sr ) { struct unw_reg_info * r ; if ( ! desc_is_active ( qp , t , sr ) ) return ; r = sr -> curr . reg + decode_abreg ( abreg , <NUM_LIT> ) ; r -> where = UNW_WHERE_PSPREL ; r -> when = sr -> region_start + MIN ( ( int ) t


<s> unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << ( i * <NUM_LIT>


<s> unsigned getMaxBytesForLoopAlignment ( ) const { return MaxBytesForLoopAlignment


<s> if ( ! LastMI -> killsRegister ( <STR_LIT> ) && ! checkCCKill ( * LastMI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = skipDebugInstructionsForward ( std :: next ( MachineBasicBlock :: iterator ( LastMI ) ) , MBB -> end ( ) ) ; createPHIsForSelects ( MIItBegin , MIItEnd ,


<s> assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { SDValue GotAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags |


<s> if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode ( ) , <NUM_LIT> ) ; } } return Chain


<s> else if ( Subtarget . has<ISA_LIT>64 ( ) ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Subtarget . has<ISA_LIT>32r2 ( ) ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else EFlags |= ELF :: EF_MIPS_ARCH_32 ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) EFlags |= ELF :: EF_MIPS_MICROMIPS ; if ( Subtarget . isABI_O32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; Reloc :: Model RM = Subtarget . getRelocationModel


<s> bool isGPRegisterReserved ( size_t i ) const { return ReservedGPRegisters [


<s> return ( __m256d ) __builtin_ia32_vfnmsubpd256_mask ( ( __v4df ) __A , ( __v4df )


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return *


<s> if ( ! Errata602117 && ! NonConsecutiveRegs ) return false ; bool isT2 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isLd = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool EvenDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool EvenUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg


<s> assert ( Matrix . size ( ) == <NUM_LIT> && <STR_LIT> ) ; TransposedMatrix . resize ( <NUM_LIT> ) ; static constexpr int IntMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = makeArrayRef ( IntMask1 , <NUM_LIT> ) ; Value * IntrVec1 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec2 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask2 , <NUM_LIT> ) ; Value * IntrVec3 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec4 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask3 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask3 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec3 , IntrVec4 , Mask ) ; static constexpr int IntMask4 [ ] = { <NUM_LIT> ,


<s> static DecodeStatus DecodeDPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> if ( TT . isOSBinFormatMachO ( ) ) return <STR_LIT> ; if ( LittleEndian ) return <STR_LIT> ; return


<s> SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return createCMovFP ( DAG , Cond , True ,


<s> bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowGPR = ZFI -> getLowSavedGPR ( ) ; unsigned HighGPR = ZFI -> getHighSavedGPR ( ) ; unsigned StartOffset = RegSpillOffsets [ LowGPR ] ; if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT>


<s> return __builtin_ia32_subph128_mask ( __B , __C , _mm_setzero_ph ( ) ,


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF

:: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> NewMask |= ITState . Mask & ( <NUM_LIT> << TZ ) ; NewMask |= ( Cond != ITState . Cond ) << TZ ; NewMask |= <NUM_LIT> << ( TZ - <NUM_LIT> ) ; ITState . Mask =


<s> unsigned CPELogAlign = getCPELogAlign ( * CPEMI ) ; MachineBasicBlock * UserMBB = UserMI -> getParent ( ) ; const BasicBlockInfo & UserBBI = BBInfo [ UserMBB -> getNumber ( ) ] ; if ( BBHasFallthrough ( UserMBB ) ) { unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex +


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc


<s> void rs6000_output_symbol_ref ( FILE * file , rtx x ) { const char * name = XSTR ( x , <NUM_LIT> ) ; tree decl = SYMBOL_REF_DECL ( x ) ; if ( decl && DECL_P ( decl ) && DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) && name [ strlen (


<s> case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> )


<s> virtual bool gate ( function * ) { return TARGET_AVX && ! TARGET_AVX512F && TARGET_VZEROUPPER &&


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = vec_max ( a , b


<s> return __builtin_loongson_paddusb ( s ,


<s> PointerSize = ( is64Bit && ! isX32 && ! isNaCl ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT>


<s> char * <ISA_LIT>JITInfo :: allocateThreadLocalMemory ( size_t size ) { TLSOffset -= size ; return TLSOffset ; llvm_unreachable ( <STR_LIT> ) ; return


<s> bool MIEquivalentToCmp = ( ReusableCCMask == CCValues && CCValues == <STR_LIT> ( CompareFlags ) ) ; if ( ! MIEquivalentToCmp ) { SmallVector < MachineOperand * , <NUM_LIT> > AlterMasks ; for ( unsigned int I = <NUM_LIT> , E = CCUsers . size ( ) ; I != E ; ++ I ) { MachineInstr * MI = CCUsers [ I ] ; unsigned Flags = MI -> getDesc ( ) . TSFlags ; unsigned FirstOpNum ; if ( Flags & <STR_LIT> ) FirstOpNum = <NUM_LIT> ; else if ( Flags & <STR_LIT> ) FirstOpNum = MI -> getNumExplicitOperands ( ) - <NUM_LIT> ; else return false ; unsigned CCValid = MI -> getOperand ( FirstOpNum ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( FirstOpNum + <NUM_LIT> ) . getImm ( ) ; unsigned OutValid = ~ ReusableCCMask & CCValid ; unsigned OutMask = ~ ReusableCCMask & CCMask ; if ( OutMask != <NUM_LIT> && OutMask != OutValid ) return false ; AlterMasks . push_back ( & MI -> getOperand ( FirstOpNum ) ) ; AlterMasks . push_back ( & MI -> getOperand ( FirstOpNum + <NUM_LIT> ) ) ; } for ( unsigned I = <NUM_LIT> , E = AlterMasks . size ( ) ; I != E ; I += <NUM_LIT> ) { AlterMasks [ I ] -> setImm ( CCValues ) ; unsigned CCMask = AlterMasks [ I + <NUM_LIT> ] -> getImm ( ) ; if ( CCMask & ~ ReusableCCMask ) AlterMasks [ I + <NUM_LIT> ] -> setImm ( ( CCMask & ReusableCCMask ) | ( CCValues & ~ ReusableCCMask ) ) ; } } if ( ! ConvOpc ) { int CCDef = MI . findRegisterDefOperandIdx ( <STR_LIT> , false , true , TRI ) ; assert ( CCDef >= <NUM_LIT>


<s> getShiftRight16Imm ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> if ( MI -> isReturn ( ) ) return ; E = MI -> getNumOperands ( ) ; for ( ; I != E ; ++ I ) insertDefUse ( MI -> getOperand ( I ) , RegDefs


<s> FunctionPass * llvm :: create<ISA_LIT>PreEmit ( ) { return new <ISA_LIT>PreEmit (


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) &&


<s> for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBUtils -> clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; JumpTableEntryIndices . clear ( ) ; JumpTableUserIndices . clear (


<s> unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = <NUM_LIT> ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return <NUM_LIT> ; } unsigned UseAdj = <NUM_LIT> ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - <NUM_LIT> ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == <STR_LIT> ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> ) { return Subtarget . isCortexA9 ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( UseMI -> isBranch ( ) ) return <NUM_LIT> ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > <NUM_LIT> && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) )


<s> action = _US_UNWIND_FRAME_RESUME | _US_FORCE_UNWIND ; resuming = <NUM_LIT> ; } else action = _US_UNWIND_FRAME_STARTING | _US_FORCE_UNWIND ; if ( entry_code == _URC_OK ) { UCB_SAVED_CALLSITE_ADDR ( ucbp ) = saved_vrs . core . r [ R_PC ] ; next_vrs = saved_vrs ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( action , ucbp , ( void * ) & next_vrs ) ; saved_vrs . prev_sp = next_vrs . core . r [ R_SP ] ; } else { action |= _US_END_OF_STACK ; saved_vrs . prev_sp = saved_vrs . core . r [ R_SP


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & LII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc


<s> WideVT = VT ; ExtVec = getSVESafeBitCast ( VT , Vec1 , DAG ) ; } else { WideVT = InVT . widenIntegerVectorElementType ( * ( DAG . getContext ( ) ) ) ; ExtVec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec1 ) ; } if ( Idx == <NUM_LIT> ) { SDValue HiVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ExtVec , HiVec0 ) ; } else if ( Idx == InVT . getVectorMinNumElements ( ) ) { SDValue LoVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoVec0 , ExtVec ) ; } return SDValue ( ) ; } if ( Idx == <NUM_LIT> && isPackedVectorType ( InVT , DAG ) && Op .

getOperand ( <NUM_LIT> ) . isUndef ( ) ) return Op ;


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind


<s> EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; return


<s> bool <ISA_LIT>BaseInstrInfo :: isLdstSoMinusReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; return <STR_LIT> ( OffImm


<s> inline tree function_instance :: base_vector_type (


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness (


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( const GlobalValue * GV , const SDLoc & dl , int64_t Offset , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget . classifyGlobalReference ( GV ) ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( getGlobalWrapperKind ( GV , OpFlags


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_resume ( void ) { __builtin_tresume (


<s> SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op . getOperand ( <NUM_LIT> ) ) ; SDValue And0 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op0 , DAG . getConstant ( Mask - <NUM_LIT> , IntValTy ) ) ; SDValue And1 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op1 , DAG . getConstant ( Mask , IntValTy ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> ,


<s> rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ; if ( GET_MODE ( op ) == V4SFmode || GET_MODE ( op ) == V2SFmode ) tmp = gen_lowpart ( SImode , tmp ) ; return INTVAL (


<s> bool <ISA_LIT>AsmPrinter :: printAsmRegInClass ( const MachineOperand & MO , const TargetRegisterClass * RC , unsigned AltName , raw_ostream & O ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI ->


<s> MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified =


<s> SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , ZeroVal ) ; Ops [ <NUM_LIT> ] =


<s> return __builtin_mve_vqshlq_r_sv8hi ( __a ,


<s> if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ) { MachineBasicBlock & B = * I ++ ; Changed |= processBlock


<s> bool <ISA_LIT>FastISel :: IsMemCpySmall ( uint64_t


<s> if ( fs . sp_realigned && cfa_offset > fs . sp_realigned_fp_last ) { gcc_assert ( cfa_offset >= fs . sp_realigned_offset ) ; return false ; } return fs .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo


<s> case CmpInst :: FCMP_OGT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UNE : CondCode =


<s> MachineBasicBlock :: const_iterator I = MBB . begin ( ) ; for ( ; & * I != A && & * I != B ; ++ I ) ; return & *


<s> if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , <STR_LIT> ) ; return true ; } } } if ( SelectAddrModeUnscaled ( N , Size , Base , OffImm ) ) return false ; Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT>


<s> if ( * I == <STR_LIT> ) { LiveCPSR = true ; break ; } } MachineBasicBlock :: iterator MII = MBB . begin ( ) , E = MBB . end ( ) ; MachineBasicBlock :: iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = next ( MII ) ; MachineInstr * MI = & * MII ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI ,


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const


<s> static <ISA_LIT>Operand * CreateGPRReg ( unsigned Index , const MCRegisterInfo * RegInfo

, SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> static DecodeStatus DecodeShiftRight8Imm ( llvm :: MCInst & Inst , unsigned

Val , uint64_t Address , const void * Decoder ) {


<s> bool has<ISA_LIT>2Ops ( ) const { return <ISA_LIT>ArchVersion >=


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : if ( Subtarget -> hasVFP2 ( ) && ! isVarArg ) { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; } case CallingConv :: C : { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; else if ( Subtarget -> hasVFP2 ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : if ( ! isVarArg ) return (


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == <NUM_LIT> ) { return true ; } return false


<s> bool hasDotProd ( ) const { return HasDotProd


<s> any_addr_mask = <NUM_LIT> ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = <NUM_LIT> ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |=


<s> if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return false


<s> return new <ISA_LIT>CodeEmitter ( TM , JCE


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm18Lsl3Encoding ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT>


<s> void RegDefsUses :: setUnallocatableRegs ( const MachineFunction & MF ) { BitVector AllocSet = TRI . getAllocatableSet ( MF ) ; for ( unsigned R : AllocSet . set_bits ( ) ) for ( MCRegAliasIterator AI ( R , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AllocSet . set ( * AI ) ; AllocSet . set ( <STR_LIT> ) ; AllocSet . set (


<s> TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; } return


<s> } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) && emitFPU ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( !


<s> MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , <STR_LIT> , MBB ) ) ; MCE . emitWordLE (


<s> static bool needsShadowCallStackPrologueEpilogue ( MachineFunction & MF ) { if ( ! ( llvm :: any_of ( MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) , [ ] ( const auto & Info ) { return Info . getReg ( ) == <STR_LIT> ; } ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) ) return false ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; return true


<s> for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; MIB . addMBB ( TBB )


<s> vabal_high_u16 ( uint32x4_t a , uint16x8_t b , uint16x8_t c ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> bool <ISA_LIT>DAGToDAGISel :: tryFoldVecLoad ( SDNode * Root , SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( ! <STR_LIT> ( N . getNode ( ) ) || useNonTemporalLoad ( cast < LoadSDNode > ( N ) ) || ! IsProfitableToFold ( N , P , Root )

|| ! IsLegalToFold ( N , P , Root , OptLevel ) ) return false ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; bool HasRepeatedElts = false ; SmallVector < int , <NUM_LIT> > Mask ( NumElts , SM_SentinelUndef ) ; SmallVector < SDValue , <NUM_LIT> > Uniques ( V -> op_begin ( ) , V -> op_end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue Op = Uniques [ i ] ; if ( Op . isUndef ( ) ) continue ; Mask [ i ]


<s> default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( Scale


<s> Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( *


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo (


<s> OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; const unsigned EntryByteSize = Subtarget -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ; const unsigned TOCEntriesByteSize = TOC . size ( ) * EntryByteSize ; if ( TOCEntriesByteSize > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first ) ) ; OutStreamer -> SwitchSection


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const


<s> if ( ! TEST_HARD_REG_BIT ( reg_class_contents [ CR_REGS ] , regno )


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor (


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset <<


<s> return __aarch64_vset_lane_any ( __elem ,


<s> if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op

) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ;


<s> if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = Op . getScalarValueSizeInBits ( ) ; unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned EltBits ; if ( <STR_LIT> ( Imm , EltBits ) == <NUM_LIT> ) EltSize = <NUM_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( EltSize > VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N )


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCExpr * IdVal = nullptr ; SMLoc S ; bool isParenExpr = false ; <ISA_LIT>AsmParser :: OperandMatchResultTy Res = MatchOperand_NoMatch ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand * Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( Base , IdVal , S , E , * this ) ) ; return


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM

, CodeModel :: Model CM , CodeGenOpt :: Level OL ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; return nullptr ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> auto StatusOrErr = RealVal . convertFromString ( Desc -> Repr , APFloat :: rmTowardZero ) ; if ( ! StatusOrErr || * StatusOrErr != APFloat :: opOK ) llvm_unreachable ( <STR_LIT> ) ; if ( getFPImm ( ) . bitwiseIsEqual ( RealVal ) )


<s> if ( AlignBoundary == Align :: None ( ) || AlignBranchType == <STR_LIT> ) return false ; MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( Assembler . isBundlingEnabled ( ) && Sec -> isBundleLocked ( ) ) return false ; if ( ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] || STI . getFeatureBits


<s> static void fixupFuncForFI ( SelectionDAG & DAG , int FrameIdx , EVT VT ) { if ( VT != <STR_LIT> ) return ; if ( FrameIdx < <NUM_LIT> ) return ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF


<s> static bool ix86_expand_vec_perm_vpermt2 ( rtx target , rtx mask , rtx op0 , rtx op1 , struct expand_vec_perm_d * d ) { machine_mode mode = GET_MODE ( d ? d -> op0 : op0 ) ; machine_mode maskmode = mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) = NULL ; switch ( mode ) { case E_V16QImode : if ( TARGET_AVX512VL && TARGET_AVX512VBMI ) gen = gen_avx512vl_vpermt2varv16qi3 ; break ; case E_V32QImode : if ( TARGET_AVX512VL && TARGET_AVX512VBMI ) gen = gen_avx512vl_vpermt2varv32qi3 ; break ; case E_V64QImode : if ( TARGET_AVX512VBMI ) gen = gen_avx512bw_vpermt2varv64qi3 ; break ; case E_V8HImode : if ( TARGET_AVX512VL && TARGET_AVX512BW ) gen = gen_avx512vl_vpermt2varv8hi3 ; break ; case E_V16HImode : if ( TARGET_AVX512VL && TARGET_AVX512BW ) gen = gen_avx512vl_vpermt2varv16hi3 ; break ; case E_V32HImode : if ( TARGET_AVX512BW ) gen = gen_avx512bw_vpermt2varv32hi3 ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermt2varv4si3 ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermt2varv8si3 ; break ; case E_V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vpermt2varv16si3 ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermt2varv4sf3 ; maskmode = V4SImode ; } break ; case E_V8SFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermt2varv8sf3 ; maskmode = V8SImode ; } break ; case E_V16SFmode : if ( TARGET_AVX512F ) { gen = gen_avx512f_vpermt2varv16sf3 ; maskmode = V16SImode ; } break ; case E_V2DImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermt2varv2di3 ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermt2varv4di3 ; break ; case E_V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vpermt2varv8di3 ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermt2varv2df3 ; maskmode = V2DImode ; } break ; case E_V4DFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermt2varv4df3 ; maskmode = V4DImode ; } break ; case E_V8DFmode : if ( TARGET_AVX512F ) { gen = gen_avx512f_vpermt2varv8df3 ; maskmode = V8DImode ; } break ; default : break ; } if ( gen == NULL ) return false ; if ( d ) { rtx vec [ <NUM_LIT> ] ; target = d


<s> SDValue Hi = DAG . getConstant ( V . lshr ( <NUM_LIT> ) . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) std :: swap ( Lo , Hi ) ; return DAG . getBuildVector ( <STR_LIT> , DL , { Hi ,


<s> return __builtin_loongson_punpckhbh_s ( s , t


<s> mcInst . setOpcode ( insn . instructionID ) ; memset ( & mcInst . native_opcode [ <NUM_LIT> ] , <NUM_LIT> , sizeof ( mcInst . native_opcode ) ) ; memcpy ( & mcInst . native_opcode [ <NUM_LIT> ] , insn . native_opcode , sizeof ( mcInst . native_opcode ) ) ; memcpy ( & mcInst . prefixPresent [ <NUM_LIT> ] , & insn . prefixPresent [ <NUM_LIT> ] , sizeof ( uint8_t ) * <NUM_LIT> ) ; if ( insn .


<s> unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 (


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned RegNum = Tok . getIntVal ( ) ; if ( RegNum != <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * op = <STR_LIT> ( <STR_LIT> , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( op ) ; Parser . Lex (