<s> return true ; } case SQRT : case MOD : if ( float_mode_p ) { * total = loongarch_fp_div_cost ( mode ) ; return false ; } case UDIV : case UMOD : if ( ! speed ) { * total = COSTS_N_INSNS ( loongarch_idiv_insns ( mode ) ) ; } else if ( mode == DImode ) * total = loongarch_cost -> int_div_di ; else * total = loongarch_cost -> int_div_si ; return false ; case SIGN_EXTEND : * total = loongarch_sign_extend_cost ( XEXP ( x , <NUM_LIT> ) ) ; return false ; case ZERO_EXTEND : * total = loongarch_zero_extend_cost ( XEXP ( x , <NUM_LIT> ) ) ; return false ; case TRUNCATE : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ASHIFTRT || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LSHIFTRT ) && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && ( ( INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == DImode ) || ( TARGET_64BIT && INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == TImode ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == MULT && ( ( GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SIGN_EXTEND ) || ( GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ZERO_EXTEND && ( GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ZERO_EXTEND ) ) ) ) { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) + <NUM_LIT> ; else if ( mode == DImode ) * total = loongarch_cost -> int_mult_di ; else * total = loongarch_cost -> int_mult_si ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { rtx op = XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , i ) ; if ( TARGET_64BIT && GET_CODE ( op ) == ZERO_EXTEND && GET_MODE ( op ) == DImode ) * total += rtx_cost ( op , DImode , MULT , i , speed ) ; else * total += rtx_cost ( XEXP ( op , <NUM_LIT> ) , VOIDmode , GET_CODE ( op ) , <NUM_LIT> , speed ) ; } return true ; } return false ; case FLOAT : case UNSIGNED_FLOAT : case FIX : case FLOAT_EXTEND : case FLOAT_TRUNCATE : * total = loongarch_cost -> fp_add ; return false ; case SET


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && ! Subtarget -> hasFP64 ( ) && <STR_LIT> ) ; RTLIB ::


<s> return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > <NUM_LIT> : TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ) { tree t = fold_build_pointer_plus_hwi ( valist , <NUM_LIT> *


<s> return ( vector unsigned char ) __builtin_altivec_vxor ( ( vector signed int ) a1 , ( vector


<s> static SmallVector < int , <NUM_LIT> > getPSHUFShuffleMask ( SDValue N ) { MVT VT = N . getSimpleValueType ( ) ; SmallVector < int , <NUM_LIT> > Mask ; bool IsUnary ; bool HaveMask = getTargetShuffleMask ( N . getNode ( ) , VT , Mask , IsUnary ) ; ( void ) HaveMask ; assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - LaneElts && <STR_LIT> ) ; Mask . resize ( LaneElts


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex <=


<s> LegalizerHelper Helper ( MIRBuilder . getMF ( ) ) ; MachineInstr * NewMI = nullptr ; Helper . MIRBuilder . recordInsertions ( [ & ] ( MachineInstr * MI ) { if ( MI -> getOpcode ( ) == G_SDIV || MI -> getOpcode ( ) == G_UDIV ) NewMI = MI ; } ) ; auto Result = Helper . widenScalar ( MI , <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; Helper . MIRBuilder . stopRecordingInsertions ( ) ; if ( Result == LegalizerHelper :: UnableToLegalize ) { return false ; } assert ( NewMI && <STR_LIT> ) ; assert ( ( NewMI -> getOpcode ( ) == G_SDIV || NewMI -> getOpcode ( ) == G_UDIV ) && <STR_LIT> ) ; assert ( MRI . getType ( NewMI -> getOperand ( <NUM_LIT> ) . getReg (

) ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask (

Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode (


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> )

&& ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ;


<s> splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= <NUM_LIT> || ( step == <NUM_LIT> && copies == <NUM_LIT> ) ) ) ; else return false ; for ( i = <NUM_LIT> ; i < nunits - <NUM_LIT> ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + <NUM_LIT> ) & ( step - <NUM_LIT> ) ) == <NUM_LIT> ) desired_val = val ; else desired_val = msb_val


<s> switch ( ErrCode ) { case Match_MissingFeature : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidOperand : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSuffix : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed32SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed64SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed128SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectRelocImm ( SDValue N , SDValue & Op ) { if ( auto * CN = dyn_cast < ConstantSDNode > ( N ) ) { Op = CurDAG -> getTargetConstant ( CN -> getAPIntValue ( ) , SDLoc ( CN ) , N . getValueType ( ) ) ; return true ; } EVT VT = N . getValueType ( ) ; bool WasTruncated = false ; if ( N . getOpcode ( ) == <STR_LIT> ) { WasTruncated = true ; N = N . getOperand ( <NUM_LIT> ) ; } if ( N . getOpcode ( ) != <STR_LIT> ) return false ; unsigned Opc = N . getOperand ( <NUM_LIT> ) -> getOpcode ( ) ; if ( Opc != <STR_LIT> || ! WasTruncated ) { Op = N . getOperand ( <NUM_LIT> ) ; return ! WasTruncated


<s> MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> * <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( Flags ,


<s> for ( const MachineBasicBlock * S : MBB . successors ( ) ) if ( S != & SuccBB ) for ( const auto & LI : S -> liveins ( ) ) Uses


<s> void ChangeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getCurrentSection ( ) . first ] = std :: move ( LastEMSInfo ) ; MCELFStreamer :: ChangeSection ( Section , Subsection ) ; auto LastMappingSymbol = LastMappingSymbols . find (


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> unsigned Binary = ( <STR_LIT> ( SoImm


<s> if ( ! Subtarget . isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage


<s> unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end (


<s> static unsigned int flags_from_mode ( machine_mode mode ) { switch ( mode ) { case E_CC_ZSmode : return CC_FLAG_S | CC_FLAG_Z ; case E_CC_ZSOmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O ; case E_CC_ZSCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C ; case E_CCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C ; case E_CC_Fmode : return CC_FLAG_FP ; default : gcc_unreachable (


<s> if ( LastEMS == EMS_Data ) return ; EmitMappingSymbol (


<s> enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int )


<s> if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsVFReg = ( MI . getNumOperands ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! ConvertibleImmForm && ! instrHasImmForm ( Opc , IsVFReg , III , true ) ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * DefMI = getDefMIPostRA ( Reg , MI , SeenIntermediateUse ) ; if ( DefMI ) { switch ( DefMI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( MF . getFunctionNumber


<s> if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ <NUM_LIT> ] ) return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine (


<s> <STR_LIT> Cond = <STR_LIT> ( JmpI . getOpcode ( ) ) ; unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ; JmpI . setDesc ( TII -> get ( <STR_LIT> ( Inverted ? <STR_LIT> : <STR_LIT> ) ) ) ; const int ImplicitEFLAGSOpIdx = <NUM_LIT>


<s> Register Arg = getRegForValue ( * i ) ; if ( ! Arg . isValid ( ) ) return false ; Flags . setOrigAlign ( Align ( DL . getABITypeAlignment ( ArgTy ) ) ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; Register CalleeReg ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV , <NUM_LIT> , <NUM_LIT> ) ; else MIB . addExternalSymbol ( IntrMemName , <NUM_LIT> ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < Register , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , isVarArg ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ; return


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return MI ->


<s> bool IsLargeCodeModel = MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ; unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; const char * Symbol ; if ( Is64Bit ) { if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get


<s> unsigned Kind = Fixup . getTargetKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return Kind - FirstLiteralRelocationKind ; switch ( Kind )


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op


<s> if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = <ISA_LIT>MCExpr :: VK_SECREL_LO12 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = <ISA_LIT>MCExpr :: VK_SECREL_HI12 ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , RefKind , Ctx ) ; return MCOperand :: createExpr (


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> || DefMI -> getParent ( ) !=

FrameSetup -> getParent ( ) ) return nullptr ;


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ; assert ( ( ResVT . getSizeInBits ( ) == <NUM_LIT> || ResVT . getSizeInBits ( )


<s> DEBUG ( errs ( ) << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << MI ) ; MCE . processDebugLoc ( MI . getDebugLoc ( ) , true ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; emitWord ( getBinaryCodeForInstr (


<s> static const <ISA_LIT>MCExpr * CreateGOTTPREL ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_AARCH64_GOTTPREL ,


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; return


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( VTs , Ops , dl ,

MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ;


<s> int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned


<s> bool isMem128_RC256 ( ) const { return isMem128 ( ) && isMemIndexReg (


<s> static tree ix86_stack_protect_fail (


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; bool IsF128 = ( VT == <STR_LIT> ) ; assert ( VT . isFloatingPoint ( ) && VT != <STR_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && <STR_LIT> ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl ,


<s> if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack (


<s> assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetNaCl ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) &&


<s> i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent


<s> return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return selectShift ( I , MRI , MF ) ; case TargetOpcode :: G_SDIV : return selectSDiv ( I , MRI , MF ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectIntrinsicWSideEffects ( I , MRI , MF ) ; } return false


<s> static Optional < int64_t > getVectorShiftImm ( Register Reg , MachineRegisterInfo & MRI ) { assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ; MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ; return get<ISA_LIT>VectorSplatScalar ( * OpMI , MRI


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( )


, ( __mmask32 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> case <STR_LIT> : case <STR_LIT> : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case


<s> Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( IndxTy -> isVectorTy ( ) ) IndxTy = IndxTy -> getVectorElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor > <NUM_LIT> ) { Type * SplitSrcTy = VectorType :: get ( SrcVTy -> getScalarType ( ) , VF / SplitFactor ) ; return SplitFactor * getGSVectorCost ( Opcode , SplitSrcTy , Ptr , Alignment , AddressSpace ) ; } const int GSOverhead = ( Opcode == Instruction :: Load ) ? ST -> getGatherOverhead ( ) : ST -> getScatterOverhead ( ) ; return GSOverhead + VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( )


<s> if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != - <NUM_LIT> ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = false ; } else return false ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( LHS ) ; if ( BW == <NUM_LIT> && ! Is64Bit ) SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , SrcIsKill , <STR_LIT> ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; if ( IsBitTest ) MIB . addImm ( TestBit ) ; MIB . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) ,


<s> if ( CC == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> && LHS -> hasOneUse ( ) ) { auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> bool <ISA_LIT>BranchExpansion :: handleFPUDelaySlot ( ) { if ( STI -> has<ISA_LIT>32 ( ) || STI -> has<ISA_LIT>4


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC : FixupKind = <STR_LIT>


<s> return ggc_cleared_alloc < machine_function > (


<s> void <ISA_LIT>BasicBlockUtils :: adjustBBOffsetsAfter ( MachineBasicBlock * BB ) { assert ( BB -> getParent ( ) == & MF && <STR_LIT> ) ; unsigned BBNum = BB -> getNumber ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << <STR_LIT> << BB -> getNumber ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << <STR_LIT> << <STR_LIT> << MF . getNumBlockIDs ( ) << <STR_LIT> ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF . getNumBlockIDs ( ) ; i < e ; ++ i ) { const Align Align = MF . getBlockNumbered ( i ) -> getAlignment ( ) ; const unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( Align ) ; const unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( Align ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits == KnownBits ) break ; BBInfo [ i ] . Offset =


<s> const <ISA_LIT>CallEntry * & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = new <ISA_LIT>CallEntry


<s> Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; if ( ! Subtarget -> useConstIslands ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; } unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> ,


<s> unsigned getReg ( ) const override { assert ( ( Kind == k_Register ) && <STR_LIT>


<s> return <ISA_LIT>ABIInfo ( ABI :: O32


<s> target_node = ix86_valid_target_attribute_tree ( decl , attrs , & global_options , & global_options_set , <NUM_LIT> ) ; gcc_assert ( target_node ) ; if ( target_node == error_mark_node ) return <NUM_LIT> ; new_target = TREE_TARGET_OPTION ( target_node ) ; gcc_assert ( new_target ) ; enum ix86_builtins builtin_fn = IX86_BUILTIN_CPU_IS ; const char * arch_name = attrs_str + strlen ( <STR_LIT> ) ; if ( startswith ( arch_name , <STR_LIT> ) ) { arg_str = arch_name ; builtin_fn = IX86_BUILTIN_CPU_SUPPORTS ; if ( strcmp ( arch_name , <STR_LIT> ) == <NUM_LIT> ) priority = P_X86_64_BASELINE ; else if ( strcmp ( arch_name , <STR_LIT> ) == <NUM_LIT> ) priority = P_X86_64_V2 ; else if ( strcmp ( arch_name , <STR_LIT> ) == <NUM_LIT> ) priority = P_X86_64_V3 ; else if ( strcmp ( arch_name , <STR_LIT> ) == <NUM_LIT> ) priority = P_X86_64_V4 ; } else if ( new_target -> arch_specified && new_target -> arch > <NUM_LIT> ) for ( i = <NUM_LIT> ; i < pta_size ; i ++ ) if ( processor_alias_table [ i ] . processor == new_target -> arch ) { const pta * arch_info = & processor_alias_table [ i ] ; switch ( arch_info -> priority ) { default : arg_str = arch_info -> name ; priority = arch_info -> priority ; break ; case P_PROC_DYNAMIC : switch ( new_target -> arch ) { case PROCESSOR_NEHALEM : if ( TARGET_PCLMUL_P ( new_target -> x_ix86_isa_flags ) ) { arg_str = <STR_LIT> ; priority = P_PCLMUL ; } else { arg_str = <STR_LIT> ; priority = P_PROC_SSE4_2 ; } break ; case PROCESSOR_SANDYBRIDGE


<s> arg = TREE_STRING_POINTER ( TREE_VALUE ( attr ) ) ; for ( ptr = pcs_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if (

streq ( arg , ptr -> arg ) ) return ptr -> value ;


<s> putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else { gcc_assert ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } break ; case MINUS : if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '-' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']' , file ) ; break ; case UNSPEC : if ( XINT ( x , <NUM_LIT> ) == UNSPEC_STACK_CHECK ) { bool f = i386_asm_output_addr_const_extra ( file , x ) ; gcc_assert ( f ) ; break ; } gcc_assert ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) ; output_pic_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , code ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_PLTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_PCREL : fputs ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> , file ) ; break ; case UNSPEC_GOTPCREL : fputs ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> , file ) ; break ; case UNSPEC_GOTTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TPOFF : fputs ( <STR_LIT> , file ) ; break ; case


<s> assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT


<s> bool hasSlowDivide ( ) const { return HasSlowDivide


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; for ( unsigned J = I -> getDesc ( ) . getNumOperands ( ) , E = I -> getNumOperands ( ) ; J < E ; ++ J ) { const MachineOperand & MO = I -> getOperand ( J ) ; if ( MO . isMCSymbol ( ) && ( MO . getTargetFlags ( ) & <STR_LIT> ) ) MIB . addSym ( MO . getMCSymbol ( ) , <STR_LIT> ) ; } } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I )


<s> return ArePtrs64bit ( ) ? <STR_LIT> :


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : <NUM_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; if ( isVarArg ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : errs ( ) << <STR_LIT> << LocVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC =


<s> static SDValue combine<ISA_LIT>ShufflesRecursively ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , {

} , <NUM_LIT> , false , true , DAG , Subtarget ) ;


<s> struct DecodeTable { const uint8_t * P ; bool DecodePred ; } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT> , Address , this


<s> DAG . makeEquivalentMemoryOrdering ( Ld , V ) ; } else if ( ! BroadcastFromReg ) { return SDValue ( ) ; } else if ( BitOffset != <NUM_LIT> ) { if ( ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( ( BitOffset % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; assert ( ( BitOffset % V . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( V . getValueSizeInBits ( ) == <NUM_LIT> || V . getValueSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ExtractIdx = BitOffset / V . getScalarValueSizeInBits ( ) ; V = extract128BitVector ( V , ExtractIdx , DAG , DL ) ; } if ( Opcode == <STR_LIT> && ! V . getValueType ( ) . isVector ( ) ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V ) ) ; if ( V . getValueType ( ) . getScalarType ( ) != BroadcastVT . getScalarType ( ) ) { assert ( NumEltBits == BroadcastVT . getScalarSizeInBits ( ) && <STR_LIT> ) ; MVT ExtVT ; if ( V . getValueType ( ) . isVector ( ) ) { unsigned NumSrcElts = V . getValueSizeInBits ( ) / NumEltBits ; ExtVT = <STR_LIT> ( BroadcastVT . getScalarType ( ) , NumSrcElts ) ; } else { ExtVT = BroadcastVT . getScalarType ( ) ; } V = DAG . getBitcast ( ExtVT , V ) ; } if ( ! Subtarget . is64Bit ( ) && V . getValueType ( ) == <STR_LIT> ) { V = DAG . getBitcast ( <STR_LIT> , V ) ; unsigned NumBroadcastElts = BroadcastVT . getVectorNumElements ( ) ; BroadcastVT = <STR_LIT> ( <STR_LIT> , NumBroadcastElts ) ; } if ( V . getValueSizeInBits ( ) > <NUM_LIT> ) { MVT ExtVT = V . getSimpleValueType ( ) . getScalarType ( ) ; ExtVT = <STR_LIT> ( ExtVT , <NUM_LIT> / ExtVT . getScalarSizeInBits ( ) ) ; V = extract128BitVector ( peekThroughBitcasts ( V ) , <NUM_LIT> , DAG , DL ) ; V = DAG . getBitcast ( ExtVT , V ) ; } return DAG . getBitcast ( VT , DAG . getNode ( Opcode , DL , BroadcastVT ,


<s> auto * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueSizeInBits ( ) ) return false ; ShiftVal = Amount ; return


<s> SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL ,


<s> LowerExternalSymbolOperand ( const MachineOperand & MO ) { std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; if ( MO . getTargetFlags


<s>
O
<<
'#'
<<
FP
->
getValueAPF
(
)
.
convertToFloat
(
)
;
if
(
isVerbose
(
)
)
{
O
<<
<STR_LIT>
<<
MAI
->
getCommentString
(
)
<<
' '
;
WriteAsOperand
(
O
,
FP
,
false


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true , Result ) ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; std :: pair < SDNode * , SDNode * > LoHi = selectMULT ( Node , MultOpc , DL , NodeTy , true , true ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . first , <NUM_LIT> ) ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . second , <NUM_LIT> ) ) ; return std :: make_pair ( true , nullptr ) ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> :


<s> emit_insn ( gen_iwmmxt_clrdi ( mode == DImode ? x : gen_rtx_SUBREG (


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetPICBaseSymbol ( ) const { const TargetLowering * TLI = AsmPrinter . TM . getTargetLowering ( ) ; return static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ->

getPICBaseSymbol ( AsmPrinter . MF , Ctx ) ;


<s> return shouldSignReturnAddress ( llvm :: any_of ( MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) , [ ] ( const auto & Info ) { return Info . getReg ( ) ==


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( type ) , type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; rs6000_move_block_from_reg ( GP_ARG_MIN_REG + first_reg_offset , mem , nregs ) ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && TARGET_FPRS && ! no_rtl && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { int fregno = next_cum . fregno , nregs ; rtx cr1 = gen_rtx_REG ( CCmode , CR1_REGNO ) ; rtx lab = gen_label_rtx ( ) ; int off = ( GP_ARG_NUM_REG * reg_size ) + ( ( fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , cr1 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , lab ) , pc_rtx ) ) ) ; for ( nregs = <NUM_LIT> ; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun -> va_list_fpr_size ; fregno ++ , off += UNITS_PER_FP_WORD , nregs ++ ) { mem = gen_rtx_MEM ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode , plus_constant ( Pmode , save_area , off ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ) ) ; emit_move_insn ( mem , gen_rtx_REG ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode


<s> EVT InSVT = InVT . getScalarType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; if ( TLI . isOperationLegal ( <STR_LIT> , DstVT ) ) return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> reportParseError ( <STR_LIT> ) ; return false ; } Options . setNoreorder ( ) ; Parser . Lex ( ) ; return


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI ,


<s> return ( ( vec_uint4 ) ( si_gb ( ( qword ) ( a )


<s> static void register_svpattern ( ) { auto_vec < string_int_pair , <NUM_LIT> > values ; values . quick_push ( string_int_pair ( <STR_LIT> # UPPER ,


<s> int64x2x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU ,


<s> bool <ISA_LIT>FastISel :: SelectFPTrunc ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return


<s> SMLoc getStartLoc ( ) const { return StartLoc


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; uint64_t CstVal = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue


<s> RecipOp = Opcode == ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RecipOp = ( ( VT . isVector ( ) ) ? <STR_LIT> : <STR_LIT> ) + RecipOp ; RecipOp += ( VT . getScalarType ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { EVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT>


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; } return SDValue ( ) ; } unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getScalarSizeInBits ( ) ; unsigned ToSz = StVT . getScalarSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( )


<s> bool isS16ImmX4 ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm ( ) ) && ( getImm


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) ) { CanAcceptPredicationCode =


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return LPAC :: encode<ISA_LIT>AluCode ( AluCode ) == LPAC :: ADD && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == AddOffset || MI -> getOperand ( <NUM_LIT> )


<s> int __init_environment ( void * unused __attribute__ ( ( __unused__ ) ) ) { void ( * const * pctor ) ( void ) ; static struct object object ; if ( __register_frame_info ) __register_frame_info ( __EH_FRAME_BEGIN__ , & object ) ; for ( pctor = & __CTOR_END__ - <NUM_LIT> ; pctor > & __CTOR_LIST__ ; -- pctor ) if ( * pctor != NULL ) ( *


<s> void <ISA_LIT>InstPrinter :: printSaveRestore ( const MCInst * MI , raw_ostream & O ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != <NUM_LIT> ) O << <STR_LIT> ; if ( MI -> getOperand ( i ) . isReg ( ) ) printRegName ( O , MI -> getOperand ( i ) . getReg


<s> return emit_insn ( gen_rtx_SET ( VOIDmode , x


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } } if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; return ; } } DEBUG ( dbgs ( ) << <STR_LIT> << RI . getName ( SrcReg ) << <STR_LIT> << RI . getName ( DestReg ) << '\n' ) ; llvm_unreachable (


<s> Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; } SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDNode * VStA = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Opc = QOpcodes1 [ OpcodeIndex ] ; SDNode * VStB = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStB , <NUM_LIT> ) ; ReplaceUses ( SDValue ( N ,


<s> return ( __m128i ) __builtin_ia32_cvttps2dq128_mask ( ( __v4sf ) __A , (


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDXAddr20Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) ,


<s> SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> break ; case V4HImode : unpack_l = gen_unpack2_l ; unpack_h = gen_unpack2_h ; plus = gen_addv2si3 ; break ; default : gcc_unreachable ( ) ; } if ( unsignedp ) x = CONST0_RTX ( mode ) ; else { bool neg ; x = gen_reg_rtx ( mode ) ; neg = ia64_expand_vecint_compare ( LT , mode , x , operands [ <NUM_LIT> ] , CONST0_RTX ( mode ) ) ; gcc_assert ( ! neg ) ; } l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; s = gen_reg_rtx ( wmode


<s> return false ; } if ( CanTailCallOpt ) return lowerTailCall ( MIRBuilder , Info , OutArgs ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( F , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , InArgs , Handler ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) . Options

. GuaranteedTailCallOpt ) ? alignTo ( Handler . StackSize , <NUM_LIT> ) : <NUM_LIT> ;


<s> CurState = EXITS_CLEAN ; } else if ( CurState == PASS_THROUGH ) { BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = I ; CurState = EXITS_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << getBlockExitStateName ( CurState ) << '\n' ) ; if ( CurState == EXITS_DIRTY ) for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; BlockStates [ MBB . getNumber ( ) ] .


<s> assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode (


<s> bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> hasDelaySlot ( ) ) { MachineBasicBlock :: iterator J = I ; ++ FilledSlots ; Changed = true ; BuildMI ( MBB , ++ J , I -> getDebugLoc ( )


<s> assert ( frameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } else { frameSize += <NUM_LIT> ; frameSize = RoundUpToAlignment ( frameSize , <NUM_LIT> ) ; } return


<s> switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( createMemLibcall ( MIRBuilder , MRI , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent


<s> if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> && <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scale = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned IndexReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> ) ; assert ( Scale == <NUM_LIT> ) ; assert ( BaseReg == <STR_LIT> ) ; assert ( IndexReg == <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MatchesSPAdj ( MI ) ) { const MachineOperand & Offset = MI . getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( Offset . getImm ( ) ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; } ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && !

OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> bool hasFastVariablePerLaneShuffle ( ) const { return HasFastVariablePerLaneShuffle


<s> } else { if ( RtMI -> getOpcode ( ) == getMatchingNonSExtOpcode ( RtMI -> getOpcode ( ) ) ) { BitExtMI1 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( ImmsLow ) ; } else { BitExtMI1 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( RtMI ) ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBLow ) . addImm ( ImmsLow ) ; } BitExtMI2 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( Rt2MI ) ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBHigh ) . addImm ( ImmsHigh ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( BitExtMI1 ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( BitExtMI2 ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent ( ) ; return NextI ; } assert ( isPromotableZeroStoreInst ( I ) && <STR_LIT> ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * MergeMI ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) <<


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = a / b


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( ( ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) || DEFAULT_ABI == ABI_ELFv2 ) && type && TYPE_ALIGN ( type ) > <NUM_LIT> ) { bool aggregate_p = ( AGGREGATE_TYPE_P ( type ) && ! SCALAR_FLOAT_MODE_P ( elt_mode ) ) ; if ( aggregate_p != ( mode == BLKmode ) ) { static bool warned ; if ( ! warned && warn_psabi ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , ( int ) TYPE_ALIGN ( type ) / BITS_PER_UNIT ) ; } } if ( aggregate_p )


<s> void <ISA_LIT>InstPrinter :: printSVCROp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned svcrop = MO . getImm ( ) ; const auto * SVCR = <STR_LIT> ( svcrop ) ; assert ( SVCR && <STR_LIT>


<s> rtx_insn * insn = DF_INSN_UID_GET ( insn_uid ) -> insn ; rtx def_set = single_set ( insn ) ; if ( def_set && REG_P ( SET_DEST ( def_set ) ) && ! HARD_REGISTER_P ( SET_DEST ( def_set ) ) ) bitmap_set_bit ( defs , REGNO ( SET_DEST ( def_set ) ) ) ; df_ref ref ; df_ref def ; for ( ref = DF_INSN_UID_DEFS ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! HARD_REGISTER_P ( DF_REF_REG ( ref ) ) ) for ( def = DF_REG_DEF_CHAIN ( DF_REF_REGNO ( ref ) ) ; def ; def = DF_REF_NEXT_REG ( def ) ) analyze_register_chain ( candidates , def ) ; for ( ref = DF_INSN_UID_USES ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if (

! DF_REF_REG_MEM_P ( ref ) ) analyze_register_chain ( candidates , ref ) ;


<s> unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( <STR_LIT> ( Elt ) && ! cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return true ; } return false


<s> bool PicMode = TM . getRelocationModel ( ) == Reloc :: PIC_ ; bool LE = TM . isLittleEndian ( ) ; LLVMContext & Context = M -> getContext ( ) ; std :: string Name = F -> getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; std :: string LocalName = <STR_LIT> + Name ; Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; std :: string AsmText ; if ( PicMode ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += <STR_LIT> + LocalName + <STR_LIT> ; } else AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += swapFPIntParams ( PV , M , LE , false ) ; AsmText += <STR_LIT> ; AsmText += LocalName + <STR_LIT> + Name + <STR_LIT> ; EmitInlineAsm ( Context , BB , AsmText


<s> static MCTargetStreamer * create<ISA_LIT>NullTargetStreamer ( MCStreamer &


<s> break ; case VOIDmode : case QImode : case HImode : case SImode : regbase = GP_ARG_FIRST ; break ; case DImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; case TImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; } if ( * arg_words >= ( unsigned ) MAX_ARGS_IN_REGISTERS ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , struct_p ? <STR_LIT> : <STR_LIT> ) ; ret = <NUM_LIT> ; } else { gcc_assert ( regbase != - <NUM_LIT> ) ; if ( ! type || TREE_CODE ( type ) != RECORD_TYPE || ! named || ! TYPE_SIZE_UNIT ( type ) || ! tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && TREE_CODE ( TREE_TYPE ( field ) ) == REAL_TYPE && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD && tree_fits_shwi_p ( bit_position ( field ) ) && int_bit_position ( field ) % BITS_PER_WORD == <NUM_LIT> ) break ; if ( ! field || mode == DFmode ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { unsigned int chunks ; HOST_WIDE_INT bitpos ; unsigned int regno ; unsigned int i ; chunks = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) / UNITS_PER_WORD ; if ( chunks + * arg_words + bias > ( unsigned ) MAX_ARGS_IN_REGISTERS ) chunks = MAX_ARGS_IN_REGISTERS - * arg_words - bias ; ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( chunks ) ) ; bitpos = <NUM_LIT> ; regno = regbase + * arg_words + bias ; field = TYPE_FIELDS ( type ) ; for ( i = <NUM_LIT> ; i < chunks ;


<s> return ( __m64 ) __builtin_arm_wunpckehsh (


<s> const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return ParseMemory ( Operands ) ; case AsmToken :: LCurly : return ParseRegisterList ( Operands ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal


<s> void emitAssignment ( MCSymbol * S , const MCExpr * Value ) override { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( copyLocalEntry ( Symbol , Value )


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT


<s> if ( CCMI -> getOpcode ( ) != TargetOpcode :: G_ICMP ) return false ; Register LHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! VRegAndVal ) std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! VRegAndVal || VRegAndVal -> Value != <NUM_LIT> ) { MachineIRBuilder MIB ( I ) ; if ( ! emitIntegerCompare ( CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , MIB ) ) return false ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return


<s> static MCSymbol * getPICLabel ( const char * Prefix , unsigned FunctionNumber , unsigned LabelId , MCContext & Ctx ) { MCSymbol * Label = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> +

Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ;


<s> MCDataFragment * Frag = getOrCreateDataFragment ( ) ; Frag -> getFixups ( ) . push_back ( MCFixup :: create ( Frag -> getContents (


<s> bool <ISA_LIT>TTIImpl :: isLegalNTStore ( Type * DataType , unsigned Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < <NUM_LIT> || DataSize > <NUM_LIT> || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == <NUM_LIT> ) return ST -> hasAVX ( ) ; else if ( DataSize == <NUM_LIT> ) return ST -> hasSSE1 ( ) ; return true


<s> if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForcedVEXEncoding !=


<s> if ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ) t = DECL_CONTEXT ( decl ) ; return t


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false


<s> if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * Subtarget . getRegisterInfo ( ) ; LivePhysRegs LiveRegs ( TRI ) ; LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; const MachineRegisterInfo & MRI =


<s> uint8_t BitE = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitF = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD


<s> if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT>


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return Subtarget -> hasSVE ( ) ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ! Subtarget -> useSVEForFixedLengthVectors ( ) ) return false ; if ( VT . getFixedSizeInBits ( ) > Subtarget ->

getMinSVEVectorSizeInBits ( ) ) return false ;


<s> if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , Load . getDebugLoc ( ) , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Call . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Call . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( Call , & Ops [ <NUM_LIT> ] , Ops . size (


<s> case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_DISPATCHSETUP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT (


<s> OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( & * I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) { if ( NewTBB != ( FBB ? FBB : getFallThroughMBB ( & MBB , TBB ) ) ) return true ; BranchCode = <STR_LIT> ; } else return true ; Cond [ <NUM_LIT> ] . setImm ( BranchCode


<s> static unsigned getRegOperandNumElts ( const MCInst * MI , unsigned ScalarSize , unsigned OperandIndex ) { unsigned OpReg = MI -> getOperand ( OperandIndex ) . getReg ( ) ; return getVectorRegSize ( OpReg )


<s> codes [ cost ] . code = UNKNOWN ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = low_part & ~ ( IMM_REACH - <NUM_LIT> ) ; codes [ cost ] . curr_value = codes [ cost ] . value ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - <NUM_LIT> ) ; if ( iorv != <NUM_LIT> ) { codes [ cost ] . code = IOR ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = iorv ; codes [ cost ] . curr_value = low_part ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ <NUM_LIT> ] = { ( value & LU32I_B ) == <NUM_LIT> , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ <NUM_LIT> ] = { ( value & LU52I_B ) == <NUM_LIT> , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( HOST_WIDE_INT_1U << <NUM_LIT> ) ) >> <NUM_LIT> ; int sign51 = ( value & ( HOST_WIDE_INT_1U << <NUM_LIT> ) ) >> <NUM_LIT> ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = value & LU52I_B ; codes [ cost ] . curr_value = value ; return cost + <NUM_LIT> ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( value & LU32I_B ) | ( sign51 ? LU52I_B


<s> Inst . addOperand ( MCOperand :: createImm ( MCE


<s> if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emitNops ( Num


<s> for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return


<s> if ( ! In . isUndef ( ) && cast < ConstantSDNode > ( In ) -> getAPIntValue ( ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; KnownBits Known


<s> static inline unsigned getImm12 ( uint32_t insn


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI


<s> const APInt & ConstValue = C -> getAPIntValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned TrailingZeroes = ConstValue . countTrailingZeros ( ) ; if ( TrailingZeroes ) { if ( N0 -> hasOneUse ( ) && ( isSignExtended ( N0 . getNode ( ) , DAG ) || isZeroExtended ( N0 . getNode ( ) , DAG ) ) ) return SDValue ( ) ; if ( N -> hasOneUse ( ) && ( N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> || N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; } APInt ShiftedConstValue = ConstValue . ashr ( TrailingZeroes ) ; unsigned ShiftAmt , AddSubOpc ; bool ShiftValUseIsN0 = true ; bool NegateResult = false ; if ( ConstValue . isNonNegative ( ) ) { APInt SCVMinus1 = ShiftedConstValue - <NUM_LIT> ; APInt CVPlus1 = ConstValue + <NUM_LIT> ; if ( SCVMinus1 . isPowerOf2 ( ) ) { ShiftAmt = SCVMinus1 . logBase2 ( ) ; AddSubOpc = <STR_LIT> ; } else if ( CVPlus1 . isPowerOf2 ( ) ) { ShiftAmt = CVPlus1 . logBase2 ( ) ; AddSubOpc = <STR_LIT> ; } else return SDValue ( ) ; } else { APInt CVNegPlus1 = - ConstValue + <NUM_LIT> ; APInt CVNegMinus1 = - ConstValue - <NUM_LIT> ; if ( CVNegPlus1 . isPowerOf2 ( ) ) { ShiftAmt = CVNegPlus1 . logBase2 ( ) ; AddSubOpc = <STR_LIT> ; ShiftValUseIsN0 =


<s> APInt ShAmt = N1C -> getAPIntValue ( ) ; Mask = Mask . shl ( ShAmt ) ; if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ; } } if ( auto * N1BV = dyn_cast < BuildVectorSDNode > ( N1 ) ) if ( auto * N1SplatC = N1BV -> getConstantSplatNode ( ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( N1SplatC -> getZExtValue ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; } return SDValue (


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineFunction :: iterator It = BB ; ++ It ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned oldval = dest ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * TRC , * TRCsp ; if ( Size == <NUM_LIT> ) { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } else { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; unsigned scratch = MRI . createVirtualRegister (


<s> const uint16_t * SubReg = TM . getRegisterInfo ( ) -> getSubRegisters ( DstReg ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , * SubReg ) . addReg ( LoReg ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , * ( SubReg + <NUM_LIT> ) ) .


<s> case EQ : case NE : return CCZmode ; case GEU : case GTU : case LTU : case LEU : return CCmode ; case GE : case LT : if ( op1 == const0_rtx ) return CCGOCmode ; else return CCGCmode ; case GT : case LE : if ( op1 == const0_rtx ) return CCNOmode ; else return


<s> inline SDValue getI32Imm ( unsigned Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm , DL ,


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF ::


<s> bool LowOverheadLoop :: RecordVPTBlocks ( MachineInstr * MI ) { if ( isVCTP ( MI ) && VCTP ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } if ( isVCTP ( MI ) ) VCTP = MI ; unsigned VPROpNum = MI -> getNumOperands ( ) - <NUM_LIT> ; bool IsUse = false ; if ( MI -> getOperand ( VPROpNum ) . isReg ( ) && MI -> getOperand ( VPROpNum ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( VPROpNum ) . isUse ( ) ) { if ( ! MI -> getOperand ( VPROpNum - <NUM_LIT> ) . isImm ( ) || MI -> getOperand ( VPROpNum - <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } bool IsDef = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) - <NUM_LIT> ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO .


<s> FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: getRealLinkageName ( ParentFunc -> getName ( ) ) , TheModule ) ; BasicBlock * EntryBB = BasicBlock :: Create


<s> rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ; if ( GET_MODE ( op ) == V4SFmode )


<s> scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; } if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget


<s> bool <ISA_LIT>ConstantIslands :: fixupImmediateBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand (


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> >


<s> break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; full_interleave = true ; break ; default : gcc_unreachable ( ) ; } res_l = expand_simple_binop ( himode , code , op1_l , op2_l , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; res_h = expand_simple_binop ( himode , code , op1_h , op2_h , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( res_l && res_h ) ; d . target = dest ; d . op0 = gen_lowpart ( qimode , res_l ) ; d . op1 = gen_lowpart ( qimode , res_h ) ; d . vmode = qimode ; d . nelt = GET_MODE_NUNITS ( qimode ) ; d . one_operand_p = false ; d . testing_p = false ; if ( full_interleave ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> + ( ( i & <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : ( i & <NUM_LIT> ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; } ok = ix86_expand_vec_perm_const_1 ( & d


<s> unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( ! isUndefOrEqual ( BitI1 ,


<s> static DecodeStatus DecodeGPRMM16RegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Address , const void * Decoder ) {


<s> return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { }

, <NUM_LIT> , false , true , DAG , Subtarget ) ;


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; gcc_assert ( SYMBOL_REF_P ( x ) ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( SYMBOL_REF_P ( x ) ) return


<s> if ( MO . getTargetFlags ( ) & <STR_LIT> ) { auto MOFrag = ( MO . getTargetFlags ( ) & <STR_LIT> ) ; if ( MOFrag == <STR_LIT> || MOFrag == <STR_LIT> || MOFrag == <STR_LIT> || MOFrag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; auto RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind


<s> void <ISA_LIT>AsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LowercaseString ( getRegisterName ( stackReg ) ) ) + <STR_LIT> + Twine ( stackSize ) + <STR_LIT> + Twine (

LowercaseString ( getRegisterName ( returnReg ) ) ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; uint64_t MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign <


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p =


<s> SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IMask


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned ConstraintID = InlineAsm :: getMemoryConstraintID ( MO . getImm ( ) ) ; switch ( ConstraintID ) { case InlineAsm :: Constraint_ZC : { const <ISA_LIT>Subtarget & Subtarget = MO . getParent ( ) -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) ) return


<s> EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( getSTI ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return


<s> unsigned getPartialUpdateClearance (


<s> return __builtin_neon_vrndpv4hf ( __a )


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


uint64x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> float d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a )


<s> static bool hasVPRUse ( MachineInstr & MI ) { return MI . findRegisterUseOperandIdx ( <STR_LIT> )


<s> static void arm_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { cfun -> machine -> uses_anonymous_args = <NUM_LIT> ; if ( cum -> nregs < NUM_ARG_REGS ) * pretend_size =

( NUM_ARG_REGS - cum -> nregs ) * UNITS_PER_WORD ;


<s> return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_N1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm7_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm11_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm16 : case Match_SImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm20_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm26_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo )


<s> for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( )


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return true


<s> std :: tuple < unsigned , SDValue , SDValue > <ISA_LIT>DAGToDAGISel :: findAddrModeSVELoadStore ( SDNode * N , unsigned Opc_rr , unsigned Opc_ri , const SDValue & OldBase , const SDValue & OldOffset , unsigned Scale ) { SDValue NewBase = OldBase ; SDValue NewOffset =


<s> return ( EncVal << <NUM_LIT> ) | ( EncVal


<s> static SDValue LowerF128_FPROUND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return Op ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F64 ) , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F32 ) , <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue ( <NUM_LIT> ,


<s> b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> )


<s> rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ; rws_sum [ regno ] . first_pred