<s> SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) { Mask . push_back ( i


<s> } else { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * LazyPtrHa16 = <ISA_LIT>MCExpr :: CreateHa ( LazyPtrExpr , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( LazyPtrHa16 ) ) ; const MCExpr * LazyPtrLo16 = <ISA_LIT>MCExpr :: CreateLo ( LazyPtrExpr , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( LazyPtrLo16 ) . addExpr ( LazyPtrLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection )


<s> if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT || ! TARGET_FLOAT_RETURNS_IN_80387 ) return <NUM_LIT> ; if ( ( func || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype ,


<s> return ( unsigned ) __builtin_ia32_vcvtss2usi32 ( ( __v4sf )


<s> static void mips_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( TARGET_MIPS16 ) sorry ( <STR_LIT> ) ; if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r3 , plus_constant ( Pmode ,


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options )


<s> OperandMatchResultTy parseGR128 ( OperandVector & Operands


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass

( create<ISA_LIT>Os16Pass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf ; save_fp = INTVAL ( En4 ) & <NUM_LIT> ; save_gp = INTVAL ( En4 ) & <NUM_LIT> ; save_lp = INTVAL ( En4 ) & <NUM_LIT> ; extra_count = <NUM_LIT> ; if ( save_fp ) extra_count ++ ; if ( save_gp ) extra_count ++ ; if ( save_lp ) extra_count ++ ; if ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM ) num_use_regs = extra_count ; else num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + <NUM_LIT> + extra_count ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + <NUM_LIT> ) ) ; par_index = <NUM_LIT> ; offset = - ( num_use_regs * <NUM_LIT> ) ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { if ( regno == SP_REGNUM ) break ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if ( save_fp ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if ( save_gp ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || SrcVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; if ( NumElts < <NUM_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG

. getConstantFP ( <NUM_LIT> , dl , SrcVT ) ) ;


<s> if ( crtl -> drap_reg ) drap = REGNO ( crtl -> drap_reg ) ; else drap = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( i != drap && ! df_regs_ever_live_p ( i ) ) return i ; } return INVALID_REGNUM


<s> PM -> add ( create<ISA_LIT>ISelDag (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: encodeMatrixIndexGPR32 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup >

& Fixups , const MCSubtargetInfo & STI ) const {


<s> unsigned NumGPRs ; if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { unsigned RBegin , REnd ; CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; ArgRegsSize = NumGPRs * <NUM_LIT> ; if ( NumGPRs && Align > <NUM_LIT> && ( ArgRegsSize < ArgSize || InRegsParamRecordIdx >= CCInfo . getInRegsParamsCount


<s> case CallingConv :: GHC : return CC ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2 ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv


<s> break ; case <STR_LIT> : if ( ! ST . hasP8Vector ( ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! ST . hasP9Vector ( ) ) return false ; break ; default : return false ; } SDValue LoadedVal ( N , <NUM_LIT> ) ; if ( ! LoadedVal . hasOneUse ( ) ) return false ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI . getUse ( ) . get ( ) . getResNo ( ) == <NUM_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) return false ; return


<s> return decodeUImmOperand < <NUM_LIT> >


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_reg256_found = false


<s> case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ; } } switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShOps [ <NUM_LIT> ] , <NUM_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , VT , ShAmt ) ; return DAG . getNode ( Opc , dl , VT ,


<s> static MCStreamer * create<ISA_LIT>MachOStreamer ( MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream

& OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll , bool DWARFMustBeAtTheEnd ) {


<s> return ( __m128 ) __builtin_ia32_cmpnleps ( ( __v4sf ) __A , (


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>64 ) ; const unsigned ArgArea = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgArea ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . isExtInLoc ( ) ) Offset += <NUM_LIT>


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { Register NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 )


<s> if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else { rtx sum = XEXP ( op , <NUM_LIT> ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , <NUM_LIT> ) ) ; if ( summand < <NUM_LIT> || summand > g_switch_value ) return <NUM_LIT> ; sym_ref = XEXP ( sum , <NUM_LIT> ) ; } return SYMBOL_REF_SMALL_P ( sym_ref


<s> if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx ; return


<s> void addMRSSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; bool


<s> if ( ! TARGET_USE_GOT || cfun -> machine -> global_pointer == INVALID_REGNUM || mips_must_initialize_gp_p ( ) ) return false ; if ( ! mips_has_long_branch_p ( ) ) return false ; cfun -> machine -> must_initialize_gp_p = true ; split_all_insns_noflow (


<s> SMLoc E = Tok . getLoc ( ) ; int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) Val = INT32_MIN ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , E ) ) ; return MatchOperand_Success ; } bool haveEaten = false ; bool isAdd = true ; int Reg = - <NUM_LIT> ; if ( Tok . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; haveEaten = true ; } else if ( Tok . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; isAdd = false ; haveEaten = true ; } if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { if ( ! haveEaten ) return MatchOperand_NoMatch ; Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePostIdxReg ( Reg , isAdd , <STR_LIT> , <NUM_LIT> , S , E ) ) ; return MatchOperand_Success


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode (

) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> return ( ( qword ) ( vec_mulo ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT>


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , withTargetFlags ( Op , LoTF , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Hi


<s> AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl


<s> bool mips_must_initialize_gp_p ( void ) { return cfun -> machine -> must_initialize_gp_p


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 , DAG . getNode ( <STR_LIT> , DL , VT , N0 , N1 ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N1 , N0 ) , N0 ) ; } <STR_LIT> CC ; switch ( Opcode ) { case <STR_LIT> : CC = <STR_LIT> :: SETLT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETGT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETULT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETUGT ; break ; default : llvm_unreachable (


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack

( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> return ( ( vec_uchar16 ) ( si_cntb ( ( qword ) ( a


<s> SDLoc SL ( N ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> ) ; EVT LdType = N -> getValueType ( <NUM_LIT> ) ; unsigned ImmSum = <NUM_LIT> ; uint16_t MathOpc = ( Inc ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { SDValue Val = N -> getOperand ( i ) ; Ptr = CurDAG -> getNode ( MathOpc , SL , VTList , Ptr , Offset ) ; ImmSum += <NUM_LIT> ; Value * NullPtr = <NUM_LIT> ; MachineMemOperand * MMO = new MachineMemOperand ( MachinePointerInfo ( NullPtr , ImmSum ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; UsePtr = ( B ) ? PrevPtr : Ptr ; SDValue ResNode ; if ( Ld ) { if ( Val -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { Chain = Val -> getOperand ( <NUM_LIT> ) ; } RegisterSDNode * RegNode = dyn_cast < RegisterSDNode > ( Val -> getOperand ( <NUM_LIT> ) ) ; const MCRegisterInfo * RI = Dec -> getDisassembler ( ) -> getMCDirector ( ) -> getMCRegisterInfo ( ) ; if ( RI -> isSubRegisterEq ( RI -> getProgramCounter ( ) , RegNode -> getReg ( ) ) ) { ResNode = CurDAG -> getNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRoot ( ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Chain ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Ptr ) ; CurDAG -> setRoot ( ResNode ) ; return ; } else { ResNode = CurDAG -> getLoad ( LdType , SL , Chain , UsePtr , MachinePointerInfo :: getConstantPool ( ) , false , false , true , <NUM_LIT> ) ; SDValue C2R = CurDAG -> getCopyToReg ( ResNode . getValue ( <NUM_LIT> ) , SL , RegNode -> getReg ( ) , ResNode ) ; Chain = C2R ; if ( Val -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { CurDAG -> ReplaceAllUsesOfValueWith ( Val , ResNode ) ; CurDAG -> ReplaceAllUsesOfValueWith ( Val . getValue ( <NUM_LIT> )


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective =


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCRetInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val


<s> static DecodeStatus DecodeBitfieldMaskOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned msb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) { Check ( S , MCDisassembler :: SoftFail ) ; lsb = msb ; } uint32_t msb_mask = <NUM_LIT>


<s> static inline uint8_t encodeAdvSIMDModImmType5 (


<s> void addMemRegOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> :

<STR_LIT> , Memory . ShiftImm , Memory . ShiftType ) ;


<s> else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasV6Ops ( ) ) return <NUM_LIT> ; if ( isZExt ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isZExt ) { Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; isBoolZext = true ; break ; } return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; if ( isBoolZext ) MIB . addImm (


<s> unsigned NumOfElm = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [


<s> O << <STR_LIT> << TRI -> getAsmName ( MI -> getOperand ( OpNum ) . getReg


<s> void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeItem :: TextAttribute ; Item -> StringValue = std :: string ( Value


<s> auto Imm = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( Imm !=


<s> assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg ,


<s> return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT> : return HasV8MBaselineOps ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> int ix86_mode_needed ( int entity , rtx insn ) { enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < <NUM_LIT> ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return mode ; break ; case I387_FLOOR : if ( mode == I387_CW_FLOOR ) return mode ; break ; case


<s> bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; assert ( ( isT2 || MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; int OffImm = getMemoryOpOffset ( * MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) . cloneMemRefs ( * MI ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) . cloneMemRefs ( * MI ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool <STR_LIT> ( unsigned v ) { if ( v == <NUM_LIT> ) return false ; return isShiftedMask_32 ( ~ v


<s> } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ idx ] . getFrameIdx ( ) << <STR_LIT> << CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == <NUM_LIT> ) ? - Count : i ; assert ( ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( StrOpc == <STR_LIT> || StrOpc == <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MBB . addLiveIn ( Reg1 ) ; MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } return true


<s> Type * RetTy = RetVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; bool SignExtend = shouldSignExtendTypeInLibCall ( RetVT , IsSigned ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallConv , RetTy , Callee , std :: move ( Args ) ) . setNoReturn ( DoesNotReturn ) . setDiscardResult ( ! IsReturnValueUsed ) . setSExtResult

( SignExtend ) . setZExtResult ( ! SignExtend ) ;


<s> bool hasMP1E2 ( ) const { return HasMP1E2


<s> void <ISA_LIT>FrameInfo :: getInitialFrameState ( std :: vector < MachineMove > & Moves ) const { MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT>


<s> bool Reg1IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI . getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MB == <NUM_LIT> && ME == <NUM_LIT> ) return nullptr ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI . getDebugLoc ( ) , MI . getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI . getOperand ( <NUM_LIT> ) . setReg


<s> const MCDisassembler * Dis = static_cast < const


<s> SDValue <ISA_LIT>TargetLowering :: combineSHL ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( auto Value = stripModuloOnShift ( * this , N , DCI . DAG ) ) return Value ; return SDValue (


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getMcpu ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI


<s> <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val


<s> if ( TheTriple . isOSDarwin ( ) ) return isEH ? DWARFFlavour :: <ISA_LIT>_32_DarwinEH : DWARFFlavour :: <ISA_LIT>_32_Generic ; if ( TheTriple . getOS ( ) == Triple :: MinGW32 || TheTriple . getOS ( ) == Triple :: Cygwin ) return DWARFFlavour :: <ISA_LIT>_32_Generic ; return DWARFFlavour :: <ISA_LIT>_32_Generic


<s> bool <ISA_LIT>TargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL ,


<s> if ( ! NumZeros ) { isLeft = false ; NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , false , DAG ) ; if ( ! NumZeros ) return false ; } bool SeenV1 = false ; bool SeenV2 = false ; for ( unsigned i = NumZeros ; i < NumElems ; ++ i ) { unsigned Val = isLeft ? ( i - NumZeros ) : i ; int Idx_ = SVOp -> getMaskElt ( isLeft ? i : ( i - NumZeros ) ) ; if ( Idx_ < <NUM_LIT> ) continue ; unsigned Idx = ( unsigned ) Idx_ ; if ( Idx < NumElems ) SeenV1 = true ; else { Idx -= NumElems ; SeenV2 = true ; } if ( Idx != Val ) return false ; } if ( SeenV1 && SeenV2 ) return false ; ShVal = SeenV1 ? SVOp -> getOperand ( <NUM_LIT>


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Nand = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; SDValue And = notValue ( DAG , DL , VT , Nand ) ; return And


<s> assert ( LdNode && LdNode -> getOffset ( ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , <NUM_LIT> ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo


<s> bool <ISA_LIT>ConstantIslands :: mayOptimizeThumb2Instruction ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; unsigned CurOp = <STR_LIT> ( Desc ) ; unsigned CurByte =


<s> for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) { ++ I


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> :


<s> if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee


<s> if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ; } } } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [


<s> for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return


<s> SDNode * ABDNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue NewABD = tryCombineLongOpWithDup ( <STR_LIT> , ABDNode , DCI , DAG ) ; if ( ! NewABD . getNode ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , NewABD ) ; } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getScalarSizeInBits ( ) ; ElementCount SrcEC = SrcVT . getVectorElementCount ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , SrcEC ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo ,


<s> O << A64CondCodeToString ( static_cast < <STR_LIT> > ( MO . getImm ( )


<s> unsigned int mips_case_values_threshold ( void ) { if ( TARGET_MIPS16 &&


<s> poly_int64 per_register_size = GET_MODE_SIZE ( mode ) ; unsigned int nregs = hard_regno_nregs ( regno , mode ) ; if ( nregs > <NUM_LIT> ) per_register_size = exact_div ( per_register_size , nregs ) ; if ( abi_id == ARM_PCS_SIMD || abi_id == ARM_PCS_TLSDESC ) return maybe_gt ( per_register_size , <NUM_LIT> ) ; return maybe_gt ( per_register_size ,


<s> MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; auto ExpandVMOVCopies = [ this ] ( SmallPtrSet < MachineInstr * , <NUM_LIT> > & VMOVCopies ) { for ( auto * MI : VMOVCopies ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto MIB1 = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> + ( Dst - <STR_LIT> ) * <NUM_LIT> ) . addReg ( <STR_LIT> + ( Src - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; ( void ) MIB1 ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB1 ) ; auto MIB2 = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> + ( Dst - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . addReg ( <STR_LIT> + ( Src - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB2 ) ; ( void ) MIB2 ; MI -> eraseFromParent ( ) ; } } ; if ( LoLoop . Revert ) { if ( isWhileLoopStart ( * LoLoop . Start ) ) RevertWhile ( LoLoop . Start ) ; else RevertDo ( LoLoop . Start ) ; if ( LoLoop . Dec == LoLoop . End ) RevertLoopEndDec ( LoLoop . End ) ; else RevertLoopEnd ( LoLoop . End , RevertLoopDec ( LoLoop . Dec ) ) ; } else { ExpandVMOVCopies ( LoLoop . VMOVCopies ) ; LoLoop . Start = ExpandLoopStart ( LoLoop


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { DebugLoc dl = N -> getDebugLoc ( ) ; switch ( N -> getOpcode ( ) ) { default : assert ( false && <STR_LIT> ) ; return ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; std :: vector < EVT > NodeTys ; SDValue Ops [ <NUM_LIT> ] , Result , MFFSreg , InFlag , FPreg ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; MFFSreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Lo ; Ops [ <NUM_LIT> ] = Hi ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] =


<s> for ( int i = <NUM_LIT> ; i != Size ; ++ i ) if ( BlendMask & ( <NUM_LIT> << i ) ) ScaledMask |= ( ( <NUM_LIT> <<

Scale ) - <NUM_LIT> ) << ( i * Scale ) ;


<s> unsigned M = MatchInstructionImpl ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfo ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : UnsizedMemOp -> getLocRange ( ) ; return Error ( UnsizedMemOp -> getStartLoc ( ) , <STR_LIT> + Mnemonic + <STR_LIT> ,


<s> EVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG )


<s> unsigned <ISA_LIT>ABIInfo :: GetGPRMoveOp ( ) const { return ArePtrs64bit ( )


<s> assert ( Kind == k_Barrier && <STR_LIT> ) ; return Barrier .


<s> getExprForDwarfGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res ,


<s> bool Split = false ; MVT ConstVecVT = VT ; unsigned NumElts = VT . getVectorNumElements ( ) ; bool In64BitMode = DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ; if ( ! In64BitMode && VT . getVectorElementType ( ) == <STR_LIT> ) { ConstVecVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Split = true ; } MVT EltVT = ConstVecVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { bool IsUndef = Values [ i ] <


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( T , TT ) ; MachineLocation Dst ( MachineLocation :: VirtualFP


<s> for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { MachineInstr & MI = * I ; uint64_t Flags = MI . getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI . isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI . isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI . isImplicitDef ( ) && <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( MI . isCall ( ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = nullptr ; if ( I != BB . begin ( ) ) PrevMI = & * std :: prev ( I ) ; ++ NumFP ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( { MachineBasicBlock :: iterator PrevI


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout

* Layout , const MCFixup * Fixup ) const {


<s> std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) || STI . useSoftFloat ( ) ) TS . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) TS


<s> if ( GET_CODE ( XEXP ( addr2 , <NUM_LIT> ) ) != REG ) return <NUM_LIT> ; else { reg2 = REGNO ( XEXP ( addr2 , <NUM_LIT> ) ) ; if ( GET_CODE ( XEXP ( addr2 , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; offset2 = INTVAL ( XEXP ( addr2 , <NUM_LIT> ) ) ; } } else if ( GET_CODE ( addr2 ) != REG ) return <NUM_LIT> ; else { reg2 = REGNO ( addr2 ) ; offset2 = <NUM_LIT> ; } if ( reg1 != reg2 ) return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > (


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( Opc ) return DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; Opc = Unsigned ? <STR_LIT> : <STR_LIT>


<s> if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , Ty , DAG ) ; return getAddrNonPIC ( N , Ty , DAG ) ; } return getAddrLocal ( N , Ty , DAG , Subtarget .

isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isLikeA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode (


<s> AlignmentIsInBytes = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; LabelSuffix = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective =


<s> case CallingConv :: Tail : case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI : return isTargetWin64 ( ) ; case CallingConv :: Win64 : return true ; case CallingConv :: <ISA_LIT>_64_SysV


<s> MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( ! Subtarget . isThumb ( )


<s> SDLoc DL ( N ) ; if ( CMP0 . getOpcode ( ) != <STR_LIT> || CMP0 != CMP1 ) return SDValue ( ) ; SDValue CMP00 = CMP0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP01 = CMP0 -> getOperand ( <NUM_LIT> ) ; EVT VT = CMP00 . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { bool ExpectingFlags = false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ! ExpectingFlags && UI != UE ; ++ UI ) switch ( UI -> getOpcode ( ) ) { default : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ExpectingFlags = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT ,


<s> bool hasResetReferenceBitsMultiple ( ) const { return HasResetReferenceBitsMultiple


<s> Inst . addOperand ( MCOperand :: CreateImm


<s> return ( __m256 ) __builtin_ia32_permvarsf256 ( ( __v8sf )


<s> int lastpos = pos - <NUM_LIT> ; while ( lastpos < LINELEN - <NUM_LIT> && isdigit ( linebuf [ lastpos + <NUM_LIT> ] ) ) ++ lastpos ; if ( lastpos >= LINELEN - <NUM_LIT> ) { diag ( lastpos , <STR_LIT> ) ; exit ( <NUM_LIT> ) ; } if ( lastpos < pos


<s> printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } O << '[' ; if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; } else { assert ( DispSpec . isExpr ( ) &&


<s> for ( auto * MI : Killed ) BasicBlocks . insert ( MI -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; RDA -> getReachingLocalUses ( & MI , <STR_LIT> , ITBlocks [ & MI ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; for ( auto * MI : Killed ) { if ( MachineOperand * MO = MI -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA -> getMIOperand ( MI , * MO ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( MI ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ModifiedITs . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * MI : Killed ) dbgs ( ) << <STR_LIT> << * MI ) ; LoLoop . ToRemove . insert ( Killed . begin ( )


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum


<s> if ( gbr_disp . is_reg ( ) && REGNO ( gbr_disp . reg ( ) ) == GBR_REG ) { for ( df_ref d = DF_REG_DEF_CHAIN ( GBR_REG ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( TEST_HARD_REG_BIT ( regs_invalidated_by_call , GBR_REG


<s> if ( mode == DImode && ne == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && nb == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && GET_CODE ( operands [ <NUM_LIT> ] ) != LSHIFTRT && CONST_INT_P ( operands [ <NUM_LIT> ] ) && ne == INTVAL ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( nb < <NUM_LIT> && ne < <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT>


<s> if ( Imm >= <NUM_LIT> ) { VMX = VMXu ; Imm -= <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addReg ( Src , getKillRegState ( KillSrc ) ) ; break ; case <STR_LIT> : BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addImm ( MImm ) ; break ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addReg ( Src , getKillRegState ( KillSrc ) ) . addReg ( VMX ) ; break ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addImm ( MImm ) . addReg ( VMX ) ; break ; } MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register VMZu = getVM512Upper ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register VMZl = getVM512Lower ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; bool KillSrc = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register VMZ = VMZl ; if ( Imm >= <NUM_LIT> ) { VMZ = VMZu ; Imm -= <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , Dest ) . addReg ( VMZ ) . addImm ( Imm ) ; MachineInstr * Inst = MIB . getInstr ( ) ; MI . eraseFromParent ( ) ; if ( KillSrc ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; Inst -> addRegisterKilled ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , TRI , true ) ; } return true ; } case <STR_LIT> : case <STR_LIT>


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { case <STR_LIT> : case <STR_LIT>


<s> return ( __m256 ) __builtin_ia32_vpermilvarps256 ( ( __v8sf ) __A , ( __v8si )


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoReorder ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc


<s> HANDLE mmap_handle ; char * object_name = NULL ; OSVERSIONINFO version_info ; int r ; version_info . dwOSVersionInfoSize = sizeof ( version_info ) ; if ( size == <NUM_LIT> ) return <NUM_LIT> ; if ( ( offset & ( va_granularity - <NUM_LIT> ) ) != <NUM_LIT> || size > pch_VA_max_size ) return - <NUM_LIT> ; GetVersionEx ( & version_info ) ; char local_object_name [ sizeof ( OBJECT_NAME_FMT ) + sizeof ( DWORD ) * <NUM_LIT> ] ; if ( version_info . dwMajorVersion > <NUM_LIT> ) { snprintf ( local_object_name , sizeof ( local_object_name ) , OBJECT_NAME_FMT <STR_LIT> , GetCurrentProcessId ( ) ) ; object_name = local_object_name ; } mmap_handle = CreateFileMappingA ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , <NUM_LIT> , <NUM_LIT> , object_name ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , <STR_LIT> ) ; return - <NUM_LIT> ; } for ( r = <NUM_LIT> ; r < <NUM_LIT> ; r ++ ) { mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , <NUM_LIT> , offset


<s> DebugLoc dl = Loc -> getDebugLoc ( ) ; unsigned PReg = Loc -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PRegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( PReg ) ; bool isKill = Loc -> getOperand ( <NUM_LIT> ) . isKill ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; Regs . push_back ( std :: make_pair ( PReg , isKill ) ) ; for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; unsigned Reg = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; isKill = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( NewOffset == Offset + ( int ) Size && ( ( isAM4 && RegNum > PRegNum ) || RegNum == PRegNum + <NUM_LIT> ) ) { Offset += Size ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; PRegNum = RegNum ; } else { if ( MergeOps ( MBB , ++ Loc , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) { Merges . push_back ( prior ( Loc ) ) ; for ( unsigned j = SIndex ; j < i ; ++ j ) { MBB . erase ( MemOps [ j ] . MBBI ) ; MemOps [ j ] . Merged = true ; } } MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > Pos ) { Pos = MemOps [ i ] . Position ; Loc = MemOps [ i ] . MBBI ; } } bool BaseKill = Loc -> findRegisterUseOperandIdx ( Base , true ) != - <NUM_LIT> ; if ( MergeOps ( MBB , ++ Loc , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) { Merges . push_back ( prior ( Loc ) ) ; for ( unsigned i = SIndex , e = MemOps . size ( ) ; i != e ; ++ i ) { MBB . erase ( MemOps [ i ] . MBBI


<s> rtl_opt_pass * make_pass_track_speculation ( gcc :: context * ctxt ) { return new pass_track_speculation ( ctxt


<s> if ( ! GA ) return false ; Optional < ConstantRange > CR = GA -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR ) return Width == <NUM_LIT> && TM . getCodeModel ( ) == CodeModel :: Small ; return CR -> getSignedMin ( ) . sge ( - <NUM_LIT> << Width ) && CR -> getSignedMax ( )


<s> if ( I -> isTerminator ( ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( std :: next ( I ) == E ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( ( I -> isBranch ( ) && ! ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> || I ->


<s> void <ISA_LIT>TargetLowering :: initVPUActions ( ) { for ( MVT LegalVecVT : AllVectorVTs ) { setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT ,


<s> case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && ( N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> return ( uint32x2_t ) __builtin_aarch64_uhaddv2si ( ( int32x2_t ) __a , (


<s> TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * TargetBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand


<s> return ( __m256i ) __builtin_ia32_punpckldq256_mask ( ( __v8si ) __A , ( __v8si ) __B , (


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val


<s> Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = <NUM_LIT> ; break ; case MCK_1 : ImmVal = <NUM_LIT> ; break ; case MCK_2 : ImmVal = <NUM_LIT> ; break ; case MCK_3 : ImmVal = <NUM_LIT> ; break ; default :


<s> TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale


<s> case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! Check ( S , DecodeBFLabelOperand < false , true , true , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Address , Decoder ) ) || ! Check ( S , DecodeBFLabelOperand < false , false , true , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { uint32_t CanonicalLCTP = <NUM_LIT> , SBZMask = <NUM_LIT> ; if ( ( Insn & ~ SBZMask ) != CanonicalLCTP ) return MCDisassembler :: Fail ; if ( Insn != CanonicalLCTP ) Check ( S ,


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , Subtarget . isABI_N32 ( ) ||


<s> for ( auto & Elem : Vec . Parts ) MatchingElements &= ( Elem ==


<s> return __builtin_mve_vcmpcsq_n_v16qi ( __a ,


<s> bool hasProcessorAssist ( ) const { return


<s> return is<ISA_LIT>64 ( ) && hasPCRelativeMemops ( ) && isELFv2ABI ( ) && CodeModel :: Medium == getTargetMachine ( ) .


<s> for ( int op_num = d -> op_count - <NUM_LIT> ; op_num >= <NUM_LIT> ; op_num -- ) { machine_mode op_mode = d -> op_modes [ op_num ] ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ op_num ] ; tree eltype = aarch64_simd_builtin_type ( op_mode , qualifiers ) ; if ( op_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } tree ftype = build_function_type ( return_type , args ) ; tree attrs = aarch64_get_attributes ( FLAG_AUTO_FP , d -> op_modes


<s> bool <ISA_LIT>FrameLowering :: needsFrameIndexResolution ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasStackObjects ( ) || MF

. getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


<s> if ( DisableForwardSearch || ! Slot -> isCall ( ) ) return false ; RegDefsUses RegDU ( TM ) ; NoMemInstr NM ; Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Filler , Slot ) ) return false ; MBB . splice ( std :: next ( Slot


<s> return ( getExtendEncoding ( ET ) << <NUM_LIT> ) | unsigned


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegName ( RegShiftedReg . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegName ( RegShiftedReg . ShiftReg ) << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegName ( RegShiftedImm . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_ConstantPoolImmediate : OS << <STR_LIT> << * getConstantPoolImm ( ) ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << RegName ( * I ) ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ; } case k_VectorList : OS << <STR_LIT> << VectorList . Count << <STR_LIT> << RegName ( VectorList . RegNum ) << <STR_LIT> ; break ; case


<s> return ( int8x16_t ) __builtin_aarch64_srshlv16qi ( __a ,


<s> unsigned int regno ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_MMX_REG ; else if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT>


<s> static bool BBIsJumpedOver ( MachineBasicBlock * MBB ) { if ( MBB -> pred_size ( ) != <NUM_LIT> || MBB -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * Succ = * MBB


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; assert ( IdxMode != <STR_LIT> &&


<s> <ISA_LIT>_64RelType Type = getType64 ( Fixup . getKind ( ) , Modifier , IsPCRel ) ; if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Ctx , Fixup . getLoc ( ) , Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ; return getRelocType32 ( Modifier , getType32 (


<s> int value = INTVAL ( operands [ <NUM_LIT> ] ) ; int max , i ; value = value & <NUM_LIT> ; if ( value == <NUM_LIT> ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movt ( operands [ <NUM_LIT> ] , get_t_reg_rtx ( ) ) ) ; return ; } else if ( code == ASHIFT ) { if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) { emit_insn ( gen_andsi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return ; } } } else if ( value ==


<s> { <STR_LIT> , rs6000_d_handle_target_float_abi } , { <STR_LIT> , rs6000_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers


<s> bool hasThumb ( ) const { return STI . getFeatureBits (


<s> static SDValue performMULCombine ( SDNode * N , SelectionDAG & DAG , const TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>SETargetLowering * TL ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) ) return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) ,

VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ;


<s> if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; updateValueMap ( I , Result ) ; return true


<s> static <ISA_LIT>Operand * MorphToMEMrr ( unsigned Base , <ISA_LIT>Operand * Op ) { unsigned offsetReg = Op -> getReg ( ) ; Op -> Kind = k_MemoryReg ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = offsetReg ; Op -> Mem . Off


<s> static const char * stripRegisterPrefix ( const char * RegName ) { switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f'


<s> mips_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src ,


<s> for ( auto & MI : Successor -> instrs ( ) ) { if ( ! MI . isPHI ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) + <NUM_LIT> ; i != e ; i += <NUM_LIT> ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . getMBB ( ) == OrigMBB ) { if ( MI . getOperand ( i - <NUM_LIT> ) . isReg ( ) ) { MachineInstr * DefMI = MRI -> getVRegDef ( MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ) ; if ( DefMI -> getParent ( ) == NewMBB ||

! OrigMBB -> isSuccessor ( Successor ) ) {


<s> ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } } if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; GEPs . push_back ( V ) ; if ( const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( U -> getOperand ( <NUM_LIT> ) ) ) { V = GEP ; goto redo_gep ; } else if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) { return true ; } AM = SavedAM ; for ( SmallVectorImpl < const Value * > :: reverse_iterator I = GEPs . rbegin ( ) , E = GEPs . rend ( ) ; I != E ; ++ I ) if ( handleConstantAddresses ( * I , AM ) ) return true ; return false ; unsupported_gep : break ; } } return handleConstantAddresses ( V , AM


<s> if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Size ) ; if ( ! ParseRegister ( SegReg , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Size ) ; } const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getParser ( ) . getContext ( ) ) ; if ( getParser ( ) . ParseExpression ( Disp ,


<s> return ( __m64 ) __builtin_ia32_paddw ( ( __v4hi


<s> MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = Mang -> getSymbol ( GV ) ; } } else { SymToPrint = Mang -> getSymbol


<s> return ( __m512i ) __builtin_ia32_cvttpd2uqq512_mask ( ( __v8df ) __A , ( __v8di )


<s> <STR_LIT> Pred = getInstrPredicate ( First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; } else { EarliestI = std :: prev ( EarliestI ) ; } for ( MachineInstr * MI : Cand . Instrs ) MBB . erase ( MI ) ; if ( EarliestAtBegin ) EarliestI = MBB . begin ( ) ; else EarliestI = std :: next ( EarliestI ) ; auto FixupRange = make_range ( EarliestI , iterator ( Merged ) ) ; if ( isLoadSingle ( Opcode ) ) { for ( MachineInstr & MI : FixupRange ) { for ( unsigned & ImpDefReg : ImpDefs ) { for ( MachineOperand & MO : MI . implicit_operands ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != ImpDefReg ) continue ; if ( MO . readsReg ( ) ) MO . setIsUndef ( ) ; else if ( MO . isDef ( ) ) ImpDefReg = <NUM_LIT> ; } } } MachineInstrBuilder MIB ( * Merged -> getParent ( ) -> getParent ( ) , Merged ) ; for ( unsigned ImpDef : ImpDefs ) MIB . addReg ( ImpDef , RegState :: ImplicitDefine ) ; } else { assert ( isi32Store ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; for ( MachineInstr & MI : FixupRange ) { for ( MachineOperand & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . isKill ( ) ) continue ; if ( KilledRegs . count ( MO . getReg ( ) ) ) MO . setIsKill ( false ) ; } } assert ( ImpDefs . empty ( ) ) ; } return


<s> mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) PROMOTE_FUNCTION_MODE ( mode , unsignedp , type ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != <NUM_LIT>


<s> if ( ( GET_CODE ( x ) == PRE_MODIFY && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == REG && REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) && ( ! strict || REGNO ( x ) < FIRST_PSEUDO_REGISTER ) ) return <NUM_LIT> ; if ( xstormy16_below100_symbol ( x , mode ) ) return


<s> getParser ( ) . getStreamer ( ) . EmitThumbFunc


<s> void mips_expand_vec_cond_expr ( machine_mode mode , machine_mode vimode , rtx * operands ) { rtx cond = operands [ <NUM_LIT> ] ; rtx cmp_op0 = operands [ <NUM_LIT> ] ; rtx cmp_op1 = operands [ <NUM_LIT> ] ; rtx cmp_res = gen_reg_rtx ( vimode ) ; mips_expand_msa_cmp ( cmp_res , GET_CODE ( cond ) , cmp_op0 , cmp_op1 ) ; if ( operands [ <NUM_LIT> ] == CONSTM1_RTX ( vimode ) && operands [ <NUM_LIT> ] == CONST0_RTX ( vimode ) ) emit_move_insn ( operands [ <NUM_LIT> ] , cmp_res ) ; else { rtx src1 = gen_reg_rtx ( vimode ) ; rtx src2 = gen_reg_rtx ( vimode ) ; rtx mask = gen_reg_rtx ( vimode ) ; rtx bsel ; emit_move_insn ( mask , cmp_res ) ; if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop1 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop1 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop1 , gen_rtx_SUBREG ( vimode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; } emit_move_insn ( src1 , xop1 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONSTM1_RTX ( vimode ) ) ; emit_move_insn ( src1 , mask ) ; } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop2 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_rtx_SUBREG ( vimode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 ,


<s> if ( valid && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SImode ) ) valid = UBYTE_INT ( offset + GET_MODE_SIZE ( mode )


<s> unsigned <ISA_LIT>AsmParser :: getGPR ( int RegNo ) { return getReg ( isGP64bit ( ) ? <STR_LIT> : <STR_LIT> , RegNo


<s> void ia64_expand_unpack ( rtx operands [ <NUM_LIT> ] , bool unsignedp , bool


<s> enum machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = <NUM_LIT> ; if ( REG_P ( op ) ) { if ( FP_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) + <NUM_LIT> : REGNO ( op ) ) ; if ( ACC_HI_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) : REGNO ( op ) + <NUM_LIT> ) ; } if ( MEM_P ( op ) ) return mips_rewrite_small_data (

adjust_address ( op , word_mode , byte ) ) ;


<s> unsigned NumArgs = Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ; if ( ! NumArgs ) return false ; return cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getArgFlags (


<s> return ( uint32x2_t ) __builtin_neon_vqmovunv2di (


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveR19R20X (


<s> if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( create<ISA_LIT>CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass (

create<ISA_LIT>StorePairSuppressPass ( ) ) ;


<s> void <ISA_LIT>CodeEmitter :: emitConstPoolAddress ( unsigned CPI , unsigned Reloc ) { MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI , <NUM_LIT>


<s> static SDValue matchPMADDWD ( SelectionDAG & DAG , SDValue Op0 , SDValue Op1 , const SDLoc & DL , EVT VT , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || VT . getVectorNumElements ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; SDValue Mul ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; i += <NUM_LIT> ) { SDValue Op0L = Op0 -> getOperand ( i ) , Op1L = Op1 -> getOperand ( i ) , Op0H = Op0 -> getOperand ( i + <NUM_LIT> ) , Op1H = Op1 -> getOperand ( i + <NUM_LIT> ) ; if ( Op0L . getOpcode ( ) != <STR_LIT> || Op1L . getOpcode ( ) != <STR_LIT> || Op0H . getOpcode ( ) != <STR_LIT> || Op1H . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * Const0L = dyn_cast < ConstantSDNode > ( Op0L -> getOperand ( <NUM_LIT> ) ) ; auto * Const1L = dyn_cast < ConstantSDNode > ( Op1L -> getOperand ( <NUM_LIT> ) ) ; auto * Const0H = dyn_cast < ConstantSDNode > ( Op0H -> getOperand ( <NUM_LIT> ) ) ; auto * Const1H = dyn_cast < ConstantSDNode > ( Op1H -> getOperand ( <NUM_LIT> ) ) ; if ( ! Const0L || ! Const1L || ! Const0H || ! Const1H ) return SDValue ( ) ; unsigned Idx0L = Const0L -> getZExtValue ( ) , Idx1L = Const1L -> getZExtValue ( ) , Idx0H =

Const0H -> getZExtValue ( ) , Idx1H = Const1H -> getZExtValue ( ) ;


<s> int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> &&


<s> MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; BlockInfo . insert ( BlockInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; computeBlockSize ( * OrigBB ) ; computeBlockSize ( * NewBB ) ; adjustBlockOffsets ( * OrigBB ) ; ++ NumSplit ; return NewBB


<s> SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; return CallResult . second


<s> void LLVMInitializePowerPCTarget ( ) { RegisterTargetMachine < <ISA_LIT>32TargetMachine > A (


<s> while ( CmpMI != Br -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; Register Reg = CmpMI -> getOperand ( <NUM_LIT> )


<s> xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , GOT_SYMBOL_NAME ) ; if ( flag_pic ) { char name [ <NUM_LIT> ] ; get_pc_thunk_name ( name , REGNO ( dest ) ) ; pic_labels_used |= <NUM_LIT> << REGNO ( dest ) ; xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; xops [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , xops [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , xops ) ; if ( machopic_should_output_picbase_label ( ) || ! label ) ASM_OUTPUT_LABEL ( asm_out_file , MACHOPIC_FUNCTION_BASE_NAME ) ; if ( label ) targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( label ) ) ; } else { if ( TARGET_MACHO ) gcc_unreachable ( ) ; xops [ <NUM_LIT> ] = gen_rtx_LABEL_REF ( Pmode , label ? label : gen_label_rtx ( ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( xops [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ; } if ( ! TARGET_MACHO ) output_asm_insn


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am

, SmallSet < Instruction * , <NUM_LIT> > & cil ) {


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_load_epi64 ( void const * __P ) { return ( __m128i ) ( * ( __v2di *


<s> I = <NUM_LIT> - CLO ; CTO = CLO + CountTrailingOnes_64 ( Imm ) - ( <NUM_LIT> - Size ) ; } assert ( Size > I && <STR_LIT> ) ; unsigned Immr = ( Size - I ) & ( Size - <NUM_LIT> ) ; uint64_t NImms = ~ ( Size - <NUM_LIT> ) << <NUM_LIT> ; NImms |= ( CTO - <NUM_LIT> ) ; unsigned N = ( ( NImms >> <NUM_LIT> ) & <NUM_LIT> ) ^ <NUM_LIT> ; Encoding = ( N << <NUM_LIT> ) | ( Immr << <NUM_LIT> ) | ( NImms & <NUM_LIT> ) ; return


<s> unsigned TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( Reg , RegState ::

Kill ) . addReg ( Reg , RegState :: Kill ) ;


<s> void emitRRR ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , unsigned Reg2 , SMLoc IDLoc , SmallVectorImpl <


<s> __builtin_ia32_pmovusqb512mem_mask ( ( unsigned long long * ) __P , ( __v8di )


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI


<s> switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; default : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32 ; } case FK_SecRel_2 : return COFF :: IMAGE_REL_<ISA_LIT>_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH20T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH24T ; case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BLX23T


<s> Inst . addOperand ( MCOperand :: CreateReg ( CRRegs [


<s> return __builtin_mve_vcaddq_rot90_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a ,


<s> getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 ,


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = <NUM_LIT> ; char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT>


<s> void <ISA_LIT>ATTAsmPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const char * Modifier ) { assert ( Modifier == <NUM_LIT> && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << '%' ; unsigned Reg = Op . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i64 : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i32 : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i16 : EVT :: i8 ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << TRI -> getAsmName ( Reg ) ; return ; } else if ( Op . isImm ( ) ) { O << '$' ; O << Op . getImm ( ) ; return ; } else if ( Op . isMCValue ( ) ) { O << '$' ; Op . getMCValue ( ) . print ( O


<s> bool isCheriHWAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_CheriHWRegs && RegIdx . Index


<s> return ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( getMemBaseReg ( ) == <STR_LIT> || getMemBaseReg ( ) == <STR_LIT> || getMemBaseReg ( ) == <STR_LIT> ) && isa < MCConstantExpr >

( getMemDisp ( ) ) && cast < MCConstantExpr > ( getMemDisp ( ) ) -> getValue ( ) == <NUM_LIT> ;


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS


<s> static DecodeStatus DecodeVSFRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo


<s> bool isSelectSupported ( SelectSupportKind Kind ) const override { return ( Kind != SelectSupportKind


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind , const MCExpr * Expr ,


__artificial__ ) ) _mm_mfence ( void ) {


<s> return ( __m128i ) __builtin_ia32_cvttpd2uqq128_mask ( ( __v2df ) __A ,


<s> return __builtin_mve_vsubq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) ,


<s> unsigned getBarrier ( ) const { assert ( Kind == k_Barrier && <STR_LIT> ) ; return Barrier


<s> int mt_function_arg_boundary ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED