<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) .


<s> return ( ( __m128d ) vec_cmpgt ( ( __v2df


<s> bool mips_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits ,


<s> unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT> ) / <NUM_LIT> ; Align Alignment = commonAlignment ( TFL -> getStackAlign ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Alignment ) ; return AddrReg . getReg


<s> default : return true ; } return isUIntN ( NumBits , Value ) || isIntN ( NumBits , static_cast


<s> int64_t Imm = Op . getImm ( ) ; if ( ExtendFrom < <NUM_LIT> ) Imm = SignExtend64 ( Imm , ExtendFrom ) ; return Imm ==


<s> static bool expandSHXDROT ( MachineInstrBuilder & MIB , const MCInstrDesc & Desc ) { MIB -> setDesc ( Desc ) ; int64_t ShiftAmt = MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt ) ; return true


<s> const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , is64Bit ?

<STR_LIT> : <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ;


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add (


<s> MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align &


<s> Register HintReg = getSubReg ( UACCPhys , ResultOp -> getSubReg ( ) ) ; Hints . push_back ( HintReg ) ; } break ; } case <STR_LIT> : { ResultOp = & Use . getOperand ( <NUM_LIT> ) ; ResultReg = ResultOp -> getReg ( ) ; if ( MRI -> getRegClass ( ResultReg ) -> contains ( <STR_LIT> ) && VRM -> hasPhys ( ResultReg ) ) { Register ACCPhys = VRM -> getPhys ( ResultReg ) ; assert ( ( ACCPhys >= <STR_LIT> && ACCPhys <= <STR_LIT> ) && <STR_LIT> ) ; Register HintReg = <STR_LIT> + ( ACCPhys - <STR_LIT> ) ; Hints . push_back ( HintReg ) ; } break ; } } } return


<s> return __builtin_ia32_vcvtph2qq512_mask_round ( __B , _mm512_setzero_si512 ( )


<s> static SDValue lowerMSASplatImm ( SDValue Op , unsigned ImmOp , SelectionDAG & DAG , bool IsSigned = false ) { auto * CImm = cast < ConstantSDNode > ( Op -> getOperand


<s> static bool is_store_insn ( rtx insn ) { if ( ! insn || ! INSN_P (


<s> assert ( ! Subtarget -> has<ISA_LIT>32r6 ( ) ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode (


<s> compression_flags = mips_get_compress_on_flags ( * attributes ) ; nocompression_flags = mips_get_compress_off_flags ( * attributes ) ; if ( TREE_CODE ( decl ) != FUNCTION_DECL ) { if ( nocompression_flags ) error ( <STR_LIT> , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags ) error ( <STR_LIT> , mips_get_compress_on_name ( nocompression_flags ) ) ; } else { compression_flags |= mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) ; nocompression_flags |= mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) ; if ( compression_flags && nocompression_flags ) error ( <STR_LIT> , DECL_NAME ( decl ) , mips_get_compress_on_name ( compression_flags ) , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags & MASK_MIPS16 && compression_flags & MASK_MICROMIPS ) error ( <STR_LIT> , DECL_NAME ( decl ) , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_FLIP_MIPS16 && ! DECL_ARTIFICIAL ( decl ) && compression_flags == <NUM_LIT> && nocompression_flags == <NUM_LIT> ) { name = mflip_mips16_use_mips16_p ( decl ) ? <STR_LIT> : <STR_LIT> ; * attributes = tree_cons ( get_identifier ( name ) , NULL ,


<s> <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && <ISA_LIT>SubTarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( FI ) ; SDValue Chain ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp ,

FIPtr , MPI , false , false , <NUM_LIT> ) ;


<s> PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case <STR_LIT> : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && ( ! Subtarget -> hasInt256 ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) ) ) return SDValue ( ) ; SDValue Amt = N -> getOperand (


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( )


<s> void <ISA_LIT>StackTagging :: alignAndPadAlloca ( AllocaInfo & Info ) { const Align NewAlignment = max ( MaybeAlign ( Info . AI -> getAlignment ( ) ) , kTagGranuleSize ) ; Info . AI -> setAlignment ( NewAlignment ) ; uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; uint64_t AlignedSize = alignTo ( Size , kTagGranuleSize ) ; if ( Size == AlignedSize ) return ; Type * AllocatedType = Info . AI -> isArrayAllocation ( ) ? ArrayType :: get ( Info . AI -> getAllocatedType ( ) , cast < ConstantInt > ( Info . AI -> getArraySize ( ) ) -> getZExtValue ( ) ) : Info . AI -> getAllocatedType ( ) ; Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( )


<s> static SDValue PerformShuffleCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) )


<s> unsigned UpperElts = NumElts - NumSrcElts ; if ( ! Zeroable . extractBits ( UpperElts , NumSrcElts ) . isAllOnesValue ( ) ) continue ; SrcVT = <STR_LIT> ( EltSizeInBits * Scale ) ; SrcVT = <STR_LIT> ( SrcVT , NumSrcElts ) ; DstVT = <STR_LIT> ( EltSizeInBits ) ; if ( ( NumSrcElts * EltSizeInBits ) >= <NUM_LIT> ) { DstVT = <STR_LIT> ( DstVT , NumSrcElts ) ; } else


<s> if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; DOUT << <STR_LIT> ; MI . print ( DOUT ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget ( tm . getSubtarget < <ISA_LIT>Subtarget >


<s> const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; for ( size_t i = <NUM_LIT> ; i < RegList . size ( ) ; ++ i ) { unsigned Reg = MRI -> getEncodingValue ( RegList [ i ] ) ; assert ( Reg < ( IsVector ? <NUM_LIT> : <NUM_LIT> ) && <STR_LIT> ) ; unsigned Bit = ( <NUM_LIT> << Reg ) ; if ( ( Mask & Bit ) == <NUM_LIT> ) { Mask |= Bit ; ++ Count ; } } SPOffset -= Count * ( IsVector ? <NUM_LIT> : <NUM_LIT> ) ; FlushPendingOffset ( ) ; if ( IsVector ) UnwindOpAsm . EmitVFPRegSave ( Mask ) ; else UnwindOpAsm . EmitRegSave (


<s> errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt (


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getConstant ( CC , DL , <STR_LIT> ) , LHS , RHS , Dest ) ; return Cmp


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const override { poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> ) ) ; return aarch64_sve_data_mode ( m_to_mode , nunits )


<s> bool hasFastBEXTR ( ) const { return


<s> void addSIMDImmType10Operands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL ,


<s> return static_cast < VariantKind > ( Kind


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static DecodeStatus DecodeCR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , HalfSize , HalfSize , Half * HalfSize ) ) { MatchB = true ; break ; } } return MatchA &&


<s> Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . isFloatingPoint ( ) ) { Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , VT ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } else { unsigned Num32BitElts = VT . getSizeInBits ( ) / <NUM_LIT> ; Vec = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ( <STR_LIT>


<s> return ( __m512h ) __builtin_ia32_getexpph512_mask ( ( __v32hf ) __A , ( __v32hf ) _mm512_setzero_ph ( ) , ( __mmask32 ) -


<s> if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysCR ( Num , S , getLoc ( )


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDAddr20Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups ) ; uint64_t Disp = getMachineOpValue ( MI , MI .

getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ;


<s> if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TBB , BranchWeight ) ; fastEmitBranch ( FBB , DbgLoc ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , Target -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( Target , BranchWeight ) ; return true ; } else if ( foldXALUIntrinsic ( CC , I , BI -> getCondition ( ) ) ) { unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( ! CondReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TBB , BranchWeight ) ; fastEmitBranch ( FBB , DbgLoc ) ; return true ; } unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondRegIsKill = hasTrivialKill ( BI -> getCondition ( ) ) ; emitICmp_ri ( <STR_LIT> , CondReg , CondRegIsKill , <NUM_LIT> ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CC = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TBB


<s> unsigned SecondReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ThirdReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( has<ISA_LIT>1 ( ) && ! has<ISA_LIT>2 ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ThirdReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , <STR_LIT> , ATReg , IDLoc , Instructions ) ; createNop ( false ,


<s> auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF . front ( ) ) ; bool Changed = false ; for ( auto ML : MLI ) { if ( ! ML -> getParentLoop ( ) ) Changed |= ProcessLoop (


<s> case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned LExtIndex = LHS . getConstantOperandVal ( <NUM_LIT> ) ; unsigned RExtIndex = RHS . getConstantOperandVal ( <NUM_LIT> ) ; if ( LExtIndex == <NUM_LIT> && RExtIndex == <NUM_LIT> && ( HOpcode == <STR_LIT> || HOpcode == <STR_LIT> ) ) std :: swap ( LExtIndex , RExtIndex ) ; if ( LExtIndex != <NUM_LIT> || RExtIndex != <NUM_LIT> ) return Op ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; EVT VecVT = X . getValueType ( ) ; unsigned BitWidth = VecVT . getSizeInBits ( ) ; assert ( ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; if ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) X = extract128BitVector ( X , <NUM_LIT> , DAG , DL ) ; SDValue HOp = DAG . getNode ( HOpcode , DL , X . getValueType ( ) , X , X ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getSimpleValueType ( ) , HOp , DAG .

getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>MCStreamer


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isImm ( ) ) return addImmOperands ( Inst , N


<s> if ( count != <NUM_LIT> ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , GP_REG_FIRST +


<s> case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return ! TARGET_MIPS16 && cmp1 == const1_rtx ; case LT : case


<s> if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( TARGET_32BIT_MS_ABI && cfun -> calls_setjmp ) return true ; if ( TARGET_64BIT_MS_ABI && get_frame_size ( ) >


<s> LiveInterval LI = LIs . getInterval ( reg ) ; SlotIndex SI = LIs . getInstructionIndex (


<s> const MCExpr * getExpr ( ) const { assert ( Kind == Expression &&


<s> const EDInstInfo * <ISA_LIT>GenericDisassembler :: getEDInfo ( )


<s> static void mips_multi_start ( void ) { mips_multi_members . truncate (


<s> void addModImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> unsigned <ISA_LIT>ABIInfo :: GetFramePtr ( )


<s> return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; MCInst Noop


<s> const int NumEltBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; assert ( ( Subtarget . hasSSSE3 ( ) && VT . is128BitVector ( ) ) || ( Subtarget . hasAVX2 ( ) && VT . is256BitVector ( ) ) || ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) ) ) ; SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ( NumBytes ) ; SDValue ZeroMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue V ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / NumEltBytes ] ; if ( M <


<s> xops [ <NUM_LIT> ] = stack_pointer_rtx ; xops [ <NUM_LIT> ] = reg ; xops [ <NUM_LIT> ] = const0_rtx ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg ; xops [ <NUM_LIT> ] = end ; output_asm_insn ( <STR_LIT> , xops


<s> scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( <NUM_LIT> ) ) ; return e . use_exact_insn ( code_for_while ( unspec ,


<s> return ( __m256i ) __builtin_ia32_pmovswb512_mask ( ( __v32hi ) __A , ( __v32qi ) _mm256_setzero_si256 ( )


<s> if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizePICCallPass


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> unsigned char <ISA_LIT>Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) && ! GV -> hasInternalLinkage ( ) ) return <STR_LIT> ; auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( *

GV -> getParent ( ) , GV ) ) return <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> case E_V4SImode : if ( ! REG_P ( target ) || REGNO ( target ) < FIRST_PSEUDO_REGISTER ) new_target = gen_reg_rtx ( mode ) ; else new_target = target ; var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_DUPLICATE ( mode , var ) ; x = gen_rtx_VEC_MERGE ( mode , x , CONST0_RTX ( mode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( new_target , x ) ) ; if ( one_var != <NUM_LIT> ) { if ( mode != V4SFmode && TARGET_SSE2 ) { emit_insn ( gen_sse2_pshufd_1 ( new_target , new_target , const1_rtx , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) ; if ( target != new_target ) emit_move_insn ( target , new_target ) ; return true ; } if ( mode != V4SFmode ) { tmp = gen_reg_rtx ( V4SFmode ) ; emit_move_insn ( tmp , gen_lowpart ( V4SFmode , new_target ) ) ; } else tmp = new_target ; emit_insn ( gen_sse_shufps_v4sf ( tmp , tmp , tmp , const1_rtx , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> + <NUM_LIT> : <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( one_var == <NUM_LIT> ? <NUM_LIT> + <NUM_LIT> : <NUM_LIT> + <NUM_LIT> ) ) ) ; if ( mode != V4SFmode ) emit_move_insn ( target , gen_lowpart ( V4SImode , tmp ) ) ; else if ( tmp != target ) emit_move_insn ( target , tmp ) ; } else if ( target != new_target ) emit_move_insn ( target , new_target ) ; return true ; case E_V8HImode : case E_V16QImode : vsimode = V4SImode ; goto widen ; case E_V4HImode : case E_V8QImode : if ( ! mmx_ok ) return false ; vsimode = V2SImode ; goto widen ; widen : if ( one_var != <NUM_LIT> ) return false ; var = convert_modes ( SImode , GET_MODE_INNER ( mode ) , var , true ) ; x = gen_reg_rtx ( vsimode ) ; if ( ! ix86_expand_vector_init_one_nonzero ( mmx_ok , vsimode , x , var , one_var ) )


<s> SDValue LoForNormalShift = DAG . getNode ( <STR_LIT> , dl , VT , LoBitsForLo , HiBitsForLo ) ; Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , dl , DAG ) ; CCVal = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue LoForBigShift = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , LoForBigShift , LoForNormalShift , CCVal , Cmp ) ; SDValue HiForNormalShift = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue HiForBigShift = Opc == <STR_LIT> ? DAG . getNode ( Opc , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , dl , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT ,

HiForBigShift , HiForNormalShift , CCVal , Cmp ) ;


<s> getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; if ( offset == INT32_MIN ) { Val = <NUM_LIT> ; offset =


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= selectMBB ( MBB ) ; return


<s> for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) if ( Reg == CSRegs [ i


<s> return ( ( RegIdx . Index >= <NUM_LIT> && RegIdx . Index <= <NUM_LIT> )

|| RegIdx . Index == <NUM_LIT> || RegIdx . Index == <NUM_LIT> ) ;


<s> return RegIdx . Index >= <NUM_LIT> && RegIdx


<s> SDValue Broadcast = LowerVectorBroadcast ( Op , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getValueType ( ) . getSimpleVT ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( )


<s> static SDValue ConvertBooleanCarryToCarryFlag ( SDValue BoolCarry , SelectionDAG & DAG ) { SDLoc DL ( BoolCarry ) ; EVT CarryVT = BoolCarry


<s> bool <ISA_LIT>16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg


<s> __inline__ static unsigned long long sh_media_MSUBS_UB ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm


<s> case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx


<s> if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } return align


<s> Value * <ISA_LIT>IREmitter :: visitATOMSWAP64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> if ( RetTy -> isVectorTy ( ) && ID == <STR_LIT> ) return getNumVectorRegs ( RetTy ) ; return -


<s> void <ISA_LIT>TargetAsmStreamer :: emitArch ( unsigned Arch ) { OS << <STR_LIT> << <STR_LIT> (


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , IsFadd ) && shouldUseHorizontalOp ( LHS == RHS , DAG ,

Subtarget ) ) return DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> else Opc = isSub ? <STR_LIT> : <STR_LIT> ; const unsigned MaxEncoding = <NUM_LIT> ; const unsigned ShiftSize = <NUM_LIT> ; const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; while ( ( ( unsigned ) Offset ) >= ( <NUM_LIT> << ShiftSize ) ) { unsigned ThisVal ; if ( ( ( unsigned ) Offset ) > MaxEncodableValue ) { ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; SrcReg =


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ( hasV7Ops ( ) || hasV8Ops ( ) ) && ( Num == <NUM_LIT> || Num == <NUM_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S ) ) ; return


<s> return LowerELFTLSLocalExec ( GV , ThreadBase , DL , DAG ) ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model ==


<s> if ( convertToBRCT ( MI , Compare , CCUsers ) ) { BranchOnCounts += <NUM_LIT> ; return true ; } if ( convertToLoadAndTrap ( MI , Compare , CCUsers ) ) { LoadAndTraps += <NUM_LIT> ; return true ; } } if ( ( ! CCRefs && convertToLoadAndTest ( MI , Compare , CCUsers ) ) || ( ! CCRefs . Def && ( adjustCCMasksForInstr ( MI , Compare , CCUsers ) || convertToLogical ( MI , Compare , CCUsers ) ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; if ( Compare . mayRaiseFPException ( ) && ( MI . isCall ( ) || MI . hasUnmodeledSideEffects ( ) ) ) break ; } for ( MachineBasicBlock :: iterator MBBI = std :: next ( MachineBasicBlock :: iterator ( & Compare ) ) , MBBE = MBB . end ( ) ; MBBI != MBBE ;


<s> bool <ISA_LIT>PreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn


<s> unsigned int call_properties ( const function_instance


<s> inline static bool isMImmVal ( uint64_t Val ) { if ( Val == <NUM_LIT> ) { return true ; } if ( isMask_64 ( Val )


<s> bool <ISA_LIT>InstrInfo :: isValidToBeChangedReg ( MachineInstr * ADDMI , unsigned Index , MachineInstr * & ADDIMI , int64_t & OffsetAddi , int64_t OffsetImm ) const { assert ( ( Index == <NUM_LIT> || Index == <NUM_LIT> ) && <STR_LIT> ) ; MachineOperand & MO = ADDMI -> getOperand ( Index ) ; if ( ! MO . isKill ( ) ) return false ; bool OtherIntermediateUse = false ; ADDIMI = getDefMIPostRA ( MO . getReg ( ) ,


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return <STR_LIT>


<s> aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( <STR_LIT> , ftype_jcvt , AARCH64_JSCVT ) ; if ( ! TARGET_ILP32 ) aarch64_init_pauth_hint_builtins ( ) ; if ( TARGET_TME )


<s> bool Modified = false ; for ( auto & MBB : MF ) Modified |= selectMBB ( MBB ) ; return


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , <STR_LIT> ) ; return true


<s> case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } if ( isTargetShuffle ( Opc ) ) { bool IsUnary ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask , IsUnary ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; Known . Zero . setAllBits ( ) ; Known . One . setAllBits ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { Known . resetAll ( ) ; break ; } else if ( M == SM_SentinelZero ) { Known . One . clearAllBits ( ) ; continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { Known . resetAll ( ) ; break ; } DemandedOps [ OpIdx ] . setBit ( EltIdx ) ; } for ( unsigned i = <NUM_LIT> ; i != NumOps && ! Known . isUnknown ( ) ;


<s> if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue InVec = Op -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; EVT SVT = SrcVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , InVec , DAG . getIntPtrConstant ( i ) ) ) ; SDValue Undef = DAG . getUNDEF ( SVT ) ; for ( unsigned i = NumElts , e = NumElts * <NUM_LIT> ; i != e ; ++ i ) Elts . push_back ( Undef ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , NewVT , Elts ) ; SDValue ToV2F64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } assert ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits


<s> return ( __m256d ) __builtin_ia32_scalefpd256_mask ( ( __v4df ) __A , ( __v4df ) __B , ( __v4df ) _mm256_setzero_pd ( ) , (


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv2di (


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> EVT PtrVT = Op . getValueType ( ) ; GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; SDLoc DL ( GSDN ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT


<s> void setVarArgsGPRIndex ( int Index ) { VarArgsGPRIndex = Index


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( ( RegInfo -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ) ; MIB . addImm (


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target ,


<s> MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg

( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel )


<s> char ConstraintLetter = Constraint [ <NUM_LIT> ] ; switch ( ConstraintLetter ) { default : break ; case 'z' : { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return ; if ( Op . getValueType ( ) == <STR_LIT> ) Result = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else Result = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; break ; } case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return ; uint64_t CVal = C -> getZExtValue ( ) ; switch ( ConstraintLetter ) { case 'I' : if ( isUInt < <NUM_LIT> > ( CVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( CVal ) ) break ; return ; case 'J' : { uint64_t NVal = - C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( NVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( NVal ) ) { CVal = C -> getSExtValue ( ) ; break ; } return ; } case 'K' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'L' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'M' : { if ( ! isUInt < <NUM_LIT> > ( CVal ) ) return ; if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ ( uint32_t ) CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } case 'N' : { if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> )


<s> if ( ARM_DOUBLEWORD_ALIGN ) for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) if ( mp -> refcount > <NUM_LIT> && mp -> fix_size >= <NUM_LIT> ) { align64 = <NUM_LIT> ; break ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( scan ) , ( unsigned long ) minipool_barrier -> address , align64 ? <NUM_LIT> : <NUM_LIT> ) ; scan = emit_label_after ( gen_label_rtx ( ) , scan ) ; scan = emit_insn_after ( align64 ? gen_align_8 ( ) : gen_align_4 ( ) , scan ) ; scan = emit_label_after ( minipool_vector_label , scan ) ; for ( mp = minipool_vector_head ; mp != NULL ; mp = nmp ) { if ( mp -> refcount > <NUM_LIT> ) { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , ( unsigned ) mp -> offset , ( unsigned long ) mp -> min_address , ( unsigned long ) mp -> max_address ) ; arm_print_value ( dump_file , mp -> value ) ; fputc ( '\n' , dump_file ) ; } rtx val = copy_rtx ( mp -> value ) ; switch ( GET_MODE_SIZE ( mp -> mode ) ) { case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_1 ( val ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_2 ( val ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_4 ( val ) , scan


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )


<s> switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : { bool NonFlagUse = false ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User -> use_begin ( ) ; } if ( User -> getOpcode ( ) != <STR_LIT> && User -> getOpcode ( ) != <STR_LIT> && ( User -> getOpcode ( ) != <STR_LIT> || UOpNo != <NUM_LIT> ) ) { NonFlagUse =


<s> unsigned char code ; code = * dp ++ ; decoder = unw_decode_table [ inside_body ] [ code >> <NUM_LIT> ] ; dp = ( * decoder ) ( dp , code , arg ) ; return dp


<s> bool isBranchTarget ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return true ; int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return false ; assert ( N > <NUM_LIT> && <STR_LIT> ) ; return ( Val >= - ( ( <NUM_LIT> << ( N - <NUM_LIT> ) ) << <NUM_LIT> ) && Val <= ( ( ( <NUM_LIT> << (

N - <NUM_LIT> ) ) - <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . isCPI ( ) || ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && isGVStub ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , TM ) ) ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> )


<s> MachineInstr * MUL = MRI . getUniqueVRegDef ( Root . getOperand ( IdxMulOpd ) . getReg ( ) ) ; Register ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; Register SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg2 ; bool Src2IsKill ; if ( ReplacedAddend ) { SrcReg2 = * ReplacedAddend ; Src2IsKill = true ; } else { SrcReg2 = Root . getOperand ( IdxOtherOpd ) . getReg ( ) ; Src2IsKill = Root . getOperand ( IdxOtherOpd ) . isKill ( ) ; } if ( Register :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( Register :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass


<s> SDValue <ISA_LIT>TargetLowering :: LowerABS ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT != <STR_LIT> || Subtarget . hasP8Altivec ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Y = DAG . getNode ( <STR_LIT> , dl , VT , Zero


<s> if ( in_p ) { if ( REGCLASS_HAS_FP_REG ( rclass ) && immediate_operand ( ( x ) , mode ) && ! ( ( fp_zero_operand ( x ) || fp_one_operand ( x ) ) && mode == SFmode ) ) switch ( mode ) { case E_SFmode : sri -> icode = CODE_FOR_reload_insf__frn ; return NO_REGS ; case E_DFmode : sri -> icode = CODE_FOR_reload_indf__frn ; return NO_REGS ; case E_SImode : return FPUL_REGS ; default : abort ( ) ; } if ( rclass == FPUL_REGS && ( ( REG_P ( x ) && ( REGNO ( x ) == MACL_REG || REGNO ( x ) == MACH_REG || REGNO ( x ) == T_REG ) ) || GET_CODE ( x ) == PLUS ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && immediate_operand ( x , mode ) ) { if ( satisfies_constraint_I08 ( x ) || fp_zero_operand ( x ) ) return GENERAL_REGS ; else if ( mode == SFmode ) return FP_REGS ; sri -> icode = CODE_FOR_reload_insi__i_fpul ; return NO_REGS ; } if ( rclass == FPSCR_REGS && ( ( REG_P ( x ) && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) || ( MEM_P ( x ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) ) ) return GENERAL_REGS ; } if ( ( ( REGCLASS_HAS_FP_REG ( rclass ) && ( REG_P ( x ) && ( GENERAL_OR_AP_REGISTER_P ( REGNO ( x ) ) || ( FP_REGISTER_P ( REGNO ( x ) ) && mode == SImode && TARGET_FMOVD ) ) ) ) || ( REGCLASS_HAS_GENERAL_REG ( rclass ) && REG_P ( x ) && FP_REGISTER_P ( REGNO ( x ) ) ) ) && ( mode == SFmode || mode == SImode ) ) return FPUL_REGS ; if ( ( rclass == FPUL_REGS || ( REGCLASS_HAS_FP_REG ( rclass ) && mode == SImode ) ) && ( MEM_P ( x ) || ( REG_P ( x ) && ( REGNO ( x ) >= FIRST_PSEUDO_REGISTER || REGNO ( x ) == T_REG || system_reg_operand ( x , VOIDmode ) ) ) ) ) { if ( rclass == FPUL_REGS ) return GENERAL_REGS ; return NO_REGS ; } if ( ( rclass == MAC_REGS || rclass == PR_REGS ) && REG_P ( x ) && ! GENERAL_REGISTER_P ( REGNO ( x ) ) && rclass != REGNO_REG_CLASS ( REGNO ( x ) ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && true_regnum ( x ) == - <NUM_LIT> ) return GENERAL_REGS ; if ( ( mode == QImode || mode == HImode ) && rclass != R0_REGS && satisfies_constraint_Sdd ( x ) && sh_disp_addr_displacement

( x ) <= sh_max_mov_insn_displacement ( mode , false ) ) return R0_REGS ;


<s> punpckhwd_u ( uint32x2_t s , uint32x2_t t ) { return __builtin_loongson_punpckhwd_u ( s , t


<s> return StringRef ( Tok . Data , Tok .


<s> if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; a = arm_function_value ( TREE_TYPE ( exp ) , decl , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl )


<s> static uint16_t name ( struct InternalInstruction * insn , OperandType type , \ uint8_t index , uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ if ( insn -> rexPrefix && index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _AX + index ; \ case TYPE_R32 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_TMM : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _TMM0 + index ; \ case TYPE_VK : \ index &= <NUM_LIT> ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_VK_PAIR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ##

_K0_K1 + ( index / <NUM_LIT> ) ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( ( index & <NUM_LIT> ) > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + ( index & <NUM_LIT> ) ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_MVSIBX : \ return prefix ## _XMM0 + index ; \ case TYPE_MVSIBY : \ return prefix ## _YMM0 + index ; \ case TYPE_MVSIBZ : \ return prefix ## _ZMM0 + index ; \ } \ }


<s> void setGlobalValue ( const GlobalValue * G


<s> static void replace_swap_with_copy ( swap_web_entry * insn_entry , unsigned i ) { rtx_insn * insn = insn_entry [ i ] . insn ; rtx body = PATTERN ( insn ) ; rtx src_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx copy = gen_rtx_SET ( SET_DEST ( body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( insn ) ) ; df_insn_rescan ( new_insn ) ; if ( dump_file ) { unsigned int new_uid = INSN_UID ( new_insn ) ; fprintf ( dump_file , <STR_LIT> , i , new_uid ) ; } df_insn_delete ( insn ) ; remove_insn ( insn ) ; insn -> set_deleted


<s> if ( ! isMMSourceRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI , Entry )


<s> if ( instance . reads_global_state_p ( ) ) attrs = add_attribute ( <STR_LIT> , attrs ) ; else attrs = add_attribute (


<s> unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg


<s> return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { int16_t imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Alignment || ( imm % Alignment ) == <NUM_LIT> ) ) { KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSKnown . Zero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } Disp = DAG . getTargetConstant ( imm , dl , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { int16_t Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! Alignment || ( Imm % Alignment ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , dl , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> :

<STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) ->


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; const unsigned StackOffset = <NUM_LIT> ; bool IsLittleEndian = DAG . getDataLayout ( ) . isLittleEndian ( ) ; unsigned InIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ InIdx ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ InIdx ] . Flags . isSRet ( ) ) { if ( InIdx != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIPtr = DAG . getFrameIndex ( FrameIdx , <STR_LIT> ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , dl , Chain , FIPtr , MachinePointerInfo ( ) ) ; InVals . push_back ( Arg ) ; continue ; } if ( VA . isRegLoc ( ) ) { if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) ; unsigned VRegHi = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , VRegHi ) ; SDValue HiVal = DAG . getCopyFromReg ( Chain , dl , VRegHi , <STR_LIT> ) ; assert ( i + <NUM_LIT> < e ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; SDValue LoVal ; if ( NextVA . isMemLoc ( ) ) { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , StackOffset + NextVA . getLocMemOffset ( ) , true ) ; SDValue FIPtr = DAG . getFrameIndex ( FrameIdx , <STR_LIT> ) ; LoVal = DAG . getLoad ( <STR_LIT> , dl , Chain , FIPtr , MachinePointerInfo ( ) ) ; } else { unsigned loReg = MF . addLiveIn ( NextVA . getLocReg ( ) , & <STR_LIT> ) ; LoVal = DAG . getCopyFromReg ( Chain , dl , loReg , <STR_LIT> ) ; } if ( IsLittleEndian ) std :: swap ( LoVal , HiVal ) ; SDValue WholeValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoVal , HiVal ) ; WholeValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , WholeValue ) ; InVals . push_back ( WholeValue ) ; continue ; } unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( )


<s> int64_t Offset ; if ( parseImmExpr ( Offset )


<s> <ISA_LIT>DisassemblerBase ( STI , Ctx , bigEndian ) { IsMicro<ISA_LIT> = STI . getFeatureBits ( )


<s> else if ( DestVT == <STR_LIT> ) { unsigned Src64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Src64 ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = Src64 ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) . addImm (


<s> if ( ! MemOp0 -> isSimple ( ) || ! MemOp1 -> isSimple ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( isConsecutiveAccess ( MemOp0 , MemOp1 , DL , SE ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true


<s> printSOImm ( O , V1 , VerboseAsm , TAI ) ; O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O <<


<s> void addVCTP ( MachineInstr * MI ) { if ( ! VCTP ) { VCTP = MI ; FoundOneVCTP = true ; } else FoundOneVCTP = false


<s> case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT>


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; return


<s> void <ISA_LIT>CodeEmitter :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI


<s> LoadCmpBB -> addLiveIn ( DesiredLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredHi . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addOperand ( DesiredLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addOperand ( DesiredHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( StatusReg , RegState :: Kill ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , RegState :: Kill ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( NewLo .


<s> <ISA_LIT>MCAsmInfoCOFF :: <ISA_LIT>MCAsmInfoCOFF ( const Triple & Triple ) { AsmTransCBE = x86_asm_table


<s> if ( parseToken ( AsmToken :: Comma ) ) return addErrorSuffix ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitValueToAlignment (


<s> case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FSQRT : case TargetOpcode


<s> assert ( ! FirstMI . hasOrderedMemoryRef ( ) && ! TII -> isLdStPairSuppressed ( FirstMI ) && <STR_LIT> ) ; unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return ! <ISA_LIT>InstrInfo :: isPreLdSt ( FirstMI ) ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } if ( ! PairIsValidLdStrOpc ) return false ; if ( isNarrowStore ( OpcA ) || isNarrowStore ( OpcB )


<s> if ( ! Check ( S , DecodeGPR32RegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPR32RegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : if ( ! Check ( S , DecodeGPR64RegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPR64RegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : llvm_unreachable ( <STR_LIT> )


<s> for ( const MachineOperand & MO : Orig . operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { ClobbersEFLAGS = true ; break ; } } if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT>


<s> int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset +

LoadSize <= ( UnscaledStOffset + StoreSize ) ) ;


<s> return <STR_LIT> . contains ( reg ) || <STR_LIT> . contains ( reg


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder )


<s> if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( DstVT == <STR_LIT> && ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY_TO_REGCLASS ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = TmpReg ; } unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = <ISA_LIT>SubTarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( I , DstVT , DestReg , IsSigned ) ; if ( IntReg == <NUM_LIT> ) return


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAligned } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAligned } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCCodeEmitter :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind )


<s> if ( DestRC != SrcRC ) { if ( ( ( DestRC == <STR_LIT> ) && ( SrcRC == <STR_LIT> ) ) || ( ( SrcRC == <STR_LIT> ) && ( DestRC == <STR_LIT> ) ) ) { } else { return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .


<s> if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ) ; MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget . is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot

, MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ) ;


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; AllowsUnalignedMem = false ; Thumb2DSP =


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . ParseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Identifier . end ( ) ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E ; if ( getParser ( ) . ParseExpression ( IdVal , E ) ) return true ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E ; if ( parseRelocOperand ( IdVal , E ) ) return true ; Operands . push_back ( <STR_LIT> ( IdVal ,


<s> } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr & NewMI = * std :: prev ( MBBI ) ; NewMI . copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ; unsigned StackPtr = TRI -> getStackRegister ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstrBuilder MIB ; if ( StackAdj == <NUM_LIT> ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; } else if ( isUInt < <NUM_LIT> > ( StackAdj ) ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addImm ( StackAdj ) ; } else { assert ( ! STI -> is64Bit (


<s> unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( Lo ) { Register TmpReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TmpReg ) . addImm ( Hi ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo


<s> SDLoc dl ( Op ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( )


<s> BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; const uint32_t * RegMask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( * MF , CallingConv :: C ) ; if ( IsLP64 ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } if ( ! Is64Bit ) BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg )


<s> return ( __m256i ) __builtin_ia32_vgf2p8affineqb_v32qi ( ( __v32qi )


<s> vmovn_high_s32 ( int16x4_t a , int32x4_t b ) { int16x8_t result = vcombine_s16 ( a , vcreate_s16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) :


<s> return <STR_LIT> ; } else if ( STI . hasAVX ( ) ) { return <STR_LIT> ; } else if ( STI . hasSSE2 ( ) ) { return <STR_LIT> ; } } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { if ( ( STI . hasAVX512 ( ) ) && ( STI . hasVLX ( ) ) ) { return <STR_LIT> ; } else if ( STI . hasAVX ( ) ) { return <STR_LIT>


<s> bool hasPartwordAtomics ( ) const { return HasPartwordAtomics


<s> OperandMatchResultTy parseADDR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> , <ISA_LIT>Operand :: ADDR64Reg


<s> val = gen_lowpart ( SImode , val ) ; x = gen_rtx_TRUNCATE ( HImode , val ) ; x = gen_rtx_VEC_DUPLICATE ( mode , x ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; return true ; } goto widen ; case V8QImode : if ( ! mmx_ok ) return false ; goto widen ; case V8HImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) { struct expand_vec_perm_d dperm ; rtx tmp1 , tmp2 ; permute : memset ( & dperm , <NUM_LIT> , sizeof ( dperm ) ) ; dperm . target = target ; dperm . vmode = mode ; dperm . nelt = GET_MODE_NUNITS ( mode ) ; dperm . op0 = dperm . op1 = gen_reg_rtx ( mode ) ; dperm . one_operand_p = true ; tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; emit_move_insn ( dperm . op0 , gen_lowpart ( mode , tmp2 ) ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER (


<s> if ( mode == VOIDmode && op != NULL_RTX ) mode = GET_MODE ( op ) ; if ( mode == CCmode || mode == CC_UNSmode || mode == DImode ) return <NUM_LIT> ; if ( ( mode == CC_FPmode || mode == DFmode ) && ( code == GT || code == LT


<s> return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ; else FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset


<s> unsigned getCCOutOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return MI . getOperand ( Op ) . getReg ( )


<s> ops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; ops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; output_move_double ( ops , false , & count ) ; return count


<s> <ISA_LIT>PreRASchedStrategy ( const MachineSchedContext *


<s> struct decl_chain * warned = ( struct decl_chain * ) xmalloc ( sizeof * warned ) ; warned -> fndecl = fndecl ; warned -> next =


<s> } O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << TRI -> getAsmName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3

. getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> case FK_Data_4 : return ELF :: R_390_TLS_LDM32 ; case FK_Data_8 : return ELF :: R_390_TLS_LDM64 ; case <STR_LIT> : return ELF ::


<s> CodeModel :: Model CM = TM . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { if ( Offset & <NUM_LIT> ) { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Offset & ~ uint64_t ( <NUM_LIT> ) ) ; Offset &= <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } Result = DAG . getNode ( <STR_LIT>


<s> int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_ABI_IGNORED ( field ) ) { unsigned int flag ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( field ) ) ) flag = WARN_PSABI_NO_UNIQUE_ADDRESS ; else if ( cxx17_empty_base_field_p ( field ) ) flag = WARN_PSABI_EMPTY_CXX17_BASE ; else continue ; if ( warn_psabi_flags ) { * warn_psabi_flags |= flag ; continue ; } } else if ( DECL_BIT_FIELD ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) { if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) continue ; if ( warn_psabi_flags ) { * warn_psabi_flags |= WARN_PSABI_ZERO_WIDTH_BITFIELD ; continue ; } } sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep , warn_psabi_flags ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST )


<s> bool isSysCR ( ) const { return Kind


, <NUM_LIT> , ( __mmask32 ) - <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> unsigned getT2AddrModeSORegOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> static void lowerMUL_LOHI32 ( SelectionDAG & DAG , const SDLoc & DL , unsigned Extend , SDValue Op0 , SDValue Op1 , SDValue & Hi , SDValue & Lo ) { Op0 = DAG . getNode ( Extend , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL ,


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } return false


<s> if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass (

create<ISA_LIT>OptimizeBarriersPass ( ) ) ;


<s> MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , ++ MachineBasicBlock :: iterator ( I ) , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg


<s> std :: pair < unsigned , unsigned > <ISA_LIT>InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned


<s> static MCStreamer * create<ISA_LIT>MachOStreamer ( MCContext & Ctx , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool DWARFMustBeAtTheEnd ) { return createMachOStreamer ( Ctx , MAB , OS ,

Emitter , false , DWARFMustBeAtTheEnd ) ;


<s> if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetELF ( ) )

return LowerELFGlobalTLSAddress ( Op , DAG ) ;


<s> const DataLayout * getDataLayout ( ) const override { return &


<s> if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) return IsFP ? <STR_LIT> : <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) || Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) return IsFP ? <STR_LIT> : <STR_LIT> ; return <NUM_LIT>


<s> if ( hasInlineStackProbe ( MF ) ) return <STR_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF

. getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;


<s> return __builtin_mve_vcaddq_rot270_sv16qi ( __a ,


<s> if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDiu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = Subtarget . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDiu ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = Subtarget . isABI_N64 ( ) ?


<s> if ( MaxAlign == <NUM_LIT> ) return ; if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) { if ( VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == <NUM_LIT> ) MaxAlign = <NUM_LIT> ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( auto * EltTy : STy -> elements


<s> if ( ( Val & Upper ) && ( Val & Upper ) != Upper ) return false ; return <STR_LIT> ( Val & ~ Upper , sizeof (


<s> SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShMsk0 ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt0 . getOperand ( <NUM_LIT> ) ) && ShAmt0 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk0 = ShAmt0 ; ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; } SDValue ShMsk1 ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1 . getOperand ( <NUM_LIT> ) ) && ShAmt1 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1 ; ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; } if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> || ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; std :: swap ( ShMsk0 , ShMsk1 ) ; } auto GetFunnelShift = [ & DAG , & DL , VT , Opc ] ( SDValue Op0 , SDValue Op1 , SDValue Amt ) { if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Amt ) ) ; } ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1Op1 . getOperand ( <NUM_LIT> ) ) && ShAmt1Op1 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1Op1 ; ShAmt1Op1 = ShAmt1Op1 . getOperand (


<s> if ( target_flags_explicit & MASK_MEMCPY ) return


<s> SDLoc DL ( Op ) ; unsigned VaListSize = Subtarget -> isTargetDarwin ( ) ? <NUM_LIT> : <NUM_LIT> ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , DL , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( VaListSize , DL , <STR_LIT> ) , <NUM_LIT> , false ,

false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; bool Valid ; uint32_t Bits = <STR_LIT> ( ) . fromString ( getSysReg


<s> tocrel = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol , tocreg ) , UNSPEC_TOCREL ) ; if ( TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ( ) ) return tocrel ; hi = gen_rtx_HIGH ( Pmode , copy_rtx ( tocrel ) ) ; if ( largetoc_reg != NULL )


<s> } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( VT . isInteger ( ) && ! Subtarget -> hasAVX2 ( ) ) { int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getNode ( <STR_LIT> , DL , FpVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , FpVT , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV32I8VectorShuffle ( Op , V1 , V2


<s> unsigned Register = GPRDecoderTable [ ( RegNo ) ] ; Inst . addOperand ( MCOperand :: createReg (


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> unsigned <ISA_LIT>16InstrInfo :: basicLoadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned & NewImm ) const { const TargetRegisterClass * RC = & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Imm ) ; NewImm =


<s> auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( ! VT . isInteger ( ) ) return SDValue ( ) ; if ( isNullConstant ( FalseVal ) ) { if ( CC == <STR_LIT> && isOneConstant ( TrueVal ) ) { if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV5TOps ( ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Sub ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , dl , VTs , FalseVal , Sub ) ; SDValue Carry = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Neg . getValue ( <NUM_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , dl , VTs , Sub , Neg , Carry ) ; } } else if ( CC == <STR_LIT> && ! isNullConstant ( RHS ) && ( ! Subtarget -> isThumb1Only ( ) || isPowerOf2Constant ( TrueVal ) ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , LHS , RHS ) ; SDValue CPSRGlue = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl

, <STR_LIT> , Sub . getValue ( <NUM_LIT> ) , SDValue ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector (


<s> USItype bit = <NUM_LIT> ; USItype res = <NUM_LIT> ; while ( den < num && bit && ! ( den & ( <NUM_LIT> << <NUM_LIT> ) ) ) { den <<= <NUM_LIT> ; bit <<= <NUM_LIT> ; } while ( bit ) { if ( num >= den ) { num -= den ; res |= bit ; } bit >>= <NUM_LIT> ; den >>=


<s> if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , CurrVT , Op0 , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , CurrVT , Op0 , NibbleShift ) ; SDValue HiZ = DAG . getSetCC ( DL , CurrVT , Hi , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , CurrVT , InRegLUT , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , CurrVT , InRegLUT , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , CurrVT , Lo , HiZ ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , CurrVT , Lo , Hi ) ; while ( CurrVT != VT ) { int CurrScalarSizeInBits = CurrVT . getScalarSizeInBits ( ) ; int CurrNumElts = CurrVT . getVectorNumElements ( ) ; MVT NextSVT = <STR_LIT> ( CurrScalarSizeInBits * <NUM_LIT> ) ; MVT NextVT = <STR_LIT> ( NextSVT , CurrNumElts / <NUM_LIT> ) ; SDValue Shift = DAG . getConstant ( CurrScalarSizeInBits , DL , NextVT ) ; SDValue HiZ = DAG . getSetCC ( DL , CurrVT , DAG . getBitcast ( CurrVT , Op0 ) , DAG . getBitcast ( CurrVT , Zero ) , <STR_LIT> ) ; HiZ = DAG . getBitcast ( NextVT , HiZ ) ; SDValue ResNext = Res = DAG . getBitcast ( NextVT ,