<s> if ( B . succ_empty ( ) ) return nullptr ; auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end (

) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) {


<s> return ( __mmask16 ) __builtin_ia32_ucmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target

, uint64_t & Value , bool & IsResolved ) {


<s> if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return AsmPrinter :: GetCPISymbol ( CPID


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; addExpr ( Inst , getMemOffset


<s> unsigned <ISA_LIT>RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT>


<s> const unsigned NewReg = constrainOperandRegClass ( II , getRegForValue ( I -> getNewValOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const unsigned ResultReg1 = createResultReg ( ResRC ) ; const unsigned ResultReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( ResultReg1 , RegState :: Define ) . addReg ( ResultReg2 , RegState :: Define ) . addReg ( AddrReg ) . addReg ( DesiredReg ) . addReg ( NewReg ) ; assert ( ( ResultReg1 + <NUM_LIT> ) == ResultReg2 && <STR_LIT> ) ; updateValueMap ( I , ResultReg1 , <NUM_LIT>


<s> SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } else if ( Subtarget -> isTargetWindows ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize (


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ,


<s> } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSX ( ) && <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , ArrayRef < SDValue > ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ]


<s> if ( TARGET_NEON ) switch ( mode ) { case E_HFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HFmode : V8HFmode ; case E_SFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode ; case E_SImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode ; case E_HImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode ; case E_QImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode ; case E_DImode : if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) return V2DImode ; break ; default : ; } if ( TARGET_REALLY_IWMMXT ) switch ( mode ) { case E_SImode


<s> machine_mode mode = amount -> mode ; unsigned val = UINTVAL ( CONST_VECTOR_ELT ( amount , <NUM_LIT> ) ) ; val &= GET_MODE_UNIT_BITSIZE ( mode ) - <NUM_LIT> ; if ( ! val ) return <STR_LIT> ; rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; operands [ <NUM_LIT> ] = gen_const_vec_duplicate ( mode ,


<s> static tree ia64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= IA64_BUILTIN_max ) return error_mark_node ; return ia64_builtins [ code


<s> else if ( Subtarget . isTargetXPLINK64 ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Offset = Reg && ! Subtarget . isTargetXPLINK64 ( ) ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( Offset ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) { if ( Subtarget -> hasCondMov ( ) && ! True . getValueType ( ) . isFloatingPoint ( ) ) return Op ; return DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , Cond , True , False ) ; } SDValue CCNode = Cond . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , True . getValueType


<s> const Thumb2RegisterInfo & getRegisterInfo ( ) const { return


<s> if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueC , FalseC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , TrueC -> getValueType ( <NUM_LIT> ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , <STR_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier =


<s> Value * <ISA_LIT>IREmitter :: visitVSHLLi ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parsePrimaryExpr ( Res , EndLoc ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; bool TryRegParse = getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) ) ; if ( ! TryRegParse || ParseRegister ( RegNo , StartLoc


<s> unsigned <ISA_LIT>InstrInfo :: getLoadAndTest ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Dest = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Index = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ) ; if ( Dest == Index ) return Warning ( Ops [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = Inst . getOperand ( Inst . getNumOperands ( ) - <STR_LIT> - <NUM_LIT> ) . getReg ( ) ; unsigned Src2Enc = MRI -> getEncodingValue ( Src2 ) ; if ( Src2Enc % <NUM_LIT> != <NUM_LIT> ) { StringRef RegName = <ISA_LIT>IntelInstPrinter :: getRegisterName ( Src2 ) ; unsigned GroupStart = ( Src2Enc / <NUM_LIT> ) * <NUM_LIT> ; unsigned GroupEnd = GroupStart + <NUM_LIT> ; return Warning ( Ops [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> + RegName + <STR_LIT> + RegName . take_front ( <NUM_LIT> ) + Twine ( GroupStart ) + <STR_LIT> + RegName . take_front ( <NUM_LIT> ) + Twine ( GroupEnd ) + <STR_LIT> ) ; } break ; } } const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; if ( ( MCID . TSFlags & <STR_LIT> ) == <NUM_LIT> ) { MCPhysReg HReg = <STR_LIT> ; bool UsesRex = MCID . TSFlags & <STR_LIT> ; unsigned NumOps = Inst . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { const MCOperand & MO = Inst . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) HReg = Reg ; if ( <STR_LIT> ( Reg ) || <STR_LIT> ( Reg ) ) UsesRex = true ; } if ( UsesRex && HReg != <STR_LIT> ) { StringRef RegName = <ISA_LIT>IntelInstPrinter :: getRegisterName ( HReg ) ; return Error ( Ops [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> + RegName + <STR_LIT> <STR_LIT> ) ; } } return


<s> auto * U = WorkList . pop_back_val ( ) ; if ( & * U == PHIUpdate ) continue ; if ( isa < StoreInst > ( U ) || isa < LoadInst > ( U ) ) continue ; if ( const auto * II = dyn_cast < IntrinsicInst > ( U ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : continue ; default : break ; } } if ( auto * BC = dyn_cast < BitCastInst > ( U ) ) { Type * DstETy = BC -> getDestTy ( ) -> getPointerElementType ( ) ; Type * SrcETy = BC -> getSrcTy ( ) -> getPointerElementType ( ) ; SrcETy = SrcETy -> isArrayTy ( ) ? SrcETy -> getArrayElementType ( ) : SrcETy ; int64_t IVScale = Scale -> getSExtValue ( ) * ECType -> getNumElements


<s> rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg


<s> pAddend = pRel . r_addend ; } else { pOffset = mcld :: bswap64 ( pRel . r_offset ) ; r_info = mcld :: bswap64 ( pRel . r_info ) ; pAddend = mcld :: bswap64 ( pRel . r_addend ) ; } pType = mcld :: bswap32 ( r_info >> <NUM_LIT> ) ; pSymIdx = r_info & <NUM_LIT> ; return true


<s> if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask


<s> cfun -> machine -> some_ld_name = XSTR ( x , <NUM_LIT> ) ; return <NUM_LIT> ; } return <NUM_LIT>


<s> static void buildDefCFAReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned Reg , const <ISA_LIT>InstrInfo * ZII ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineModuleInfo & MMI = MF . getMMI


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 ,

V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg

) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ;


<s> dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; if ( sr . saved ) size -= UNITS_PER_WORD ; HOST_WIDE_INT rounded_size = size & - probe_interval ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ; rtx insn ; if ( address_no_seg_operand ( addr , Pmode ) ) insn = emit_insn ( gen_rtx_SET ( sr . reg , addr ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; insn = emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , sr . reg , m -> fs . cfa_offset + rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx size_rtx = GEN_INT ( rounded_size ) ; insn = emit_insn ( gen_adjust_stack_and_probe ( Pmode , sr . reg , sr . reg , size_rtx ) ) ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) { m -> fs . cfa_offset += rounded_size ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . cfa_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } m -> fs . sp_offset += rounded_size ; emit_insn ( gen_blockage ( ) ) ; if ( size != rounded_size ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( rounded_size - size ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS1 ( SDNode * Op , SDValue N , SDValue

& Base , SDValue & OffImm , SDValue & Offset ) {


<s> if ( ( unsigned long ) LARCH_ACTUAL_TUNE < N_TUNE_TYPES ) return


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) mode = TARGET_32BIT ? SImode : DImode ; return mode


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ; if ( isSVR4ABI ( ) && is64BitMode ( ) ) Fixups . push_back ( MCFixup :: Create

( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> if ( ! CondReg ) return false ; bool CondIsKill = hasTrivialKill ( TI -> getOperand ( <NUM_LIT> ) ) ; if ( SrcVT == <STR_LIT> ) { CondReg = FastEmitInst_extractsubreg ( <STR_LIT> , CondReg , CondIsKill , <STR_LIT> ) ; CondIsKill = true ; } unsigned ANDReg = emitAND_ri ( <STR_LIT> , CondReg , CondIsKill , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; emitICmp_ri ( <STR_LIT> , ANDReg , true , <NUM_LIT> ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CC = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TBB , BranchWeight ) ; FastEmitBranch ( FBB , DbgLoc ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent (


<s> void insertSWIFTRRegisterCheckForJump ( MachineFunction & MF ) { for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { DebugLoc DL3 = MF . begin ( ) -> begin ( ) -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { unsigned int targetReg = <STR_LIT> ; if ( I -> getOpcode ( ) == <STR_LIT> ) targetReg = <STR_LIT> ; else { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; targetReg = I -> getOperand ( <NUM_LIT> ) . getReg


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI )

. addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS2Operand ( const MachineInstr * MI , int Op , raw_ostream & O ) { printThumbAddrModeRI5Operand ( MI , Op ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget (


<s> void <ISA_LIT>AsmPrinter :: NaClAlignIndirectJumpTargets ( MachineFunction & MF ) { if ( MachineJumpTableInfo * JtInfo = MF . getJumpTableInfo ( ) ) { const std :: vector < MachineJumpTableEntry > & JT = JtInfo -> getJumpTables ( ) ; for ( unsigned I = <NUM_LIT> ; I < JT . size (


<s> static inline TOCKey getTombstoneKey ( ) { return { nullptr , MCSymbolRefExpr ::


<s> std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; SDValue RC = Op . getOperand ( <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , LoVT , Lo , RC ) ; Hi = DAG . getNode ( <STR_LIT> , dl , HiVT , Hi


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg (


<s> switch ( get_attr_type ( insn ) ) { case TYPE_DIV : case TYPE_SDIV : case TYPE_DDIV : case


<s> const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo ,


<s> IP -> EndIdx = I -> EndIdx ; IP -> Repl32CR = IP -> Repl32CR || I -> Repl32CR ; IP -> Repl32Coalesced = true ; I = BitGroups . erase ( I ) ; continue ; } else { if ( I -> StartIdx == <NUM_LIT> && I -> EndIdx == <NUM_LIT> ) { assert ( std :: next ( I ) == BitGroups . end ( ) && <STR_LIT> ) ; auto IN = BitGroups . begin ( ) ; if ( IP -> Repl32 && IN -> Repl32 && I -> V == IP -> V && I -> V == IN -> V && ( I -> RLAmt % <NUM_LIT> ) == IP -> RLAmt && ( I -> RLAmt % <NUM_LIT> ) == IN -> RLAmt && IP -> EndIdx == <NUM_LIT> && IN -> StartIdx == <NUM_LIT> && I != IP && IsAllLow32 ( * I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I -> V . getNode ( ) << <STR_LIT> << I -> RLAmt << <STR_LIT> << I -> StartIdx << <STR_LIT> << I -> EndIdx << <STR_LIT> << IP -> StartIdx << <STR_LIT> << IP -> EndIdx << <STR_LIT> << IN -> StartIdx << <STR_LIT> << IN -> EndIdx << <STR_LIT> ) ; if ( IP == IN ) { IP -> StartIdx = <NUM_LIT> ; IP -> EndIdx = <NUM_LIT> ; IP -> Repl32CR = IP -> Repl32CR || I -> RLAmt >= <NUM_LIT> ; IP -> Repl32Coalesced = true ; I = BitGroups . erase ( I ) ; } else { IP -> EndIdx = IN -> EndIdx ; IP -> Repl32CR = IP -> Repl32CR || IN -> Repl32CR || I -> RLAmt >= <NUM_LIT> ; IP -> Repl32Coalesced


<s> if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ( <STR_LIT> , ExtVT . getSizeInBits ( ) / <NUM_LIT> ) ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = -


<s> const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = <NUM_LIT> ; switch ( mode ) { case E_QImode : idx = <NUM_LIT> ; break ; case E_HImode : idx = <NUM_LIT> ; break ; case E_SImode : idx = <NUM_LIT> ; break ; case E_DImode : idx = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case AARCH64_LDOP_PLUS : gen = plus [ idx ] ; break ; case AARCH64_LDOP_XOR : gen = eor [ idx ] ; break ; case AARCH64_LDOP_OR : gen = ior [ idx ] ; break ; case AARCH64_LDOP_BIC : gen = bic [ idx ] ; break ; default : gcc_unreachable (


<s> char * curr_feature_string = xstrdup ( opts -> x_ix86_tune_ctrl_string ) ; char * orig = curr_feature_string ; int i ; do { bool clear = false ; next_feature_string = strchr ( curr_feature_string , ',' ) ; if ( next_feature_string ) * next_feature_string ++ = '\0' ; if ( * curr_feature_string == '^' ) { curr_feature_string ++ ; clear = true ; } for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) { if ( ! strcmp ( curr_feature_string , ix86_tune_feature_names [


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) ,

false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( Flags . memcpy_real_source ) ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsLinux ( IsLinuxOpt ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName


<s> if ( const <ISA_LIT>InstrRelaxTableEntry * I = lookupShortTable ( RelaxOp ) ) return I -> DstOp ; return


<s> ++ NumFP ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI (


<s> return ( __m512i ) __builtin_ia32_pmaxsq512_mask ( ( __v8di ) __A , (


<s> MCRelocationInfo * llvm :: create<ISA_LIT>MachORelocationInfo (


<s> unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . isUndef ( ) ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl

, ResultVT , makeArrayRef ( Vec -> op_begin ( ) + IdxVal , ElemsPerChunk ) ) ;


<s> case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_HA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HA ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HA ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_LO


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( JIT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , isLittle ( isLittle ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) { initAsmInfo (


<s> if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS .

getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ;


<s> pcmpeqw_s ( int32x2_t s , int32x2_t t ) { return __builtin_loongson_pcmpeqw_s ( s , t )


<s> } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; int FrameIdx = MFFrame . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; } return true


<s> tree arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg3 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx op3 = expand_normal ( arg3 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node || arg3 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != mode0 || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode0 ) ) target = gen_reg_rtx ( mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 ,


<s> if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > <NUM_LIT> ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp ) ; frame_rtx = operands [ <NUM_LIT> ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( Pmode , frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_move_insn ( tmp , operands [ <NUM_LIT> ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNO ) , operands [ <NUM_LIT> ] ) ; cfun -> machine -> lr_save_state = info ->


<s> Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isS16 ( Mul . getOperand ( <NUM_LIT> ) , DAG ) ) { Opcode = <STR_LIT> ; Op0 = Mul . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul . getOperand ( <NUM_LIT> ) ; } else if ( isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) && isSRA16 ( Mul . getOperand ( <NUM_LIT> ) ) ) { Opcode = <STR_LIT> ; Op0 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Op1 = Mul -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } if ( ! Op0 || ! Op1 ) return SDValue ( ) ; SDValue SMLAL = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 , Op1 , Lo , Hi ) ; SDValue HiMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; SDValue LoMLALResult ( SMLAL . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) ,


<s> static const Constant * getTargetConstantFromNode ( LoadSDNode * Load ) { if ( ! Load ) return nullptr ; SDValue Ptr = Load -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) == <STR_LIT> ) Ptr = Ptr -> getOperand ( <NUM_LIT> ) ; auto * CNode = dyn_cast < ConstantPoolSDNode > ( Ptr ) ; if ( ! CNode || CNode -> isMachineConstantPoolEntry ( ) || CNode -> getOffset (


<s> case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSPLAT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG


<s> int VectorIndex = <NUM_LIT> ; if ( Subtarget . isLittleEndian ( ) ) VectorIndex = <NUM_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ,

DAG . getTargetConstant ( VectorIndex , dl , <STR_LIT> ) ) ;


<s> break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC =


<s> return __builtin_mve_vbicq_fv4sf ( __a ,


<s> for ( MachineOperand & MO : MI . operands ( ) ) if ( isTilePhysReg


<s> return ( __mmask64 ) __builtin_ia32_cvtb2mask512 ( ( __v64qi )


<s> if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return i


<s> case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; else return CSR_64_AllRegs_SaveList ; } else { if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; else return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList


<s> return FI <= OutArgFIRange . first && FI >= OutArgFIRange .


<s> assert ( RestoreGPRs . LowGPR != RestoreGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( RestoreGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg != RestoreGPRs . LowGPR && Reg != RestoreGPRs . HighGPR && <STR_LIT> . contains ( Reg ) ) MIB . addReg ( Reg


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister


<s> if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return V ; if ( getT2SOImmValSplatVal ( Imm & <NUM_LIT> ) != - <NUM_LIT>


<s> bool ClobbersEFLAGS = Orig . modifiesRegister ( <STR_LIT> , & TRI ) ; if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig


<s> stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; unsigned int orig_count = count ; retval = adjust_cost_for_freq ( stmt_info , where , count * stmt_cost ) ; m_costs [ where ] += retval ; update_target_cost_per_stmt ( kind , stmt_info , where , orig_count ) ; } return retval


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI , MRI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI ,


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT ,

MachineBasicBlock & FMBB , unsigned NumF ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return TT . isOSDarwin ( ) || ReserveX18 ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ; case <STR_LIT> : case <STR_LIT> : return hasBasePointer ( MF ) ; } return false


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction &


<s> static inline uint8_t encodeAdvSIMDModImmType9 ( uint64_t Imm ) { return ( Imm & <NUM_LIT> )


<s> if ( T -> isIntegerTy ( ) ) return true ; if ( T -> isPointerTy (


<s> ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = <NUM_LIT> ; ri_gp_value = <NUM_LIT> ; const MCRegisterInfo * TRI = Context . getRegisterInfo ( ) ; GPR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; AFGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; MSA128BRegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP0RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP2RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP3RegClass = & ( TRI -> getRegClass ( <STR_LIT>


<s> Error ( CantUnwindLoc , <STR_LIT> ) ; return true ; } getTargetStreamer ( ) . emitHandlerData ( ) ; return false


<s> for ( int i = ( <NUM_LIT> - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) Ostream

<< static_cast < char > ( ( Value >> i ) & <NUM_LIT> ) ;


<s> typedef unsigned int uv4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return __builtin_sh_media_MMULSUM_WQ ( ( uv4hi ) mm ,


<s> static <ISA_LIT>Operand CreateImm ( MCValue Val ) { <ISA_LIT>Operand Res ; Res . Kind


<s> return hasSVE ( ) && getMinSVEVectorSizeInBits ( ) >=


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , IntEltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , IntEltVT ) ; if ( EltVT . isFloatingPoint ( ) ) { Zero = DAG . getNode ( <STR_LIT> , DL , EltVT , Zero ) ; AllOnes = DAG . getNode ( <STR_LIT> , DL , EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V


<s> const <ISA_LIT>MCSymbolRefExpr * <ISA_LIT>MCSymbolRefExpr :: Create ( VariantKind Kind , const

MCSymbol * Symbol , int Offset , MCContext & Ctx ) {


<s> bool hasFP16FML ( ) const { return HasFP16FML


<s> if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * TRI . legalclasstypes_begin ( * RC ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first , MMOs . second ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs .


<s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } return


<s> return MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ->


<s> SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , dl , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; return DAG . getFPExtendOrRound ( Sub , dl , Op . getSimpleValueType ( )


<s> SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue StoreChain = DAG . getEntryNode ( ) ; SDValue Ops [ ] = { StoreChain , DAG . getConstant ( <STR_LIT>


<s> void <ISA_LIT>TargetLowering :: LowerFP_TO_INTForReuse ( SDValue Op , ReuseLoadInfo & RLI , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; Align Alignment ( DAG . getEVTAlign ( Tmp .


<s> int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT> ) ; return ; } assert ( pos < <NUM_LIT> && <STR_LIT> ) ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( size - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT>


<s> const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN64 ( ) ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) , GV -> isThreadLocal ( ) ) ; if ( Subtarget . useXGOT ( ) || HugeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , GV -> isThreadLocal ( ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction


<s> void <ISA_LIT>HazardRecognizer970 :: Reset ( ) { LastWasBL8_ELF = false ; EndDispatchGroup (


<s> if ( ! RM . hasValue ( ) ) return Reloc ::


<s> static MachineInstr * insertCopy ( const <ISA_LIT>InstrInfo * TII , MachineInstr * MI , unsigned Dst , unsigned Src , bool IsKill ) { MachineInstrBuilder MIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get

( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ;


<s> int RegisterWidth = VecVT . getSizeInBits ( ) ; int NumElts = VecVT . getVectorNumElements ( ) ; int FieldWidth = RegisterWidth / NumElts ; if ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) { SDValue TransV = DAG . getNode ( <STR_LIT> , dl , FullVT , Vec ) ; SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , FullVT , TransV , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , FullVT , ShiftV , DAG . getConstant ( <NUM_LIT> , FullVT ) ) ) ; } else { assert ( VecVT . getVectorElementType ( ) . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; Idx = getTruncateOrZeroExtend ( Idx , DAG


<s> SDLoc DL ( Store ) ; SDValue Value0 = extractSubVector ( StoredVal , <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Value1 = extractSubVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment

, Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> MaxLoadSize = ST -> is64Bit ( ) ? <NUM_LIT> :


prefix , asm_switch -> name , suffix ) ;


<s> return new <ISA_LIT>ConstantPoolSymbol ( C , s , <NUM_LIT> ,


<s> const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize


<s> if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2StsMap [ Base ] . push_back ( MI ) ; StBases . push_back ( Base ) ; } } if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear ( ) ; LdBases . clear (


<s> return Mask && Mask -> getValue ( ) . isIntN


<s> HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasADX = false ; IsBTMemSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PostRAScheduler = false ; PadShortFunctions =


<s> if ( ! LD || LD -> getExtensionType ( ) != ET || LD -> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ; if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsDereferenceable = LD -> isDereferenceable ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD -> getAlign ( ) ; RLI . AAInfo = LD -> getAAInfo ( ) ; RLI . Ranges = LD -> getRanges ( ) ; RLI . ResChain = SDValue ( LD , LD -> isIndexed ( ) ? <NUM_LIT> :


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSLinux ( ) ) return make_unique < <ISA_LIT>LinuxTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return make_unique < TargetLoweringObjectFileELF > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile


<s> static machine_mode mode_from_flags ( unsigned int f ) { if ( f & CC_FLAG_FP ) return CC_Fmode ; if ( f &


<s> const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> * cost_scale ; int i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , <NUM_LIT> ) ) || satisfies_constraint_J16 ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; else return <NUM_LIT> + rtx_cost ( XEXP ( x , <NUM_LIT> ) , AND , <NUM_LIT> , ! optimize_size ) ; } if ( ( i == <NUM_LIT> || i == <NUM_LIT> ) && code == AND ) return <NUM_LIT> * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return <NUM_LIT> * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return <NUM_LIT> *


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>leTargetMachine > X ( The<ISA_LIT>leTarget ) ; RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ; RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z (


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return DAG . getIntPtrConstant ( <NUM_LIT> * <NUM_LIT> ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) ,


<s> } if ( RC == & <STR_LIT> && EnableGPRToVecSpills ) InflateGPRC ++ ; } if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> && Subtarget . hasP8Vector ( ) ) return & <STR_LIT> ; } return TargetRegisterInfo :: getLargestLegalSuperClass (


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( Subtarget . hasAVX2 ( )


<s> Args . reserve ( NumArgs ) ; ArgRegs . reserve ( NumArgs ) ; ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs ; i != ie ; ++ i ) { <STR_LIT> Flags = CLI . OutFlags [ i ] ; if ( Flags . isInReg ( ) || Flags . isSRet ( ) || Flags . isNest ( ) || Flags . isByVal ( ) ) return false ; Value * ArgValue = CLI . OutVals [ i ] ; Type * ArgTy = ArgValue -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder MIB ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) { if ( CLI . IsPatchPoint ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; else return false ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; } for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; EVT CarryVT = Carry . getValueType ( ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getAllOnesConstant


<s> static void mips_annotate_pic_calls ( void ) { basic_block bb ; rtx_insn * insn ; FOR_EACH_BB_FN ( bb , cfun ) FOR_BB_INSNS ( bb , insn ) { rtx call , reg , symbol , second_call ; second_call = <NUM_LIT> ; call = mips_call_expr_from_insn ( insn , & second_call ) ; if ( ! call ) continue ; gcc_assert ( MEM_P ( XEXP ( call , <NUM_LIT> ) ) ) ; reg = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! REG_P ( reg ) ) continue ; symbol = mips_find_pic_call_symbol ( insn , reg , true ) ; if ( symbol ) { mips_annotate_pic_call_expr ( call , symbol ) ; if ( second_call ) mips_annotate_pic_call_expr ( second_call


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; assert ( ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> )


<s> return false ; case <STR_LIT> : ExpandRetRA ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : ExpandBuildPairF64 ( MBB , MI ) ; break ; case <STR_LIT> : ExpandExtractElementF64 ( MBB


<s> rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , true ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv4sf


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetLinux ( ) )

return TargetLowering :: insertSSPDeclarations ( M ) ;


<s> if ( ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ROOTNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) return SDValue ( ) ; SDValue Mult = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; SDValue AddOperand = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; if ( ! Mult . hasOneUse ( ) ) return SDValue ( ) ; SDValue MultLHS = Mult -> getOperand ( <NUM_LIT> ) ; SDValue MultRHS = Mult -> getOperand ( <NUM_LIT> ) ; bool IsSigned = MultLHS -> getOpcode ( ) == <STR_LIT> && MultRHS -> getOpcode ( ) == <STR_LIT> ; bool IsUnsigned = MultLHS -> getOpcode ( ) == <STR_LIT> && MultRHS -> getOpcode ( ) == <STR_LIT> ; if ( ! IsSigned && ! IsUnsigned ) return SDValue ( ) ; SDLoc DL ( ROOTNode


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , FK_Data_4 ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , (

MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> void setVarArgsRegSaveSize ( unsigned


<s> emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_3b ( tmp2 , tmp1 , got , lab ) ) ; emit_insn ( gen_load_toc_v4_PIC_3c ( dest , tmp2 , got , lab ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { emit_insn ( gen_load_toc_v4_pic_si ( ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_insn ( gen_load_toc_v4_PIC_1 ( symF ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ; } else { rtx tocsym , lab ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( toc_label_name ) ) ; need_toc_init = <NUM_LIT> ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tocsym , lab ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( dest , dest , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; } emit_insn ( gen_addsi3 ( dest , temp0 , dest ) ) ; } else if ( TARGET_ELF && ! TARGET_AIX && flag_pic == <NUM_LIT> && TARGET_MINIMAL_TOC ) { rtx realsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( toc_label_name ) ) ; need_toc_init = <NUM_LIT> ; emit_insn ( gen_elf_high ( dest , realsym )


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm


<s> bool isBDRAddr64Disp12 ( ) const { return isMemDisp12 ( BDRMem ,


<s> bool isU7ImmX4 ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && ( getImm


<s> DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> ; if ( Available . size ( ) == <NUM_LIT> ) dbgs ( ) << <STR_LIT> ; Candidate c ( SU


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy


<s> break ; case PROCESSOR_POWER6 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_EXTS : case TYPE_CNTLZ : case TYPE_TRAP : case TYPE_MUL : case TYPE_FPCOMPARE : case TYPE_MFCR : case TYPE_MTCR : case TYPE_MFJMPR : case TYPE_MTJMPR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_SHIFT : if ( get_attr_dot ( insn ) == DOT_NO || get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) return true ; else break ; case TYPE_DIV : if ( get_attr_size ( insn ) == SIZE_32 ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER7 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MTCR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * SI ) const { return


<s> Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , <STR_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } MCBinaryExpr :: Opcode Opcode ; switch ( Tok . getKind ( ) ) { case AsmToken :: Plus : Opcode = MCBinaryExpr :: Add ; Parser . Lex ( ) ; break ; case AsmToken :: Minus : Opcode = MCBinaryExpr :: Sub ; Parser . Lex ( ) ; break ; case AsmToken :: Star : Opcode = MCBinaryExpr :: Mul ; Parser . Lex ( ) ; break ; case AsmToken :: Pipe : Opcode = MCBinaryExpr :: Or ; Parser . Lex ( ) ; break ; case AsmToken :: Amp : Opcode = MCBinaryExpr :: And ; Parser . Lex ( ) ; break ; case AsmToken :: LessLess : Opcode = MCBinaryExpr :: Shl ; Parser . Lex ( ) ; break ; case AsmToken :: GreaterGreater : Opcode = MCBinaryExpr :: LShr ; Parser . Lex ( ) ; break ; case AsmToken :: Caret : Opcode = MCBinaryExpr :: Xor ; Parser . Lex ( ) ; break ; case AsmToken ::


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer &


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( )


<s> Scale = Scale & ~ <NUM_LIT> ; return Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ; case <STR_LIT> : if ( Scale == <NUM_LIT> ) return true ; if ( ! AM . HasBaseReg && Scale == <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT>


<s> SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getNode ( <STR_LIT> , DL , VT ,


<s> if ( known_eq ( width , <NUM_LIT> ) ) switch ( mode ) { case E_DFmode : return V2DFmode ; case E_SFmode : return V4SFmode ; case E_HFmode : return V8HFmode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : break ; } else switch ( mode ) { case E_SFmode : return V2SFmode ; case E_HFmode : return V4HFmode ; case E_SImode : return V2SImode ; case


<s> case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair


<s> static unsigned int aarch64_estimated_sve_vq ( ) { return estimated_poly_value ( BITS_PER_SVE_VECTOR ) /


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction &


<s> return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && UseSSEReg && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return true


<s> return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT>


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv2di ( __a )


<s> unsigned OrigBROpcode = BSI . OrigBranch -> getOpcode ( ) ; unsigned InvertedOpcode = OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned NewBROpcode = BSI . InvertNewBranch ? InvertedOpcode : OrigBROpcode ; MachineBasicBlock * OrigTarget = BSI . OrigBranch -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * OrigFallThrough = OrigTarget == * ThisMBB -> succ_begin ( ) ? * ThisMBB -> succ_rbegin ( ) : * ThisMBB -> succ_begin ( ) ; MachineBasicBlock * NewBRTarget = BSI . BranchToFallThrough ? OrigFallThrough : OrigTarget ; BranchProbability ProbToNewTarget = ! BSI . MBPI ? BranchProbability :: getUnknown ( ) : BSI . MBPI -> getEdgeProbability ( ThisMBB , NewBRTarget ) ; MachineBasicBlock :: iterator InsertPoint = BSI . SplitBefore ; const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ThisMBB -> getIterator ( ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( ++ It , NewMBB ) ; NewMBB -> splice ( NewMBB -> end ( ) , ThisMBB , InsertPoint , ThisMBB -> end ( ) ) ; NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; findPotentiallylBlockedCopies ( MF ) ; for ( auto LoadStoreInstPair : BlockedLoadsStoresPairs ) { MachineInstr * LoadInst = LoadStoreInstPair . first ; int64_t LdDispImm = getDispOperand ( LoadInst ) . getImm ( ) ; DisplacementSizeMap BlockingStoresDispSizeMap ; SmallVector < MachineInstr * , <NUM_LIT> > PotentialBlockers = findPotentialBlockers ( LoadInst ) ; for ( auto PBInst : PotentialBlockers ) { if ( ! isPotentialBlockingStoreInst ( PBInst -> getOpcode ( ) , LoadInst -> getOpcode ( ) ) || ! isRelevantAddressingMode ( PBInst ) ) continue ; int64_t PBstDispImm = getDispOperand ( PBInst ) . getImm ( ) ; assert ( PBInst -> hasOneMemOperand ( ) && <STR_LIT> ) ; unsigned PBstSize = ( * PBInst -> memoperands_begin ( ) ) -> getSize ( ) ; if ( hasSameBaseOpValue ( LoadInst , PBInst ) && isBlockingStore ( LdDispImm , getRegSizeInBytes ( LoadInst ) , PBstDispImm , PBstSize ) ) updateBlockingStoresDispSizeMap ( BlockingStoresDispSizeMap , PBstDispImm , PBstSize ) ; } if ( BlockingStoresDispSizeMap . empty ( ) ) continue ; MachineInstr * StoreInst = LoadStoreInstPair . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadInst -> dump ( ) ) ; LLVM_DEBUG ( StoreInst -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; removeRedundantBlockingStores ( BlockingStoresDispSizeMap ) ; breakBlockedCopies ( LoadInst , StoreInst , BlockingStoresDispSizeMap ) ; updateKillStatus ( LoadInst , StoreInst ) ; ForRemoval . push_back ( LoadInst ) ; ForRemoval . push_back ( StoreInst ) ; } for ( auto RemovedInst : ForRemoval ) { RemovedInst -> eraseFromParent ( ) ; } ForRemoval . clear ( )


<s> V8DeprecatedInsts = false ; IsVIS = false ; std :: string CPU = <STR_LIT> ; CPU =


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count /


<s> GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( ! G ) return false ; if ( CodeModel :: Medium == TM . getCodeModel ( ) || CodeModel :: Large == TM . getCodeModel ( ) ) return TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , G -> getGlobal ( ) ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! GV -> isStrongDefinitionForLinker ( ) ) return false ; if ( TM . getFunctionSections ( ) || GV -> hasComdat ( ) || Caller -> hasComdat ( ) || GV -> getSection ( ) != Caller -> getSection ( ) ) return false ; if ( const auto * F = dyn_cast < Function > ( GV ) ) { if ( F -> getSectionPrefix ( ) != Caller -> getSectionPrefix ( ) ) return false ; } if ( ! TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) ,


<s> return __builtin_mve_vldrbq_z_uv8hi ( ( __builtin_neon_qi *


<s> return CC_<ISA_LIT>_GHC ; case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: PreserveMost : case CallingConv :: CXX_FAST_TLS : case CallingConv :: Swift : if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; if ( ! IsVarArg ) return CC_<ISA_LIT>_DarwinPCS ; return Subtarget -> isTargetILP32 ( ) ?


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger


<s> O << '\n' ; if ( ! GVNonLazyPtrs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( StringMap < std :: string > :: iterator I = GVNonLazyPtrs . begin ( ) , E = GVNonLazyPtrs . end ( ) ; I != E ; ++ I ) { O << I -> second << <STR_LIT> ; O << <STR_LIT> << I -> getKeyData ( ) << <STR_LIT> ; O <<


<s> uint64_t ByteA = Imm & <NUM_LIT> ; uint64_t ByteB = Imm & <NUM_LIT> ; uint64_t ByteC = Imm & <NUM_LIT> ; uint64_t ByteD = Imm & <NUM_LIT> ; uint64_t ByteE = Imm & <NUM_LIT> ; uint64_t ByteF = Imm & <NUM_LIT> ; uint64_t ByteG = Imm & <NUM_LIT>


<s> return __builtin_ia32_vcvtdq2ph256_mask ( ( __v8si ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) -


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_BRJT && <STR_LIT> ) ; Register JTAddr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned JTI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; Register Index = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setJumpTableEntryInfo ( JTI , <NUM_LIT> , nullptr ) ; auto JumpTableInst = MIB . buildInstr ( <STR_LIT> , { TargetReg , ScratchReg } , { JTAddr , Index } ) . addJumpTableIndex ( JTI ) ; MIB . buildInstr ( <STR_LIT> , { } , { TargetReg } ) ; I . eraseFromParent (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) ,

Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI = MBB ; if ( llvm :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = llvm :: next ( MBBI


<s> SMLoc TagLoc ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { StringRef Name = Parser . getTok ( ) . getIdentifier ( ) ; Tag = <STR_LIT> ( Name ) ; if ( Tag == - <NUM_LIT> ) { Error ( TagLoc , <STR_LIT> + Name ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( ! CE ) { Error ( TagLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Tag = CE -> getValue ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; StringRef StringValue = <STR_LIT> ; bool IsStringValue = false ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = false ; if ( Tag == <STR_LIT> || Tag == <STR_LIT> ) IsStringValue = true ; else if ( Tag == <STR_LIT> ) { IsStringValue = true ; IsIntegerValue = true ; } else if ( Tag < <NUM_LIT> || Tag % <NUM_LIT> == <NUM_LIT> ) IsIntegerValue = true ; else if ( Tag % <NUM_LIT> == <NUM_LIT> ) IsStringValue = true ; else llvm_unreachable ( <STR_LIT>


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * ImmVal ; if ( Parser . parseExpression ( ImmVal ) || ! isa < MCConstantExpr > ( ImmVal ) || cast < MCConstantExpr > ( ImmVal )


<s> rtx last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE

) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back (


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OS .


<s> if ( mode1 == PTImode || mode1 == OOmode || mode1 == XOmode || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode ) return mode1 == mode2 ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2


<s> MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition


<s> else if ( selected_cpu ) { const char * truncated_name = aarch64_rewrite_selected_cpu ( selected_cpu -> name ) ; asm_fprintf ( asm_out_file , <STR_LIT> , truncated_name ) ; aarch64_print_extension (


<s> if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == - <NUM_LIT> ) x = XEXP ( x , <NUM_LIT> ) ; if ( RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && ! ALTIVEC_VECTOR_MODE ( mode ) && ! SPE_VECTOR_MODE ( mode ) && ! ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DImode ) ) && TARGET_UPDATE && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( rs6000_legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( legitimate_constant_pool_address_p ( x )


<s> orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , <NUM_LIT> ) ) ) { offset = XEXP ( y , <NUM_LIT> ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , <NUM_LIT> ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP


<s> static struct register_pass_info f = { p , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; register_pass ( & f


<s> auto AllowContract = [ & DAG ] ( SDNode * N ) { return DAG . getTarget ( ) . Options . AllowFPOpFusion == FPOpFusion :: Fast || N -> getFlags ( ) . hasAllowContract ( ) ; } ; if ( N -> getOpcode ( ) != <STR_LIT> || ! Subtarget . hasFP16 ( ) || ! AllowContract ( N ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue CFmul


<s> BuildMI ( MBB , I , DL , get ( Opc ) ,

DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> break ; } case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ) ; break ; case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; case <STR_LIT> : emitConstPoolInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI ,


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_empty ( void ) { __builtin_ia32_emms (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) ==


<s> if ( LP64 ) { if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } MBB . erase (


<s> if ( isNeg ) return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( ( V & <NUM_LIT> ) != <NUM_LIT>


<s> unsigned RsReg = RsRegOp . getReg ( ) ; unsigned RtReg ; int64_t ImmValue ; const MCOperand & RtOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( RtOp . isReg ( ) || RtOp . isImm ( ) ) && <STR_LIT> ) ; if ( RtOp . isReg ( ) ) RtReg = RtOp . getReg ( ) ; else ImmValue = RtOp . getImm ( ) ; unsigned DivOp ; unsigned ZeroReg ; unsigned SubOp ; if ( Is<ISA_LIT>64 ) { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } else { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } bool UseTraps = useTraps ( ) ; unsigned Opcode = Inst . getOpcode ( ) ; bool isDiv = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isRem = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( RtOp . isImm ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( ImmValue == <NUM_LIT> ) { if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( isRem && ( ImmValue == <NUM_LIT> || ( Signed && ( ImmValue == - <NUM_LIT> ) ) ) ) { TOut . emitRRR ( <STR_LIT> , RdReg , ZeroReg , ZeroReg , IDLoc , STI ) ; return false ; } else if ( isDiv && ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( isDiv && Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } TOut . emitII ( <STR_LIT> , <NUM_LIT> ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue <ISA_LIT>CC ; SDValue Flag = EmitCmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueV ) ; Ops . push_back ( FalseV