<s> const LLT ShiftTy = MRI . getType ( ShiftReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy . isVector ( ) ) return false ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; auto * AmtMI = MRI . getVRegDef ( ShiftReg ) ; assert ( AmtMI && <STR_LIT> ) ; if ( AmtMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { MachineIRBuilder MIB ( I ) ; auto Trunc = MIB . buildInstr ( TargetOpcode :: COPY , { SrcTy } , { } ) . addReg ( ShiftReg , <NUM_LIT> , <STR_LIT> ) ; MRI . setRegBank ( Trunc . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( Trunc . getReg ( <NUM_LIT> ) ) ; } return true ; } case TargetOpcode :: G_STORE : return contractCrossBankCopyIntoStore ( I , MRI ) ; case TargetOpcode :: G_PTR_ADD : return convertPtrAddToAdd ( I , MRI ) ; default : return


<s> static __inline qword si_rotqbii ( qword a , int count ) { vec_uchar16 x , y ; vec_uchar16 result ; x = vec_splat ( ( vec_uchar16 ) ( si_from_int ( count & <NUM_LIT> ) ) , <NUM_LIT> ) ; y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) )

) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> else op [ o ] = args [ ( int ) hex_value ( ao ) ] ; if ( ! ( * insn_data [ code ] . operand [ o ] . predicate ) ( op [ o ] , GET_MODE ( op [ o ] ) ) ) { if ( c == '+' || c == '=' ) { copyto [ o ] = op [ o ] ; op [ o ] = gen_reg_rtx ( omode ) ; } else op [ o ] = copy_to_mode_reg ( omode , op [ o ] ) ; } if ( ao == 'r' ) retval = op [ o ] ; } pat = GEN_FCN ( code ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; emit_insn ( pat ) ; for ( o = <NUM_LIT> ; s16builtins [ i ] . arg_ops [ o ] ; o ++ ) if ( copyto [ o ] ) { emit_move_insn ( copyto [ o ] , op [ o ] ) ; if ( op [ o ] == retval ) retval = copyto [ o ] ; } return retval


, short __q02 , short __q01 , short __q00 ) {


<s> static void aarch64_emit_mult ( rtx dst , rtx ptrue , rtx src1 , rtx src2 ) { if ( ptrue ) emit_insn ( gen_aarch64_pred ( UNSPEC_COND_FMUL , GET_MODE ( dst ) , dst , ptrue , src1 , src2 , gen_int_mode ( SVE_RELAXED_GP , SImode ) ) ) ; else emit_set_insn ( dst , gen_rtx_MULT ( GET_MODE ( dst


<s> SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , EVT ) ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; unsigned NumDefs = TID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = TID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn )


<s> machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op .


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> if ( nonfinite ( z ) ) return z ; x . dval [ <NUM_LIT> ] = z ; zz = aa + cc ; if ( fabs ( a ) > fabs ( c ) ) x . dval [ <NUM_LIT> ] = a - z + c + zz ; else x . dval [ <NUM_LIT> ] = c - z + a + zz ; } else { q = a - z ; zz = q + c + ( a - ( q + z ) ) + aa + cc ; if ( zz == <NUM_LIT> ) return z ; xh = z + zz ; if ( nonfinite ( xh ) )


<s> MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand


<s> return ( __m512i ) __builtin_ia32_pmovsxbw512_mask ( ( __v32qi ) __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32


<s> SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , SDLoc ( MemcpyCall ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; return


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } const MCSection * StaticInitSect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_REGULAR | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection (


<s> unsigned IndexSize = DL . getPointerSizeInBits ( ) ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext


<s> Name += Suffix ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) :


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS

, false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> bool <ISA_LIT>16TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const { return false


<s> <ISA_LIT>ConstantPoolValue :: ~ <ISA_LIT>ConstantPoolValue ( ) { free ( ( void *


<s> const REAL_VALUE_TYPE * r ; if ( ! ( CONST_DOUBLE_P ( x ) && X87_FLOAT_MODE_P ( mode ) ) ) return - <NUM_LIT> ; if ( x == CONST0_RTX ( mode ) ) return <NUM_LIT> ; if ( x == CONST1_RTX ( mode ) ) return <NUM_LIT> ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( mode == XFmode && ( optimize_function_for_size_p ( cfun ) || TARGET_EXT_80387_CONSTANTS ) && ! flag_rounding_math ) { int


<s> switch ( CC ) { default : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode *


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INTDirectMove ( SDValue Op , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( )


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = isOneConstant ( RHS ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } if ( BaseOp ) { SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; Value = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; Overflow = Value . getValue ( <NUM_LIT> ) ; } return std :: make_pair (


<s> if ( BB_HEAD ( bb ) == insn ) BB_HEAD ( bb ) = b ; if ( BB_END ( bb ) == insn ) BB_END ( bb ) = a ; } if ( insn == BB_END ( bb ) ) break ; insn = NEXT_INSN ( insn


<s> switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { bool Changed = false ; Changed |= Helper . tryCombineExtendingLoads ( MI ) ; Changed |= Helper . tryCombineIndexedLoadStore ( MI ) ; return Changed ; } case TargetOpcode :: G_STORE : return Helper . tryCombineIndexedLoadStore ( MI ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt ? <NUM_LIT>


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isABI_N64 ( ) || Subtarget . isABI_N32 ( ) ) ReginfoSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP ,


<s> return ( ( optimize_size || arm_ld_sched )


<s> virtual <ISA_LIT>JITInfo * getJITInfo (


<s> enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return <NUM_LIT> ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) ) return arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && REG_P ( addend ) ) return <NUM_LIT> ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( ( CONST_INT_P ( xop1 ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE (


<s> return SrcAS < <NUM_LIT> && DestAS <


<s> tree gimple_folder :: force_vector ( gimple_seq & stmts , tree vectype , tree value ) { if ( ! VECTOR_TYPE_P ( TREE_TYPE ( value ) ) ) value = gimple_build_vector_from_val ( & stmts , vectype


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getMcpu ( )


<s> case ORDERED : * code = reverse_condition_maybe_unordered ( * code ) ; return true


<s> void <ISA_LIT>InstructionSelector :: renderFPImm64 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getFPImm (


<s> SmallVector < std :: pair < unsigned , std :: string > , <NUM_LIT> > MapAndConstraints ; bool Error = MatchInstruction ( IDLoc , Operands , Out , Kind ,

Opcode , MapAndConstraints , ErrorInfo ) ;


<s> if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS

) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ;


<s> if ( ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasOpaqueSPAdjustment ( ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned BaseReg = TRI -> getBaseRegister ( ) ; for ( unsigned R : ClobberSet ) if ( BaseReg == R ) return true ; return false


<s> if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg2 = AvailableRegs . pop_back_val ( ) ; unsigned SaveReg1 = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg1 , SaveReg2 ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( SaveReg1 , RegState :: Define ) . addReg ( SaveReg2 , RegState :: Define ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { if ( AvailableRegs . size ( ) >= <NUM_LIT> ) { unsigned SaveReg = AvailableRegs . pop_back_val ( ) ; ClearedFPRegs . emplace_back ( Reg , SaveReg , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( Reg ) . add ( predOps ( <STR_LIT> ) ) ; } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm (

Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand ::


<s> void addImmOperands ( MCInst & Inst , unsigned N )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst ShlInst , FenceInst ; bool Parse32 = is32BitMode ( ) || Code16GCC ; unsigned Basereg = is64BitMode ( ) ? <STR_LIT> : ( Parse32 ? <STR_LIT> : <STR_LIT> ) ; const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; auto ShlMemOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT> , <NUM_LIT> , SMLoc { } , SMLoc { } , <NUM_LIT> ) ; ShlInst . setOpcode ( <STR_LIT> ) ; ShlMemOp -> addMemOperands ( ShlInst , <NUM_LIT> ) ; ShlInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; FenceInst . setOpcode ( <STR_LIT> ) ; Out . emitInstruction ( ShlInst , getSTI ( ) ) ; Out . emitInstruction ( FenceInst , getSTI (


<s> if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) { ShuffleMask . clear ( ) ; return ; } if ( isa < UndefValue > ( COp ) ) ShuffleMask . push_back ( SM_SentinelUndef ) ; else { APInt Element = cast < ConstantInt > ( COp ) -> getValue ( ) ; Element = Element . getLoBits ( EltMaskSize ) ; ShuffleMask . push_back ( Element .


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return BB


<s> offset -= <NUM_LIT> ; } if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) { rtx tmpreg , retreg ; rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } tmpreg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; retreg = gen_rtx_REG ( DImode , MMIX_rJ_REGNUM ) ; emit_move_insn ( tmpreg , retreg ) ; insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , tmpreg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , retreg ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -= <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_REG ( DImode , <NUM_LIT> ) , gen_rtx_REG ( DImode , MMIX_rO_REGNUM ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ; offset -= <NUM_LIT> ; } offset -= ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = ( stack_space_to_allocate > ( <NUM_LIT> - offset - <NUM_LIT> ) ?

( <NUM_LIT> - offset - <NUM_LIT> ) : stack_space_to_allocate ) ;


<s> args . reserve ( nargs ) ; for ( unsigned int i = <NUM_LIT> ; i < nargs ; ++ i ) args . quick_push ( expand_normal ( CALL_EXPR_ARG ( call_expr , i ) ) ) ; return base -> expand ( * this


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> IsConstant = true ; Imm = CE -> getValue ( ) ; } if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr )


<s> Type * Ty = I -> getType ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getVectorNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) , Mask -> getType ( ) } , { Ptr , Builder .


<s> vtst_p64 ( poly64x1_t a , poly64x1_t b ) { return ( uint64x1_t ) ( ( a & b ) != __AARCH64_INT64_C (


<s> if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value


<s> CurrentSection = nullptr ; CachedEntries . clear ( )


<s> BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> eraseFromParent ( ) ; MadeChange = true ; } if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { MI -> eraseFromParent ( ) ; MadeChange =


<s> unsigned getNumFixupKinds ( ) const { return


<s> assert ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else llvm_unreachable ( <STR_LIT>


<s> if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; if ( ! TM . getDataSections ( ) ) OutStreamer -> emitLabel ( EmittedInitSym ) ; llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const


<s> } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } } if ( Opcode == Instruction :: FRem ) { unsigned Cost = ( VF * LIBCALL_COST ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> && ScalarBits == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } } else { if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) return <NUM_LIT> ; if ( Opcode == Instruction :: FRem ) return LIBCALL_COST ; if ( Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) return ( ScalarBits >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: Or ) return <NUM_LIT> ; if ( Opcode == Instruction :: Xor && ScalarBits


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum +


<s> HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT>

&& CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: parseSetReorderDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setReorder (


<s> if ( ResultPtr >= <NUM_LIT> ) * ( ( intptr_t * ) RelocPos ) |= <NUM_LIT> << <STR_LIT> ; else { * ( ( intptr_t * ) RelocPos ) &= ~ ( <NUM_LIT> << <STR_LIT> ) ; ResultPtr = - ResultPtr ; } if ( MR -> getRelocationType ( ) == <STR_LIT> ) ResultPtr = ResultPtr >> <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; * ( ( intptr_t * ) RelocPos ) |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { * ( ( intptr_t * ) RelocPos ) |= ( intptr_t ) ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; ResultPtr = ( ResultPtr & <NUM_LIT> ) >> <NUM_LIT> ; assert ( ResultPtr >= - <NUM_LIT> && ResultPtr <= <NUM_LIT> ) ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; * ( ( intptr_t * )


<s> } else if ( type == TYPE_IMM ) { switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_IW : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_ID : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_IO : break ; } } switch ( type ) { case TYPE_XMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_YMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_ZMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; default : break ; } if ( ! tryAddingSymbolicOperand ( immediate + pcrel , isBranch , insn . startLocation , insn . immediateOffset , insn . immediateSize , mcInst , Dis ) ) mcInst . addOperand ( MCOperand :: createImm ( immediate ) ) ; if ( type == TYPE_MOFFS ) { MCOperand segmentReg ; segmentReg = MCOperand :: createReg ( segmentRegnums [ insn . segmentOverride ] ) ; mcInst . addOperand (


<s> unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; } return


<s> return __builtin_aarch64_lceiluv2dfv2di_us (


<s> return __builtin_mve_vrndaq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , Align ( <NUM_LIT> ) , false , false , false , false , MachinePointerInfo

( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; llvm :: sort ( Candidates , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti || Candidate -> CanMergeToLSDouble ) { MachineInstr * Merged = MergeOpsUpdate ( * Candidate ) ; if ( Merged ) { Changed = true ; unsigned Opcode = Merged -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MergeBaseUpdateLSDouble ( * Merged ) ; else MergeBaseUpdateLSMultiple ( Merged ) ; } else { for ( MachineInstr * MI : Candidate -> Instrs ) { if ( MergeBaseUpdateLoadStore ( MI ) ) Changed = true ; } } } else { assert ( Candidate -> Instrs . size ( ) == <NUM_LIT> ) ; if ( MergeBaseUpdateLoadStore ( Candidate -> Instrs . front ( ) ) ) Changed = true ; } } Candidates . clear ( ) ; for ( MachineInstr * MI : MergeBaseCandidates )


<s> assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI , true


<s> return parseRegister ( Operands , RegGR , <STR_LIT> ,


<s> MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . dropDebugNumber ( ) ; if ( KillsOp0 ) freeStackSlotAfter ( I , Op0 ) ; if ( KillsOp1 && Op0 != Op1 )


<s> const MachineBasicBlock * MBB = Inst . getParent ( ) ; const MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * MI1 = MRI . getUniqueVRegDef ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MI2 = MRI . getUniqueVRegDef ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AssocOpcode = Inst . getOpcode ( ) ; Commuted = MI1 -> getOpcode ( ) != AssocOpcode && MI2 -> getOpcode ( ) == AssocOpcode ; if ( Commuted ) std :: swap ( MI1 , MI2 ) ; if ( MI1 -> getOpcode ( ) == AssocOpcode && hasReassociableOperands ( * MI1 , MBB ) && MRI . hasOneNonDBGUse ( MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ; return


<s> if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - <NUM_LIT> ) ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF )


<s> AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV8Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV7Ops ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV6T2Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV6Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TEOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV4TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasNEON ( ) && emitFPU ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> ,


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes - <NUM_LIT> - i ) ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) &


<s> } else if ( write_symbols == DBX_DEBUG ) return ; else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ; fprintf ( stream , <STR_LIT> , num_source_filenames ) ; output_quoted_string ( stream


<s> return is<ISA_LIT>64 ( ) ? <STR_LIT>


<s> default : break ; case CmpInst :: FCMP_UEQ : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_ONE : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } if ( CondCodes ) { unsigned TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg1 , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC = getCompareCC ( Predicate ) ; assert ( ( CC !=


<s> donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , <NUM_LIT> , neglab ) ; expand_float ( out , in , <NUM_LIT> ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx ,


<s> bool isMasterReg ( unsigned int reg ) { for ( int i = <NUM_LIT> ; i < functionCallArgs . size ( ) ; ++

i ) if ( functionCallArgs [ i ] == reg ) return true ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString =


<s> if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return <NUM_LIT> ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? <NUM_LIT> : <NUM_LIT> ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( zero_constant ( op , mode ) )


<s> unsigned <ISA_LIT>16InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return <NUM_LIT>


<s> return ( vector unsigned int ) __builtin_altivec_vadduws ( ( vector signed int )


<s> OS << V . getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << '+' ; printOperand ( MI ,


<s> getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false


<s> SMLoc S = Tok . getLoc ( ) ; if ( isOperandRegister ( Tok ) ) { if ( ParseRegisterOperand ( & Operands , <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( parseMemOffset ( IdVal ) ) return MatchOperand_ParseFail ; if ( std :: string ( Parser . getTok ( ) . getString ( ) ) != <STR_LIT> ) { Error ( Parser . getTok ( ) . getLoc


<s> bool SelectAddrImmOffs ( SDValue N , SDValue & Out ) const { if ( isa < ConstantSDNode > ( N ) || N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { Out = N ; return true ; } return false


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return


<s> } if ( TARGET_AVX && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( GET_MODE ( op0 ) != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; } op1 = gen_lowpart ( V32QImode , op1 ) ; case MODE_VECTOR_FLOAT : ix86_avx256_split_vector_move_misalign ( op0 , op1 ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; break ; default : gcc_unreachable ( ) ; } return ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( GET_MODE ( op0 ) != V16QImode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V16QImode ) ; } op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_loaddquv16qi ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } else if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { emit_insn ( gen_sse2_loadupd ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( op0 ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { rtx t ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { if ( GET_MODE ( op0 ) != V4SFmode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V4SFmode ) ; } op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_loadups ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; return ; } if ( mode != V4SFmode ) t


<s> rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vspltisb || icode == CODE_FOR_altivec_vspltish || icode == CODE_FOR_altivec_vspltisw ) { if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < - <NUM_LIT> ) { error ( <STR_LIT>


<s> break ; case SImode : gen_neg = gen_negsi2 ; break ; case DImode : gen_neg = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } e1 = gen_reg_rtx ( inmode ) ; e2 = gen_reg_rtx ( inmode ) ; res = gen_reg_rtx ( outmode ) ; half = CONST_DOUBLE_FROM_REAL_VALUE ( dconsthalf , inmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , op1 ) , UNSPEC_FXAM ) ) ) ; emit_insn ( gen_abs ( e1 , op1 ) ) ; half = force_reg ( inmode , half ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_PLUS ( inmode , e1 , half ) ) ) ; if ( inmode != XFmode ) { tmp1 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp1 , gen_rtx_FLOAT_EXTEND ( XFmode , e2 ) ) ) ; } else tmp1 = e2 ; switch ( outmode ) { case SFmode : case DFmode : { rtx tmp0 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_frndintxf2_floor ( tmp0 , tmp1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( <NUM_LIT> , tmp0 ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; case XFmode : emit_insn ( gen_frndintxf2_floor ( res , tmp1 ) ) ; break ; case HImode : emit_insn ( gen_lfloorxfhi2 ( res , tmp1 ) ) ; break ; case SImode : emit_insn ( gen_lfloorxfsi2 ( res , tmp1 ) ) ; break ; case DImode : emit_insn ( gen_lfloorxfdi2 ( res , tmp1 ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_neg ( res , res ) ) ; emit_label ( jump_label )


<s> unsigned getRegisterBitWidth ( bool Vector ) const { if ( Vector ) { return


<s> bool isToken ( ) const override { return Kind


<s> Inst . addOperand ( MCOperand :: CreateImm ( ( Imm + Add ) & ( Add


<s> __arm_mcr ( const unsigned int __coproc , const unsigned int __opc1 , uint32_t __value ,

const unsigned int __CRn , const unsigned int __CRm , const unsigned int __opc2 ) {


<s> enum reg_class xstormy16_preferred_reload_class ( rtx x , enum


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return


<s> bool isTargetLinux ( ) const { return TargetTriple .


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = build_same_sized_truth_vector_type ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( RegInfo -> requiresRegisterScavenging ( MF ) ) if ( needsFP ( MF )


<s> Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: <ISA_LIT> ; UseParensForSymbolVariant =


<s> machine_mode inner_dmode = GET_MODE_INNER ( dmode ) ; machine_mode inner_smode = GET_MODE_INNER ( smode ) ; int nunits = <NUM_LIT> / GET_MODE_SIZE ( inner_dmode ) ; machine_mode sse_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits ) . require ( ) ; machine_mode sse_half_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits / <NUM_LIT> ) . require ( ) ; nunits = <NUM_LIT> / GET_MODE_SIZE ( inner_smode ) ; machine_mode sse_smode = mode_for_vector ( GET_MODE_INNER ( smode ) , nunits ) . require ( ) ; rtx dest = lowpart_subreg ( sse_dmode , op0 , GET_MODE (


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( Stalls && -- Stalls == <NUM_LIT> ) LastMI = <NUM_LIT> ; ScoreboardHazardRecognizer :: AdvanceCycle


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! <ISA_LIT>FI -> mips16SPAliasRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; const TargetInstrInfo & TII = * MF . getTarget


<s> OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end (

) ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 ) llvm_unreachable ( <STR_LIT> ) ; if ( ! AFI -> isLRSpilled ( ) ) report_fatal_error ( <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister


<s> unsigned RBegin , REnd ; CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = Subtarget -> getFrameLowering ( ) -> getStackAlignment ( ) ; ArgRegsSize = NumGPRs * <NUM_LIT> ; if ( NumGPRs && Align > <NUM_LIT> && ( ArgRegsSize < ArgSize || InRegsParamRecordIdx >= CCInfo . getInRegsParamsCount ( ) ) ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Padding = OffsetToAlignment ( ArgRegsSize + AFI -> getArgRegsSaveSize ( ) , Align ) ; ArgRegsSaveSize = ArgRegsSize +


<s> return false ; } case AsmToken :: LBrac : return ParseMemory ( Operands ) ; case AsmToken :: LCurly : return ParseRegisterList ( Operands ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return false ; case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( ParsePrefix ( RefKind ) ) return


<s> LLVM_FALLTHROUGH ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ) ; } if ( ! TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; switch ( getLexer ( ) . getKind ( )


<s> return ( __m128i ) __builtin_ia32_pminub128_mask ( ( __v16qi ) __A , ( __v16qi ) __B , ( __v16qi ) _mm_setzero_di ( ) ,


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target ,


<s> BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; return BB


<s> FunctionPass * llvm :: create<ISA_LIT>FlagsCopyLoweringPass ( ) { return new <ISA_LIT>FlagsCopyLoweringPass


<s> } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature =


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelPLT ( ) const { assert ( m_pRelPlt != NULL


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) { Tmp . back ( ) = Suffixes [ I ] ; Match [ I ] = MatchInstructionImpl ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match [ I ] == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } Op . setTokenValue ( Base ) ; unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange


<s> if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) { NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; WasCandidate = true ; } } break ; case <STR_LIT> : NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; WasCandidate = true ; break ; case <STR_LIT> : case <STR_LIT>


<s> tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ( ImmValue & <NUM_LIT> ) == ImmValue ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; createShiftOr < <NUM_LIT> , true > ( ImmValue , RegOp . getReg


<s> return getSTI ( ) . getFeatureBits (


<s> return new <ISA_LIT>PreLegalizerCombiner


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return ; default : break ; } unsigned NumOp = Inst . getNumOperands ( ) ; assert ( ( NumOp == <NUM_LIT> || NumOp == <NUM_LIT> ) && <STR_LIT> ) ; unsigned StartOp = NumOp == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & BaseRegOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; assert ( BaseRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned OpCode = Inst . getOpcode ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned BaseReg = BaseRegOp . getReg ( ) ; unsigned TmpReg = DstReg ; const MCInstrDesc & Desc = getInstDesc ( OpCode ) ; int16_t DstRegClass = Desc . OpInfo [ StartOp ] . RegClass ; unsigned DstRegClassID = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( DstRegClass ) . getID ( ) ; bool IsGPR = ( DstRegClassID == <STR_LIT> ) || ( DstRegClassID == <STR_LIT> ) ; if ( ! IsLoad || ! IsGPR || ( BaseReg == DstReg ) ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return ; } auto emitInstWithOffset = [ & ] ( const MCOperand & Off ) { if ( NumOp == <NUM_LIT> ) TOut . emitRRX ( OpCode , DstReg , TmpReg , Off , IDLoc , STI ) ; else TOut . emitRRRX ( OpCode , DstReg , DstReg , TmpReg , Off , IDLoc , STI ) ; } ; if ( OffsetOp . isImm (


<s> else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg


<s> for ( MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) || MI . isPseudo ( ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Offset = <NUM_LIT> ; if ( is<ISA_LIT>FrameOffsetLegal ( MI , Offset , nullptr , nullptr , nullptr ) == <ISA_LIT>FrameOffsetCannotUpdate


<s> rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem ,


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( Cond . empty ( ) && ! FBB && TBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> )


<s> return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ; if ( Subtarget -> hasXMM ( ) ) getMaxByValAlign (


<s> MachineInstr * Save ; MachineInstr * Restore ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { Register Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg && <STR_LIT> ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; Save = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Restore = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) ; } else { Save = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; Restore = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) .

addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL ,

Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA


<s> if ( arm_stack_protector_guard == SSP_GLOBAL )

return default_stack_protect_guard ( ) ;


<s> ix86_unsafe_math_optimizations = flag_unsafe_math_optimizations ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_tree = build_target_option_node ( & global_options , & global_options_set ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; static bool prev_no_caller_saved_registers ; if ( TARGET_64BIT && ( call_used_or_fixed_reg_p ( SI_REG ) == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; else if ( prev_no_caller_saved_registers != cfun -> machine -> no_caller_saved_registers ) reinit_regs ( ) ; if ( cfun -> machine -> func_type != TYPE_NORMAL || cfun -> machine -> no_caller_saved_registers ) { const char * isa ; if ( TARGET_SSE ) isa = <STR_LIT> ; else if ( TARGET_MMX ) isa = <STR_LIT> ; else if ( TARGET_80387 ) isa = <STR_LIT> ; else isa = NULL ; if ( isa != NULL ) { if ( cfun -> machine -> func_type != TYPE_NORMAL ) sorry ( cfun -> machine -> func_type == TYPE_EXCEPTION ? G_ ( <STR_LIT> <STR_LIT> ) : G_ ( <STR_LIT> <STR_LIT> ) , isa ) ; else sorry ( <STR_LIT> <STR_LIT> , isa ) ; cfun -> machine -> func_type = TYPE_NORMAL ; cfun -> machine -> no_caller_saved_registers


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value == <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned


<s> Value * <ISA_LIT>IREmitter :: visitVSEXT ( const SDNode *


<s> if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOp ) break ; Chain . push_back ( V ) ; case <STR_LIT> : V = V . getOperand ( <NUM_LIT> ) ; continue ; } break ; } while ( V . hasOneUse ( ) ) ; break ; } break ; } if ( ! V . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > VMask = getPSHUFShuffleMask ( V ) ; for ( int & M : Mask ) M = VMask [ M ] ; V = DAG . getNode ( V . getOpcode ( ) , DL , V . getValueType ( ) , V . getOperand ( <NUM_LIT> ) , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; while ( ! Chain . empty ( ) ) { SDValue W = Chain . pop_back_val ( ) ; if ( V . getValueType ( ) != W . getOperand ( <NUM_LIT> ) . getValueType ( ) ) V = DAG . getBitcast ( W . getOperand ( <NUM_LIT> ) . getValueType ( ) , V ) ; switch ( W . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case


<s> bool isIndirect ( ) { return Target != nullptr && Target -> isReg (


<s> const Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { if ( ! isIntExtFree ( ZExt ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { if ( ! isIntExtFree ( SExt ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction ::


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> && ! FeatureBits [ <STR_LIT> ] ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> } if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setNoMacro ( ) ; Parser . Lex (


<s> case VECTOR_NONE : ret = <STR_LIT> ; break ; case VECTOR_ALTIVEC : ret = <STR_LIT> ; break ; case VECTOR_VSX : ret = <STR_LIT> ; break ; case VECTOR_P8_VECTOR : ret = <STR_LIT> ;


<s> Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } llvm_unreachable (


<s> moxie_compute_frame ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> size_for_adjusting_sp ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ! fixed_regs [ regno ] && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) { int i = cfun -> machine -> size_for_adjusting_sp ; while ( ( i >= <NUM_LIT> ) && ( i <=


<s> SDValue <ISA_LIT>TargetLowering :: LowerBUILD_VECTORvXi1 ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef (


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg (


<s> } if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSSolaris ( ) ) return llvm :: make_unique < <ISA_LIT>SolarisTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return llvm :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return llvm :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable ( <STR_LIT>


<s> if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious


<s> Out . EmitBundleLock ( false ) ; MCInst Tmp ; Tmp . setOpcode ( Opc ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( ImmOp ) ; Out . EmitInstruction ( Tmp , STI ) ; EmitRegFix ( STI , <STR_LIT> ,


<s> while ( Iter != EndIter ) { NextPred = getVPTInstrPredicate ( * Iter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred == <STR_LIT> || MaxSteps == <NUM_LIT> ) break ; -- MaxSteps


<s> if ( NumBytes >= - <NUM_LIT> && NumBytes < <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( ADDri ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; return ; } if ( NumBytes >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HI22 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm (


<s> return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo

-> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> OS << <STR_LIT> << <STR_LIT> ( ArchExt


<s> if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , <STR_LIT> , name ) ; } else fprintf ( file , <STR_LIT> , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , size , align / BITS_PER_UNIT ) ; fputc ( '\n' ,


<s> Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part0 , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part1 , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineBasicBlock :: iterator I = SinglePredMBB -> getFirstTerminator ( ) ; I != SinglePredMBB -> end ( ) ; I ++ ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; bool TakenBranch = ( I -> isBranch ( ) && ( TII -> getBranchInfo ( * I ) . Target -> isReg ( ) || TII -> getBranchInfo ( * I ) . Target -> getMBB ( ) == MBB ) ) ; HazardRec -> emitInstruction ( & * I , TakenBranch ) ; if ( TakenBranch


<s> static bool BBIsJumpedOver ( MachineBasicBlock * MBB ) { if ( MBB -> pred_size ( ) != <NUM_LIT> ||

MBB -> succ_size ( ) != <NUM_LIT> ) return false ;


<s> SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . isUndef ( ) ) { InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec0 . getSimpleValueType ( ) != VT ) return SDValue ( ) ; } if ( InVec1 . isUndef ( ) ) { InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getSimpleValueType ( ) != VT ) return SDValue ( ) ; } if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) { if ( ExpectedOpcode == <STR_LIT> ) return SDValue ( ) ; std :: swap ( Op0 , Op1 ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } if ( InVec1 != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; std :: swap ( ExpectedOpcode , NextExpectedOpcode


<s> assert ( m_pGOTPLT != NULL && <STR_LIT> ) ; return *


<s> bool ToEFLAGS = DestReg == <STR_LIT> ; int Reg = FromEFLAGS ? DestReg : SrcReg ; bool is32 = <STR_LIT> . contains ( Reg ) ; bool is64 = <STR_LIT> . contains ( Reg ) ; if ( ( FromEFLAGS || ToEFLAGS ) && ( is32 || is64 ) ) { int Mov = is64 ? <STR_LIT> : <STR_LIT> ; int Push = is64 ? <STR_LIT> : <STR_LIT> ; int Pop = is64 ? <STR_LIT> : <STR_LIT> ; int AX = is64 ? <STR_LIT> : <STR_LIT> ; bool AXDead = ( Reg == AX ) || ( MachineBasicBlock :: LQR_Dead == MBB . computeRegisterLiveness ( & getRegisterInfo ( ) , AX , MI ) ) ; if ( ! AXDead ) BuildMI ( MBB , MI , DL , get ( Push ) ) . addReg ( AX , getKillRegState ( true ) ) ; if ( FromEFLAGS ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( Mov ) , Reg ) . addReg ( AX ) ; } if ( ToEFLAGS


<s> while ( type && type -> name && ! found && res == AARCH64_PARSE_OK ) { if ( strcmp ( str , type -> name ) == <NUM_LIT> ) { found = true ; res = type -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , <STR_LIT> , & token_save ) ; } else type ++ ; } if ( found && res == AARCH64_PARSE_OK ) { bool found_subtype = true ; while ( found_subtype ) { found_subtype = false ; const aarch64_branch_protect_type * subtype = type -> subtypes ; while ( str && subtype && subtype -> name && ! found_subtype && res == AARCH64_PARSE_OK ) { if ( strcmp ( str , subtype -> name ) == <NUM_LIT> ) { found_subtype = true ; res = subtype -> handler (


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast


<s> bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg


<s> if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( )


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineBasicBlock :: reverse_iterator RI = MachineBasicBlock :: reverse_iterator ( I ) , RE = CmpInstr -> getParent ( ) == MI -> getParent ( ) ? MachineBasicBlock :: reverse_iterator ( ++ Def ) : CmpInstr -> getParent ( ) -> rend ( ) ; MachineInstr * Movr0Inst = <NUM_LIT> ; for ( ; RI != RE ; ++ RI ) { MachineInstr * Instr = & * RI ; if ( isRedundantFlagInstr ( CmpInstr , SrcReg , SrcReg2 , CmpValue , Instr ) ) { Sub = Instr ; break ; } if ( Instr -> modifiesRegister ( <STR_LIT> , TRI ) || Instr -> readsRegister ( <STR_LIT> , TRI ) ) { if ( ! Movr0Inst && ( Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> || Instr -> getOpcode ( ) == <STR_LIT> ) && Instr -> registerDefIsDead ( <STR_LIT> , TRI ) ) { Movr0Inst = Instr ; continue ; } return false ; } } if ( ! Sub ) return false ; bool IsSwapped = ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ; bool IsSafe = false ; SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > OpsToUpdate ; MachineBasicBlock :: iterator E = CmpInstr -> getParent ( ) -> end ( ) ; for ( ++ I ; I != E ; ++ I ) { const MachineInstr & Instr


<s> Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else


<s> if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( IsIntegerCC ( CC ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; if ( ! FBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB


<s> EVT AVT = <STR_LIT> ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) AVT = <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getValueType ( AVT ) ) ; Ops . push_back ( InFlag ) ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft )


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction *


<s> machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > <NUM_LIT> ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; if ( ! generate ) return x ; x = copy_to_mode_reg ( inner_mode , x


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP


<s> if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true


<s> AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; } EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) ,


<s> SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG


<s> const MCRegisterInfo * MRI = TM . getMCRegisterInfo ( ) ; int act_reg = - <NUM_LIT> ; for ( auto reg_iterator = MF -> live_in_types . begin ( ) ; reg_iterator != MF -> live_in_types . end ( ) ; reg_iterator ++ ) { if ( MRI -> isSuperOrSubRegisterEq ( reg_iterator -> first , Reg ) ) act_reg = reg_iterator -> first ; } if ( act_reg != - <NUM_LIT> ) return MF -> live_in_types . find ( act_reg ) -> second ; else { if ( MF -> getFunction ( ) -> isVarArg ( ) ) return <NUM_LIT> ; return


<s> bool isMOVK32Imm ( ) const { static const <ISA_LIT>MCExpr :: VariantKind PermittedModifiers [ ] = { <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0_NC , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1_NC , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0_NC , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G0_NC , <ISA_LIT>MCExpr ::


<s> return StringSwitch < unsigned > ( CC . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .


<s> Contents += UppercaseString ( String ) ; Contents += <NUM_LIT>


<s> } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> return __builtin_mve_vclzq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) ,


<s> OperandMatchResultTy parseADDR32 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands


<s> Type * Int8PtrType = Type :: getInt8PtrTy ( Context ) ; Type * ArgTys [ <NUM_LIT> ] = { Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType } ; FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: dropLLVMManglingEscape ( ParentFunc -> getName ( ) ) , TheModule ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB ) ; Value * LSDA = emitEHLSDA ( Builder , ParentFunc ) ; Value * CastPersonality = Builder . CreateBitCast ( PersonalityFn , TargetFuncTy -> getPointerTo ( ) ) ; auto AI = Trampoline -> arg_begin ( ) ; Value * Args [ <NUM_LIT> ] = { LSDA , & * AI ++ , & * AI ++ , & * AI ++ , & * AI ++ } ; CallInst * Call = Builder . CreateCall


<s> Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Value = MCE -> getValue ( ) ; if ( Value != <NUM_LIT> && Value != <NUM_LIT> && Value != <NUM_LIT> && Value != <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Value ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , DB -> Name , ExprLoc , getContext ( ) , true ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Operand = Tok . getString ( ) ; auto DB = <STR_LIT> ( Operand ) ; if ( ! DB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , Tok . getString ( ) , getLoc ( ) , getContext ( ) , true ) ) ; Parser . Lex (


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle && ! isLittleEndian ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { unsigned SrcElt = PermMask [ i ] < <NUM_LIT> ? <NUM_LIT> : PermMask [ i ] ; for ( unsigned j = <NUM_LIT> ; j != BytesPerElement ; ++ j ) if ( isLittleEndian ) ResultMask . push_back (

DAG . getConstant ( <NUM_LIT> - ( SrcElt * BytesPerElement + j ) , <STR_LIT> ) ) ;


<s> static const <ISA_LIT>MCExpr * CreateLower16 ( const MCExpr *


<s> MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand (