<s> } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno


<s> if ( REGNO ( reg ) == GP_REG_FIRST + <NUM_LIT> && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + <NUM_LIT> ) reg = gen_rtx_REG ( GET_MODE ( reg ) , DWARF_FRAME_RETURN_COLUMN ) ; set = gen_rtx_SET ( VOIDmode , mem


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> O << formatImm ( MI -> getOperand ( Op ) . getImm (


<s> return ( __m64 ) __builtin_ia32_psubb ( ( __v8qi )


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I


<s> const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; if ( ! RI -> getRegClass ( <STR_LIT> ) . contains ( RegNum ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , false , S , getLoc ( ) , Ctx ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * ImmVal ; if ( Parser . parseExpression ( ImmVal ) || ! isa < MCConstantExpr > ( ImmVal ) || cast < MCConstantExpr > ( ImmVal ) -> getValue ( ) != <NUM_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , false , S


<s> bool isPredictableSelectIsExpensive ( ) const { return PredictableSelectIsExpensive


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) { <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping ( this ) ; Is64Bit = TT . isArch64Bit ( ) ; IsWin64 = Is64Bit && TT . isOSWindows ( ) ; if ( Is64Bit ) { SlotSize = <NUM_LIT> ; bool Use64BitReg = TT . getEnvironment ( ) !=


<s> return ( __m128i ) __builtin_ia32_cvtps2udq128_mask ( ( __v4sf ) __A , ( __v4si )


<s> bool isImm0_127 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( )


<s> Result = ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ; } return APInt ( N ,


<s> for ( Use & U : PHI -> uses ( ) ) replaceWithTileLoad (


<s> return new <ISA_LIT>SIMDInstrOpt ( )


<s> const char * getPassName ( ) const override { return


<s> if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ,

DAG . getTargetConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> if ( isa < ConstantInt > ( V ) || isa < Argument > ( V ) ) return true ; if ( isa < StoreInst > ( V ) || isa < LoadInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( auto * ICmp = dyn_cast < ICmpInst > ( V ) ) return ICmp -> isEquality ( ) || ! ICmp -> isSigned ( ) ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) ) return true ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; else if ( auto * Cast = dyn_cast < CastInst > ( V ) ) { if ( isa < ZExtInst > ( Cast ) ) return Cast -> getDestTy ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ; else if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return Trunc -> getDestTy ( ) -> getScalarSizeInBits ( ) <= TypeSize ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast <


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; const <ISA_LIT>InstrInfo * InstrInfo = static_cast < const <ISA_LIT>InstrInfo *


<s> return ( __m128d ) __builtin_ia32_cvtudq2pd128_mask ( ( __v4si ) __A , ( __v2df )


<s> int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , FIdx , MachinePointerInfo ( ) ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , Store ,


<s> bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineInstr * MI = & * MBBI ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos && ( ! MI -> getDesc ( ) . isBranch ( ) && ! MI -> getDesc ( ) . isReturn ( ) ) ) { MachineInstr * NMI = & * MBBI ; MI = NMI ; DebugLoc ndl = NMI -> getDebugLoc ( ) ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getPredicate ( NMI , NPredReg ) ; if ( NCC == OCC ) { Mask |= ( <NUM_LIT> << Pos ) ; } else if ( NCC != CC ) break ; -- Pos ; ++ MBBI ; } Mask |= ( <NUM_LIT> <<


<s> if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ; InstructionCost Cost = BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; Cost *= CostFactor ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return


<s> if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; MVT ResTy ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; switch ( NumLanes ) { default : return SDValue ( ) ; case <NUM_LIT> : ResTy = FloatBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ResTy = <STR_LIT> ; break ; } SDLoc DL ( N ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getConstant ( IntrinsicOpcode , DL , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , DL , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return FixConv


<s> bool enableAdvancedRASplitCost ( ) const override { return true


<s> static const uint16_t CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const uint16_t * CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs ; for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return -


<s> for ( unsigned i = BB -> getNumber ( ) + <NUM_LIT> , e = BB -> getParent ( ) -> getNumBlockIDs ( ) ; i < e ; ++ i ) { BBOffsets [ i ] += delta ; if ( ! isThumb ) continue ; MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) && ! HasInlineAsm ) { if ( MBB -> begin ( ) -> getOpcode ( ) == <STR_LIT> ) { unsigned OldOffset = BBOffsets [ i ] - delta ; if ( ( OldOffset % <NUM_LIT> ) == <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta += <NUM_LIT> ; } else if ( ( OldOffset % <NUM_LIT> ) != <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } } MachineInstr * ThumbJTMI = prior ( MBB -> end ( ) ) ; if ( ThumbJTMI -> getOpcode ( ) == <STR_LIT> ) { unsigned NewMIOffset = GetOffsetOf ( ThumbJTMI ) ; unsigned OldMIOffset = NewMIOffset - delta ; if ( ( OldMIOffset % <NUM_LIT> ) == <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } else if ( ( OldMIOffset % <NUM_LIT> ) != <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta += <NUM_LIT> ; } } if ( delta == <NUM_LIT> ) return ; } MBBI = llvm :: next


<s> unsigned getAdrLabelOpValue ( const MachineInstr &


<s> bool HasEVEX = ( TSFlags & <STR_LIT> ) == <STR_LIT> ; int CD8_Scale = ( TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( ! HasEVEX || CD8_Scale == <NUM_LIT> ) return isInt < <NUM_LIT> > ( Value ) ; assert ( isPowerOf2_32 ( CD8_Scale ) && <STR_LIT> ) ; if ( Value & ( CD8_Scale - <NUM_LIT> ) ) return


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvt_roundss_si32 ( __m128 __A , const int __R ) { return ( int ) __builtin_ia32_vcvtss2si32 ( ( __v4sf )


<s> switch ( type ) { default : unreachable ( <STR_LIT> ) ; case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : unreachable ( <STR_LIT> ) ; case MODRM_ONEENTRY : return dec -> instructionIDs [ <NUM_LIT> ] ; case


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ; return false


<s> if ( OrigImm < <NUM_LIT> && OrigImm >= - <NUM_LIT> ) { NewReg = OrigReg ; NewImm = OrigImm ; ATUsed = false ; } else { const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; int ImmLo = OrigImm & <NUM_LIT> ; int ImmHi = ( ( ( unsigned ) OrigImm & <NUM_LIT> ) >> <NUM_LIT> ) + ( ( OrigImm & <NUM_LIT> ) != <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( ImmHi ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ,

<STR_LIT> ) . addReg ( OrigReg ) . addReg ( <STR_LIT> ) ;


<s> bool isBareSImm10 ( ) const { return isBareImm ( isInt < <NUM_LIT> >


<s> return static_cast < MCELFStreamer &


<s> if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; return true


<s> using namespace TargetOpcode ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR , G_SHL , G_ASHR ,


<s> TargetRegistry :: RegisterAsmPrinter ( The<ISA_LIT>64Target


<s> const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) setAction ( { BinOp , Ty


<s> if ( GET_MODE ( x ) == VOIDmode ) x = convert_to_mode ( mode , x , <NUM_LIT> ) ; return x


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT )


<s> assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case


<s> return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : { SDValue RV = performSelectCombine ( N , DCI ) ; if ( ! RV . getNode ( ) ) RV = performAcrossLaneMinMaxReductionCombine ( N , DAG , Subtarget ) ; return RV ; } case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : return performAcrossLaneAddReductionCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool allowMixed16_32 ( ) const { return in<ISA_LIT>16ModeDefault ( ) | AllowMixed16_32


<s> static int rs6000_elf_reloc_rw_mask ( void ) { if ( flag_pic ) return


<s> virtual bool runOnFunction ( Function & Fn ) { if ( Fn . hasAvailableExternallyLinkage ( ) ) return


<s> case <STR_LIT> : return <NUM_LIT> ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : case FK_SecRel_2 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) .

addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr


<s> SDValue <ISA_LIT>TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter ) : MCELFStreamer ( Context , MAB , OS , Emitter ) { RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this , Context ) ; <ISA_LIT>OptionRecords . push_back ( std :: unique_ptr <

<ISA_LIT>RegInfoRecord > ( RegInfoRecord ) ) ;


<s> return ( uint16x4_t ) __builtin_neon_vshrn_nv4si ( ( int32x4_t ) __a ,


<s> return ( intptr_t ) ( MR -> getResultPointer ( ) ) ; case <STR_LIT> : return ( intptr_t ) ( MR -> getResultPointer ( ) ) - MR -> getConstantVal ( ) ; case <STR_LIT> : return getJumpTableBaseAddr ( MR -> getJumpTableIndex ( ) ) ; case <STR_LIT> : case <STR_LIT> : return getConstantPoolEntryAddr ( MR -> getConstantPoolIndex ( ) ) ; case <STR_LIT>


<s> for ( InstClassification Classification = Skip ; Classification != Exit ; ++ I ) { if ( I == StackPtrCopyInst ) continue ; Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ; if ( Classification != Convert ) continue ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp & ( SlotSize - <NUM_LIT> ) ) return ; StackDisp >>= Log2SlotSize ; assert ( ( size_t ) StackDisp < Context . ArgStoreVector . size ( ) && <STR_LIT> ) ; if ( Context . ArgStoreVector [ StackDisp ] != nullptr ) return ; Context . ArgStoreVector [ StackDisp ] = & * I ; for ( const MachineOperand & MO : I -> uses ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( RegInfo . isPhysicalRegister ( Reg ) ) UsedRegs . insert ( Reg ) ; } } -- I ; if ( I == MBB . end ( ) || ! I -> isCall ( ) ) return ; Context . Call = & * I ; if ( ( ++ I ) -> getOpcode ( ) != TII -> getCallFrameDestroyOpcode ( ) ) return ; auto MMI = Context . ArgStoreVector . begin ( ) , MME = Context . ArgStoreVector


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count


<s> MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; Ignore . insert ( VCTPs . begin ( ) , VCTPs . end ( ) ) ; if ( TryRemove ( Def , RDA , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) { if ( FoundSub || ! IsValidSub ( MI , ExpectedVectorWidth ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << * MI ) ; return false ; } FoundSub = true ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI ,


<s> if ( PtrTy != LLT :: pointer ( <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PtrTy << <STR_LIT> << LLT :: pointer ( <NUM_LIT> ) << '\n' ) ; return false ; } const unsigned PtrReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & PtrRB = * RBI . getRegBank ( PtrReg , MRI , TRI ) ; assert ( PtrRB . getID ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MRI . getSize ( PtrReg ) == <NUM_LIT> && <STR_LIT> ) ; const unsigned ValReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & RB = * RBI . getRegBank ( ValReg , MRI , TRI ) ; const unsigned NewOpc = selectLoadStoreUIOp ( I . getOpcode ( ) , RB . getID ( ) , MemTy . getSizeInBits ( ) ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; I . removeTypes ( ) ; I . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } case TargetOpcode :: G_MUL : { if ( unsupportedBinOp ( I , RBI , MRI , TRI ) ) return false ; const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << RB << <STR_LIT> ) ; return false ; } unsigned ZeroReg ; unsigned NewOpc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { NewOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { NewOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << Ty << <STR_LIT> << LLT :: scalar ( <NUM_LIT> ) << <STR_LIT> << LLT :: scalar ( <NUM_LIT> ) << '\n' ) ; return false ; } I . setDesc ( TII . get ( NewOpc ) ) ; I . removeTypes ( ) ; I . addOperand ( MachineOperand :: CreateReg ( ZeroReg , false ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_AND : case TargetOpcode :: G_SHL


<s> LoadSDNode * LD = cast < LoadSDNode > ( N1 . getNode ( ) ) ; if ( StOp -> getOperand ( <NUM_LIT> ) != LD -> getOperand ( <NUM_LIT> ) ) return NULL ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc32 : VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { LD -> getBasePtr ( ) , N2 , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( StOp , Opc , <STR_LIT> , <STR_LIT> , Ops0 , <NUM_LIT> ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs (


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % <NUM_LIT> ) return false ; uint64_t NumNops =


<s> if ( RegisterSDNode * RegNode = dyn_cast_or_null < RegisterSDNode > ( Base_Reg . getNode ( ) ) ) return RegNode -> getReg ( )


<s> align_rtx = expand_binop ( Pmode , and_optab , scratch1 , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_2_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; } emit_label ( align_4_label ) ; mem = change_address ( src , SImode , out ) ; emit_move_insn ( scratch , mem ) ; emit_insn ( gen_add2_insn ( out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode ,


<s> unsigned getSsatBitPosValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> bool <ISA_LIT>InstructionSelector :: selectCompareBranch ( MachineInstr & I , MachineFunction & MF , MachineRegisterInfo & MRI ) const { Register CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * CCMI = MRI . getVRegDef ( CondReg ) ; if ( CCMI -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CondReg = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CCMI = MRI . getVRegDef ( CondReg ) ; } MachineIRBuilder MIB ( I ) ; unsigned CCMIOpc = CCMI -> getOpcode ( ) ; if ( CCMIOpc == TargetOpcode :: G_FCMP ) return selectCompareBranchFedByFCmp ( I , * CCMI , MIB ) ; if ( CCMIOpc == TargetOpcode :: G_ICMP ) return selectCompareBranchFedByICmp ( I , * CCMI , MIB ) ; if ( ProduceNonFlagSettingCondBr ) { emitTestBit ( CondReg , <NUM_LIT> , true , I . getOperand ( <NUM_LIT> ) . getMBB ( ) ,


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) || MF . hasEHFunclets (


<s> } } if ( allMatched ) { eltVal = lowestEltVal ; break ; } size *= <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> ; i < size ; ++ i ) { eltVal = ror ( eltVal , size ) ; uint32_t clz = countLeadingZeros ( eltVal ) - ( <NUM_LIT> - size ) ; uint32_t cto = CountTrailingOnes_64 ( eltVal ) ; if ( clz + cto == size ) { unsigned immr = size - ( i + <NUM_LIT> ) ; uint64_t nimms = ~ ( size - <NUM_LIT> ) << <NUM_LIT> ; nimms |= ( cto - <NUM_LIT> ) ; unsigned N = ( ( nimms >> <NUM_LIT> ) & <NUM_LIT> ) ^ <NUM_LIT> ; encoding = ( N << <NUM_LIT> ) | ( immr << <NUM_LIT> ) | ( nimms & <NUM_LIT> ) ; return true ; } } return false


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsi_u32 ( unsigned int __X ) { return __X & -


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return

getMachineOpValue ( MI , MO , Fixups , STI ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeInt ( const ConstantInt * CI , MVT VT ) { if ( VT > <STR_LIT> ) return <NUM_LIT> ; if ( ! CI -> isZero ( ) ) return FastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; const TargetRegisterClass * RC = ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg

) . addReg ( ZeroReg , getKillRegState ( true ) ) ;


<s> bool hasFastScalarShiftMasks ( ) const


<s> return __builtin_mve_vbrsrq_n_sv16qi ( __a ,


<s> assert ( VT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> static unsigned getLoadRegOpcode ( unsigned DestReg , const TargetRegisterClass * RC , bool isStackAligned


<s> void addVectorReg128Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG


<s> if ( A_Base == B_Base && A_Base ) report_fatal_error ( <STR_LIT> , false ) ; if ( A -> isUndefined ( ) || B -> isUndefined ( ) ) { StringRef Name = A -> isUndefined ( ) ? A -> getName ( ) : B -> getName ( ) ; Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; } Value += Writer -> getSymbolAddress ( * A , Layout ) - ( ! A_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * A_Base , Layout ) ) ; Value -= Writer -> getSymbolAddress ( * B , Layout ) - ( ! B_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * B_Base , Layout ) ) ; if ( ! A_Base ) Index = A -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_UNSIGNED ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; Writer -> addRelocation ( A_Base , Fragment -> getParent ( ) , MRE ) ; if ( B_Base ) RelSymbol = B_Base ; else Index = B -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_SUBTRACTOR ; } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Asm . addLocalUsedInReloc ( * Symbol ) ; } RelSymbol = Asm . getAtom ( * Symbol ) ; if ( Symbol -> isInSection ( ) ) { const MCSectionMachO & Section = static_cast < const MCSectionMachO & > ( * Fragment -> getParent ( ) ) ; if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) RelSymbol = nullptr ; } if ( RelSymbol ) { if ( RelSymbol != Symbol ) Value += Layout . getSymbolOffset ( * Symbol ) - Layout . getSymbolOffset ( * RelSymbol ) ; } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) { Index = Symbol -> getFragment ( ) -> getParent ( )


<s> return gen_rtx_SET ( VOIDmode , dest , GEN_INT ( val &


<s> return ( __m128i ) __builtin_ia32_pminsb128 ( ( __v16qi ) __X ,


<s> if ( nops <= <NUM_LIT> && arm_tune_xscale && ! optimize_size ) return false ; return


<s> return __builtin_ia32_rsqrtph256_mask ( __B , _mm256_setzero_ph ( )


<s> unsigned leaOutReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg ) ; MachineInstr * InsMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg , RegState :: Define , <STR_LIT> ) . addReg ( Src , getKillRegState ( isKill ) ) ; MachineInstrBuilder MIB = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( Opc ) , leaOutReg ) ; switch ( MIOpc ) { default : llvm_unreachable ( <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned ShAmt = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> << ShAmt ) . addReg ( leaInReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg2 , RegState :: Define , <STR_LIT> ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill , <STR_LIT> ) ; if ( LV )


<s> EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg , Addr ,


<s> if ( VT == <STR_LIT> ) return Subtarget .

hasDSP ( ) ? & <STR_LIT> : & <STR_LIT> ;


<s> if ( known_eq ( TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( pred ) ) , TYPE_VECTOR_SUBPARTS ( vectype ) ) ) return pred ; return gimple_build ( & stmts , VIEW_CONVERT_EXPR , truth_type_for (


<s> const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; OS << SRE -> getSymbol (


<s> I != E ; I ++ ) { if ( ! Limit ) return false ; -- Limit ; bool isDef = any_of ( I -> operands ( ) , [ DefReg , TRI ] ( MachineOperand & MOP ) { return MOP . isReg ( ) && MOP . isDef ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , DefReg ) ; }


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 ,


<s> static DecodeStatus DecodeT2BROperand ( llvm :: MCInst & Inst , unsigned Val

, uint64_t Address , const void * Decoder ) {


<s> if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( ArgVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , OpVT , Op , DAG . getTargetConstant ( <STR_LIT> ,


<s> auto RHSCst = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( RHSCst && isLegalArithImmed ( RHSCst -> Value . getSExtValue ( ) ) ) return false ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> )


<s> if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , S , Tok . getEndLoc


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Value ; SDValue Overflow ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Value = DAG . getNode ( <STR_LIT> , dl , VTs , LHS , RHS ) ; Overflow = ConvertCarryFlagToBooleanCarry ( Value . getValue ( <NUM_LIT> ) , VT , DAG ) ; break ; case <STR_LIT> : Value = DAG . getNode ( <STR_LIT> , dl , VTs , LHS , RHS ) ; Overflow = ConvertCarryFlagToBooleanCarry ( Value . getValue ( <NUM_LIT> ) , VT , DAG ) ; Overflow = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Overflow ) ; break ; } return DAG . getNode ( <STR_LIT> , dl , VTs , Value


<s> if ( VT . isVector ( ) ) { if ( useSVEForFixedLengthVectorVT ( VT , Subtarget -> useSVEForFixedLengthVectors ( ) ) ) return LowerFixedLengthVectorStoreToSVE ( Op , DAG ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) && VT == <STR_LIT> && MemVT == <STR_LIT> ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { return LowerStore128 ( Op , DAG ) ; } else if ( MemVT == <STR_LIT> ) { SDValue Value = StoreNode ->


<s> } } else if ( reset ) { tree id_list ; tree id ; tree nmi , warm ; unsigned int lower_bound ; unsigned int upper_bound ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; lower_bound = <NUM_LIT> ; upper_bound = <NUM_LIT> ; if ( TREE_CODE ( id ) != INTEGER_CST || wi :: ltu_p ( wi :: to_wide ( id ) , lower_bound ) || wi :: gtu_p ( wi :: to_wide ( id ) , upper_bound ) ) error ( <STR_LIT> ) ; nmi = lookup_attribute ( <STR_LIT> , func_attrs ) ; warm = lookup_attribute ( <STR_LIT> , func_attrs ) ; if ( nmi != NULL_TREE ) { tree nmi_func_list ; tree nmi_func ; nmi_func_list = TREE_VALUE (


<s> static void EmitOR ( MCStreamer & OutStreamer , MCOperand & RS1 , MCOperand & Imm , MCOperand & RD ,


<s> V = peekThroughBitcasts ( V ) ; return <STR_LIT> ( V .


<s> static MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler


<s> SDValue FirstInput = N -> getOperand ( <NUM_LIT> ) ; assert ( FirstInput . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned FirstConversion = FirstInput . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> ) { bool IsSplat = true ; bool Is32Bit = FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> ; EVT SrcVT = FirstInput . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; EVT TargetVT = N -> getValueType ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue NextOp = N -> getOperand ( i ) ; if ( NextOp . getOpcode ( ) !=


<s> static inline uint32_t __ev_get_u32_internal ( __ev64_opaque__ a , uint32_t pos ) { union { __ev64_opaque__ v ; uint32_t i [


<s> OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer .

EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( IndexReg != <NUM_LIT> ) IndexReg = TRI -> getSubReg ( IndexReg , <STR_LIT> ) ; } MachineInstr * NewMI = nullptr ; if ( BaseReg != <NUM_LIT> && IndexReg != <NUM_LIT> && Disp . getImm ( ) == <NUM_LIT> && ( DestReg == BaseReg || DestReg == IndexReg ) ) { unsigned NewOpcode = getADDrrFromLEA ( MI . getOpcode ( ) ) ; if ( DestReg != BaseReg ) std :: swap ( BaseReg , IndexReg ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) . addReg ( IndexReg ) . addReg ( Base . getReg ( ) , RegState :: Implicit ) . addReg ( Index . getReg ( ) , RegState :: Implicit ) ; } else { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) . addReg ( IndexReg ) ; } } else if ( DestReg == BaseReg && IndexReg == <NUM_LIT> ) { if ( OptIncDec && ( Disp . getImm ( ) == <NUM_LIT> || Disp . getImm ( ) == - <NUM_LIT> ) ) { bool IsINC = Disp . getImm ( ) == <NUM_LIT> ; unsigned NewOpcode = getINCDECFromLEA ( MI . getOpcode (


<s> union { int i ; float f ; } u ; u . f = fg ; return u . i


<s> } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( ! Subtarget -> useConstIslands ( ) && Subtarget -> hasV6T2Ops ( ) && VT == <STR_LIT> ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( ! Subtarget -> useConstIslands ( ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align ==


<s> static bool hasLockPrefix ( const MachineInstr & MI ) { return MI . getDesc ( ) .


<s> if ( ( ! REG_P ( arg ) && ! MEM_P ( arg ) ) || GET_MODE ( arg ) != SFmode ) arg = force_reg ( SFmode , arg ) ; if ( target == NULL_RTX || ! REG_P ( target ) ) target = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lrintsf2 ( target , arg ) ) ; return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( JUMP_P ( subinsn ) && get_attr_length ( subinsn ) > normal_length && ( any_condjump_p ( subinsn ) || any_uncondjump_p ( subinsn ) ) ) return true ; return false


<s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { MachineInstr & MI = * MBBI ; switch ( MI . getOpcode (


<s> void addToWaitingQueue ( const MachineInstr * MI , const MachineInstr *


<s> unsigned getStackAlignment ( ) const { return stackAlignment


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask . push_back


<s> SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( SPReg == - <NUM_LIT> ) { Parser . eatToEndOfStatement ( ) ; Error ( SPRegLoc , <STR_LIT> ) ; return false ; } if ( SPReg == <STR_LIT> || SPReg == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; Error ( SPRegLoc , <STR_LIT> ) ; return false ; } int64_t Offset = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc OffsetLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) ) { Parser . eatToEndOfStatement ( ) ; Error ( OffsetLoc , <STR_LIT> ) ; return


<s> water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP , CloserWater ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID

) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != const0_rtx ) ) return <NUM_LIT> ; break ; case CCmode : if ( req_mode == CCGCmode ) return <NUM_LIT> ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return <NUM_LIT> ; case CCGOCmode


<s> op1 = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; op2 = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; constant_op = ( CONSTANT_P ( op1 ) ) ? op1 : op2 ; tmp = gen_reg_rtx ( GET_MODE ( constant_op ) ) ; emit_move_insn ( tmp , constant_op ) ; if ( CONSTANT_P ( op1 ) ) new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , tmp , op2 ) ; else new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , op1 , tmp ) ; emit_move_insn ( target ,


<s> } for ( RelLsIter R = RelocLs . begin ( ) ; R != RelocLs . end ( ) ; ++ R ) if ( NeedsMatchingLo ( Asm , * R ) && ! HasMatchingLo ( Asm , R , -- RelocLs . end ( ) ) ) Unmatched . push_back ( R ) ; for ( std :: vector < RelLsIter > :: iterator U = Unmatched . begin ( ) ; U != Unmatched . end ( ) ; ++ U ) { RelLsIter LoPos = RelocLs . end ( ) , HiPos = * U ; bool MatchedLo = false ; for ( RelLsIter R = RelocLs . begin ( ) ; R != RelocLs . end ( ) ; ++ R ) { if ( ( R -> Reloc . Type == ELF :: R_CPU0_LO16 ) && HasSameSymbol ( * HiPos , * R ) && ( CompareOffset ( * R , * HiPos ) >= <NUM_LIT> ) && ( ( LoPos == RelocLs . end ( ) ) || ( ( CompareOffset ( * R , * LoPos ) < <NUM_LIT> ) ) || ( ! MatchedLo && ! CompareOffset


<s> const MCRegisterClass * RC ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) RC = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) RC = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) RC = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; else return Error ( RegLoc , <STR_LIT> ) ; Registers . push_back ( std :: pair < unsigned , SMLoc > ( Reg , RegLoc ) ) ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) return Error ( EndLoc , <STR_LIT> ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! RC -> contains ( EndReg ) )


<s> vrev64_u32 ( uint32x2_t a ) { return __builtin_shuffle ( a , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT>


<s> int Opc = I -> getOpcode ( ) ; if ( I -> isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode = <STR_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; unsigned LongFormMaxOffs = ( ( <NUM_LIT> << LongFormBits


<s> MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : <NUM_LIT> ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const TargetData & TD = * MF -> getTarget ( ) . getTargetData ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI


<s> const char * sh_symbian_strip_name_encoding ( const char * name ) { int skip


<s> return Subtarget -> isTargetWindows ( ) && ! Subtarget -> is64Bit


<s> static void EmitRet ( const MCOperand * AmtOp , bool Is64Bit , MCStreamer & Out ) { MCInst POPInst ; POPInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; POPInst . addOperand ( MCOperand :: CreateReg ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; Out . EmitInstruction ( POPInst ) ; if ( AmtOp ) { assert ( ! Is64Bit ) ; MCInst ADDInst ; unsigned ADDReg = <STR_LIT> ; ADDInst . setOpcode (


<s> __builtin_aarch64_st1v2si ( ( __builtin_aarch64_simd_si * ) a , ( int32x2_t


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue VAList = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue Stack = DAG . getFrameIndex ( FuncInfo -> getVariadicStackIdx ( ) , getPointerTy ( ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ) ; int GPRSize = FuncInfo -> getVariadicGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVariadicGPRIdx ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false ,


<s> Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode >


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } assert ( ( Tok . is ( AsmToken :: Colon ) || Tok . is ( AsmToken :: Comma ) ) && <STR_LIT> ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; E = Parser . getTok ( ) . getLoc ( ) ; SMLoc AlignmentLoc = Tok . getLoc ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE ) return Error ( E , <STR_LIT> ) ; unsigned Align = <NUM_LIT> ; switch ( CE -> getValue ( ) ) { default : return Error ( E , <STR_LIT> ) ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , nullptr , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , Align , false , S , E , AlignmentLoc ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex


<s> case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : return <NUM_LIT> ; case SYMBOL_TLSGD : case SYMBOL_TLSLDM : return <NUM_LIT> ; case SYMBOL_PCREL64 : return <NUM_LIT> ; case


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent (


<s> SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } getTargetStreamer ( ) . emitObjectArch ( ID ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement )


<s> static DecodeStatus DecodeSysRegOperand ( const <STR_LIT> & Mapper , llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { bool ValidNamed ; Mapper . toString ( Val , ValidNamed


<s> if ( ! IsTailCall ) return IsIndirect ? getBLRCallOpcode ( CallerF ) : ( unsigned ) <STR_LIT> ; if ( ! IsIndirect ) return <STR_LIT>


<s> case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) AddMACCandidate ( Candidates , I , MulOp0 , MulOp1 ) ; return false


<s> if ( TT . isOSBinFormatMachO ( ) ) return make_unique < <ISA_LIT>_MachoTargetObjectFile


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler


<s> for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end ( ) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo [ MaxCountRemainder ] . second ) MaxCountRemainder = j ; if ( RemainderOffsetInfo [ MaxCountRemainder ] . second < DispFormPrepMinThreshold ) return false ; if ( MaxCountRemainder == <NUM_LIT> ) return true ; const SCEV * Offset = BucketChain . Elements [ RemainderOffsetInfo [ MaxCountRemainder ] . first ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant > ( SE -> getNegativeSCEV ( Offset ) ) ; } std :: swap ( BucketChain . Elements [ RemainderOffsetInfo [ MaxCountRemainder ] . first ] , BucketChain


<s> MCSection * findAssociatedSection ( )


<s> } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set (


<s> unsigned Qm = CTX . getRegisterInfo ( ) -> getEncodingValue ( M0 . getReg ( ) ) ; int32_t Imm = M1 . getImm ( ) ; bool isAdd = Imm >= <NUM_LIT> ; Imm >>= shift ; if ( ! isAdd ) Imm = - ( uint32_t ) Imm ; Imm &= <NUM_LIT> ; if ( isAdd ) Imm


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT>


<s> break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT>


<s> switch ( Kind ) { default : break ; case MCK__35_0 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__35_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__35_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op . getReg ( )


<s> MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( &


<s> if ( SDValue V = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getBitcast ( FpVT , V1 ) ; V2 = DAG . getBitcast ( FpVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case


<s> buildCallOperands ( Ops , CFlags , dl , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget ) ; if ( CFlags . IsTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ; Chain = DAG . getNode ( CallOpc , dl , ReturnTypes , Ops ) ; Glue = Chain . getValue


<s> return DAG . getFrameIndex ( FI , PtrVT ) ; } if ( Flags . isCopyElisionCandidate ( ) && VA . getLocInfo ( ) != CCValAssign :: Indirect && ! ExtendedInMem ) { EVT ArgVT = Ins [ i ] . ArgVT ; SDValue PartAddr ; if ( Ins [ i ] . PartOffset == <NUM_LIT> ) { int FI = MFI . CreateFixedObject ( ArgVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , false ) ; PartAddr = DAG . getFrameIndex ( FI , PtrVT ) ; return DAG . getLoad ( ValVT , dl , Chain , PartAddr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { int64_t PartBegin = VA . getLocMemOffset ( ) ; int64_t PartEnd = PartBegin + ValVT . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI . getObjectIndexBegin ( ) ; for ( ; MFI . isFixedObjectIndex ( FI ) ; ++ FI ) { int64_t ObjBegin = MFI . getObjectOffset ( FI ) ; int64_t ObjEnd = ObjBegin + MFI . getObjectSize ( FI ) ; if ( ObjBegin <= PartBegin && PartEnd <= ObjEnd ) break ; } if ( MFI . isFixedObjectIndex ( FI


<s> bool isSImm9 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasSSE1 ( ) ) return false ; ++ FPRCnt ; break ; } if ( GPRCnt > <NUM_LIT> ) return false ; if ( FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned SrcReg ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SrcReg = GPR32ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : SrcReg = GPR64ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : case <STR_LIT> : SrcReg = XMMArgRegs [ FPRIdx ++ ] ; break ; } unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & Arg


<s> vaba_u32 ( uint32x2_t a , uint32x2_t b , uint32x2_t c ) { uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size =


<s> case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; } switch ( MI . getOperand ( * AddrIdx ) . getReg ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case CondCode : CC = o . CC ; break ; case Token : Tok = o . Tok ; break ; case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) || Parser . getTok ( ) . is ( AsmToken :: String ) ) { MCSymbol * Func = getParser ( ) . getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . emitThumbFunc ( Func ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; return false ; } } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( ! isThumb ( ) )


<s> if ( ! STI . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } STI . InitMCProcessorInfo ( CPU , <STR_LIT> ) ; STI . InitCPUSchedModel ( CPU ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> virtual void getAnalysisUsage ( AnalysisUsage


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) )


<s> bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else


<s> static __inline qword si_xor ( qword a ,


<s> break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << * getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand ::


<s> return ( unsigned ) __builtin_ia32_vcvttsd2usi32 ( ( __v2df )


<s> return __builtin_mve_vmladavxq_sv4si ( __a ,


<s> unsigned <ISA_LIT>RegisterInfo :: getPICCallReg ( void


<s> static bool DisassembleLdMiscFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned &


<s> if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ; if ( unsigned FirstReg = MRI . getSubReg ( Reg ,


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = Subtarget . is<ISA_LIT>64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( MI . getOperand (

<NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ;


<s> if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; } else { assert ( Opc == <STR_LIT> && <STR_LIT> ) ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT>


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O << <STR_LIT> ; printOperand ( MI , OpNo ) ; O << <STR_LIT> ; return false


<s> static DecodeStatus DecodeMVEPairVectorIndexOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( start


<s> code = GEU ; } break ; case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_1_ccno ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_ext_1_cc ( scratch , scratch , const1_rtx ) ) ; code = NE ; } break ; case LE : case UNLE : if ( code == LE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = LTU ; } else { emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case EQ : case UNEQ : if ( code == EQ && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT (


<s> bool SelectShiftRegShifterOperand ( SDValue N , SDValue & A , SDValue & B , SDValue


<s> return ( __m128i ) vec_cmpeq ( ( __v2di ) __X ,


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! MF . getTarget ( )

. Options . RealignStack ) return false ;


<s> return __builtin_ia32_vcvtph2psx128_mask ( __B , _mm_setzero_ps ( ) ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2AddrModeImm7 ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) ,


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getTheARM64Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getTheARM64Target ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getTheARM64_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getTheARM64_32Target ( ) , create<ISA_LIT>ExternalSymbolizer


<s> return TPWithOff ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue SymAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; } else llvm_unreachable


<s> REAL_VALUE_TYPE r ; if ( GET_MODE ( x ) == VOIDmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return !


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill


<s> return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType ::


<s> RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; } } else if ( NoCrypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT>


<s> FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias , * Mang ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; OutStreamer -> EmitBytes ( Flags )


<s> if ( ! Src1Ty . isVector ( ) || ! Src2Ty . isVector ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned BytesPerElt = DstTy . getElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < Constant * , <NUM_LIT> > CstIdxs ; for ( int Val : Mask ) { Val = Val < <NUM_LIT> ? <NUM_LIT> : Val ; for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIB ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIB ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; auto TBL1 = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI ,


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> hasPreallocatedCall ( )


<s> case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getOnesVector ( ExtVT ,


<s> return ( int32x2_t ) __builtin_neon_vcvtsv2sf


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx


<s> unsigned EltSize = Val -> getScalarSizeInBits ( ) ; if ( EltSize == <NUM_LIT> ) { unsigned MfvsrdIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrdIndex ) return <NUM_LIT> ; } else if ( EltSize == <NUM_LIT> ) { unsigned MfvsrwzIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrwzIndex ) return <NUM_LIT> ; } return CostFactor ; } else if ( ST -> hasDirectMove ( ) ) return <NUM_LIT> ; } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> ) LHSPenalty


<s> if ( TailCall . getOpcode ( ) != <STR_LIT> && TailCall . getOpcode ( ) != <STR_LIT> ) { return false ; } if ( Subtarget . isTargetWin64 ( ) ) { return false ; } assert ( BranchCond . size ( ) == <NUM_LIT> ) ; if ( BranchCond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) { return false ; } const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = TailCall . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getTCReturnAddrDelta ( ) != <NUM_LIT> || TailCall . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { return


<s> HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false


<s> ScheduleHazardRecognizer :: HazardType <ISA_LIT>HazardRecognizer970 :: getHazardType ( SUnit * SU , int Stalls ) { assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return NoHazard ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return NoHazard ; if ( NumIssued != <NUM_LIT> && ( isFirst || isSingle ) ) return Hazard ; if ( isCracked && NumIssued > <NUM_LIT> ) return Hazard ; switch ( InstrType ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> if ( ST -> isSwift ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( )


<s> return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind ::


<s> bool isVecListTwoDByteIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( )


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ,


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . add ( predOps ( Pred

, PredReg ) ) . setMIFlags ( MIFlags ) ;


<s> if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return NON_PREFIXED_DEFAULT ; unsigned int r = reg_or_subregno ( reg ) ; if ( ! HARD_REGISTER_NUM_P ( r ) ) return NON_PREFIXED_DEFAULT ; unsigned size = GET_MODE_SIZE ( mode ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode || size == <NUM_LIT> || FLOAT128_2REG_P ( mode ) ) return NON_PREFIXED_D ; else if ( size < <NUM_LIT> ) return NON_PREFIXED_X ; else if ( TARGET_VSX && size >= <NUM_LIT> && ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || mode == TImode || mode == CTImode ) ) return ( TARGET_P9_VECTOR ) ? NON_PREFIXED_DQ : NON_PREFIXED_X ; else return NON_PREFIXED_DEFAULT ; } else if ( ALTIVEC_REGNO_P ( r ) ) { if ( ! TARGET_P9_VECTOR


<s> if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ExternalSymbolSDNode * S = cast < ExternalSymbolSDNode > ( JumpTarget ) ; JumpTarget = getAddrGlobal ( S , CLI . DL , JumpTarget . getValueType ( ) , DAG , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( S -> getSymbol ( ) ) ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) <STR_LIT> , Callee ) ) ; } Ops . push_back ( JumpTarget


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) .


<s> unsigned And_imm = <NUM_LIT> ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isOpcWithIntImmediate ( N , <STR_LIT> , And_imm ) ) { if ( And_imm & ( And_imm + <NUM_LIT> ) ) return nullptr ; unsigned Srl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = countTrailingOnes ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SwitchEQNEToPLMI = false ; if ( ! Subtarget -> isThumb ( ) ) return ; SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isZero ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm ) -> SDNode * { if ( Subtarget -> isThumb2 ( ) ) { Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } else { SDValue Ops [ ] = { CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } } ; if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode (


<s> } else { DestBB -> setLogAlignment ( <NUM_LIT> ) ; Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return true


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } const <ISA_LIT>FunctionInfo * AFI_Caller = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e


<s> return ResultReg ; } unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; EmitInst ( <STR_LIT> , TmpReg ) . addImm ( Hi ) ; EmitInst ( <STR_LIT> , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else { EmitInst ( <STR_LIT> , ResultReg ) . addImm ( Hi


<s> RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS , RHS , Ops ) ; return DAG . getNode ( <STR_LIT> , dl


<s> static bool doesCalleeRestoreStack ( CallingConv :: ID CallConv , bool TailCallOpt ) { return CallConv == CallingConv ::