<s> SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; } if ( FromEltVT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Extends ; for ( unsigned i = <NUM_LIT> ; i < Loads . size ( ) ; i ++ ) { SDValue LoadBC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ i ] ) ; SDValue FPExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadBC , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Extends . push_back


<s> } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasThumb2DSP ( ) && (

Mask & <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { if ( SDValue Elt = getShuffleScalarElt ( Op , i , DAG , <NUM_LIT> ) ) { Elts . push_back ( Elt ) ; continue ; } return SDValue


<s> return new <ISA_LIT>FastISel ( funcInfo , libInfo


<s> RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) { if ( LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } else if ( LHS == FalseVal && RHS == TrueVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) || MF . hasEHFunclets ( ) ) { if ( needsStackRealignment ( MF ) ) return


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget . isELFv2ABI ( ) ) { <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer . getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( <NUM_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) || TM . getRelocationModel ( ) != Reloc :: PIC_ ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; assert ( TM . getCodeModel ( ) != CodeModel :: Small


<s> Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } Base = DAG . getRegister ( <STR_LIT> , N . getValueType ( ) ) ; Index =


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction &


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn ) ) ) return true ; return false


<s> if ( isPromotableZeroStoreOpcode ( MI ) && getLdStRegOp ( MI ) . getReg ( ) != <STR_LIT> ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator MergeMI = findMatchingInsn ( MBBI , Flags , LdStLimit , true ) ; if ( MergeMI != E )


<s> MCValue Val ; if ( ! E -> EvaluateAsRelocatable ( Val , nullptr , nullptr ) ) return false ; if ( ! Val . getSymA ( ) || Val . getSymA ( )

-> getSymbol ( ) . isUndefined ( ) ) return false ;


<s> DebugLoc Loc ; MachineBasicBlock & Entry = * MF . begin ( ) ; auto EntryInsertPt = Entry . SkipPHIsLabelsAndDebug ( Entry . begin ( ) ) ; bool HasVulnerableLoad = hasVulnerableLoad ( MF ) ; SmallVector < BlockCondInfo , <NUM_LIT> > Infos = collectBlockCondInfo ( MF ) ; if ( ! HasVulnerableLoad && Infos . empty ( ) ) return true ; const int PoisonVal = - <NUM_LIT> ; PS -> PoisonReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PS -> PoisonReg ) . addImm ( PoisonVal ) ; ++ NumInstsInserted ; if ( HasVulnerableLoad && FenceCallAndRet ) { BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) ) ; ++ NumInstsInserted ; ++ NumLFENCEsInserted ; } if ( FenceCallAndRet && Infos . empty ( ) ) return true ; if ( HardenInterprocedurally && ! FenceCallAndRet ) { PS -> InitialReg = extractPredStateFromSP ( Entry , EntryInsertPt , Loc ) ; } else { PS -> InitialReg = MRI -> createVirtualRegister ( PS -> RC ) ; unsigned PredStateSubReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto ZeroI = BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateSubReg ) ; ++ NumInstsInserted ; MachineOperand * ZeroEFLAGSDefOp = ZeroI -> findRegisterDefOperand ( <STR_LIT> ) ; assert ( ZeroEFLAGSDefOp && ZeroEFLAGSDefOp -> isImplicit ( ) && <STR_LIT> ) ; ZeroEFLAGSDefOp -> setIsDead ( true ) ; BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PS -> InitialReg ) . addImm ( <NUM_LIT> ) . addReg ( PredStateSubReg ) . addImm ( <STR_LIT> ) ; } canonicalizePHIOperands ( MF ) ; PS -> SSA . Initialize ( PS -> InitialReg ) ; PS -> SSA . AddAvailableValue ( & Entry , PS -> InitialReg ) ; auto CMovs = tracePredStateThroughCFG ( MF , Infos ) ; if ( HardenInterprocedurally ) { for ( MachineBasicBlock & MBB : MF ) { assert ( ! MBB . isEHScopeEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isEHFuncletEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isCleanupFuncletEntry ( ) && <STR_LIT> ) ; if ( ! MBB . isEHPad ( ) ) continue ; PS -> SSA . AddAvailableValue ( & MBB , extractPredStateFromSP ( MBB , MBB . SkipPHIsAndLabels ( MBB . begin ( ) ) , Loc ) ) ; } } if ( HardenIndirectCallsAndJumps ) unfoldCallAndJumpLoads ( MF ) ; tracePredStateThroughBlocksAndHarden ( MF ) ; for ( MachineInstr * CMovI : CMovs ) for ( MachineOperand &


<s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : RegisterBankInfo ( <STR_LIT> ) { createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBFPR = getRegBank ( <STR_LIT> ) ; ( void ) RBFPR ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBCCR = getRegBank ( <STR_LIT> ) ; ( void ) RBCCR ; assert ( RBCCR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBCCR . getSize ( ) == <NUM_LIT>


<s> if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiMul = & MULOp ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 -> getOpcode ( ) == Opc ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 -> getOpcode ( ) == Opc ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( LoMul -> getNode ( ) != HiMul -> getNode ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> )


<s> rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ; if ( val & <NUM_LIT> ) return IN_RANGE (


<s> static StringRef select<ISA_LIT>ArchFeature ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; if ( CPU . empty ( ) || CPU


<s> enum { N = <NUM_LIT> , Z = <NUM_LIT> , C = <NUM_LIT> , V = <NUM_LIT> } ; switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case HS : return C ; case LO : return <NUM_LIT> ; case MI : return


<s> static SDValue PerformOrCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue R = CMPEQCombine ( N , DAG , DCI , Subtarget ) ; if ( R . getNode ( ) ) return R ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ! Subtarget -> hasSSSE3 ( ) || ( VT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue Amt = Mask . getOperand ( <NUM_LIT> ) ; if ( isSplatVector ( Amt . getNode ( ) ) ) { SDValue SclrAmt = Amt -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( SclrAmt ) ) SraAmt = C


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( WriteBack ) { if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT MaskEltVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> static DecodeStatus DecodeVecShiftL32Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void


<s> static void assureFPCallStub ( Function & F , Module * M , const <ISA_LIT>TargetMachine & TM ) { if ( TM . isPositionIndependent ( ) ) return ; LLVMContext & Context = M -> getContext ( ) ; bool LE = TM . isLittleEndian ( ) ; std :: string Name ( F . getName ( ) ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; std :: string AsmText ; AsmText += <STR_LIT> ; AsmText += swapFPIntParams ( PV , M , LE , true ) ; if ( RV != NoFPRet ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } else { AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } switch ( RV ) { case FRet : AsmText += <STR_LIT> ; break ; case DRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CFRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CDRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText +=


<s> unsigned <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { switch ( cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true


<s> static const CostTblEntry ShuffleTbl [ ] = { { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost


<s> Value * <ISA_LIT>IREmitter :: visitVZEXT_LOAD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> return ( __m128 ) __builtin_ia32_ps_ps256 ( (


<s> static DecodeStatus DecodeShiftRight16Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val )


<s> RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I8 : RTLIB :: UDIV_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I16 : RTLIB :: UDIV_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I32 : RTLIB :: UDIV_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I64 : RTLIB :: UDIV_I64 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I128 :


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm4 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> ) |


<s> bool <ISA_LIT>DAGToDAGISel :: tryIntCompareInGPR ( SDNode * N ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> && N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return false ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None || ! TM . is<ISA_LIT>64 ( ) ) return false ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT>


<s> if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; if ( ! isUnary ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM

, CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> :


<s> while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || (

OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ;


<s> Tmp . addOperand ( MCOperand :: CreateReg ( Reg64 ) ) ; Tmp . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Out . EmitInstruction (


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg

( ) == <STR_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) {


<s> void <ISA_LIT>InstPrinter :: printS8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printSImmOperand < <NUM_LIT> > ( MI


<s> case MEK_GOT_PAGE : OS << <STR_LIT> ; break ; case MEK_GOT_OFST : OS << <STR_LIT> ; break ; case MEK_GPREL : OS << <STR_LIT> ; break ; case MEK_HI : OS << <STR_LIT> ; break ; case MEK_HIGHER : OS << <STR_LIT> ; break ; case MEK_HIGHEST : OS << <STR_LIT> ; break ; case MEK_LO : OS << <STR_LIT> ; break ; case MEK_NEG : OS << <STR_LIT> ; break ; case MEK_PCREL_HI16 : OS << <STR_LIT> ; break ; case MEK_PCREL_LO16 : OS << <STR_LIT> ; break ; case MEK_TLSGD : OS <<


<s> void <ISA_LIT>ELFDynamic :: applyTargetEntries ( const ELFFileFormat & pFormat ) { if ( config ( ) . options ( ) . hasNow ( ) ) { if ( pFormat . hasGOT ( ) ) applyOne ( llvm :: ELF :: DT_PLTGOT , pFormat . getGOT ( ) . addr ( ) ) ; } else


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI = MBB ; if ( llvm :: next ( MBBI ) == MBB -> getParent ( )


<s> MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> EmitAssignment ( S , MCConstantExpr :: create ( int64_t ( <NUM_LIT> ) , MMI -> getContext ( ) ) ) ; } } OutStreamer -> EmitSyntaxDirective


<s> Align MaxAlign = MFI . getMaxAlign ( ) ; bool HasRedZone = Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) ; return ( IsLargeFrame || ! HasRedZone ) &&


<s> if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val , S , EndLoc ) ) ; return


<s> rtx i = NULL ; const unsigned HOST_WIDE_INT fpbits = TARGET_FMOVD ? ( FPSCR_PR | FPSCR_SZ ) : FPSCR_PR ; if ( prev_mode != FP_MODE_NONE && prev_mode != mode ) i = gen_xorsi3 ( tmp , tmp , force_reg ( SImode , GEN_INT ( fpbits ) ) ) ; else if ( mode == FP_MODE_SINGLE ) i = gen_andsi3 ( tmp , tmp , force_reg ( SImode , GEN_INT ( ~ fpbits ) ) ) ; else if ( mode == FP_MODE_DOUBLE ) i = gen_iorsi3 ( tmp , tmp , force_reg ( SImode , GEN_INT ( fpbits )


<s> const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; if ( OpFlags != <STR_LIT> ) assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags


<s> unsigned getGPRCalleeSavedArea2Size (


<s> bool isLRSpilled ( ) const { return LRSpilled


<s> const char * x86DisassemblerGetInstrName ( unsigned Opcode , void * mii ) { const MCInstrInfo * MII = static_cast < const MCInstrInfo * > ( mii ) ; return MII -> getName ( Opcode )


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UserOffset = getUserOffset ( U ) ; int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = llvm :: find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase


<s> gcc_assert ( preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT ) ; gcc_assert ( preferred_alignment <= stack_alignment_needed ) ; if ( TARGET_SEH ) cfun -> machine -> use_fast_prologue_epilogue = false ; else if ( ! optimize_bb_for_size_p ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) && cfun -> machine -> use_fast_prologue_epilogue_nregs != frame -> nregs ) { int count = frame -> nregs ; struct cgraph_node * node = cgraph_node :: get ( current_function_decl ) ; cfun -> machine -> use_fast_prologue_epilogue_nregs = count ; if ( count ) count = ( count - <NUM_LIT> ) * FAST_PROLOGUE_INSN_COUNT ; if ( node -> frequency < NODE_FREQUENCY_NORMAL || ( flag_branch_probabilities && node -> frequency < NODE_FREQUENCY_HOT ) ) cfun -> machine -> use_fast_prologue_epilogue = false ; else cfun -> machine -> use_fast_prologue_epilogue = ! expensive_function_p ( count ) ; } frame -> save_regs_using_mov = ( TARGET_PROLOGUE_USING_MOVE && cfun -> machine -> use_fast_prologue_epilogue && flag_stack_check != STATIC_BUILTIN_STACK_CHECK ) ; offset = UNITS_PER_WORD ; if ( ix86_static_chain_on_stack ) offset += UNITS_PER_WORD ; if ( frame_pointer_needed ) offset += UNITS_PER_WORD ; frame -> hfp_save_offset = offset ; frame -> hard_frame_pointer_offset = offset ; offset += frame -> nregs * UNITS_PER_WORD ; frame -> reg_save_offset = offset ; if ( TARGET_SEH ) frame -> hard_frame_pointer_offset = offset ; if ( frame -> nsseregs ) { if ( ix86_incoming_stack_boundary >= <NUM_LIT> ) offset = ROUND_UP ( offset , <NUM_LIT> ) ; offset += frame -> nsseregs * <NUM_LIT> ; } frame -> sse_reg_save_offset = offset ; if ( stack_realign_fp ) offset = ROUND_UP ( offset , stack_alignment_needed ) ; frame -> va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size ; offset += frame ->


<s> bool RegisterOnly = ( bool ( C . CCMask & <STR_LIT> ) != bool ( C . CCMask & <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( RegisterOnly , <STR_LIT> ) ) ; } return DAG . getNode ( C . Opcode , DL , <STR_LIT> ,


<s> Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return getDirectBrEncoding ( MI , OpNo , Fixups ,


<s> bool isExtend64 ( ) const { if ( ! isExtend (


<s> <ISA_LIT>64elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM


<s> if ( SIBLING_CALL_P ( insn ) ) { if ( direct_p ) { if ( ix86_nopic_noplt_attribute_p ( call_op ) ) { if ( TARGET_64BIT ) xasm = <STR_LIT> ; else xasm = <STR_LIT> ; } else xasm = <STR_LIT> ; } else if ( TARGET_SEH ) xasm = <STR_LIT> ; else xasm = <STR_LIT> ; output_asm_insn ( xasm , & call_op ) ; return <STR_LIT> ; } if ( TARGET_SEH ) { rtx_insn * i ; for ( i = NEXT_INSN ( insn ) ; i ; i = NEXT_INSN ( i ) ) { if ( INSN_P ( i ) ) break ; if ( NOTE_P ( i ) && NOTE_KIND ( i ) == NOTE_INSN_EPILOGUE_BEG && ! flag_non_call_exceptions && ! can_throw_internal ( insn ) ) { seh_nop_p = true ; break ; } } if ( i == NULL ) seh_nop_p = true ; } if ( direct_p ) { if ( ix86_nopic_noplt_attribute_p ( call_op ) ) { if ( TARGET_64BIT ) xasm = <STR_LIT> ; else xasm =


<s> static scalar_int_mode sparc_cstore_mode ( enum insn_code icode ATTRIBUTE_UNUSED ) { return ( TARGET_ARCH64 ? DImode


<s> unsigned <ISA_LIT>16InstrInfo :: whichOp8u_or_16simm ( unsigned shortOp , unsigned longOp , int64_t Imm ) { if ( isUInt < <NUM_LIT> > ( Imm ) )


<s> return TargetTriple . getVendor ( ) == Triple


<s> LHS = DAG . getNode ( <STR_LIT> , dl , OpVT , LHS , Amt ) ; RHS = DAG . getNode ( <STR_LIT> , dl , OpVT , RHS , Amt ) ; } else { SDValue Mask = DAG . getConstant ( ( <NUM_LIT> << EltSizeInBits ) - <NUM_LIT> , dl , OpVT ) ; LHS = DAG . getNode ( <STR_LIT> , dl , OpVT , LHS , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , OpVT , RHS , Mask ) ; } ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; } ; if ( ! PackHiHalf ) { LHS = DAG . getNode ( <STR_LIT> , dl , OpVT , LHS , Amt ) ; RHS = DAG . getNode ( <STR_LIT> , dl , OpVT , RHS , Amt ) ; } LHS = DAG . getNode ( <STR_LIT> , dl , OpVT , LHS , Amt ) ; RHS = DAG . getNode ( <STR_LIT> , dl , OpVT , RHS , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS ,


<s> if ( ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( N0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = N0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ; } SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , TLI . getPointerTy ( ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue tmp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , widenType , & Ops [ <NUM_LIT> ] ,


<s> RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; } I . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * I . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Depth = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; if ( Depth == <NUM_LIT> && IntrinID == <STR_LIT> ) { if ( ! MFReturnAddr ) { MFI . setReturnAddressIsTaken ( true ) ; MFReturnAddr = getFunctionLiveInPhysReg ( MF , TII , <STR_LIT> , <STR_LIT> ) ; } if ( STI . hasPAuth ( ) ) { MIB . buildInstr ( <STR_LIT> , { DstReg } , { MFReturnAddr } ) ; } else { MIB . buildCopy ( { Register ( <STR_LIT> ) } , { MFReturnAddr } ) ; MIB . buildInstr ( <STR_LIT> ) ; MIB . buildCopy ( { DstReg } , { Register ( <STR_LIT> ) } ) ; } I . eraseFromParent ( ) ; return true ; } MFI . setFrameAddressIsTaken ( true ) ; Register FrameAddr ( <STR_LIT> ) ; while ( Depth -- ) { Register NextFrame = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto Ldr = MIB . buildInstr ( <STR_LIT> , { NextFrame } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Ldr , TII , TRI , RBI ) ; FrameAddr = NextFrame ; } if ( IntrinID == <STR_LIT> ) MIB . buildCopy ( { DstReg } , { FrameAddr } ) ; else { MFI . setReturnAddressIsTaken ( true ) ; if ( STI . hasPAuth ( ) ) { Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . buildInstr ( <STR_LIT> , { TmpReg } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; MIB . buildInstr ( <STR_LIT> , { DstReg } , { TmpReg } ) ; } else { MIB . buildInstr ( <STR_LIT> , { Register ( <STR_LIT> ) } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; MIB . buildInstr ( <STR_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) ; unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ; TransferImpOps ( MI , MIB


<s> void <ISA_LIT>ELFDynamic :: applyTargetEntries ( const ELFFileFormat & pFormat ) { if ( pFormat . hasGOT ( ) ) applyOne ( llvm :: ELF :: DT_PLTGOT , pFormat . getGOT (


<s> bool <ISA_LIT>InstrInfo :: StoreRegToStackSlot ( MachineFunction & MF , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs , bool & NonRI , bool & SpillsVRS ) const { DebugLoc DL ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else { CmpMask = CmpValue = <NUM_LIT> ; } return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else { CmpMask = CmpValue = <NUM_LIT> ; } return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; } return


<s> else if ( AFI -> isDPRCalleeSavedAreaFrame ( FI ) ) Offset -= AFI -> getDPRCalleeSavedAreaOffset ( ) ; else if ( needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } } else if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || MFI -> hasVarSizedObjects ( ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , <NUM_LIT> , CCInfo . getInRegsParamsCount ( ) ,

<NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ;


<s> IRBuilder < > PreBuilder ( TileDP ) ; PreBuilder . SetInsertPoint ( TileDP ) ; Value * NDWord = PreBuilder . CreateLShr ( N , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; Value * KDWord = PreBuilder . CreateLShr ( K , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; BasicBlock * Start = InsertI -> getParent ( ) ; BasicBlock * End = SplitBlock ( InsertI -> getParent ( ) , InsertI , & DTU , LI , nullptr , <STR_LIT> ) ; IRBuilder < > Builder ( TileDP ) ; Value * ResVec = createTileDPLoops < IntrID > ( Start , End , Builder , M , NDWord , KDWord , C , A , B ) ; Builder . SetInsertPoint ( End -> getFirstNonPHI ( ) ) ; Value * ResAMX = Builder . CreateBitCast ( ResVec , Type :: get<ISA_LIT>_AMXTy ( Builder . getContext ( ) ) ) ; for ( auto UI = TileDP -> use_begin ( ) , UE = TileDP -> use_end ( ) ; UI != UE ; ) { Instruction * I = cast < Instruction > ( ( UI ++ ) -> getUser ( ) ) ; Value * Vec ; if ( match ( I , m_BitCast ( m_Value ( Vec ) ) ) ) { I -> replaceAllUsesWith ( ResVec ) ; I -> eraseFromParent ( )


<s> SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; return


<s> if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is512BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i + <NUM_LIT> ) ) return false ; return true


<s> void <ISA_LIT>InstPrinter :: printMemExtend ( const MCInst * MI , unsigned OpNum , raw_ostream & O , char SrcRegKind , unsigned Width ) { bool SignExtend = MI -> getOperand ( OpNum ) . getImm ( ) ; bool DoShift = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm


<s> } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , ShiftVal , IsZExt ) ; break ; case Instruction :: AShr : ResultReg = emitASR_ri ( RetVT , SrcVT , Op0Reg , ShiftVal , IsZExt ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_ri ( RetVT , SrcVT , Op0Reg , ShiftVal , IsZExt ) ; break ; } if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op1Reg ) return false ; unsigned ResultReg = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_rr ( RetVT , Op0Reg , Op1Reg ) ; break ; case Instruction :: AShr : ResultReg = emitASR_rr ( RetVT , Op0Reg , Op1Reg ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_rr ( RetVT , Op0Reg


<s> RegList = RRegList ; unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; unsigned RegAlign = alignTo ( Align , <NUM_LIT> ) / <NUM_LIT> ; while ( RegIdx % RegAlign != <NUM_LIT> && RegIdx < RegList . size ( ) ) State . AllocateReg ( RegList [ RegIdx ++ ] ) ; break ; } case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx


<s> if ( Ty -> isVectorTy ( ) && AM . BaseOffs != <NUM_LIT> && ! Subtarget . hasP9Vector ( ) ) return false ; if ( AM . BaseOffs <= - ( <NUM_LIT> << <NUM_LIT> ) || AM . BaseOffs >= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case <NUM_LIT> : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true


<s> rtx addr_pattern ; if ( addr_regno != reg_regno ) addr_pattern = gen_pcrel_opt_ld_addr ( addr_reg , addr_symbol , label_num , reg_di ) ; else addr_pattern = gen_pcrel_opt_ld_addr_same_reg ( addr_reg , addr_symbol , label_num ) ; validate_change ( addr_insn , & PATTERN ( addr_insn ) , addr_pattern , false ) ; rtvec v_load = gen_rtvec ( <NUM_LIT> , mem_inner , reg_di , label_num ) ; rtx new_load = gen_rtx_UNSPEC ( GET_MODE ( mem_inner ) , v_load , UNSPEC_PCREL_OPT_LD_RELOC ) ; if ( GET_CODE ( mem ) != GET_CODE ( mem_inner ) ) new_load = gen_rtx_fmt_e ( GET_CODE ( mem ) , reg_mode , new_load ) ; rtx new_load_set = gen_rtx_SET ( reg , new_load ) ; rtx load_clobber = gen_rtx_CLOBBER ( VOIDmode , ( addr_regno == reg_regno ? gen_rtx_SCRATCH ( Pmode ) : addr_reg ) ) ; rtx new_load_pattern = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , new_load_set , load_clobber ) ) ; validate_change ( load_insn , & PATTERN ( load_insn ) , new_load_pattern , false ) ; if ( ! apply_change_group ( ) ) { counters . failed_loads ++ ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( addr_insn ) , INSN_UID ( load_insn ) ) ; return ; } counters . loads ++ ; if ( next_nonnote_insn ( addr_insn ) == load_insn ) counters . adjacent_loads ++ ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( addr_insn ) , INSN_UID ( load_insn


<s> ShuffleSrcs [ i ] = SourceVecs [ i ] ; VEXTOffsets [ i ] = <NUM_LIT> ; continue ; } else if ( SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) < NumElts ) { return SDValue ( ) ; } assert ( SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> * NumElts && <STR_LIT> ) ; if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts ) { VEXTOffsets [ i ] = <NUM_LIT> ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { VEXTOffsets [ i ] = MinElts [ i ] ; SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( VEXTOffsets [ i ] , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts


<s> O << <STR_LIT> << LabelId << <STR_LIT> << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << <STR_LIT> ; O << <STR_LIT>


<s> } <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( TrueVal , FalseVal ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>CC2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT ,

Result , TrueVal , <ISA_LIT>CC2 , CCR , Cmp2 ) ;


<s> int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , ByteSize , ByteSize ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( SSFISize , SSFISize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Result , StackSlot , DAG . getValueType ( Op . getValueType ( ) ) , InFlag } ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack (

SSFI ) , MachineMemOperand :: MOStore , SSFISize , SSFISize ) ;


<s> if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != Ins . size ( ) ; i ++ ) { <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) )


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { PatternNodeWithChain = N ; if ( IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , Parent , Root , OptLevel ) ) { auto * MI = cast < MemIntrinsicSDNode > ( PatternNodeWithChain ) ; return selectAddr ( MI , MI -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , N . getNode ( ) , Root , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; return selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index ,


<s> unsigned NativeWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( )

== AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ;


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg


<s> uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; int64_t Offset = getFrameIndexOffset ( MF , Save . getFrameIdx ( ) ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , SPOffsetFromCFA +


<s> if ( crtl -> args . size <= <NUM_LIT> && crtl -> args . size != - <NUM_LIT> ) { if ( layout . frame_size - INCOMING_FRAME_SP_OFFSET + crtl -> args . size <= <NUM_LIT> ) layout . fp_minus_ap = layout . frame_size - INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = <NUM_LIT> - crtl -> args . size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size - INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size - INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( <STR_LIT> ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; Reserved . set ( <STR_LIT> ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Register BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> StubLayout Result = { <NUM_LIT> * <NUM_LIT> + <NUM_LIT> , <NUM_LIT> } ; return Result


<s> <ISA_LIT>InstrInfo :: BranchType R = TII -> AnalyzeBranch ( MBB , TrueBB , FalseBB , Cond , false , BranchInstrs ) ; if ( ( R == <ISA_LIT>InstrInfo :: BT_None ) || ( R == <ISA_LIT>InstrInfo :: BT_NoBranch ) ) return std :: make_pair ( R , nullptr ) ; if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Cond , BranchInstrs [ <NUM_LIT> ] ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) && ( FalseBB == & Dst ) ) return std :: make_pair (

<ISA_LIT>InstrInfo :: BT_Uncond , BranchInstrs [ <NUM_LIT> ] ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) ,


<s> for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg , i } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder ,


<s> return llvm :: is_sorted ( ArgLocs , [ ] ( const CCValAssign & A , const CCValAssign & B ) -> bool { return A . getValNo ( )


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MemTy = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = buildLoad ( LLT :: scalar ( <NUM_LIT> ) , Addr , MemTy , MPO ) ; MIRBuilder . buildTrunc ( ValVReg , LoadVReg ) ; } else


<s> bool isDoubleSpacedVectorAllLanes ( ) const { return Kind == k_VectorListAllLanes && VectorList


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) .

addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MI -> isCall ( ) && MO . isRegMask ( ) && !

clobbersAllYmmRegs ( MO ) ) return true ;


<s> return ( __m128d ) __builtin_ia32_minpd ( ( __v2df )


<s> if ( j == <NUM_LIT> ) break ; if ( ! BucketChain . Elements [ j ] . Offset || BucketChain . Elements [ j ] . Offset -> isZero ( ) ) break ; const SCEV * Offset = BucketChain . Elements [ j ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant > ( SE -> getNegativeSCEV ( Offset ) ) ; } std :: swap ( BucketChain . Elements [ j ] , BucketChain . Elements


<s> if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv ::


<s> bool NZCVKilled = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor (


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames

( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) {


<s> if ( ! II -> mayStore ( ) || ! II -> hasOneMemOperand ( ) ) continue ; const Value * MemPtr = II -> memoperands ( ) [ <NUM_LIT> ] -> getValue ( ) ; if ( ! MemPtr ) continue ; StringRef Name = MemPtr -> getName ( ) ; if ( ! Name . startswith ( <STR_LIT> ) ) continue ; auto N = Name . find ( <STR_LIT> ) ; StringRef STileIdx = Name . slice ( <NUM_LIT> ,


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return <STR_LIT>


<s> SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT>


<s> SDLoc dl ( Op ) ; if ( Subtarget -> hasDivide ( ) && Op -> getValueType ( <NUM_LIT> ) . isSimple ( ) && Op -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> ) { unsigned DivOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; const SDValue Dividend = Op -> getOperand ( <NUM_LIT> ) ; const SDValue Divisor = Op -> getOperand ( <NUM_LIT> ) ; SDValue Div = DAG . getNode ( DivOpcode , dl , VT , Dividend , Divisor ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , VT , Div , Divisor ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , dl , VT , Dividend , Mul ) ; SDValue Values [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , Values ) ; } RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT


<s> AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr . getOperand ( <NUM_LIT> ) ; if ( dyn_cast < ConstantPoolSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = LoVal . getOperand ( <NUM_LIT> ) ; return true ; } } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> if ( mode == VOIDmode ) return satisfies_constraint_I06 ( op ) ; size = GET_MODE_SIZE ( mode ) ; return ( ! ( INTVAL ( op ) & ( size - <NUM_LIT> ) ) && INTVAL ( op ) >= - <NUM_LIT> * size && INTVAL ( op ) < <NUM_LIT> * size ) ; } else { const HOST_WIDE_INT offset = INTVAL ( op


<s> AssemblerOptions . back ( ) -> setNoReorder ( ) ; getTargetStreamer ( ) . emitDirectiveSetNoReorder ( ) ; Parser . Lex (


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return &


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ; setIndexedStoreAction ( im , VT . getSimpleVT ( )


<s> return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Node -> getChain ( ) , Node -> getBasePtr (

) , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ;


<s> tree ix86_builtin_decl ( unsigned code , bool ) { if ( code >= IX86_BUILTIN_MAX ) return error_mark_node ; return ix86_builtins [ code


<s> unsigned SType = <NUM_LIT> ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG

. getConstant ( SType , DL , <STR_LIT> ) ) ;


<s> rtx tmp ; rtx p ; rtx jmp ; gcc_assert ( GET_CODE ( PATTERN ( branch ) ) == SEQUENCE ) ; if ( INSN_DELETED_P ( branch ) ) return NULL_RTX ; slot = XVECEXP ( PATTERN ( branch ) , <NUM_LIT> , <NUM_LIT> ) ; tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( tmp ) return NULL_RTX ; jmp = XVECEXP ( PATTERN ( branch ) , <NUM_LIT> , <NUM_LIT> ) ; tmp = PATTERN ( jmp ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( ! tmp ) return branch ; p = PREV_INSN ( branch ) ; NEXT_INSN ( p ) = slot ; PREV_INSN ( slot ) = p ; NEXT_INSN ( slot ) = jmp ; PREV_INSN ( jmp


<s> MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) { moveToTop ( Reg , I ) ; assert ( StackTop > <NUM_LIT> &&


<s> void onDispExpr ( ) { switch ( State ) { default : State = IBES_ERROR ; break ; case IBES_START : State = IBES_DISP_EXPR


<s> if ( Mask . getSimpleValueType ( ) == <STR_LIT> && Subtarget . is32Bit ( ) ) { if ( MaskVT == <STR_LIT> ) { assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> ,


<s> return ( _TEXASRU_EXTRACT_BITS ( texasru , <NUM_LIT> ,


<s> if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT>


<s> unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; const MCInstrDesc & MCID = get ( Opc ) ; MachineInstrBuilder MIB = BuildMI ( & MBB , DL , MCID ) ; for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { if ( Cond [ i ] . isReg ( ) ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; else if ( Cond [ i ] . isImm ( ) ) MIB . addImm ( Cond [ i ] . getImm ( ) ) ; else assert ( false && <STR_LIT> ) ; } MIB . addMBB (


<s> return ( int32x2_t ) __builtin_neon_vreinterpretv2siv4hi ( (


<s> return isImm ( ) && dyn_cast < MCConstantExpr > (


<s> case CmpInst :: FCMP_ORD : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_OEQ : LLVM_FALLTHROUGH ; case CmpInst :: FCMP_UNE : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_UGE : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_ULT : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_ULE : CC = <STR_LIT> ; break ; case CmpInst :: ICMP_SGT : CC =


<s> int eq_neq_comparison_operator ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == EQ || GET_CODE


<s> return DecodeSysRegOperand ( <STR_LIT> ( ) , Inst ,


<s> if ( OrigTy . getSizeInBits ( ) >= <NUM_LIT> ) return N ; EVT NewVT = getExtensionTo64Bits ( OrigTy ) ; return DAG . getNode ( ExtOpcode , SDLoc ( N ) , NewVT


<s> void pushReg ( unsigned Reg ) { assert ( Reg < <NUM_LIT> && <STR_LIT> ) ; assert ( StackTop < <NUM_LIT>


<s> Value * <ISA_LIT>DCInstruction :: translateScaledImmediate ( unsigned MIOperandNo , unsigned Scale , unsigned Bits ) { APInt Val = APInt ( Bits , getImmOp


<s> vec_uchar16 av ; vec_uchar16 cnt_hi , cnt_lo , cnt , tmp1 , tmp2 , tmp3 ; vec_uchar16 four = vec_splat_u8 ( <NUM_LIT> ) ; vec_uchar16 nib_cnt = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uchar16 eight = vec_splat_u8 ( <NUM_LIT> ) ; vec_uchar16 sixteen = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uchar16 twentyfour = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; av = ( vec_uchar16 ) ( a ) ; cnt_hi = vec_perm ( nib_cnt , nib_cnt , vec_sr ( av , four ) ) ; cnt_lo = vec_perm ( nib_cnt , nib_cnt , av ) ; cnt = vec_add ( cnt_hi , vec_and ( cnt_lo , vec_cmpeq ( cnt_hi , four ) ) ) ; tmp1 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( eight ) ) ; tmp2 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( sixteen ) ) ; tmp3 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( twentyfour ) ) ; cnt = vec_add ( cnt , vec_and ( tmp1 , vec_cmpeq ( cnt , eight ) ) ) ; cnt = vec_add ( cnt , vec_and ( tmp2 , vec_cmpeq ( cnt , sixteen ) ) ) ; cnt = vec_add ( cnt , vec_and ( tmp3 , vec_cmpeq ( cnt , twentyfour ) ) ) ; return ( qword ) ( ( vec_sr ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) (


<s> if ( ! isa < IntegerType > ( V -> getType ( ) ) ) return false ; if ( isa < StoreInst > ( I ) || isa < TerminatorInst > ( I ) || isa < TruncInst > ( I ) || isa < ICmpInst > ( I ) ) return false ; if ( auto * ZExt = dyn_cast < ZExtInst > ( I ) ) return ! ZExt -> getDestTy ( ) -> isIntegerTy ( <NUM_LIT> ) ; return true


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_ShifterImmediate ) ; Op -> ShifterImm . isASR = isASR ; Op -> ShifterImm . Imm = Imm ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( Conversion . XORValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . XORValue , DL , <STR_LIT> ) ) ; if ( Conversion . AddValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . AddValue , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . Bit , DL , <STR_LIT> ) ) ; if ( Conversion . Bit != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>

, Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , TM ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified =


<s> return __builtin_mve_vshrq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a ,


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT>


<s> assert ( ! CFlags . IsPatchPoint && <STR_LIT> ) ; if ( isTOCSaveRestoreRequired ( Subtarget ) ) { const MCRegister StackPtrReg = Subtarget . getStackPointerRegister ( ) ; SDValue StackPtr = DAG . getRegister ( StackPtrReg , RegVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , StackPtr , TOCOff ) ; Ops . push_back ( AddTOC ) ; } if ( Subtarget . usesFunctionDescriptors ( ) && ! CFlags . HasNest ) Ops . push_back ( DAG . getRegister ( Subtarget . getEnvironmentPointerRegister ( ) , RegVT ) ) ; if ( CFlags . IsTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; } if ( CFlags . IsTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! CFlags . IsPatchPoint && ! Subtarget . isUsingPCRelativeCalls ( ) ) Ops . push_back ( DAG . getRegister ( Subtarget . getTOCPointerRegister ( ) , RegVT ) ) ; if ( CFlags . IsVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo


<s> bool single_dest_per_chain ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { for ( int i = v -> length ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { tag_insn_info * insn_info = ( * v ) [ i ] ; for ( int j = v -> length ( ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { if ( in_same_chain ( insn_info -> insn , ( * v ) [ j ] -> insn , REGNO ( insn_info -> dest ) ) ) { v -> ordered_remove ( j ) ; i = v -> length ( ) ; break ; } } } return true


<s> break ; case ZeroCompare :: LEZExt : case ZeroCompare :: LESExt : { if ( Is32Bit ) { LHS = signExtendInputIfNeeded ( LHS ) ; SDValue Neg = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , <NUM_LIT> ) ; ToExtend = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Neg , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } else { SDValue Addi = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; ToExtend = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addi , LHS ) , <NUM_LIT> ) ; } break ; } } if ( ! Is32Bit && ( CmpTy == ZeroCompare :: GEZExt || CmpTy == ZeroCompare :: LEZExt ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ToExtend , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( ! Is32Bit && ( CmpTy == ZeroCompare :: GESExt || CmpTy == ZeroCompare :: LESExt ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ToExtend , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; assert ( Is32Bit && <STR_LIT> ) ; switch ( CmpTy ) { case ZeroCompare :: GEZExt : { SDValue ShiftOps [ ] = { ToExtend , S -> getI32Imm ( <NUM_LIT> , dl ) , S -> getI32Imm ( <NUM_LIT> , dl ) , S -> getI32Imm ( <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; } case ZeroCompare :: GESExt : return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ToExtend , S -> getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; case ZeroCompare :: LEZExt


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S


<s> bool <ISA_LIT>AsmParser :: parseDirective<ISA_LIT> ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) || check ( ! has<ISA_LIT> ( ) , L , <STR_LIT> ) ) return true ; if ( isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32


<s> bool isTargetFreeBSD ( ) const { return TargetTriple .


<s> if ( ! MEM_P ( op ) ) return false ; if ( offsettable_address_p ( strict , GET_MODE ( op ) , XEXP ( op , <NUM_LIT>


<s> else { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; } ops [ <NUM_LIT> ] = reg ; break ; case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> ) templ = <STR_LIT> ; else templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; ops [ <NUM_LIT> ] = reg ; break ; } case LABEL_REF : case PLUS : { int i ; int overlap = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * i ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , DImode , <NUM_LIT> * i ) ; if ( reg_overlap_mentioned_p ( ops [ <NUM_LIT> ] , mem ) ) { gcc_assert ( overlap == - <NUM_LIT> ) ; overlap = i ; } else { sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } } if ( overlap != - <NUM_LIT> ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * overlap ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , SImode , <NUM_LIT> * overlap ) ; sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } return <STR_LIT> ; } default : gcc_unreachable ( )


<s> uint64_t MaxIndex = <NUM_LIT> ; uint64_t RetElSize = RetElVT . getStoreSize ( ) . getKnownMinSize ( ) ; ConstantSDNode * OffsetConst = dyn_cast < ConstantSDNode > ( Offset . getNode ( ) ) ; if ( nullptr == OffsetConst || OffsetConst -> getZExtValue ( ) > MaxIndex * RetElSize || OffsetConst -> getZExtValue ( ) % RetElSize ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType (


<s> assert ( DataTy -> isVectorTy ( ) && <STR_LIT> ) ; auto * VTy = cast < FixedVectorType > ( DataTy ) ; unsigned NumElems = VTy -> getNumElements ( ) ; unsigned EltSize = VTy -> getScalarSizeInBits ( ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; unsigned VectorCost = NumElems * LT . first ; unsigned ScalarCost = NumElems * LT . first + BaseT :: getScalarizationOverhead ( VTy , { } ) ; if ( Alignment < EltSize / <NUM_LIT> ) return ScalarCost ; unsigned ExtSize = EltSize ; if ( I != nullptr ) { if ( ( I -> getOpcode ( ) == Instruction :: Load || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && I -> hasOneUse ( ) ) { const User * Us = * I -> users ( ) . begin ( ) ; if ( isa < ZExtInst > ( Us ) || isa < SExtInst > ( Us ) ) { unsigned TypeSize = cast < Instruction > ( Us ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( TypeSize == <NUM_LIT> && ( EltSize == <NUM_LIT> || EltSize == <NUM_LIT> ) ) || ( TypeSize == <NUM_LIT> && EltSize == <NUM_LIT> ) ) && TypeSize * NumElems == <NUM_LIT> ) { ExtSize = TypeSize ; } } } TruncInst * T ; if ( ( I -> getOpcode ( ) == Instruction :: Store || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && ( T = dyn_cast < TruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) { unsigned TypeSize = T -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( EltSize == <NUM_LIT> && TypeSize == <NUM_LIT> ) || ( EltSize == <NUM_LIT> && ( TypeSize == <NUM_LIT> || TypeSize == <NUM_LIT> ) ) ) && TypeSize * NumElems == <NUM_LIT> ) ExtSize = TypeSize ; } } if ( ExtSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( ExtSize == <NUM_LIT> ) return VectorCost ; if ( ExtSize != <NUM_LIT> && ExtSize != <NUM_LIT> ) return ScalarCost ; if ( auto BC = dyn_cast < BitCastInst > ( Ptr ) ) Ptr = BC -> getOperand ( <NUM_LIT> ) ; if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) return ScalarCost ; unsigned Scale = DL . getTypeAllocSize ( GEP -> getResultElementType ( ) ) ; if ( Scale != <NUM_LIT> && Scale * <NUM_LIT> != ExtSize ) return ScalarCost ; if ( auto ZExt = dyn_cast < ZExtInst > ( GEP -> getOperand ( <NUM_LIT> ) ) ) { if ( ZExt -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) <= ExtSize ) return VectorCost ; } return ScalarCost


_mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCFPmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; case <NUM_LIT> : code = EQ ; break ; case <NUM_LIT> : emit_insn ( gen_move_from_CR_ov_bit ( target , scratch ) ) ; return target ; default : error ( <STR_LIT> ) ; return const0_rtx ; } tmp = gen_rtx_fmt_ee ( code , SImode , scratch , const0_rtx ) ; emit_move_insn ( target , tmp ) ; return target


<s> unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Out ) . addReg ( Reg1 ) . addImm ( <STR_LIT> ) . addReg ( Reg2 ) . addImm ( <STR_LIT> ) ; return Out


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , Min , Max , Val ) ) { OffImm = CurDAG -> getTargetConstant ( Val , SDLoc ( N )


<s> out = operands [ <NUM_LIT> ] ; in = force_reg ( mode , operands [ <NUM_LIT> ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , const_double_from_real_value ( REAL_VALUE_ATOF ( <STR_LIT> , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_FIX ( DImode , gen_rtx_FIX (


<s> if ( mode != TFmode && FLOAT128_IBM_P ( TFmode ) ) set_conv_libfunc ( sext_optab , mode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , IFmode , mode , <STR_LIT> ) ; if ( mode != TFmode && FLOAT128_IBM_P ( TFmode ) ) set_conv_libfunc ( trunc_optab , TFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SDmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT ) set_optab_libfunc ( sqrt_optab ,


<s> IsFixed . resize ( Ins . size ( ) , true ) ; CCState :: AnalyzeFormalArguments ( Ins


<s> static DecodeStatus DecodeFPR16RegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler


<s> iq2000_load_reg = <NUM_LIT> ; iq2000_load_reg2 = <NUM_LIT> ; iq2000_load_reg3 = <NUM_LIT> ; iq2000_load_reg4 = <NUM_LIT> ; return ret ; } set_reg = operands [ <NUM_LIT> ] ; if ( set_reg == <NUM_LIT> ) return ret ; while ( GET_CODE ( set_reg ) == SUBREG ) set_reg = SUBREG_REG ( set_reg ) ; mode = GET_MODE ( set_reg ) ; dslots_number_nops = num_nops ; iq2000_load_reg = set_reg ; if ( GET_MODE_SIZE ( mode ) > ( unsigned ) ( UNITS_PER_WORD ) ) iq2000_load_reg2 = gen_rtx_REG ( SImode


<s> EVT VT = Mld -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getScalarSizeInBits ( ) ; unsigned FromSz = LdVT . getScalarSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue


<s> MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( AddressRegI64 ) ) ; Op . addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT>


<s> if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc


<s> for ( ; B != E ; ++ B ) if ( ! B -> isDebugValue ( ) ) return B ; return


<s> __builtin_ia32_pmovwb128mem_mask ( ( unsigned long long * ) __P


<s> assert ( Node -> getIDom ( ) == HeadNode && <STR_LIT> ) ; while ( Node -> getNumChildren ( ) ) DomTree -> changeImmediateDominator ( Node -> getChildren ( ) . back ( ) , HeadNode ) ; DomTree -> eraseNode (


<s> bool isPositionIndependent ( ) const { return TM . isPositionIndependent


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i64scatter_epi32 ( int *


<s> return ( __m256i ) __builtin_ia32_vplzcntd_256_mask ( ( __v8si ) __A ,


<s> switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } unsigned ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes &&


<s>
void
FPOStateMachine
::
emitFrameDataRecord
(
MCStreamer
&
OS
,
MCSymbol
*
Label
)
{
unsigned
CurFlags
=
Flags
;
if
(
Label
==
FPO
->
Begin
)
CurFlags
|=
FrameData
::
IsFunctionStart
;
FrameFunc
.
clear
(
)
;
raw_svector_ostream
FuncOS
(
FrameFunc
)
;
const
MCRegisterInfo
*
MRI
=
OS
.
getContext
(
)
.
getRegisterInfo
(
)
;
assert
(
(
StackAlign
==
<NUM_LIT>
||
FrameReg
!=
<NUM_LIT>
)
&&
<STR_LIT>
)
;
StringRef
CFAVar
=
StackAlign
==
<NUM_LIT>
<STR_LIT>
:
<STR_LIT>
;
if
(
FrameReg
)
{
FuncOS
<<
CFAVar
<<
' '
<<
printFPOReg
(
MRI
,
FrameReg
)
<<
' '
<<
FrameRegOff
<<
<STR_LIT>
;
if
(
StackAlign
)
{
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
' '
<<
StackOffsetBeforeAlign
<<
<STR_LIT>
<<
StackAlign
<<
<STR_LIT>
;
}
}
else
{
FuncOS
<<
CFAVar
<<
<STR_LIT>
;
}
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
for
(
RegSaveOffset
RO
:
RegSaveOffsets
)
FuncOS
<<
printFPOReg
(
MRI
,
RO
.
Reg
)
<<
' '
<<
CFAVar
<<
' '
<<
RO
.
Offset
<<
<STR_LIT>
;
CodeViewContext
&
CVCtx
=
OS
.
getContext
(
)
.
getCVContext
(
)
;
unsigned
FrameFuncStrTabOff
=
CVCtx
.
addToStringTable
(
FuncOS
.
str
(
)
)
.
second
;
unsigned
MaxStackSize
=
<NUM_LIT>
;
OS
.
emitAbsoluteSymbolDiff
(
Label
,
FPO
->
Begin
,
<NUM_LIT>
)
;
OS
.
emitAbsoluteSymbolDiff
(
FPO
->
End
,
Label
,
<NUM_LIT>
)
;
OS
.
emitInt32
(
LocalSize
)
;
OS
.
emitInt32
(
FPO
->
ParamsSize
)
;
OS
.
emitInt32


<s> auto LowerAsEXTRQ = [ & ] ( ) { int Len = HalfSize ; for ( ; Len >= <NUM_LIT> ; -- Len ) if ( ! Zeroable [ Len - <NUM_LIT> ] ) break ; assert ( Len > <NUM_LIT> && <STR_LIT> ) ; SDValue Src ; int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( M > HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask , <NUM_LIT> , Idx ) ) { } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , <NUM_LIT> ) ) { Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else


<s> void <ISA_LIT>FlagsCopyLoweringPass :: rewriteCopy ( MachineInstr & MI , MachineOperand & FlagUse , MachineInstr