<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return , true ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align = GET_MODE_ALIGNMENT ( V4SFmode ) ; mem = choose_baseaddr ( cfa_offset , & align ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , align ) ; gcc_assert ( ! ( cfa_offset & ( align / BITS_PER_UNIT - <NUM_LIT> ) ) ) ; set_mem_align ( mem , align ) ; emit_insn ( gen_rtx_SET ( reg , mem ) ) ; ix86_add_cfa_restore_note ( NULL ,


<s> else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return NULL ; if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return NULL ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; break ; } } return foldMemoryOperandImpl ( MF , MI , Ops [ <NUM_LIT> ] ,


<s> } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; unsigned ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , true , OpReg


<s> Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++


<s> unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; if ( isThumb2 ) { MRI . constrainRegClass ( dest , & <STR_LIT> ) ; MRI . constrainRegClass ( ptr , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg )

. setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>InstPrinter :: printLogicalImm64 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint64_t Val = MI -> getOperand ( OpNum ) . getImm


<s> case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; } if ( ConvertedOp ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( WideVal . getOpcode ( ) , WideVT ) ) { SDValue V0 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( ConvertedOp , dl , VT , V0 , V1 ) ; } } } if ( Opcode == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , Op . getValueType ( ) ) ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op ->


<s> expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI )


<s> gcc_checking_assert ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) && REGNO ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name (


<s> switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ) ; case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( OpNum - OP_VEXT1 + <NUM_LIT> , dl , <STR_LIT> ) ) ; case OP_VUZPL


<s> void <ISA_LIT>FuchsiaTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize (


<s> unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; unsigned NumBytes = LinkageSize + <NUM_LIT> * PtrByteSize ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) report_fatal_error ( <STR_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SDValue InFlag ; if ( isTailCall )


<s> else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case E_V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case E_V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case E_V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case E_V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode &&


<s> while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr


<s> bool requiresRealignment = RealignStack && ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ; if ( <NUM_LIT> && requiresRealignment && MFI -> hasVarSizedObjects


<s> static DecodeStatus DecodeVecShiftR8Imm ( MCInst & Inst , unsigned Imm , uint64_t

Addr , const MCDisassembler * Decoder ) {


<s> return Op && PredicatedInsts . count ( Op ) && isPredicatedOnVCTP ( Op ) ; } ; auto IsOperandInvariant = [ & ] ( MachineInstr * MI , unsigned Idx ) { MachineOperand & MO = MI -> getOperand ( Idx ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) return true ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Defs ; RDA . getGlobalReachingDefs ( MI , MO . getReg ( ) , Defs ) ; if ( Defs . empty ( ) ) return true ; for ( auto * Def : Defs ) if ( Def -> getParent ( ) == VPT -> getParent ( ) ) return false ; return


<s> SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VT , N0 , ShiftAmt ) ; Created . push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op ) ; Created . push_back ( Op . getNode (


<s> } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg


<s> char push_buf [ <NUM_LIT> ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = - <NUM_LIT> ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) indirect_thunk_needed = true ; indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; snprintf ( push_buf , sizeof ( push_buf ) , <STR_LIT> , TARGET_64BIT ? 'q' : 'l' , xasm ) ; if ( sibcall_p ) { output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { char indirectlabel1 [ <NUM_LIT> ] ; char indirectlabel2 [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( MEM_P ( call_op ) ) { struct ix86_address parts ; rtx addr = XEXP ( call_op , <NUM_LIT> ) ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx ) { if ( parts . index ) { addr = gen_rtx_MULT ( Pmode , parts . index , GEN_INT ( parts . scale ) ) ; addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , addr ) ; } else addr = stack_pointer_rtx ; rtx disp ; if ( parts . disp != NULL_RTX ) disp = plus_constant ( Pmode , parts . disp , UNITS_PER_WORD ) ; else disp = GEN_INT ( UNITS_PER_WORD ) ; addr = gen_rtx_PLUS ( Pmode , addr , disp ) ; call_op = gen_rtx_MEM ( GET_MODE ( call_op ) , addr ) ; } } output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file


<s> static void mips_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn )


<s> default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { assert ( <NUM_LIT> && <STR_LIT>


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleCRC ( ) { OS <<


<s> MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignMask ( EltSizeInBits ) ) , dl , LogicVT ) ; SDValue MagMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignedMaxValue ( EltSizeInBits ) ) , dl , LogicVT ) ; if ( IsFakeVector ) Sign = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign , SignMask ) ; SDValue MagBits ; if ( ConstantFPSDNode * Op0CN = isConstOrConstSplatFP ( Mag ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; APF . clearSign ( ) ; MagBits = DAG . getConstantFP ( APF , dl , LogicVT ) ; } else { if ( IsFakeVector ) Mag = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag ) ; MagBits = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag , MagMask ) ; } SDValue Or = DAG . getNode ( <STR_LIT> , dl , LogicVT ,


<s> if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned EReg = createResultReg ( & <STR_LIT> ) ; unsigned NPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , EReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NPReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( NPReg ) . addReg ( EReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_UNE : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned NEReg = createResultReg ( & <STR_LIT> ) ; unsigned PReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NEReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , PReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( PReg ) . addReg ( NEReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_OGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : SwapArgs = false


<s> bool enableInterleavedAccessVectorization ( ) { return ! ST -> hasSVE


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF


<s> if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) , XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( x != orig_x && legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) ) x = legitimize_tls_address ( x ) ; else if ( flag_pic ) x = legitimize_pic_address ( x , mode , <NUM_LIT> ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x ,


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem


<s> const <ISA_LIT>Subtarget & ST = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * )


<s> * __P = __builtin_ia32_vec_ext_v2df (


<s> if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg

) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ;


<s> assert ( FPO -> Begin && FPO -> End && FPO -> PrologueEnd && <STR_LIT> ) ; MCSymbol * FrameBegin = Ctx . createTempSymbol ( ) , * FrameEnd = Ctx . createTempSymbol ( ) ; OS . emitIntValue ( unsigned ( DebugSubsectionKind :: FrameData ) , <NUM_LIT> ) ; OS . emitAbsoluteSymbolDiff ( FrameEnd , FrameBegin , <NUM_LIT> ) ; OS . emitLabel ( FrameBegin ) ; OS . emitValue ( MCSymbolRefExpr :: create ( FPO -> Function , MCSymbolRefExpr :: VK_COFF_IMGREL32 , Ctx ) , <NUM_LIT> ) ; FPOStateMachine FSM ( FPO ) ; FSM . emitFrameDataRecord ( OS , FPO -> Begin ) ; for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM


<s> case CortexA35 : break ; case CortexA53 : case CortexA55 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR82 : case CortexX1 : case CortexX1C : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA510 : case CortexA710 : case CortexX2 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case NeoverseN2 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case Neoverse512TVB : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor =


<s> unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( ( OffBits >> <NUM_LIT> ) &


<s> } int TaggedFI = - <NUM_LIT> ; if ( OpIndex >= <NUM_LIT> ) { const MachineOperand & MO = MI . getOperand ( OpIndex ) ; if ( MO . isFI ( ) ) { int FI = MO . getIndex ( ) ; if ( FI >= <NUM_LIT> && FI < MFI . getObjectIndexEnd ( ) && FrameObjects [ FI ] . IsValid ) TaggedFI = FI ; } } if ( TaggedFI >= <NUM_LIT> ) GB . AddMember ( TaggedFI ) ; else GB . EndCurrentGroup ( ) ; } GB . EndCurrentGroup ( ) ; } const <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Optional < int > TBPI = AFI . getTaggedBasePointerIndex ( ) ; if ( TBPI ) { FrameObjects [ * TBPI ] . ObjectFirst = true ; FrameObjects [ * TBPI ] . GroupFirst = true ; int FirstGroupIndex = FrameObjects [ * TBPI ] . GroupIndex ; if ( FirstGroupIndex >= <NUM_LIT> ) for ( FrameObject & Object : FrameObjects ) if ( Object . GroupIndex == FirstGroupIndex ) Object . GroupFirst = true ; } llvm :: stable_sort ( FrameObjects , FrameObjectCompare ) ; int i = <NUM_LIT> ; for ( auto & Obj : FrameObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto & Obj : FrameObjects ) { if ( ! Obj .


<s> rtx tempLR , tmp3 , mem ; rtx first , last ; tempLR = gen_reg_rtx ( Pmode ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; tmp3 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; first = emit_insn ( gen_load_toc_v4_PIC_1b ( tempLR , gsym ) ) ; emit_move_insn ( tmp1 , tempLR ) ; emit_move_insn ( tmp2 , mem ) ; emit_insn ( gen_addsi3 ( tmp3 , tmp1 , tmp2 ) ) ; last = emit_move_insn ( got , tmp3 ) ; REG_NOTES ( last ) = gen_rtx_EXPR_LIST ( REG_EQUAL , gsym , REG_NOTES ( last ) ) ; REG_NOTES ( first ) = gen_rtx_INSN_LIST ( REG_LIBCALL , last , REG_NOTES ( first ) ) ; REG_NOTES ( last ) = gen_rtx_INSN_LIST ( REG_RETVAL , first , REG_NOTES ( last ) ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( TARGET_64BIT ) insn = gen_tls_gd_64 ( r3 , got , addr ) ; else insn = gen_tls_gd_32 ( r3 , got , addr ) ; start_sequence ( ) ; emit_insn ( insn ) ; tga = gen_rtx_MEM ( Pmode , rs6000_tls_get_addr ( ) ) ; insn = gen_call_value ( r3 , tga , const0_rtx , const0_rtx ) ; insn = emit_call_insn ( insn ) ; CONST_OR_PURE_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r3 ) ; insn = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insn , dest , r3 , addr ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( TARGET_64BIT ) insn = gen_tls_ld_64 ( r3 , got ) ; else insn = gen_tls_ld_32 ( r3 , got ) ; start_sequence ( ) ; emit_insn ( insn ) ; tga = gen_rtx_MEM ( Pmode , rs6000_tls_get_addr ( ) ) ; insn = gen_call_value ( r3 , tga , const0_rtx , const0_rtx ) ; insn = emit_call_insn ( insn ) ; CONST_OR_PURE_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn


<s> IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA


( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return needsAggressiveScheduling ( DarwinDirective )


<s> APInt VP1 = Value + <NUM_LIT> ; if ( VP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } } else { APInt VNP1 = - Value + <NUM_LIT> ; if ( VNP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , ShiftedVal ) ; } APInt VNM1 = - Value - <NUM_LIT> ; if ( VNM1 .


begin ( ) , * e = ConstantCasts . end ( ) ;


<s> static bool mmix_function_value_regno_p ( const


<s> RegisterTarget < Triple :: sparcv9 , true > Y ( getThe<ISA_LIT>V9Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcel , true > Z ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> ,


<s> bool <ISA_LIT>Subtarget :: isABI_EABI (


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM


<s> case <STR_LIT> : Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler ::


<s> unsigned getValueBit ( int64_t Val , unsigned


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) ,


<s> return ( __m128i ) __builtin_ia32_vcvtps2ph_mask ( ( __v4sf ) __A , __I , (


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & TheTriple ) { if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( ) == Triple :: thumbeb ) ) IsLittleEndian = false ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive =


<s> bool Changed = false ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( * MBB ) ) { if ( isProfitableToTransform ( MI ) ) { transformInstruction ( MI ) ; Changed = true ; } } return


<s> unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false


<s> bool <ISA_LIT>MCAsmInfo :: isAcceptableChar ( char C ) const { if ( AssemblerDialect == AD_ATT ) return MCAsmInfo :: isAcceptableChar (


<s> assert ( Mask . empty ( ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumEltsPerLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; unsigned Offset = Unary ? <NUM_LIT> : NumElts ; unsigned Repetitions = <NUM_LIT> << ( NumStages - <NUM_LIT> ) ; unsigned Increment = <NUM_LIT> << NumStages ; assert ( ( NumEltsPerLane >> NumStages ) > <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( unsigned Stage = <NUM_LIT> ; Stage != Repetitions ; ++ Stage ) { for ( unsigned Elt = <NUM_LIT> ; Elt != NumEltsPerLane ; Elt += Increment ) Mask . push_back (


<s> BlockAddressSDNode * BA = cast < BlockAddressSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget ->


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { bool HasAVX = Subtarget . hasAVX ( ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , false ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , true ) ; case <STR_LIT> : case <STR_LIT> : return ExpandMOVImmSExti8 ( MIB ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * getSymbol


<s> Inst . setLoc ( IDLoc ) ; if ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { const MCExpr * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( MCConstantExpr :: create ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) , getContext ( ) ) , Inst . getLoc ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } else { const MCExpr * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , Inst


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return cfun -> machine -> frame . reg_offset [


<s> addRegOffset ( BuildMI ( testMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( StackPtr ) . addReg ( FinalStackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( testMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; testMBB -> addSuccessor ( testMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; testMBB -> addLiveIn ( FinalStackPtr ) ; tailMBB -> splice ( tailMBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor


<s> static bool rs6000_debug_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { bool ret = rs6000_can_change_mode_class ( from ,


<s> static const SetOfMachineInstr * getUses ( const InstrToInstrs * sets , unsigned


<s> return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; } MBBI = Compare , MBBE = MBB . end ( ) ; while ( ++ MBBI != MBBE ) { MachineInstr & MI = * MBBI ; if ( preservesValueOf ( MI , SrcReg ) ) { if ( convertToLoadAndTest ( MI ) ) { EliminatedComparisons += <NUM_LIT> ; return


<s> if ( known_lt ( poly_size , min_probe_threshold ) || ! flag_stack_clash_protection ) { aarch64_sub_sp ( temp1 , temp2 , poly_size , frame_related_p ) ; return ; } HOST_WIDE_INT size ; if ( ! poly_size . is_constant ( & size ) ) { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; print_dec ( poly_size , dump_file ) ; fprintf ( dump_file , <STR_LIT> ) ; } aarch64_add_offset ( Pmode , temp1 , CONST0_RTX ( Pmode ) , poly_size , temp1 , temp2 , false , true ) ; rtx_insn * insn = get_last_insn ( ) ; if ( frame_related_p ) { rtx stack_ptr_copy = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_move_insn ( stack_ptr_copy , stack_pointer_rtx ) ; emit_insn ( gen_stack_tie ( stack_ptr_copy , stack_pointer_rtx ) ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_ptr_copy ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx probe_const = gen_int_mode ( min_probe_threshold , Pmode ) ; rtx guard_const = gen_int_mode ( guard_size , Pmode ) ; insn = emit_insn ( gen_probe_sve_stack_clash ( Pmode , stack_pointer_rtx , stack_pointer_rtx , temp1 , probe_const , guard_const ) ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , gen_int_mode ( poly_size , Pmode ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } return ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , size ) ; HOST_WIDE_INT rounded_size = ROUND_DOWN ( size , guard_size ) ; HOST_WIDE_INT residual = size - rounded_size ; if ( rounded_size <= STACK_CLASH_MAX_UNROLL_PAGES * guard_size ) { for ( HOST_WIDE_INT i = <NUM_LIT> ; i < rounded_size ; i += guard_size ) { aarch64_sub_sp ( NULL , temp2 , guard_size , true ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , guard_used_by_caller ) ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { aarch64_add_offset ( Pmode , temp1 , stack_pointer_rtx , - rounded_size , temp1 , NULL , false , true ) ; rtx_insn * insn = get_last_insn ( ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , temp1 , rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } insn = emit_insn ( gen_probe_stack_range ( stack_pointer_rtx , stack_pointer_rtx , temp1 ) ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size ) ; } if ( residual ) { HOST_WIDE_INT residual_probe_offset = guard_used_by_caller


<s> if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; Register AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; Register ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC , ! IsSigned ) ) return <NUM_LIT> ; return ResultReg


<s> Value * SourceVal = Y -> getArgOperand ( <NUM_LIT> ) ; if ( I -> getType ( ) != SourceVal -> getType ( ) ) return false ; I -> replaceAllUsesWith ( SourceVal ) ; I -> eraseFromParent ( )


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; } else { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; } MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent (


<s> unsigned <ISA_LIT>ELFObjectWriter :: getEFlags ( ) const { return ELF :: EF_<ISA_LIT>_EABIMASK &


<s> RegisterAsmPrinter < MandarinAsmPrinter > X ( TheMandarinTarget


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; bool IsNaCl = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return


<s> break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && ( N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || N0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> || SExtVT == <STR_LIT> ) { V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , VT ) ; } if ( SExtVT == <STR_LIT> ) { assert ( <NUM_LIT> == DAG . ComputeNumSignBits ( V ) && <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getUNDEF ( <STR_LIT> ) ) ; } else assert ( SExtVT . getScalarType ( ) != <STR_LIT> && <STR_LIT> ) ; if ( FPCastVT != <STR_LIT> ) V = DAG . getBitcast ( FPCastVT , V ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; return DAG . getZExtOrTrunc ( V


<s> inline vector unsigned char vec_vsrab ( vector unsigned char


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty (


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; int Offset = <NUM_LIT> ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int FixedOff = - MFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; MaxAlign = std :: max ( Align


<s> bool isPostIdxReg ( ) const { return isPostIdxRegShifted ( ) && PostIdxReg


<s> if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID


<s> unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout (


<s> static bool shouldSExtOperand ( const Instruction * Inst , int


<s> bool Changed = false ; for ( unsigned EntryIdx = <NUM_LIT> ; EntryIdx < SwapVector . size ( ) ; ++ EntryIdx ) { if ( SwapVector [ EntryIdx ] . WillRemove ) { Changed = true ; MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ EntryIdx ] . VSEId ) ) ; DEBUG ( MI -> dump ( ) ) ; MI -> eraseFromParent ( ) ; } } return


<s> static SDValue combineFP_EXTEND ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasF16C ( ) || Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; bool IsStrict = N -> isStrictFPOpcode ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; Src = DAG . getBitcast (


<s> bool x86_extended_reg_mentioned_p ( rtx insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , INSN_P ( insn ) ? PATTERN ( insn ) : insn , NONCONST ) { const_rtx x = *


<s> return parseRegister ( Operands , RegFP , <STR_LIT> ,


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= ( Rn << <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler


<s> if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } if ( hasMSA ( ) && ! MSAWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r5 ( ) ) { errs ( ) << <STR_LIT> <<


<s> callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_Ghc_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_R


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - TRI -> getEncodingValue ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; HasGPSaveArea = true ; } if ( PFI -> usesPICBase ( ) ) { int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; MinGPR = std :: min < unsigned > ( MinGPR , <STR_LIT> ) ; HasGPSaveArea = true ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { int FI = PFI


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true


<s> if ( targetm . calls . must_pass_in_stack ( arg ) || ( * cum + XSTORMY16_WORD_SIZE ( arg . type

, arg . mode ) > NUM_ARGUMENT_REGISTERS ) ) return NULL_RTX ;


<s> if ( CALL_P ( insn ) ) return <STR_LIT> ; if ( reg_mentioned_p ( gen_rtx_REG ( SImode , LR_REGNUM ) ,


<s> if ( Index ) O << '%' << getRegisterName ( Index ) << ',' ; O << '%' << getRegisterName ( Base ) << ')' ; } else assert ( ! Index &&


<s> static Optional < uint64_t > evaluateMemOpAddrForAddrMode3 ( const MCInst & Inst , const MCInstrDesc & Desc , unsigned MemOpIndex , uint64_t Addr ) { if ( MemOpIndex + <NUM_LIT> >= Desc . getNumOperands ( ) ) return None ; const MCOperand & MO1 = Inst . getOperand ( MemOpIndex ) ; const MCOperand & MO2 = Inst . getOperand ( MemOpIndex + <NUM_LIT> ) ; const MCOperand & MO3 = Inst . getOperand


<s> static DecodeStatus DecodeShiftRight64Imm ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler :: Success


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Large : emitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO32 , MCRegOP , OutContext , STI ) ; break ; } return ; } MCOperand RegGOT = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegPLT = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr ::

VK_<ISA_LIT>_PC_LO32 , GOTLabel , OutContext ) ;


<s> AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) ==

<NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ;


<s> if ( for_return != <NUM_LIT> || GET_MODE_SIZE ( mode ) >= <NUM_LIT> || COMPLEX_MODE_P ( mode ) ||

GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return mode ;


<s> MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg1 ) ) ; TmpInst . addOperand ( Op2 )


<s> return & InstrInfo . getRegisterInfo (


<s> } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getScalarSizeInBits ( ) ; ElementCount SrcEC = SrcVT . getVectorElementCount ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , SrcEC ) ; SDLoc DL ( N )


<s> unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget -> ClassifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB


<s> emit_use ( gen_rtx_REG ( SImode , IP_REGNUM ) ) ; bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( ! callee_saved_reg_p ( regno ) && ( ! IN_RANGE ( regno , FIRST_VFP_REGNUM , LAST_VFP_REGNUM ) || TARGET_HARD_FLOAT ) ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit (


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: CreateMemForInlineAsm ( unsigned SegReg , const MCExpr * Disp , unsigned BaseReg , unsigned IndexReg , unsigned Scale , SMLoc Start , SMLoc End , unsigned Size , StringRef Identifier , InlineAsmIdentifierInfo & Info ) { if ( isa < MCSymbolRefExpr > ( Disp ) ) { if ( ! Info . IsVarDecl ) { unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ( RegNo , Start , End , true , SMLoc ( ) , Identifier , Info . OpDecl ) ; } if ( ! Size ) { Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } } BaseReg = BaseReg ? BaseReg :


<s> bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void emitInlineAsmStart ( const MCSubtargetInfo & StartInfo ) const override ; void emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const override ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg


<s> return ( ( qword ) ( vec_ld ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) (

b ) ) ) ) , ( vector unsigned char * ) ( <NUM_LIT> ) ) ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ; SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , SDTys , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , VLDDup . getValue ( <NUM_LIT> ) ) ; return VLDDup ; } return SDValue (


<s> if ( LHS -> getType ( ) -> getPointerAddressSpace ( ) != <NUM_LIT> || RHS -> getType ( ) -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; if ( ! isa < GlobalObject > ( LHS ) || ! isa < GlobalVariable > ( RHS ) || LHS -> isThreadLocal ( ) || RHS -> isThreadLocal ( ) || RHS -> getName ( ) != <STR_LIT> || ! RHS -> hasExternalLinkage ( ) || cast < GlobalVariable > ( RHS ) -> hasInitializer ( ) || RHS -> hasSection ( ) ) return nullptr ; return MCSymbolRefExpr :: create ( TM . getSymbol ( LHS ) , MCSymbolRefExpr :: VK_COFF_IMGREL32


<s> case TCTX_POINTER_ARITH : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_FIELD : if ( silent_p ) ; else if ( lang_GNU_CXX ( ) ) error_at ( loc , <STR_LIT> , type ) ; else error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_ARRAY_ELEMENT : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_ALLOCATION : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_DEALLOCATION


<s> if ( ! isSysReg ( ) ) return false ; return ( SysReg . PStateField == <STR_LIT> || SysReg . PStateField == <STR_LIT>

|| SysReg . PStateField == <STR_LIT> ) ;


<s> bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? TII . getFrameSize ( * I ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : <NUM_LIT> ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL


<s> CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; if ( ! fun ) return false ; fntype = fun ; if ( ! TYPE_P ( fun ) ) fntype = TREE_TYPE ( fun ) ; if ( ( ! incoming && ! prototype_p ( fntype ) ) || stdarg_p ( fntype ) ) return true ; INIT_CUMULATIVE_INCOMING_ARGS ( args_so_far_v , fntype , NULL_RTX ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; if ( incoming ) { gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) { tree parm


<s> if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; if ( EmbeddedData && GVA -> isConstant ( ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ; return IsInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) .


<s> static SDValue combineExtSetcc ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return


<s> if ( Memory . BaseRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory


<s> assert ( ( ( ! Subtarget . hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant (


<s> SDValue <ISA_LIT>TargetLowering :: cFromDDC ( SelectionDAG & DAG , const SDLoc DL , SDValue Offset ) const { auto GetDDC = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; auto DDC = DAG . getNode ( <STR_LIT> ,


<s> void setEmitNOAT ( ) { EmitNOAT = true


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const TargetInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , UC ( Parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer


<s> return createMachOStreamer ( Ctx , std :: move ( MAB ) , OS

, std :: move ( Emitter ) , false , DWARFMustBeAtTheEnd ) ;


<s> op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg ( Pmode , op1 ) ; if ( REG_POINTER ( op1 ) ) std :: swap ( op0 , op1 ) ; if ( virt_or_elim_regno_p ( REGNO ( op0 ) ) ) { base = expand_binop ( Pmode , add_optab , op0 , offset_rtx , NULL_RTX , true , OPTAB_DIRECT ) ; return gen_rtx_PLUS ( Pmode , base , op1 ) ; } base = expand_binop ( Pmode , add_optab , op0 , op1 , NULL_RTX , true , OPTAB_DIRECT ) ; x = gen_rtx_PLUS ( Pmode , base , offset_rtx ) ; } HOST_WIDE_INT size ; if ( GET_MODE_SIZE ( mode ) . is_constant ( & size ) ) { HOST_WIDE_INT base_offset = aarch64_anchor_offset ( offset , size , mode ) ; if ( base_offset !=


<s> if ( CmpMask != ~ <NUM_LIT> ) { if ( ! isSuitableForMask ( MI , SrcReg , CmpMask , false ) ) { MI = <NUM_LIT> ; for ( MachineRegisterInfo :: use_iterator UI = MRI -> use_begin ( SrcReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getParent ( ) != CmpInstr -> getParent ( ) ) continue ; MachineInstr * PotentialAND = & * UI ; if ( ! isSuitableForMask ( PotentialAND , SrcReg , CmpMask , true ) ) continue ; MI = PotentialAND ; break ; } if ( ! MI ) return false ; } } if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI .


<s> const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . has<ISA_LIT>64 ( ) ) return Subtarget . has<ISA_LIT>64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . has<ISA_LIT>32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat (

) ) return CSR_SingleFloatOnly_SaveList ;


<s> const char * fmt ; int i ; if ( SYMBOL_REF_P ( x ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return <NUM_LIT> ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j --

) if ( symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ) ; FalseMBB -> insert ( FalseInsertionPoint , NewMI ) ; for ( auto & MOp : NewMI -> uses ( ) ) { if ( ! MOp . isReg ( ) ) continue ; auto It = FalseBBRegRewriteTable . find ( MOp . getReg ( ) ) ; if ( It == FalseBBRegRewriteTable . end ( ) ) continue ; MOp . setReg ( It -> second ) ; MOp . setIsKill ( false ) ; } } MBB -> erase ( MachineBasicBlock :: iterator ( MI ) , std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; FalseBBRegRewriteTable [ NewCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ] = TmpReg ; } DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> ( * MIIt ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; auto Op1Itr = RegRewriteTable . find ( Op1Reg ) ; if ( Op1Itr != RegRewriteTable . end ( ) ) Op1Reg = Op1Itr -> second . first ; auto Op2Itr = RegRewriteTable . find ( Op2Reg ) ; if ( Op2Itr != RegRewriteTable . end ( ) ) Op2Reg = Op2Itr -> second . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( FalseMBB ) . addReg ( Op2Reg ) . addMBB ( MBB ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIIt -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIB -> dump ( ) ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } MBB -> erase ( MIItBegin , MIItEnd ) ; if ( MachineLoop * L = MLI -> getLoopFor ( MBB ) ) { L -> addBasicBlockToLoop ( FalseMBB , MLI -> getBase ( ) ) ; L -> addBasicBlockToLoop ( SinkMBB , MLI -> getBase ( )


<s> static DecodeStatus DecodeMemMMImm12 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler ::


<s> unsigned NumNOPBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordStackMap ( * MILabel , MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII


<s> return ( __m64 ) __builtin_ia32_psadbw ( ( __v8qi )


<s> scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; emit_insn ( ix86_gen_one_cmpl2 ( scratch2 , scratch1 ) ) ; emit_insn ( ix86_gen_add3 ( out , scratch2 , constm1_rtx ) ) ; } return true


<s> void addRegG8RCNoX0Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> int body = ( code & <NUM_LIT> ) != <NUM_LIT> ; unw_word rlen ; rlen = ( code


<s> return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : { unsigned Imm = ( OpNum - OP_VEXT1 + <NUM_LIT> ) * getExtFactor ( OpLHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } case OP_VUZPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VUZPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VTRNL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case


<s> return ( __m128h ) __builtin_ia32_movaps128_mask ( ( __v4sf ) _mm_conj_pch ( __A ) , (


<s> unsigned <ISA_LIT>ELFObjectWriter :: getEFlags ( ) const { return ELF :: EF_MIPS_NOREORDER | ELF


<s> int r , m ; for ( r = <NUM_LIT> ; r < FIRST_PSEUDO_REGISTER ; ++ r ) for ( m = <NUM_LIT> ; m < NUM_MACHINE_MODES ; ++ m ) if ( rs6000_hard_regno_mode_ok ( r

, m ) ) rs6000_hard_regno_mode_ok_p [ m ] [ r ] = true ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS (


<s> if ( Imm & <NUM_LIT> ) return int8_t ( Imm ) == T ( Imm ) ; if ( Imm & <NUM_LIT> ) return int16_t ( Imm ) == T ( Imm ) ; return Imm == <NUM_LIT>


<s> const int mult = ( named ? <NUM_LIT> : <NUM_LIT> ) ; unsigned int nwords ; if ( slotno == ( named ? SPARC_FP_ARG_MAX : SPARC_INT_ARG_MAX ) - <NUM_LIT> ) nwords = <NUM_LIT> ; else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nwords ) ) ; if ( size < UNITS_PER_WORD ) XVECEXP ( regs , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( unsigned int i = <NUM_LIT> ; i < nwords ; i ++ ) XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno + i * mult ) , GEN_INT ( i * UNITS_PER_WORD ) ) ; return


<s> return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; default : return <NUM_LIT>


<s> m_pRelocator = new <ISA_LIT>Relocator ( * this , config ( ) ) ; } return true


<s> } case <STR_LIT> : { if ( IsRHSNegOne ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GEZExt ) ; if ( IsRHSZero ) { if ( CmpInGPR == ICGPR_NonExtIn ) return SDValue ( ) ; LHS = signExtendInputIfNeeded ( LHS ) ; RHS = signExtendInputIfNeeded ( RHS ) ; SDValue Neg = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Neg , S -> getI32Imm ( <NUM_LIT> , dl ) , S -> getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } std :: swap ( LHS , RHS ) ; ConstantSDNode * RHSConst = dyn_cast < ConstantSDNode > ( RHS ) ; IsRHSZero = RHSConst && RHSConst -> isNullValue ( ) ; IsRHSOne = RHSConst && RHSConst -> getSExtValue ( ) == <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { if ( IsRHSOne ) { if ( CmpInGPR == ICGPR_NonExtIn ) return SDValue ( ) ; return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: LEZExt ) ; } if ( IsRHSZero ) { SDValue ShiftOps [ ] = { LHS , S -> getI32Imm ( <NUM_LIT> , dl ) , S -> getI32Imm ( <NUM_LIT> , dl ) , S -> getI32Imm ( <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; } if ( CmpInGPR == ICGPR_NonExtIn ) return SDValue ( ) ; LHS = signExtendInputIfNeeded ( LHS ) ; RHS = signExtendInputIfNeeded ( RHS ) ; SDValue SUBFNode = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , RHS , LHS ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SUBFNode , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( CmpInGPR == ICGPR_NonExtIn ) return SDValue ( ) ; LHS = zeroExtendInputIfNeeded ( LHS ) ; RHS = zeroExtendInputIfNeeded ( RHS


<s> if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true ,


<s> static bool isVShiftLImm ( SDValue Op , EVT VT , int64_t & Cnt ) { assert ( VT . isVector ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>MCCodeGenInfo (


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return


<s> AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> ,


<s> void aarch64_init_simd_builtins ( void ) { if ( aarch64_simd_builtins_initialized_p ) return ; aarch64_simd_builtins_initialized_p = true ; aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( )


<s> return ( __m256i ) __builtin_ia32_cvttpd2udq512_mask ( ( __v8df ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8


<s> if ( TgtBB != ML . getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML . getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML . getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( isWhileLoopStart ( * Start ) ) { MachineBasicBlock * TargetBB = getWhileLoopStartTargetBB ( * Start ) ; if ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( TargetBB ) || ! BBUtils -> isBBInRange ( Start , TargetBB , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } return true ; } ; StartInsertPt = MachineBasicBlock :: iterator ( Start ) ; StartInsertBB = Start -> getParent (


<s> auto * Mgs = cast < <ISA_LIT>MaskedGatherScatterSDNode > ( Parent ) ; AM . IndexReg = Mgs -> getIndex ( ) ; AM . Scale = cast < ConstantSDNode > ( Mgs -> getScale ( ) ) -> getZExtValue ( ) ; unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( N


<s> void scalar_chain :: convert_reg ( rtx_insn * insn , rtx dst , rtx src ) { start_sequence ( ) ; if ( ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) { rtx tmp = assign_386_stack_local ( smode , SLOT_STV_TEMP ) ; emit_move_insn ( tmp , src ) ; if ( ! TARGET_64BIT && smode == DImode ) { emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } else emit_move_insn ( dst , copy_rtx ( tmp ) ) ; } else if ( ! TARGET_64BIT && smode == DImode ) { if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx


<s> insn = next_active_insn ( insn ) ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX ) break ; if ( get_attr_length ( insn ) == <NUM_LIT> && jump_insn == next_active_insn ( insn ) )


<s> if ( flag_verbose_asm || flag_debug_asm ) pru_dump_frame_layout (


<s> neg = <NUM_LIT> ; } if ( b < <NUM_LIT> ) b = - b ; res = udivmodsi4 ( a , b , <NUM_LIT> ) ; if ( neg ) res


<s> if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return N -> getOperand ( <NUM_LIT> ) ; return N


<s> return ( __m128d ) __builtin_ia32_vfmaddpd ( - ( __v2df ) __A , (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT


<s> } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; SmallVector < unsigned , <NUM_LIT> > ImpDefs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( MIOperands MO ( memOps [ i ] . MBBI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) || ! MO -> isImplicit ( ) || MO -> isDead ( ) ) continue ; unsigned DefReg = MO -> getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; } } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs , ImpDefs ) ) return ; Merges . push_back ( prior


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; } unsigned ResultReg = fastEmitInst_rri ( Opc , RC , LHSReg , LHSIsKill , RHSReg , RHSIsKill , <STR_LIT> ( <STR_LIT> , ShiftImm ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , true , Mask ) ; } return ResultReg


<s> unsigned getNumFixupKinds ( ) const override { return