<s> unsigned CalleeSavedFrameSize = <NUM_LIT> ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment


<s> mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , <NUM_LIT> ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , permute_reg


<s> return __builtin_ia32_cvttsd2si ( ( __v2df )


<s> if ( Subtarget . isDarwin ( ) ) return <NUM_LIT> ; unsigned Align = Subtarget . is<ISA_LIT>64 ( ) ? <NUM_LIT>


<s> std :: string <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSWindows ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; } return <ISA_LIT>ArchFeature


<s> return ( __m128 ) __builtin_ia32_minss ( ( __v4sf )


<s> bool i386_pe_type_dllexport_p ( tree ) { return


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( searchSymbolAlias ( Operands , <STR_LIT>


<s> void addImm0_4095NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> if ( get<ISA_LIT>Subtarget ( ) . hasNEON ( ) ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . hasV8Ops ( ) && ! get<ISA_LIT>Subtarget (

) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ;


<s> return __builtin_mve_vclsq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> if ( ! Uses . count ( MO . getReg ( ) ) ) continue ; MO . setIsKill (


<s> EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue (


<s> rtx_insn * insn , * next_insn ; int issue_rate ; int can_issue_more ; int slot , i ; bool group_end ; int group_count = <NUM_LIT> ; rtx * group_insns ; issue_rate = rs6000_issue_rate ( ) ; group_insns = XALLOCAVEC ( rtx , issue_rate ) ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } can_issue_more = issue_rate ; slot = <NUM_LIT> ; insn = get_next_active_insn ( prev_head_insn , tail ) ; group_end = false ; while ( insn != NULL_RTX ) { slot = ( issue_rate - can_issue_more


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V


<s> static void segv_crash_handler ( int sig ATTRIBUTE_UNUSED ) { internal_error (


<s> unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; assert ( EntrySize == <NUM_LIT> ) ; assert ( isPowerOf2_64 ( EntrySize ) ) ; auto PtrInfo = MachinePointerInfo :: getCapTable ( DAG . getMachineFunction ( ) ) ; SDValue Jumptable = getDataFromCapTable ( cast < JumpTableSDNode > ( Table . getNode ( ) ) , dl , PTy , DAG , Chain , PtrInfo ) ; Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( Log2_32 ( EntrySize ) , dl , <STR_LIT> ) ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; auto LoadAddr = DAG . getPointerAdd ( dl , Jumptable , Index ) ; SDValue JTEntryValue = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadAddr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT ) ; Chain = JTEntryValue . getValue ( <NUM_LIT> ) ; assert ( isJumpTableRelative (


<s> if ( MI . getOpcode ( ) != TargetOpcode :: LOAD_STACK_GUARD ) return false ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel


<s> std :: string MASSEntryStr = MASSEntry . str ( ) ; if ( isFiniteCallSafe ( CI ) ) MASSEntryStr += <STR_LIT> ; FunctionCallee FCache = M -> getOrInsertFunction ( MASSEntryStr , Func . getFunctionType ( ) , Func . getAttributes ( ) ) ; CI . setCalledFunction ( FCache ) ; return true


<s> static void adjustICmpTruncate ( SelectionDAG & DAG , const SDLoc & DL , Comparison & C ) { if ( C . Op0 . getOpcode ( ) == <STR_LIT> && C . Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { auto * L = cast < LoadSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( L -> getMemoryVT ( ) . getStoreSizeInBits ( ) <= C . Op0 . getValueSizeInBits ( ) ) { unsigned Type = L -> getExtensionType ( ) ; if ( ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) || ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) ) { C . Op0 = C . Op0 . getOperand ( <NUM_LIT> ) ; C . Op1 = DAG . getConstant ( <NUM_LIT> , DL , C


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src ,

SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


<s> if ( OrShadowOffset ) { OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ShadowBase ) , STI ) ; auto OpCode = AccessInfo . AccessSizeIndex == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; OutStreamer -> emitInstruction ( MCInstBuilder ( OpCode ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; } else { auto OpCode = AccessInfo . AccessSizeIndex == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; OutStreamer -> emitInstruction ( MCInstBuilder ( OpCode ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ShadowBase ) .


<s> Inst . addOperand ( MCOperand :: createReg ( getGPRMM16Reg (


<s> PM . add ( create<ISA_LIT>ExpandPseudoPass ( *


<s> static unsigned getFixupKindNumBytes ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : case FK_SecRel_2 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> Register AmtReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto * CstMI = MRI . getVRegDef ( AmtReg ) ; assert ( CstMI && <STR_LIT> ) ; if ( CstMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) return true ; unsigned Amount = CstMI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; assert ( MRI . getType ( AmtReg ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ExtCst = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , AmtReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg ( <NUM_LIT> ) ) ; return


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT>


<s> return ! name . startswith ( <STR_LIT> ) && ! name . startswith ( <STR_LIT> ) && GNULDBackend

:: mayHaveUnsafeFunctionPointerAccess ( pSection ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED , rtx pic_reg ) { rtx l1 , labelno , pic_tmp , pic_rtx ; if ( crtl -> uses_pic_offset_table == <NUM_LIT> || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1


<s> else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , Value , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; else if ( VA . getLocInfo ( ) == CCValAssign ::


<s> static DecodeStatus DecodeMVE_MEM_3_pre ( MCInst & Inst , unsigned Val , uint64_t Address


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitADD ( Register DefReg , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ; auto ImmFns = selectArithImmed ( RHS ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; auto AddMI = MIRBuilder . buildInstr ( Opc ,


<s> return ( __m64 ) __builtin_arm_wsadhz ( ( __v4hi ) __A ,


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return known_eq ( cfun -> machine ->


<s> static MCSymbolRefExpr :: VariantKind getModifierVariantKind ( <STR_LIT> Modifier ) { switch ( Modifier ) { case <STR_LIT> : case <STR_LIT> : return MCSymbolRefExpr :: VK_None ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ; case <STR_LIT> : return MCSymbolRefExpr :: VK_SECREL ; case <STR_LIT>


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; } AssemblerDialect =


<s> return :: isPSHUFDMask ( N -> getMask ( ) , N -> getValueType


<s> auto * Store = cast < MaskedStoreSDNode > ( Op ) ; SDLoc DL ( Op ) ; EVT VT = Store -> getValue ( ) . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; auto NewValue = convertToScalableVector ( DAG , ContainerVT , Store -> getValue ( ) ) ; SDValue Mask = convertFixedMaskToScalableVector ( Store -> getMask ( )


<s> assert ( Reg < <STR_LIT> && <STR_LIT> ) ; unsigned GPRs = GPRMap [ Reg ] ; assert ( GPRs != <NUM_LIT> && <STR_LIT> ) ; if ( GPRs & LiveOther ) return false ; uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <STR_LIT> ( Imm ) ) { MI . setDesc ( TII -> get ( LLIxL ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ( Reg ) ) ; return true


<s> case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Value = Value . getValue ( <NUM_LIT> ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS


<s> store_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode : store_string = <STR_LIT> ; break ; case E_DImode : case E_DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else fatal_insn ( <STR_LIT> , reg ) ; if ( ! MEM_P ( mem ) ) fatal_insn ( <STR_LIT> , mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; fusion_split_address ( addr , & hi , & lo ) ; emit_fusion_addis ( tmp_reg , hi ) ; emit_fusion_load_store ( reg , tmp_reg , lo , store_string ) ; return


<s> CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath && LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 ) ; } return Result


<s> return ( __m256i ) __builtin_ia32_cvttpd2qq256_mask ( ( __v4df ) __A , ( __v4di ) _mm256_setzero_si256 ( ) ,


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return true


<s> for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isCmseEntry && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; } Regs . clear ( ) ; if ( MI != MBB . end ( ) )


<s> unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec , VecIdx


<s> if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if (


<s> static DecodeStatus decodeBDAddr64Disp20Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const void * Decoder ) { return decodeBDAddr20Operand ( Inst , Field , <STR_LIT>


<s> int <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Imm . getActiveBits ( ) >= <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( Bits == <NUM_LIT> || ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ~ SImmVal < <NUM_LIT> ) || <STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( MachineRegisterInfo :: reg_iterator ri = MRI . reg_begin ( <STR_LIT> ) , re = MRI . reg_end ( ) ; ri != re ; ++ ri ) if ( ri -> isCopy ( ) ) return true ; return false


<s> return ( unsigned char ) __builtin_ia32_ktestzqi ( __A , __B


<s> __vector unsigned long long __a = ( __vector unsigned long


<s> int BaseState = ParentBaseState ; auto & BBColors = BlockColors [ BB ] ; assert ( BBColors . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( auto * FuncletPad = dyn_cast < FuncletPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) { auto BaseStateI = FuncInfo . FuncletBaseStateMap . find ( FuncletPad ) ; if ( BaseStateI != FuncInfo . FuncletBaseStateMap . end ( ) ) BaseState = BaseStateI -> second ; } return BaseState


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; unsigned Imm = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Imm , <NUM_LIT> * Rot ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; else MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT>


<s> __inline__ static unsigned short sh_media_unaligned_LD_UW ( void * p ) { unsigned char * addr = p ; return sh_media_MSHFLO_B ( addr [ <NUM_LIT> ] , addr [ <NUM_LIT>


<s> long int <ISA_LIT>ELFWriterInfo :: computeRelocation ( unsigned SymOffset , unsigned RelOffset , unsigned RelTy ) const { if ( RelTy == ELF :: R_MIPS_GOT16 ) return SymOffset - ( RelOffset + <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT>


<s> if ( exc -> exception_cleanup ) ( * exc -> exception_cleanup ) ( _URC_FOREIGN_EXCEPTION_CAUGHT


<s> RegisterAsmParser < <ISA_LIT>ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterAsmParser < <ISA_LIT>ATTAsmParser > Y ( The<ISA_LIT>_64Target ) ; LLVMInitialize<ISA_LIT>AsmLexer (


<s> Map [ GR64Regs [ I ] ] = I ; Map [ GR128Regs [ I ] ] = I ; Map [ FP128Regs [ I ] ] = I ; } for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { Map [ VR32Regs [ I ] ] = I ; Map [ VR64Regs [ I ] ] = I ; Map [ VR128Regs [ I


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base


<s> return decodeBDXAddr20Operand ( Inst , Field ,


<s> unsigned Reg = F128RegDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable (


<s> return ( __m128i ) __builtin_ia32_pmovdb128_mask ( ( __v4si ) __A , (


<s> const RegisterBankInfo :: InstructionMapping & <ISA_LIT>RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_UMULH : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : case G_FSUB : case G_FMUL : case G_FDIV : case G_FABS : case G_FSQRT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_FCMP : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , FPRValueMapping , FPRValueMapping } ) ; break ; } case G_FPEXT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_FPTRUNC : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } SDNode * St ; if ( Subtarget -> hasPAuth ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else { SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ; St = DAG . getMachineNode ( <STR_LIT> ,


<s> bool <ISA_LIT>InstPrinter :: isV9 ( const MCSubtargetInfo & STI


<s> static void EmitRegTruncate ( const llvm :: MCSubtargetInfo & STI


<s> if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; return


<s> AssemblerOptions . back ( ) -> setMacro ( ) ; Parser . Lex ( ) ; return false


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: CreateMemForInlineAsm ( unsigned SegReg , const MCExpr * Disp , unsigned BaseReg , unsigned IndexReg , unsigned Scale , SMLoc Start , SMLoc End , unsigned Size , StringRef Identifier , InlineAsmIdentifierInfo & Info ) { if ( isa < MCSymbolRefExpr > ( Disp ) && Info . OpDecl && ! Info . IsVarDecl ) { if ( ! Size ) { Size = getPointerWidth ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start ,


<s> return COFF :: IMAGE_REL_AMD64_ADDR32 ; } FixupKind = FK_PCRel_4 ; } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_I386_DIR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_I386_DIR32 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_I386_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_I386_SECREL


<s> return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . eatToEndOfStatement


<s> DFtype dh , dl ; dh = ( SItype ) ( u >> ( sizeof ( SItype ) * <NUM_LIT> ) ) ; dh *= <NUM_LIT> * ( ( ( UDItype ) <NUM_LIT> ) << ( ( sizeof ( SItype ) * <NUM_LIT>


<s> static DecodeStatus DecodeMveVCTP ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler


<s> return ( __m128d ) __builtin_ia32_cvtdq2pd128_mask ( ( __v4si ) __A , (

__v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ,


<s> void <ISA_LIT>InstPrinter :: printExtendedRegister ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )


<s> unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check


<s> rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , <NUM_LIT> ) , op1 ) ) { return


<s> const TargetRegisterClass * RC = getRegClass ( MCID , Index , & RI , MF ) ; unsigned NumDefs = MCID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; SDLoc dl ( N ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * TRI . legalclasstypes_begin ( * RC ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first


<s> case InlineAsm :: Constraint_X : case InlineAsm :: Constraint_p : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back (


<s> const FeatureBitset & FeatureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> && ! FeatureBits [ <STR_LIT> ] ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) )


<s> if ( NumElts == <NUM_LIT> ) return true ; if ( NumElts == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) ) || isSHUFPMask

( Mask , VT , Subtarget -> hasAVX ( ) , true ) ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID ,


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << LowercaseString ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand


<s> unsigned char OpFlags = Subtarget . classifyGlobalReference ( GV ) ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl ,


<s> setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB


<s> MCSymbol * <ISA_LIT>FunctionInfo :: getTOCOffsetSymbol ( ) const { const DataLayout & DL = MF . getDataLayout ( ) ; return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( MF . getFunctionNumber (


<s> ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs (


<s> if ( BV -> isConstantSplat ( APVal , APUndef , BitSize , HasAnyUndefs , <NUM_LIT> , true ) ) if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return CFP -> getValueAPF ( ) . isNegZero ( ) ; return


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Word0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( LoIdx , <STR_LIT> ) ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue And0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue And1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Word1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , And0 , And1 ) ; if ( ! isLittle ) std :: swap ( Word0 , Word1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Word0


<s> else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= <NUM_LIT> && align < BITS_PER_WORD ) return BITS_PER_WORD ; return


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseMulImm4 ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! TokE . getString ( ) . equals_lower ( <STR_LIT> ) || Parser . getLexer ( ) . peekTok ( ) . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail


<s> if ( LastOpc == UncondBrOpc ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( LastOpc != UncondBrOpc ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_CondUncond


<s> MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator E = MI . getParent ( ) -> end ( ) ; if ( ! TII -> isCandidateToMergeOrPair ( MI ) ) return false ; if ( isPromotableZeroStoreOpcode ( MI ) && getLdStRegOp ( MI ) . getReg ( ) != <STR_LIT> )


<s> if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size && align < BITS_PER_WORD )


<s> if ( SDValue Res = combineVectorCompareAndMaskUnaryOp ( N , DAG ) ) return Res ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; if ( InVT . isVector ( ) && InVT . getScalarSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = <STR_LIT> ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; if ( DCI . isBeforeLegalize ( ) || TruncVT != <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } assert ( InVT == <STR_LIT> && <STR_LIT> ) ; SDValue Cast = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Cast , Cast , { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Shuf ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Subtarget . hasX87 ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT


<s> if ( CALL_P ( complete_insn ) ) return TYPE_BRANCH ; if ( GET_CODE ( insn ) != SET ) return TYPE_ARITH ; if ( SET_DEST ( insn ) == pc_rtx ) return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasE2 ( ) ) return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; else return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT>


<s> if ( count == <NUM_LIT> || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { insn = mode == DImode ? gen_addsi3 : gen_adddi3 ; while ( count -- > <NUM_LIT> ) emit_insn ( insn ( operand , operand , operand ) ) ; } else { insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; emit_insn ( insn ( operand , operand ,


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ; const TargetMachine & TM = getTargetMachine ( ) ; if ( ! TM . Options . UseSoftFloat && Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case <NUM_LIT> :


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F ) { return


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { if ( Subtarget . allowMixed16_32 ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; PM . add ( createNoTargetTransformInfoPass ( ) ) ; } else LLVMTargetMachine :: addAnalysisPasses ( PM


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT


<s> virtual const MandarinTargetLowering * getTargetLowering ( ) const { return &


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue

Size , unsigned , bool , bool , MachinePointerInfo , MachinePointerInfo ) const {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << TargetMBB . getNumber ( ) << <STR_LIT> ) ; for ( auto & Use : MI . uses ( ) ) { if ( Use . isReg ( ) && Register :: isVirtualRegister ( Use . getReg ( ) ) ) { MachineInstr * DefInst = MRI -> getVRegDef ( Use . getReg ( ) ) ; if ( DefInst -> isPHI ( ) && DefInst -> getParent ( ) == MI . getParent ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } LLVM_DEBUG ( dbgs ( )


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( ! TM ) return true ; TLSModel :: Model Model = TM -> getTLSModel ( GV ) ; return Model == TLSModel :: GeneralDynamic


<s> Args . push_back ( getContext ( ) . GetOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT> == NbArgs ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ; Lex ( ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ; getStreamer ( ) . EmitLOHDirective ( ( MCLOHType ) Kind , Args ) ; return false


<s> return __builtin_mve_vcvtmq_m_sv4si ( __arm_vuninitializedq_s32 ( )


<s> if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg )


<s> void emitARM64WinCFISaveFPLRX ( int Offset ) override { OS << <STR_LIT> << Offset <<


<s> case <STR_LIT> : return STI -> isTargetDarwin ( ) ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ; case <STR_LIT> : case <STR_LIT> : return hasBasePointer ( MF


<s> case 'r' : case 'f' : case 'q' : case 'v' : if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ; return RegName +


<s> case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return


<s> assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( ( ! Subtarget . hasDQI ( ) && ( VecVT . getVectorNumElements ( ) == <NUM_LIT> ) ) || ( VecVT . getVectorNumElements ( ) < <NUM_LIT> ) ) { VecVT = <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , DAG . getUNDEF ( VecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } unsigned MaxSift = VecVT . getVectorNumElements ( )


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins


<s> if ( RegNo == <NUM_LIT> || RegNo == <NUM_LIT> )


<s> case EQ : branch = <STR_LIT> ; break ; case GE : branch = <STR_LIT> ; break ; case GT : branch = <STR_LIT> ; break ; case LE : branch = <STR_LIT> ; break ; case LT : branch = <STR_LIT> ; break ; case UNORDERED : branch = <STR_LIT> ; break ; case ORDERED : branch = <STR_LIT> ; break ; case UNGT : branch = <STR_LIT> ; break ; case UNLT : branch = <STR_LIT> ; break ; case UNEQ : branch = <STR_LIT> ; break ; case UNGE : branch = <STR_LIT> ; break ; case UNLE : branch = <STR_LIT> ; break ; case LTGT : branch = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } string [ <NUM_LIT> ] = '\0' ; if ( ! TARGET_V9 ) strcpy ( string , <STR_LIT> ) ; strcat ( string , branch ) ; } else { switch ( code ) { case NE : branch = <STR_LIT> ; break ; case EQ : branch = <STR_LIT> ; break ; case GE : if ( mode == CC_NOOVmode || mode == CCX_NOOVmode ) branch = <STR_LIT> ; else branch = <STR_LIT> ; break ; case GT : branch = <STR_LIT> ; break ; case LE : branch = <STR_LIT> ; break ; case LT : if ( mode == CC_NOOVmode || mode == CCX_NOOVmode ) branch = <STR_LIT> ; else branch = <STR_LIT> ; break ; case GEU : branch = <STR_LIT> ; break ; case GTU : branch = <STR_LIT> ; break ; case LEU : branch = <STR_LIT> ; break ; case LTU : branch = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } strcpy ( string , branch ) ; } spaces -= strlen ( branch ) ; p = strchr ( string , '\0' ) ; if ( annul && ! far ) { strcpy ( p , <STR_LIT> ) ; p += <NUM_LIT> ; spaces -= <NUM_LIT> ; } if ( TARGET_V9 ) { rtx note ; int v8 = <NUM_LIT> ; if ( ! far && insn && INSN_ADDRESSES_SET_P ( ) ) { int delta = ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( delta < - <NUM_LIT> || delta >= <NUM_LIT> ) v8 = <NUM_LIT> ; } if ( mode == CCFPmode || mode == CCFPEmode ) { static char v9_fcc_labelno [ ] = <STR_LIT> ; v9_fcc_labelno [ <NUM_LIT> ] = REGNO ( cc_reg ) - SPARC_FIRST_V9_FCC_REG + '0' ; labelno = v9_fcc_labelno ; if ( v8 ) { gcc_assert ( REGNO ( cc_reg


<s> return static_cast < const <ISA_LIT>TargetMachine & > ( TM


<s> static void insertDAGNode ( SelectionDAG * DAG , SDNode * Pos , SDValue N ) { if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId ( ) >


<s> B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder ( Entry ) ; Builder . CreateRetVoid


<s> Observer . changingInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( WideReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( WideZero . getReg ( <NUM_LIT> ) ) ; Observer . changedInstr ( MI )


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = FUNCTION_ARG_SIZE ( mode , type ) ; cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & <NUM_LIT>

) && type != NULL_TREE && arg_size > <NUM_LIT> ) ) ;


<s> return ( poly16x4_t ) __builtin_neon_vget_highv8hi ( (


<s> SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_really_used_regs [ i ] , call_really_used_regs [ i + <NUM_LIT> ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i


<s> bool ParseDirective ( AsmToken DirectiveID ) override { return


<s> Register ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc =


<s> static Constant * SegmentOffset ( IRBuilderBase & IRB , int Offset , unsigned AddressSpace ) { return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( )


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI .


<s> static DecodeStatus DecodeT2AddrModeImm8s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val ,


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & ,


<s> if ( isImm ( ) ) { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Val )


<s> <ISA_LIT>PreLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true ,

false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) {


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = TM . getSubtargetImpl ( )


<s> unsigned mmix_local_alignment ( tree type ATTRIBUTE_UNUSED , unsigned basic_align


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false


<s> Value * <ISA_LIT>IREmitter :: visitMOVDQ2Q ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> int end ; if ( i <= <NUM_LIT> ) i += <NUM_LIT> ; if ( remainder & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) { end = i - <NUM_LIT> ; if ( end < <NUM_LIT> ) end += <NUM_LIT> ; temp1 = remainder & ( ( <NUM_LIT> << end ) | ( ( i < end ) ? ( <NUM_LIT> >> ( <NUM_LIT> - end ) ) : <NUM_LIT> ) ) ; remainder &=


<s> extern __inline __m512i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_maskz_loadu_epi64 ( __mmask8 __U , void const * __P ) { return ( __m512i ) __builtin_ia32_loaddqudi512_mask ( ( const long long * ) __P , ( __v8di ) _mm512_setzero_si512 ( ) ,


<s> static DecodeStatus DecodeVecShiftR16ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const


<s> const TargetOptions & Options = getTargetMachine ( ) . Options ; EVT VT = getValueType ( User -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( <STR_LIT> , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) return false ; return


<s> } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( ) ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT>


<s> std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , false ) ) { DOUT << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return DecrementOldEntry ( CPI , CPEMI ) ? <NUM_LIT>


<s> unsigned getVarArgsFrameIndex ( ) const { return


<s> SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT>


<s> static bool aarch64_validate_mcpu ( const char * str , const struct processor * * res , unsigned long * isa_flags ) { enum aarch64_parse_opt_result parse_res = aarch64_parse_cpu ( str , res , isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) return true ; switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> ,


<s> void EmitPersonalityIndex ( unsigned PI ) { assert ( PI < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ; EmitByte ( <STR_LIT> :: EHT_COMPACT


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo


<s> bool isParenExpr = false ; <ISA_LIT>AsmParser :: OperandMatchResultTy Res = MatchOperand_NoMatch ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT>


<s> ExtraOpc = <STR_LIT> ; HiOpc = <STR_LIT> ; return <STR_LIT> ; } llvm_unreachable (


<s> aarch64_layout_frame ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) { if ( from == ARG_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - crtl -> outgoing_args_size ; if ( from == FRAME_POINTER_REGNUM ) return ( cfun -> machine ->

frame . hard_fp_offset - cfun -> machine -> frame . saved_varargs_size ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v )


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ; advanceTo ( MBB ->


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI , OpNum , O


<s> if ( fi >= Size ) { Size *= <NUM_LIT> ; if ( fi >= Size ) Size = fi + <NUM_LIT> ; GPRCS2Frames . resize ( Size ) ; } GPRCS2Frames [ fi


<s> if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) return Error ( SRegLoc , <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; auto pair = std :: make_pair ( RegisterKind , ( unsigned ) RegNum ) ; if ( RegisterReqs . insert ( std :: make_pair ( Name , pair ) ) . first -> second != pair ) Warning ( L , <STR_LIT> + Name + <STR_LIT> ) ; return


<s> unsigned addr = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( ! Check ( S , RnDecoder ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , AddrDecoder ( Inst , addr


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op


<s> EVT PtrVT = Src . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( Loop , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , DL , PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ; return DAG . getNode ( Sequence , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , DL


<s> else if ( Reg . Group == RegAR ) RegNo = <STR_LIT> [ Reg . Num ] ; else if ( Reg . Group == RegCR ) RegNo = <STR_LIT> [ Reg . Num ] ; StartLoc = Reg . StartLoc ; EndLoc = Reg . EndLoc ; return


<s> } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV


<s> Stalls = <NUM_LIT> ; ITBlockSize = <NUM_LIT>


<s> MIB -> setDesc ( Desc ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; assert ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MIB -> getOperand

( <NUM_LIT> ) . getReg ( ) == Reg && <STR_LIT> ) ;


<s> getParser ( ) . Lex ( ) ; if ( ! getParser ( ) . parseIdentifier ( CodeID ) ) { if ( CodeID != <STR_LIT> ) return Error ( startLoc , <STR_LIT> ) ; Code = true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ; getStreamer ( ) . emitWinCFIPushFrame


<s> assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( STI . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT>


<s> case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue


<s> if ( ! decl ) return ; if ( ! cfun -> machine -> vector_load_decls ) cfun -> machine -> vector_load_decls = hash_set < tree > :: create_ggc ( <NUM_LIT> ) ; cfun -> machine -> vector_load_decls -> add


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < <NUM_LIT> ) { remove_insn ( insn ) ; return false ; } return


<s> intptr_t Addr = ( intptr_t ) MCE . getCurrentPCValue ( ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( Addr , ( intptr_t ) Fn , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> * <NUM_LIT> ) ; return MCE . finishGVStub ( F ) ; } MCE . startGVStub ( F , <NUM_LIT> * <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) MCE . getCurrentPCValue ( ) ; if ( is64Bit ) { MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; } else if ( TM . getSubtargetImpl ( ) -> isMachoABI ( ) ) { MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; } else { MCE . emitWordBE


<s> void <ISA_LIT>AsmPrinter :: printSOImmOperand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm


<s> bool InMBB = true ; if ( I ) { Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags


<s> RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; return N ; } if ( Opc == <STR_LIT> && isNullConstant ( RHS ) ) { if ( AN -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent && AN -> getSyncScopeID ( ) == SyncScope :: System ) { SDValue NewChain = emitLockedStackOp ( DAG , Subtarget , Chain , DL ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue LockOp = lowerAtomicArithWithLOCK ( N , DAG , Subtarget ) ; assert ( ! N -> hasAnyUseOfValue (


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ! VT . isFloatingPoint ( ) ) setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( ! VT . isFloatingPoint ( ) && VT != <STR_LIT> && VT != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Legal ) ; if ( VT . isFloatingPoint ( ) && ( VT . getVectorElementType ( ) != <STR_LIT> || Subtarget -> hasFullFP16 ( ) ) ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = (


<s> & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize < <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( uint32_t ( ~ <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ) ; else if ( BitSize == <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( ~ uint32_t ( <NUM_LIT> ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ,


<s> static int Lookup ( ArrayRef < TableEntry > Table , unsigned Opcode ) { const TableEntry * I = std :: lower_bound ( Table . begin ( ) , Table .


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return true


<s> MF -> push_back ( BB ) ; const Align MaxAlign = MCP -> getConstantPoolAlign ( ) ; const unsigned MaxLogAlign = Log2 ( MaxAlign ) ; BB -> setAlignment ( MaxAlign ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxLogAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; Align Alignment = CPs [ i ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ; unsigned LogAlign = Log2 ( Alignment ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxLogAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i


<s> if ( NewBB == CurBB ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB , CurBB ) ; if ( ! CommonDominator ) continue ; if ( CommonDominator != NewBB ) { assert ( CommonDominator != CurBB && <STR_LIT> ) ; NewPt = CommonDominator -> getTerminator ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; DEBUG ( NewPt -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo , IPI


<s> SDValue Intr = DAG . getNode ( Opc , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops . begin ( ) , Ops . size ( ) ) ; SDValue OutLo = DAG . getCopyFromReg ( Intr . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , Intr . getValue ( <NUM_LIT> ) ) ; SDValue OutHi = DAG . getCopyFromReg ( OutLo . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , OutLo . getValue ( <NUM_LIT> ) ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutLo , OutHi ) ; if ( ! HasChainIn ) return Out ; SDValue Vals [ ] = { Out , OutHi . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Vals


<s> assert ( DefMI ) ; if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI ->


<s> static bool classof ( const <ISA_LIT>MCSymbolRefExpr * ) { return


<s> OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( JMP64r << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , dl , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; unsigned char ModRM = N86R11 | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( ModRM , dl , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; } else { const Function * Func = cast < Function > ( cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) ; CallingConv :: ID CC = Func -> getCallingConv ( ) ; unsigned NestReg ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: <ISA_LIT>_StdCall : { NestReg = <STR_LIT> ; FunctionType * FTy = Func -> getFunctionType ( ) ; const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . hasAttribute ( Idx , Attribute :: InReg ) ) { auto & DL = DAG . getDataLayout ( ) ; InRegCount += ( DL . getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; } if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv


<s> if ( check ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) , getLoc ( ) , <STR_LIT>


<s> addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions ( ) ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( )


<s> bool isProgramMemoryAddress ( T * V ) { return cast < PointerType > ( V -> getType ( ) )

-> getAddressSpace ( ) == ProgramMemory ;


<s> case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_HA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HA ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HA ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ADDR16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_LO ; break ; } break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_ADDR14 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>64_TOC ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO : Type = ELF :: R_<ISA_LIT>64_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>64_TOC16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_LO ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_ENTRY : Type = ELF :: R_<ISA_LIT>64_TOC16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL16_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_LO_DS ; break ; } break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>64_TLS ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT>


<s> return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) .

Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> static int mips_adjust_cost ( rtx insn ATTRIBUTE_UNUSED , rtx link , rtx dep ATTRIBUTE_UNUSED , int cost ) { if ( REG_NOTE_KIND ( link ) != <NUM_LIT> ) return <NUM_LIT> ; return cost


<s> Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , DAG . getUNDEF ( WideVecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; return


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddr ( P , N . getOperand ( <NUM_LIT> ) ,

Base , Scale , Index , Disp , Segment ) ;


<s> } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : if ( ( Value & <NUM_LIT> ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; } Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { StringRef type = Kind == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + type + <STR_LIT> ) ; return <NUM_LIT> ; } break ; case


<s> unsigned getNumPICLabels ( ) const { return PICLabelUId


<s> MCWinCOFFStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll , bool IncrementalLinkerCompatible ) { auto * S = new <ISA_LIT>WinCOFFStreamer ( Context , std :: move ( MAB ) , std ::

move ( Emitter ) , std :: move ( OW ) ) ;


<s> if ( Offset >= ( <NUM_LIT> << <NUM_LIT> ) ) return SDValue ( ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; Type * T = GV -> getValueType ( ) ; if ( ! T -> isSized ( ) || Offset > GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( T ) ) return SDValue ( ) ; SDLoc DL ( GN ) ; SDValue Result = DAG . getGlobalAddress ( GV , DL , <STR_LIT> , Offset ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( MinOffset


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr


<s> if ( ! isMemory ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( (

Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == INT32_MIN ;