<s> SDValue TVal = Op -> getOperand ( <NUM_LIT> ) ; SDValue FVal = Op -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( Ty . isScalableVector ( ) ) { SDValue TruncCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCVal ) ; MVT PredVT = <STR_LIT> ( <STR_LIT> , Ty . getVectorElementCount ( ) ) ; SDValue SplatPred = DAG . getNode ( <STR_LIT> , DL , PredVT , TruncCC ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , SplatPred , TVal , FVal ) ; } if ( <STR_LIT> ( CCVal ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( CCVal -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , CCVal . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( OFCC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal -> getOperand (


<s> auto Op = MI -> getOperand ( OpNum ) ; auto CC = ( <STR_LIT> ) Op .


<s> APInt Zeroable = computeZeroableShuffleElements ( OrigMask , V1 , V2 ) ; if ( Zeroable . isAllOnesValue ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > ZeroableMask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( V2IsZero ) { assert ( ! Zeroable . isNullValue ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElements ; ++ i ) if ( OrigMask [ i ] != SM_SentinelUndef && Zeroable [ i ] ) ZeroableMask [ i ] = SM_SentinelZero ; } SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( ZeroableMask , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , OrigMask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( find ( WidenedMask , SM_SentinelZero ) != WidenedMask . end ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] =


<s> bool isConstantMemOff ( ) const { return isMem ( ) && isa < MCConstantExpr >


<s> bool IsVRReg ( unsigned Reg , MachineRegisterInfo & MRI ) { return IsRegInClass ( Reg ,


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags )


<s> return ( vector signed int ) __builtin_altivec_vupkhsh ( (


<s> if ( MO . isReg ( ) ) O << '%' << getRegisterName ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O , MAI ) ; else llvm_unreachable ( <STR_LIT>


<s> static void sh_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { enum rtx_code tmp_code = ( enum rtx_code ) * code ; sh_canonicalize_comparison ( tmp_code , * op0 , * op1 , VOIDmode , op0_preserve_value ) ; * code = ( int )


<s> const RegisterBankInfo * <ISA_LIT>Subtarget ::


<s> return __builtin_aarch64_uqshlv8qi_uus ( __a ,


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> } const MachineFunction * MF = TailCall . getParent ( ) -> getParent ( ) ; if ( Subtarget . isTargetWin64 ( ) && MF -> hasWinCFI ( ) ) { return false ; } assert ( BranchCond . size ( ) == <NUM_LIT> ) ; if ( BranchCond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) { return false ; } const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo


<s> int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! OpVal . getNode ( ) ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( ! OpVal . getNode ( ) ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; if ( ! APInt ( ValSizeInBytes * <NUM_LIT> , Value ) . isSplat ( ByteSize * <NUM_LIT> ) ) return SDValue ( ) ; int MaskVal = SignExtend32 ( Value , ByteSize * <NUM_LIT> ) ; if ( MaskVal == <NUM_LIT> ) return SDValue


<s> static SDValue combineFMinNumFMaxNum ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && VT == <STR_LIT> ) || ( VT . isVector ( ) && TLI . isTypeLegal ( VT ) ) ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op1 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op0 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 ,


<s> sign = ia64_unpack_sign ( operands [ <NUM_LIT> ] , unsignedp ) ; wmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; ia64_unpack_assemble ( l , operands [ <NUM_LIT> ] , sign , false


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: AExt : case CCValAssign :: AExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : case CCValAssign :: ZExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt : case CCValAssign :: SExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ; } return


<s> static int mips_symbol_insns ( enum mips_symbol_type type , machine_mode mode ) { if ( mode != MAX_MACHINE_MODE && MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ; return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ?


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( )


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { MVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; Register ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; updateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT>


<s> if ( isCall ( Inst , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitMask ( TargetReg , IndirectBranchMaskReg , STI ) ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; PendingCall = true ; return ; } if ( PendingCall ) { <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; EmitBundleUnlock (


<s> assert ( RestoreGPRs . LowGPR != RestoreGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( RestoreGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg != RestoreGPRs . LowGPR && Reg != RestoreGPRs . HighGPR && <STR_LIT> . contains

( Reg ) ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr .


<s> } } MVT LaneVT = <STR_LIT> ( VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LaneMask ; LaneMask . resize ( NumLanes * <NUM_LIT> , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL , V1 , V2 , LaneMask ) ; LaneShuffle = DAG . getBitcast ( VT


<s> return target ; } rtx_vector_builder int_builder ( VNx16QImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i < builder . encoded_nelts ( ) ; ++ i ) int_builder . quick_push ( INTVAL ( builder . elt ( i ) ) ? constm1_rtx : const0_rtx ) ; return aarch64_convert_sve_data_to_pred ( target , VNx16BImode ,


<s> bool <ISA_LIT>TargetMachine :: addSimpleCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( )


<s> } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; while ( Bytes ) { unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; ThisVal /= Scale ; if ( isTwoAddr ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( DestReg ) . addImm ( ThisVal ) ; if ( NeedPred ) MIB = AddDefaultPred ( MIB ) ; } else { bool isKill = BaseReg != <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( BaseReg , getKillRegState ( isKill ) ) . addImm ( ThisVal ) ; if ( NeedPred ) MIB = AddDefaultPred ( MIB ) ; BaseReg = DestReg ; if ( Opc == <STR_LIT> ) { NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; NeedPred = NeedCC =


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfptstsfi_eq_dd || icode == CODE_FOR_dfptstsfi_lt_dd || icode == CODE_FOR_dfptstsfi_gt_dd || icode == CODE_FOR_dfptstsfi_unordered_dd || icode == CODE_FOR_dfptstsfi_eq_td || icode == CODE_FOR_dfptstsfi_lt_td || icode == CODE_FOR_dfptstsfi_gt_td || icode == CODE_FOR_dfptstsfi_unordered_td ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg0 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_xststdcdp || icode == CODE_FOR_xststdcsp || icode == CODE_FOR_xvtstdcdp || icode == CODE_FOR_xvtstdcsp ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg1 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode


<s> if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( isUnsupportedFloatingType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else if ( Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { if ( isNonFoldablePartialRegisterLoad ( LoadMI , MI , MF ) ) return nullptr ; MOs . append ( LoadMI . operands_begin ( ) + NumOps - <STR_LIT> , LoadMI . operands_begin ( ) + NumOps ) ; break ; } } return foldMemoryOperandImpl ( MF , MI , Ops [ <NUM_LIT> ] , MOs , InsertPt ,


<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getLogAlignment ( ) , MIPS_NACL_BUNDLE_LOG_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; TS . setUsesMicro<ISA_LIT> ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS


<s> x ^= x >> <NUM_LIT> ; x &= <NUM_LIT> ; return ( <NUM_LIT> >> x


<s> return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) &&

getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> return Kind == Immediate && isUInt < <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_cvtps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8


<s> rtx mask ; gcc_checking_assert ( ! BYTES_BIG_ENDIAN ) ; mask = GEN_INT ( one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; mask = gen_const_vec_duplicate (


<s> SDValue <ISA_LIT>TargetLowering :: LowerDarwin_VASTART ( SDValue Op , SelectionDAG & DAG ) const { <ISA_LIT>FunctionInfo * FuncInfo = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL (


<s> SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal )


<s> if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ; else Const = ConstantFP :: get ( Type :: getDoubleTy ( C ) , Val . bitsToDouble ( ) ) ; } else Const = Constant :: getIntegerValue ( Type :: getIntNTy ( C , ScalarSize ) ,


<s> if ( Subtarget . hasSSE41 ( ) || BitSize == <NUM_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( NumSrcBits , NumPackedBits ) ; if ( ( N1 . isUndef ( ) || IsZero1 || DAG . MaskedValueIsZero ( N1 , ZeroMask ) ) && ( N2 . isUndef ( ) || IsZero2 || DAG . MaskedValueIsZero ( N2 , ZeroMask ) ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } bool IsAllOnes1 = llvm :: isAllOnesOrAllOnesSplat ( N1 , false ) ; bool IsAllOnes2 = llvm :: isAllOnesOrAllOnesSplat ( N2 , false ) ; if ( ( N1 . isUndef ( ) || IsZero1 || IsAllOnes1 || DAG . ComputeNumSignBits ( N1 ) > NumPackedBits ) && ( N2 . isUndef ( ) || IsZero2 || IsAllOnes2 || DAG . ComputeNumSignBits ( N2 ) > NumPackedBits ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true


<s> createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; return SDValue (


<s> if ( isMacho ) return LP64 ? <NUM_LIT> : <NUM_LIT> ; return -


<s> bool <ISA_LIT>AsmParser :: cvtLdWriteBackRegAddrMode3 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands (


<s> __inline__ static void sh_media_OCBI ( void * mm , int s ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char


<s> rtx mask = gen_reg_rtx ( mode ) ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse ; emit_insn ( insn ( mask , op0 , op1 , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask


<s> SDValue LoweredLogical = computeLogicOpInGPR ( SDValue ( N , <NUM_LIT> ) ) ; if ( ! LoweredLogical ) return false ; SDLoc dl ( N ) ; bool IsBitwiseNegate = LoweredLogical . getMachineOpcode ( ) == <STR_LIT> ; unsigned SubRegToExtract = IsBitwiseNegate ? <STR_LIT> : <STR_LIT> ; SDValue CR0Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue LHS = LoweredLogical . getOperand ( <NUM_LIT> ) ; SDValue RHS = LoweredLogical . getOperand ( <NUM_LIT> ) ; SDValue WideOp ; SDValue OpToConvToRecForm ; if ( IsBitwiseNegate && LoweredLogical . getOperand ( <NUM_LIT> ) . getMachineOpcode ( ) == <STR_LIT> ) OpToConvToRecForm = LoweredLogical . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else if ( IsBitwiseNegate ) OpToConvToRecForm = LoweredLogical . getOperand ( <NUM_LIT> ) ; else OpToConvToRecForm = LoweredLogical ; uint16_t NonRecOpc = OpToConvToRecForm . getMachineOpcode ( ) ; int NewOpc = <ISA_LIT>InstrInfo :: getRecordFormOpcode ( NonRecOpc ) ; if ( NewOpc != - <NUM_LIT> && IsBitwiseNegate ) { assert ( LoweredLogical . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; std :: vector < SDValue > Ops ; for ( int i = <NUM_LIT> , e = OpToConvToRecForm . getNumOperands ( ) ; i < e ; i ++ ) Ops . push_back ( OpToConvToRecForm . getOperand ( i ) ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc , dl , OpToConvToRecForm . getValueType ( ) , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { assert ( ( NewOpc != - <NUM_LIT> || ! IsBitwiseNegate ) && <STR_LIT> ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc == - <NUM_LIT> ? <STR_LIT> : NewOpc , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; } SDValue SRIdxVal = CurDAG -> getTargetConstant ( SubRegToExtract , dl , <STR_LIT> ) ; SDValue CRBit = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , CR0Reg , SRIdxVal , WideOp . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; ReplaceNode ( N , CRBit . getNode ( ) ) ; return


<s> printUImmOperand < <NUM_LIT> > ( MI , OpNum ,


<s> MachineInstrBuilder MIB = BuildMI ( MBB , Pos , DebugLoc ( ) , TII . get ( Opc ) ) ; if ( IsPostDec ) MIB . addDef ( <STR_LIT> ) ; MIB . addReg ( Reg2 , getDefRegState ( true ) ) . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . setMIFlag


<s> regno = true_regnum ( reg ) ; if ( regno < <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= <NUM_LIT> ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + getReg ( ) - <STR_LIT>


<s> static MCDisassembler * create<ISA_LIT>64Disassembler ( const Target & T , const MCSubtargetInfo &


<s> MII -- ; MachineInstr * CurrentMI = & * MII ; if ( CurrentMI -> getOpcode ( ) == DupOpcode && CurrentMI -> getNumOperands ( ) == <NUM_LIT> && CurrentMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && CurrentMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == LaneNumber ) { * DestReg = CurrentMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase (


<s> Optional < unsigned > getVScaleForTuning


<s> } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSX ( ) && <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode (


<s> * special = SH_CONCAT ; return <NUM_LIT> ; } if ( GET_CODE ( body ) == PARALLEL ) { rtx expr = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( expr ) == SET && v2df_reduction_p ( SET_SRC ( expr ) ) ) return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VPERM && XVECLEN ( SET_SRC ( body ) , <NUM_LIT> ) == <NUM_LIT> && GET_CODE ( XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ) == REG ) { rtx mask_reg = XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) if ( rtx_equal_p ( DF_REF_REG ( use ) , mask_reg ) ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( def_link && ! def_link -> next && const_load_sequence_p ( insn_entry , DF_REF_INSN


<s> InFlag = SDValue ( ) ; StoreTailCallArgumentsToStackSlot ( DAG , Chain , TailCallArguments , MemOpChains2 , dl ) ; if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains2 ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , InFlag , dl ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStandardEncoding ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode

( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ;


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return true ; return false


<s> assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != -


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask .

push_back ( l + ( ( Imm >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ) ;


<s> unsigned WideBits = getScalarSizeInBits ( Ty ) * cast < VectorType > ( Ty ) -> getNumElements ( ) ; assert ( WideBits > <NUM_LIT>


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 .


<s> int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum + param_size > CSKY_NPARM_REGS ) * pcum = CSKY_NPARM_REGS ; else * pcum


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Constant * Const = nullptr ; if ( ! match ( TCP . Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) && ! match ( TCP . Induction , m_Or ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; Instruction * Insert = nullptr ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero ( ) ) ) ) return false ; auto * Phi = dyn_cast < PHINode > ( IV ) ; if ( ! Phi ) return


<s> if ( Subtarget -> hasXMMInt ( ) ) return <STR_LIT> ; if ( Subtarget -> hasXMM ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasXMMInt ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOffsetOfOperator ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: Tilde ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite (


<s> if ( num_regs == <NUM_LIT> && ! arm_arch6 ) { if ( first_reg == <NUM_LIT> ) first_reg -- ; num_regs ++ ; } if ( num_regs > <NUM_LIT> ) { arm_emit_vfp_multi_reg_pop ( first_reg , <NUM_LIT> , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + <NUM_LIT> , num_regs - <NUM_LIT> , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( VOIDmode , base_reg , plus_constant ( Pmode , base_reg , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( j = <NUM_LIT> , i = first_reg ; j < num_regs ; i += <NUM_LIT> ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( VOIDmode , reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + <NUM_LIT> ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = <NUM_LIT> ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx )


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> && <STR_LIT> ) ; VT = <STR_LIT> ; } } else { if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } } bool RV ; unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV && <STR_LIT> ) ; ( void ) RV ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; Dest . Offset += Size ; Src . Offset +=


<s> case BUILT_IN_SQRT : if ( out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return MIPS_GET_BUILTIN ( msa_fsqrt_d ) ; break ; case BUILT_IN_SQRTF : if ( out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n ==


<s> return ( __m128i ) __builtin_ia32_pmovsxwd128_mask ( ( __v8hi ) __A , (


<s> CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; tree arg_type , fntype ; bool first_param = true ; function_args_iterator args_iter ; uint32_t padding_bits_to_clear [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( ! CALL_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , <NUM_LIT> ) > <NUM_LIT> ) ; call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; unspec = XEXP ( call , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) != UNSPEC || XINT ( unspec , <NUM_LIT> ) != UNSPEC_NONSECURE_MEM ) continue ; bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , NUM_ARG_REGS ) ; if ( TARGET_HARD_FLOAT_ABI ) { auto_sbitmap float_bitmap ( maxregno + <NUM_LIT> ) ; bitmap_clear ( float_bitmap ) ; bitmap_set_range ( float_bitmap , FIRST_VFP_REGNUM , D7_VFP_REGNUM - FIRST_VFP_REGNUM + <NUM_LIT> ) ; bitmap_ior ( to_clear_bitmap , to_clear_bitmap , float_bitmap ) ; } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; address_regnum = REGNO ( XEXP ( address , <NUM_LIT> ) ) ; if ( address_regnum < R0_REGNUM + NUM_ARG_REGS ) bitmap_clear_bit ( to_clear_bitmap , address_regnum ) ; set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( ) ; emit_insn ( gen_blockage ( ) ) ; fntype = TREE_TYPE ( MEM_EXPR ( address ) ) ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , NULL_TREE ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; uint64_t to_clear_args_mask ; machine_mode arg_mode = TYPE_MODE ( arg_type ) ; if ( VOID_TYPE_P ( arg_type ) ) continue ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg_mode , arg_type , true ) ; arg_rtx = arm_function_arg ( args_so_far , arg_mode , arg_type , true ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno )

) bitmap_clear_bit ( to_clear_bitmap , regno ) ;


<s> if ( SDValue Flags = combineSetCCEFLAGS ( Cond , CC , DAG , Subtarget ) ) { if ( FalseOp . getValueType ( ) != <STR_LIT> || hasFPCMov ( CC ) ) { SDValue Ops [ ] = { FalseOp , TrueOp , DAG . getConstant ( CC , DL , <STR_LIT> ) , Flags } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } } if ( ConstantSDNode * TrueC = dyn_cast < ConstantSDNode > ( TrueOp ) ) { if ( ConstantSDNode * FalseC = dyn_cast < ConstantSDNode > ( FalseOp ) ) { if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueC , FalseC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , TrueC -> getValueType ( <NUM_LIT> ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; return Cond ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT>


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: systemz > X (


<s> auto MaybeZero = getConstantVRegValWithLookThrough ( MaybeSub -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; return MaybeZero && MaybeZero -> Value . getZExtValue


<s> if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true ; } } if ( ! IsUnary )


<s> lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops ,


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) << <NUM_LIT> ) ) ; NumOpsAdded = <NUM_LIT>


<s> case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case E_V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case E_V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case E_V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , <NUM_LIT> ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case E_V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case E_V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target ,


<s> return ( __m64 ) __builtin_ia32_pfsubr ( ( __v2sf


<s> return ( __m64 ) __builtin_ia32_psubsb ( ( __v8qi )


<s> Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc LaneLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( LaneLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } continue ; } if ( ! Spacing ) Spacing = <NUM_LIT> + ( Reg == OldReg + <NUM_LIT> ) ; if ( Reg != OldReg + Spacing ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Count ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; switch ( LaneKind ) { case NoLanes : if ( Count == <NUM_LIT> ) { const MCRegisterClass * RC = ( Spacing == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] : & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; FirstReg = MRI -> getMatchingSuperReg ( FirstReg , <STR_LIT> , RC ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , ( Spacing == <NUM_LIT> ) , S , E ) ) ; break ; case AllLanes : if ( Count == <NUM_LIT> ) { const MCRegisterClass * RC = ( Spacing == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] : & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; FirstReg = MRI -> getMatchingSuperReg ( FirstReg , <STR_LIT> , RC ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateVectorListAllLanes ( FirstReg , Count , ( Spacing == <NUM_LIT> ) , S , E ) ) ; break ; case IndexedLane : Operands . push_back ( <ISA_LIT>Operand :: CreateVectorListIndexed ( FirstReg , Count , LaneIndex , ( Spacing == <NUM_LIT> ) , S ,


<s> return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit )


<s> const MCSection * <ISA_LIT>ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx )


<s> bool <ISA_LIT>TTIImpl :: useNeonVector ( const Type * Ty ) const { return isa < FixedVectorType > ( Ty )

&& ! ST -> useSVEForFixedLengthVectors ( ) ;


<s> static SDValue combineSetCCEFLAGS ( SDValue EFLAGS , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG


<s> if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( E ) ) { const int64_t Value = MCE -> getValue ( ) ; if ( Value > UINT32_MAX ) report_fatal_error ( <STR_LIT> ) ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : return ( int32_t ( Value ) & <NUM_LIT> ) >> <NUM_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT>


<s> static rtx ix86_validate_address_register ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; if ( mode != SImode && mode != DImode ) return NULL_RTX ; if ( REG_P ( op ) ) return op ; else if ( SUBREG_P ( op ) ) { rtx reg = SUBREG_REG ( op ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; mode = GET_MODE ( reg ) ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return NULL_RTX ; if ( register_no_elim_operand ( reg , mode ) ) return reg ; } return


<s> warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , ret_type ) ; return <NUM_LIT> ; } tree t ; int i ; tree type_arg_types = TYPE_ARG_TYPES ( TREE_TYPE ( node -> decl ) ) ; bool decl_arg_p = ( node -> definition || type_arg_types == NULL_TREE ) ; for ( t = ( decl_arg_p ? DECL_ARGUMENTS ( node -> decl ) : type_arg_types ) , i = <NUM_LIT> ; t && t != void_list_node ; t = TREE_CHAIN ( t ) , i ++ ) { tree arg_type = decl_arg_p ? TREE_TYPE ( t ) : TREE_VALUE ( t ) ; switch ( TYPE_MODE ( arg_type ) ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_SFmode : case E_DFmode : if ( ! AGGREGATE_TYPE_P ( arg_type ) ) break ; default : if ( clonei -> args [ i ] . arg_type == SIMD_CLONE_ARG_TYPE_UNIFORM ) break ; warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , arg_type ) ; return <NUM_LIT> ; } } if ( ! TREE_PUBLIC ( node -> decl ) ) { if ( TARGET_AVX512F ) clonei -> vecsize_mangle


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( trySelect ( Node ) ) return ; switch ( Opcode )


<s> if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ; return Subtarget . isTarget64BitLP64 ( )


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> return aarch64_vfp_is_call_or_return_candidate ( mode , type , & pcum ->


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret


<s> } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( SHUFPDMask ,


<s> virtual void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const LLVM_OVERRIDE ; virtual bool mayNeedRelaxation ( const MCInst & Inst ) const LLVM_OVERRIDE ; virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const LLVM_OVERRIDE ; virtual void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const LLVM_OVERRIDE ; virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const LLVM_OVERRIDE ; virtual MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const LLVM_OVERRIDE { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const LLVM_OVERRIDE { return false ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return getRelaxedOpcode ( Inst . getOpcode ( ) ) != <NUM_LIT> ; } bool <ISA_LIT>MCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != ( int64_t ) Value ; } void <ISA_LIT>MCAsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { unsigned Opcode = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; assert ( Opcode && <STR_LIT> ) ; Res = Inst ; Res . setOpcode ( Opcode ) ; } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count ,


<s> LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue MaskCasted = DAG . getBitcast (


<s> unsigned Res = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( Res ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( ! Operand . isImm ( ) ) return Error ( Operand . getStartLoc ( ) , <STR_LIT> ) ; switch ( Res ) { case Match_InvalidSImm ## nbits : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> ) ; case Match_InvalidUImm ## nbits : \ return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> ) ; case Match_InvalidSImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> , \ <STR_LIT> ) ; case Match_InvalidUImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> , \ <STR_LIT> ) ; CASE_MATCH_INVALID_UIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_SIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_UIMM_LSB0 ( <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case


<s> return ( isMOVLMask ( Mask , SVT ) || isCommutedMOVLMask ( Mask , SVT , true ) || isSHUFPMask ( Mask , SVT ) || isSHUFPMask ( Mask , SVT , true ) || isBlendMask ( Mask , SVT , Subtarget -> hasSSE41 (


<s> NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT>


<s> if ( Subtarget -> is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext (

) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ;


<s> unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI =


<s> printFormattedRegName ( & MAI , RegNo ,


<s> gcc_assert ( compute_now == ( pic_reg != NULL_RTX ) ) ; if ( ! crtl -> uses_pic_offset_table || compute_now ) { gcc_assert ( can_create_pseudo_p ( ) || ( pic_reg != NULL_RTX && REG_P ( pic_reg ) && GET_MODE ( pic_reg ) == Pmode ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! compute_now && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = <NUM_LIT> ; } else { rtx_insn * seq , * insn ; if ( pic_reg == NULL_RTX ) pic_reg = gen_reg_rtx ( Pmode ) ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = pic_reg ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && ! compute_now ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( <NUM_LIT> , pic_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P

( insn ) ) INSN_LOCATION ( insn ) = prologue_location ;


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r632 , Instr , Insn , Address , this , STI ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( hasCOP3 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM , this ) , DL ( computeDataLayout ( Subtarget ) ) , InstrInfo ( <ISA_LIT>InstrInfo ::

create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , JITInfo ( ) {


<s> if ( MRI . isSSA ( ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( ! III . ZeroIsSpecialOrig ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; if ( MI . getOperand ( III . ZeroIsSpecialOrig ) . getReg ( ) != <STR_LIT> && MI . getOperand ( III . ZeroIsSpecialOrig ) . getReg ( ) != <STR_LIT> ) return false ; return true


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { unsigned Align = getStackAlignment ( ) ; int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount = alignTo ( Amount , Align


<s> unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d


<s> return ( ( vec_double2 ) ( si_dfnma ( ( qword ) ( a ) , ( qword ) ( b


<s> if ( Opcode == <STR_LIT> ) { if ( isShiftMask ) Mask = Mask << Shift ; Indeterminant = ~ ( <NUM_LIT> << Shift ) ; } else if ( Opcode == <STR_LIT> ) { if ( isShiftMask ) Mask = Mask >> Shift ; Indeterminant = ~ ( <NUM_LIT> >> Shift ) ; Shift = <NUM_LIT> - Shift ; } else if ( Opcode == <STR_LIT>


<s> extern __inline __m128h __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_castph256_ph128 ( __m256h __A ) { union { __m128h a [ <NUM_LIT> ] ; __m256h v ; } u = { . v =


<s> if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getAnyExtOrTrunc ( Src . getOperand ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == N1Opc && ( N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> ) ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal ( <NUM_LIT> ) ; if ( N00Index == N01Index && N10Index == N11Index && N00Index == <NUM_LIT> && N10Index == N00VT . getVectorNumElements ( ) ) return DAG . getNode ( N0Opc , dl , VT , N00Source , N01Source ) ; } } } if ( N -> getNumOperands ( ) == <NUM_LIT> && N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N -> getNumOperands ( ) != <NUM_LIT> || N1Opc != <STR_LIT> ) return SDValue ( ) ; SDValue RHS = N1 -> getOperand ( <NUM_LIT> ) ; MVT RHSTy = RHS . getValueType ( ) . getSimpleVT ( ) ; if ( ! RHSTy . isVector ( ) ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MVT ConcatTy = <STR_LIT> ( RHSTy . getVectorElementType ( ) , RHSTy

. getVectorNumElements ( ) * <NUM_LIT> ) ;


<s> bool SplitStack = MF . shouldSplitStack ( ) ; bool Lower = ( Subtarget -> isOSWindows ( ) && ! Subtarget -> isTargetMacho ( ) ) || SplitStack ; SDLoc dl ( Op ) ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDNode * Node = Op . getNode ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue Tmp1 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp2 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp3 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Chain = Tmp1 . getOperand ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * getTargetMachine ( ) . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ; } SDValue Chain = Op . getOperand


<s> const char * arm_mangle_type ( const_tree type ) { if ( TARGET_AAPCS_BASED && lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type )


<s> static inline __ev64_opaque__ __internal_ev_mwhssfanw ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhssf ( a


<s> CCAssignFn * getReturnCC ( CallingConv :: ID CallConv ) { switch ( CallConv ) { default : return RetCC_<ISA_LIT>_C ; case CallingConv ::


<s> const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL ,

Chain , StackSlot , MachinePointerInfo ( ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState ::


<s> static ShapeT getShape ( const MachineInstr & MI , MachineRegisterInfo * MRI ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand & MO2 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; ShapeT Shape ( & MO1 ,


<s> this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI )


<s> assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned NumVectors = getNumberOfParts ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return (

Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ;


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b )


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS ,


<s> bool isVectorReg ( ) const { return Kind == Register && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (

getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ;


<s> crx_compute_save_regs ( ) ; crx_compute_frame ( ) ; if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : <NUM_LIT> ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == FRAME_POINTER_REGNUM ) return ( sum_regs + local_vars_size ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( sum_regs + local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : <NUM_LIT> ) ) ; else abort (


<s> switch ( insn_type ) { case TYPE_STORE : if ( dep_type == TYPE_IALU || dep_type == TYPE_SHIFT ) { if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) break ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) )


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return new <ISA_LIT>WinCOFFStreamer ( Context , MAB , * Emitter ,


<s> if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return


<s> MachineOperand & OffsetMO = MI -> getOperand ( <NUM_LIT> ) ; uint64_t Offset = ( MFFrame -> getMaxCallFrameSize ( ) + <STR_LIT> + OffsetMO . getImm ( ) ) ; unsigned NewOpcode = getOpcodeForOffset ( <STR_LIT> , Offset ) ; assert ( NewOpcode && <STR_LIT>


<s> return static_cast < <ISA_LIT>DCFunction & > ( DCBasicBlock


<s> Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getElementType ( ) , BaseAddr

, VecTy -> getNumElements ( ) * Factor ) ;


<s> assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL =


<s> void addRegVFRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( VFRegs [


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return get<ISA_LIT>RegisterNumbering ( <STR_LIT>


<s> void addACC64DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional <


<s> src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset ==


<s> unsigned Mul = ( NumElems == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != NumElems ; ++ i ) { int Elt = SVOp -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt %= HalfSize ; unsigned Shamt = i ; if ( NumElems == <NUM_LIT> )


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallingConv = <STR_LIT> ; return SpecialCallingConv


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) return false ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS


__mask , __m128i __index , long long const * __addr , int __scale ) {


<s> if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( )


<s> if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; return ! isa < ConstantSDNode


<s> return ( _TEXASRU_EXTRACT_BITS ( texasru , <NUM_LIT> , <NUM_LIT> ) ) ?


<s> bool useSVEForFixedLengthVectors ( )


<s> return __builtin_ia32_vtestcps256 ( ( __v8sf ) __M , ( __v8sf )


<s> bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub


<s> void onNot ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_OR : case IES_XOR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_LBRAC : State = IES_NOT ; IC . pushOperator


<s> return _mm_set_epi64x ( ( long long ) __q1


<s> return __builtin_mve_vcvtmq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; if ( Immediate ) { int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; } else { Ops . push_back ( N -> getOperand ( <NUM_LIT>


<s> Op = DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Op ) ; SDValue TruncNode = DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode ) ; SDValue Delta = DAG . getConstant ( <NUM_LIT> - EltVT . getSizeInBits ( ) , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl


<s> bool targetSchedulesPostRAScheduling ( ) const override


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O <<


<s> unsigned <ISA_LIT>TTI :: getShuffleCost ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { return TargetTransformInfo :: getShuffleCost ( Kind ,


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> bool <ISA_LIT>TargetLowering :: splitValueIntoRegisterParts ( SelectionDAG & DAG , const SDLoc & DL , SDValue Val , SDValue * Parts , unsigned NumParts , MVT PartVT , Optional < CallingConv :: ID > CC ) const { EVT ValVT = Val . getValueType ( ) ; if ( PartVT == <STR_LIT> && ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || ValVT == <STR_LIT> ) ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL


<s> static SDValue getFullRegister ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl (


<s> MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo .


<s> LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset


<s> TM . resetSubtarget ( & MF ) ; return false


<s> unsigned getMemBaseReg ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem . BaseReg


<s> return ( __m512i ) __builtin_ia32_psraq512_mask ( ( __v8di ) __A , ( __v2di ) __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 )


<s> if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> << fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc ,


<s> else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window (


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N ,


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; return Binary | <STR_LIT> ( MO1 . getImm


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType )

: <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> void <ISA_LIT>SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF


<s> DenseMap < SDValue , APInt > SrcOpMap ; EVT VT = <STR_LIT> ; assert ( Op . getOpcode ( ) == unsigned ( BinOp ) && <STR_LIT> ) ; Opnds . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == unsigned ( BinOp ) ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; auto * Idx = dyn_cast < ConstantSDNode > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Idx ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( ! SrcOpMap . empty ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt EltCount = APInt :: getZero ( NumElts ) ; M = SrcOpMap . insert ( std :: make_pair ( Src , EltCount ) ) . first ; SrcOps . push_back ( Src ) ; } unsigned CIdx = Idx -> getZExtValue ( ) ; if ( M -> second [ CIdx ] ) return false ; M -> second . setBit ( CIdx ) ; } if ( SrcMask


<s> if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> isLittle ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; bool Changes = MatchSMLAD ( F ) ; return Changes


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return true ; else if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return ( regno & <NUM_LIT> ) == <NUM_LIT> ; } else if ( FP_REGNUM_P ( regno )


<s> * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; return true ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; __asm { mov eax , value cpuid mov esi , rEAX mov dword ptr [ esi ] , eax mov esi , rEBX mov dword ptr [ esi ] , ebx mov esi , rECX mov dword ptr [ esi ] ,

ecx mov esi , rEDX mov dword ptr [ esi ] , edx }


<s> if ( NumBytes && ! canUseRedZone ( MF ) ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( FrameLabel , - NumBytes ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } else if ( NumBytes ) { ++ NumRedZoneFunctions ; } return ; } int FPOffset = <NUM_LIT> ; if ( HasFP ) FPOffset = getFPOffsetInPrologue ( MBBI ) ; while ( isCSSave ( MBBI ) ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; const unsigned Alignment = MFI -> getMaxAlignment ( ) ; const bool NeedsRealignment = RegInfo -> needsStackRealignment ( MF ) ; unsigned scratchSPReg = <STR_LIT> ; if ( NumBytes && NeedsRealignment ) { scratchSPReg = <STR_LIT> ; } if ( NumBytes && ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , scratchSPReg , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; if ( NumBytes && NeedsRealignment ) { const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( NrBitsToZero > <NUM_LIT> ) ; assert ( scratchSPReg != <STR_LIT> ) ; uint32_t andMaskEncoded = ( <NUM_LIT> << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero ) << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero -


<s> rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return <NUM_LIT> ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( GET_CODE ( x ) == AND && ( op == EQ || op == NE ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) ) return arm_select_dominance_cc_mode ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , DOM_CC_X_AND_Y ) ; if ( GET_CODE ( x ) == IOR && ( op == EQ || op == NE ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) ) return arm_select_dominance_cc_mode ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , DOM_CC_X_OR_Y ) ; if ( TARGET_THUMB1 && GET_MODE ( x ) == SImode && ( op == EQ || op == NE ) && GET_CODE ( x ) == ZERO_EXTRACT && XEXP ( x , <NUM_LIT> ) == const1_rtx ) return CC_Nmode ; if ( GET_MODE ( x ) == SImode && y == const0_rtx && ( op == EQ || op == NE || op == LT || op == GE ) && ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == AND || GET_CODE ( x ) == IOR || GET_CODE ( x ) == XOR || GET_CODE ( x ) == MULT || GET_CODE ( x ) == NOT || GET_CODE ( x ) == NEG || GET_CODE ( x ) == LSHIFTRT || GET_CODE ( x ) == ASHIFT || GET_CODE ( x ) == ASHIFTRT || GET_CODE ( x ) == ROTATERT || ( TARGET_32BIT && GET_CODE ( x ) == ZERO_EXTRACT ) ) ) return CC_NOOVmode ; if ( GET_MODE ( x ) == QImode && ( op == EQ || op == NE ) ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) || rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) ) ) return CC_Cmode ; if ( GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ) { switch ( op ) { case EQ : case NE : if ( y == const0_rtx ) return CC_Zmode ; if ( ! TARGET_32BIT ) return CC_Zmode ; case LTU : case LEU : case GTU : case GEU : if ( TARGET_32BIT ) return CC_CZmode ; case LT : case LE : case GT