<s> } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; if ( Offset != MFI . getObjectOffset ( FI ) ) return false ; if ( ! Flags . isByVal ( ) && ! MFI . isImmutableObjectIndex ( FI ) ) return false ; if ( VA . getLocVT ( ) . getSizeInBits ( ) > Arg . getValueSizeInBits ( ) ) { if ( Flags . isZExt ( ) != MFI . isObjectZExt ( FI ) || Flags . isSExt ( ) != MFI


<s> static DecodeStatus DecodeCheriGPROrCNullRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( PromotedGlobals . count ( GV ) ) return ; AsmPrinter :: emitGlobalVariable ( GV


<s> static void mips_file_start ( void ) { default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , mips_mdebug_abi_name ( ) ) ; if ( mips_abi == ABI_EABI || mips_abi == ABI_O64 ) fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , TARGET_LONG64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT ) fprintf ( asm_out_file , <STR_LIT> , mips_nan == MIPS_IEEE_754_2008 ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_NO_FLOAT ) fputs ( <STR_LIT> , asm_out_file ) ; ; else if ( ! TARGET_HARD_FLOAT_ABI ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ! TARGET_DOUBLE_FLOAT ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_FLOATXX ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_FLOAT64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file


<s> static void aarch64_simd_clone_adjust ( struct cgraph_node * node ) { tree t = TREE_TYPE ( node -> decl


<s> return ( ( qword ) ( vec_andc ( vec_sl ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b


<s> static void demoteInst ( MCInst & Inst , const MCInstrInfo & InstInfo ) { unsigned NewOpc = demoteOpcode ( Inst . getOpcode ( ) ) ; Inst . setOpcode ( NewOpc ) ; const MCOperandInfo * OpInfo = InstInfo . get ( Inst


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * PtrAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Root . getReg ( ) , MRI ) ; if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineInstr * OffsetInst = getDefIgnoringCopies ( PtrAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; return selectExtendedSHL ( Root , PtrAdd -> getOperand ( <NUM_LIT> ) , OffsetInst -> getOperand ( <NUM_LIT> ) , SizeInBytes ,


<s> if ( fn -> decl == NULL ) return true ; if ( fn -> stdarg ) return true ; for ( t = DECL_ARGUMENTS ( fn -> decl ) ; t ; t = TREE_CHAIN ( t ) ) { if ( ! use_register_for_decl ( t ) ) return true ; if ( DECL_MODE ( t ) != SImode ) return true ; } return false


<s> tmp [ <NUM_LIT> ] = force_reg ( fltmode , ix86_build_const_vector ( fltmode , <NUM_LIT> , tmp [ <NUM_LIT> ] ) ) ; if ( TARGET_FMA ) { tmp [ <NUM_LIT> ] = gen_rtx_FMA ( fltmode , tmp [ <NUM_LIT> ] , tmp [ <NUM_LIT> ] , tmp [ <NUM_LIT> ] ) ; emit_move_insn ( target , tmp [ <NUM_LIT> ] ) ; } else { tmp [ <NUM_LIT> ] = expand_simple_binop ( fltmode , MULT , tmp [ <NUM_LIT> ] , tmp [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp [ <NUM_LIT> ] = expand_simple_binop ( fltmode , PLUS , tmp [ <NUM_LIT> ] , tmp [ <NUM_LIT> ] , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( tmp [ <NUM_LIT> ] != target ) emit_move_insn ( target , tmp [


<s> if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( ! isAligned ( StackAlign , CC . ExpectedDist ) ) Advantage -= <NUM_LIT> ; Advantage += ( CC . ExpectedDist >> Log2SlotSize


<s> unsigned Opcode = MI . getOpcode ( ) ; int TargetMemOpcode = <STR_LIT> ( Opcode ) ; if ( TargetMemOpcode != - <NUM_LIT> ) { MI . setDesc ( TII -> get ( TargetMemOpcode ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( DstReg != SrcMO . getReg ( ) ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) .


<s> calculateWinCXXEHStateNumbers ( & F , FuncInfo ) ; addStateStoresToFunclet ( RegNode , FuncInfo , F , - <NUM_LIT> ) ; int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex = RegNodeEscapeIndex ; Constant * FI8 = ConstantExpr :: getBitCast ( & F , Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ) ; for ( auto P : FuncInfo . HandlerBaseState ) { Function * Handler = const_cast < Function * > ( P . first ) ; int BaseState = P . second ; IRBuilder < > Builder ( & Handler -> getEntryBlock ( ) , Handler -> getEntryBlock ( ) . begin ( ) ) ; Value * ParentFP = Builder . CreateCall ( FrameAddress , { Builder . getInt32 ( <NUM_LIT> ) } ) ; Value * RecoveredRegNode = Builder . CreateCall ( FrameRecover , { FI8 , ParentFP , Builder . getInt32


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> lshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( lshift , shmax ) ; result = vec_sl ( ( __v4su ) __A , lshift ) ; result = vec_sel ( ( __v4su ) shmask , result , shmask ) ; return ( __m128i )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo (


<s> WriteGraph ( OS , G , false , <STR_LIT> + MF . getName ( )


<s> SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) != <STR_LIT> ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( UI -> getNumOperands ( ) > <NUM_LIT> ) return false ; if ( UI -> getNumOperands ( ) == <NUM_LIT> && UI -> getOperand ( UI -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; HasRet = true ; } if ( ! HasRet


<s> Op -> ModImm . Rot = Rot ; Op -> StartLoc = S ; Op -> EndLoc =


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , *


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt ::


<s> return ( __m256 ) __builtin_ia32_rndscaleps_256_mask ( ( __v8sf ) __A , __imm , ( __v8sf ) _mm256_setzero_ps ( ) , (


<s> assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MRI -> replaceRegWith ( SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg


<s> int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register BasePtr ; int64_t Offset = ( TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getDebugOffset ( ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) { if ( OpcodeForOffset == <STR_LIT> && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVector ( ) ) { OpcodeForOffset = <STR_LIT> ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( &


<s> while ( CurrVT != VT ) { int CurrScalarSizeInBits = CurrVT . getScalarSizeInBits ( ) ; int CurrNumElts = CurrVT . getVectorNumElements ( ) ; MVT NextSVT = <STR_LIT> ( CurrScalarSizeInBits * <NUM_LIT> ) ; MVT NextVT = <STR_LIT> ( NextSVT , CurrNumElts / <NUM_LIT> ) ; SDValue Shift = DAG . getConstant ( CurrScalarSizeInBits , DL , NextVT ) ; SDValue HiZ = DAG . getSetCC ( DL , CurrVT , DAG . getBitcast ( CurrVT , Op0 ) , DAG . getBitcast ( CurrVT , Zero ) , <STR_LIT> ) ; HiZ = DAG . getBitcast ( NextVT , HiZ ) ; SDValue ResNext = Res = DAG . getBitcast ( NextVT , Res ) ; SDValue R0 = DAG . getNode ( <STR_LIT> , DL , NextVT , ResNext , Shift ) ; SDValue R1 = DAG . getNode ( <STR_LIT> , DL , NextVT , HiZ , Shift ) ; R1 = DAG . getNode ( <STR_LIT> , DL , NextVT , ResNext , R1 ) ; Res = DAG . getNode ( <STR_LIT> , DL ,


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , MODE_32BIT ,


<s> else if ( recog_memoized ( prev ) == CODE_FOR_block_branch_redirect ) need_block = <NUM_LIT> ; } if ( GET_CODE ( PATTERN ( jump ) ) == RETURN ) { if ( ! need_block ) return prev ; return emit_insn_before ( gen_block_branch_redirect ( const0_rtx ) , jump ) ; } dest = XEXP ( SET_SRC ( PATTERN ( jump ) ) , <NUM_LIT> ) ; if ( optimize && ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - addr + ( unsigned ) <NUM_LIT> > <NUM_LIT> + <NUM_LIT> ) ) { rtx_insn * scan ; unsigned attempt = <NUM_LIT> , used ; int jump_left = flag_expensive_optimizations + <NUM_LIT> ; for ( scan = jump ; ( scan = PREV_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( scan -> deleted ( ) ) continue ; code = GET_CODE ( scan ) ; if ( code == CODE_LABEL || code == JUMP_INSN ) break ; if ( code == INSN && GET_CODE ( PATTERN ( scan ) ) != USE && GET_CODE ( PATTERN ( scan ) ) != CLOBBER && get_attr_in_delay_slot ( scan ) == IN_DELAY_SLOT_YES ) { attempt &= ~ regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; break ; } } for ( used = dead = <NUM_LIT> , scan = JUMP_LABEL_AS_INSN ( jump ) ; ( scan = NEXT_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( scan -> deleted ( ) ) continue ; code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT> ) &


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; unsigned SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( Y . getOpcode ( ) == <STR_LIT> && Y . getOperand ( <NUM_LIT> ) == X && <STR_LIT> ( Y . getOperand ( <NUM_LIT> ) . getNode ( ) ) && X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { assert ( ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) && <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; EVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getNode ( <STR_LIT> , DL , BlendVT , X ) ; Y = DAG . getNode ( <STR_LIT> , DL , BlendVT , Y ) ; Mask = DAG . getNode ( <STR_LIT> , DL , BlendVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , BlendVT , Mask , Y , X ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask ) ; } } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 .


<s> bool isExtSymbol ( ) const { return Kind ==


<s> trackLivenessAfterRegAlloc ( const MachineFunction & MF


<s> void addDupAlignedMemory64or128Operands ( MCInst & Inst , unsigned N


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op .


<s> if ( optimize_size ) return <NUM_LIT> ; insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT>


<s> static int loongarch_zero_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT>


<s> const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( <STR_LIT> ) ; Align Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( <STR_LIT> ) ; Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = <STR_LIT> ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) . addImm ( <NUM_LIT> ) ; unsigned Opc = <STR_LIT>


<s> if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , CSKY_LR_REGNUM


<s> MVT getScalarShiftAmountTy ( const DataLayout &


<s> DebugLoc DL = MI . getDebugLoc ( ) ; Register Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Lane == <NUM_LIT> ) { unsigned Wt = Ws ; if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { Register Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( Lane ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return


<s> bool isExynosM1 ( ) const { return CPUString


<s> <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return true ; Parser . Lex ( ) ; int RegNum = TryParseRegister ( ) ; if ( RegNum == - <NUM_LIT> ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShifter ( ShiftTy , S ,


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; return *


<s> if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm (


<s> const MCSymbolRefExpr * Sym2 = MCSymbolRefExpr :: create ( BB2 -> getSymbol ( ) , * Ctx ) ; const MCBinaryExpr * Sub = MCBinaryExpr :: createSub ( Sym1 , Sym2 , * Ctx ) ; return MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( Kind


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool isIXAddr = usesIXAddr ( MI ) ; bool noImmForm = ! MI . isInlineAsm ( ) && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI -> getObjectOffset


<s> int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( decl == NULL || TARGET_THUMB ) return false ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_SHORT ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_LONG ; if ( call_type == CALL_LONG && ( flag_pic || ! TREE_ASM_WRITTEN ( decl ) ) ) return false ; if ( TARGET_INTERWORK && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) ) return false ; return


<s> minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; Value * Val , * LHS , * RHS ; if ( match ( V , m_Trunc ( m_Value ( Val ) ) ) ) { if ( cast < TruncInst > ( I ) -> getDestTy ( ) -> getIntegerBitWidth ( ) == MaxBitWidth ) return IsNarrowSequence < MaxBitWidth > ( Val , VL ) ; } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { return false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) != MaxBitWidth ) return false ; if ( match ( Val , m_Load ( m_Value ( ) ) ) ) { auto * Ld = cast < LoadInst > ( Val ) ; if ( ! LoadPairs . count ( Ld ) && ! OffsetLoads . count ( Ld ) ) return false ; VL . push_back (


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT ,


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB


<s> tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ; return


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . createTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <NUM_LIT> : { const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ScratchRegI32 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <STR_LIT> , ScratchRegI32 , Out ) ; break ; } case


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB ,


<s> LoadSDNode * Load = cast < LoadSDNode > ( CmpOp0 ) ; unsigned NumBits = Load -> getMemoryVT ( ) . getStoreSizeInBits ( ) ; if ( NumBits != <NUM_LIT> && NumBits != <NUM_LIT> ) return ; ConstantSDNode * Constant = cast < ConstantSDNode > ( CmpOp1 ) ; uint64_t Value = Constant -> getZExtValue ( ) ; uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Load -> getExtensionType ( ) == <STR_LIT> ) { int64_t SignedValue = Constant -> getSExtValue ( ) ; if ( uint64_t ( SignedValue ) + ( <NUM_LIT> << ( NumBits - <NUM_LIT> ) ) > Mask ) return ; if ( IsUnsigned ) Value &= Mask ; else if ( CCMask == <STR_LIT> || CCMask == <STR_LIT> ) Value &= Mask , IsUnsigned = true ; else if ( NumBits == <NUM_LIT> ) { if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ; else if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask


<s> abort ( ) ; } break ; } case TargetInstrInfo :: DBG_LABEL : case TargetInstrInfo :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case TargetInstrInfo :: IMPLICIT_DEF : case TargetInstrInfo :: DECLARE : case <STR_LIT> : break ; case <STR_LIT> : emitConstPoolInstruction ( MI ) ; break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT>


<s> op1 = crx_compare_op1 ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; ret = gen_rtx_COMPARE ( CCmode , op0 ,


<s> } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE -> getValue ( ) >= <NUM_LIT> && CE -> getValue


<s> Value * <ISA_LIT>IREmitter :: visitFNSTSW16r ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & Chains [ <NUM_LIT> ] , Chains . size ( ) ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; DebugLoc DL = St -> getDebugLoc ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) != <STR_LIT> || StVal . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; DebugLoc dl = StVal .


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail


<s> std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & TRI ] ( outliner :: Candidate & C ) { C . initLRU ( TRI ) ; } ) ; auto CantGuaranteeValueAcrossCall = [ ] ( outliner :: Candidate & C ) { LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . empty ( ) ) return outliner :: OutlinedFunction ( ) ; unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , DL


<s> } Options . setMacro ( ) ; Parser . Lex ( ) ; return false


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return *


<s> unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget -> hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ; Highs = DAG . getNode ( <STR_LIT> , dl , VT , Highs ,


<s> bool is16BitMode ( ) const { return getSTI ( ) . getFeatureBits


<s> case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; return ( ! EnableMinSize ) ? Helper . tryCombineMemCpyFamily ( MI , MaxLen ) : false ; } default : break ; } } if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; return false


<s> if ( ! MCE ) return false ; return <STR_LIT> ( ~ MCE -> getValue (


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> CTX . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> unsigned Align = DAG . getDataLayout ( ) . getPreferredAlignment ( GVar ) ; unsigned RequiredPadding = <NUM_LIT> - ( Size % <NUM_LIT> ) ; bool PaddingPossible = RequiredPadding == <NUM_LIT> || ( CDAInit && CDAInit -> isString ( ) ) ; if ( ! PaddingPossible || Align > <NUM_LIT> || Size > ConstpoolPromotionMaxSize || Size == <NUM_LIT> ) return SDValue ( ) ; unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext


<s> int i , len ; if ( count != <NUM_LIT> ) return NULL_RTX ; rp = get_hard_reg_initial_val ( Pmode , <NUM_LIT> ) ; if ( TARGET_64BIT || TARGET_NO_SPACE_REGS ) return rp ; saved_rp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( saved_rp , rp ) ; ins = copy_to_reg ( gen_rtx_AND ( Pmode , rp , MASK_RETURN_ADDR ) ) ; label = gen_label_rtx ( ) ; if ( TARGET_PA_20 ) { insns [ <NUM_LIT> ] = <NUM_LIT> ; insns [ <NUM_LIT> ] = - <NUM_LIT> ; len = <NUM_LIT> ; } else { insns [ <NUM_LIT> ] = <NUM_LIT> ; insns [ <NUM_LIT> ] = <NUM_LIT> ; insns [ <NUM_LIT> ] = <NUM_LIT> ; insns [ <NUM_LIT> ] = - <NUM_LIT> ; len = <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < len ; i ++ ) { rtx op0 = gen_rtx_MEM ( SImode , plus_constant ( Pmode , ins , i * <NUM_LIT> ) ) ; rtx op1 = GEN_INT ( insns [ i ] ) ; emit_cmp_and_jump_insns ( op0 , op1 , NE , NULL , SImode , <NUM_LIT> , label ) ; } emit_move_insn ( saved_rp , gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant (

Pmode , frameaddr , - <NUM_LIT> ) ) ) ) ;


<s> return __builtin_shuffle ( a , ( uint32x4_t ) { <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> struct loongarch_address_info addr ; int factor ; if ( ! loongarch_classify_address ( & addr , x , mode , false ) ) return <NUM_LIT> ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode


<s> CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == <NUM_LIT> && bytes [ i + <NUM_LIT> ] == bytes [ <NUM_LIT> ] && bytes [ i + <NUM_LIT> ] == <NUM_LIT> ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , bytes [ i ] == bytes [ <NUM_LIT> ] ) ; CHECK ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ( bytes [ i ] == <NUM_LIT> || bytes [ i ] == <NUM_LIT> ) && bytes [ i ] == bytes [ ( i + <NUM_LIT> ) % idx ] ) ; } while ( <NUM_LIT> ) ; if ( immtype == - <NUM_LIT> ) return - <NUM_LIT> ; if ( elementwidth ) * elementwidth = elsize ; if ( modconst ) { unsigned HOST_WIDE_INT imm = <NUM_LIT> ; if ( invmask != <NUM_LIT> ) for ( i = <NUM_LIT> ; i < idx ; i ++ ) bytes [ i ] ^= invmask ; if ( immtype


_mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return ( ( qword ) ( vec_xor ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_ushort ( b ) ) ,


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment *

DF , const MCAsmLayout & Layout ) const {


<s> SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Mask , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Val , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Val } ) ; Result = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Vec . getSimpleValueType ( )

, { HalfIdx , PackedElt , Vec } ) , <NUM_LIT> ) ;


<s> MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT>


<s> return __builtin_loongson_psubb_s ( s ,


<s> static __inline__ float __fabsf ( float x ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const llvm :: Function & ) const override { return &


<s> return Kind == k_VectorIndex && VectorIndex


<s> case <STR_LIT> : case <STR_LIT> : assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CC = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CC =


<s> return __builtin_mve_vcaddq_rot90v16qi ( __a ,


<s> return DAG . getTarget ( ) . shouldAssumeDSOLocal ( * Mod , GV ) && ! dyn_cast_or_null < GlobalIFunc > ( GV ) ; } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV ) ; } return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName

) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ;


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , STI , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS


<s> assert ( isalpha ( RegName [ <NUM_LIT> ] ) && isdigit ( RegName [ <NUM_LIT> ] ) ) ; O << ( RegName + <NUM_LIT> ) ; } else O << '%'


<s> FunctionPass * llvm :: create<ISA_LIT>ShortenInstPass (


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( )


<s> unsigned getAdrLabelOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> Triple TheTriple ( TT ) ; StackGrowsUp = true ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AlignDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ; HasDotTypeDotSizeDirective =


<s> return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind


<s> static bool IsFrameChange ( MachineInstr & MI ) { return MI . modifiesRegister ( <STR_LIT> , NULL ) || MI . modifiesRegister ( <STR_LIT>


<s> LoadSDNode * LoadA = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( <NUM_LIT> - I ) ) ; LoadSDNode * LoadB = cast < LoadSDNode > ( StoreA -> getValue


<s> <ISA_LIT>ProcFamilyEnum getProcFamily ( ) const { return


<s> if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MI -> setDesc ( TII -> get ( OppositeBranchOpcode ) ) ; BMI -> getOperand ( BMITargetOperand ) . setMBB ( DestBB ) ; MI -> getOperand ( TargetOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( * MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addMBB ( NextBB ) ; } Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br .


<s> const unsigned PtrBits = <NUM_LIT> ; if ( isa < MCTargetExpr > ( getMemOff ( ) ) || ( isConstantMemOff ( ) && isIntN ( PtrBits , getConstantMemOff ( ) ) ) ) return true ; MCValue Res ; bool IsReloc = getMemOff ( ) -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; return IsReloc && isIntN ( PtrBits , Res . getConstant


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) const { llvm_unreachable ( <STR_LIT> ) ; return SDValue ( )


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return RC -> hasSubClassEq ( MRI -> getRegClass ( Reg


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { X = N0 . getOperand ( <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == <NUM_LIT> ) return <NUM_LIT> ; if ( rs6000_cpu_attr != CPU_CELL ) return <NUM_LIT> ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return <NUM_LIT> ; return


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) +


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT ,


<s> if ( Parser . parseIntToken ( Offset , <STR_LIT> ) || parseEOL


<s> if ( TARGET_MICROMIPS ) fprintf ( asm_out_file , <STR_LIT> ) ; else fprintf ( asm_out_file , <STR_LIT> ) ; if ( ! flag_inhibit_size_directive ) { fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file


<s> auto ScalarOC = getScalarReductionOpcode ( VVPOpcode , IsMaskReduction ) ; return getNode ( ScalarOC , ResVT , { StartV , ReductionResV } ) ; } ; if ( ! scalarizeStartParam && StartV ) { assert ( hasReductionStartParam ( VVPOpcode ) ) ; return AttachStartValue ( getNode ( VVPOpcode , ResVT , { StartV , VectorV , Mask , AVL }


<s> bool hasFP ( const MachineFunction & MF ) const { return false


<s> x = avoid_constant_pool_reference ( x ) ; if ( UNARY_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values ) ; return simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; } if ( ARITHMETIC_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x


<s> unsigned GlobalBaseReg = getInstrInfo ( ) ->


<s> ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; AssemblerDialect = <NUM_LIT> ; SupportsDebugInformation =


<s> bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpeq ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c ,


<s> Kind = MCLOH_AdrpLdr ; Args . push_back ( L1 ) ; Args . push_back ( Candidate ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( L1 ) ) && <STR_LIT> ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( Candidate ) ) && <STR_LIT> ) ; ++ NumADRPToLDR ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << ( IsL2Add ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * L1 << '\n' << * L2 << '\n' << * Candidate << '\n' ) ; Kind = IsL2Add ? MCLOH_AdrpAddLdr : MCLOH_AdrpLdrGotLdr ; Args . push_back ( L1 ) ; Args . push_back ( L2 ) ; Args . push_back ( Candidate ) ; PotentialADROpportunities . remove ( L2 ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( L1 ) ) && <STR_LIT> ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( L2 ) ) && <STR_LIT> ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( Candidate ) ) && <STR_LIT> ) ; if ( Candidate -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) if ( ImmediateDefOpc == <STR_LIT> ) ++ NumADDToLDR ; else ++ NumLDRToLDR ; else if ( ImmediateDefOpc == <STR_LIT> ) ++ NumADDToLDRWithImm ; else ++ NumLDRToLDRWithImm ; } } else { if ( ImmediateDefOpc == <STR_LIT> ) continue ; else { DEBUG ( dbgs ( ) << <STR_LIT> << ( IsL2Add ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * L1 << '\n' << * L2 << '\n' << * Candidate << '\n' ) ; Kind = IsL2Add ? MCLOH_AdrpAddStr : MCLOH_AdrpLdrGotStr ; Args . push_back ( L1 ) ; Args . push_back ( L2 ) ; Args . push_back ( Candidate ) ; PotentialADROpportunities . remove ( L2 ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( L1 ) ) && <STR_LIT> ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert (


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm


<s> unsigned getMemBase ( ) const { assert ( ( Kind == k_Memory ) && <STR_LIT>


<s> auto * RHSC = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSC || RHSC -> getZExtValue ( ) != <NUM_LIT> || LHS -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> NewCC = <STR_LIT> ( <STR_LIT> ( LHS -> getConstantOperandVal ( <NUM_LIT> ) ) ) ; SDLoc DL ( N ) ; return getSETCC ( NewCC , LHS -> getOperand ( <NUM_LIT> ) ,


<s> unsigned <ISA_LIT>SEInstrInfo :: getAnalyzableBrOpc ( unsigned Opc ) const { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ; MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( ) - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildMaskLowPtrBits ( PtrTy ,


<s> static __inline int __attribute__ ( ( __always_inline__ ) ) _mm_cvtsi64_si32 (


<s> Value * <ISA_LIT>IREmitter :: visitMOVLHPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Binary |= getAddrModeSBit ( MI , TID ) ; unsigned NumDefs = TID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( TID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( TID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( TID . Opcode == <STR_LIT> ) || ( TID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary


<s> Instruction * InsertionPoint ; if ( isa < Instruction > ( OffsSecondOperand ) ) InsertionPoint = & cast < Instruction > ( OffsSecondOperand ) -> getParent ( ) -> back ( ) ; else InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( Instruction :: Mul , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * Product = BinaryOperator :: Create ( Instruction :: Mul , IncrementPerRound , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * NewIncrement = BinaryOperator :: Create ( Instruction :: Add , Phi , Product , <STR_LIT> , cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement ) -> back ( ) ) . getPrevNode ( ) ) ; Phi -> addIncoming ( StartIndex , Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; Phi -> addIncoming ( NewIncrement , Phi -> getIncomingBlock ( LoopIncrement ) ) ; Phi -> removeIncomingValue ( ( unsigned ) <NUM_LIT> ) ; Phi -> removeIncomingValue ( ( unsigned


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerFLT_ROUNDS_ ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue FPCR_64 = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) } ) ; Chain = FPCR_64 . getValue ( <NUM_LIT> ) ; SDValue FPCR_32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPCR_64 ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPCR_32 , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant (


<s> if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; return


<s> MVT EVT = VT . getVectorElementType ( ) ; SDValue Addr = Load -> getOperand ( <NUM_LIT> ) ; SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( Index

* EVT . getStoreSize ( ) , Addr . getSimpleValueType ( ) ) ) ;


<s> return spe_expand_stv_builtin ( CODE_FOR_spe_evstdwx , arglist ) ; case SPE_BUILTIN_EVSTWHEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhex , arglist ) ; case SPE_BUILTIN_EVSTWHOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhox , arglist ) ; case SPE_BUILTIN_EVSTWWEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwex , arglist ) ; case SPE_BUILTIN_EVSTWWOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwox , arglist ) ; case SPE_BUILTIN_EVSTDD : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdd , arglist ) ; case SPE_BUILTIN_EVSTDH : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdh , arglist ) ; case SPE_BUILTIN_EVSTDW : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdw , arglist ) ; case SPE_BUILTIN_EVSTWHE : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhe , arglist ) ; case SPE_BUILTIN_EVSTWHO : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwho , arglist ) ; case SPE_BUILTIN_EVSTWWE : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwe , arglist ) ; case SPE_BUILTIN_EVSTWWO : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwo , arglist ) ; case SPE_BUILTIN_MFSPEFSCR : icode = CODE_FOR_spe_mfspefscr ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ; case SPE_BUILTIN_MTSPEFSCR : icode = CODE_FOR_spe_mtspefscr ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) (


<s> SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false


<s> if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return <NUM_LIT> ; if ( GET_CODE ( x2 ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( x2 ) , 'I' ) ) return <NUM_LIT> ; return <NUM_LIT> ; } return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x


<s> if ( ! F . getSubtarget < <ISA_LIT>Subtarget > ( ) . balanceFPOps ( ) ) return false ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock ( MBB ) ; } return Changed


<s> EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ,


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering (


<s> return ( int16x4_t ) __builtin_neon_vmlav4hi ( __a ,


<s> static HOST_WIDE_INT aarch64_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD ) ; return


<s> dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB

, TII , MachineInstr :: FrameDestroy ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool IsSibCall = ! MF . getTarget ( ) . Options . GuaranteedTailCallOpt ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CallingConv :: ID CalleeCC = Info . CallConv ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , true ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; MIB . addImm ( <NUM_LIT> ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; int FPDiff = <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; if ( ! IsSibCall ) { unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( )


<s> Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec =


<s> IPI -> second . push_back ( UseIt ) ; Instruction * OldInstr = IPI -> first ; InsertPts [ NewPt ] = std :: move ( IPI -> second ) ; IPI = InsertPts . find


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op


<s> if ( TARGET_INTERLINK_COMPRESSED ) { if ( ! TARGET_COMPRESSION && mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) == <NUM_LIT> ) return true ; if ( TARGET_COMPRESSION && mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) == <NUM_LIT> ) return true ; } return false


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsADDiu ( int64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { GetInstSeqLs ( ( Imm + <NUM_LIT> ) & ~ <NUM_LIT> , RemSize


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> )


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p = strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \

putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> bool <ISA_LIT>InstrInfo :: isPredicable (


<s> if ( ! sh_need_epilogue_known ) { rtx epilogue ; start_sequence ( ) ; sh_expand_epilogue ( ) ; epilogue = gen_sequence (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << '\n' ) ; LLVM_DEBUG ( F . dump ( ) ) ; bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F . dump ( ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed


<s> void <ISA_LIT>AsmParser :: applyLVILoadHardeningMitigation ( MCInst & Inst , MCStreamer & Out ) { auto Opcode = Inst . getOpcode ( ) ; auto Flags = Inst . getFlags ( ) ; if ( ( Flags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { rtx tmp ; switch ( code ) { case LTGT : case UNEQ : return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED


<s> static bool CC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ; return


<s> inline Optional < unsigned > getSVEPredPatternFromNumElements ( unsigned MinNumElts ) { switch ( MinNumElts ) { default : return None ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return MinNumElts ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case


<s> void <ISA_LIT>CodeEmitter :: emitMiscInstruction ( const MachineInstr & MI ) { unsigned Opcode = MI . getDesc ( ) . Opcode ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( Opcode == <STR_LIT> ) { unsigned Imm = getMachineOpValue ( MI , <NUM_LIT> ) ; Binary &= ~ ( <NUM_LIT> >> <NUM_LIT> ) ; Binary |= ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Binary &= ~ ( <NUM_LIT> >> <NUM_LIT> ) ; Binary |= ( Imm &


<s> gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VMULESB : case ALTIVEC_BUILTIN_VMULESH : case ALTIVEC_BUILTIN_VMULEUB : case ALTIVEC_BUILTIN_VMULEUH : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , VEC_WIDEN_MULT_EVEN_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VMULOSB : case ALTIVEC_BUILTIN_VMULOSH : case ALTIVEC_BUILTIN_VMULOUB : case ALTIVEC_BUILTIN_VMULOUH : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , VEC_WIDEN_MULT_ODD_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case VSX_BUILTIN_DIV_V2DI : case VSX_BUILTIN_UDIV_V2DI : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , TRUNC_DIV_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case VSX_BUILTIN_XVDIVSP : case VSX_BUILTIN_XVDIVDP : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , RDIV_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VAND : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; lhs = gimple_call_lhs ( stmt ) ; gimple * g = gimple_build_assign ( lhs , BIT_AND_EXPR , arg0 , arg1 ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; return true ; } case ALTIVEC_BUILTIN_VANDC : { arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt ,


<s> if ( CFP -> isNullValue ( ) ) return fastMaterializeFloatZero ( CFP ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const APFloat Val = CFP -> getValueAPF ( ) ; bool Is64Bit = ( VT == <STR_LIT> ) ; int Imm = Is64Bit ? <STR_LIT> ( Val ) : <STR_LIT> ( Val ) ; if ( Imm != - <NUM_LIT> ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; return fastEmitInst_i ( Opc , TLI . getRegClassFor ( VT ) , Imm ) ; } if ( Subtarget -> isTargetMachO ( ) && TM . getCodeModel ( ) == CodeModel :: Large ) { unsigned Opc1 = Is64Bit ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc1 ) , TmpReg ) . addImm ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; return ResultReg ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT


<s> } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( invert_move ) { tmp = op_true ; op_true = op_false ; op_false = tmp ; } cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return <NUM_LIT>


<s> getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; Reserved . set ( <STR_LIT> , <STR_LIT> + <NUM_LIT> ) ; } const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( )

; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll ( __X


<s> ArrayRef < int > OrigMask = SVOp -> getMask ( ) ; int MaskStorage [ <NUM_LIT> ] = { OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] , OrigMask [ <NUM_LIT> ] } ; MutableArrayRef < int > Mask ( MaskStorage ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , OrigMask , Subtarget , DAG ) ) return ZExt ; auto isV1 = [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ; auto isV2 = [ ] ( int M ) { return M >= <NUM_LIT> ; } ; int NumV1Inputs = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , isV1 ) ; int NumV2Inputs = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , isV2 ) ; if ( NumV2Inputs == <NUM_LIT> ) return lowerV8I16SingleInputVectorShuffle ( DL , V1 , Mask , Subtarget , DAG ) ; assert ( NumV1Inputs > <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Rotate ; if ( NumV1Inputs + NumV2Inputs <= <NUM_LIT> ) return lowerV8I16BasicBlendVectorShuffle ( DL


) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + <NUM_LIT> ; else * cost = insn_default_latency


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags =


<s> static SDValue combineFMA ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { if ( SDValue NegVal = isFNEG ( V . getOperand ( <NUM_LIT> )


<s> case <STR_LIT> : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > <NUM_LIT> && ML -> getSubLoops ( ) . empty ( ) ) return Align ( <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize >


<s> if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) ) OpFlag = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubNoDynamic ( ) ) { OpFlag = <STR_LIT> ; } SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , OpFlag ) ; DebugLoc DL = Op . getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc ::


<s> static inline __ev64_opaque__ __internal_ev_mwhsmiaaw ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> if ( frame_pointer_needed ) { if ( fp_offset ) return gen_frame_mem ( DImode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD ) ) ; else return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ) ; } return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , fp_offset + cfun -> machine -> frame . saved_regs_size


<s> bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc , <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; return false ; } return Error ( ExtLoc , <STR_LIT> +


<s> VectorType * ShuffleVecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * ShuffleEltTy = ShuffleVecTy -> getVectorElementType ( ) ; unsigned ShuffleElemSize = DL . getTypeSizeInBits ( ShuffleEltTy ) ; unsigned WideInstSize ; if ( ! Subtarget . hasAVX ( ) || ( Factor != <NUM_LIT> && Factor != <NUM_LIT> ) ) return false ; if ( isa < LoadInst > ( Inst ) ) { WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> &&


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set (

MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> void <ISA_LIT>AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection (


<s> SDValue TargetCC = DAG . getTargetConstant ( get<ISA_LIT>CC ( CC ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , LHS , RHS , TargetCC } ; return DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue FNStSW = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TruncFPSW ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FNStSW , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue TruncSrl = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Srl ) ; assert ( Subtarget -> hasLAHFSAHF ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl


<s> if ( Subtarget . hasFp256 ( ) ) if ( SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ) return Res ; return SDValue ( )


<s> SDValue LHS1 = extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType


<s> if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , <STR_LIT> , INTVAL ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) , FALSE ) ; if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( &


<s> <ISA_LIT>Relocator :: Result thm_jump8 ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { Relocator :: DWord P = pReloc . place ( ) ; Relocator :: DWord A = helper_sign_extend ( ( pReloc . target ( ) & <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>ATTAsmParser :: isSrcOp ( <ISA_LIT>Operand & Op ) { unsigned basereg = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ; return ( Op . isMem ( ) && ( Op . Mem . SegReg == <NUM_LIT> || Op . Mem . SegReg == <STR_LIT> ) && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast < MCConstantExpr

> ( Op . Mem . Disp ) -> getValue ( ) == <NUM_LIT> && Op . Mem . BaseReg == basereg && Op . Mem . IndexReg == <NUM_LIT> ) ;


<s> MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO ,

MachineMemOperand :: MOStore , Size , <NUM_LIT> ) ;


<s> pextrh_u ( uint16x4_t s , int field ) { return __builtin_loongson_pextrh_u ( s ,


<s> MCAsmBackend * llvm :: createThumbBEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT ,


<s> if ( Name == <STR_LIT> ) { MappedKind = FK_Data_4 ; return true ; } return MCAsmBackend :: getFixupKind (


<s> static <ISA_LIT>Operand * CreateBarrier ( unsigned Val , SMLoc S , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> int Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator E = MBB -> end ( ) ; NextI != E && Count < kScanLimit ; ++ NextI ) { MachineInstr & MI = * NextI ; bool ZeroData ; int64_t Size , Offset ; if ( isMergeableStackTaggingInstruction ( MI , Offset , Size , ZeroData ) ) { if ( ZeroData != FirstZeroData ) break ; Instrs . emplace_back ( & MI , Offset , Size ) ; continue ; } if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) break ; if ( MI . mayLoadOrStore ( ) || MI . hasUnmodeledSideEffects ( ) ) break ; } MachineBasicBlock :: iterator InsertI = Instrs . back ( ) . MI ; InsertI ++ ; llvm :: stable_sort ( Instrs , [ ] ( const TagStoreInstr & Left , const TagStoreInstr & Right ) { return Left . Offset < Right . Offset ; } ) ; int64_t CurOffset = Instrs [ <NUM_LIT> ] . Offset ; for ( auto & Instr : Instrs ) { if ( CurOffset > Instr . Offset ) return NextI ; CurOffset = Instr . Offset + Instr . Size ; } TagStoreEdit TSE ( MBB , FirstZeroData ) ; Optional < int64_t > EndOffset ; for ( auto & Instr : Instrs ) { if ( EndOffset && * EndOffset != Instr . Offset ) { TSE . emitCode ( InsertI , TFI , false ) ; TSE . clear ( ) ; } TSE . addInstruction ( Instr ) ; EndOffset = Instr . Offset +


<s> static SDValue PerformTRUNCATECombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Avg = detectAVGPattern ( N -> getOperand ( <NUM_LIT> ) , N -> getValueType

( <NUM_LIT> ) , DAG , Subtarget , SDLoc ( N ) ) ;


<s> SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Mask = APInt :: getAllOnesValue ( BitWidth ) , Zeros , Ones ; DAG . ComputeMaskedBits ( Op0 , Mask , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 .


<s> if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; if ( TARGET_IAMCU ) return iamcu_alignment ( type , computed ) ; mode = TYPE_MODE ( strip_array_types ( type )


<s> if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT>


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = false ; WeakRefDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler =


<s> if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> rtx insv = d -> op0 ; HOST_WIDE_INT idx = - <NUM_LIT> ; for ( unsigned HOST_WIDE_INT i = <NUM_LIT> ; i < nelt ; i ++ ) { HOST_WIDE_INT elt ; if ( ! d -> perm [ i ] . is_constant ( & elt ) ) return false ; if ( elt == ( HOST_WIDE_INT ) i ) continue ; if ( idx != - <NUM_LIT> ) { idx = - <NUM_LIT> ; break ; } idx = i ; } if ( idx == - <NUM_LIT> ) { insv = d -> op1 ; for ( unsigned HOST_WIDE_INT i = <NUM_LIT> ; i < nelt ; i ++ ) { if ( d -> perm [ i ] . to_constant ( ) == ( HOST_WIDE_INT ) ( i + nelt ) ) continue ; if ( idx != - <NUM_LIT> ) return false ; idx = i ; } if ( idx == - <NUM_LIT> ) return false ; } if ( d -> testing_p ) return true ; gcc_assert ( idx != - <NUM_LIT> ) ; unsigned extractindex = d -> perm [ idx ] . to_constant ( ) ; rtx extractv = d -> op0 ; if ( extractindex >= nelt ) { extractv = d -> op1 ; extractindex -= nelt ; } gcc_assert ( extractindex < nelt ) ; emit_move_insn ( d -> target , insv ) ; insn_code icode = code_for_aarch64_simd_vec_copy_lane ( mode ) ; expand_operand ops [ <NUM_LIT> ] ; create_output_operand ( & ops [ <NUM_LIT> ] , d -> target , mode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , d -> target , mode ) ; create_integer_operand ( & ops [ <NUM_LIT> ] , <NUM_LIT> << idx ) ; create_input_operand ( & ops [ <NUM_LIT> ] , extractv ,


<s> auto * C0 = dyn_cast < Constant > ( Op0 ) ; auto * C1 = dyn_cast < Constant > ( Op1 ) ; auto * CI00 = C0 ? dyn_cast_or_null < ConstantInt > ( C0 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; auto * CI10 = C1 ? dyn_cast_or_null < ConstantInt > ( C1 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; if ( CI00 && CI10 ) { APInt V00 = CI00 -> getValue ( ) ; APInt V10 = CI10 -> getValue ( ) ; APInt Mask = APInt :: getLowBitsSet ( <NUM_LIT> , Length ) . shl ( Index ) ; V00 = V00 & ~ Mask ; V10 = V10 . zextOrTrunc ( Length ) . zextOrTrunc ( <NUM_LIT> ) . shl ( Index ) ; APInt Val = V00 | V10 ; Type * IntTy64 = Type :: getInt64Ty ( II . getContext ( ) ) ; Constant * Args [ ] = { ConstantInt :: get ( IntTy64 , Val . getZExtValue ( ) ) , UndefValue :: get ( IntTy64 ) } ; return ConstantVector :: get ( Args ) ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) { Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; Constant * CILength = ConstantInt :: get ( IntTy8 , Length , false ) ; Constant * CIIndex = ConstantInt :: get ( IntTy8 , Index ,


<s> return ( __m256d ) __builtin_ia32_permdf256_mask ( ( __v4df ) __X , __imm , (


<s> int offset ; if ( to == STACK_POINTER_REGNUM ) offset = sparc_compute_frame_size ( get_frame_size ( ) , crtl -> is_leaf ) ; else offset = <NUM_LIT> ; offset += SPARC_STACK_BIAS


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr


<s> if ( TM . getSubtargetImpl ( ) -> isDarwin ( ) ) return new <ISA_LIT>MachOTargetObjectFile ( ) ; return new TargetLoweringObjectFileELF (


<s> assert ( CPE && <STR_LIT> ) ; if ( -- CPE -> RefCount == <NUM_LIT> ) { RemoveDeadCPEMI ( CPEMI


<s> isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , MaskVT ) ; else MaskInReg = DAG . getNode ( <STR_LIT> , dl


<s> return tls_symbolic_operand_type ( x ) !=


<s> void <ISA_LIT>InstPrinter :: printBarrierOption ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; bool Valid ; StringRef Name ; if ( Opcode == <STR_LIT> ) Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; else Name = <STR_LIT> ( ) . toString ( Val , Valid


<s> if ( CS -> arg_size ( ) != CallerFn -> arg_size ( ) ) return false ; ImmutableCallSite :: arg_iterator CalleeArgIter = CS -> arg_begin ( ) ; ImmutableCallSite :: arg_iterator CalleeArgEnd = CS -> arg_end ( ) ; Function :: const_arg_iterator CallerArgIter = CallerFn -> arg_begin ( ) ; for ( ; CalleeArgIter != CalleeArgEnd ; ++ CalleeArgIter , ++ CallerArgIter ) { const Value * CalleeArg =


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel (

TT , JIT , RM ) , getEffective<ISA_LIT>CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) {


<s> unsigned imm = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return MCDisassembler ::


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = getFrameIndexOffset ( MF , FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . setDesc ( TII . getMemoryInstr ( MI . getOpcode ( ) , Offset


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>JTIPICJumpTableLabel ( unsigned uid ) const { const DataLayout & DL = getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid ; return OutContext . getOrCreateSymbol ( Name


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ( * I ) == <STR_LIT> ) break ; I -> eraseFromParent


<s> case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , <NUM_LIT> ) ; int Cost = <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast


<s> } unsigned PermMask = <NUM_LIT> , Imm = <NUM_LIT> ; unsigned ControlBitsNum = WidenedMask . size ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { Imm = ( WidenedMask [ i ] == SM_SentinelUndef ) ? <NUM_LIT> : WidenedMask [ i ] ; PermMask |= ( Imm % WidenedMask . size ( ) ) << ( i * ControlBitsNum ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , Ops [

<NUM_LIT> ] , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ;


<s> return new <ISA_LIT>AsmBackend ( T , MRI , STI . getTargetTriple ( ) , STI .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return &


<s> void DecodeVPERM2F128Mask ( unsigned Imm , SmallVectorImpl < unsigned > & ShuffleMask ) { return DecodeVPERM2F128Mask ( <STR_LIT> , Imm ,


<s> void <ISA_LIT>AsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) { if ( PromotedGlobals . count ( GV


<s> return parseAddress ( Operands , <STR_LIT> , <ISA_LIT>Operand ::