<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool HasFP = TFI -> hasFP ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! HasFP || ( needsStackRealignment ( MF ) && FrameIndex >= <NUM_LIT> ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; unsigned FrameReg = getFrameRegister ( MF ) ; if ( FrameIndex >= <NUM_LIT> ) { if ( hasBasePointer ( MF ) ) FrameReg = getBaseRegister ( ) ; else if ( needsStackRealignment ( MF ) ) FrameReg = <STR_LIT> ; } if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! Reg ) Reg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( Reg && <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( ( uint32_t ) Offset >> <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( Offset & <NUM_LIT> ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( Reg , false , false , true ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG


<s> bool abiUsesSoftFloat ( ) const { return


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMsa ( ) ; return


<s> for ( auto * Sym : UpdateOther ) copyLocalEntry ( Sym , Sym


<s> bool CanNegateL ; if ( ! isConjunctionDisjunctionTree ( O0 , CanNegateL , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; if ( ! isConjunctionDisjunctionTree ( O1 , CanNegateR , Depth + <NUM_LIT> ) ) return false ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL && ! CanNegateR ) return false ; CanNegate = CanNegateL && CanNegateR ; } else { bool NeedsNegOutL = O0 -> getOpcode ( ) == <STR_LIT> ; bool NeedsNegOutR = O1 -> getOpcode ( )


<s> return int_nregs ; } else { int align = ix86_function_arg_boundary ( mode , type ) / BITS_PER_WORD ; cum -> words = ( cum -> words + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; cum -> words += words ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT>

|| Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) {


<s> if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned RegNum = Tok . getIntVal ( ) ; if ( RegNum != <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * op = <STR_LIT> ( <STR_LIT> , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( op ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> RegisterTarget < Triple :: sparcv9 , true > Y


<s> bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg


<s> static DecodeStatus DecodeAddrMode7Operand ( MCInst & Inst , unsigned Val , uint64_t


<s> SDLoc dl ( N ) ; MVT VT = N -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ld = N -> getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( Ld ) ) { unsigned DestIndex = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) >> <NUM_LIT> ; Ld = NarrowVectorLoadToElement ( cast < LoadSDNode > ( Ld ) ,


<s> } else cr6_form_int = TREE_INT_CST_LOW ( cr6_form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; switch ( cr6_form_int ) { case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero ( target ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero_reverse ( target ) ) ; break ; case <NUM_LIT>


<s> case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB =


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ,


<s> __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmplt (


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI .


<s> static SDValue performSpliceCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return N ->


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> ,


<s> unsigned getMemBase ( ) const { assert ( Kind == k_Memory && <STR_LIT>


<s> if ( WidenedMask [ <NUM_LIT> ] == <NUM_LIT> && IsHighZero ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsLowZero ) && ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsHighZero ) && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask ,


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand (


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode


<s> return std :: make_unique < <ISA_LIT>WinCOFFObjectWriter


<s> static tree build_const_pointer ( tree t ) { return build_pointer_type ( build_qualified_type ( t ,


<s> unsigned CPELogAlign = getCPELogAlign ( * U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = ++ Water -> getIterator ( ) ; if ( NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockLogAlignment = NextBlock -> getLogAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size


<s> rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case E_V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask =


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR (


<s> unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( ! resolveTargetShuffleInputs ( peekThroughBitcasts ( Src ) , Ops , Mask , DAG ) ) return SDValue ( ) ; if ( Mask . size ( ) != NumSrcElts ) { if ( ( NumSrcElts % Mask . size ( ) ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ScaledMask ; int Scale = NumSrcElts / Mask . size ( ) ; scaleShuffleMask ( Scale , Mask , ScaledMask ) ; Mask = std :: move ( ScaledMask ) ; } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 (


<s> HiOffset = ( ImmOffset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; } else ExprOffset = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; TempInst . setLoc ( IDLoc ) ; const MCInstrDesc & Desc = getInstDesc ( Inst . getOpcode ( ) ) ; int16_t RegClassOp0 = Desc . OpInfo [ <NUM_LIT> ] . RegClass ; unsigned RegClassIDOp0 = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RegClassOp0 ) . getID ( ) ; bool IsGPR = ( RegClassIDOp0 == <STR_LIT> ) || ( RegClassIDOp0 == <STR_LIT> ) ; if ( isLoad && IsGPR && ( BaseRegNum != RegOpNum ) ) TmpRegNum = RegOpNum ; else { int AT = getATReg ( IDLoc ) ; if ( ! AT ) return ; TmpRegNum = getReg ( ( isGP64bit ( ) ) ? <STR_LIT> : <STR_LIT> , AT ) ; } TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectImmShifterOperand ( SDValue N , SDValue & BaseReg , SDValue & Opc , bool CheckProfitability ) { if ( DisableShifterOp ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Ops [ <NUM_LIT> ] ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg (


<s> if ( region . readBytes ( address , <NUM_LIT> , ( uint8_t * ) Bytes , NULL ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return MCDisassembler :: Fail ; } insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [

<NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) { emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) ) , operand_subword ( operands [ <NUM_LIT> ] , WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) , operand_subword ( operands [ <NUM_LIT> ] , ! WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; return true ; } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) operands [ <NUM_LIT> ] = spill_xfmode_rfmode_operand ( operands [ <NUM_LIT> ] , <NUM_LIT> , mode ) ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ) ; return true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GR_REGNO_P ( REGNO ( operands [ <NUM_LIT> ] ) ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx op1 = gen_rtx_REG ( TImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; op1 = gen_rtx_SUBREG ( mode , op1 , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = spill_xfmode_rfmode_operand ( op1 , <NUM_LIT> , mode ) ; } else { rtx in [ <NUM_LIT> ] ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) ; in [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; in [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operands [


rs6000_xcoff_output_toc_section_asm_op , NULL ) ;


<s> static SDValue buildMergeScalars ( SelectionDAG & DAG , SDLoc DL , EVT VT , SDValue Op0 , SDValue Op1 ) { if ( Op0 . isUndef ( ) ) { if ( Op1 . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> bool <ISA_LIT>BaseInstrInfo :: isCPSRDefined ( const MachineInstr & MI ) { for ( const auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT>

&& MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasAddiLoadFusion = false


<s> <ISA_LIT>PostLegalizerLoweringInfo ( bool OptSize , bool MinSize ) : CombinerInfo ( true , false , nullptr , true , OptSize , MinSize ) { if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) ) report_fatal_error (


<s> virtual const MandarinSubtarget * getSubtargetImpl


<s> const ConstantFP * FV = cast < ConstantFPSDNode > ( Node ) -> getConstantFPValue ( ) ; EVT DestType = Node -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = TLI . getDataLayout ( ) -> getABITypeAlignment


<s> if ( is_ms_hook ) { int i , filler_count = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; unsigned int filler_cc = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < filler_count ; i += <NUM_LIT> ) fprintf ( asm_out_file , ASM_LONG <STR_LIT> , filler_cc ) ; } SUBTARGET_ASM_UNWIND_INIT (


<s> if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is64BitVector ( ) ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is128BitVector ( ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( RegVT == Ins [ i ] . VT && <STR_LIT> ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ArgOffset = VA . getLocMemOffset ( ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint32_t BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; int FI = MFI -> CreateFixedObject ( ArgSize , ArgOffset + BEAlign , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue ArgValue ; <STR_LIT> ExtType = <STR_LIT> ; MVT MemVT = VA . getValVT


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target ,


<s> else { fnaddr = gen_sym2PIC ( fnaddr ) ; PUT_MODE ( fnaddr , Pmode ) ; } } if ( ! TARGET_PT_FIXED && ( ! is_sym || TARGET_INVALID_SYMBOLS ) && ( ! REG_P ( fnaddr ) || ! TARGET_REGISTER_P ( REGNO ( fnaddr ) ) ) ) { rtx tr = gen_reg_rtx ( PDImode ) ; emit_insn ( gen_ptabs ( tr , fnaddr ) ) ; fnaddr =


<s> return __builtin_mve_vaddvq_sv8hi ( __a )


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm (


<s> void rs6000_print_patchable_function_entry ( FILE * file , unsigned HOST_WIDE_INT patch_area_size , bool record_p ) { unsigned int flags = SECTION_WRITE | SECTION_RELRO ; if ( ! ( TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2 ) &&

HAVE_GAS_SECTION_LINK_ORDER ) flags |= SECTION_LINK_ORDER ;


<s> if ( Printer . TM . getTargetTriple ( ) . isOSDarwin ( ) ) return lowerSymbolOperandDarwin ( MO , Sym ) ; assert ( Printer . TM . getTargetTriple ( ) . isOSBinFormatELF (


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } return SDValue


<s> rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc -> vec_pairing


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E

; ++ I ) if ( * I == NextBB ) return true ;


<s> Mode = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true


<s> bool isTargetFTOL ( ) const { return Subtarget -> isTargetKnownWindowsMSVC ( ) && ! Subtarget ->


<s> { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } } ; return makeArrayRef (


<s> bool <ISA_LIT>ConstantIslands :: isOffsetInRange ( unsigned UserOffset , unsigned TrialOffset , unsigned


<s> unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & CP_PREFETCH_MEMORY


<s> unsigned NumOperands = MI . getNumOperands ( ) ; auto GetBlendDomains = [ & ] ( unsigned ImmWidth , bool Is256 ) { uint16_t validDomains = <NUM_LIT> ; if ( MI . getOperand ( NumOperands - <NUM_LIT> ) . isImm ( ) ) { unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! isInt < <NUM_LIT> > ( Addr . getOffset ( ) ) ) { unsigned TempReg = materialize32BitInt ( Addr . getOffset ( ) , & <STR_LIT> ) ; Register DestReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addReg ( Addr . getReg ( ) ) ; Addr . setReg ( DestReg ) ; Addr . setOffset (


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned RegNo , RegKind ; if ( ! matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , RegKind , S , E ) ) ; ResTy = MatchOperand_Success ; } else { ResTy = parseMEMOperand ( Operands ) ; } if ( ResTy != MatchOperand_Success


<s> if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . hasFP64 ( ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT>


<s> SmallVector < int , <NUM_LIT> > Mask ( Original . begin ( ) , Original . end ( ) ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; bool ForceV1Zero = false , ForceV2Zero = false ; unsigned BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( M == i ) continue ; if ( M == i + Size ) { BlendMask |= <NUM_LIT> << i ; continue ; } if ( Zeroable [ i ] ) { if ( V1IsZero ) { ForceV1Zero = true ; Mask [ i ] = i ; continue ; } if ( V2IsZero ) { ForceV2Zero = true ; BlendMask |= <NUM_LIT> << i ; Mask [ i ] = i + Size ; continue ; } } return SDValue ( ) ; } if ( ForceV1Zero ) V1 = getZeroVector ( VT , Subtarget , DAG , DL ) ; if ( ForceV2Zero ) V2 = getZeroVector ( VT , Subtarget , DAG , DL ) ; auto ScaleBlendMask = [ ] ( unsigned BlendMask , int Size , int Scale ) { unsigned ScaledMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Size ; ++ i ) if ( BlendMask & ( <NUM_LIT> << i ) ) for ( int j = <NUM_LIT> ; j != Scale ; ++ j ) ScaledMask |= <NUM_LIT> << ( i * Scale + j ) ; return ScaledMask ; } ; switch ( VT . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) { int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; BlendMask = ScaleBlendMask ( BlendMask , Mask . size ( ) , Scale ) ; MVT BlendVT = VT . getSizeInBits ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , BlendVT , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { int Scale = <NUM_LIT> / VT . getVectorNumElements ( ) ; BlendMask = ScaleBlendMask ( BlendMask , Mask . size ( ) , Scale ) ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> ,


<s> unsigned Opc = II -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; Register BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opc == <STR_LIT> ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; Register NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const <ISA_LIT>InstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TII -> copyPhysReg ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , NewDestReg , BasePtr

, MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ;


<s> static SDValue GetTLSADDR ( SelectionDAG & DAG , SDValue Chain , GlobalAddressSDNode * GA , SDValue * InFlag , const EVT PtrVT , unsigned ReturnReg , unsigned char OperandFlags ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType (

<NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ;


<s> if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT>


<s> case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT>


<s> SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case


<s> addrtype = crx_decompose_address ( addr , & address ) ; gcc_assert ( addrtype != CRX_INVALID ) ; if ( addrtype == CRX_ABSOLUTE ) cost += <NUM_LIT> ; if ( addrtype == CRX_POST_INC ) cost -= <NUM_LIT> ; if ( address . base ) cost ++ ; if ( address . index && address . scale == <NUM_LIT> ) cost += <NUM_LIT> ; if ( address . disp && ! INT_CST4 ( INTVAL ( address . disp ) ) ) cost += <NUM_LIT> ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr ,


<s> const MCExpr * Length ; if ( parseAddress ( Base , Disp , Index , Length , Regs , RegKind ) ) return MatchOperand_ParseFail ; if ( Index && MemKind != BDXMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveInsn ( DirectiveID . getLoc


<s> return new <ISA_LIT>PassConfig ( this


<s> void <ISA_LIT>AsmPrinter :: printPredicateOperand ( const MachineInstr * MI , int OpNum


<s> case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> )


<s> const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; unsigned FGR32RegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; unsigned AFGR64RegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; for ( const auto & I


<s> return __builtin_ia32_vcvtdq2ph256_mask ( ( __v8si ) __B , _mm_setzero_ph ( ) ,


<s> bool Thumb2ITBlock :: MoveCopyOutOfITBlock ( MachineInstr * MI , <STR_LIT> CC , <STR_LIT> OCC , RegisterSet & Defs , RegisterSet & Uses ) { if ( ! isCopy ( MI ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>ISelDag ( * this )


<s> basic_block * bbs = get_loop_body ( loop ) ; int nbbs = loop -> num_nodes ; int vec_cost = data -> cost [ vect_body ] , not_vec_cost = <NUM_LIT> ; int i , density_pct ; for ( i = <NUM_LIT> ; i < nbbs ; i ++ ) { basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs )


<s> while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) return false ; CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; if ( ! isSink ( V ) && ! isSource ( V ) ) { if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I -> operands ( ) ) { if ( ! AddLegalInst ( U ) ) return false ; } } } if ( isSource ( V ) || shouldPromote ( V ) ) { for ( Use & U : V -> uses ( ) ) { if ( ! AddLegalInst ( U . getUser ( ) ) ) return false ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * I : CurrentVisited ) I -> dump ( ) ; ) ; unsigned ToPromote = <NUM_LIT> ; for ( auto * V : CurrentVisited ) { if ( Sources . count (


<s> static bool shouldGuaranteeTCO ( CallingConv :: ID CC , bool GuaranteedTailCallOpt ) { return ( GuaranteedTailCallOpt && canGuaranteeTCO ( CC ) ) || CC

== CallingConv :: Tail || CC == CallingConv :: SwiftTail ;


<s> return SelectThumbAddrModeRI ( N , Base ,


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseOperand


<s> if ( OptIncDec && ( Disp . getImm ( ) == <NUM_LIT> || Disp . getImm ( ) == - <NUM_LIT> ) ) { bool IsINC = Disp . getImm ( ) == <NUM_LIT> ; unsigned NewOpcode = getINCDECFromLEA ( MI . getOpcode ( ) , IsINC ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) . addReg ( Base . getReg ( ) , RegState :: Implicit ) ; } else { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) ; } } else { unsigned NewOpcode = getADDriFromLEA ( MI . getOpcode ( ) , Disp ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) . addImm ( Disp . getImm ( ) ) . addReg ( Base . getReg ( ) , RegState :: Implicit ) ; } else { NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) , DestReg ) . addReg ( BaseReg ) . addImm ( Disp . getImm ( ) ) ; } } } else if ( BaseReg != <NUM_LIT> && IndexReg != <NUM_LIT> && Disp . getImm ( ) == <NUM_LIT> ) { return optLEAALU ( I , MBB ) ; } else return


<s> case AsmToken :: Integer : case AsmToken :: Minus : case AsmToken :: Plus : return ( getParser ( ) . parseExpression ( Res ) ) ; case AsmToken :: Percent : return parseRelocOperand ( Res ) ; case AsmToken :: LParen : return false ; } return true


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa . mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = OffsetA < OffsetB ? OffsetA :


<s> vld1_lane_s16 ( const int16_t * __a , int16x4_t __b , const int __c ) { return ( int16x4_t ) __builtin_neon_vld1_lanev4hi ( ( const __builtin_neon_hi * )


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; BestLEA = nullptr ; for ( auto DefMI : List ) { int64_t AddrDispShiftTemp = getAddrDispShift ( MI , MemOpNo , * DefMI , <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) ) continue ; if ( TII -> getRegClass ( Desc , MemOpNo + <STR_LIT> , TRI , * MF ) != MRI -> getRegClass ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; int DistTemp = calcInstrDist (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT ,


<s> if ( Operands . size ( ) == <NUM_LIT> && ( ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) != ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && ( ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) != ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) { Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( )


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL ,


<s> static void loongarch_save_restore_reg ( machine_mode mode , int

regno , HOST_WIDE_INT offset , loongarch_save_restore_fn fn ) {


<s> if ( ! BaseT :: areFunctionArgsABICompatible ( Caller , Callee , Args ) ) return false ; const TargetMachine & TM = getTLI (


<s> if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> static Value * UseTlsOffset ( IRBuilder < > & IRB , unsigned Offset ) { Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = <STR_LIT> ( M , <STR_LIT>


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> FOp = <STR_LIT> ; MOp = <STR_LIT> ; break ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ValOpIdx = <STR_LIT> ; unsigned VSrc = MI -> getOperand ( ValOpIdx ) . getReg ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { MachineOperand & Operand = MI -> getOperand ( i ) ; if ( Operand . isReg ( ) ) Operand . setIsKill ( false ) ; MIB . addOperand ( Operand ) ; } MachineInstr * FOpMI = MIB ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i


<s> SmallVector < int , <NUM_LIT> > DMask = getPSHUFShuffleMask ( D ) ; int NOffset = N . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; int VOffset = V . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; int WordMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { WordMask [ i + NOffset ] = Mask [ i ] + NOffset ; WordMask [ i + VOffset ] = VMask [ i ] + VOffset ; } int MappedMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) MappedMask [ i ] = <NUM_LIT> * DMask [ WordMask [ i ] / <NUM_LIT> ] + WordMask [ i ] % <NUM_LIT> ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( std :: equal ( std :: begin ( MappedMask ) , std :: end ( MappedMask ) , std :: begin ( UnpackLoMask ) ) || std :: equal ( std :: begin ( MappedMask ) , std :: end ( MappedMask ) , std :: begin ( UnpackHiMask ) ) ) { V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , D . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( V . getNode


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( TM . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( <STR_LIT> ) ; else Reserved . reset


<s> ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf (


<s> OutStreamer . AddBlankLine ( ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; OutStreamer . AddBlankLine ( ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT>


<s> switch ( CM ) { default : break ; case CodeModel :: Default : CM = RM == Reloc :: PIC_ ? CodeModel :: Small :


<s> int sh_loop_align ( rtx_insn * label ) { rtx_insn * next = label ; if ( ! optimize || optimize_size ) return <NUM_LIT> ; do next = next_nonnote_insn ( next ) ; while ( next && LABEL_P ( next ) ) ; if ( ! next || ! INSN_P ( next ) || recog_memoized ( next )

== CODE_FOR_consttable_2 ) return <NUM_LIT> ;


<s> SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) break ; SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TopPart , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue MulRHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( Mul , <NUM_LIT> ) ) ; } } return SelectCode ( N )


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; LLVM_FALLTHROUGH ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT>


<s> Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; } assert ( Opc && <STR_LIT> ) ; MFI . setStackID ( FI , StackID ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DebugLoc ( ) , get ( Opc )

) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ;


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; const std :: string & Fn =


<s> void emitRR ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { emitRX ( Opcode , Reg0 , MCOperand :: createReg ( Reg1 )


<s> int Reg = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int Base = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Reg ] ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; return MCDisassembler :: Success


<s> case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder


<s> if ( c == REG ) return <NUM_LIT> ; if ( c == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; return <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget -> ClassifyBlockAddressReference ( ) ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result =

DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> <ISA_LIT>StackTagging ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>StackTaggingPass ( * PassRegistry :: getPassRegistry


<s> JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Target - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) ; return Result ; } JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Target ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Target ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT>


<s> MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> return ( uint8x8_t ) __builtin_neon_vtstv8qi ( ( int8x8_t


<s> rtx Rb , Re ; rtx sp_adjust_insn ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { nds32_emit_stack_v3pop ( Rb , Re , GEN_INT ( <NUM_LIT> ) , GEN_INT ( sp_adjust ) ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - <NUM_LIT> * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn


<s> const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FixupKind ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> ,


<s> ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = (


<s> static void rs6000_print_builtin_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , <STR_LIT> , & rs6000_builtin_mask_names [ <NUM_LIT> ] ,

ARRAY_SIZE ( rs6000_builtin_mask_names ) ) ;


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT>


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> void <ISA_LIT>AsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo


<s> if ( STI . in<ISA_LIT>16Mode ( ) ) return llvm ::


<s> if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( <NUM_LIT> ) . integer_p ) icode = code_for_aarch64_pred_fnma ( e . vector_mode ( <NUM_LIT> ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLS , e . vector_mode ( <NUM_LIT> ) ) ; return e . use_pred_x_insn ( icode ) ; } insn_code icode = e . direct_optab_handler ( cond_fnma_optab


<s> return __builtin_aarch64_reduc_plus_scal_v2sf (


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler :: Success


<s> TPOff = LowerTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue HiDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc , LoDesc , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; ThreadBase = LowerTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else llvm_unreachable ( <STR_LIT> )


<s> bool hasPOPCNT ( ) const { return HasPOPCNT


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( CastOpc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , dl , VT , Op


<s> void <ISA_LIT>InstPrinter :: printPCRelTLSOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printPCRelOperand ( MI , OpNum , O ) ; if ( ( unsigned ) OpNum + <NUM_LIT> < MI -> getNumOperands ( ) ) { const MCOperand & MO = MI -> getOperand


<s> unsigned int precision = and_val . get_precision ( ) ; unsigned HOST_WIDE_INT mask = <NUM_LIT> ; for ( unsigned int shift = <NUM_LIT> ; shift < precision ; shift += <NUM_LIT> ) { if ( and_val == ~ mask && ( ior_val & mask ) == ior_val ) return shift ; mask <<= <NUM_LIT>


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ; O << <STR_LIT>


<s> assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; assert ( Kind == MCSymbolRefExpr :: VK_None || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_LO || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_HI ) ; OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) { OS <<


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 ; } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken ::


<s> int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getBuildVector ( <STR_LIT> , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DAG . getBuildVector ( <STR_LIT> , DL , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; else V = V1InUse ? V1 : V2 ; return DAG . getBitcast ( VT


<s> return new <ISA_LIT>SETargetLowering ( TM )


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction (


<s> if ( ! OPTION_SET_P ( rs6000_current_cmodel ) ) SET_CMODEL ( CMODEL_MEDIUM ) ; if ( ( rs6000_isa_flags_explicit & OPTION_MASK_MINIMAL_TOC ) != <NUM_LIT> ) { if ( OPTION_SET_P ( rs6000_current_cmodel ) && rs6000_current_cmodel != CMODEL_SMALL ) error ( <STR_LIT> ) ; if ( TARGET_MINIMAL_TOC ) SET_CMODEL ( CMODEL_SMALL ) ; else if ( TARGET_PCREL || ( PCREL_SUPPORTED_BY_OS && ( rs6000_isa_flags_explicit & OPTION_MASK_PCREL ) == <NUM_LIT> ) ) ; else SET_CMODEL ( CMODEL_SMALL ) ; } if ( rs6000_current_cmodel != CMODEL_SMALL ) { if ( ! OPTION_SET_P ( TARGET_NO_FP_IN_TOC ) ) TARGET_NO_FP_IN_TOC = rs6000_current_cmodel == CMODEL_MEDIUM ; if ( ! OPTION_SET_P ( TARGET_NO_SUM_IN_TOC ) ) TARGET_NO_SUM_IN_TOC = <NUM_LIT> ; } if ( TARGET_PLTSEQ && DEFAULT_ABI != ABI_ELFv2 ) { if ( OPTION_SET_P ( rs6000_pltseq ) ) warning ( <NUM_LIT> , <STR_LIT> , <STR_LIT> ) ; rs6000_pltseq =


<s> <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) { initAsmInfo (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ST -> hasNEON ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> return <NUM_LIT> - HasFP ; } case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return <NUM_LIT> - HasFP - ( STI . isR9Reserved


<s> static StructReturnType argsAreStructReturn ( ArrayRef < <STR_LIT> > Ins , bool IsMCU ) { if ( Ins . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) || IsMCU )


<s> char symbol_name [ <NUM_LIT> ] ; total_n_vectors = nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < total_n_vectors ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , i ) ; fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < total_n_vectors ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , i ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file ,


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( TheTriple


<s> return ( __m128 ) __builtin_ia32_vbroadcastss_ps ( ( __v4sf


<s> gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return ( INTEGRAL_TYPE_P ( lhs_type ) && INTEGRAL_TYPE_P ( rhs_type )

&& TYPE_PRECISION ( lhs_type ) < TYPE_PRECISION ( rhs_type ) ) ;


<s> NeedsIndirectEncoding = true ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; CommentString = <STR_LIT> ; SetDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; UsedDirective = <STR_LIT> ; WeakDefDirective = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; HiddenDirective = <STR_LIT> ; ProtectedDirective = <STR_LIT> ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { JumpTableSpecialLabelPrefix = <STR_LIT> ; } SupportsDebugInformation = true ; NeedsSet = true ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection = <STR_LIT> ; DwarfMacInfoSection = <STR_LIT> ; SupportsExceptionHandling = true ; GlobalEHDirective = <STR_LIT> ; SupportsWeakOmittedEHFrame = false ; AbsoluteEHSectionOffsets = false ; DwarfEHFrameSection = <STR_LIT> ; DwarfExceptionSection =


<s> bool <ISA_LIT>Subtarget :: supportsAddressTopByteIgnored ( ) const { if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isDriverKit ( ) )


<s> case <STR_LIT> : Conv = DAG . getNode ( IsSigned ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( IsSigned || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Conv = DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> ,


<s> uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) !=


<s> uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ;


<s> if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = & *


<s> const struct d_target_info_spec handlers [ ] = { { <STR_LIT> , pa_d_handle_target_float_abi } , { <STR_LIT> , pa_d_handle_target_object_format } , {


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; bool IsFadd = N -> getOpcode ( ) == <STR_LIT> ; auto HorizOpcode = IsFadd ? <STR_LIT> : <STR_LIT> ; assert ( ( IsFadd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) &&

isHorizontalBinOp ( LHS , RHS , IsFadd ) && shouldUseHorizontalOp ( LHS == RHS , DAG , Subtarget ) ) return DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> return MOP . isReg ( ) && MOP . isDef ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , DefReg ) ; } ) ; if ( ! Fn ( I , isDef )


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . has<ISA_LIT>64r6 ( ) ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; unsigned Opc = invertFPCondCodeUser ( CC


<s> static SDValue LowerMINMAX ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntBinary ( Op , DAG ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ; return SDValue ( )


<s> if ( I -> isDeclaration ( ) ) continue ; if ( EmitSpecialLLVMGlobal ( I ) ) continue ; std :: string name = Mang -> getValueName ( I ) ; Constant * C = I -> getInitializer ( ) ; unsigned Align = TD -> getPreferredAlignmentLog ( I ) ; bool bCustomSegment = false ; switch ( I -> getLinkage ( ) ) { case GlobalValue :: CommonLinkage : case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: AppendingLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: DLLExportLinkage : DLLExportedGVs . insert ( name ) ; case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << <STR_LIT> ; case GlobalValue :: InternalLinkage : SwitchToSection ( TAI -> getDataSection ( ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ! bCustomSegment ) EmitAlignment ( Align , I ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) O << name << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> << I -> getName ( ) ; O << '\n' ; EmitGlobalConstant ( C ) ; if ( bCustomSegment ) O << name << <STR_LIT> ; } if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) ) { SwitchToDataSection ( <STR_LIT> ) ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> ; } for ( StringSet < > :: iterator i = DLLExportedGVs . begin ( ) , e =


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT>


<s> Type * FieldTys [ ] = { EHLinkRegistrationTy -> getPointerTo ( <NUM_LIT> ) , Type :: getInt8PtrTy ( Context ) } ; EHLinkRegistrationTy -> setBody ( FieldTys


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: parseIdentifier ( ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; SMLoc End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res , * RHS = nullptr ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( Lexer . getKind ( ) != AsmToken :: Identifier ) return nullptr ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return nullptr ; if ( Identifier . equals_lower ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; else if ( Identifier . equals_lower ( <STR_LIT> ) ) Kind =


<s> bool isFloatingPoint_64 ( InstType InstTy , unsigned OpSize ) const { if ( InstTy == InstType :: FloatingPoint && OpSize == <NUM_LIT> )


<s> use_sse = true ; if ( mode == HFmode ) vmode = V8HFmode ; } else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } dst = operands [ <NUM_LIT> ] ; src = operands [ <NUM_LIT> ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( use_sse ) { rtx mask , use , clob ; mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode || mode == TFmode ) par = gen_rtvec ( <NUM_LIT> , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( <NUM_LIT> , set , use , clob ) ; } } else { rtx clob ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( <NUM_LIT> ,


<s> if ( auto * MemN = dyn_cast < MemSDNode > ( Op . getNode ( ) ) ) return MemN -> getBasePtr ( ) ; switch ( Op -> getOpcode ( ) ) { case <STR_LIT>


<s> int32_t d32 ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; insn -> displacementOffset = insn -> readerCursor - insn -> startLocation ; switch ( insn -> eaDisplacement ) { case EA_DISP_NONE : break ; case EA_DISP_8 : if ( consume ( insn , d8 ) ) return - <NUM_LIT> ; insn -> displacement = d8 ; break ; case EA_DISP_16 : if ( consume ( insn , d16 ) ) return - <NUM_LIT> ; insn -> displacement = d16 ; break ; case


<s> return ( int8x16_t ) __builtin_aarch64_srshr_nv16qi (


<s> Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints


<s> LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; if ( IsTailCall ) { assert ( ! Flags . isByVal ( ) && <STR_LIT> ) ; Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( <NUM_LIT> ) ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) . getReg ( <NUM_LIT> ) ; auto OffsetReg = MIRBuilder . buildConstant ( s64 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg ,


<s> rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } return ; } case llvm :: ELF :: R_<ISA_LIT>_ABS16 : case llvm :: ELF :: R_<ISA_LIT>_ABS12 : case llvm :: ELF :: R_<ISA_LIT>_THM_ABS5 : case llvm :: ELF :: R_<ISA_LIT>_ABS8 : case llvm :: ELF :: R_<ISA_LIT>_BASE_ABS : case llvm :: ELF :: R_<ISA_LIT>_MOVW_ABS_NC : case llvm :: ELF :: R_<ISA_LIT>_MOVT_ABS : case llvm :: ELF :: R_<ISA_LIT>_THM_MOVW_ABS_NC : case llvm :: ELF :: R_<ISA_LIT>_THM_MOVT_ABS : { if ( config ( ) . isCodeIndep ( ) ) { error ( diag :: non_pic_relocation ) << getName ( pReloc . type ( ) ) << pReloc . symInfo ( ) -> name ( ) ; } return ; } case llvm :: ELF :: R_<ISA_LIT>_GOTOFF32 : case llvm :: ELF :: R_<ISA_LIT>_GOTOFF12 : { return ; } case llvm :: ELF :: R_<ISA_LIT>_TARGET2 : pReloc . setType ( llvm :: ELF :: R_<ISA_LIT>_GOT_PREL ) ; case llvm :: ELF :: R_<ISA_LIT>_GOT_BREL : case llvm :: ELF :: R_<ISA_LIT>_GOT_PREL : { if ( rsym -> reserved ( ) & ReserveGOT )


<s> unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , CallSeqStart , dl , SPDiff , isTailCall , isPatchPoint , hasNest , RegsToPass , Ops , NodeTys , CS , Subtarget ) ; if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! isPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) CallOpc = <STR_LIT> ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops , dl , true


<s> bool ShufpdMask = true ; bool CommutableMask = true ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef || ZeroLane [ i & <NUM_LIT> ] ) continue ; if ( Mask [ i ] < <NUM_LIT> ) return false ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i

] > Val + <NUM_LIT> ) ShufpdMask = false ;


<s> return ( uint16x4_t ) __builtin_neon_vcgev4hi (


<s> Function * DMB = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Constant * CDomain = Builder . getInt32 ( Domain


<s> tmp = plus_constant ( frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; MEM_NOTRAP_P ( tmp ) = <NUM_LIT> ; set_mem_alias_set ( tmp , rs6000_sr_alias_set ) ; emit_move_insn ( tmp , operands [ <NUM_LIT> ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM )


<s> TRI = STI -> getRegisterInfo ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isAIXABI ( ) ) { assert ( ! Subtarget . hasAltivec ( ) && <STR_LIT> ) ; return TM . is<ISA_LIT>64 ( ) ? CSR_AIX64_RegMask : CSR_AIX32_RegMask ; } if ( CC == CallingConv ::


<s> } } ; if ( ShiftImm >= RetVT . getSizeInBits ( ) ) return <NUM_LIT> ; const TargetRegisterClass * RC ; unsigned Opc ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; } unsigned ResultReg = fastEmitInst_rri ( Opc , RC , LHSReg , LHSIsKill , RHSReg , RHSIsKill , <STR_LIT> ( <STR_LIT> , ShiftImm ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: protectRegisterSpill ( unsigned Reg , const MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; const TargetRegisterClass * RC = TRI -> isPhysicalRegister ( Reg ) ? TRI -> getMinimalPhysRegClass ( Reg ) : MRI . getRegClass ( Reg ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || RC -> hasSuperClassEq ( & <STR_LIT> ) || RC -> hasSuperClassEq ( & <STR_LIT> ) || RC -> hasSuperClassEq ( &

<STR_LIT> ) ) return MF -> protectSpills ( ) ;


<s> rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( VOIDmode , vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( VOIDmode , reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec (


<s> bool RHSSeenZero = false ; bool RHSOk = canChangeToInt ( RHS , RHSSeenZero , Subtarget ) ; if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF


<s> res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT>


<s> SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VTSize > InVTSize ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( )


<s> if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; break ; case <STR_LIT> : case


<s> if ( ! decl || TREE_CODE ( fntype ) != FUNCTION_TYPE ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } * no_add_attrs |= cmse_func_args_or_return_in_stack ( NULL , name , fntype ) ; if ( * no_add_attrs ) return NULL_TREE ; type = TREE_TYPE ( decl ) ; type = build_distinct_type_copy ( type ) ; TREE_TYPE ( decl ) = type ; fntype = type ; while ( TREE_CODE ( fntype ) != FUNCTION_TYPE ) { type =


<s> SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] =


<s> return ( __m128i ) __builtin_ia32_pmovzxbq128_mask ( ( __v16qi ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOffsetOfOperator ( ) { const AsmToken & Tok = Parser . getTok ( ) ; SMLoc OffsetOfLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * Val ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) )


<s> Value * StartIndex = BinaryOperator :: Create ( ( Instruction :: BinaryOps ) Opcode , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * Product = BinaryOperator :: Create ( ( Instruction :: BinaryOps ) Opcode , IncrementPerRound , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * NewIncrement = BinaryOperator :: Create ( Instruction :: Add , Phi , Product , <STR_LIT> , cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement ) -> back ( ) ) . getPrevNode ( ) ) ; Phi -> addIncoming ( StartIndex , Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; Phi -> addIncoming ( NewIncrement , Phi -> getIncomingBlock ( LoopIncrement ) ) ; Phi -> removeIncomingValue ( ( unsigned ) <NUM_LIT> ) ; Phi -> removeIncomingValue ( ( unsigned )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHNop ( SMLoc


( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , & ShufMask2 [ <NUM_LIT> ] ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ; } return SDValue (


<s> BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg (

Reg , RegState :: Kill ) , FrameIndex ) ;