<s> auto * CCValid = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * CCMask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValid || ! CCMask ) return SDValue ( ) ; int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue CCReg = N -> getOperand ( <NUM_LIT> ) ; if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getConstant ( CCMaskVal ,


<s> return ( __m128d ) __builtin_ia32_cmpneqpd ( ( __v2df ) __A ,


<s> MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = ( NEONRegSpacing ) TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState (


<s> case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( <NUM_LIT> , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back


<s> unsigned OffImm = Opc . getImm ( ) ; return <STR_LIT> ( OffImm )


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm8Operand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum


<s> if ( ExtIdxVal != <NUM_LIT> ) { int VecNumElts = OpVT . getVectorNumElements ( ) ; int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( VecNumElts ) ; for ( int i = <NUM_LIT> ; i != VecNumElts ; ++ i ) Mask [ i ] = i ; for ( int i = <NUM_LIT> ; i != SubVecNumElts ; ++ i ) Mask [ i + IdxVal ] = i + ExtIdxVal + VecNumElts ; return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast


<s> } for ( i = <NUM_LIT> ; i < sr -> epilogue_count ; ++ i ) pop ( sr ) ; sr -> epilogue_count = <NUM_LIT> ; sr -> epilogue_start = UNW_WHEN_NEVER ; if ( ! body ) push ( sr ) ; sr -> region_start += sr -> region_len ; sr -> region_len = rlen ; sr -> in_body = body ; if ( ! body )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2ShifterOperandReg ( SDValue N , SDValue & BaseReg , SDValue & Opc ) { if ( DisableShifterOp ) return false ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) ) ; return


<s> if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexM7 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment =


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrSize ) ) ; unsigned NewList = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( NewList , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo

( ) , MachineMemOperand :: MOStore , PtrSize , PtrSize ) ) ;


<s> } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONDataInsn = Insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } uint32_t NEONCryptoInsn = Insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } uint32_t NEONv8Insn = Insn32 ; NEONv8Insn &= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8NEON32 , MI , NEONv8Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Result = decodeInstruction ( DecoderTableThumb2CoProc32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail


<s> void <ISA_LIT>InstrInfo :: expandLOCPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned HighOpcode ) const { Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode = isHighReg ( Reg ) ? HighOpcode : LowOpcode ; MI . setDesc ( get ( Opcode )


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) ,


<s> return create ( VK_<ISA_LIT>_LO , Expr


<s> static DecodeStatus DecodeGR128BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) ,

<NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> if ( ix86_expand_sse_fp_minmax ( operands [ <NUM_LIT> ] , code , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return true ; cmp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , code , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ix86_expand_sse_movcc ( operands [ <NUM_LIT> ] , cmp , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true


<s> const MCOperand & Op1 = MI -> getOperand ( OpNum ) ; const MCOperand & Op2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Op1 . getReg ( ) ) ; unsigned Offset = Op2 . getImm ( ) ; if ( Offset ) { O << <STR_LIT> << Offset


<s> return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE


<s> case MODE_VECTOR_FLOAT : if ( ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) || ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) || ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) || ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) || ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) ) units = GET_MODE_SIZE ( mode ) ; } return COSTS_N_INSNS ( CEIL ( GET_MODE_SIZE (


<s> return new <ISA_LIT>AsmBackend ( T , MRI , STI . getTargetTriple ( ) , STI . getCPU


<s> if ( isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) )


<s> if ( IntOp != <STR_LIT> ) return SDValue ( ) ; assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; SDValue ExitBlock = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , Elements , ExitBlock } ; SDValue Res = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( Int . getValue ( <NUM_LIT> ) , Int . getOperand ( <NUM_LIT> ) ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerShift ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl


, prefer_vector_width_type , ix86_move_max , ix86_store_max , true , true ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerWin64_i128OP ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget . isTargetWin64 ( ) && <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType ::


<s> } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % <NUM_LIT> == <NUM_LIT> ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) || (

TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) ) return true ;


<s> SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IMask ,


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == <STR_LIT> ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , this , false , dl ) ; return ; } MachineInstr * MI = MBB . getParent (


<s> if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . isELFv2ABI ( ) ) { <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( <NUM_LIT> ) ; } if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is<ISA_LIT>64 ( ) || ! isPositionIndependent ( ) ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; if ( M . getPICLevel ( ) == PICLevel :: SmallPIC ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCSymbol * CurrentPos = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HasI64In ) { SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InLo , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InHi , Chain . getValue ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . append ( Op -> op_begin ( ) + HasChainIn + <NUM_LIT> , Op -> op_end ( ) ) ; Ops . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } else { Ops . push_back ( Chain ) ; Ops . append ( Op -> op_begin ( ) +


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target (


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_mask ( ( __v16qi ) __A , ( __v64qi ) _mm512_undefined_si512 ( ) , (


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ; MachineInstrBuilder DstPtr


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; return TargetLowering :: getInlineAsmMemConstraint


<s> return __builtin_aarch64_ld1v4si ( ( const __builtin_aarch64_simd_si * ) a


<s> int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ; } return Offset


<s> Value * M , * N , * Ptr , * Stride , * Tile ; if ( IsTileLoad ) match ( TileLoadStore , m_Intrinsic < <STR_LIT> > ( m_Value ( M ) , m_Value ( N ) , m_Value ( Ptr ) , m_Value ( Stride ) ) ) ; else match ( TileLoadStore , m_Intrinsic < <STR_LIT> > ( m_Value ( M ) , m_Value ( N ) , m_Value ( Ptr ) , m_Value ( Stride ) , m_Value ( Tile ) ) ) ; Instruction * InsertI = TileLoadStore ; IRBuilder < > PreBuilder ( TileLoadStore ) ; PreBuilder . SetInsertPoint ( TileLoadStore ) ; Value * NDWord = PreBuilder . CreateLShr ( N , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; Value * StrideDWord = PreBuilder . CreateLShr ( Stride , PreBuilder . getInt64 ( <NUM_LIT> ) ) ; BasicBlock * Start = InsertI -> getParent ( ) ; BasicBlock * End = SplitBlock ( InsertI -> getParent ( ) , InsertI , & DTU , LI , nullptr , <STR_LIT> ) ; IRBuilder < > Builder ( TileLoadStore ) ; Value * ResVec = createTileLoadStoreLoops < IsTileLoad > ( Start , End , Builder , M , NDWord , Ptr , StrideDWord , IsTileLoad ? nullptr : Tile ) ; if ( IsTileLoad ) { Builder . SetInsertPoint ( End -> getFirstNonPHI ( ) ) ; Value * ResAMX = Builder . CreateBitCast ( ResVec , Type :: get<ISA_LIT>_AMXTy ( Builder . getContext ( ) ) ) ; for ( auto UI = TileLoadStore -> use_begin ( ) , UE = TileLoadStore -> use_end ( ) ; UI != UE ; ) { Instruction * I = cast < Instruction > ( ( UI ++ ) -> getUser ( ) ) ; Value * Vec ; if ( match ( I , m_BitCast ( m_Value


<s> return getPCRelEncoding ( MI , OpNum , Fixups ,


<s> static enum mips_shadow_set mips_use_shadow_register_set ( tree type ) { tree attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; tree args ; if ( attr == NULL ) return SHADOW_SET_NO ; args = TREE_VALUE ( attr ) ; if ( args == NULL


<s> SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , & Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , & Flags ) ; } ExtraSteps = <NUM_LIT>


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return


<s> assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; warnIfNoMacro ( IDLoc ) ; unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; bool IsLargeOffset = ! ( isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) && isInt < <NUM_LIT> > ( OffsetValue ) ) ; if ( IsLargeOffset ) { if ( loadImmediate ( OffsetValue , ATReg , SrcReg , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Out , STI ) ) return true ; } int64_t FirstOffset = IsLargeOffset ? <NUM_LIT> : OffsetValue ; int64_t SecondOffset = IsLargeOffset ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; if ( isLittle ( ) ) std :: swap ( FirstOffset , SecondOffset ) ; unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg ; unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg ; unsigned LbuSrcReg = IsLargeOffset ?


<s> if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) ->

required_extensions & ~ required_extensions ) == <NUM_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int Size ; if ( Desc . getSize ( ) == <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) Size = Desc . getSize ( ) ; else llvm_unreachable ( <STR_LIT> ) ; uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; if ( isThumb ( ) && Size == <NUM_LIT> ) { EmitConstant ( Binary >> <NUM_LIT> , <NUM_LIT> , OS ) ; EmitConstant ( Binary & <NUM_LIT> , <NUM_LIT> , OS ) ; } else EmitConstant ( Binary


<s> uint64_t MulAmt2 = <NUM_LIT> ; if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } SDLoc DL ( N ) ; SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL ,


<s> MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { signed Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand


<s> SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 .


<s> case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case


<s> static rtx loongarch_got_load_tls_ie ( rtx dest , rtx sym ) { return gen_got_load_tls_ie ( Pmode ,


<s> if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> )


<s> <ISA_LIT>SLSHardening ( ) : MachineFunctionPass (


<s> } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI


<s> if ( RegIdx != array_lengthof ( GPRArgRegs ) ) ArgRegBegin = std :: min ( ArgRegBegin , ( unsigned ) GPRArgRegs [ RegIdx ] ) ; } unsigned TotalArgRegsSaveSize = <NUM_LIT> * ( <STR_LIT> - ArgRegBegin ) ; AFI -> setArgRegsSaveSize ( TotalArgRegsSaveSize ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ VA . getValNo ( ) ] . isOrigArg ( ) ) { std :: advance ( CurOrigArg , Ins [ VA . getValNo ( ) ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ VA . getValNo ( ) ] . getOrigArgIndex ( ) ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( )


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI )


<s> tree f_next_gp , f_next_gp_limit , f_next_cop , f_next_stack ; tree next_gp , next_gp_limit , next_cop , next_stack ; tree t , u ; int ns ; ns = cfun -> machine -> arg_regs_to_save ; f_next_gp = TYPE_FIELDS ( va_list_type_node ) ; f_next_gp_limit = DECL_CHAIN ( f_next_gp ) ; f_next_cop = DECL_CHAIN ( f_next_gp_limit ) ; f_next_stack = DECL_CHAIN ( f_next_cop ) ; next_gp = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_gp ) , valist , f_next_gp , NULL_TREE ) ; next_gp_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_gp_limit ) , valist , f_next_gp_limit , NULL_TREE ) ; next_cop = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_cop ) , valist , f_next_cop , NULL_TREE ) ; next_stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_gp , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = fold_build_pointer_plus_hwi ( u , <NUM_LIT> * ns ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_gp_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = fold_build_pointer_plus_hwi ( u , <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_cop , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , nextarg ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_stack , u


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_adds_pu8 ( __m64 __m1 , __m64 __m2 ) { __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __m1 ) ; b = ( __vector unsigned char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c


<s> getVectorInstrCost ( unsigned Opcode , Type * Val , unsigned Index ) { if ( Opcode == Instruction :: InsertElement && Val -> getScalarType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return ( ( Index % <NUM_LIT> == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ExtractElement ) { int Cost = ( ( Val -> getScalarSizeInBits ( ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( Index == <NUM_LIT> && Val -> getScalarType ( ) -> isIntegerTy ( ) ) Cost += <NUM_LIT> ; return Cost


<s> unsigned int flags = <NUM_LIT> ; if ( lookup_attribute ( <STR_LIT> , attributes ) != NULL ) flags |= MASK_MIPS16


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_es ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Z ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Zy ; return TargetLowering :: getInlineAsmMemConstraint (


<s> if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! TLI . expandABS ( N , res , DAG ) ) return SDValue


<s> uint64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( ! foldOffsetIntoAddress ( Val , AM ) ) return false ; break ; } case <STR_LIT> : if ( ! matchWrapper ( N , AM


<s> Streamer . visitUsedExpr ( * getSubExpr (


<s> if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode ) return ( ( regno - GP_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == <NUM_LIT> || ( MIN_FPRS_PER_FMT == <NUM_LIT>


<s> assert ( NumOps >= <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned RegClass = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn )


<s> bool <ISA_LIT>DAGToDAGISel :: isMaskZeroExtended ( SDNode * N ) const { if ( N -> getOpcode ( ) == <STR_LIT> ) return isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) || isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) ; return isLegalMaskCompare ( N


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF


<s> aarch_ra_sign_scope = AARCH_FUNCTION_NONE ; aarch_enable_bti = <NUM_LIT> ; if ( rest ) { error ( <STR_LIT> , rest , str ) ; return


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( auto & BB : F ) { for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ) { MachineInstr & MI = * I ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; unsigned FiOpc = TII . getFiFromFiMalkrz ( Opc ) ; if ( FiOpc != <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; MIBundleBuilder Bundle ( BB , I ) ; unsigned MalkrzOpc = TII . getMalkrzFromFiMalkrz ( Opc ) ; unsigned MalkrzNumOperands = TII . get ( MalkrzOpc ) . getNumOperands ( ) ; MachineInstrBuilder Malkrz = BuildMI ( F , DL , TII . get ( MalkrzOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < MalkrzNumOperands ; i ++ ) { Malkrz . add ( MI . getOperand ( i ) ) ; } Bundle . prepend ( Malkrz ) ; unsigned FiNumOperands = TII . get ( FiOpc ) . getNumOperands ( ) ; MachineInstrBuilder Fi = BuildMI ( F , DL , TII . get ( FiOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < FiNumOperands ; i ++ ) { Fi . add ( MI . getOperand ( i + MalkrzNumOperands ) ) ; } Bundle . prepend ( Fi ) ; I = BB . erase ( MI ) ; } else { ++ I


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer


<s> void rs6000_secondary_reload_gpr ( rtx reg , rtx mem , rtx scratch , bool store_p ) { int regno = true_regnum ( reg ) ; enum reg_class rclass ; rtx addr ; rtx scratch_or_premodify = scratch ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , store_p ? <STR_LIT> : <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( reg ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && HARD_REGISTER_NUM_P ( regno ) ) ; gcc_assert ( MEM_P (


<s> MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> int <ISA_LIT>TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == <NUM_LIT> ) return <NUM_LIT> ; if ( Opcode == Instruction :: And ) { if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) return


<s> return false ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex


<s> unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= ( Bits + <NUM_LIT> ) ; int32_t tmp = ( int32_t ) MO2 . getImm


<s> return ( vector signed int ) __builtin_altivec_vcmpequw ( ( vector signed int ) a1


<s> void <ISA_LIT>16InstrInfo :: restoreFrame ( unsigned SP , int64_t FrameSize , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( * MF ) ; bool SaveS2 = Reserved [ <STR_LIT> ] ; MachineInstrBuilder MIB ; unsigned Opc = ( ( FrameSize <= <NUM_LIT> ) && ! SaveS2 ) ? <STR_LIT> : <STR_LIT> ; if ( ! isUInt < <NUM_LIT> > ( FrameSize ) ) { unsigned Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; FrameSize = Base ; if ( isInt < <NUM_LIT> > ( Remainder ) ) BuildAddiuSpImm ( MBB , I , Remainder ) ; else adjustStackPtrBig ( SP , Remainder , MBB , I , <STR_LIT> , <STR_LIT> ) ; } MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; addSaveRestoreRegs ( MIB , CSI , RegState :: Define ) ; if ( SaveS2 ) MIB . addReg ( <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrByteSize , PtrByteSize ) ; const MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , <NUM_LIT> ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( TT . find ( <STR_LIT> ) == std :: string ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef Cpu , StringRef FeatureString , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CodeModel , CodeGenOpt :: Level OptLevel , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( ) , TT , Cpu , FeatureString , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CodeModel , CodeModel :: Medium ) , OptLevel ) , Subtarget ( TT , Cpu , FeatureString , * this , Options , getCodeModel ( ) , OptLevel ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) { initAsmInfo ( )


<s> OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Weak ) ; OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Hidden ) ; OutStreamer -> EmitLabel ( Sym ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerAsmOutputForConstraint ( SDValue & Chain , SDValue * Flag , SDLoc DL , const AsmOperandInfo & OpInfo , SelectionDAG & DAG ) const { <STR_LIT> Cond = parseConstraintCode ( OpInfo . ConstraintCode ) ; if ( Cond == <STR_LIT> ) return SDValue ( ) ; if ( OpInfo . ConstraintVT . isVector ( ) || ! OpInfo . ConstraintVT . isInteger ( ) || OpInfo . ConstraintVT . getSizeInBits ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; SDValue EFlags ; if ( Flag ) { EFlags = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , * Flag ) ; Chain = EFlags . getValue ( <NUM_LIT> ) ; } else EFlags = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; SDValue CC = getSETCC ( Cond , EFlags , DL , DAG ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL ,


<s> MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave [ * HiRegToSave ] ) { bool isKill = ! MRI . isLiveIn ( * HiRegToSave ) ; if ( isKill && ! MRI . isReserved ( * HiRegToSave ) ) MBB . addLiveIn ( * HiRegToSave ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * CopyReg , RegState :: Define ) . addReg ( * HiRegToSave , getKillRegState ( isKill ) ) . add ( predOps ( <STR_LIT> ) ) ; RegsToPush . push_back ( * CopyReg ) ; CopyReg = findNextOrderedReg ( ++ CopyReg , CopyRegs , AllCopyRegsEnd


<s> icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf ; break ; case DFmode : cmp_mode = DFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; target = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; aarch64_cond = aarch64_get_condition_code_1 ( cc_mode , ( rtx_code ) cmp_code ) ; if ( bit_code != AND ) { prev = gen_rtx_fmt_ee ( REVERSE_CONDITION ( GET_CODE ( prev ) , GET_MODE ( XEXP ( prev , <NUM_LIT> ) ) ) , VOIDmode , XEXP ( prev , <NUM_LIT> ) , const0_rtx ) ; aarch64_cond = AARCH64_INVERSE_CONDITION_CODE ( aarch64_cond ) ; } create_fixed_operand ( & ops [ <NUM_LIT> ] , XEXP ( prev , <NUM_LIT> ) ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , target ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op0 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op1 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , prev ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , GEN_INT ( aarch64_cond ) ) ; push_to_sequence ( * gen_seq ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) { end_sequence ( ) ; return NULL_RTX ; } * gen_seq = get_insns ( ) ; end_sequence ( ) ; return gen_rtx_fmt_ee ( ( rtx_code ) cmp_code , VOIDmode ,


<s> bool isUImm5 ( ) const { return isUImm < <NUM_LIT> > (


<s> SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl


<s> Operands . erase ( Operands . begin ( ) , Operands . begin ( ) + <NUM_LIT> ) ; Operands . insert ( Operands . begin ( ) , <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , <STR_LIT> ( MCConstantExpr :: create ( LPCC :: ICC_T , getContext ( ) ) , NameLoc , NameLoc ) ) ; } if ( Lexer . is ( AsmToken :: EndOfStatement ) && Name . startswith ( <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> ) { Operands . erase ( Operands . begin ( ) , Operands . begin ( ) + <NUM_LIT> ) ; Operands . insert ( Operands . begin ( ) , <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; } while ( Lexer . isNot ( AsmToken :: EndOfStatement ) && Lexer . is ( AsmToken :: Comma ) ) { Lex ( ) ; if ( parseOperand ( & Operands , Mnemonic ) != MatchOperand_Success ) return true ; } if ( IsMemoryAssignmentError ( Operands ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return true ; } if ( MaybePredicatedInst ( Operands ) ) { Operands . insert ( Operands . begin ( ) + <NUM_LIT> , <STR_LIT> ( MCConstantExpr :: create ( LPCC :: ICC_T , getContext ( ) ) , NameLoc , NameLoc ) ) ; } return false


<s> return __builtin_aarch64_lfrintnudfdi_us ( __a )


<s> bool UseOffset = true ; const TargetRegisterClass * RC = MRI . getRegClass ( SrcReg ) ; bool Is32BitInt = RC -> hasSuperClassEq ( & <STR_LIT> ) ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( Is32BitInt && <STR_LIT> ) ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , UseOffset , IndexReg ) ; bool IsVSSRC = isVSSRCRegClass ( RC ) ; bool IsVSFRC = isVSFRCRegClass ( RC ) ; bool Is32VSXStore = IsVSSRC && Opc == <STR_LIT> ; bool Is64VSXStore = IsVSFRC && Opc == <STR_LIT> ; if ( ( Is32VSXStore || Is64VSXStore ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXStore || Is64VSXStore ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlign ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXStore || Is64VSXStore ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc


<s> processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( ! usePackedStack ( MF ) ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> ) ; int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach


<s> EVT VT = <STR_LIT> ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ; } MVT TestVT = VT . is128BitVector ( ) ?


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( RHSC * <NUM_LIT> < MFI . getObjectSize ( FI ) ) { if ( ! MFI . isFixedObjectIndex ( FI ) && MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; if ( MFI . getObjectAlignment ( FI ) >= <NUM_LIT> ) { Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy (


<s> else if ( ( OpMI = getOpcodeDef ( TargetOpcode :: G_FCONSTANT , I . getOperand ( Idx ) . getReg ( ) , MRI ) ) ) Csts . emplace_back ( const_cast < ConstantFP * > ( OpMI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) ) ) ; else return false ; } Constant * CV = ConstantVector :: get ( Csts ) ; MachineIRBuilder MIB ( I ) ; if ( CV -> isNullValue ( ) ) { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstSize == <NUM_LIT> ) { auto Mov = MIB . buildInstr ( <STR_LIT> , { DstReg } , { } ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Mov , TII , TRI , RBI ) ; } else if ( DstSize == <NUM_LIT> ) { auto Mov = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { } ) . addImm ( <NUM_LIT> ) ; MIB . buildInstr ( TargetOpcode :: COPY , { DstReg } , { } ) . addReg ( Mov . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } } auto * CPLoad = emitLoadFromConstantPool ( CV , MIB ) ; if ( ! CPLoad


<s> if ( isInt < <NUM_LIT> > ( Amount ) ) BuildAddiuSpImm ( MBB , I , Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; bool IsILP32 = Options . getABIName (


<s> TS . forbidModuleDirective ( ) ; if ( MI -> isDebugValue ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( InConstantPool && MI -> getOpcode ( ) != <STR_LIT> ) { OutStreamer -> EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer -> EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer -> EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) && I


<s> const char * ret = ret_p ? <STR_LIT> : <STR_LIT> ; if ( regno != INVALID_REGNUM ) { const char * reg_prefix ; if ( LEGACY_INT_REGNO_P ( regno ) ) reg_prefix = TARGET_64BIT ? <STR_LIT> : <STR_LIT> ; else reg_prefix = <STR_LIT> ; sprintf ( name , <STR_LIT> , ret , prefix , reg_prefix , reg_names [ regno ] ) ; } else sprintf ( name , <STR_LIT> , ret , prefix ) ; } else { if ( regno != INVALID_REGNUM ) ASM_GENERATE_INTERNAL_LABEL ( name


<s> bool useCheriExactEquals ( ) const { return


<s> InsertedThunks = true ; return true ; } if ( Is64Bit ) { assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; populateThunk ( MF , <STR_LIT> ) ; } else { if ( MF . getName ( ) == EAXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == ECXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDIThunkName ) populateThunk ( MF , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; } return true


<s> rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_return_addr_mask ( reg ) ) ; return reg


<s> if ( Instr . getOpcode ( ) == <STR_LIT> ) { ExpandVastartSaveXmmRegs ( & ( MF . front


<s> void EmitByte ( unsigned char C , raw_ostream &


<s> return ( uint32x2_t ) __builtin_aarch64_urhaddv2si ( ( int32x2_t ) __a , ( int32x2_t )


<s> AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> )

, <STR_LIT> ) . addReg ( <STR_LIT> ) ) ;


<s> TRI = ST . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; SchedModel . init ( & ST ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; const MachineOperand * BaseOp ; int64_t Offset ; if ( TII -> getMemOperandWithOffset ( MI , BaseOp , Offset , TRI ) && BaseOp -> isReg ( ) ) { unsigned BaseReg = BaseOp -> getReg ( ) ; if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT>


<s> APInt ImmValue ; EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ( Signed && ImmValue . isSignedIntN ( ImmBitSize ) ) || ( ! Signed && ImmValue . isIntN ( ImmBitSize ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue , EltTy ) ; return true ; } } return


<s> uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return true


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { if ( ! <ISA_LIT>FI -> getLOHRelated ( ) . empty (


<s> TextSections . insert ( TLOFMacho . getConstTextCoalSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = TextSections . size ( ) ; i != e ; ++ i ) OutStreamer . SwitchSection ( TextSections [ i ] ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } const MCSection * StaticInitSect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR | MachO :: S_ATTR_PURE_INSTRUCTIONS , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( StaticInitSect ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getCStringSection (


<s> rtx fusion_wrap_memory_address ( rtx old_mem ) { rtx old_addr = XEXP ( old_mem , <NUM_LIT> ) ; rtvec v = gen_rtvec ( <NUM_LIT> , old_addr ) ; rtx new_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_FUSION_ADDIS ) ; return replace_equiv_address_nv ( old_mem , new_addr ,


<s> } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else return ; MI -> addRegisterKilled ( Reg ,


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI , LiveIntervals * LIS ) const { return


<s> if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchVersion = V4T ; else <ISA_LIT>ArchVersion = V4 ; } } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion =


<s> return __builtin_neon_vmul_lanev8hf ( __a ,


<s> } if ( adj_off >= <NUM_LIT> ) return false ; if ( off_val < <NUM_LIT> ) { adj_off = - adj_off ; new_off = - new_off ; } mem_1 = change_address ( mem_1 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off ) ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; msize = GET_MODE_SIZE ( mode ) ; mem_2 = change_address ( mem_2 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize ) ) ; mem_3 = change_address ( mem_3 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; mem_4 = change_address ( mem_4 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI ( OSType


<s> startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST (

VOIDmode , reg , GEN_INT ( intoffset ) ) ;


<s> debug ( <STR_LIT> ) ; return true ; } mcInst . setOpcode ( insn . instructionID ) ; int index ; insn . numImmediatesTranslated = <NUM_LIT> ; for ( index = <NUM_LIT> ; index < <ISA_LIT>_MAX_OPERANDS ; ++ index ) { if ( insn . operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . operands [ index ] , insn , Dis ) ) { return true ; } } } return false


<s> if ( Enable<ISA_LIT>FastISel ) return new <ISA_LIT>FastISel


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! MFI -> isLRSpilled ( ) ) report_fatal_error ( <STR_LIT> ) ; Br . MaxDisp = ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Value > <NUM_LIT> ) { llvm_unreachable (


<s> return parseAddress ( Operands , BDRMem


<s> return ( __m512i ) __builtin_ia32_packuswb512_mask ( ( __v32hi ) __A , ( __v32hi )


<s> return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) .

hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> void <ISA_LIT>InstPrinter :: printBDAddrOperand ( const MCInst * MI , int


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> assert ( ! BytesAdded && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( IsIntegerCC ( CC ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; if ( ! FBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT>


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! Inst . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; } return TargetInstrInfo :: hasReassociableOperands ( Inst ,


<s> for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) { Function :: const_arg_iterator FuncArg = MF . getFunction ( ) . arg_begin ( ) ; if ( Ins [ i ] . Flags . isSRet ( ) ) { OriginalArgWasF128 . push_back ( false ) ; OriginalArgWasFloat . push_back (


<s> assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! isPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( CallOpc == <STR_LIT> && ! resideInSameSection ( MF . getFunction ( ) , Callee ,


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; FalseReg . setImplicit


<s> else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } if ( isVCTP ( MI ) && ! AddVCTP ( MI ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; bool IsUse = false ; unsigned LastOpIdx = MI -> getNumOperands ( ) - <NUM_LIT> ; for ( auto & Op : enumerate ( reverse ( MCID . operands ( ) ) ) ) { const MachineOperand & MO = MI -> getOperand ( LastOpIdx - Op . index ( ) ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( <STR_LIT> ( Op . value ( ) . OperandType ) ) { VPTState :: addInst ( MI ) ; IsUse = true ; } else if ( MI -> getOpcode ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } bool RequiresExplicitPredication = ( MCID . TSFlags & <STR_LIT> ) == <NUM_LIT> ; if ( isDomainMVE ( MI ) && RequiresExplicitPredication ) { if ( ! IsUse && producesDoubleWidthResult ( * MI ) ) { DoubleWidthResultInstrs . insert ( MI ) ; return


<s> return CurDAG -> getTargetConstant ( Imm , DL ,


<s> if ( WantExtend ) { <STR_LIT> Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) , true ) ; if ( Ext == <STR_LIT> ) return false ; Offset = narrowIfNeeded ( CurDAG , N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SignExtend = CurDAG -> getTargetConstant ( Ext == <STR_LIT> , dl , <STR_LIT> ) ; } else { Offset = N . getOperand ( <NUM_LIT> ) ; SignExtend = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; } unsigned LegalShiftVal = Log2_32 ( Size


<s> bool isMSRSystemRegister ( ) const { if ( ! isSysReg ( ) ) return false ; bool


<s> if ( Addr . BaseType == Address :: FrameIndexBase ) { int FI = Addr . Base . FI ; int Offset = Addr . Offset ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { signed Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand (


<s> AllowDollarAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; AllowHashAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; DotIsPC = ( AssemblerDialect == AD_ATT ) ; StarIsPC = ( AssemblerDialect == AD_HLASM ) ; EmitGNUAsmStartIndentationMarker = ( AssemblerDialect == AD_ATT ) ; AllowAtInName = ( AssemblerDialect == AD_HLASM ) ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo ,


<s> SDValue True = CurDAG -> getTargetConstant ( T -> getZExtValue ( ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC


<s> if ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype )


<s> if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } Tmp0 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) ; SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue MaskNot = DAG . getNode ( <STR_LIT> , dl , OpVT , Mask , DAG . getNode ( <STR_LIT> , dl , OpVT , AllOnes ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 , Mask ) , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 , MaskNot ) ) ; if ( VT == <STR_LIT> ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } return Res ; } if ( SrcVT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Tmp1 , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; SDValue Mask1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Mask2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 , Mask1 ) ; if ( VT == <STR_LIT> ) { Tmp0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 ) , Mask2 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 , Tmp1 ) ) ; } Tmp0 = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Tmp0 , <NUM_LIT> ) ; SDValue Lo = Tmp0 . getValue ( <NUM_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 . getValue


<s> return CU :: UNWIND_ARM64_MODE_DWARF ; case MCCFIInstruction :: OpDefCfa : { unsigned XReg = getXRegFromWReg ( * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ) ; if ( XReg != <STR_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; assert ( XReg == <STR_LIT> && <STR_LIT> ) ; assert ( i + <NUM_LIT> < e && <STR_LIT> ) ; const MCCFIInstruction & LRPush = Instrs [ ++ i ] ; assert ( LRPush . getOperation ( ) == MCCFIInstruction :: OpOffset && <STR_LIT> ) ; const MCCFIInstruction & FPPush = Instrs [ ++ i ] ; assert ( FPPush . getOperation ( ) == MCCFIInstruction :: OpOffset && <STR_LIT> ) ; unsigned LRReg = * MRI . getLLVMRegNum ( LRPush . getRegister ( ) , true ) ; unsigned FPReg = * MRI . getLLVMRegNum ( FPPush . getRegister ( ) , true ) ; LRReg = getXRegFromWReg ( LRReg ) ; FPReg = getXRegFromWReg ( FPReg ) ; assert ( LRReg == <STR_LIT> && FPReg == <STR_LIT> && <STR_LIT> ) ; CompactUnwindEncoding |= CU :: UNWIND_ARM64_MODE_FRAME ; HasFP = true ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { assert ( StackSize == <NUM_LIT> && <STR_LIT> ) ; StackSize = std :: abs ( Inst . getOffset ( ) ) ; break ; } case MCCFIInstruction :: OpOffset : { unsigned Reg1 = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( i + <NUM_LIT> == e ) return CU :: UNWIND_ARM64_MODE_DWARF ; const MCCFIInstruction & Inst2 = Instrs [ ++ i ] ; if ( Inst2 . getOperation ( ) != MCCFIInstruction :: OpOffset ) return CU :: UNWIND_ARM64_MODE_DWARF ; unsigned Reg2 = * MRI . getLLVMRegNum ( Inst2 . getRegister ( ) , true ) ; Reg1 = getXRegFromWReg ( Reg1 ) ; Reg2 = getXRegFromWReg ( Reg2


<s> void <ISA_LIT>TargetLowering :: insertCopiesSplitCSR ( MachineBasicBlock * Entry , const SmallVectorImpl < MachineBasicBlock * > & Exits ) const { const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * IStart = TRI -> getCalleeSavedRegsViaCopy ( Entry -> getParent ( ) ) ; if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute ::


<s> else CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return OptLevel >= CodeGenOpt ::


<s> if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ; mips_emit_binary ( code , target , zie , const0_rtx


<s> if ( ST -> hasNEON ( ) ) { if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , VT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) V2 = V1 ; return DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; } } if ( ST -> hasMVEIntegerOps ( ) ) { if ( isVMOVNMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V2 , V1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( isVMOVNMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( ST -> hasNEON ( ) && V1 -> getOpcode ( ) == <STR_LIT> && V2 -> isUndef ( ) ) { SDValue SubV1 = V1 -> getOperand ( <NUM_LIT> ) ; SDValue SubV2 = V1 -> getOperand ( <NUM_LIT> ) ; EVT SubVT = SubV1 . getValueType ( ) ; assert ( llvm :: all_of ( ShuffleMask , [ & ] ( int i ) { return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . setPic ( OutContext . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI (


<s> int64_t SignedValue = static_cast < int64_t > ( Value ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return AdrImmBits ( Value & <NUM_LIT> ) ; case <STR_LIT> : assert ( ! IsResolved ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return AdrImmBits ( Value & <NUM_LIT> ) ; return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved


<s> bool isSImm20 ( ) const { return isSImm < <NUM_LIT> > ( )


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if (

! isUndefOrEqual ( Mask [ e + i ] , i ) ) return false ;


<s> auto matchAsInsertPS = [ & ] ( SDValue VA , SDValue VB , ArrayRef < int > CandidateMask ) { unsigned ZMask = <NUM_LIT> ; int VADstIndex = - <NUM_LIT> ; int VBDstIndex = - <NUM_LIT> ; bool VAUsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == CandidateMask [ i ] ) { VAUsedInPlace = true ; continue ; } if ( VADstIndex >= <NUM_LIT> || VBDstIndex >= <NUM_LIT> ) return false ; if ( CandidateMask [ i ] < <NUM_LIT> ) { VADstIndex = i ; } else { VBDstIndex = i ; } } if ( VADstIndex < <NUM_LIT> && VBDstIndex < <NUM_LIT> ) return false ; unsigned VBSrcIndex = <NUM_LIT> ; if ( VADstIndex >= <NUM_LIT> ) { VBSrcIndex = CandidateMask [ VADstIndex ] ; VBDstIndex = VADstIndex ; VB = VA ; } else { VBSrcIndex = CandidateMask [ VBDstIndex ] - <NUM_LIT> ; } if ( ! VAUsedInPlace ) VA = DAG . getUNDEF ( <STR_LIT> ) ; V1 = VA ; V2 = VB ; InsertPSMask = VBSrcIndex << <NUM_LIT> | VBDstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } ; if ( matchAsInsertPS ( V1 , V2 , Mask ) ) return true ; SmallVector < int , <NUM_LIT> > CommutedMask ( Mask . begin (


<s> return ( STI -> getFeatureBits ( ) &


<s> SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( ) , ResNo ) ) ; } std :: vector < SDValue >


<s> Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New


<s> <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result .


<s> MachineOperand SrcBase = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; uint64_t SrcDisp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t Length = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * EndMBB = ( Length > <NUM_LIT> && Opcode == <STR_LIT> ? splitBlockAfter ( MI , MBB ) : <NUM_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) > <NUM_LIT> ) { bool HaveSingleBase = DestBase . isIdenticalTo ( SrcBase ) ; uint64_t StartCountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t StartSrcReg = forceReg ( MI , SrcBase , TII ) ; uint64_t StartDestReg = ( HaveSingleBase ? StartSrcReg : forceReg ( MI , DestBase , TII ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t ThisSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t ThisDestReg = ( HaveSingleBase ? ThisSrcReg : MRI . createVirtualRegister ( RC ) ) ; uint64_t NextSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextDestReg = ( HaveSingleBase ? NextSrcReg : MRI . createVirtualRegister ( RC ) ) ; RC = & <STR_LIT> ; uint64_t ThisCountReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextCountReg = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * NextMBB = ( EndMBB ? emitBlockAfter ( LoopMBB ) : LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB


<s> bool isImm32 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> if ( Subtarget . isABI_CheriPureCap ( ) ) { Reserved . set ( ABI . GetStackPtr ( ) ) ; if ( FL -> hasFP ( MF ) ) Reserved . set ( ABI . GetFramePtr ( ) ) ; if ( FL -> hasBP ( MF ) ) Reserved . set ( ABI . GetBasePtr ( ) ) ; if ( Subtarget . useCheriCapTable ( ) ) Reserved . set ( ABI . GetGlobalCapability ( ) ) ; } if ( Cheri8 ) for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCheri8Regs ) ; ++ I ) Reserved . set ( ReservedCheri8Regs [ I ] ) ; if ( Cheri16 ) for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCheri16Regs ) ; ++ I ) Reserved . set ( ReservedCheri16Regs [ I ] ) ; } else Reserved . set ( <STR_LIT> ) ; if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( hasStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( MCPhysReg Reg : <STR_LIT> ) Reserved . set ( Reg ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } return


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) ||


<s> MachineInstr & MI = * MBBI ; MachineInstr * OriginalCall ; MachineOperand & CallTarget = MI . getOperand ( <NUM_LIT> ) ; assert ( ( CallTarget . isGlobal ( ) || CallTarget . isReg ( ) ) && <STR_LIT> ) ; unsigned Opc = CallTarget . isGlobal ( ) ? <STR_LIT> : <STR_LIT> ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; OriginalCall -> addOperand ( CallTarget ) ; unsigned RegMaskStartIdx = <NUM_LIT> ; while ( ! MI . getOperand ( RegMaskStartIdx ) . isRegMask ( ) ) { assert ( MI . getOperand ( RegMaskStartIdx ) . isReg (


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; unsigned Reg = MRI . getDwarfRegNum (


<s> MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start = I ; BasicBlock :: const_iterator End = II ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr )


<s> void printi16mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT>


<s> pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { int first_store_pos = - <NUM_LIT> ; pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT>


_mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_RTX_NAME ( code ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( x ) ; return ret


<s> static reg_class_t mmix_preferred_reload_class ( rtx