<s> EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; if ( MRI . getRegClass ( SrcReg ) == & <STR_LIT> ) { unsigned KSrcReg = SrcReg ; SrcReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , SrcReg ) . addReg ( KSrcReg ) ; SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; } SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg (


<s> unsigned Lo = TestSecondOperand ? NumElems : <NUM_LIT> ; unsigned Hi = Lo + NumElems ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , ( int ) Lo , ( int ) Hi ) ) return false ; return true


<s> for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_PTR_ADD , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s8 } , { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 ,


<s> bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SaveSP = Op . getOperand (


<s> MCSubtargetInfo STI = getSubtargetInfo ( ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) , STI ) ; if ( MI -> getOpcode ( ) ==


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm


<s> BuildMI ( * MBB , MI , DL , TII -> get ( CompareOpcode ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII


<s> bool isNEONi16ByteReplicate ( ) const { return isNEONByteReplicate (


<s> unsigned <ISA_LIT>AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return


<s> MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value &


<s> static bool aarch64_rtx_costs_wrapper ( rtx x , machine_mode mode , int outer , int param , int * cost , bool speed ) { bool result = aarch64_rtx_costs ( x , mode , outer , param , cost , speed ) ; if ( dump_file && ( dump_flags


<s> return ( __m256i ) __builtin_ia32_loaddqusi256_mask ( ( const int * ) __P , ( __v8si ) __W ,


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MPI , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( DstVT , <STR_LIT> , dl , Store2 , StackSlot , MPI , Align ( <NUM_LIT> ) , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF ) , PtrVT ) ; unsigned CPAlignment = cast < ConstantPoolSDNode > ( FudgePtr ) -> getAlignment ( ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT>


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { return RM . hasValue ( ) ? * RM


<s> return SelectAddrModeIndexedBitWidth ( N , true , <NUM_LIT> , Size


<s> static inline uint64_t decodeLogicalImmediate ( uint64_t val , unsigned regSize ) { unsigned N = ( val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned immr = ( val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned imms = val & <NUM_LIT> ; assert ( ( regSize == <NUM_LIT> || N == <NUM_LIT> ) && <STR_LIT> ) ; int len = <NUM_LIT> - countLeadingZeros ( ( N << <NUM_LIT> ) | ( ~ imms


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg (


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> bool hasModifier ( ) const { return Modifier !=


<s> printSymbolLo ( MI , OpNo ) ; O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( OpNo

+ <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ;


<s> case <NUM_LIT> : return HasMemoryOperand ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return HasMemoryOperand ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return HasMemoryOperand ? <STR_LIT> :


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue (


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; if ( ! EnableQuadPrecision || ( Op . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOpcode ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT>

) . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> LoadSDNode * LdNode = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; assert ( LdNode && LdNode -> getOffset ( ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , <NUM_LIT> ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 ,


<s> if ( MI . getNumOperands ( ) == <NUM_LIT> ) return nullptr ; MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return nullptr ; return &


<s> } op0_word = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; op1_word = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , op0_word , op1_word , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ; cy_clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; if ( mode == HImode ) vec = gen_rtvec ( <NUM_LIT> , branch , cy_clobber ) ; else if ( code == NE || code == EQ ) vec = gen_rtvec ( <NUM_LIT> , branch , gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; else { rtx sub ; sub = gen_rtx_SET ( VOIDmode , op0 , gen_rtx_MINUS ( SImode , op0 , op1 ) ) ; sub = gen_rtx_CLOBBER ( SImode , op0 ) ; vec = gen_rtvec ( <NUM_LIT> , branch , sub , cy_clobber ) ; } emit_jump_insn ( gen_rtx_PARALLEL ( VOIDmode


<s> MVT VT = N -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ld = N -> getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( Ld ) ) { unsigned DestIndex = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) >> <NUM_LIT> ; Ld = NarrowVectorLoadToElement ( cast < LoadSDNode > ( Ld ) , DestIndex , DAG ) ; SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT


<s> return Kind == k_Register && Reg . Kind ==


<s> static inline const char * getAddrOpcStr ( AddrOpc Op ) { return Op == sub ?


<s> if ( isThumbTwo ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) { if ( ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isT2SOImm ( ) ) return false ; if ( inITBlock ( ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm0_7 ( ) ) return false ; return true ; } if ( isThumbTwo ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! inITBlock ( ) || ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) ) return true ; if ( isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && ( Operands . size ( ) == <NUM_LIT> || Operands . size ( ) == <NUM_LIT> ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <STR_LIT> && static_cast < <ISA_LIT>Operand * > (

Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> ) return true ;


<s> return StringRef ( Tok . Data , Tok . Length


<s> bool <ISA_LIT>AsmPrinter :: isLongBranchPseudo ( int Opcode ) const { return


<s> machine = ( machine_function * ) ggc_alloc_cleared ( sizeof ( machine_function ) ) ; machine -> func_type =


<s> MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . addOperand ( Compare . getOperand ( I ) ) ; MIB . addOperand ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) MIB . addRegMask ( RegMask ) ; MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MBBI -> clearRegisterKills ( SrcReg , TRI


<s> TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer (


<s> unsigned <ISA_LIT>BaseInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const { const MachineBasicBlock & MBB = * MI -> getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI


<s> MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit


<s> static SDValue LowerVECTOR_SHUFFLE_256 ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned NumLaneElems = NumElems / <NUM_LIT> ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NVT = <STR_LIT> ( EltVT , NumLaneElems ) ; SDValue Shufs [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned l = <NUM_LIT> ; l < <NUM_LIT> ; ++ l ) { int InputUsed [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned LaneStart = l * NumLaneElems ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof (


<s> std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; IRBuilder < > Builder ( LD ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( LD -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic (


<s> bool <ISA_LIT>TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttribute ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector (


<s> return ( __mmask16 ) __builtin_ia32_ucmpd512_mask ( ( __v16si ) __X , ( __v16si )


<s> rtx t1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_zero_extendhisi2 ( t1 , op ) ) ; emit_insn ( gen_ashlsi3 ( t1 , t1 , GEN_INT ( <NUM_LIT> ) ) ) ; op = gen_lowpart ( SFmode , t1 ) ; } * pop0 = op ; op = gen_lowpart ( HImode , op1 ) ; if ( CONST_INT_P ( op ) ) op = simplify_const_unary_operation ( FLOAT_EXTEND , SFmode , op1 , BFmode ) ; else { rtx t1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_zero_extendhisi2 ( t1 , op ) ) ; emit_insn ( gen_ashlsi3 ( t1 , t1 , GEN_INT ( <NUM_LIT> ) ) ) ; op = gen_lowpart ( SFmode , t1 ) ; } * pop1 = op ; return ix86_prepare_fp_compare_args ( code , pop0 , pop1 ) ; } if ( ! is_sse && ( unordered_compare || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || standard_80387_constant_p ( op1 ) == <NUM_LIT> ) && GET_CODE ( op1 ) != FLOAT ) || ix86_fp_comparison_strategy ( code ) == IX86_FPCMP_COMI ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == <NUM_LIT> || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == <NUM_LIT> ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == <NUM_LIT> ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) { std :: swap ( op0 , op1


<s> static bool needsFP ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF .


<s> bool <ISA_LIT>CTRLoops :: isInductionOperation ( const MachineInstr * MI , unsigned IVReg ) const { return ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg


<s> assert ( ( Cond . empty ( ) || ( getMalkrzFromFiMalkrz ( Cond [ <NUM_LIT> ] . getImm ( ) ) == <STR_LIT> && get ( Cond [ <NUM_LIT> ] . getImm ( ) ) . getNumOperands ( ) == Cond . size ( ) ) ) && <STR_LIT> ) ; assert ( ! BytesAdded && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; MachineInstrBuilder Malkrz = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) . addMBB ( TBB ) ; for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; i ++ ) { Malkrz . add ( Cond [ i ] ) ; } ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> case <STR_LIT> : if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) return COFF :: IMAGE_REL_ARM64_SECREL_LOW12A ; if ( RefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) return COFF :: IMAGE_REL_ARM64_SECREL_HIGH12A ; } return COFF :: IMAGE_REL_ARM64_PAGEOFFSET_12A ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) return COFF :: IMAGE_REL_ARM64_SECREL_LOW12L ; } return COFF :: IMAGE_REL_ARM64_PAGEOFFSET_12L ; case <STR_LIT> : return COFF :: IMAGE_REL_ARM64_REL21 ; case <STR_LIT> : return COFF :: IMAGE_REL_ARM64_PAGEBASE_REL21 ; case <STR_LIT> : return COFF :: IMAGE_REL_ARM64_BRANCH14 ; case <STR_LIT>


<s> void <ISA_LIT>RegisterInfo :: lowerDynamicAlloc ( MachineBasicBlock :: iterator II ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; Align MaxAlign = MFI . getMaxAlign ( ) ; assert ( isAligned ( MaxAlign , maxCallFrameSize ) && <STR_LIT> ) ; ( void ) MaxAlign ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; Register NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; prepareDynamicAlloca ( II , NegSizeReg , KillNegSizeReg , Reg ) ; if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT>


<s> attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ <NUM_LIT> ] ) == DImode && ( ! body || ! dep_between_memop_and_curr


<s> DebugLoc DL = Op . getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( )


<s> static unsigned int rs6000_parm_start ( machine_mode mode , const_tree type , unsigned int nwords ) { unsigned int


<s> unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ; return x == <NUM_LIT> || x == <NUM_LIT> || x == <NUM_LIT> ; } if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) && REG_P ( XEXP ( op0 , <NUM_LIT> ) ) ) { unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo


<s> const MCSymbolRefExpr * PersonalityRef = MCSymbolRefExpr :: Create ( Personality , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( PersonalityRef , <NUM_LIT> , <NUM_LIT> ) ; uint32_t Entry = <NUM_LIT> ; uint32_t NumExtraEntryWords = <NUM_LIT> ; Entry |= NumExtraEntryWords << <NUM_LIT> ; Entry |= UNWIND_OPCODE_FINISH << <NUM_LIT> ; Entry |= UNWIND_OPCODE_FINISH << <NUM_LIT> ; Entry |= UNWIND_OPCODE_FINISH


<s> void EmitARM64WinCFISaveFReg ( unsigned Reg , int Offset


<s> static void getDoubleRegPair ( unsigned DoubleReg , unsigned & EvenReg , unsigned & OddReg ) { static const unsigned EvenHalvesOfPairs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned OddHalvesOfPairs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned DoubleRegsInOrder [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( DoubleRegsInOrder ) / sizeof ( unsigned ) ; ++ i )

if ( DoubleRegsInOrder [ i ] == DoubleReg ) {


<s> if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) , TD -> getPointerSize ( <NUM_LIT> ) ) ; } Stubs . clear


<s> } if ( stub_head ) { struct stub_list * q ; for ( q = stub_head ; q != NULL ; q = q -> next ) { const char * name = q -> name ; const char * oname ; if ( name [ <NUM_LIT> ] == '*' ) ++ name ; oname = name ; if ( name [ <NUM_LIT> ] == '.' ) ++ name ; if ( ! startswith ( name , <STR_LIT> ) ) continue ; name += <NUM_LIT> ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> <STR_LIT> , oname ,


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl

, VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc == <STR_LIT>


<s> void addCoprocRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> args = void_list_node ; for ( a = strlen ( s16builtins [ i ] . arg_types ) - <NUM_LIT> ; a >= <NUM_LIT> ; a -- ) { switch ( s16builtins [ i ] . arg_types [ a ] ) { case 's' : arg = short_integer_type_node ; break ; case 'S' : arg = short_unsigned_type_node ; break ; case 'l' : arg = long_integer_type_node ; break ; case 'L' : arg = long_unsigned_type_node ; break ; default : gcc_unreachable ( ) ; } if ( a == <NUM_LIT> ) ret_type =


<s> float f [ <NUM_LIT> ] ; } u ; u . f [ <NUM_LIT> ] = a ; u . f [ <NUM_LIT>


<s> } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; const <ISA_LIT>InstrInfo * TII = ST -> getInstrInfo ( ) ; unsigned Start , End ; if ( TII -> isRxSBGMask ( Imm . getZExtValue ( ) , BitSize , Start , End ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( auto * Op = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) )

) return Op -> getZExtValue ( ) == <NUM_LIT> ;


<s> } unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } return


<s> bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print ( OS ,


<s> static MCTargetStreamer * create<ISA_LIT>NullTargetStreamer ( MCStreamer & S ) { return new <ISA_LIT>TargetStreamer (


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; MaskVT = <STR_LIT> ( EltVT , Mask . size ( ) ) ; } MVT LogicVT = VT ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { Zero = DAG . getConstantFP ( <NUM_LIT> , DL , EltVT ) ; APFloat AllOnesValue = APFloat :: getAllOnesValue ( SelectionDAG :: EVTToAPFloatSemantics ( EltVT ) , EltVT . getSizeInBits ( ) ) ; AllOnes = DAG . getConstantFP ( AllOnesValue , DL , EltVT ) ; LogicVT = <STR_LIT> ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Mask . size ( ) ) ; } else { Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V ) return SDValue (


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) != REG || REGNO ( operands [ <NUM_LIT> ] ) != EH_RETURN_STACKADJ_REGNO ) { rtx sp


<s> bit_cost = <NUM_LIT> ; if ( sparc_costs -> int_mul_bit_factor ) { int nbits ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; for ( nbits = <NUM_LIT> ; value != <NUM_LIT> ; value &= value - <NUM_LIT> ) nbits ++ ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_DOUBLE && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == VOIDmode ) { rtx x1 = XEXP ( x , <NUM_LIT> ) ; unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW ( x1 ) ; unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH ( x1 ) ; for ( nbits = <NUM_LIT> ; value1 != <NUM_LIT> ; value1 &= value1 - <NUM_LIT> ) nbits ++ ; for ( ; value2 != <NUM_LIT> ; value2 &= value2 - <NUM_LIT> ) nbits ++ ; } else nbits = <NUM_LIT> ; if ( nbits < <NUM_LIT> ) nbits = <NUM_LIT> ; bit_cost = ( nbits - <NUM_LIT> ) / sparc_costs -> int_mul_bit_factor ; bit_cost = COSTS_N_INSNS ( bit_cost ) ; } if ( mode == DImode ) * total = sparc_costs -> int_mulX + bit_cost ; else * total = sparc_costs -> int_mul + bit_cost ; } return false ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( <NUM_LIT> ) + sparc_costs -> shift_penalty ; return false ; case DIV : case UDIV : case MOD : case UMOD : if ( float_mode_p ) { if ( mode == DFmode ) * total = sparc_costs -> float_div_df ; else * total = sparc_costs -> float_div_sf ; } else { if ( mode == DImode ) * total = sparc_costs -> int_divX ; else * total = sparc_costs -> int_div ; } return false ; case NEG : if ( ! float_mode_p ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ABS : case FLOAT : case UNSIGNED_FLOAT : case FIX : case UNSIGNED_FIX : case FLOAT_EXTEND : case FLOAT_TRUNCATE : * total = sparc_costs -> float_move ; return false ; case SQRT : if ( mode == DFmode ) * total = sparc_costs -> float_sqrt_df ; else * total = sparc_costs -> float_sqrt_sf ; return false ; case COMPARE : if ( float_mode_p ) * total = sparc_costs -> float_cmp ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case IF_THEN_ELSE : if ( float_mode_p ) * total = sparc_costs -> float_cmove ; else * total = sparc_costs ->


<s> ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createMacroFusionDAGMutation ( DAG -> TII ) ) ; return DAG


<s> if ( start == nbits ) return start ; gcc_assert ( start < nbits ) ; for ( unsigned int i = start ; i < nbits ; i ++ ) if ( bitmap_bit_p ( bmp , i ) ) return i ; return nbits


<s> return ( __m128i ) __builtin_ia32_vpcomeqb ( ( __v16qi )


<s> setCC ( <STR_LIT> , Builder -> CreateICmpEQ ( LHS , RHS ) ) ; setCC ( <STR_LIT> , Builder -> CreateICmpNE ( LHS , RHS ) ) ; return computeEFLAGSForDef ( Builder -> CreateSub ( LHS , RHS ) , OldEFLAGS ) ; } else { setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUEQ ( LHS , RHS ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUNO ( LHS , RHS ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpULT ( LHS ,


<s> if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , <NUM_LIT> ) = shallow_copy_rtvec ( XVEC ( pat , <NUM_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , <NUM_LIT> , i )


<s> Align getStackAlignment ( ) const { return StackAlignment


<s> for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; LHSElts . push_back ( LHS ) ; RHSElts . push_back ( RHS ) ; } SDValue LHS = DAG . getBuildVector ( VT , DL , LHSElts ) ; SDValue RHS = DAG . getBuildVector ( VT , DL , RHSElts ) ; return DAG . getNode ( Opcode , DL


<s> static void aarch64_restore_callee_saves ( poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { unsigned regno ; unsigned regno2 ; poly_int64 offset ; rtx anchor_reg = NULL_RTX , ptrue = NULL_RTX ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) { bool frame_related_p = aarch64_emit_cfi_for_reg_p ( regno ) ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; machine_mode mode = aarch64_reg_save_mode ( regno ) ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; rtx base_rtx = stack_pointer_rtx ; if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) aarch64_adjust_sve_callee_save_base ( mode , base_rtx , anchor_reg , offset , ptrue ) ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) emit_insn (

gen_aarch64_pred_mov ( mode , reg , ptrue , mem ) ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } return


<s> aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , AARCH64_SIMD_BUILTIN_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_builtin_data ) ; i ++ , fcode ++ ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] = { <NUM_LIT> } ; aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ op_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ op_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ op_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = aarch64_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> ,


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && UseSSEReg && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = IsStrict ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , SrcVT , Chain , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first


<s> else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_predicate ) op_mode = HImode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; if ( qualifiers & qualifier_void_pointer ) eltype = qualifiers & qualifier_const ? const_ptr_type_node : ptr_type_node ; else { eltype = arm_simd_builtin_type ( op_mode , qualifiers ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; } if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed = false ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * , <NUM_LIT> > Starts ; SmallVector < MachineInstr * , <NUM_LIT> > Decs ; SmallVector < MachineInstr * , <NUM_LIT> > Ends ; for ( auto & I : MBB ) { if ( IsLoopStart ( I ) ) Starts . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Decs . push_back ( &


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOT_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PIC_BASE_OFFSET , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_GOTTPOFF , <STR_LIT> } , { MO_INDNTPOFF , <STR_LIT> } , { MO_TPOFF , <STR_LIT> } , { MO_DTPOFF , <STR_LIT> } , { MO_NTPOFF , <STR_LIT> } , { MO_GOTNTPOFF , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_DARWIN_STUB , <STR_LIT> } , { MO_DARWIN_NONLAZY , <STR_LIT> } , { MO_DARWIN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_TLVP , <STR_LIT> } , { MO_TLVP_PIC_BASE , <STR_LIT> } , { MO_SECREL , <STR_LIT> } } ; return makeArrayRef (


<s> void ELF<ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) IsResolved = false ; if ( IsResolved ) ( void ) adjustFixupValue ( Fixup


<s> bool <ISA_LIT>LowOverheadLoops :: ProcessLoop ( MachineLoop * ML ) { bool Changed = false ; for ( auto I = ML -> begin ( ) , E = ML -> end ( ) ; I != E ; ++ I ) Changed |= ProcessLoop ( * I ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true , true ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; } ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ||


<s> const char * getPassName ( ) const override { return


<s> FunctionPass * create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>TargetMachine & TM


<s> return sh_recog_treg_set_expr_reent_count >


<s> switch ( AddrMode ) { case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) *


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> gcc_assert ( producer && consumer ) ; dest = ia64_single_set ( producer ) ; gcc_assert ( dest ) ; reg = SET_DEST ( dest ) ; gcc_assert ( reg ) ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; gcc_assert ( GET_CODE ( reg ) == REG ) ; src = ia64_single_set ( consumer ) ; gcc_assert ( src ) ; mem = SET_SRC ( src ) ; gcc_assert ( mem ) ; if ( GET_CODE ( mem ) == UNSPEC && XVECLEN ( mem , <NUM_LIT> ) > <NUM_LIT> ) mem = XVECEXP ( mem , <NUM_LIT> , <NUM_LIT> ) ; else if ( GET_CODE ( mem ) == IF_THEN_ELSE ) { gcc_assert ( XINT ( XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_LDCCLR ) ; mem = XEXP ( mem , <NUM_LIT> ) ; } while ( GET_CODE ( mem ) == SUBREG || GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( mem ) == UNSPEC ) { int c = XINT ( mem , <NUM_LIT> ) ; gcc_assert ( c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A || c == UNSPEC_LDSA ) ; mem = XVECEXP ( mem , <NUM_LIT> , <NUM_LIT> ) ; } gcc_assert ( GET_CODE ( mem ) == LO_SUM ||


<s> if ( I != EnclosedInstrs . end ( ) ) { if ( I -> second != C . getID ( ) ) C . setAllIllegal ( ) ; return ; } EnclosedInstrs [ MI ] = C . getID ( ) ; C . addInstruction ( MI ) ; for ( int i = <NUM_LIT> ; i != NumDomains ; ++ i ) { if ( C . isLegal ( ( RegDomain ) i ) ) { InstrConverterBase * IC = Converters . lookup ( { i , MI -> getOpcode ( ) } ) ; if ( ! IC || ! IC -> isLegal ( MI , TII ) ) C


<s> unsigned <ISA_LIT>InstrInfo :: getInstBundleLength ( const MachineInstr * MI ) const { unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle ( ) && <STR_LIT> ) ; Size += GetInstSizeInBytes ( & * I ) ; } return Size


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val

& <NUM_LIT> ) == <NUM_LIT> ) || Val == INT32_MIN ;


<s> SDValue <ISA_LIT>TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned


<s> assert ( ( BaseOp1 . isReg ( ) || BaseOp1 . isFI ( ) ) && <STR_LIT> ) ; if ( NumLoads > <NUM_LIT> ) return false ; if ( ( BaseOp1 . isReg ( ) != BaseOp2 . isReg ( ) ) || ( BaseOp1 . isReg ( ) && BaseOp1 . getReg ( ) != BaseOp2 . getReg ( ) ) || ( BaseOp1 . isFI ( ) && BaseOp1 . getIndex ( ) != BaseOp2 . getIndex ( ) ) ) return false ; const MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( ! isClusterableLdStOpcPair ( FirstOpc , SecondOpc , Subtarget )


<s> static bool arm_bfi_p ( rtx x , rtx * sub0 , rtx * sub1 ) { if ( GET_CODE ( x ) != IOR ) return false ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != AND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != AND ) return false ; return ( arm_bfi_1_p ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , sub0 , sub1 ) || arm_bfi_1_p ( XEXP ( x , <NUM_LIT> ) , XEXP (


<s> vec_ushort8 bv ; bv = vec_splat ( ( vec_ushort8 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( bv , vec_splat_u16 ( <NUM_LIT>


<s> if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( Subtarget -> isFPOnlySP ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) .

getValueType ( ) , Op . getValueType ( ) ) ;


<s> if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , <NUM_LIT> ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , <NUM_LIT> ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result ,


<s> return ( from == GENERAL_REGS && from == to


<s> } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( )


<s> AARCH64_INIT_MEMTAG_BUILTINS_DECL ( IRG , irg , irg , fntype ) ; fntype = build_function_type_list ( uint64_type_node , ptr_type_node , uint64_type_node , NULL ) ; AARCH64_INIT_MEMTAG_BUILTINS_DECL ( GMI , gmi , gmi , fntype ) ; fntype = build_function_type_list ( ptrdiff_type_node , ptr_type_node , ptr_type_node , NULL ) ; AARCH64_INIT_MEMTAG_BUILTINS_DECL ( SUBP , subp , subp , fntype ) ; fntype = build_function_type_list ( ptr_type_node , ptr_type_node , unsigned_type_node , NULL ) ; AARCH64_INIT_MEMTAG_BUILTINS_DECL ( INC_TAG , inc_tag , addg , fntype ) ; fntype = build_function_type_list ( void_type_node , ptr_type_node , NULL ) ; AARCH64_INIT_MEMTAG_BUILTINS_DECL ( SET_TAG , set_tag , stg ,


<s> fprintf ( stream , <STR_LIT> , reg_names [ MMIX_STATIC_CHAIN_REGNUM ] ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream ,


<s> int pa_is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) ,

VOIDmode ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> return __builtin_mve_vrndmq_fv4sf ( __a )


<s> ri_gprmask = <NUM_LIT> ; ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = <NUM_LIT> ; ri_gp_value = <NUM_LIT> ; const MCRegisterInfo * TRI = Context . getRegisterInfo ( ) ; GPR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> )


<s> void printMemExtend ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printMemExtend ( MI , OpNum , O


<s> C . initLRU ( TRI ) ; if ( C . LRU . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerRegSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . UsedInSequence . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else { NumBytesNoStackCalls += SequenceSize ; } } if ( ! AllStackInstrsSafe || NumBytesNoStackCalls <= RepeatedSequenceLocs . size ( ) * <NUM_LIT> ) { RepeatedSequenceLocs = CandidatesWithoutStackFixups ; FrameID = MachineOutlinerNoLRSave ; } else { SetCandidateCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; } if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) { RepeatedSequenceLocs . clear ( ) ; return outliner :: OutlinedFunction ( ) ; } } if ( FlagsSetInAll & MachineOutlinerMBBFlags :: HasCalls ) { bool ModStackToSaveLR = false ; if ( std :: any_of ( FirstCand . front ( ) , FirstCand . back ( ) , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) ModStackToSaveLR = true ; else if ( FrameID != MachineOutlinerThunk && FrameID != MachineOutlinerTailCall && FirstCand . back ( ) -> isCall ( ) ) ModStackToSaveLR = true ; if ( ModStackToSaveLR ) { if ( ! AllStackInstrsSafe ) { RepeatedSequenceLocs . clear ( ) ; return outliner :: OutlinedFunction ( ) ; } NumBytesToCreateFrame += <NUM_LIT> ; } } return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize ,


<s> sigstk . ss_sp = xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( <STR_LIT> ) ; sigemptyset ( & sact . sa_mask ) ; sact . sa_flags = SA_ONSTACK | SA_SIGINFO ; sact . sa_sigaction =


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; auto PredTy = VT . getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = getPTrue ( DAG , DL


<s> tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , insn_dependent_p_1


<s> } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( Signed ) { if ( UseTraps ) { emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , Instructions ) ; return false ; } emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , Instructions ) ; return false ; } } unsigned BranchTargetNoTraps ; unsigned BranchTarget ; if ( UseTraps ) { BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , Instructions ) ; } else { BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; BranchTargetNoTraps = <NUM_LIT> ; emitRRI ( <STR_LIT> , RtReg , ZeroReg , BranchTargetNoTraps , IDLoc , Instructions ) ; } emitRR ( DivOp , RsReg , RtReg , IDLoc , Instructions ) ; if ( ! UseTraps ) emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , Instructions ) ; if ( ! Signed ) { emitR ( <STR_LIT> , RsReg , IDLoc , Instructions ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; emitRRI ( <STR_LIT> , ATReg , ZeroReg , - <NUM_LIT> , IDLoc , Instructions ) ; if ( Is<ISA_LIT>64


<s> if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , MAB , OS , Emitter , false ) ; if ( TheTriple . isOSWindows ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } return createELFStreamer ( Ctx , MAB , OS , Emitter , false


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) PointerSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; SupportsDebugInformation = true ; DwarfUsesInlineInfoSection = true


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat ( ) const { return Subtarget . useSoftFloat ( )


<s> __inline__ static unsigned long long sh_media_MCMV ( unsigned long long mm , unsigned long long mn , unsigned long long mw ) { unsigned long


<s> static enum reg_class rs6000_debug_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { enum reg_class ret = rs6000_secondary_reload_class ( rclass , mode , in ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , reg_class_names [ ret ] , reg_class_names [ rclass ] , GET_MODE_NAME ( mode ) ) ; debug_rtx ( in


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI . hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI . getLocalFrameSize ( ) < <NUM_LIT> ) return


<s> return ( vector signed int ) __builtin_altivec_vcmpeqfp ( ( vector float ) a1


<s> int <ISA_LIT>VSXSwapRemoval :: addSwapEntry ( MachineInstr * MI , <ISA_LIT>VSXSwapEntry & SwapEntry ) { SwapEntry . VSEMI = MI ; SwapEntry . VSEId = SwapVector . size


<s> initialize<ISA_LIT>BranchRelaxationPass ( * PassRegistry :: getPassRegistry


<s> addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg )


<s> emit_insn ( gen_rtx_SET ( dest , gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( <NUM_LIT> , pred , src


<s> if ( OpInfo . ConstraintVT . isVector ( ) || ! OpInfo . ConstraintVT . isInteger ( ) || OpInfo . ConstraintVT . getSizeInBits ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag . getNode ( ) ) { Flag = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Flag ) ; Chain = Flag . getValue ( <NUM_LIT> ) ; } else Flag = DAG . getCopyFromReg ( Chain ,


<s> case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; case <STR_LIT> : if ( FBB == nullptr ) { FBB = getFallThroughMBB ( & MBB , TBB ) ; assert ( FBB && <STR_LIT> <STR_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getImm ( )


<s> if ( format [ <NUM_LIT> ] == '*' && format [ <NUM_LIT> ] == 'q' ) { format += <NUM_LIT> ; return instance . elements_per_vq (


<s> if ( WinEH :: FrameInfo * CurFrame = getCurrentWinFrameInfo ( ) ) EHStreamer . EmitUnwindInfo ( * this , CurFrame


<s> } } assert ( Found && <STR_LIT> ) ; ( void ) Found ; } else { AsmRewrites . emplace_back ( AOK_Imm , BracLoc , <NUM_LIT> , FinalImmDisp ) ; } } for ( AsmRewrite & AR : AsmRewrites ) { if ( AR . Loc . getPointer ( ) < StartInBrac . getPointer ( ) ) continue ; if ( AR . Kind == AOK_ImmPrefix || AR . Kind == AOK_Imm ) AR . Kind = AOK_Delete ; } const char * SymLocPtr = SymName . data ( ) ; if ( unsigned Len = SymLocPtr - StartInBrac . getPointer ( ) ) { assert ( Len > <NUM_LIT> && <STR_LIT> ) ; AsmRewrites . emplace_back ( AOK_Skip , StartInBrac , Len


<s> MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand ( RD ) ; LEAInst . addOperand ( RS1 ) ; LEAInst . addOperand ( Imm ) ; OutStreamer . emitInstruction ( LEAInst


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return true ; } } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; Offset = N . getOperand ( <NUM_LIT> ) . getOperand (


<s> for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , Subtarget ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified = true ; createFPFnStub ( F , & M , V , Subtarget ) ; } } return Modified


<s> unsigned RotAmt = countLeadingZeros ( V ) ; if ( RotAmt >= <NUM_LIT> ) return - <NUM_LIT> ; if ( ( rotr32 ( <NUM_LIT> , RotAmt ) & V ) == V ) return ( rotr32 ( V , <NUM_LIT> - RotAmt ) &

<NUM_LIT> ) | ( ( RotAmt + <NUM_LIT> ) << <NUM_LIT> ) ;


<s> getBranchTargetOpValue1SImm16 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( ) , MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , FixupExpression , MCFixupKind ( <STR_LIT>


<s> return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; Name = <STR_LIT> ; getNameWithPrefix ( Name , GV ) ; return OutContext . getOrCreateSymbol ( Name ) ; } else if ( Subtarget -> isTargetELF ( ) ) { return getSymbol ( GV ) ; } llvm_unreachable ( <STR_LIT> )


<s> const char * <ISA_LIT>InstPrinter :: getRegisterName ( unsigned RegNo ) { return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT>


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( ArgRegsSaveSize ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ArgRegsSaveSize , MachineInstr :: FrameSetup ) ; CFAOffset -= ArgRegsSaveSize ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ( NumBytes - ArgRegsSaveSize ) , MachineInstr :: FrameSetup ) ; CFAOffset -= NumBytes - ArgRegsSaveSize ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . splitFramePushPop ( ) ) { GPRCS2Size += <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; } unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , & * std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size


<s> printAndVerify ( <STR_LIT> ) ; } if ( get<ISA_LIT>Subtarget ( ) . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } PM . add ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( )


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; return true


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand


<s> int64_t Imm = BBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand * DeadOrKillToUnset = nullptr ; if ( BBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { DeadOrKillToUnset = & BBI -> getOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * BBI << <STR_LIT> ) ; } for ( auto AfterBBI = std :: next ( BBI ) ; AfterBBI != MBB . instr_end ( ) ; ++ AfterBBI ) { int KillIdx = AfterBBI -> findRegisterUseOperandIdx ( Reg , true , TRI ) ; if ( KillIdx != - <NUM_LIT> && AfterBBI -> getOperand ( KillIdx ) . isImplicit ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( AfterBBI -> dump ( ) ) ; break ; } if ( KillIdx != - <NUM_LIT> ) { assert ( ! DeadOrKillToUnset && <STR_LIT> ) ; DeadOrKillToUnset = & AfterBBI -> getOperand ( KillIdx ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; } if ( ! AfterBBI -> modifiesRegister ( Reg , TRI ) ) continue ; if ( AfterBBI -> getOpcode ( ) != Opc ) break ; assert ( AfterBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! AfterBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) || AfterBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != Imm ) break ; if (


<s> void aarch64_asm_output_pool_epilogue ( FILE * f , const char *


<s> unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( MatchAddress ( N , AM ) ) return false ; if ( Subtarget -> isTargetNaCl64 ( ) ) { LegalizeAddressingModeForNaCl ( N , AM ) ; } EVT VT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT>


<s> return __builtin_mve_vcmulq_rot270_m_fv8hf ( __arm_vuninitializedq_f16 ( ) ,


<s> const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only

( ) ) return new <ISA_LIT>FastISel ( funcInfo , libInfo ) ;


<s> static inline unsigned getT1tRn ( uint32_t insn


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , <STR_LIT> , true ) ; return false ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MI -> getOperand ( OpNo ) . isReg ( ) ) return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ <NUM_LIT> ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : printOperand ( MI , OpNo , <STR_LIT> ) ; return false ; } } printOperand ( MI , OpNo )


<s> return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; loongarch_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = loongarch_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; } else if ( isInt < <NUM_LIT> > ( Val ) ) { llvm_unreachable ( <STR_LIT>


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_NONE : return <NUM_LIT> ; case FK_Data_1 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , MachineInstr :: mmo_iterator MMOBegin , MachineInstr :: mmo_iterator MMOEnd , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( The<ISA_LIT>_64Target


<s> static bool arm_default_short_enums (


MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( AM . Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; } return


<s> unsigned get<ISA_LIT>BranchTargetOpValue ( const MachineInstr & MI ,


<s> return __builtin_ia32_rsqrtph128_mask ( __B , _mm_setzero_ph ( ) ,


<s> WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += Half ) { unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ; Idx += <NUM_LIT> ; } } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; if ( VT . is64BitVector ( ) && EltSz


<s> const char * getPassName ( ) const override { return


<s> } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( Subtarget -> isTargetWin64 ( ) ) { CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; } CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = ( ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } if ( ! Subtarget -> is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; unsigned Reg = VA . getLocReg


<s> while ( ( ( unsigned ) Offset ) >= ( <NUM_LIT> << ShiftSize ) ) { unsigned ThisVal ; if ( ( ( unsigned ) Offset ) > MaxEncodableValue ) { ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI && SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ThisVal ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset ==


<s> const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned VRegSize = RegInfo . getMinimalPhysRegClass ( Dst ) -> getSize ( ) / <NUM_LIT> ; const TargetRegisterClass * RC = RegInfo . intRegClass ( VRegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc ) , VR0 ) . addReg ( Src ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , DstLo


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Register RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> MachineFunctionPass :: getAnalysisUsage


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) -> getAttributes (

) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_SaveList ;


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; MVT OpVT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool IsI1Vector = OpVT . getVectorElementType ( ) == <STR_LIT> ; SDLoc dl ( N ) ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( <STR_LIT> ( Vec . getNode ( ) ) ) { if ( <STR_LIT> ( SubVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , dl ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SubVec . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { unsigned Idx2Val = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( IdxVal + Idx2Val , dl ) ) ; } if ( SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> && SubVec . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && SubVec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Ins = SubVec . getOperand ( <NUM_LIT> ) ; if ( Ins . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ( Ins . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Ins . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) <= SubVecVT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT>

, dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , Ins . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_None ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ; case <STR_LIT> : return

MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF ;


<s> <ISA_LIT>LongBranchStub :: <ISA_LIT>LongBranchStub ( const uint32_t * pData , size_t pSize , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : m_pData ( pData ) , m_Name ( <STR_LIT> ) , m_Size ( pSize ) { for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) { addFixup ( *


<s> } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = <NUM_LIT> ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = <NUM_LIT> ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return


<s> static unsigned int rx_function_arg_boundary ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED ) { if ( TARGET_GCC_ABI ) return STACK_BOUNDARY ; if ( type ) { if ( DECL_P ( type ) ) return


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) ,


<s> if ( Dot == StringRef :: npos ) Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; else { if ( Name . startswith ( <STR_LIT> ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; int Cc = ConvertCcString ( Format ) ; if ( Cc == - <NUM_LIT> ) { return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex (


<s> Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , false , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , true , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( )


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( SVT == <STR_LIT> ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; } else { SmallVector < SDValue , <NUM_LIT> > ShOps = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG .

getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ;


<s> int ret = <NUM_LIT> ; int align_words ; if ( DEFAULT_ABI == ABI_V4 ) return <NUM_LIT> ; if ( USE_ALTIVEC_FOR_ARG_P ( cum , mode , type , named ) && cum -> nargs_prototype >= <NUM_LIT> ) return <NUM_LIT> ; if ( rs6000_darwin64_abi && mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) return <NUM_LIT> ; align_words = rs6000_parm_start ( mode , type , cum -> words ) ; if ( USE_FP_FOR_ARG_P ( cum , mode , type ) && ! ( type && ( cum -> nargs_prototype <= <NUM_LIT> || ( DEFAULT_ABI == ABI_AIX

&& TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) ) {


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm


<s> void setSRetReturnReg ( unsigned Reg ) { SRetReturnReg = Reg


<s> std :: unique_ptr < CSEConfigBase > <ISA_LIT>PassConfig :: getCSEConfig ( )


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , uint64_t required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! *


<s> if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned DivOpc ; bool Is64bit = ( DestVT == <STR_LIT> ) ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT>


<s> return false ; } const ArrayRef < MCPhysReg > GPR32ArgRegs = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const ArrayRef < MCPhysReg > FGR32ArgRegs = { <STR_LIT> , <STR_LIT> } ; const ArrayRef < MCPhysReg > AFGR64ArgRegs = { <STR_LIT> , <STR_LIT> } ; ArrayRef < MCPhysReg > :: iterator NextGPR32 = GPR32ArgRegs . begin ( ) ; ArrayRef < MCPhysReg > :: iterator NextFGR32 = FGR32ArgRegs . begin ( ) ; ArrayRef < MCPhysReg > :: iterator NextAFGR64 = AFGR64ArgRegs . begin ( ) ; struct AllocatedReg { const TargetRegisterClass * RC ; unsigned Reg ; AllocatedReg ( const TargetRegisterClass * RC , unsigned Reg ) : RC ( RC ) , Reg ( Reg ) { } } ; SmallVector < AllocatedReg , <NUM_LIT> > Allocation ; unsigned Idx = <NUM_LIT> ; for ( const auto & FormalArg : F -> args ( ) ) { if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Type * ArgTy = FormalArg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Idx - <NUM_LIT> ) << <STR_LIT> << ArgVT . getEVTString ( ) << <STR_LIT> ) ; if ( ! ArgVT . isSimple ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) && ! F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ZExt ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextGPR32 == GPR32ArgRegs . end ( ) ) { DEBUG ( dbgs ( ) <<


<s> static __inline qword si_nor ( qword a , qword b ) { return ( ( qword ) ( vec_nor ( ( vec_uchar16 ) ( a ) , ( vec_uchar16


<s> if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } } return false


<s> if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; if ( Subtarget -> is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT>


<s> rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS (