<s> unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( )


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return false ; return true


<s> assert ( ( Kind == k_MImmOp ) && <STR_LIT> ) ; return MImm .


<s> MachineOperand & Divisor = MI -> getOperand ( <NUM_LIT> ) ; MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; Divisor . setIsKill ( false


<s> static SDValue createStoreLR ( unsigned Opc , SelectionDAG & DAG , StoreSDNode * SD , SDValue Chain , unsigned Offset ) { SDValue Ptr = SD -> getBasePtr ( ) , Value = SD -> getValue ( ) ; EVT MemVT = SD -> getMemoryVT ( ) , BasePtrVT = Ptr . getValueType ( ) ; SDLoc DL ( SD ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , BasePtrVT ) ) ; SDValue Ops [ ] = { Chain , Value , Ptr } ; return DAG . getMemIntrinsicNode ( Opc , DL , VTList , Ops , <NUM_LIT>


<s> SMLoc getEndLoc ( ) const { return EndLoc


<s> } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> && ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address ,


<s> MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; BlockAddress * BA = BlockAddress :: get ( const_cast < Function * > ( MF . getFunction ( ) ) , const_cast < BasicBlock * > ( DestMBB -> getBasicBlock ( ) ) ) ; DestMBB -> setHasAddressTaken ( ) ; SDValue BlockPtr = DAG . getBlockAddress ( BA , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , ReturnReg , BlockPtr ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain

, DAG . getRegister ( ReturnReg , PtrVT ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printDecimal32 ( unsigned Value , raw_ostream & O ) { O << <STR_LIT> ; O << Value


<s> MCAsmParser & Parser = getParser ( ) ; AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { IsPicEnabled = false ; getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } return false ; } if ( Option == <STR_LIT> ) { IsPicEnabled = true ; getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { return Error ( Parser . getTok ( ) . getLoc (


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo ::


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return ParseMemOperand ( <NUM_LIT> , Parser . getTok ( ) . getLoc ( ) ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return nullptr ; if ( RegNo == <STR_LIT> ||


<s> if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return


<s> void addMemTBBOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI )


<s> __builtin_ia32_vfmaddss3_mask ( A , B , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_mask3 ( A , B , C , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_mask3 ( A , B , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_maskz ( A , B , C , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_maskz ( A , B , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_mask ( A , B , - ( C ) , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_mask ( A , B , - ( C ) , U , R ) ( __m128d ) __builtin_ia32_vfmsubsd3_mask3 ( A , B , C , U , R ) ( __m128 ) __builtin_ia32_vfmsubss3_mask3 ( A , B , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_maskz ( A , B , - ( C ) , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_maskz ( A , B , - ( C ) , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_mask ( A , - ( B ) , C , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_mask ( A , - ( B ) , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_mask3 ( A , - ( B ) , C , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_mask3 ( A , - ( B ) , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_maskz ( A , - ( B ) , C , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_maskz ( A , - ( B ) , C , U , R ) ( __m128d ) __builtin_ia32_vfmaddsd3_mask ( A , - ( B ) , - ( C ) , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_mask ( A , - ( B ) , - ( C ) , U , R ) ( __m128d ) __builtin_ia32_vfmsubsd3_mask3 ( A , - ( B ) , C , U , R ) ( __m128 ) __builtin_ia32_vfmsubss3_mask3 ( A , - ( B ) , C , U

, R ) ( __m128d ) __builtin_ia32_vfmaddsd3_maskz ( A , - ( B ) , - ( C ) , U , R ) ( __m128 ) __builtin_ia32_vfmaddss3_maskz ( A , - ( B ) , - ( C ) , U , R ) extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_comi_round_ss ( __m128 __A , __m128 __B , const int __P , const int __R ) {


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } if ( selectImpl ( I , CoverageInfo ) ) { return true ; } return


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetCRC


<s> real_2expN ( & TWO52r , fmt -> p - <NUM_LIT> , mode ) ; TWO52 = const_double_from_real_value ( TWO52r , mode ) ; TWO52 = force_reg ( mode ,


<s> RegisterTarget < Triple :: mmix > Y ( getThe<ISA_LIT>Target ( )


<s> uint64_t flags ( ) const { return llvm :: ELF


<s> return decodeRegisterClass ( Inst , RegNo


<s> SDValue Elt = DAG . getConstant ( Val , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ReqVT , Res


<s> assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & CCOp = MI . getOperand


<s> return TYPE_MODE ( type ) ; } else if ( ( ( size == <NUM_LIT> && TARGET_64BIT ) || size == <NUM_LIT> ) && ! TARGET_SSE && ! TARGET_IAMCU ) { static bool warnedsse ; static bool warnedsse_ret ; if ( cum && cum -> warn_sse && ! warnedsse ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse = true ; } else if ( ! TARGET_64BIT && in_return && ! warnedsse_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse_ret = true ; } } else if ( ( size == <NUM_LIT> && ! TARGET_64BIT ) && ( ! cfun || cfun -> machine -> func_type == TYPE_NORMAL ) && ! TARGET_MMX && ! TARGET_IAMCU ) { static bool warnedmmx ; static bool warnedmmx_ret ; if ( cum && cum -> warn_mmx && ! warnedmmx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedmmx = true ; } else if ( in_return && ! warnedmmx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedmmx_ret = true ; } } return mode ; } gcc_unreachable ( ) ; } } return


<s> if ( Subtarget . hasCMov ( ) ) if ( SDValue RV = combineIntegerAbs ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( isFNEG ( N ) ) return combineFneg


<s> bool <ISA_LIT>NamedImmMapper :: validImm ( uint32_t Value ) const { return Value <


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT>


<s> return symbol ; } note = find_reg_equal_equiv_note ( def_insn ) ; if ( note && GET_CODE ( XEXP ( note , <NUM_LIT> ) ) == SYMBOL_REF ) return XEXP ( note , <NUM_LIT> ) ; if ( recurse_p && REG_P ( src ) ) return mips_find_pic_call_symbol ( def_insn , src , false ) ; } return


<s> bool <ISA_LIT>InstructionSelector :: isWorthFoldingIntoExtendedReg ( MachineInstr & MI , const MachineRegisterInfo & MRI ) const { Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . hasOneUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasMinSize ( ) ) return true ; if ( ! STI . hasLSLFast ( ) ) return false ; return all_of ( MRI . use_instructions ( DefReg ) , [ ] ( MachineInstr

& Use ) { return Use . mayLoadOrStore ( ) ; } ) ;


<s> else if ( TARGET_X32_P ( ix86_isa_flags ) ) return <STR_LIT> ; else return


<s> } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( stdarg_p ( fntype ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( tsize > <NUM_LIT> ) { rtx tsize_rtx = GEN_INT ( tsize ) ; rtx adjustment_rtx , dwarf_pattern ; rtx_insn * insn ; if ( tsize > <NUM_LIT> ) { adjustment_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( adjustment_rtx , tsize_rtx ) ; } else adjustment_rtx = tsize_rtx ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , adjustment_rtx ) ) ; dwarf_pattern = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - tsize ) ) ; iq2000_annotate_frame_insn ( insn , dwarf_pattern ) ; save_restore_insns ( <NUM_LIT> ) ; if ( frame_pointer_needed ) { rtx_insn * insn = <NUM_LIT> ; insn = emit_insn ( gen_movsi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( insn ) RTX_FRAME_RELATED_P


<s> return __builtin_mve_vcmulq_fv4sf ( __a ,


<s> SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT>


<s> if ( Subtarget -> getProcFamily ( ) == <ISA_LIT>Subtarget :: Falkor && I . getMetadata ( FALKOR_STRIDED_ACCESS_MD ) !=


<s> iterator_range < const_edge_iterator > edges ( )


<s> else return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; Amount = <NUM_LIT> ; if ( St != <STR_LIT> ) { Loc = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) && HashTok . isNot ( AsmToken :: Dollar ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE ) return Error ( Loc , <STR_LIT> ) ; int64_t Imm = CE ->


<s> if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; Opc = getTargetVShiftUniformOpcode ( Opc , true ) ; if ( SVT == <STR_LIT> ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else if ( ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ( ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> || ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) ) { ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; MVT AmtTy = ShAmt . getSimpleValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , AmtTy , ShAmt ) ; if ( Subtarget . hasSSE41 ( ) ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else { SDValue ByteShift = DAG . getConstant ( ( <NUM_LIT> - AmtTy . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast ( <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( )


<s> if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp &


<s> FeatureBitset OldMode = STI . getFeatureBits ( ) & AllModes ; unsigned FB = ComputeAvailableFeatures ( STI . ToggleFeature ( OldMode . flip ( mode ) ) ) ; setAvailableFeatures ( FB )


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( DisableFramePointerElim ( MF ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer (


<s> case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG


<s> if ( Type == ELF :: R_MIPS_HI16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_HI16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_HI16 ) return ELF :: R_MIPS16_LO16 ; if ( Reloc . OriginalSymbol -> getBinding ( ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF


<s> unsigned RegNum ; OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! parseOptionalToken ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } parseOptionalToken ( AsmToken


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsSlowLEA = ST . slowLEA ( ) ; bool IsSlow3OpsLEA = ST . slow3OpsLEA ( ) ; bool LEAUsesAG = ST . LEAusesAG ( ) ; bool OptIncDec = ! ST . slowIncDec ( ) || MF . getFunction ( ) . hasOptSize ( ) ; bool UseLEAForSP = ST . useLeaForSP ( ) ; TSM . init ( & ST ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; auto * PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; auto * MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineBasicBlock & MBB : MF ) { bool OptIncDecPerBB = OptIncDec || llvm :: shouldOptimizeForSize ( & MBB , PSI , MBFI ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( WidthExpr , EndLoc ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( WidthExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Width = CE -> getValue ( ) ; if ( Width < <NUM_LIT> || Width > <NUM_LIT> - LSB ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBitfield ( LSB , Width , S , EndLoc ) ) ; return MatchOperand_Success


<s> SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( OrigArg . Ty -> isVoidTy ( ) ) return true ; EVT VT = SplitVTs [ <NUM_LIT> ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == <NUM_LIT> ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; } SmallVector < unsigned ,


<s> if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( )


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) ->


<s> static Optional < uint64_t > evaluateMemOpAddrForAddrModeT2_pc ( const MCInst & Inst , const MCInstrDesc & Desc ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> unsigned getThumbBRTargetOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGEOFF ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr


<s> static bool isLegalMaskCompare ( SDNode * N , const <ISA_LIT>Subtarget * Subtarget ) { unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Opcode == <STR_LIT> ) OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true


<s> SDValue TOCOff = DAG . getIntPtrConstant ( TOCAnchorOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( RegVT , dl , LDChain , AddTOC , MPI . getWithOffset ( TOCAnchorOffset ) , Alignment , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( EnvPtrOffset , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , RegVT , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( RegVT , dl , LDChain , AddPtr , MPI . getWithOffset ( EnvPtrOffset ) , Alignment , MMOFlags ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , TOCReg , TOCPtr , Glue ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; Glue = TOCVal . getValue ( <NUM_LIT> ) ; assert ( ( ! hasNest || ! Subtarget . isAIXABI ( ) ) && <STR_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , EnvPtrReg , LoadEnvPtr , Glue ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; Glue = EnvVal . getValue


<s> unsigned OffsetsElemCount = cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ; assert ( Ty -> getNumElements ( ) == OffsetsElemCount ) ; ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ; if ( ZextOffs ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; FixedVectorType * OffsetType = cast < FixedVectorType > ( Offsets -> getType ( ) ) ; if ( ! ZextOffs || cast < FixedVectorType > ( ZextOffs -> getDestTy ( ) ) -> getElementType ( ) -> getScalarSizeInBits

( ) != <NUM_LIT> ) if ( ! checkOffsetSize ( Offsets , OffsetsElemCount ) ) return nullptr ;


<s> return ( __m128 ) __builtin_ia32_subps ( ( __v4sf )


<s> if ( ! Subtarget -> isThumb ( ) ) return <STR_LIT> ( AbsImm ) != - <NUM_LIT> ; if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> ( AbsImm ) !=


<s> bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; const TargetMachine & TM = F . getTarget ( ) ; MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; TII = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; RCI . runOnMachineFunction ( F


<s> case Instruction :: Store : return selectStore ( I ) ; case Instruction :: SDiv : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: UDiv : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I )


<s> SDValue PermMask = Op . getOperand ( <NUM_LIT> ) ; if ( V2 . getOpcode ( ) == <STR_LIT> ) { if ( <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> ) || <STR_LIT> ( PermMask . getNode ( ) , true ) || <STR_LIT> ( PermMask . getNode ( ) , true ) || <STR_LIT> ( PermMask . getNode ( ) , true ) != - <NUM_LIT> || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , true ) ) { return Op ; } } if ( <STR_LIT> ( PermMask . getNode ( ) , false ) || <STR_LIT> ( PermMask . getNode ( ) , false ) || <STR_LIT> ( PermMask . getNode ( ) , false ) != - <NUM_LIT> || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) || <STR_LIT> ( PermMask . getNode ( ) , <NUM_LIT> , false ) ) return Op ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT>


<s> static bool pa_can_eliminate ( const int from , const int to ) { if ( TARGET_64BIT && from == ARG_POINTER_REGNUM ) return false ; return ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed :


<s> for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return


<s> bool anyregs = false ; for ( TargetRegisterClass :: const_iterator I = <STR_LIT> . begin ( ) , E = <STR_LIT> . end ( ) ; I != E ; ++ I ) if ( MF -> getRegInfo ( ) . isPhysRegUsed ( * I ) ) { anyregs = true ; break ; } if ( ! anyregs ) return false ; MachineBasicBlock * Entry = MF -> begin ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > DFI = df_ext_begin ( Entry , Visited ) , DFE = df_ext_end ( Entry , Visited ) ; DFI != DFE ; ++ DFI ) { MBB = * DFI ; enterBasicBlock ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { MachineInstr * mi = I ; if ( mi -> isDebugValue ( ) ) continue ; ++ Distance ; std :: pair < uint16_t , uint16_t > domp = TII -> GetSSEDomain ( mi ) ; if ( domp . first ) if ( domp . second ) visitSoftInstr ( mi , domp . second ) ; else visitHardInstr ( mi , domp . first ) ; else if ( LiveRegs ) visitGenericInstr ( mi ) ; } if ( LiveRegs ) LiveOuts . insert ( std :: make_pair ( MBB , LiveRegs ) ) ; LiveRegs = <NUM_LIT> ; } for ( LiveOutMap :: const_iterator i = LiveOuts . begin ( ) , e = LiveOuts . end ( ) ; i != e ; ++ i ) delete [ ] i -> second ; LiveOuts . clear ( ) ; Avail . clear ( ) ; Allocator . DestroyAll (


<s> return sh_recog_treg_set_expr_reent_count >


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI ->


<s> case CPU_SUBTYPE_POWERPC_602 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603e : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603ev : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_604 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_604e : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_620 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_750 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_7400 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_7450 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_970 : return <STR_LIT> ; default


<s> const struct toc_hash_struct * thc = ( const struct toc_hash_struct * ) hash_entry ; return rs6000_hash_constant ( thc -> key ) ^ thc ->


<s> return <NUM_LIT> ; case <STR_LIT> : return Emiti1Ext ( SrcReg , DestVT , isZExt ) ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; } if ( DestVT == <STR_LIT> || DestVT == <STR_LIT>


<s> if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) &


<s> else return ( is<ISA_LIT>SOImm ( ) || is<ISA_LIT>SOImmNeg


<s> if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Branch24Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_ThumbBranch22Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_ThumbBranch22Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Half ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Half ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Half ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Half


<s> rtvec r = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( r , <NUM_LIT> ) = reg ; RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } else for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn (


<s> insertDefsUses ( Slot , RegDefs , RegUses ) ; bool SawLoad = false ; bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; MachineBasicBlock :: instr_iterator FI = I . getReverse ( ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> isPseudo ( ) ) break ; if ( delayHasHazard ( FI , SawLoad , SawStore , RegDefs , RegUses ) ) { insertDefsUses ( FI , RegDefs , RegUses ) ; continue ; } Filler = FI ; return true


<s> emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , <NUM_LIT> ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , cond , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x


<s> auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl


<s> return Kind == k_FPImm && ( getFPImm ( ) == ( unsigned ) -


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI ,


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine (


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) ; MachineIRBuilder MIB ( MI ) ; const APFloat & ImmValAPF = MI . getOperand ( <NUM_LIT> ) . getFPImm


( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > DefSrcs ; if ( ! Register :: isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; Register DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { MRI -> constrainRegClass ( NewReg , MRI -> getRegClass ( ( * I ) -> getReg ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << printReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg (


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = <NUM_LIT> ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC ->


<s> bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX (


<s> static std :: string computeDataLayout ( StringRef TT , StringRef CPU , const TargetOptions & Options , bool isLittle ) { const Triple Triple ( TT ) ; auto ABI = computeTargetABI ( Triple , CPU , Options ) ; std :: string Ret


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= <NUM_LIT> ? AtomicExpansionKind :: LLSC :


<s> OptimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; MinimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return


<s> case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } if ( ! ( rs6000_default_cpu && rs6000_default_cpu [ <NUM_LIT> ] ) && ! global_options_set . x_rs6000_cpu_index ) { fputs ( <STR_LIT> , asm_out_file ) ; if ( ( rs6000_isa_flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> ,


<s> return ( __m64 ) __builtin_arm_wsubbus ( ( __v8qi ) __m1 ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue V = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> ,


<s> bool branch_if ; if ( GET_CODE ( cond ) == NE && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = true ; else if ( GET_CODE ( cond ) == EQ && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = false ; else gcc_unreachable ( ) ; if ( branch_target_bb == BRANCH_EDGE ( cbranch_insn_bb ) -> dest ) return branch_if ; else if ( branch_target_bb == FALLTHRU_EDGE ( cbranch_insn_bb ) -> dest ) return ! branch_if ; else gcc_unreachable (


<s> SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned N0Opc = N0 -> getOpcode ( ) , N1Opc = N1 -> getOpcode ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == <STR_LIT> && N1Opc == <STR_LIT> ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; if ( N00VT == N10 . getValueType ( ) && ( N00VT == <STR_LIT> || N00VT == <STR_LIT> ) && N00VT . getScalarSizeInBits ( ) == <NUM_LIT> * VT . getScalarSizeInBits ( ) ) { MVT MidVT = ( N00VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( MidVT . getVectorNumElements ( ) ) ; for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == N1Opc && ( N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> ) ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal ( <NUM_LIT>


<s> if ( poly_int_rtx_p ( x , & offset ) ) return aarch64_offset_temporaries ( false , offset ) <= <NUM_LIT> ; x = strip_offset ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > <NUM_LIT> ) return false ; if ( maybe_ne ( offset , <NUM_LIT> ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x )


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i *


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( MF . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ; nextOffset += FrameOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstFrameOffset ) ; return DAG . getStore ( thirdStore , dl , FR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false ,


<s> } if ( TARGET_LONG_DOUBLE_128 ) { if ( ! TARGET_IEEEQUAD ) init_float128_ibm ( TFmode


<s> return ( __m128i ) __builtin_ia32_maskloadq ( ( const __v2di *


<s> Decrement ? -- First : ++ First ; if ( First == Last ) break ; if ( First -> isDebugInstr ( ) ) continue ; if ( isSuitableAluInstr ( IsSpls , First , * Base , * Offset ) ) { return First ; } if ( First != Last


<s> switch ( MachineRelTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT>


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> Barrier . Data = Str .


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit


<s> return ( __m128h ) __builtin_ia32_vfcmulcsh_mask_round ( ( __v8hf ) __B , (


<s> APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG ) ; TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Op1 , DemandedMask ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne

, TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ;


<s> static bool isInt32Immediate ( SDValue N , unsigned & Imm ) { return isInt32Immediate ( N . getNode ( ) , Imm


<s> return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand


<s> bool Filler :: findDelayInstr ( MachineBasicBlock & MBB , MachineBasicBlock :: instr_iterator slot , MachineBasicBlock :: instr_iterator & Filler ) { SmallSet < unsigned , <NUM_LIT> > RegDefs ; SmallSet < unsigned , <NUM_LIT> > RegUses ; insertDefsUses ( slot , RegDefs , RegUses ) ; bool sawLoad = false ; bool sawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I ( slot ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: instr_iterator FI ( llvm :: next (


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { StackAlignment = <NUM_LIT> ; DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false


<s> if ( AllVisited . count ( & I ) ) continue ; if ( isa < ICmpInst > ( I ) ) { auto & CI = cast < ICmpInst > ( I ) ; if ( CI . isSigned ( ) || ! isa < IntegerType > ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) ) ) continue ; for ( auto & Op : CI . operands ( ) ) { if ( auto * I = dyn_cast < Instruction > ( Op ) ) MadeChange |= TryToPromote ( I ) ; } } } Promoter -> Cleanup ( ) ; LLVM_DEBUG ( if ( verifyFunction ( F , & dbgs ( ) ) ) { dbgs ( ) ; report_fatal_error ( <STR_LIT> )


<s> switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; } int VScale = <NUM_LIT> ; if ( Opc == <STR_LIT> ) VScale = <NUM_LIT> ; else if ( Opc == <STR_LIT> ) VScale = <NUM_LIT> ; const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; Register TmpReg = DestReg ; if ( TmpReg == <STR_LIT> ) TmpReg = MBB . getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; do { uint64_t ThisVal = std :: min < uint64_t > ( Offset , MaxEncodableValue ) ; unsigned LocalShiftSize = <NUM_LIT> ; if ( ThisVal > MaxEncoding ) { ThisVal = ThisVal >> ShiftSize ; LocalShiftSize = ShiftSize ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; Offset -= ThisVal << LocalShiftSize ; if ( Offset == <NUM_LIT> ) TmpReg = DestReg ; auto MBI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , TmpReg ) . addReg ( SrcReg ) . addImm ( Sign * ( int ) ThisVal ) ; if ( ShiftSize ) MBI = MBI . addImm ( <STR_LIT> ( <STR_LIT> , LocalShiftSize ) ) ; MBI = MBI . setMIFlag ( Flag ) ; auto Change = VScale == <NUM_LIT> ? StackOffset :: getFixed ( ThisVal << LocalShiftSize ) : StackOffset :: getScalable ( VScale * ( ThisVal << LocalShiftSize ) ) ; if ( Sign == - <NUM_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) CFAOffset += Change ; else CFAOffset -= Change ; if ( EmitCFAOffset &&


<s> printOperand ( MI , Op , O ) ; O << <STR_LIT> ; O << markup (


<s> gcc_assert ( i == <NUM_LIT> ) ; * factor = <NUM_LIT> ; * offset = <NUM_LIT> ; return AARCH64_DWARF_VG


<s> int index = - <NUM_LIT> ; if ( post_update_insn_p ( producer ) ) index = - <NUM_LIT> ; rtx last_two_def_reg = extract_nth_access_reg ( producer ,


<s> address = XEXP ( address , <NUM_LIT> ) ; if ( GET_CODE ( address ) == PLUS ) address = XEXP ( address , <NUM_LIT> ) ; address = XVECEXP ( address , <NUM_LIT>


<s> bool <ISA_LIT>InstructionSelector :: buildUnalignedStore ( MachineInstr & I , unsigned Opc , MachineOperand & BaseAddr , unsigned Offset , MachineMemOperand * MMO ) const { MachineInstr * NewInst = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opc ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( BaseAddr ) . addImm ( Offset ) . addMemOperand ( MMO ) ; if ( ! constrainSelectedInstRegOperands ( * NewInst , TII , TRI , RBI ) ) return false ; return


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> << <STR_LIT> << MF . getFrameInfo ( ) . getObjectAlignment ( FrameIndex ) << <STR_LIT> ) ; eliminateFI ( MI , FIOperandNum , FrameIndex


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) ,


<s> return ( int64x2_t ) __builtin_aarch64_ssri_nv2di (


<s> else if ( TheTriple . isOSBinFormatCOFF ( ) ) MAI = new <ISA_LIT>MCAsmInfoCOFF ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; MAI = new <ISA_LIT>MCAsmInfoELF ( TheTriple ) ; } unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects (


<s> <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugInstr ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; Register NPredReg ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( ( NCC ^ CC ) & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , ++ LastITMI -> getIterator ( ) ) ; Modified = true ; ++ NumITs


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( Size == <NUM_LIT> && <STR_LIT> ) ; auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , <NUM_LIT> ) ; MIRBuilder . buildLoad ( ValVReg ,


<s> rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , IsVarArg , MF , TM , RetLocs , * DAG . getContext ( ) ) ; RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ; unsigned Reg = VA .


<s> } } if ( Subtarget -> isThumb1Only ( ) ) { SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) ==


<s> assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get

( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> static const unsigned * findNextOrderedReg ( const unsigned * CurrentReg , SmallSet < unsigned ,

SetSize > & EnabledRegs , const unsigned * OrderEnd ) {


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return S ; } if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address ,


<s> return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering


<s> MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ; TmpInst . setOpcode (


<s> return MatchOperand_ParseFail ; } break ; case BDXMem : if ( HaveReg1 ) { if ( parseAddressRegister ( Reg1 ) ) return MatchOperand_ParseFail ; if ( HaveReg2 ) Index = Regs [ Reg1 . Num ] ; else Base = Regs [ Reg1 . Num ] ; } if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDLMem : if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( HaveReg1 && HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDRMem : if ( ! HaveReg1 || Reg1 . Group != RegGR ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LengthReg = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDVMem : if ( ! HaveReg1 || Reg1 . Group != RegV ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = <STR_LIT> [ Reg1 . Num ]


<s> vrev32q_p16 ( poly16x8_t a ) { return __builtin_shuffle ( a , ( uint16x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> SDLoc dl ( N ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * TRI . legalclasstypes_begin ( * RC ) ; auto MMOs = extractLoadMMOs ( cast < MachineSDNode > ( N ) -> memoperands ( ) , MF ) ; if ( MMOs . empty ( ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load ) , MMOs ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC


<s> bool <ISA_LIT>TTIImpl :: isTypeLegal ( Type * Ty ) { return


<s> case <STR_LIT> : if ( Subtarget . hasE2 ( ) ) return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; else return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitSelectPseudo ( MI ,


<s> const llvm :: <STR_LIT> * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF


<s> cumulative_args_t args_so_far ; tree arg_type , fntype ; bool using_r4 , first_param = true ; function_args_iterator args_iter ; uint32_t padding_bits_to_clear [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; uint32_t * padding_bits_to_clear_ptr = & padding_bits_to_clear [ <NUM_LIT> ] ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( ! CALL_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , <NUM_LIT> ) > <NUM_LIT> ) ; call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; unspec = XEXP ( call , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) != UNSPEC || XINT ( unspec , <NUM_LIT> ) != UNSPEC_NONSECURE_MEM ) continue ; to_clear_mask = ( <NUM_LIT> << ( NUM_ARG_REGS ) ) - <NUM_LIT> ; maxregno = NUM_ARG_REGS - <NUM_LIT> ; if ( TARGET_HARD_FLOAT_ABI ) { float_mask = ( <NUM_LIT> << ( D7_VFP_REGNUM + <NUM_LIT> ) ) - <NUM_LIT> ; float_mask &= ~ ( ( <NUM_LIT> << FIRST_VFP_REGNUM ) - <NUM_LIT> ) ; to_clear_mask |= float_mask ; maxregno = D7_VFP_REGNUM ; } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; to_clear_mask &= ~ ( <NUM_LIT> << REGNO ( XEXP ( address , <NUM_LIT> ) ) ) ; set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( )


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable (


<s> if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ RegClassID ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> static void setRequiredFeatureString ( FeatureBitset FBS , std :: string & Str ) { if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { auto ext = std :: find_if ( std :: begin ( ExtensionMap ) , std :: end

( ExtensionMap ) , [ & ] ( const Extension & e ) {


<s> case IC_MINUS : Val = Op1 . second - Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_MULTIPLY : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = Op1 . second * Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_DIVIDE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; assert ( Op2 . second != <NUM_LIT> && <STR_LIT> ) ; Val = Op1 . second / Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; } } } assert ( OperandStack . size ( ) == <NUM_LIT> && <STR_LIT> ) ; return OperandStack . pop_back_val ( )


<s> MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , <NUM_LIT> , TRI , * ( MBB -> getParent ( ) ) ) ) ; MachineInstr * NewLoad = BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LoadDisp ) . addReg ( <STR_LIT> ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; if ( LoadBase . isReg ( ) ) getBaseOperand ( NewLoad ) . setIsKill ( false ) ; LLVM_DEBUG ( NewLoad -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; auto PrevInstrIt = skipDebugInstructionsBackward ( std :: prev ( MachineBasicBlock :: instr_iterator ( StoreInst ) ) , MBB -> instr_begin ( ) ) ; if ( PrevInstrIt . getNodePtr ( ) == LoadInst ) StInst = LoadInst ; MachineInstr * NewStore = BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT>

) . addImm ( StoreDisp ) . addReg ( <STR_LIT> ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ;


<s> unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler


<s> static inline uint64_t ror ( uint64_t elt , unsigned


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit


<s> OS << <ISA_LIT>CondCodeToString ( getCondCode ( ) ) ; break ; case CCOut : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case Immediate : getImm ( ) -> print ( OS ) ; break ; case Memory : OS << <STR_LIT> ; break ; case Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case RegisterList


<s> const MCExpr * Expr = <NUM_LIT> ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ;


<s> if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: insertS<ISA_LIT>Declarations ( M


<s> if ( GET_CODE ( op1 ) != CONST_INT ) { sparc_emit_set_symbolic_const64 ( op0 , op1 , temp ) ; return ; } if ( ! temp ) temp = gen_reg_rtx ( DImode ) ; high_bits = ( ( INTVAL ( op1 ) >> <NUM_LIT> ) & <NUM_LIT> ) ; low_bits = ( INTVAL ( op1 ) & <NUM_LIT> ) ; analyze_64bit_constant ( high_bits , low_bits , & highest_bit_set , & lowest_bit_set , & all_bits_between_are_set ) ; if ( ( ( highest_bit_set == <NUM_LIT> || lowest_bit_set == <NUM_LIT> ) && all_bits_between_are_set != <NUM_LIT> ) || ( ( highest_bit_set - lowest_bit_set ) < <NUM_LIT> ) ) { HOST_WIDE_INT the_const = - <NUM_LIT> ; int shift = lowest_bit_set ; if ( ( highest_bit_set != <NUM_LIT> && lowest_bit_set != <NUM_LIT> ) || all_bits_between_are_set == <NUM_LIT> ) { the_const = create_simple_focus_bits ( high_bits , low_bits , lowest_bit_set , <NUM_LIT> ) ; } else if ( lowest_bit_set == <NUM_LIT> ) shift = - ( <NUM_LIT> - highest_bit_set ) ; gcc_assert ( SPARC_SIMM13_P ( the_const ) ) ; gcc_assert ( shift != <NUM_LIT> ) ; emit_insn ( gen_safe_SET64 ( temp , the_const ) ) ; if ( shift > <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , temp , GEN_INT ( shift ) ) ) ) ; else if ( shift < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LSHIFTRT ( DImode , temp , GEN_INT ( - shift ) ) ) ) ; return ; } if ( ( highest_bit_set - lowest_bit_set ) < <NUM_LIT> ) { unsigned HOST_WIDE_INT focus_bits = create_simple_focus_bits ( high_bits , low_bits , lowest_bit_set , <NUM_LIT> ) ; gcc_assert ( SPARC_SETHI_P ( focus_bits ) ) ; gcc_assert ( lowest_bit_set != <NUM_LIT> ) ; emit_insn ( gen_safe_HIGH64 ( temp , focus_bits ) ) ; if ( lowest_bit_set < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LSHIFTRT ( DImode , temp , GEN_INT ( <NUM_LIT> - lowest_bit_set ) ) ) ) ; else if ( lowest_bit_set > <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , temp

, GEN_INT ( lowest_bit_set - <NUM_LIT> ) ) ) ) ;


<s> Val = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( ST -> isThumb1Only ( ) ) { if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT>


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , MemTy , commonAlignment ( STI . getStackAlignment ( ) , LocMemOffset ) ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != nullptr ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize


<s> } else if ( CopyVT == <STR_LIT> && ( Is64Bit && ! Subtarget . hasSSE2 ( ) ) ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; VA . convertToReg ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Val = getv64i1Argument ( VA , RVLocs [ ++ I ] , Chain , DAG , dl , Subtarget , & InFlag ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( )

, Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc ,


<s> break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName ,


<s> SDNode * N = Op . getNode ( ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Value = N -> getOperand ( <NUM_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNum , SMLoc Start , SMLoc End ) { auto Op = make_unique < <ISA_LIT>Operand > (


<s> rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; return gw_consumed_by_ex_dep_p ( consumer ,


<s> static tree build_const_pointer ( tree t


<s> return ( __m512h ) __builtin_ia32_vfmaddcph512_maskz_round ( ( __v32hf ) __B , ( __v32hf ) __C , (


<s>
assert
(
CSRegs
[
i
+
<NUM_LIT>
]
&&
<STR_LIT>
)
;
const
unsigned
OddReg
=
CSRegs
[
i
]
;
const
unsigned
EvenReg
=
CSRegs
[
i
+
<NUM_LIT>
]
;
assert
(
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
^
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
&&
<STR_LIT>
)
;
const
bool
OddRegUsed
=
SavedRegs
.
test
(
OddReg
)
;
const
bool
EvenRegUsed
=
SavedRegs
.
test
(
EvenReg
)
;
if
(
!
OddRegUsed
&&
!
EvenRegUsed
)
{
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
UnspilledCSGPRs
.
push_back
(
OddReg
)
;
UnspilledCSGPRs
.
push_back
(
EvenReg
)
;
}
else
{
UnspilledCSFPRs
.
push_back
(
OddReg
)
;
UnspilledCSFPRs
.
push_back
(
EvenReg
)
;
}
continue
;
}
unsigned
Reg
=
<STR_LIT>
;
if
(
OddRegUsed
^
EvenRegUsed
)
{
Reg
=
OddRegUsed
EvenReg
:
OddReg
;
SavedRegs
.
set
(
Reg
)
;
}
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
OddReg
,
RegInfo
)
)
;
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
EvenReg
,
RegInfo
)
)
;
assert
(
(
(
OddReg
==
<STR_LIT>
&&
EvenReg
==
<STR_LIT>
)
||
(
RegInfo
->
getEncodingValue
(
OddReg
)
+
<NUM_LIT>
==
RegInfo
->
getEncodingValue
(
EvenReg
)
)
)
&&
<STR_LIT>
)
;
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
NumGPRSpilled
+=
<NUM_LIT>
;
if
(
Reg
!=
<STR_LIT>
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
ExtraCSSpill
=
true
;
}
else
NumFPRSpilled
+=
<NUM_LIT>
;
CanEliminateFrame
=
false
;
}
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
MFI
->
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
(
NumGPRSpilled
+
NumFPRSpilled
)
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
&&
!
ExtraCSSpill
)
{
assert
(
(
(
UnspilledCSGPRs
.
size
(
)
&
<NUM_LIT>
)
==
<NUM_LIT>
)
&&
<STR_LIT>
)
;
unsigned
Count
=
<NUM_LIT>
;
while
(
!
UnspilledCSGPRs
.
empty
(
)
&&
Count
<
<NUM_LIT>
)
{
unsigned
Reg
=
UnspilledCSGPRs
.
back
(
)
;
UnspilledCSGPRs
.
pop_back
(
)
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
PrintReg
(
Reg
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
Reg
)
;
ExtraCSSpill
=
true
;
++
Count
;
}
if
(
!
ExtraCSSpill
)
{
const
TargetRegisterClass
*
RC
=
&
<STR_LIT>


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) )


<s> std :: vector < Value * > AsmArgs ; FunctionType * AsmFTy = FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes , false ) ; InlineAsm * IA = InlineAsm :: get ( AsmFTy , AsmText , <STR_LIT> , true , false , InlineAsm :: AD_ATT ) ; CallInst :: Create ( IA , AsmArgs ,


<s> if ( ! REG_P ( addr ) ) return <NUM_LIT> ; if ( REGNO ( addr ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( ( TARGET_THUMB || ! frame_pointer_needed ) && REGNO ( addr ) == SP_REGNUM ) return <NUM_LIT> ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && REGNO ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == REGNO ( addr ) && GET_CODE ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM && CONST_INT_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) { value = INTVAL ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; } } if ( value == <NUM_LIT> ) { debug_rtx ( addr ) ; warning ( <NUM_LIT> , <STR_LIT> ) ; value = <NUM_LIT> ; } return


<s> if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) &&

! IsCCallConvention ( CalleeCC ) ) return false ;


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE ->


<s> bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else { HOST_WIDE_INT caller_isa ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; HOST_WIDE_INT callee_isa = callee_opts -> x_rs6000_isa_flags ; HOST_WIDE_INT explicit_isa = callee_opts -> x_rs6000_isa_flags_explicit ; if ( caller_tree ) caller_isa = TREE_TARGET_OPTION ( caller_tree ) -> x_rs6000_isa_flags ; else caller_isa = rs6000_isa_flags ; cgraph_node * callee_node = cgraph_node :: get ( callee ) ; if ( ipa_fn_summaries && ipa_fn_summaries -> get ( callee_node ) != NULL ) { unsigned int info = ipa_fn_summaries -> get ( callee_node )


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineMemOperand * MMO = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; return DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N ->

getOperand ( <NUM_LIT> ) } , N -> getSimpleValueType ( <NUM_LIT> ) , MMO ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo


<s> void <ISA_LIT>CmovConverterPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU


<s> int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlign ( FrameIndex ) . value ( ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI

-> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ;


<s> auto * IntrI = dyn_cast < IntrinsicInst > ( BitCast -> getOperand ( <NUM_LIT> ) ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; if ( ! isa < UndefValue > ( IntrI -> getOperand ( <NUM_LIT> ) ) || ! cast < ConstantInt > ( IntrI -> getOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return false ; auto * Load = dyn_cast < LoadInst > ( IntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! Load || ! Load -> isSimple ( ) ) return false ; if ( Load -> getType (


<s> O << <STR_LIT> ; printSrcIdx ( MI , OpNo , O


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const

MCAsmLayout * Layout , const MCFixup * Fixup ) const {


<s> assert ( Value == <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> O << ( int ) MI -> getOperand ( OpNo ) . getImm


<s> if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy


<s> else rc = reverse_condition ( rc ) ; } if ( XEXP ( cmp , <NUM_LIT> ) == const0_rtx && GET_CODE ( XEXP ( cmp , <NUM_LIT> ) ) == REG && cmp_mode == DImode && v9_regcmp_p ( rc ) ) cc_reg = XEXP ( cmp , <NUM_LIT> ) ; else cc_reg = gen_compare_reg_1 ( rc , XEXP ( cmp , <NUM_LIT> ) , XEXP ( cmp , <NUM_LIT> ) ) ; cmp = gen_rtx_fmt_ee ( rc , GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_IF_THEN_ELSE ( mode , cmp


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; return static_cast < <ISA_LIT>TargetStreamer & >


<s> RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg2 ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { MBB . addLiveIn ( Reg2


<s> ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; return


<s> static SDValue tryAdvSIMDModImm8 ( unsigned NewOp , SDValue Op , SelectionDAG & DAG , const APInt & Bits ) { if ( Bits . getHiBits ( <NUM_LIT> ) == Bits . getLoBits ( <NUM_LIT> ) ) { uint64_t Value = Bits . zextOrTrunc ( <NUM_LIT> ) . getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( Value ) ) { Value = <STR_LIT> ( Value ) ; SDLoc dl ( Op ) ; SDValue Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } } return SDValue ( )


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetIOS ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( &


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; unsigned VL = N -> getValueType ( <NUM_LIT> )


<s> FunctionPass * llvm :: create<ISA_LIT>DelaySlotFillerPass (


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo

( ) , false , false , false , <NUM_LIT> ) ;


<s> else return NULL ; if ( TM . getTargetData ( ) -> isBigEndian ( ) ) std :: swap ( Offset0 , Offset1 ) ; SDNode * LD0 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Offset0 , Base , Chain ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; SDValue I0 = CurDAG -> getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , Undef , SDValue ( LD0 , <NUM_LIT> ) ) ; SDNode * LD1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Offset1 , Base , SDValue ( LD0 , <NUM_LIT> ) ) ; SDValue I1 = CurDAG -> getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , I0 , SDValue ( LD1 , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , I1 ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Chain ) ; cast < MachineSDNode > ( LD0 ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; cast < MachineSDNode > ( LD1 ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; return I1 . getNode (