<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> } MCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; MCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; MCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; MCE . emitByte ( <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; MCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; MCE . emitByte ( <NUM_LIT> ) ; MCE . emitWordLE ( ( intptr_t ) Fn - MCE . getCurrentPCValue


<s> if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else { MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; } return true ; } else if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> :


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void *


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case E_DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable (


<s> First = false ; dbgs ( ) << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) , <NUM_LIT> , MRI ) ; } dbgs ( ) << <STR_LIT> <<


<s> void <ISA_LIT>FastTileConfig :: rewriteTileCfg ( SmallVector < MachineOperand * > & ShapedTiles , std :: map < unsigned , MachineInstr * > & RowCfgs , std :: map < unsigned , MachineInstr * > & ColCfgs ) { assert ( ( RowCfgs . size ( ) == ShapedTiles . size ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = ShapedTiles . size ( ) ; I < E ; I ++ ) { MachineOperand * MO = ShapedTiles [ I ] ; unsigned TmmIdx = getTilePhysRegIdx (


<s> if ( ! MulConstantOptimization ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; if ( isPowerOf2_64 ( C -> getZExtValue ( ) ) ) return SDValue ( ) ; int64_t SignMulAmt = C -> getSExtValue ( ) ; assert ( SignMulAmt != INT64_MIN && <STR_LIT> ) ; uint64_t AbsMulAmt = SignMulAmt < <NUM_LIT> ? - SignMulAmt : SignMulAmt ; SDLoc DL ( N ) ; if ( AbsMulAmt == <NUM_LIT> || AbsMulAmt == <NUM_LIT> || AbsMulAmt == <NUM_LIT> ) { SDValue NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( AbsMulAmt , DL , VT ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; return NewMul ; } uint64_t MulAmt1 = <NUM_LIT> ; uint64_t MulAmt2 = <NUM_LIT> ; if ( ( AbsMulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = AbsMulAmt / <NUM_LIT> ; } else if ( ( AbsMulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = AbsMulAmt / <NUM_LIT> ; } else if ( ( AbsMulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = AbsMulAmt / <NUM_LIT> ; } SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || ( SignMulAmt >= <NUM_LIT> && ( MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( SignMulAmt >= <NUM_LIT> && N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG .


<s> assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && <STR_LIT> ) ; EVT SubVT = V1 . getValueType ( ) ; EVT SubSVT = SubVT . getScalarType ( ) ; unsigned SubNumElts = SubVT . getVectorNumElements ( ) ; unsigned SubVectorWidth = SubVT . getSizeInBits ( ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , SubSVT , <NUM_LIT> * SubNumElts ) ; SDValue V = insertSubVector ( DAG . getUNDEF ( VT )

, V1 , <NUM_LIT> , DAG , dl , SubVectorWidth ) ;


<s> if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) -> setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( pushregs == NPARM_REGS ( SImode ) ) current_function_args_info . call_cookie |= ( CALL_COOKIE_INT_REG ( <NUM_LIT> , <NUM_LIT> ) | CALL_COOKIE_STACKSEQ ( pushregs - <NUM_LIT> ) ) ; else current_function_args_info . call_cookie |= CALL_COOKIE_STACKSEQ ( pushregs ) ; current_function_pretend_args_size += <NUM_LIT> * n_intregs ; } if ( TARGET_SHCOMPACT ) return const0_rtx ; } if ( ! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5 ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( TARGET_SHMEDIA ) n_floatregs = <NUM_LIT> ; bufsize = ( n_intregs * UNITS_PER_WORD ) + ( n_floatregs * UNITS_PER_WORD ) ; if ( TARGET_SHMEDIA ) regbuf = gen_frame_mem ( BLKmode , gen_rtx_REG ( Pmode , ARG_POINTER_REGNUM ) ) ; else if ( n_floatregs & <NUM_LIT> ) { rtx addr ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , XEXP ( regbuf , <NUM_LIT> ) ) ; emit_insn ( gen_iorsi3 ( addr , addr , GEN_INT ( UNITS_PER_WORD ) ) ) ; regbuf = change_address ( regbuf , BLKmode , addr ) ; } else if ( STACK_BOUNDARY < <NUM_LIT> && TARGET_FPU_DOUBLE && n_floatregs ) { rtx addr , mask ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , plus_constant ( XEXP ( regbuf , <NUM_LIT> ) , <NUM_LIT> ) ) ; mask = copy_to_mode_reg ( Pmode , GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( addr , addr , mask ) ) ; regbuf = change_address ( regbuf , BLKmode , addr ) ; } else regbuf = assign_stack_local ( BLKmode , bufsize , TARGET_FPU_DOUBLE ? <NUM_LIT> : <NUM_LIT> ) ; alias_set = get_varargs_alias_set ( ) ; set_mem_alias_set ( regbuf , alias_set ) ; if ( n_intregs > <NUM_LIT> ) move_block_from_reg ( BASE_ARG_REG ( SImode ) + first_intreg , adjust_address ( regbuf , BLKmode

, n_floatregs * UNITS_PER_WORD ) , n_intregs ) ;


<s> return isInt < <NUM_LIT> > ( CN . getSExtValue ( ) ) && (

( CN . getSExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; InitMandarinMCRegisterInfo ( X , <STR_LIT> ) ; return


<s> if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return <NUM_LIT> ; OpNum = <NUM_LIT> ; const MachineOperand & MO = MI . getOperand (


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , * this , Fast ) ) ; return


<s> lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) { DAG . getContext ( ) -> emitError ( <STR_LIT>


<s> } int64_t LegalShiftVal = Log2_32 ( SizeInBytes ) ; if ( LegalShiftVal == <NUM_LIT> ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * OffsetInst , MRI ) ) return None ; Register OffsetReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; Register CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ?


<s> use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , <NUM_LIT> ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( )


<s> } else { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; } Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OddReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( EvenReg == OddReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isT2 ) OffReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = llvm :: getInstrPredicate ( Op0 , PredReg ) ; dl = Op0 -> getDebugLoc ( ) ; return


<s> if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType (


<s> if ( std :: is_same < int16_t , std :: make_signed_t < T >> :: value ) return IsImm8 || IsImm16 || uint16_t ( Imm & ~ <NUM_LIT> ) == Imm ; return IsImm8 || IsImm16


<s> static __inline vec_double2 spu_slqw ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbi ( ( qword )


<s> return mips_address_insns ( addr , SImode


<s> else { return false ; } int Num1s = ( ImmS & ( Width - <NUM_LIT> ) ) + <NUM_LIT> ; if ( Num1s == Width ) return false ; int Rotation = ( ImmR & ( Width - <NUM_LIT> ) ) ; uint64_t Mask = ( <NUM_LIT> << Num1s ) - <NUM_LIT> ; uint64_t WidthMask = Width == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << Width ) - <NUM_LIT> ; Mask = ( Mask >> Rotation ) | ( ( Mask << ( Width - Rotation ) ) & WidthMask ) ; Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegWidth / Width ; ++ i ) { Imm |= Mask ; Mask <<=


<s> bool <ISA_LIT>GOT :: hasGOT1 ( ) const { return ( ( ! m_GOT . empty ( ) ) || ( ! m_GOTPLT . empty


<s> for ( unsigned Op : { G_SDIV , G_UDIV } ) { for ( auto Ty : { s8 , s16 } ) setAction ( { Op , Ty } , WidenScalar ) ; if ( ST . hasDivideIn<ISA_LIT>Mode ( ) ) setAction ( { Op , s32 } , Legal ) ; else setAction ( { Op , s32 } , Libcall ) ; } for ( unsigned Op : { G_SREM , G_UREM } ) if ( ST . hasDivideIn<ISA_LIT>Mode ( ) ) setAction ( { Op , s32 } , Lower ) ; else if ( AEABI ( ST ) ) setAction ( { Op , s32 } , Custom ) ; else setAction ( { Op , s32 } , Libcall ) ; for ( unsigned Op : { G_SEXT , G_ZEXT } ) { setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_SELECT , s32 } , Legal ) ; setAction ( { G_SELECT , p0 } , Legal ) ; setAction ( { G_SELECT , <NUM_LIT> , s1 } , Legal ) ; setAction ( { G_BRCOND , s1 } , Legal ) ; setAction ( { G_CONSTANT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_CONSTANT , Ty } , WidenScalar ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal ) ; setAction ( { G_FADD , s64 } , Legal ) ; setAction ( { G_LOAD , s64 } , Legal ) ; setAction ( { G_STORE , s64 } , Legal ) ; setAction ( { G_FCMP , s1 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT> , s64 } , Legal ) ; } else { for ( auto Ty : { s32 , s64 } ) setAction ( { G_FADD , Ty } , Libcall ) ; setAction ( { G_FCMP , s1 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT> , s32 } , Custom ) ; setAction ( { G_FCMP , <NUM_LIT> , s64 } ,


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned AtomicOp = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock :: iterator II ( MI ) ; Register PtrCopy = MRI . createVirtualRegister ( MRI . getRegClass ( Ptr ) ) ; Register OldValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( OldVal ) ) ; Register NewValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( NewVal ) ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , PtrCopy ) . addReg ( Ptr ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , OldValCopy ) . addReg ( OldVal ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , NewValCopy ) . addReg ( NewVal ) ; BuildMI ( * BB , II , DL , TII -> get ( AtomicOp ) ) . addReg ( Dest , RegState :: Define | RegState :: EarlyClobber ) . addReg ( PtrCopy , RegState :: Kill ) . addReg ( OldValCopy , RegState :: Kill ) . addReg ( NewValCopy , RegState :: Kill ) . addReg ( Scratch , RegState :: EarlyClobber | RegState :: Define | RegState :: Dead | RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return BB


<s> return __builtin_mve_vabdq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> static bool IsWritingToVCCR ( MachineInstr & Instr ) { if ( Instr . getNumOperands ( ) == <NUM_LIT> ) return false ; MachineOperand & Dst = Instr . getOperand ( <NUM_LIT> ) ; if ( ! Dst . isReg ( ) ) return false ; Register DstReg = Dst . getReg ( ) ; if ( ! DstReg . isVirtual ( )


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties ::


<s> fprintf ( file , <STR_LIT> ) ; for ( i = CONST_VECTOR_NUNITS ( x ) ; i -- ; ) { rtx element ; element = CONST_VECTOR_ELT ( x , i ) ; fprintf ( file , pattern , INTVAL ( element ) ) ; } return <NUM_LIT>


<s> for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) || MFI . getStackSize ( ) > <NUM_LIT> || MFI . getNumObjects ( ) > <NUM_LIT> ) return UnknownCallOutlineType ; return outliner :: InstrType :: Legal ; } if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) { bool MightNeedStackFixUp = ( Flags & ( MachineOutlinerMBBFlags :: LRUnavailableSomewhere | MachineOutlinerMBBFlags :: HasCalls ) ) ; if ( ! MightNeedStackFixUp ) return outliner :: InstrType :: Legal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( checkAndUpdateStackOffset ( & MI , Subtarget . getStackAlignment ( ) . value ( ) , false ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> ,


<s> unsigned getMaxDisp ( ) const { unsigned xMaxDisp = ConstantIslandsSmallOffset

? ConstantIslandsSmallOffset : MaxDisp ;


<s> return AssemblerDialect == <NUM_LIT>


<s> if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask


<s> HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_adddi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset + <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; offset -= <NUM_LIT> ; } if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) { rtx tmpreg , retreg ; rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } tmpreg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; retreg = gen_rtx_REG ( DImode , MMIX_rJ_REGNUM ) ; emit_move_insn ( tmpreg , retreg ) ; insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , tmpreg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , retreg ) , REG_NOTES ( insn ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -=


<s> void EmitARM64WinCFIContext ( ) override { OS <<


<s> void <ISA_LIT>GNULDBackend :: orderSymbolTable ( Module & pModule ) { if ( config ( ) . options ( ) . hasGNUHash (


<s> newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; if ( mode != TImode && ! reg_or_short_operand ( oldval , mode ) ) oldval = copy_to_mode_reg ( mode , oldval ) ; if ( reg_overlap_mentioned_p ( retval , newval ) ) newval = copy_to_reg ( newval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; cond = gen_reg_rtx ( CCmode ) ; if ( mode != TImode ) x = gen_rtx_COMPARE ( CCmode , x , oldval ) ; else { rtx xor1_result = gen_reg_rtx ( DImode ) ; rtx xor2_result = gen_reg_rtx ( DImode ) ; rtx or_result = gen_reg_rtx ( DImode ) ; rtx new_word0 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx new_word1 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx old_word0 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; rtx old_word1 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; emit_insn ( gen_xordi3 ( xor1_result , new_word0 , old_word0 ) ) ; emit_insn ( gen_xordi3 ( xor2_result , new_word1 , old_word1 ) ) ; emit_insn ( gen_iordi3 ( or_result , xor1_result , xor2_result ) ) ; x = gen_rtx_COMPARE ( CCmode , or_result , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; x = newval ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , newval , mask ) ; emit_store_conditional ( orig_mode , cond , mem , x ) ; if ( ! is_weak


<s> _Unwind_Word _Unwind_GetGR ( struct _Unwind_Context * context , int index ) { _Unwind_Word ret ; char nat ; if ( index == <NUM_LIT> )


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic ==

<STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) {


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal


<s> assert ( isLEA ( First ) && isLEA ( Last ) && <STR_LIT> ) ; if ( MRI -> getRegClass ( First . getOperand ( <NUM_LIT> ) . getReg ( ) ) != MRI -> getRegClass ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; AddrDispShift = getAddrDispShift ( Last , <NUM_LIT> , First , <NUM_LIT> ) ; for ( auto & MO : MRI -> use_nodbg_operands ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOpNo < <NUM_LIT> ) return false ; MemOpNo += <STR_LIT> ( Desc ) ; if ( ! isIdenticalOp ( MI . getOperand ( MemOpNo + <STR_LIT> ) , MO ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) if ( i != ( unsigned ) ( MemOpNo + <STR_LIT> ) && isIdenticalOp ( MI . getOperand ( i


<s> return __builtin_aarch64_ld1v8hi ( ( const __builtin_aarch64_simd_hi *


<s> void addRegF8RCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , isN32 ( ) || isN64 (


<s> fputs ( <STR_LIT> , f ) ; } while ( imports_list ) { fprintf ( f , <STR_LIT> ) ; assemble_name ( f , imports_list -> name ) ; fputc ( '\n' , f ) ; imports_list = imports_list


<s> static unsigned getNextSVEVectorRegister ( unsigned Reg ) { if ( Reg == <STR_LIT> ) return <STR_LIT> ; else return Reg


<s> void <ISA_LIT>RegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { unsigned FIOperandNum = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands (


<s> rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ <NUM_LIT> ] ; in = force_reg ( inmode , operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode


<s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects

( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ;


<s> ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { GRLenVT = <STR_LIT> ; GRLen = <NUM_LIT> ; } TargetABI = Is64Bit ? <STR_LIT> : <STR_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>ExpandPseudo (


<s> Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> } } } else if ( value == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return ; } max = shift_insns [ value ] ; for ( i = <NUM_LIT> ; i < max ; i ++ ) gen_ashift ( code , shift_amounts [ value ] [ i ]


<s> } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size


<s> return ! ( RC == & <STR_LIT> || RC == & <STR_LIT>


<s> const int shiftl = ( __N & <NUM_LIT> ) * <NUM_LIT> ; const __m64 shiftD = ( const __m64 ) __D << shiftl ; const __m64 mask = <NUM_LIT> << shiftl ; __m64 result = ( __A & ( ~ mask ) )


<s> Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( ! Hash ) return MatchOperand_NoMatch ; TokError ( <STR_LIT> )


<s> MCDisassembler ( STI , Ctx ) , IsN64 ( STI . getFeatureBits

( ) & <STR_LIT> ) , isBigEndian ( bigEndian ) {


<s> if ( TARGET_SPE && regno < <NUM_LIT> && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SFmode && mode != SDmode && mode != SCmode ) ) ) ; else return NULL_RTX ; regno = REGNO ( reg ) ; words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - <NUM_LIT> ) / UNITS_PER_FP_WORD ; gcc_assert ( words <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < words ; i ++ , regno ++ ) { if ( BYTES_BIG_ENDIAN ) { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno ) ; } else { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno +


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF )


<s> return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG


<s> _Float16 _Complex a ; float b ; } u = { . a


<s> int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = *


<s> return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT> ,


<s> void DecodePSHUFBMask ( ArrayRef < uint64_t > RawMask , SmallVectorImpl < int > & ShuffleMask ) { for ( int i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { uint64_t M = RawMask [ i ] ; if ( M == ( uint64_t


<s> static bool selectExtract ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI


<s> rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { loongarch_rewrite_small_data_1 ( & XEXP ( * loc , <NUM_LIT> ) ) ; iter . skip_subrtxes


<s> return ( int32x2_t ) __builtin_neon_vqrdmulh_nv2si ( __a ,


<s> if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , call


<s> std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( Tp ) ; unsigned Cost = <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) Cost = <NUM_LIT> ; return Cost * LT


_mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> gcc_assert ( rclass == GENERAL_REGS || rclass == BASE_REGS ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PRE_MODIFY ) { gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) == XEXP ( addr , <NUM_LIT> ) ) ; scratch_or_premodify = XEXP ( addr , <NUM_LIT> ) ; if ( ! HARD_REGISTER_P ( scratch_or_premodify ) ) scratch_or_premodify = find_replacement ( & XEXP ( addr , <NUM_LIT> ) ) ; addr = XEXP ( addr , <NUM_LIT> ) ; } gcc_assert ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) ; rs6000_emit_move ( scratch_or_premodify , addr


<s> MachineInstrBuilder HiInst = BuildMI ( MBB , I , DL , get ( HiOpc ) ) ; if ( HasExplicitDef ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; unsigned DstHi = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; LoInst . addReg ( DstLo , RegState :: Define ) ; HiInst . addReg ( DstHi , RegState :: Define ) ; } LoInst . addReg ( SrcLo . getReg ( ) , getKillRegState ( SrcLo . isKill (


<s> void FPS :: shuffleStackTop ( const unsigned char * FixStack , unsigned FixCount , MachineBasicBlock :: iterator I ) { while ( FixCount --


<s> inline unsigned getVMOVModImmOpCmode ( unsigned ModImm ) { return ( ModImm >> <NUM_LIT> ) &


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) ,


<s> unsigned Other = MCELF :: getOther ( SymbolData ) << <NUM_LIT> ; Other &= ~ ELF :: STO_<ISA_LIT>64_LOCAL_MASK ; Other |= ( MCELF :: getOther ( Data ) << <NUM_LIT> ) & ELF :: STO_<ISA_LIT>64_LOCAL_MASK ; MCELF :: setOther ( SymbolData ,


<s> dbgs ( ) << <STR_LIT> ; PMul1 -> Root -> dump ( ) ) ; auto * VecLd0 = cast < LoadInst > ( PMul0 -> VecLd [ <NUM_LIT> ] ) ; auto * VecLd1 = cast < LoadInst > ( PMul1 -> VecLd [ <NUM_LIT> ] ) ; Acc = CreateSMLADCall ( VecLd0 , VecLd1 , Acc , PMul1 -> Exchange , InsertAfter ) ; InsertAfter = Acc ; } if ( Acc != Reduction .


<s> if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; return LowerVectorCTLZInRegLUT ( Op , DL ,


<s> unsigned A15SDOptimizer :: createExtractSubreg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , DebugLoc DL , unsigned DReg , unsigned Lane , const TargetRegisterClass * TRC ) { unsigned Out = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: COPY ) , Out ) . addReg ( DReg , <NUM_LIT> , Lane ) ; return Out


<s> if ( ! Subtarget -> isCallingConvWin64 ( F -> getFunction ( ) -> getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget -> hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI -> eraseFromParent ( ) ; return EndMBB


<s> O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> ) { O << <STR_LIT> ; if ( L == <NUM_LIT> || L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O ,


<s> emit_insn_before ( gen_move_insn ( subreg , CONSTM1_RTX ( V2DImode ) ) , insn ) ; src = gen_rtx_XOR ( V2DImode , src , subreg ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ; if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode , src , <NUM_LIT> ) ; else subreg = copy_rtx_if_shared ( src ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) ) , insn ) ; dst = gen_rtx_REG ( CCmode , FLAGS_REG ) ; src = gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , copy_rtx_if_shared ( src ) , copy_rtx_if_shared ( src ) ) , UNSPEC_PTEST ) ; break ; case CONST_INT : convert_op ( & src , insn ) ; break ; default : gcc_unreachable (


<s> } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } } } if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) ) ) { int ShiftAmt = matchVectorShuffleAsShift ( ShuffleVT , Shuffle , MaskScalarSizeInBits ,

Mask , <NUM_LIT> , Zeroable , Subtarget ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( getSymbol ( ZCPV -> getGlobalValue ( ) )

, getModifierVariantKind ( ZCPV -> getModifier ( ) ) , OutContext ) ;


) ) _mm_load_sd ( double const * __P ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineLoop * ML : MLI -> getBase ( ) . getLoopsInPreorder ( ) ) { Modified |= LowerWhileLoopStart ( ML ) ; Modified |= MergeLoopEnd ( ML ) ; Modified |= ConvertTailPredLoop ( ML , DT ) ; } for ( MachineBasicBlock & MBB : Fn ) { Modified |= HintDoLoopStartReg ( MBB ) ; Modified |= ReplaceConstByVPNOTs ( MBB , DT ) ; Modified |= ReplaceVCMPsByVPNOTs ( MBB ) ; Modified |= ReduceOldVCCRValueUses ( MBB ) ; Modified |= ConvertVPSEL ( MBB ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_maskz_loadu_epi16 ( __mmask16 __U , void const * __P ) { return ( __m256i ) __builtin_ia32_loaddquhi256_mask ( ( const short * ) __P , ( __v16hi ) _mm256_setzero_si256 ( ) , (


<s> BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Highest ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Higher ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Hi ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Lo ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( BalTgtMBBSize == BalTgtMBB -> size ( ) ) ; assert ( LongBrMBB -> size ( ) + BalTgtMBBSize == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor (


<s> static reg_class_t loongarch_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( reg_class_subset_p ( FP_REGS , rclass ) && loongarch_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; return


<s> if ( Alignment >= DataSize && ( DataSize == <NUM_LIT> || DataSize == <NUM_LIT> ) ) return DataSize == <NUM_LIT> ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false


<s> MCELFStreamer :: emitValueImpl ( Value , Size , Loc


<s> if ( ! sparc_tls_symbol ) sparc_tls_symbol = gen_rtx_SYMBOL_REF


<s> bool isKMasked ( ) const { return ( Attributes & ( KMergeMasked | KZeroMasked


<s> if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < <NUM_LIT> || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x )


<s> SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg ( ) ; unsigned Reg1 = cast < RegisterSDNode > ( V1 ) -> getReg ( ) ; SDValue PairedReg ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T0 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T1 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , } ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT>


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: CreateImm ( ( ~ Value >> Shift )


<s> static int readMaskRegister ( struct InternalInstruction * insn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( insn -> vectorExtensionType !=


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : return make_vector < unsigned > ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> unsigned <ISA_LIT>ABIInfo :: GetStackPtr ( )


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm ) [


<s> MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) && MO . isDef ( ) ) { assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( i ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( implicitlyDefinesOverlappingReg ( MO . getReg ( ) , MI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } unsigned NewReg ; switch ( MI . getDesc ( ) . OpInfo [ i ] . RegClass ) { default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; case <STR_LIT> : NewReg = <STR_LIT> ; break ; case <STR_LIT> : NewReg = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; MO . setReg ( NewReg ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; ++


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ~ ( ~ ImmValue & ~ ( ~ ImmValue + <NUM_LIT> ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue . countPopulation ( ) - <NUM_LIT> , SDLoc ( N ) , EltTy ) ; return true ; } } return


<s> Value * <ISA_LIT>IREmitter :: visitVRSHRN (


<s> if ( ts & BEGIN_DATA ) { if ( ts & BEGIN_CONTROL ) gen_ld = gen_ld_sa ; else gen_ld = gen_ld_a ; } else if ( ts & BEGIN_CONTROL ) { if ( ( spec_info -> flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL ) || ia64_needs_block_p ( ts ) ) gen_ld = gen_ld_s ; else gen_ld = gen_ld_s_a ; } else if ( ts == <NUM_LIT> ) gen_ld = gen_ld_ ; else gcc_unreachable ( ) ; return gen_ld [


<s> string Reg = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string RegOff = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * offset = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , RegOff ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * bytes_to_bits = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , Reg ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * add = ctx -> add ( <NUM_LIT>

, bytes_to_bits , offset , <NUM_LIT> ) ;


<s> while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_<ISA_LIT>_AllRegs_Vector_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute

:: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> return __builtin_mve_vcaddq_rot90v8hi ( __a ,


<s> const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedGlobals [ i ] -> getName ( ) ; if ( Subtarget -> isTargetWindows ( ) ) name += <STR_LIT> ; else name += <STR_LIT> ; OutStreamer . EmitBytes ( name ) ; } for ( unsigned i = <NUM_LIT> , e = DLLExportedFns . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedFns [ i ] -> getName ( ) ; OutStreamer . EmitBytes ( name ) ; } } } if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs .


<s> addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; } if ( Triple ( TM -> getTargetTriple ( )


<s> void <ISA_LIT>InstPrinter :: printMandatoryPredicateOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString ( CC )


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { llvm_unreachable (


<s> unsigned Reg = I64RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> if ( isa < ScalableVectorType > ( Arg . getType ( ) ) ) return false ; if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn )


<s> return_type = DECL_RESULT ( current_function_decl ) ; if ( TARGET_MIPS16 && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return <NUM_LIT> ; if ( cfun -> machine -> frame . initialized ) return cfun -> machine -> frame . total_size == <NUM_LIT> ; return compute_frame_size ( get_frame_size (


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> if ( Op != TargetOpcode :: COPY && ! MI . isPHI ( ) ) return false ; return getRegBank ( MI . getOperand ( <NUM_LIT> ) . getReg


<s> void addRegPairOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ++ ) ) ; Inst . addOperand ( MCOperand ::


<s> for ( auto I = MBB -> rbegin ( ) ; I != MBB -> rend ( ) ; LR . stepBackward ( * I ) , ++ I ) { MachineInstr & MI = * I ; if ( ! TII -> isStridedAccess ( MI ) ) continue ; Optional < LoadInfo > OptLdI = getLoadInfo ( MI ) ; if ( ! OptLdI ) continue ; LoadInfo LdI = * OptLdI ; Optional < unsigned > OptOldTag = getTag ( TRI , MI , LdI ) ; if ( ! OptOldTag ) continue ; auto & OldCollisions = TagMap [ * OptOldTag ] ; if ( OldCollisions . size ( ) <= <NUM_LIT> ) continue ; bool Fixed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; for ( unsigned ScratchReg : <STR_LIT> ) { if ( ! LR . available ( ScratchReg ) || MRI . isReserved ( ScratchReg ) ) continue ; LoadInfo NewLdI ( LdI ) ; NewLdI . BaseReg = ScratchReg ; unsigned NewTag = * getTag ( TRI , MI , NewLdI ) ; if ( TagMap . count ( NewTag ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( ScratchReg , TRI ) << '\n' ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg ( ScratchReg ) ; if ( LdI . IsPrePost ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( ScratchReg , TRI ) << '\n' ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ScratchReg ) ; BuildMI ( * MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , DL , TII -> get ( <STR_LIT> ) , LdI . BaseReg ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } for ( int I = <NUM_LIT> , E = OldCollisions . size ( ) ; I != E ; ++ I ) if ( OldCollisions [ I ] == & MI ) { std :: swap ( OldCollisions [ I ] , OldCollisions [ E


<s> return ( DstRC == & <STR_LIT> || DstRC == & <STR_LIT> || DstRC == & <STR_LIT> || DstRC ==

& <STR_LIT> ) && ( SrcRC == & <STR_LIT> || SrcRC == & <STR_LIT> ) ;


<s> } for ( auto J : ToErase ) Substs . erase ( J ) ; if ( & I != G -> getKill ( ) ) { MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; bool Change = TransformAll || getColor ( MO . getReg ( ) ) != C ; if ( G -> requiresFixup ( ) && & I == G -> getLast ( ) ) Change = false ; if ( Change ) { Substs [ MO . getReg ( ) ] = Reg ; MO . setReg ( Reg ) ; Changed = true ; } } } assert ( Substs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( G -> getKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } return Changed


<s> if ( ! Fast && ! DisableIfConversion && ! Subtarget . isThumb ( ) ) PM . add ( createIfConverterPass ( ) ) ; PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return true


<s> set_optab_libfunc ( neg_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant (


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p =


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID ) const { return CSR_<ISA_LIT>_AAPCS_ThisReturn_RegMask


<s> widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << <NUM_LIT> , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> <NUM_LIT> ) ; emit_move_insn ( target , gen_lowpart ( mode ,


<s> SDValue Zero , CTTZ ; if ( CC == <STR_LIT> && SUBS . getOpcode ( ) == <STR_LIT> ) { Zero = N -> getOperand ( <NUM_LIT> ) ; CTTZ = N -> getOperand ( <NUM_LIT> ) ; } else if ( CC == <STR_LIT> && SUBS . getOpcode ( ) == <STR_LIT> ) { Zero = N -> getOperand ( <NUM_LIT> ) ; CTTZ = N -> getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; if ( ( CTTZ . getOpcode ( ) != <STR_LIT> && CTTZ . getOpcode ( ) != <STR_LIT> ) || ( CTTZ . getOpcode ( ) == <STR_LIT> && CTTZ . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; assert ( ( CTTZ . getValueType ( ) == <STR_LIT> || CTTZ . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isNullConstant ( Zero ) || ! isNullConstant ( SUBS . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue X = CTTZ . getOpcode ( ) == <STR_LIT> ? CTTZ . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : CTTZ . getOperand ( <NUM_LIT> ) ; if ( X != SUBS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned BitWidth = CTTZ . getOpcode ( ) == <STR_LIT> ? CTTZ . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) : CTTZ . getValueSizeInBits ( ) ; SDValue BitWidthMinusOne = DAG . getConstant ( BitWidth - <NUM_LIT> , SDLoc ( N ) , CTTZ . getValueType ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , CTTZ .

getValueType ( ) , CTTZ , BitWidthMinusOne ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_store_ps ( float * __P , __m128 __A ) { assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ; vec_st ( ( __v4sf ) __A , <NUM_LIT> , (


<s> if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; EVT ResTy = Op . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ResTy ) ) return SDValue ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) { EVT SatVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( SatVT . getScalarSizeInBits ( ) != IntBits ) return SDValue ( ) ; } SDLoc DL ( N ) ; bool IsSigned = ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; unsigned IntrinsicOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getConstant ( IntrinsicOpcode , DL , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant


<s> void emitBytes ( StringRef Data ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitBytes (


<s> return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) ,


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return ( MO . getImm (


<s> static bool isDomainMVE ( MachineInstr * MI ) { uint64_t Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; return Domain == <STR_LIT>


<s> case <STR_LIT> : Value = <NUM_LIT> ; return true ; case <STR_LIT> : Value = <NUM_LIT> ; return true ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ) return false ; Value = <NUM_LIT> ; return true ; case <STR_LIT> : { const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( ! Src . isImm ( ) ) return


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags ,


<s> SDValue ChainIn = Op -> getOperand ( <NUM_LIT> ) ; SDValue Address = Op -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Op -> getOperand ( <NUM_LIT> ) ; EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc =


<s> maskcmp = true ; cmp_mode = nbits > <NUM_LIT> ? int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; bool ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest


<s> } else for ( unsigned int ti = <NUM_LIT> ; group . types [ ti ] [ <NUM_LIT> ] != NUM_TYPE_SUFFIXES ; ++ ti ) { type_suffix_pair types = { explicit_type0 ? group . types [ ti ] [ <NUM_LIT> ] : NUM_TYPE_SUFFIXES , explicit_type1 ? group . types [ ti ] [ <NUM_LIT> ] : NUM_TYPE_SUFFIXES } ; function_instance instance ( group . base_name , * group . base , * group . shape , mode , types , group . preds [ pi ] ) ; add_overloaded_function ( instance , group . required_extensions


<s> static bool rs6000_attribute_takes_identifier_p (


<s> if ( errorToBool ( StatusOrErr . takeError ( ) ) || * StatusOrErr != APFloat :: opOK ) llvm_unreachable ( <STR_LIT> ) ; if ( getFPImm ( ) . bitwiseIsEqual ( RealVal ) ) return


<s> cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , <NUM_LIT> ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; Results . push_back ( lowerGR128ToI128 ( DAG , Res ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; if ( cast < AtomicSDNode > ( N ) -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Res = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Res ) , <NUM_LIT> ) ; Results . push_back ( Res ) ; break ; } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; SDValue Success = emitSETCC ( DAG , DL , Res . getValue ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; Success = DAG . getZExtOrTrunc ( Success , DL , N -> getValueType ( <NUM_LIT> ) ) ; Results . push_back ( lowerGR128ToI128 ( DAG , Res ) ) ; Results . push_back ( Success ) ; Results . push_back ( Res . getValue


<s> emit_insn ( shift ( tmp2 , tmp1 , operands [ <NUM_LIT> ] ) ) ; rtx tmp3 = ix86_expand_ti_to_v1ti ( tmp2 ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp3 ) ; return ; } HOST_WIDE_INT bits = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( bits == <NUM_LIT> ) { emit_move_insn ( operands [ <NUM_LIT> ] , op1 ) ; return ; } if ( ( bits & <NUM_LIT> ) == <NUM_LIT> ) { rtx tmp = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp ) ; return ; } rtx tmp1 = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp1 , op1 , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp1 , op1 , GEN_INT ( <NUM_LIT> ) ) ) ; rtx tmp2 = force_reg ( V2DImode , gen_lowpart


<s> static bool MaybePredicatedInst ( const OperandVector & Operands ) { if ( Operands . size ( ) < <NUM_LIT> || ! IsRegister ( * Operands [ <NUM_LIT> ] ) || ! IsRegister ( * Operands [


<s> BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2


<s> SmallVector < MachineOperand , <NUM_LIT> > AfterOps ; SmallVector < MachineOperand , <NUM_LIT> > ImpOps ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( i >= Index && i < Index + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( Op . isReg ( ) && Op . isImplicit ( ) ) ImpOps . push_back ( Op ) ; else if ( i < Index ) BeforeOps . push_back ( Op ) ; else if ( i > Index ) AfterOps . push_back ( Op ) ; } if ( UnfoldLoad ) { std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; loadRegFromAddr ( MF , Reg , AddrOps , RC , MMOs . first , MMOs . second , NewMIs ) ; if ( UnfoldStore ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> + <STR_LIT> ; ++ i ) { MachineOperand & MO = NewMIs [ <NUM_LIT> ] -> getOperand ( i ) ; if ( MO . isReg ( ) ) MO . setIsKill ( false ) ; } } } MachineInstr * DataMI = MF . CreateMachineInstr ( MCID , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , DataMI ) ; if ( FoldedStore ) MIB . addReg ( Reg , RegState :: Define ) ; for ( MachineOperand & BeforeOp : BeforeOps ) MIB . addOperand ( BeforeOp ) ; if ( FoldedLoad ) MIB . addReg ( Reg ) ; for ( MachineOperand & AfterOp : AfterOps ) MIB . addOperand ( AfterOp ) ; for ( MachineOperand & ImpOp : ImpOps ) { MIB . addReg ( ImpOp . getReg ( ) , getDefRegState ( ImpOp . isDef ( ) ) | RegState :: Implicit | getKillRegState ( ImpOp . isKill ( ) ) | getDeadRegState ( ImpOp . isDead ( ) ) | getUndefRegState ( ImpOp . isUndef ( ) ) ) ; } switch ( DataMI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( __m128i ) __builtin_ia32_psubd128 ( ( __v4si


<s> unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( SrcReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc =


<s> void <ISA_LIT>InstPrinter :: printS16ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printSImmOperand < <NUM_LIT> > ( MI ,


<s> bool nds32_gw_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; return gw_consumed_by_ex_dep_p ( consumer , last_def_reg )


<s> static MachineInstr * canFoldIntoSelect ( unsigned Reg , const MachineRegisterInfo & MRI ) { if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr ,

DontMoveAcrossStores ) ) return nullptr ;


<s> SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ; } return SDValue (


<s> SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( ! Res . getNode ( ) ) return ; if ( N -> getNumValues ( ) == <NUM_LIT> ) { Results . push_back ( Res ) ; return ; } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = N -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back


<s> memset ( insn , <NUM_LIT> , sizeof ( struct InternalInstruction ) ) ; insn -> reader = reader ; insn -> readerArg = readerArg ; insn -> dlog = logger ; insn -> dlogArg = loggerArg ; insn -> startLocation = startLoc ; insn -> readerCursor = startLoc ; insn -> mode = mode ; insn -> numImmediatesConsumed = <NUM_LIT> ; if ( readPrefixes ( insn ) || readOpcode ( insn ) || getID ( insn , miiArg ) || insn -> instructionID == <NUM_LIT> || readOperands ( insn ) ) return - <NUM_LIT> ; insn -> operands = & x86OperandSets [ insn -> spec -> operands ] [ <NUM_LIT> ] ; insn -> length = insn -> readerCursor - insn -> startLocation ; dbgprintf ( insn , <STR_LIT> , startLoc , insn -> readerCursor , insn -> length ) ; if ( insn -> length > <NUM_LIT> ) dbgprintf (


<s> const char * maybe_suffix_2 = <STR_LIT> ; if ( ALL_FIXED_POINT_MODE_P ( from ) && ALL_FIXED_POINT_MODE_P ( to ) && UNSIGNED_FIXED_POINT_MODE_P ( from ) == UNSIGNED_FIXED_POINT_MODE_P ( to ) && ALL_FRACT_MODE_P ( from ) == ALL_FRACT_MODE_P ( to ) ) maybe_suffix_2 = <STR_LIT> ; sprintf ( buffer , <STR_LIT> , funcname , fromname , toname , maybe_suffix_2 ) ; set_conv_libfunc ( optable , to


<s> bool SoftFloat = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSoftFloat ( ) ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( usePackedStack ( MF ) && ! ( IsVarArg && ! SoftFloat ) ) { if ( <STR_LIT> . contains ( Reg ) ) Offset


<s> return SelectionDAGISel :: runOnMachineFunction (


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn )


<s> gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU )


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , unsigned offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_RegisterMask : break ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_ExternalSymbol


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << ( MO2 . getImm ( ) << <NUM_LIT> ) ; } O <<


<s> cerr << <STR_LIT> << LocVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( LocVT , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) ,


<s> unsigned NumStores = getNumInterleavedAccesses ( SubVecTy , DL ) ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = Op0 -> getType ( ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen


<s> aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta ,


<s> return ( uint32x4_t ) __builtin_neon_vmullu_nv4hi ( ( int16x4_t ) __a ,


<s> case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT>


<s> int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~


<s> break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R6 ( ) ; break ; } return false


<s> void FixupLEAPass :: processInstructionForSLM ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr * MI = I ; const int opcode = MI -> getOpcode ( ) ; if ( ! isLEA ( opcode ) ) return ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) || ! TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) return ; const unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; int addrr_opcode , addri_opcode ; switch ( opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : case


<s> <ISA_LIT>FunctionInfo * AFI = Entry -> getParent ( ) -> getInfo <


<s> static bool shouldSExtOperand ( const Instruction * Inst , int OpIdx ) { if ( isa < SelectInst > ( Inst ) && OpIdx


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( )


<s> bool inMicro<ISA_LIT>32r6Mode ( ) const { return InMicro<ISA_LIT>Mode &&


<s> static unsigned findScratchRegister ( RegScavenger * RS , const TargetRegisterClass * RC , <ISA_LIT>FunctionInfo * AFI ) { unsigned Reg = RS ? RS -> FindUnusedReg ( RC ) : ( unsigned ) <STR_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ; return Reg


<s> return ( __m64 ) __builtin_arm_wqmulm ( ( __v4hi ) a , (


<s> if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return SDValue ( ) ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT>


<s> return getParser ( ) . hasPendingError ( ) ? true : Error ( L ,


<s> Pass * llvm :: createMVELaneInterleavingPass ( ) { return new MVELaneInterleaving (


<s> for ( ; it != end ( ) ; ++ it ) { llvm :: cast < <ISA_LIT>_64GOTEntry > ( * it ) . setValue ( plt_addr + <NUM_LIT> ) ; plt_addr += pPLT . getPLT1Size (


<s> return NumElem * Cost + SplitCost ; } } if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST ->

isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ;


<s> int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count ==


<s> reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> :


<s> SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode ,


<s> getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo > <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! Options . setATReg ( AtRegNo ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( )


<s> int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE (