<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionEntryLabel ( ) { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current . first , Current . second ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( )


<s> Op1 = DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) ; Opcode = <STR_LIT> ; } else { Op0 = LHS ; Op1 = RHS ; Opcode = <STR_LIT> ; } SDValue NeonCmpAlt ; bool SwapIfRegArgs = false ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Invert = true ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; case <STR_LIT> : Invert = true ; CC = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; case <STR_LIT> : Invert = true ; CC = <STR_LIT> ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : NeonCmpAlt = DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , DAG . getCondCode ( <STR_LIT> ) ) ; CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : NeonCmpAlt = DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , DAG . getCondCode ( <STR_LIT> ) ) ; CC = <STR_LIT> ; SwapIfRegArgs = true ; break ; } if ( Opcode == <STR_LIT> && SwapIfRegArgs ) { CC = getSetCCSwappedOperands ( CC ) ; std :: swap ( Op0 , Op1 ) ; } SDValue NeonCmp = DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , DAG .


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ; const MachineMemOperand * MemOperand = * MI . memoperands_begin ( ) ; if ( MemOperand -> isVolatile ( ) ) return false ; return true


<s> Encoding = ( get<ISA_LIT>RegisterNumbering ( Op1 . getReg ( ) ) << <NUM_LIT> ) ; if ( Op2 . isImm ( ) ) { assert ( isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) && <STR_LIT> ) ; Encoding |= ( Op2 . getImm ( ) & <NUM_LIT> ) ; if ( Op2 . getImm ( ) != <NUM_LIT> ) { if ( LPAC :: isPreOp ( AluOp . getImm ( ) ) ) Encoding |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( LPAC :: isPostOp ( AluOp . getImm ( ) ) ) Encoding |= ( <NUM_LIT> << <NUM_LIT> ) ; } } else getMachineOpValue ( Inst , Op2 , Fixups , SubtargetInfo ) ; return


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) *


<s> void addNEONi16splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue (


<s> unsigned Opcode = Node -> getOpcode ( ) ; SDLoc DL ( Node ) ; EVT NodeTy = Node -> getValueType ( <NUM_LIT> ) ; unsigned MultOpc ; switch ( Opcode ) { default : break ; case <STR_LIT>


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) )

Inst . addOperand ( MCOperand :: createImm ( Val << <NUM_LIT> ) ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] ,


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool hasGPR = false ; unsigned FirstReg = <NUM_LIT> ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( ! MF . protectCSRs ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else if ( ! hasGPR ) { FirstReg = Reg ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; hasGPR = true ; } else { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , FirstReg ) . addReg ( FirstReg ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( MF . protectCSRs ( ) && hasGPR ) { assert (


<s> MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; restoreMBB -> setHasAddressTaken ( ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ! isPositionIndependent ( ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget . is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget . classifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB ( restoreMBB ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; thisMBB -> addSuccessor (


<s> SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT>


<s> CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat


<s> EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL .


<s> Info . PtrVal = Inst -> getArgOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Info . ReadMem = false ; Info . WriteMem = true ; Info . PtrVal = Inst -> getArgOperand ( Inst -> arg_size ( ) - <NUM_LIT> ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case <STR_LIT> : case <STR_LIT> : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case <STR_LIT> : case <STR_LIT> : Info . MatchingId


<s> addPreEmitPass ( PassManagerBase & PM


<s> Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( Contents , <NUM_LIT> ) ; Contents . clear


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crc32q ( unsigned long long __C , unsigned long long __V ) { return __builtin_ia32_crc32di ( __C


<s> __builtin_ia32_scatterpfqpd ( mask , ( __v8di ) index , ( long long const


<s> if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo ->


<s> static SDValue lowerMSASplatImm ( SDValue Op , unsigned ImmOp , SelectionDAG & DAG ) { return DAG . getConstant ( Op -> getConstantOperandVal ( ImmOp ) ,


<s> ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isReverseMask ( ShuffleMask , VT ) ) { SDValue cast = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; SDValue rbit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , cast ) ; SDValue srl = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rbit , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , srl ) ; } SDValue PredAsVector = PromoteMVEPredVector ( dl , V1 , VT , DAG ) ; EVT NewVT = PredAsVector . getValueType ( ) ; SDValue Shuffled = DAG . getVectorShuffle ( NewVT , dl , PredAsVector , DAG . getUNDEF ( NewVT ) , ShuffleMask ) ; if ( VT == <STR_LIT> ) { SDValue BC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shuffled ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BC , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Shuffled ,


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterMCNaClExpander ( * T , create<ISA_LIT>MCNaClExpander ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & The<ISA_LIT>LETarget , & TheThumbLETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; for ( Target * T : { & The<ISA_LIT>BETarget , & TheThumbBETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>LETarget , create<ISA_LIT>LEAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>BETarget


<s> FunctionPass * llvm :: create<ISA_LIT>AvoidTrailingCallPass ( ) { return new <ISA_LIT>AvoidTrailingCallPass


<s> case UNSPEC_TPOFF : x = XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_MACHOPIC_OFFSET : return legitimate_pic_address_disp_p ( x ) ; default : return false ; } case SYMBOL_REF


<s> SDValue getCapToCapTable ( NodeTy * N , const SDLoc & DL , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , unsigned SmallFlag , unsigned HiOpc ) const { assert ( ABI . IsCheriPureCap


<s> S = Parser . getTok ( ) . getLoc ( ) ; if ( parseMemOffset ( IdVal ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; int RegNo = op


<s> else if ( IDVal == <STR_LIT> ) parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnwindRaw ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveMovSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveThumbSet ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( DirectiveID . getLoc ( ) , 'n' ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( DirectiveID . getLoc ( ) , 'w' ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnStart ( DirectiveID . getLoc (


<s> unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addImm ( CI -> getSExtValue ( ) ) ) ; return DestReg ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType (


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall ) FI -> setOutliningStyle ( <STR_LIT> ) ; else if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; unsigned TailOpcode ; if ( Call -> getOpcode ( ) == <STR_LIT> ) { TailOpcode = <STR_LIT> ; } else { assert ( Call -> getOpcode ( ) == <STR_LIT> || Call -> getOpcode ( ) == <STR_LIT> ) ; TailOpcode = <STR_LIT> ; } MachineInstr * TC = BuildMI ( MF , DebugLoc ( ) , get ( TailOpcode ) ) . add ( Call -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB . insert ( MBB . end ( ) , TC ) ; Call -> eraseFromParent ( ) ; FI -> setOutliningStyle ( <STR_LIT> ) ; } bool IsLeafFunction = true ; auto IsNonTailCall = [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; IsLeafFunction = false ; if ( ! MBB . isLiveIn ( <STR_LIT> ) )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> MachineBasicBlock * ThisMBB = BSI . OrigBranch -> getParent ( ) ; MachineFunction * MF = ThisMBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; if ( ThisMBB -> succ_size ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; unsigned OrigBROpcode = BSI . OrigBranch -> getOpcode ( ) ; unsigned InvertedOpcode = OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned NewBROpcode = BSI . InvertNewBranch ? InvertedOpcode : OrigBROpcode ; MachineBasicBlock * OrigTarget = BSI . OrigBranch -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * OrigFallThrough = OrigTarget == * ThisMBB -> succ_begin ( ) ? * ThisMBB -> succ_rbegin ( ) : * ThisMBB -> succ_begin ( ) ; MachineBasicBlock * NewBRTarget = BSI . BranchToFallThrough ? OrigFallThrough : OrigTarget ; BranchProbability ProbToNewTarget = ! BSI . MBPI ? BranchProbability :: getUnknown ( ) : BSI . MBPI -> getEdgeProbability ( ThisMBB , NewBRTarget ) ; MachineBasicBlock :: iterator InsertPoint = BSI . SplitBefore ; const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ThisMBB -> getIterator ( ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( ++ It , NewMBB ) ; NewMBB -> splice ( NewMBB -> end ( ) , ThisMBB , InsertPoint , ThisMBB -> end ( ) ) ; NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbToNewTarget . getCompl ( ) ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ; if ( BSI . MIToDelete ) BSI . MIToDelete -> eraseFromParent ( ) ; auto FirstTerminator = NewMBB -> getFirstTerminator ( ) ; if ( BSI . NewCond ) { assert ( FirstTerminator -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; FirstTerminator -> getOperand ( <NUM_LIT> ) . setReg ( BSI . NewCond -> getOperand ( <NUM_LIT>


<s> if ( Parent && ( LS = dyn_cast < LSBaseSDNode > ( Parent ) ) ) { EVT VT = LS -> getMemoryVT ( ) ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > LS -> getAlignment ( ) ) { assert ( TLI . allowsUnalignedMemoryAccesses ( VT ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( )


<s> virtual MCObjectWriter * createObjectWriter ( raw_ostream


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - <NUM_LIT> - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> (


<s> static bool isUndefOrZeroOrInRange ( ArrayRef < int > Mask , int Low , int Hi ) { return llvm :: all_of ( Mask , [ Low , Hi ] ( int M ) { return isUndefOrZeroOrInRange ( M , Low , Hi )


<s> __builtin_ia32_storedqusi512_mask ( ( int * ) __P , (


<s> return ( uint16x4_t ) __builtin_neon_vreinterpretv4hiv8qi (


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PCREL ; const MachineInstr * MI = MO . getParent ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; const MachineFunction * MF = MI -> getMF ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr

= MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> static SDValue combinePMULDQ ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( LHS ) && ! DAG . isConstantIntBuildVectorOrConstantInt ( RHS ) ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N )

, N -> getValueType ( <NUM_LIT> ) , RHS , LHS ) ;


<s> return get_hard_reg_initial_val ( mode ,


<s> if ( Kind . isReadOnly ( ) ) { const auto * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( GVar && GVar -> isConstant ( ) && GVar -> getInitializer ( ) -> needsDynamicRelocation (

) ) Kind = SectionKind :: getReadOnlyWithRel ( ) ;


<s> return __builtin_mve_vmovnbq_uv4si ( __a ,


<s> std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( CPEntry & CPE : CPEs ) if ( CPE . CPEMI == CPEMI ) return & CPE ; return nullptr


<s> while ( lastpos < LINELEN - <NUM_LIT> && ( isalnum ( linebuf [ lastpos + <NUM_LIT> ] ) || linebuf [ lastpos + <NUM_LIT> ] == '_' ) ) ++ lastpos ; if ( lastpos >= LINELEN - <NUM_LIT> ) { diag ( lastpos , <STR_LIT> ) ; exit ( <NUM_LIT> ) ; } if ( lastpos < pos ) return <NUM_LIT> ; char * buf = ( char * ) malloc (


<s> Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII ,


<s> int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsByteShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; V1 = DAG . getNode ( <STR_LIT> , DL


<s> return __builtin_neon_vmul_nv8hf ( __a ,


<s> Ops1 [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op1 , Idx ) ; } Op0 = DAG . getBuildVector ( Pow2VT , DL , Ops0 ) ; Op1 = DAG . getBuildVector ( Pow2VT , DL , Ops1 ) ; } SDValue Res = SplitOpsAndApply ( DAG , Subtarget , DL , Pow2VT , { Op0 , Op1 } , AVGBuilder ) ; if ( NumElemsPow2 == NumElems ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return AVGSplitter ( Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } auto FindAddLike = [ & ] ( SDValue V , SDValue & Op0 , SDValue & Op1 ) { if ( <STR_LIT> == V . getOpcode ( ) ) { Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } if ( <STR_LIT> != V . getOpcode ( ) ) return false ; V = V . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) != VT || <STR_LIT> != V . getOpcode ( ) || ! DAG . haveNoCommonBitsSet ( V . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) ) ) return false ; Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand


<s> static DecodeStatus DecodeVecShiftL64Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftLImm ( Inst ,


<s> <ISA_LIT>MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true


<s> unsigned FalseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; if ( ! convertPrevCompareToBranch ( MBB , MI , CCMask , JoinMBB ) ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent ( ) ; return


<s> SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( )

, RetAddrFI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL ,


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function


<s> emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } } else emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( vmode , vreg , <NUM_LIT> ) , gen_gpr_to_xmm_move_src ( vmode , reg ) ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_conversion_insns ( seq , insn


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( ( ShifterImm . isASR <<


<s> virtual const char * getPassName ( ) const { return


<s> ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> )


<s> else if ( Align >= <NUM_LIT> && ( IsLE || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , LD -> getOffset ( ) , Offset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( IsLE || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , LD -> getOffset ( ) , Offset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Ops ) ; transferMemOperands ( N , New ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N ) ; return


<s> __attribute__ ( ( __vector_size__ ( <NUM_LIT> ) )


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << ( unsigned ) Binary << std :: dec << <STR_LIT> ; DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << ( unsigned ) ( Binary >> <NUM_LIT> ) << std :: dec << <STR_LIT> ; MCE . emitDWordLE ( Binary


<s> bool isCortexA8 ( ) const { return <ISA_LIT>ProcFamily ==


<s> gcc_assert ( REG_P ( slot ) ) ; emit_move_insn ( slot ,


<s> MachineFunction :: iterator OldNext = std :: next ( BBi ) ; bool B = TII -> analyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != & MF -> front ( ) && ! TII -> analyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( BB ) ; BB -> updateTerminator ( OldNext != MF -> end ( ) ? & * OldNext : nullptr ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; for ( const MachineBasicBlock :: RegisterMaskPair & RegMaskPair : BB -> liveins ( ) ) NewBB -> addLiveIn ( RegMaskPair ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> replaceSuccessor ( BB ,


<s> return ( __m128h ) __builtin_ia32_vfmsubsh3_mask3 ( ( __v8hf ) __W , ( __v8hf ) __A , (


<s> } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) >

<NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ;


<s> const LLT v16s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_INSERT , Ty } , Legal ) ; setAction ( { G_EXTRACT , <NUM_LIT> , Ty } , Legal ) ; } for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) { setAction ( { G_INSERT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_EXTRACT , Ty } , Legal ) ; } for ( const auto & Ty : { v32s8 , v64s8 , v16s16 , v32s16 , v8s32 , v16s32 , v4s64 , v8s64 } ) { setAction ( { G_MERGE_VALUES , Ty


<s> DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( &


<s> if ( Opc == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeBgtzGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address ,


<s> virtual ~ <ISA_LIT>CallingConventionRegisters ( )


<s> <STR_LIT> Cond ; if ( SDValue C = IsCMPZCSINC ( N , Cond ) ) if ( Cond == <STR_LIT> ) return C ; return SDValue (


<s> if ( ! ( Defs & ( <NUM_LIT> << RegNo ) ) ) Kills |= ( <NUM_LIT> << RegNo ) ; else Defs &= ~ ( <NUM_LIT> << RegNo ) ; } assert ( ( Kills & Defs ) == <NUM_LIT> && <STR_LIT> ) ; while ( Kills && Defs ) { unsigned KReg = countTrailingZeros ( Kills ) ; unsigned DReg = countTrailingZeros ( Defs ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> << DReg << <STR_LIT> ) ; std :: swap ( Stack [ getSlot ( KReg ) ] , Stack [ getSlot ( DReg ) ] ) ; std :: swap ( RegMap [ KReg ] , RegMap [ DReg ] ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; Defs &= ~ ( <NUM_LIT> << DReg ) ; } if ( Kills && I != MBB -> begin ( ) ) { MachineBasicBlock :: iterator I2 = std :: prev ( I ) ; while (


<s> for ( unsigned I = <NUM_LIT> ; I != array_lengthof ( HardFloatLibCalls ) ; ++ I ) { assert ( ( I == <NUM_LIT> || HardFloatLibCalls [ I - <NUM_LIT> ] < HardFloatLibCalls [ I ] ) && <STR_LIT> ) ; if ( HardFloatLibCalls [ I ] . Libcall != RTLIB :: UNKNOWN_LIBCALL ) setLibcallName ( HardFloatLibCalls [ I ] . Libcall , HardFloatLibCalls [ I ] . Name ) ; } setLibcallName ( RTLIB :: O_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: O_F32


<s> <ISA_LIT>3DNowLevel = NoThreeDNow ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false


<s> const LLT SrcTy = MRI . getType ( SrcReg ) ; assert ( ! ( SrcTy == LLT :: scalar ( <NUM_LIT> ) && DstTy == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( ! ( SrcTy == LLT :: scalar ( <NUM_LIT> ) && DstTy == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; const static struct ZextEntry { LLT SrcTy ; LLT DstTy ; unsigned MovOp ; bool NeedSubregToReg ; } OpTable [ ] = { { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , false } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , true } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , true } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> , true } } ; auto ZextEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ SrcTy , DstTy ] ( const ZextEntry & El ) { return El . DstTy == DstTy && El . SrcTy == SrcTy ; } ) ; if ( ZextEntryIt != std :: end ( OpTable ) ) { const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } unsigned TransitRegTo = DstReg ; unsigned TransitRegFrom = SrcReg ; if ( ZextEntryIt -> MovOp ) { if ( ZextEntryIt -> NeedSubregToReg ) { TransitRegFrom = MRI . createVirtualRegister ( getRegClass ( LLT :: scalar ( <NUM_LIT> ) , DstReg , MRI ) ) ; TransitRegTo = TransitRegFrom


<s> void <ISA_LIT>InstPrinter :: printAlignedLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( ) << <NUM_LIT> ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O <<


<s> register struct tostruct * top ; register struct tostruct * prevtop ; register long toindex ; static char already_setup ; if ( ! already_setup ) { extern char etext [ ] ; extern char _start [ ] ; extern char _init [ ] ; already_setup = <NUM_LIT> ; monstartup ( _start < _init ? _start : _init , etext ) ; on_exit ( _mcleanup , <NUM_LIT> ) ; atexit ( _mcleanup ) ; } if ( profiling ) { goto out ; } profiling ++ ; frompcindex = ( unsigned short * ) ( ( long ) frompcindex - ( long ) s_lowpc ) ; if ( ( unsigned long ) frompcindex > s_textsize ) { goto done ; } frompcindex = & froms [ ( ( long ) frompcindex ) / ( HASHFRACTION * sizeof ( * froms ) ) ] ; toindex = * frompcindex ; if ( toindex == <NUM_LIT> ) { toindex = ++ tos [ <NUM_LIT> ] . link ; if ( toindex >= tolimit ) { goto overflow ; } * frompcindex = toindex ; top = & tos [ toindex ] ; top -> selfpc = selfpc ; top -> count = <NUM_LIT> ; top -> link = <NUM_LIT> ; goto done ; } top = & tos [ toindex ] ; if ( top -> selfpc == selfpc ) { top -> count ++ ; goto done ; } for ( ; ; ) { if ( top -> link == <NUM_LIT> ) { toindex = ++ tos [ <NUM_LIT> ] . link ; if ( toindex >= tolimit ) { goto overflow ; } top = & tos [ toindex ] ; top -> selfpc = selfpc ; top -> count = <NUM_LIT> ; top -> link = * frompcindex ; * frompcindex = toindex


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( )


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) , MII ( MII ) , UC ( _Parser ) { MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> evaluateAsRelocatable ( Res ,


<s> SDValue Trmp = Op . getOperand ( <NUM_LIT> ) ; SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> :


<s> } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! U ) { if ( imm == <NUM_LIT> ) imm = INT32_MIN ; else imm = -


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS


<s> static bool moxie_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { int regno = REGNO ( reg ) ; if ( strict_p ) return HARD_REGNO_OK_FOR_BASE_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( reg_renumber [ regno ] ) ; else return ! HARD_REGISTER_NUM_P ( regno )


<s> const BinaryOperator * BinOp = dyn_cast < BinaryOperator > ( Inst ) ; if ( BinOp && isa < ConstantInt > ( BinOp -> getOperand ( <NUM_LIT> ) ) ) OpdIdx = <NUM_LIT> ; Last = Inst -> getOperand ( OpdIdx ) ; Inst = dyn_cast < Instruction > ( Last ) ; } while ( Inst && canGetThrough ( Inst ) && shouldGetThrough ( Inst ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Last << '\n' ) ; DenseMap < Value * , Instruction * > :: iterator AlreadySeen = SeenChains . find ( Last ) ; if ( insert || AlreadySeen != SeenChains . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SExtInsts . push_back ( SExt ) ; if ( AlreadySeen != SeenChains . end ( ) && AlreadySeen -> second != nullptr ) { DEBUG ( dbgs ( ) <<


<s> static __inline __m128d __attribute__ ( ( __always_inline__ ) ) _mm_load_sd ( double const * __P ) { return _mm_set_sd (


<s> Lo = DAG . getBitcast ( ByteVT , Lo ) ; Hi = DAG . getBitcast ( ByteVT , Hi ) ; if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getTargetConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( )


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM . isPositionIndependent (


<s> default : return false ; case <STR_LIT> : { CC = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( isZeroOrAllOnes ( N1 , AllOnes ) ) { Invert = false ; OtherOp = N2 ; return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : { if ( AllOnes ) return false ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; Invert = true ; return true ; } case <STR_LIT> : { CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> ,


<s> V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <=


<s> rtx nsse_reg ; int set ; tree fntype ; int stdarg_p ; int i ; if ( ! TARGET_64BIT ) return ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size ) return ; ix86_save_varrargs_registers = <NUM_LIT> ; cfun -> stack_alignment_needed = <NUM_LIT> ; fntype = TREE_TYPE ( current_function_decl ) ; stdarg_p = ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; next_cum = * cum ; if ( stdarg_p ) function_arg_advance ( & next_cum , mode , type , <NUM_LIT> ) ; if ( ! no_rtl ) save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; for ( i = next_cum . regno ; i < ix86_regparm && i < next_cum . regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( next_cum . sse_nregs && cfun -> va_list_fpr_size ) { label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( Pmode , label ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; nsse_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendqidi2 ( nsse_reg , gen_rtx_REG ( QImode , <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , gen_rtx_MULT ( Pmode , nsse_reg , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( next_cum . sse_regno ) emit_move_insn ( nsse_reg , gen_rtx_CONST ( DImode , gen_rtx_PLUS ( DImode , label_ref , GEN_INT ( next_cum . sse_regno * <NUM_LIT> ) ) ) ) ; else emit_move_insn ( nsse_reg ,


<s> InstructionCost <ISA_LIT>TTIImpl :: getGSVectorCost ( unsigned Opcode , Type * SrcVTy , const Value * Ptr , Align Alignment , unsigned AddressSpace ) { assert ( isa < VectorType > ( SrcVTy ) && <STR_LIT> ) ; unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; auto getIndexSizeInBits = [ ] ( const Value * Ptr , const DataLayout & DL ) { unsigned IndexSize = DL . getPointerSizeInBits ( ) ; const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; const Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; auto * IndexVTy = FixedVectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < InstructionCost , MVT > IdxsLT = TLI

-> getTypeLegalizationCost ( DL , IndexVTy ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) return ne ? <STR_LIT> : <STR_LIT> ; else if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> && ! mep_vliw_function_p ( cfun -> decl ) ) return ne ? <STR_LIT> : <STR_LIT> ; else return ne ? <STR_LIT> :


<s> for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * I -> getVectorNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , <NUM_LIT> , <NUM_LIT> ) + getMemoryOpCost ( Instruction :: Load , I , <NUM_LIT> , <NUM_LIT> ) ; } return


<s> static const char * const suffix [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_WRITE ) smclass = <NUM_LIT> ; else smclass = <NUM_LIT> ; fprintf ( asm_out_file , <STR_LIT> , ( flags & SECTION_CODE ) ? <STR_LIT> : <STR_LIT>

, name , suffix [ smclass ] , flags & SECTION_ENTSIZE ) ;


<s> case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , const1_rtx ) ) ; code = NE ; } break ; case LE : case UNLE : if ( code == LE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = LTU ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case EQ : case UNEQ : if ( code == EQ && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case NE : case LTGT : if ( code == NE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT>


<s> if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; Register Reg = VA . getLocReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return false ; if ( Outs [ I ] . Flags . isSwiftSelf ( ) || Outs [ I ] . Flags . isSwiftError (


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; } } else if ( CalleeMO . isGlobal ( ) ) { const GlobalValue * GValue = CalleeMO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create ( MOSymbol , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( SymVar ) ) ; EncodedBytes += <NUM_LIT>


<s> SDLoc DL ( N ) ; MVT VT = N . getSimpleValueType ( ) ; SDValue Copy = AM . Segment ; SDValue T = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; AM . Segment = T ; if ( matchAddress ( N , AM ) ) return false ; assert ( T == AM . Segment ) ; AM . Segment = Copy ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity


<s> for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlign ( FrameIdx ) ) ; NewMIs . back ( ) ->


<s> return isThumb ( ) && ( STI . getFeatureBits ( ) &


<s> reg_size = <NUM_LIT> ; } else if ( reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , reg , nregs ) ; return ; } else abort ( ) ; if ( offset != nregs * reg_size ) abort ( ) ; fprintf ( asm_out_file , <STR_LIT> ) ; offset = <NUM_LIT> ; lastreg = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= nregs ; i ++ ) { e = XVECEXP ( p , <NUM_LIT> , i ) ; if ( GET_CODE ( e ) != SET || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != MEM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG ) abort ( ) ; reg = REGNO ( XEXP ( e , <NUM_LIT> ) ) ; if ( reg < lastreg ) abort ( ) ; if ( i != <NUM_LIT> ) fprintf ( asm_out_file ,


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddI -> dump ( ) ) ; ++


<s> static tree mips_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( mips_builtins ) )


<s> void <ISA_LIT>Relocator :: applyDebugStringOffset ( Relocation &


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size


<s> case E_IFmode : case E_KFmode : extra = <NUM_LIT> ; break ; default : break ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = sext_hwi ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , gen_int_mode ( high_int , Pmode ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC_OR_PCREL && ! flag_pic && ! CONST_INT_P ( x ) && ! CONST_WIDE_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg , x ) ) ; else emit_insn ( gen_macho_high ( Pmode , reg , x ) ) ; return gen_rtx_LO_SUM ( Pmode , reg , x ) ; } else if ( TARGET_TOC && SYMBOL_REF_P ( x ) && constant_pool_expr_p ( x ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( x ) , Pmode ) ) return create_TOC_reference ( x , NULL_RTX ) ; else return x


<s> bool isZeroExtended ( const MachineInstr & MI , const unsigned depth = <NUM_LIT> )


<s> rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_CODE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE ) ; emit_move_insn ( mem ,


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc =


<s> if ( <STR_LIT> ( V2 ) || WillBeConstantPoolLoad ( V2 ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask


<s> bool mayNeedRelaxation ( const MCInst & Inst


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost =


<s> visited_bbs . reserve ( <NUM_LIT> ) ; basic_block bb ; FOR_EACH_BB_REVERSE_FN ( bb , fun ) for ( rtx_insn * next_i , * i = NEXT_INSN ( BB_HEAD ( bb ) ) ; i != NULL_RTX && i != BB_END ( bb ) ; i = next_i ) { next_i = NEXT_INSN ( i ) ; if ( ! INSN_P ( i ) || ! NONDEBUG_INSN_P ( i ) ) continue ; rtx setcc_val = const_setcc_value ( PATTERN ( i ) ) ; if ( setcc_val != NULL_RTX ) { update_ccreg_mode ( GET_MODE ( XEXP ( PATTERN ( i ) , <NUM_LIT> ) ) ) ; log_msg ( <STR_LIT> , bb -> index ) ; log_insn ( i ) ; log_msg ( <STR_LIT> ) ; ccreg_values . clear


<s> BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant >


<s> unsigned Opc = <NUM_LIT> ; Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) .


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> &&


<s> emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups ) ; return ; } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; } else { assert ( IndexReg . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; } emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_2 , StartByte , OS , Fixups ) ; return ; } bool UseDisp8 = MI . getFlags ( ) & <STR_LIT> ; bool UseDisp32 = MI . getFlags ( ) & <STR_LIT> ; bool AllowNoDisp = ! UseDisp8 && ! UseDisp32 ; bool AllowDisp8 = ! UseDisp32 ; if ( ! ForceSIB && IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! STI . hasFeature ( <STR_LIT> ) || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_4 , StartByte , OS , Fixups ) ; return ; } if ( BaseRegNo != N86 :: EBP ) { if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } if ( Disp . isExpr ( ) ) { auto * Sym = dyn_cast < MCSymbolRefExpr > ( Disp . getExpr ( ) ) ; if ( Sym && Sym -> getKind ( ) == MCSymbolRefExpr :: VK_TLSCALL ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Sym , FK_NONE , MI . getLoc ( ) ) ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } } } if ( Disp . isImm ( ) && AllowDisp8 ) { int ImmOffset = <NUM_LIT> ; if ( isDispOrCDisp8 ( TSFlags , Disp . getImm ( ) , ImmOffset ) ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups , ImmOffset ) ; return ; } } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; unsigned Opcode = MI . getOpcode ( ) ; unsigned FixupKind = Opcode == <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitSled ( const MachineInstr & MI , SledKind Kind ) { if ( MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ) { MI . emitError ( <STR_LIT> <STR_LIT> ) ; return ; } static const int8_t NoopsInSledCount = <NUM_LIT> ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; emitNops ( NoopsInSledCount )


<s> static unsigned copyPhysRegOpcode_AVX512 ( unsigned & DestReg , unsigned & SrcReg ) { if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return


<s> SDLoc DL ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Op . getValueType ( ) != <STR_LIT> ) return ; Op = SDValue ( DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getTargetConstant (

<STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> return ( __m256 ) __builtin_ia32_movshdup256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( ) ,


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & FuncInfo

, const TargetLibraryInfo * LibInfo ) const {


<s> PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister


<s> return __arm_vcaddq_rot90_x_f32 ( __a ,


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else report_fatal_error (


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v16qi ( ( __builtin_aarch64_simd_qi *


<s> if ( AluI == MachineBasicBlock :: iterator ( ) ) return false ; bool BaseIndexDef , AluDestRef ; MachineOperand * KilledBase , * KilledIndex ; checkRegUsage ( I , AluI , BaseIndexDef , AluDestRef , & KilledBase , & KilledIndex ) ; MachineBasicBlock :: iterator InsertPos = AluI ; if ( BaseIndexDef ) { if ( AluDestRef ) return false ; InsertPos = I ; KilledBase = KilledIndex = nullptr ; } Register AluDestReg = AluI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register BaseReg = I -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; Register IndexReg = I -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { BaseReg = TRI -> getSubReg ( BaseReg , <STR_LIT> ) ; IndexReg = TRI -> getSubReg ( IndexReg , <STR_LIT> ) ; } if ( AluDestReg == IndexReg ) { if ( BaseReg == IndexReg ) return false ; std :: swap ( BaseReg , IndexReg ) ; std :: swap ( KilledBase , KilledIndex ) ; } if ( BaseReg == IndexReg ) KilledBase = nullptr ; MachineInstr * NewMI1 , * NewMI2 ; unsigned NewOpcode = AluI -> getOpcode ( ) ; NewMI1 = BuildMI ( MBB , InsertPos , AluI -> getDebugLoc ( ) , TII -> get ( NewOpcode ) , AluDestReg ) . addReg ( AluDestReg , RegState :: Kill ) . addReg ( BaseReg , KilledBase ? RegState :: Kill : <NUM_LIT> ) ; NewMI1 -> addRegisterDead ( <STR_LIT> , TRI ) ; NewMI2 = BuildMI ( MBB , InsertPos , AluI -> getDebugLoc ( ) , TII -> get ( NewOpcode ) , AluDestReg ) . addReg ( AluDestReg , RegState :: Kill ) . addReg ( IndexReg , KilledIndex ? RegState :: Kill : <NUM_LIT> ) ; NewMI2 -> addRegisterDead ( <STR_LIT> , TRI ) ; if ( KilledBase ) KilledBase -> setIsKill ( false ) ; if ( KilledIndex ) KilledIndex -> setIsKill ( false ) ; MBB . getParent ( ) -> substituteDebugValuesForInst ( * AluI , * NewMI1 , <NUM_LIT> ) ; MBB . getParent ( ) -> substituteDebugValuesForInst ( * AluI , * NewMI2 ,


<s> bool <ISA_LIT>InstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ; MachineBasicBlock :: iterator I = LoopEnd -> getFirstTerminator ( ) ; if ( I != LoopEnd -> end ( ) && isBDNZ (


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO


<s> if ( GPRSaveSize != <NUM_LIT> ) { GPRIdx = MFI -> CreateStackObject ( GPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize ( FPRSaveSize


<s> void addVectorIndexSOperands ( MCInst & Inst ,


<s> } const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; SE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; if ( ! SE ) return false ; DarwinRefKind = SE -> getKind ( ) ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; auto AddendExpr = dyn_cast < MCConstantExpr > (


<s> static inline bool is_complex_IBM_long_double ( machine_mode mode ) { return mode == ICmode || ( ! TARGET_IEEEQUAD && mode


<s> I != E ; ++ I ) printModuleLevelGV ( I ) ; O << '\n' ; return AsmPrinter :: doFinalization ( M


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false


<s> return std :: make_unique < <ISA_LIT>ELFTargetObjectFile >


<s> SDValue InvMask = DAG . getNOT ( DL , Mask , VT ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Mask , In1 ) ; SDValue SelInv = DAG . getNode ( <STR_LIT> , DL , VT , InvMask , In2 ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> addr [ <NUM_LIT> ] = k ; addr [ <NUM_LIT> ]


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>BaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getHiLo16ImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; const MCExpr * E = MO . getExpr ( ) ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; MCFixupKind Kind


<s> emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , <NUM_LIT> ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out ,


<s> initGlobalBaseReg ( MF ) ; init<ISA_LIT>16SPAliasReg (


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; std :: vector < EVT > ResTys ; bool is64BitVector = VT . is64BitVector ( ) ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT>


<s> const MCOperand & SegReg = MI -> getOperand ( Op + <STR_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <STR_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; }


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef TuneCPU , StringRef FS ) { if ( CPU . empty ( ) ) CPU = <STR_LIT> ; if ( TuneCPU . empty ( ) ) TuneCPU = <STR_LIT> ; std :: string FullFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple ) ; assert ( ! FullFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SubVector1 , OffsetPtr , S -> getPointerInfo ( ) , S


<s> case ALTIVEC_BUILTIN_STVXL : return altivec_expand_stv_builtin ( CODE_FOR_altivec_stvxl , arglist ) ; case ALTIVEC_BUILTIN_MFVSCR : icode = CODE_FOR_altivec_mfvscr ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ; case ALTIVEC_BUILTIN_MTVSCR : icode = CODE_FOR_altivec_mtvscr ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_DSSALL : emit_insn ( gen_altivec_dssall ( ) ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_DSS : icode = CODE_FOR_altivec_dss ; arg0 = TREE_VALUE ( arglist ) ; STRIP_NOPS ( arg0 ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg0 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; emit_insn ( gen_altivec_dss ( op0 ) ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_VEC_INIT_V4SI : case ALTIVEC_BUILTIN_VEC_INIT_V8HI : case ALTIVEC_BUILTIN_VEC_INIT_V16QI : case ALTIVEC_BUILTIN_VEC_INIT_V4SF : return altivec_expand_vec_init_builtin ( TREE_TYPE ( exp ) , arglist , target ) ; case ALTIVEC_BUILTIN_VEC_SET_V4SI : case ALTIVEC_BUILTIN_VEC_SET_V8HI : case ALTIVEC_BUILTIN_VEC_SET_V16QI : case ALTIVEC_BUILTIN_VEC_SET_V4SF : return altivec_expand_vec_set_builtin ( arglist ) ; case ALTIVEC_BUILTIN_VEC_EXT_V4SI : case ALTIVEC_BUILTIN_VEC_EXT_V8HI


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; case <STR_LIT> : KnownZero |= APInt :: getHighBitsSet ( Mask . getBitWidth ( ) , Mask . getBitWidth ( ) - <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned IntId = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NumLoBits = <NUM_LIT> ; switch ( IntId ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { switch ( IntId ) { default : llvm_unreachable ( <STR_LIT>


<s> ReverseIter LastBr = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; if ( ( LastBr == End ) || ( ! LastBr -> isConditionalBranch ( ) && ! LastBr -> isUnconditionalBranch ( ) ) ) return ; ReverseIter FirstBr = getNonDebugInstr ( llvm :: next ( LastBr ) , End ) ; if ( ( FirstBr == End ) || ( ! FirstBr -> isConditionalBranch ( ) && ! FirstBr -> isUnconditionalBranch


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( TheThumbTarget


<s> for ( const MachineInstr & MI : * MBB )

BBI . Size += TII -> getInstSizeInBytes ( MI ) ;


<s> SDValue Glue = expandIntrinsicWChainHelper ( N , DL , DAG , Opcode , <NUM_LIT> , Subtarget , Results ) ; if ( Opcode != <STR_LIT> ) return ; SDValue Chain = Results [ <NUM_LIT> ] ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Glue ) ; Results [ <NUM_LIT> ] = ecx ; Results . push_back ( ecx . getValue ( <NUM_LIT>


<s> Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset = <NUM_LIT> ; } } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result

, MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> return false ; case V4DImode : if ( ! TARGET_64BIT ) return false ; case V4DFmode : case V8SFmode : case V8SImode : case V16HImode : case V32QImode : case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << <NUM_LIT> , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var


<s> return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; OutStreamer -> EmitValueToAlignment (


create<ISA_LIT>PagerandoOptimizerPass ( ) {


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this ,


<s> if ( ! MI . hasOneMemOperand ( ) ) return false ; if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ; const MachineMemOperand * MemOperand = * MI . memoperands_begin ( ) ; if ( MemOperand -> isVolatile ( ) ) return false ; return


<s> static void x86_print_call_or_nop ( FILE * file , const char * target ) { if ( flag_nop_mcount ) fprintf ( file , <STR_LIT> ) ; else fprintf ( file , <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmOpIdx = FIOperandNum + <NUM_LIT> ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ; if ( Offset % <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; } FIOp . ChangeToRegister ( <STR_LIT> , false ) ; ImmOp . setImm (


<s> if ( IsScale1 && ( DstR == BaseR || DstR == IndexR ) ) { const MachineOperand & Src = DstR == BaseR ? Index : Base ; MachineInstr * NewMI = BuildMI ( MBB , MI , DL , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( MBB , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } return NewMI ; } if ( ! IsInefficientBase || ( ! IsInefficientIndex && IsScale1 ) ) { MachineInstr * NewMI = BuildMI ( MBB , MI , DL , TII -> get ( LEAOpcode ) ) . add ( Dst ) . add ( IsInefficientBase ? Index : Base ) . add ( Scale ) . add ( IsInefficientBase ? Base : Index ) . addImm ( <NUM_LIT> ) . add ( Segment ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( MBB , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; LLVM_DEBUG ( NewMI -> dump ( ) ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT>


<s> Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( hasBasePointer ( MF


<s> getThumbBLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return encodeThumbBLOffset ( MO .


<s> for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) . getCalleeSavedInfo ( )

) if ( CSI . getReg ( ) == <STR_LIT> ) return true ;


<s> unsigned numSubRegs = <NUM_LIT> ; unsigned movOpc = <NUM_LIT> ; const unsigned * subRegIdx = nullptr ; const unsigned DFP_FP_SubRegsIdx [ ] = { <STR_LIT> , <STR_LIT> } ; const unsigned QFP_DFP_SubRegsIdx [ ] = { <STR_LIT> , <STR_LIT> } ; const unsigned QFP_FP_SubRegsIdx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . isV9 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { subRegIdx = DFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . isV9 ( ) ) { if ( Subtarget . hasHardQuad ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { subRegIdx = QFP_DFP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else { subRegIdx = QFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc =


<s> if ( TARGET_32BIT && DEFAULT_ABI == ABI_V4 ) { if ( rs6000_passes_vector ) fprintf ( asm_out_file , <STR_LIT> , ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( rs6000_returns_struct ) fprintf ( asm_out_file , <STR_LIT> , aix_struct_return ? <NUM_LIT> : <NUM_LIT> ) ; } if ( TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2 ) file_end_indicate_exec_stack ( ) ; if ( flag_split_stack ) file_end_indicate_split_stack ( ) ; if ( cpu_builtin_p ) { switch_to_section ( data_section ) ; fprintf ( asm_out_file , <STR_LIT> , TARGET_32BIT


<s> void <ISA_LIT>SETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; <ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee


<s> default : return <NUM_LIT> ; case <STR_LIT> : return


<s> if ( UseSoftFloat || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) return false ; return Imm . isZero ( ) || Imm .


<s> return gen_rtx_IOR ( DImode , src , GEN_INT (