<s> vec_uint4 bytes ; bits = vec_sl ( vec_and ( ( vec_ushort8 ) ( a ) , vec_splat_u16 ( <NUM_LIT> ) ) , ( ( vec_ushort8 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; bytes = ( vec_uint4 ) vec_sums ( ( vec_int4 ) ( vec_sum4s ( ( vec_short8 ) ( bits ) , (

vec_int4 ) { <NUM_LIT> } ) ) , ( vec_int4 ) { <NUM_LIT> } ) ;


<s> CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) ) { if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && !

isDispSafeForFrameIndex ( Val ) ) return true ;


<s> ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveThumb ( SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) .


<s> if ( Subtarget . hasAVX512 ( ) && ( Subtarget . useAVX512Regs ( ) || ! VT . is512BitVector ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ; bool AShift = LShift && VT != <STR_LIT> && VT != <STR_LIT> ; return ( Opcode == <STR_LIT> )


<s> virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment

, const MCAsmLayout & Layout ) const LLVM_OVERRIDE {


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx >= NumOps ) return false ; assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; assert ( ( ! isPrePost || ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx + <NUM_LIT> >= NumOps ) return false ; assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && ( OpInfo [ OpIdx + <NUM_LIT> ] . RegClass == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; if ( getIBit ( insn ) == <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg (


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this


<s> if ( isa < MCSymbolRefExpr > ( Disp ) && ! Info . IsVarDecl ) { unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : ( is32BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; return <STR_LIT> ( RegNo , Start , End , true , SMLoc ( ) , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) { if ( ! Size ) { Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , Start , End , Size , Identifier , Info


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) ->


<s> ASESet = <NUM_LIT> ; if ( P . hasDSP ( ) ) ASESet |= <STR_LIT> ; if ( P . hasDSPR2 ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMSA ( ) ) ASESet |= <STR_LIT> ; if ( P . inMicro<ISA_LIT>Mode ( ) ) ASESet |= <STR_LIT> ; if ( P . in<ISA_LIT>16Mode ( ) )


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned BitWidth = N1 . getValueSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; if ( DAG . getTargetLoweringInfo ( ) . SimplifyDemandedBits ( N1 , DemandedMask , DCI ) ) { DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } return SDValue (


<s> initializeFixupBWInstPassPass ( * PassRegistry :: getPassRegistry (


<s> return ; if ( MBBI == MBB . end ( ) ) return ; MachineBasicBlock :: iterator NI = std :: next ( MBBI ) ; if ( NI == MBB . end ( ) ) return ; unsigned Opc = NI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= NI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( NI ) ; MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes += NI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( NI ) ; MBBI =


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData (


<s> SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS .

getValueType ( ) != <STR_LIT> ) return Op ;


<s> return ( vector unsigned char ) __builtin_altivec_vperm_4si ( ( vector signed int ) a1 , ( vector signed int ) a2


<s> MVT VT = Op . getSimpleValueType ( ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned SHDOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( SHDOp , DL , VT , Op0


<s> switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind =


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Op1 || Op1 -> getOpcode ( ) != <STR_LIT> )


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( ! isLdStMul ) { MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm (


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode )

&& GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ;


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It


<s> if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ( ImmediateOffsetNeedsLowering || Addr . getOffsetReg ( ) ) && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , true ) ; else if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , false ) ; else ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) ) ; } if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffsetReg ( <NUM_LIT> ) ; Addr . setShift ( <NUM_LIT> ) ; Addr . setExtendType ( <STR_LIT> ) ; } if ( ImmediateOffsetNeedsLowering


<s> bool <ISA_LIT>16DAGToDAGISel :: selectAddr16 ( SDValue Addr , SDValue &


<s> bool <ISA_LIT>TargetLowering :: convertSelectOfConstantsToMath ( EVT


return create<ISA_LIT>MachORelocationInfo ( Ctx ) ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; getTargetStreamer ( ) . setCanHaveModuleDir ( false ) ; if ( ! mnemonicIsValid ( Name , <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; return Error ( NameLoc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc , * this ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) && ParseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( )


<s> vabdl_high_s32 ( int32x4_t a , int32x4_t b ) { int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> bool rs6000_keep_leaf_when_profiled ( void


<s> return __builtin_ia32_vcvtdq2ph512_mask_round ( ( __v16si ) __A , _mm256_setzero_ph ( ) , ( __mmask16 ) -


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , getEffectiveRelocModel (

TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) , Subtarget ( TargetTriple , CPU , computeFSAdditions ( FS , OL , TT ) , * this ) {


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( ContainerVT . isInteger ( ) && ( VT != ContainerVT ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load


<s> if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand (


<s> return __aarch64_vset_lane_any ( * __src , __vec ,


<s> if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm (


<s> MI . removeOperand ( i ) ; -- i ; -- e ; } assert ( ( ClobbersFPStack || STReturns == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! ClobbersFPStack ) return ; unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ; while ( StackTop > <NUM_LIT> ) popReg ( ) ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N - I - <NUM_LIT> ) ; if ( STReturns ) I


<s> static SDValue performSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Split = split16BStores ( N , DCI , DAG , Subtarget ) ; if ( Split . getNode ( ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG )


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( GV ) { int64_t GlobalOffset = <NUM_LIT> ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { std :: swap ( GlobalOffset , Offset ) ; } Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , GlobalOffset , OpFlags ) ; } else { Result = DAG . getTargetExternalSymbol ( ExternalSym , PtrVT , OpFlags ) ; } if ( ForCall && ! NeedsLoad && ! HasPICReg && Offset == <NUM_LIT> ) return Result ; Result = DAG . getNode ( getGlobalWrapperKind ( GV , OpFlags ) , dl , PtrVT , Result ) ; if ( HasPICReg )


<s> type = TYPE_MOFFS32 ; break ; case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } else if ( type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64 ) { uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO : type =


<s> if ( IsMasked ( & I ) ) { FixedVectorType * VecTy = getVectorType ( cast < IntrinsicInst > ( & I ) ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; } else if ( auto * Int = dyn_cast < IntrinsicInst > ( & I ) ) { if ( Int -> getIntrinsicID ( ) == <STR_LIT> ) continue ; for ( auto & U : Int ->


<s> DebugLoc dl = Node -> getDebugLoc ( ) ; EVT DestType = Node -> getValueType ( <NUM_LIT> ) ; unsigned DestWidth = DestType . getSizeInBits ( ) ; unsigned MOVOpcode ; EVT MOVType ; int UImm16 , Shift ; uint32_t LogicalBits ; uint64_t BitPat = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( A64Imms :: isMOVZImm ( DestWidth , BitPat , UImm16 , Shift ) ) { MOVType = DestType ; MOVOpcode = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( A64Imms :: isMOVNImm ( DestWidth , BitPat , UImm16 , Shift ) ) { MOVType = DestType ; MOVOpcode = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( DestWidth == <NUM_LIT> && A64Imms :: isMOVNImm ( <NUM_LIT> , BitPat , UImm16 , Shift ) ) { MOVType = <STR_LIT> ; MOVOpcode = <STR_LIT> ; } else if ( A64Imms :: isLogicalImm ( DestWidth , BitPat , LogicalBits ) ) { MOVOpcode = DestWidth == <NUM_LIT> ?


<s> static bool jumpTableFollowsTB ( MachineInstr * JTMI , MachineInstr * CPEMI ) { MachineFunction :: iterator MBB = JTMI ->


<s> in_order = true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned e = dcopy . perm [ i ] ; if ( GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> && e >= nelt && ( e & ( nelt / <NUM_LIT> - <NUM_LIT> ) ) < min ) e = e - min - ( nelt / <NUM_LIT> ) ; else e = e - min ; if ( e != i ) in_order = false ; dcopy . perm [ i ] = e ; } dcopy . one_operand_p = true ; if ( single_insn_only_p && ! in_order ) return false ; if ( d -> testing_p ) { if ( in_order ) return true ; dcopy . op1 = dcopy . op0 ; return expand_vec_perm_1 ( & dcopy ) ; } shift = GEN_INT ( min * GET_MODE_UNIT_BITSIZE ( d -> vmode ) ) ; if ( GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ) { target = gen_reg_rtx ( V1TImode ) ; emit_insn ( gen_ssse3_palignrv1ti ( target , gen_lowpart ( V1TImode , dcopy . op1 ) , gen_lowpart ( V1TImode , dcopy . op0 ) , shift ) ) ; } else { target = gen_reg_rtx ( V2TImode ) ; emit_insn ( gen_avx2_palignrv2ti ( target , gen_lowpart ( V2TImode , dcopy . op1 ) , gen_lowpart ( V2TImode , dcopy . op0 ) , shift ) ) ; } dcopy . op0 = dcopy . op1 = gen_lowpart ( d ->


<s> if ( ! OutVT . isVector ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT


<s> AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . Disp += BA -> getOffset ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; } else llvm_unreachable (


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ; return ( Len << <NUM_LIT> ) | ( Base << <NUM_LIT> ) |


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv4hi ( ( int16x4_t


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return Subtarget -> has<ISA_LIT>32r2Or64 ( ) ; default : return false


<s> case E_HImode : case E_SImode : case E_DImode : case E_TImode : return true ; case E_SFmode : case E_DFmode : case E_XFmode : case E_RFmode : return true ; case E_TFmode : return true ; default : return false


<s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) )


<s> static void EmitMoveRegReg ( const llvm :: MCSubtargetInfo & STI , bool Is64Bit , unsigned ToReg ,


<s> uint32_t getISAExtensionValue ( ) { return ( uint32_t ) ISAExtension


<s> if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] || Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> is32Bit ( ) ) return <NUM_LIT> ; return


<s> BuildMI ( MBB , II , dl , CopyInst , ActualNegSizeReg ) . addReg ( NegSizeReg ) . addReg ( NegSizeReg ) ; NegSizeReg = ActualNegSizeReg ; KillNegSizeReg = false ; } prepareDynamicAlloca ( II , NegSizeReg , KillNegSizeReg , FramePointer ) ; if ( NegSizeReg != ActualNegSizeReg ) BuildMI ( MBB , II , dl , CopyInst , ActualNegSizeReg ) . addReg ( NegSizeReg ) . addReg ( NegSizeReg ) ; MBB . erase ( II )


<s> OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } if ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && RelaxedOp == <STR_LIT> ) { Res . setOpcode ( RelaxedOp ) ; Res . addOperand ( MCOperand :: createImm


<s> SDValue Input0 , Input1 ; SmallVector < int , <NUM_LIT> > OpMask ; if ( ! resolveTargetShuffleInputs ( Op , Input0 , Input1 , OpMask ) ) return false ; assert ( VT . getVectorNumElements ( ) == OpMask . size ( ) && <STR_LIT> ) ; assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; int MaskWidth = std :: max < int > ( OpMask . size ( ) , RootMask . size ( ) ) ; int RootRatio = std :: max < int > ( <NUM_LIT> , OpMask . size ( ) / RootMask . size ( ) ) ; int OpRatio = std :: max < int > ( <NUM_LIT> , RootMask . size ( ) / OpMask . size ( ) ) ; assert ( ( ( RootRatio == <NUM_LIT> && OpRatio == <NUM_LIT> ) || ( RootRatio == <NUM_LIT> ) != ( OpRatio == <NUM_LIT> ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . reserve ( MaskWidth ) ; for ( int i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { int RootIdx = i / RootRatio ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask . push_back ( RootMask


<s> return ( __m128i ) __builtin_ia32_pmovsxwd128 ( ( __v8hi


<s> return decodeRegisterClass ( Inst , RegNo ,


_mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SDLoc dl ( Node ) ; EVT T = Node -> getValueType ( <NUM_LIT> ) ; SDValue negOp = DAG . getNode ( <STR_LIT> , dl , T , DAG . getConstant ( <NUM_LIT> , dl ,

T ) , Node -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasLazyResolverStub ( GV , TM ) ) return Lo ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Lo , NULL , <NUM_LIT> , false


<s> return IN_RANGE ( val , ( HOST_WIDE_INT_M1U << ( rx_max_constant_size * <NUM_LIT> ) ) , ( <NUM_LIT> << ( rx_max_constant_size * <NUM_LIT>


<s> if ( ! MBB -> isLiveIn ( <STR_LIT> ) ) MBB -> addLiveIn ( <STR_LIT> ) ; return NewMBB ; } ; auto EmitCondJump = [ & ] ( unsigned CC , MachineBasicBlock * ThenMBB ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ThenMBB ) . addImm ( CC ) ; auto * ElseMBB = CreateMBB ( ) ; MF -> insert ( InsPt , ElseMBB ) ; MBB = ElseMBB ; MBBI = MBB -> end ( ) ; } ; auto EmitCondJumpTarget = [ & ] ( unsigned CC , unsigned Target ) { auto * ThenMBB = CreateMBB ( ) ; TargetMBBs . push_back ( { ThenMBB , Target } ) ; EmitCondJump ( CC , ThenMBB ) ; } ; auto EmitTailCall = [ & ] ( unsigned Target ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) ) ; } ; std :: function < void ( unsigned , unsigned ) > EmitBranchFunnel = [ & ] ( unsigned FirstTarget , unsigned NumTargets ) { if ( NumTargets == <NUM_LIT> ) { EmitTailCall ( FirstTarget ) ; return ; } if ( NumTargets == <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT> ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget ) ; EmitTailCall ( FirstTarget + <NUM_LIT> ) ; return ; } if ( NumTargets < <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT> ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget + <NUM_LIT> ) ; EmitBranchFunnel ( FirstTarget + <NUM_LIT> , NumTargets - <NUM_LIT> ) ; return ; } auto * ThenMBB = CreateMBB ( ) ; CmpTarget ( FirstTarget + ( NumTargets / <NUM_LIT> ) ) ; EmitCondJump ( <STR_LIT> , ThenMBB ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget + ( NumTargets / <NUM_LIT> ) ) ; EmitBranchFunnel ( FirstTarget + ( NumTargets / <NUM_LIT> ) + <NUM_LIT> , NumTargets - ( NumTargets / <NUM_LIT> ) - <NUM_LIT> ) ; MF -> insert ( InsPt , ThenMBB ) ; MBB = ThenMBB ; MBBI = MBB -> end ( ) ; EmitBranchFunnel ( FirstTarget , NumTargets / <NUM_LIT> ) ; } ; EmitBranchFunnel ( <NUM_LIT> , ( JTInst -> getNumOperands ( ) - <NUM_LIT> ) /


<s> if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp )


<s> return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - <NUM_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( )


<s> EVT NewVT = getExtensionTo64Bits ( OrigTy ) ; return DAG . getNode ( ExtOpcode , N -> getDebugLoc ( ) , NewVT


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode


<s> bool from_partial_sve_p = from_sve_p && ( from_flags & VEC_PARTIAL ) ; bool to_partial_sve_p = to_sve_p && ( to_flags & VEC_PARTIAL ) ; bool from_pred_p = ( from_flags & VEC_SVE_PRED ) ; bool to_pred_p = ( to_flags & VEC_SVE_PRED ) ; if ( from_pred_p != to_pred_p ) return false ; if ( from_partial_sve_p != to_partial_sve_p ) return false ; if ( from_partial_sve_p && ( aarch64_sve_container_bits ( from ) != aarch64_sve_container_bits ( to ) || GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) ) return false ; if ( maybe_ne ( BITS_PER_SVE_VECTOR , <NUM_LIT> ) ) { if ( from_sve_p && ! to_sve_p && maybe_gt ( GET_MODE_BITSIZE ( to ) ,


<s> } } if ( mova_p ( from ) ) { switch ( untangle_mova ( & num_mova , & mova , from ) ) { case <NUM_LIT> : if ( flag_pic ) { rtx src = SET_SRC ( PATTERN ( from ) ) ; if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_SYMOFF ) last_symoff = from ; } break ; case <NUM_LIT> : return find_barrier ( <NUM_LIT> , <NUM_LIT> , mova ) ; case <NUM_LIT> : { leading_mova = <NUM_LIT> ; barrier_before_mova = good_barrier ? good_barrier : found_barrier ; } default : break ; } if ( found_si > count_si ) count_si = found_si ; } else if ( JUMP_TABLE_DATA_P ( from ) && GET_CODE ( PATTERN ( from ) ) == ADDR_DIFF_VEC ) { if ( ( num_mova > <NUM_LIT> && GET_MODE ( prev_nonnote_insn ( from ) ) == VOIDmode ) || ( num_mova && ( prev_nonnote_insn ( from ) == XEXP ( MOVA_LABELREF ( mova ) , <NUM_LIT> ) ) ) ) num_mova -- ; if ( barrier_align ( next_real_insn ( from ) ) == align_jumps . levels [ <NUM_LIT> ] . log ) { good_barrier = found_barrier ; break ; } else { rtx body = PATTERN ( from ) ; inc = XVECLEN ( body , <NUM_LIT> ) * GET_MODE_SIZE ( GET_MODE ( body ) ) ; } } else if ( JUMP_P ( from ) && ! TARGET_SH2 && ! optimize_size ) new_align = <NUM_LIT> ; if ( JUMP_P ( from ) && get_attr_type ( from ) == TYPE_CBRANCH && ! sequence_insn_p ( from ) ) inc += <NUM_LIT> ; if ( found_si ) { count_si += inc ; if ( new_align > si_align ) { si_limit -= ( count_si - <NUM_LIT> ) & ( new_align - si_align ) ; si_align = new_align ; } count_si = ( count_si + new_align - <NUM_LIT> ) & - new_align ; } if ( found_hi ) { count_hi += inc ; if ( new_align > hi_align ) { hi_limit -= ( count_hi - <NUM_LIT> ) & ( new_align - hi_align ) ; hi_align = new_align ; } count_hi = ( count_hi + new_align - <NUM_LIT> ) & - new_align ; } from = NEXT_INSN ( from ) ; } if ( num_mova ) { if ( leading_mova ) { fixup_mova ( mova ) ; return find_barrier ( <NUM_LIT> , <NUM_LIT> ,


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( ( mips_abi == ABI_32 && TARGET_FLOAT32 ) && FP_RETURN != GP_RETURN && (

regno == FP_RETURN + <NUM_LIT> || regno == FP_RETURN + <NUM_LIT> ) ) return true ;


<s> if ( ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode )


<s> bool isSVEFPImm8 ( ) const { return Kind == k_FPImm && ( getFPImm ( ) != ( unsigned ) - <NUM_LIT>


<s> __inline__ static unsigned char sh_media_NSB ( long long mm ) { unsigned char res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> (


<s> static unsigned getPrefixes ( OperandVector & Operands ) { unsigned Result = <NUM_LIT> ; <ISA_LIT>Operand & Prefix = static_cast < <ISA_LIT>Operand & > ( * Operands . back ( ) ) ; if ( Prefix . isPrefix ( ) ) { Result = Prefix .


<s> StringRef Kind ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ParseSuffix && Kind . empty ( ) ) return MatchOperand_NoMatch ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEDataVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , S , getContext ( ) ) ) ; OperandMatchResultTy Res = tryParseVectorIndex ( Operands ) ; if ( Res == MatchOperand_ParseFail ) return MatchOperand_ParseFail ; return MatchOperand_Success ; } getParser ( ) .


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT>


<s> inline vector unsigned int vec_mergel ( vector unsigned int a1 , vector unsigned int


<s> const SMLoc S = getLoc ( ) ; StringRef Kind ; int RegNum = - <NUM_LIT> ; auto Res = tryParseSVERegister ( RegNum , Kind , RegKind :: SVEPredicateVector ) ; if ( Res != MatchOperand_Success ) return Res ; unsigned ElementWidth = StringSwitch < unsigned > ( Kind . lower ( ) ) . Case ( <STR_LIT> , - <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! ElementWidth


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( )


<s> if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; if ( Subtarget -> isTargetWindows ( ) && Addr . getGlobalValue ( ) && Addr . getGlobalValue ( ) -> hasExternalWeakLinkage ( ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? getBLRCallOpcode ( * MF ) : ( unsigned ) <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol ,


<s> switch ( Modifier ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> if ( skipFunction ( mf . getFunction ( ) ) ) return false ; MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget ( ) .


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O


<s> vst1q_p64 ( poly64_t * a , poly64x2_t b ) { __builtin_aarch64_st1v2di_sp ( ( __builtin_aarch64_simd_di * ) a , ( poly64x2_t


<s> return ( __m128d ) __builtin_ia32_getexpsd_mask_round ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) , (


<s> while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE (


<s> auto MOTW = llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) )

CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo ::


<s> cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else if ( TARGET_OUTLINE_ATOMICS ) { if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; rtx func = aarch64_atomic_ool_func ( mode , mod_s , & aarch64_ool_cas_names ) ; rval = emit_library_call_value ( func , NULL_RTX , LCT_NORMAL , r_mode , oldval , mode , newval , mode , XEXP ( mem , <NUM_LIT> ) , Pmode ) ; cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else { insn_code code = code_for_aarch64_compare_and_swap ( mode ) ; if ( ! insn_data [ code ] . operand [ <NUM_LIT> ] . predicate ( oldval , mode ) ) oldval = force_reg ( mode


<s> case <STR_LIT> : ImmOpnd = & MBBI -> getOperand ( ImmIdx ) ; break ; } if ( ImmOpnd ) ImmOpnd -> setImm ( ImmOpnd


<s> if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == <NUM_LIT> || ( MIN_FPRS_PER_FMT == <NUM_LIT> && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= <NUM_LIT> && ( regno & <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & <NUM_LIT> ) != <NUM_LIT> ) ; if ( TARGET_LOONGSON_MMI && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * <NUM_LIT> ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * <NUM_LIT> && ( ( regno - DSP_ACC_REG_FIRST

) & <NUM_LIT> ) == <NUM_LIT> ) return true ;


<s> if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == HARD_FRAME_POINTER_REGNUM ) { moxie_compute_frame ( ) ; ret = - cfun -> machine -> callee_saved_reg_size ; } else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == HARD_FRAME_POINTER_REGNUM ) ret = <NUM_LIT> ; else abort (


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ]


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA


<s> getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return


<s> O << ( uint64_t ) MI -> getOperand ( OpNo ) . getImm


<s> if ( CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) return CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return JumpTableEntryIndices [ CPEMI -> getOperand ( <NUM_LIT> ) . getIndex (


<s> if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) &&

! FLOAT128_IEEE_P ( mode ) ) return true ;


<s> return isSImm < <NUM_LIT> , <NUM_LIT> >


<s> tree ix86_handle_shared_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) !=


<s> report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & <NUM_LIT> ) == <NUM_LIT> ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return <NUM_LIT> ; if ( TARGET_REDUCED_REGS ) start_regno = <NUM_LIT> ; else start_regno = <NUM_LIT> ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ <NUM_LIT> ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m =


<s> const auto * I = cast < Instruction > ( V ) ; if ( FuncInfo . MBBMap [ I -> getParent ( )


<s> return ( __m128i ) __builtin_ia32_pmovzxbd128 (


<s> assert ( m_pRelDyn != NULL && <STR_LIT> ) ; return *


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( unsigned short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo , STI ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi (


<s> MIRBuilder . getMRI ( ) -> addLiveIn (


<s> return ( vector float ) __builtin_altivec_vmaddfp ( ( vector float ) a1 , ( vector float


<s> if ( mips_near_type_p ( type1 ) && mips_far_type_p ( type2 ) ) return


<s> Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) return false ; if ( ! State . AllocateReg ( ArgGPRs ) ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true


<s> __tmp . f = __builtin_ia32_vec_ext_v4sf ( ( __v4sf ) __X , __N ) ; return __tmp . i


<s> if ( isa < MemIntrinsicSDNode > ( Root ) ) return cast < MemIntrinsicSDNode > ( Root ) -> getMemoryVT ( ) ; const unsigned Opcode = Root -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; case


<s> static SDValue getTargetShuffleNode ( unsigned Opc , DebugLoc dl , EVT VT , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } I -> eraseFromParent ( ) ; Paired -> eraseFromParent ( ) ; return NextI


<s> if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue (


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT>


<s> } if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; SmallVector < APInt , <NUM_LIT> > SrcPartials ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps , & SrcPartials ) && SrcOps . size ( ) == <NUM_LIT> ) { unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ; } } } if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( SDValue R = combineBitOpWithShift ( N , DAG ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , DCI , Subtarget ) ) return FPLogic ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; APInt UpperElts = APInt :: getHighBitsSet ( NumElts , HalfElts ) ; if ( NumElts >= <NUM_LIT> && N1 . getOpcode ( ) == <STR_LIT> && N1 . getConstantOperandAPInt ( <NUM_LIT> ) == HalfElts && DAG . MaskedValueIsZero ( N0 , APInt

( <NUM_LIT> , <NUM_LIT> ) , UpperElts ) ) {


<s> unsigned NumRegs = TLI . getNumRegistersForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; ++ i ) { <STR_LIT> Flags = Arg . Flags [ <NUM_LIT> ] ; if ( i == <NUM_LIT> ) Flags . setOrigAlign ( TLI . getABIAlignmentForCallingConv ( Arg . Ty , DL ) ) ; else Flags . setOrigAlign ( Align ( <NUM_LIT> ) ) ; ISDArgs . emplace_back ( Flags , RegisterVT , VT , true , OrigArgIndices [ ArgNo ] , <NUM_LIT> ) ; } ++ ArgNo


<s> MachineInstrBuilder MIB = MIRBuilder . buildInstr ( <STR_LIT> ) ; assert ( MIB . getInstr ( ) && <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; if ( VReg ) { MIRBuilder . setInstr ( * MIB . getInstr ( ) , true ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; handleAssignments ( MIRBuilder , AssignFn , <STR_LIT> ( Val -> getType ( ) ) , VReg , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } ) ; } return true


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFCCReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_FCC , RegInfo , S , E


<s> MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FCCRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler


<s> static SDValue getTruncateOrZeroExtend ( SDValue V , SelectionDAG & DAG , MVT ToVT ) { SDNodeTreeBuilder b ( V , & DAG ) ; MVT VT = V .


<s> II = TM . getInstrInfo ( ) ; TD = TM . getTargetData ( ) ; Is64BitMode = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; do { DEBUG ( dbgs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { const MCInstrDesc & Desc = I -> getDesc ( ) ; emitInstruction ( * I ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValueSub1 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return MI . getOperand ( OpNo ) . getImm ( ) -


<s> static DecodeStatus DecodeVecShiftR16ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , isO32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , Subtarget -> mipsSEUsesSoftFloat ( ) , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc (


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; unsigned Opcode = MI . getOpcode


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand & MO2 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; ShapeT Shape ( & MO1 , & MO2


<s> reg_parm_stack_space = <NUM_LIT> ; break ; case ABI_AIX : case ABI_DARWIN : reg_parm_stack_space = TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_ELFv2 : if ( rs6000_function_parms_need_stack ( fun , incoming ) ) reg_parm_stack_space = TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ; else reg_parm_stack_space = <NUM_LIT> ; break ; } return reg_parm_stack_space


<s> return ( unsigned ) __builtin_ia32_vcvttss2usi32 ( ( __v4sf ) __A ,


<s> MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , TII . get ( Opcode ) ) ; unsigned NumAddrOps = MOs . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; if ( NumAddrOps < <NUM_LIT> ) MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return MIB . addImm (


<s> if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { if ( NoHelperNeeded . find ( S -> getSymbol ( ) ) != NoHelperNeeded . end ( ) ) { LookupHelper = false ; } } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . Args , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg ,


<s> rel_entry . setType ( pTarget . getCopyRelType ( ) ) ; assert ( pSym . outSymbol ( ) -> hasFragRef ( ) ) ; rel_entry . targetRef ( ) . assign ( * pSym .


<s> MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( )


<s> bool <ISA_LIT>LowerMASSVEntries :: lowerMASSVCall ( CallInst * CI , Function & Func , Module & M , const <ISA_LIT>Subtarget * Subtarget ) { if ( CI -> use_empty ( ) ) return false ; std :: string MASSVEntryName = createMASSVFuncName ( Func , Subtarget ) ; FunctionCallee FCache = M . getOrInsertFunction ( MASSVEntryName , Func . getFunctionType ( ) , Func . getAttributes ( ) ) ; CI -> setCalledFunction (


<s> static <ISA_LIT>Operand * createInvalid ( SMLoc


<s> rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> ,


<s> if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; } SDVTList VTs = DAG . getVTList ( CmpVT , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1


<s> CurrMI = & ( MBB -> instr_back ( ) ) ; } } liveInstrs . insert ( CurrMI ) ; VisitedBBlist . insert ( CurrMI -> getParent ( ) ) ; while ( MachineInstr * MI = CurrMI -> getPrevNode ( ) ) { CurrMI = MI ; if ( MI == def ) break ; liveInstrs . insert ( CurrMI ) ; } if ( CurrMI != def ) { for ( MachineBasicBlock * MBB : CurrMI -> getParent ( ) -> predecessors ( ) ) { if ( ! VisitedBBlist . count ( MBB ) ) BBlist . push ( MBB ) ; } } while ( ! BBlist . empty ( ) ) { MachineBasicBlock * curBB = BBlist . top ( ) ; BBlist . pop ( ) ; if ( VisitedBBlist . count ( curBB ) ) { continue ; } VisitedBBlist . insert ( curBB ) ; if ( curBB -> empty ( ) ) { for ( MachineBasicBlock * MBB : curBB -> predecessors ( ) ) { if ( ! VisitedBBlist . count ( MBB ) ) BBlist . push ( MBB ) ; } continue ; } CurrMI = & ( curBB -> instr_back ( ) ) ; for ( MachineInstr * MI = CurrMI ; MI != NULL ; MI = CurrMI -> getPrevNode ( ) ) { CurrMI = MI ; if ( MI == def ) break ; liveInstrs . insert ( CurrMI ) ; } if ( CurrMI != def ) { for ( MachineBasicBlock * MBB : CurrMI -> getParent ( ) -> predecessors ( ) ) { if ( ! VisitedBBlist . count ( MBB ) ) BBlist . push ( MBB ) ; } } } } for ( std :: set < MachineInstr * > :: iterator i = liveInstrs . begin ( ) ; i != liveInstrs . end ( ) ; ) { if ( ( * i ) -> isPHI ( ) ) { i = liveInstrs . erase ( i ) ; } else { ++ i ; } } LR -> addLiveInstrs (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( LHS ) && ! DAG . isConstantIntBuildVectorOrConstantInt ( RHS ) ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , RHS , LHS ) ; if ( <STR_LIT> ( RHS . getNode ( ) ) ) return RHS ; APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; SDValue DemandedLHS = DAG . GetDemandedBits ( LHS , DemandedMask ) ; SDValue DemandedRHS = DAG . GetDemandedBits ( RHS , DemandedMask ) ; if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsO32 ( ) ) return makeArrayRef (


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ; return X


<s> int Latency = <ISA_LIT>GenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } u ; u . v = a ; u . i [ pos ] = b ; return u


<s> MachineInstr * A15SDOptimizer :: elideCopies ( MachineInstr * MI ) { if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! TRI -> isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MachineInstr * Def = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! Def ) return nullptr ; return elideCopies ( Def


<s> SDValue <ISA_LIT>TargetLowering :: LowerDIV ( SDValue Op , SelectionDAG & DAG , unsigned NewOp ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector


<s> SDValue Perm = DAG . getNode ( <STR_LIT> , dl , VecVT , Mask , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Perm , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ) ; } return SDValue ( ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal ,


<s> SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> ) { O << <STR_LIT> ; if ( L == <NUM_LIT> || L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O ,


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym ->


<s> gcc_assert ( GET_CODE ( real ) == PARALLEL ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( real , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( real , <NUM_LIT> , i ) ) == SET ) { rtx set = XVECEXP ( real , <NUM_LIT> , i ) ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitExternalGlobal ( const GlobalVariable * GV ) { std :: string Name = getGlobalLinkName ( GV ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( GV -> hasHiddenVisibility ( ) ) HiddenGVStubs . insert ( Name ) ; else GVStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; return ; } O << Name


<s> return convReg ( BusyRegs [ REG_OFFSET_ADDRESS ]


<s> return __builtin_aarch64_sshlv4hi ( __a ,


<s> else if ( mode == DFmode || mode == DImode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case QImode : store_string = <STR_LIT> ; break ; case HImode : store_string = <STR_LIT> ; break ; case SImode : case SFmode : store_string = <STR_LIT> ; break ; case DImode : case DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else fatal_insn ( <STR_LIT> , reg ) ; if ( ! MEM_P ( mem ) ) fatal_insn ( <STR_LIT> , mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; fusion_split_address ( addr , & hi , & lo ) ; emit_fusion_addis ( tmp_reg , hi , <STR_LIT> , GET_MODE_NAME ( mode ) ) ; emit_fusion_load_store ( reg , tmp_reg , lo , store_string ) ; return <STR_LIT>


<s> if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( INTEGER_CLASS_P ( regclass ) ) return regclass ; if ( IS_STACK_MODE ( mode ) && standard_80387_constant_p ( x ) > <NUM_LIT> ) { if ( FLOAT_CLASS_P ( regclass ) ) return FLOAT_REGS ; } return NO_REGS


<s> unsigned getStartOpcode ( ) const { bool IsDo = isDoLoopStart ( * Start ) ; if ( ! IsTailPredicationLegal ( ) ) return IsDo


<s> MachineOperand Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , Modifier ) ; O << ':' ; } printLeaMemReference ( MI , Op ,


<s> assert ( Fixup . Offset + Size <= DF . getContents ( ) . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) DF . getContents ( ) [ Fixup . Offset + i ] = uint8_t ( Value >> (


<s> case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getMBB


<s> if ( ! TARGET_64BIT ) { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; if ( ASSEMBLER_DIALECT == <NUM_LIT> ) fputs ( <STR_LIT> , f ) ; else fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; if ( TARGET_PA_20 ) { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> ,


<s> default : return get<ISA_LIT>SubSuperRegister_ ( Reg , <STR_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( info != <NUM_LIT> ) { mips_arch_info = info ; mips_arch = info -> cpu


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo


<s> void llvm :: createSplat2ShuffleMask ( MVT VT , SmallVectorImpl < int > & Mask , bool Lo ) { assert ( Mask . empty ( ) && <STR_LIT> ) ; int NumElts = VT . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { int Pos = i / <NUM_LIT> ; Pos += ( Lo ? <NUM_LIT> : NumElts / <NUM_LIT> ) ; Mask . push_back (


<s> static rtx_insn * aarch64_prev_real_insn ( rtx_insn * insn ) { if ( ! insn ) return NULL ; do { insn = prev_real_insn ( insn


<s> unsigned getNumFixupKinds ( ) const { return


<s> static bool arm_macro_fusion_p ( void ) { return current_tune -> fusible_ops !=


<s> case VK_<ISA_LIT>_LO : return SignExtend64 < <NUM_LIT> > ( Value ) ; case VK_<ISA_LIT>_HI : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) &


<s> MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxLogAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } LLVM_DEBUG ( BB -> dump


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = <NUM_LIT> ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence (


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < <NUM_LIT>


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) ||

Memory . Alignment != <NUM_LIT> ) return false ;


<s> const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned i = <NUM_LIT> , e = CSI . size ( ) ; for ( ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg (


<s> unsigned Size = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<=


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * Info = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( Info ) ; return


<s> return __builtin_ia32_vcvtw2ph512_mask_round ( ( __v32hi ) __B , _mm512_setzero_ph ( )


<s> void addAdrLabelOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> } } else if ( i == nargs - <NUM_LIT> ) { if ( ! insn_p -> operand [ nargs ] . predicate ( op , SImode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( INTVAL ( op ) == NO_ROUND ) redundant_embed_rnd = <NUM_LIT> ; } else { if ( VECTOR_MODE_P ( mode ) ) op = safe_vector_operand ( op , mode ) ; op = fixup_modeless_constant ( op , mode ) ; if ( GET_MODE ( op ) == mode || GET_MODE ( op ) == VOIDmode ) { if ( optimize || ! match ) op = copy_to_mode_reg ( mode , op ) ; } else { op = copy_to_reg ( op ) ; op = simplify_gen_subreg ( mode , op , GET_MODE ( op ) , <NUM_LIT> ) ; } } args [ i ] . op = op ; args [ i ] . mode = mode ; } switch ( nargs ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return <NUM_LIT> ; if ( redundant_embed_rnd ) pat = ix86_erase_embedded_rounding ( pat ) ; emit_insn (


<s> Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : FixupKind =


<s> tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , <NUM_LIT> ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , <NUM_LIT> ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type )


<s> return Create ( VK_<ISA_LIT>_HI16 , Expr


<s> if ( mode == V16QImode || mode == V32QImode ) { int extra = <NUM_LIT> ; if ( TARGET_XOP && mode == V16QImode ) extra = <NUM_LIT> ; else if ( TARGET_SSSE3 ) extra = <NUM_LIT> ; return ix86_vec_cost ( mode , cost -> mulss * <NUM_LIT> + cost -> sse_op * extra ) ; } else if ( mode == V2DImode || mode == V4DImode ) { if ( TARGET_XOP && mode == V2DImode ) return ix86_vec_cost ( mode , cost -> mulss * <NUM_LIT> +


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV


<s> void LLVMInitialize<ISA_LIT>MCRegisterInfo ( ) { TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target ,


<s> return ( long long ) __builtin_ia32_vcvtss2si64 ( ( __v4sf ) __A , __R


<s> SDValue SubtractCarry = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , ShiftR , ShiftL , SubtractCarry ) , <NUM_LIT> ) ; } case <STR_LIT> : { if ( IsRHSNegOne ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GEZExt ) ; if ( IsRHSZero ) { SDValue Addi = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue Nor = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addi , LHS ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Nor , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } std :: swap ( LHS , RHS ) ; ConstantSDNode * RHSConst = dyn_cast < ConstantSDNode > ( RHS ) ; IsRHSZero = RHSConst && RHSConst -> isZero ( ) ; IsRHSOne = RHSConst && RHSConst -> getSExtValue ( ) == <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { if ( IsRHSOne ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: LEZExt ) ; if ( IsRHSZero ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue SRADINode = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue SRDINode = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , RHS , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue SUBFC8Carry = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , RHS , LHS ) , <NUM_LIT> ) ; SDValue ADDE8Node = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SRDINode , SRADINode , SUBFC8Carry ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ADDE8Node , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue SUBFC8Carry = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LHS


<s> static bool isLDSTPPI ( InsnType insn ) { return ( ( ( insn ) &


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> return __aarch64_vget_lane_any ( __a ,


<s> const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; int ImmLo = ( short ) ( OrigImm & <NUM_LIT> ) ; int ImmHi = ( ( ( unsigned ) OrigImm & <NUM_LIT> ) >> <NUM_LIT> ) + ( ( OrigImm & <NUM_LIT> ) != <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT>


<s> return ( uint16x8_t ) __builtin_neon_vshluv8hi ( ( int16x8_t ) __a ,


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || MI . getOpcode ( ) == <STR_LIT> ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; return false ; } } Predicated . insert ( MI ) ; } SmallSet < Register , <NUM_LIT> > LiveOuts ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; for ( auto * MBB : ExitBlocks ) for ( const MachineBasicBlock :: RegisterMaskPair & RegMask : MBB -> liveins ( ) ) if ( QPRs -> contains ( RegMask . PhysReg ) ) LiveOuts . insert ( RegMask . PhysReg ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveMIs ; assert ( ML . getNumBlocks ( ) ==


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; EVT SclVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! SclVT . isScalarInteger ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Vec ; SmallVector < int , <NUM_LIT> > ShuffleMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts == SclVT . getSizeInBits ( ) && <STR_LIT> ) ; if ( NumElts > EltSizeInBits ) { assert ( ( NumElts % EltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = NumElts / EltSizeInBits ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , EltSizeInBits ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; Vec = DAG . getBitcast ( VT , Vec ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) ShuffleMask . append ( EltSizeInBits , i ) ; Vec = DAG . getVectorShuffle ( VT , DL , Vec , Vec , ShuffleMask ) ; } else if ( Subtarget . hasAVX2 ( ) && NumElts < EltSizeInBits && ( SclVT == <STR_LIT> || SclVT == <STR_LIT> || SclVT == <STR_LIT> ) ) { assert ( ( EltSizeInBits % NumElts ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = EltSizeInBits / NumElts ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , NumElts


<s> if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromHi = DAG . getCopyFromReg ( InChain , DL , HI , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromHi ) ; } return SDValue (


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MFI -> hasVarSizedObjects ( ) || spillsCR ( MF ) || spillsVRSAVE ( MF ) || hasNonRISpills ( MF ) || ( hasSpills ( MF ) && ! isInt < <NUM_LIT> > ( StackSize ) ) ) { const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = Subtarget . is<ISA_LIT>64 ( ) ? G8RC : GPRC ; RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; if ( spillsCR ( MF ) || spillsVRSAVE ( MF ) ) RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC


<s> assert ( ( ResVT . is256BitVector ( ) || ResVT . is512BitVector ( ) ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; if ( ResVT . is256BitVector ( ) ) return concat128BitVectors ( V1 , V2 , ResVT , NumElems , DAG , dl ) ; if ( Op . getNumOperands ( ) == <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue V3 = Op . getOperand ( <NUM_LIT> ) ; SDValue V4 = Op . getOperand ( <NUM_LIT> ) ; return concat256BitVectors ( concat128BitVectors ( V1 , V2 , HalfVT , NumElems / <NUM_LIT> , DAG , dl ) , concat128BitVectors ( V3 , V4 , HalfVT , NumElems / <NUM_LIT> , DAG , dl )


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo *


<s> ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( )


<s> void addInst ( MachineInstr * MI , SetVector < MachineInstr * > & Preds ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( ! Divergent && ! set_difference ( Preds , VPST -> Predicates ) . empty ( ) ) { Divergent = & Insts . back ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Divergent -> MI ) ; } Insts . emplace_back ( MI , Preds ) ; assert ( Insts . size ( ) <= <NUM_LIT> &&


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! Subtarget -> hasVFP3Base ( ) ) return false ; if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) && <STR_LIT> ( Imm ) != - <NUM_LIT> ) return true ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != -


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; result = ( poly8x8_t ) __builtin_aarch64_tbx4v8qi ( ( int8x8_t ) __r , __o , ( int8x8_t ) __idx ) ; return result


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream &


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMSA128Reg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_MSA128 , RegInfo , S , E


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move (

OW ) , std :: move ( Emitter ) ) , IsThumb ( IsThumb ) {


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property ::


<s> static bool aarch64_evpc_dup ( struct expand_vec_perm_d * d ) { rtx out = d -> target ; rtx in0 ; HOST_WIDE_INT elt ; machine_mode vmode = d -> vmode ; rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( d -> vec_flags == VEC_SVE_DATA && elt >= <NUM_LIT> * GET_MODE_UNIT_SIZE ( vmode ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; lane = GEN_INT ( elt


<s> case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; return false ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; return false ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; return false ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; return false ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; return false


<s> unsigned NativeWidth = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) { return needsCmpXchgNb ( MemType ) ? AtomicRMWExpansionKind :: CmpXChg : AtomicRMWExpansionKind :: None ; } AtomicRMWInst :: BinOp Op = AI -> getOperation ( ) ; switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : case AtomicRMWInst :: Add : case AtomicRMWInst :: Sub : return AtomicRMWExpansionKind :: None ; case AtomicRMWInst :: Or : case AtomicRMWInst :: And : case AtomicRMWInst :: Xor : return ! AI -> use_empty ( ) ? AtomicRMWExpansionKind :: CmpXChg : AtomicRMWExpansionKind :: None ; case AtomicRMWInst ::


<s> const Function & F = MF -> getFunction ( ) ; for ( Function :: const_arg_iterator I = F . arg_begin ( ) , E = F . arg_end ( ) ; I != E ; I ++