<s> case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return false ; } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr *


<s> struct ix86_address parts ; int cost = <NUM_LIT> ; int ok = ix86_decompose_address ( x , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base

) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ;


<s> unsigned Emitter < CodeEmitter > :: get<ISA_LIT>RegNum ( unsigned RegNo ) const { return II -> getRegisterInfo ( ) . get<ISA_LIT>RegNum


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , dl , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , RetAddrFI


<s> return TargetTriple . getEnvironment ( ) == Triple ::


<s> return ( uint64x1_t ) __builtin_neon_vqshl_u_ndi ( (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const


<s> if ( TARGET_SHMEDIA ) tramp = expand_simple_binop ( Pmode , PLUS , tramp , const1_rtx ,

gen_reg_rtx ( Pmode ) , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64

( ) ) return getAddrNonPIC ( N , Ty , DAG ) ;


<s> ++ name ; if ( ISDIGIT ( p [ <NUM_LIT> ] ) ) name = ggc_alloc_string ( name , p - name ) ; else { gcc_assert ( ISDIGIT ( * name ) ) ; name ++ ; gcc_assert ( name == p


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const { return Subtarget ->


<s> VADstIndex = i ; } else { VBDstIndex = i ; } } if ( VADstIndex < <NUM_LIT> && VBDstIndex < <NUM_LIT> ) return false ; unsigned VBSrcIndex = <NUM_LIT> ; if ( VADstIndex >= <NUM_LIT> ) { VBSrcIndex = CandidateMask [ VADstIndex ] ; VBDstIndex = VADstIndex ; VB = VA ; } else { VBSrcIndex = CandidateMask [ VBDstIndex ] - <NUM_LIT> ; } if ( ! VAUsedInPlace ) VA = DAG . getUNDEF ( <STR_LIT> ) ; V1 = VA ; V2 = VB ; InsertPSMask = VBSrcIndex << <NUM_LIT> | VBDstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return


<s> } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , Addr , <STR_LIT> ) ; } else { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; } return true


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val & <NUM_LIT> ) ==


<s> Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC7_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC10_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_DISP ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT>


<s> return ( __mmask8 ) __builtin_ia32_ucmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> vqmovn_high_s32 ( int16x4_t a , int32x4_t b ) { int16x8_t result = vcombine_s16 ( a , vcreate_s16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) :


<s> int CC ; if ( Name == <STR_LIT> ) return getATReg ( ) ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; if ( is<ISA_LIT>64 ( ) && <NUM_LIT> <= CC && CC <=


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op .

getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> return __aarch64_vdup_laneq_s32 ( __a ,


<s> bool SelectAddrMode2Base ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc )


<s> bool has<ISA_LIT>5 ( ) const { return <ISA_LIT>ArchVersion >= <ISA_LIT>5


<s> Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , DebugLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getBlockAddress ( AM . BlockAddr , <STR_LIT> ,


<s> PC . GV = new GlobalVariable ( * F . getParent ( ) , C . getType ( ) , true , GlobalValue :: InternalLinkage , nullptr , <STR_LIT> , nullptr , GlobalVariable :: NotThreadLocal ) ; PC . GV -> setInitializer ( & C ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( PC . GV -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( )


<s> bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { for ( int InsertedCount = <NUM_LIT> ; InsertedCount < <NUM_LIT> ; InsertedCount ++ ) BuildMI ( MBB , MBBI


<s> static bool checkAndUpdateEFLAGSKill ( MachineBasicBlock :: iterator SelectItr , MachineBasicBlock * BB , const TargetRegisterInfo * TRI ) { MachineBasicBlock :: iterator miI ( std :: next ( SelectItr ) ) ; for ( MachineBasicBlock :: iterator miE = BB -> end ( )


<s> vrev32q_u16 ( uint16x8_t a ) { return __builtin_shuffle ( a , ( uint16x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> static void aarch64_emit_sve_predicated_cond ( rtx target , rtx_code code , rtx pred , rtx op0 , rtx op1 ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( pred ) , gen_rtvec ( <NUM_LIT> , pred , op0 ,

op1 ) , aarch64_unspec_cond_code ( code ) ) ;


<s> unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> <<


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiv16qi ( (


<s> MRI = & MF . getRegInfo ( ) ; TII = STI . getInstrInfo ( ) ; TSchedModel . init ( STI . getSchedModel ( ) , & STI , TII ) ; for ( MachineBasicBlock & MBB : MF ) { MachineLoop * CurrLoop = MLI . getLoopFor ( & MBB ) ; if ( ! CurrLoop || CurrLoop -> getHeader ( ) != & MBB || ! CurrLoop -> getSubLoops ( ) . empty ( ) ) continue ; CmovGroups CmovInstGroups ; if ( ! collectCmovCandidates ( CurrLoop , CmovInstGroups ) ) continue ; if ( ! checkForProfitableCmovCandidates ( CurrLoop , CmovInstGroups ) ) continue ; Changed = true ; for ( auto & Group : CmovInstGroups ) convertCmovInstsToBranches ( Group ) ; } return Changed


<s> static bool csky_can_use_ldstm ( int mask , int * br , int * er ) { int regno ; int begin_reg = <NUM_LIT> , end_reg = <NUM_LIT> ; int count = <NUM_LIT> ; if ( ! TARGET_MULTIPLE_STLD ) return false ; if ( mask & <NUM_LIT> )


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; unsigned XorOp = MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static DecodeStatus DecodeT2LdStPre ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addr |= Rn << <NUM_LIT> ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Rt == <NUM_LIT> ) Inst . setOpcode ( <STR_LIT> ) ; else Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( ! load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( load )


<s> if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode


<s> bool canUseCMPXCHG16B ( ) const { return hasCX16 ( ) && is64Bit (


<s> static void set_reg ( struct unw_reg_info * reg , enum unw_where where , int when , unsigned long


<s> if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [ slot ] = true ; pcum -> can_split = false ; } gcc_assert ( pcum -> can_split == false ) ; return ; } } ncrn = pcum -> aapcs_ncrn ; if ( ncrn & <NUM_LIT> ) { int res = arm_needs_doubleword_align ( mode , type ) ; if ( res < <NUM_LIT> && warn_psabi && currently_expanding_gimple_stmt ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; else if ( res > <NUM_LIT> ) ncrn ++ ; } nregs = ARM_NUM_REGS2 ( mode , type ) ; gcc_assert ( nregs >= <NUM_LIT> ) ; nregs2 = nregs ? nregs : <NUM_LIT> ; if ( ncrn + nregs2 <= NUM_ARG_REGS ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = ncrn + nregs ; return ; } if ( ncrn < NUM_ARG_REGS && pcum -> can_split ) { pcum -> aapcs_reg = gen_rtx_REG (


<s> if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg


<s> int is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) , Pmode

) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setNoMacro ( ) ; getTargetStreamer ( ) . emitDirectiveSetNoMacro (


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; MakeLibCallOptions CallOptions


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) && ! TARGET_SECURE_PLT && ( ! constant_pool_empty_p ( ) || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name == '.' ) desc_name ++ ; if ( TREE_PUBLIC ( decl ) ) fprintf ( file ,


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , unsigned offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm (


<s> __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector signed short ) vec_splats


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( ) const { return true


<s> return ( uint64x1_t ) { __builtin_aarch64_urshldi_uus ( __a [ <NUM_LIT> ]


<s> static bool isT1i32Load ( unsigned Opc


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>8 ; case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF


<s> return false ; } bool Gatscat = true ; for ( User * U : I -> users ( ) ) { if ( ! isa < Instruction > ( U ) ) return false ; if ( isa < GetElementPtrInst > ( U ) || isGatherScatter ( dyn_cast < IntrinsicInst > ( U ) ) ) { return Gatscat ; } else { unsigned OpCode = cast < Instruction > ( U ) -> getOpcode ( ) ; if ( ( OpCode == Instruction :: Add || OpCode == Instruction :: Mul || OpCode == Instruction :: Shl || isAddLikeOr ( cast < Instruction > ( U ) , DL )

) && hasAllGatScatUsers ( cast < Instruction > ( U ) , DL ) ) {


<s> else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par


<s> if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits ,


) _mm_set_epi64x ( long long __q1 , long long __q0 ) {


<s> assert ( got_entry != NULL ) ; Relocator :: Address GOT_S = pParent . getTarget ( ) . getGOT ( ) . addr ( ) + got_entry -> getOffset ( ) ; Relocator :: DWord A = pReloc . target ( )


<s> unsigned Op = MI . getOpcode ( ) ; if ( isPreISelGenericFloatingPointOpcode ( Op ) ) return true ; if ( Op != TargetOpcode :: COPY && ! MI . isPHI ( ) ) return false ; auto * RB = getRegBank ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( RB == & <STR_LIT> ) return


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TV = Op . getOperand ( <NUM_LIT> ) , FV = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue Sel1 ; if ( isFloatingPointZero ( RHS ) ) switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default :


<s> static inline unsigned getT2SOImmValRotate ( unsigned V ) { if ( ( V & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned RotAmt = CountTrailingZeros_32 (


<s> static bool compareMbbNumbers ( const MachineBasicBlock * LHS , const MachineBasicBlock * RHS ) { return LHS -> getNumber ( )


<s> MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WVT ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero ( N0 , Mask17 ) )


<s> SDValue Avg = detectAVGPattern ( N -> getOperand ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> )


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Reserved . set ( <STR_LIT> + i ) ; } const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> ,

MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> return __builtin_mve_vcaddq_rot270_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; unsigned FI = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = FIOperandNum + <NUM_LIT> ; break ; } MachineOperand & ImmOp = MI


<s> if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x ) ; } if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target ,


__artificial__ ) ) _mm256_bcstnebf16_ps ( const void * __P ) {


<s> if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT


<s> if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; } } if ( ! DoMerge ) return false ; bool isDPR = NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( isAM5 ) Offset = <STR_LIT> ( AddSub == <STR_LIT> ? <STR_LIT> : <STR_LIT> , true , ( isDPR ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( isAM2 ) Offset = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; else Offset = AddSub == <STR_LIT> ? - Bytes : Bytes ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) ; } else if ( isLd ) { if ( isAM2 ) BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; else BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else


<s> void addAbsMemOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp ( )


<s> bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && DstTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else return false ; Index = Index / DstTy . getSizeInBits ( ) ; I . getOperand ( <NUM_LIT> ) . setImm ( Index ) ; return constrainSelectedInstRegOperands ( I , TII , TRI ,


<s> if ( ! isIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry


<s> SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { while ( <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & nextTok = Parser . getTok ( ) ; if ( nextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ) { int Val = MCE -> getValue ( ) ; if ( Str == <STR_LIT> ) { Val = Val & <NUM_LIT> ; } else if ( Str == <STR_LIT> ) { int LoSign = Val & <NUM_LIT> ; Val = ( Val & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoSign ) Val ++ ; } Res = MCConstantExpr :: Create ( Val


<s> getMveAddrModeRQOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & M0 = MI . getOperand ( OpIdx ) ; const MCOperand & M1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( M0 . getReg ( ) ) ; unsigned Qm = CTX . getRegisterInfo ( ) -> getEncodingValue ( M1 . getReg ( ) ) ; assert ( Qm < <NUM_LIT> && <STR_LIT>


<s> OperandMatchResultTy parseBDAddr64 ( SmallVectorImpl < MCParsedAsmOperand * >


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getCondBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) )

return getMachineOpValue ( MI , MO , Fixups , STI ) ;


<s> return & InstrInfo . getRegisterInfo


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveFPLR ( int


<s> MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBUtils -> adjustBBSize ( MI -> getParent ( ) , - TII -> getInstSizeInBytes ( * MI ) ) ; MI -> eraseFromParent ( ) ; BBUtils -> adjustBBOffsetsAfter ( MBB ) ; return true


<s> case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S4 ( SDValue N , SDValue & Base , SDValue


<s> return ( TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI && ( ! cfun -> machine -> has_local_indirect_jump || cfun -> machine

-> indirect_branch_type == indirect_branch_keep ) ) ;


<s> if ( <ISA_LIT>SubTarget . isDarwin ( ) || ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return ; SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; unsigned FirstOp ; unsigned StorageOpcode = N -> getMachineOpcode ( ) ; switch ( StorageOpcode ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) || N -> getConstantOperandVal ( FirstOp ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( )


<s> SDValue V = Insert128BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl ) ; return Insert128BitVector ( V , V2 , NumElems / <NUM_LIT> , DAG


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( regno == ARG_REGISTER ( <NUM_LIT> ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM ) || ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ; return false


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCMN ( MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; return emitADDS ( Is32Bit ? <STR_LIT> : <STR_LIT>


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass ( create<ISA_LIT>Os16 ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloat


<s> void <ISA_LIT>ConstantIslands :: DoInitialPlacement ( MachineFunction & Fn , std :: vector < MachineInstr * > & CPEMIs ) { MachineBasicBlock * BB = Fn . CreateMachineBasicBlock ( ) ; Fn . push_back ( BB ) ; const std :: vector < MachineConstantPoolEntry > & CPs = Fn . getConstantPool ( ) -> getConstants ( ) ; const TargetData & TD = * Fn . getTarget ( ) . getTargetData ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypePaddedSize ( CPs [ i ] . getType ( ) ) ; assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry


<s> static SDValue lowerFP_TO_SINT_STORE ( StoreSDNode * SD , SelectionDAG & DAG ) { SDValue Val = SD -> getValue ( ) ; if ( Val . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FPTy = EVT :: getFloatingPointVT ( Val . getValueSizeInBits ( ) ) ; SDValue Tr = DAG . getNode ( <STR_LIT> , SDLoc ( Val ) , FPTy , Val . getOperand


<s> return false ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; if ( RegNo == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { if ( Tok . getString ( ) . size ( ) == <NUM_LIT> ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo = <STR_LIT> ; break ; case '7' : RegNo = <STR_LIT> ; break ; case '8' : RegNo = <STR_LIT> ; break ; case '9' : RegNo = <STR_LIT> ; break ; } } else if ( Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) [ <NUM_LIT> ] == '1' ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; } } if ( RegNo != <NUM_LIT> ) { EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; return false ; } } if ( RegNo == <NUM_LIT> ) { if ( isParsingIntelSyntax ( ) ) return true ; return Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } Parser . Lex ( ) ; return false


<s> bool supportsEfficientVectorElementLoadStore ( ) { return true


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateReg (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FPVector ( SDValue Op , SelectionDAG & DAG , const SDLoc & dl ) const { unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; bool SignedConv = Opc == <STR_LIT> ; if ( SignedConv && ! Subtarget . hasP9Altivec ( ) ) return SDValue ( ) ; SDValue Wide = widenVec ( DAG , Op . getOperand ( <NUM_LIT> ) , dl ) ; EVT WideVT = Wide . getValueType ( ) ; unsigned WideNumElts = WideVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> >


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast <


<s> if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; if ( ! IsVarArg ) return CC_<ISA_LIT>_DarwinPCS ; return Subtarget -> isTargetILP32 ( ) ? CC_<ISA_LIT>_DarwinPCS_ILP32_VarArg : CC_<ISA_LIT>_DarwinPCS_VarArg ; case CallingConv :: Win64 : return IsVarArg ? CC_<ISA_LIT>_Win64_VarArg : CC_<ISA_LIT>_AAPCS ; case CallingConv ::


<s> bool isPMADDWDSlow ( ) const { return


<s> unsigned int nelts_per_vq ; if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor ,

& nelts_per_vq ) ) gcc_unreachable ( ) ;


<s> case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) { rtx tmp = sh_compare_op0 ; sh_compare_op0 = sh_compare_op1 ; sh_compare_op1 = tmp ; } mode = GET_MODE ( sh_compare_op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( ( code != EQ && code != NE && ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && sh_compare_op1 != const0_rtx )

|| ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ;


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) .


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR


<s> assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems > <NUM_LIT> || ( NumElems == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) ) return splitVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( ) ) && <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , NewVT


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( XPLINKSpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets [ XPLINKSpillOffsetTable

[ I ] . Reg ] = XPLINKSpillOffsetTable [ I ] . Offset ;


<s> MachineBasicBlock * MBB = MFp -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> getInstSizeInBytes ( * MI ) ; ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) ,


<s> int i , k ; rtx rvec [ GP_ARG_NUM_REG + <NUM_LIT> ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == <NUM_LIT> || ( n_units == <NUM_LIT> && mode != BLKmode ) ) return gen_rtx_REG ( mode


<s> return __builtin_mve_vmvnq_m_uv4si ( __arm_vuninitializedq_u32 ( )


<s> PrivateLabelPrefix = <STR_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CodePointerSize = IsILP32 ? <NUM_LIT> : <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; UseDataRegionDirectives = true ; ExceptionsType = ExceptionHandling ::


<s> return ( __m128 ) __builtin_ia32_scalefps128_mask ( ( __v4sf ) __A , ( __v4sf )


<s> if ( Subtarget -> hasCMov ( ) ) if ( SDValue RV = performIntegerAbsCombine ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) )


<s> Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . parseAbsoluteExpression ( Value ) ) return nullptr ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } SMLoc MemEnd = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( is64BitMode ( ) || ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) ) && BaseReg != <STR_LIT> ) { Error ( BaseLoc , <STR_LIT> ) ; return nullptr ; } if ( BaseReg == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( BaseLoc , ErrMsg ) ; return nullptr ; } if ( SegReg || BaseReg || IndexReg ) return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , MemStart , MemEnd ) ; return <STR_LIT> ( Disp ,


<s> break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl


<s> unsigned getFramePred ( const MachineInstr & MI ) const { assert ( isFrameInstr (


<s> if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val > High ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CE , Loc , Parser


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return


<s> case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG


<s> void addMSRSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( LOADOpc ) , AccPhyReg ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; thisMBB -> addSuccessor ( mainMBB ) ; MachineBasicBlock * origMainMBB = mainMBB ; mainMBB -> addLiveIn ( AccPhyReg ) ; unsigned AccReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: COPY ) , AccReg ) . addReg ( AccPhyReg ) ; unsigned t1 = MRI . createVirtualRegister ( RC ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ARITHOpc = getNonAtomicOpcode ( Opc ) ; BuildMI ( mainMBB , DL , TII -> get ( ARITHOpc ) , t1 ) . addReg ( SrcReg ) . addReg ( AccReg ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned t2 = MRI . createVirtualRegister ( RC ) ; unsigned NOTOpc ; unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc ( Opc , NOTOpc ) ; BuildMI ( mainMBB , DL , TII -> get ( ANDOpc ) , t2 ) . addReg ( SrcReg ) . addReg ( AccReg ) ; BuildMI ( mainMBB , DL , TII -> get ( NOTOpc ) , t1 ) . addReg ( t2 ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CMPOpc ; unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc ( Opc , CMPOpc ) ; BuildMI ( mainMBB , DL , TII -> get ( CMPOpc ) ) . addReg ( SrcReg ) . addReg ( AccReg ) ; if ( Subtarget -> hasCMov ( )


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( VTs , Ops , dl , MemIntr

-> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ;


<s> extern __inline __m512i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_loadu_epi64 ( void const * __P ) { return * ( __m512i_u * )


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) return CE -> getValue ( )


<s> SDValue ArgValueLo , ArgValueHi ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( nullptr == InFlag ) { Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValueLo = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValueHi = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; } else { ArgValueLo = DAG . getCopyFromReg ( Root , Dl , VA . getLocReg ( ) , <STR_LIT> , * InFlag ) ; * InFlag = ArgValueLo . getValue ( <NUM_LIT> ) ; ArgValueHi = DAG . getCopyFromReg ( Root , Dl , NextVA . getLocReg ( ) , <STR_LIT> , * InFlag ) ; * InFlag = ArgValueHi . getValue ( <NUM_LIT> ) ; } Lo = DAG . getBitcast ( <STR_LIT> , ArgValueLo ) ; Hi = DAG . getBitcast ( <STR_LIT> , ArgValueHi ) ; return DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> ,


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) { OutStreamer -> EmitRawText ( <STR_LIT>


<s> MCSubtargetInfo STI = getSubtargetInfo ( ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer -> emitInstruction (


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register BasePtr ; int64_t Offset = ( TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getDebugOffset ( ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) { if ( OpcodeForOffset == <STR_LIT> && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasVector ( ) ) { OpcodeForOffset = <STR_LIT> ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset =


<s> SmallSet < MachineBasicBlock * , <NUM_LIT> > RestoreBlocks ; if ( MFI . getSavePoint ( ) ) { SaveBlocks . insert ( MFI . getSavePoint ( ) ) ; RestoreBlocks . insert ( MFI . getRestorePoint ( ) ) ; } else { SaveBlocks . insert ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) if ( MBB . isReturnBlock ( ) ) RestoreBlocks . insert ( & MBB ) ; } SmallVector < MachineBasicBlock * , <NUM_LIT> > WorkList ; SmallSet < MachineBasicBlock * , <NUM_LIT> > VisitedBlocks ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . front ( ) . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . isReturnBlock ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MBB ) ; } } auto CheckOutsideInst = [ & UnsaveableRegs , TRI ] ( MachineInstr & MI ) { for ( Register Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( MI . modifiesRegister ( Reg , TRI ) ) { UnsaveableRegs . set ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg ) << <STR_LIT> << MI << <STR_LIT> ) ; } } } ; while ( ! WorkList . empty ( ) ) { MachineBasicBlock * MBB = WorkList . pop_back_val ( ) ; if ( VisitedBlocks . count ( MBB ) ) continue ; VisitedBlocks . insert ( MBB ) ; bool IsSave = SaveBlocks . count ( MBB ) ; bool IsRestore = RestoreBlocks . count ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << IsSave << <STR_LIT> << IsRestore << <STR_LIT> ) ; if ( IsRestore ) { LivePhysRegs LPR ( * TRI ) ; LPR . addLiveOuts ( * MBB ) ; for ( auto & Term : reverse ( MBB -> terminators ( ) ) ) { LPR . stepBackward ( Term ) ; CheckOutsideInst ( Term


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps

&& ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return false ;


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! is12BitOnly && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DEBUG ( errs ( ) << <STR_LIT> ; AM12


<s> int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; return false


<s> } if ( TARGET_SOFT_FLOAT ) arm_fpu_attr = FPU_NONE ; else arm_fpu_attr = FPU_VFP ; if ( TARGET_AAPCS_BASED ) { if ( TARGET_CALLER_INTERWORKING ) error ( <STR_LIT> ) ; else if ( TARGET_CALLEE_INTERWORKING ) error ( <STR_LIT> ) ; } if ( ! arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE ) sorry ( <STR_LIT> ) ; if ( use_cmse && ! arm_arch_cmse ) error ( <STR_LIT> ) ; if ( use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM ) error ( <STR_LIT> ) ; if (


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ,


<s> return ( cost + set_src_cost ( XEXP ( x , <NUM_LIT> ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , GET_MODE (

x ) , GET_CODE ( x ) , <NUM_LIT> , speed ) ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( )


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ?


<s> HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFloat128 = false ; IsISA3_0 = false ; UseLongCalls =


<s> mips_init_cumulative_args ( & cum , NULL ) ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { machine_mode mode ; struct mips_arg_info info ; if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = SFmode ; else if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = DFmode ; else gcc_unreachable


<s> if ( TheTriple . isOSWindows ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple .


<s> if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq


<s> if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( isZExt ) ? ( int ) CIVal . getZExtValue ( ) : ( int ) CIVal . getSExtValue ( ) ; if ( Imm < <NUM_LIT> && Imm != ( int ) <NUM_LIT> ) { isNegativeImm = true ; Imm = - Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } } else if ( const ConstantFP * ConstFP = dyn_cast < ConstantFP > ( Src2Value ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) if ( ConstFP -> isZero ( ) && ! ConstFP -> isNegative ( ) ) UseImm = true ; } unsigned CmpOpc ; bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm )


<s> if ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && Op . hasOneUse ( ) && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { unsigned BitWidth = VT . getSizeInBits ( ) ; const APInt & ShAmt = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShAmt . ult ( BitWidth ) ) { unsigned MaskBits = BitWidth - ShAmt . getZExtValue ( ) ; APInt Mask = Op . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , MaskBits ) : APInt :: getLowBitsSet ( BitWidth , MaskBits ) ; if ( Mask . isSignedIntN ( <NUM_LIT> ) ) { Op = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } } if ( Op . getOpcode ( ) != <STR_LIT> || ! Op . hasOneUse ( ) ) return SDValue ( ) ; Op = Op .


<s> case CONST : case SYMBOL_REF : if ( tls_symbolic_operand_type ( x ) == <NUM_LIT> ) { HOST_WIDE_INT addend = <NUM_LIT> ; rtx op = x ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; op = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; } if ( any_offset_symbol_operand ( op , mode ) || function_operand ( op , mode ) ) return true ; if ( aligned_offset_symbol_operand ( op , mode ) ) return ( addend & <NUM_LIT> ) == <NUM_LIT> ; return false ; } return false ; case CONST_VECTOR


<s> inline vector float vec_ceil ( vector float a1 ) { return ( vector float ) __builtin_altivec_vrfip ( ( vector


<s> NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( )


<s> SDValue Base , Disp , Index ; if ( ! selectBDXAddr ( <STR_LIT> , <STR_LIT> , Op , Base , Disp


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( ! Is64Bit && Idx == <STR_LIT> ) Idx = <STR_LIT> ; return <ISA_LIT>GenRegisterInfo :: getSubClassWithSubReg ( RC ,


<s> if ( Reg ) { assert ( Reg == <STR_LIT> && <STR_LIT> ) ; O <<


<s> case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTargetWin64 ( ) ) return & <STR_LIT> ; else if ( Subtarget . is64Bit ( ) ) return & <STR_LIT> ; const Function * F =


<s> for ( ImmutableCallSite :: arg_iterator II = CS . arg_begin ( ) , IE = CS . arg_end ( ) ; II != IE ; ++ II ) { unsigned AttrIdx = II - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrIdx , Attribute :: InReg ) || CS . paramHasAttr ( AttrIdx , Attribute :: StructRet ) || CS . paramHasAttr ( AttrIdx , Attribute :: Nest ) || CS . paramHasAttr ( AttrIdx , Attribute :: ByVal ) ) return false ; <STR_LIT> Flags ; if ( CS . paramHasAttr ( AttrIdx , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrIdx , Attribute :: ZExt ) ) Flags . setZExt ( ) ; Type * ArgTy = ( * II ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( * II ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * II ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) return false ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB .

addReg ( RegArgs [ II ] , RegState :: Implicit ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; assert ( ! ( STI . is64Bit ( ) && STI . isTargetWindowsCoreCLR ( ) ) && <STR_LIT> ) ; const uint64_t StackProbeSize = TLI . getStackProbeSize


<s> return <ISA_LIT>ABIInfo ( ABI :: N64


<s> bool IsLogical = ( Compare -> getDesc ( ) . TSFlags & <STR_LIT> ) != <NUM_LIT> ; if ( Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI , TM . getRegisterInfo ( ) ) ) return true ; return


<s> if ( IncInstruction -> getNumUses ( ) != <NUM_LIT> ) { IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , Phi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; Phi -> setIncomingValue ( IncrementingBlock , IncInstruction ) ; } NewPhi = Phi ; } else { NewPhi = PHINode :: Create ( Phi -> getType ( ) , <NUM_LIT> , <STR_LIT> , Phi ) ; NewPhi -> addIncoming ( Phi -> getIncomingValue ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , Phi -> getIncomingBlock ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , NewPhi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; NewPhi -> addIncoming ( IncInstruction , Phi -> getIncomingBlock ( IncrementingBlock ) ) ; IncrementingBlock = <NUM_LIT> ; } IRBuilder < > Builder ( BB -> getContext ( ) ) ; Builder . SetInsertPoint ( Phi ) ; Builder . SetCurrentDebugLocation ( Offs -> getDebugLoc ( ) ) ; switch ( Offs -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Or : pushOutAdd ( NewPhi , OffsSecondOperand , IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; break ; case Instruction :: Mul : case Instruction :: Shl : pushOutMulShl ( Offs -> getOpcode ( ) , NewPhi , IncrementPerRound , OffsSecondOperand , IncrementingBlock , Builder ) ; break ; default : return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Offs -> replaceAllUsesWith (


<s> addPass ( new IRTranslator ( getOptLevel (


<s> return __builtin_mve_vaddvq_uv16qi ( __a )


<s> SDValue <ISA_LIT>TargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op


<s> const <ISA_LIT>FunctionInfo * MFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineRegisterInfo :: def_iterator RI = MF . getRegInfo ( ) . def_begin ( LR ) ; return RI != MF . getRegInfo ( ) .

def_end ( ) || MFI -> isLRStoreRequired ( ) ;


<s> switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction & MF = * BB -> getParent ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBITCASTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static __inline qword si_fcmgt ( qword a , qword b ) { vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb )

, vec_andc ( ( vec_float4 ) ( b ) , msb ) ) ) ) ;


<s> TargetLoweringBase :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( SI ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind


<s> bool <ISA_LIT>FastISel :: SelectSIToFP ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; if ( ! I -> getOperand ( <NUM_LIT> ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , Op ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor (


<s> extern __inline __m128d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i32gather_pd ( double const * base , __m128i index , const int scale ) { __v2df zero = _mm_setzero_pd ( ) ; __v2df mask = _mm_cmpeq_pd (


<s> return expand_one_builtin ( CODE_FOR_rx , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_SRRD : return expand_one_builtin ( CODE_FOR_srrd , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_SRWR : return expand_one_builtin ( CODE_FOR_srwr , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_WB : return expand_one_builtin ( CODE_FOR_wb , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_WX : return expand_one_builtin ( CODE_FOR_wx , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUC32L : return expand_one_builtin ( CODE_FOR_luc32l , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUC64 : return expand_one_builtin ( CODE_FOR_luc64 , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUC64L : return expand_one_builtin ( CODE_FOR_luc64l , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUK : return expand_one_builtin ( CODE_FOR_luk , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LULCK : return expand_one_builtin ( CODE_FOR_lulck , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUM32 : return expand_one_builtin ( CODE_FOR_lum32 , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUM32L : return expand_one_builtin ( CODE_FOR_lum32l , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUM64 : return expand_one_builtin ( CODE_FOR_lum64 , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LUM64L : return expand_one_builtin ( CODE_FOR_lum64l , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_LURL : return expand_one_builtin ( CODE_FOR_lurl , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_MRGB : code [ <NUM_LIT> ] = CONST_INT ; return expand_one_builtin ( CODE_FOR_mrgb , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_SRRDL : return expand_one_builtin ( CODE_FOR_srrdl , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_SRULCK : return expand_one_builtin ( CODE_FOR_srulck , target , exp , code , <NUM_LIT> ) ; case IQ2000_BUILTIN_SRWRU


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } TypeSize ScaleValue ( <NUM_LIT> , false ) ; unsigned Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = ScaleValue . isScalable ( ) ; unsigned Scale = ScaleValue . getKnownMinSize ( ) ; int64_t Offset = IsMulVL ? SOffset . getScalableBytes ( ) : SOffset . getBytes ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable ( ) && <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) *


<s> } if ( CI -> getType ( ) == Type :: Int16Ty && AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) == <STR_LIT> ) { return LowerToBSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) == Type :: Int64Ty && Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { std :: vector < std :: string > Words ; SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ; if ( Words . size ( ) == <NUM_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> ) { Words . clear ( ) ; SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ; if ( Words . size ( ) == <NUM_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> ) { Words . clear ( ) ; SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ; if ( Words . size ( ) == <NUM_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> && Words [ <NUM_LIT> ] == <STR_LIT> ) { return LowerToBSwap ( CI ) ; } } } } break ; } return false


<s> SDValue Imm ; SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } } SDValue Splat = DAG . getNode ( <STR_LIT> , DL , CmpVT , Imm ) ; SDValue ID = DAG . getTargetConstant ( ReplacementIID , DL , <STR_LIT> ) ; SDValue Op0 , Op1 ; if ( Invert ) { Op0 =


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ; PSHUFDMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * RepeatedMask [ i ] + <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getRegisterBitWidth ( bool Vector ) const { if ( ! Vector ) return <NUM_LIT> ; if ( ST -> hasVector ( ) )


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem .


<s> return ( __m512i ) __builtin_ia32_vplzcntd_512_mask ( ( __v16si ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( E , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorIndex ( MCE -> getValue ( ) , SIdx ,


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> unsigned Opc = Cmp . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; bool IllegalFPCMov = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! isScalarFPTypeInSSEReg ( VT ) ) IllegalFPCMov = ! hasFPCMov ( cast < ConstantSDNode > ( CC ) -> getSExtValue ( ) ) ; if ( ( is<ISA_LIT>LogicalCmp ( Cmp ) && ! IllegalFPCMov ) || Opc == <STR_LIT> ) { Cond = Cmp ; addTest = false ; } } else if ( CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || ( ( CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> ) && Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) { SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; unsigned <ISA_LIT>Opcode ; unsigned <ISA_LIT>Cond ; SDVTList VTs ; switch ( CondOpcode ) { case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue <ISA_LIT>Op = DAG . getNode ( <ISA_LIT>Opcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = <ISA_LIT>Op . getValue ( <NUM_LIT> ) ; else Cond = <ISA_LIT>Op . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( <ISA_LIT>Cond , <STR_LIT> ) ; addTest = false ; } if ( addTest ) { if ( isTruncWithZeroHighBitsInput ( Cond , DAG ) ) Cond = Cond . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { SDValue NewSetCC = LowerToBT ( Cond , <STR_LIT> , DL , DAG ) ; if ( NewSetCC . getNode ( ) ) { CC = NewSetCC . getOperand ( <NUM_LIT> ) ; Cond = NewSetCC . getOperand ( <NUM_LIT> ) ; addTest = false ; } } } if ( addTest ) { CC = DAG . getConstant ( <STR_LIT> , <STR_LIT>


<s> if ( MachineInstOpcode == <STR_LIT> ) MRI . setRegClass ( Op0 , & <STR_LIT> ) ; else if ( MachineInstOpcode == <STR_LIT> ) MRI . setRegClass ( Op0 , & <STR_LIT> ) ; const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ?


<s> uint32_t size = pSD . getSection ( ) . size ( ) ; llvm :: StringRef region = pInput . memArea ( ) -> request ( offset , size ) ; if ( region . size ( ) == <NUM_LIT> ) { frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; } else { frag = new RegionFragment ( region ) ; } ObjectBuilder :: AppendFragment ( * frag , pSD ) ; return


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { assert ( Type == MachO :: <ISA_LIT>_RELOC_VANILLA && <STR_LIT> ) ; const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE


<s> BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT>

) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ;


<s> if ( ! isAddress || RegNo ) { RegNo = Regs [ RegNo ] ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; return MCDisassembler :: Success


<s> return RetCC_<ISA_LIT>_APCS_Custom_f64 ( ValNo , ValVT , LocVT ,


<s> if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - <NUM_LIT> ) { regno = crtl -> args . info . regs - <NUM_LIT> ; if ( regno > MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ) regno = MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ; } cfun -> machine -> highest_saved_stack_register =


<s> if ( ABI . IsCheriPureCap ( ) ) { unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( CapType ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SV = SV -> stripPointerCasts ( ) ; assert ( isCheriPointer ( SV -> getType ( ) , & DAG . getDataLayout ( ) ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue CapAddr = Op . getOperand


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> int check_regno ; rtx elt ; rtx elt_reg ; rtx elt_mem ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { elt = XVECEXP ( op , <NUM_LIT> , i + par_index ) ; if ( GET_CODE ( elt ) != SET ) return false ; elt_reg = load_p ? SET_DEST ( elt ) : SET_SRC ( elt ) ; elt_mem = load_p ? SET_SRC ( elt ) : SET_DEST ( elt ) ; if ( GET_CODE ( elt_reg ) != REG || GET_MODE ( elt_reg ) != SImode ) return false ; if ( GET_CODE ( elt_mem ) != MEM || GET_MODE ( elt_mem ) != SImode ) return false ; check_regno = first_elt_regno + i ; if ( REGNO ( elt_reg ) != ( unsigned int ) check_regno


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { const TargetInstrInfo * TII = TM -> getInstrInfo ( ) ; assert ( TII && <STR_LIT> ) ; return new <ISA_LIT>HazardRecognizer970 (


<s> if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < <ISA_LIT>FunctionInfo >

( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ;


<s> case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase


<s> if ( TARGET_LINUX_ABI ) file_end_indicate_exec_stack ( ) ; fprintf ( asm_out_file , <STR_LIT>


<s> if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ) { int Val = MCE -> getValue ( ) ; if ( Str == <STR_LIT> ) { Val = Val & <NUM_LIT> ; } else if ( Str == <STR_LIT> ) { Val = ( Val & <NUM_LIT> ) >> <NUM_LIT> ; } Res = MCConstantExpr :: Create ( Val , getContext ( ) ) ; return false ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( IdVal ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( Str ) ; Res = MCSymbolRefExpr :: Create ( Symbol , VK , getContext ( ) ) ; return false ; } return


<s> static const unsigned CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const unsigned * CURegs = ( Is64Bit ? CU64BitRegs : CU32BitRegs ) ; uint32_t RegEnc = <NUM_LIT> ; for ( int I = <NUM_LIT> ; I >= <NUM_LIT> ; -- I ) { unsigned Reg = SavedRegs [ I ] ; if ( Reg == <NUM_LIT> ) break ; int CURegNum = getCompactUnwindRegNum ( CURegs , Reg ) ; if ( CURegNum == - <NUM_LIT> ) return ~ <NUM_LIT> ; RegEnc |= ( CURegNum & <NUM_LIT> ) << ( <NUM_LIT> - I ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT>


<s> bool isWin64 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( ) ; unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != &


<s> if ( TM . getOptLevel ( ) != CodeGenOpt :: None ) substitutePass ( & PostRASchedulerID ,


<s> bool hasJAVA ( ) const { return HasJAVA