<s> MCObjectWriter * create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS )


<s> if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> || IntWidth


<s> bool hasFastHorizontalOps ( ) const { return


<s> FnStart = getContext ( ) . createTempSymbol (


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT


<s> const DataLayout * getDataLayout ( ) const { return & DL


<s> return STI . getFeatureBits ( ) [ <STR_LIT>


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ; return


<s> bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) --


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState


<s> bool isShrImm64 ( ) const { return isShrFixedWidth ( <NUM_LIT>


<s> unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs


<s> SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = <NUM_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString (

) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64


<s> machine -> use_eh_return_p = <NUM_LIT> ; machine -> naked_p = <NUM_LIT> ; machine -> fp_as_gp_p = <NUM_LIT> ; machine -> strict_aligned_p =


<s> if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT>


<s> unsigned NumEltsPerLane = VT . getVectorNumElements ( ) / NumLanes ; assert ( ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( EltSize == <NUM_LIT> || EltSize == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { uint64_t Selector = RawMask [ i ] ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) &


<s> enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ <NUM_LIT> ] ; cop1 = operands [ <NUM_LIT> ] ; if ( code == LT || code == GE ) { rtx t ; code = swap_condition ( code ) ; t = cop0 ; cop0 = cop1 ; cop1 = t ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr ,


<s> return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm


<s> vrev64_u16 ( uint16x4_t a ) { return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> ,


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG


<s> if ( TT . getOS ( ) == Triple :: AIX ) return false ; return FullRegNamesWithPercent ||


<s> if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> isOne ( ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) { assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , LHS . getValue ( <NUM_LIT> ) , DAG ) ; if ( CC == <STR_LIT> ) OFCC = getInvertedCondCode ( OFCC ) ; SDValue CCVal = DAG . getConstant ( OFCC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( LHS ) , <STR_LIT> , Chain , Dest , CCVal , Overflow ) ; } if ( LHS . getValueType ( ) . isInteger ( ) ) { assert ( ( LHS . getValueType ( ) == RHS . getValueType ( ) ) && ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ) ; const ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) { if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; if ( Test . getValueType ( ) == <STR_LIT> ) Test =

DAG . getAnyExtOrTrunc ( Test , dl , <STR_LIT> ) ;


<s> StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym .


<s> for ( const MachineOperand & MO : Use -> operands ( ) ) { if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Defs . count ( Reg ) ) return false ; } if ( HighLatencyCPSR ) return true ; if ( Use -> getOpcode ( ) == <STR_LIT> || Use -> getOpcode ( ) == <STR_LIT> ) return false ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . useBWIRegs ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue SubusLHS , SubusRHS ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS =


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ! VT . isFloatingPoint ( ) && VT . getSimpleVT ( ) != <STR_LIT> && VT . getSimpleVT ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ; setIndexedStoreAction ( im , VT . getSimpleVT ( )


<s> bool Is64 = TT . is<ISA_LIT>64 ( ) ; return create<ISA_LIT>MachObjectWriter ( Is64 , ( Is64 ? MachO :: CPU_TYPE_POWERPC64 : MachO :: CPU_TYPE_POWERPC )


<s> -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , Offset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) || ! UsedRegUnits . available ( BaseReg ) ) return E ; } while ( MBBI != B && Count < Limit


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> } else if ( opcode == <STR_LIT> || opcode == <STR_LIT> || opcode == <STR_LIT> ) { break ; } } firstTerminator = I ; unsigned int count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; I != firstTerminator ; ++ I ) { count ++ ; } if ( count <= <NUM_LIT> ) continue ; MachineInstr * Signature1 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( signatureIndex * <NUM_LIT> ) ; MachineInstr * Signature2 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( signatureIndex * <NUM_LIT> ) ; MachineInstr * Signature3 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( signatureIndex * <NUM_LIT> ) ; MachineInstr * Signature4 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( signatureIndex * <NUM_LIT> ) ; MachineInstr * Signature5 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( signatureIndex * <NUM_LIT> ) ; signatureIndex += <NUM_LIT> ; MBB -> insert ( startPoint , Signature1 ) ; MBB -> insert ( startPoint , Signature2 ) ; MBB -> insert ( startPoint


<s> static DecodeStatus DecodeSImmWithOffset ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { int32_t Imm = SignExtend32 < Bits


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef Triple ) { MCRegisterInfo * X = new MCRegisterInfo


<s> return ; } StackOffset Offset ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) ) ; } else if ( Tagged ) { StackOffset SPOffset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) ) ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg =


<s> __extension__ static __inline void vst2_u64 ( uint64_t * __a , uint64x1x2_t val ) { __builtin_aarch64_simd_oi __o ; uint64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp


<s> static void replaceFI ( MachineFunction & MF , MachineBasicBlock :: iterator II , MachineInstr & MI , const

DebugLoc & dl , unsigned FIOperandNum , int Offset , Register FrameReg ) {


<s> unsigned <ISA_LIT>Subtarget :: getMinSVEVectorSizeInBits ( ) const { assert ( HasSVE && <STR_LIT> ) ; assert ( SVEVectorBitsMin % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( ( SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == <NUM_LIT> ) && <STR_LIT> ) ; if ( SVEVectorBitsMax == <NUM_LIT> ) return ( SVEVectorBitsMin /


<s> virtual void EmitConstantPool ( ) LLVM_OVERRIDE { if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool


<s> static void makeRelocationInfo ( MachO :: any_relocation_info & MRE , const uint32_t FixupOffset , const uint32_t Index , const unsigned IsPCRel , const unsigned Log2Size , const unsigned IsExtern , const


<s> const auto & MFIa = a . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & MFIb = b . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return MFIa -> shouldSignWithBKey ( ) == MFIb -> shouldSignWithBKey (


<s> return TargetTriple . isOSBinFormatELF (


<s> return ( int16x4_t ) __builtin_aarch64_subhnv4si (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Chain = DAG . getStore ( Chain , DL , Lo , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . getAlignment ( ) , Nd . getTBAAInfo ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; return DAG . getStore ( Chain , DL , Hi , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd

. isNonTemporal ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) , Nd . getTBAAInfo ( ) ) ;


<s> else return nullptr ; SDValue Op0 ; int DstLSB , Width ; if ( ! isBitfieldPositioningOp ( CurDAG , SDValue ( N , <NUM_LIT> ) , false , Op0 , DstLSB , Width ) ) return nullptr ; unsigned ImmR = ( VT . getSizeInBits ( ) - DstLSB ) % VT . getSizeInBits ( ) ; unsigned ImmS = Width - <NUM_LIT> ; SDLoc DL ( N


<s> if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned long long __Y ) { return ( ( __X << ( <NUM_LIT> - __Y ) ) >> ( <NUM_LIT>


<s> __vi4 = ( __vector signed int ) ( __vector unsigned long long ) { __A , __B } ; __vf4 = ( __vector float ) vec_ctf ( __vi4 , <NUM_LIT>


<s> bool targetHandlesStackFrameRounding ( ) const


<s> return INSN_P ( insn ) ? mep_store_data_bypass_1 ( prev , PATTERN


<s> return xmalloc ( sizeof ( struct _ia64_sched_context


<s> if ( ! AsmParser . useOddSPReg ( ) && RegIdx . Index & <NUM_LIT> ) AsmParser . getParser ( )

. printError ( StartLoc , <STR_LIT> <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( ! Section ) { getStreamer ( ) . initSections ( false , getSTI ( ) ) ; Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } assert ( Section && <STR_LIT> ) ; if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> ) ; return false


<s> if ( isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT>


<s> static bool CC_<ISA_LIT>_64_VectorCall ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ArgFlags . isSecArgPass ( ) ) { if ( ArgFlags . isHva ( ) ) return CC_<ISA_LIT>_VectorCallAssignRegister ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; return true ; } if ( ! ( ValVT . isFloatingPoint ( ) || ( ValVT . isVector ( ) && ValVT . getSizeInBits


<s> __rv . __o = __builtin_neon_vld3v8bf ( ( const __builtin_neon_bf * ) __ptr ) ; return __rv .


<s> unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT>


<s> StringRef getPassName ( ) const override { return


<s> bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset


<s> if ( ( factor & <NUM_LIT> ) == <NUM_LIT> ) snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , factor / <NUM_LIT> ) ; else snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , factor / <NUM_LIT> ) ; return buffer


<s> assert ( ( Kind == k_Immediate ) && <STR_LIT> ) ; return Imm . Val


<s> return __builtin_mve_vqdmulhq_n_sv16qi ( __a ,


<s> addRegisterClass ( VT , <STR_LIT> ) ; addTypeForNEON ( VT , <STR_LIT>


<s> EVT ValTy = Addr . getValueType ( ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; return true ; } return false


<s> break ; default : Opcode = <STR_LIT> ; break ; } LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; auto CASDst = MRI . createGenericVirtualRegister ( s128 ) ; auto CASDesired = MRI . createGenericVirtualRegister ( s128 ) ; auto CASNew = MRI . createGenericVirtualRegister ( s128 ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASDesired } , { } ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASNew } , { } ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( Opcode , { CASDst } , { CASDesired , CASNew , Addr } ) ; MIRBuilder . buildExtract ( { DstLo } , { CASDst } , <NUM_LIT> ) ; MIRBuilder . buildExtract ( { DstHi } , { CASDst } , <NUM_LIT> ) ; } else { auto Scratch = MRI . createVirtualRegister ( & <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( <STR_LIT> , { DstLo , DstHi , Scratch } , { Addr , DesiredI -> getOperand ( <NUM_LIT> ) , DesiredI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) } ) ; } CAS . cloneMemRefs ( MI ) ; constrainSelectedInstRegOperands ( * CAS , * ST -> getInstrInfo ( ) , * MRI . getTargetRegisterInfo ( ) , * ST -> getRegBankInfo ( ) ) ; MIRBuilder . buildMerge ( MI . getOperand ( <NUM_LIT> ) , {


<s> static void VerifyVectorType ( MVT VT , EVT ArgVT ) { if ( ArgVT . isVector ( ) && ! VT . isVector

( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } Optional < MCFixupKind > <ISA_LIT>MCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_390_NONE ) . Case ( <STR_LIT> , ELF :: R_390_8 ) . Case ( <STR_LIT> , ELF :: R_390_16 ) . Case ( <STR_LIT> , ELF :: R_390_32 ) . Case ( <STR_LIT> , ELF :: R_390_64 ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } bool <ISA_LIT>MCAsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind (


<s> } return ; } if ( arm_ccfsm_state == <NUM_LIT> ) { if ( simplejump_p ( insn ) ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) { start_insn = next_nonnote_insn ( start_insn ) ; } if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == arm_target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) reverse = TRUE ; else return ; } else if ( GET_CODE ( body ) == RETURN ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == arm_target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) { reverse = TRUE ; seeking_return = <NUM_LIT> ; } else return ; } else return ; } gcc_assert ( ! arm_ccfsm_state || reverse ) ; if ( GET_CODE ( insn ) != JUMP_INSN ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped ; int fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; rtx this_insn = start_insn , label = <NUM_LIT> ; if ( get_attr_conds ( insn ) == CONDS_JUMP_CLOB ) { jump_clobbers = <NUM_LIT> ; return ; } if ( reverse ) { if ( ! seeking_return ) label = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) seeking_return = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) { seeking_return = <NUM_LIT> ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; for ( insns_skipped = <NUM_LIT> ; ! fail && ! succeed && insns_skipped ++ < max_insns_skipped ; ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; switch ( GET_CODE ( this_insn ) ) { case CODE_LABEL


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N1 ) ) { uint64_t ShiftAmt = C -> getZExtValue ( ) ; if ( VT == <STR_LIT> && ShiftAmt == <NUM_LIT> && DAG . MaskedValueIsZero ( N00 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 , N1 ) ; if ( VT == <STR_LIT> && ShiftAmt == <NUM_LIT> && DAG . MaskedValueIsZero ( N00 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) )


<s> if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; seh = cfun -> machine ->


<s> Type * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; Value * BTC = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; Builder . SetInsertPoint ( L -> getLoopPreheader ( ) -> getTerminator ( ) ) ; Value * NumElements = getNumElements ( L -> getLoopPreheader ( ) , BTC ) ; Builder . SetInsertPoint ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( ActiveLaneMask ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * VCTPCall = Builder . CreateCall ( VCTP , Processed


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> void rbt_new ( struct rbt_strings * t ) { t -> rbt_nil = ( rbt_string_node * ) malloc ( sizeof ( rbt_string_node ) ) ; t -> rbt_nil -> color =


<s> int hi = lo + MaskWidth ; if ( any_of ( Mask , [ lo , hi ] ( int i ) { return ( lo <= i ) && ( i < hi ) ; } ) ) { UsedInputs . push_back ( Inputs [ i ] ) ; continue ; } for ( int & M : Mask ) if ( lo <=


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , MaybeAlign Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return <NUM_LIT> ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( ST -> hasNEON ( ) && Src -> isVectorTy ( ) && ( Alignment && * Alignment != Align ( <NUM_LIT> ) ) && cast < VectorType > ( Src ) -> getElementType ( ) -> isDoubleTy ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; return LT . first * <NUM_LIT> ; } if ( ST -> hasMVEFloatOps ( ) && isa < FixedVectorType > ( Src ) && I && ( ( Opcode == Instruction :: Load && I -> hasOneUse ( ) && isa < FPExtInst > ( * I -> user_begin

( ) ) ) || ( Opcode == Instruction :: Store && isa < FPTruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) ) {


<s> raw_svector_ostream VecOS ( Code ) ; Emitter . emitPrefix ( RF . getInst ( ) , VecOS , STI ) ; assert ( Code . size ( ) < <NUM_LIT> && <STR_LIT> ) ; unsigned ExistingPrefixSize = Code . size ( ) ; if ( TargetPrefixMax <= ExistingPrefixSize ) return <NUM_LIT> ; return TargetPrefixMax - ExistingPrefixSize ; } ( ) ; const unsigned PrefixBytesToAdd = std :: min ( MaxPossiblePad , RemainingPrefixSize ) ; if ( PrefixBytesToAdd == <NUM_LIT> ) return false ; const uint8_t Prefix = determinePaddingPrefix ( RF . getInst (


<s> SET_NEXT_INSN ( PREV_INSN ( note ) ) = note ; SET_PREV_INSN ( NEXT_INSN ( note ) ) = note ; } note = prev ; } } else if ( ! NONJUMP_INSN_P ( insn ) ) first = <NUM_LIT> ; } for ( insn = insns ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NOTE_P ( insn ) ) continue ; if ( ! NONJUMP_INSN_P ( insn ) ) { last = <NUM_LIT> ; continue ; } if ( GET_MODE ( insn ) == TImode ) saw_scheduling = <NUM_LIT> ; if ( ! saw_scheduling ) continue ; if ( TARGET_IVC2 ) { rtx_insn * core_insn = NULL ; if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_MODE ( insn ) == TImode ) { for ( last = insn ; NEXT_INSN ( last ) && GET_MODE ( NEXT_INSN ( last ) ) == VOIDmode && NONJUMP_INSN_P ( NEXT_INSN ( last ) ) ; last = NEXT_INSN ( last ) ) { if ( core_insn_p ( last ) ) core_insn = last ; } if ( core_insn_p ( last ) ) core_insn = last ; if ( core_insn && core_insn != insn ) { if ( PREV_INSN ( core_insn ) ) SET_NEXT_INSN ( PREV_INSN ( core_insn ) ) = NEXT_INSN (


<s> if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM


<s> else return <STR_LIT> . hasSubClassEq ( c ) || <STR_LIT> . hasSubClassEq ( c ) || <STR_LIT> . hasSubClassEq ( c ) || <STR_LIT>


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> assert ( MI . getOperand ( OpIdx ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; return MO1 . getImm ( )


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase (


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; unsigned IsTop = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( Op1 -> isUndef ( ) ) return Op0 ; if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; APInt Op1DemandedElts = APInt :: getSplat ( NumElts , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt Op0DemandedElts = IsTop ? Op1DemandedElts : APInt :: getSplat ( NumElts , APInt :: getHighBitsSet ( <NUM_LIT> ,


<s> assert ( Op && <STR_LIT> ) ; if ( ! Op -> isReg ( ) ) return nullptr ; unsigned Reg = Op -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg


<s> return ( int16x4_t ) __builtin_neon_vmvnv4hi (


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) && <STR_LIT> ) ; const unsigned CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineInstr & TestInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( DestMBB ) ; constrainSelectedInstRegOperands ( TestInst , TII , TRI , RBI ) ; I . eraseFromParent (


<s> return Error ( IdLoc , <STR_LIT> ) ; case Match_InvalidOperand : { ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IdLoc ; } return Error ( ErrorLoc


<s> unsigned NumGPRs ; if ( CCInfo . isFirstByValRegValid ( ) ) NumGPRs = <STR_LIT> - CCInfo . getFirstByValReg ( ) ; else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ]


<s> EVT WidenedVT ; if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDLoc dl ( Op ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl ,


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; if ( V . getOpcode ( ) == <STR_LIT> ) if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N

) , VT , V . getOperand ( <NUM_LIT> ) ) ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: match<ISA_LIT>AsmModifiers ( const MCExpr * & EVal , SMLoc & EndLoc ) { AsmToken Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return false ; StringRef name = Tok . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: parseVariantKind ( name ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . getKind ( ) != AsmToken :: LParen ) return false ; Parser . Lex ( ) ; const MCExpr * subExpr ; if ( Parser . parseParenExpression ( subExpr ,


<s> const char * loongarch_output_move_index_float ( rtx x , machine_mode mode , bool ldr ) { int index = exact_log2 ( GET_MODE_SIZE ( mode ) ) ; if ( ! IN_RANGE ( index , <NUM_LIT> , <NUM_LIT> ) ) return NULL ; struct loongarch_address_info


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true


<s> bool useNEONForSinglePrecisionFP ( ) const { return hasNEON ( ) &&


<s> if ( icode == CODE_FOR_altivec_vspltisb || icode == CODE_FOR_altivec_vspltish || icode == CODE_FOR_altivec_vspltisw ) { if ( ! CONST_INT_P ( op0 ) || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < - <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return


<s> int64_t Val = getConstantImm ( ) ; return <NUM_LIT> <= Val &&


<s> ++ OpIdx ; Skipped = true ; } Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) ++ OpIdx ; if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg


<s> dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( loongarch_got_load_tls_le ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; default : gcc_unreachable (


<s> if ( ! Subtarget . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( * this ) ) ; return


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; if ( RegCtx . AddressReg ( <STR_LIT> ) != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . AddressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . GetOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: Create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT>


<s> EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = VT . isInteger ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = VT . isFloatingPoint ( ) ; break ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl ,


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return


<s> } if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto SHA1Inst = MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { SrcReg } ) ; constrainSelectedInstRegOperands ( * SHA1Inst , TII , TRI , RBI ) ; if ( DstReg != I . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIRBuilder . buildCopy ( { I . getOperand ( <NUM_LIT> ) } , { DstReg } ) ; RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; } I . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * I . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Depth = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; if ( Depth == <NUM_LIT> && IntrinID == <STR_LIT> ) { if ( ! MFReturnAddr ) { MFI . setReturnAddressIsTaken ( true ) ; MFReturnAddr = getFunctionLiveInPhysReg ( MF , TII , <STR_LIT> , <STR_LIT> ) ; } if ( STI . hasV8_3aOps ( ) ) { MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { MFReturnAddr } ) ; } else { MIRBuilder . buildCopy ( { Register ( <STR_LIT> ) } , { MFReturnAddr } ) ; MIRBuilder . buildInstr ( <STR_LIT> ) ; MIRBuilder . buildCopy ( { DstReg } , { Register ( <STR_LIT> ) } ) ; } I . eraseFromParent ( ) ; return true ; } MFI . setFrameAddressIsTaken ( true


<s> if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> || ArgVT == <STR_LIT> || ! VA . isRegLoc ( ) || VA . needsCustom ( ) ) return false ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) return false ; } NumBytes = CCInfo . getNextStackOffset ( ) ; NumBytes = std :: max ( NumBytes , LinkageSize + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameSetupOpcode ( ) ) ) . addImm ( NumBytes ) ; unsigned NextGPR = <STR_LIT> ; unsigned NextFPR = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT ,

TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + <NUM_LIT> ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else if ( j != PC_REGNUM ) { if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG (


<s> SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp


<s> unsigned DstRegSize = RI -> getRegSizeInBits ( * getRegClass ( Desc , <NUM_LIT> , RI , MF ) ) ; unsigned SrcRegSize = RI -> getRegSizeInBits ( * getRegClass ( Desc , <NUM_LIT> , RI ,


<s> int <ISA_LIT>FrameLowering :: getSEHFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const auto * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTLSModel ( GV , getTargetMachine ( ) . getRelocationModel ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit (


<s> MO_TLSDESC . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( * OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitToStreamer ( * OutStreamer , Ldr ) ; MCInst Add ; Add . setOpcode ( <STR_LIT> ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( SymTLSDescLo12 ) ; Add . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <NUM_LIT> ) ) ) ; EmitToStreamer ( * OutStreamer , Add ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT> ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( * OutStreamer , TLSDescCall


<s> unsigned cpuSubTypeFromString ( StringRef CPUName ) { unsigned Mcpu = StringSwitch < unsigned > ( CPUName ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_601 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_602 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_603 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_750 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_7400 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_7450 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_970 ) . Case

( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Default ( MachO :: CPU_SUBTYPE_POWERPC_ALL ) ;


<s> const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx


<s> return isMemDisp20 ( ADDR64Reg , true


<s> unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> && RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return false ; if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New .


<s> static bool arm_promote_prototypes ( const_tree


<s> return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper ) +


<s> if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O


<s> -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end (


<s> F . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { F ,


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; return ret


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) ) return <STR_LIT> ; return


<s> if ( Cursor -> getType ( ) == IVTy ) EarliestReplacement = Cursor ; auto * IntrinsicCursor = dyn_cast < IntrinsicInst > ( Cursor ) ; if ( ! IntrinsicCursor || ! ( IntrinsicCursor -> getIntrinsicID ( ) == <STR_LIT> || IntrinsicCursor -> getIntrinsicID ( ) == <STR_LIT> ) ) break ; CandidatesForRemoval . insert ( CandidatesForRemoval . begin ( ) , IntrinsicCursor ) ; Cursor = IntrinsicCursor -> getOperand (


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX )

) return altivec_builtin_mask_for_load ;


<s> case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed ,


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo


<s> static rtx or1k_function_value ( const_tree valtype , const_tree , bool ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) ,


<s> bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , STI . getFeatureBits ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , Name , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned Opt = Mapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Mnemonic == <STR_LIT> && Opt != <STR_LIT> ) { TokError ( <STR_LIT> ) ; return


<s> typename __altivec_bool_ret < vec_step ( T ) > :: __ret \ NAME ( T a1 , U a2 ) \ {


<s> bool hasPredCtrl ( ) const { return HasPredCtrl


<s> gcc_assert ( GET_CODE ( recog_data . operand [ i ] ) != SYMBOL_REF && ( GET_CODE ( recog_data . operand [ i ] ) != CONST || ( GET_CODE ( XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ) == MINUS && ( XEXP ( XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) , <NUM_LIT> ) == global_offset_table ) && ( GET_CODE ( XEXP ( XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST ) ) ) ) ; case <NUM_LIT> : default : return <NUM_LIT>


<s> return ( __m256i ) __builtin_ia32_psrlv16hi_mask ( ( __v16hi ) __A , ( __v16hi )


<s> const char * section ; if ( rx_small_data_limit == <NUM_LIT> ) return false ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) || DECL_COMMON ( decl ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) return ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) ; size = int_size_in_bytes ( TREE_TYPE ( decl )


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> unsigned NextExpectedOpcode = <STR_LIT> ; bool AddFound = false ; bool SubFound = false ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . getOpcode ( ) == <STR_LIT> ) { InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec0 . getSimpleValueType ( ) != VT ) return SDValue ( ) ; } if ( InVec1 . getOpcode ( ) == <STR_LIT> ) { InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getSimpleValueType ( ) != VT ) return SDValue ( ) ; } if ( InVec0 != Op0 .


<s> if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration (

) ) || GV -> hasCommonLinkage ( ) ) ) return false ;


<s> const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp


<s> if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; * align = MEM_ALIGN ( mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress


<s> break ; default : break ; } } for ( MachineDomTreeNode :: iterator I = Node -> begin ( ) , E = Node -> end ( ) ; I != E ; ++ I ) { Changed |= VisitNode ( * I


<s> return ( __m256i ) __builtin_ia32_cvtmask2d256 (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSetFP


<s> rtx opfalse = op_false ? op_false : CONST0_RTX ( data_mode ) ; if ( * negate ) std :: swap ( optrue , opfalse ) ; if ( ( code != EQ && GET_MODE_SIZE ( mode ) != <NUM_LIT> && vector_all_ones_operand ( opfalse , data_mode ) && optrue == CONST0_RTX ( data_mode ) ) || ( code == GTU && GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) >= <NUM_LIT> && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ! vector_all_ones_operand ( optrue , data_mode ) || opfalse != CONST0_RTX ( data_mode ) ) ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; switch ( mode ) { case E_V16SImode : gen = ( code == GTU ) ? gen_uminv16si3 : gen_sminv16si3 ; break ; case E_V8DImode : gen = ( code == GTU ) ? gen_uminv8di3 : gen_sminv8di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; break ; case E_V32QImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv32qi3 : gen_sminv32qi3 ; break ; case E_V16HImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv16hi3 : gen_sminv16hi3 ; break ; case E_V8SImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv8si3 : gen_sminv8si3 ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) { gen = ( code == GTU ) ? gen_uminv4di3 : gen_sminv4di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; } break ; case E_V16QImode : if ( code == GTU && TARGET_SSE2 ) gen = gen_uminv16qi3 ; else if ( code == GT && TARGET_SSE4_1 ) gen = gen_sminv16qi3 ; break ; case E_V8HImode : if ( code == GTU && TARGET_SSE4_1 ) gen = gen_uminv8hi3 ; else if ( code == GT && TARGET_SSE2 ) gen = gen_sminv8hi3 ; break ; case E_V4SImode : if ( TARGET_SSE4_1 ) gen = ( code == GTU ) ? gen_uminv4si3 : gen_sminv4si3 ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) { gen = ( code == GTU ) ? gen_uminv2di3 : gen_sminv2di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; } break ; default : break ; } if ( gen ) { rtx tem = gen_reg_rtx ( mode ) ; if ( ! vector_operand ( cop0 , mode ) ) cop0 = force_reg ( mode , cop0 ) ; if ( ! vector_operand ( cop1 , mode ) ) cop1 = force_reg ( mode , cop1 ) ; * negate = ! * negate ; emit_insn ( gen ( tem , cop0 ,


<s> void <ISA_LIT>InstPrinter :: printAlignedLabel ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm


<s> mips_va_arg ( valist , type ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ fprintf ( FILE , \

<STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> void setCPR1SizeFromPredicates ( const PredicateLibrary & P ) { if ( P . mipsSEUsesSoftFloat ( ) ) CPR1Size = AFL_REG_NONE ; else if ( P . hasMSA ( ) ) CPR1Size = AFL_REG_128 ; else CPR1Size = P . isFP64bit ( ) ? AFL_REG_64


<s> return ( __m64 ) __builtin_arm_wsadh ( ( __v4hi ) __A , (


<s> Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FI ) .

addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> InstrInfo . reset ( <ISA_LIT>InstrInfo :: create ( * this ) ) ; FrameLowering . reset ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) ; TLInfo . reset ( <ISA_LIT>TargetLowering :: create ( * this ) ) ; } else { InstrInfo16 . swap ( InstrInfo ) ; FrameLowering16 . swap


<s> auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo


<s> static struct mips_multi_member * mips_multi_add ( void ) { mips_multi_member empty


<s> if ( E ) EVal = <ISA_LIT>MCExpr :: Create ( Variant , E , false , getParser ( ) . getContext ( ) ) ; return


<s> assert ( GV -> getVisibility ( ) == GlobalValue :: DefaultVisibility && <STR_LIT> ) ; LinkageAttr = MCSA_LGlobal ; break ; case GlobalValue :: AppendingLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: CommonLinkage : llvm_unreachable ( <STR_LIT> ) ; } assert ( LinkageAttr != MCSA_Invalid && <STR_LIT> ) ; MCSymbolAttr VisibilityAttr = MCSA_Invalid ; if ( ! TM . getIgnoreXCOFFVisibility ( ) ) { switch ( GV -> getVisibility ( ) ) { case GlobalValue :: DefaultVisibility : break ; case GlobalValue ::


<s> ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; SDValue Shuffle = DAG . getVectorShuffle ( ExtVT ,


<s> if ( ! RHS ) return true ; uint32_t RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC > <NUM_LIT> || RHSC % <NUM_LIT> != <NUM_LIT> ) return true ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) ->


<s> bool addMemSet ( uint64_t Offset , MemSetInst * MSI ) { uint64_t StoreSize = cast < ConstantInt > ( MSI -> getLength ( ) ) -> getZExtValue ( ) ; if ( ! addRange ( Offset , Offset + StoreSize , MSI ) ) return false ; IRBuilder < > IRB ( MSI ) ; applyMemSet ( IRB , Offset , Offset + StoreSize , cast < ConstantInt > ( MSI -> getValue ( ) ) ) ; return true


<s> return gen_got_load_tls_gd ( Pmode , dest ,


<s> bool <ISA_LIT>TargetLowering :: hasCopyImplyingStackAdjustment ( MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; return any_of ( MRI . reg_instructions ( <STR_LIT> ) , [ ] ( const MachineInstr & RI ) { return RI .


<s> if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> :


<s> MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg )

. addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ <NUM_LIT> ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == <NUM_LIT> || ImmVal == <NUM_LIT> ) return TTI :: TCC_Free ; } ImmIdx = <NUM_LIT> ; break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && Imm . getZExtValue ( ) == <NUM_LIT> ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize


<s> assert ( Arg . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg (


<s> const SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = LHS . getValueType ( ) ; SDLoc DL ( N ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; if ( VT == <STR_LIT> && isNullConstant ( RHS ) ) { SDValue <ISA_LIT>CC ; if ( SDValue V = MatchVectorAllZeroTest ( LHS , CC , DL , Subtarget , DAG , <ISA_LIT>CC ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , <ISA_LIT>CC , V ) ) ; } } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { SDValue Op0 = LHS ; SDValue Op1 = RHS ; <STR_LIT> TmpCC = CC ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; TmpCC = <STR_LIT> ( TmpCC ) ; } bool IsSEXT0 = ( Op0 . getOpcode ( ) == <STR_LIT> ) && ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( Op1 . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( TmpCC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( TmpCC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( TmpCC == <STR_LIT> || TmpCC == <STR_LIT> ) return DAG . getNOT ( DL , Op0 . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( TmpCC == <STR_LIT> || TmpCC == <STR_LIT> ) && <STR_LIT> ) ; return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( OpVT . getVectorElementType ( ) == <STR_LIT> || OpVT . getVectorElementType ( ) == <STR_LIT> ) ) { SDValue Setcc = DAG . getSetCC ( DL , OpVT , LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Setcc ) ; } if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> && LHS . getValueType ( ) == <STR_LIT>

) return LowerVSETCC ( SDValue ( N , <NUM_LIT> ) , Subtarget , DAG ) ;


<s> static tree rx_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= RX_BUILTIN_max


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>WinCOFFObjectWriter ( OS


<s> Register Reg = Op -> getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg )


<s> for ( size_t i = <NUM_LIT> ; i < <STR_LIT> . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , <STR_LIT> . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked (


<s> void i386_pe_asm_named_section ( const char * name , unsigned int flags , tree decl ) { char flagchars [ <NUM_LIT> ] , * f = flagchars ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'e' ; if ( ( flags & ( SECTION_CODE | SECTION_WRITE ) ) == <NUM_LIT> ) { * f ++ = 'd' ; * f ++ = 'r' ; } else { if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_PE_SHARED ) * f ++ = 's' ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'n' ; } if ( startswith ( name , LTO_SECTION_NAME_PREFIX ) ) * f ++ = '0' ; * f = '\0' ; fprintf ( asm_out_file , <STR_LIT> , name , flagchars ) ; if ( flags


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectZExt ( const Instruction * I ) { EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! TLI . isTypeLegal ( DstVT ) ) return false ; unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ;


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { rtx very_unlikely = GEN_INT ( REG_BR_PROB_BASE / <NUM_LIT> - <NUM_LIT> ) ; rtx x


<s> unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Value * PassThru = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getVectorNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return false ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return false ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask ,


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } return true


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; unsigned Imm = MMO . getOffset ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) .

getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ;


<s> CONST_SECTION_FUNCTION void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP )


<s> unsigned NewOpc = mergedOpcode ( MemInstr -> getOpcode ( ) , AluOffset . isImm ( ) ) ; assert ( AluOpcode != LPAC :: UNKNOWN && <STR_LIT> ) ; assert ( NewOpc != <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder InstrBuilder = BuildMI ( * BB , MemInstr , MemInstr -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; InstrBuilder . addReg ( Dest . getReg ( ) , getDefRegState ( true ) ) ; InstrBuilder . addReg ( Base . getReg ( ) , getKillRegState ( true ) ) ; if ( AluOffset . isReg ( ) ) InstrBuilder . addReg ( AluOffset . getReg (


<s> unsigned <ISA_LIT>ELFWriterInfo :: getAbsoluteLabelMachineRelTy ( ) const { return is64Bit ? <STR_LIT>


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM , new <ISA_LIT>TargetObjectFile ( ) ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setIntDivIsCheap ( false ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { llvm_unreachable (


<s> virtual bool gate ( function * ) { return aarch64_bti_enabled (


<s> tree t ; t = rs6000_builtin_types [ id < <NUM_LIT> ? ~ id : id ] ; return id < <NUM_LIT> ? build_pointer_type ( t ) :


<s> if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: AShr : ResultReg = emitASR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; } if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op1Reg ) return false ; bool Op1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_rr ( RetVT , Op0Reg , Op0IsKill , Op1Reg


<s> setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; LegalizeAction Act = ( IntVT == <STR_LIT> ) ? Promote : Legal ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT FPVT : <STR_LIT> ( ) ) { setOperationAction ( <STR_LIT> , FPVT , Expand ) ; setOperationAction ( <STR_LIT> , FPVT , Expand ) ; } for ( MVT VT : <STR_LIT> ( ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT FPVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , FPVT , Legal ) ; } for ( MVT VT : <STR_LIT> ( ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; setMinCmpXchgSizeInBits ( <NUM_LIT> ) ; setSupportsUnalignedAtomics (


<s> pandn_sh ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pandn_sh ( s , t


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * TFL = Subtarget . getFrameLowering < <ISA_LIT>ELFFrameLowering >


<s> FunctionPass * llvm :: create<ISA_LIT>SEISelDAG ( <ISA_LIT>TargetMachine & TM , CodeGenOpt ::


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv ::

GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ;


<s> tree arg = call_expr_nargs ( exp ) >= <NUM_LIT> ? CALL_EXPR_ARG ( exp , <NUM_LIT> ) : NULL_TREE ; rtx op = arg ? expand_normal ( arg ) : NULL_RTX ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case RX_BUILTIN_BRK : emit_insn ( gen_brk ( ) ) ; return NULL_RTX ; case RX_BUILTIN_CLRPSW : if ( ! valid_psw_flag ( op , <STR_LIT> ) ) return NULL_RTX ; return rx_expand_void_builtin_1_arg ( op , gen_clrpsw , false ) ; case RX_BUILTIN_SETPSW : if ( ! valid_psw_flag ( op , <STR_LIT> ) ) return NULL_RTX ; return rx_expand_void_builtin_1_arg ( op , gen_setpsw , false ) ; case RX_BUILTIN_INT : return rx_expand_void_builtin_1_arg ( op , gen_int , false ) ; case RX_BUILTIN_MACHI : return rx_expand_builtin_mac ( exp , gen_machi ) ; case RX_BUILTIN_MACLO : return rx_expand_builtin_mac ( exp , gen_maclo ) ; case RX_BUILTIN_MULHI : return rx_expand_builtin_mac ( exp , gen_mulhi ) ; case RX_BUILTIN_MULLO : return rx_expand_builtin_mac ( exp , gen_mullo ) ; case RX_BUILTIN_MVFACHI : return rx_expand_int_builtin_0_arg ( target , gen_mvfachi ) ; case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc


<s> std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc (


<s> DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent ( ) ; return NextI


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo ( )


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const RegisterBank * RegBank = RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = &


<s> unsigned getReg ( ) const { if ( Kind == k_RegisterIndex && RegIdx . Index == <NUM_LIT> && RegIdx . Kind & RegKind_GPR ) return getGPR32Reg ( ) ; assert ( Kind == k_PhysRegister &&


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getTheARM64Target ( )


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t


<s> return Kind == k_VectorListAllLanes && VectorList


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> )


<s> AssemblerDialect = AsmWriterVariant == Default ? <NUM_LIT> : AsmWriterVariant ; PointerSize = <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective =


<s> const LDSymbol * getGOTSymbol ( ) const { return m_pGOTSymbol


<s> const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF .


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , MII ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) )


<s> void <ISA_LIT>InstPrinter :: printU48ImmOperand ( const MCInst * MI , int OpNum


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; std :: string Str = Tok . getIdentifier ( ) . str ( ) ; Parser . Lex ( ) ; const MCExpr * IdVal ; SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { while ( <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & nextTok = Parser . getTok ( ) ; if ( nextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc


<s> static DecodeStatus DecodeVMRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler


<s> report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain


<s> static bool aarch64_vector_mode_p ( machine_mode mode ) { return aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p


<s> HOST_WIDE_INT gp_reg_size ; HOST_WIDE_INT fp_reg_size ; long mask ; gp_reg_size = <NUM_LIT> ; fp_reg_size = <NUM_LIT> ; mask = <NUM_LIT> ; extra_size = IQ2000_STACK_ALIGN ( ( <NUM_LIT> ) ) ; var_size = IQ2000_STACK_ALIGN ( size ) ; args_size = IQ2000_STACK_ALIGN ( crtl -> outgoing_args_size ) ; if ( args_size == <NUM_LIT> && cfun -> calls_alloca ) args_size = <NUM_LIT> * UNITS_PER_WORD ; total_size = var_size + args_size + extra_size ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno ) ) { gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == ( int ) INVALID_REGNUM ) break ; gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) ; } } gp_reg_rounded = IQ2000_STACK_ALIGN ( gp_reg_size ) ; total_size += gp_reg_rounded + IQ2000_STACK_ALIGN ( fp_reg_size ) ; if ( total_size == extra_size && ! profile_flag ) total_size = extra_size = <NUM_LIT> ; total_size += IQ2000_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> extra_size = extra_size ; cfun -> machine -> gp_reg_size = gp_reg_size ; cfun -> machine -> fp_reg_size = fp_reg_size ; cfun -> machine -> mask = mask ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> num_gp = gp_reg_size / UNITS_PER_WORD ; if ( mask ) { unsigned long offset ; offset = ( args_size + extra_size + var_size + gp_reg_size - GET_MODE_SIZE ( gpr_mode ) ) ; cfun -> machine -> gp_sp_offset = offset ; cfun -> machine -> gp_save_offset = offset


<s> AnalyzeArguments ( CCInfo , ArgLocs , Outs ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , dl , PtrVT , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , dl ) ) ; SDValue MemOp ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; MemOp = DAG . getMemcpy ( Chain , dl , PtrOff , Arg , SizeNode , Flags . getByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; } else { MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i


<s> const <ISA_LIT>TargetLowering * <ISA_LIT>TargetLowering :: create ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) { return llvm :: create<ISA_LIT>SETargetLowering ( TM


<s> bool isExtend64 ( ) const { if ( Kind != k_Extend )


<s> if ( isAllOnesConstant ( Mask ) ) return Op ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc = getZeroVector (


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName


<s> OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT>


<s> } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type ==