<s> DebugLoc dl = N -> getDebugLoc ( ) ; SDValue MemAddr , Align ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; unsigned Vec0Idx = <NUM_LIT> ; if ( ! SelectAddrMode6 ( N , N -> getOperand ( AddrOpIdx ) , MemAddr , Align ) ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( PairQRegs ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc .


<s> r = REAL_VALUE_ATOF ( strings_fpa [ i ] , DFmode ) ; values_fpa [ i ] = r ; } fpa_consts_inited =


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isFloatTy ( ) && I

-> getOperand ( <NUM_LIT> ) -> getType ( ) -> isDoubleTy ( ) ) {


<s> else return false ; if ( Register Reg = State . AllocateReg ( RegList ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else return false ; return


<s> void <ISA_LIT>InstPrinter :: printLogicalImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint64_t Val ; A64Imms :: isLogicalImmBits ( RegWidth , MO . getImm ( ) , Val ) ; O << <STR_LIT> ; O . write_hex ( Val


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getBuildVector


<s> const <ISA_LIT>RegisterInfo * RI = TM . getRegisterInfo ( ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( RI -> getStackRegister ( ) , stackGrowth ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ; MachineLocation CSDst ( RI -> getStackRegister ( ) , stackGrowth ) ; MachineLocation CSSrc ( RI -> getRARegister (


<s> void <ISA_LIT>MCAsmStreamer :: EmitValueToAlignment ( unsigned ByteAlignment , int64_t Value , unsigned ValueSize , unsigned MaxBytesToEmit ) { if ( ByteAlignment == <NUM_LIT> || ByteAlignment == <NUM_LIT> || ByteAlignment == <NUM_LIT> ) { CurrentAlignmentToValue = ByteAlignment ; return ; } if ( ByteAlignment % <NUM_LIT> == <NUM_LIT>


<s> static void mep_reload_pointer ( int regno , const char * symbol ) { rtx reg , sym ; if ( ! df_regs_ever_live_p ( regno ) && crtl -> is_leaf ) return ; reg = gen_rtx_REG ( SImode , regno ) ; sym = gen_rtx_SYMBOL_REF ( SImode , symbol ) ; emit_insn ( gen_movsi_topsym_s ( reg , sym ) ) ; emit_insn ( gen_movsi_botsym_s ( reg ,


<s> EDInstInfo * <ISA_LIT>GenericDisassembler :: getEDInfo ( ) const { return instInfo<ISA_LIT>


<s> SWITCH_TO_SECTION_FUNCTION void \ drectve_section ( ) \ { \ if ( in_section != in_drectve ) \ { \ fprintf

( asm_out_file , <STR_LIT> , <STR_LIT> ) ; \ in_section = in_drectve ; \ } \ }


<s> Type * Ty = SrcValue1 -> getType ( ) ; EVT SrcEVT = TLI . getValueType ( Ty , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>SubTarget . useCRBits ( ) ) return false ; long Imm = <NUM_LIT> ; bool UseImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg2 = ExtReg ; } } if ( ! UseImm ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) , DestReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) , DestReg

) . addReg ( SrcReg1 ) . addImm ( Imm ) ;


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeSoReg ( SDValue N , SDValue & Base

, SDValue & OffReg , SDValue & ShImm ) {


<s> assert ( N == <NUM_LIT> && isMemModeImmThumb ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseRegNum


<s> setAvailableFeatures ( ComputeAvailableFeatures ( & TM . getSubtarget < <ISA_LIT>Subtarget >


<s> return ( __mmask8 ) __builtin_ia32_cmppd512_mask ( ( __v8df ) __X , ( __v8df )


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( <STR_LIT>


<s> void setISAExtensionFromPredicates ( const PredicateLibrary & P ) { if ( P . hasCn<ISA_LIT> ( )


<s> if ( ! ReduceToLwp && ! ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return false ; Register reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( reg == <STR_LIT> ) return false ; if ( ! ImmInRange ( MI , Entry ) )


<s> __inline__ static unsigned long long sh_media_MEXTR4 ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> static __inline qword si_mpyu ( qword a , qword b ) { return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) (


<s> ComplexRendererFns selectAddrModeUnscaled128 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root , <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return <STR_LIT> ; } if ( Subtarget . hasAltivec ( ) && Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( ( Op . isMemset ( ) && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { return


<s> return __builtin_mve_vorrq_m_n_uv8hi ( __a ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasXMMInt ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT>


<s> void FixupLEAPass :: processInstructionForSLM ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr * MI = I ; const int opcode = MI -> getOpcode ( ) ; if ( opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> ) return ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) || ! TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) return ; const unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; int addrr_opcode , addri_opcode ; switch ( opcode ) { case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; default : assert ( false && <STR_LIT> ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = <NUM_LIT> ; const MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MachineOperand & Src1 = MI -> getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & Src2 = MI -> getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . addOperand ( Dst ) . addOperand ( Src1 ) . addOperand ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI -> getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . addOperand ( Dst ) . addOperand ( SrcR ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump


<s> return None ; } const Function * Fn = MF . getFunction ( ) ; bool NoImplicitFloatOps = Fn -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool isSoftFloat = Subtarget . useSoftFloat ( ) ; assert ( ! ( isSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( isSoftFloat || NoImplicitFloatOps || ! Subtarget . hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit [ ]


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = Subtarget . getFrameLowering ( ) -> getReturnSaveOffset ( ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , false ) ; FI -> setReturnAddrSaveIndex (


<s> bool sh_cannot_force_const_mem_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return


<s> return __builtin_mve_vrmlaldavhq_sv4si ( __a ,


<s> static SDValue PerformSubCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ->


<s> Op -> PostIdxReg . isAdd = isAdd ; Op -> PostIdxReg . ShiftTy = ShiftTy ; Op -> PostIdxReg . ShiftImm = ShiftImm ; Op -> StartLoc


<s> bool isImmThumbSR ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue


<s> MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; } if ( OpVT . is512BitVector ( ) && SubVecVT . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue


<s> if ( GET_CODE ( insn ) == JUMP_INSN && JUMP_LABEL ( insn ) != NULL && ( ( table = next_real_insn ( JUMP_LABEL ( insn ) ) ) == next_real_insn ( insn ) ) && table != NULL && GET_CODE ( table ) == JUMP_INSN && ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC || GET_CODE ( PATTERN ( table ) ) == ADDR_DIFF_VEC ) ) return table ; return NULL_RTX


<s> if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; } return DAG . getNode ( Opc , SDLoc ( N ) , VT


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new

<ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags &


<s> MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned I = <NUM_LIT> , E = CPUsers . size ( ) ; I != E ; ++

I ) CPChange |= handleConstantPoolUser ( I ) ;


<s> case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return Is64Bit ? COFF :: IMAGE_REL_AMD64_REL32 : COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32NB : COFF :: IMAGE_REL_I386_DIR32NB ; return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable ( <STR_LIT> ) ; case FK_SecRel_4 : return Is64Bit ? COFF :: IMAGE_REL_AMD64_SECREL : COFF :: IMAGE_REL_I386_SECREL ; default : llvm_unreachable ( <STR_LIT>


<s> const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } return MO .


<s> tree new_target , new_optimize ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; if ( TARGET_DEBUG_TARGET ) { tree tname = DECL_NAME ( fndecl ) ; fprintf ( stderr , <STR_LIT> ) ; if ( tname ) fprintf ( stderr , <STR_LIT> , ( int ) IDENTIFIER_LENGTH ( tname ) , IDENTIFIER_POINTER ( tname ) ) ; else fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; rs6000_debug_target_options ( args , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; if ( flags ) fprintf ( stderr , <STR_LIT> , flags ) ; fprintf ( stderr , <STR_LIT> ) ; } old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; ret = rs6000_inner_target_options ( args , true ) ; if ( ret ) { ret = rs6000_option_override_internal ( false ) ; new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( ! new_target ) ret = false ; else if ( fndecl


<s> emitLoadStoreInstruction ( MI , <STR_LIT> ) ; emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ; return ; } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode

== <STR_LIT> ) Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) ;


<s> if ( Domain == <STR_LIT> ) { unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; } else if ( Domain == <STR_LIT> ) { if ( TID . mayStore ( ) || TID . mayLoad ( ) ) return false ; } else { return false


<s> case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint , VT


<s> Warning ( IDLoc , <STR_LIT> ) ; TOut . emitRRR ( isGP64bit ( ) ? <STR_LIT> : <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Reg , Reg , IDLoc , STI ) ; return false ; } if ( Imm > - <NUM_LIT> && Imm < <NUM_LIT> ) { Imm = - Imm ; Opc = isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = <STR_LIT> ; } } if ( ! isUInt < <NUM_LIT> > ( Imm ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( loadImmediate ( Imm , ATReg , <STR_LIT> , true , isGP64bit ( ) , IDLoc ,


<s> MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = emitMul_rr ( SrcVT , Src0Reg , Src0IsKill , Src1Reg , Src1IsKill ) ; if ( ! ResultReg ) return false ; updateValueMap ( I


<s> BuildMI ( MBB , I , I -> getDebugLoc ( )

, get ( Opc ) ) . addReg ( <STR_LIT> ) ;


<s> Mangler * Mang = AP . Mang ; const DataLayout * DL = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; MCContext & Ctx = AP . OutContext ; bool isDarwin = Triple ( TM . getTargetTriple ( ) ) . isOSDarwin ( ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV =


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { EnableVPU = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) )


<s> return ( uint64x2_t ) __builtin_neon_vmlsluv2si ( ( int64x2_t ) __a , (


<s> vmovn_high_u64 ( uint32x2_t a , uint64x2_t b ) { uint32x4_t result = vcombine_u32 ( a , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Sel ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnesValue ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } if ( CTVal -> isNullValue ( ) && CFVal -> isAllOnesValue ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; FVal = Other ; TVal = DAG . getNode ( <STR_LIT> , dl , Other . getValueType ( ) , Other , DAG . getConstant ( - <NUM_LIT> , dl , Other . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Sel . getValueType ( ) , FVal , TVal , CCVal , Cmp ) ; } return


<s> LLVMContext & Ctx = M . getContext ( ) ; auto Ty = F -> getFunctionType ( ) ; Function * Fn = Function :: Create ( Ty , GlobalValue :: WeakAnyLinkage , N , & M ) ; Fn -> setDoesNotReturn ( ) ; Fn -> setVisibility ( GlobalValue :: DefaultVisibility ) ; Fn -> setCallingConv ( CallingConv :: C ) ; Fn -> setSection ( <STR_LIT> ) ; Fn -> setIsMaterializable ( true ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; Fn -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , Fn ) ; IRBuilder < > Builder ( Entry ) ; Builder . CreateUnreachable (


<s> if ( PHI -> getNumIncomingValues ( ) != <NUM_LIT> ) return false ; if ( PHI -> getIncomingValue ( <NUM_LIT> ) == I ) { EntryBB = PHI -> getIncomingBlock ( <NUM_LIT> ) ; BackEdgeBB = PHI -> getIncomingBlock ( <NUM_LIT> ) ; } else if ( PHI -> getIncomingValue ( <NUM_LIT> )


<s> SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt * AndC = isPowerOf2Constant ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; KnownBits Known ; DAG . computeKnownBits ( Y , Known ) ; if ( ( OrCI & Known . Zero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ; } for ( unsigned BitInY = <NUM_LIT> , NumActiveBits = OrCI .


<s> } if ( ! Value . getNode ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( usesOnlyOneValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , & Ops [ <NUM_LIT> ] , NumElts ) ; Val = LowerBUILD_VECTOR ( Val , DAG , ST ) ; if ( Val . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } SDValue Val = IsSingleInstrConstant ( Value , DAG , ST , dl ) ; if ( Val . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( isConstant ) return SDValue ( ) ; if ( NumElts >= <NUM_LIT> ) { SDValue shuffle = ReconstructShuffle ( Op , DAG ) ; if ( shuffle != SDValue ( ) ) return shuffle ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc


<s> } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream


<s> assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( <NUM_LIT>


<s> return new <ISA_LIT>SEDAGToDAGISel ( TM ,


<s> } Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: Address P = pReloc . place ( ) ; if ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: DWord X = S +


<s> static void aarch64_parse_fuse_string ( const char * fuse_string , struct tune_params * tune ) { tune -> fusible_ops = aarch64_parse_boolean_options ( fuse_string , aarch64_fusible_pairs , tune -> fusible_ops


<s> SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , NextPtr , VAListPtr , SV , <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . getLoad ( VT , dl , InChain , VAList , NULL , <NUM_LIT> ) ; SDValue V = DAG . getLoad ( <STR_LIT> , dl , InChain ,


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveInsn ( DirectiveID .


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Flag = EmitCMP ( LHS , RHS , CC ,


<s> <ISA_LIT>Lowering = TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ; <ISA_LIT>SubTarget = TM . getSubtargetImpl ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true


<s> case <STR_LIT> : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol ( ) ) ) { unsigned Other = S -> getOther ( ) <<


<s> assert ( getInstDesc ( Inst . getOpcode ( ) ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MCOperand Offset = Inst . getOperand ( <NUM_LIT> ) ; if ( Offset . isExpr ( ) ) { Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) { Inst . setOpcode ( <STR_LIT> ) ; } else { if ( ! isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> printGVStub ( ( * I ) -> getNameStart ( ) , <STR_LIT> ) ; } } if ( ! InStubSection && ! GVStubs . empty ( ) ) SwitchToDataSection ( <STR_LIT> ) ; for ( StringSet < > :: iterator i = GVStubs . begin ( ) , e = GVStubs . end ( ) ; i != e ; ++ i ) printGVStub ( i -> getKeyData ( ) ) ; if ( ! HiddenGVStubs . empty ( ) ) { SwitchToSection ( TAI -> getDataSection ( ) ) ; for ( StringSet < > :: iterator i = HiddenGVStubs . begin ( ) , e = HiddenGVStubs . end ( ) ; i != e ; ++ i ) printHiddenGVStub ( i -> getKeyData ( ) ) ; } DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; O << <STR_LIT> ; } else if ( Subtarget -> isTargetCygMing ( ) ) { for ( StringSet < > :: iterator i = FnStubs . begin ( ) , e = FnStubs . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> << COFF :: C_EXT << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ; } DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; } else if ( Subtarget -> isTargetELF ( ) ) { DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; } return AsmPrinter :: doFinalization (


<s> if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ; if ( Elt -> getAPIntValue ( ) . isNullValue ( ) ) return SDValue ( ) ; NewVecC . push_back ( DAG . getConstant ( Elt -> getAPIntValue ( ) - <NUM_LIT> , DL ,


<s> return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case


<s> SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( CallOpc == <STR_LIT> && ! callsShareTOCBase ( & MF . getFunction ( ) , Callee , DAG . getTarget ( ) ) ) { CallOpc = <STR_LIT> ; } } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops , dl , true ) , InFlag , dl ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl ,


<s> return ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ; OS . write_zeros ( Count % <NUM_LIT>


<s> Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ; Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool


<s> const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = MEMORY_REG_IMM ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem . OffsetReg


<s> union { qword q ; long long l [ <NUM_LIT> ] ; } x ; x . l [ <NUM_LIT> ] = l ; return ( x .


<s> SDValue Addic = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , AddInput , getI32Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addic , Addic , Addic . getValue ( <NUM_LIT> ) )


<s> unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } SDLoc DL ( N ) ; MVT VT = N


<s> return DisassembleNVectorShift ( MI , Opcode , insn , NumOps


<s> SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { assert ( ( InVT . isInteger ( ) && ( InVT . getSizeInBits ( ) <= <NUM_LIT> ) ) && <STR_LIT> ) ; if ( InVT . getSizeInBits ( ) >= <NUM_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } assert ( VT . getVectorNumElements ( ) == InVT . getVectorNumElements ( ) && <STR_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return LowerTruncateVecI1 ( Op , DAG , Subtarget ) ; if ( Subtarget . hasAVX512 ( ) ) { if ( InVT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , getExtendInVec ( <STR_LIT> , DL , <STR_LIT> , In , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } if ( InVT . getScalarSizeInBits ( ) == DAG . ComputeNumSignBits ( In ) ) if ( SDValue V = truncateVectorCompareWithPACKSS ( VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getBitcast ( <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT>


<s> return __builtin_loongson_paddd_u ( s


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; if ( Format == FP_FORMAT_S || Format == FP_FORMAT_W ) return getReg (


<s> else { unsigned Remainder = cast < SCEVConstant > ( BucketChain . Elements [ j ] . Offset ) -> getAPInt ( ) . urem ( Form ) ; if ( RemainderOffsetInfo . find ( Remainder ) == RemainderOffsetInfo . end ( ) ) RemainderOffsetInfo [ Remainder ] = std :: make_pair ( j , <NUM_LIT> ) ; else RemainderOffsetInfo [ Remainder ] . second ++ ; } } unsigned MaxCountRemainder = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end ( ) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo [ MaxCountRemainder ] . second ) MaxCountRemainder = j ; if ( RemainderOffsetInfo [ MaxCountRemainder ] . second < DispFormPrepMinThreshold ) return false ; if ( MaxCountRemainder == <NUM_LIT> ) return true ; const SCEV * Offset = BucketChain . Elements [ RemainderOffsetInfo

[ MaxCountRemainder ] . first ] . Offset ;


<s> int regs_saved = calc_live_regs ( & live_regs_mask ) ; int total_auto_space = rounded_frame_size ( regs_saved ) - regs_saved_rounding ; target_flags = save_flags ; int total_saved_regs_space = regs_saved + regs_saved_rounding ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM )


<s> DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs


<s> insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( stack_offset ) ) ) , reg ) , REG_NOTES ( insn ) ) ; } else emit_move_insn ( reg ,


<s> if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = <NUM_LIT> ; vec_safe_iterate ( extern_symbols , i , & p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols


<s> assert ( MI -> getOpcode ( ) == TargetOpcode :: COPY && <STR_LIT> ) ; for ( const auto & MO : MI -> operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return <NUM_LIT> ; RegDomain OpDomain = getDomain ( MRI -> getRegClass ( MO . getReg ( ) ) , MRI -> getTargetRegisterInfo ( ) ) ; if ( OpDomain == DstDomain ) return - <NUM_LIT> ; } return


<s> return ( DEFAULT_ABI == ABI_ELFv2 && ( rs6000_isa_flags & OPTION_MASK_PCREL ) !=


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; return ret


<s> rtx base ; HOST_WIDE_INT offset ; mips_get_cprestore_base_and_offset ( & base , & offset ,


( STMT_VINFO_DEF_TYPE ( stmt_info ) ) ) ;


<s> assert ( MBBI != MBB . begin ( ) && <STR_LIT> ) ; assert ( std :: prev ( MBBI ) -> isBarrier ( ) && <STR_LIT> <STR_LIT> ) ; assert ( std :: prev ( MBBI ) -> isTerminator ( ) && <STR_LIT> ) ; const TargetInstrInfo * TII = ST ->


<s> int64_t Imm = * COff ; if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; return ; } } } else if ( I . getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) { AM . Base . FrameIndex = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; AM . BaseType =


<s> if ( isSub ) NumBytes = - NumBytes ; while ( NumBytes ) { unsigned RotAmt = <STR_LIT> ( NumBytes ) ; unsigned ThisVal = NumBytes & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; assert ( ThisVal && <STR_LIT> ) ; NumBytes &= ~ ThisVal ; int SOImmVal = <STR_LIT> ( ThisVal ) ; assert ( SOImmVal != - <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( SOImmVal ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; BaseReg = DestReg


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return <NUM_LIT> ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return <NUM_LIT> ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ; else return <NUM_LIT>


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType


<s> return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode


<s> if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) -> optForSize ( ) && hasPartialRegUpdate ( MI . getOpcode ( ) ) ) return nullptr ; unsigned Alignment = <NUM_LIT> ; if ( LoadMI . hasOneMemOperand ( ) ) Alignment = ( * LoadMI . memoperands_begin ( ) ) -> getAlignment ( ) ; else switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( ( TAI -> hasDotTypeDotSizeDirective ( ) ) && Subtarget -> isLinux ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; emitFrameDirective ( MF ) ; printSavedRegsBitmask ( MF


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; <ISA_LIT>InstPrinter :: printOperand ( MO ,


<s> table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX2InsertExtract ) ; } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQ ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQMasked ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] ==


<s> unsigned int n_insns = <NUM_LIT> ; if ( align > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) align = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; n_insns = <NUM_LIT> ; if ( n_bytes % ( <NUM_LIT> * align ) != <NUM_LIT> ) { if ( ( n_bytes % ( <NUM_LIT> * align ) ) >= align ) n_insns += <NUM_LIT> ; if ( ( n_bytes % align ) != <NUM_LIT> ) n_insns += <NUM_LIT> ; } return n_insns


<s> type_class_index tclass = fi . type_suffix ( <NUM_LIT> ) . tclass ; unsigned int element_bits = GET_MODE_BITSIZE


<s> assert ( ( SegReg || BaseReg || IndexReg || DefaultBaseReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; auto Res = std :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem .


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N


<s> if ( ! SP ) return Status ; if ( Opcode == <STR_LIT> ) SP -> InitIT ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else if ( InITBlock ( ) ) SP -> UpdateIT ( ) ; return Status


<s> void <ISA_LIT>TTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . getDarwinDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime


<s> MachineInstr * FixupBWInstPass :: tryReplaceInstr ( MachineInstr * MI , MachineBasicBlock & MBB ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) return tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case <STR_LIT> : return tryReplaceLoad ( <STR_LIT> , MI


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI ->

getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> SDLoc DL ( N ) ; SDValue X = N0 . getOperand ( <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( X , APInt :: getBitsSetFrom ( VT . getSizeInBits ( ) , <NUM_LIT> ) ) ) { X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Setnp = getSETCC ( <STR_LIT> , Flags , DL , DAG ) ; return DAG . getZExtOrTrunc ( Setnp , DL , N -> getValueType ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Parity = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getZExtOrTrunc ( Parity , DL , N -> getValueType ( <NUM_LIT> ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Hi16 = DAG . getNode ( <STR_LIT> , DL , VT , X ,


<s> bool isFloatingPoint_32or64 ( InstType InstTy


<s> return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> )

, DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> , false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> if ( is32Bit ( VT ) ) Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; else if ( DAG . ComputeNumSignBits ( Op1 ) > <NUM_LIT> ) Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; SDValue Ops [ <NUM_LIT> ] ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op0 , Op1 , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops , DL


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( L , <STR_LIT> ) ; StringRef Mode = Tok . getString ( ) ; if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) Parser . Lex ( ) ; else if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) return Error ( L , <STR_LIT> ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return false


<s> bool Changed = false ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; if ( ! DI ) { DI = ReferenceDI ; } Location L = diToLocation ( DI ) ; DenseSet < unsigned > & Set = Seen [ L ] ; const std :: pair < DenseSet < unsigned > :: iterator , bool > TryInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! TryInsert . second ) { unsigned BF , DF , CI = <NUM_LIT> ; DILocation :: decodeDiscriminator ( DI -> getDiscriminator ( ) , BF , DF , CI ) ; Optional < unsigned > EncodedDiscriminator = DILocation :: encodeDiscriminator ( MemOpDiscriminators [ L ] + <NUM_LIT> , DF , CI ) ; if ( ! EncodedDiscriminator ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << DI -> getFilename ( ) << <STR_LIT> << DI -> getLine ( ) << <STR_LIT> << DI -> getColumn ( ) << <STR_LIT> ) ; continue ; } ++ MemOpDiscriminators [ L ] ; DI = DI -> cloneWithDiscriminator ( EncodedDiscriminator . getValue ( ) ) ; updateDebugInfo ( & MI , DI ) ; Changed =


<s> assert ( Reg < <NUM_LIT> && <STR_LIT> ) ; if ( StackTop >= <NUM_LIT> ) report_fatal_error (


<s> rtx mem , addr , base , insn ; addr = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( mode , addr ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( mode ) ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( VOIDmode ,


<s> return new <ISA_LIT>PreLegalizerCombiner ( IsOptNone


<s> bool aarch64_use_pseudo_pic_reg ( void ) { return aarch64_cmodel


<s> if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ,

CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> MCSymbol * Start = getContext ( ) . createTempSymbol ( ) ; EmitLabel ( Start ) ; auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; getAssembler ( ) . registerSymbol ( * Symbol ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF


<s> if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return


<s> if ( isThumb2 ) { MRI . constrainRegClass ( dest , & <STR_LIT> ) ; MRI . constrainRegClass ( oldval , & <STR_LIT> ) ; MRI . constrainRegClass ( newval , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) .


<s> SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val > High ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> void <ISA_LIT>16InstrInfo :: ExpandRetRA16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get


<s> bool <ISA_LIT>DCInstruction :: translateImplicit ( unsigned RegNo ) { assert ( RegNo ==


<s> void <ISA_LIT>FrameLowering :: emitPrologueInsns ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int NumBytes , bool RequireFPUpdate ) const { DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> )


<s> return rs6000_hard_regno_mode_ok_p [ mode ]


<s> RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? <STR_LIT> : <STR_LIT> ) ; return RegNum


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction &


<s> StackTop = <NUM_LIT> ; df_iterator_default_set < MachineBasicBlock * > Processed ; MachineBasicBlock * Entry = & MF . front ( ) ; LiveBundle & Bundle = LiveBundles [ Bundles -> getBundle ( Entry -> getNumber ( ) , false ) ] ; if ( ( Entry -> getParent ( ) -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_RegCall ) && ( Bundle . Mask && ! Bundle . FixCount ) ) { assert ( ( Bundle . Mask & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Bundle . FixCount = <NUM_LIT> ; Bundle . FixStack [ <NUM_LIT> ] = <NUM_LIT> ; } bool Changed = false ; for ( MachineBasicBlock * BB : depth_first_ext ( Entry , Processed ) ) Changed |= processBasicBlock ( MF , * BB ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineBasicBlock & BB : MF ) if ( Processed . insert ( & BB ) . second ) Changed |= processBasicBlock ( MF , BB ) ; LiveBundles . clear ( ) ; return Changed


<s> } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign


<s> unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; if ( ! A -> getFragment ( ) ) Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { assert ( Type == MachO :: <ISA_LIT>_RELOC_VANILLA && <STR_LIT> ) ; const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 =


<s> for ( i = <NUM_LIT> * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_set_insn ( reg1 , plus_constant ( ptr_mode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( reg1 ) ; } rem = size - ( i - PROBE_INTERVAL ) ; if ( rem > <NUM_LIT> ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , reg1 , - base ) ) ; emit_stack_probe ( plus_constant ( ptr_mode , reg1 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( ptr_mode , reg1 , - rem ) ) ; } else { rtx reg2 = gen_rtx_REG ( ptr_mode , PROBE_STACK_SECOND_REG ) ; HOST_WIDE_INT rounded_size = size & - PROBE_INTERVAL ; emit_set_insn ( reg1 , plus_constant ( ptr_mode , stack_pointer_rtx , - first ) ) ; emit_set_insn ( reg2 , plus_constant ( ptr_mode , stack_pointer_rtx , - ( first + rounded_size ) ) ) ; if ( ptr_mode == DImode ) emit_insn ( gen_probe_stack_range_di ( reg1 , reg1 , reg2 ) ) ; else emit_insn ( gen_probe_stack_range_si ( reg1 , reg1 , reg2 ) ) ; if ( size


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { if ( dep_type == REG_DEP_TRUE && recog_memoized ( insn ) >= <NUM_LIT> && recog_memoized ( dep ) >= <NUM_LIT> && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = <NUM_LIT> ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = <NUM_LIT> ; return false


<s> static MCOperand createPCXCallOP ( MCSymbol * Label , MCContext & OutContext ) { return create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_Sparc_WDI<ISA_LIT>30


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getImm34EncodingNoPCRel ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getImm34Encoding ( MI , OpNo , Fixups , STI


<s> bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> getDesc ( ) . hasDelaySlot ( ) ) { MachineBasicBlock :: iterator D = MBB . end ( ) ; MachineBasicBlock :: iterator J = I ; if ( ! DisableDelaySlotFiller ) D =


<s> MBBInfos . clear ( ) ; MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> GetInstSizeInBytes ( & * MI ) ; ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; if ( ( Br != End ) && ! Br -> isIndirectBranch ( ) && ( Br -> isConditionalBranch ( ) || ( Br -> isUnconditionalBranch ( ) && IsPIC ) ) ) MBBInfos [ I ] . Br = ( ++ Br


<s> uint64_t NumResidualBytes = MFI . getStackSize ( ) - NumInitialBytes ; uint64_t ArgumentPopSize = <NUM_LIT> ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; MachineInstrBuilder MIB ; if ( RetOpcode == <STR_LIT> ) { MIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( JumpTarget . isGlobal ( ) ) { MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; } else { assert ( JumpTarget . isSymbol ( ) && <STR_LIT> ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else { assert ( RetOpcode == <STR_LIT> && JumpTarget . isReg ( ) && <STR_LIT> ) ; MIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; MIB . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) MIB -> addOperand ( MBBI -> getOperand ( i ) ) ; MachineInstr * NewMI = std :: prev ( MBBI ) ; MBB . erase ( MBBI ) ; MBBI = NewMI ; ArgumentPopSize = StackAdjust . getImm ( ) ; } else { ArgumentPopSize = FuncInfo -> getArgumentStackToRestore ( ) ; } assert ( NumInitialBytes % <NUM_LIT> == <NUM_LIT> && NumResidualBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( NumInitialBytes + ArgumentPopSize != <NUM_LIT> ) { emitSPUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , NumInitialBytes + ArgumentPopSize ) ; -- MBBI ; } MachineBasicBlock :: iterator FirstEpilogue = MBBI ; while ( MBBI != MBB . begin ( ) ) { -- MBBI ; unsigned FrameOp ; for ( FrameOp = <NUM_LIT> ; FrameOp < MBBI -> getNumOperands ( ) ; ++ FrameOp ) { if ( MBBI -> getOperand ( FrameOp ) . isFI ( ) ) break ; } if ( FrameOp == MBBI -> getNumOperands ( ) ) break ; int FrameIdx = MBBI -> getOperand ( FrameOp ) . getIndex ( ) ; if ( FrameIdx < MinCSFI || FrameIdx > MaxCSFI ) break ; FirstEpilogue = MBBI ; } if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { int64_t StaticFrameBase ; StaticFrameBase = - ( NumInitialBytes + FuncInfo ->


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> return ( toc_relative_expr_p ( x , strict , & tocrel_base , & tocrel_offset ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) ) || mode == QImode || offsettable_ok_by_alignment (

XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , INTVAL ( tocrel_offset ) , mode ) ) ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( Subtarget -> isTargetWin64 ( ) ) { CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; } CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = ( ( <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } if ( ! Subtarget -> is64Bit ( ) && ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { unsigned NumInRegs = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs


<s> bool nds32_n13_last_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; return n13_consumed_by_e1_dep_p ( consumer , last_def_reg


<s> if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return


<s> return __aarch64_vget_lane_any ( __a ,


<s> unsigned StackProbeSize = <NUM_LIT> ; const Function & Fn = MF . getFunction ( ) ; if ( Fn . hasFnAttribute ( <STR_LIT> ) ) Fn . getFnAttribute ( <STR_LIT> ) . getValueAsString ( )

. getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> const Function & F = * MIRBuilder . getMF ( ) . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeSizeInBits ( Val -> getType ( ) ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ResReg = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIRBuilder . setInstr ( * Return , true ) ; MachineInstr * Copy = MIRBuilder .


<s> unsigned ZextRatio = ResSize / SrcSize ; bool IsZext = true ; for ( unsigned i = <NUM_LIT> ; i < SrcType . getVectorNumElements ( ) ; ++ i ) { if ( i % ZextRatio ) { if ( Shuffle -> getMaskElt ( i ) > <NUM_LIT> ) { IsZext = false ; break ; } } else { if ( Shuffle -> getMaskElt ( i ) != ( int ) ( i / ZextRatio ) ) { IsZext = false ; break ; } } } if ( ! IsZext ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > Mask ; unsigned NumElems = SrcType . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( i % ZextRatio ) Mask . push_back ( NumElems ) ; else Mask . push_back ( i / ZextRatio ) ; SDValue NewShuffle = DAG . getVectorShuffle ( Shuffle -> getValueType ( <NUM_LIT> ) , DL , Shuffle -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , SrcType ) , Mask ) ; return DAG . getBitcast ( N0 .


<s> initialize<ISA_LIT>AvoidSFBPassPass ( * PassRegistry :: getPassRegistry ( )


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetDarwin ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ,


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT>


<s> extern __inline __m512 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_loadu_ps ( void const * __P ) { return * ( __m512_u * )


<s> bool <ISA_LIT>TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT , const SelectionDAG & DAG , const MachineMemOperand & MMO ) const { if ( ! Subtarget . hasAVX512 ( ) && ! LoadVT . isVector ( ) && BitcastVT . isVector ( ) && BitcastVT . getVectorElementType ( ) == <STR_LIT> ) return false ; if ( ! Subtarget . hasDQI ( ) && BitcastVT == <STR_LIT> && LoadVT


<s> if ( IdxVal == <NUM_LIT> && Result . getValueType ( ) . is256BitVector ( ) && ! Result . isUndef ( ) ) { EVT ResultVT = Result . getValueType ( ) ; SDValue ZeroIndex = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( ResultVT ) ; SDValue Vec256 = DAG . getNode ( <STR_LIT> , dl , ResultVT , Undef , Vec , ZeroIndex ) ; MVT ScalarType = ResultVT . getVectorElementType ( ) . getSimpleVT ( ) ; if ( ScalarType . isFloatingPoint ( ) ) { unsigned ScalarSize = ScalarType . getSizeInBits ( ) ; assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned MaskVal = ( ScalarSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Result = DAG . getBitcast ( CastVT , Result ) ; Vec256 = DAG . getBitcast ( CastVT , Vec256 ) ; Vec256 = DAG . getNode ( <STR_LIT> , dl , CastVT ,


<s> if ( IsPreDec ) Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; else Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , Pos , DebugLoc ( ) , TII . get ( Opc ) ) ; if ( IsPreDec ) MIB .


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; const SMLoc S = getLoc ( ) ; const AsmToken & FPImmTok = Parser . getTok ( ) ; if ( FPImmTok . isNot ( AsmToken :: Real ) ) return MatchOperand_NoMatch ; bool Valid ; unsigned ValID = MapperClass ( ) . fromString ( FPImmTok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { Error ( S , <STR_LIT> )


<s> if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else default_elf_select_rtx_section ( mode , x


<s> if ( Load -> getExtensionType ( ) == <STR_LIT> ) { int64_t SignedValue = Constant -> getSExtValue ( ) ; if ( uint64_t ( SignedValue ) + ( <NUM_LIT> << ( NumBits - <NUM_LIT> ) ) > Mask ) return ; if ( IsUnsigned ) Value &= Mask ; else if ( CCMask == <STR_LIT> || CCMask == <STR_LIT> ) Value &= Mask , IsUnsigned = true ; else if ( NumBits == <NUM_LIT> ) { if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ; else if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ; else return ; } } else if ( Load -> getExtensionType ( ) == <STR_LIT> ) { if ( Value > Mask )


<s> return ( __m512i ) __builtin_ia32_psrawi512_mask ( ( __v32hi ) __A , __imm , (


<s> switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev64v16qi ; break ; case V8QImode : gen = gen_aarch64_rev64v8qi ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev32v16qi ; break ; case V8QImode : gen = gen_aarch64_rev32v8qi ; break ; case V8HImode : gen = gen_aarch64_rev64v8hi ; break ; case V4HImode : gen = gen_aarch64_rev64v4hi ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev16v16qi ; break ; case V8QImode : gen = gen_aarch64_rev16v8qi ; break ; case V8HImode : gen = gen_aarch64_rev32v8hi ; break ; case V4HImode : gen = gen_aarch64_rev32v4hi ; break ; case V4SImode : gen = gen_aarch64_rev64v4si ; break ; case V2SImode : gen = gen_aarch64_rev64v2si ; break ; case V4SFmode : gen = gen_aarch64_rev64v4sf ; break ; case V2SFmode : gen = gen_aarch64_rev64v2sf ; break ; case V8HFmode : gen = gen_aarch64_rev64v8hf ; break ; case V4HFmode : gen = gen_aarch64_rev64v4hf ; break ; default : return false ; } break ; default : return false ; } for ( i = <NUM_LIT> ; i < nelt ; i += diff + <NUM_LIT> ) for ( j = <NUM_LIT> ; j <= diff ; j += <NUM_LIT> ) { gcc_assert ( i + j <


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { assert ( MI && <STR_LIT> ) ; StackOffset SaveOffset ( Offset


<s> return ( __m512 ) __builtin_ia32_broadcastss512 ( ( __v4sf ) __A , (

__v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( auto * BVAmt = dyn_cast < BuildVectorSDNode > ( Amt ) ) { if ( auto * RotateConst = BVAmt -> getConstantSplatNode ( ) ) { uint64_t RotateAmt = RotateConst -> getAPIntValue ( ) . getZExtValue ( ) ; assert ( RotateAmt < VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , R , DAG . getConstant ( RotateAmt , DL , <STR_LIT> ) ) ; } } return DAG . getNode ( <STR_LIT> , DL , VT , R ,


<s> bool isDoubleSpacedVectorIndexed ( ) const { return Kind == k_VectorListIndexed


<s> bool isImm0_255 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> static SDValue lowerV16I32VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int ,


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt ::

None ) addPass ( create<ISA_LIT>CTRLoopsVerify ( ) ) ;


<s> SDValue BasePtr = LdNode -> getBasePtr ( ) ; if ( isa < FrameIndexSDNode > ( BasePtr . getNode ( ) ) ) { return Op ; } EVT MemVT = LdNode -> getMemoryVT ( ) ; if ( MemVT == <STR_LIT> ) return lowerLoadF128 ( Op , DAG ) ; return Op


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; return N0 ; } return LowerSDIV_v4i16 ( N0 , N1 , dl


<s> break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false , InstrNum ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg


<s> int BaseRegNum = Op -> getReg ( ) ; bool Preindexed = false ; bool Postindexed = false ; bool OffsetIsReg = false ; bool Negative = false ; bool Writeback = false ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Preindexed = true ; Parser . Lex ( ) ; int OffsetRegNum ; bool OffsetRegShifted ; enum ShiftType ShiftType ; const MCExpr * ShiftAmount ; const MCExpr * Offset ; if ( ParseMemoryOffsetReg ( Negative , OffsetRegShifted , ShiftType , ShiftAmount , Offset , OffsetIsReg , OffsetRegNum , E ) ) return true ; const AsmToken & RBracTok = Parser . getTok ( ) ; if ( RBracTok . isNot ( AsmToken :: RBrac ) ) return Error ( RBracTok . getLoc ( ) , <STR_LIT> ) ; E = RBracTok . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { E = ExclaimTok . getLoc ( ) ; Writeback = true ; Parser . Lex ( ) ; } <ISA_LIT>Operand :: CreateMem ( Op , BaseRegNum , OffsetIsReg , Offset , OffsetRegNum , OffsetRegShifted , ShiftType

, ShiftAmount , Preindexed , Postindexed , Negative , Writeback , S , E ) ;


<s> llvm :: call_once ( InitGroupsOnceFlag , [ ] ( ) { get<ISA_LIT>InstrFMA3Info


<s> if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getBitcast ( HVT , OpLo ) ; OpHi = DAG . getBitcast ( HVT , OpHi


<s> switch ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return <NUM_LIT> ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE ( GET_MODE ( src ) ) ) return <NUM_LIT> ; } break ; default : abort (


<s> const <ISA_LIT>Subtarget * Subtarget = & MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>CallingConventionRegisters * Regs = Subtarget ->


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { <ISA_LIT>InstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + <NUM_LIT> ) . getImm (

) , MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) , OS ) ;


<s> __builtin_ia32_directstoreu_u32 ( ( unsigned int *


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl , int caller ) { struct cgraph_node * local_info_node = NULL ; struct cgraph_node * target = NULL ; cfun -> machine -> silent_p = false ; memset ( cum , <NUM_LIT> , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; local_info_node = cgraph_node :: local_info_node ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( local_info_node && local_info_node -> local && local_info_node -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> maybe_vaarg = ( fntype ? ( ! prototype_p ( fntype ) || stdarg_p ( fntype ) ) : ! libname ) ; cum -> decl = fndecl ; cum -> warn_empty = ! warn_abi || cum -> stdarg ; if ( ! cum -> warn_empty && fntype ) { function_args_iterator iter ; tree argtype ; bool seen_empty_type = false ; FOREACH_FUNCTION_ARGS ( fntype , argtype , iter ) { if ( argtype == error_mark_node || VOID_TYPE_P ( argtype ) ) break ; if ( TYPE_EMPTY_P ( argtype ) ) seen_empty_type = true ; else if (


<s> DiagnosticPredicate isMatrixRegOperand ( ) const { if ( ! isMatrix ( ) ) return DiagnosticPredicateTy :: NoMatch ; if ( getMatrixKind ( ) != Kind || ! <ISA_LIT>MCRegisterClasses [ RegClass ] . contains ( getMatrixReg ( ) ) || EltSize != getMatrixElementWidth ( ) ) return


<s> else Index = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , Align ( AM . Align ) , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ; assert ( AM . SymbolFlags


<s> static int arm_default_branch_cost ( bool speed_p , bool predictable_p ATTRIBUTE_UNUSED ) { if ( TARGET_32BIT ) return ( TARGET_THUMB2 && !


<s> if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_APCS_FRAME && TARGET_ARM && TARGET_HARD_FLOAT && decl && arm_is_long_call_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) return false ; if ( TREE_CODE ( exp ) == CALL_EXPR ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) return false ; } if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl &&


<s> if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { ExtendToInt64 ( Base , dl ) , ExtendToInt64 ( V , dl ) , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart ; unsigned RLAmt1 = ( <NUM_LIT> + RLAmt - RLAmt2


<s> case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case


<s> EVT DstTy = TLI -> getValueType ( Dst ) ; if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ; static const TypeConversionCostTblEntry < MVT > ConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; int Idx = ConvertCostTableLookup < MVT > ( ConversionTbl , array_lengthof ( ConversionTbl ) , ISD

, DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ;


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON ( EVT VT ) { addRegisterClass ( VT , <STR_LIT> ) ; addTypeForNEON ( VT , <STR_LIT>


<s> Offset += getOffsetOfLocalArea ( ) ; } if ( IsWin64Prologue ) { assert ( ! MFI . hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return StackOffset :: getFixed ( - SEHFrameOffset ) ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return StackOffset :: getFixed ( Offset + StackSize ) ; } } else if ( TRI -> hasStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else


<s> return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF ||

TargetTriple . getEnvironment ( ) == Triple :: EABIHF ;


<s> const char * const name ; } flags [ ] = { { OPTION_MASK_POWER10 , OTHER_POWER10_MASKS , <STR_LIT> } , { OPTION_MASK_P9_VECTOR , OTHER_P9_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_P8_VECTOR , OTHER_P8_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_VSX , OTHER_VSX_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_ALTIVEC , OTHER_ALTIVEC_MASKS , <STR_LIT> } , } ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( flags ) ; i ++ ) { HOST_WIDE_INT no_flag = flags [ i ] . no_flag ; if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) { HOST_WIDE_INT dep_flags = flags [ i ] . dep_flags ; HOST_WIDE_INT set_flags = ( rs6000_isa_flags_explicit & rs6000_isa_flags & dep_flags ) ; if ( set_flags


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , N0 ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getConstant

( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ;


<s> Value * <ISA_LIT>IREmitter :: visitWrapperRIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> static void loongarch_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) accessible_reg_set &= ~ ( reg_class_contents [ FP_REGS ]


<s> OperandMatchResultTy parseGR32 ( OperandVector & Operands ) { return parseRegister ( Operands , RegGR ,


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; return ( _TEXASRU_EXTRACT_BITS ( texasru , <NUM_LIT> ,


<s> Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result +=


<s> void dump ( ) { cerr << <STR_LIT> << this << '\n' ; if ( BaseType == RegBase ) { cerr << <STR_LIT> ; if ( Base . Reg . getNode ( ) != <NUM_LIT> ) Base . Reg . getNode ( ) -> dump ( ) ; else cerr << <STR_LIT> ; cerr << '\n' ; } else


<s> SDLoc dl ( N ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || ! V2 . getOperand ( <NUM_LIT> ) . isUndef ( ) || ! V1 . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> )


<s> if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> &&

( Offset >> shift ) << shift == Offset ) return true ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return