<s> <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , SuffixLoc , getContext ( ) , true ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , NameLoc , NameLoc , getContext ( ) ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , SuffixLoc , getContext ( ) , true ) ) ; } bool condCodeFourthOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeSecondOperand = ( Head == <STR_LIT> || Head == <STR_LIT> ) ; bool condCodeThirdOperand = ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { unsigned N = <NUM_LIT> ; do { if ( parseOperand ( Operands , ( N == <NUM_LIT> && condCodeFourthOperand ) || ( N == <NUM_LIT> && condCodeThirdOperand ) || ( N == <NUM_LIT> && condCodeSecondOperand ) , condCodeSecondOperand || condCodeThirdOperand ) ) { return true ; } if ( parseOptionalToken ( AsmToken :: RBrac ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; if ( parseOptionalToken ( AsmToken :: Exclaim ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; if ( parseOptionalToken ( AsmToken :: RCurly ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; ++ N ; } while ( parseOptionalToken ( AsmToken :: Comma ) ) ; } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT>


<s> unsigned getVectorListCount ( ) const { assert ( Kind == k_VectorList && <STR_LIT> ) ; return VectorList . Count


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return


<s> const MCSymbolRefExpr * Start = MCSymbolRefExpr :: Create ( StartLabel , OutContext ) ; const MCSymbolRefExpr * Cur = MCSymbolRefExpr :: Create ( CurLabel , OutContext ) ; const MCBinaryExpr * Sub = MCBinaryExpr :: CreateSub ( Cur , Start , OutContext ) ; const MCBinaryExpr * Add = MCBinaryExpr :: CreateAdd ( GOT


<s> return ( uint16x4_t ) __builtin_neon_vld1_dupv4hi ( ( const __builtin_neon_hi *


<s> unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2


<s> static unsigned getCallOpcode ( <ISA_LIT>TargetLowering :: CallFlags CFlags , const Function & Caller , const SDValue & Callee , const <ISA_LIT>Subtarget & Subtarget , const TargetMachine & TM ) { if ( CFlags . IsTailCall ) return <STR_LIT> ; if ( CFlags . IsIndirect ) { return isTOCSaveRestoreRequired ( Subtarget ) ? <STR_LIT> : <STR_LIT> ; } if ( Subtarget . isUsingPCRelativeCalls ( ) ) { assert ( Subtarget . is64BitELFABI ( ) && <STR_LIT> ) ; return <STR_LIT> ; } if ( Subtarget . isAIXABI ( ) || Subtarget . is64BitELFABI ( ) ) return callsShareTOCBase ( & Caller

, Callee , TM ) ? <STR_LIT> : <STR_LIT> ;


<s> static DecodeStatus DecodeMemMMReglistImm4Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; if ( DecodeRegListOperand16 ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV (


<s> bool <ISA_LIT>InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>LowOverheadLoops :: runOnMachineFunction ( MachineFunction & mf ) { const <ISA_LIT>Subtarget & ST = mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasLOB ( ) ) return false ; MF = & mf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; MF -> getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( * MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF -> front ( ) ) ; bool Changed = false ; for ( auto ML : * MLI ) { if ( ML -> isOutermost ( ) ) Changed |= ProcessLoop ( ML ) ; } Changed |= RevertNonLoops


<s> virtual const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return FrameLowering .


<s> return ! Revert && FoundAllComponents ( ) && VCTP && ! CannotTailPredicate && ML


<s> assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createImm ( Length + <NUM_LIT> ) ) ; return MCDisassembler


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget .


<s> uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; uint32_t I = <NUM_LIT> ; I |= Sign << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> :


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addReg ( Src , getKillRegState ( KillSrc ) ) ; break ; case <STR_LIT> : BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addImm ( MImm ) ; break ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addReg ( Src , getKillRegState ( KillSrc ) ) . addReg ( VMX ) ; break ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( VMX ) . addImm ( Imm ) . addImm ( MImm ) . addReg ( VMX ) ; break ; } MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register VMZu = getVM512Upper ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register VMZl = getVM512Lower ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; bool KillSrc = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register VMZ = VMZl ; if ( Imm >= <NUM_LIT> ) { VMZ = VMZu ; Imm -= <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , Dest ) . addReg ( VMZ ) . addImm ( Imm ) ; MachineInstr * Inst = MIB . getInstr (


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . getString ( ) == <STR_LIT> ) { Parser . Lex ( ) ; getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . Lex ( ) ; getTargetStreamer ( ) .


<s> static bool isBR_CC ( unsigned Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT>


<s> Register ZReg = ZRegTable [ Idx ] ; unsigned Opc = OpcTable [ Idx ] ; auto CmpMI = MIB . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return &


<s> assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; assert ( dom && <STR_LIT> ) ; const uint16_t * table = lookup ( MI -> getOpcode ( ) , dom ) ; if ( ! table ) { assert ( ( Subtarget . hasAVX2 ( ) ||


<s> switch ( NewOpc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; } else if (


<s> } unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info . Var . Decl ; IsGlobalLV = Info . Var . IsGlobalLV ; } if ( IsGlobalLV && ( BaseReg || IndexReg ) ) { return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End ) ; } else


<s> bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( ! Subtarget -> isTargetMachO ( ) && IsThreadLocal ) return <NUM_LIT> ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( Subtarget -> useMovt ( * FuncInfo . MF ) && ( Subtarget -> isTargetMachO ( ) || ! IsPositionIndependent ) ) { unsigned Opc ; unsigned char TF = <NUM_LIT> ; if ( Subtarget -> isTargetMachO ( ) ) TF = <STR_LIT> ; if ( IsPositionIndependent ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( IsPositionIndependent ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( IsPositionIndependent ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; return NewDestReg ; } } } if ( IsIndirect ) { MachineInstrBuilder


<s> break ; } int Cost = <NUM_LIT> ; SDValue RHS = Handle . getValue ( ) . getOperand ( <NUM_LIT> ) ; if ( ! RHS . getNode ( ) -> hasOneUse ( ) || RHS . getNode ( ) -> getOpcode ( ) == <STR_LIT> || RHS . getNode ( ) -> getOpcode ( ) == <STR_LIT> || RHS . getNode ( ) -> getOpcode ( ) == <STR_LIT> || ( RHS . getNode ( ) -> getOpcode ( ) == <STR_LIT> && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) ++ Cost ; if ( ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) && AM . Base_Reg -> getOpcode ( ) != <STR_LIT> && ! AM . Base_Reg . getNode ( ) -> hasOneUse ( ) ) || AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) -- Cost ; if ( ( AM . hasSymbolicDisplacement ( ) && ! Backup . hasSymbolicDisplacement ( ) ) + ( ( AM . Disp != <NUM_LIT> ) && ( Backup . Disp == <NUM_LIT> ) ) + ( AM . Segment . getNode ( ) && ! Backup . Segment . getNode ( ) ) >= <NUM_LIT> ) -- Cost ; if ( Cost >= <NUM_LIT> ) { AM = Backup ; break ; } SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , dl , N . getValueType ( ) ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , dl , N . getValueType ( ) , Zero , RHS ) ; AM . IndexReg = Neg ; AM . Scale = <NUM_LIT> ; insertDAGNode ( * CurDAG , Handle . getValue ( ) , Zero ) ; insertDAGNode ( * CurDAG , Handle . getValue ( ) , Neg ) ; return false ; } case <STR_LIT> : if ( ! matchAdd ( N , AM , Depth ) ) return false ; break ; case <STR_LIT> : if ( CurDAG -> haveNoCommonBitsSet ( N . getOperand ( <NUM_LIT> ) , N . getOperand ( <NUM_LIT> ) ) && ! matchAdd ( N , AM , Depth ) ) return false ; break ; case <STR_LIT> : { if ( AM . IndexReg . getNode ( ) != nullptr || AM . Scale != <NUM_LIT> ) break ; SDValue Shift = N . getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> && Shift . getOpcode ( ) != <STR_LIT> ) break ; SDValue X = Shift . getOperand ( <NUM_LIT> ) ; if ( X . getSimpleValueType ( ) . getSizeInBits ( ) > <NUM_LIT> ) break ; if ( ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) break ; uint64_t Mask = N . getConstantOperandVal ( <NUM_LIT> ) ; if ( ! foldMaskAndShiftToExtract ( * CurDAG , N , Mask , Shift , X


<s> User * First = dyn_cast < User > ( Pair . first ) ; User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; Instruction * I = cast < Instruction > ( U . getUser


<s> const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else


<s> unsigned Size = getLSMultipleTransferSize ( FirstMI ) ; unsigned SIndex = <NUM_LIT> ; unsigned EIndex = MemOps . size ( ) ; do { const MachineInstr * MI = MemOps [ SIndex ] . MI ; int Offset = MemOps [ SIndex ] . Offset ; const MachineOperand & PMO = getLoadStoreRegOp ( * MI ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( PReg ) ; unsigned Latest = SIndex ; unsigned Earliest = SIndex ; unsigned Count = <NUM_LIT> ; bool CanMergeToLSDouble = STI -> isThumb2 ( ) && isNotVFP && isValidLSDoubleOffset ( Offset ) ; if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> hasSlowOddRegister ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; if ( AssumeMisalignedLoadStores && ! mayCombineMisaligned ( * STI , * MI ) ) CanMergeToLSMulti = CanMergeToLSDouble = false ; for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I ,


<s> CurDAG -> ComputeMaskedBits ( Op1 , APInt :: getAllOnesValue ( <NUM_LIT> ) , RKZ , RKO ) ; unsigned TargetMask = LKZ . getZExtValue ( ) ; unsigned InsertMask = RKZ . getZExtValue ( ) ; if ( ( TargetMask | InsertMask ) == <NUM_LIT> ) { unsigned Op0Opc = Op0 . getOpcode ( ) ; unsigned Op1Opc = Op1 . getOpcode ( ) ; unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( InsertMask && isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT>


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ; if ( LD . getNode ( ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Shuffle = PerformTargetShuffleCombine ( SDValue ( N , <NUM_LIT> ) , DAG , DCI , Subtarget ) ; if ( Shuffle . getNode ( ) ) return Shuffle ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back (


<s> return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED


<s> for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target , & The<ISA_LIT>elTarget } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer


<s> MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S


<s> static DecodeStatus DecodeGR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MRI . isPhysRegUsed ( reg ) ) continue ; unsigned mapped_reg = ( reg - <STR_LIT> + <STR_LIT> ) ; assert ( ! MRI . isPhysRegUsed ( mapped_reg ) ) ; MRI . replaceRegWith ( reg , mapped_reg ) ; MRI . setPhysRegUnused ( reg


<s> rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( ! value || ! addr || ! MEM_P ( SET_SRC ( value ) ) ) return <NUM_LIT> ; value = SET_DEST ( value ) ; addr = SET_DEST (


<s> if ( getParser ( ) . parseExpression ( Value ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken ::


<s> if ( Kind != k_Register || Reg . Kind != RegKind :: SVEPredicateVector ) return DiagnosticPredicateTy :: NoMatch ; if ( isSVEVectorReg < Class > ( ) && ( ElementWidth == <NUM_LIT> || Reg . ElementWidth == ElementWidth ) )


<s> CCAssignFn * <ISA_LIT>FastISel :: use<ISA_LIT>32CCs ( unsigned Flag ) { if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4 ; else if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4_ByVal ; else if ( Flag == <NUM_LIT> ) return


<s> TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm2


<s> <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , GA , NULL , <NUM_LIT> ,


<s> break ; case <STR_LIT> : case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_32 ; break ; case <STR_LIT> : case FK_Data_2 : Type = ELF :: R_<ISA_LIT>_16 ; break ; case <STR_LIT> : case FK_Data_1 : Type = ELF :: R_<ISA_LIT>_8 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_LO_16_IN_INSN ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_HI_16_IN_INSN ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_INSN_REL_26 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_GOTPC_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_GOTPC_LO16 ; break ; case <STR_LIT> : Type = ELF ::


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> ,


<s> if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; OpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , OpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true ; } unsigned CmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CmpReg == <NUM_LIT> ) return false ; unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CmpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , CmpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( CmpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT>


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> )


<s> void <ISA_LIT>AsmBackend :: handleAssemblerFlag ( MCAssemblerFlag Flag ) { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case


<s> if ( BV -> isConstant ( ) && IndexWidth > <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits ( ) ; if ( IndexWidth != <NUM_LIT> && IndexWidth != <NUM_LIT> ) { MVT EltVT = IndexWidth > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT IndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , Index . getValueType ( ) . getVectorNumElements ( ) ) ; Index = DAG . getSExtOrTrunc ( Index , DL , IndexVT ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } SDValue Mask = GorS -> getMask ( ) ; if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue (


<s> if ( Reg == <STR_LIT> ) I . setRestored ( false ) ; if ( ( <STR_LIT> . contains ( Reg ) ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs [ Reg ] = true ; } auto Terminator = MBB . getFirstTerminator ( ) ; if ( Terminator != MBB . end ( ) && Terminator -> getOpcode ( ) == <STR_LIT> ) { CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; for ( auto Op : Terminator -> implicit_operands ( ) ) { if ( Op . isReg ( ) ) CopyRegs [ Op . getReg ( ) ] = false ; } } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllLoRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; auto HiRegToRestore = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToRestore , AllHighRegsEnd ) ; while ( HiRegToRestore != AllHighRegsEnd ) { assert ( ! CopyRegs . none ( ) ) ; auto CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PopMIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; while ( HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { PopMIB . addReg ( * CopyReg , RegState


<s> switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case 'v' : if ( RegName [ <NUM_LIT> ] == 's' ) return


<s> unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( IntNo ) { default : return SDValue


<s> if ( abi_id == ABI_VZEROUPPER ) return ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( ( TARGET_64BIT && REX_SSE_REGNO_P ( regno ) ) || LEGACY_SSE_REGNO_P ( regno ) ) ) ; return SSE_REGNO_P ( regno ) && GET_MODE_SIZE (


<s> for ( unsigned i = NumElems / <NUM_LIT> , j = <NUM_LIT> ; i != NumElems ; ++ i , ++ j ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , j ) || SVOp -> getMaskElt ( j ) >= <NUM_LIT> ) return false ; return


<s> SDValue NOT ( SDValue A ) { MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNOT ( dl , A , VT


<s> void printdwordmem ( const MCInst * MI ,


<s> static unsigned HOST_WIDE_INT mips_asan_shadow_offset ( void


<s> align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ; return IN_RANGE ( offset , <NUM_LIT> ,


, __artificial__ ) ) _mm_setzero_si128 ( void ) {


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP = true ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } FrameReg = <STR_LIT> ; return FrameOffset + MF . getFrameInfo ( ) .


<s> } } else { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; switch ( Val . getValueType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Val ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) )


<s> void <ISA_LIT>FrameInfo :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } const bool IsWrite = MII . get ( Inst . getOpcode ( ) ) . mayStore ( ) ; RegisterContext RegCtx ( <STR_LIT> , <STR_LIT> , IsSmallMemAccess ( AccessSize ) ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Ix = <NUM_LIT> ; Ix < Operands . size ( ) ; ++ Ix ) { assert ( Operands [ Ix ] ) ; MCParsedAsmOperand & Op = * Operands [ Ix ] ; if ( Op . isMem ( ) ) { <ISA_LIT>Operand & MemOp = static_cast < <ISA_LIT>Operand & > ( Op ) ; if ( IsStackReg ( MemOp . getMemBaseReg ( ) ) || IsStackReg ( MemOp . getMemIndexReg ( ) ) ) { continue ; } InstrumentMemOperandPrologue ( RegCtx , Ctx , Out ) ; InstrumentMemOperand ( MemOp , AccessSize , IsWrite , RegCtx , Ctx , Out ) ; InstrumentMemOperandEpilogue ( RegCtx , Ctx


<s> unsigned Res = MI . getOperand ( OpNo ) . getImm ( ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return Res >>


<s> machine_mode aarch64_hard_regno_caller_save_mode ( unsigned regno , unsigned , machine_mode mode ) { if ( PR_REGNUM_P ( regno ) ) return mode ; if ( known_ge ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return mode ; else return


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg (

MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> if ( UseReg ) return isThumb2 ? <STR_LIT> : <STR_LIT> ; else return isThumb2 ? <STR_LIT> :


<s> Inst . addOperand ( MCOperand :: CreateImm ( getPrefetch ( )


<s> return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , FK_Data_4 ) . Default ( MCAsmBackend


<s> return Start -> getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode (


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) MBB . erase (


<s> bool isELF32_ABI ( ) const { return ! isDarwin ( ) &&


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym


<s> return isGPRAsmReg ( ) && RegIdx . Index


<s> vec_uchar16 bits ; vec_uint4 bytes ; bits = vec_sl ( vec_and ( ( vec_uchar16 ) ( a ) , vec_splat_u8 ( <NUM_LIT> ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; bytes = ( vec_uint4 ) vec_sum2s ( ( vec_int4 ) ( vec_sum4s ( bits , ( ( vec_uint4 ) { <NUM_LIT> } ) ) ) , ( ( vec_int4 ) { <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_perm ( bytes , bytes , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && SubVec . getNode ( ) -> getValueType

( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> ) {


<s> clonei -> mask_mode = VOIDmode ; switch ( clonei -> vecsize_mangle ) { case 'b' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'c' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'e' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; if ( TYPE_MODE ( base_type ) == QImode ) clonei -> mask_mode = DImode ; else clonei -> mask_mode = SImode ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen /= GET_MODE_BITSIZE ( TYPE_MODE ( base_type ) ) ; } else if ( clonei -> simdlen > <NUM_LIT> ) { tree ctype = ret_type ; if ( TREE_CODE ( ret_type ) == VOID_TYPE ) ctype = base_type ; int cnt = GET_MODE_BITSIZE ( TYPE_MODE ( ctype ) ) * clonei -> simdlen ; if ( SCALAR_INT_MODE_P ( TYPE_MODE ( ctype ) ) ) cnt /= clonei -> vecsize_int ; else cnt /= clonei -> vecsize_float ; if ( cnt > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) { warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , clonei -> simdlen ) ; return <NUM_LIT> ; } } return


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && ! cfun -> machine -> use_shadow_register_set_p ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_really_used_regs [


<s> static bool sparc_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( ! TARGET_VIS2 ) return false ; if ( ! target ) return true ; if ( vmode != V8QImode ) return false ; rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 =


<s> if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE1 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE2 ; ToggleFeature ( <STR_LIT> ) ; } if ( ECX & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE3 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSSE3 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE41 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE42 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = AVX ; ToggleFeature ( <STR_LIT> ) ; } bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasPCLMUL = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasFMA = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasMOVBE = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasPOPCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasAES = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature (


<s> unsigned getT2AddrModeImm8OpValue ( const MachineInstr & MI


<s> int _U_Qfunord ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD ) !=


<s> AM . Base_Reg = AM . IndexReg ; AM . Scale = <NUM_LIT> ; } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr && AM . IndexReg . getNode ( ) == nullptr && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false


<s> } switch ( TSFlags & <STR_LIT> ) { default : break ; case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } } if ( SegmentReg != <NUM_LIT> ) return <STR_LIT> ( SegmentReg ) ; if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; if ( MemoryOperand >= <NUM_LIT> )


<s> gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_INC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; default : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; break ; } sprintf ( buff , templ , load ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : sp ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : <STR_LIT> , integer_p ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops )


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; assert ( N0 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Subtarget . hasAVX512 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( ( double ) ( <NUM_LIT> << <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWordMask ) ; SDValue fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI ) ; fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI , TWOHW ) ; SDValue fLO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI ,


<s> vpaddlq_s8 ( int8x16_t a ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else if ( DstSize == <NUM_LIT> ) RC = STI . isFP64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn (


<s> } else if ( mcop . isImm ( ) ) { if ( i == <NUM_LIT> && ( mc . getOpcode ( ) == <STR_LIT> || mc . getOpcode ( ) == <STR_LIT> ) ) { mi -> addOperand ( MachineOperand :: CreateMBB ( bb -> jump -> mbb ) ) ; } else mi -> addOperand ( MachineOperand :: CreateImm ( mcop . getImm ( ) ) ) ; } else if ( mcop . isFPImm ( ) ) { } else if ( mcop . isExpr ( ) ) { } else if ( mcop .


<s> needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MemoryReg ) ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = <STR_LIT> ; Op -> Mem . Off


<s> ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( VLdLn ) , { MemOp } ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; } SuperReg = SDValue (


<s> if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > (


<s> if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } return


<s> auto * BV2 = dyn_cast < BuildVectorSDNode > ( V2 ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != ExpectedMask [ i ] ) { auto * MaskBV = Mask [ i ] < Size ? BV1


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return <STR_LIT>


<s> if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [ code


<s> SDValue Big = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstantFP ( <NUM_LIT> , dl , SrcVT ) ) ) ; if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , Small , Big ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Small


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] && ExtraCode [ <NUM_LIT> ] != 'a' ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum


<s> if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) || ( Reg == ExcludedReg ) ) return ; if ( MO . isDef ( ) ) RegDefs


<s> static int sh_target_reg_class ( void ) { return TARGET_SHMEDIA ? TARGET_REGS :


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> vmovl_high_s32 ( int32x4_t a ) { int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> void addMemThumbRROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { return <NUM_LIT>


<s> static const MachineOperand & getLdStRegOp ( const


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) && ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetWindows ( ) ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget -> isTargetNaCl ( ) ) { RetValReg = Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Zext = DAG . getZExtOrTrunc ( Val , dl , <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Zext , Flag ) ; } else { Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; } Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & RetOps [ <NUM_LIT> ] , RetOps . size (


<s> if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> ; if ( UseCycle < <NUM_LIT> ) UseCycle = <NUM_LIT> ; UseCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; } else { UseCycle = <NUM_LIT> ; } return UseCycle


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ,


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; if ( Subtarget . isTargetNaCl ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType (


<s> if ( high == <NUM_LIT> || high == - <NUM_LIT> ) return <NUM_LIT> ; high >>= <NUM_LIT> ; if ( low == <NUM_LIT> ) return num_insns_constant_wide ( high ) + <NUM_LIT> ; else if ( high == <NUM_LIT> )

return num_insns_constant_wide ( low ) + <NUM_LIT> ;


<s> initialize<ISA_LIT>BranchExpansionPass ( * PassRegistry :: getPassRegistry ( )


<s> void markPhysRegUsed ( unsigned PhysReg ) override { MIRBuilder . getMRI ( ) -> addLiveIn (


<s> return DecodeRegisterClassByID ( Inst , RegNo ,


<s> return ( __m512i ) __builtin_ia32_broadcasti32x4_512 ( ( __v4si ) __A , ( __v16si ) _mm512_undefined_epi32 ( ) ,


<s> int idx , vlen = XVECLEN ( body , <NUM_LIT> ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( <STR_LIT> , asm_out_file ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_DIFF_ELT ( asm_out_file , body , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , <NUM_LIT> , idx ) , <NUM_LIT> ) ) , CODE_LABEL_NUMBER ( base ) ) ; } if ( TARGET_GAS ) fputs ( <STR_LIT> ,


<s> Optional < int > getMaskPos ( unsigned Opc ) { auto PosOpt = <STR_LIT> ( Opc ) ; if ( PosOpt ) return * PosOpt ; if ( isVVPBinaryOp ( Opc ) ) return <NUM_LIT> ; switch ( Opc ) { case <STR_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG ->

getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ;


<s> int NumElts = Mask . size ( ) ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { int M = Mask [ i ] ; assert ( ( M == SM_SentinelUndef || ( <NUM_LIT> <= M && M < ( <NUM_LIT> * NumElts ) ) ) && <STR_LIT> ) ; if ( M < <NUM_LIT> ) continue ; int StartIdx = i - ( M % NumElts ) ; if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; SDValue MaskV = M < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return - <NUM_LIT> ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi )


<s> if ( GET_MODE ( value ) == VOIDmode && size > <NUM_LIT> ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= <NUM_LIT> ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= <NUM_LIT> ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = <NUM_LIT> ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize ,


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode (


<s> const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> const MachineOperand * Base ; int64_t Offset ; bool OffsetIsScalable ; if ( ! getMemOperandWithOffset ( MemI , Base , Offset

, OffsetIsScalable , TRI ) ) return None ;


<s> static SDValue combineBVOfConsecutiveLoads ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( N ) ; bool InputsAreConsecutiveLoads = true ; bool InputsAreReverseConsecutive = true ; unsigned ElemSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue FirstInput = N -> getOperand ( <NUM_LIT> ) ; bool IsRoundOfExtLoad = false ; if ( FirstInput . getOpcode ( ) == <STR_LIT> && FirstInput . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = dyn_cast < LoadSDNode > ( FirstInput . getOperand ( <NUM_LIT> ) ) ; IsRoundOfExtLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } if ( ! IsRoundOfExtLoad && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { if ( IsRoundOfExtLoad && N -> getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NextInput = IsRoundOfExtLoad ? N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i ) ; if ( NextInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue PreviousInput = IsRoundOfExtLoad ? N -> getOperand ( i - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( PreviousInput ) ; LoadSDNode * LD2 = dyn_cast < LoadSDNode > ( NextInput ) ; if ( IsRoundOfExtLoad && LD2 -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isConsecutiveLS ( LD2 , LD1 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreConsecutiveLoads = false ; if ( ! isConsecutiveLS ( LD1 , LD2 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreReverseConsecutive = false ; if ( ! InputsAreConsecutiveLoads && ! InputsAreReverseConsecutive ) return SDValue ( ) ; } assert ( ! ( InputsAreConsecutiveLoads && InputsAreReverseConsecutive ) && <STR_LIT> ) ; SDValue FirstLoadOp = IsRoundOfExtLoad ? FirstInput . getOperand ( <NUM_LIT> ) : FirstInput ; SDValue LastLoadOp = IsRoundOfExtLoad ? N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( FirstLoadOp ) ; LoadSDNode * LDL = dyn_cast < LoadSDNode > ( LastLoadOp ) ; if (


<s>
}
O
<<
TAI
->
getCOMMDirective
(
)
<<
name
<<
','
<<
Size
;
if
(
TAI
->
getCOMMDirectiveTakesAlignment
(
)
)
O
<<
','
<<
(
TAI
->
getAlignmentIsInBytes
(
)
(
<NUM_LIT>
<<
Align
)
:
Align
)
;
}
if
(
VerboseAsm
)
{
O
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;
PrintUnmangledNameSafely
(
GVar
,
O
)
;
}
O
<<
'\n'
;
return
;
}
}
switch
(
GVar
->
getLinkage
(
)
)
{
case
GlobalValue
::
CommonLinkage
:
case
GlobalValue
::
LinkOnceAnyLinkage
:
case
GlobalValue
::
LinkOnceODRLinkage
:
case
GlobalValue
::
WeakAnyLinkage
:
case
GlobalValue
::
WeakODRLinkage
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
<<
TAI
->
getWeakDefDirective
(
)
<<
name
<<
'\n'
;
}
else
if
(
Subtarget
->
isTargetCygMing
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
<STR_LIT>
<STR_LIT>
;
}
else
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
}
break
;
case
GlobalValue
::
DLLExportLinkage
:
case
GlobalValue
::
AppendingLinkage
:
case
GlobalValue
::
ExternalLinkage
:
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
case
GlobalValue
::
PrivateLinkage
:
case
GlobalValue
::
InternalLinkage
:
break
;
default
:
assert
(
<NUM_LIT>
&&
<STR_LIT>
)
;
}
EmitAlignment
(
Align
,
GVar
)
;
O
<<
name
<<
<STR_LIT>
;
if
(
VerboseAsm
)
{
O
<<
name
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;
PrintUnmangledNameSafely
(
GVar
,
O
)


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO2 . getReg (


<s> if ( STI . getFeatureBits ( ) & llvm :: <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand (

<NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) {


<s> return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) )


<s> rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx


<s> if ( Disable<ISA_LIT>LEAOpt || skipFunction ( * MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) -> optForSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( )


<s> else return function_value_ms_32 ( orig_mode , mode , fntype , fn , valtype ) ; } else if ( TARGET_64BIT ) return function_value_64 ( orig_mode , mode , valtype ) ; else return function_value_32 ( orig_mode , mode , fntype


<s> void printi8mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo ,


<s> unsigned LOOPi = ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ; return


<s> case <STR_LIT> : return ELF :: R_390_PC16DBL ; case <STR_LIT> : return ELF :: R_390_PC24DBL ; case <STR_LIT> : return ELF :: R_390_PC32DBL ; } llvm_unreachable (


<s> if ( MO . isReg ( ) ) return TM . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI


<s> SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case BND0_REG : case BND1_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG


<s> Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: Tilde ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( )


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( IsIntegerCC ( CC ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; Register UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; Register DefReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isFloatTy ( ) || ! V -> getType ( ) -> isDoubleTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg (


<s> bool isMemDisp12 ( MemoryKind MemKind , RegisterKind RegKind ) const { return isMem ( MemKind , RegKind ) && inRange ( Mem . Disp , <NUM_LIT> ,


<s> void addCCRAsmRegOperands ( MCInst & Inst


<s> EVT InVT = Zext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned RegSize = std :: max ( <NUM_LIT> , InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; MVT SadVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; return SplitOpsAndApply ( DAG , Subtarget , DL , SadVT , { SadOp0 , SadOp1


<s> if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == <NUM_LIT> || size == <NUM_LIT> ) { if ( ! TARGET_ARCH32 || size == <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT> ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 || sparc_cpu == PROCESSOR_NIAGARA7 ) return <NUM_LIT> ; return <NUM_LIT> ; } return <NUM_LIT>


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg


<s> opt_pass * clone ( ) final override { return new pass_stv ( m_ctxt


<s> return decodeBDAddr12Operand ( Inst , Field , <STR_LIT>


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( )


<s> SDValue <ISA_LIT>cc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( SExt -> getType ( ) != ConsideredSExtType ) return false ; for ( const User * U : SExt -> users ( ) ) { if ( isa < GetElementPtrInst > ( U ) ) return true ; } return


<s> bool isCheapToSpeculateCtlz ( ) const


<s> Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } else { DestReg1 = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg1 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) { GlobalBaseReg = MRI . createVirtualRegister ( TLI . getRegClassFor ( VT ) ) ; AFI -> setGlobalBaseReg ( GlobalBaseReg ) ; } unsigned DestReg2 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; DestReg2 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg2 , <NUM_LIT> ) ; DestReg1 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg1 , <NUM_LIT> ) ; GlobalBaseReg = constrainOperandRegClass ( TII . get ( Opc ) , GlobalBaseReg , <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg2 ) . addReg ( DestReg1 ) . addReg ( GlobalBaseReg ) ; if ( ! UseGOTOFF ) MIB .


<s> if ( window_num == <NUM_LIT> ) { if ( dispatch_window_list -> next ) init_window ( <NUM_LIT> ) ; init_window ( <NUM_LIT> ) ; return dispatch_window_list ; } dispatch_window_list -> next


<s> assert ( Node -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue X = Node -> getOperand ( <NUM_LIT> ) ; SDValue C = Node -> getOperand ( <NUM_LIT> ) ; auto * BVN = dyn_cast < BuildVectorSDNode > ( C ) ; if ( ! BVN ) return false ; APInt SplatValue ,


<s> if ( RegNo > sizeof ( SRDecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = SRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> if ( ! Subtarget -> hasInt256 ( ) && VT . is256BitVector ( ) ) return SDValue ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V2 . getOpcode ( ) != <STR_LIT> || ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Shift = <NUM_LIT> ; while ( ( <NUM_LIT> << Shift ) < NumElems ) { if ( SVOp -> getMaskElt ( <NUM_LIT> << Shift ) == <NUM_LIT> ) break ; Shift += <NUM_LIT> ; if ( Shift > <NUM_LIT> ) return SDValue ( ) ; } unsigned Mask = ( <NUM_LIT> << Shift ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int EltIdx = SVOp -> getMaskElt (


<s> } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_VECTOR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } else if ( ( addr_mask != <NUM_LIT> ) && TARGET_MMA && ( m2 == OOmode || m2 == XOmode ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) { addr_mask |= RELOAD_REG_QUAD_OFFSET ; if ( m2 == OOmode ) addr_mask |= RELOAD_REG_INDEXED ; } } if ( rc == RELOAD_REG_VMX && msize == <NUM_LIT> && ( addr_mask &


<s> APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , BoolCarry , DAG . getConstant ( NegOne , DL ,


<s> auto * CIdx = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( CIdx && CIdx -> getAPIntValue ( ) . ult ( VecVT . getVectorNumElements ( ) ) && ! DemandedElts [ CIdx -> getZExtValue ( ) ] ) return Vec ; break ; } case <STR_LIT> : if ( DemandedBits . isSignMask ( ) && <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return Op . getOperand ( <NUM_LIT> ) ; break ; } APInt ShuffleUndef , ShuffleZero ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; if ( getTargetShuffleInputs ( Op , DemandedElts , ShuffleOps , ShuffleMask , ShuffleUndef , ShuffleZero , DAG , Depth , false ) ) { int NumOps = ShuffleOps . size ( ) ; if ( ShuffleMask . size ( ) == ( unsigned ) NumElts && llvm :: all_of ( ShuffleOps , [ VT ] ( SDValue V ) { return VT . getSizeInBits ( ) == V . getValueSizeInBits ( ) ; } ) ) { if ( DemandedElts . isSubsetOf ( ShuffleUndef ) ) return DAG . getUNDEF ( VT ) ; if ( DemandedElts . isSubsetOf ( ShuffleUndef | ShuffleZero ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( Op ) ) ; APInt IdentityOp = APInt :: getAllOnesValue ( NumOps ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = ShuffleMask [ i ] ; if ( ! DemandedElts [ i ] || ShuffleUndef [ i ] ) continue ; int OpIdx = M / NumElts ; int EltIdx = M % NumElts ; if ( M < <NUM_LIT> || EltIdx != i ) { IdentityOp . clearAllBits ( ) ; break ; } IdentityOp &= APInt :: getOneBitSet ( NumOps , OpIdx ) ; if ( IdentityOp == <NUM_LIT>


<s> case ARM_PCS_AAPCS64 : return DFmode ; case ARM_PCS_SIMD : return TFmode ; case ARM_PCS_SVE : if ( aarch64_emit_cfi_for_reg_p ( regno ) ) return VNx2DImode ; return VNx16QImode ; case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MO -> OperandType == MCOI :: OPERAND_MEMORY ) return i ; i ++ ; } return -


<s> SDValue BaseShAmt ; EVT EltVT = VT . getVectorElementType ( ) ; if ( Amt . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned i , j ; for ( i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( Amt . getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; break ; } for ( j = i ; j != NumElts ; ++ j ) { SDValue Arg = Amt . getOperand ( j ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; if ( Arg != Amt . getOperand ( i ) ) break ; } if ( i != NumElts && j == NumElts ) BaseShAmt = Amt . getOperand ( i ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; if ( Amt . getOpcode ( ) == <STR_LIT> && cast < ShuffleVectorSDNode > ( Amt ) -> isSplat ( ) ) { SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( Amt ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , Amt , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } } if ( BaseShAmt . getNode ( ) ) { if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT


<s> unsigned NumElts = Mask . size ( ) ; unsigned Len = NumElts - ( ZeroLo + ZeroHi ) ; if ( ! isSequentialOrUndefInRange ( Mask , ZeroLo , Len , Mask [ ZeroLo ] ) ) return SDValue ( ) ; unsigned Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; ArrayRef < int > StubMask = Mask . slice ( ZeroLo , Len ) ; if ( ! isUndefOrInRange ( StubMask , <NUM_LIT> , NumElts ) && ! isUndefOrInRange ( StubMask , NumElts , <NUM_LIT> * NumElts ) ) return SDValue ( ) ; SDValue Res = Mask [ ZeroLo ] < ( int ) NumElts ? V1 : V2 ; Res = DAG . getBitcast ( <STR_LIT> , Res ) ; if ( ZeroLo == <NUM_LIT> ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * ZeroHi , DL , <STR_LIT> ) ) ; } else if ( ZeroHi == <NUM_LIT> ) { unsigned Shift = Mask [ ZeroLo ] % NumElts ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * ZeroLo , DL , <STR_LIT> ) ) ; } else if ( ! Subtarget . hasSSSE3 ( ) ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Shift += Mask [ ZeroLo ] % NumElts ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( Scale * ZeroLo , DL , <STR_LIT> ) ) ; } else return SDValue ( ) ; return DAG . getBitcast ( VT


<s> int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent ( )


<s> int64_t Imm = MI -> getOperand ( Op ) . getImm ( ) ; assert ( ( Imm &


<s> if ( ! BYTES_BIG_ENDIAN ) return PAD_UPWARD ; if ( type ? ( INTEGRAL_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) || POINTER_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || SCALAR_FLOAT_MODE_P ( mode ) ) ) return PAD_DOWNWARD ; return PAD_UPWARD


<s> int64_t popOperand ( ) { assert ( ! PostfixStack . empty ( ) && <STR_LIT> ) ; ICToken Op = PostfixStack . pop_back_val ( ) ; if ( ! ( Op . first == IC_IMM || Op . first == IC_REGISTER )


<s> void addMemOffsOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand ::


<s> StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } Triple


<s> assert ( Modifier && <STR_LIT> ) ; if ( ! strcmp ( Modifier , <STR_LIT> ) ) { unsigned ID = MI -> getOperand ( OpNum ) . getImm ( ) ; OutStreamer . EmitLabel ( GetCPISymbol ( ID ) ) ; } else { assert ( ! strcmp ( Modifier , <STR_LIT> ) && <STR_LIT> ) ; unsigned CPI = MI -> getOperand ( OpNum ) . getIndex ( ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPI ] ; if ( MCPE . isMachineConstantPoolEntry ( )


<s> NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Lo ; Ops [ <NUM_LIT> ] = Hi ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = MFFSreg ; Ops [ <NUM_LIT> ] = FPreg ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl ,


<s> LoadInst * <ISA_LIT>TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , Align ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded )


<s> Src1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( Src1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) { assert ( Src1 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } if ( ! Src0 ) { SubReg0 = <NUM_LIT> ; Src0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src0 , OrigSrc0 , true ) ; } if ( ! Src1 ) { SubReg1 = <NUM_LIT> ; Src1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src1 , OrigSrc1 , true ) ; } unsigned Dst = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) , Dst ) . addReg ( Src0 , getKillRegState ( true ) , SubReg0 ) . addReg ( Src1 , getKillRegState ( true ) , SubReg1 ) ; insertCopy ( TII , MI , MI -> getOperand ( <NUM_LIT> ) . getReg


<s> if ( auto * Op2 = dyn_cast < ConstantSDNode > ( Src2 ) ) { int64_t Value = ( - Op2 -> getAPIntValue ( ) ) . getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Value ) || Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getConstant ( Value , DL , MemVT ) ; } else if ( Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getNode ( <STR_LIT> , DL , MemVT , DAG . getConstant ( <NUM_LIT> , DL , MemVT ) , Src2 ) ; if ( NegSrc2 . getNode ( ) ) return DAG . getAtomic ( <STR_LIT> , DL , MemVT , Node -> getChain ( ) , Node -> getBasePtr ( ) , NegSrc2 , Node -> getMemOperand ( ) ) ; return Op ; } return lowerATOMIC_LOAD_OP ( Op , DAG


<s> Patterns . push_back ( Pattern ) ; Found = true ; } } ; typedef MachineCombinerPattern MCP ; switch ( Opc ) { default : break ; case <STR_LIT> : assert ( Root . getOperand ( <NUM_LIT> ) . isReg ( ) && Root . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDWI_OP1 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDXI_OP1 ) ; break ; case


<s> return arm_find_sub_rtx_with_code ( pattern ,


<s> if ( FI >= <NUM_LIT> ) Offset += getUnallocatedTopBytes ( MF ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize