<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU , bool isLittle ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; } case Triple ::


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> if ( VT == <STR_LIT> || ! VT . isSimple ( ) ) return false ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf64 ) return false ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> ) return false ; return ( AllowI1 && VT == <STR_LIT> ) ||


<s> unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Imm . getActiveBits ( ) >= <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( Bits == <NUM_LIT> || ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ~ SImmVal < <NUM_LIT> ) || <STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ; return


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass >


<s> c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 <<= <NUM_LIT> - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 =


<s> MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII -> get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr ) . addImm ( HighOffset )


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Parser . getTok ( ) . getIdentifier ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ , getContext ( ) ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( SDValue Res = tryCombineToEXTR ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineToBSL ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineVecOrNot ( N , DCI ) ) return Res ; return SDValue ( )


<s> static bool isBrAnalysisUnpredicatedTerminator ( const MachineInstr * MI , const <ISA_LIT>InstrInfo & TII ) { if ( MI -> getOpcode ( ) == <STR_LIT> )


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( STI , Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; Out . EmitBundleUnlock


<s> int short_memory_operand ( rtx x , enum machine_mode mode ) { if ( ! memory_operand ( x , mode )


<s> SelectAddrMode2Worker ( N , Base , Offset , Opc ) ; return


<s> if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <= Offset2 && <STR_LIT> ) ; return Offset1 + <NUM_LIT> ==


<s> NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128DRegisterClass ; } else llvm_unreachable ( <STR_LIT> ) ; assert ( NSize != <NUM_LIT> && RegDecoder != nullptr ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , NSize ) ; MI . addOperand ( MCOperand :: CreateImm ( tmp


<s> V2 = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; if ( HiIndex >= <NUM_LIT> ) { Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } else { Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } } Locs . clear ( ) ; Locs . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LoMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > HiMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > * MaskPtr = & LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = & HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; ( * MaskPtr ) [ LoIdx ] = Idx ; LoIdx ++ ; } else


<s> if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } addr = XEXP ( orig_src , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_src = replace_equiv_address ( orig_src , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } if ( might_overlap && num_reg + <NUM_LIT> >= MAX_MOVE_REG && bytes > move_bytes ) return <NUM_LIT> ; gcc_assert ( mode != BLKmode ) ; src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; if ( move_with_length ) { loads [ num_reg ] = ( * gen_func . movlen ) ( tmp_reg , src , move_bytes ) ; stores [ num_reg ++ ] = ( * gen_func . movlen ) ( dest , tmp_reg , move_bytes ) ; } else { loads [ num_reg ] = ( * gen_func . mov )


<s> if ( GET_CODE ( lhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) return <NUM_LIT> ; for ( ; link ; link = link -> next ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; rtx use_body = PATTERN ( use_insn ) ; if ( GET_CODE ( use_body ) != SET || GET_CODE ( SET_SRC ( use_body ) ) != UNSPEC || XINT ( SET_SRC ( use_body ) , <NUM_LIT> ) != UNSPEC_VSX_XXSPLTW || XVECEXP ( SET_SRC ( use_body ) , <NUM_LIT> , <NUM_LIT> ) != const0_rtx ) return <NUM_LIT> ; } } return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_CONCAT && ( GET_MODE ( SET_SRC ( body ) ) == V2DFmode || GET_MODE ( SET_SRC ( body ) ) == V2DImode ) ) { * special = SH_CONCAT ; return <NUM_LIT> ; } if ( GET_CODE ( body ) == PARALLEL ) { rtx expr = XVECEXP ( body , <NUM_LIT> ,


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT ,


<s> void OptimizePICCall :: incCntAndSetReg ( const Value * Entry , unsigned Reg ) { CntRegP P = ScopedHT . lookup (


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget (


<s> return ( ( qword ) ( vec_nmsub ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b )


<s> static bool isLDSTUIMM ( InsnType insn ) { return ( ( ( insn ) &


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) )


<s> if ( ! isSATValidOnAVX512Subtarget ( In . getValueType ( ) , VT , Subtarget ) ) return SDValue ( ) ; return detectUSatPattern ( In , VT , DAG ,


<s> const MCSymbol * <ISA_LIT>ELFObjectWriter :: undefinedExplicitRelSym ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { assert ( Target . getSymA ( ) && <STR_LIT> ) ; const MCSymbol & Symbol = Target . getSymA ( ) -> getSymbol ( ) . AliasedSymbol ( ) ; unsigned RelocType = getRelocTypeInner ( Target , Fixup , IsPCRel ) ; bool EmitThisSym = RelocType != ELF :: R_<ISA_LIT>64_TOC ; if ( EmitThisSym && ! Symbol . isTemporary


<s> bool <ISA_LIT>InvISelDAG :: SelectT2ShifterOperandReg ( SDValue N , SDValue & BaseReg , SDValue & Opc ) { return


<s> } case <STR_LIT> : { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ImmVal = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( DstReg ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( SOImmValV1 ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT>


<s> unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( unsigned R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , false ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept (


<s> if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += 'p' ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( <STR_LIT> ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += 'm' ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( SoftFloat ) Key += FS . empty ( ) ?


<s> static void mips_reorg ( void ) { if ( TARGET_MIPS16 ) mips16_lay_out_constants ( ) ; else if ( TARGET_EXPLICIT_RELOCS ) { if ( mips_flag_delayed_branch ) dbr_schedule ( get_insns ( ) , dump_file ) ; mips_avoid_hazards (


<s> MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT>


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM , false ) ) return false ; return <ISA_LIT>FastEmitStore ( VT , I -> getOperand ( <NUM_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> :


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset +=


<s> unsigned reservedArgArea ( ) const { return


<s> return ( MO1 . isImm ( ) && MO2 . isImm ( ) ) || ( MO1 . isCPI ( ) && MO2 . isCPI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isJTI ( ) && MO2 . isJTI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isSymbol ( ) && MO2 . isSymbol ( ) && MO1 . getSymbolName ( ) == MO2 . getSymbolName (

) ) || ( MO1 . isGlobal ( ) && MO2 . isGlobal ( ) && MO1 . getGlobal ( ) == MO2 . getGlobal ( ) ) || ( MO1 . isBlockAddress ( ) && MO2 . isBlockAddress ( ) && MO1 . getBlockAddress ( ) == MO2 . getBlockAddress ( ) ) || ( MO1 . isMCSymbol ( ) && MO2 . isMCSymbol ( ) && MO1 . getMCSymbol ( ) == MO2 . getMCSymbol ( ) ) ;


<s> } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , true ) ; -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( Terminator == MBB . end ( ) || ! isTailCallOpcode ( Terminator -> getOpcode ( ) ) ) { int Offset = - <NUM_LIT> * <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if (


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( ! Subtarget . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( * this ) ) ; return true


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode


<s> auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg && TheReg -> isInRequiredFeatures ( { <STR_LIT> } ) ) { O << TheReg -> Name ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } } auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } O << SYSm ; return ; } unsigned SpecRegRBit = Op . getImm ( ) >> <NUM_LIT> ; unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable (


<s> unsigned SrcAddrSpace = ~ <NUM_LIT> ; const Function * F = I -> getParent ( ) -> getParent ( ) ; if ( const auto * MC = dyn_cast < MemTransferInst > ( I ) ) { ConstantInt * C = dyn_cast < ConstantInt > ( MC -> getLength ( ) ) ; if ( ! C ) return - <NUM_LIT> ; const unsigned Size = C -> getValue ( ) . getZExtValue ( ) ; const Align DstAlign = * MC -> getDestAlign ( ) ; const Align SrcAlign = * MC -> getSourceAlign ( ) ; MOp = MemOp :: Copy ( Size , false , DstAlign , SrcAlign , false , false ) ; DstAddrSpace = MC -> getDestAddressSpace ( ) ; SrcAddrSpace = MC -> getSourceAddressSpace ( ) ; } else if ( const auto * MS = dyn_cast < MemSetInst > ( I ) ) { ConstantInt * C = dyn_cast < ConstantInt > ( MS -> getLength ( ) ) ; if ( ! C ) return - <NUM_LIT> ; const unsigned Size = C -> getValue ( ) . getZExtValue ( ) ; const Align DstAlign = * MS -> getDestAlign ( ) ; MOp = MemOp :: Set ( Size , false , DstAlign , false , false ) ; DstAddrSpace = MS -> getDestAddressSpace ( ) ; } else llvm_unreachable (


<s> } if ( code == UNEQ && HONOR_NANS ( compare_mode ) ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) == CONST_DOUBLE ) REAL_VALUE_FROM_CONST_DOUBLE ( c1 , op1 ) ; if ( HONOR_INFINITIES ( compare_mode ) && code != GT && code != UNGE && ( GET_CODE ( op1 ) != CONST_DOUBLE || real_isinf ( & c1 ) ) && ( ( ! rtx_equal_p ( op0 , false_cond ) && ! rtx_equal_p ( op1 , false_cond ) ) || ( ! rtx_equal_p ( op0 , true_cond ) && ! rtx_equal_p ( op1 , true_cond ) ) ) ) return <NUM_LIT> ; if ( ! is_against_zero ) { temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_MINUS ( compare_mode , op0 , op1 ) ) ) ; op0 = temp ; op1 = CONST0_RTX ( compare_mode ) ; } if ( ! HONOR_NANS ( compare_mode ) ) switch ( code ) { case GT : code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; break ; case UNGE : code = GE ; break ; case UNEQ : code = EQ ; break ; default : break ; } switch ( code ) { case GE : break ; case LE : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case ORDERED : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_ABS ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case EQ : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_NEG ( compare_mode , gen_rtx_ABS


<s> xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1


<s> <STR_LIT> getVPTPred ( ) const { assert ( isVPTPred ( )


<s> case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEDNOW_MAP ; }


<s> void rs6000_secondary_reload_gpr ( rtx reg , rtx mem , rtx scratch , bool store_p ) { int regno = true_regnum ( reg ) ; enum reg_class rclass ; rtx addr ; rtx scratch_or_premodify = scratch ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , store_p ? <STR_LIT> : <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( reg ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && HARD_REGISTER_NUM_P ( regno ) ) ; gcc_assert ( MEM_P ( mem ) ) ; rclass = REGNO_REG_CLASS ( regno ) ; gcc_assert ( rclass == GENERAL_REGS || rclass == BASE_REGS ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PRE_MODIFY ) { gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) == XEXP ( addr , <NUM_LIT> ) ) ; scratch_or_premodify = XEXP ( addr


<s> RegisterTarget < Triple :: aarch64 , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getParent ( ) -> getParent ( ) -> getTarget (


<s> MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext ( ) ; UnsupportedFPMode = Subtarget -> isFP64bit ( ) || Subtarget


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( get<ISA_LIT>RegisterNumbering ( MinGPR ) , get<ISA_LIT>RegisterNumbering ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSAVESaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx


<s> bool IsStore = ( Instruction :: Store == Opcode ) ; VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , Alignment , AddressSpace ) ; unsigned NumElem = SrcVTy -> getVectorNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShiftAmt = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr


<s> if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / ElSize ; unsigned NumEltsPerLane = <NUM_LIT> / ElSize ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Selector = RawMask [ i ] ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; if ( ( M2Z & <NUM_LIT> ) != <NUM_LIT> && MatchBit != ( M2Z & <NUM_LIT> ) ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } int Index = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; if ( ElSize == <NUM_LIT> ) Index += ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; else Index += Selector & <NUM_LIT> ; int Src = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; Index += Src


<s> } if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> for ( const SDNode * User : Flags -> uses ( ) ) { <STR_LIT> CC ; switch ( User -> getOpcode ( ) ) { default : return true ; case <STR_LIT> : case <STR_LIT> : CC = ( <STR_LIT> ) User -> getConstantOperandVal ( <NUM_LIT> ) ; break ; case <STR_LIT> : CC = ( <STR_LIT> ) User -> getConstantOperandVal ( <NUM_LIT> ) ; break ; case <STR_LIT>


<s> void <ISA_LIT>AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands ,


<s> Value * BasePtr = II . getOperand ( <NUM_LIT> ) ; Value * Index = II . getOperand ( <NUM_LIT> ) ; Type * Ty = II . getType ( ) ; Type * BasePtrTy = BasePtr -> getType ( ) ; Value * PassThru = ConstantAggregateZero :: get ( Ty ) ; Value * IndexBase ; if ( match ( Index , m_Intrinsic < <STR_LIT> > ( m_Value ( IndexBase ) , m_SpecificInt ( <NUM_LIT> ) ) ) ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II


<s> return ( from == RETURN_ADDRESS_POINTER_REGNUM && ( ! leaf_function_p ( ) || ( to == GP_REG_FIRST + <NUM_LIT> && leaf_function_p ( ) ) ) ) || ( from != RETURN_ADDRESS_POINTER_REGNUM

&& ( to == HARD_FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed ) ) ) ;


<s> if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> return ( __m64 ) __builtin_arm_walignr3 ( ( __v8qi )


<s> auto & Table = MemUnfoldTable -> Table ; auto I = llvm :: lower_bound ( Table , MemOp ) ; if ( I != Table . end ( ) && I -> KeyOp == MemOp ) return & * I ; return nullptr


<s> static tree rx_decl_for_addr ( rtx op ) { if ( GET_CODE ( op ) == MEM ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == CONST ) op


<s> return ( long long ) __builtin_ia32_vcvttsd2si64 ( (


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ; case


<s> void <ISA_LIT>TargetLowering :: insertCopiesSplitCSR ( MachineBasicBlock * Entry , const SmallVectorImpl < MachineBasicBlock * > & Exits ) const { const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * IStart = TRI -> getCalleeSavedRegsViaCopy ( Entry -> getParent ( ) ) ; if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI ->


<s> static bool mips_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( mips_abi == ABI_EABI ) { int size ; if ( mode == DImode || mode == DFmode || mode == DQmode || mode == UDQmode || mode == DAmode || mode == UDAmode ) return <NUM_LIT> ; size = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return size == - <NUM_LIT> || size > UNITS_PER_WORD ; } else { return targetm . calls . must_pass_in_stack ( mode


<s> bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( MaxAlign <= TargetAlign && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = LP64 ? G8RC : GPRC ; unsigned Reg ; if ( EnableRegisterScavenging ) Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; else Reg = <STR_LIT> ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { if ( EnableRegisterScavenging ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg


<s> addPass ( create<ISA_LIT>LongBranchPass ( ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> return std :: is_sorted ( ArgLocs . begin ( ) , ArgLocs . end ( ) , [ ] ( const CCValAssign & A , const CCValAssign & B ) -> bool { return A . getValNo ( ) < B . getValNo ( ) ; } )


<s> if ( ! extractConstantMask ( C , <NUM_LIT> , UndefElts , RawMask ) ) return ; unsigned NumElts = RawMask . size ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Element = RawMask [ i ] ; if ( Element & ( <NUM_LIT> << <NUM_LIT> ) ) ShuffleMask . push_back ( SM_SentinelZero ) ; else { unsigned Base = i & ~ <NUM_LIT> ; int Index = Base + ( Element &


<s> return ( __m512 ) __builtin_ia32_rsqrt14ps512_mask ( ( __v16sf ) __A , (

__v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned )


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand ::


<s> if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF .

getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;


<s> const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( ! Subtarget . hasP8Vector ( ) ) return false ; bool IsLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ShuffleKind == <NUM_LIT> ) { if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i

* <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ;


<s> OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE (


<s> rtx t1 = gen_reg_rtx ( V4HImode ) ; int i ; elt = convert_modes ( SImode , HImode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) ,


<s> if ( Kind != k_Register || Reg . Kind != RegKind :: SVEPredicateVector ) return DiagnosticPredicateTy


<s> if ( Data != std :: end ( IntrinsicsWithChain ) &&


<< SH_FE_EXCEPT_SHIFT ) | SH_FE_ALL_EXCEPT ) ) ;


<s> return ( ( vec_double2 ) ( si_dfnms ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c


<s> if ( isCPEntryInRange ( UserMI , UserOffset , CPE . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPE . CPI << <STR_LIT> ) ; U . CPEMI = CPE . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPE . CPI ) ; break ; } CPE .


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR64Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! isFP64 ( ) )


<s> if ( AbsoluteBase && AbsoluteIndex ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( AbsoluteBase ) { AddrReg = IndexReg . getReg ( ) ; } else if ( AbsoluteIndex ) { assert ( ! BaseReg . getReg ( ) && <STR_LIT> ) ; assert ( Scale . getImm ( ) == <NUM_LIT> ) ; AddrReg = <NUM_LIT> ; } else { if ( ! BaseReg . getReg ( ) ) { BaseReg . setReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; AddrReg = IndexReg . getReg ( ) ; } else if ( ! FlagUseZeroBasedSandbox ) { assert ( ! IndexReg . getReg ( ) && <STR_LIT> ) ; IndexReg . setReg ( BaseReg . getReg ( ) ) ; Scale . setImm ( <NUM_LIT> ) ; BaseReg . setReg ( <STR_LIT> ) ; AddrReg = IndexReg . getReg ( ) ; } else { llvm_unreachable ( <STR_LIT> )


<s> bool isShlImm16 ( ) const { return isShlFixedWidth ( <NUM_LIT>


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , bool Is64Bit , uint8_t


<s> return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT>

|| IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzmsk_u64 ( unsigned long long __X ) { return ~ __X & ( __X


<s> if ( ( FLOAT128_IEEE_P ( mode ) && ieee128_float_type_node == long_double_type_node ) || ( FLOAT128_IBM_P ( mode ) && ibm128_float_type_node ==

long_double_type_node ) ) return COMPLEX_MODE_P ( mode ) ? E_TCmode : E_TFmode ;


<s> return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ; return true ; } MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT .


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getScalarSizeInBits ( ) ; return ( Index * ElSize ) %


<s> } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( OpImmCode , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; } else { unsigned ImmReg = DstReg ; if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg = ATReg ; } if ( loadImmediate ( ImmValue , ImmReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out , STI


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( ) { MCStreamer :: EmitWinEHHandlerData (


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT ,


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_ssaddv4hi3 ( ( v4hi )


<s> case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasDQI ( ) ) return false ; const uint16_t * table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableCustomAVX512LogicInstrs ) ; assert ( table && <STR_LIT> ) ; if ( Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; MI . setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : if ( Domain != dom && Domain != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { commuteInstruction ( MI , false ) ; return true ; } if ( Opcode == <STR_LIT> ) return true ; break ; case <STR_LIT> : { if ( Domain


<s> return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI -> setDesc ( get (


<s> unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset &&

BBInfo [ i ] . KnownBits == KnownBits ) break ;


<s> bool isADDR128 ( ) const { return false


<s> FunctionPass * llvm :: create<ISA_LIT>EmitGPRestorePass ( <ISA_LIT>TargetMachine & tm ) { return new Inserter


<s> bool <ISA_LIT>DAGToDAGISel :: SelectShiftedRegister ( SDValue N , bool AllowROR , SDValue & Reg , SDValue & Shift ) { <STR_LIT> ShType = getShiftTypeForNode ( N ) ; if ( ShType == <STR_LIT> ) return false ; if ( ! AllowROR && ShType == <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { unsigned BitSize = N . getValueSizeInBits ( ) ; unsigned Val = RHS -> getZExtValue ( ) & ( BitSize - <NUM_LIT> ) ; unsigned ShVal = <STR_LIT> ( ShType , Val ) ; Reg = N . getOperand (


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y


<s> if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . isMIPS32 ( ) )


<s> unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , NumBytes ) ; } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( hasFP ( MF ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , FramePtr , - NumBytes , TII , * this , dl ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( )


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> fprintf ( asm_out_file , <STR_LIT> ) ; } for ( i = <NUM_LIT> ; i < NDS32_N_ISR_VECTORS ; i ++ ) { if ( nds32_isr_vectors [ i ] . category == NDS32_ISR_INTERRUPT || nds32_isr_vectors [ i ] . category == NDS32_ISR_EXCEPTION ) { fprintf ( asm_out_file , <STR_LIT> , i ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_isr_jmptbl_section ( i ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_isr_vector_section (


<s> if ( IsSubWord ) BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = MRI . createVirtualRegister ( RC ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal

) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ;


<s> case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ; case V2DImode : gen = gen_aarch64_zip1v2di ;


<s> unsigned NumElems = Mask . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Arg = Mask . getOperand ( i ) ; if ( Arg . getOpcode ( ) != <STR_LIT> ) { unsigned Val = cast < ConstantSDNode > ( Arg )


<s> static inline unsigned getAM6Opc ( bool WB = false ) { return ( int )


<s> <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> ; return Binary ; } Binary |= SBits << <NUM_LIT> ; unsigned Offset = <STR_LIT> ( MO1 . getImm


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t > :: min ( ) ) ; } return false


<s> } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> && <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Tmp ) ; BuildMI ( * MBB , MI , DL , TII -> get

( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ;


<s> emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , <NUM_LIT> ) ; emit_move_insn ( temp , static_chain ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , <NUM_LIT> ) ; emit_move_insn ( reg_fnaddr , XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ) ; emit_move_insn ( temp , reg_fnaddr ) ; emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode ,


addPass ( createThumb2ITBlockPass ( ) ) ;


<s> static SDValue performSignExtendInRegCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned SOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ExtOp = Src -> getOperand ( <NUM_LIT> ) ; auto VT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; ( void ) EltTy ; assert ( ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) && <STR_LIT> ) ; EVT ExtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , ExtOp . getValueType ( ) , ExtOp , DAG . getValueType ( ExtVT ) ) ; return DAG . getNode ( SOpc , DL , N -> getValueType ( <NUM_LIT> ) , Ext ) ; } unsigned NewOpc ; unsigned MemVTOpNum = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case


<s> static SDValue getTestBitOperand ( SDValue Op , unsigned & Bit , bool & Invert , SelectionDAG & DAG ) { if ( ! Op -> hasOneUse ( ) ) return Op ; if ( Op -> getOpcode ( ) == <STR_LIT> && Bit < Op -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; } if ( Op -> getNumOperands ( ) != <NUM_LIT> ) return Op ; auto * C = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return Op ; switch ( Op -> getOpcode ( ) ) { default : return Op ; case <STR_LIT> : if ( ( C -> getZExtValue ( ) >> Bit ) & <NUM_LIT> ) return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; return Op ; case <STR_LIT> : if ( C -> getZExtValue ( ) <= Bit && ( Bit - C -> getZExtValue ( ) ) < Op -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { Bit = Bit - C -> getZExtValue ( ) ; return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; } return Op


<s> createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const Align Alignment = isThumb ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( NewMBB -> getAlignment ( ) < Alignment ) NewMBB -> setAlignment ( Alignment ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . add ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPEAlign (


<s> bool isCondBr ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm (


<s> if ( ! CurFrame ) return ; auto Inst = WinEH :: Instruction ( UnwindCode , nullptr , Reg , Offset ) ; if ( InEpilogCFI ) CurFrame -> EpilogMap [ CurrentEpilog ] . Instructions .


<s> x . l [ <NUM_LIT> ] = l ; return ( x . q


<s> emitDirectiveModuleFP ( ABIFlagsSection . getFpABI (


<s> const Register CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineInstr * CCMI = MRI . getVRegDef ( CondReg ) ; if ( CCMI -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) CCMI = MRI . getVRegDef ( CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( CCMI -> getOpcode ( ) != TargetOpcode :: G_ICMP ) return false ; Register LHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getConstantVRegVal ( RHS , MRI ) ) std :: swap ( RHS , LHS ) ; const auto RHSImm = getConstantVRegVal ( RHS , MRI ) ; if ( ! RHSImm || * RHSImm != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank


<s> void <ISA_LIT>AIXAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! TM . getXCOFFTracebackTable ( ) ) return ; emitTracebackTable (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A1 ) ; SDValue TmpAns = b . OR ( b . AND ( Tmp , A2 ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND ( A1 , b . NOT ( A2 ) ) ) , b . OR ( Tmp , A2 ) ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , TmpAns , b . SRL < <NUM_LIT>


<s> return ( __m128i ) vec_abs ( ( __v16qi


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SrcVT == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( SrcVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( SrcVT , VT ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , VT , Src , CallOptions , SDLoc ( Op ) ) . first ; } if ( VT . isVector ( ) ) { if ( VT == <STR_LIT> && SrcVT == <STR_LIT> ) { MVT ResVT = <STR_LIT> ; MVT TruncVT = <STR_LIT> ; unsigned Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; if ( ! IsSigned && ! Subtarget . hasVLX ( ) ) { ResVT = <STR_LIT> ; TruncVT = <STR_LIT> ; Opc = <STR_LIT> ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDValue Res = DAG . getNode ( Opc , dl , ResVT , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && SrcVT == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && UseSSEReg ) { if ( Subtarget . hasAVX512 ( ) ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , dl


<s> if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; int Size = <NUM_LIT> ; EmitInstruction ( Binary , Size


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset


<s> if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> ,


<s> void addImmThumbSROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Imm = CE -> getValue (


<s> return this -> m_insn_fma_head_map -> put ( node -> get_insn (


<s> return __builtin_loongson_psubh_u ( s ,


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFP<ISA_LIT>v8Base ( ) && ! ST -> hasVFP2Base ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ST -> hasMVEIntegerOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr >


<s> bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> emitRX ( Opcode , Reg0 , MCOperand :: createReg (


<s> if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineHorizontalMinMaxResult ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = scalarizeExtEltFP ( N ,


<s> if ( DAG . getTarget ( ) . Options . UnsafeFPMath ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue V = Op -> getOperand ( <NUM_LIT> ) ; MVT VecIntVT = V . getSimpleValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL


<s> for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) StoreVal |= ByteVal << ( I * <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstant ( StoreVal , DL , <STR_LIT> (

Size * <NUM_LIT> ) ) , Dst , DstPtrInfo , false , false , Align ) ;


<s> int i ; enum calling_abi call_abi ; const int * parm_regs ; if ( TARGET_MPX && BND_REGNO_P ( regno ) ) return true ; if ( ! TARGET_64BIT ) { if ( TARGET_MACHO ) return ( regno < REGPARM_MAX || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ! fixed_regs [ regno ] ) ) ; else return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs =


<s> regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) stack_space_to_deallocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_deallocate += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_deallocate += <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_deallocate += <NUM_LIT> ; if ( ( stack_space_to_deallocate % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , stack_space_to_deallocate ) ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= <NUM_LIT> ; regno ++ ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { if ( offset > <NUM_LIT> ) { mmix_emit_sp_add ( offset ) ; stack_space_to_deallocate -= offset ; offset = <NUM_LIT> ; } emit_move_insn ( gen_rtx_REG ( DImode , regno ) , gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ) ; offset += <NUM_LIT> ; } offset += ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) offset += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) offset += <NUM_LIT> ; if ( frame_pointer_needed ) { if ( offset > <NUM_LIT> ) { mmix_emit_sp_add ( offset ) ; stack_space_to_deallocate -= offset ; offset =


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> void <ISA_LIT>MCExpr :: PrintImpl ( raw_ostream & OS ) const { bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print ( OS ) ; if ( closeParen ) OS <<


<s> bool <ISA_LIT>PreLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value )


<s> inline int vec_all_le ( vector float a1 , vector


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) || TheTriple . isWindowsCoreCLREnvironment


<s> return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_DTPREL_LO , E , Ctx ) ; case AsmToken :: PercentGot : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT , E , Ctx ) ; case AsmToken :: PercentGot_Disp : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT_DISP , E , Ctx ) ; case AsmToken :: PercentGot_Hi : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT_HI16 , E , Ctx ) ; case AsmToken :: PercentGot_Lo : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT_LO16 , E , Ctx ) ; case AsmToken :: PercentGot_Ofst : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT_OFST , E , Ctx ) ; case AsmToken :: PercentGot_Page : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOT_PAGE , E , Ctx ) ; case AsmToken :: PercentGottprel : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GOTTPREL , E , Ctx ) ; case AsmToken :: PercentGp_Rel : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_GPREL , E , Ctx ) ; case AsmToken :: PercentCapTab_Rel : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_CAPTABLEREL , E , Ctx ) ; case AsmToken :: PercentHi : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , E , Ctx ) ; case AsmToken :: PercentHigher : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHER , E , Ctx ) ; case AsmToken :: PercentHighest : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHEST ,


<s> } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ; if ( ! SVT . isVector ( ) || SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) * <NUM_LIT> ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc dl ( N ) ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( idx ) { SDValue HalfIdx = DAG . getConstant ( NumElements , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Source , HalfIdx


<s> return getSubtargetImpl ( ) -> getSelectionDAGInfo (


<s> } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( TARGET_RELOCATABLE && ! TARGET_SECURE_PLT && ( get_pool_size ( ) != <NUM_LIT> || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , buf ) ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( DEFAULT_ABI == ABI_AIX


<s> static const TargetRegisterClass * getRegClassForTypeOnBank ( LLT Ty , const RegisterBank & RB ) { if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <=


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOperand ( OperandVector * Operands , StringRef Mnemonic ) { OperandMatchResultTy Result ; if ( Result == MatchOperand_Success ) return Result ; if ( Result == MatchOperand_ParseFail ) { Parser . eatToEndOfStatement ( ) ; return Result ; } std :: unique_ptr < <ISA_LIT>Operand > Op =


<s> } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CallerCC , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( )


<s> unsigned Opcode = MI . getOpcode ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) .


<s> delete static_cast < aarch64_vector_costs * >


<s> const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; const RegisterBank & DstRB = * RBI . getRegBank ( Dst , MRI , TRI ) ; if ( EltRB != DstRB ) return false ; if ( any_of ( make_range ( I . operands_begin ( ) + <NUM_LIT> , I . operands_end ( ) ) , [ & MRI ] ( const MachineOperand & Op ) { return ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , Op . getReg ( ) , MRI ) ; } ) ) return false


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i ] . Tag == Attribute ) return & Contents [ i ] ; return


<s> return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : emit_insn ( gen_move_from_CR_ov_bit ( target , scratch ) ) ; return target ; case <NUM_LIT> : code = EQ ; break ; case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; default : error ( <STR_LIT> ) ; return const0_rtx ; } tmp = gen_rtx_fmt_ee ( code , SImode


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MBBSymbolExpr

) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ;