<s> static bool FPCCTo<ISA_LIT>CC ( <STR_LIT> CC , <STR_LIT> & CondCode , <STR_LIT> & CondCode2 ) { bool Invert = false ; CondCode2 = <STR_LIT> ; switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT>


<s> bool <ISA_LIT>16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MF )


<s> Value = <STR_LIT> ( Value ) ; MovTy = isWide ? <STR_LIT> : <STR_LIT> ; } if ( isAdvSIMDModImm ) { SDLoc dl ( Op ) ; SDValue Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } } return SDValue ( )


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( CoprocReg ) ; Op -> Cop . Val = CopVal ; Op -> StartLoc = S


<s> bool hasCrypto ( ) const { return HasCrypto


<s> rtx sh_movt_set_dest ( const rtx_insn * i ) { if ( i == NULL ) return NULL ; const_rtx p = PATTERN ( i ) ; return GET_CODE ( p ) == SET && arith_reg_dest ( XEXP ( p , <NUM_LIT> ) , SImode ) && t_reg_operand ( XEXP ( p , <NUM_LIT> ) , VOIDmode ) ? XEXP


<s> MFI -> setFrameAddressIsTaken ( true ) ; SDValue Chain = getFLUSHW ( Op , DAG ) ; RetAddr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , VT ) ; for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetAddr , DAG . getIntPtrConstant ( (

i == depth - <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ;


<s> default : return MCDisassembler :: Fail ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; } Inst . addOperand ( MCOperand :: CreateImm


<s> } else { assert ( AFI -> getTailCallReservedStack ( ) == <NUM_LIT> && <STR_LIT> ) ; const unsigned VarArgsArea = AFI -> getVarArgsGPRSize ( ) ; const unsigned UnwindHelpObject = ( MF . hasEHFunclets (


<s> bool allowMixed16_32 ( ) const { return in<ISA_LIT>16ModeDefault ( ) |


<s> MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VLdDup ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo )


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) { markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( hasBasePointer ( MF ) ) { markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> static unsigned getSVEGatherScatterOverhead ( unsigned Opcode ) { return Opcode == Instruction :: Load ?

SVEGatherOverhead : SVEScatterOverhead ;


<s> if ( df_regs_ever_live_p ( <NUM_LIT> ) || profile_flag ) return <NUM_LIT> ; if ( cfun -> machine -> initialized ) return

cfun -> machine -> total_size == <NUM_LIT> ;


<s> break ; default : gcc_unreachable ( ) ; } break ; case FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_SIGN_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case DImode : func = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case UNSIGNED_FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_ZERO_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case DImode : func = <STR_LIT> ; break ; default : gcc_unreachable ( )


<s> Ty * PCRelCand = dyn_cast < Ty > ( N ) ; return PCRelCand && ( PCRelCand -> getTargetFlags ( )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) ||

isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ;


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot


<s> if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || isPositionIndependent ( ) ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } int Index = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; uint64_t Element = RawMask [ i ] ; if ( ElSize == <NUM_LIT> ) Index += (


<s> Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . SimpleTy ) { default : return nullptr ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I64 ] ; break ; } assert ( Opc != <NUM_LIT> && <STR_LIT> ) ; SDValue Ret ; if ( isUnOp ) { SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Val , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops


<s> return __builtin_mve_vcaddq_rot270_uv16qi ( __a ,


<s> static const unsigned FPOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; const TargetRegisterClass * RC ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; bool IsRet64Bit = RetVT == <STR_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = FPOpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = FPOpcTable [ Idx ] [


<s> bool <ISA_LIT>TargetLowering :: DoesCalleeRestoreStack ( CallingConv :: ID CallCC , bool TailCallOpt ) const { return ( CallCC == CallingConv :: Fast && TailCallOpt ) || CallCC ==

CallingConv :: Tail || CallCC == CallingConv :: SwiftTail ;


<s> static const char * GetFPUName ( unsigned ID ) { switch ( ID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; } return nullptr


<s> MemObjSize *= <NUM_LIT> << ( CD8V & <NUM_LIT> ) ; } else { bool EVEX_b = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; if ( ! EVEX_b ) { unsigned EVEX_LL = ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVEX_LL += ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; assert ( EVEX_LL < <NUM_LIT> && <STR_LIT> ) ; unsigned NumElems = ( <NUM_LIT> << ( EVEX_LL + <NUM_LIT> ) ) / MemObjSize ; NumElems /= <NUM_LIT> << ( CD8V & <NUM_LIT> ) ; MemObjSize *= NumElems ; } } unsigned MemObjMask = MemObjSize - <NUM_LIT> ; assert ( ( MemObjSize & MemObjMask ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value & MemObjMask ) return false ; Value /= MemObjSize ; bool Ret = ( Value == ( signed char ) Value ) ; if ( Ret )


<s> break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: STATEPOINT : NumBytes = StatepointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( NumBytes == <NUM_LIT> ) NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case


<s> static const <ISA_LIT>InstrFMA3Group * getFMA3Group ( unsigned Opcode ) { initGroupsOnce ( ) ; const <ISA_LIT>InstrFMA3Info * FMA3Info = get<ISA_LIT>InstrFMA3Info ( ) ; auto I = FMA3Info -> OpcodeToGroup . find ( Opcode ) ; if ( I == FMA3Info -> OpcodeToGroup . end ( ) ) return nullptr ; return I ->


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( - ValueofRHS ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , LHS , DAG . getValueType ( <STR_LIT> ) ) ; Cmp = emitComparison ( SExt , DAG . getConstant ( ValueofRHS , RHS . getValueType ( ) ) , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) ; return Cmp ; } } } } Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC , <STR_LIT>


<s> unsigned Res = get<ISA_LIT>SubSuperRegisterOrZero ( Reg , VT , High ) ; if ( Res == <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; return


<s> setRegionSize ( <NUM_LIT> ) ; return StartOffset ; } for ( std :: vector < unsigned > :: iterator i = CSRs . begin ( ) ; i != CSRs . end ( ) ; ) { if ( ! MRI -> isPhysRegModified ( * i ) ) i = CSRs . erase ( i ) ; else ++ i ; } unsigned Count = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> getObjectRegion ( i ) == this ) { unsigned ObjSize = MFI -> getObjectSize ( i ) ; unsigned Offset = StartOffset + Count ; unsigned Alignment = MFI -> getObjectAlignment ( i ) ; unsigned Padding =


<s> if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_vsx_dform_quad ( mode ) )


<s> return ( isTargetELF ( ) && ! isTargetNaCl ( ) ) || TM . getRelocationModel ( ) == Reloc


<s> int regno ; int fp_sp_offset = ( get_frame_size ( ) + crtl -> outgoing_args_size + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( fromreg == MMIX_ARG_POINTER_REGNUM && toreg == MMIX_FRAME_POINTER_REGNUM ) return <NUM_LIT> ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <=


<s> SDValue Imm = Node -> getOperand ( <NUM_LIT> ) ; const ConstantInt * Val = cast < ConstantSDNode > ( Imm ) -> getConstantIntValue ( ) ; Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && tryFoldLoad ( Node , N2 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , N2 . getOperand ( <NUM_LIT> ) , InFlag } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; InFlag = SDValue ( CNode , <NUM_LIT> ) ; ReplaceUses ( N2 . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; CurDAG -> setNodeMemRefs ( CNode , { cast < LoadSDNode > ( N2 ) -> getMemOperand ( ) } ) ; return CNode


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token , Parser ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size (


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _MM_SET_EXCEPTION_STATE (


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; TLI = TLIP ? & TLIP -> getTLI ( * L -> getHeader ( ) -> getParent ( ) ) : nullptr ; DL = & L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ; Setup = FindLoopIterations ( Preheader -> getSinglePredecessor ( ) ) ; if ( ! Setup ) return false ; } IntrinsicInst * Decrement = nullptr ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( IsDecrement ( I ) ) { Decrement = cast < IntrinsicInst > ( & I ) ; break ; } } } if ( ! Decrement ) return false ; ClonedVCTPInExitBlock = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * L << * Setup << <STR_LIT> << * Decrement << <STR_LIT> ) ; if ( TryConvert ( Setup -> getArgOperand ( <NUM_LIT> ) ) ) { if ( ClonedVCTPInExitBlock ) RematerializeIterCount ( ) ; return true ; } return false


<s> return ( unsigned long long ) __builtin_sssubv4hi3 ( ( v4hi )


<s> rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x ,


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const


<s> case GT : return UNSPEC_COND_GT ; case LE : return UNSPEC_COND_LE ; case GE : return UNSPEC_COND_GE ; case LTU : return UNSPEC_COND_LO ; case GTU


<s> if ( ( Subtarget . hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget . hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc =


<s> MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> isLoadFoldBarrier ( ) ) return nullptr ; return DefMI


<s> else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < <NUM_LIT> && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < <NUM_LIT> && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true , false ) ) regno = BX_REG ; else if ( ! ( regparm == <NUM_LIT> && static_chain_p ) && ix86_save_reg ( SI_REG , true , false ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true , false ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ?


<s> Inst . addOperand ( MCOperand :: createImm ( CE


<s> unsigned SuperReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasDirectMove


<s> static void moveBelowOrigChain ( SelectionDAG * CurDAG , SDValue Load , SDValue Call , SDValue OrigChain ) { SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back (


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo


<s> static DecodeStatus DecodeDSPRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPR32RegisterClass ( Inst , RegNo , Address , Decoder


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ; return false


<s> bool isGlobalRegFI ( int FI ) const { return GlobalRegFI && ( FI ==


<s> fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case <NUM_LIT> : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case <NUM_LIT> : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'L' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case <NUM_LIT>


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( CC == <STR_LIT> && getSTI ( ) . getFeatureBits ( ) [


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize - TFI . getOffsetOfLocalArea ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) &&


<s> if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++


<s> lowerLongBranchADDiu ( const MachineInstr * MI , MCInst & OutMI , int Opcode , MCSymbolRefExpr :: VariantKind Kind ) const { OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; } OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand (


<s> ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( )


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> static const char * mips_get_compress_on_name ( unsigned int flags


<s>
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
bool
CanEliminateFrame
=
NumRegsSpilled
==
<NUM_LIT>
;
unsigned
CFSize
=
MFI
.
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
NumRegsSpilled
;
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
(
CFSize
>
EstimatedStackSizeLimit
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPRPaired
;
NumRegsSpilled
=
SavedRegs
.


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != <STR_LIT> )


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT>

) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , EFLAGS ) ;


<s> MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> EmitInstruction ( CallInst , getSubtargetInfo ( ) ) ; } auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel )


<s> MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead =


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout


<s> const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsLR = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ! IsARPop && ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC && ListContainsLR ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( inITBlock ( ) && ! lastInITBlock ( ) && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; return


<s> const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , basereg , <NUM_LIT> , <NUM_LIT> , Loc ,


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef


<s> static int write_header_file ( void ) { write_autogenerated_header ( header_file ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; write_decls ( ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; return


<s> else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; unsigned MovRIOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned AddSubRROpc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; if ( Reg ) { BuildMI ( MBB , MBBI , DL , TII . get ( MovRIOpc ) , Reg ) . addImm ( Offset ) . setMIFlag ( Flag ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AddSubRROpc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } else if ( Offset > <NUM_LIT> * Chunk ) { assert ( Is64Bit && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Rax , RegState :: Kill ) . setMIFlag ( Flag ) ; if ( isSub ) Offset = - ( Offset - SlotSize ) ; else Offset = Offset + SlotSize ; BuildMI ( MBB , MBBI , DL , TII . get ( MovRIOpc ) , Rax ) . addImm ( Offset ) . setMIFlag ( Flag ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Rax ) . addReg ( Rax ) . addReg ( StackPtr ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Rax ) . addReg ( Rax ) , StackPtr , false , <NUM_LIT> ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , StackPtr ) , StackPtr , false , <NUM_LIT> ) ; return ; } } while ( Offset ) { uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == SlotSize ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) . setMIFlag ( Flag ) ; Offset -= ThisVal ; continue ; } } BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) . setMIFlag ( Flag ) ; Offset -= ThisVal


<s> AU . setPreservesAll ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> int getStackPointerRegister ( ) override final { return <STR_LIT>


<s> return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto Rz = Operands . back ( ) -> getReg ( ) ; Operands . pop_back (


<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field =


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF .


<s> void <ISA_LIT>AsmPrinter :: LowerSTACKMAP ( MCStreamer & OutStreamer , StackMaps & SM , const MachineInstr & MI ) { unsigned NumNOPBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; SM . recordStackMap ( MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ++ MII ; NumNOPBytes -= <NUM_LIT>


<s> if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx


<s> SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; NotSrc = DAG . getBitcast ( SrcVT , NotSrc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , NotSrc ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; KnownBits KnownRHS = DAG . computeKnownBits ( RHS ) ; if ( KnownRHS . isConstant ( ) && KnownRHS . getConstant ( ) . isPowerOf2


<s> case AND : return <STR_LIT> ; case OR : return <STR_LIT> ; case XOR : return <STR_LIT> ; case SHL : return <STR_LIT> ; case SRL : return <STR_LIT>


<s> } gcc_assert ( param_string_cst ) ; if ( fn_code == IX86_BUILTIN_CPU_IS ) { tree ref ; tree field ; tree final ; unsigned int field_val = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < num_arch_names ; i ++ ) if ( processor_alias_table [ i ] . model != <NUM_LIT> && strcmp ( processor_alias_table [ i ] . name , TREE_STRING_POINTER ( param_string_cst ) ) == <NUM_LIT> ) break ; if ( i == num_arch_names ) { error ( <STR_LIT> , TREE_STRING_POINTER ( param_string_cst ) ) ; return integer_zero_node ; } field = TYPE_FIELDS ( ix86_cpu_model_type_node ) ; field_val = processor_alias_table [ i ] . model ; if ( field_val > M_CPU_TYPE_START && field_val < M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( field ) ; field_val -= M_CPU_TYPE_START ; } if ( field_val > M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( DECL_CHAIN ( field ) ) ; field_val -= M_CPU_SUBTYPE_START ; } ref = build3 ( COMPONENT_REF , TREE_TYPE ( field ) , ix86_cpu_model_var , field , NULL_TREE ) ; final = build2 ( EQ_EXPR , unsigned_type_node , ref , build_int_cstu ( unsigned_type_node , field_val ) ) ; return build1 ( NOP_EXPR , integer_type_node , final ) ; } else if ( fn_code == IX86_BUILTIN_CPU_SUPPORTS ) { tree ref ; tree array_elt ; tree field ; tree final ; unsigned int field_val = <NUM_LIT> ; unsigned int NUM_ISA_NAMES = ARRAY_SIZE ( isa_names_table ) ; for ( i = <NUM_LIT> ; i < NUM_ISA_NAMES ; i ++ ) if ( strcmp ( isa_names_table [ i ] . name , TREE_STRING_POINTER ( param_string_cst ) ) == <NUM_LIT> ) break ; if ( i == NUM_ISA_NAMES ) { error ( <STR_LIT> , TREE_STRING_POINTER ( param_string_cst ) ) ; return integer_zero_node ; } unsigned feature = isa_names_table [ i ] . feature ; if ( feature >= INT_TYPE_SIZE ) { if ( ix86_cpu_features2_var == nullptr ) { tree index_type = build_index_type ( size_int ( SIZE_OF_CPU_FEATURES ) ) ; ix86_cpu_features2_type_node = build_array_type ( unsigned_type_node , index_type ) ; ix86_cpu_features2_var = make_var_decl ( ix86_cpu_features2_type_node , <STR_LIT> ) ; varpool_node :: add ( ix86_cpu_features2_var ) ; } feature -= INT_TYPE_SIZE ; tree index = size_int ( feature / INT_TYPE_SIZE ) ; feature = feature % INT_TYPE_SIZE ; array_elt = build4 ( ARRAY_REF , unsigned_type_node , ix86_cpu_features2_var , index , NULL_TREE , NULL_TREE ) ; } else { field = TYPE_FIELDS ( ix86_cpu_model_type_node ) ; while ( DECL_CHAIN ( field ) ) field = DECL_CHAIN ( field ) ; ref = build3 ( COMPONENT_REF , TREE_TYPE ( field ) , ix86_cpu_model_var , field , NULL_TREE ) ; array_elt = build4 ( ARRAY_REF , unsigned_type_node , ref , integer_zero_node , NULL_TREE , NULL_TREE ) ; } field_val = <NUM_LIT> << feature ; final = build2 ( BIT_AND_EXPR , unsigned_type_node , array_elt , build_int_cstu ( unsigned_type_node , field_val ) ) ; if ( feature == INT_TYPE_SIZE - <NUM_LIT> ) return build2 ( NE_EXPR , integer_type_node , final , build_int_cst (


<s> inline const MachineInstrBuilder & addLeaOffset ( const MachineInstrBuilder & MIB , int Offset ) { return MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) .


<s> bool <ISA_LIT>A57FPLoadBalancing :: runOnBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: set < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC


<s> bool ix86_lea_for_add_ok ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; unsigned int regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ; unsigned int regno2 = true_regnum ( operands [ <NUM_LIT> ] ) ; if ( regno0 != regno1 && regno0 != regno2 ) return true ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p (


<s> if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64


<s> case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT> : emitVFPLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitVFPLoadStoreMultipleInstruction (


<s> addPass ( create<ISA_LIT>PreEmitPeepholePass ( ) ) ; addPass ( create<ISA_LIT>ExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>EarlyReturnPass ( ) ) ; addPass ( create<ISA_LIT>BranchSelectionPass ( ) )


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( create<ISA_LIT>TLSDynamicCallPass


<s> return TARGET_32BIT ? arm_arm_address_cost ( x


<s> } } else if ( Op . isExpr ( ) ) { const MCExpr * Expr = Op . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * SR = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( SR -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } else if ( ! isEvaluated ( Expr ) ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } } } } if ( needsExpansion ( Inst ) ) expandInstruction ( Inst , IDLoc , Instructions ) ; else Instructions . push_back ( Inst


<s> if ( itype == NT_MACRO ) { do ( void ) cpp_get_token ( pfile ) ; while ( -- idx > <NUM_LIT> ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; expand_bool_pixel = __pixel_keyword ; rid_code = RID_MAX ; } else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; expand_bool_pixel = __bool_keyword ; rid_code = RID_MAX ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT || ( rid_code == RID_DOUBLE && TARGET_VSX ) || ( rid_code == rid_int128 ( ) && TARGET_VADDUQM ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; } } else if ( TARGET_VADDUQM && ( ident == C_CPP_HASHNODE ( __int128_type ) || ident == C_CPP_HASHNODE ( __uint128_type ) ) )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst ,


<s> return __builtin_aarch64_reduc_smax_scal_v4hi (


<s> EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> &&


<s> spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LowGPR = <NUM_LIT> ; unsigned HighGPR = <STR_LIT> ; unsigned StartOffset = - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; assert ( Offset && <STR_LIT> ) ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset >


<s> static DecodeStatus DecodeCFRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler ::


<s> bool <ISA_LIT>InstructionSelector :: tryOptCompareBranchFedByICmp ( MachineInstr & I , MachineInstr & ICmp , MachineIRBuilder & MIB ) const { assert ( ICmp . getOpcode ( ) == TargetOpcode :: G_ICMP ) ; assert ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) ; if ( ! ProduceNonFlagSettingCondBr ) return false ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( ICmp . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; MachineInstr * AndInst = getOpcodeDef ( TargetOpcode :: G_AND , LHS , MRI ) ; if ( VRegAndVal && ! AndInst ) { int64_t C = VRegAndVal -> Value . getSExtValue ( ) ; if ( C == - <NUM_LIT> && Pred == CmpInst :: ICMP_SGT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } if ( C == <NUM_LIT> && Pred == CmpInst :: ICMP_SLT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , true , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } } if ( ICmpInst :: isEquality ( Pred ) ) { if ( ! VRegAndVal ) { std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; AndInst = getOpcodeDef ( TargetOpcode :: G_AND , LHS , MRI ) ; } if ( VRegAndVal && VRegAndVal -> Value == <NUM_LIT> ) { if ( AndInst && tryOptAndIntoCompareBranch ( * AndInst , Pred == CmpInst :: ICMP_NE , DestMBB , MIB ) ) { I . eraseFromParent ( ) ; return true ; } auto LHSTy = MRI . getType ( LHS


<s> FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS ) return const0_rtx ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; op [ nopnds ] = expand_normal ( arg ) ; if ( ! insn_op -> predicate ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = nonvoid ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++


<s> rtx aarch64_endian_lane_rtx ( machine_mode mode , unsigned int n ) { return gen_int_mode ( ENDIAN_LANE_N ( GET_MODE_NUNITS ( mode ) , n


<s> return ( int32_t ) __builtin_aarch64_sqshl_nsi (


<s> if ( DstElVT . getSizeInBits ( ) < <NUM_LIT> || DstElVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( SrcVT . is512BitVector ( ) || Subtarget . hasVLX ( ) ) return SrcElVT . getSizeInBits ( ) >=


<s> static DecodeStatus DecodeDPairRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> return isUImm < <NUM_LIT> , <NUM_LIT>


<s> bool hasLowDefLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx ) const override { return


<s> if ( ! TARGET_NEON_FP16 ) return GENERAL_REGS ; if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , <NUM_LIT> , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc


<s> return true ; } if ( Opcode == <STR_LIT> ) { const GlobalValue * Global = MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addGlobalAddress ( Global ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } return false


<s> if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && ( ( OI . getOperand

( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;


<s> if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; MVT ShuffleVT = FloatDomain ? <STR_LIT> : <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } if ( ! FloatDomain && ( Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ) { bool Lo = Mask [ <NUM_LIT> ] == <NUM_LIT> ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; MVT ShuffleVT ; switch ( Mask . size ( ) ) { case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; } ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB ) && Subtarget -> hasSSSE3 ( ) ) { SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int Ratio = <NUM_LIT> / Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ <NUM_LIT> ] ) { if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands


<s> ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult . first


<s> bool DestIsHigh = isHighReg ( DestReg ) ; bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get ( LowOpcodeK ) ) ; else { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . getOperand ( <NUM_LIT> )


<s> assert ( Subtarget -> isTargetDarwin ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , NULL ) ; const uint64_t ByteSize = TLI . getDataLayout ( ) -> getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = TLI . getDataLayout ( ) -> getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SDValue SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_ADD , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SUB , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_MUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FADD , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSUB , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FMUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FDIV , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return MSA2OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSQRT , MIRBuilder , ST ) ; case <STR_LIT> : return MSA2OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSQRT , MIRBuilder , ST ) ; default : break ; } return true


<s> unsigned ShiftBits = countLeadingZeros ( Mask ) ; if ( RHSV && ( RHSV > <NUM_LIT> || ( RHSV << ShiftBits ) <= <NUM_LIT> ) ) { SDValue ShiftAmt = DAG . getConstant ( ShiftBits , dl , <STR_LIT> ) ; LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , ShiftAmt ) ; RHS = DAG . getConstant ( RHSV << ShiftBits , dl , <STR_LIT> ) ; } } } if ( Subtarget -> isThumb1Only ( ) && LHS -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) == <NUM_LIT> && CC == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) < <NUM_LIT> ) { unsigned ShiftAmt = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) + <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ShiftAmt , dl , <STR_LIT> ) ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Shift . getValue ( <NUM_LIT> ) , SDValue ( ) ) ; <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return Chain . getValue ( <NUM_LIT> ) ; } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( isNullConstant ( RHS ) ) { switch ( CondCode ) { default :


<s> SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT>


<s> if ( -- CPE -> RefCount == <NUM_LIT> ) { RemoveDeadCPEMI ( CPEMI ) ; CPE -> CPEMI


<s> unsigned Binary = <NUM_LIT> ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT>


<s> const AsmToken & Tok = Parser . getTok ( ) ; int64_t OrigDispVal , DotDispVal ; if ( const MCConstantExpr * OrigDisp = dyn_cast < MCConstantExpr > ( Disp ) ) OrigDispVal = OrigDisp -> getValue ( ) ; else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 ; break ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = AsmPrinter . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_MCSymbol : Symbol = MO . getMCSymbol ( ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: createExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: create (


<s> __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi


<s> loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex ,


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( RetrySwapVal ) . addReg ( NegBitShift ) . addImm ( - BitSize ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , RetryOldVal ) . addReg ( OldVal ) . addReg ( StoreVal


<s> if ( tls_unspec_mentioned_p ( x ) ) return true ; if ( csky_symbol_mentioned_p ( x ) || csky_label_mentioned_p (


<s> using namespace TargetOpcode ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) ; computeTables (


<s> if ( ! VR || TargetRegisterInfo :: isPhysicalRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode >


<s> ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] = <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Shuffle ) ; } else { V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getConstant ( V2Index * EltVT . getSizeInBits ( ) / <NUM_LIT> , DL , DAG . getTargetLoweringInfo ( ) . getScalarShiftAmountTy ( <STR_LIT> ) ) ) ; V2 = DAG . getBitcast ( VT , V2 ) ; } } return V2


<s> f = ggc_alloc_cleared ( sizeof ( struct machine_function


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; } return


<s> StackOffset <ISA_LIT>FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return StackOffset :: getFixed ( getSEHFrameIndexOffset ( MF ,


<s> bool enableLongBranchPass ( ) const { return hasStandardEncoding ( ) || inMicro<ISA_LIT>Mode ( ) || allowMixed16_32


<s> unsigned Bytes = Arg . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI -> isFixedObjectIndex (


<s> const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getWindowsStackProbePreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Callee , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return


<s> MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs (


<s> SDValue Lo = DAG . getBlockAddress ( BA , <STR_LIT> , <NUM_LIT> , true , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi


<s> if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) { markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( hasBasePointer ( MF )


<s> SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool

( ) , <STR_LIT> , false , false , <NUM_LIT> ) ;


<s> if ( GET_CODE ( reg1 ) != REG ) return <NUM_LIT> ; const int regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; const int regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return <NUM_LIT> ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return <NUM_LIT> ; } return <NUM_LIT>


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret ; Ret +=


<s> MachineInstr * FixupBWInstPass :: tryReplaceCopy ( MachineInstr * MI ) const { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; auto & OldDest = MI -> getOperand ( <NUM_LIT> ) ; auto & OldSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; unsigned NewSrcReg = get<ISA_LIT>SubSuperRegister ( OldSrc . getReg ( ) , <NUM_LIT> ) ; auto * TRI = & TII -> getRegisterInfo ( ) ; if ( TRI -> getSubRegIndex ( NewSrcReg , OldSrc . getReg ( ) ) != TRI -> getSubRegIndex ( NewDestReg , OldDest . getReg ( ) ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewDestReg ) . addReg ( NewSrcReg , RegState :: Undef ) . addReg ( OldSrc . getReg ( ) , RegState :: Implicit ) ; for ( auto & Op : MI -> implicit_operands ( ) ) if ( Op . getReg ( ) != ( Op . isDef ( ) ? NewDestReg : NewSrcReg ) ) MIB . add ( Op ) ; return MIB


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler (


<s> void <ISA_LIT>AnalyzeImmediate :: GetShortestSeq ( InstSeqLs & SeqLs , InstSeq & Insts ) { <STR_LIT> ShortestSeq = SeqLs . end ( ) ; unsigned ShortestLength = <NUM_LIT> ; for ( <STR_LIT> S = SeqLs . begin ( ) ; S != SeqLs . end ( ) ; ++ S ) { ReplaceADDiuSHLWithLUi ( * S ) ; assert ( S -> size ( )


<s> unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned ShifterVal = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned ImmVal = Imm & <NUM_LIT> ; if ( ShifterVal != <NUM_LIT> && ShifterVal != <NUM_LIT> ) return Fail ; if ( Datasize ) { if ( Rd == <NUM_LIT> && ! S ) DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; } else { if ( Rd == <NUM_LIT> && ! S ) DecodeGPR32spRegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32spRegisterClass ( Inst , Rn , Addr ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTarget26OpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) )


<s> bool enableWritePrefetching ( ) const


<s> if ( op1 == CONST0_RTX ( SFmode ) ) { if ( GP_REG_P ( regno0 ) ) ret = <STR_LIT> ; } else { delay = DELAY_LOAD ; ret = <STR_LIT> ; } } else if ( code1 == LABEL_REF ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == SYMBOL_REF || code1 == CONST ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == PLUS ) { rtx add_op0 = XEXP ( op1 , <NUM_LIT> ) ; rtx add_op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST_INT ) add_op0 = XEXP ( op1 , <NUM_LIT> ) , add_op1 = XEXP ( op1 , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = add_op0 ; operands [ <NUM_LIT> ] = add_op1 ; ret = <STR_LIT> ; } else if ( code1 == HIGH ) { operands [ <NUM_LIT> ] = XEXP ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } } else if ( code0 == MEM ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op0 , <NUM_LIT> ) ; if ( code1 == REG ) { int regno1 = REGNO ( op1 ) + subreg_offset1 ; if ( GP_REG_P ( regno1 ) ) { switch ( mode ) { case E_SFmode : ret = <STR_LIT> ; break ; case E_SImode : ret = <STR_LIT> ; break ; case E_HImode : ret = <STR_LIT> ; break ; case E_QImode : ret = <STR_LIT> ; break ; default : break ; } } } else if ( code1 == CONST_INT && INTVAL ( op1 ) == <NUM_LIT> ) { switch ( mode ) { case E_SFmode : ret = <STR_LIT> ; break ; case E_SImode : ret = <STR_LIT> ; break ; case E_HImode : ret = <STR_LIT> ; break ; case E_QImode : ret = <STR_LIT> ; break ; default : break ; } } else if ( code1 == CONST_DOUBLE && op1 == CONST0_RTX ( mode ) ) { switch ( mode ) { case E_SFmode : ret = <STR_LIT> ; break ; case E_SImode : ret = <STR_LIT> ; break ; case E_HImode : ret = <STR_LIT> ; break ; case E_QImode : ret = <STR_LIT> ; break ; default : break ; } } } if ( ret == <NUM_LIT> ) { abort_with_insn ( insn , <STR_LIT> ) ; return <NUM_LIT> ; } if ( delay != DELAY_NONE ) return iq2000_fill_delay_slot (


<s> void addFPR64asZPRRegOperands ( MCInst & Inst , unsigned N )


<s> rtl_opt_pass * make_pass_analyze_swaps ( gcc :: context * ctxt


<s> return <ISA_LIT>Lowering -> SelectAddressRegReg ( N , Base , Index , * CurDAG


<s> MCELFStreamer :: EmitValueImpl ( Value , Size , Loc ) ; Labels . clear ( )


<s> EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> ) return false ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; updateValueMap ( I ,


<s> MachineBasicBlock * DestBB = nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . isMBB ( ) ) { DestBB = MI -> getOperand ( i ) . getMBB ( ) ; break ; } } assert ( DestBB && <STR_LIT> ) ; if ( isBBInRange ( MI , DestBB , Br . OffsetBits ) )


<s> SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftElts = <NUM_LIT> , InsertAtByte = <NUM_LIT> ; bool Swap = false ; unsigned LittleEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned BigEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = N -> getMask ( ) ; int OriginalOrder [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool FoundCandidate = false ; unsigned VINSERTBSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < BytesInVector ; ++ i ) { unsigned CurrentElement = Mask [ i ] ; if ( V2 . isUndef ( ) && CurrentElement != VINSERTBSrcElem ) continue ; bool OtherElementsInOrder = true


<s> unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT>


<s> DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase


<s> DEBUG ( const MachineLoop * Loop = MLI -> getLoopFor ( MBB ) ; if ( Loop && Loop -> getHeader ( ) == MBB ) dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; ) ; MachineBasicBlock * SinglePredMBB = getSingleSchedPred ( MBB , MLI -> getLoopFor ( MBB ) ) ; if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; DEBUG ( dbgs ( ) << <STR_LIT> << SinglePredMBB -> getNumber ( ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; for ( MachineBasicBlock :: iterator I = SinglePredMBB -> getFirstTerminator ( ) ; I != SinglePredMBB -> end ( ) ; I ++ ) { DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> unsigned int regno ; switch ( mode ) { case SFmode : case SCmode : case DFmode : case DCmode : case TFmode : case SDmode : case DDmode : case TDmode : regno = FIRST_SSE_REG ; break ; case XFmode : case XCmode : regno = FIRST_FLOAT_REG ; break ; case TCmode : return NULL ; default : regno = AX_REG ; } return gen_rtx_REG ( mode , regno ) ; } else if ( POINTER_TYPE_P ( valtype ) ) { mode = word_mode ; } ret = construct_container ( mode , orig_mode , valtype , <NUM_LIT> , X86_64_REGPARM_MAX , X86_64_SSE_REGPARM_MAX

, x86_64_int_return_registers , <NUM_LIT> ) ;


<s> void dump ( ) { errs ( ) << <STR_LIT> << this << '\n' ; errs ( ) << <STR_LIT> ; if ( Base . getNode ( ) ) Base . getNode ( ) -> dump ( ) ; else errs ( ) <<


<s> PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CodePointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; } else { WinEHEncodingType = WinEH :: EncodingType :: <ISA_LIT> ; } ExceptionsType = ExceptionHandling :: WinEH ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT>


<s> bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ; DEBUG ( { dbgs ( )


<s> } if ( which == <NUM_LIT> ) for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which != <NUM_LIT> ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d .


<s> break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl ,


<s> neg_b = ( vec_ushort8 ) vec_sub ( vec_splat_s16 ( <NUM_LIT> ) , ( vec_short8 ) ( b ) ) ; mask = vec_sra ( vec_sl ( neg_b , vec_splat_u16 ( <NUM_LIT> ) ) , vec_splat_u16 (


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; if ( TheTriple . isOSWindows ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple


<s> const char * option_part = strchr ( token , '=' ) ; if ( ! option_part ) { error ( <STR_LIT> , token ) ; return ; } length = option_part - token ; option_part


<s> static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ; unsigned ClassID =


<s> unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitLD_F16_PSEUDO ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) ) ) MIB . add ( MO ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( Rt , <NUM_LIT> , <STR_LIT> ) ; Rt =


<s> phase1_vrs saved_vrs ; _Unwind_Reason_Code pr_result ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ; saved_vrs . core = entry_vrs -> core ; saved_vrs . demand_save_flags = ~ ( _uw ) <NUM_LIT> ; do { if ( get_eit_entry ( ucbp , saved_vrs . core . r [ R_PC ] ) != _URC_OK ) return _URC_FAILURE ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( _US_VIRTUAL_UNWIND_FRAME , ucbp , ( void * ) & saved_vrs ) ; } while ( pr_result == _URC_CONTINUE_UNWIND ) ; restore_non_core_regs ( & saved_vrs ) ; if ( pr_result != _URC_HANDLER_FOUND ) { return _URC_FAILURE


<s> unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC


<s> Inst . addOperand ( MCOperand :: createImm ( Insn + <NUM_LIT>


<s> StringRef <STR_LIT> ( FpABIKind Value ) { switch ( Value ) { case FpABIKind :: XX : return <STR_LIT> ; case FpABIKind :: S32 : return <STR_LIT> ; case FpABIKind :: S64 : return


<s> SMLoc RegLoc = RegTok . getLoc ( ) ; if ( RegTok . isNot ( AsmToken :: Identifier ) ) { Error ( RegLoc , <STR_LIT> ) ; return true ; } int RegNum = TryParseRegister ( ) ; if ( RegNum == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return true ; } if ( IsRange ) { int Reg = PrevRegNum ; do { ++ Reg ; Registers . push_back ( std :: make_pair ( Reg , RegLoc ) ) ; } while ( Reg != RegNum ) ; } else { Registers . push_back ( std :: make_pair ( RegNum , RegLoc ) ) ; } PrevRegNum = RegNum ; } while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) ; const AsmToken & RCurlyTok = Parser . getTok ( ) ; if ( RCurlyTok . isNot ( AsmToken :: RCurly ) ) { Error ( RCurlyTok . getLoc ( ) , <STR_LIT> ) ; return true ; } SMLoc E = RCurlyTok . getLoc ( ) ; Parser . Lex