<s> case AND : case IOR : case XOR : case NOT : * total = COSTS_N_INSNS ( mode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; break ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( mode == DImode ) * total = COSTS_N_INSNS ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) ? <NUM_LIT> : <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ABS : if ( mode == SFmode || mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case PLUS : case MINUS : if ( mode == SFmode || mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case NEG : * total = ( mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; break ; case MULT : if ( mode == SFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; bool all_low_regs , bind_old_new ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && aarch_mm_needs_acquire ( model_rtx ) ; bool use_release = TARGET_HAVE_LDACQ && aarch_mm_needs_release ( model_rtx ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode


<s> bool <ISA_LIT>FunctionInfo :: needsDwarfUnwindInfo ( ) const { if ( ! NeedsDwarfUnwindInfo . hasValue ( ) ) NeedsDwarfUnwindInfo = MF . needsFrameMoves ( ) && ! MF .

getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ;


<s> MCRegister DestRegHi = RI . getMatchingSuperReg ( RI . getSubReg ( DestReg , <STR_LIT> ) , <STR_LIT> , & <STR_LIT> ) ; MCRegister DestRegLo = RI . getMatchingSuperReg ( RI . getSubReg ( DestReg , <STR_LIT> ) , <STR_LIT> , & <STR_LIT> ) ; if ( DestRegHi != SrcReg ) copyPhysReg ( MBB , MBBI , DL , DestRegHi , SrcReg , false ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestRegLo ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } if ( SrcReg == <STR_LIT> ) { auto MIB = BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) ; if ( KillSrc ) { const MachineFunction * MF = MBB . getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; MIB -> addRegisterKilled ( SrcReg , TRI ) ; } return ; } if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << ( <STR_LIT> - <NUM_LIT> ) ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = STI . hasVector ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg


<s> return ( int16_t ) __builtin_neon_vget_lanev8hi (


<s> if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > <NUM_LIT> && CmpVal <= Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal < Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( CmpVal == Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( Mask == Low + High ) { if ( CCMask == <STR_LIT> && CmpVal == Low ) return <STR_LIT> ; if ( CCMask == <STR_LIT> && CmpVal ==


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MachineOperand & Src1 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & Src2 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . add ( Dst ) . add ( Src1 ) . add ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . add ( Dst ) . add ( SrcR ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( NewMI )


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> )


<s> Register Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isCmseEntry && ! isTrap && AFI -> getArgumentStackToRestore ( ) == <NUM_LIT> && STI . hasV5TOps ( ) && MBB . succ_empty ( ) && ! hasPAC ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm (


<s> uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; bool hasAVX2 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX2 ( ) ; uint16_t validDomains = <NUM_LIT> ; if ( domain && lookup ( MI -> getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ; else if ( domain && lookupAVX2 ( MI -> getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? <NUM_LIT> : <NUM_LIT> ; return std :: make_pair ( domain , validDomains


<s> if ( ( flag_cf_protection & CF_BRANCH ) ) emit_insn ( gen_nop_endbr ( ) ) ; if ( REG_P ( this_param ) ) this_reg = this_param ; else if ( vcall_offset ) { this_reg = gen_rtx_REG ( Pmode , AX_REG ) ; emit_move_insn ( this_reg , this_param ) ; } else this_reg = NULL_RTX ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; rtx delta_dst = this_reg ? this_reg : this_param ; if ( TARGET_64BIT ) { if ( ! x86_64_general_operand ( delta_rtx , Pmode ) ) { tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; emit_move_insn ( tmp , delta_rtx ) ; delta_rtx = tmp ; } } ix86_emit_binop ( PLUS , Pmode , delta_dst , delta_rtx ) ; } if ( vcall_offset ) { rtx vcall_addr , vcall_mem , this_mem ; tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; this_mem = gen_rtx_MEM ( ptr_mode , this_reg ) ; if ( Pmode != ptr_mode ) this_mem = gen_rtx_ZERO_EXTEND ( Pmode , this_mem ) ; emit_move_insn ( tmp , this_mem ) ; vcall_addr = plus_constant ( Pmode , tmp , vcall_offset ) ; if ( TARGET_64BIT && ! ix86_legitimate_address_p ( ptr_mode , vcall_addr , true ) ) { rtx tmp2 = gen_rtx_REG ( Pmode , R11_REG ) ; emit_move_insn ( tmp2 , GEN_INT ( vcall_offset ) ) ; vcall_addr = gen_rtx_PLUS ( Pmode , tmp , tmp2 ) ; } vcall_mem = gen_rtx_MEM ( ptr_mode , vcall_addr ) ; if ( Pmode != ptr_mode ) emit_insn ( gen_addsi_1_zext ( this_reg , gen_rtx_REG ( ptr_mode , REGNO ( this_reg ) ) , vcall_mem ) ) ; else ix86_emit_binop ( PLUS , Pmode , this_reg , vcall_mem ) ; } if ( this_reg && this_reg != this_param ) emit_move_insn ( this_param ,


<s> if ( ! TT . isOSDarwin ( ) && ! JIT && ( TT . getArch ( ) == Triple :: ppc64 || TT .

getArch ( ) == Triple :: ppc64le ) ) return CodeModel :: Medium ;


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> static __inline__ double __fnmadd ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return


<s> if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand (

<NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ;


<s> return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags (


<s> const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; assert ( StackAlign >= <NUM_LIT> && isPowerOf2_32 ( StackAlign ) && <STR_LIT> ) ; unsigned StackProbeSize = <NUM_LIT> ; const Function & Fn = MF . getFunction ( ) ; if ( Fn . hasFnAttribute ( <STR_LIT> ) ) Fn . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; StackProbeSize &= ~ ( StackAlign - <NUM_LIT> ) ; return StackProbeSize ? StackProbeSize


<s> ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IdLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } default : break ; } llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>Subtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const { Mutations . push_back ( create<ISA_LIT>MacroFusionDAGMutation (


<s> if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && Subtarget . is64Bit ( ) ) { return Op ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG .


<s> else if ( REG_P ( op0 ) && MEM_P ( op1 ) ) ret = ( quad_int_reg_operand ( op0 , GET_MODE ( op0 ) ) && quad_memory_operand ( op1 , GET_MODE ( op1 ) ) && ! reg_overlap_mentioned_p ( op0 , op1 ) ) ; else if ( MEM_P ( op0 ) && REG_P ( op1 ) ) ret = ( quad_memory_operand ( op0 , GET_MODE ( op0 ) ) && quad_int_reg_operand ( op1 , GET_MODE ( op1 ) ) ) ; else ret = false


<s> if ( getOptLevel ( ) == CodeGenOpt ::

None ) addPass ( create<ISA_LIT>O0PreLegalizerCombiner ( ) ) ;


<s> return ; case VK_AARCH64_DTPREL_G2 : case VK_AARCH64_DTPREL_G1 : case VK_AARCH64_DTPREL_G1_NC : case VK_AARCH64_DTPREL_G0 : case VK_AARCH64_DTPREL_G0_NC : case VK_AARCH64_DTPREL_HI12 : case VK_AARCH64_DTPREL_LO12 : case VK_AARCH64_DTPREL_LO12_NC : case VK_AARCH64_GOTTPREL_G1 : case VK_AARCH64_GOTTPREL_G0_NC : case VK_AARCH64_GOTTPREL : case VK_AARCH64_GOTTPREL_LO12


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue >> & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; <ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI


<s> return ( float64x1_t ) { __builtin_aarch64_scvtfdi ( vget_lane_s64 (


<s> bool <ISA_LIT>TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( <STR_LIT> , ResVT )


<s> rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( ( d -> vec_flags & VEC_SVE_DATA ) && elt * ( aarch64_sve_container_bits ( vmode ) / <NUM_LIT> ) >= <NUM_LIT> ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; lane = GEN_INT ( elt ) ; rtx parallel = gen_rtx_PARALLEL ( vmode , gen_rtvec ( <NUM_LIT> , lane ) ) ; rtx select = gen_rtx_VEC_SELECT ( GET_MODE_INNER ( vmode ) , in0 , parallel ) ; emit_set_insn ( out , gen_rtx_VEC_DUPLICATE ( vmode , select ) ) ; return


<s> bool IsPD = VecTy -> getScalarType ( ) -> isDoubleTy ( ) ; unsigned NumLaneElts = IsPD ? <NUM_LIT> : <NUM_LIT> ; assert ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) ; int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt


<s> FuncInfo -> setUsesTOCBasePtr ( ) ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { Register Reg = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTOCPointerRegister ( ) ; MachineOperand MO = MachineOperand :: CreateReg ( Reg , false , true ) ; MI . addOperand ( * MF , MO ) ; MI . setDesc ( TII -> get (


<s> void addRegVSFRCOperands ( MCInst & Inst , unsigned N


<s> Value * Src2 = Vals [ Next ( ) ] ; Type * VecTy = ResEVT . getTypeForEVT ( * Ctx ) ; assert ( VecTy -> isVectorTy ( ) ) ; assert ( VecTy == Src1 -> getType ( ) && VecTy == Src2 -> getType ( ) ) ; unsigned NumElt = VecTy -> getVectorNumElements ( ) ; Value * Res = UndefValue ::


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( auto * ConstantMask = dyn_cast < ConstantDataVector > ( Mask ) ) return getNegativeIsTrueBoolVec ( ConstantMask ) ; Value * ExtMask ; if ( PatternMatch :: match ( Mask , PatternMatch :: m_SExt ( PatternMatch :: m_Value ( ExtMask ) ) ) && ExtMask -> getType (

) -> isIntOrIntVectorTy ( <NUM_LIT> ) ) return ExtMask ;


<s> bool is64 = ( MI . getOpcode ( ) == <STR_LIT> ) ; unsigned Op = Subtarget . useCheriExactEquals ( ) ? ( is64 ? <STR_LIT> : <STR_LIT> ) : ( is64 ? <STR_LIT> : <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( Op ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI .

getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> bool isVectorIndex32 ( ) const { if ( Kind != k_VectorIndex ) return false ; return VectorIndex . Val


<s> return ( __m128i ) __builtin_ia32_gatherdiv2di ( ( __v2di ) src , base , ( __v2di ) index ,


<s> LLVM_DUMP_METHOD void <ISA_LIT>ConstantPoolValue :: dump ( ) const { errs ( ) << <STR_LIT> << *


<s> if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) type |= ARM_FT_CMSE_ENTRY ; return


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l'


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( * MF


<s> static __inline qword si_fs ( qword a , qword b ) { return ( ( qword ) ( vec_sub ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b )


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) { MachineBasicBlock :: iterator NMI = std :: next ( MI ) ; modified |= handleInst ( * MBB , MI ) ; MI = NMI ; } } return modified


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { return false


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ActiveLaneMask << <STR_LIT> ) ; auto * VecTy = getVectorType ( I ) ; if ( ! IsSafeActiveMask ( ActiveLaneMask , TripCount , VecTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; InsertVCTPIntrinsic ( ActiveLaneMask , TripCount , VecTy ) ; } Cleanup ( Predicates , L ) ; return


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectLoad ( const Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( <ISA_LIT>FastEmitLoad ( VT , AM


<s> int NumLaneElts = NumElts / NumLanes ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx <


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( isPositionIndependent ( ) && ! Subtarget .


<s> return ( __m128i ) __builtin_ia32_sha1msg1 ( ( __v4si )


<s> if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createMem ( MemoryKind MemKind , RegisterKind RegKind , unsigned Base , const MCExpr * Disp , unsigned Index , const MCExpr * LengthImm , unsigned LengthReg , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindMem , StartLoc , EndLoc ) ; Op -> Mem . MemKind


<s> return ( __m64 ) __builtin_ia32_punpckldq ( ( __v2si ) __m1 , (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [


<s> static SDValue combineAdd ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { const SDNodeFlags Flags = N -> getFlags ( ) ; if ( Flags . hasVectorReduction ( ) ) { if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; if ( SDValue MAdd = combineLoopMAddPattern ( N , DAG , Subtarget ) ) return MAdd ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand


<s> if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; else if ( sibcall_p && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_symPCREL_label2reg ( reg , sym , lab ) ) ; else emit_insn ( gen_symPLT_label2reg ( reg , sym ,


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; return false ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; if ( RegNo == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { if ( Tok . getString ( ) . size ( ) == <NUM_LIT> ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo = <STR_LIT> ; break ; case '7' : RegNo = <STR_LIT> ; break ; case '8' : RegNo = <STR_LIT> ; break ; case '9' : RegNo = <STR_LIT> ; break ; } } else if ( Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) [ <NUM_LIT> ] == '1' ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; } } if ( RegNo != <NUM_LIT> )


<s> static DecodeStatus DecodeVR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo

, uint64_t Address , const void * Decoder ) {


<s> <ISA_LIT>Relocator :: Result tls ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { return Relocator :: Unsupported


<s> static SDValue OptimizeConditionalInDecrement ( SDNode * N , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Ext = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Ext . getOpcode ( ) != <STR_LIT> || ! Ext . hasOneUse ( ) ) return SDValue ( ) ; SDValue SetCC = Ext . getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> || ! SetCC . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC = ( <STR_LIT> ) SetCC . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = SetCC . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue NewCmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CmpOp0 , DAG . getConstant ( <NUM_LIT> , DL , CmpOp0 . getValueType ( ) ) ) ; SDValue OtherVal = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( - <NUM_LIT> , DL , OtherVal . getValueType ( ) ) , NewCmp ) ; return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( <NUM_LIT> ,


<s> V = DAG . getAnyExtOrTrunc ( V , DL , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } ; SmallVector < SDValue , <NUM_LIT> > Ops ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Splat ) { if ( Splat . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; Splat = CreateMMXElement ( Splat ) ; if ( Subtarget . hasSSE1 ( ) ) { if ( NumElts == <NUM_LIT> ) Splat = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstant ( <STR_LIT> , DL , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , Splat , Splat ) ; unsigned ShufMask = ( NumElts > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstant ( <STR_LIT> , DL , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , Splat , DAG . getTargetConstant ( ShufMask , DL , <STR_LIT> ) ) ; } Ops . append ( NumElts , Splat ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Ops . push_back ( CreateMMXElement (


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr (


<s> break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else { if ( auto * C = dyn_cast < ConstantSDNode > ( ImmOpnd ) ) { Offset += C -> getSExtValue ( ) ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( Offset % <NUM_LIT> ) != <NUM_LIT> ) continue ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) continue ; ImmOpnd = CurDAG -> getTargetConstant ( Offset , SDLoc ( ImmOpnd ) , ImmOpnd . getValueType ( ) ) ; } else if ( Offset != <NUM_LIT> ) { continue ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( GV -> getAlignment ( ) < <NUM_LIT> && ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT>

|| StorageOpcode == <STR_LIT> || ( Offset % <NUM_LIT> ) != <NUM_LIT> ) ) {


<s> SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > DUPMask ( CCVT . getVectorNumElements ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getVectorShuffle ( CCVT , DL , SetCC , SetCC , DUPMask . data ( ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , ResVT . changeVectorElementTypeToInteger ( ) , Mask ) ; return DAG . getSelect ( DL , ResVT , Mask , N -> getOperand ( <NUM_LIT> ) , N -> getOperand


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const


<s> if ( VT . isScalableVector ( ) ) { if ( VT . getVectorElementType ( ) != <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; } uint64_t VTSize = VT . getFixedSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . isScalableVector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . isScalableVector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } else { PredicateConstraint PC = parsePredicateConstraint ( Constraint ) ; if ( PC != PredicateConstraint :: Invalid ) { if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; bool restricted = ( PC == PredicateConstraint ::


<s> return ( __m256d ) __builtin_ia32_expanddf256_maskz ( ( __v4df ) __A , ( __v4df ) _mm256_setzero_pd ( )


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; SpillsVRS = true ; }


<s> if ( Level == BeforeLegalizeTypes ) return true ; if ( Subtarget -> isThumb ( ) && Subtarget -> isThumb1Only ( ) ) return true ; if ( N -> getOpcode ( ) !=


<s> if ( ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) || ! CE ) return std :: make_pair ( ( const MCSymbolRefExpr * ) <NUM_LIT> , ( int64_t ) <NUM_LIT> ) ; return std :: make_pair ( cast < MCSymbolRefExpr > ( LHS ) , CE -> getValue ( ) ) ; } if ( Kind != MCExpr :: SymbolRef ) return std :: make_pair ( ( const MCSymbolRefExpr * ) <NUM_LIT> , ( int64_t ) <NUM_LIT> ) ; return std :: make_pair ( cast < MCSymbolRefExpr > (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & , const Triple

& TT , StringRef , const MCTargetOptions & ) {


<s> if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT InVT = Src . getValueType ( ) ; if ( InVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; APInt ShiftAmt ; if ( ! <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) , ShiftAmt ) || ShiftAmt != <NUM_LIT> ) return SDValue ( ) ; SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = LHS . getOpcode ( ) ; if ( ( ExtOpc != <STR_LIT> && ExtOpc != <STR_LIT> ) || RHS . getOpcode ( ) != ExtOpc ) return SDValue ( ) ; LHS = LHS . getOperand


<s> __o = __builtin_aarch64_ld3rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o ,


<s> t = __ev_mwhumi ( a , b ) ; return __ev_addumiaaw ( t


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; assert ( DstRB . getID ( ) == SrcRB . getID ( ) && <STR_LIT> ) ; assert ( DstTy . getSizeInBits ( ) > SrcTy . getSizeInBits ( ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( canTurnIntoCOPY ( SrcRC , DstRC ) ) return selectTurnIntoCOPY ( I , MRI , SrcReg , SrcRC , DstReg , DstRC ) ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } if ( SrcRC == DstRC ) { I . setDesc ( TII . get ( <STR_LIT> ) ) ; return true


<s> mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = !


<s> if ( ! BO -> getType ( ) -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; bool Changed = false ; Changed |= trySADReplacement ( BO -> getOperand ( <NUM_LIT>


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode (


<s> bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt ,


<s> SmallVector < Value * , <NUM_LIT> > Args { GP , Vec } ; <STR_LIT> IntID = <STR_LIT> ; auto * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Vec -> getType ( ) ) ; return CallInst :: Create ( Intr -> getFunctionType (


<s> default : return true ; case ELF :: R_<ISA_LIT>_PREL31 : case ELF :: R_<ISA_LIT>_ABS32


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) && shouldTransformMulToShiftsAddsSubs ( C -> getAPIntValue ( ) , VT , DAG , Subtarget ) ) return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ; return SDValue ( N


<s> else { SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FrameAddr , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; FrameAddr = DAG . getLoad ( <STR_LIT> , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } } return FrameAddr


<s> if ( strcmp ( gcc_exec , collect_gcc ) == <NUM_LIT> ) { target_compiler = XDUPVEC ( char , name , strlen ( name ) + <NUM_LIT> ) ; found = true ; goto out ; } target_compiler = concat ( gcc_path , <STR_LIT> , name , NULL ) ; if ( access_check ( target_compiler , X_OK ) == <NUM_LIT> ) { found = true ; goto out ; } n_paths = parse_env_var ( getenv ( <STR_LIT> ) , & paths ) ; for ( i = <NUM_LIT> ; i < n_paths ; i


<s> vpaddq_s8 ( int8x16_t a , int8x16_t b ) { int8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> if ( ! Src -> isVectorTy ( ) && Opcode == Instruction :: Load && I != nullptr && I -> hasOneUse ( ) ) { const Instruction * UserI = cast < Instruction > ( * I -> user_begin ( ) ) ; unsigned Bits = Src -> getScalarSizeInBits ( ) ; bool FoldsLoad = false ; switch ( UserI -> getOpcode ( ) ) { case Instruction :: ICmp : case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : FoldsLoad = ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ; break ; } if ( FoldsLoad ) { assert ( UserI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( UserI -> getOperand ( i ) == I ) continue ; if ( LoadInst * LI = dyn_cast < LoadInst > ( UserI -> getOperand ( i ) ) ) { if ( LI -> hasOneUse ( ) ) return i == <NUM_LIT> ; } } return <NUM_LIT> ; } } unsigned NumOps = getNumberOfParts ( Src ) ; if ( Src -> getScalarSizeInBits ( ) == <NUM_LIT> )


<s> int i ; int nelts = sizeof ( arm_simd_types ) / sizeof ( arm_simd_types [ <NUM_LIT> ] ) ; tree tdecl ; arm_simd_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( arm_simd_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( arm_simd_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_floatHF_type_node , <STR_LIT> ) ; arm_simd_polyQI_type_node = build_distinct_type_copy ( intQI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyQI_type_node , <STR_LIT> ) ; arm_simd_polyHI_type_node = build_distinct_type_copy ( intHI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyHI_type_node , <STR_LIT> ) ; arm_simd_polyDI_type_node = build_distinct_type_copy ( unsigned_intDI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyDI_type_node , <STR_LIT> ) ; arm_simd_polyTI_type_node = build_distinct_type_copy ( unsigned_intTI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyTI_type_node , <STR_LIT> ) ; arm_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; arm_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; arm_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ]


<s> src = tmp ; } } break ; case CONST_INT : switch ( standard_sse_constant_p ( src , TImode ) ) { case <NUM_LIT> : src = CONST0_RTX ( GET_MODE ( dst ) ) ; break ; case <NUM_LIT> : src = CONSTM1_RTX ( GET_MODE ( dst ) ) ; break ; default : gcc_unreachable ( ) ; } if ( MEM_P ( dst ) ) { tmp = gen_reg_rtx ( V1TImode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } break ; case AND : if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == NOT ) { convert_op ( & XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , insn ) ; convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( XEXP ( src , <NUM_LIT> ) , V1TImode ) ; PUT_MODE ( src , V1TImode ) ; break ; } case XOR : case IOR : convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( src , V1TImode ) ; if ( MEM_P ( dst ) ) { tmp = gen_reg_rtx ( V1TImode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } break ; case NOT : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; tmp = gen_reg_rtx ( V1TImode ) ; emit_insn_before ( gen_move_insn ( tmp , CONSTM1_RTX ( V1TImode ) ) , insn ) ; src = gen_rtx_XOR ( V1TImode , src , tmp ) ; if ( MEM_P ( dst ) ) { tmp = gen_reg_rtx ( V1TImode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } break ; case COMPARE : dst = gen_rtx_REG ( CCmode , FLAGS_REG ) ; src = convert_compare ( XEXP ( src , <NUM_LIT> ) , XEXP ( src , <NUM_LIT> ) , insn ) ; break ; case ASHIFT : case


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) { MachineSDNode :: mmo_iterator MemOp = MF ->


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRE ( ) ) || ( VT ==

<STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) {


<s> bool isNameEqual ( std :: string Other , const FeatureBitset & FeatureBits ) const { if ( FeatureBitSet . any ( ) && ( FeatureBitSet & FeatureBits ) . none ( ) ) return false ; return Name == Other


<s> uint64_t Size = initMBBInfo ( ) ; if ( Size <= MaxForwardRange || ! mustRelaxABranch ( ) ) return false ; setWorstCaseAddresses (


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( ShadowRegI8 ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize


<s> bool isVectorReg ( ) const { return Kind == Register && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_ADD , G_SUB , G_MUL } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_UADDO , G_UADDE , G_USUBO , G_USUBE , G_UMULO } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( G_UMULH ) . legalFor ( { s32 } ) . maxScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor


<s> assert ( ScratchIdx != e && <STR_LIT> ) ; int64_t ID = MI . getOperand ( StartIdx ) . getImm ( ) ; assert ( ( int32_t ) ID == ID && <STR_LIT> ) ; bool isAnyRegCC = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) == CallingConv :: AnyReg ; assert ( ( ( hasDef && isAnyRegCC ) || ! hasDef ) && <STR_LIT> ) ; int64_t StackMapIdx = isAnyRegCC ? StartIdx + <NUM_LIT> : StartIdx + <NUM_LIT> + MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ; assert ( StackMapIdx <= MI . getNumOperands ( ) && <STR_LIT> ) ; SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , StackMapIdx ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end ( ) ) , isAnyRegCC && hasDef ) ; unsigned EncodedBytes = <NUM_LIT> ; int64_t CallTarget = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ; if ( CallTarget ) { EncodedBytes = <NUM_LIT> ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI . getOperand ( ScratchIdx ) . getReg ( ) ) . addImm ( CallTarget ) ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI . getOperand


<s> if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual (

Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> bool isDef = any_of ( I -> operands ( ) , [ DefReg , TRI ] ( MachineOperand & MOP ) { return MOP . isReg ( ) && MOP . isDef ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , DefReg ) ; }


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { Register TempReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT>


<s> Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight


<s> if ( VT . isVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL

, VT ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> void \ sbss_section ( ) \ { \ if ( in_section != in_sbss ) \ { \ in_section = in_sbss ; \

fprintf ( asm_out_file , <STR_LIT> , SBSS_SECTION_ASM_OP ) ; \ } \ }


<s> else { m_prev_psw_reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_mvfc ( m_prev_psw_reg , GEN_INT ( CTRLREG_PSW ) )


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; if ( ! isTailCall ) { if ( isVector ) { SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset


<s> return classifyLocalReference ( nullptr )


<s> if ( Op . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( ! LHS . getValueType ( ) . isFloatingPoint ( ) ) return Op ; SDValue RHS = Op . getOperand


<s> initialize<ISA_LIT>TDCPassPass ( * PassRegistry :: getPassRegistry ( )


<s> } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return combineAddOrSubToADCOrSBB ( N ,


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain ,


<s> if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , MF , RVLocs , C ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) ) { unsigned NumInRegs =


<s> const unsigned char * pc = context -> ra ; if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) != <NUM_LIT> ) return NULL ; if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> || * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) { struct sigframe { char gap [ SIGNAL_FRAMESIZE ] ; unsigned long pad [ <NUM_LIT> ] ; struct gcc_regs * regs ; } * frame = ( struct sigframe * ) context -> cfa ; return frame -> regs ; } else if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> || * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) { struct rt_sigframe { char gap [ SIGNAL_FRAMESIZE + <NUM_LIT> ] ; char siginfo [ <NUM_LIT> ] ; struct gcc_ucontext uc ; } * frame = ( struct rt_sigframe * ) context -> cfa ; return frame -> uc


<s> bool isLikeA9 ( ) const { return isCortexA9 ( ) || isCortexA15 (


<s> reg_increment = GET_MODE_SIZE ( mode ) ; regs_per_val = reg_increment / <NUM_LIT> ; offset_adj = return_pc ? <NUM_LIT> : <NUM_LIT> ; if ( count <= <NUM_LIT> || GET_CODE ( XVECEXP ( op , <NUM_LIT> , offset_adj ) ) != SET || ( load && ! REG_P ( SET_DEST ( XVECEXP ( op , <NUM_LIT> , offset_adj ) ) ) ) ) return false ; elt = XVECEXP ( op , <NUM_LIT> , offset_adj ) ; if ( GET_CODE ( SET_SRC ( elt ) ) == PLUS ) { i ++ ; base = <NUM_LIT> ; update = true ; if ( ! REG_P ( SET_DEST ( elt ) ) || ! REG_P ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) || ( REGNO ( SET_DEST ( elt ) ) != REGNO ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) ) || ! CONST_INT_P ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) || INTVAL ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) != ( ( count - <NUM_LIT> - offset_adj ) * reg_increment ) ) return false ; } i = i + offset_adj ; base = base + offset_adj ; if ( ( count <= i ) && ( mode == SImode ) ) return false ; elt = XVECEXP ( op , <NUM_LIT> , i - <NUM_LIT> ) ; if ( GET_CODE ( elt ) != SET ) return false ; if ( load ) { reg = SET_DEST ( elt ) ; mem = SET_SRC ( elt ) ; } else { reg = SET_SRC ( elt ) ; mem = SET_DEST ( elt ) ; } if ( ! REG_P ( reg ) || ! MEM_P ( mem ) ) return false ; regno = REGNO (


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( RHS ) return false ; ShReg = N . getOperand ( <NUM_LIT> ) ; if ( CheckProfitability && ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) )


<s> if ( val & IX86_HLE_ACQUIRE && ! ( is_mm_acquire ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST | IX86_HLE_ACQUIRE ; } if ( val & IX86_HLE_RELEASE && ! ( is_mm_release ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST | IX86_HLE_RELEASE ; } return


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>ExternalSymbolizer


<s> SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , const BranchProbability & Probability ) const { if ( ! TCycles || ! FCycles ) return false ; unsigned TUnpredCost = Probability . getNumerator ( ) * TCycles ; TUnpredCost /= Probability . getDenominator (


<s> CCInfo . AnalyzeCallOperands ( OutVTs , CLI . OutFlags , CCAssignFnForCall ( CC ) ) ; NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; for ( CCValAssign & VA : ArgLocs ) { const Value * ArgVal = CLI . OutVals [ VA . getValNo ( ) ] ; MVT ArgVT = OutVTs [ VA . getValNo ( ) ] ; unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = ( ArgVT . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; Align Alignment = DL . getABITypeAlign ( ArgVal


<s> SDValue Load = DAG . getNode ( Opcode , DL , { LoadVT , <STR_LIT> } , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( VT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load


<s> static SDValue expandV4F32ToV2F64 ( SelectionDAG & DAG , int Start , SDLoc DL , SDValue Op ) { int Mask [ ] = { Start , - <NUM_LIT> , Start + <NUM_LIT> , - <NUM_LIT> } ; Op = DAG . getVectorShuffle ( <STR_LIT> , DL , Op , DAG . getUNDEF (


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; assert ( ( RegClass == <STR_LIT> || RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRd ( insn , isSP ) ) ) ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; RegClass = OpInfo [ OpIdx ]


. isReg ( ) && Use . getReg ( ) == Reg ) return true ;


, ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> return ( MemVT . getSizeInBits ( ) <=


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> static tree ix86_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256


<s> if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = NormalizeCmpValue ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = NormalizeCmpValue ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> :


<s> if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , <NUM_LIT> , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS (

mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ;


<s> return ( __m512i ) __builtin_ia32_pmovsxdq512_mask ( ( __v8si ) __X , (

__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> } return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple


<s> return ( __m128i ) __builtin_ia32_pmovwb128_mask ( ( __v8hi ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 )


<s> int hilo_delay , i ; split_all_insns_noflow ( ) ; cfun -> machine -> ignore_hazard_length_p = true ; shorten_branches ( get_insns ( ) ) ; cfun -> machine -> all_noreorder_p = true ; if ( current_function_profile ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4120 ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4130 && ! ISA_HAS_MACCHI ) cfun -> machine -> all_noreorder_p = false ; last_insn = <NUM_LIT> ; hilo_delay = <NUM_LIT> ; delayed_reg = <NUM_LIT> ; lo_reg = gen_rtx_REG ( SImode , LO_REGNUM ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) mips_avoid_hazard ( last_insn , XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) , & hilo_delay , & delayed_reg , lo_reg ) ; else mips_avoid_hazard ( last_insn , insn , & hilo_delay , & delayed_reg , lo_reg ) ; last_insn =


<s> BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB


<s> static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> bool <ISA_LIT>TTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegal ( IsSigned ?


<s> TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , <STR_LIT>


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( TT . find ( <STR_LIT> ) == std


<s> int i ; rtx regs [ <NUM_LIT> ] ; i = <NUM_LIT> ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= <NUM_LIT> ) { rtx mem = gen_frame_mem ( BLKmode , regs [ i ]


<s> for ( unsigned I = <NUM_LIT> ; I != NumOps ; ++ I ) { SDValue SrcOp = Op . getOperand ( I ) ; if ( ! SrcOp . getValueType ( ) . isVector ( ) ) { LoOps [ I ] = HiOps [ I ] = SrcOp ; continue ; } std :: tie ( LoOps [ I ] , HiOps [ I ] ) = splitVector ( SrcOp , DAG , dl ) ; } EVT LoVT ,


<s> static MachineBasicBlock * emitBlockAfter ( MachineBasicBlock * MBB ) { MachineFunction & MF = * MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = MF . CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MF . insert ( llvm :: next ( MachineFunction :: iterator ( MBB ) ) , NewMBB ) ; return NewMBB


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask


<s> bool SelectAddrImmX4 ( SDValue N , SDValue & Disp , SDValue & Base ) { return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , *


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return STI -> isTargetDarwin ( ) || ReserveX18 ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ; case <STR_LIT> : case <STR_LIT>


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ; return SDValue ( )


<s> unsigned Opc = N -> getMachineOpcode ( ) ; const MCInstrDesc & MCID = getInstrInfo ( ) -> get ( Opc ) ; int CondNo = <STR_LIT> ( MCID ) ; if ( CondNo <


<s> if ( DAG . getNodeIfExists ( <STR_LIT> , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT (


<s> if ( auto Value = stripModuloOnShift ( * this , N , DCI . DAG ) ) return Value ; return SDValue ( )


<s> static DecodeStatus decodePC32DBLBranchOperand ( MCInst & Inst , uint64_t Imm


<s> static unsigned getNumVectorRegs ( Type * Ty ) { auto * VTy = cast < FixedVectorType > ( Ty ) ; unsigned WideBits = getScalarSizeInBits ( Ty ) * VTy -> getNumElements ( ) ; assert ( WideBits > <NUM_LIT> && <STR_LIT> ) ; return ( ( WideBits % <NUM_LIT> ) ? ( ( WideBits / <NUM_LIT> )

+ <NUM_LIT> ) : ( WideBits / <NUM_LIT> ) ) ;


<s> static SDValue lowerShuffleAsInsertPS ( const SDLoc & DL , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned InsertPSMask ; if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( )


<s> case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case


<s> if ( ShiftExtend . Amount != <NUM_LIT> && ShiftExtend . Amount != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; int64_t Imm = ShiftExtend . Amount / <NUM_LIT> -


<s> if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) ,

<NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) == cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType (


<s> return __builtin_mve_vmaxavq_sv4si ( __a ,


<s> if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) return Error ( L , <STR_LIT> ) ; bool WasThumb = isThumb ( ) ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( )


<s> Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain .


<s> if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_IMM3 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_IMM5 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_XMM128 || insn -> spec -> operands [ index ] . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize


<s> unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc


<s> static int ix86_reloc_rw_mask ( void


<s> if ( isa < ScalableVectorType > ( Ty ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return true ; unsigned shift = Log2_64


<s> VariantKind getKind ( ) const { return Kind


<s> return MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . add ( Offset


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { if ( DefRelocModel == Reloc :: Default && ( ! Subtarget . isTargetDarwin ( ) || ! Subtarget . is64Bit ( ) ) ) setRelocationModel ( Reloc :: Static ) ; if ( Subtarget . is64Bit ( ) ) { if ( Subtarget . isTargetDarwin ( ) ) setCodeModel ( CodeModel :: Small ) ; else setCodeModel ( CodeModel :: Large ) ; } PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ; } return


<s> ( ( struct u8 * ) ptr ) -> data = data ; return data


<s> unsigned IndexReg = Index . getReg ( ) ; if ( STI . hasFeature ( <STR_LIT> ) && BaseReg == <NUM_LIT> && IndexReg == <NUM_LIT> && Disp . isImm ( ) && Disp . getImm ( ) < <NUM_LIT> ) return true ; if ( ( BaseReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) || ( IndexReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> Register VReg ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; Register FrameReg ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg


<s> static DecodeStatus decodePC24DBLBranchOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * >

( getTargetMachine ( ) . getObjFileLowering ( ) ) ;


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . removeOperand


<s> static bool mips_use_debug_exception_return_p (


<s> if ( auto Mgs = dyn_cast < MaskedGatherScatterSDNode > ( Parent ) ) return selectAddrOfGatherScatterNode < MaskedGatherScatterSDNode > ( Mgs , N , Base , Scale , Index , Disp , Segment ) ; if ( auto <ISA_LIT>Gather = dyn_cast < <ISA_LIT>MaskedGatherSDNode > ( Parent ) ) return selectAddrOfGatherScatterNode < <ISA_LIT>MaskedGatherSDNode > ( <ISA_LIT>Gather , N , Base


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , MVT VT ) const { if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; return ( VT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT )

|| isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ;


<s> static SDValue PerformHWLoopCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { <STR_LIT> CC ; SDValue Cond ; int Imm = <NUM_LIT> ; bool Negate = false ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest ; if ( N -> getOpcode ( ) == <STR_LIT> ) { CC = <STR_LIT> ; Cond = N -> getOperand ( <NUM_LIT> ) ; Dest = N -> getOperand ( <NUM_LIT> ) ; } else { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; Cond = N -> getOperand ( <NUM_LIT> ) ; Dest = N -> getOperand ( <NUM_LIT> ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { if ( ! Const -> isOne ( ) && ! Const -> isNullValue ( ) ) return SDValue ( ) ; Imm = Const -> getZExtValue ( ) ; } else return SDValue ( ) ; } SDValue Int = SearchLoopIntrinsic ( Cond , CC , Imm , Negate ) ; if ( ! Int ) return SDValue ( ) ; if ( Negate ) CC = <STR_LIT> ( CC , <STR_LIT> ) ; auto IsTrueIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; auto IsFalseIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; assert ( ( IsTrueIfZero ( CC , Imm ) || IsFalseIfZero ( CC , Imm ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Elements = Int . getOperand ( <NUM_LIT>


<s> if ( MEM_P ( dst ) ) igain = - COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case AND : case XOR : case IOR : if ( ! MEM_P ( dst ) ) igain = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ASHIFT : case LSHIFTRT : op1val = INTVAL ( XEXP ( src , <NUM_LIT> ) ) ; if ( optimize_insn_for_size_p ( ) ) { if ( op1val == <NUM_LIT> || op1val == <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val >= <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val == <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else scost = COSTS_N_BYTES ( <NUM_LIT> ) ; if ( ( op1val & <NUM_LIT> ) == <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val > <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else vcost = TARGET_AVX ? COSTS_N_BYTES ( <NUM_LIT> ) : COSTS_N_BYTES ( <NUM_LIT> ) ; } else { scost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( ( op1val & <NUM_LIT> ) == <NUM_LIT> ) vcost = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( op1val > <NUM_LIT> ) vcost = COSTS_N_INSNS ( <NUM_LIT> ) ; else vcost = TARGET_AVX ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; } igain = scost - vcost ; break ; case ASHIFTRT : op1val = INTVAL ( XEXP ( src , <NUM_LIT> ) ) ; if ( optimize_insn_for_size_p ( ) ) { if ( op1val == <NUM_LIT> || op1val == <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val == <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val == <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val >= <NUM_LIT> ) scost = COSTS_N_BYTES ( <NUM_LIT> ) ; else scost = COSTS_N_BYTES ( <NUM_LIT> ) ; if ( op1val == <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val == <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val == <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( op1val >= <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( TARGET_AVX2 && op1val == <NUM_LIT> ) vcost = COSTS_N_BYTES ( <NUM_LIT> ) ; else if ( TARGET_SSE4_1 && op1val == <NUM_LIT> ) vcost =


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( SDValue V = combineShiftToPMULH ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand (


<s> } ; do { const MachineGadgetGraph :: Edge * CheapestSoFar = nullptr ; MachineGadgetGraph :: NodeSet GadgetSources { * Graph } , GadgetSinks { * Graph } ; for ( const auto & N : Graph -> nodes ( ) ) { if ( ElimNodes . contains ( N ) ) continue ; for ( const auto & E : N . edges ( ) ) { if ( IsGadgetEdge ( E ) ) { GadgetSources . insert ( N ) ; GadgetSinks . insert ( * E . getDest ( ) ) ; } } } for ( const auto & N : Graph -> nodes ( ) ) { if ( ElimNodes . contains ( N ) ) continue ; for ( const auto & E : N . edges ( ) ) { if ( IsCFGEdge ( E ) ) { if ( GadgetSources . contains ( N ) || GadgetSinks . contains ( * E . getDest ( ) ) ) { if ( ! CheapestSoFar || E . getValue ( ) < CheapestSoFar -> getValue ( ) ) CheapestSoFar = & E ; } } } } assert ( CheapestSoFar && <STR_LIT> ) ; CutEdges . insert ( * CheapestSoFar ) ; ElimEdges . insert ( * CheapestSoFar ) ; } while ( elimMitigatedEdgesAndNodes ( * Graph , ElimEdges , ElimNodes ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CutEdges . count ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; int FencesInserted = insertFences ( MF , * Graph , CutEdges ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( strncmp ( con , <STR_LIT> , <NUM_LIT> ) != <NUM_LIT> ) continue ; con += <NUM_LIT> ; if ( strchr ( con , ',' ) != NULL ) { error ( <STR_LIT> ) ; continue ; } bool invert = false ; if ( con [ <NUM_LIT> ] == 'n' ) invert = true , con ++ ; machine_mode mode = CCmode ; rtx_code code = UNKNOWN ; switch ( con [ <NUM_LIT> ] ) { case 'a' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = NE ; break ; case 'b' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = NE ; break ; case 'c' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; break ; case 'e' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; case 'g' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GE ; break ; case 'l' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LE ; break ; case 'o' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCOmode , code = EQ ; break ; case 'p' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCPmode , code = EQ ; break ; case 's' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCSmode , code = EQ ; break ; case


<s> } r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; r1 = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_load_split_stack_limit ( r0 ) ) ; alloc_hi = ( - allocate + <NUM_LIT> ) & ~ <NUM_LIT> ; alloc_lo = - allocate - alloc_hi ; if ( alloc_hi != <NUM_LIT> ) { emit_insn ( gen_add3_const ( r12 , r1 , alloc_hi ) ) ; if ( alloc_lo != <NUM_LIT> ) emit_insn ( gen_add3_const ( r12 , r12 , alloc_lo ) ) ; else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( insn ) = ok_label ; add_reg_br_prob_note ( insn , profile_probability :: very_likely ( ) ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( r0 , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_frame_store ( r0 , r1 , info -> lr_save_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_call_insn ( gen_call ( gen_rtx_MEM ( SImode , morestack_ref ) , const0_rtx , const0_rtx ) ) ; call_fusage = NULL_RTX ; use_reg ( & call_fusage , r12 ) ; use_reg ( & call_fusage , r0 ) ; add_function_usage_to ( insn ,


<s> MVT InVT = In . getSimpleValueType ( ) ; MVT VTElt = VT . getVectorElementType ( ) ; MVT InVTElt = InVT . getVectorElementType ( ) ; SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT , In .


<s> if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Op . getImm ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Op . getImm ( ) ) ) { const <ISA_LIT>MCExpr * LHSSymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ; return ( LHSSymbolRefExpr && LHSSymbolRefExpr -> getKind

( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ;


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) .


<s> SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> ,

<STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( TheARM64leTarget ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser >


<s> if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return <NUM_LIT> ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return <NUM_LIT> ; } } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return GET_MODE_SIZE ( mode )


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv16qi (


<s> unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return


<s> Value * Pg = II . getArgOperand ( <NUM_LIT> ) ; Value * Vec = II . getArgOperand ( <NUM_LIT> ) ; auto IntrinsicID = II . getIntrinsicID ( ) ; bool IsAfter = IntrinsicID == <STR_LIT> ; if ( auto * SplatVal = getSplatValue ( Vec ) ) return IC . replaceInstUsesWith ( II , SplatVal ) ; Value * LHS , * RHS ; if ( match ( Vec , m_OneUse ( m_BinOp ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) ) { if ( isSplatValue ( LHS ) || isSplatValue ( RHS ) ) { auto * OldBinOp = cast < BinaryOperator > ( Vec ) ; auto OpC = OldBinOp -> getOpcode ( ) ; auto * NewLHS = Builder . CreateIntrinsic ( IntrinsicID , { Vec -> getType ( ) } , { Pg , LHS } ) ; auto * NewRHS = Builder . CreateIntrinsic ( IntrinsicID , { Vec -> getType ( ) } , { Pg , RHS } ) ; auto * NewBinOp = BinaryOperator :: CreateWithCopiedFlags ( OpC , NewLHS , NewRHS , OldBinOp , OldBinOp -> getName ( ) , & II ) ; return IC . replaceInstUsesWith ( II , NewBinOp ) ; } } auto * C = dyn_cast < Constant > ( Pg ) ; if ( IsAfter && C && C -> isNullValue ( ) ) { auto * IdxTy = Type :: getInt64Ty ( II . getContext ( ) ) ; auto * Extract = ExtractElementInst :: Create ( Vec , ConstantInt :: get ( IdxTy , <NUM_LIT> ) ) ; Extract -> insertBefore ( & II ) ; Extract -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , Extract ) ; } auto * IntrPG = dyn_cast < IntrinsicInst > ( Pg ) ; if ( ! IntrPG ) return None ; if ( IntrPG -> getIntrinsicID ( ) != <STR_LIT> ) return None ; const auto PTruePattern = cast < ConstantInt > ( IntrPG -> getOperand ( <NUM_LIT> )


<s> ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; return ret


<s> bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB ,


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 . getImm