<s> Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb232 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFPV832 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONDataInsn = insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } MI . clear ( ) ; uint32_t NEONCryptoInsn = insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } MI . clear


<s> if ( isLegalAddressingMode ( AM , Ty , AS ) ) return AM . Scale != <NUM_LIT> ; return - <NUM_LIT>


<s> if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return <STR_LIT> + ( Reg - <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return <STR_LIT> +


<s> lowerLongBranchLUi ( MI , OutMI ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ; return


<s> unsigned <ISA_LIT>AsmParser :: matchSVEVectorNameAlias ( StringRef Name ) { unsigned RegNum = matchSVEVectorRegName ( Name ) ; if ( RegNum == <NUM_LIT> ) RegNum = matchReqRegisterNameAlias ( Name , RegKind :: SVEVector ) ; return RegNum


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( createELFObjectTargetWriter ( )


<s> BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP (


<s> bool <ISA_LIT>Subtarget :: enablePostRAMachineScheduler ( ) const { if ( ! enableMachineScheduler ( ) ) return


<s> return __builtin_mve_vrshrq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a


<s> static int findContiguousZerosAtLeast ( uint64_t Imm , unsigned Num ) { unsigned HiTZ = countTrailingZeros < uint32_t > ( Hi_32 ( Imm ) ) ; unsigned LoLZ = countLeadingZeros < uint32_t > ( Lo_32 ( Imm ) ) ; if ( ( HiTZ + LoLZ ) >= Num ) return ( <NUM_LIT> + HiTZ ) ; return


<s> SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Op0 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; if ( IsStrict ) return DAG . getMergeValues ( { Op0 , Chain } , dl ) ; return Op0 ; } } if ( Op0 . getSimpleValueType ( ) . isInteger ( ) ) { SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC ) ; if ( ! EFLAGS ) return SDValue ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> ,

dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ;


<s> static HOST_WIDE_INT vax_starting_frame_offset ( void ) { return TARGET_ELF ? -


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned RegNum = RegLst


<s> return __builtin_ia32_scalefsh_mask_round ( __A , __B , _mm_setzero_ph ( ) , ( __mmask8 ) -


<s> void <ISA_LIT>InstPrinter :: printSORegImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( )


<s> assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; if ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) Binary |= encodeVFPRn (


<s> return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC16 : ELF :: R_<ISA_LIT>_64_16 ; case RT64_8 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC8 : ELF :: R_<ISA_LIT>_64_8 ; } case MCSymbolRefExpr :: VK_GOT : switch ( Type ) { case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC64 : ELF :: R_<ISA_LIT>_64_GOT64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC32 : ELF :: R_<ISA_LIT>_64_GOT32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT64_64 ) ; assert ( ! IsPCRel ) ; return ELF :: R_<ISA_LIT>_64_GOTOFF64 ; case MCSymbolRefExpr :: VK_TPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_TPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_TPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_DTPOFF64


<s> bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc2 , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , false , OffUndef , Pred , PredReg , TII , isT2 ) ; NewBBI = llvm ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameDestroyOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , IsVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT>64_ELF_FIS ) ; CCValAssign & VA = RVLocs [ <NUM_LIT> ] ; assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MVT DestVT = VA . getValVT ( ) ; MVT CopyVT = DestVT ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned SourcePhysReg = VA . getLocReg ( ) ; unsigned ResultReg = <NUM_LIT> ; if ( RetVT == CopyVT ) { const TargetRegisterClass * CpyRC = TLI . getRegClassFor ( CopyVT ) ; ResultReg = createResultReg ( CpyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( CopyVT == <STR_LIT>


<s> if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] )


<s> if ( ! isShiftExtend ( ) ) return false ; if ( getShiftExtendAmount ( ) > Max )


<s> MVT EltVT = VT . getVectorElementType ( ) ; MVT V0VT = V0 . getSimpleValueType ( ) ; assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; MVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx /


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . shadowReg ( <STR_LIT> ) ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . addressReg ( <STR_LIT> ) ) ) ; if ( RegCtx . ScratchReg != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . scratchReg ( <STR_LIT> ) ) ) ; } StoreFlags (


<s> assert ( SatWidth <= DstElementWidth && <STR_LIT> ) ; if ( DstVT . isScalableVector ( ) ) return SDValue ( ) ; EVT SrcElementVT = SrcVT . getVectorElementType ( ) ; if ( SrcElementVT == <STR_LIT> && ( ! Subtarget -> hasFullFP16 ( ) || DstElementWidth > <NUM_LIT> ) ) { MVT F32VT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , F32VT , SrcVal ) ; SrcVT = F32VT ; SrcElementVT = <STR_LIT> ; SrcElementWidth = <NUM_LIT> ; } else if ( SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT . getScalarType ( ) ) ) ; if ( SrcElementWidth < SatWidth || SrcElementVT == <STR_LIT> ) return SDValue ( ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , IntVT , SrcVal , DAG . getValueType ( IntVT . getScalarType ( ) ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sext ( SrcElementWidth )


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg ,


<s> if ( unsigned PatchBytes = SOpers . getNumPatchBytes ( ) ) { EmitNops ( * OutStreamer , PatchBytes , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } else { const MachineOperand & CallTarget = SOpers . getCallTarget ( ) ; MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst


<s> return CallCC == CallingConv :: Fast &&


<s> static SDValue getTargetVShiftNode ( unsigned Opc , SDLoc dl , MVT VT , SDValue SrcOp , SDValue ShAmt , SelectionDAG & DAG ) { assert ( ShAmt . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShOps ) ; MVT EltVT = VT . getVectorElementType ( ) ; EVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT .


<s> if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MI . eraseFromParent ( ) ; return DoneMBB


<s> SMLoc getStartLoc ( ) const { return


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue


<s> unsigned <STR_LIT> ( <STR_LIT> CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void addVecListIndexedOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( VectorList . RegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI ->


<s> switch ( RC -> getID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( isHReg ( Reg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT>


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = TM . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } FPUTopSavedRegOff = FPUBitmask ? ( HasAFGR64Reg ? - AFGR64RegSize : - FGR32RegSize ) : <NUM_LIT> ; CPUTopSavedRegOff = CPUBitmask ? - CSFPRegsSize - CPURegSize : <NUM_LIT> ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << CPUTopSavedRegOff << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask , O ) ; O << <STR_LIT> << FPUTopSavedRegOff


<s> return ( __m128d ) __builtin_ia32_vfmaddpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , - (


<s> SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR


<s> if ( NeedsWinCFI ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsUnwindInfo ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > (


<s> int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /=


<s> for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn ,


<s> return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) )


<s> bool HasRegForVL = false ; unsigned RegForVL ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ) { MachineBasicBlock :: iterator MI = I ; unsigned Reg = getVL ( * MI ) ; if ( Reg != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegName ( Reg ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( HasRegForVL ? RegName ( RegForVL ) : <STR_LIT> ) << <STR_LIT> ) ; if ( ! HasRegForVL || RegForVL != Reg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegName ( Reg ) << <STR_LIT> ) ; BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) ; HasRegForVL = true ; RegForVL = Reg ; Changed = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } if ( HasRegForVL ) { if ( MI -> definesRegister ( RegForVL , TRI ) || MI -> modifiesRegister ( RegForVL , TRI ) || MI -> killsRegister ( RegForVL , TRI ) || MI -> isCall ( ) ) { LLVM_DEBUG ( dbgs ( ) << RegName ( RegForVL ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; HasRegForVL = false ; } } ++ I ; } return Changed


<s> else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ; MI . getOperand ( OpNo + <NUM_LIT> )


<s> uint64_t getLocalStackSize ( ) const { return LocalStackSize


<s> if ( Subtarget -> isTargetNaCl64 ( ) ) return LowerToTLSNaCl64 ( GA , DAG , getPointerTy ( ) , model ) ; switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , getPointerTy ( ) , Subtarget -> is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : if ( llvm :: TLSUseCall && Subtarget -> isTargetNaCl ( ) ) { return LowerToTLSExecCall ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } else { return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) , getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; } } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit (


<s> const char * function_resolver :: get_scalar_type_name ( type_suffix_index type ) { return vector_types [ type_suffixes [ type ]


<s> vmull_s32 ( int32x2_t a , int32x2_t b ) { int64x2_t result


<s> } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned


<s> } Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Carry , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Result = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = emitSETCC ( DAG , DL , Result . getValue ( <NUM_LIT> ) , CCValid , CCMask ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL


<s> if ( TT . isOSDarwin ( ) ) return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; return llvm :: make_unique < <ISA_LIT>64LinuxTargetObjectFile > (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { SMLoc CurLoc = getLoc ( ) ; StringRef CPU , ExtensionString ; std :: tie ( CPU , ExtensionString ) = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) . split ( '+' ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( CurLoc , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; CurLoc = incrementLoc ( CurLoc , CPU . size ( ) ) ; ExpandCryptoAEK ( llvm :: <STR_LIT> ( CPU ) , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { CurLoc = incrementLoc ( CurLoc , <NUM_LIT> ) ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } bool FoundExtension = false ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; FoundExtension =


<s> SDValue getAddrGlobalLargeGOT ( NodeTy * N , EVT Ty , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDLoc DL ( N ) ; SDValue GetImm = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode (


<s> LHS = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , CmpVT . getVectorElementType ( ) , LHS , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , CmpVT . getVectorElementType ( ) , RHS , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SetCC = DAG . getSetCC ( SDLoc ( N ) , <STR_LIT> , LHS , RHS , cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) )


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionEntryLabel ( ) { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; const MCSection * Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName (


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: WebKit_JS : return CC_<ISA_LIT>_WebKit_JS ; case CallingConv :: GHC : return CC_<ISA_LIT>_GHC ; case CallingConv :: C : case CallingConv


<s> uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ,


<s> HOST_WIDE_INT locals_size = get_frame_size ( ) ; int regno ; HOST_WIDE_INT stack_space_to_deallocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; HOST_WIDE_INT offset = crtl -> outgoing_args_size ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) stack_space_to_deallocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_deallocate += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_deallocate += <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_deallocate += <NUM_LIT> ; if ( ( stack_space_to_deallocate % <NUM_LIT> ) != <NUM_LIT> ) internal_error

( <STR_LIT> , stack_space_to_deallocate ) ;


<s> return VRI . RLAmt == EffRLAmt ; } ; for ( auto & BG : BitGroups ) { if ( ! MatchingBG ( BG ) ) continue ; if ( BG . StartIdx <= BG . EndIdx ) { for ( unsigned i = BG . StartIdx ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } else { for ( unsigned i = BG . StartIdx ; i < Bits . size ( ) ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; for ( unsigned i = <NUM_LIT> ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } } bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; bool NeedsRotate = VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( bool ) Res ; if ( Use32BitInsts ) NumAndInsts += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; else NumAndInsts += getInt64Count ( Mask ) + <NUM_LIT> ; unsigned NumRLInsts = <NUM_LIT> ; bool FirstBG = true ; bool MoreBG = false ; for ( auto & BG : BitGroups ) { if ( ! MatchingBG ( BG ) ) { MoreBG = true ; continue ; } NumRLInsts += SelectRotMask64Count ( BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , ! FirstBG ) ; FirstBG = false ; } DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << ( VRI . Repl32 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << NumAndInsts << <STR_LIT> << NumRLInsts << <STR_LIT> ) ; if ( NumAndInsts > NumRLInsts ) continue ; if ( ( Use32BitInsts || MoreBG ) &&


<s> if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneCrossing [ <NUM_LIT> ] && LaneCrossing [ <NUM_LIT> ] ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneUsed [ <NUM_LIT> ] && LaneUsed [ <NUM_LIT> ] ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int & M = InLaneMask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( ( M % Size ) / LaneSize ) != ( i / LaneSize ) ) M = ( M % LaneSize ) + ( ( i / LaneSize ) * LaneSize ) + Size ; } assert ( ! is128BitLaneCrossingShuffleMask ( VT , InLaneMask ) && <STR_LIT> ) ; if ( ! AllLanes && ! is128BitLaneRepeatedShuffleMask ( VT , InLaneMask ) ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast ( PVT


<s> static bool isEqOrNe ( MachineInstr * BI ) { <STR_LIT> Pred = ( <STR_LIT> ) BI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredCond = <STR_LIT>


<s> bool useWideStrideVFP ( ) const { return


<s> return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode )


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getUNDEF ( Op . getValueType (

) ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> return true ; } if ( elt % <NUM_LIT> == <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( perm [ i ] != elt || perm [ i + <NUM_LIT> ] != elt + <NUM_LIT> ) break ; if ( i == <NUM_LIT> ) { int field = BYTES_BIG_ENDIAN ? elt / <NUM_LIT> : <NUM_LIT> - elt / <NUM_LIT> ; x = gen_reg_rtx ( V8HImode ) ; emit_insn ( gen_altivec_vsplth_direct ( x , gen_lowpart ( V8HImode , op0 ) , GEN_INT ( field ) ) ) ; emit_move_insn ( target , gen_lowpart ( V16QImode , x ) ) ; return true ; } } if ( elt % <NUM_LIT> == <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( perm [ i ] != elt || perm [ i + <NUM_LIT> ] != elt + <NUM_LIT> || perm [ i + <NUM_LIT> ] != elt + <NUM_LIT> || perm [ i + <NUM_LIT> ] != elt + <NUM_LIT> ) break ; if ( i == <NUM_LIT> ) { int field = BYTES_BIG_ENDIAN ? elt / <NUM_LIT> : <NUM_LIT> - elt / <NUM_LIT> ; x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_altivec_vspltw_direct ( x , gen_lowpart ( V4SImode , op0 ) , GEN_INT ( field ) ) ) ; emit_move_insn ( target , gen_lowpart ( V16QImode , x ) ) ; return true ; } } } for ( j = <NUM_LIT> ; j < ARRAY_SIZE ( patterns ) ; ++ j ) { bool swapped ; if ( ( patterns [ j ] . mask & rs6000_isa_flags ) == <NUM_LIT> ) continue ; elt = patterns [ j ] . perm [ <NUM_LIT> ] ; if ( perm [ <NUM_LIT> ] == elt ) swapped = false ; else if ( perm [ <NUM_LIT> ] == elt + <NUM_LIT> ) swapped = true ; else continue ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { elt = patterns [ j ] . perm [ i ] ; if ( swapped ) elt = ( elt >= <NUM_LIT> ? elt - <NUM_LIT> : elt + <NUM_LIT> ) ; else if ( one_vec && elt >= <NUM_LIT> ) elt -= <NUM_LIT> ; if ( perm [ i ] != elt ) break ; } if ( i == <NUM_LIT> ) { enum insn_code icode = patterns [ j ] . impl ; machine_mode omode = insn_data [ icode ] . operand [ <NUM_LIT>


<s> int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , ( int64_t ) FPDiff - SlotSize , false ) ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI


<s> if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . hasOneUse ( ) && IsLegalToFold ( N1 , Op , Op , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N1 ) ; if ( ! isValidIndexedLoad ( LD ) ) return NULL ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc32 : VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr


<s> static void sparc_dwarf_handle_frame_unspec ( const char * label , rtx pattern ATTRIBUTE_UNUSED , int index ATTRIBUTE_UNUSED ) { gcc_assert ( index == UNSPECV_SAVEW


<s> return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 ,


<s> setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT>


<s> unsigned PCLabelId = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = <NUM_LIT> ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) -> getContext ( ) , ACPV -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( ACPV -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV ,


<s> return ELF :: R_MIPS_PC19_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PC18_S3 ; case <STR_LIT> : return ELF :: R_MIPS_PC21_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PC26_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_GPRel_4 : if ( isN64 ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveZero = true ) { EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; unsigned NumElts = Op . getValueType ( )


<s> if ( Val < <NUM_LIT> || Val == CmpVal ) return true ; return false


<s> return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; return SDValue ( )


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode *


<s> if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; return EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , Op . getValueType ( ) , dl , DAG ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , Op . getValueType ( ) , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , Op . getValueType ( ) , dl ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerToBT ( SDValue Op , <STR_LIT> CC , const SDLoc & dl , SelectionDAG & DAG ) const { if ( Op . getOpcode ( ) == <STR_LIT> ) return LowerAndToBT ( Op , CC , dl , DAG ) ; if ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) return LowerTruncateToBT


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int32_t Imm = Memory . OffsetImm -> getValue ( ) ; if ( Imm == INT32_MIN ) Imm


<s> if ( processInstruction ( Inst , IDLoc , Instructions ) ) return true ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) Out . EmitInstruction ( Instructions [ i ] , STI ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresDifferentSrcAndDst : return Error ( IDLoc , <STR_LIT> ) ; } return true


<s> static unsigned CalculateStackSlotAlignment ( EVT ArgVT , EVT OrigVT , <STR_LIT> Flags , unsigned PtrByteSize ) { unsigned Align = PtrByteSize ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; else if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; if ( Flags . isByVal ( ) ) { unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > PtrByteSize ) { if ( BVAlign % PtrByteSize != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; Align = BVAlign ; } } if ( Flags . isInConsecutiveRegs ( ) ) { if ( Flags . isSplit ( ) && OrigVT != <STR_LIT> ) Align =


<s> return to == HARD_FRAME_POINTER_REGNUM ||


<s> crx_compute_save_regs ( ) ; crx_compute_frame ( ) ; if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : <NUM_LIT> ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == FRAME_POINTER_REGNUM ) return ( sum_regs + local_vars_size ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( sum_regs + local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size :


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const override { return true


<s> auto I = llvm :: lower_bound ( Ranges , Start , [ ] ( const Range & LHS , uint64_t RHS ) { return LHS . End <= RHS ; } ) ; if ( I != Ranges . end ( ) && End > I -> Start ) { return false ; } Ranges . insert ( I , { Start , End


<s> { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; aarch64_init_data_intrinsics ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( <STR_LIT> , ftype_jcvt


<s> const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) { if ( arm_disable_literal_pool ) sorry ( <STR_LIT> <STR_LIT> ) ; return


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrFI ( SDValue Addr , SDValue & Base ) const { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { EVT ValTy = Addr .


<s> if ( EFLAGS . getOpcode ( ) == <STR_LIT> ) { if ( isAllOnesConstant ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue Carry = EFLAGS . getOperand ( <NUM_LIT> ) ; while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) { uint64_t CarryCC = Carry . getConstantOperandVal ( <NUM_LIT> ) ; SDValue CarryOp1 = Carry . getOperand ( <NUM_LIT> ) ; if ( CarryCC == <STR_LIT> ) return CarryOp1 ; if ( CarryCC == <STR_LIT> ) { if ( CarryOp1 . getOpcode ( ) == <STR_LIT> && CarryOp1 . getNode ( ) -> hasOneUse ( ) && CarryOp1 . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( CarryOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue SubCommute = DAG . getNode ( <STR_LIT> , SDLoc ( CarryOp1 ) , CarryOp1 -> getVTList ( ) , CarryOp1 . getOperand ( <NUM_LIT> ) , CarryOp1 . getOperand ( <NUM_LIT> ) ) ; return SDValue ( SubCommute . getNode ( ) , CarryOp1 . getResNo ( ) ) ; } } if ( CarryCC == <STR_LIT> && CarryOp1 . getOpcode ( ) == <STR_LIT> && isOneConstant ( CarryOp1 . getOperand ( <NUM_LIT> ) ) ) return CarryOp1 ; } } } return SDValue (


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { SubOpc = <STR_LIT> ; SubRC = & <STR_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned NewVR = MRI . createVirtualRegister ( SubRC ) ; MachineInstrBuilder MIB1 = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( SubOpc ) , NewVR ) . addReg ( ZeroReg ) . addOperand ( Root . getOperand ( <NUM_LIT> ) ) ; InsInstrs . push_back ( MIB1 ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR , <NUM_LIT> ) ) ; MUL = genMaddR ( MF , MRI , TII , Root , InsInstrs , <NUM_LIT> , Opc , NewVR , RC ) ; break ; } case MachineCombinerPattern :: MC_MULSUBW_OP2 : case MachineCombinerPattern :: MC_MULSUBX_OP2 : if ( Pattern == MachineCombinerPattern :: MC_MULSUBW_OP2 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } MUL = genMadd ( MF , MRI , TII , Root , InsInstrs , <NUM_LIT> , Opc , RC ) ; break ; case MachineCombinerPattern :: MC_MULSUBWI_OP1 : case MachineCombinerPattern :: MC_MULSUBXI_OP1 : { const TargetRegisterClass * OrrRC ; unsigned BitSize , OrrOpc , ZeroReg ; if ( Pattern == MachineCombinerPattern :: MC_MULSUBWI_OP1 ) { OrrOpc = <STR_LIT> ; OrrRC = & <STR_LIT> ; BitSize = <NUM_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { OrrOpc = <STR_LIT> ; OrrRC = & <STR_LIT> ; BitSize = <NUM_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned NewVR = MRI . createVirtualRegister ( OrrRC ) ; int Imm = Root . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Root . getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned Val = Root . getOperand ( <NUM_LIT> ) . getImm ( ) ; Imm = Imm << Val ; } uint64_t UImm = - Imm << ( <NUM_LIT> - BitSize ) >> ( <NUM_LIT> - BitSize ) ; uint64_t Encoding ; if ( <STR_LIT> ( UImm , BitSize , Encoding ) ) { MachineInstrBuilder MIB1 = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( OrrOpc ) , NewVR ) . addReg ( ZeroReg ) . addImm ( Encoding ) ; InsInstrs . push_back ( MIB1 )


<s> return <ISA_LIT>Lowering . SelectAddressRegImmShift ( N , Disp ,


<s> static void ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl ,


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>16InstrInfo ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>16InstrInfo (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasDQI ( ) ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( NumOperands == <NUM_LIT> && RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> LLVMContext & Ctx = AI -> getContext ( ) ; unsigned Imm = countTrailingZeros ( cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; Function * BitTest = <STR_LIT> ( AI -> getModule ( ) , IID , AI -> getType ( ) ) ; Value * Addr = Builder . CreatePointerCast ( AI -> getPointerOperand ( ) , Type :: getInt8PtrTy ( Ctx ) ) ; Value * Result = Builder . CreateCall ( BitTest , { Addr , Builder . getInt8 ( Imm ) } ) ; I -> replaceAllUsesWith ( Result ) ; I -> eraseFromParent (


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst

, Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> u = Imm | ( Imm << <NUM_LIT> ) ; if ( Vs == u ) return ( ( ( Vs == V ) ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | Imm ; if ( Vs == ( u | ( u << <NUM_LIT> ) ) ) return ( <NUM_LIT> << <NUM_LIT>


<s> case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryStoreIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryStoreIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum ,


<s> assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; if ( Shift >= DstBits ) return <NUM_LIT> ; unsigned ImmR = RegSize - Shift ; unsigned ImmS = std :: min < unsigned > ( SrcBits - <NUM_LIT> , DstBits - <NUM_LIT> - Shift ) ; static const unsigned OpcTable [ <NUM_LIT>


<s> if ( TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , ( DECL_NAME ( caller ) ? IDENTIFIER_POINTER ( DECL_NAME ( caller ) ) : <STR_LIT> ) , ( DECL_NAME ( callee ) ? IDENTIFIER_POINTER ( DECL_NAME ( callee ) ) : <STR_LIT> ) , ( ret ? <STR_LIT> : <STR_LIT> ) ) ; return ret


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ,


<s> else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg ,


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) return Op ; if ( Src . getValueType ( ) == <STR_LIT> ) { if ( Op . getValueType ( ) == <STR_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) ,


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord


<s> int64_t Offset = TargetFrameLowering :: getFrameIndexReference ( MF


<s> SDLoc DL ( Op ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned Opcode = Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( Opcode != Op -> getOperand ( i ) . getOpcode ( ) ) return SDValue ( ) ; bool IsShift = false ; switch ( Opcode ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsShift = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT ) ) return SDValue ( ) ; break ; } SmallVector < SDValue , <NUM_LIT> > LHSElts , RHSElts ; for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; if ( RHS . getValueSizeInBits ( ) != VT . getScalarSizeInBits


<s> std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; std :: string AsmText ; AsmText += <STR_LIT> ; AsmText += swapFPIntParams ( PV , M , LE , true ) ; if ( RV != NoFPRet ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } else { AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } switch ( RV ) { case FRet : AsmText += <STR_LIT> ; break ; case DRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CFRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText +=


<s> static __inline int __get_cpuid ( unsigned int __level , unsigned int * __eax , unsigned int

* __ebx , unsigned int * __ecx , unsigned int * __edx ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( SDValue Res = tryCombineToEXTR ( N


<s> void addComplexRotationOddOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ( CE -> getValue (


<s> Reloc :: Model RelocM = TM . getRelocationModel ( ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) return <NUM_LIT> ; if ( ! isThumb && ( RelocM == Reloc :: PIC_ ) ) return <NUM_LIT> ; unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg

) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ;


<s> static unsigned getMatchingLoType ( const ELFRelocationEntry & Reloc ) { unsigned Type = Reloc . Type ; if ( Type == ELF :: R_MIPS_HI16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_HI16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_HI16 ) return ELF :: R_MIPS16_LO16 ; if ( Reloc . OriginalSymbol && Reloc . OriginalSymbol -> getBinding ( ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine (


<s> if ( ! C ) return nullptr ; int Addr = C -> getZExtValue ( ) ; if ( ( Addr & <NUM_LIT> ) != <NUM_LIT> || SignExtend32 < <NUM_LIT> > ( Addr ) != Addr ) return nullptr ; return DAG . getConstant ( ( int ) C -> getZExtValue ( ) >> <NUM_LIT> , DAG . getTargetLoweringInfo

( ) . getPointerTy ( ) ) . getNode ( ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success ; } if ( RegNo == <NUM_LIT> ) Check ( S , MCDisassembler :: SoftFail ) ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address ,


<s> return __builtin_mve_vmladavq_p_sv16qi ( __a ,


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { Triple TheTriple ( TT ) ; MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> unsigned Opcode = IsLoad ? <STR_LIT> : <STR_LIT> ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SecondReg = nextReg ( FirstReg ) ; unsigned BaseReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SecondReg ) return true ; warnIfRegIndexIsAT ( FirstReg , IDLoc ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; MCOperand & FirstOffset = Inst . getOperand ( <NUM_LIT> ) ; signed NextOffset = FirstOffset . getImm ( ) + <NUM_LIT> ; MCOperand SecondOffset = MCOperand :: createImm ( NextOffset ) ; if ( ! isInt < <NUM_LIT> > ( FirstOffset . getImm ( ) ) || ! isInt < <NUM_LIT> > ( NextOffset ) ) return true ; if ( FirstReg != BaseReg || ! IsLoad ) { TOut . emitRRX ( Opcode , FirstReg , BaseReg , FirstOffset ,


<s> return N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) && isa < ConstantSDNode > ( N

-> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return NULL ; EVT LoadedVT = LD -> getMemoryVT ( ) ; bool isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( Op , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl

< unsigned > & Ops , MachineInstr * LoadMI ) const {


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , STI , O ) ; return ; } const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 .


<s> if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT>


<s> __o = __builtin_aarch64_ld4v16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; return


<s> bool <ISA_LIT>RegisterInfo :: isFixedRegister ( const MachineFunction & MF , MCRegister PhysReg ) const { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST .


<s> case IES_XOR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case


<s> case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand ::


<s> void addGR32orGR64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getReg ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = getGR32FromGR64 (


<s> float64x1x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rdf ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o


<s> MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( LdarOp ) , Dest . getReg ( ) ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CmpOp ) , ZeroReg ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) . addImm ( ExtendImm ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( StlrOp ) , StatusReg ) . addOperand


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) /


<s> return __builtin_mve_vmovlbq_uv16qi (


<s> unsigned getRsaSize ( ) const { return


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack


<s> if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 's' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ]

== 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ;


<s> MVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( Subtarget -> isThumb ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT>


<s> bool isDirectBr ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > (

getImm ( ) ) && ( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; }


<s> } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = <NUM_LIT> ; credit -= get_attr_length ( prev ) ; } if ( prev && GET_CODE ( prev ) == JUMP_INSN && JUMP_LABEL ( prev ) ) { rtx x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? <NUM_LIT> : <NUM_LIT>


<s> Type * <ISA_LIT>TargetLowering :: shouldConvertSplatType ( ShuffleVectorInst * SVI ) const { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return nullptr ; Type * SVIType = SVI -> getType ( ) ; Type * ScalarType = SVIType -> getScalarType ( ) ; if ( ScalarType -> isFloatTy ( ) ) return Type :: getInt32Ty


<s> unsigned SubReg1 = <STR_LIT> , SubReg2 = <STR_LIT> ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( SubReg1 , SubReg2 ) ; SDValue Lo = DAG . getTargetExtractSubreg ( SubReg1 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( SubReg2 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Lo , Hi ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; return ; } unsigned Opcode ; switch ( MemOp -> getMergedOrdering ( ) ) { case AtomicOrdering :: Monotonic : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: Acquire : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: Release : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } auto Desired = splitInt128 ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; auto New = splitInt128 ( N -> getOperand


<s> APLength = APLength . zextOrTrunc ( <NUM_LIT> ) ; unsigned Index = APIndex . getZExtValue ( ) ; unsigned Length = APLength == <NUM_LIT> ? <NUM_LIT> : APLength . getZExtValue ( ) ; unsigned End = Index + Length ; if ( End > <NUM_LIT> ) return UndefValue :: get ( II . getType ( ) ) ; if ( ( Length % <NUM_LIT> ) == <NUM_LIT> && ( Index % <NUM_LIT> ) == <NUM_LIT> ) { Length /= <NUM_LIT> ; Index /= <NUM_LIT> ; Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; auto * ShufTy = FixedVectorType :: get ( IntTy8 , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; for ( int i = <NUM_LIT> ; i != ( int ) Index ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != ( int ) Length ; ++ i ) ShuffleMask . push_back ( i + <NUM_LIT> ) ; for ( int i = Index + Length ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( - <NUM_LIT> ) ; Value * SV = Builder . CreateShuffleVector ( Builder . CreateBitCast ( Op0 , ShufTy ) , Builder . CreateBitCast ( Op1 , ShufTy ) , ShuffleMask ) ; return Builder . CreateBitCast ( SV , II . getType ( ) ) ; } Constant * C0 = dyn_cast < Constant > ( Op0 ) ; Constant * C1 = dyn_cast < Constant > ( Op1 ) ; ConstantInt * CI00 = C0 ? dyn_cast_or_null < ConstantInt > ( C0 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; ConstantInt * CI10 = C1 ? dyn_cast_or_null < ConstantInt > ( C1 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; if ( CI00 &&


<s> SelectRoot ( * CurDAG ) ; CurDAG -> RemoveDeadNodes (


<s> return std :: find_if ( MBB -> begin ( ) , MBB -> end ( ) , [ ] ( MachineInstr & MI ) -> bool { return MI . getOpcode (


<s> static inline bool getAM4WBFlag ( unsigned Mode ) { return ( Mode >> <NUM_LIT> )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> OperandMatchResultTy parseBDXAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , <STR_LIT> , ADDR64Reg ,


<s> assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt * AndC = isPowerOf2Constant ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; KnownBits Known = DAG . computeKnownBits ( Y ) ; if ( ( OrCI & Known . Zero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX ,


<s> uws . next = ptr + <NUM_LIT> ; uws . bytes_left = <NUM_LIT> ; uws . words_left = ( ( * ptr ) >> <NUM_LIT> ) & <NUM_LIT> ; return __gnu_unwind_execute ( context ,


<s> HOST_WIDE_INT offset ; if ( loongarch_tls_symbol_p ( x ) ) return loongarch_legitimize_tls_address ( x ) ; loongarch_split_plus ( x , & base , & offset ) ; if ( offset != <NUM_LIT> ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL ,


<s> if ( missing_extensions == <NUM_LIT> ) return check_required_registers ( location , fndecl ) ; static const struct { aarch64_feature_flags flag ; const char * name ; } extensions [ ] = { { AARCH64_FL_ ## IDENT , EXT_NAME } , } ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( extensions ) ; ++ i ) if ( missing_extensions & extensions [ i ]


<s> SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Imm = Node -> getOperand ( <NUM_LIT> ) ; const ConstantInt * Val = cast < ConstantSDNode > ( Imm ) -> getConstantIntValue ( ) ; Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && N1 -> getOpcode ( ) == <STR_LIT> && N1 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N1 . getNode ( ) , N1 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N1 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( Load . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < LoadSDNode > ( Load ) -> getMemOperand ( ) ; CNode -> setMemRefs ( MemOp , MemOp +


<s> bool SelectAddrModeUnscaled64 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeUnscaled ( N , <NUM_LIT> , Base


<s> if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == <STR_LIT> ) { if ( int CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; CalleeAmt *= - <NUM_LIT> ; unsigned StackReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase (


<s> const char * RecipOp ; if ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) RecipOp = <STR_LIT> ; else if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) RecipOp = <STR_LIT> ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; UseOneConstNR =


<s> switch ( BrOpc ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i )


<s> emit_cmp_and_jump_insns ( index , range , GTU , NULL_RTX , SImode , <NUM_LIT> , default_label ) ; int_index = gen_lowpart_common ( HImode , index ) ; emit_insn ( gen_ashlhi3 ( int_index , int_index ,


<s> return ( float32x2_t ) __builtin_neon_vmla_lanev2sf ( __a ,


<s> if ( GET_CODE ( op ) != CONST_VECTOR || GET_MODE ( op ) != mode ) return false ; first = CONST_VECTOR_ELT ( op , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) if ( ! rtx_equal_p ( first , CONST_VECTOR_ELT ( op , i ) ) ) return false ; return true


<s> unsigned Align = MF . getFrameInfo ( ) -> getObjectAlignment ( FI ) ; assert ( ( - ( Offset + StackSize ) ) % Align == <NUM_LIT> ) ; Align = <NUM_LIT> ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset +


<s> addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; * offset = <NUM_LIT> ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , <NUM_LIT> ) ) ; addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; } if ( ! REG_P ( addr_rtx ) ) return false ; * base =


<s> if ( CC >= LPCC :: UNKNOWN ) OS << <STR_LIT> ; else OS << <ISA_LIT>CondCodeToString ( CC


<s> if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ; if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type ==

GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get


<s> } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; if ( mode != BLKmode ) { rtx tmp_reg = gen_reg_rtx ( mode ) ; emit_insn ( ( * gen_func . mov ) ( tmp_reg , src ) ) ; stores [ num_reg ++ ] = ( * gen_func . mov ) ( dest , tmp_reg ) ; } if ( mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes ) { int i ; for ( i = <NUM_LIT> ; i < num_reg ; i ++ ) emit_insn ( stores [ i ] ) ; num_reg = <NUM_LIT> ; } if ( mode == BLKmode ) { if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) ) { rtx src_reg = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; src = replace_equiv_address ( src , src_reg ) ; } set_mem_size ( src , move_bytes ) ; if ( ! REG_P ( XEXP ( dest , <NUM_LIT> ) ) ) { rtx dest_reg = copy_addr_to_reg ( XEXP ( dest , <NUM_LIT> ) ) ; dest = replace_equiv_address ( dest , dest_reg ) ; } set_mem_size ( dest , move_bytes


<s> else if ( el_mode == SFmode && n == <NUM_LIT> ) { name [ <NUM_LIT> ] = 's' ; name [ <NUM_LIT> ] = '4' ; } else return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; sprintf ( name + <NUM_LIT> , <STR_LIT> , bname + <NUM_LIT> ) ; arity = <NUM_LIT> ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ;


<s> for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) if ( N -> getOperand


<s> llvm :: FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo


<s> bool isVectorIndexS ( ) const { return Kind == k_VectorIndex && VectorIndex .


<s> bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM ,


<s> case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: SwiftTail : return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList : CSR_64_SwiftError_SaveList ; if ( IsWin64 ) return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList


<s> MaskVal = MaskVal . trunc ( <NUM_LIT> ) ; } SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( MaskVal . getBitWidth ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ; unsigned MinWidth = NegMaskVal . getMinSignedBits ( ) ; if ( MinWidth > <NUM_LIT> || ( MinWidth > <NUM_LIT> && MaskVal . getMinSignedBits ( ) <= <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> && MaskVal . getBitWidth ( ) < <NUM_LIT> ) { NegMaskVal = NegMaskVal . zext ( <NUM_LIT> ) ; HighZeros = HighZeros . zext ( <NUM_LIT> ) ; } if ( ! CurDAG -> MaskedValueIsZero ( And0 , HighZeros ) ) return false ; if ( NegMaskVal . isAllOnesValue (


<s> return ( uint32x4_t ) __builtin_neon_vmlslu_lanev4hi ( ( int32x4_t ) __a , (


<s> DWORD tls_index = TlsAlloc ( ) ; if ( tls_index != <NUM_LIT> ) { * key = tls_index ; status = __mingwthr_key_dtor ( * key , dtor ) ; } else status = ( int ) GetLastError ( ) ; return status


<s> static void updateOperandRegConstraints ( MachineFunction & MF , MachineInstr & NewMI , const TargetInstrInfo & TII ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; for ( int Idx : llvm :: seq < int > ( <NUM_LIT> , NewMI . getNumOperands ( ) ) ) { MachineOperand & MO = NewMI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg . isVirtual ( ) ) continue ; auto * NewRC = MRI . constrainRegClass ( Reg , TII . getRegClass ( NewMI . getDesc ( ) , Idx , & TRI , MF ) ) ; if ( ! NewRC )


<s> void addLogicalImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr >


<s> <ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg ) ; return Generated . tryCombineAll ( Observer , MI , B


<s> if ( SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getValueType ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && isNullConstant ( SrcOp . getOperand ( <NUM_LIT> ) ) ) N = SrcOp . getNode ( ) ; } SDValue HOp = N -> getOperand ( <NUM_LIT> ) ; if ( HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> && HOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && HOp . getOperand ( <NUM_LIT> ) != HOp . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; auto updateHOp = [ ] ( SDValue HorizOp , SelectionDAG & DAG ) { SDValue X ; if ( HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) ) { assert ( ! HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; X = HorizOp . getOperand ( <NUM_LIT> ) ; } else if ( HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) ) { assert ( ! HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; X = HorizOp . getOperand (


<s> const int mov_insn_sz = mov_insn_size ( mode , false ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , false ) ; const int max_disp_next = max_disp + mov_insn_sz ; HOST_WIDE_INT align_modifier = offset > <NUM_LIT> ? mov_insn_sz : <NUM_LIT> ; HOST_WIDE_INT offset_adjust ; if ( mode_sz < <NUM_LIT> || mode_sz > <NUM_LIT> || max_disp < <NUM_LIT> ) return res ; if ( mov_insn_sz == <NUM_LIT> ) align_modifier = <NUM_LIT> ; offset_adjust = ( ( offset + align_modifier ) & ~ max_disp ) - align_modifier ; if ( mode_sz + offset - offset_adjust <= max_disp_next ) { res . offset_adjust = GEN_INT ( offset_adjust ) ; res . mov_disp = GEN_INT ( offset - offset_adjust ) ; } return


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain


<s> void <ISA_LIT>CodeEmitter :: emitMiscArithInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } unsigned OpIdx = <NUM_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( ) || MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary ) ; return ; } Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( MCID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ; Binary |= ShiftAmt << <STR_LIT> ; emitWordLE ( Binary


<s> SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand ( <NUM_LIT> ) ; if ( NegC ) C = C . getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( ! NegMul ) Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , dl , VT , A