<s> INIT_CUMULATIVE_ARGS ( cum , funtype , NULL_RTX , <NUM_LIT> , <NUM_LIT> ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) structure_value_byref = <NUM_LIT> ; if ( structure_value_byref && sh_struct_value_rtx ( function , <NUM_LIT> ) == <NUM_LIT> ) { tree ptype = build_pointer_type ( TREE_TYPE ( funtype ) ) ; sh_function_arg_advance ( pack_cumulative_args ( & cum ) , Pmode , ptype , true ) ; } this_rtx = sh_function_arg ( pack_cumulative_args ( & cum ) , Pmode , ptr_type_node , true ) ; if ( ! call_used_regs [ <NUM_LIT> ] || fixed_regs [ <NUM_LIT> ] ) error ( <STR_LIT> ) ; scratch0 = scratch1 = scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; { if ( call_used_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) scratch1 = gen_rtx_REG ( ptr_mode , <NUM_LIT> ) ; if ( call_used_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; } this_value = plus_constant ( Pmode , this_rtx , delta ) ; if ( vcall_offset && ( simple_add || scratch0 != scratch1 ) && strict_memory_address_p ( ptr_mode , this_value ) ) { emit_load_ptr ( scratch0 , this_value ) ; did_load = <NUM_LIT> ; } if ( ! delta ) ; else if ( simple_add ) emit_move_insn ( this_rtx , this_value ) ; else { emit_move_insn ( scratch1 , GEN_INT ( delta ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch1 ) ) ; } if ( vcall_offset ) { rtx offset_addr ; if ( ! did_load ) emit_load_ptr ( scratch0 , this_rtx ) ; offset_addr = plus_constant ( Pmode , scratch0 , vcall_offset ) ; if ( strict_memory_address_p ( ptr_mode , offset_addr ) ) ; else if ( scratch0 != scratch1 ) { emit_move_insn ( scratch1 , GEN_INT (


<s> static void seh_emit_push ( FILE * f , struct seh_frame_state * seh , rtx reg ) { unsigned int regno = REGNO ( reg ) ; gcc_checking_assert ( GENERAL_REGNO_P ( regno ) ) ; seh -> sp_offset += UNITS_PER_WORD ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += UNITS_PER_WORD ; fputs ( <STR_LIT> , f ) ; print_reg ( reg , <NUM_LIT> , f ) ; fputc ( '\n' , f


<s> return n8_consumed_by_addr_in_p ( consumer


<s> } State = ( Name == <STR_LIT> ? EMS_Text : EMS_Data ) ; auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; emitLabel ( Symbol


<s> if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType


<s> gcc_assert ( compute_now == ( pic_reg != NULL_RTX ) ) ; if ( SYMBOL_REF_P ( orig ) || LABEL_REF_P ( orig ) ) { if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } rtx_insn * insn ; if ( ( LABEL_REF_P ( orig ) || ( SYMBOL_REF_P ( orig ) && SYMBOL_REF_LOCAL_P ( orig ) && ( SYMBOL_REF_DECL ( orig ) ? ! DECL_WEAK ( SYMBOL_REF_DECL ( orig ) ) : <NUM_LIT> ) && ( ! SYMBOL_REF_FUNCTION_P ( orig ) || arm_fdpic_local_funcdesc_p ( orig ) ) ) ) && NEED_GOT_RELOC && arm_pic_data_is_text_relative ) insn = arm_pic_static_addr ( orig , reg ) ; else { require_pic_register ( pic_reg , compute_now ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; return orig ; } if ( reg


<s> for ( std :: list < MachineInstr * > :: iterator iter = instrs . begin ( ) ; iter != instrs . end ( ) ; ++ iter ) { MBB -> remove ( * iter ) ; MBB -> insert ( I , * iter ) ; } instrs . clear (


<s> rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , global_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence (


<s> MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = FIOperandNum + <NUM_LIT> ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp .


<s> unsigned GlobalBaseReg = TM . getInstrInfo ( ) ->


<s> } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> >


<s> return In64BitMode && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl (


<s> UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD =


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS8 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS16

) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS32 ) . Default ( - <NUM_LIT> ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return new <ISA_LIT>_64MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( TT . isOSLinux ( ) ) return new


<s> if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ; MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT>


<s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; SmallVector < MachineOperand , <NUM_LIT> > CondPrior ; MachineFunction :: iterator BBi = BB -> getIterator ( ) ; MachineFunction :: iterator OldPrior = std :: prev ( BBi ) ; bool B = TII -> AnalyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != MF -> begin ( ) && ! TII -> AnalyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB ->


<s> return isMemDisp12 ( BDRMem , ADDR64Reg )


<s> if ( InVT . getVectorElementType ( ) != <STR_LIT> || N01 . getValueType ( ) != InVT || N10 . getValueType ( ) != InVT || N11 . getValueType ( ) != InVT ) return SDValue ( ) ; if ( N00 . getOpcode ( ) != <STR_LIT> || N01 . getOpcode ( ) != <STR_LIT> || N10 . getOpcode ( ) != <STR_LIT> || N11 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue In0 , In1 ; for ( unsigned i = <NUM_LIT> ; i != N00 . getNumOperands ( ) ; ++ i ) { SDValue N00Elt = N00 . getOperand ( i ) ; SDValue N01Elt = N01 . getOperand ( i ) ; SDValue N10Elt = N10 . getOperand ( i ) ; SDValue N11Elt = N11 . getOperand ( i ) ; if ( N00Elt . getOpcode ( ) != <STR_LIT> || N01Elt . getOpcode ( ) != <STR_LIT> || N10Elt . getOpcode ( ) != <STR_LIT> || N11Elt . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * ConstN00Elt = dyn_cast < ConstantSDNode > ( N00Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN01Elt = dyn_cast < ConstantSDNode > ( N01Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN10Elt = dyn_cast < ConstantSDNode > ( N10Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN11Elt = dyn_cast < ConstantSDNode > ( N11Elt . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstN00Elt || ! ConstN01Elt || ! ConstN10Elt || ! ConstN11Elt ) return SDValue ( ) ; unsigned IdxN00 = ConstN00Elt -> getZExtValue ( ) ; unsigned IdxN01 = ConstN01Elt -> getZExtValue ( ) ; unsigned IdxN10 = ConstN10Elt -> getZExtValue ( ) ; unsigned IdxN11 = ConstN11Elt -> getZExtValue ( ) ; if ( IdxN00 > IdxN10 ) { std :: swap ( IdxN00 , IdxN10 ) ; std :: swap ( IdxN01 , IdxN11 ) ; } if ( IdxN00 != <NUM_LIT> * i || IdxN10 != <NUM_LIT> * i + <NUM_LIT> || IdxN01 != <NUM_LIT> * i || IdxN11 != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; SDValue N00In = N00Elt . getOperand ( <NUM_LIT> ) ; SDValue N01In = N01Elt . getOperand ( <NUM_LIT> ) ; SDValue N10In = N10Elt . getOperand ( <NUM_LIT> ) ; SDValue N11In = N11Elt . getOperand ( <NUM_LIT> ) ; if ( ! In0 ) { In0 = N00In ; In1 =


<s> SDValue CC = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , One , Zero


<s> void addMemoryRegisterOffset128Operands ( MCInst & Inst , unsigned N ) { addMemoryRegisterOffsetOperands ( Inst , N , Mem . ShiftVal ==


<s> for ( scan = get_insns ( ) ; scan != NULL_RTX ; scan = NEXT_INSN ( scan ) ) if ( GET_CODE ( scan ) == NOTE && NOTE_LINE_NUMBER ( scan ) == NOTE_INSN_FUNCTION_BEG ) break ; if ( scan == NULL_RTX ) scan = get_insns ( ) ; insn = emit_insn_after ( insn , scan ) ; pop_topmost_sequence (


<s> unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back (


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) &&


<s> if ( Subtarget -> hasNEON ( ) && emitFPU ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! UnsafeFPMath ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( NoInfsFPMath && NoNaNsFPMath ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <NUM_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> ,


<s> return pParent . getTarget ( ) . getGOT ( )

. addr ( ) + got_entry -> getOffset ( ) ;


<s> static DecodeStatus decodePredicateOperand ( MCInst & Inst , unsigned Val , uint64_t

Address , const MCDisassembler * Decoder ) {


<s> SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses < int >


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const std :: string & TT ) { switch ( Triple ( TT ) . getOS ( ) ) { case Triple :: Darwin : return new Darwin<ISA_LIT>_32AsmBackend ( T ) ; case Triple :: MinGW32 : case Triple ::


<s> auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , PtrVT , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc (


<s> void <ISA_LIT>AsmPrinter :: printDecimal16 ( unsigned Value , raw_ostream & O ) { O <<


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) ,

GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , SpilledCSRegs ( MF . getTarget ( ) . getRegisterInfo ( ) -> getNumRegs ( ) ) , JumpTableUId ( <NUM_LIT> ) , ConstPoolEntryUId ( <NUM_LIT> ) {


<s> unsigned <ISA_LIT>COFFTargetAsmInfo :: PreferredEHDataFormat ( DwarfEncoding :: Target Reason , bool Global ) const { CodeModel :: Model CM = TM . getCodeModel ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { unsigned Format = <NUM_LIT> ; if ( ! is64Bit ) Format


<s> <ISA_LIT>InstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + <NUM_LIT> )

. getImm ( ) , MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) , OS ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode *


<s> if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; } XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( new_reg ) , new_reg , and_mask ) ; SET_SRC ( body ) =


<s> } emit_insn ( insn ) ; if ( TARGET_64BIT ) insn = gen_tls_tprel_lo_64 ( dest , tmp , addr ) ; else insn = gen_tls_tprel_lo_32 ( dest , tmp , addr ) ; emit_insn ( insn ) ; } else { rtx got , tga , tmp1 , tmp2 ; if ( TARGET_64BIT ) got = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else { if ( flag_pic == <NUM_LIT> ) got = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; else { rtx gsym = rs6000_got_sym ( ) ; got = gen_reg_rtx ( Pmode ) ; if ( flag_pic == <NUM_LIT> ) rs6000_emit_move ( got , gsym , Pmode ) ; else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr , got ) , UNSPEC_TLSGD ) ; tga = rs6000_tls_get_addr ( ) ; global_tlsarg = arg ; if ( TARGET_TLS_MARKERS ) { rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , argreg , Pmode ) ; } else emit_library_call_value ( tga , dest , LCT_CONST ,


<s> break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Printer . MF -> getContext ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! LdSt -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; BaseReg = LdSt -> getOperand ( <NUM_LIT> ) . getReg


<s> val = INTVAL ( first ) ; first_byte = val & <NUM_LIT> ; for ( i = <NUM_LIT> ; i < bytes ; i ++ ) { val >>= <NUM_LIT> ; if ( ( val & <NUM_LIT> ) != first_byte ) return false ; } return true


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_epi64 ( long long int const * base , __m128i index , const int scale ) { __v2di src = __extension__ ( __v2di


<s> return parseRegister ( Operands , RegCR , <STR_LIT>


<s> bool isTargetWindowsCoreCLR ( ) const { return TargetTriple . isWindowsCoreCLREnvironment


<s> bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , HalfSize , HalfSize , Half *


<s> if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++


<s> if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i *

<NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) ) return false ;


<s> return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : if ( VT == <STR_LIT> ) { ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnesValue ( )


<s> unsigned DemoteRegTo32_ ( unsigned RegIn ) { if ( RegIn == <NUM_LIT> )


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction &


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . else_blk ( ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT

) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ;


<s> if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return SImode ; return mode


<s> MF = & mf ; MCP = mf . getConstantPool ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) || ! <ISA_LIT>Subtarget :: useConstantIslands ( ) ) { return false ; } TII = ( const <ISA_LIT>16InstrInfo * ) MF -> getTarget ( ) . getInstrInfo ( ) ; MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! PrescannedForConstants ) prescanForConstants ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) )


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg ,


<s> if ( <ISA_LIT>ScalarSSEf32 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment . value ( ) ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT


<s> bool hardenSlsNoComdat ( ) const { return HardenSlsNoComdat


<s> const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) ) ; return res


<s> static bool expandNOVLXStore ( MachineInstrBuilder & MIB , const TargetRegisterInfo * TRI , const MCInstrDesc & StoreDesc , const MCInstrDesc & ExtractDesc , unsigned SubIdx ) { Register SrcReg = MIB -> getOperand ( <STR_LIT> ) . getReg ( ) ; if ( TRI -> getEncodingValue ( SrcReg ) < <NUM_LIT> ) { MIB -> setDesc ( StoreDesc ) ; } else { MIB -> setDesc ( ExtractDesc ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <STR_LIT> ) . setReg ( SrcReg ) ; MIB . addImm (


<s> rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label )


<s> void addImm0_508s4NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitLoadAndTestCmp0 ( MachineInstr & MI , MachineBasicBlock * MBB , unsigned Opcode ) const { MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned SrcReg = MI . getOperand (


<s> if ( aarch64_simd_decl_p ( cfun -> decl ) && ! crtl -> is_leaf ) return false ; return


<s> if ( <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ( ImmValue & <NUM_LIT> ) == ImmValue ) { tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; createShiftOr < <NUM_LIT> , true > ( ImmValue , RegOp . getReg


<s> uint64_t Immed = cast < ConstantSDNode > ( N . getNode ( ) ) -> getZExtValue ( ) ; unsigned ShiftAmt ; if ( Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; } else if ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; Immed = Immed >> <NUM_LIT> ; } else return false ; unsigned ShVal = <STR_LIT> ( <STR_LIT>


<s> if ( ! Def ) return false ; Register DefDstReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DefDstTy = MRI . getType ( DefDstReg ) ; Register StoreSrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT StoreSrcTy = MRI . getType ( StoreSrcReg ) ; if ( ! DefDstTy . isValid ( ) ) return false ; if ( DefDstTy . getSizeInBits ( ) != StoreSrcTy . getSizeInBits ( ) ) return false ; if ( RBI . getRegBank ( StoreSrcReg , MRI , TRI ) == RBI . getRegBank ( DefDstReg , MRI , TRI ) ) return false ; I . getOperand ( <NUM_LIT> ) . setReg ( DefDstReg ) ; return


) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( Pattern == <STR_LIT> ) { LLVMContext & Ctx = II . getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( & II ) ; Constant * StepVal = ConstantInt :: get ( II . getType ( ) , NumElts ) ; auto * VScale = Builder . CreateVScale ( StepVal ) ; VScale -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , VScale ) ; } unsigned MinNumElts = getNumElementsFromSVEPredPattern ( Pattern ) ; return MinNumElts && NumElts >= MinNumElts ? Optional < Instruction * > ( IC . replaceInstUsesWith ( II , ConstantInt :: get ( II . getType ( ) , MinNumElts )


<s> return DAG . ComputeMinSignedBits ( V ) <= <NUM_LIT> ; } ; auto IsZext = [ & DAG ] ( SDValue V ) { return DAG . computeKnownBits ( V ) . countMaxActiveBits ( ) <= <NUM_LIT> ; } ; bool IsSigned = IsSext ( LHS ) && IsSext ( RHS ) ; bool IsUnsigned = IsZext ( LHS ) && IsZext ( RHS ) ; if ( ! IsSigned && ! IsUnsigned ) return SDValue ( ) ; bool IsTruncateFree = ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && RHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ; unsigned InSizeInBits = InVT . getSizeInBits ( ) ; if ( IsUnsigned && ! IsTruncateFree && Subtarget . hasInt256 ( ) && ! ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && VT . is256BitVector ( ) ) && ( InSizeInBits % <NUM_LIT> ) == <NUM_LIT> ) { EVT BCVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , BCVT , DAG . getBitcast ( BCVT , LHS ) , DAG . getBitcast ( BCVT , RHS ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( InVT , Res ) ) ; } LHS = DAG . getNode ( <STR_LIT> ,


<s> work_register = thumb_find_work_register ( live_regs_mask ) ; if ( ARM_EABI_UNWIND_TABLES ) asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , SP_REGNUM ) ; if ( dwarf2out_do_frame ( ) ) { char * l = dwarf2out_cfi_label ( ) ; cfa_offset = cfa_offset + <NUM_LIT> ; dwarf2out_def_cfa ( l , SP_REGNUM , cfa_offset ) ; } if ( l_mask ) { thumb_pushpop ( f , l_mask , <NUM_LIT> , & cfa_offset , l_mask ) ; offset = bit_count ( l_mask ) * UNITS_PER_WORD ; } else offset = <NUM_LIT> ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> + current_function_pretend_args_size ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> ) ; if ( l_mask ) { asm_fprintf ( f , <STR_LIT> , work_register , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> ) ; asm_fprintf ( f , <STR_LIT> , work_register , ARM_HARD_FRAME_POINTER_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset ) ; } else { asm_fprintf ( f , <STR_LIT> , work_register , ARM_HARD_FRAME_POINTER_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset ) ; asm_fprintf ( f , <STR_LIT> , work_register , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> ) ; } asm_fprintf ( f , <STR_LIT> , work_register , LR_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> ) ; asm_fprintf ( f , <STR_LIT> , work_register , SP_REGNUM , offset + <NUM_LIT> ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , work_register ) ; } else if ( ( l_mask & <NUM_LIT> ) != <NUM_LIT> || ( high_regs_pushed == <NUM_LIT> && l_mask ) ) thumb_pushpop ( f , l_mask , <NUM_LIT> , & cfa_offset , l_mask ) ; if ( high_regs_pushed ) { unsigned


<s> if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) ||

STI . isFP64bit ( ) ) ) TS . emitDirectiveModuleFP ( ) ;


<s> printAndVerify ( <STR_LIT> ) ; } if ( get<ISA_LIT>Subtarget ( ) . hasNEON ( ) ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID


<s> if ( Reg > <NUM_LIT> ) return false ; aTReg =


<s> static bool resolveTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG ) { if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs


<s> int LastLoadedElt = - <NUM_LIT> ; SmallBitVector LoadMask ( NumElems , false ) ; SmallBitVector ZeroMask ( NumElems , false ) ; SmallBitVector UndefMask ( NumElems , false ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { SDValue Elt = peekThroughBitcasts ( Elts [ i ] ) ; if ( ! Elt . getNode ( ) ) return SDValue ( ) ; if ( Elt . isUndef ( ) ) UndefMask [ i ] = true ; else if ( <STR_LIT> ( Elt ) || <STR_LIT> ( Elt . getNode ( ) ) ) ZeroMask [ i ] = true ; else if ( <STR_LIT> ( Elt . getNode ( ) ) ) { LoadMask [ i ] = true ; LastLoadedElt = i ; if ( ( NumElems * Elt . getValueSizeInBits ( ) ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; } else return SDValue ( ) ; } assert ( ( ZeroMask | UndefMask | LoadMask ) . count ( ) == NumElems && <STR_LIT> ) ; if ( UndefMask . count ( ) == NumElems ) return DAG . getUNDEF ( VT ) ; if ( ( ZeroMask | UndefMask ) . count ( ) == NumElems ) return VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; int FirstLoadedElt = LoadMask . find_first ( ) ; SDValue EltBase = peekThroughBitcasts ( Elts [ FirstLoadedElt ] ) ; LoadSDNode * LDBase = cast < LoadSDNode > ( EltBase ) ; EVT LDBaseVT = EltBase . getValueType ( ) ; bool IsConsecutiveLoad = true ; bool IsConsecutiveLoadWithZeros = true ; for ( int i = FirstLoadedElt + <NUM_LIT> ; i <= LastLoadedElt ; ++ i ) { if ( LoadMask [ i ] ) { SDValue Elt = peekThroughBitcasts ( Elts [ i ] ) ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . areNonVolatileConsecutiveLoads ( LD , LDBase , Elt . getValueType ( ) . getStoreSizeInBits ( ) / <NUM_LIT> , i - FirstLoadedElt ) ) { IsConsecutiveLoad = false ; IsConsecutiveLoadWithZeros = false ; break ; } } else if ( ZeroMask [ i ] ) { IsConsecutiveLoad = false ; } } auto CreateLoad = [ & DAG , & DL ] ( EVT VT , LoadSDNode * LDBase ) { auto MMOFlags = LDBase -> getMemOperand ( ) -> getFlags ( ) ; assert ( ! ( MMOFlags & MachineMemOperand :: MOVolatile ) && <STR_LIT> ) ; SDValue NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , MMOFlags ) ; DAG . makeEquivalentMemoryOrdering ( LDBase , NewLd ) ; return NewLd


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MI ,


<s> RegisterMCAsmInfoFn Y ( The<ISA_LIT>elTarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend (


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lzcnt32 ( unsigned int __X ) { return __builtin_ia32_lzcnt_u32 (


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregciv2di (


<s> if ( PTR_IN ( emergency_reg_state , rs ) ) atomic_free ( & emergency_reg_state_free ,


<s> if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > <NUM_LIT> ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7


<s> if ( Pmode == DImode ) ASSERT_RTL_DUMP_EQ_WITH_REUSE ( <STR_LIT>

<STR_LIT> <STR_LIT> <STR_LIT> , pat , & r ) ;


<s> static const MCPhysReg RegListGPR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ] =


<s> unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT>

) . addReg ( Fs ) . addImm ( <STR_LIT> ) ;


<s> void printlea64_32mem ( const MachineInstr * MI , unsigned OpNo ) { printMemReference ( MI , OpNo


<s> void <ISA_LIT>AsmParser :: expandLoadAddressImm ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { MCInst tmpInst ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp .


<s> inline vector unsigned short vec_mladd ( vector unsigned short a1 , vector unsigned short a2 , vector unsigned short a3 ) { return ( vector unsigned short ) __builtin_altivec_vmladduhm ( ( vector signed short ) a1 , ( vector signed short ) a2 ,


<s> return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , ( (


<s> } else if ( i == <NUM_LIT> ) { if ( ( firstMVT == <STR_LIT> ) || ( firstMVT == <STR_LIT> ) ) { if ( ArgVT == <STR_LIT> ) { VA . convertToReg ( <STR_LIT> ) ; } else if ( ArgVT == <STR_LIT> ) { VA . convertToReg ( <STR_LIT> ) ; } } } if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType


<s> inline unsigned getRegAsGR64 ( unsigned Reg


<s> } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable ; else InstTable = ReverseSTiTable ; } int Opcode = Lookup ( InstTable , MI . getOpcode ( ) ) ; assert ( Opcode != - <NUM_LIT> && <STR_LIT> ) ; unsigned NotTOS = ( TOS == Op0 ) ? Op1 : Op0 ; MBB -> remove ( & * I ++ ) ; I = BuildMI ( * MBB , I , dl , TII -> get ( Opcode ) ) . addReg ( getSTReg ( NotTOS ) ) ; if ( ! MI . mayRaiseFPException ( ) ) I -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; if ( KillsOp0 && KillsOp1 && Op0 != Op1 ) { assert ( ! updateST0 && <STR_LIT> ) ; popStackAfter ( I ) ; } unsigned UpdatedSlot = getSlot ( updateST0 ? TOS : NotTOS ) ; assert ( UpdatedSlot < StackTop && Dest < <NUM_LIT> ) ; Stack [ UpdatedSlot ] =


<s> count = <NUM_LIT> ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS ) count ++ ; else count


<s> MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackPtr ) . addReg ( physSPReg ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; const unsigned XORMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( XORMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB ) ; BuildMI ( tailMBB , DL , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FinalStackPtr ) ; tailMBB -> splice ( tailMBB -> end ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( testMBB ) ; MI . eraseFromParent ( )


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 ,


<s> unsigned Opcode , CCValid ; if ( CmpOp0 . getOpcode ( ) == <STR_LIT> && CmpOp0 . getResNo ( ) == <NUM_LIT> && CmpOp0 -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) && isIntrinsicWithCCAndChain ( CmpOp0 , Opcode , CCValid ) ) return getIntrinsicCmp ( DAG , Opcode , CmpOp0 , CCValid , Constant , Cond ) ; } Comparison C ( CmpOp0 , CmpOp1 ) ; C . CCMask = CCMaskForCondCode ( Cond ) ; if ( C . Op0 . getValueType ( ) . isFloatingPoint ( ) ) { C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; adjustForFNeg ( C ) ; } else { C . CCValid =


<s> return RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC

. hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr &


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> __inline__ static unsigned long long sh_media_MSHARD_L ( unsigned long long mm , unsigned int


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case


<s> assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; auto I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; UpdateOther . clear


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( frame_size > PROBE_INTERVAL && frame_size > STACK_CHECK_PROTECT ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size - STACK_CHECK_PROTECT ) ; } else if ( frame_size > <NUM_LIT> ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size ) ; } aarch64_sub_sp ( IP0_REGNUM , initial_adjust , true ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; if ( frame_pointer_needed ) { if ( callee_adjust == <NUM_LIT> ) aarch64_save_callee_saves ( DImode , callee_offset , R29_REGNUM , R30_REGNUM , false ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT


<s> return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm (


<s> unsigned TUnpredCost = Probability . getNumerator ( ) * TCycles ; TUnpredCost /= Probability . getDenominator ( ) ; uint32_t Comp = Probability . getDenominator ( ) - Probability . getNumerator ( ) ; unsigned FUnpredCost = Comp * FCycles ; FUnpredCost /= Probability . getDenominator ( ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += <NUM_LIT> ; UnpredCost += Subtarget . getMispredictionPenalty ( ) /


<s> case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , &


<s> case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR82 : case CortexX1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT>


<s> if ( ( flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POWER10 ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( rs6000_aix_extabi ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P9_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FLOAT128_KEYWORD ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( define_p ) rs6000_define_or_undefine_macro (


<s> static DecodeStatus DecodeGPR64noxzrRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo

, uint64_t Address , const void * Decoder ) {


<s> return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( <STR_LIT> , Ty ) , DAG . getNode ( <STR_LIT> , DL


<s> return ( poly8x8_t ) __builtin_neon_vdup_nv8qi ( ( __builtin_neon_qi


<s> return getTM < Dcpu16TargetMachine > ( )


<s> auto * PtrTy = cast < PointerType > ( I -> getOperand ( TypeOp ) -> getType ( ) ) ; return cast < VectorType > ( PtrTy -> getElementType


<s> if ( ! EnableConstpoolPromotion || DAG . getMachineFunction ( ) . getTarget ( ) . Options . EnableFastISel ) return SDValue ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVar || ! GVar -> hasInitializer ( ) || ! GVar -> isConstant ( ) || ! GVar -> hasGlobalUnnamedAddr ( ) || ! GVar -> hasLocalLinkage ( ) ) return SDValue ( ) ; auto * Init = GVar -> getInitializer ( ) ; if ( ! isSimpleType ( Init -> getType ( ) ) ) return SDValue ( ) ; auto * CDAInit = dyn_cast < ConstantDataArray > ( Init ) ; unsigned Size = DAG . getDataLayout ( ) . getTypeAllocSize ( Init -> getType ( ) ) ; unsigned Align = GVar -> getAlignment ( ) ; unsigned RequiredPadding = <NUM_LIT> - ( Size % <NUM_LIT> ) ; bool PaddingPossible = RequiredPadding == <NUM_LIT> || ( CDAInit && CDAInit -> isString ( ) ) ; if ( ! PaddingPossible || Align > <NUM_LIT> || Size > ConstpoolPromotionMaxSize ) return SDValue ( ) ; unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction


<s> int64_t ImmValue = ImmOp . getImm ( ) ; tmpInst . setLoc ( IDLoc ) ; if ( <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ( ImmValue & <NUM_LIT> ) == ImmValue ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( unsigned Reg : RegList ) Inst . addOperand ( MCOperand :: createReg (


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode


<s> return ( __m128d ) __builtin_ia32_unpcklpd ( ( __v2df ) __A , (


<s> bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return


<s> assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( BB -> getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; return


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) -> getGPR32Reg ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst , Expr


<s> O << <STR_LIT> << '$' << LowercaseString ( getRegisterName ( stackReg ) ) << ',' << stackSize

<< ',' << '$' << LowercaseString ( getRegisterName ( returnReg ) ) << '\n' ;


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext &


<s> return REG_P ( x ) && INT_REG_OK_FOR_BASE_P


<s> else return GET_MODE_BITSIZE ( GET_MODE_INNER ( mode


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) )


<s> static SDValue getShuffleVectorZeroOrUndef ( SDValue V2 , unsigned Idx , bool IsZero , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { EVT VT = V2 . getValueType ( ) ; SDValue V1 = IsZero ? getZeroVector ( VT , Subtarget , DAG , V2 . getDebugLoc ( ) ) : DAG . getUNDEF ( VT ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( i


<s> if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; <ISA_LIT>MachineFunctionInfo * MFI = F . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < <NUM_LIT>


<s> while ( <NUM_LIT> ) { unsigned NextReg = SrcReg ; MachineInstr * Inst = MRI -> getVRegDef ( SrcReg ) ; if ( BB1 && Inst -> getOpcode ( ) == <STR_LIT> && Inst -> getParent ( ) == BB2 ) { NextReg = getIncomingRegForBlock ( Inst , BB1 ) ; BB1 = nullptr ; } else if ( Inst -> isFullCopy ( ) ) NextReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( NextReg == SrcReg || ! Register :: isVirtualRegister ( NextReg


<s> ArgValues . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Root , FIN , NULL , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumGPRs = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned VARegSize = ( <NUM_LIT> - NumGPRs ) * <NUM_LIT> ; unsigned VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ; unsigned ArgOffset = <NUM_LIT> ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; ArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsFrameIndex = MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; NumGPRs < <NUM_LIT> ; ++ NumGPRs ) { TargetRegisterClass * RC ; if ( AFI -> isThumbFunction ( ) ) RC = <STR_LIT> ; else RC = <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ NumGPRs ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , NULL , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } if ( ! MemOps . empty ( ) ) Root = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; } else VarArgsFrameIndex = MFI -> CreateFixedObject ( <NUM_LIT>


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } if ( ! Subtarget -> isLittle ( ) )


<s> unsigned ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal > <NUM_LIT> ) return false ; const SDNode * Node = V . getNode ( ) ; for ( SDNode * UI : Node -> uses ( ) ) if ( ! isa < MemSDNode > ( * UI ) ) for ( SDNode * UII : UI -> uses ( ) ) if ( ! isa < MemSDNode > ( * UII ) ) return false ; return


<s> uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; SmallVector < const SDNode * , <NUM_LIT> > Worklist ; Visited . insert ( Addr . getNode ( ) ) ; Worklist . push_back ( User ) ; Worklist . push_back ( LD ) ; Worklist . push_back ( Vector . getNode ( ) ) ; if ( SDNode :: hasPredecessorHelper ( LD , Visited , Worklist ) || SDNode :: hasPredecessorHelper ( User , Visited , Worklist ) ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( Lane ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ; SDValue NewResults [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( UpdN . getNode ( ) ,


<s> rtx_insn * insn ; int lrm_count = ( num_regs % <NUM_LIT> ) ? ( num_regs + <NUM_LIT> ) : ( num_regs + <NUM_LIT> ) ; for ( i = LAST_IWMMXT_REGNUM ; i >= FIRST_IWMMXT_REGNUM ; i -- ) if ( reg_needs_saving_p ( i ) ) { rtx addr = gen_frame_mem ( V2SImode , plus_constant ( Pmode , hard_frame_pointer_rtx , - lrm_count * <NUM_LIT> ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( V2SImode , i ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( V2SImode , i ) , NULL_RTX ) ; lrm_count += <NUM_LIT> ; } } gcc_assert ( saved_regs_mask & ( <NUM_LIT> << IP_REGNUM ) ) ; saved_regs_mask &= ~ ( <NUM_LIT> << IP_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << SP_REGNUM ) ; if ( really_return && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> calls_eh_return ) saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; else saved_regs_mask &= ~ ( <NUM_LIT> << PC_REGNUM ) ; num_regs = bit_count ( saved_regs_mask ) ; if ( ( offsets -> outgoing_args != ( <NUM_LIT> + num_regs ) ) || cfun -> calls_alloca ) { rtx_insn * insn ; emit_insn ( gen_blockage ( ) ) ; insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - <NUM_LIT> * num_regs ) ) ) ; arm_add_cfa_adjust_cfa_note ( insn , - <NUM_LIT> * num_regs , stack_pointer_rtx , hard_frame_pointer_rtx ) ; } arm_emit_multi_reg_pop ( saved_regs_mask ) ; if ( IS_INTERRUPT ( func_type ) ) { rtx_insn * insn ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( SImode , IP_REGNUM ) , addr


<s> unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; int offset_diff ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ; offset_diff = cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine ->


<s> bool isToken ( ) const override { return Kind == Token


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand ::


<s> rtx parts [ <NUM_LIT> ] ; int nregs ; int i ; regno = REGNO ( rtl ) ; if ( ! CSKY_VREG_P ( regno ) ) return NULL_RTX ; if ( CSKY_VREG_HI_P ( regno ) ) regno += <NUM_LIT> ; mode = GET_MODE ( rtl ) ; if ( GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return NULL_RTX ; if ( TARGET_SINGLE_FPU ) { nregs = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i += <NUM_LIT> ) if ( TARGET_BIG_ENDIAN ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i + <NUM_LIT> ) ; parts [ i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + i ) ; } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + i + <NUM_LIT> ) ; } } else { nregs = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i


<s> ( IsF128 ? APFloat :: IEEEquad : APFloat :: IEEEsingle ) ; const unsigned SizeInBits = VT . getSizeInBits ( ) ; SmallVector < Constant * , <NUM_LIT> > CV ( VT == <STR_LIT> ? <NUM_LIT> : ( IsF128 ? <NUM_LIT> : <NUM_LIT> ) , ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( SizeInBits , <NUM_LIT> ) ) ) ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getHighBitsSet ( SizeInBits , <NUM_LIT> ) ) ) ; Constant * C = ConstantVector :: get ( CV ) ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; MVT LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( IsF128 ? <STR_LIT> : <STR_LIT> ) ; SDValue Mask1 = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; if ( ! IsF128 ) Op1 = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 , Mask1 ) ; if ( ConstantFPSDNode * Op0CN = dyn_cast < ConstantFPSDNode > ( Op0 ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; if ( APF . isPosZero ( ) ) return IsF128 ? SignBit : DAG . getNode ( <STR_LIT> , dl , SrcVT , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits , SizeInBits - <NUM_LIT> ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; SDValue Val = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; if ( ! isa < ConstantFPSDNode > ( Op0 ) ) { if ( ! IsF128 ) Op0 = DAG . getNode (


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( )

&& ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) , CS ) ;


<s> auto Store = cast < StoreSDNode > ( Op ) ; SDLoc DL ( Op ) ; EVT VT = Store -> getValue ( ) . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; auto NewValue = convertToScalableVector ( DAG , ContainerVT , Store ->


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case VK_<ISA_LIT>_HI : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGH : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; break ; case VK_<ISA_LIT>_HIGHA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case VK_<ISA_LIT>_HIGHESTA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; } Sym = MCSymbolRefExpr :: create ( & Sym ->


<s> unsigned getOriginalCPIdx ( unsigned CloneIdx ) const { DenseMap < unsigned , unsigned > :: const_iterator I = CPEClones . find ( CloneIdx ) ; if ( I != CPEClones . end ( ) ) return I -> second ; else return -


<s> SDValue <ISA_LIT>TargetLowering :: LowerELFTLSDescCall ( SDValue SymAddr , SDValue DescAddr , SDLoc DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; SDValue Func = DAG . getNode ( <STR_LIT> , DL , PtrVT , SymAddr ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( ) ; SDValue Glue , Chain ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Func ) ; Ops . push_back ( SymAddr ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT )


<s> bool hasXMMInt ( ) const { return hasSSE2 ( ) || hasAVX (


<s> if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( ML ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( IsLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( IsVCTP ( & MI ) ) LoLoop . addVCTP ( & MI ) ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { if ( LoLoop . FoundOneVCTP ) LoLoop . ScanForVPR ( & MI ) ; LoLoop . CheckTPValidity ( & MI ) ; } if ( ! LoLoop . Dec || LoLoop . End || LoLoop . Revert ) continue ; for ( auto & MO : MI . operands ( ) ) { if ( MI . getOpcode ( ) != <STR_LIT> && MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; LoLoop . Revert


<s> <STR_LIT> getShiftExtendType ( ) const { if ( Kind == k_ShiftExtend ) return ShiftExtend . Type ; if ( Kind == k_Register ) return


<s> assert ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI -> getUniqueVRegDef (


<s> bool isImmThumbSR ( ) const { return isImmediate < <NUM_LIT> , <NUM_LIT> > (


<s> const auto * SVCR = <STR_LIT> ( Tok . getString ( ) ) ; if ( SVCR && SVCR -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = SVCR -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSVCR ( PStateImm , Tok . getString ( ) , S


<s> const MCExpr * <ISA_LIT>LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; if ( ! Subtarget -> is64Bit ( ) || Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) -> getCallingConv ( ) ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName (


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; return MCDisassembler :: Success


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast <


<s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction (


<s> SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setHasCalls ( true ) ; SDValue TGA = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 , DAG ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , TGA ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , withTargetFlags ( Op , ldTF , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , Offset , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD , DAG ) ) ; } assert ( model == TLSModel :: LocalExec ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 , DAG ) ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ,


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target


<s> unsigned MatchInstruction ( const OperandVector & Operands , MCInst & Inst , uint64_t & ErrorInfo , FeatureBitset & MissingFeatures , bool matchingInlineAsm , unsigned VariantID = <NUM_LIT> ) { if ( Code16GCC ) SwitchMode ( <STR_LIT>


<s> else if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwin_VASTART ( Op , DAG ) ; else return LowerAAPCS_VASTART ( Op


<s> void addMemoryIndexed128Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && isMemoryIndexed128 ( ) && <STR_LIT> ) ; addMemoryIndexedOperands ( Inst ,


<s> unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( ! isClusterableLdStOpcPair ( FirstOpc , SecondOpc , Subtarget ) ) return false ; if ( ! isLdStSafeToCluster ( FirstLdSt , TRI ) || ! isLdStSafeToCluster ( SecondLdSt , TRI ) ) return false ; int64_t Offset1 = <NUM_LIT> , Offset2 = <NUM_LIT> ; unsigned Width1 = <NUM_LIT> , Width2 = <NUM_LIT> ; const MachineOperand * Base1 = nullptr , * Base2 = nullptr ; if ( ! getMemOperandWithOffsetWidth ( FirstLdSt , Base1 , Offset1 , Width1 , TRI ) || ! getMemOperandWithOffsetWidth ( SecondLdSt , Base2 , Offset2 , Width2 , TRI ) || Width1 != Width2 ) return false ; assert ( Base1 == & BaseOp1 && Base2 == & BaseOp2 && <STR_LIT> ) ; assert ( Offset1 <= Offset2 && <STR_LIT> ) ; return Offset1 + Width1 ==


<s> int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; r = REAL_VALUE_NEGATE ( r ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) )


<s> else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; Result . getNode ( ) -> setTrapInfo ( Op -> getTrapInfo ( ) ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } return


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) && <STR_LIT> ) ; const unsigned CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineInstr & TestInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( DestMBB ) . addImm ( <STR_LIT> ) ; constrainSelectedInstRegOperands ( TestInst , TII , TRI ,


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , bool HasAVX2 ) { return :: isUNPCKH_v_undef_Mask ( N -> getMask ( ) , N

-> getValueType ( <NUM_LIT> ) , HasAVX2 ) ;


<s> const auto * TRC = TII -> getRegClass ( TII -> get ( LoadInst -> getOpcode ( ) ) , <NUM_LIT> , TRI , * LoadInst -> getParent ( ) -> getParent ( ) ) ; return TRI -> getRegSizeInBits ( * TRC


<s> bool <ISA_LIT>CallLowering :: LowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , const SmallVectorImpl < unsigned > & VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; unsigned NumArgs = Args . size ( ) ; Function :: const_arg_iterator CurOrigArg = Args . begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { MVT ValVT = <STR_LIT> ( CurOrigArg -> getType ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , <STR_LIT> ( ) , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void ) Res ; } assert ( ArgLocs . size ( ) == Args . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MIRBuilder . getMBB ( ) . addLiveIn ( VA . getLocReg ( ) ) ; MIRBuilder . buildInstr ( TargetOpcode :: COPY , VRegs [ i ] , VA . getLocReg ( ) ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : break ; case CCValAssign :: AExt : case CCValAssign ::


<s> static DecodeStatus DecodeVST4LN ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT>


<s> RegCtx . AddBusyReg ( DstReg ) ; RegCtx . AddBusyReg ( SrcReg ) ; RegCtx . AddBusyReg ( CntReg ) ; InstrumentMemOperandPrologue ( RegCtx , Ctx , Out ) ; { const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , SrcReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , SrcReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , DstReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true ,


<s> StackOffset SaveOffset = StackOffset :: getFixed ( Offset ) ; return is<ISA_LIT>FrameOffsetLegal ( * MI

, SaveOffset ) & <ISA_LIT>FrameOffsetIsLegal ;


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT> + <STR_LIT>


<s> return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) , true ) ) ; } return false


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> | <STR_LIT> ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return <STR_LIT> | <STR_LIT> ; return <STR_LIT> ; } if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny )

&& GV -> hasExternalWeakLinkage ( ) ) return <STR_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI ) { EmitSled ( MI , SledKind :: TAIL_CALL


<s> const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) || IsMCU )


<s> case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_ABS_NC


<s> return ( CallConv == CallingConv :: Fast && TailCallOpt ) || CallConv == CallingConv :: Tail

|| CallConv == CallingConv :: SwiftTail ;


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { unsigned Size = <NUM_LIT> << getFixupKindLog2Size ( Fixup . getKind ( ) ) ; assert ( Fixup . getOffset ( ) + Size <= DataSize && <STR_LIT> ) ; assert ( isIntN ( Size * <NUM_LIT> +


<s> if ( TREE_CODE ( exp ) == STRING_CST

) return MAX ( align , FASTEST_ALIGNMENT ) ;


<s> uint64_t FrameSize = StackSize - <NUM_LIT> ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> )


<s> if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ; auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NodeType , dl , <STR_LIT> , SrcVec , DAG . getIntPtrConstant ( SubvecIdx


<s> static __inline qword si_dfma ( qword a , qword b , qword c ) { union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , cc , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] + cc . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] + cc . d [ <NUM_LIT> ] ; return ( ( qword ) ( dd .


) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( __m512i ) __builtin_ia32_psrav8di_mask ( ( __v8di ) __X , ( __v8di ) __Y , (


<s> static void rx_function_arg_advance ( cumulative_args_t cum , const function_arg_info & arg ) { * get_cumulative_args ( cum ) += rx_function_arg_size ( arg . mode , arg . type