<s> case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return SDValue (


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT>


<s> size_t ReadCount = getLexer ( ) . peekTokens ( Buf ) ; if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens )


<s> int n_new = riscv_flatten_aggregate_argument ( type , fields , true ) ; for ( int i = <NUM_LIT> ; i < n_new ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) { n_new = - <NUM_LIT> ; break ; } if ( ( n_old != n_new ) && ( warned == <NUM_LIT> ) ) { warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ; warned = <NUM_LIT> ; } return n_new > <NUM_LIT> ? n_new : <NUM_LIT>


, gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT>


<s> const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } } return


<s> addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>CoreVHwlpBlocksPass ( )


<s> static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { MCContext & Ctx = AP . OutContext ; <ISA_LIT>MCExpr :: VariantKind Kind ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr ::


<s> return DecodeGPRRegisterClass ( Inst , RegNo , Address ,


<s> if ( insn -> is_real ( ) && ( types & REAL_SET ) ) return true ; if ( insn -> is_phi ( ) && ( types & PHI_SET ) ) return true ; if ( insn -> is_bb_head ( ) && ( types &


<s> return pred == PRED_TYPE_m || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu || pred


<s> FunctionPass * llvm :: create<ISA_LIT>MakeCompressibleOptPass


<s> void <ISA_LIT>InstPrinter :: printVTypeI ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; <ISA_LIT>VType :: printVType ( Imm , O


<s> unsigned getVType ( ) const { assert ( Kind == KindTy ::


<s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT>


<s> tree function_instance :: get_arg_type ( unsigned opno )


<s> FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : FixupKind = <STR_LIT> ; break ; default : break ; } } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> if ( AVLReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; if ( AVLReg . isVirtual ( ) && AVLReg == PrevOutVL ) return true ; if ( PrevVSETVLI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( AVLReg != PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; if ( AVLReg == <STR_LIT> ) { return PrevOutVL


<s> if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else { Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr


<s> switch ( ID ) { case TargetStackID :: Default : case TargetStackID :: ScalableVector : return true ; case TargetStackID :: NoAlloc : case TargetStackID ::


<s> static const struct riscv_cpu_info * riscv_parse_cpu ( const char * cpu_string ) { for ( unsigned i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_cpu_info_table ) ; i ++ ) if ( strcmp ( riscv_cpu_info_table [ i ] . name , cpu_string ) == <NUM_LIT> ) return riscv_cpu_info_table + i ; error ( <STR_LIT>


<s> if ( Pmode == DImode ) return gen_tls_add_tp_ledi ( dest , base , tp , sym ) ; else return gen_tls_add_tp_lesi ( dest , base


<s> if ( ! riscv_tls_symbol ) riscv_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; func = gen_rtx_MEM ( FUNCTION_MODE , riscv_tls_symbol ) ; start_sequence ( ) ; emit_insn ( riscv_got_load_tls_gd ( a0 , sym ) ) ; insn = emit_call_insn ( gen_call_value ( result , func , const0_rtx , NULL ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn


<s> if ( ST -> hasVInstructions ( ) && MaxVectorSizeInBits !=

<NUM_LIT> ) return MaxVectorSizeInBits / <STR_LIT> ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; if ( N . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue Srl = N . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) return false ; uint64_t VC1 = N . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 >= <NUM_LIT> || VC1 != maskTrailingZeros < uint64_t > ( <NUM_LIT> - VC2 ) ) return false ; RS1 = Srl . getOperand


<s> inline static bool isMaskAgnostic ( unsigned VType ) { return VType &


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; if ( Subtarget . hasStdExtA ( ) ) { setMaxAtomicSizeInBitsSupported ( Subtarget . getXLen ( ) ) ; setMinCmpXchgSizeInBits ( <NUM_LIT> ) ; } else { setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; unsigned FunctionAlignment = Subtarget . hasStdExtC ( )


<s> char * function_builder :: finish_name ( ) { obstack_1grow ( & m_string_obstack , <NUM_LIT> ) ; return ( char * ) obstack_finish ( &


<s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( )


<s> for ( const insn_info * i = insn -> next_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( find_access ( i -> defs ( ) , VL_REGNUM ) ) return nullptr ; if ( read_vl_insn_p ( i -> rtl


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) )


<s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK


<s> MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) )

-> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp


<s> if ( MEM_P ( op ) ) return <NUM_LIT> ; if ( unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( GET_MODE ( op ) == HImode


<s> SDValue <ISA_LIT>TargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Src . getValueType ( ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; if ( ! IsRV32E64 ) { SplatOne = DAG . getSplatVector ( VecVT , DL , SplatOne ) ; SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ; } else { SplatOne = DAG . getNode ( <STR_LIT> ,


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( SelectionDAG & DAG ) { return reinterpret_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget


<s> static unsigned compute_vlmax ( unsigned vector_bits , unsigned elt_size , unsigned min_size ) { return ( ( vector_bits / elt_size )


<s> auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ; setTargetABI ( <STR_LIT> ( STI . getTargetTriple ( ) , Features , MAB . getTargetOptions ( ) .


<s> if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) ,


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == XLenVT && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value


<s> OperandMatchResultTy parsePairGR64 ( OperandVector & Operands


<s> return ! cfun -> machine -> interrupt_handler_p || df_regs_ever_live_p (


startswith ( <STR_LIT> ) ) return false ;


<s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> +


<s> EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ValueVT == <STR_LIT> && PartVT == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize %


<s> if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Adjust ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP (


<s> insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask


<s> Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == <NUM_LIT> ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags &


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; setMinimumJumpTableEntries (


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue


<s> if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI

( ) ) return TailPaddingAmount :: None ;


<s> bool <ISA_LIT>ExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; unsigned BaseOpc = <STR_LIT> ( Op . getOpcode ( ) ) ; while ( getTypeAction ( * DAG . getContext ( ) , VecEVT ) == TargetLowering :: TypeSplitVector ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Vec , DL ) ; VecEVT = Lo . getValueType ( ) ; Vec = DAG . getNode ( BaseOpc , DL , VecEVT , Lo , Hi ) ; } if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT (


<s> <ISA_LIT>InstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + <NUM_LIT>


<s> MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; MCSTI = & NewSTI ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI


<s> return DAG . getDataLayout ( ) . getPrefTypeAlign ( VT . getTypeForEVT ( * DAG . getContext


<s> static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case <NUM_LIT> : return Name == <STR_LIT> || Name == <STR_LIT> ; case <NUM_LIT> : return Name ==


<s> Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> )


<s> static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode , rtx x ) { int align , size ; if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) )


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VT . isVector ( ) ) { MVT SplatCondVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue CondSplat = VT . isScalableVector ( ) ? DAG . getSplatVector ( SplatCondVT , DL , CondV ) : DAG . getSplatBuildVector ( SplatCondVT , DL , CondV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , CondSplat , TrueV , FalseV ) ; } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; return isLegalElementTypeForRVV ( DataType -> getScalarType ( )


<s> return SET_DEST ( XVECEXP ( PATTERN ( rinsn ) , <NUM_LIT> ,


<s> enum rtx_code dest_code , src_code ; machine_mode mode ; bool dbl_p ; dest_code = GET_CODE ( dest ) ; src_code = GET_CODE ( src ) ; mode = GET_MODE ( dest ) ; dbl_p = ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ; if ( dbl_p && riscv_split_64bit_move_p ( dest , src ) ) return <STR_LIT> ; if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? <STR_LIT> : <STR_LIT> ; if ( src_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( src_code == CONST_INT ) return <STR_LIT> ; if ( src_code == HIGH ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return <STR_LIT> ; case SYMBOL_ABSOLUTE : return <STR_LIT> ; case SYMBOL_PCREL : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] .


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] (

int64_t Imm ) { return isInt < <NUM_LIT> > ( Imm ) ; } ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; unsigned Opcode ; bool IsScalableVector = true ; bool IsZvlsseg = true ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI ,


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && (

Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr


<s> unsigned getIncomingArgSize ( ) const { return


<s> static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) { if ( riscv_tls_symbol_p ( x


<s> return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & OpIdx .


<s> if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ; else return <STR_LIT>


<s> void riscv_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ]


<s> CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT>


<s> SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain


<s> void addVTypeIOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getVType


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ; if ( ! VT . isFixedLengthVector ( ) )


<s> unsigned <ISA_LIT>AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { switch ( Op ) { default : return Op ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> SDValue PassThru = Load -> getPassThru ( ) ; SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT


<s> bool willForceRelocations ( ) const { return ForceRelocs || STI . getFeatureBits ( )


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS (


<s> switch ( Inst . getOpndKind ( ) ) { case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; break ; case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ; break ; case


<s> State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT


<s> bool <ISA_LIT>ELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL ,


<s> Register Rs = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Rt = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = Rs == GAReg ? Rt : Rs ; if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ; MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand (


<s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ <NUM_LIT> ] , bool ignore_zero_width_bit_field_p ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ; return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> , ignore_zero_width_bit_field_p


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm (


<s> auto * SVal = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; if ( ! SVal || SVal -> getKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev )


<s> TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCObjectFileInfo ( * T , create<ISA_LIT>MCObjectFileInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T ,


<s> unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; unsigned MaxELen = Subtarget . getELEN ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; switch ( EltVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool isUnknown ( ) const { return State == Unknown


<s> case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; case LTGT : tmp0 = riscv_force_binary ( word_mode , LT , cmp_op0 , cmp_op1 ) ; tmp1 = riscv_force_binary ( word_mode , GT , cmp_op0 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , IOR , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; default : gcc_unreachable ( )


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ; return false


<s> bool <ISA_LIT>TargetLowering :: shouldRemoveExtendFromGSIndex ( EVT


<s> return combineSelectAndUseCommutative ( N ,


<s> static DecodeStatus DecodePulpV2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPRRegisterClass ( Inst , RegNo , Address ,


<s> switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops ( Num ) ; return true ; } break ; } case <STR_LIT> : OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> ) ->


<s> static void riscv_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ; delta = bits /


<s> MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandVMSGE ( MI , OS , Fixups , STI ) ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT>


<s> generateInstSeq ( Chunk . getSExtValue ( ) , IsRV64 , MatSeq ) ; Cost += MatSeq . size ( ) ; } return std :: max (


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int Lower , int Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> +


<s> auto Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr


<s> void setAVLImm ( unsigned Imm ) { AVLImm = Imm ; State = AVLIsImm


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI .


<s> return new <ISA_LIT>DAGToDAGISel ( TM )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( )


<s> rawResult = DAG . getNode ( <STR_LIT> , DL , RegTy , dummy , V1 ) ; } else { rawResult = DAG . getNode ( <STR_LIT> , DL , RegTy , dummy , V1 ) ; } signed_bit = DAG . getNode ( <STR_LIT> , DL , RegTy , DAG . getNode ( <STR_LIT> , DL , RegTy , rawResult , DAG . getConstant ( <NUM_LIT> , DL , RegTy ) ) , DAG . getConstant ( lowShift , DL , RegTy ) ) ; mask = DAG . getNode ( <STR_LIT> , DL , RegTy , signed_bit , DAG . getConstant ( lowShift - <NUM_LIT> , DL , RegTy ) ) ; SDValue finalResult = DAG . getNode ( <STR_LIT> , DL , RegTy , rawResult , mask ) ; return finalResult


<s> NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor


<s> return insn1 -> compare_with ( insn2 ) <


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT (


<s> MCValue E ; if ( ! Value -> evaluateAsRelocatable ( E , nullptr , nullptr ) ) return false ; if ( E . getSymA ( ) == nullptr || E . getSymB ( ) == nullptr ) return false ; const auto & A = E . getSymA ( ) -> getSymbol ( ) ; const auto & B = E . getSymB ( ) -> getSymbol ( ) ; LHS = MCBinaryExpr :: create ( MCBinaryExpr :: Add , MCSymbolRefExpr :: create ( & A , C ) , MCConstantExpr :: create ( E . getConstant ( ) , C ) , C ) ; RHS = E . getSymB ( ) ; return ( A . isInSection ( ) ? A . getSection ( ) . hasInstructions ( ) : ! A . getName ( ) . empty ( ) ) || ( B . isInSection ( ) ? B . getSection ( ) . hasInstructions ( ) :


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq (


<s> unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPRRegisterClass ( Inst , Rs2 , Address


<s> std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , CPUName


<s> auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> }


<s> static unsigned getSCForRMW ( AtomicOrdering Ordering , int Width ) { if ( Width == <NUM_LIT> ) return


<s> return ST -> getMaxInterleaveFactor (


<s> uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6


<s> NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NF = isRVVSpillForZvlsseg ( Opcode ) -> first ; return <NUM_LIT> * ( <NUM_LIT> * NF -


<s> Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary ,


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT )


<s> static SDValue performXORCombine ( SDNode * N , SelectionDAG & DAG ) { return combineSelectAndUseCommutative ( N , DAG , false


<s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , ContainerVT , CC , Op1 , Op2 , VL ) ; return convertFromScalableVector ( VT , Select , DAG


<s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) .

addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ;


<s> return hasStdExtV ( ) ? MaxInterleaveFactor :


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( )


<s> } else if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { immediate = <NUM_LIT> ; registr = <NUM_LIT> ; } assert ( immediate != <NUM_LIT> && registr != <NUM_LIT> ) ; int n = MI . getOperand ( immediate ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , isset ) ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( r_pos <= l_pos ) ; unsigned opcode = isset ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder pbclrMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pbclrMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pbclrMI . addOperand ( MI . getOperand ( registr ) ) ; pbclrMI . addImm ( l_pos -


<s> bool isUImm20LUI ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; }


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) &&


<s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Identifier . size ( ) ) ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) .


<s> } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT


<s> return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case


<s> widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ; return wi :: umin ( min_size , <NUM_LIT> ) .


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT

, RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) {


<s> bool shouldNormalizeToSelectSequence ( LLVMContext & , EVT )


<s> case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) ||


<s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { assert ( RS && <STR_LIT> ) ; assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ; MachineFunction * MF = MBB . getParent (


<s> static SDValue unpackFromRegLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { llvm_unreachable ( <STR_LIT> )


<s> else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT ) d_add_builtin_version


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO . getReg ( )


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_EXPAND_PSEUDO_NAME


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo


<s> if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT ) OS << <STR_LIT> ; if ( HasVariant ) OS


<s> assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV ->


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset )


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth --


<s> SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> inline static unsigned encodeVTYPE ( <ISA_LIT>VLMUL VLMUL , <ISA_LIT>VSEW VSEW , bool TailAgnostic , bool MaskAgnostic ) { unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = static_cast < unsigned > ( VSEW ) ; unsigned VTypeI = ( ( VLMULBits & <NUM_LIT> ) << <NUM_LIT> ) | ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic )


<s> static void simple_poly_selftest ( const char * arch , enum riscv_abi_type abi , const std :: vector < machine_mode > & modes ) { riscv_selftest_arch_abi_setter rv ( arch , abi ) ; rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ; set_new_first_and_last_insn ( NULL ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned >


<s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> static bool bindsLocally ( const GlobalValue * GV , Reloc :: Model RM ) { if ( RM == Reloc ::


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopIfBodyMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopIfBodyMBB ) ; MF -> insert ( ++ LoopIfBodyMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopIfBodyMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopIfBodyMBB -> addSuccessor ( LoopTailMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand (

IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ;


<s> switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand ::


<s> return isBareSimmNLsb0 < <NUM_LIT> > (


<s> if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord ) ) return Builder

. CreateFence ( AtomicOrdering :: Release ) ;


<s> * offset_ptr = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; } else { * base_ptr = x ; * offset_ptr =


<s> FeatureBitStack . push_back ( getSTI ( ) . getFeatureBits


<s> if ( ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) && ( riscv_align_data_type == riscv_align_data_type_xlen )

) return MAX ( align , BITS_PER_WORD ) ;


<s> if ( ! isTypeLegal ( Src ) || ! isTypeLegal ( Dst ) ) return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; if ( Src -> getScalarSizeInBits ( ) > ST -> getELEN ( ) || Dst -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; int PowDiff = ( int ) Log2_32 ( Dst -> getScalarSizeInBits ( ) ) - ( int ) Log2_32 ( Src -> getScalarSizeInBits ( ) ) ; switch ( ISD ) { case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> assert ( PtrIsCap ) ; switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd (

ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> void pushHwlpBasicBlock ( const MachineBasicBlock * BB


<s> Sew . ashrInPlace ( <NUM_LIT> ) ; unsigned SewLog2 = Sew . logBase2 ( ) ; unsigned LmulLog2 = Lmul . logBase2 ( ) ; Op -> VType . Sew = static_cast < VSEW > ( SewLog2 ) ; if ( Fractional ) { unsigned Flmul = <NUM_LIT> - LmulLog2 ; Op -> VType . Lmul = static_cast < VLMUL > ( Flmul ) ; Op -> VType . Encoding = ( ( Flmul & <NUM_LIT> ) << <NUM_LIT> ) | ( ( SewLog2 & <NUM_LIT> ) <<


<s> bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHS = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( DAG . getConstant ( IsLHS ? std :: max ( MaskIndex , <NUM_LIT> ) : <NUM_LIT> , DL , XLenVT ) ) ; GatherIndicesRHS . push_back ( DAG . getConstant ( IsLHS ? <NUM_LIT> : MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ; IndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; } MVT IndexContainerVT = ContainerVT . changeVectorElementType ( IndexVT . getScalarType ( ) ) ; SDValue Gather ; if ( SDValue SplatValue = DAG . getSplatValue ( V1 ) ) { Gather = lowerScalarSplat ( SplatValue , VL , ContainerVT , DL , DAG , Subtarget ) ; } else { SDValue LHSIndices = DAG . getBuildVector ( IndexVT , DL , GatherIndicesLHS ) ; LHSIndices = convertToScalableVector ( IndexContainerVT , LHSIndices , DAG , Subtarget ) ; V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ; } if ( ! V2 . isUndef ( ) ) { MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SelectMask = convertToScalableVector ( MaskContainerVT , SelectMask , DAG , Subtarget ) ; SDValue RHSIndices = DAG . getBuildVector ( IndexVT , DL ,


<s> return MF . getFunction ( ) . hasMinSize


<s> switch ( lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return ! isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> )


<s> unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ; return static_cast < <ISA_LIT>VSEW > ( VSEW


<s> * extend = true ; mem = XEXP ( mem , <NUM_LIT> ) ; } if ( ! MEM_P ( mem ) || GET_MODE ( mem ) != SImode ) return false ; * addr = XEXP ( mem ,


<s> return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type (


<s> bool demand_p ( enum demand_type type


<s> void <ISA_LIT>AsmParser :: emitCapLoadTLSIEAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand TmpReg = Inst .


<s> int <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; const DataLayout & DL = getDataLayout ( ) ; return <STR_LIT> ( Imm , DL . getTypeSizeInBits ( Ty ) , getST ( ) -> is64Bit


<s> bool <ISA_LIT>MergeBaseOffsetOpt :: detectLuiAddiGlobal ( MachineInstr & HiLUI , MachineInstr * & LoADDI ) { if ( HiLUI . getOpcode ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || HiLUI . getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || HiLUI . getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned HiLuiDestReg = HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ; if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress ||

LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return new yaml :: <ISA_LIT>MachineFunctionInfo ( *


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF


<s> void setManipulatesSP ( bool MSP ) { ManipulatesSP =


<s> return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type


<s> ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( Scalar ) ; if ( isOneConstant ( VL ) && ( ! Const || isNullConstant ( Scalar ) || ! isInt < <NUM_LIT> > ( Const -> getSExtValue ( ) ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Scalar , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Scalar , VL ) ; } assert ( XLenVT == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> &&


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; } else Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true


<s> unsigned HOST_WIDE_INT loval = sext_hwi ( val , <NUM_LIT> ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; cost = <NUM_LIT> + riscv_build_integer ( codes , loval , VOIDmode ) ; if ( loval != hival ) cost += riscv_build_integer ( codes , hival , VOIDmode ) ; return cost


<s> MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) ,

StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm ,


<s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { bool HasStdExtC = STI -> getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ?


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { assert ( Expr && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; bool IsConstant = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { IsConstant = RE -> evaluateAsConstant ( Imm ) ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { IsConstant = true ; Imm = CE -> getValue ( ) ; } if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm


<s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc :: Model RM , CodeModel :: Model CM ) const { if ( GV -> getAlignment ( ) == <NUM_LIT> ) return false ; if ( CM == CodeModel :: Small ) return bindsLocally ( GV , RM ) ; return


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> emit_insn ( gen_th_fmv_hw_w_x ( dest , high_src , low_src ) ) ; return ; } if ( FP_REG_RTX_P ( src ) ) { rtx low_dest = riscv_subword ( dest , false ) ; rtx high_dest = riscv_subword ( dest , true ) ; emit_insn ( gen_th_fmv_x_w ( low_dest , src ) ) ; emit_insn ( gen_th_fmv_x_hw ( high_dest , src ) ) ; return ; } } rtx low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false )


<s> if ( parseRegister ( Reg ) ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Reg . Prefix == 'x' && Reg . Number < <NUM_LIT> ) RegNo = GR32Regs [ Reg . Number ] ; else if ( Reg . Prefix == 'f' && Reg . Number < <NUM_LIT> ) RegNo = FP32Regs [ Reg . Number ] ; else if ( Reg . Prefix == 'e' && Reg . Number <= <NUM_LIT> ) RegNo = ER64Regs [ Reg . Number ] ; else return Error ( Reg . StartLoc , <STR_LIT> ) ; StartLoc = Reg . StartLoc ; EndLoc = Reg .


<s> bool hasStdExtZksh ( ) const { return HasStdExtZksh


<s> for ( const auto & ArgIdx : enumerate ( Args ) ) { MVT ArgVT = ArgIdx . value ( ) . VT ; if ( ArgVT . isScalableVector ( ) && ArgVT . getVectorElementType ( ) . SimpleTy == <STR_LIT> ) return ArgIdx


<s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! MBB . isLiveIn ( Reg ) , CS . getFrameIdx ( ) , RC , TRI ) ; } return true


<s> static std :: unique_ptr < <ISA_LIT>Operand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( SystemRegister ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ; Op -> StartLoc =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( UseGPRForF64 && XLen == <NUM_LIT> && ValVT == <STR_LIT> ) { assert ( ! ArgFlags . isSplit ( ) && PendingLocs . empty ( ) && <STR_LIT> ) ; Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF32 ) Reg = State . AllocateReg ( ArgFPR32s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16 ) Reg = State . AllocateReg ( ArgFPR16s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR32s ) ; else if ( ValVT . isScalableVector ( ) ) { switch ( ValVT . getSizeInBits ( ) . getKnownMinSize ( ) ) { case <NUM_LIT> : Reg = State . AllocateReg ( ArgVR2s


<s> AU . addRequired < MachineLoopInfo >


<s> TargetStackID :: Value <ISA_LIT>FrameLowering :: getStackIDForScalableVectors ( ) const { return TargetStackID ::


<s> void vector_infos_manager :: release ( void ) { if ( ! vector_insn_infos . is_empty ( ) ) vector_insn_infos . release ( ) ; if ( ! vector_block_infos . is_empty ( ) ) vector_block_infos . release ( ) ; if ( ! vector_exprs . is_empty ( ) ) vector_exprs . release ( ) ; gcc_assert ( to_refine_vsetvls . is_empty ( ) ) ; gcc_assert ( to_delete_vsetvls . is_empty ( ) ) ; if ( optimize > <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: getOpcodeForOffset ( unsigned Opcode , int64_t Offset ) const { int64_t Offset2 = Offset ; if ( isInt < <NUM_LIT> > ( Offset ) && isInt < <NUM_LIT> > ( Offset2 ) ) { return Opcode ; } if ( isInt < <NUM_LIT> > ( Offset ) && isInt < <NUM_LIT> > ( Offset2 ) ) { return Opcode ; } return <NUM_LIT>


<s> Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT>


<s> bool isToken ( ) const override { return Kind


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> if ( TREE_CODE ( x ) == VAR_DECL && DECL_SECTION_NAME ( x ) ) { const char * sec = DECL_SECTION_NAME ( x ) ; return strcmp ( sec , <STR_LIT> ) == <NUM_LIT> || strcmp ( sec , <STR_LIT> ) == <NUM_LIT> ; } return riscv_size_ok_for_small_data_p ( int_size_in_bytes ( TREE_TYPE ( x )


<s> riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; riscv_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , IsRV32 ? IsVarArg ? CC_<ISA_LIT>32_VAR : CC_<ISA_LIT>32 : IsVarArg ? CC_<ISA_LIT>64_VAR : CC_<ISA_LIT>64 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; if ( Subtarget . isRV64 ( ) ) RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . isRV32 ( ) ) { RC = & <STR_LIT> ; } else { RC = & <STR_LIT> ; } } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . hasD ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . hasF ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { if ( Subtarget . hasD ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . hasF ( ) ) RC = & <STR_LIT> ; else if ( Subtarget . isRV64 ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain


<s> case US_PLUS : case EQ : case NE : case LE : case LEU : case GT : case GTU : return simm5_p ( x ) ; case LT : case LTU


<s> static bool riscv_legitimate_address_p ( enum machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info addr ; return riscv_classify_address ( & addr ,


<s> static bool isVsetvli ( MachineInstr & instr ) { return instr . getOpcode


<s> if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true


<s> uint64_t StackAlign = getStackAlignment ( ) ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) { return <NUM_LIT> - StackAlign


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI


<s> bool hasVInstructionsAnyF ( ) const { return hasVInstructionsF32


<s> bool <ISA_LIT>GatherScatterLowering :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( )


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer ::


<s> static void riscv_va_start ( tree valist , rtx


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR32C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg


<s> bool UseDefaultPreferences = true ; if ( ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) || ST -> getTuneCPU ( ) . contains ( <STR_LIT> ) ) UseDefaultPreferences = false ; if ( UseDefaultPreferences ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP , ORE ) ; UP . UpperBound = true ; UP . OptSizeThreshold = <NUM_LIT> ; UP . PartialOptSizeThreshold = <NUM_LIT> ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( )


<s> assert ( BasePhi -> getNumIncomingValues ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned IncrementingBlock = BasePhi -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; assert ( BasePhi -> getIncomingValue ( IncrementingBlock ) == Inc && <STR_LIT> ) ; Builder . SetInsertPoint ( GEP ) ; Ops [ * VecOperand ] = BasePhi ; Type * SourceTy = GEP -> getSourceElementType ( ) ; Value * BasePtr = Builder . CreateGEP ( SourceTy , Ops [ <NUM_LIT> ] , makeArrayRef ( Ops ) . drop_front ( ) ) ; Builder . SetInsertPoint ( BasePhi -> getIncomingBlock ( <NUM_LIT> - IncrementingBlock ) -> getTerminator ( ) ) ; Type * IntPtrTy = DL -> getIntPtrType ( BasePtr -> getType ( ) ) ; assert ( Stride -> getType ( ) == IntPtrTy && <STR_LIT> ) ; if ( TypeScale != <NUM_LIT> ) Stride = Builder . CreateMul ( Stride , ConstantInt :: get ( IntPtrTy , TypeScale ) ) ; auto P = std :: make_pair ( BasePtr , Stride ) ; StridedAddrs [ GEP ] = P ; return


<s> while ( true ) { if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MI = MRI . getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI ) return