<s> bool addRange ( uint64_t Start , uint64_t End , Instruction * Inst ) { auto I = std :: lower_bound ( Ranges . begin ( ) , Ranges . end ( ) , Start , [ ] ( const Range & LHS , uint64_t RHS ) { return LHS . End <= RHS ; } ) ; if ( I != Ranges . end ( ) && End > I


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) { GlobalBaseReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; } else { GlobalBaseReg = PC ; } <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg


<s> Op -> RegShiftedImm . ShiftTy = ShTy ; Op -> RegShiftedImm . SrcReg = SrcReg ; Op -> RegShiftedImm . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> bool IsShuf0 = getTargetShuffleInputs ( BC0 , Ops0 , Mask0 , DAG ) && ! isAnyZero ( Mask0 ) && scaleShuffleElements ( Mask0 , <NUM_LIT> , ScaledMask0 ) && all_of ( Ops0 , [ ] ( SDValue Op ) { return Op . getValueSizeInBits ( ) == <NUM_LIT> ; } ) ; bool IsShuf1 = getTargetShuffleInputs ( BC1 , Ops1 , Mask1 , DAG ) && ! isAnyZero ( Mask1 ) && scaleShuffleElements ( Mask1 , <NUM_LIT> , ScaledMask1 ) && all_of ( Ops1 , [ ] ( SDValue Op ) { return Op . getValueSizeInBits ( ) == <NUM_LIT> ; } ) ; if ( IsShuf0 || IsShuf1 ) { if ( ! IsShuf0 ) { Ops0 . assign ( { BC0 } ) ; ScaledMask0 . assign ( { <NUM_LIT> , <NUM_LIT> } ) ; } if ( ! IsShuf1 ) { Ops1 . assign ( { BC1 } ) ; ScaledMask1 . assign ( { <NUM_LIT> , <NUM_LIT> } ) ; } SDValue LHS , RHS ; int PostShuffle [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; auto FindShuffleOpAndIdx = [ & ] ( int M , int & Idx , ArrayRef < SDValue > Ops ) { if ( M < <NUM_LIT> ) return true ; Idx = M % <NUM_LIT> ; SDValue Src = Ops [ M / <NUM_LIT> ] ; if ( ! LHS || LHS == Src ) { LHS = Src ; return true ; } if ( ! RHS || RHS == Src ) { Idx += <NUM_LIT> ; RHS = Src ; return true ; } return false ; } ; if ( FindShuffleOpAndIdx ( ScaledMask0 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops0 ) && FindShuffleOpAndIdx ( ScaledMask0 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops0 ) && FindShuffleOpAndIdx ( ScaledMask1 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops1 ) && FindShuffleOpAndIdx ( ScaledMask1 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops1 ) ) { LHS = DAG . getBitcast ( SrcVT , LHS ) ; RHS = DAG . getBitcast ( SrcVT , RHS ? RHS : LHS ) ; MVT ShufVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Res = DAG . getNode ( Opcode , DL , VT , LHS , RHS ) ; Res = DAG . getBitcast ( ShufVT , Res ) ; Res = DAG . getVectorShuffle ( ShufVT , DL , Res , Res , PostShuffle ) ; return DAG . getBitcast ( VT , Res ) ; } } } if ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SmallVector < int > Mask0 , Mask1 ; SmallVector < SDValue > Ops0 , Ops1 ; SmallVector < int , <NUM_LIT> >


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL


<s> return ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed


<s> case Instruction :: LShr : case Instruction :: AShr : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = <NUM_LIT> ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= <NUM_LIT> && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> is<ISA_LIT>64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI


<s> break ; case <STR_LIT> : case <STR_LIT> : return performAddSubLongCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DCI ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT>


<s> bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c ) ; dd . d [ <NUM_LIT> ] = cc . d [ <NUM_LIT> ] - aa . d [ <NUM_LIT> ] * bb


<s> static void emitLEAzzi ( MCStreamer & OutStreamer , MCOperand & Imm , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand (


<s> unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , Align ) ; unsigned LoadOp = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) && <STR_LIT> ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp =


<s> bool <ISA_LIT>BaseInstrInfo :: getInsertSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPair & BaseReg , RegSubRegPairAndIdx & InsertedReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isInsertSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : const MachineOperand & MOBaseReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ; InsertedReg . SubIdx = <STR_LIT> +


<s> EmitSled ( MI , SledKind :: FUNCTION_EXIT


<s> if ( ! SetCCI . mayStore ( ) ) { assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Register OldReg = SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI -> clearKillFlags ( OldReg ) ; MRI -> replaceRegWith ( OldReg , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add


<s> insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) )

insn_entry [ uid ] . is_live_out = <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return <STR_LIT>


<s> _Float16 _Complex a ; float b ; } u = { .


<s> assert ( CE != nullptr && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( )


<s> static SDValue tryCombineToEXTR ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue LHS ; uint32_t ShiftLHS = <NUM_LIT> ; bool LHSFromHi = false ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , LHS , ShiftLHS , LHSFromHi ) ) return SDValue ( ) ; SDValue RHS ; uint32_t ShiftRHS = <NUM_LIT> ; bool RHSFromHi = false ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , RHS , ShiftRHS , RHSFromHi ) ) return SDValue ( ) ; if ( LHSFromHi == RHSFromHi ) return SDValue ( ) ; if ( ShiftLHS + ShiftRHS != VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( LHSFromHi ) { std :: swap ( LHS , RHS ) ; std :: swap ( ShiftLHS , ShiftRHS ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , DAG . getConstant ( ShiftRHS ,


<s> if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> == RB . getID ( ) ) return Isload ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) || Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) { if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> == RB . getID ( ) ) return Isload ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload ? <STR_LIT> : <STR_LIT> ; else return Isload ? <STR_LIT> : <STR_LIT> ; } return Opc


<s> } if ( VECTOR_MODE_P ( mode ) ) * cost += current_tune -> addr_mode_costs -> vector [ op_type ] ; else if ( FLOAT_MODE_P ( mode ) ) * cost += current_tune -> addr_mode_costs -> fp [ op_type ] ; else * cost += current_tune -> addr_mode_costs -> integer [ op_type ] ; } if ( speed_p ) { if ( FLOAT_MODE_P ( mode ) ) { if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) * cost += extra_cost -> ldst . loadd ; else * cost += extra_cost -> ldst . loadf ; } else if ( VECTOR_MODE_P ( mode ) ) * cost += extra_cost -> ldst . loadv ; else { if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) * cost += extra_cost -> ldst . ldrd ; else * cost += extra_cost -> ldst . load ; } } return true


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , REGNO ( oldreg ) , reg_class_names [ alt [ opno1 ] . cl ] ) ; HARD_REG_SET unavailable ; REG_SET_TO_HARD_REG_SET ( unavailable , & live ) ; SET_HARD_REG_BIT ( unavailable , REGNO ( oldreg ) ) ; IOR_COMPL_HARD_REG_SET ( unavailable , call_used_reg_set ) ; IOR_HARD_REG_SET ( unavailable , fixed_reg_set ) ; IOR_HARD_REG_SET ( unavailable , output_risky ) ; IOR_COMPL_HARD_REG_SET ( unavailable , reg_class_contents [ alt [ opno1 ] . cl ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! TEST_HARD_REG_BIT ( unavailable , i ) ) break ; if ( i == FIRST_PSEUDO_REGISTER ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; continue ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , i ) ; rtx newreg = gen_rtx_REG ( recog_data . operand_mode [ opno1 ] , i ) ; validate_change ( insn , recog_data . operand_loc [ opno1 ] , newreg , false ) ; insn = emit_insn_before ( gen_move_insn ( newreg , oldreg ) ,


<s> if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; flags = SYMBOL_REF_FLAGS ( symbol ) ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_THREAD_LOCAL_P ( decl ) ) flags &= ~ SYMBOL_FLAG_HAS_BLOCK_INFO ; SYMBOL_REF_FLAGS ( symbol ) = flags ; symname = XSTR ( symbol , <NUM_LIT> ) ; if ( decl && DECL_P ( decl ) && DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && ( ( TREE_CODE ( decl ) == VAR_DECL && ! DECL_THREAD_LOCAL_P ( decl ) ) || TREE_CODE ( decl ) == FUNCTION_DECL ) && symname [ strlen ( symname ) - <NUM_LIT> ] != ']' ) { char * newname = ( char * ) alloca ( strlen


<s> if ( ! Subtarget -> useConstIslands ( ) )


<s> return ! DataType -> getScalarType ( ) -> isIntegerTy ( <NUM_LIT> ) && isElementTypeLegalForScalableVector (


<s> if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; Register InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } Register ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , InputReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return


<s> case <STR_LIT> : if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions


<s> if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewA , RegY , KillY , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRA , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ; InsInstrs . push_back ( MINewB ) ; InsInstrs . push_back ( MINewC ) ; } else if ( Pattern == MachineCombinerPattern :: REASSOC_XMM_AMM_BMM ) { assert ( NewVRD && <STR_LIT> ) ; MachineInstrBuilder MINewA = BuildMI ( * MF , Leaf -> getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFMULInst ] ) , NewVRA ) . addReg ( RegM11 , getKillRegState ( KillM11 ) ) . addReg ( RegM12 , getKillRegState ( KillM12 ) ) ; MachineInstrBuilder MINewB = BuildMI ( * MF , Prev -> getDebugLoc ( ) , get ( FmaOp ) , NewVRB ) . addReg ( RegX , getKillRegState ( KillX ) ) . addReg ( RegM21 , getKillRegState ( KillM21 ) ) . addReg ( RegM22 , getKillRegState ( KillM22 ) ) ; MachineInstrBuilder MINewD = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FmaOp ) , NewVRD ) . addReg ( NewVRA , getKillRegState ( true ) ) . addReg ( RegM31 , getKillRegState ( KillM31 ) ) . addReg ( RegM32 , getKillRegState ( KillM32 ) ) ; if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewD , NewVRA , true , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRD , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewD , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ; InsInstrs . push_back ( MINewB ) ; InsInstrs . push_back ( MINewD ) ; InsInstrs . push_back ( MINewC ) ; } assert ( ! InsInstrs . empty ( ) && <STR_LIT> ) ; DelInstrs . push_back ( Leaf ) ; DelInstrs . push_back ( Prev


<s> SDValue Hint = Op . getOperand ( <NUM_LIT> ) ; unsigned HintVal ; if ( dyn_cast < ConstantSDNode > ( Hint ) == nullptr || ( HintVal = dyn_cast < ConstantSDNode > ( Hint ) -> getZExtValue ( ) ) > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned Opcode = ( HintVal ? Intr . Opc1 : Intr . Opc0 ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getPrefetchNode ( Opcode , Op , DAG , Mask , Base , Index , Scale , Chain ) ; } case RDTSC : { SmallVector < SDValue , <NUM_LIT> > Results ; getReadTimeStampCounter ( Op . getNode ( ) , dl , Intr . Opc0 , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case RDPMC : { SmallVector < SDValue , <NUM_LIT> > Results ; getReadPerformanceCounter ( Op . getNode ( ) , dl , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case XTEST : { SDVTList VTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue InTrans = DAG . getNode ( <STR_LIT> , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , InTrans ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , dl , Op -> getValueType ( <NUM_LIT> ) , SetCC ) ; return DAG . getNode ( <STR_LIT> , dl , Op -> getVTList ( ) , Ret , SDValue ( InTrans . getNode ( ) , <NUM_LIT> ) ) ; } } llvm_unreachable ( <STR_LIT> )


<s> auto & MF = DAG . getMachineFunction ( ) ; auto & TFL = * Subtarget . getFrameLowering ( ) ; const unsigned SPOffset = TFL . has128ByteRedZone ( MF ) ? - <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . is64Bit ( ) ) { SDValue Zero = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( SPOffset , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT>


<s> return ( uint32x2_t ) __builtin_neon_vshrn_nv2di ( (


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI


<s> InstructionCost <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands , TTI :: TargetCostKind CostKind ) { if ( isa < CastInst > ( U ) || isa < LoadInst > ( U ) || isa < StoreInst > ( U ) ) return BaseT :: getUserCost ( U , Operands , CostKind ) ; if ( U -> getType ( ) -> isVectorTy ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , U -> getType ( ) ) ; return LT . first * BaseT :: getUserCost (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> DEBUG ( { unsigned Block = MI -> getParent ( ) -> getNumber ( ) ; const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; }


<s> switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT>


<s> static SDValue performXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return


<s> static Optional < int64_t > getVectorShiftImm ( Register Reg , MachineRegisterInfo & MRI ) { assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ; MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ; if ( OpMI -> getOpcode ( ) != TargetOpcode :: G_BUILD_VECTOR ) return


<s> start = <STR_LIT> ; } if ( global_options_set . x_rs6000_tune_index ) { fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_tune_index ] . name ) ; start = <STR_LIT> ; } if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata


<s> assert ( AFI -> getStoredByValParamsPadding ( ) == <NUM_LIT> && <STR_LIT> ) ; AFI -> setStoredByValParamsPadding ( Padding ) ; } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ByValStoreOffset - ( int64_t ) TotalArgRegsSaveSize , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; if ( Padding ) { MFI -> CreateFixedObject ( Padding , ArgOffset + ByValStoreOffset - ( int64_t ) ArgRegsSaveSize , false ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } AFI -> setArgRegsSaveSize ( ArgRegsSaveSize + AFI -> getArgRegsSaveSize ( ) ) ; if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; return FrameIndex ; } else


<s> unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . emitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OS . emitInstruction ( MCInstBuilder ( Opc ) , STI ) ; break ; case <STR_LIT> : OS . emitInstruction ( MCInstBuilder ( Opc ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) , STI ) ; break ; case <STR_LIT> : case <STR_LIT> : OS . emitInstruction ( MCInstBuilder ( Opc ) . addReg ( BaseReg ) . addImm ( ScaleVal ) . addReg ( IndexReg ) . addImm ( Displacement ) . addReg ( SegmentReg ) , STI ) ; break ; } assert ( NopSize <= NumBytes && <STR_LIT>


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F ) { return false


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo (


<s> if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { int Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; return SegmentOffset ( IRB , Offset ,


<s> else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , <NUM_LIT> ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) .


<s> int i ; int end_reg ; if ( ! TARGET_PUSHPOP ) return false ; if ( mask == <NUM_LIT> ) return false ; if ( mask & <NUM_LIT> ) return false ; for ( end_reg = <NUM_LIT> , i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( ! end_reg && ( mask & ( <NUM_LIT> << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( <NUM_LIT> << i ) ) ) return false ; } for ( end_reg = <NUM_LIT> , i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( ! end_reg && ( mask & ( <NUM_LIT> << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( <NUM_LIT>


<s> Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; std :: string Str = Tok . getIdentifier ( ) . str ( ) ; std :: string LabelStr ; Parser . Lex ( ) ; const MCExpr * IdVal ; SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Dot ) Parser


<s> rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return


<s> case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , <STR_LIT> ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , <STR_LIT> ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt (


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame , DAG . getIntPtrConstant ( TD -> getPointerSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo (


<s> void <ISA_LIT>TargetLowering :: addTypeForNEON ( EVT VT , EVT PromotedLdStVT , EVT PromotedBitwiseVT ) { if ( VT != PromotedLdStVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; } EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT .


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; if ( ! TLI . hasStandaloneRem ( VT ) ) { return false ; } RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I64 : RTLIB :: UREM_I64 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I128 :


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV ->


<s> if ( ! SU -> SchedClass && SchedModel -> hasInstrSchedModel ( ) ) SU -> SchedClass = SchedModel ->

resolveSchedClass ( SU -> getInstr ( ) ) ;


<s> assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || Register :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT> ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT


<s> unsigned TargetAlign = getStackAlignment ( ) ; if ( TargetAlign == <NUM_LIT> && ( NumGPRSpills & <NUM_LIT> ) ) { if ( CS1Spilled && ! UnspilledCS1GPRs . empty ( ) ) { for ( unsigned i = <NUM_LIT> , e = UnspilledCS1GPRs . size ( ) ; i != e ; ++ i ) { unsigned Reg = UnspilledCS1GPRs [ i ] ; if ( ! AFI -> isThumb1OnlyFunction ( ) || is<ISA_LIT>LowRegister ( Reg ) || Reg == <STR_LIT> ) { MRI . setPhysRegUsed ( Reg ) ; if ( ! MRI . isReserved ( Reg ) ) ExtraCSSpill = true ; break ; } } } else if ( ! UnspilledCS2GPRs . empty ( ) && ! AFI -> isThumb1OnlyFunction ( ) ) { unsigned Reg = UnspilledCS2GPRs . front ( ) ; MRI . setPhysRegUsed ( Reg ) ; if ( ! MRI . isReserved ( Reg ) ) ExtraCSSpill = true ; } } if ( BigStack && ! ExtraCSSpill ) { unsigned NumExtras = TargetAlign / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > Extras ; while ( NumExtras && ! UnspilledCS1GPRs . empty ( ) ) { unsigned Reg = UnspilledCS1GPRs . back ( ) ; UnspilledCS1GPRs . pop_back ( ) ; if ( ! MRI . isReserved ( Reg ) && ( ! AFI -> isThumb1OnlyFunction ( ) || is<ISA_LIT>LowRegister ( Reg ) || Reg == <STR_LIT> ) ) { Extras . push_back ( Reg ) ; NumExtras -- ; } } if ( ! AFI -> isThumb1OnlyFunction ( ) ) { while ( NumExtras && ! UnspilledCS2GPRs . empty ( ) ) { unsigned Reg = UnspilledCS2GPRs . back ( ) ; UnspilledCS2GPRs . pop_back ( ) ; if ( ! MRI . isReserved ( Reg ) ) { Extras . push_back ( Reg ) ; NumExtras -- ; } } } if ( Extras . size ( ) && NumExtras == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Extras . size ( ) ; i != e ; ++ i ) { MRI . setPhysRegUsed ( Extras [ i ] ) ; } } else if ( ! AFI -> isThumb1OnlyFunction ( ) ) { const TargetRegisterClass * RC


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( )


<s> SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = Elt . getConstantOperandVal ( <NUM_LIT> ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold =


<s> static void mips_emit_move_or_split ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type , NULL ) ; else mips_emit_move ( dest ,


<s> __o = __builtin_aarch64_ld3v4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregciv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = STI . getRegisterInfo ( ) ; if ( ! STI . isTargetLinux ( ) || ! ( Info . CallConv == CallingConv :: C || Info . CallConv == CallingConv :: <ISA_LIT>_64_SysV ) ) return false ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Info . Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : Info . OrigArgs ) { if ( OrigArg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; splitToValueTypes ( OrigArg , SplitArgs , DL , Info . CallConv ) ; } <ISA_LIT>OutgoingValueAssigner Assigner ( CC_<ISA_LIT> ) ; <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; bool IsFixed = Info . OrigArgs . empty ( ) ? true : Info . OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( Info . CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Assigner . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { if ( Info . OrigRet . Regs . size ( ) > <NUM_LIT> ) return false ; SplitArgs . clear ( ) ; SmallVector < Register ,


<s> if ( POINTER_SIZE == <NUM_LIT> ) return ( HOST_WIDE_INT_1 << <NUM_LIT>


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , SDLoc ( N ) ,


<s> void <ISA_LIT>ELFStreamer :: EmitPersonality ( const


<s> ev = ( __ev64_opaque__ ) __ev_create_fs ( a , b ) ; return ( __ev64_opaque__ ) __builtin_spe_evfsctsf ( ( __v2sf


<s> case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( getSubtarget ( ) . isTargetNaCl ( ) ? <STR_LIT> : <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI ) ; case TargetOpcode ::


<s> unsigned Opc = LoLoop . IsTailPredicationLegal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . End -> eraseFromParent ( ) ; LoLoop . Dec -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop .


<s> } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsWin64 ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize ( FPRSaveSize ) ; } if ( ! MemOps . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != <NUM_LIT> && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char >

Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const {


<s> unsigned int operand2Opc = N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( operand2Opc == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , N , BRLTys , { SDValue ( SelectIndexedLoad ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ; } else if ( operand2Opc == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , N , BRLTys , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { uint64_t M = RawMask [ i ] ; M = ( EltSize == <NUM_LIT> ? ( ( M >> <NUM_LIT> ) & <NUM_LIT> ) : ( M & <NUM_LIT> ) ) ; unsigned LaneOffset = i & ~ (


<s> void <ISA_LIT>TargetStreamer :: emitCantUnwind (


<s> enum rtx_code cmp_code = * code ; * code = NE ; * op0 = loongarch_allocate_fcc ( FCCmode ) ; * op1 = const0_rtx ; loongarch_emit_binary ( cmp_code , * op0 , cmp_op0 ,


<s> EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ; auto SelectOpcode = VT . isVector (


<s> switch ( Opcode ) { default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> SelectAddrMode2Worker ( Op , N , Base


<s> assert ( ! FirstMI . hasOrderedMemoryRef ( ) && ! TII -> isLdStPairSuppressed ( FirstMI ) && <STR_LIT> ) ; unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return true ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned )


<s> bool <ISA_LIT>IntelAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned

OpNo , unsigned AsmVariant , const char * ExtraCode ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerSRA_PARTS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT>


<s> MachineOperand Src ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Suppress ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Mode ( MI . getOperand ( <NUM_LIT> ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT>


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp


<s> int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex = RegNodeEscapeIndex ; Constant * FI8 = ConstantExpr :: getBitCast ( & F , Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ) ; for ( auto P : FuncInfo . HandlerBaseState ) { Function * Handler = const_cast < Function * > ( P . first ) ; int BaseState = P . second ; IRBuilder < > Builder ( & Handler -> getEntryBlock ( ) , Handler -> getEntryBlock ( ) . begin ( ) ) ; Value * ParentFP = Builder . CreateCall ( FrameAddress , { Builder . getInt32 ( <NUM_LIT> ) } ) ; Value * RecoveredRegNode = Builder . CreateCall ( FrameRecover , { FI8 , ParentFP , Builder . getInt32 (


<s> SmallVector < int , <NUM_LIT> > ZeroableMask ( Mask . begin ( ) , Mask . end ( ) ) ; if ( V2IsZero ) { assert ( ! Zeroable . isNullValue ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i != Size ; ++ i ) if ( Mask [

i ] != SM_SentinelUndef && Zeroable [ i ] ) ZeroableMask [ i ] = SM_SentinelZero ;


<s> return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getMemoryVT ( ) , LD -> isVolatile ( ) , LD -> isInvariant ( ) ,

LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> MCSymbol * <ISA_LIT>_MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , const TargetMachine & TM , MachineModuleInfo * MMI ) const { return TM . getSymbol


<s> static inline void desc_reg_gr ( unsigned char reg , unsigned char dst , struct unw_state_record * sr ) { set_reg ( sr -> curr . reg + reg , UNW_WHERE_GR , sr

-> region_start + sr -> region_len - <NUM_LIT> , dst ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>BaseInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { MachineInstrBuilder MIB ; MachineBasicBlock :: iterator CallPt ; unsigned Opc ; bool isThumb = Subtarget . isThumb ( ) ; if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; It -- ; return CallPt ; } saveLROnStack ( MBB , It )


<s> ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { unsigned rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm


<s> return __builtin_mve_vcmpeqq_n_fv4sf ( __a ,


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo (


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( GET_CODE ( length ) == CONST_INT ) { if ( INTVAL ( length ) <= <NUM_LIT> * MAX_MOVE_BYTES ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) ) ; return true


<s> return MIB . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm


<s> static bool isCSRestore ( MachineInstr & MI , const MCPhysReg * CSRegs ) { if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) return true ; else if ( MI . getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) if ( !

isCalleeSavedRegister ( MI . getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ;


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> static bool isCSRestore ( MachineInstr & MI , const MCPhysReg * CSRegs ) { if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) return true ; else if ( MI . getOpcode (


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> void <ISA_LIT>FrameLowering :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) , unsigned NumAlignedDPRCS2Regs , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , true , false , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG

. getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( )

-> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ;


<s> assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo


<s> Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return Sum ; } } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= DataSize && <STR_LIT> ) ; assert ( NumBytes <= FullSizeBytes && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes - <NUM_LIT> - i ) ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> (


<s> InstructionCost <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , TTI :: CastContextHint CCH , TTI :: TargetCostKind CostKind , const Instruction * I ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; InstructionCost Cost = BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind , I ) ; Cost = vectorCostAdjustment ( Cost , Opcode , Dst ,


<s> int getFramePointerRegister ( ) override final {


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ) { <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const


<s> if ( Reg == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , true , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast <


<s> } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VSRegs [ IntVal ] ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VRegs [ IntVal ] ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = CRRegs [ IntVal ] ; } else return true ; getParser ( ) . Lex ( ) ; return false ; } return


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> static rtx hppa_tls_call ( rtx arg ) { rtx ret ; ret = gen_reg_rtx


<s> void <ISA_LIT>AsmPrinter :: emitAsanReportError ( Module & M , unsigned Reg , const ASanAccessInfo & AccessInfo , MCSubtargetInfo & STI ) { std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; MCSymbol * ReportError = OutContext . getOrCreateSymbol ( <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> + Reg ) , STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( ReportError , MCSymbolRefExpr :: VK_PLT , OutContext ) )


<s> Value * <ISA_LIT>IREmitter :: visitVPERMV3 ( const SDNode *


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return <STR_LIT> ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( ! GV ) return <STR_LIT> ; if ( GV -> hasDLLImportStorageClass (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else if ( const <ISA_LIT>MCExpr * ME = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { ME -> print ( OS ) ; return ; } else SRE = cast < MCSymbolRefExpr > ( Expr ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT>


<s> ModulePass * llvm :: create<ISA_LIT>16HardFloat ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>16HardFloat ( TM


<s> static bool csky_can_use_ldstm ( int mask , int * br , int * er ) { int regno ; int begin_reg = <NUM_LIT> , end_reg = <NUM_LIT> ; int count = <NUM_LIT> ; if ( ! TARGET_MULTIPLE_STLD ) return false ; if ( mask & <NUM_LIT> ) return false ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( mask & <NUM_LIT> <<


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand


<s> assert ( Load -> getMemoryVT ( ) == Store -> getMemoryVT ( ) && <STR_LIT> ) ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( Load -> getBasePtr ( ) . getOpcode ( ) == <STR_LIT> ) return false ; if ( Store -> getBasePtr ( ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( Load -> isInvariant ( ) ) return true ; if ( Load -> getAlignment ( ) >= Size && Store -> getAlignment ( ) >= Size ) return true ; const Value * V1 = Load -> getSrcValue ( ) ; const Value * V2 = Store -> getSrcValue ( ) ; if ( ! V1 || ! V2 ) return false ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( )


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( ( SetCCOpcode == <STR_LIT> || SetCCOpcode == <STR_LIT> ) && <STR_LIT> ( Op0 . getNode ( ) ) ) std :: swap ( Op0 , Op1 ) ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : SSECC =


<s> MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; WorkList . append ( Node -> begin ( ) , Node ->


<s> } if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) if ( <ISA_LIT>ELFStreamer * MES = dyn_cast < <ISA_LIT>ELFStreamer > ( & OutStreamer ) ) MES -> emit<ISA_LIT>STOCG ( * Subtarget , CurrentFnSym , ( unsigned ) ELF :: STO_MIPS_MICROMIPS ) ; OutStreamer . EmitLabel


<s> InConstantPool = true ; } OutStreamer -> emitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) emitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else emitGlobalConstant ( MF -> getDataLayout ( ) , MCPE .


<s> Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; MemOpCost *= getSVEGatherScatterOverhead ( Opcode ) ; return LT . first * MemOpCost * getMaxNumElements (


<s> return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op , DAG


<s> EVT VecVT = N -> getValueType ( <NUM_LIT> ) ; EVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits (


<s> EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( ! IsPIC && ! IsN64 ) { JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; HiPart = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI ) ; JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; } else { unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OfstFlag = IsN64 ? <STR_LIT>


<s> return ( <NUM_LIT> && ( ! TARGET_SHCOMPACT || crtl -> args . info . stack_regs == <NUM_LIT> ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC ( decl ) ) || ( decl && DECL_VISIBILITY


<s> rtx insn , next_tail , head , tail ; get_block_head_tail ( b , & head , & tail ) ; next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + <NUM_LIT> * find_insn_regmode_weight


<s> MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) ConvertVPTBlocks ( LoLoop ) ; for ( auto * I : LoLoop . ToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; I -> eraseFromParent ( ) ; } for ( auto * I : LoLoop . BlockMasksToRecompute ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; recomputeVPTBlockMask ( * I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; } } PostOrderLoopTraversal DFS ( LoLoop . ML , * MLI ) ; DFS . ProcessLoop ( ) ; const SmallVectorImpl < MachineBasicBlock * > & PostOrder =


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { assert ( ( ( Val && ! VRegs . empty ( ) ) || ( ! Val && VRegs . empty ( ) ) ) && <STR_LIT> ) ; if ( VRegs . size ( ) > <NUM_LIT> ) return false ; MIRBuilder . buildInstr ( <STR_LIT> ) ; return true


<s> SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp ,


<s> static SDValue setBounds ( SelectionDAG & DAG , SDValue Val , uint64_t Length , bool CSetBoundsStatsLogged ) { return setBounds ( DAG , Val , DAG . getIntPtrConstant ( Length , SDLoc ( Val


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL =


<s> } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; if ( Offset != MFI . getObjectOffset ( FI ) ) return false ; if ( VA . getLocVT ( ) . getSizeInBits ( ) > Arg . getValueSizeInBits ( ) ) { if ( Flags . isZExt ( ) != MFI . isObjectZExt ( FI ) || Flags . isSExt ( ) != MFI . isObjectSExt


<s> SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , NewPtr , Ld -> getSrcValue (

) , Ld -> getSrcValueOffset ( ) + <NUM_LIT> , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , NewAlign ) ;


<s> bool Hash = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; Hash = true ; } bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val <


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE )


<s> EVT VT = V . getValueType ( ) ; unsigned Opcode = V . getOpcode ( ) ; if ( const ShuffleVectorSDNode * SV = dyn_cast < ShuffleVectorSDNode > ( N ) ) { int Elt = SV -> getMaskElt ( Index ) ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElems = ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SDValue ImmN ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( ShufVT . getVectorElementType ( ) ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? N -> getOperand ( <NUM_LIT>


<s> unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation DstML1 ( MachineLocation :: VirtualFP , Offset + <NUM_LIT> ) ; MachineLocation SrcML0 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; MachineLocation SrcML1 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; if ( ! STI . isLittle ( ) ) std :: swap


<s> bool <ISA_LIT>FastISel :: EmitStore ( MVT VT , unsigned SrcReg , Address & Addr , unsigned Alignment ) { if ( VT != <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( SrcReg ) . addReg

( Addr . Base . Reg ) . addImm ( Addr . Offset ) ;


<s> setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> - i ] , VPAlign [ i ] , false ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , true , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec , VecElems , Builder ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec

[ i ] , UndefValue :: get ( Vec [ <NUM_LIT> ] -> getType ( ) ) , VPShuf ) ;


<s> return Ctx . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getMetadata ( ) ,


<s> unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock & prologueMBB = MF . front ( ) ; MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( MachineBasicBlock :: livein_iterator I = prologueMBB . livein_begin ( ) , E = prologueMBB . livein_end ( ) ; I != E ; I ++ ) { stackCheckMBB -> addLiveIn ( * I ) ; incStackMBB -> addLiveIn ( * I ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT>


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( Subtarget -> hasXOP ( ) && <STR_LIT> ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Lower256IntArith ( Op , DAG ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( auto * BVAmt = dyn_cast < BuildVectorSDNode > ( Amt ) ) { if ( auto * RotateConst = BVAmt ->


<s> rtx lo , pattern ; lo = gen_rtx_REG ( SImode , LO_REGNO ) ; if ( dest ) pattern = gen_mulsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) ) ; else pattern = gen_mulsi3_lo ( lo , src1 , src2 ) ; mep_rewrite_mult ( insn ,


<s> return Kind == Immediate && isUInt < <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthExtractVectorElt ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; assert ( InVT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , InVT ) ; SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op . getOperand (


<s> return mips_abi == ABI_EABI && arg . named


<s> bool isMoveWideImm ( unsigned RegWidth , const <ISA_LIT>MCExpr :: VariantKind * PermittedModifiers , unsigned NumModifiers ) const { if ( ! isImmWithLSL ( ) ) return false ; if ( ImmWithLSL . ShiftAmount % <NUM_LIT> != <NUM_LIT> ) return false ; if ( ImmWithLSL . ShiftAmount >= RegWidth ) return


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT MaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; SDLoc dl ( Op


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) )


<s> return ( __m256i ) __builtin_ia32_pmaddubsw256 ( ( __v32qi ) __X ,


<s> if ( ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & <NUM_LIT> ) ^


<s> if ( ! isLoweredToCall ( F ) ) continue ; } return ; } if ( I . getType ( ) -> isVectorTy ( ) ) return ; SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold =


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static


<s> OpIdx = <NUM_LIT> ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { unsigned Sm = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm + <NUM_LIT> ) ) ) ; OpIdx += <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRm


<s> void <ISA_LIT>SEInstrInfo :: ExpandBuildPairF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & Mtc1Tdd = get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg

( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ;


<s> if ( Amount != <NUM_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; bool isThumb = AFI -> isThumbFunction ( ) ; <STR_LIT> Pred = isThumb ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = isThumb ? <NUM_LIT> : Old -> getOperand ( <NUM_LIT> ) .


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size (


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; uint64_t Immed ; if ( Root . isImm ( ) ) Immed = Root . getImm ( ) ; else if ( Root . isCImm ( ) ) Immed = Root . getCImm ( ) -> getZExtValue ( ) ; else if ( Root . isReg ( ) ) { MachineInstr * Def = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( Def -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) return false ; MachineOperand & Op1 = Def -> getOperand ( <NUM_LIT> ) ; if ( ! Op1 . isCImm ( ) || Op1 . getCImm ( ) -> getBitWidth ( ) > <NUM_LIT> ) return false ; Immed = Op1 . getCImm ( ) -> getZExtValue ( ) ; } else return false ; unsigned ShiftAmt ; if ( Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; } else if ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; Immed = Immed >> <NUM_LIT> ; } else return false ; unsigned ShVal = <STR_LIT> ( <STR_LIT> , ShiftAmt ) ; Result1 . ChangeToImmediate ( Immed ) ; Result1 . clearParent ( ) ; Result2 . ChangeToImmediate ( ShVal ) ; Result2 . clearParent ( ) ; return


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> )


<s> Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState (


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; MVT OpVT = N0 . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; APInt DemandedBits = APInt :: getAllOnes ( OpVT . getScalarSizeInBits ( ) ) ; APInt DemandedHiElts = APInt :: getSplat ( <NUM_LIT> * NumElts , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; bool Op0HiZero = DAG . MaskedValueIsZero ( N0 . getOperand ( <NUM_LIT> ) , DemandedBits , DemandedHiElts ) || DAG . MaskedValueIsZero ( N0 . getOperand ( <NUM_LIT> ) , DemandedBits , DemandedHiElts ) ; bool Op1HiZero = DAG . MaskedValueIsZero ( N1 . getOperand ( <NUM_LIT> ) , DemandedBits , DemandedHiElts ) || DAG . MaskedValueIsZero ( N1 . getOperand ( <NUM_LIT> ) , DemandedBits , DemandedHiElts ) ; if ( ! Op0HiZero || ! Op1HiZero ) return SDValue ( ) ; SmallVector < int > Mask ; for ( int i = <NUM_LIT> ; i != (


<s> static const char * pru_comparison_str ( enum rtx_code cond ) { switch ( cond ) { case NE : return <STR_LIT> ; case EQ :


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned NumInserted = <NUM_LIT> ; if ( ! Cond . empty ( ) ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . add ( Cond


<s> return ( __a + ( __b * __aarch64_vget_lane_any (


<s> const MCInstrDesc & MCid = I -> getDesc ( ) ; switch ( MCid . getOpcode ( ) ) { default : ++ I ; continue ; case <STR_LIT> : BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addReg ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; case <STR_LIT> : ExpandBuildPairF64 ( MBB , I ) ; break ; case <STR_LIT> : ExpandExtractElementF64 ( MBB , I ) ; break ; } MBB . erase ( I ++ ) ; Changed = true


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG


<s> SDValue <ISA_LIT>16DAGToDAGISel :: get<ISA_LIT>16SPAliasReg ( ) { unsigned <ISA_LIT>16SPAliasReg = MF -> getInfo < <ISA_LIT>FunctionInfo


<s> if ( attr ) return ( TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) == <NUM_LIT> ) ; if ( ix86_function_type_abi ( fntype ) == MS_ABI ) return true ; } return KEEP_AGGREGATE_RETURN_POINTER !=


<s> MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF


<s> case Instruction :: Store : return <ISA_LIT>SelectStore ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: Call : return <ISA_LIT>SelectCall ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I


<s> return parseRegister ( Operands , RegGR , <STR_LIT> ,


<s> static bool canUseLocalRelocation ( const MCSectionMachO & Section , const MCSymbol & Symbol , unsigned Log2Size ) { if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) return true ; if ( Log2Size !=


<s> insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case


<s> case MCK_3 : ImmVal = <NUM_LIT> ; break ; default : return Match_InvalidOperand ; } <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( Op . isImm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain


<s> rtx_insn * insn ; unsigned int int_arg_first ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( TARGET_FLAT ) { sparc_leaf_function_p = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } else if ( flag_delayed_branch ) { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_INCOMING_INT_ARG_FIRST ; } else { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } if ( TARGET_ARCH64 && aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , int_arg_first + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , int_arg_first ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! SPARC_SIMM13_P ( delta ) ) { rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ] && vcall_offset < - <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch2 , vcall_offset_rtx ) ; vcall_offset_rtx = scratch2 ; } else { rtx increment = GEN_INT ( - <NUM_LIT> ) ; while ( ! SPARC_SIMM13_P ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch , increment ) ) ; vcall_offset += <NUM_LIT> ; } vcall_offset_rtx = GEN_INT ( vcall_offset ) ; } emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , scratch , vcall_offset_rtx ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function


<s> char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( SPARC_STACK_BIAS ) ; output_asm_insn ( <STR_LIT> , xops


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable (


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask (


<s> return __aarch64_vdup_laneq_u32 ( __a ,


<s> rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = <NUM_LIT> ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( )


<s> return ( __m64 ) __builtin_arm_wmulwum ( ( __v2si )