<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { if ( DefRelocModel == Reloc :: Default ) setRelocationModel ( Reloc :: Static ) ; PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel ,


<s> for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) ==


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> x . q = q ; return ( x . d [ <NUM_LIT> ]


<s> index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / <NUM_LIT> , true ) ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / <NUM_LIT> , true ) ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case vec_construct : { int cost = ix86_vec_cost ( mode , ix86_cost -> sse_op


<s> int NumElements = VT . getVectorNumElements ( ) ; assert ( VT . getScalarSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ( int ) Mask . size ( ) == NumElements && <STR_LIT> ) ; auto Lower = [ & ] ( int Scale ) -> SDValue { SDValue InputV ; bool AnyExt = true ; for ( int i = <NUM_LIT> ; i < NumElements ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) continue ; if ( i % Scale != <NUM_LIT> ) { if ( ! Zeroable [ i ] ) return SDValue ( ) ; AnyExt = false ; continue ; } SDValue V = Mask [ i ] < NumElements ? V1 : V2 ; if ( ! InputV ) InputV = V ; else if ( InputV != V ) return SDValue ( ) ; if ( Mask [ i ] % NumElements != i / Scale ) return SDValue (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> static DecodeStatus DecodeBranchTarget21MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>ELFMCAsmInfo :: setUseIntegratedAssembler ( bool Value ) { UseIntegratedAssembler =


<s> tmpInst . setOpcode ( Opcode ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( SrcReg ) ) ; tmpInst . addOperand ( Imm


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target


<s> else Reg = V64RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> unsigned AndOp = getANDriOpcode ( Uses64BitFramePtr , Val ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) ,

Reg ) . addReg ( Reg ) . addImm ( Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig (


<s> for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale *= <NUM_LIT> ) { bool Match = true ; unsigned NumDstElts = NumMaskElts / Scale ; for ( unsigned i = <NUM_LIT> ; i != NumDstElts && Match ; ++ i ) { Match &= isUndefOrEqual ( Mask [ i * Scale ] , ( int ) i ) ; Match &= isUndefOrZeroInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; } if ( Match ) { unsigned SrcSize = std :: max ( <NUM_LIT> , NumDstElts * MaskEltSize ) ; MVT ScalarTy = MaskVT . isInteger ( ) ? MaskVT . getScalarType ( ) : <STR_LIT> ( MaskEltSize ) ; SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) { V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( <STR_LIT> ) ; } else Shuffle = unsigned ( <STR_LIT> ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; default : return


<s> VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ; } return false ; } case <STR_LIT> : { VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ; } return


<s> return MatchOperand_ParseFail ; } auto PRFM = LookupByEncoding ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM . getValueOr ( <STR_LIT> ) , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByName ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( * PRFM , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex (


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( ( index & <NUM_LIT> ) > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + ( index & <NUM_LIT> ) ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_BNDR

: \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ case TYPE_MVSIBX : \ return prefix ## _XMM0 + index ; \ case TYPE_MVSIBY : \ return prefix ## _YMM0 + index ; \ case TYPE_MVSIBZ : \ return prefix ## _ZMM0 + index ; \ } \ }


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . TargetABI == <ISA_LIT>TargetMachine :: <STR_LIT> ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; switch ( Kind ) { case Immediate : Inst . addOperand ( MCOperand :: createImm ( getImm ( ) ) ) ; break ; case ContextImmediate


<s> void FPS :: shuffleStackTop ( const unsigned char * FixStack , unsigned FixCount , MachineBasicBlock :: iterator I ) { while ( FixCount -- ) { unsigned OldReg = getStackEntry ( FixCount ) ; unsigned Reg = FixStack [ FixCount ] ; if ( Reg == OldReg ) continue ; moveToTop ( Reg , I )


<s> OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_SPESpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat8Spill


<s> assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || DestReg . isVirtual ( ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; } return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg ,


<s> AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Equal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; Tok = Parser . getTok ( ) ; if ( ! parseFpABIValue ( FpAbiVal , <STR_LIT> ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveSetFp ( FpAbiVal ) ; Parser . Lex ( ) ; return false


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else if ( IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveSEHAllocStack ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHPrologEnd ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveR19R20X ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFPLR ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFPLRX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveReg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveLRPair ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFReg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( Loc


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is64BitVector ( ) ) return SDValue ( ) ; unsigned LoadIdx = IsLaneOp ? <NUM_LIT> : <NUM_LIT> ; SDNode * LD = N -> getOperand ( LoadIdx ) . getNode ( ) ; if ( LD -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lane ; if ( IsLaneOp ) { Lane = N -> getOperand ( <NUM_LIT> ) ; auto * LaneC = dyn_cast < ConstantSDNode > ( Lane ) ; if ( ! LaneC || LaneC -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; } LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; SmallVector < const SDNode * , <NUM_LIT> > Worklist ; Visited . insert ( Addr . getNode ( ) ) ; Worklist . push_back ( User ) ; Worklist . push_back ( LD ) ; Worklist . push_back ( Vector .


<s> continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; Predicates . insert ( Predicate ) ; IRBuilder < > Builder ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( cast < Instruction > ( Predicate ) ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * TailPredicate = Builder . CreateCall ( VCTP , Processed ) ; Predicate -> replaceAllUsesWith ( TailPredicate ) ; NewPredicates [ Predicate ] = cast < Instruction > ( TailPredicate ) ; Value * Remaining = Builder . CreateSub ( Processed , Factor ) ; Processed -> addIncoming ( Remaining , L ->


<s> auto NewCarryReg = DAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , <STR_LIT> , OldCarry ) ; auto NewCarry = DAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , OldCarry . getValueType

( ) , SDValue ( NewCarryReg , <NUM_LIT> ) , DAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ;


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI


<s> if ( Reg > <NUM_LIT> ) return false ; ATReg = Reg ; return true


<s> void iq2000_expand_eh_return ( rtx address ) { HOST_WIDE_INT gp_offset = cfun ->


<s> bool <ISA_LIT>InstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const { if ( ! N -> isMachineOpcode ( ) ) return false ; DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( N -> getMachineOpcode ( ) ) ; if ( I == MemOp2RegOpTable . end ( ) ) return false ; unsigned Opc = I -> second . first ; unsigned Index = I -> second . second & <NUM_LIT> ; bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; const TargetInstrDesc & TID = get ( Opc ) ; const TargetRegisterClass * RC = TID . OpInfo [ Index ] . getRegClass ( & RI ) ; unsigned NumDefs = TID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back


<s> else if ( cortexa7_younger ( file , verbose , insn ) && first_younger == - <NUM_LIT> ) first_younger = i ; } if ( first_younger == - <NUM_LIT> ) { if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; return ; } if ( first_older_only == - <NUM_LIT> ) { if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; return ; } if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ first_older_only ] ) , INSN_UID ( ready [ first_younger ] ) ) ; rtx_insn * first_older_only_insn =


<s> SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << TypeShiftAmt ) | ( ( unsigned ) i >> ( SplatBitSize - TypeShiftAmt ) ) ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << <NUM_LIT> ) | ( i < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) { SDValue T = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; return BuildVSLDOI ( T , T , <NUM_LIT> , Op . getValueType ( ) , DAG , dl ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << <NUM_LIT> ) | ( i < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) { SDValue T = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; return BuildVSLDOI ( T , T , <NUM_LIT> , Op . getValueType ( ) , DAG , dl ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << <NUM_LIT> ) | ( i < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) { SDValue T = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; return BuildVSLDOI ( T , T , <NUM_LIT> , Op . getValueType ( ) , DAG , dl ) ; } } return SDValue ( )


<s> if ( SDValue V = PerformVQDMULHCombine ( N , DAG ) ) return V ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; auto IsSignedSaturate = [ & ] ( SDNode * Min , SDNode * Max ) { if ( Min -> getOpcode ( ) != <STR_LIT> ) std :: swap ( Min , Max ) ; if ( Min -> getOpcode ( ) != <STR_LIT> || Max -> getOpcode ( ) != <STR_LIT> ) return false ; APInt SaturateC ; if ( VT == <STR_LIT> ) SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; else SaturateC = APInt ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ; APInt MinC , MaxC ; if ( ! <STR_LIT> ( Min -> getOperand ( <NUM_LIT> ) . getNode ( ) , MinC ) || MinC != SaturateC ) return false ; if ( ! <STR_LIT> ( Max -> getOperand ( <NUM_LIT> ) . getNode ( ) , MaxC ) || MaxC != ~ SaturateC ) return false ; return true ; } ; if ( IsSignedSaturate ( N , N0 . getNode ( ) ) ) { SDLoc DL (


<s> bool isProfitableForNoCSROpt ( const Function & F ) const override { return false


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg


<s> SDValue Ones = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> || ! Shift . hasOneUse ( ) || ! <STR_LIT> ( Ones . getNode ( ) ) ) return SDValue ( ) ; auto * ShiftAmt = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ; EVT ShiftEltTy = Shift . getValueType ( ) . getVectorElementType ( ) ; if ( ! ShiftAmt || ShiftAmt -> getZExtValue ( ) != ShiftEltTy . getSizeInBits


<s> static DecodeStatus DecodeMSA128BRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> } } if ( ! parseOptionalToken ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , StartLoc , EndLoc ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , StartLoc , EndLoc ) ; } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc BaseLoc = getLexer ( ) . getLoc ( ) ; const MCExpr * E ; StringRef ErrMsg ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) && getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseExpression ( E , EndLoc ) || check ( ! isa < <ISA_LIT>MCExpr > ( E ) , BaseLoc , <STR_LIT> ) ) return nullptr ; BaseReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return ErrorOperand ( BaseLoc , <STR_LIT> , SMRange ( BaseLoc , EndLoc ) ) ; } if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( E , EndLoc ) ) return nullptr ; if ( ! isa < <ISA_LIT>MCExpr > ( E ) ) { int64_t ScaleVal ; if ( ! E -> evaluateAsAbsolute ( ScaleVal , getStreamer ( ) . getAssemblerPtr ( ) ) ) return ErrorOperand ( Loc , <STR_LIT> ) ; if ( ScaleVal != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } else { IndexReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> ) return ErrorOperand ( Loc , <STR_LIT> ) ; if ( IndexReg == <STR_LIT> ) return ErrorOperand ( Loc , <STR_LIT> ) ; if ( parseOptionalToken ( AsmToken :: Comma )


<s> bool NonRI = false , SpillsVRS = false ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment


<s> static bool regJustKilledBefore ( const LiveIntervals & LIs , unsigned reg , const MachineInstr & MI ) { const LiveInterval & LI = LIs . getInterval ( reg ) ; SlotIndex SI = LIs . getInstructionIndex ( MI ) ; return LI . expiredAt (


<s> SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VTs


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB

, OS , Emitter , RelaxAll , NoExecStack ) ;


<s> static unsigned AddLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { assert ( RC -> contains ( PReg ) &&


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn )


<s> return ShOpcVal == <STR_LIT> && ( ShAmt == <NUM_LIT> || ( Subtarget -> isSwift (


<s> void sh_pr_interrupt ( struct cpp_reader * pfile ATTRIBUTE_UNUSED ) { sh_add_function_attribute ( <STR_LIT> )


<s> static TargetLowering :: ArgListTy getDivRemArgList ( const SDNode * N , LLVMContext * Context , const <ISA_LIT>Subtarget * Subtarget ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } if ( Subtarget -> isTargetWindows ( ) && Args . size ( ) >= <NUM_LIT> ) std :: swap ( Args [ <NUM_LIT> ] , Args [ <NUM_LIT> ] ) ; return


<s> static struct machine_function * mmix_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > (


<s> MCAsmParser & getParser ( ) const { return Parser


<s> for ( unsigned i = <NUM_LIT> , ie = ValueRotsVec . size ( ) ; i < ie ; ++ i ) if ( ValueRotsVec [ i ] . Repl32 ) { if ( ValueRotsVec [ i ] . NumGroups > ValueRotsVec [ <NUM_LIT> ] . NumGroups ) MaxGroupsIdx = i ; break ; } } ValueRotInfo & VRI = ValueRotsVec [ MaxGroupsIdx ] ; bool NeedsRotate = false ; if ( VRI . RLAmt ) { NeedsRotate = true ; } else if ( VRI . Repl32 ) { for ( auto & BG : BitGroups ) { if ( BG . V != VRI . V || BG . RLAmt != VRI . RLAmt || BG . Repl32 != VRI . Repl32 ) continue ; if ( BG . StartIdx < <NUM_LIT> && BG . EndIdx < <NUM_LIT> && BG . StartIdx < BG . EndIdx ) continue ; NeedsRotate = true ; break ; } } if ( NeedsRotate ) Res = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , InstCnt ) ; else Res = VRI . V ; if ( Res ) eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt && BG . Repl32 == VRI . Repl32 ; } ) ; } if ( ! Res ) for ( auto I = BitGroups . begin ( ) , IE = BitGroups . end ( ) ; I != IE ; ++ I ) { if ( SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , false ) < SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , true ) ) { if ( I != BitGroups . begin ( ) ) { BitGroup BG =


<s> case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; } DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeSImm < <NUM_LIT> > ( Inst , offset , Addr , Decoder ) ; if ( writeback && Rt == Rn && Rn != <NUM_LIT> ) { return


<s> if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == <NUM_LIT> || ImmVal == <NUM_LIT> ) return TTI :: TCC_Free ; } ImmIdx = <NUM_LIT> ; break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && Imm . getZExtValue ( ) == <NUM_LIT> ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction ::


<s> static SDValue performVecReduceAddCombineWithUADDLP ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue VecReduceOp0 = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = VecReduceOp0 . getOpcode ( ) ; if ( Opcode != <STR_LIT> || VecReduceOp0 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue ABS = VecReduceOp0 ; if ( ABS -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || ABS -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue SUB = ABS -> getOperand ( <NUM_LIT> ) ; unsigned Opcode0 = SUB -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; unsigned Opcode1 = SUB -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( SUB -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> || SUB -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; bool IsZExt = false ; if ( Opcode0 == <STR_LIT> && Opcode1 == <STR_LIT> ) { IsZExt = true ; } else if ( Opcode0 == <STR_LIT> &&


<s> Value * <ISA_LIT>IREmitter :: visitVST4_UPD ( const


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == OpInfo [ <NUM_LIT> ] . RegClass && OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; unsigned RegClassPair = OpInfo [ <NUM_LIT> ] . RegClass ; unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 (


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( create<ISA_LIT>BranchTargetsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) )

addPass ( createCFGuardLongjmpPass ( ) ) ;


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = XEXP

( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( create<ISA_LIT>PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None &&

EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) {


<s> DebugLoc DL = MI . getDebugLoc ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; bool IsPrimed = <STR_LIT> . contains ( DestReg ) ; Register Reg = <STR_LIT> + ( DestReg - ( IsPrimed ? <STR_LIT> : <STR_LIT> ) ) * <NUM_LIT> ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; emitAccSpillRestoreInfo ( MBB , IsPrimed , true ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg ) , FrameIndex , IsLittleEndian ? <NUM_LIT> : <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg + <NUM_LIT> ) , FrameIndex , IsLittleEndian ? <NUM_LIT>


<s> void DecodePSHUFHWMask ( unsigned NumElts , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { for ( unsigned l = <NUM_LIT> ; l


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { MCValue Value ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , Layout , Fixup ) ) return false ; if ( Value . isAbsolute ( ) ) { int64_t Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; if ( ( Fixup == nullptr || ( unsigned ) Fixup -> getKind ( ) != <STR_LIT> ) && ( Result >= <NUM_LIT> ) ) return false ; Res = MCValue :: get ( Result ) ; } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr ::


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) ) ; return


<s> return getGOT ( GN , DAG , TargetFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , TargetFlags ) ; } else { Result = getAddr ( GN , DAG , TargetFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result

, MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerWindowsGlobalTLSAddress ( Op , DAG ) ; llvm_unreachable (


<s> else if ( DEFAULT_ABI != ABI_DARWIN ) { bool is_local = ( fndecl && ! DECL_EXTERNAL ( fndecl ) && ! DECL_WEAK ( fndecl ) && ( * targetm . binds_local_p ) ( fndecl ) ) ; if ( is_local ) ; else if ( flag_plt ) { if ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) cum -> call_cookie |= CALL_LONG ; } else { if ( ! ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; } } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 ) ) { cum -> escapes = call_ABI_of_interest ( fndecl ) ; if ( cum -> escapes ) { tree return_type ; if ( fntype ) { return_type = TREE_TYPE ( fntype


<s> static Target The<ISA_LIT>elTarget ; return


<s> Hi = DAG . getBitcast ( ByteVT , Hi ) ; if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getTargetConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ByteVT == <STR_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - ByteRotation ; int HiByteShift = ByteRotation ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getTargetConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getTargetConstant ( HiByteShift , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT>

, DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; StringRef Symbol = STI . getTargetLowering ( ) -> getStackProbeSymbolName ( MF ) ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; } unsigned AX = Uses64BitFramePtr


<s> assert ( ! InsertPts . empty ( ) && <STR_LIT> ) ; for ( const auto & IPI : InsertPts ) { IRBuilder < > Builder ( IPI . first ) ; LoadInst * LoadedCst = Builder . CreateLoad ( & PromotedGV ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadedCst -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs (


<s> return selectBDAddr ( <STR_LIT> , Addr , Base , Disp


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Elt = Op . getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || Elt . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != VT . getVectorElementType ( ) ) return false ; if ( ! V0 . getNode ( ) ) { V0 = Elt . getOperand ( <NUM_LIT> ) ; V0NumElts = V0 . getValueType ( ) . getVectorNumElements ( ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V0 ) { Mask [ i ] = ( cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; continue ; } else if ( ! V1 . getNode ( ) ) { V1 = Elt . getOperand ( <NUM_LIT> ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V1 ) { unsigned Lane = cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) ->


<s> return ( __m128i ) __builtin_ia32_broadcasti32x2_128_mask ( ( __v4si ) __A , ( __v4si )

_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC


<s> if ( Op1 && Op2 && Op1 -> getIntrinsicID ( ) == <STR_LIT> && Op2 -> getIntrinsicID ( ) == <STR_LIT> && Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) == Op2 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) { Value * Ops [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) , Op2 -> getArgOperand ( <NUM_LIT> ) } ; Type * Tys [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; Module * M = I -> getParent ( ) ->


<s> const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute (


<s> FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls . resize ( CmpInst :: LAST_FCMP_PREDICATE + <NUM_LIT> ) ; FCmp64Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F64 , CmpInst ::


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function &


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || STI . isTargetDarwin ( ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasD32 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved )


<s> switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return NULL ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg


<s> if ( TARGET_64BIT ) aputs ( <STR_LIT> ) ; else if ( TARGET_PA_20 )


<s> assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Result ; SDLoc DL ( Op ) ; ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress (

GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ;


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> )


<s> else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue (


<s> key . m_pInfo = pInfo ; key . m_Addend = pAddend ; GotEntryMapType :: iterator it = m_GotLocalEntriesMap . find ( key ) ; if ( it == m_GotLocalEntriesMap . end ( )


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TM . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF


<s> if ( ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) == <STR_LIT> )


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand


<s> void <ISA_LIT>ConstantIslands :: verify ( MachineFunction & MF ) { assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - <NUM_LIT> ] + BBSizes [ i - <NUM_LIT> ] == BBOffsets [ i ] ) ; if ( ! isThumb ) return ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , E = MF . end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) && MBB -> begin ( ) -> getOpcode (


<s> if ( MO . isImm ( ) ) { O << <STR_LIT> ; O . write_hex ( MO . getImm ( ) ) ; } else MO . getExpr ( ) -> print ( O


<s> if ( JUMP_P ( insn ) && INSN_CODE ( insn ) == CODE_FOR_return ) return <STR_LIT> ; if ( NONDEBUG_INSN_P ( insn ) && INSN_CODE ( insn ) < <NUM_LIT> && ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) ) return <STR_LIT> ; return


<s> bool supportPrintSchedInfo ( ) const override


<s> Address ( ) : Kind ( RegBase ) , ExtType ( <STR_LIT> ) , OffsetReg ( <NUM_LIT> ) , Shift ( <NUM_LIT> ) , Offset ( <NUM_LIT> ) , GV ( nullptr ) { Base . Reg =


<s> if ( ( N . getOpcode ( ) == <STR_LIT> ) || ( N . getOpcode ( ) == <STR_LIT> && ( N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ||

N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) ) ) return true ;


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ; } O <<


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc


<s> if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } } return false


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( NumStages != <NUM_LIT> && SizeBits == <NUM_LIT> && Subtarget . hasVLX ( ) ) return SDValue ( ) ; unsigned MaxPackBits = <NUM_LIT> ; if ( CurrentEltBits > <NUM_LIT> && ( PackOpcode == <STR_LIT> || Subtarget . hasSSE41 ( ) ) ) MaxPackBits = <NUM_LIT> ; SDValue Res ; for ( unsigned i = <NUM_LIT> ; i != NumStages ; ++ i ) { unsigned SrcEltBits = std :: min ( MaxPackBits , CurrentEltBits ) ; unsigned NumSrcElts = SizeBits / SrcEltBits ; MVT SrcSVT = <STR_LIT> ( SrcEltBits ) ; MVT DstSVT = <STR_LIT> ( SrcEltBits / <NUM_LIT> ) ; MVT SrcVT = <STR_LIT> ( SrcSVT , NumSrcElts ) ; MVT DstVT = <STR_LIT> ( DstSVT , NumSrcElts * <NUM_LIT> ) ; Res = DAG . getNode ( PackOpcode , DL , DstVT , DAG . getBitcast ( SrcVT , V1 ) , DAG . getBitcast ( SrcVT , V2 ) ) ; V1 = V2 = Res ; CurrentEltBits /= <NUM_LIT> ; } assert ( Res && Res . getValueType ( ) == VT && <STR_LIT> ) ; return Res


<s> virtRegs . insert ( LR -> virtRegs . begin ( ) , LR


<s> case <NUM_LIT> : return UNSPEC_FCMLA ; case <NUM_LIT> : return UNSPEC_FCMLA90 ; case <NUM_LIT> : return UNSPEC_FCMLA180 ; case <NUM_LIT> : return UNSPEC_FCMLA270 ; default : gcc_unreachable


<s> ITState . Cond = <STR_LIT> ( ITState . Cond ) ; } else


<s> else if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImmWithLSL ( Imm , <NUM_LIT> , true , S , E ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc


<s> return isConstantImm ( ) ? ( isInt < Bits > ( getConstantImm ( ) ) || isUInt < Bits > ( getConstantImm ( ) ) )


<s> if ( parseRegisterList ( Operands ) ) return false ; <ISA_LIT>Operand & Op = ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ; if ( ! IsVector && ! Op . isRegList ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( IsVector && ! Op . isDPRRegList ( ) ) { Error ( L , <STR_LIT>


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF .

getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> bool ix86_fp_jump_nontrivial_p ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return true ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return bypass_code != UNKNOWN || second_code


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) ; MBB . insert ( MBB . end


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) { MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = & getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition


<s> return ( __m128i ) __builtin_ia32_vpcomtrueq ( ( __v2di ) __A , (


<s> void setDPRCalleeSavedGapSize ( unsigned


<s> bool hasRequiredFeatures ( FeatureBitset ActiveFeatures


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results ,


<s> if ( W16AvailableInBlock && W17AvailableInBlock && NZCVAvailableInBlock ) Flags |= MachineOutlinerMBBFlags :: UnsafeRegsDead ; LRU . addLiveOuts ( MBB ) ; if ( W16AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( W17AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( NZCVAvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( any_of ( MBB , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; MachineFunction * MF = MBB


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM == Reloc :: Static ) ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , NULL , <NUM_LIT> ) ; return


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc &


<s> if ( ! MO1 . isReg ( ) || MO1 . getReg ( ) != <STR_LIT> || MO2 . getReg ( ) || ! MO3 . isImm ( ) ) return None ; unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> Op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( Op == <STR_LIT> ) return


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF

. getTarget ( ) . getRegisterInfo ( ) ) ;


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: hardenEdgesWithLFENCE ( MachineFunction & MF ) { SmallSetVector < MachineBasicBlock * , <NUM_LIT> > Blocks ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . succ_size ( ) <= <NUM_LIT> ) continue ; auto TermIt = MBB . getFirstTerminator ( ) ; if ( TermIt == MBB . end ( ) || ! TermIt -> isBranch ( ) ) continue ; for ( MachineBasicBlock * SuccMBB : MBB . successors ( ) ) if ( ! SuccMBB ->

isEHPad ( ) ) Blocks . insert ( SuccMBB ) ;


<s> LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addExpr ( Lower . getExpr ( MI -> getOperand ( <NUM_LIT> ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> ## <NUM_LIT> : LoweredMI = lowerRILow ( MI , <STR_LIT> ) ;


<s> LiveBundles . resize ( Bundles -> getNumBundles ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { setKillFlags ( MBB ) ; const unsigned Mask = calcLiveInMask ( &


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoAVX2 ( ) { if ( ! Subtarget . hasAVX2 ( ) ) return ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT>


<s> Align = GetVLDSTAlign ( Align , dl , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( ! IsImmUpdate ) { if ( isVSTfixed ( Opc ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc


<s> if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> opts = TREE_TARGET_OPTION ( target_tree ) ; if ( ( ix86_builtins_isa [ ( int ) code ] . isa & opts -> x_ix86_isa_flags ) || ( ix86_builtins_isa [ ( int ) code ] . isa2 & opts -> x_ix86_isa_flags2 ) ) return ix86_builtin_decl ( code , true ) ; else return


<s> rtx fn , insn , retval ; tree return_type ; machine_mode return_mode ; const char * name ; return_type = DECL_RESULT ( current_function_decl ) ; return_mode = DECL_MODE ( return_type ) ; name = ACONCAT ( ( <STR_LIT> , mips16_call_stub_mode_suffix ( return_mode ) , NULL ) ) ; fn = mips16_stub_function


<s> if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } if ( frame_pointer_needed ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno


<s> return ( __m256i ) __builtin_ia32_paddusb256 ( ( __v32qi )


<s> return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return SelectCmp ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectSIToFP ( I ) ; case Instruction :: FPToSI : return SelectFPToSI ( I ) ; case Instruction :: FAdd : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: SDiv : return SelectSDiv (


<s> if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( ! TM . isPositionIndependent ( ) ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand (


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT>


<s> while ( state -> insns_left == <NUM_LIT> || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state

, insn ) >= <NUM_LIT> ) ) mips_sim_next_cycle ( state ) ;


<s> if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } if ( VT . isInteger ( ) && VT . getScalarSizeInBits ( ) < <NUM_LIT> && canWidenShuffleElements ( Mask ) ) { SmallVector < int , <NUM_LIT> > NewMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) NewMask . push_back ( Mask [ i ] != - <NUM_LIT> ? Mask [ i ] / <NUM_LIT> : ( Mask [ i + <NUM_LIT> ] != - <NUM_LIT> ? Mask [ i + <NUM_LIT> ] / <NUM_LIT> : - <NUM_LIT> ) ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , NewVT , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , NewMask ) ) ; } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> return emitIntExt ( SrcVT , SrcReg , DestVT


<s> for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = OutStreamer -> getContext ( ) . getXCOFFSection ( cast < MCSymbolXCOFF > ( I . first ) -> getUnqualifiedName ( ) , XCOFF :: XMC_TC , XCOFF :: XTY_SD , XCOFF :: C_HIDEXT , SectionKind :: getData ( ) ) ; cast < MCSymbolXCOFF > ( I . second ) ->


<s> MCSymbol * Label = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> + Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ; return


<s> CPEMI -> eraseFromParent ( ) ; BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( & * CPEBB -> begin ( ) ) ) ; adjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB ) && <STR_LIT>


<s> unsigned Register = <NUM_LIT> ; switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler ::


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Narrow ? NarrowVector ( SuperReg , *


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; bool Modified =


<s> Type * Tys [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; Module * M = I -> getParent ( ) -> getParent ( ) -> getParent ( ) ; auto Fn = <STR_LIT> ( M , I -> getIntrinsicID ( ) , Tys ) ; auto CI = CallInst :: Create ( Fn , Ops , I -> getName ( ) , I ) ; I -> replaceAllUsesWith ( CI ) ; I -> eraseFromParent ( ) ; if ( Op1 -> use_empty ( ) ) Op1 -> eraseFromParent ( ) ; if ( Op2 -> use_empty ( ) ) Op2 -> eraseFromParent


<s> static __inline unsigned long long sh_media_MABS_W ( unsigned long long mm ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_absv4hi2 ( (


<s> if ( ( SD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) || ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) return SDValue ( ) ; bool IsLittle = Subtarget -> isLittle ( ) ; SDValue Value = SD -> getValue ( ) , Chain = SD -> getChain ( ) ; EVT VT = Value . getValueType ( ) ; if ( ( VT == <STR_LIT> ) || SD -> isTruncatingStore ( ) ) { SDValue SWL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateStoreLR ( <STR_LIT> , DAG , SD , SWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } assert ( VT == <STR_LIT> ) ; SDValue SDL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle ? <NUM_LIT>


<s> bool useSSE = isScalarFPTypeInSSEReg ( DstVT ) ; if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( DstVT , <STR_LIT> ) ; SDValue FILDOps [ ] = { Chain , Pointer } ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , FILDOps , SrcVT , PtrInfo , Alignment , MachineMemOperand :: MOLoad ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( useSSE ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = DstVT . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( SSFISize , SSFISize , false ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Tys = DAG . getVTList (


<s> unsigned getReg213Opcode ( ) const { assert ( RegOpcodes && <STR_LIT>


<s> Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return VSt ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ; SDNode * VStA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , MemAddr . getValueType ( ) , <STR_LIT> , OpsA , <NUM_LIT> ) ; cast < MachineSDNode > ( VStA ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VStA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return false ; const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> int fd ; fd = open ( <STR_LIT> , O_RDONLY ) ; if ( fd != - <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd )


<s> if ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( T ) ; if ( ! is64Bit || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppc64 ) && ( T .

isOSAIX ( ) || T . isOSLinux ( ) ) ) Ret += <STR_LIT> ;


<s> SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRange , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) { return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( Operand . getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand . getLocRange ( ) ; return Error ( Operand . getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MissingFeature ) == <NUM_LIT> ) { ErrorInfo = ErrorInfoMissingFeature ; return ErrorMissingFeature ( IDLoc , ErrorInfoMissingFeature , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) ,


<s> return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT>


<s> unsigned int max_arg_words = <NUM_LIT> ; unsigned int offset = <NUM_LIT> ; if ( ! TARGET_64BIT ) return <NUM_LIT> ; if ( FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words )


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel (


<s> } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto MaskOp = Mask -> getOpcode ( ) ; if ( ( MaskOp != <STR_LIT> && MaskOp != <STR_LIT> && MaskOp != <STR_LIT> && MaskOp != <STR_LIT> ) || ( Mask -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return false ; break ; } default : return false ; } if ( Pred -> getParent ( ) != PTest -> getParent ( ) ) return false ; MachineBasicBlock :: iterator I = Pred , E = PTest ; ++ I ; for ( ; I != E ; ++ I ) { const MachineInstr & Inst = * I ; if ( Inst . modifiesRegister ( <STR_LIT> , TRI ) ) return false ; } Pred -> setDesc ( TII -> get ( NewOp ) ) ; PTest -> eraseFromParent ( ) ; if ( OpChanged ) { bool succeeded = UpdateOperandRegClass ( Pred ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; Pred -> addRegisterDefined ( <STR_LIT> , TRI ) ; } if ( Pred -> registerDefIsDead ( <STR_LIT> , TRI ) ) { unsigned i = <NUM_LIT> , e


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , StringRef TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT , true ) , Subtype ( st ) { HasDataInCodeSupport =


<s> bool isMSRSystemRegister ( ) const { if ( ! isSysReg (


<s> if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false


<s> void <ISA_LIT>FrameLowering :: emitStackProbeInline ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const


<s> bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITStates . push_back ( CCBits ) ; else ITStates . push_back ( CCBits ^ <NUM_LIT> ) ; } ITStates . push_back (


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr


<s> if ( I -> isPseudo ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; OutStreamer -> EmitInstruction ( TmpInst0 , getSubtargetInfo ( ) ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( )


<s> static DecodeStatus decodePC32DBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address


<s> bool isFloat = ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; int Imm = <NUM_LIT> ; bool UseImm = false ; bool isNegativeImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( Src2Value ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( isZExt ) ? ( int ) CIVal . getZExtValue ( ) : ( int ) CIVal . getSExtValue ( ) ; if ( Imm < <NUM_LIT> && Imm != ( int ) <NUM_LIT> ) { isNegativeImm = true ; Imm = - Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } } else if ( const ConstantFP * ConstFP = dyn_cast < ConstantFP > ( Src2Value ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) if ( ConstFP -> isZero ( ) && ! ConstFP -> isNegative ( ) ) UseImm = true ; } unsigned CmpOpc ; bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm


<s> if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; needIndirectCall = false ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( ! DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isJITCodeModel ( ) ) { unsigned OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && <ISA_LIT>SubTarget . getDarwinVers ( ) < <NUM_LIT> && ( G -> getGlobal ( ) -> isDeclaration ( ) || G -> getGlobal ( ) -> isWeakForLinker ( ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; needIndirectCall = false ; } } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && <ISA_LIT>SubTarget . getDarwinVers ( ) < <NUM_LIT> ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> ,


<s> static DecodeStatus DecodeLoadInt ( MCInst & Inst , unsigned insn , uint64_t Address , const MCDisassembler *


<s> return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val


<s> __inline__ static unsigned long long sh_media_MSHFLO_B ( unsigned long long mm , unsigned long long mn ) { unsigned long long res


<s> ix86_compute_frame_layout ( & frame ) ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs +


<s> SmallVector < uint32_t , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; } if ( VecElems ==


<s> return __builtin_mve_vdupq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> static SDValue lowerVECTOR_SHUFFLE_ILVEV ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { assert ( ( Indices . size ( ) % <NUM_LIT> ) == <NUM_LIT> ) ; int WsIdx = <NUM_LIT> ; int WtIdx = ResTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Indices . size ( ) ; i += <NUM_LIT> ) { if ( Indices [ i ] != - <NUM_LIT> && Indices [ i ] != WsIdx ) return SDValue ( ) ; if ( Indices [ i + <NUM_LIT> ] != - <NUM_LIT> && Indices [ i + <NUM_LIT> ] !=


<s> if ( EltIdx < <NUM_LIT> ) continue ; if ( EltIdx < <NUM_LIT> ) V2Only = false ; else V1Only = false ; } if ( TLI . getSubtarget ( ) -> hasSSSE3 ( ) ) { SmallVector < SDValue , <NUM_LIT> > pshufbMask ; bool TwoInputs = ! ( V1Only || V2Only ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> || ( TwoInputs && EltIdx >= <NUM_LIT> ) ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; continue ; } pshufbMask . push_back ( DAG . getConstant ( EltIdx , <STR_LIT> ) ) ; } if ( V2Only ) V1 = V2 ; V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( ! TwoInputs ) return V1 ; pshufbMask . clear ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; continue ; } pshufbMask . push_back ( DAG . getConstant ( EltIdx - <NUM_LIT> , <STR_LIT> ) ) ; } V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , V2 ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) ; SDValue NewV = V2Only ? V2 : V1 ; for ( int i = <NUM_LIT> ; i != <NUM_LIT>


<s> <ISA_LIT>CallFrameOptimization :: InstClassification <ISA_LIT>CallFrameOptimization :: classifyInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const <ISA_LIT>RegisterInfo & RegInfo , DenseSet < unsigned int > & UsedRegs ) { if ( MI == MBB . end ( ) ) return Exit ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Convert


<s> Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; bool IsLittleEndian = ( Endian == <STR_LIT> ) ; if ( IsLittleEndian && ( NumBytes == <NUM_LIT> ) ) { Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( Value & <NUM_LIT> ) ; Data [ Offset + <NUM_LIT> ] |= uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; } else { for ( unsigned I = <NUM_LIT> ; I != NumBytes ; I


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>V9Target ( ) ,


<s> SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Vec256 = DAG . getBitcast ( CastVT , Vec256 ) ; Vec256 = DAG . getNode ( <STR_LIT> , dl , CastVT , Result , Vec256 , Mask ) ; return DAG . getBitcast ( ResultVT


<s>
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
unsigned
SVECSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
{
auto
RegSize
=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
SVECSStackSize
+=
RegSize
;
else
CSStackSize
+=
RegSize
;
}
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
int64_t
SVEStackSize
=
alignTo
(
SVECSStackSize
+
estimateSVEStackObjectOffsets
(
MFI
)
,
<NUM_LIT>
)
;
bool
CanEliminateFrame
=
(
SavedRegs
.
count
(
)
==
<NUM_LIT>
)
&&
!
SVEStackSize
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
SVEStackSize
||
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPR
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;
int
FI
=
MFI
.
CreateStackObject
(
Size
,
Align
,
false
)
;
RS
->
addScavengingFrameIndex
(


<s> addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr = reg ; } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) ; rtx op1 = XEXP ( addr , <NUM_LIT> ) ; op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg (


<s> if ( const auto * BKey = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) return BKey -> getZExtValue ( ) ; return false ; } const StringRef Key = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( Key . equals_insensitive ( <STR_LIT> ) || Key . equals_insensitive


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> MCELFStreamer * llvm :: create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return new <ISA_LIT>ELFStreamer ( Context , MAB


<s> } break ; case TYPE_DIV : switch ( get_attr_size ( insn ) ) { case SIZE_32 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divsi ; break ; case SIZE_64 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divdi ; break ; default : gcc_unreachable ( ) ; } break ; case TYPE_FP : cost = n * rs6000_cost -> fp ; break ; case TYPE_DMUL : cost = n * rs6000_cost -> dmul ; break ; case TYPE_SDIV : cost = n * rs6000_cost -> sdiv ; break ; case TYPE_DDIV : cost = n * rs6000_cost -> ddiv ; break ; case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_MFCR : case


<s> int getGlobalRegFI ( ) const { return


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; if ( ! IsZExt ) { Op0 = emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; if ( ! Op0 ) return <NUM_LIT> ; SrcVT = RetVT ; SrcBits = SrcVT . getSizeInBits ( ) ; IsZExt = true ; } unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { Register TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 ) . addImm ( <STR_LIT> ) ; Op0 =


<s> return ( uint8x8_t ) __builtin_neon_vrshluv8qi ( ( int8x8_t )


<s> if ( VectorList . ElementKind != ElementKind ) return false ; if ( VectorList . IsSVE ) return


<s> MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ValOpIdx = <STR_LIT> ; unsigned VSrc = MI . getOperand ( ValOpIdx ) . getReg ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { MachineOperand & Operand = MI . getOperand ( i ) ; if ( Operand . isReg ( ) ) Operand . setIsKill ( false ) ; MIB . addOperand (


<s> static DecodeStatus DecodeVMOVRRS ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> case 'v' : if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ; return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] ==


<s> static DecodeStatus DecodeVLD3LN ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> )


<s> bool hasAnyFloatExt ( ) const { return hasFPUv2 ( )