<s> sh_emit_storesi ( tramp_mem , <NUM_LIT> , fnaddr ) ; } else { sh_emit_storehi ( tramp_mem , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; sh_emit_storehi ( tramp_mem , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; sh_emit_storesi ( tramp_mem , <NUM_LIT> , cxt ) ; sh_emit_storesi ( tramp_mem , <NUM_LIT> , fnaddr ) ; } if ( TARGET_HARD_SH4 ) { if ( ! TARGET_INLINE_IC_INVALIDATE || ( ! ( TARGET_SH4A || TARGET_SH4_300 ) && TARGET_USERMODE ) ) emit_library_call ( function_symbol ( NULL , <STR_LIT> , FUNCTION_ORDINARY ) . sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , tramp , SImode ) ; else emit_insn ( gen_ic_invalidate_line


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout


<s> void <ISA_LIT>CondBrTuning :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG (


<s> return reload_completed && cfun -> machine -> frame .


<s> if ( ACPV -> isPromotedGlobal ( ) ) { auto * ACPC = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) ; for ( const auto * GV : ACPC -> promotedGlobals ( ) ) { if ( ! EmittedPromotedGlobalLabels . count ( GV ) ) { MCSymbol * GVSym = getSymbol ( GV ) ; OutStreamer -> emitLabel ( GVSym ) ; EmittedPromotedGlobalLabels . insert ( GV ) ; } } return emitGlobalConstant ( DL , ACPC -> getPromotedGlobalInit ( ) ) ; } MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { MCSym = getMBBExceptionSym ( MF -> front ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( DotSym


<s> const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << Log2 ( BBI . PostAlign ) << format (


<s> rtx reg_temp ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; reg_temp = ! can_create_pseudo_p ( ) ? reg : gen_reg_rtx ( Pmode ) ; base = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg_temp ) ; offset = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; if ( CONST_INT_P ( offset ) ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else { rtx mem = force_const_mem ( Pmode , orig ) ; return machopic_legitimize_pic_address ( mem , Pmode


<s> MachineFunctionProperties getRequiredProperties ( )


<s> uint64_t MaxVal = ( ( uint64_t ( <NUM_LIT> ) << Bits ) - <NUM_LIT> ) * Scale ; return Val <= MaxVal && ( Val % Scale )


<s> static bool hasMFENCE ( const <ISA_LIT>Subtarget & Subtarget ) { return Subtarget . hasSSE2 ( ) || Subtarget


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard && ! isVarArg

) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ;


<s> assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ; int NumOp = MI . getNumExplicitOperands ( ) ; assert ( MI . getOperand ( NumOp - <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; return MI . getOperand ( NumOp - <NUM_LIT>


<s> else if ( CONST_INT_P ( y_hi ) ) insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; else insn = emit_insn ( gen_cmpsi3_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LE : case GT : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , y_lo , x_lo , scratch ) , const0_rtx ) ; rtx_insn * insn = emit_insn ( gen_rscsi3_CC_NVout_scratch ( scratch , y_hi , x_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LTU : case GEU : { if ( y_lo == const0_rtx ) { if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; return arm_gen_compare_reg ( code , x_hi , y_hi , NULL_RTX ) ; } if ( ! arm_add_operand ( y_lo , SImode ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , x_lo , y_lo , NULL_RTX ) , const0_rtx ) ; if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; if ( ! arm_not_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; rtx_insn * insn ; if ( y_hi == const0_rtx ) insn = emit_insn ( gen_cmpsi3_0_carryin_CC_Bout ( scratch , x_hi , cmp1 ) ) ; else if ( CONST_INT_P ( y_hi ) ) { y_hi = GEN_INT ( UINTVAL ( y_hi ) & <NUM_LIT> ) ; insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; } else insn = emit_insn ( gen_cmpsi3_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LEU : case GTU : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU ,


<s> if ( Subtarget -> hasFp256 ( ) ) { SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; } return SDValue ( )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None

) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ;


<s> Value * Res = <NUM_LIT> ; if ( ! Offset -> isZero ( ) ) Res = Offset ; if ( Index ) { if ( ! Scale -> isOne ( ) ) Index = Builder -> CreateMul ( Index , Scale ) ; Res = ( Res ? Builder -> CreateAdd ( Index , Res ) : Index ) ; } if ( Base ) Res = ( Res ? Builder -> CreateAdd ( Base , Res ) : Base ) ; if ( VT != <STR_LIT> ) { Type * PtrTy = EVT ( VT ) . getTypeForEVT ( * Ctx ) ->


<s> std :: map < unsigned , IntrinsicData > :: const_iterator itr = IntrWithoutChainMap . find ( IntNo ) ; if ( itr == IntrWithoutChainMap . end ( ) ) return NULL ; return & ( itr -> second


<s> if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { SMLoc Loc = getLexer ( ) . getLoc (


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF


<s> assert ( usesFunctionDescriptors ( ) && <STR_LIT> ) ; return Is<ISA_LIT>64 ? <STR_LIT>


) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode =


<s> ( * lang_hooks . types . register_builtin_type ) ( intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type )

( unsigned_intTI_type_node , <STR_LIT> ) ;


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned ShuffleKind , SelectionDAG & DAG ) { bool IsLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ShuffleKind == <NUM_LIT> ) { if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <NUM_LIT>


<s> emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask = NULL_RTX ; int hwcap_offset ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_supports_info ) ; i ++ ) if ( strcmp ( hwcap , cpu_supports_info [ i ] . hwcap ) == <NUM_LIT> ) { mask = GEN_INT ( cpu_supports_info [ i ] . mask ) ; hwcap_offset = TCB_HWCAP_OFFSET ( cpu_supports_info [ i ] . id ) ; break ; } if ( mask == NULL_RTX ) { error ( <STR_LIT> , hwcap , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx tcb_hwcap = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( hwcap_offset ) ) ) ; emit_move_insn ( tcb_hwcap , tcbmem ) ; rtx scratch1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( scratch1 , gen_rtx_AND ( SImode , tcb_hwcap , mask ) ) ) ; rtx scratch2 = gen_reg_rtx (


<s> if ( ! intr && ! excp && ! reset ) return ; if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( <NUM_LIT> ) : ( <NUM_LIT> ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ <NUM_LIT> ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = TREE_INT_CST_LOW ( id ) + <NUM_LIT> + <NUM_LIT> ; strcpy ( nds32_isr_vectors [ <NUM_LIT> ] . func_name , func_name ) ; nmi = lookup_attribute ( <STR_LIT> , func_attrs ) ; warm = lookup_attribute ( <STR_LIT> , func_attrs ) ; if ( nmi != NULL_TREE ) { tree nmi_func_list ; tree nmi_func ; nmi_func_list = TREE_VALUE ( nmi ) ; nmi_func = TREE_VALUE ( nmi_func_list ) ; strcpy ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name , IDENTIFIER_POINTER ( nmi_func ) ) ; } if ( warm != NULL_TREE ) { tree


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> return ( uint32x4_t ) __builtin_neon_vmul_nv4si ( ( int32x4_t


<s> if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base


<s> if ( ! isUInt < <NUM_LIT> > ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) ) ) return false ; if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; if ( MRI . getRegClass ( SrcReg ) == & <STR_LIT> ) { unsigned KSrcReg = SrcReg ; SrcReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , SrcReg ) . addReg ( KSrcReg ) ; SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; } SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] .


<s> case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { if ( SetCCOpcode == <STR_LIT> ) { SDValue UNORD , EQ ; UNORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; EQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , UNORD , EQ ) ; } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( ! isFP && VT . getSizeInBits ( ) == <NUM_LIT> ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT>


<s> void <ISA_LIT>AnalyzeImmediate :: ReplaceADDiuSHLWithLUi ( InstSeq & Seq ) { if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SHL ) || ( Seq [ <NUM_LIT> ] . ImmOpnd < <NUM_LIT> ) ) return ; int64_t Imm = SignExtend64 < <NUM_LIT> > ( Seq [ <NUM_LIT> ]


<s> ISARevision = <NUM_LIT> ; if ( P . has<ISA_LIT>5 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>4 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>3 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>2 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>1 ( ) ) ISALevel = <NUM_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , MBBI , MI -> getDebugLoc ( ) , get ( ThreeOperandOpcode ) ) . addOperand ( Dest ) ; MIB . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) MIB . addOperand ( MI -> getOperand ( I ) ) ; return finishConvertToThreeAddress ( MI , MIB , LV ) ; } } if ( LogicOp And = interpretAndImmediate ( Opcode ) ) { uint64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned


<s> if ( RM == Reloc :: Static ) return true ; return GV -> hasLocalLinkage ( ) || !


<s> unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI


<s> assert ( Align > <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( shiftLo >> <NUM_LIT> == <NUM_LIT> ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd , Addr


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> &&


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ; while ( UseMI -> isCopy ( ) || UseMI -> isInsertSubreg ( ) ) { Reg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; UseMI = & * MRI -> use_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ; } return


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) DestRC = <STR_LIT> ; if ( SrcRC == <STR_LIT> ) SrcRC = <STR_LIT> ; if ( DestRC != SrcRC ) { if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) return false ; if ( DestRC -> getSize ( ) != <NUM_LIT> && DestRC -> getSize ( ) != <NUM_LIT> ) return false ; } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg


<s> unsigned BestGrowth = ~ <NUM_LIT> ; MachineBasicBlock * UserBB = U . MI -> getParent ( ) ; unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( getCPELogAlign ( U . CPEMI ) ) ; if ( CloserWater && MinNoSplitDisp > U . getMaxDisp ( ) / <NUM_LIT> ) return false ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( AssemblerOptions . back ( ) . get ( ) ) ) ; getTargetStreamer ( ) . emitDirectiveSetPush (


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg


<s> unsigned sign1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( sign1 != sign2 ) return MCDisassembler :: Fail ; const unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DecodeStatus S = DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; unsigned Val = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction ( Insn ,


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return


<s> static SDValue ChangeVSETULTtoVSETULE ( SDLoc dl , SDValue Op1 , SelectionDAG & DAG ) { BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Op1 . getNode ( ) ) ; if ( ! BV ) return SDValue ( ) ; MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , dl , EVT ) ) ; } return DAG . getBuildVector ( VT ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Value , SMLoc Start ,


<s> return ! flag_pic || ( TARGET_64BIT && ix86_cmodel


<s> static PHINodeSet getPromotablePHINodes ( const Function & F ) { PHINodeSet Promotable ; for ( auto & BB : F ) for ( auto & I : BB ) if ( const PHINode * P = dyn_cast < PHINode > ( & I ) ) if ( P -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Promotable . insert ( P ) ; SmallVector < const PHINode * , <NUM_LIT> > ToRemove ; for ( const auto & P : Promotable ) { auto IsValidUser = [ ] ( const Value * V ) -> bool { return isa < ReturnInst > ( V ) || isa < CallInst > ( V ) || isa < PHINode > ( V ) || isa < DbgInfoIntrinsic > ( V ) ; } ; auto IsValidOperand = [ ] ( const Value *


<s> bool Error = MatchInstruction ( IDLoc , Operands , Out , Kind , Opcode , MapAndConstraints , ErrorInfo ) ; return


<s> if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else { Ext = getExtendTypeForNode ( N ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) ; } assert ( Ext != <STR_LIT> && Ext != <STR_LIT> ) ; Reg = narrowIfNeeded ( CurDAG , Reg ) ; Shift = CurDAG -> getTargetConstant ( getArithExtendImm ( Ext , ShiftVal ) , <STR_LIT> ) ; return isWorthFolding (


<s> rtx base , offset ; if ( CONST_INT_P ( x ) && loongarch_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( loongarch_symbolic_constant_p ( base , & type ) ) { if ( IMM12_INT ( offset ) && loongarch_symbol_insns ( type , MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ; } if ( tls_referenced_p ( x ) ) return


<s> unsigned Offset ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; Offset = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , Offset ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; End = SMLoc :: getFromPointer ( DotDispStr . data


<s> return true ; case 'H' : if ( OpNo == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo +


<s> if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitIntValue ( ImmOp32 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; if ( emitPartialAddress ( TOut , IDLoc , Sym ) ) return


<s> __o = __builtin_aarch64_ld3rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o ,


<s> return __builtin_aarch64_smaxpv2si ( a , b


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc


<s> assert ( Ty . isScalar ( ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS


<s> assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return


<s> unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType


<s> return ( ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type )


<s> void <ISA_LIT>TargetStreamer :: emitR ( unsigned Opcode , unsigned Reg0 , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MCInst TmpInst ; TmpInst . setOpcode ( Opcode


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > Flags [ ] = { { MO_GOT , <STR_LIT> } , { MO_GOT_CALL , <STR_LIT> } , { MO_GPREL , <STR_LIT> } , { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_DTPREL_HI , <STR_LIT> } , { MO_DTPREL_LO , <STR_LIT> } , { MO_GOTTPREL , <STR_LIT> } , { MO_TPREL_HI , <STR_LIT> } , { MO_TPREL_LO , <STR_LIT> } , { MO_GPOFF_HI , <STR_LIT> } , { MO_GPOFF_LO , <STR_LIT> } , { MO_GOT_DISP , <STR_LIT> } , { MO_GOT_PAGE , <STR_LIT> } , { MO_GOT_OFST , <STR_LIT> } , { MO_HIGHER , <STR_LIT> } , { MO_HIGHEST , <STR_LIT> } , { MO_GOT_HI16 , <STR_LIT> } , { MO_GOT_LO16 , <STR_LIT> } , { MO_CALL_HI16 , <STR_LIT> } , { MO_CALL_LO16 , <STR_LIT> } , { MO_JALR


<s> const SDNode * Node = N . getNode ( ) ; for ( SDNode * UI : Node -> uses ( ) ) { if ( ! isa < MemSDNode > ( * UI ) ) return false ; } if ( isa < ConstantSDNode > ( RHS ) ) { int64_t ImmOff = ( int64_t ) cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( ImmOff % Size == <NUM_LIT> && ImmOff >= <NUM_LIT> && ImmOff < ( <NUM_LIT> << Scale ) ) || isPreferredADD ( ImmOff ) || isPreferredADD ( - ImmOff ) ) return false ; SDLoc DL ( N . getNode ( ) ) ; SDValue Ops [ ] = { RHS } ; SDNode * MOVI = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; SDValue MOVIV = SDValue ( MOVI , <NUM_LIT> ) ; N = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , MOVIV ) ; } bool IsExtendedRegisterWorthFolding = isWorthFolding


<s> RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( Chain , RetTyABI , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , Callee , Args , DAG , SDLoc ( Op ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty ( ) && <STR_LIT>


<s> auto * ConstMask = dyn_cast < ConstantDataVector > ( Mask ) ; if ( ! ConstMask ) return false ; unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( Vec -> getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast (


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) Binary = <NUM_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Binary = <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd )


<s> unsigned oc = MI . getOpcode ( ) ; if ( oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } else if ( oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> ) . getReg (


<s> rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = <NUM_LIT> ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = <NUM_LIT> ; return false ; } } } } return true


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOT_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PIC_BASE_OFFSET , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_GOTPCREL_NORELAX , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_GOTTPOFF , <STR_LIT> } , { MO_INDNTPOFF , <STR_LIT> } , { MO_TPOFF , <STR_LIT> } , { MO_DTPOFF , <STR_LIT> } , { MO_NTPOFF , <STR_LIT> } , { MO_GOTNTPOFF , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_DARWIN_NONLAZY , <STR_LIT> } , { MO_DARWIN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_TLVP

, <STR_LIT> } , { MO_TLVP_PIC_BASE , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_COFFSTUB , <STR_LIT> } } ;


<s> return ( uint32x2_t ) __builtin_aarch64_urecpev2si ( ( int32x2_t


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = false ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; WeakRefDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_STORE ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; SDValue Chain = DAG . getTruncStore ( Node -> getChain ( ) , SDLoc ( Op ) , Node -> getVal ( ) , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ; if ( Node -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Chain = SDValue ( DAG . getMachineNode (

<STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Chain ) , <NUM_LIT> ) ;


<s> void \ private_data_section ( ) \ { \ if ( in_section != private_data ) \ { \ fprintf ( asm_out_file , <STR_LIT>

, \ xcoff_private_data_section_name ) ; \ in_section = private_data ; \ } \ }


<s> return MO . isImm ( ) && ( MO . getImm ( ) == <NUM_LIT> || MO . getImm ( ) == <NUM_LIT> || MO . getImm (

) == <NUM_LIT> || MO . getImm ( ) == <NUM_LIT> ) ;


<s> dsecond . one_operand_p = true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) if ( d -> perm [ i ] >= nelt ) { dsecond . perm [ i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ] = d -> perm [ i ] - nelt ; if ( d -> perm [ i ] - nelt != i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ) ident2 = false ; dsecond . perm [ i / <NUM_LIT> + ( i >= lane ? lane : lane / <NUM_LIT> ) ] = d -> perm [ i ] - nelt ; } else { dfirst . perm [ i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ] = d -> perm [ i ] ; if ( d -> perm [ i ] != i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ) ident1 = false ; dfirst . perm [ i / <NUM_LIT> + ( i >= lane ? lane : lane / <NUM_LIT> ) ] = d -> perm [ i ] ; } if ( two_insn && ! ident1 && ! ident2 ) return false ; if ( ! d -> testing_p ) { if ( ! ident1 ) dfinal . op0 = dfirst . target = gen_reg_rtx ( d -> vmode ) ; if ( ! ident2 ) dfinal . op1 = dsecond . target = gen_reg_rtx ( d -> vmode ) ; if ( d -> perm [ <NUM_LIT> ] >= nelt ) std :: swap ( dfinal . op0 , dfinal . op1 ) ; } bool ok ; rtx_insn * seq1 = NULL , * seq2 = NULL ; if ( ! ident1 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq1 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( ! ident2 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dsecond ) ; seq2 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { dfinal . perm [ i ] = i


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemArgument ( SDValue Chain , CallingConv :: ID CallConv , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , const CCValAssign & VA , MachineFrameInfo & MFI , unsigned i ) const { <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = shouldGuaranteeTCO ( CallConv , DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI . setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI ,


<s> bool EvexToVexInstPass :: CompressEvexToVexImpl ( MachineInstr & MI ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( Desc . TSFlags & <STR_LIT> ) return false ; static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex128CompressTable ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return


<s> unsigned Opc = ( DestReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; } else if ( ( SrcRC == <STR_LIT> ) && ( DestRC == <STR_LIT> ) ) { unsigned Opc = ( SrcReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; } else return false ; return true ; } if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg ) ; else if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; else if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; else if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; else return false ; return true


<s> if ( CC == CallingConv :: WebKit_JS ) return CC_<ISA_LIT>_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_GHC ; if ( CC == CallingConv :: CFGuard_Check

) return CC_<ISA_LIT>_Win64_CFGuard_Check ;


<s> return ( uint32x2_t ) __builtin_neon_vqrshrnu_nv2di ( (


<s> static bool unscaleOffset ( unsigned Opc , int64_t &


<s> EVT VT = Trunc . getValueType ( ) ; if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , false ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , true ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc .


<s> result = result * <NUM_LIT> + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * <NUM_LIT> + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = <NUM_LIT> ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * <NUM_LIT> + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result


<s> emit_insn ( gen_andqi3 ( ret , gen_lowpart ( QImode , tag ) , gen_int_mode ( and_imm , QImode ) ) ) ; } else emit_move_insn ( ret , gen_lowpart ( QImode , tag ) ) ; return


<s> unsigned Qd = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= cmode << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( cmode == <NUM_LIT> && Inst . getOpcode ( ) == <STR_LIT> ) return


<s> void <ISA_LIT>InstPrinter :: printAddrModeMemSrc ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { auto Op1 = MI -> getOperand ( OpNum


<s> continue ; } NumRLInsts += SelectRotMask64Count ( BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , ! FirstBG ) ; FirstBG = false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << ( VRI . Repl32 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << NumAndInsts << <STR_LIT> << NumRLInsts << <STR_LIT> ) ; if ( NumAndInsts > NumRLInsts ) continue ; if ( ( Use32BitInsts || MoreBG ) && NumAndInsts == NumRLInsts ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ) VRot = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; else VRot = VRI . V ; SDValue TotalVal ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( VRot , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( VRot , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcmp ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src1 , SDValue Src2 , SDValue Size , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; Chain = emitCLC ( DAG , DL , Chain , Src1 , Src2 , Bytes ) ; SDValue Glue = Chain . getValue ( <NUM_LIT>


<s> MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = std :: max ( FFI -> getMaxAlignment ( ) , calculateMaxStackAlignment ( FFI ) ) ; FFI -> setMaxAlignment (


<s> Val = CE -> getValue ( ) ; } else if ( isMem ( ) ) { if ( ! Memory . OffsetImm || Memory . OffsetRegNum ) return false ; if ( Memory . BaseRegNum != <STR_LIT> ) return false ; Val = Memory . OffsetImm -> getValue


<s> SDLoc DL ( Op ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; MVT ExtVT


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand

:: MOLoad | MachineMemOperand :: MOInvariant , Size , <NUM_LIT> ) ;


<s> setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT ,


<s> int64_t Size ; if ( parseImmExpr ( Size ) ) return


( __v16sf ) _mm512_undefined_ps ( ) , - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> auto ValAndVReg = getConstantVRegValWithLookThrough ( PtrAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ValAndVReg ) { unsigned Scale = Log2_32 ( SizeInBytes ) ; int64_t ImmOff = ValAndVReg -> Value ; if ( ImmOff % SizeInBytes == <NUM_LIT> && ImmOff >= <NUM_LIT> && ImmOff < ( <NUM_LIT> << Scale ) ) return None ; auto isPreferredADD = [ ] ( int64_t ImmOff ) { if ( ( ImmOff & <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ImmOff & <NUM_LIT> ) !=


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI ,


<s> if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > <NUM_LIT> : TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ) { tree t = fold_build_pointer_plus_hwi ( valist , <NUM_LIT> * UNITS_PER_WORD - <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> * UNITS_PER_WORD ) ) ; gimplify_assign ( unshare_expr ( valist ) ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerCCCArguments ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; if ( isVarArg ) llvm_report_error ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : cerr << <STR_LIT> << LocVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) ) ; SDValue FIN = DAG . getFrameIndex ( FI ,


<s> } Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs = <STR_LIT> ( AM3Opc ) ) { Binary |= ( ImmOffs >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ImmOffs & <NUM_LIT> ) ; } emitWordLE ( Binary


<s> auto TestI = BuildMI ( MBB , Pos , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addImm ( - <NUM_LIT> ) ; ( void ) TestI ; DEBUG ( dbgs ( ) << <STR_LIT> ; TestI -> dump ( ) ) ; ++


<s> for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale += Scale ) { unsigned SrcEltBits = EltSizeInBits * Scale ; if ( SrcEltBits < <NUM_LIT> && ! Subtarget . hasBWI ( ) ) continue ; unsigned NumHalfSrcElts = NumElts / Scale ; unsigned NumSrcElts = <NUM_LIT> * NumHalfSrcElts ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , NumSrcElts , <NUM_LIT> , Scale ) || isUndefInRange ( Mask , NumHalfSrcElts , NumHalfSrcElts ) ) continue ; unsigned UpperElts = NumElts - NumSrcElts ; if ( UpperElts > <NUM_LIT> && ! Zeroable . extractBits ( UpperElts , NumSrcElts ) . isAllOnesValue ( ) ) continue ; bool UndefUppers = UpperElts > <NUM_LIT> && isUndefInRange ( Mask , NumSrcElts , UpperElts ) ; MVT ConcatVT = <STR_LIT> ( VT . getScalarType ( ) , NumElts * <NUM_LIT> ) ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , ConcatVT


<s> void setSpillsVRSAVE ( ) { SpillsVRSAVE =


<s> gcc_assert ( POINTER_BOUNDS_MODE_P ( GET_MODE ( bounds ) ) ) ; if ( ! register_operand ( bounds , BNDmode ) ) bounds = copy_to_mode_reg ( BNDmode , bounds ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr


<s> unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) ; return


<s> return TRI -> getEncodingValue ( RegNo


<s> NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask


<s> const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ; return


<s> auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace (


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>Target ( )


<s> return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | ( <NUM_LIT>


<s> const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; callsEHReturn = ( MMI ? MMI -> callsEHReturn ( ) : false ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned GhcCalleeSavedRegs [ ] = { <NUM_LIT> } ; static const unsigned CalleeSavedRegs32Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const unsigned CalleeSavedRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const unsigned CalleeSavedRegsWin64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB

, MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ;


<s> size = int_size_in_bytes ( type ) ; if ( ( ! type || VECTOR_INTEGER_TYPE_P ( type ) || INTEGRAL_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( SCALAR_INT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) && ! COMPLEX_MODE_P ( mode ) && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || size == <NUM_LIT> ) ) return false ; return size != <NUM_LIT> && size != <NUM_LIT> && size != <NUM_LIT> && size != <NUM_LIT> ; } else { int needed_intregs , needed_sseregs ; return examine_argument ( mode , type , <NUM_LIT> , & needed_intregs , & needed_sseregs ) ; } } else { size = int_size_in_bytes ( type ) ; if ( TARGET_IAMCU ) return VECTOR_MODE_P ( mode ) || size < <NUM_LIT> || size > <NUM_LIT> ; if ( mode ==


<s> static rtx mips_get_tp ( void ) { return mips_expand_thread_pointer ( gen_reg_rtx ( Pmode


<s> return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> && <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scale = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned IndexReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> ) ; assert ( Scale == <NUM_LIT> ) ; assert ( BaseReg == <STR_LIT> ) ; assert ( IndexReg == <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } else { auto NextMBBI = MBBI ; ++ NextMBBI ; BuildMI ( MBB , NextMBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIBundleBuilder ( MBB , MBBI , NextMBBI ) ; finalizeBundle ( MBB , MBBI . getInstrIterator ( ) ) ; return true ; } } if ( Opc == <STR_LIT> && MatchesSPAdj ( MI )


<s> case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : return combineVZextMovl ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineVZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


( __v8hi ) _mm_setzero_hi ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override { return


<s> if ( CONST_INT_P ( y ) ) y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } return aarch64_gen_compare_reg ( code , x


<s> bool runOnMachineFunction ( MachineFunction & F ) override { <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) ; STI = static_cast < const <ISA_LIT>Subtarget * > ( & F . getSubtarget ( ) ) ; bool Result = AsmPrinter ::


<s> unsigned CPEOffset = UserBBI . postOffset ( CPEAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UserMBB ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . add ( predOps ( <STR_LIT> ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBUtils -> computeBlockSize ( UserMBB ) ; BBUtils -> adjustBBOffsetsAfter ( UserMBB ) ; return ; } } const Align Align = MF -> getAlignment ( ) ; assert ( Align >= CPEAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( Align , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << Log2 ( Align ) << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; MachineBasicBlock :: iterator I = UserMI ; ++ I ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) , PredReg = <NUM_LIT> ; I -> getOpcode ( ) != <STR_LIT> && getITInstrPredicate ( * I , PredReg ) != <STR_LIT> ; Offset += TII -> getInstSizeInBytes ( * I ) , I


<s> ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ; if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ; if ( isSigned ) { if ( Hi0 -> getSExtValue ( ) == Lo0 -> getSExtValue ( ) >> <NUM_LIT> && Hi1 -> getSExtValue ( ) == Lo1 -> getSExtValue ( ) >> <NUM_LIT> ) return true ; } else { if ( Hi0 -> isNullValue ( ) && Hi1 -> isNullValue ( ) ) return true ; } return false ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getVectorElementType ( ) .


<s> aarch64_def_or_undef ( TARGET_FLOAT , <STR_LIT> , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } else cpp_undef ( pfile , <STR_LIT> ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_DOTPROD , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; cpp_undef ( pfile , <STR_LIT> ) ; cpp_undef ( pfile , <STR_LIT> ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( <STR_LIT> ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( <STR_LIT> ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( TARGET_SVE ) { int


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Src -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; if ( DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && Subtarget -> useSVEForFixedLengthVectors ( ) && VT . isFixedLengthVector ( ) && VT . getFixedSizeInBits ( ) >= Subtarget -> getMinSVEVectorSizeInBits ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue ExtLoad = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , N0 . getValueType ( ) , LN0 -> getMemOperand ( ) ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( N0 . getNode ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , ExtLoad , DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( N0 ) ) ) , ExtLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N


<s> if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg


<s> static bool isCSRestore ( MachineInstr * MI , const unsigned * CSRegs ) { if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) return true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i32scatter_ps ( void *


<s> return ( __m128i ) __builtin_ia32_pmovqb128_mask ( ( __v2di ) __A ,


<s> printOperand ( MI , Op + <STR_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; O << * DispSpec . getExpr ( ) ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op + <STR_LIT> , O ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <STR_LIT> , O ) ; unsigned ScaleVal = MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT>


<s> void <ISA_LIT>TargetAsmStreamer :: emitUnwindRaw ( int64_t Offset , const SmallVectorImpl < uint8_t > & Opcodes ) { OS << <STR_LIT> << Offset ; for ( SmallVectorImpl < uint8_t > :: const_iterator OCI = Opcodes . begin ( ) , OCE = Opcodes . end ( ) ; OCI != OCE ; ++ OCI ) OS << <STR_LIT> << utohexstr


<s> inline SDValue getSmallIPtrImm ( unsigned


<s> return __builtin_ia32_comilt ( ( __v4sf ) __A , (


<s> machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; val = force_reg ( GET_MODE ( val ) , val ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) { rtx insn = NULL_RTX ; rtx elt_rtx = GEN_INT ( elt ) ; if ( mode == V2DFmode ) insn = gen_vsx_set_v2df ( target , target , val , elt_rtx ) ; else if ( mode == V2DImode ) insn = gen_vsx_set_v2di ( target , target , val , elt_rtx ) ; else if ( TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_UPPER_REGS_DI && TARGET_POWERPC64 ) { if ( mode == V4SImode ) insn = gen_vsx_set_v4si_p9 ( target , target , val , elt_rtx ) ; else if ( mode == V8HImode ) insn = gen_vsx_set_v8hi_p9 ( target , target , val , elt_rtx ) ; else if ( mode == V16QImode ) insn = gen_vsx_set_v16qi_p9 ( target , target , val , elt_rtx ) ; } if ( insn ) { emit_insn ( insn ) ; return ; } } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == <NUM_LIT> ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> )


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( )


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq (


<s> } else if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg ) ; return


<s> MachineOperand MO = MI . getOperand ( OpNo ) ; if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI ,


<s> static bool pru_valid_const_ubyte_offset ( machine_mode mode , HOST_WIDE_INT offset ) { bool valid = UBYTE_INT ( offset ) ; if ( valid && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SImode ) ) valid = UBYTE_INT ( offset

+ GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ;


<s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsShift = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT ) ) return SDValue ( ) ; break ; } SmallVector < SDValue , <NUM_LIT> > LHSElts , RHSElts ; for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; if ( RHS . getValueSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { if ( ! IsShift ) return SDValue ( ) ; RHS = DAG . getZExtOrTrunc ( RHS , DL , VT . getScalarType ( ) ) ; } LHSElts . push_back ( LHS ) ; RHSElts . push_back ( RHS ) ; } if ( IsShift && any_of ( RHSElts , [ & ] ( SDValue V ) { return RHSElts [ <NUM_LIT> ] != V ; } ) ) return SDValue ( ) ; SDValue LHS = DAG . getBuildVector ( VT , DL , LHSElts ) ; SDValue RHS = DAG . getBuildVector ( VT , DL , RHSElts ) ; SDValue Res = DAG . getNode ( Opcode , DL , VT , LHS , RHS ) ; if ( ! IsShift )


<s> void addCCRAsmRegOperands ( MCInst & Inst , unsigned


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { assert ( ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; MVT NewVT = <STR_LIT> ( EltVT , <NUM_LIT> / VT . getScalarSizeInBits ( ) ) ; SDValue Vec512 = DAG . getNode ( <STR_LIT> , dl , NewVT , DAG . getUNDEF ( NewVT ) , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Vec512 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( <NUM_LIT> < NumElems ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op . getOperand ( <NUM_LIT> ) , dl ) ; MVT OutVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; Lo = DAG . getNode ( Op . getOpcode ( ) , dl , OutVT , Lo ) ; Hi = DAG . getNode ( Op . getOpcode ( ) , dl , OutVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; } MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , VMask , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; return SDValue ( Res , <NUM_LIT>


<s> oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( label2 ) ; if ( ! ( use_acquire || use_release ) )


<s> } maxshift = innersize * <NUM_LIT> ; if ( isleftshift ) { if ( last_elt >= maxshift ) return <NUM_LIT> ; } else { if ( last_elt == <NUM_LIT> || last_elt > maxshift ) return <NUM_LIT> ; } if ( elementwidth ) * elementwidth = innersize * <NUM_LIT> ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , <NUM_LIT> ) ; return <NUM_LIT>


<s> RHSC >>= <NUM_LIT> ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } } } return false


<s> SDValue Op0Op1 = Op0 -> getOperand ( <NUM_LIT> ) ; SDValue Op1Op0 = Op1 -> getOperand ( <NUM_LIT> ) ; SDValue Op1Op1 = Op1 -> getOperand ( <NUM_LIT> ) ; bool IsLittleEndian = ! Subtarget -> isLittle ( ) ; SDValue IfSet , IfClr , Cond ; bool IsConstantMask = false ; APInt Mask , InvMask ; if ( isVSplat ( Op0Op0 , Mask , IsLittleEndian ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; if ( isVSplat ( Op1Op0 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op1 ; else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) && isVSplat ( Op0Op1 , Mask , IsLittleEndian ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; if ( isVSplat ( Op1Op0 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op1 ; else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) ) { if ( isBitwiseInverse ( Op0Op0 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op0Op0 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr =


<s> vrsqrtsq_f32 ( float32x4_t a , float32x4_t b ) { float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> static hashval_t hash ( const char * s


<s> struct mips16e_save_restore_info info ; unsigned int i , end ; char * s ; if ( ! mips16e_save_restore_pattern_p ( pattern , adjust , & info ) ) gcc_unreachable ( ) ; s = strcpy ( buffer , adjust > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; s += strlen ( s ) ; if ( info . nargs > <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ GP_ARG_FIRST ] , reg_names [ GP_ARG_FIRST + info . nargs - <NUM_LIT> ] ) ; else if ( info . nargs == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ GP_ARG_FIRST ] ) ; s += sprintf ( s , <STR_LIT> , ( int ) info . size ) ; if ( BITSET_P ( info . mask , <NUM_LIT> ) ) s += sprintf ( s , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; if ( BITSET_P ( info . mask , <NUM_LIT> ) ) s += sprintf ( s , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; end = ARRAY_SIZE ( mips16e_s2_s8_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_s2_s8_regs , end ) ; if ( i < end ) s = mips16e_add_register_range ( s , mips16e_s2_s8_regs [ end - <NUM_LIT> ] , mips16e_s2_s8_regs [ i ] ) ; end = ARRAY_SIZE ( mips16e_a0_a3_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_a0_a3_regs ,


<s> return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned RegTarget ; if ( Is64Bit ) { RegTarget = ( HideSandboxBase ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } else { RegTarget = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Is64Bit && ! FlagUseZeroBasedSandbox ? <STR_LIT> : <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * PtrAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Root . getReg ( ) , MRI ) ; if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineOperand & LHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineOperand & RHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineInstr * OffsetInst = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; auto ExtendedShl = selectExtendedSHL ( Root , LHS , OffsetInst ->

getOperand ( <NUM_LIT> ) , SizeInBytes , true ) ;


<s> if ( PredMBBInfo -> Modified ) fixupModifiedCond ( PredMBB ) ; CC = PredMBBInfo -> BranchCode ; if ( ! ( CC == <STR_LIT> && BranchPath . size ( ) == <NUM_LIT> ) ) replaceBrDest ( PredMBB , & MBB , MBBInfo -> FBB ) ; MachineBasicBlock * RootMBB = BranchPath . back ( ) ; TargetMBBInfo * RootMBBInfo = getMBBInfo ( RootMBB ) ; assert ( RootMBBInfo && <STR_LIT> ) ; if ( RootMBBInfo -> Modified ) fixupModifiedCond ( RootMBB ) ; CC = RootMBBInfo -> BranchCode ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator UncondBrI = findUncondBrI ( RootMBB ) ; <STR_LIT> NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = <STR_LIT> ; break ; case <STR_LIT> : NewCC = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( RootMBBInfo -> FBB ) . addImm ( NewCC ) ; BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII -> get (


<s> O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O << '\n' ; return ; } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: CommonLinkage : O << <STR_LIT> << name << '\n' << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : cerr << <STR_LIT> ; abort ( ) ; } EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O <<


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( Subtarget . is64Bit (


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsVariable ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsVariable ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsVariable ?


<s> if ( <ISA_LIT>InstrInfo :: isVRRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; else if ( <ISA_LIT>InstrInfo :: isVFRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; } const char * RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; if ( ! Subtarget -> isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand


<s> IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case


<s> if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! StVal . hasOneUse ( ) ) return SDValue ( ) ; if ( DAG . isBaseWithConstantOffset ( St . getBasePtr ( ) ) ) { int64_t Offset = St . getBasePtr ( ) -> getConstantOperandVal ( <NUM_LIT> ) ; if ( Offset < - <NUM_LIT> || Offset > <NUM_LIT> ) return SDValue ( ) ; } for ( int I = <NUM_LIT> ; I <


<s> Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo (


<s> RK = RegKind :: SVEPredicateVector ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ( Kind == k_Register && Reg . Kind == RK ) && <ISA_LIT>MCRegisterClasses [ Class ] . contains (


<s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . FeatureBits =


<s> Relocator :: Address S = pReloc . symValue ( ) ; if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; Relocator :: DWord X = helper_get_page_address ( S + A ) - helper_get_page_address ( P ) ; pReloc . target ( ) = helper_reencode_adr_imm ( pReloc . target ( ) ,


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] =


<s> int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = - <NUM_LIT> ; continue ; } APInt Index = cast < ConstantInt > ( COp ) -> getValue ( ) ; Index = Index . zextOrTrunc ( <NUM_LIT> ) . getLoBits ( <NUM_LIT> ) ; if ( IsPD ) Index . lshrInPlace ( <NUM_LIT> ) ; Index += APInt ( <NUM_LIT> , ( I / NumLaneElts ) * NumLaneElts ) ; Indexes [ I ] = Index . getZExtValue ( ) ; } auto V1 = II . getArgOperand (


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = <NUM_LIT>


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return const_cast < <ISA_LIT>TargetLowering * > (


<s> unsigned FullSizeBytes ; if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FullSizeBytes && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes - <NUM_LIT> - i ) ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> (


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT>


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_cvtusepi64_storeu_epi16 ( void *


<s> HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ; UseNaClTrap =


<s> bool <ISA_LIT>AsmParser :: reportParseError ( SMLoc Loc , const Twine & ErrorMsg ) { return Error ( Loc


<s> bool isSplitCSR ( ) const { return IsSplitCSR


<s> printNamedImmOperand ( SomeNamedImmMapper ( ) , MI , OpNum ,


<s> if ( unsigned Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; return false ; } unsigned Off = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Off , LocVT , LocInfo ) ) ; return false ; } unsigned UnallocIntReg = State . getFirstUnallocated ( IntRegs , IntRegsSize ) ; if ( ValVT == <STR_LIT> ) { if ( IntRegs [ UnallocIntReg ] == ( unsigned ( <STR_LIT> ) ) ) { State . AllocateReg ( IntRegs , IntRegsSize ) ; UnallocIntReg ++ ; } if ( IntRegs [ UnallocIntReg ] == ( unsigned ( <STR_LIT> ) ) || IntRegs [ UnallocIntReg ] == ( unsigned ( <STR_LIT> ) ) ) { unsigned Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT