<s> unsigned EltNo ; if ( MI -> getOpcode ( ) == <STR_LIT> ) EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; else EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; else MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] .


<s> static bool mips_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return ! TARGET_64BIT || inprec <= <NUM_LIT> || outprec >


<s> const uint16_t * ArgRegs = CC . intArgRegs ( ) ; const CCState & CCInfo = CC . getCCInfo ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs , NumRegs ) ; unsigned RegSize = CC . regSize ( ) ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex (


<s> if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT ,


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , StoreAddrReg , StoreAddr ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( StoreAddrReg


<s> else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! loongarch_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; loongarch_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr


<s> SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( Index * EVT . getStoreSize ( ) , dl , Addr . getSimpleValueType ( ) ) ) ; SDValue NewLoad = DAG . getLoad ( EVT , dl , Load -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Load -> getMemOperand ( ) , <NUM_LIT> , EVT . getStoreSize ( ) ) ) ; return


<s> if ( is_sse ) { if ( TARGET_AVX ) { strcpy ( buf , ssep ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , ssep + <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } return buf ; } strcpy ( buf , p ) ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case MULT : case PLUS : if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; } if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; case MINUS : case DIV : if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT>


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> static DecodeStatus DecodeMVE_MEM_1_pre ( MCInst & Inst , unsigned Val , uint64_t Address , const


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_X ; return TargetLowering :: getInlineAsmMemConstraint (


<s> return std :: max ( Log2 ( std :: max ( PostAlign , Align )


<s> SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , NewSP ) ; if ( StoreBackchain ) Chain = DAG . getStore ( Chain , DL ,

Backchain , NewSP , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : Cond = Cond . getNode ( ) -> getOperand ( <NUM_LIT> ) ; addTest = false ; break ; } } } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; addTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; SDValue User = SDValue ( * Op . getNode ( ) -> use_begin ( ) , <NUM_LIT> ) ; if ( User . getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User . getOperand ( <NUM_LIT> ) ; SDValue NewBR = DAG . UpdateNodeOperands ( User , User . getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> (


<s> getTargetStreamer ( ) . EmitARM64WinCFIEpilogStart ( ) ; return


<s> if ( ! IsSigned ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned


<s> if ( SVEVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; return ( std :: max ( SVEVectorBitsMin , SVEVectorBitsMax )


<s> if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } MachineInstrBuilder MIBuilder = BuildMI ( Block , MBIter , dl , TII -> get ( <STR_LIT> ) ) ; MachineBasicBlock :: iterator VPSTInsertPos = MIBuilder . getInstr ( ) ; int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; do { ++ MBIter ; NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; } while ( NextPred != <STR_LIT> && NextPred == Pred && ++ VPTInstCnt < <NUM_LIT> ) ; switch ( VPTInstCnt ) { case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: T ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TT ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TTT ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TTTT ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstr * LastMI = & * MBIter ; finalizeBundle ( Block , VPSTInsertPos . getInstrIterator ( ) , ++ LastMI -> getIterator (


<s> for ( auto SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( (

* SI ) -> isLiveIn ( <STR_LIT> ) ) return true ;


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> adjustsStack ( ) ) return true ; return MFI -> hasVarSizedObjects ( ) || MFI ->


<s> for ( i = <NUM_LIT> ; i < n ; ++ i ) current_frame_info . gr_used_mask |=


<s> rtx_insn * insns ; rtx orig_op0 = op0 ; HOST_WIDE_INT addend_lo , addend_hi ; switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : start_sequence ( ) ; tga_op1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_load_dtpmod ( tga_op1 , op1 ) ) ; tga_op2 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_load_dtprel ( tga_op2 , op1 ) ) ; tga_ret = emit_library_call_value ( gen_tls_get_addr ( ) , NULL_RTX , LCT_CONST , Pmode , tga_op1 , Pmode , tga_op2 , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; if ( GET_MODE ( op0 ) != Pmode ) op0 = tga_ret ; emit_libcall_block ( insns , op0 , tga_ret , op1 ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : start_sequence ( ) ; tga_op1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_load_dtpmod ( tga_op1 , op1 ) ) ; tga_op2 = const0_rtx ; tga_ret = emit_library_call_value ( gen_tls_get_addr ( ) , NULL_RTX , LCT_CONST , Pmode , tga_op1 , Pmode , tga_op2 , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; tga_eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LD_BASE ) ; tmp = gen_reg_rtx (


<s> if ( Imm & ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) return Fail ; if ( Imm & ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) ) Imm |= ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm


<s> if ( ParseRes != MatchOperand_Success ) { getLexer ( ) . UnLex ( LCurly ) ; return ParseRes ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned PrevReg = FirstReg ; unsigned Count = <NUM_LIT> ; SmallSet < unsigned , <NUM_LIT> > DRegs ; <ISA_LIT>Operand :: ComputeRegsForAlias ( FirstReg , DRegs , ElementWidth ) ; SmallSet < unsigned , <NUM_LIT> > SeenRegs ; SeenRegs . insert ( FirstReg ) ; while ( parseOptionalToken ( AsmToken :: Comma ) ) { TileLoc = getLoc ( ) ; unsigned Reg , NextElementWidth ; ParseRes = ParseMatrixTile ( Reg , NextElementWidth ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( ElementWidth != NextElementWidth ) { Error ( TileLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( Reg ) <= ( RI -> getEncodingValue ( PrevReg ) ) ) Warning ( TileLoc , <STR_LIT> ) ; if ( SeenRegs . contains ( Reg ) ) Warning ( TileLoc , <STR_LIT> ) ; else { SeenRegs . insert ( Reg ) ; <ISA_LIT>Operand :: ComputeRegsForAlias ( Reg , DRegs , ElementWidth ) ; } PrevReg = Reg ; ++ Count ; } if ( parseToken ( AsmToken :: RCurly , <STR_LIT> ) ) return


<s> __v4si result ; result = vec_cts ( ( __v4sf ) __A , <NUM_LIT> ) ; return ( __m128i


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int BackChainIdx = FI -> getFramePointerSaveIndex ( ) ; if ( ! BackChainIdx ) { BackChainIdx = MFI -> CreateFixedObject ( <NUM_LIT> , - <STR_LIT> , false ) ; FI -> setFramePointerSaveIndex ( BackChainIdx ) ; } SDValue BackChain = DAG . getFrameIndex (


<s> Parser . EatToEndOfStatement ( ) ; return Error ( L , <STR_LIT> ) ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) ) ; Parser . Lex (


<s> NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; } NumMIs += Bytes / Chunk ; if ( ( Bytes % Chunk ) != <NUM_LIT> ) NumMIs ++ ; if ( ExtraOpc )


<s> return isUImm < <NUM_LIT> , <NUM_LIT> > (


<s> raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I )


<s> if ( VOID_TYPE_P ( arg_type ) ) continue ; function_arg_info arg ( arg_type , true ) ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg ) ; arg_rtx = arm_function_arg ( args_so_far , arg ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx )

, & padding_bits_to_clear [ <NUM_LIT> ] ) ;


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ; } else


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; addPass ( createMVELaneInterleavingPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) )

addPass ( createCFGuardCheckPass ( ) ) ;


<s> BasicBlock * Latch = L -> getLoopLatch ( ) ; for ( Instruction & I : reverse ( * Latch ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , R ) ) continue ; if ( ! CreateParallelPairs ( R ) ) continue ; InsertParallelMACs ( R ) ; Changed = true ; AllAdds . insert ( R . getAdds ( ) . begin ( ) , R . getAdds ( ) . end ( ) ) ; } return Changed


<s> HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU

!= <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> if ( ! TARGET_64BIT ) { attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ; if ( attr ) return ( TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) == <NUM_LIT> ) ; if ( ix86_function_type_abi ( fntype ) == MS_ABI ) return true ; } return KEEP_AGGREGATE_RETURN_POINTER != <NUM_LIT>


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } mcInst . setOpcode ( NewOpc ) ; } } else if ( type == TYPE_IMM5 ) { if ( immediate >= <NUM_LIT> ) { unsigned NewOpc ; switch ( mcInst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } mcInst . setOpcode ( NewOpc ) ; } } switch ( type ) { case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM256 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM512 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_REL8 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case


<s> for ( auto & M : R . MACCandidates ) M -> Root -> dump ( ) ; dbgs ( ) << <STR_LIT> ; ) ; } Instructions Reads , Writes ; AliasCandidates ( Header , Reads , Writes ) ; for ( auto & R : Reductions ) { if ( AreAliased ( AA , Reads , Writes , R . MACCandidates ) ) return false ; PMACPairList PMACPairs = CreateParallelMACPairs ( R . MACCandidates


<s> extract_hi = gen_vec_extract_hi_v32hf ; extract_lo = gen_vec_extract_lo_v32hf ; } else { half_mode = V32QImode ; extract_hi = gen_vec_extract_hi_v64qi ; extract_lo = gen_vec_extract_lo_v64qi ; } vhi = gen_reg_rtx ( half_mode ) ; vlo = gen_reg_rtx ( half_mode ) ; idx_hi = gen_reg_rtx ( GET_MODE ( idx ) ) ; emit_insn ( extract_hi ( vhi , target ) ) ; emit_insn ( extract_lo ( vlo , target ) ) ; vec [ <NUM_LIT> ] = idx_hi ; vec [ <NUM_LIT> ] = idx ; vec [ <NUM_LIT> ] = GEN_INT ( n_elts / <NUM_LIT> ) ; ix86_expand_binary_operator ( MINUS , GET_MODE ( idx ) , vec ) ; ix86_expand_vector_set_var ( vhi , val , idx_hi ) ; ix86_expand_vector_set_var ( vlo , val , idx ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , vlo , vhi ) ) ) ; return ; } if ( FLOAT_MODE_P ( GET_MODE_INNER ( mode ) ) ) { switch ( mode ) { case E_V2DFmode : cmp_mode = V2DImode ; break ; case E_V4DFmode : cmp_mode = V4DImode ; break ; case E_V8DFmode : cmp_mode = V8DImode ; break ; case E_V2SFmode : cmp_mode = V2SImode ; break ; case E_V4SFmode : cmp_mode = V4SImode ; break ; case E_V8SFmode : cmp_mode = V8SImode ; break ; case E_V16SFmode


<s> static bool BBIsJumpedOver ( MachineBasicBlock * MBB ) { if ( MBB -> pred_size ( ) != <NUM_LIT> || MBB -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * Succ = * MBB -> succ_begin ( ) ; MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; MachineInstr * PredMI = & Pred -> back ( ) ; if ( PredMI -> getOpcode ( ) == <STR_LIT> || PredMI -> getOpcode ( ) == <STR_LIT> ) return PredMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) == Succ ; return false


<s> if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VorrVT ; SDValue Val = isVMOVModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VorrVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VorrVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vorr = DAG . getNode ( <STR_LIT> , dl , VorrVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter


<s> HOST_WIDE_INT pa_compute_frame_size ( poly_int64 size , int * fregs_live ) { int freg_saved = <NUM_LIT> ; int i , j ; size = ( size + UNITS_PER_WORD - <NUM_LIT> ) & ~ ( UNITS_PER_WORD - <NUM_LIT> ) ; if ( size || frame_pointer_needed ) size += pa_starting_frame_offset ( ) ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; ++ i ) continue ; size += i * UNITS_PER_WORD ; } for ( i = <NUM_LIT> , j = frame_pointer_needed ? <NUM_LIT> : <NUM_LIT> ; i >= j ; i -- ) if ( df_regs_ever_live_p ( i ) ) size += UNITS_PER_WORD ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { freg_saved = <NUM_LIT> ; size += <NUM_LIT> ; } if ( freg_saved


<s> return ( float16x4_t ) __builtin_neon_vcvtuv4hi (


<s> case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( Subtarget -> hasLazyResolverStub ( GV ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV


<s> unsigned NumElems = RegVT . getVectorNumElements ( ) ; unsigned MemSz = MemVT . getSizeInBits ( ) ; assert ( RegSz > MemSz && <STR_LIT> ) ; if ( Ext == <STR_LIT> && RegSz == <NUM_LIT> && ! Subtarget . hasInt256 ( ) ) { SDValue Load ; if ( MemSz == <NUM_LIT> ) { assert ( TLI . isTypeLegal ( MemVT ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; Load = DAG . getLoad ( MemVT , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; } else { assert ( MemSz < <NUM_LIT> && <STR_LIT> ) ; EVT HalfEltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , RegVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; EVT HalfVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , HalfEltVT , NumElems ) ; Load = DAG . getExtLoad ( Ext , dl , HalfVecVT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; } assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getSExtOrTrunc ( Load , dl , RegVT ) ; } assert ( isPowerOf2_32 ( RegSz * MemSz * NumElems ) && <STR_LIT> ) ; MVT SclrLoadTy = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && ( ( MemSz % Tp . getSizeInBits ( ) ) == <NUM_LIT> ) ) { SclrLoadTy = Tp ; } } if ( TLI . isTypeLegal ( <STR_LIT> ) && SclrLoadTy . getSizeInBits ( ) < <NUM_LIT> && ( <NUM_LIT> <= MemSz ) ) SclrLoadTy = <STR_LIT> ; unsigned NumLoads = MemSz / SclrLoadTy . getSizeInBits ( ) ; assert ( ( Ext != <STR_LIT> || NumLoads == <NUM_LIT> ) && <STR_LIT> ) ; unsigned loadRegZize =


<s> } u ; u . v = a ; return u . i [ pos


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; resetUnwindDirectiveParserState ( ) ; getParser ( ) . getStreamer ( )


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) { SDValue BAHi = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALo = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT>


<s> switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : return true ; case MEMMODEL_RELAXED : return false


<s> Type * MemoryTy = InputTy ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( TruncInst * Trunc = dyn_cast < TruncInst > ( Input ) ) { Value * PreTrunc = Trunc -> getOperand ( <NUM_LIT> ) ; Type * PreTruncTy = PreTrunc -> getType ( ) ; if ( PreTruncTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { Input = PreTrunc ; InputTy = PreTruncTy ; } } if ( InputTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , InputTy , Ptr , Builder ) ; if ( ! BasePtr


<s> LLVM_DEBUG ( NewLoad -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) StInst = LoadInst ; MachineInstr * NewStore = BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StoreDisp ) . addReg ( <STR_LIT> ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; if ( StoreBase . isReg ( ) ) getBaseOperand


<s> case SFmode : return ( gen_aarch64_frecpssf ) ; case V2SFmode : return ( gen_aarch64_frecpsv2sf ) ; case V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case DFmode : return ( gen_aarch64_frecpsdf ) ; case V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable


<s> SmallVector < unsigned , <NUM_LIT> > A15SDOptimizer :: getReadDPRs ( MachineInstr * MI ) { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isKill ( ) ) return SmallVector < unsigned , <NUM_LIT> > ( ) ; SmallVector < unsigned ,


<s> OS << <STR_LIT> << RegIdx . Index << <STR_LIT> << RegIdx . Kind << <STR_LIT> << StringRef ( RegIdx . Tok . Data , RegIdx . Tok . Length ) << <STR_LIT> ; break ; case k_Token : OS << getToken ( ) ; break ; case


<s> if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; subregs = <NUM_LIT> ; } if ( subregs ) address = gen_reg_rtx ( Pmode ) ; else address = reg ; if ( GET_CODE ( orig ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( orig ) ) { rtx_tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , orig ) , ( gotrel_p ? UNSPEC_PIC_SYMBOL_GOT : UNSPEC_PIC_SYMBOL_PLT ) ) ; optimize_p = gotrel_p ; if ( flag_pic != <NUM_LIT> ) { emit_move_insn ( address , rtx_tmp ) ; rtx_tmp = gen_rtx_MULT ( Pmode , address , GEN_INT ( <NUM_LIT> ) ) ; } pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_reg , rtx_tmp ) ) ; } else { if ( flag_pic == <NUM_LIT> && ! gotrel_p ) { pic_ref = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , orig ) , UNSPEC_PIC_SYMBOL_BSR ) ; return pic_ref ; } else if ( flag_pic == <NUM_LIT> && ( GET_CODE ( orig ) == SYMBOL_REF ) && SYMBOL_REF_FUNCTION_P ( orig ) ) { pic_ref = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , orig ) , UNSPEC_PIC_SYMBOL_GRS ) ; return pic_ref ; } else { rtx_tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , orig ) , UNSPEC_PIC_SYMBOL_GOTOFF ) ; emit_move_insn ( address , rtx_tmp ) ; pic_ref = gen_rtx_PLUS ( Pmode , address , pic_reg ) ; optimize_p = true ; } } insn = emit_move_insn ( reg , pic_ref


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO .


<s> static DecodeStatus DecodeUImmWithOffsetAndScale ( MCInst & Inst , unsigned Value , uint64_t Address , const MCDisassembler * Decoder ) { Value &= ( ( <NUM_LIT> << Bits ) -


<s> rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || !


<s> bool nds32_expand_movmemsi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { if ( nds32_expand_movmemsi_unroll ( dstmem , srcmem , total_bytes , alignment ) ) return true ; if ( ! optimize_size && optimize > <NUM_LIT> ) return nds32_expand_movmemsi_loop ( dstmem , srcmem ,


<s> bool IsRegLoc = VA . isRegLoc ( ) ; unsigned Offset = <NUM_LIT> ; unsigned LocMemOffset = <NUM_LIT> ; unsigned MemCpySize = ByValSize ; if ( ! IsRegLoc ) LocMemOffset = VA . getLocMemOffset ( ) ; else { const uint16_t * Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; const uint16_t * RegEnd = <ISA_LIT>64IntRegs + <NUM_LIT> ; for ( ; ( Reg != RegEnd ) && ( ByValSize >= Offset + <NUM_LIT> ) ; ++ Reg , Offset += <NUM_LIT> ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( <STR_LIT> , dl , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( * Reg , LoadVal ) ) ; } if ( ! ( MemCpySize = ByValSize - Offset ) ) return ; if ( Reg != RegEnd ) { assert ( ( ByValSize < Offset + <NUM_LIT> ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset ,


<s> Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = <STR_LIT> (


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal


<s> if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM || GET_CODE ( operands [ <NUM_LIT> ] ) == MEM )

&& ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return FALSE ;


<s> Parser . Lex ( ) ; if ( check ( Mode == <STR_LIT> || Mode == <STR_LIT> , L , <STR_LIT> ) || check ( Mode != <STR_LIT> && Mode != <STR_LIT> , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement


<s> else return _URC_END_OF_STACK ; new_cfa = ( _Unwind_Ptr ) sc ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = STACK_POINTER_REGNUM ; fs -> cfa_offset = new_cfa - ( _Unwind_Ptr ) context -> cfa ; new_cfa -= <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = ( _Unwind_Ptr ) & ( sc -> sc_regs [ i ] ) - new_cfa ; } fs -> regs . reg [ SIGNAL_UNWIND_RETURN_COLUMN ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SIGNAL_UNWIND_RETURN_COLUMN ] . loc . offset = ( _Unwind_Ptr ) & ( sc -> sc_pc )


<s> unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) >> <NUM_LIT> ; return ( OffBits & <NUM_LIT>


<s> case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee )


<s> int64_t Val = MCE -> getValue ( ) ; uint64_t Upper = UINT64_C ( - <NUM_LIT> ) << ( sizeof ( T ) * <NUM_LIT> ) << ( sizeof ( T ) * <NUM_LIT> ) ; if ( ( Val & Upper ) && ( Val & Upper ) != Upper ) return false ; return <STR_LIT> ( Val & ~ Upper , sizeof


<s> TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return


<s> if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , <NUM_LIT> ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } } return false


<s> unsigned <ISA_LIT>16SPAliasReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> get<ISA_LIT>16SPAliasReg ( ) ; return CurDAG -> getRegister ( <ISA_LIT>16SPAliasReg , TLI .


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ; std :: string FullFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple ) ; assert ( ! FullFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> <<


<s> return MatchOperand_ParseFail ; } if ( Tok . is ( AsmToken :: Integer ) && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { if ( Tok . getIntVal ( ) > <NUM_LIT> || isNegative ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } APFloat F ( ( double ) <STR_LIT> ( Tok . getIntVal ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( F , true , S , getContext ( ) ) ) ; } else { APFloat RealVal ( APFloat :: IEEEdouble ( ) ) ; auto StatusOrErr = RealVal . convertFromString ( Tok . getString ( ) , APFloat :: rmTowardZero ) ; if ( ! StatusOrErr ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isNegative ) RealVal . changeSign ( ) ; if ( AddFPZeroAsLiteral && RealVal . isPosZero (


<s> rtx mt_function_arg ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int slotno , regno ; rtx reg ; slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , &


<s> bool <ISA_LIT>InstrInfo :: expandExtendStackPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBB . findDebugLoc ( MI ) ; MachineBasicBlock * BB = & MBB ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * syscallMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ( BB -> getIterator ( ) ) ; MF . insert ( It , syscallMBB ) ; MF . insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB


<s> lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64


<s> void mep_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { pcum -> nregs = <NUM_LIT> ; if ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype


<s> unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_AARCH64_NONE ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS16 ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS32 ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS64 ) . Default ( - <NUM_LIT> ) ; if ( Type == - <NUM_LIT>


<s> void addMem64Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst , N )


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) { <ISA_LIT>_MC :: InitLLVM2SEHRegisterMapping (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Opnd2 ; if ( isFMAddSub ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; if ( VT . is512BitVector ( )


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN


<s> void <ISA_LIT>ELFStreamer :: emitUnwindRaw ( int64_t Offset , const SmallVectorImpl < uint8_t > & Opcodes ) { FlushPendingOffset ( ) ; SPOffset = SPOffset - Offset ; UnwindOpAsm . EmitRaw (


<s> return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; case TargetOpcode :: G_SDIV : return <STR_LIT> ; case TargetOpcode :: G_UDIV : return <STR_LIT> ; default : return GenericOpc ; } } case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT>


<s> case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX : case Triple :: Darwin


<s> rtx addr = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( gen_sub2_insn ( out , addr ) ) ; return true ; } else return


<s> using namespace <ISA_LIT> ; switch ( Reg ) { case R0 : case R1 : case R2 : case R3 : case R4 : case R5 : case R6 : case R7 : case LR : case


<s> bool isCheapToSpeculateCtlz ( ) const override { return true


<s> unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? <NUM_LIT> : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) )


<s> Inst . addOperand ( MCOperand :: CreateImm ( - ( CE -> getValue (


<s> else Emit<ISA_LIT>MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ,


<s> CCMask &= CCValid ; adjustZeroCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; adjustSubwordCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; Opcode = <STR_LIT> ; if ( CCMask == <STR_LIT> || CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( CmpOp0 ) && DAG . SignBitIsZero ( CmpOp1 ) ) ) ICmpType = <STR_LIT> ; else if ( IsUnsigned ) ICmpType = <STR_LIT> ; else ICmpType = <STR_LIT> ; } if ( shouldSwapCmpOperands ( CmpOp0 , CmpOp1 , ICmpType ) ) { std :: swap ( CmpOp0 , CmpOp1 ) ; CCMask = ( ( CCMask & <STR_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ) ) ; } adjustForTestUnderMask ( DAG , Opcode , CmpOp0 , CmpOp1 , CCValid


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF )


<s> return ( int64x2_t ) __builtin_neon_vcombinedi (


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWindows ( ) ) return CSR_Win_<ISA_LIT>_AAPCS_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_<ISA_LIT>_AAVPCS_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; return CSR_<ISA_LIT>_AAPCS_SaveList


<s> SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoOut = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , MAdd ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT> ) , LoOut ) ; } if ( ! SDValue ( ADDENode , <NUM_LIT> ) . use_empty ( ) ) { SDValue HiOut = CurDAG -> getNode ( <STR_LIT> , DL ,


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget -> hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode (


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isZero ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isZero ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; return SDValue ( ) ; } if ( VT != <STR_LIT> && VT !=


<s> int Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> if ( decl && const_call_insn_operand ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , VOIDmode ) && mips_call_may_need_jalx_p ( decl ) ) return false ; if ( decl && TARGET_CALL_SAVED_GP && ! TARGET_ABICALLS_PIC0 && !

targetm . binds_local_p ( decl ) ) return false ;


<s> rtx aarch_gen_bti_c ( void ) { return gen_bti_nop (


<s> static bool const_in_range ( rtx x , int


<s> return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return lowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>MCAsmBackend ( OSABI


<s> int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } if ( MInfo . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MBB . insert ( MBB . end ( ) , ret ) ; if ( MInfo . FrameConstructionID


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) return MCDisassembler :: Fail ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ! isValidCoprocessorNumber ( Val , featureBits


<s> In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( unsigned ) VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; } if ( VT . getVectorNumElements ( ) != InVT . getVectorNumElements ( ) ) Opcode = getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ; return DAG . getNode ( Opcode ,


<s> bool useAA ( ) const override { return


<s> __arm_vddupq_u32 ( uint32_t * __a , const int


<s> MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset =


<s> bool <ISA_LIT>LoadStoreOpt :: enableNarrowLdMerge ( MachineFunction & Fn ) { bool ProfitableArch = Subtarget -> isCortexA57 ( ) || Subtarget -> isKryo ( ) ; return ProfitableArch && ! Subtarget -> requiresStrictAlign


<s> if ( ! MCE ) return true ; int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent (


<s> bool CantUseFP = needsStackRealignment ( MF ) ; return CantUseFP && CantUseSP (


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> <ISA_LIT>CA53ErratumStub :: <ISA_LIT>CA53ErratumStub ( const uint32_t * pData , size_t pSize , const char * pName , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : m_pData ( pData ) , m_Name ( pName ) , m_Size ( pSize ) { for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++


<s> addr = this_rtx ; if ( delta != <NUM_LIT> ) { if ( delta >= - <NUM_LIT> && delta < <NUM_LIT> ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_constant ( Pmode , this_regno , IP1_REGNUM , delta ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - <NUM_LIT> && vcall_offset < <NUM_LIT> * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true ,


<s> if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) && ( val & <NUM_LIT> ) == <NUM_LIT> ; else return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> - <NUM_LIT> ) ; } else return <NUM_LIT> ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index ,


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && LowerGatherScatterToInterleaved ) { addPass ( createEarlyCSEPass ( ) ) ; addPass ( createInterleavedGatherScatterPass ( TM ) ) ; addPass ( createInstructionCombiningPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass (


<s> assert ( Info != Insts . end ( ) && <STR_LIT> ) ; Info -> SPAdjust +=


<s> MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI ) { while ( NextMBBI != EndMBBI && NextMBBI -> isDebugInstr ( ) ) ++ NextMBBI ; if ( NextMBBI == EndMBBI ) return EndMBBI ; unsigned Off = isIncrementOrDecrement ( * NextMBBI , Reg , Pred , PredReg ) ; if ( Off


<s> void <ISA_LIT>GOT :: applyGOT0 ( uint64_t pAddress ) { llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin ( ) ) ) .


<s> return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc ( ) ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerMUL (


<s> if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX && ! IsAndroid ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; emitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { emitInt32 ( <STR_LIT> :: EXIDX_CANTUNWIND ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: create ( ExTab , MCSymbolRefExpr ::


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumResultVecs + <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N ->


<s> unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } return BaseT :: getCmpSelInstrCost ( Opcode ,


<s> Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( <STR_LIT> ) + <NUM_LIT> ; FReg < <STR_LIT> ; FReg += <NUM_LIT> ) Reserved .


<s> EVT SrcEVT = TLI . getValueType ( DL , Ty , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>SubTarget -> useCRBits ( ) ) return false ; long Imm = <NUM_LIT> ; bool UseImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg , IsZExt )


<s> const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return <NUM_LIT> ; static const uint16_t CallerSavedRegs32Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CallerSavedRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( DisableShifterOp ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc


<s> hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT (


<s> if ( ! ST . is<ISA_LIT>64 ( ) || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) || ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ; if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 (


<s> } if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Tmp = DAG . getConstantFP ( APF , dl , <STR_LIT> ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Tmp ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSelectCC ( dl , Op . getOperand ( <NUM_LIT> ) , Tmp


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> )


<s> MBB -> addSuccessor ( TailTestMBB ) ; MBB = LoopBodyMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , IncReg ) . addReg ( PHIReg ) . addImm ( ProbeSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ProbeSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ProbeSize - <NUM_LIT> ) . addReg ( <NUM_LIT> ) . setMemRefs ( VolLdMMO ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopTestMBB ) ; MBB -> addSuccessor ( LoopTestMBB ) ; MBB = TailTestMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( PHIReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( TailMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB = TailMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( PHIReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( PHIReg ) . setMemRefs ( VolLdMMO ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB = DoneMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT>


<s> if ( GET_CODE ( op ) == MEM ) { rtx a = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) )


<s> unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isDebugValue ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return false ; if ( MI . mayStore ( ) && mayAlias ( LoadMI , MI , TII )


<s> if ( SDValue Op = lowerVectorShuffleWithSHUFPD ( DL , VT , Mask , V1 , V2 , DAG ) ) return Op ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( ! is128BitLaneCrossingShuffleMask ( VT , Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , get1bitLaneShuffleImm8ForMask ( Mask , DL , DAG ) ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } return lowerVectorShuffleWithPERMV ( DL , VT , Mask , V1 , V2 ,


<s> <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum


<s> if ( IsOrXorXorCCZero ) { SDValue A = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue D = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp1 = DAG . getSetCC ( DL , CmpVT , A , B , <STR_LIT> ) ; SDValue Cmp2 = DAG . getSetCC ( DL , CmpVT , C , D , <STR_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , Cmp1 , Cmp2 ) ; } else { SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } if ( OpSize == <NUM_LIT> ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT>


<s> lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , copyMoveD ) ; return


<s> void setPICStyle ( PICStyles :: Style


<s> void emitSIBByte ( unsigned SS , unsigned Index , unsigned Base , unsigned & CurByte , raw_ostream & OS ) const { emitByte ( modRMByte ( SS , Index ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand


<s> } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr

. getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return


<s> assert ( Kind == k_Prefetch && <STR_LIT> ) ; return Prefetch . Val


<s> return __builtin_mve_vqdmlsdhq_sv16qi ( __inactive ,


<s> unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = GetOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBOffsets [ DestBB -> getNumber ( ) ] ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << GetOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addVecListOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst


<s> return ( float64x1_t ) { vrecped_f64 ( vget_lane_f64 (


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode

( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ;


<s> bool is64BitRes = ResVT . is64BitVector ( ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + Vec0Idx , N -> op_begin ( ) + Vec0Idx + NumVecs ) ; SDValue TblReg = createQTuple ( Regs ) ; unsigned Opc = getTBLOpc ( IsExt , is64BitRes , NumVecs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( TblReg ) ; Ops . push_back ( N -> getOperand ( Vec0Idx


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> SmallVector < std :: pair < MachineInstr * , MachineInstr * > , <NUM_LIT> > MIReplacements ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * MI = & * I ; if ( MachineInstr * NewMI = tryReplaceInstr ( MI , MBB ) ) MIReplacements . push_back ( std :: make_pair ( MI , NewMI ) ) ; LiveRegs . stepBackward ( * MI


<s> auto * MaskBV = Mask [ i ] < Size ? BV1 : BV2 ; auto * ExpectedBV = ExpectedMask [ i ] < Size ? BV1 : BV2 ; if ( ! MaskBV || ! ExpectedBV || MaskBV -> getOperand ( Mask [ i ] % Size )

!= ExpectedBV -> getOperand ( ExpectedMask [ i ] % Size ) ) return false ;


<s> break ; case Prefix : OS << <STR_LIT> << Pref . Prefixes ; break ; case Memory : OS << <STR_LIT> << Mem . ModeSize ; if ( Mem . Size ) OS << <STR_LIT> << Mem . Size ; if ( Mem . BaseReg ) OS << <STR_LIT> << <ISA_LIT>IntelInstPrinter :: getRegisterName ( Mem . BaseReg ) ; if ( Mem . IndexReg ) OS << <STR_LIT> << <ISA_LIT>IntelInstPrinter :: getRegisterName ( Mem . IndexReg ) ; if ( Mem . Scale ) OS << <STR_LIT> << Mem . Scale ; if ( Mem . Disp ) PrintImmValue


<s> inline int vec_any_gt ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgtfp_p ( __CR6_EQ_REV , a1 , a2


<s> case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicIndex ( N , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicDUP ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return LowerSVEIntrinsicEXT ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , <STR_LIT> ) ; } return SDValue (


<s> if ( SDValue Test = EmitAVX512Test ( Op0 , Op1 , CC , dl , DAG , Subtarget , <ISA_LIT>CC ) ) return Test ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; <ISA_LIT>CC = Op0 . getOperand ( <NUM_LIT> ) ; if ( Invert ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } bool IsFP = Op1 . getSimpleValueType (


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> if ( MI . hasOrderedMemoryRef ( ) ) return false ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MI . modifiesRegister ( BaseReg , TRI ) ) return false ; if ( isLdStPairSuppressed ( MI ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case


<s> return Value ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return


<s> assert ( Ty -> isVectorTy ( ) && <STR_LIT> ) ; unsigned Cost = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Ty -> getVectorNumElements ( ) ; i < e ; ++ i ) { if ( Insert ) Cost += TopTTI -> getVectorInstrCost ( Instruction :: InsertElement , Ty , i ) ; if ( Extract ) Cost += TopTTI -> getVectorInstrCost ( Instruction :: ExtractElement , Ty , i ) ; } return


<s> const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset = false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB =


<s> return <STR_LIT> ( MCII . get ( MI . getOpcode (


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator


<s> if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt ; if ( TLI . isBigEndian ( ) && SrcVT . isVector ( ) && SrcVT . getVectorNumElements ( ) > <NUM_LIT> ) Cvt = DAG . getNode ( <STR_LIT> , dl , DAG .

getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Op ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitThumbSet ( MCSymbol * Symbol , const MCExpr *


<s> if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address

, Address + imm + <NUM_LIT> , Decoder ) ;


<s> if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , <NUM_LIT> ) = shallow_copy_rtvec ( XVEC ( pat , <NUM_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set


<s> got_entry = getTarget ( ) . getGOT ( ) . create ( ) ; getTarget ( ) . getGOT ( ) . create ( ) -> setValue ( <NUM_LIT> ) ; helper_DynRel_init ( NULL , * got_entry , <NUM_LIT> , llvm :: ELF ::


<s> case <STR_LIT> : case <STR_LIT> : { unsigned OpOffset = <STR_LIT> ( Desc . TSFlags ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> + OpOffset , <NUM_LIT> + OpOffset ) ; } return false ; } case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> OS << '$' << StringRef ( getRegisterName ( RegNo


<s> Reloc :: Model getRelocationModel ( )


<s> if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ~ ( ~ ImmValue & ~ ( ~ ImmValue + <NUM_LIT> ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue . countPopulation ( )


<s> if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 ,


<s> if ( STI . hasMOPS ( ) ) { return EmitMOPS ( <STR_LIT> , DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , MachinePointerInfo { } ) ; } ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout


<s> unsigned HOST_WIDE_INT elt ; unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( arg0 ) ) ; unsigned int truncated_selector ; elt = TREE_INT_CST_LOW ( arg1 ) ; truncated_selector = elt % size ; op1 = GEN_INT ( truncated_selector ) ; } tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 ,


<s> if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) && ! Subtarget -> isFPOnlySP ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII

. get ( Opc ) , ResultReg ) . addReg ( FP ) ) ;


<s> p -> next = extern_head ; p -> decl = decl ; p -> name =


<s> void addMEMrrOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) LegacyInfo . setAction ( { MemOp , Ty } , LegacyLegalizeActions :: Legal ) ; for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { LegacyInfo . setAction ( { G_INSERT , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_EXTRACT , <NUM_LIT> , Ty } , LegacyLegalizeActions :: Legal ) ; } for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) { LegacyInfo . setAction ( { G_INSERT , <NUM_LIT> , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_EXTRACT , Ty } , LegacyLegalizeActions :: Legal ) ; } for ( const auto


<s> assert ( ( ReusableCCMask & ~ CCValues ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < MachineOperand * , <NUM_LIT> > AlterMasks ; for ( unsigned int I = <NUM_LIT> , E = CCUsers . size ( ) ; I != E ; ++ I ) { MachineInstr * MI = CCUsers [ I ] ; unsigned Flags = MI -> getDesc ( ) . TSFlags ; unsigned FirstOpNum ; if ( Flags & <STR_LIT> ) FirstOpNum = <NUM_LIT> ; else if ( Flags & <STR_LIT> ) FirstOpNum = MI -> getNumExplicitOperands ( ) - <NUM_LIT> ; else return false ; unsigned CCValid = MI -> getOperand ( FirstOpNum ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( FirstOpNum + <NUM_LIT> ) . getImm ( ) ; unsigned OutValid = ~ ReusableCCMask & CCValid ; unsigned OutMask = ~ ReusableCCMask & CCMask ; if ( OutMask != <NUM_LIT> && OutMask != OutValid ) return false ; AlterMasks . push_back ( & MI -> getOperand ( FirstOpNum ) ) ; AlterMasks . push_back ( & MI -> getOperand ( FirstOpNum + <NUM_LIT> ) ) ; } for ( unsigned I = <NUM_LIT> , E = AlterMasks . size ( ) ; I != E ; I += <NUM_LIT> ) { AlterMasks [ I ] -> setImm ( CCValues ) ; unsigned CCMask = AlterMasks [ I + <NUM_LIT> ] -> getImm ( ) ; if ( CCMask & ~ ReusableCCMask ) AlterMasks [ I + <NUM_LIT> ] -> setImm ( ( CCMask & ReusableCCMask ) | ( CCValues & ~ ReusableCCMask ) ) ; } int CCDef = MI . findRegisterDefOperandIdx ( <STR_LIT> , false , true , TRI ) ; assert ( CCDef >= <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( CCDef ) . setIsDead ( false ) ; MachineBasicBlock :: iterator MBBI = MI