<s> if ( TARGET_ALTIVEC && testing_p ) return true ; if ( ( vmode == V2SFmode && TARGET_PAIRED_FLOAT ) || ( vmode == V2SImode && TARGET_SPE ) || ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER


<s> return __builtin_neon_vcvtasv4hf ( __a )


<s> if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } if ( builtin_sha1h_p ) op1 = GEN_INT ( TARGET_BIG_END ? <NUM_LIT> : <NUM_LIT> ) ; if ( builtin_sha1h_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } unsigned SizeInBits = TripCount -> getType ( ) -> getScalarSizeInBits ( ) ; auto MaxMinusVW = APInt ( SizeInBits , ~ <NUM_LIT> ) - APInt ( SizeInBits , VectorWidth ) ; APInt UpperboundTC = SE -> getUnsignedRangeMax ( TC ) ; if ( UpperboundTC . ugt ( MaxMinusVW ) && ! ForceTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; dbgs ( ) << UpperboundTC << <STR_LIT> << MaxMinusVW << <STR_LIT> ; ) ; return false ; } auto * ECPlusVWMinus1 = SE -> getAddExpr ( EC , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ) ; ConstantRange RangeCeil = SE -> getUnsignedRange ( Ceil ) ; ConstantRange RangeTC = SE -> getUnsignedRange ( TC ) ; if ( ! RangeTC . isSingleElement ( ) ) { auto ZeroRange = ConstantRange ( APInt ( TripCount -> getType ( ) -> getScalarSizeInBits ( ) , <NUM_LIT> ) ) ; RangeTC = RangeTC . unionWith ( ZeroRange ) ; } if ( ! RangeTC . contains ( RangeCeil ) && ! ForceTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * IV = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * IVExpr = SE -> getSCEV ( IV ) ; auto * AddExpr = dyn_cast < SCEVAddRecExpr > ( IVExpr ) ; if ( ! AddExpr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; IVExpr -> dump ( ) ) ; return false ; } if ( AddExpr -> getLoop ( ) != L ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Step = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Step ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddExpr -> getOperand ( <NUM_LIT> ) -> dump ( ) ) ; return false ; } auto StepValue = Step -> getValue ( ) -> getSExtValue


<s> auto VRegAndVal = getConstantVRegValWithLookThrough ( OpMI -> getOperand ( Idx ) . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return None ; if ( Idx == <NUM_LIT> ) ImmVal = VRegAndVal -> Value ; if ( ImmVal != VRegAndVal -> Value ) return


<s> assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( LowercaseString ( Tok . getString ( ) ) ) ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> + Tok . getString ( ) + <STR_LIT> ) ; } if ( RegNo == <NUM_LIT> && ( Tok . getString ( ) == <STR_LIT> || Tok . getString ( ) == <STR_LIT> ) ) { RegNo = <STR_LIT> ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ;


<s> bool IsVector = false ; if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { StringRef Kind ; RegNum = tryMatchVectorRegister ( Kind , false ) ; if ( ! Kind . empty ( ) ) { Error ( SRegLoc , <STR_LIT> ) ; return false ; } IsVector = true ; } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; Error ( SRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false


<s> assert ( isSplatShuffleMask ( SVOp , EltSize ) ) ; if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) return ( <NUM_LIT> / EltSize ) - <NUM_LIT> - ( SVOp -> getMaskElt


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; if ( isFPCmp ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Opc = FPBranchCodeToOpc ( GetFPBranchCodeFromCond ( CC ) ) ; BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; } else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> )

. getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder


<s> else if ( ! CommonRC -> hasSubClass ( SrcRC ) ) CommonRC = <NUM_LIT> ; if ( CommonRC ) { if ( CommonRC == & <STR_LIT> || CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( CommonRC == & <STR_LIT> || CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( CommonRC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; }


<s> if ( Subtarget -> isTargetNaCl ( ) ) return new TargetLoweringObjectFileNaCl ( ) ; if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( )

) return new TargetLoweringObjectFileCOFF ( ) ;


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT>


<s> unsigned int __i = ( unsigned short ) __w << <NUM_LIT> | ( unsigned short ) __w ; return _mm_set1_pi32 ( __i


<s> else ccode = <STR_LIT> ; sprintf ( string , <STR_LIT> , ccode , label ) ; return string ; } code = GET_CODE ( op ) ; if ( ! REG_P ( XEXP ( op , <NUM_LIT> ) ) ) { code = swap_condition ( code ) ; operands = <STR_LIT> ; } else operands = <STR_LIT> ; if ( really_reversed ) code = reverse_condition ( code ) ; switch ( code ) { case EQ : ccode = <STR_LIT> ; break ; case NE : ccode = <STR_LIT> ; break ; case GE : ccode = <STR_LIT> ; break ; case LT : ccode = <STR_LIT> ; break ; case GT : ccode = <STR_LIT> ; break ; case LE : ccode = <STR_LIT> ; break ; case GEU : ccode = <STR_LIT> ; break ; case LTU : ccode = <STR_LIT> ; break ; case GTU : ccode = <STR_LIT> ; break ; case LEU : ccode = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( need_longbranch ) templ = <STR_LIT> ; else templ = <STR_LIT>


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> call_abi =


<s> static SDValue getExtendInVec ( unsigned Opc , const SDLoc & DL , EVT VT , SDValue In , SelectionDAG & DAG ) { EVT InVT = In . getValueType ( ) ; assert ( ( <STR_LIT> == Opc || <STR_LIT> == Opc ) && <STR_LIT> ) ; if ( VT . is128BitVector ( ) && InVT . is128BitVector ( ) ) return <STR_LIT> == Opc ? DAG . getSignExtendVectorInReg ( In , DL , VT ) : DAG . getZeroExtendVectorInReg ( In , DL , VT ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && InVT . getSizeInBits ( ) > <NUM_LIT> ) { int Scale = VT . getScalarSizeInBits ( ) / InVT . getScalarSizeInBits ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( int ) VT . getSizeInBits ( ) / Scale ) ) ; } return DAG . getNode ( Opc , DL , VT ,


<s> int64_t Result = Value . getConstant ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_HA16 : Result = ( ( Result >> <NUM_LIT> ) + ( ( Result & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_LO16 : Result = Result & <NUM_LIT> ; break ; } Res = MCValue :: get ( Result ) ; } else { MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM


<s> if ( ! DestSrc ) return None ; Register DestReg = DestSrc -> Destination -> getReg ( ) ; Register SrcReg = DestSrc -> Source -> getReg ( ) ; auto Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , { } ) ; if ( DestReg == DescribedReg ) return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcReg , false ) , Expr ) ; if ( MI . getOpcode ( ) == <STR_LIT> && TRI -> isSuperRegister ( DestReg , DescribedReg ) ) return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcReg , false ) , Expr ) ; if ( MI . getOpcode ( ) == <STR_LIT> && TRI -> isSubRegister ( DestReg , DescribedReg ) ) { Register SrcSubReg = TRI -> getSubReg ( SrcReg , <STR_LIT> ) ; return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcSubReg


) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT>


<s> SmallVector < Instruction * , <NUM_LIT> > DecomposedVectors ; SmallVector < Value * , <NUM_LIT> > TransposedVectors ; VectorType * ShuffleTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( isa < LoadInst > ( Inst ) ) { decompose ( Inst , Factor , ShuffleTy , DecomposedVectors ) ; Type * ShuffleEltTy = Inst -> getType ( ) ; unsigned NumSubVecElems = ShuffleEltTy -> getVectorNumElements ( ) / Factor ; switch ( NumSubVecElems ) { default : return false ; case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case <NUM_LIT>


<s> bool isMemoryUnscaledFB128 ( ) const { return isMemoryUnscaled ( ) &&


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitBPOSGE32 ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = llvm :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( VR2 ) . addMBB ( FBB


<s> memset ( rws_sum , <NUM_LIT> , sizeof (


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHPOINT ( MCStreamer & OutStreamer , StackMaps & SM , const MachineInstr & MI ) { SM . recordPatchPoint ( MI ) ; PatchPointOpers Opers ( & MI ) ; int64_t CallTarget = Opers . getMetaOper ( PatchPointOpers :: TargetPos ) . getImm ( ) ; unsigned EncodedBytes = <NUM_LIT> ; if ( CallTarget ) { assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; unsigned ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm (


<s> return __builtin_ia32_reduceph128_mask ( __A , __B , _mm_setzero_ph ( ) , ( __mmask8 ) -


<s> if ( isFullyRelaxed ( RF ) ) return false ; MCInst Relaxed ; relaxInstruction ( RF . getInst ( ) , * RF . getSubtargetInfo ( ) , Relaxed ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; Emitter . encodeInstruction ( Relaxed , VecOS , Fixups , * RF . getSubtargetInfo ( ) ) ; const unsigned OldSize = RF . getContents ( ) . size ( ) ; const unsigned NewSize = Code . size ( ) ; assert ( NewSize >= OldSize && <STR_LIT> ) ; unsigned Delta = NewSize - OldSize ; if ( Delta > RemainingSize ) return false ; RF . setInst ( Relaxed ) ; RF . getContents ( ) = Code ; RF . getFixups ( )


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> __o = __builtin_aarch64_ld4rv2df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o ,


<s> static bool usesTheStack ( const MachineFunction & MF ) { const MachineRegisterInfo & MRI = MF . getRegInfo (


<s> } llvm :: sort ( OpRegs ) ; std :: set_difference ( Regs . begin ( ) , Regs . end ( ) , OpRegs . begin ( ) , OpRegs . end ( ) , std :: back_inserter


<s> void <ISA_LIT>FrameLowering :: layoutStackRegions ( MachineFunction & MF ) const { const SmallVectorImpl < StackRegion * > & StackRegions = MF . getFrameInfo ( ) -> getStackRegions ( ) ; assert ( StackRegions . size ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; SVEVecStackRegion * Pred = static_cast < SVEVecStackRegion * > ( StackRegions [ <NUM_LIT> ] ) ; SVEVecStackRegion * Vec = static_cast < SVEVecStackRegion * > ( StackRegions [ <NUM_LIT> ] ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; bool HasFP = TFI -> hasFP ( MF ) ; uint64_t Offset = HasFP ? <NUM_LIT> : <NUM_LIT> ; Offset = Pred -> layoutRegion ( MF , Offset , <NUM_LIT> ) ; if ( HasFP && ( Pred -> getRegionSize ( ) > <NUM_LIT> ) ) { Pred -> setRegionSize ( Pred -> getRegionSize (


<s> } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; std :: vector < EVT > NodeTys ; SDValue Ops [ <NUM_LIT> ] , Result , MFFSreg , InFlag , FPreg ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; MFFSreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Lo ; Ops [ <NUM_LIT> ] = Hi ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ]


<s> static DecodeStatus DecodeDoubleRegLoad ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ( Rt & <NUM_LIT> ) || Rt == <NUM_LIT> || Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt + <NUM_LIT>


<s> if ( INSN_CODE ( insn ) == CODE_FOR_insn_group_barrier ) { gcc_assert ( GET_MODE ( insn ) != TImode ) ; if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; memcpy ( temp_dfa_state , curr_state -> dfa_state , dfa_state_size ) ; if ( curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) curr_state -> middle_bundle_stops ++ ; if ( state_transition ( temp_dfa_state , dfa_pre_cycle_insn ) >= <NUM_LIT> && curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) { free_bundle_state ( curr_state ) ; return ; } } else if ( GET_MODE ( insn ) != TImode ) { if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; curr_state -> accumulated_insns_num ++ ; gcc_assert ( ! unknown_for_bundling_p ( insn ) ) ; if ( ia64_safe_type ( insn ) == TYPE_L ) curr_state -> accumulated_insns_num ++ ; } else { if ( before_nops_num > <NUM_LIT> && get_attr_first_insn ( insn ) == FIRST_INSN_YES ) { free_bundle_state ( curr_state ) ; return ; } state_transition ( curr_state -> dfa_state , dfa_pre_cycle_insn ) ; state_transition ( curr_state -> dfa_state , NULL ) ; curr_state -> cost ++ ; if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; curr_state -> accumulated_insns_num ++ ; if ( unknown_for_bundling_p ( insn ) ) { curr_state -> after_nops_num = <NUM_LIT> - curr_state -> accumulated_insns_num % <NUM_LIT> ; curr_state -> accumulated_insns_num += <NUM_LIT> - curr_state -> accumulated_insns_num % <NUM_LIT> ; } else if ( ia64_safe_type ( insn ) == TYPE_L ) curr_state -> accumulated_insns_num ++ ; } if ( ia64_safe_type ( insn ) == TYPE_B ) curr_state -> branch_deviation += <NUM_LIT> - ( curr_state -> accumulated_insns_num - <NUM_LIT> ) % <NUM_LIT> ; if ( try_bundle_end_p && curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) { if ( ! only_bundle_end_p && insert_bundle_state ( curr_state ) ) { state_t dfa_state ; struct bundle_state * curr_state1 ; struct bundle_state * allocated_states_chain ; curr_state1 = get_free_bundle_state ( ) ; dfa_state = curr_state1 -> dfa_state ; allocated_states_chain = curr_state1 -> allocated_states_chain ; * curr_state1 = * curr_state ; curr_state1 -> dfa_state = dfa_state ; curr_state1 -> allocated_states_chain = allocated_states_chain ; memcpy ( curr_state1 -> dfa_state , curr_state -> dfa_state , dfa_state_size ) ; curr_state =


<s> unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return <NUM_LIT> ; case vec_perm : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case vec_promote_demote : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case cond_branch_taken : return <NUM_LIT> ; case unaligned_load : case vector_gather_load : if ( TARGET_P9_VECTOR ) return <NUM_LIT> ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable (


<s> __inline__ static unsigned long long sh_media_MSHLLD_L ( unsigned long long mm , unsigned int mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VSRCTmp1 ) . addReg ( NewVReg ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; insertSwap ( MI , InsertPoint , VSRCTmp2 , VSRCTmp1 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( VSRCTmp2 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; } else


<s> case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return selectShift ( I , MRI , MF ) ; case TargetOpcode ::


<s> static bool isAllInactivePredicate ( SDValue N ) { while ( N . getOpcode ( ) == <STR_LIT> ) N = N . getOperand ( <NUM_LIT> ) ; return <STR_LIT> ( N . getNode ( )


<s> if ( matchVectorShuffleWithPACK ( VT , PackVT , V1 , V2 , PackOpcode , Mask , DAG , Subtarget ) ) return DAG . getNode ( PackOpcode , DL , VT , DAG . getBitcast ( PackVT , V1 ) , DAG . getBitcast ( PackVT , V2 ) ) ; return SDValue (


<s> if ( tmv != NULL_TREE && CLASSTYPE_TYPEINFO_VAR ( tmv ) != NULL_TREE ) { tree na , ti_decl = CLASSTYPE_TYPEINFO_VAR ( tmv ) ; na = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , NULL_TREE ) ; decl_attributes ( & ti_decl , na , <NUM_LIT> ) ; } for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree thunk ; maybe_add_dllexport ( member ) ; for ( thunk = DECL_THUNKS ( member ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) maybe_add_dllexport ( thunk ) ; } for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; } else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) != NULL_TREE ) { for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllimport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; bool IsEHFuncletEpilogue = MBBI == MBB . end ( ) ? false : isFuncletReturnInstr ( * MBBI ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int FIOffset ; unsigned BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! needsStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } Register MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum +


<s> return ( uint8x16_t ) __builtin_neon_vqshluv16qi ( ( int8x16_t ) __a ,


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> static MachineInstr * foldPatchpoint ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex , const TargetInstrInfo & TII ) { MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( MI -> getOpcode ( ) ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; bool isPatchPoint = MI -> getOpcode ( ) == TargetOpcode :: PATCHPOINT ; unsigned StartIdx = isPatchPoint ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < StartIdx ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; for ( unsigned i = StartIdx ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( std :: find ( Ops . begin ( ) , Ops . end ( ) , i ) != Ops . end ( ) ) { MIB . addOperand ( MachineOperand :: CreateImm ( StackMaps :: IndirectMemRefOp ) ) ; MIB . addOperand ( MachineOperand :: CreateFI ( FrameIndex ) ) ; addOffset ( MIB


<s> if ( ! <ISA_LIT>SubTarget -> useCRBits ( ) ) return ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; if ( ! N -> hasOneUse ( ) ) return ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , O0 . getNode ( ) , O1 . getNode ( ) ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType ( <NUM_LIT> ) , Cond , TrueRes ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands (


<s> bool <ISA_LIT>AddressTypePromotion :: propagateSignExtension ( Instructions & SExtInsts ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool LocalChange = false ; SetOfInstructions ToRemove ; ValueToInsts ValToSExtendedUses ; while ( ! SExtInsts . empty ( ) ) { Instruction * SExt = SExtInsts . pop_back_val ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * SExt << '\n' ) ; if ( SExt -> use_empty ( ) && ToRemove . count ( SExt ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } while ( isa < Instruction > ( SExt -> getOperand ( <NUM_LIT> ) ) ) { Instruction * Inst = dyn_cast < Instruction > ( SExt -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Inst << '\n' ) ; if ( ! canGetThrough ( Inst ) || ! shouldGetThrough ( Inst ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; } LocalChange = true ; if ( isa < SExtInst > ( Inst ) || isa < TruncInst > ( Inst ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; while ( ! Inst -> use_empty ( ) ) { Value :: use_iterator UseIt = Inst -> use_begin ( ) ; Instruction * UseInst = dyn_cast < Instruction > ( * UseIt ) ; assert ( UseInst


<s> vld1q_p64 ( const poly64_t * a ) { return ( poly64x2_t ) __builtin_aarch64_ld1v2di ( (

const __builtin_aarch64_simd_di * ) a ) ;


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uint4 ) ( a ) , (


<s> bool isVSFRCRegister ( unsigned Register ) const { return MRI . getRegClass ( Register ) -> getID ( ) ==


<s> if ( STI . in<ISA_LIT>16Mode ( ) ) return create<ISA_LIT>16TargetLowering


<s> Op -> Kind = MEMORY_REG_REG ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem . OffsetReg = OffsetReg ; Op -> Mem . Offset


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: SwiftTail ) return CSR_<ISA_LIT>_AAPCS_SwiftTail_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Win64 ) return CSR_<ISA_LIT>_AAPCS_X18_SaveList ; if ( hasSVEArgsOrReturn ( MF )


<s> } if ( is_sse ) { if ( TARGET_AVX ) { strcpy ( buf , ssep ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , ssep + <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } return buf ; } strcpy ( buf , p ) ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case MULT : case PLUS : if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; } if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; case MINUS : case DIV : if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p


<s> MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE (


<s> if ( ! imported [ ( int ) code ] ) { imported [ ( int ) code ] = <NUM_LIT> ; strcpy ( str , import_string


<s> case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) ) ) ; return MCDisassembler ::


<s> return ( vector signed int ) __builtin_altivec_vsum4shs ( ( vector signed short )


<s> Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> Mem . FrontendSize = FrontendSize ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = false ; return Res


<s> return FI <= InArgFIRange . first && FI


<s> -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( ! LastInst -> getDesc ( ) . isBranch ( ) ) return true ; if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( LastInst -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( LastOpc != <STR_LIT> ) { int LastNumOp = LastInst -> getNumOperands ( ) ; TBB = LastInst -> getOperand ( LastNumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; for ( int i = <NUM_LIT> ; i < LastNumOp - <NUM_LIT> ; i ++ ) { Cond . push_back ( LastInst -> getOperand ( i ) ) ; } return false ; } } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; <STR_LIT> BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != <STR_LIT> && LastOpc == <STR_LIT> ) { int SecondNumOp = SecondLastInst


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) :

<ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI


<s> if ( ! cum ) return false ; if ( TARGET_SHCOMPACT ) { cum -> byref = shcompact_byref ( cum , mode , type , named ) ; return cum -> byref


<s> bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std

:: vector < CalleeSavedInfo > & CSI ) const override {


<s> PreAnalyzeCallResultForVectorFloat ( Ins , RetTy ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear (


<s> DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( Index . getOpcode ( ) == <STR_LIT> && Index . getScalarValueSizeInBits ( ) == <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == <NUM_LIT> ) { if ( DAG . SignBitIsZero ( Index . getOperand ( <NUM_LIT> ) ) ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Index . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( Index . getNode ( ) ) ; DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } } SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasAVX512 ( ) && Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Mask . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( ! Subtarget . hasAVX512 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; KnownBits Known ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , Known , TLO ) ) { DCI . AddToWorklist ( Mask . getNode ( ) ) ; DCI . CommitTargetLoweringOpt ( TLO ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue (


<s> ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; expand_fix ( op0 , adj , <NUM_LIT>


<s> unsigned Idx = WhichResult ; for ( unsigned i = <NUM_LIT> ; i != Half ; ++ i ) { int MIdx = M [ i + j * Half ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx !=


<s> MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( RI -> getStackRegister ( ) , stackGrowth ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ; MachineLocation CSDst ( RI -> getStackRegister (


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO .


<s> if ( GET_MODE_UNIT_BITSIZE ( mem_mode ) < type_suffix ( <NUM_LIT> ) . element_bits ) add_input_operand ( icode , CONSTM1_RTX ( VNx16BImode ) ) ; return generate_insn ( icode )


<s> const InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector ( ) const { return InstSelector .


<s> MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator FalseInsertionPoint = FalseMBB -> begin ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , unsigned > FalseBBRegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) { auto & MI = * MIIt ++ ; if ( ! MI . mayLoad ( ) ) { unsigned FalseReg = MI . getOperand ( <STR_LIT> ( MI ) == CC ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; while ( true ) { auto FRIt = FalseBBRegRewriteTable . find ( FalseReg ) ; if ( FRIt == FalseBBRegRewriteTable . end ( ) ) break ; FalseReg = FRIt -> second ; } FalseBBRegRewriteTable [ MI . getOperand ( <NUM_LIT> ) . getReg ( ) ] = FalseReg ; continue ; } assert ( <STR_LIT> ( MI ) == OppCC && <STR_LIT> <STR_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned TmpReg = MRI -> createVirtualRegister ( RC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( * MBB -> getParent ( ) , MI , TmpReg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; auto * NewCMOV = NewMIs . pop_back_val ( ) ; assert ( <STR_LIT> ( * NewCMOV ) == OppCC && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewCMOV -> dump ( ) ) ; MBB -> insert ( MachineBasicBlock :: iterator ( MI ) , NewCMOV ) ; if ( & * MIItBegin == & MI ) MIItBegin = MachineBasicBlock :: iterator ( NewCMOV ) ; for ( auto * NewMI : NewMIs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ) ; FalseMBB -> insert ( FalseInsertionPoint , NewMI ) ; for ( auto & MOp : NewMI -> uses ( ) ) { if ( ! MOp . isReg ( ) ) continue ; auto It = FalseBBRegRewriteTable . find ( MOp . getReg ( ) ) ; if ( It == FalseBBRegRewriteTable . end ( ) ) continue ; MOp . setReg ( It -> second ) ; MOp . setIsKill ( false ) ; } } MBB -> erase ( MachineBasicBlock :: iterator ( MI ) , std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; FalseBBRegRewriteTable [ NewCMOV -> getOperand ( <NUM_LIT> ) . getReg


<s> if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> divsd : cost -> divss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss ) ; else return cost -> divide [


<s> return ( float32x4_t ) __builtin_neon_vminnmv4sf ( a ,


<s> int Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < BitSize ; ShiftVal += <NUM_LIT> ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( <NUM_LIT> ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsFlagSetting = false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefMI . print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; NewCmp = convertToFlagSetting ( DefMI , IsFlagSetting ) ; NewBr = convertToCondBr ( MI ) ; break ; } } break ; } ( void ) NewCmp ; ( void


<s> static DecodeStatus DecodeFP32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void


<s> MachineInstr * <ISA_LIT>InstrInfo :: getConstantDefMI ( MachineInstr & MI , unsigned & ConstOp , bool & SeenIntermediateUse ) const { ConstOp = ~ <NUM_LIT> ; MachineInstr * DefMI = nullptr ; MachineRegisterInfo * MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MRI -> isSSA ( ) ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( TargetRegisterInfo :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { ConstOp = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg )


<s> return new <ISA_LIT>MCCodeEmitter ( TM ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { return LowerGlobalOrExternal ( Op , DAG ,


<s> static unsigned getADDriOpcode ( unsigned is64Bit , int64_t Imm ) { if ( is64Bit ) { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & <NUM_LIT> ) == <NUM_LIT> ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> && ! reg_addr [ mode ] . scalar_in_vmx_p ) return <NUM_LIT> ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % <NUM_LIT> ) == <NUM_LIT> ) && FP_REGNO_P ( last_regno ) ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return <NUM_LIT> ; if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) )


<s> case Type :: DoubleTyID : return true ; case Type :: FP128TyID : return EnableQuadPrecision && Subtarget . hasP9Vector (


<s> return ( __m128 ) __builtin_ia32_cvtuqq2ps256_mask ( ( __v4di ) __A , ( __v4sf )

_mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DataLayout ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_STORE ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; SDValue Chain = DAG . getTruncStore ( Node -> getChain ( ) , SDLoc ( Op ) , Node -> getVal ( ) , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Chain ) ,


<s> lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType (


<s> auto TargetABI = StringSwitch < ABI > ( ABIName ) . Case ( <STR_LIT> , ABI_ILP32S ) . Case ( <STR_LIT> , ABI_ILP32F ) . Case ( <STR_LIT> , ABI_ILP32D ) . Case ( <STR_LIT> , ABI_LP64S

) . Case ( <STR_LIT> , ABI_LP64F ) . Case ( <STR_LIT> , ABI_LP64D ) . Default ( ABI_Unknown ) ;


<s> Scale = getI8Imm ( AM . Scale , DL ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ; assert ( AM . SymbolFlags == <NUM_LIT> && <STR_LIT> ) ; Disp = CurDAG -> getMCSymbol ( AM . MCSym , <STR_LIT> ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , DL , <STR_LIT> ) ; if ( AM . Segment . getNode ( )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( N . getOpcode ( ) != <STR_LIT> ) { ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || NC -> getZExtValue ( ) != <NUM_LIT> ) return false ; Base = Offset = N ; return true ; } Base = N . getOperand


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } } ( ) ; MachineMemOperand :: Flags Flags = MachineMemOperand :: MOStore ; if ( isVolatile ) Flags |= MachineMemOperand :: MOVolatile ; if ( ! IsSet ) Flags |= MachineMemOperand :: MOLoad ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * DstOp = MF . getMachineMemOperand ( DstPtrInfo , Flags , ConstSize , Alignment ) ; auto * SrcOp = MF . getMachineMemOperand ( SrcPtrInfo , Flags , ConstSize , Alignment ) ; if ( IsSet ) { if ( SrcOrValue . getValueType ( ) != <STR_LIT> ) SrcOrValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SrcOrValue ) ; SDValue Ops [ ] = { Dst , Size , SrcOrValue


<s> bool isVK16Pair ( ) const { return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { if ( isVarArg ) { report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ;


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) ; MCE . addRelocation ( MR )


<s> if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ?


<s> isZeroExtendingOp ( MI ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MI . getParent ( ) -> getBasicBlock ( ) == & MF -> getFunction ( ) . getEntryBlock ( ) ) { Register VReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MF -> getRegInfo ( ) . isLiveIn ( VReg ) ) return SignExt ? FuncInfo -> isLiveInSExt ( VReg ) : FuncInfo -> isLiveInZExt ( VReg ) ; } if ( SrcReg == <STR_LIT> ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator II = MachineBasicBlock :: const_instr_iterator ( & MI ) ; if ( II != MBB -> instr_begin ( ) && ( -- II ) -> getOpcode ( ) == <STR_LIT> ) { const MachineInstr & CallMI = * ( -- II ) ; if ( CallMI . isCall ( ) && CallMI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) { const Function * CalleeFn = dyn_cast < Function > ( CallMI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; const IntegerType * IntTy = dyn_cast < IntegerType > ( CalleeFn -> getReturnType ( ) ) ; const AttributeSet & Attrs = CalleeFn -> getAttributes ( ) . getRetAttributes ( ) ; if ( IntTy && IntTy -> getBitWidth ( ) <= <NUM_LIT> ) return Attrs . hasAttribute ( SignExt ? Attribute :: SExt : Attribute :: ZExt ) ; } } } } if ( ! Register :: isVirtualRegister ( SrcReg )


<s> { RTLIB :: OEQ_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: O_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ]


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine (


<s> if ( ( CC == <STR_LIT> ) && ! ( ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isOneValue ( ) ) || ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ) return false ; if ( ( CC == <STR_LIT> ) && ! ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) || <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ; if ( SelectOp1 . getOpcode ( ) != <STR_LIT> ) return false ; Op0 = SelectOp1 . getOperand ( <NUM_LIT> ) ; Op1 = SelectOp1 . getOperand ( <NUM_LIT>


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( CC == <STR_LIT> && getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitCMPFPw0 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [


<s> assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , FIOperandNum , this ,


<s> unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegN = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegN ) ; Binary |= ( RegN & <NUM_LIT> )


<s> } } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant

( InNVT . getVectorNumElements ( ) , <STR_LIT> ) ) ;


<s> if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Id = getParser ( ) . getTok ( ) . getIntVal ( ) ; if ( Id <= - <NUM_LIT> && ! isValidMCLOHType ( Id ) ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } else { StringRef Name = getTok ( ) . getIdentifier ( ) ; int Id = MCLOHNameToId ( Name ) ; if ( Id == - <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } Lex ( ) ; int NbArgs = MCLOHIdToNbArgs ( Kind ) ; assert ( NbArgs != - <NUM_LIT> && <STR_LIT> ) ; SmallVector < MCSymbol * , <NUM_LIT> > Args ; for ( int Idx = <NUM_LIT> ; Idx < NbArgs ; ++ Idx ) { StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT>


<s> unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( TargetMBB ) { unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( TargetMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; } TargetMBB -> setHasAddressTaken ( ) ; } if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes

+= mergeSPUpdates ( MBB , MBBI , true ) ;


<s> RegisterTarget < Triple :: lc3 > X ( The<ISA_LIT>Target , <STR_LIT>


<s> extract_insn_cached ( insn ) ; if ( recog_data . n_operands < <NUM_LIT> ) return false ; rtx reg = recog_data . operand [ <NUM_LIT> ] ; rtx mem = recog_data . operand [ <NUM_LIT> ] ; if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return false ; if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; enum non_prefixed_form non_prefixed ; machine_mode reg_mode = GET_MODE (


<s> extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; gcc_assert ( known_eq ( GET_MODE_SIZE ( GET_MODE ( mem_1 ) ) , GET_MODE_SIZE ( GET_MODE ( mem_2 ) ) ) ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( ! aarch64_mem_pair_operand ( mem_1 , GET_MODE ( mem_1 ) ) && ! aarch64_mem_pair_operand ( mem_2 , GET_MODE ( mem_2 ) ) ) return false ; if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 , true > Y ( getThe<ISA_LIT>V9Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcel , true > Z ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> ,


<s> log_return ( false , <STR_LIT> ) ; } } if ( modified_in_p ( m_ccreg , e . cstore . insn ) && ! ( reg_dead_after_insn ( m_ccreg , e . cstore . insn ) || reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; } rtx_insn * prev_insn = e . cstore . insn ; for ( std :: vector < set_of_reg > :: const_reverse_iterator i = e . cstore_reg_reg_copies . rbegin ( ) ; i != e . cstore_reg_reg_copies . rend ( ) ; ++ i ) { if ( ! reg_dead_after_insn ( i -> set_src ( ) , i -> insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( i -> insn ) ; log_return ( false , <STR_LIT> ) ; } if ( reg_used_between_p ( i -> set_src ( ) , prev_insn , i -> insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( i -> insn ) ; log_return ( false , <STR_LIT> , REGNO ( i -> set_src ( ) ) ) ; } prev_insn = i -> insn ; } rtx cstore_dst = e . cstore_reg_reg_copies . empty ( ) ? e . cstore . set_dst ( ) : e . cstore_reg_reg_copies . front ( ) . set_dst ( ) ; if ( ! reg_dead_after_insn ( cstore_dst , trace . setcc . insn ) ) { log_msg ( <STR_LIT> )


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = MI . getOperand ( <NUM_LIT> )


<s> assert ( insn . mode == MODE_16BIT ) ; baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; } MCOperand baseReg = MCOperand :: createReg ( baseRegNo ) ; mcInst . addOperand ( baseReg ) ; MCOperand segmentReg ; segmentReg = MCOperand :: createReg ( segmentRegnums [ insn . segmentOverride ] ) ; mcInst . addOperand (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; else { <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result .


<s> SDValue NotOp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; SDValue NotOp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; case <STR_LIT>


<s> case PROCESSOR_SPARCLITE86X : return <NUM_LIT> ; case PROCESSOR_NIAGARA4 : case PROCESSOR_NIAGARA7 : case PROCESSOR_M8 : return <NUM_LIT> ; case PROCESSOR_NIAGARA : case PROCESSOR_NIAGARA2 : case PROCESSOR_NIAGARA3 : default : return <NUM_LIT>


<s> rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; } return get_attr_length ( insn


<s> int Size ; if ( Desc . getSize ( ) == <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) Size = Desc . getSize ( ) ; else llvm_unreachable ( <STR_LIT> ) ; uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( isThumb ( STI ) && Size == <NUM_LIT> ) { EmitConstant ( Binary >> <NUM_LIT> , <NUM_LIT> , OS ) ; EmitConstant ( Binary & <NUM_LIT> , <NUM_LIT> , OS


<s> std :: tie ( CC , SwapArgs ) = <STR_LIT> ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; unsigned LHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; unsigned OpCmp ; LLT Ty = MRI . getType ( LHS ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT>


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode

:: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i +


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , L ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; } } Parser . Lex (


<s> OS << <STR_LIT> << InstSyncBOptToString ( getInstSyncBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_TraceSyncBarrierOpt : OS << <STR_LIT> << TraceSyncBOptToString ( getTraceSyncBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> ; if ( Memory . BaseRegNum ) OS << <STR_LIT> << RegName ( Memory . BaseRegNum ) ; if ( Memory . OffsetImm ) OS << <STR_LIT> << * Memory . OffsetImm ; if ( Memory . OffsetRegNum ) OS << <STR_LIT> << ( Memory . isNegative ? <STR_LIT> : <STR_LIT> ) << RegName ( Memory . OffsetRegNum ) ; if ( Memory . ShiftType != <STR_LIT> ) { OS << <STR_LIT> << <STR_LIT> ( Memory . ShiftType ) ; OS << <STR_LIT> << Memory . ShiftImm ; } if ( Memory . Alignment ) OS << <STR_LIT> << Memory . Alignment ; OS << <STR_LIT> ; break ; case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << RegName ( PostIdxReg . RegNum ) ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case k_Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegName ( RegShiftedReg . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegName ( RegShiftedReg . ShiftReg ) << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegName ( RegShiftedImm . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_ConstantPoolImmediate : OS << <STR_LIT> << * getConstantPoolImm ( ) ; break ; case k_BitfieldDescriptor


<s> return ( int32x4_t ) __builtin_aarch64_ashlv4si ( __a ,


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isDoubleTy ( ) ) { const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT>


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable (


<s> rtx reg1 , reg2 ; reg1 = XEXP ( XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; reg2 = XEXP ( XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; pattern = ( sibcall_p ? gen_sibcall_value_multiple_internal ( reg1 , addr , args_size , reg2 ) : gen_call_value_multiple_internal ( reg1 , addr , args_size , reg2 ) ) ; } else pattern = ( sibcall_p ? gen_sibcall_value_internal ( result , addr , args_size ) : gen_call_value_internal ( result , addr , args_size ) ) ; insn = emit_call_insn ( pattern


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; auto mi = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; addFrameReference ( mi ,


<s> static inline void maybe_add_dllimport (


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) , OS


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == <NUM_LIT> && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != <NUM_LIT> && info -> first_gp_reg_save != <NUM_LIT> ) ) return emit_insn (


<s> SDValue Op = ReduceOp . getOperand ( <NUM_LIT> ) ; EVT OpVT = Op . getValueType ( ) ; EVT VT = ReduceOp . getValueType ( ) ; if ( ! OpVT . isScalableVector ( ) || OpVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Pg = getPredicateForVector ( DAG , DL , OpVT ) ; switch ( ReduceOp . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( isAllActivePredicate ( DAG , Pg ) ) return getPTest ( DAG , VT , Op , Op , <STR_LIT> ) ; else return getPTest ( DAG , VT , Pg , Op , <STR_LIT> ) ; case <STR_LIT> : { Op = DAG . getNode ( <STR_LIT> , DL , OpVT , Op , Pg ) ; return getPTest ( DAG , VT ,


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOTOFF_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOTOFF_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PLT_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PLT_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_LO32 )

. Case ( <STR_LIT> , VK_<ISA_LIT>_TPOFF_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPOFF_LO32 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> static __inline __m64 _mm_set_pi16 ( short __w3 , short __w2 , short __w1 , short __w0 ) { unsigned int __i1 = ( unsigned short ) __w3 <<


<s> if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return false ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to

) > GET_MODE_SIZE ( from ) ) return false ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU


<s> __vc16 = ( __vector signed char ) ( __vector unsigned long long ) { __A , __A } ; __vs8 = vec_vupkhsb ( __vc16 ) ; __vi4 = vec_vupkhsh ( __vs8 ) ; __vf1 = ( __vector float )


<s> uint64_t Control = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; static const unsigned GPRControlBit [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Control |= GPRControlBit [ <NUM_LIT> ] ; if ( TFI -> hasFP ( MF ) ) Control |= GPRControlBit [ <NUM_LIT> ] ; MI . getOperand ( <NUM_LIT> ) . setImm ( Control ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ; MI . addOperand ( MachineOperand :: CreateReg (


<s> return DAG . getStore ( Chain , DL , DAG . getConstant ( StoreVal , DL , <STR_LIT> ( Size * <NUM_LIT> )

) , Dst , DstPtrInfo , false , false , Align ) ;


<s> } } const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , std :: next (


<s> return ( ! instance . type_suffix ( <NUM_LIT> ) . integer_p ? m_unspec_for_fp : instance .


<s> MCFragment * findAssociatedFragment ( ) const override


<s> AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> return ( __m128h ) __builtin_ia32_vfcmaddcph128_mask3 ( ( __v8hf ) __A , ( __v8hf )


<s> return IREmitter :: visit ( N ) ; } if ( VisitMap . find ( N ) != VisitMap . end ( ) ) { return VisitMap [ N


<s> static SDValue LowerStore ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { StoreSDNode * St = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDLoc dl ( St ) ; SDValue StoredVal = St -> getValue ( ) ; assert ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && StoredVal . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal

, DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , nullptr ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . second ) return R ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT


<s> static const char * rs6000_get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return


<s> } SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; } if ( Model == TLSModel :: LocalDynamic ) { if ( Subtarget . isUsingPCRelativeCalls ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue MatPCRel = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , MatPCRel , TGA ) ; } SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; SDValue DtvOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TLSAddr , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DtvOffsetHi , TGA ) ; } llvm_unreachable (


<s> ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; return


<s> bool shouldExpandReduction ( const IntrinsicInst * II


<s> dl = gen_rtx_REG ( nmode , r + HARD_REGNO_NREGS ( r , nmode ) ) ; } else { dh = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ; dl = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , GET_MODE_SIZE ( nmode ) ) ; } break ; case MEM : switch ( GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) { case POST_INC : case POST_DEC : gcc_unreachable ( ) ; default : dl = operand_subword ( operands [ <NUM_LIT> ] , GET_MODE_SIZE ( nmode ) / UNITS_PER_WORD , <NUM_LIT> , omode ) ; dh = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , omode ) ; } break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case REG : if ( ! IS_PSEUDO_P ( operands [ <NUM_LIT> ] ) ) { int r = REGNO ( operands [ <NUM_LIT> ] ) ; sh = gen_rtx_REG ( nmode , r ) ; sl = gen_rtx_REG ( nmode , r + HARD_REGNO_NREGS ( r , nmode ) ) ; } else { sh = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ; sl = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , GET_MODE_SIZE ( nmode ) ) ; } break ; case CONST_DOUBLE : if ( operands [ <NUM_LIT> ] == const0_rtx ) sh = sl = const0_rtx ; else split_double ( operands [ <NUM_LIT> ] , & sh , & sl ) ; break ; case CONST_INT : if ( operands [ <NUM_LIT> ] == const0_rtx ) sh = sl = const0_rtx ; else { int vl , vh ; switch ( nmode ) { default : gcc_unreachable ( ) ; } sl = GEN_INT ( vl ) ; sh = GEN_INT ( vh ) ; } break ; case SUBREG : sl = gen_rtx_SUBREG ( nmode , SUBREG_REG ( operands [ <NUM_LIT> ] ) , SUBREG_BYTE ( operands [ <NUM_LIT> ] ) + GET_MODE_SIZE ( nmode ) ) ; sh = gen_rtx_SUBREG ( nmode , SUBREG_REG ( operands [ <NUM_LIT> ] ) , SUBREG_BYTE ( operands [ <NUM_LIT> ] ) ) ; break ; case MEM : switch ( GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) { case POST_DEC : case POST_INC : gcc_unreachable ( ) ; break ; default : sl = operand_subword ( operands [ <NUM_LIT> ] , GET_MODE_SIZE ( nmode ) / UNITS_PER_WORD , <NUM_LIT> , omode ) ; sh = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , omode ) ; if ( GET_CODE ( dl ) == REG && true_regnum ( dl ) == true_regnum ( XEXP ( XEXP ( sl , <NUM_LIT> ) , <NUM_LIT> ) ) )


<s> Skip = <NUM_LIT> ; ++ MII ; continue ; } unsigned Domain = MCID . TSFlags & <STR_LIT> ; if ( Domain == <STR_LIT> ) { if ( ++ Skip == <NUM_LIT> ) pushStack ( <NUM_LIT> ) ; } else { Skip = <NUM_LIT> ; unsigned MulOpc , AddSubOpc ; bool NegAcc , HasLane ; if ( ! TII -> isFpMLxInstruction ( MCID . getOpcode ( ) , MulOpc , AddSubOpc , NegAcc , HasLane ) || ! FindMLxHazard ( MI ) ) pushStack ( MI ) ; else { ExpandFPMLxInstruction ( MBB , MI , MulOpc , AddSubOpc ,


<s> Module & M = const_cast < Module & > ( * MMI -> getModule ( ) ) ; if ( ! MF . getName ( ) . startswith ( ThunkNamePrefix ) ) { if ( InsertedThunks ) return false ; if ( ( ! STI -> useRetpolineIndirectCalls ( ) && ! STI -> useRetpolineIndirectBranches ( ) ) || STI -> useRetpolineExternalThunk ( ) ) return false ; if ( Is64Bit ) createThunkFunction ( M , R11ThunkName ) ; else for ( StringRef Name : { EAXThunkName , ECXThunkName , EDXThunkName , EDIThunkName } ) createThunkFunction ( M ,


<s> return ( R0 . Offset > R1 . Offset ) ? <NUM_LIT> : ( (

R0 . Offset == R1 . Offset ) ? <NUM_LIT> : - <NUM_LIT> ) ;


<s> void EmitInstrWithMacroNoAT ( const MachineInstr * MI ) ; private : bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective (


<s> if ( Subtarget . isGP64bit ( ) ) return lowerFCOPYSIGN64 ( Op , DAG , Subtarget .


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) return <NUM_LIT> ; return RC


<s> bool isMOVNMovAlias ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; for ( int MOVZShift = <NUM_LIT> ; MOVZShift <= <NUM_LIT> ; MOVZShift += <NUM_LIT> ) if ( ( Value & ~ ( <NUM_LIT> << MOVZShift ) )


<s> for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << * MI ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else if ( isMla ( MI ) ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AccumReg , TRI ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; ActiveChains [ AccumReg ] -> add ( MI , Idx , getColor ( DestReg ) ) ; if ( DestReg != AccumReg ) { ActiveChains [ DestReg ] = ActiveChains [ AccumReg ] ; ActiveChains . erase ( AccumReg ) ; } return ; } DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else { for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( )


<s> static inline unsigned getT1tRm ( uint32_t insn ) { return slice ( insn ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction &


<s> unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , nullptr , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , DestAM ) ; assert ( RV && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; DestAM . Disp +=


<s> Dest = & MI . getOperand ( <NUM_LIT> ) ; } else { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand (


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( Subtarget . has<ISA_LIT>64 ( ) ) return <STR_LIT> ; return