<s> static <ISA_LIT>Operand * CreateShiftedRegister ( <STR_LIT> ShTy , unsigned SrcReg , unsigned ShiftReg , unsigned ShiftImm , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftedRegister ) ; Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg .


<s> default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return OptimizeConditionalInDecrement ( N , DAG ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case


<s> if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT>


<s> static DecodeStatus decodeRegisterClass ( MCInst & Inst , uint64_t RegNo , const unsigned ( & Regs )


<s> default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidUImm8 : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidUImm16 : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidFloatRoundMode : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; case Match_InvalidWyde : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; case Match_InvalidBranchImm16 : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> )


<s> HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ; UseNaClTrap = false ; UnsafeFPMath = false


<s> EmitBranchToAt ( ( intptr_t ) Old , ( intptr_t ) New , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( Old , <NUM_LIT>


<s> void <ISA_LIT>FrameLowering :: emitCatchRetReturnValue ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineInstr * CatchRet ) const { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MBB . getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; const DebugLoc & DL = CatchRet -> getDebugLoc ( ) ; MachineBasicBlock * CatchRetTarget = CatchRet -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( CatchRetTarget ) . addReg ( <NUM_LIT> ) ; } else


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op


<s> SDValue <ISA_LIT>TargetLowering :: BuildFILD ( SDValue Op , MVT SrcVT , SDValue Chain , SDValue StackSlot , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDVTList Tys ; bool useSSE = isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ; if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( StackSlot ) ; Ops . push_back ( DAG . getValueType ( SrcVT ) ) ; SDValue Result = DAG . getNode ( useSSE ? <STR_LIT> : <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; Tys = DAG . getVTList ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Result ) ; Ops . push_back ( StackSlot ) ; Ops . push_back ( DAG . getValueType ( Op . getValueType ( ) ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops


<s> if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt .


<s> <ISA_LIT>BankConflictHazardRecognizer :: <ISA_LIT>BankConflictHazardRecognizer ( const ScheduleDAG * DAG , int64_t CPUBankMask , bool CPUAssumeITCMConflict ) : MF ( DAG -> MF ) , DL ( DAG -> MF . getDataLayout ( ) ) , DataMask ( DataBankMask . getNumOccurrences ( ) ? int64_t ( DataBankMask

) : CPUBankMask ) , AssumeITCMBankConflict ( AssumeITCMConflict . getNumOccurrences ( ) ? AssumeITCMConflict : CPUAssumeITCMConflict ) {


<s> unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode (


<s> } JCE . emitWordLE ( ( intptr_t ) Ptr ) ; if ( ! sys :: Memory :: setRangeExecutable ( ( void * ) Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } void * PtrAddr = JCE


<s> Value * <ISA_LIT>IREmitter :: visitTLSBASEADDR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( Kind != k_Register || Reg . Kind != RegKind :: Scalar ) return DiagnosticPredicateTy :: NoMatch ; if ( isGPR64 < RegClassID > ( ) && getShiftExtendType ( ) == <STR_LIT> && getShiftExtendAmount ( ) == Log2_32 ( ExtWidth / <NUM_LIT> ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy ::


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( const GlobalVariable * GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( false ) ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isTargetNaCl64 ( ) ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt )


<s> if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ; if ( ! x ) return


<s> AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> else if ( strncmp ( str , DLL_EXPORT_PREFIX , strlen ( DLL_EXPORT_PREFIX ) ) == <NUM_LIT> ) str += strlen ( DLL_EXPORT_PREFIX ) ; if ( * str == '*' ) str +=


<s> if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList ; } else { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList


<s> if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent (


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) ,


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _serialize ( void ) { __builtin_ia32_serialize (


<s> unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII .


<s> if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = llvm :: lower_bound ( <ISA_LIT>16IntrinsicHelper , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; } return SDValue ( )


<s> return ( getSTI ( ) . getFeatureBits (


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( pru_ctable ) ; i ++ ) { if ( pru_ctable [ i ] . valid && IN_RANGE ( caddr , pru_ctable [ i ] . base , pru_ctable [ i ] . base + <NUM_LIT> )


<s> codes [ i ] . code = PLUS ; codes [ i ] . value = CONST_LOW_PART ( value ) ; } else { i = mips_build_integer ( codes , high ) ; codes [ i ] . code =


<s> break ; } } } } if ( ! Done && MatchAddress ( Addr , AM , false ) ) return false ; DOUT << <STR_LIT> ; DEBUG ( AM . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType == <STR_LIT> ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg

= CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> } else { if ( LHS . getOpcode ( ) != <STR_LIT> ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) CommuteVectorShuffleMask ( RMask , NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts ||

RIdx >= ( int ) NumElts ) ) ) continue ;


<s> bool useRegsForByval ( ) const { return CallConv != CallingConv ::


<s> return false ; } ; if ( ! std :: all_of ( Gep -> idx_begin ( ) , Gep -> idx_end ( ) , AllInvariantOrIV ) ) return false ; PointerOpnd = Gep -> getPointerOperand ( ) ; auto * PointerOpndI = dyn_cast < Instruction > ( PointerOpnd ) ; if ( PointerOpndI && PointerOpndI -> getParent ( ) != EntryBB ) if ( ( BC = dyn_cast < BitCastInst > ( PointerOpndI ) ) ) PointerOpnd = BC -> getOperand ( <NUM_LIT> ) ; PointerOpndI = dyn_cast < Instruction


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; if ( parseEOL ( ) ) return true ; getTargetStreamer ( ) . emitDirectiveVariantPCS ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; return


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>EmitLibcall ( const Instruction * I , RTLIB :: Libcall Call ) { CallingConv :: ID CC = TLI . getLibcallCallingConv ( Call ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , false ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg


<s> if ( ! IsUnscaled && ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) ) return false ; if ( IsUnscaled ) { int ElemOffset = Offset / OffsetStride ; if ( ElemOffset > <NUM_LIT> || ElemOffset < - <NUM_LIT> )


<s> void <ISA_LIT>TargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , <NUM_LIT> , <NUM_LIT> , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ <STR_LIT> ]


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO .

getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> bool isMultiStoresCheaperThanBitsMerge ( EVT LTy , EVT HTy ) const override { if ( ( LTy . isFloatingPoint ( ) && HTy . isInteger ( ) ) || ( LTy . isInteger ( ) && HTy . isFloatingPoint ( ) ) ) return true ; return


<s> tocrel = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol , tocreg ) , UNSPEC_TOCREL ) ; if ( TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ( ) ) return tocrel ; hi = gen_rtx_HIGH ( Pmode , copy_rtx ( tocrel ) ) ; if ( largetoc_reg != NULL ) { emit_move_insn ( largetoc_reg , hi


<s> return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv ::


<s> while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear (


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass


<s> SDLoc dl ( Op ) ; int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT>


<s> return ( hard_regno_mode_classes [ regno ] & sparc_mode_class [ mode ]


<s> static rtx ix86_expand_sse_pcmpestr ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg3 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg4 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx scratch0 , scratch1 ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx op3 = expand_normal ( arg3 ) ; rtx op4 = expand_normal ( arg4 ) ; machine_mode tmode0 , tmode1 , modev2 , modei3 , modev4 , modei5 , modeimm ; tmode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; tmode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modev2 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modei3 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modev4 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modei5 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modeimm = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( modev2 ) ) op0 = safe_vector_operand ( op0 , modev2 ) ; if ( VECTOR_MODE_P ( modev4 ) ) op2 = safe_vector_operand ( op2 , modev4 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , modev2 ) ) op0 = copy_to_mode_reg ( modev2 , op0 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , modei3 ) ) op1 = copy_to_mode_reg ( modei3 , op1 ) ; if ( ( optimize && ! register_operand ( op2 , modev4 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op2 , modev4 ) ) op2 = copy_to_mode_reg ( modev4 , op2 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op3 , modei5 ) ) op3 = copy_to_mode_reg ( modei5 , op3 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op4 , modeimm ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( d -> code == IX86_BUILTIN_PCMPESTRI128


<s> int <ISA_LIT>RegisterInfo :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - TFI . getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( )

) Offset -= TFI . getOffsetOfLocalArea ( ) ;


<s> case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op


<s> void EmitThumbFunc ( MCSymbol * Func ) override { getAssembler ( ) .


<s> static void getExclusiveOperation ( unsigned Size , AtomicOrdering Ord , bool isThumb2 , unsigned & LdrOpc , unsigned & StrOpc ) { static const unsigned LoadBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned LoadAcqs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreRels [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> ,


<s> RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Val = getv64i1Argument ( VA , RVLocs [ ++ I ] , Chain , DAG , dl , Subtarget , & InFlag ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && ( VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) ) { if ( VA . getValVT ( ) . isVector ( ) && ( ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) ) ) { Val = lowerRegToMasks ( Val , VA . getValVT ( ) , VA . getLocVT ( ) , dl , DAG ) ; } else Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; } InVals . push_back ( Val ) ; } return


<s> if ( IsInefficientBase && SSDstR == BaseR && ! IsScale1 ) return nullptr ; if ( LEAOpcode == <STR_LIT> && IsInefficientBase && ( IsInefficientIndex || ! IsScale1 ) ) return nullptr ; const DebugLoc DL = MI . getDebugLoc ( ) ; const MCInstrDesc & ADDrr = TII -> get ( getADDrrFromLEA ( LEAOpcode ) ) ; const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( LEAOpcode , Offset ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( IsScale1 && ( DstR == BaseR || DstR == IndexR ) ) { const MachineOperand & Src = DstR == BaseR ? Index : Base ; MachineInstr * NewMI = BuildMI ( * MFI , MI , DL , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( * MFI , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } return NewMI ; } if ( ! IsInefficientBase || ( ! IsInefficientIndex && IsScale1 ) ) { MachineInstr * NewMI = BuildMI ( * MFI , MI , DL , TII -> get ( LEAOpcode ) ) . add ( Dst ) . add ( IsInefficientBase ? Index : Base ) . add ( Scale ) . add ( IsInefficientBase ? Base : Index ) . addImm ( <NUM_LIT> ) . add ( Segment ) ; DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( * MFI , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } return NewMI ; } assert ( SSDstR != BaseR


<s> memset ( pcum , <NUM_LIT> , sizeof ( * pcum ) ) ; if ( stdarg_p ( fntype ) ) pcum -> is_stdarg =


<s> OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( ATOMIC_CMP_SWAP ) ; OPCODE ( ATOMIC_LOAD_128 ) ; OPCODE ( ATOMIC_STORE_128 ) ; OPCODE ( ATOMIC_CMP_SWAP_128 ) ; OPCODE ( LRV ) ; OPCODE ( STRV ) ; OPCODE ( VLER ) ; OPCODE ( VSTER


<s> REAL_VALUE_TYPE rv ; real_from_string ( & rv , <STR_LIT> ) ; ia64_dconst_0_5_rtx = const_double_from_real_value ( rv , DFmode ) ; } return ia64_dconst_0_5_rtx


<s> AFI . addLOHDirective ( MCLOH_AdrpAdrp , { & MI , Info . LastADRP } ) ; ++ NumADRPSimpleCandidate ; } if ( Info . IsCandidate ) { switch ( Info . Type ) { case MCLOH_AdrpAdd : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAdd , { & MI , Info . MI0 } ) ; ++ NumADRSimpleCandidate ; break ; case MCLOH_AdrpLdr : if ( supportLoadFromLiteral ( * Info . MI0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdr , { & MI , Info . MI0 } ) ; ++ NumADRPToLDR ; } break ; case MCLOH_AdrpAddLdr : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; case MCLOH_AdrpAddStr : if ( Info . MI1 != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToSTR ; break ; case MCLOH_AdrpLdrGot : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGot , { & MI , Info . MI0 } ) ; break ; case MCLOH_AdrpAdrp : llvm_unreachable ( <STR_LIT> ) ; } } handleClobber ( Info ) ; Info . LastADRP


<s> switch ( Type ) { case PPR : return <NUM_LIT> ; case GPR : case FPR64 : return <NUM_LIT>


<s> bool <ISA_LIT>TTIImpl :: expandMemCmp ( Instruction * I , unsigned & MaxLoadSize ) { MaxLoadSize = ST -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; return


<s> if ( ! VT . isSimple ( ) || ! VT . isInteger ( ) || VT . isVector ( ) ) return false ; unsigned VTSize = VT . getSimpleVT ( ) .


<s> for ( unsigned s = <NUM_LIT> ; s < NumLanes ; ++ s ) { unsigned Start = s * NumLaneElts + NumLaneElts / <NUM_LIT> ; unsigned End = s * NumLaneElts + NumLaneElts ; for ( unsigned i = Start ; i != End ; ++ i ) { ShuffleMask . push_back ( i


<s> static bool isFrameStoreOpcode ( int Opcode ) { switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const MachineConstantPoolEntry & MCPE = ( * MCPEs ) [ CPIndex ] ; JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ; GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { assert ( ! ACPV -> isStub ( ) && <STR_LIT> ) ; if ( ACPV -> isNonLazyPointer ( ) ) MCE . addRelocation ( MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , <STR_LIT> , GV , ( intptr_t ) ACPV , false ) ) ; else emitGlobalAddress ( GV , <STR_LIT> , ACPV -> isStub ( ) || isa < Function > ( GV ) , ( intptr_t ) ACPV ) ; } else { assert ( ! ACPV -> isNonLazyPointer ( ) && <STR_LIT> ) ; emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue (


<s> virtual const char * getPassName ( ) const { return


__v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> AU . addPreserved < MachineModuleInfo >


<s> if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL ; unsigned V0 , V1 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; RC = ( ABI . IsN64 ( ) ) ? & <STR_LIT> : & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; if ( ABI . IsN64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( ! MF . getTarget ( ) . isPositionIndependent


<s> static bool CC_<ISA_LIT>NoMoreRegs ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { for ( unsigned i = <NUM_LIT> ; i < NumArgRegs ; ++ i ) State . AllocateReg ( <ISA_LIT>ArgRegs [ i ] ) ; return false


<s> static rtx mips_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno , argno ; opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) mips_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return mips_expand_builtin_insn ( icode , opno , ops , has_target_p


<s> AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size ) { CFAOffset -= adjustedGPRCS1Size ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; int FI = I -> getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . isTargetMachO ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI -> getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; break ; } } if ( HasFP ) { FramePtrOffsetInBlock += MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size + ArgRegsSaveSize ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( <STR_LIT> ) . addImm ( FramePtrOffsetInBlock / <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( FramePtrOffsetInBlock ) { CFAOffset += FramePtrOffsetInBlock ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , MRI -> getDwarfRegNum ( FramePtr , true ) , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } else { unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( FramePtr , true ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ; if ( !


<s> vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( count - <NUM_LIT> )


<s> } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { EVT NewVT = Index . getValueType ( ) . changeVectorElementType ( <STR_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Index . getOpcode ( ) == <STR_LIT> && Index . getValueType ( ) . getVectorElementType ( ) == PtrVT && isa < ConstantSDNode > ( Scale ) ) { uint64_t ScaleAmt = cast < ConstantSDNode > ( Scale ) -> getZExtValue ( ) ; if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Index . getOperand ( <NUM_LIT> ) ) ) { BitVector UndefElts ; if ( ConstantSDNode * C = BV -> getConstantSplatNode ( & UndefElts ) ) { if ( UndefElts . none ( ) ) { APInt Adder = C -> getAPIntValue ( ) * ScaleAmt ; Base = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , DAG . getConstant ( Adder , DL , PtrVT ) ) ; Index = Index . getOperand ( <NUM_LIT> ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( BV -> isConstant ( ) && isa < ConstantSDNode > ( Base ) && isOneConstant ( Scale ) ) { SDValue Splat = DAG . getSplatBuildVector ( Index . getValueType ( ) , DL , Base ) ; Splat = DAG . getNode ( <STR_LIT> , DL , Index . getValueType ( ) , Index . getOperand ( <NUM_LIT> ) , Splat ) ; Index = DAG . getNode ( <STR_LIT> , DL , Index . getValueType ( ) , Index . getOperand ( <NUM_LIT> ) , Splat ) ; Base = DAG . getConstant ( <NUM_LIT> , DL


<s> bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) MRI . setPhysRegUsed ( <STR_LIT> [ I ] ) ; if ( HasFP ) MRI . setPhysRegUsed ( <STR_LIT> ) ; if ( MFFrame -> hasCalls ( ) )


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printOperand ( MI , OpNo , O ) ; return false


<s> void addSysCROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; bool IsPic = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> ,


<s> rtx_insn * mips_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1


<s> if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && ( NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION || NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) ) insn = next ; else break ; emit_insn_after ( gen_nops ( const1_rtx )


<s> inline static uint64_t getFpImmVal ( const ConstantFPSDNode * N ) { const APInt & Imm = N -> getValueAPF ( ) . bitcastToAPInt ( ) ; uint64_t Val = Imm . getZExtValue (


<s> for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return i


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR64DecoderTable [ RegNo ]


<s> if ( from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM ) return true ; if ( from_reg == FRAME_POINTER_REGNUM && to_reg

== HARD_FRAME_POINTER_REGNUM ) return true ;


<s> int rv = MEP_SAVES_NO ; if ( cfun -> machine -> reg_save_slot [ r ] ) rv = MEP_SAVES_YES ; else if ( r == LP_REGNO && ( profile_arc_flag > <NUM_LIT> || profile_flag > <NUM_LIT> ) ) rv = MEP_SAVES_YES ; else if ( r == FRAME_POINTER_REGNUM && frame_pointer_needed ) rv = MEP_SAVES_YES ; else if ( ( ! call_used_regs [ r ] || r == LP_REGNO ) && df_regs_ever_live_p ( r ) ) rv = MEP_SAVES_YES ; else if ( crtl -> calls_eh_return && ( r == <NUM_LIT> || r == <NUM_LIT> ) ) rv = MEP_SAVES_YES ; else if ( mep_interrupt_saved_reg ( r ) ) rv = MEP_SAVES_YES ; cfun -> machine -> reg_saved [ r ]


<s> switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file ) ; } else assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT


<s> if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: BigEndian && M . getPointerSize ( ) == Module :: Pointer64 )


<s> int s0 = mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' ; int s1 = mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' ; int c0 = mep_nongeneral_reg ( operands [ <NUM_LIT> ] ) ; int c1 = mep_nongeneral_reg ( operands [ <NUM_LIT> ] ) ; int which = ( s0 ? <NUM_LIT> : <NUM_LIT> ) + ( c0 ? <NUM_LIT> : <NUM_LIT> ) + ( s1 ? <NUM_LIT> : <NUM_LIT> ) + ( c1 ? <NUM_LIT> : <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , mode_name [ mode ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; switch ( which ) { case <NUM_LIT> : case <NUM_LIT> : emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O ,


<s> } else if ( SPE_VECTOR_MODE ( mode ) || ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) { if ( mode == DImode ) return x ; if ( GET_CODE ( x ) == PLUS ) { rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; rtx y ; op1 = force_reg ( Pmode , op1 ) ; if ( GET_CODE ( op2 ) != REG && ( GET_CODE ( op2 ) != CONST_INT || ! SPE_CONST_OFFSET_OK ( INTVAL ( op2 ) ) || ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ! SPE_CONST_OFFSET_OK ( INTVAL ( op2 ) + <NUM_LIT> ) ) ) ) op2 = force_reg ( Pmode , op2 ) ; y = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == DDmode ) && REG_P ( op2 ) ) return force_reg ( Pmode , y ) ; else return y ; } return force_reg ( Pmode , x ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_WIDE_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg , x ) ) ; else emit_insn ( gen_macho_high ( reg , x ) ) ; return gen_rtx_LO_SUM ( Pmode , reg , x ) ; } else if ( TARGET_TOC && GET_CODE ( x ) == SYMBOL_REF && constant_pool_expr_p ( x ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( x ) , Pmode ) ) return create_TOC_reference ( x , NULL_RTX ) ; else return


<s> return ( __m512i ) __builtin_ia32_expandloadqi512_mask ( ( const __v64qi * ) __C , ( __v64qi )


<s> if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ; if ( HasSecRelSymbolRef ( Bin -> getLHS ( ) ) || HasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2 ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_1 ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: Create ( CurByte , Expr ,


<s> <ISA_LIT>_64ATTAsmParser ( const Target & T , MCAsmParser & _Parser , TargetMachine & TM ) : <ISA_LIT>ATTAsmParser ( T , _Parser


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool hasFuseLiterals ( ) const { return


<s> if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) ++ OpIdx ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs =


<s> fputs ( COMMON_ASM_OP , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED , size , align2 ) ; fputs ( rs6000_xcoff_visibility ( decl ) , stream


<s> ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank

( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> auto TRC = TII -> getRegClass ( TII -> get ( LoadInst -> getOpcode ( ) ) , <NUM_LIT> , TRI , * LoadInst -> getParent ( ) -> getParent ( ) ) ; return TRI -> getRegSizeInBits ( * TRC )


<s> MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = fastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else


<s> unsigned char TargetFlag ; unsigned Opcode ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { TargetFlag = <STR_LIT> ; Opcode = <STR_LIT> ; } else { return LowerToTLSExecCall ( GA , DAG , PtrVT , model , true ) ; } if ( NaClDontBreakABI


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo &

MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {


<s> short s [ <NUM_LIT> ] ; } x ; x . s [


<s> const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; <STR_LIT> E = IsLittleEndian ? <STR_LIT> : <STR_LIT> ; switch ( Size ) { case <NUM_LIT> : break ; case <NUM_LIT>


<s> return __builtin_mve_vmulq_sv8hi ( __a ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getTheARM64Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > W ( getTheARM64_32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > V ( getThe<ISA_LIT>_32Target


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; if ( HasSSE2 && VT == <STR_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) , DAG . getNode

( <STR_LIT> , dl , <STR_LIT> , V2 ) , DAG ) ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsr_u64 ( unsigned long long __X ) { return __blsr_u64 ( __X )


<s> static inline bool hasImm ( uint64_t TSFlags ) { return ( TSFlags & <STR_LIT> ) !=


<s> MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , <NUM_LIT> > WorkList ( <NUM_LIT> , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode


? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ;


<s> unsigned InBits = UnpackFromEltSize * <NUM_LIT> ; EVT InVT = <STR_LIT> ( <STR_LIT> ( InBits ) , <STR_LIT> / InBits ) ; SDValue PackedOp = DAG . getNode ( <STR_LIT> , DL , InVT , Op ) ; unsigned OutBits = InBits * <NUM_LIT> ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( OutBits ) ,


<s> } assert ( ( ZeroMask | UndefMask | LoadMask ) . count ( ) == NumElems && <STR_LIT> ) ; if ( UndefMask . count ( ) == NumElems ) return DAG . getUNDEF ( VT ) ; if ( ( ZeroMask | UndefMask ) . count ( ) == NumElems ) return VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; int FirstLoadedElt = LoadMask . find_first ( ) ; SDValue EltBase = PeekThroughBitcast ( Elts [ FirstLoadedElt ] ) ; LoadSDNode * LDBase = cast < LoadSDNode > ( EltBase ) ; EVT LDBaseVT = EltBase . getValueType ( ) ; bool IsConsecutiveLoad = true ; for ( int i = FirstLoadedElt + <NUM_LIT> ; i <= LastLoadedElt ; ++ i ) { if ( LoadMask [ i ] ) { SDValue Elt = PeekThroughBitcast ( Elts [ i ] ) ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , Elt . getValueType ( ) . getStoreSizeInBits ( ) / <NUM_LIT> , i - FirstLoadedElt ) ) { IsConsecutiveLoad = false ; break ; } } else if ( ZeroMask [ i ] ) { IsConsecutiveLoad = false ; break ; } } if ( IsConsecutiveLoad && FirstLoadedElt == <NUM_LIT> && LastLoadedElt == ( int ) ( NumElems - <NUM_LIT> ) && ZeroMask . none ( ) ) { assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDValue NewLd = SDValue ( ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT>


<s> else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) Mask [ i ] = SM_SentinelZero ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) Mask [ i ] = SM_SentinelUndef ; else if ( <STR_LIT> ( Op ) ) Mask [ i ] = SM_SentinelZero ; continue ; } if ( ( V . getNumOperands ( ) % Size ) == <NUM_LIT> ) { int Scale = V -> getNumOperands ( ) / Size ; bool AllUndef = true ; bool AllZero = true ; for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) { SDValue Op = V . getOperand ( ( M * Scale ) + j ) ; AllUndef &= Op . isUndef ( ) ; AllZero &= <STR_LIT> (


<s> uint32_t rot_imm = ( imm >> rot ) | ( imm << ( ( <NUM_LIT> - rot ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( rot_imm ) ) ; return MCDisassembler


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TT , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>AsmBackendWinCOFF ( T , TT ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new <ISA_LIT>AsmBackendNaClELF ( T , TT ,


<s> bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned EndSubReg = <STR_LIT> . contains ( DestReg , SrcReg ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <STR_LIT> , e = EndSubReg + <NUM_LIT> ; i != e ;


<s> } else { if ( ( xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx |= ~ ( HOST_WIDE_INT ) <NUM_LIT> ; else if ( ( xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx |= ~ ( HOST_WIDE_INT ) <NUM_LIT> ; l = exact_log2 ( ~ xx ) ; } if ( l == - <NUM_LIT> ) output_operand_lossage ( <STR_LIT> ) ; fprintf ( file , IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC , l ) ; return ; } case 'C' : if ( GET_CODE ( x ) == SYMBOL_REF ) assemble_name ( file , XSTR ( x , <NUM_LIT> ) ) ; else if ( GET_CODE ( x ) == LABEL_REF ) output_asm_label ( x ) ; else xstormy16_print_operand_address ( file , x ) ; return ; case 'o' : case 'O' : { HOST_WIDE_INT xx = <NUM_LIT> ; if ( GET_CODE ( x ) == CONST_INT ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; if ( code == 'O' ) xx = - xx ; fprintf ( file , IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC , xx - <NUM_LIT> ) ; return ; } case 'b' : { HOST_WIDE_INT xx = <NUM_LIT> ; HOST_WIDE_INT l ; if ( GET_CODE ( x ) == CONST_INT ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; l = <NUM_LIT> - xx ; fputs ( IMMEDIATE_PREFIX , file ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , l ) ; return ; } case <NUM_LIT> : break ; default : output_operand_lossage ( <STR_LIT> ) ; return ; } switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x )


<s> SDLoc dl ( Op ) ; if ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) if ( SDValue SatValue = LowerSaturatingConditional ( Op , DAG ) ) return SatValue ; SDValue LowerSatConstant ; SDValue SatValue ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( Opcode


<s> Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc


<s> else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( i


<s> return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment . value ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && MemVT . getVectorElementCount ( ) . Min % <NUM_LIT> == <NUM_LIT> && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( MemVT . getVectorElementCount ( ) . Min / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return


<s> static DecodeStatus DecodeBranchTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> static bool mt_interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; a = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return &


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction &


<s> dbgs ( ) << <STR_LIT> ; if ( Base_Reg . getNode ( ) ) Base_Reg . getNode ( ) -> dump ( DAG ) ; else dbgs ( ) << <STR_LIT> ; if ( BaseType == FrameIndexBase ) dbgs ( ) << <STR_LIT> << Base_FrameIndex << '\n' ; dbgs ( ) << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) ) IndexReg . getNode ( ) -> dump ( DAG ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump (


<s> BitCast = B . CreatePointerBitCastOrAddrSpaceCast ( AO . ValueSrc . Base , CapPtrTy ) ; if ( Size -> getType ( ) != SizeTy ) Size = B . CreateZExt ( Size , SizeTy ) ; CallInst * SetLength = B . CreateCall ( SetLengthFn , { BitCast , Size } ) ; if ( cheri :: ShouldCollectCSetBoundsStats ) { Value * AlignmentSource = BitCast ; Instruction * DebugInst = dyn_cast < Instruction > ( AlignmentSource ) ; if ( ! DebugInst ) DebugInst = InsertPt ; cheri :: addSetBoundsStats ( Align ( getKnownAlignment ( AlignmentSource , * TD ) ) , Size , getPassName ( ) , AO . Src , <STR_LIT> , cheri :: inferSourceLocation ( DebugInst ) ) ; } if ( BitCast == AO . ValueSrc . Base ) BitCast = SetLength ; Value * Result


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createLower16 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createUpper16 ( Expr , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , OutContext ) , OutContext ) ; return MCOperand :: createExpr ( Expr


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>32R3 ( )


<s> MBB . erase ( NI ) ; MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes += NI -> getOperand


<s> static int func ( rtx mem ATTRIBUTE_UNUSED , rtx op ATTRIBUTE_UNUSED , rtx dest , rtx src ATTRIBUTE_UNUSED , rtx srcoff


<s> case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO ,


<s> void <ISA_LIT>AsmPrinter :: printPCLabel ( const MachineInstr *


<s> ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; LoadSDNode * LD = NULL ; unsigned LastLoadedElt ; if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EltVT , LD , LastLoadedElt , DAG , MFI , TLI ) ) return SDValue ( ) ; if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LD -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT>


<s> MachineFunctionPass :: getAnalysisUsage ( AU )


<s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < BitSize ; ShiftVal += <NUM_LIT> ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( <NUM_LIT> ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost (


<s> assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , getScratchReg ( ) , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( StackTop == <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64


<s> MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT> ) ; SDLoc DL ( V128Reg ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , NarrowTy , V128Reg


<s> if ( N . getOpcode ( ) == <STR_LIT> ) N = N . getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ; if ( ! LD || LD -> isVolatile ( ) ) return false ; if ( LD -> getAddressingMode ( ) != <STR_LIT> ) return false ; <STR_LIT> ExtType = LD


<s> bool <ISA_LIT>TargetLowering :: needsCmpXchgNb ( Type * MemType ) const { unsigned OpWidth = MemType -> getPrimitiveSizeInBits ( ) ; if ( OpWidth == <NUM_LIT> ) return Subtarget . canUseCMPXCHG8B ( ) && ! Subtarget . is64Bit ( ) ; if ( OpWidth == <NUM_LIT> ) return Subtarget .


<s> else if ( code == RS6000_BIF_GET_TFIAR || code == RS6000_BIF_SET_TFIAR ) return TFIAR_SPR ; else if ( code == RS6000_BIF_GET_TEXASR || code == RS6000_BIF_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == RS6000_BIF_GET_TEXASRU || code == RS6000_BIF_SET_TEXASRU ) ; return


<s> bool mep_reuse_lo_p ( rtx lo , rtx gpr , rtx_insn * insn , bool gpr_dead_p ) { bool result = mep_reuse_lo_p_1 ( lo , gpr , insn , gpr_dead_p ) ; extract_insn ( insn


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll (


<s> if ( getRegSizeInBits ( * NewRC ) < <NUM_LIT> && getRegSizeInBits ( * DstRC ) < <NUM_LIT> && getRegSizeInBits ( * SrcRC ) < <NUM_LIT> ) return true ; auto NewRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( NewRC ) ; auto SrcRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( SrcRC ) ; auto DstRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( DstRC ) ; if ( SrcRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; if ( DstRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto It = AFI -> getCoalescedWeight


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS (


<s> static <ISA_LIT>Operand * CreateFCCReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_FCC , RegInfo , S


<s> static __inline unsigned int _MM_GET_EXCEPTION_STATE ( void ) { return _mm_getcsr (


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits


<s> ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB


<s> size_t <ISA_LIT>ELFDynamic :: getSymTabNum ( const ELFFileFormat & pFormat ) const { if ( ! pFormat . hasDynSymTab ( ) ) return <NUM_LIT> ; const LDSection & dynsym = pFormat . getDynSymTab ( ) ; return dynsym . size ( ) /


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetEnvMacho ( ) ) ; if ( Subtarget -> isTargetWin64 ( ) ) { if ( Subtarget -> isTargetCygMing ( ) ) { BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; }


<s> if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) )


<s> int unsigned_p ; const_tree func ; if ( fn_decl_or_type && DECL_P ( fn_decl_or_type ) ) func = fn_decl_or_type ; else func = NULL ; mode = TYPE_MODE ( valtype ) ; unsigned_p = TYPE_UNSIGNED ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , func , <NUM_LIT> ) ; bool has_cxx_zero_width_bf = false ; bool has_cxx17_empty_base = false ; int use_fpr = mips_fpr_return_fields ( valtype , fields , & has_cxx_zero_width_bf , & has_cxx17_empty_base ) ; if ( TARGET_HARD_FLOAT && warn_psabi && has_cxx_zero_width_bf && ! has_cxx17_empty_base && use_fpr != <NUM_LIT> ) { static unsigned last_reported_type_uid ; unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( valtype ) ) ; if ( uid != last_reported_type_uid ) { static const char * url = CHANGES_ROOT_URL <STR_LIT> ; inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , url ) ; last_reported_type_uid = uid ; } } if ( has_cxx_zero_width_bf ) use_fpr = <NUM_LIT> ; if ( TARGET_HARD_FLOAT && warn_psabi && use_fpr != <NUM_LIT> && has_cxx17_empty_base ) { static unsigned last_reported_type_uid ; unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( valtype ) ) ; if ( uid != last_reported_type_uid ) { static const char * url = CHANGES_ROOT_URL <STR_LIT> ; inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , url ) ; last_reported_type_uid = uid ; } } switch ( use_fpr ) { case <NUM_LIT> : return mips_return_fpr_single ( mode , TYPE_MODE ( TREE_TYPE ( fields [ <NUM_LIT> ] ) ) ) ; case


<s> if ( ! TID . getImplicitDefs ( ) && ! TID . hasOptionalDef ( ) ) return false ; bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back (


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op ,


<s> static LoadInst * CreateLoadIns ( IRBuilder < NoFolder > & IRB , LoadInst & BaseLoad , Type * LoadTy ) { const unsigned AddrSpace = BaseLoad . getPointerAddressSpace (


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RI = TII . getRegisterInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget (


<s> return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) { I =


<s> BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setLogAlignment ( <NUM_LIT> ) ; } else CPEBB -> setLogAlignment ( getCPELogAlign ( *


<s> bool isGOTPLDpc ( MachineInstr & Instr ) { if ( Instr . getOpcode ( ) != <STR_LIT> ) return false ; const MachineOperand & LoadedAddressReg = Instr


<s> unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i +

j + <NUM_LIT> ] != j + NumElts + WhichResult ) ) return false ;


<s> GVSym -> setContainingCsect ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym


<s> case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << <NUM_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op .


<s> case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; EmitAlignment ( F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> , F ) ; O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> SmallVector < Bucket , <NUM_LIT> > <ISA_LIT>LoopInstrFormPrep :: collectCandidates ( Loop * L , std :: function < bool ( const Instruction * , const Value * ) > isValidCandidate , unsigned MaxCandidateNum ) { SmallVector < Bucket , <NUM_LIT> > Buckets ; for ( const auto & BB : L -> blocks ( ) ) for ( auto & J : * BB ) { Value * PtrValue ; Instruction * MemI ; if ( LoadInst * LMemI = dyn_cast < LoadInst > ( & J ) ) { MemI = LMemI ; PtrValue = LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( & J ) ) { MemI =


<s> rtx aarch64_mask_from_zextract_ops ( rtx width , rtx pos ) { gcc_assert ( CONST_INT_P ( width ) ) ; gcc_assert ( CONST_INT_P ( pos


<s> while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( )

<= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ;


<s> BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AllOnes ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( AllOnes ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( loopMBB ) ; MI . eraseFromParent ( ) ; return


<s> unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; bool isFloat = ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) ; unsigned CondReg = isFloat ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) ; UpdateValueMap ( I


<s> if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( d ) ) attrs = aarch64_add_attribute ( <STR_LIT> , attrs ) ; return aarch64_add_attribute ( <STR_LIT> , attrs


<s> static __inline unsigned long long sh_media_MMULFX_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode ( V2SI


<s> if ( MF . getFunction ( ) . hasFnAttribute ( Attribute


<s> EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } Register DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } unsigned RetOpc ; if ( IsCmseNSEntry ) if ( isThumb2 ) RetOpc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; else RetOpc = Subtarget -> getReturnOpcode ( ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; AddOptionalDefs ( MIB ) ; for ( unsigned R : RetRegs ) MIB . addReg ( R , RegState :: Implicit ) ; return


<s> IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load ,


<s> if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( &


<s> if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! base_reg_operand ( target , GET_MODE ( target ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( mem ) == ZERO_EXTEND || ( GET_CODE ( mem ) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN ) ) mem = XEXP ( mem , <NUM_LIT> ) ; if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target )


<s> void <ISA_LIT>JITInfo :: relocate ( void * Function , MachineRelocation * MR , unsigned NumRelocs , unsigned char * GOTBase ) { for ( unsigned i = <NUM_LIT> ; i != NumRelocs ; ++ i , ++ MR ) { void * RelocPos = ( char * ) Function + MR -> getMachineCodeOffset ( ) ; intptr_t ResultPtr = ( intptr_t ) MR -> getResultPointer ( ) ; switch ( ( <STR_LIT> ) MR -> getRelocationType ( ) ) { case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> - MR -> getConstantVal ( ) ; * ( ( unsigned * ) RelocPos ) += ( unsigned ) ResultPtr ; break ; } case <STR_LIT> :


<s> BinOpChain ( Instruction * I , ValueList & lhs , ValueList &


<s> SmallVector < int , <NUM_LIT> > PermuteMask ( Mask . size ( ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; assert ( Mask [ i ] < Size * <NUM_LIT> && <STR_LIT> ) ; if ( BlendMask [ Mask [ i ] % Size ] == - <NUM_LIT> ) BlendMask [ Mask [ i ] % Size ] = Mask [ i ] ; else if ( BlendMask [ Mask [ i ] % Size ] != Mask [ i ] ) return SDValue ( ) ; PermuteMask [ i ] = Mask [ i ] % Size ; } SDValue V = DAG . getVectorShuffle ( VT , DL , V1 , V2 , BlendMask ) ; return DAG . getVectorShuffle ( VT , DL , V , DAG .


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , Reloc :: Model RM , bool JIT ) { if ( CM ) { if ( * CM == CodeModel :: Tiny ) report_fatal_error ( <STR_LIT> , false ) ; if ( * CM == CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> , false ) ; return * CM


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFPOEndProc ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseEOL (


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; } unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return DecodeMemBarrierOption ( Inst , imm , Address , Decoder ) ; } unsigned brtarget = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2BROperand ( Inst , brtarget , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr *

DefMI , unsigned DefIdx ) const override {


<s> assert ( cast < FixedVectorType > ( SVI -> getType ( ) ) -> getNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > Indices ; auto Mask = SVI -> getShuffleMask ( ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) Indices . push_back ( Mask [ i ] ) ; ArrayRef < ShuffleVectorInst * > Shuffles = makeArrayRef


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is128BitVector ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) )