<s> case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & MCID = TII -> get ( Opc ) ; Register DestReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; BuildMI ( * Head , Head -> end ( ) , TermDL , MCID ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . add ( HeadCond [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MRI -> constrainRegClass ( HeadCond [ <NUM_LIT> ] . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; } Head -> splice ( Head -> end ( ) , CmpBB , CmpBB -> begin ( ) , CmpBB -> end ( ) ) ; unsigned Opc = <NUM_LIT> ; unsigned FirstOp = <NUM_LIT> ; bool isZBranch = false ; switch ( CmpMI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc =


<s> return __builtin_ia32_cvttss2si ( ( __v4sf )


<s> case MOV_EBP : ++ NumMovEBPInstructions ; break ; case MOV_ESP : ++ NumMovESPInstructions ; break ; case LEA_ESI : ++ NumLeaESIInstructions ; break ; case LEA_EDI : ++


<s> __o = __builtin_aarch64_ld4v2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o


<s> rtx mips_got_load ( rtx temp , rtx addr , enum mips_symbol_type type ) { rtx base , high , lo_sum_symbol ; base = mips_pic_base_register ( temp ) ; if ( temp != NULL && reg_overlap_mentioned_p ( base , temp ) ) temp = NULL ; high = mips_unspec_offset_high ( temp , base , addr ,


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) )


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler :: Success


<s> NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; DispSpec . getExpr ( ) -> print ( O , & MAI ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ; else { O << <STR_LIT> ; DispVal = -


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; uint64_t Offset = StackSize + MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . getImm ( ) ; unsigned NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes ; NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; } MBBI -> setDesc ( ZII -> get ( NewOpcode ) ) ; MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else if ( StackSize ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , StackSize


<s> unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_ARCH_ASE_M16 ; MCA . setELFHeaderEFlags ( Flags


<s> return ( __m64 ) __builtin_ia32_psllw ( ( __v4hi ) __m ,


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups , STI ) ; isAdd = <STR_LIT> ( Imm8 ) == <STR_LIT> ; } uint32_t Binary = <STR_LIT> ( Imm8 ) ; if ( isAdd ) Binary |= ( <NUM_LIT>


<s> const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; ArgInfo ArgRetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> >


<s> assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> (


<s> const auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsWin64 = Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv


<s> } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_GEP : case TargetOpcode :: G_MUL : case TargetOpcode :: G_SDIV : case TargetOpcode :: G_UDIV : case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameKindOfOperandsMapping ( MI ) ; case TargetOpcode :: G_BITCAST : { LLT DstTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT SrcTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Size = DstTy . getSizeInBits ( ) ; bool DstIsGPR = ! DstTy . isVector ( ) ; bool SrcIsGPR = ! SrcTy . isVector ( ) ; const RegisterBank & DstRB = DstIsGPR ? <STR_LIT> : <STR_LIT> ; const RegisterBank & SrcRB = SrcIsGPR ? <STR_LIT> : <STR_LIT> ; return InstructionMapping { DefaultMappingID , copyCost ( DstRB , SrcRB , Size ) , <STR_LIT> ( DstIsGPR , SrcIsGPR , Size ) , <NUM_LIT> } ; } case TargetOpcode :: G_SEQUENCE : return InstructionMapping ( ) ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < <STR_LIT> , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) )


<s> const <ISA_LIT>TargetLowering * llvm :: create<ISA_LIT>16TargetLowering ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>16TargetLowering ( TM , STI


<s> int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode ( ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; return ; } assert ( pos < <NUM_LIT> &&


<s> bool isDarwinABI ( ) const { return isTargetMachO ( ) || isDarwin


<s> computeInsertionPoint ( U -> User , U -> Op , InsertPts ) ; } while ( ++ U != E && U -> C == C ) ; auto & Promotion = PromotionCache [ C ] ; ensurePromotedGV ( F , * C , Promotion


<s> if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI


<s> unsigned Sube = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Subo = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Even = MRI . getSubReg ( Reg ,


<s> SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result .


<s> static rtx aarch64_progress_pointer ( rtx pointer ) { HOST_WIDE_INT amount = GET_MODE_SIZE ( GET_MODE


<s> void setBytesInStackArgArea ( unsigned bytes ) { BytesInStackArgArea =


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( MF , i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= FixUpImmediateBr ( MF , ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= OptimizeThumb2Instructions ( MF ) ; verify ( MF ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= UndoLRSpillRestore ( ) ; DEBUG ( errs ( ) << '\n' ; dumpBBs ( ) ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear (


<s> enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_PREFIXED_NUMERIC || iform


<s> return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : <NUM_LIT> ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : <NUM_LIT> ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : <NUM_LIT> ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : <NUM_LIT> ) | ( ( TARGET_DFP ) ?

RS6000_BTM_DFP : <NUM_LIT> ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : <NUM_LIT> ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : <NUM_LIT> ) ) ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT>

, <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ;


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> && MI . getNumOperands ( ) > <NUM_LIT> ) { MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { StringRef FuncName = MO . getGlobal ( ) -> getName ( ) ; if ( FuncName . compare_insensitive (


<s> assert ( m_pRelocator != NULL ) ; return m_pRelocator


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig


<s> EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getConstant ( InNVT . getVectorNumElements ( ) , DL , <STR_LIT> ) ) ; Lo = DAG . getNode ( N -> getOpcode ( ) , DL , LoVT , Lo ) ; Hi = DAG . getNode ( N -> getOpcode ( ) , DL , HiVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT ,


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; if ( MO . getOffset ( ) ) O << <STR_LIT> << MO .


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Chain = NewSP . getValue ( <NUM_LIT>


<s> if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> isSwift ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; if ( AssumeMisalignedLoadStores && ! mayCombineMisaligned ( * STI , * MI ) ) CanMergeToLSMulti = CanMergeToLSDouble = false ; for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I , ++ Count ) { int NewOffset = MemOps [ I ] . Offset ; if ( NewOffset != Offset + ( int ) Size ) break ; const MachineOperand & MO = getLoadStoreRegOp ( * MemOps [ I ] . MI ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) break ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; bool PartOfLSMulti = CanMergeToLSMulti ; if ( PartOfLSMulti ) { if ( RegNum <= PRegNum ) PartOfLSMulti = false ; else if ( ! isNotVFP && RegNum != PRegNum + <NUM_LIT> ) PartOfLSMulti = false ; } bool PartOfLSDouble = CanMergeToLSDouble && Count <= <NUM_LIT> ; if ( ! PartOfLSMulti && ! PartOfLSDouble ) break ; CanMergeToLSMulti &= PartOfLSMulti ; CanMergeToLSDouble &= PartOfLSDouble ; unsigned Position = MemOps [ I ] . Position ; if ( Position < MemOps [ Latest ] . Position ) Latest = I ; else if ( Position > MemOps [ Earliest ] . Position ) Earliest = I ; Offset += Size ; PRegNum = RegNum ; } MergeCandidate * Candidate = new ( Allocator . Allocate ( ) ) MergeCandidate ; for ( unsigned C = SIndex , CE = SIndex + Count ; C < CE ; ++ C ) Candidate -> Instrs . push_back ( MemOps [ C ] . MI ) ; Candidate -> LatestMIIdx = Latest - SIndex ; Candidate -> EarliestMIIdx = Earliest - SIndex ; Candidate -> InsertPos = MemOps [ Latest ] . Position ; if ( Count == <NUM_LIT> ) CanMergeToLSMulti


<s> MCOperand SymHi = MCOperand :: CreateExpr ( MCSym ) ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , * Ctx ) ; MCOperand SymLo = MCOperand :: CreateExpr ( MCSym ) ; MCInsts . resize ( <NUM_LIT> ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , RegOpnd , SymHi ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , RegOpnd , RegOpnd


<s> return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG


<s> static unsigned getCheriPostRAAtomicOp ( const MachineInstr & MI , bool * IsCapabilityArg , bool * NeedsAdditionalReg ) { case <STR_LIT> ## op ## _I8 : \ * NeedsAdditionalReg = extrareg ; \ return <STR_LIT> ## op ## _I8_POSTRA ; \ case <STR_LIT> ## op ## _I16 : \ * NeedsAdditionalReg = extrareg ; \ return <STR_LIT> ## op ## _I16_POSTRA ; \ case <STR_LIT> ## op ## _I32 : \ * NeedsAdditionalReg = extrareg ; \ return <STR_LIT> ## op ## _I32_POSTRA ; \ case <STR_LIT> ## op ## _I64 : \ *

NeedsAdditionalReg = extrareg ; \ return <STR_LIT> ## op ## _I64_POSTRA ;


<s> if ( Visited . count ( MBB ) ) continue ; for ( MachineInstr & MI : * MBB ) { if ( ! IsInvalidTPInstruction ( MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB = BuildMI ( * PreHeader , PreHeader -> getFirstTerminator ( ) , LoopStart -> getDebugLoc (


<s> else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode


<s> assert ( Ty -> isVectorTy ( ) && <STR_LIT> ) ; unsigned WideBits = getScalarSizeInBits ( Ty ) * Ty -> getVectorNumElements ( ) ; assert ( WideBits > <NUM_LIT> &&


<s> static __inline double spu_extract ( vec_double2 a , int element ) { union { vec_double2 v ; double d [


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; addPass ( create<ISA_LIT>EvexToVexInsts (


<s> MachineBasicBlock * MBB = MFI ; unsigned BlockSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber


<s> int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> ,


<s> gcc_assert ( emit_move_imm || temp1 != NULL_RTX ) ; gcc_assert ( temp1 == NULL_RTX || ! reg_overlap_mentioned_p ( temp1 , src ) ) ; unsigned HOST_WIDE_INT moffset = absu_hwi ( offset ) ; rtx_insn * insn ; if ( ! moffset ) { if ( ! rtx_equal_p ( dest , src ) ) { insn = emit_insn ( gen_rtx_SET ( dest , src ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; } return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < <NUM_LIT> && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset & <NUM_LIT> ; low_off = offset < <NUM_LIT> ? - low_off : low_off ; insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( dest , GEN_INT ( offset - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( emit_move_imm ) { gcc_assert ( temp1 != NULL_RTX || can_create_pseudo_p ( ) ) ; temp1 = aarch64_force_temporary ( mode , temp1 , gen_int_mode ( moffset , mode ) ) ; } insn = emit_insn ( offset < <NUM_LIT> ? gen_sub3_insn ( dest , src ,

temp1 ) : gen_add3_insn ( dest , src , temp1 ) ) ;


<s> CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL ,


<s> } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea1Size ( ) ) ; } if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII


<s> static bool ContainsReg ( const ArrayRef < std :: pair < unsigned , bool >> & Regs , unsigned Reg ) { for ( const std :: pair < unsigned , bool > & R : Regs ) if ( R


<s> bool isMemUnsized ( ) const { return Kind == Memory && Mem .


<s> IRBuilder < > Builder ( AMXCast ) ; AllocaInst * AllocaAddr ; Value * I8Ptr , * Stride ; auto * Src = AMXCast -> getOperand ( <NUM_LIT> ) ; auto Prepare = [ & ] ( Type * MemTy ) { AllocaAddr = createAllocaInstAtEntry ( Builder , AMXCast -> getParent ( ) , MemTy ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( AMXCast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( AMXCast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > (


<s> SmallVector < unsigned , <NUM_LIT> > Worklist ; RegDomain Domain = NoDomain ; visitRegister ( C , Reg , Domain , Worklist ) ; while ( ! Worklist . empty ( ) ) { unsigned CurReg = Worklist . pop_back_val ( ) ; if ( ! C . insertEdge ( CurReg ) ) continue ; MachineInstr * DefMI = MRI -> getVRegDef ( CurReg ) ; encloseInstr ( C , DefMI ) ; int OpEnd = DefMI -> getNumOperands ( ) ; const MCInstrDesc & Desc = DefMI -> getDesc ( ) ; int MemOp = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOp != - <NUM_LIT> ) MemOp += <STR_LIT> ( Desc ) ; for ( int OpIdx = <NUM_LIT> ; OpIdx < OpEnd ; ++ OpIdx ) { if ( OpIdx == MemOp ) { OpIdx += ( <STR_LIT> - <NUM_LIT> ) ; continue ; } auto & Op = DefMI -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; visitRegister ( C , Op . getReg ( ) , Domain , Worklist ) ; } for ( auto & UseMI : MRI -> use_nodbg_instructions ( CurReg ) ) { if ( usedAsAddr ( UseMI , CurReg , TII


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . hasOptionalDef ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO


<s> bool LookedThroughZExt = false ; if ( OffsetOpc != TargetOpcode :: G_SHL && OffsetOpc != TargetOpcode :: G_MUL ) { if ( OffsetOpc != TargetOpcode :: G_ZEXT || ! WantsExt ) return None ; OffsetInst = MRI . getVRegDef ( OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OffsetOpc = OffsetInst -> getOpcode ( ) ; LookedThroughZExt = true ; if ( OffsetOpc != TargetOpcode :: G_SHL && OffsetOpc != TargetOpcode :: G_MUL ) return None ; } int64_t LegalShiftVal = Log2_32 ( SizeInBytes ) ; if ( LegalShiftVal == <NUM_LIT> ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * OffsetInst , MRI ) ) return None ; Register OffsetReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFILL_FW ( MachineInstr * MI , MachineBasicBlock * BB ) const { return BB


<s> return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } } if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; GEPs . push_back ( V ) ; if ( const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( U -> getOperand ( <NUM_LIT> ) ) ) { V = GEP ; goto redo_gep ; } else if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) { return true ; } AM = SavedAM ; for ( SmallVectorImpl < const Value * > :: reverse_iterator I = GEPs . rbegin ( ) , E = GEPs . rend ( ) ; I != E ; ++ I ) if ( handleConstantAddresses ( * I , AM ) ) return true ; return false


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t OSABI ) : <ISA_LIT>AsmBackend ( T ) , OSABI ( OSABI


<s> getTargetStreamer ( ) . EmitARM64WinCFIAddFP ( Size ) ; return


<s> unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; bool emit_frame_chain = cfun -> machine -> frame . emit_frame_chain ; rtx_insn * insn ; if ( flag_stack_clash_protection && known_eq ( callee_adjust , <NUM_LIT> ) ) { initial_adjust += sve_callee_adjust ; sve_callee_adjust = <NUM_LIT> ; } if ( aarch64_return_address_signing_enabled ( ) ) { switch ( aarch64_ra_sign_key ) { case AARCH64_KEY_A : insn = emit_insn ( gen_paciasp ( ) ) ; break ; case AARCH64_KEY_B : insn = emit_insn ( gen_pacibsp ( ) ) ; break ; default : gcc_unreachable ( ) ; } add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( flag_stack_usage_info ) current_function_static_stack_size = constant_lower_bound ( frame_size ) ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( maybe_gt ( frame_size , PROBE_INTERVAL ) && maybe_gt ( frame_size , get_stack_check_protect ( ) ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , ( frame_size - get_stack_check_protect ( ) ) ) ; } else if ( maybe_gt ( frame_size , <NUM_LIT> ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , frame_size ) ; } rtx tmp0_rtx = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; rtx tmp1_rtx = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; gcc_assert ( known_eq ( initial_adjust , <NUM_LIT> ) || callee_adjust == <NUM_LIT> ) ; aarch64_allocate_and_probe_stack_space ( tmp0_rtx , tmp1_rtx , initial_adjust , true , false ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; poly_int64 chain_offset = ( initial_adjust + callee_adjust - cfun -> machine -> frame . hard_fp_offset ) ; gcc_assert ( known_ge ( chain_offset , <NUM_LIT> ) ) ; poly_int64 saved_regs_offset = chain_offset -


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] && ExtraCode [ <NUM_LIT> ] != 'a' ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum


<s> static bool sparc_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( decl && flag_delayed_branch && ( TARGET_ARCH64 || ! cfun -> returns_struct ) && ! ( TARGET_VXWORKS_RTP && flag_pic && ! targetm .


<s> return getShiftExtendType ( ) == <STR_LIT> && ( Shift ==


<s> V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( V ) ) & V ; if ( V == <NUM_LIT> ) return false ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; V = Imm ; if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; else if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; if ( getT2SOImmVal ( V ) !=


<s> if ( cfun -> machine -> indirect_branch_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> indirect_branch_type = ix86_indirect_branch ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep && ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_extern ) && ( flag_cf_protection & CF_RETURN ) ) error ( <STR_LIT> <STR_LIT> ) ; } if ( cfun -> machine -> function_return_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable (


<s> Op = <STR_LIT> ; break ; default : Op = <STR_LIT> ; break ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) { MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; } else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( Op == <STR_LIT> || Op == <STR_LIT> ) { MIB . addImm ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . add ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr & NewMI = * std :: prev ( MBBI ) ; NewMI . copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ; unsigned StackPtr = TRI -> getStackRegister ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstrBuilder MIB ; if ( StackAdj == <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine &


<s> return ( int ) __builtin_ia32_cvtsd2si ( ( __v2df )


<s> EmitMappingSymbol ( <STR_LIT> ) ; LastEMSInfo -> State


<s> return MCSectionELF :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , <NUM_LIT> ,

SectionKind :: getMetadata ( ) , false , Ctx ) ;


<s> return create<ISA_LIT>AsmBackend ( T , STI , MRI ,


<s> static bool canUseOrr ( uint64_t Chunk , uint64_t & Encoding ) { Chunk = ( Chunk << <NUM_LIT> ) | ( Chunk << <NUM_LIT> ) | ( Chunk <<


<s> return wi :: cmps ( * ( ( const HOST_WIDE_INT * ) x ) , * ( (


<s> section * s ; char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ; switch_to_section ( s ) ; assemble_align ( POINTER_SIZE ) ; assemble_aligned_integer ( POINTER_BYTES


<s> assert ( ! IsStrict && <STR_LIT> ) ; softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return Op0 ; } } SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! EFLAGS ) return SDValue ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } ,


<s> break ; case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear


<s>
const
char
*
JTEntryDirective
=
MAI
->
getData32bitsDirective
(
)
;
const
MachineJumpTableInfo
*
MJTI
=
MF
->
getJumpTableInfo
(
)
;
const
std
::
vector
<
MachineJumpTableEntry
>
&
JT
=
MJTI
->
getJumpTables
(
)
;
const
std
::
vector
<
MachineBasicBlock
*
>
&
JTBBs
=
JT
[
JTI
]
.
MBBs
;
bool
UseSet
=
MAI
->
hasSetDirective
(
)
&&
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
SmallPtrSet
<
MachineBasicBlock
*
,
<NUM_LIT>
>
JTSets
;
for
(
unsigned
i
=
<NUM_LIT>
,
e
=
JTBBs
.
size
(
)
;
i
!=
e
;
++
i
)
{
MachineBasicBlock
*
MBB
=
JTBBs
[
i
]
;
bool
isNew
=
JTSets
.
insert
(
MBB
)
;
if
(
UseSet
&&
isNew
)
{
O
<<
<STR_LIT>
<<
*
Get<ISA_LIT>SetPICJumpTableLabel2
(
JTI
,
MO2
.
getImm
(
)
,
MBB
)
<<
','
<<
*
MBB
->
getSymbol
(
OutContext
)
<<
'-'
<<
*
JTISymbol
<<
'\n'
;
}
O
<<
JTEntryDirective
<<
' '
;
if
(
UseSet
)
O
<<
*
Get<ISA_LIT>SetPICJumpTableLabel2
(
JTI
,
MO2
.
getImm
(
)
,
MBB
)
;
else
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
O
<<
*
MBB
->
getSymbol
(
OutContext
)
<<
'-'
<<
*
JTISymbol
;
else
O
<<
*
MBB
->
getSymbol
(
OutContext
)
;
if
(
i
!=
e


<s> mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { Register ActualRetAddrReg = MRI -> createVirtualRegister (


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( )

) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ;


<s> if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , AddrDecoder ( Inst , addr , Address , Decoder


<s> Register SrcReg = SMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , <NUM_LIT> , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) continue ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill (


<s> vld2_dup_p64 ( const poly64_t * __a ) { poly64x1x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t )


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; default : return SDValue ( ) ; } EVT SignExtSrcVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT SrcMemVT = cast < VTSDNode > ( Src -> getOperand ( MemVTOpNum ) ) -> getVT ( ) ; if ( ( SignExtSrcVT != SrcMemVT ) || ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT DstVT = N -> getValueType


<s> CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) { if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) -> getAttributes

( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_SaveList ;


<s> bool isRegList ( ) const { return Kind


<s> return ( __m512i ) __builtin_ia32_psubsw512_mask ( ( __v32hi ) __A , ( __v32hi )


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> ) ; unsigned RetReg = ValLocs [ <NUM_LIT> ] . getLocReg ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign ::


<s> if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx (


<s> else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: FPR128 ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: ZPR ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: PPR ; else llvm_unreachable ( <STR_LIT> ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; switch ( RPI . Type ) { case RegPairInfo :: GPR : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateRegisterPairing ( RPI . Reg1 , NextReg , NeedsWinCFI , NeedsFrameRecord ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR64 : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateWindowsRegisterPairing ( RPI . Reg1 , NextReg , NeedsWinCFI ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR128 : if ( <STR_LIT> . contains ( NextReg ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: PPR : case RegPairInfo :: ZPR : break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! RPI . isPaired ( ) || ! NeedsFrameRecord || RPI . Reg2

!= <STR_LIT> || RPI . Reg1 == <STR_LIT> ) && <STR_LIT> ) ;


<s> MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( )


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI )


<s> case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == <NUM_LIT> || ImmVal == <NUM_LIT> ) return TTI :: TCC_Free ; } ImmIdx = <NUM_LIT> ; break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx =


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNo , raw_ostream & O , const char * Modifier ) { O << <STR_LIT> ; printOperand ( MI , OpNo , O


<s> n = - n ; } n_rtx = GEN_INT ( n ) ; gcc_assert ( satisfies_constraint_P27 ( n_rtx ) ) ; switch ( type ) { case ASHIFTRT : emit_insn ( gen_ashrsi3_k ( reg , reg , n_rtx ) ) ; break ; case LSHIFTRT : if ( n == <NUM_LIT> ) emit_insn ( gen_shlr ( reg , reg ) ) ; else emit_insn ( gen_lshrsi3_k ( reg , reg , n_rtx ) ) ; break ; case ASHIFT : emit_insn ( gen_ashlsi3_k ( reg , reg ,


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_ostream & OS


<s> return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 || MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 && <STR_LIT> ( Imm ) < <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> RegTOpIdx = <NUM_LIT> ; RegNOpIdx = <NUM_LIT> ; LnOpIdx = <NUM_LIT> ; } else { RegTOpIdx = <NUM_LIT> ; RegNOpIdx = <NUM_LIT> ; LnOpIdx = <NUM_LIT> ; } Binary |= ( IsThumb ? <STR_LIT> : II -> getPredicate ( & MI ) ) << <STR_LIT> ; unsigned RegT = MI . getOperand ( RegTOpIdx ) . getReg ( ) ; RegT = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , RegNOpIdx ) ; unsigned LaneShift ; if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= ( Opc1


<s> break ; case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_INIT : case IES_LBRAC : if ( setSymRef ( SymRef , SymRefName , ErrMsg ) ) return true ; MemExpr = true ; State = IES_INTEGER ; IC . pushOperand ( IC_IMM ) ; if ( ParsingInlineAsm )


<s> if ( Count == <NUM_LIT> ) return SelectInt64Direct ( CurDAG , dl , Imm ) ; unsigned RMin = <NUM_LIT> ; int64_t MatImm ; unsigned MaskEnd ; for ( unsigned r = <NUM_LIT> ; r < <NUM_LIT> ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = SelectInt64CountDirect ( RImm ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = <NUM_LIT> ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - <NUM_LIT> ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( <NUM_LIT> ) << ( LS + <NUM_LIT> ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = SelectInt64CountDirect ( RImmWithOnes ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ; } } if ( ! RMin ) return SelectInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm ,


<s> if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) ) UseFastISel = false ; return UseFastISel ? <STR_LIT> ( funcInfo


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] &


<s> static void emitCallSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , const DebugLoc & dl ,

const ThumbRegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) {


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; int CombineOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto isConjugationConstant = [ ] ( const Constant * c ) { if ( const auto * CI = dyn_cast < ConstantInt > ( c ) ) { APInt ConjugationInt32 = APInt ( <NUM_LIT> , <NUM_LIT> , true ) ; APInt ConjugationInt64 = APInt ( <NUM_LIT> , <NUM_LIT> , true ) ; switch ( CI -> getBitWidth ( ) ) { case <NUM_LIT> : return false ; case <NUM_LIT> : return CI -> getValue ( ) == ConjugationInt32 ; case <NUM_LIT> : return CI -> getValue ( ) == ConjugationInt64 ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( const auto * CF = dyn_cast < ConstantFP > ( c ) ) return CF -> isNegativeZeroValue ( ) ; return false ; } ; auto combineConjugation = [ & ] ( SDValue & r ) { if ( LHS -> getOpcode ( ) == <STR_LIT> && RHS . hasOneUse ( ) ) { SDValue XOR = LHS . getOperand ( <NUM_LIT> ) ; if ( XOR -> getOpcode ( ) == <STR_LIT> && XOR . hasOneUse ( ) ) { SDValue XORRHS = XOR . getOperand ( <NUM_LIT> ) ; if ( XORRHS . getOpcode ( ) == <STR_LIT> && XORRHS . hasOneUse ( ) ) XORRHS = XORRHS . getOperand ( <NUM_LIT> ) ; if ( XORRHS . getOpcode ( ) == <STR_LIT> && XORRHS . getOperand ( <NUM_LIT> ) . getNumOperands ( ) ) { ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( XORRHS . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CP && isConjugationConstant ( CP -> getConstVal ( ) ) ) { SelectionDAG :: FlagInserter FlagsInserter ( DAG , N ) ; SDValue I2F = DAG . getBitcast ( VT , LHS . getOperand (


<s> assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' << Imm ; break ; } case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal


<s> setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( isPositionIndependent ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles ::


<s> case <STR_LIT> : case <STR_LIT> : return true ; } } if ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) { switch ( First -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , &


<s> if ( ! NeedsDwarfUnwindInfo ) NeedsDwarfUnwindInfo = MF . needsFrameMoves ( ) && ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; return * NeedsDwarfUnwindInfo


<s> return ( __m512i ) __builtin_ia32_vcvtph2dq512_mask_round ( __A , ( __v16si ) _mm512_setzero_si512 ( ) , (


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg .


== BRANCH_ISLAND_FUNCTION_NAME ( branch_island ) ) return <NUM_LIT> ;


<s> Inst . addOperand ( MCOperand :: createReg


<s> bool slowLEA ( ) const { return SlowLEA


<s> if ( BaseRegNo != N86 :: EBP ) { if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } if ( Disp . isExpr ( ) ) { auto * Sym = dyn_cast < MCSymbolRefExpr > ( Disp . getExpr ( ) ) ; if ( Sym && Sym -> getKind ( ) == MCSymbolRefExpr :: VK_TLSCALL ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Sym , FK_NONE , MI . getLoc ( ) ) ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } } } if ( Disp . isImm ( ) && AllowDisp8 ) { int ImmOffset = <NUM_LIT> ; if ( isDispOrCDisp8 ( TSFlags , Disp . getImm ( ) , ImmOffset ) ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups , ImmOffset ) ; return ; } } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; unsigned Opcode = MI . getOpcode ( ) ; unsigned FixupKind = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , MCFixupKind ( FixupKind ) , StartByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; int ImmOffset = <NUM_LIT> ; if ( BaseReg == <NUM_LIT> ) { BaseRegNo = <NUM_LIT> ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp32 = true ; } else if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp && BaseRegNo != N86 :: EBP ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; } else if ( Disp . isImm ( ) && AllowDisp8 && isDispOrCDisp8 ( TSFlags , Disp . getImm ( ) , ImmOffset ) ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp8 = true ; } else { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp32 = true ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; unsigned IndexRegNo = IndexReg . getReg ( ) ?

get<ISA_LIT>RegNum ( IndexReg ) : <NUM_LIT> ;


<s> void sparc_profile_hook ( int labelno ) { char buf [ <NUM_LIT> ] ; rtx lab , fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = RegName . size ( ) ; i != e ; ++ i ) O << ( char ) toupper ( RegName


<s> case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC32 : ELF :: R_<ISA_LIT>_64_32 ; case RT64_32S : return ELF :: R_<ISA_LIT>_64_32S ; case RT64_16 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC16 : ELF :: R_<ISA_LIT>_64_16 ; case RT64_8 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC8 : ELF :: R_<ISA_LIT>_64_8 ; } case MCSymbolRefExpr :: VK_GOT : switch ( Type ) { case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC64 : ELF :: R_<ISA_LIT>_64_GOT64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC32 : ELF :: R_<ISA_LIT>_64_GOT32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT64_64 ) ; assert ( ! IsPCRel ) ; return ELF :: R_<ISA_LIT>_64_GOTOFF64 ; case MCSymbolRefExpr :: VK_TPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_TPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_TPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_DTPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_DTPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_SIZE : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_SIZE64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_SIZE32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_64_TLSDESC_CALL ; case MCSymbolRefExpr :: VK_TLSDESC : return ELF :: R_<ISA_LIT>_64_GOTPC32_TLSDESC ; case MCSymbolRefExpr :: VK_TLSGD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSGD ; case MCSymbolRefExpr :: VK_GOTTPOFF : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_GOTTPOFF ; case MCSymbolRefExpr :: VK_TLSLD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSLD ; case MCSymbolRefExpr :: VK_PLT : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_PLT32 ; case MCSymbolRefExpr :: VK_GOTPCREL : checkIs32 ( Ctx , Loc , Type ) ; if ( ! Ctx . getAsmInfo ( ) -> canRelaxRelocations ( ) ) return ELF :: R_<ISA_LIT>_64_GOTPCREL ; switch ( Kind ) { default : return ELF :: R_<ISA_LIT>_64_GOTPCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_GOTPCRELX ; case <STR_LIT> : case <STR_LIT> : return ELF ::


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( )

) Flags |= MachineMemOperand :: MOStore ;


<s> Pass * llvm :: createMVETailPredicationPass ( )


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 , true > Y ( getThe<ISA_LIT>V9Target ( ) , <STR_LIT> ,


<s> bool MVETailPredication :: IsPredicatedVectorLoop ( ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( IsMasked ( & I ) ) { VectorType * VecTy = getVectorType ( cast < IntrinsicInst > ( & I ) ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits


<s> static bool isSignExtended ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N ) ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG , true ) ) return true ; return false


<s> return DAG -> getNode ( <STR_LIT> , dl , ToVT , Val


<s> analysis_result result = analyze ( type ) ; gcc_assert ( result != DOESNT_MATTER ) ; return result ==


<s> const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { assert ( Type == MachO :: <ISA_LIT>_RELOC_VANILLA && <STR_LIT> ) ; const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info


<s> SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Tmp3 = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , A64cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , Tmp3 . getValueType ( ) ) , Tmp3 , A64cc ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , TrueVal , FalseVal , A64cc ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && N -> getOpcode ( ) == <STR_LIT> ) { SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain ) ) continue ; MoveBelowCallSeqStart ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( )


<s> bool <ISA_LIT>AsmBackend :: needAlign ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( Assembler . isBundlingEnabled ( ) && Sec -> isBundleLocked ( ) ) return false ; if ( ! ( STI . hasFeature ( <STR_LIT> ) || STI . hasFeature ( <STR_LIT> ) ) ) return false ; return


<s> emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , <NUM_LIT> ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , <NUM_LIT> ) ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( gen_rtx_MEM ( DImode , tramp ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 ) emit_insn ( gen_flushdi ( validize_mem ( gen_rtx_MEM ( DImode , plus_constant ( tramp ,


<s> static inline bool is_complex_IBM_long_double


<s> return ( vector float ) __builtin_altivec_vaddfp ( ( vector float ) a1 , ( vector float


<s> int LaneSize = Size / <NUM_LIT> ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int & M = InLaneMask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( ( M % Size ) / LaneSize ) != ( i / LaneSize ) ) M = ( M % LaneSize ) + ( ( i / LaneSize ) * LaneSize ) + Size ; } assert ( ! is128BitLaneCrossingShuffleMask ( VT , InLaneMask ) && <STR_LIT> ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast ( PVT , V1


<s> case <STR_LIT> : return I -> getFlag ( MachineInstr :: FrameSetup ) || I

-> getFlag ( MachineInstr :: FrameDestroy ) ;


<s> uint32_t generateCompactUnwindEncoding ( ArrayRef < MCCFIInstruction > Instrs


<s> ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_PENDING_INT ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_INT_PRIORITY ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , integer , SET_INT_PRIORITY ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , CLR_PENDING_HWINT ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , SET_TRIG_LEVEL ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , SET_TRIG_EDGE ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_TRIG_TYPE ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , ptr_uint , LLW ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , ptr_uint , LWUP ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , char , ptr_uchar , LBUP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , ptr_uint , unsigned , SCW ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , ptr_uint , unsigned , SWUP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , ptr_uchar , char , SBUP ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_INVALALL ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_WBALL_ALVL ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_WBALL_ONE_LVL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_LCK ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , unsigned , CCTL_IDX_WBINVAL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_WBINVAL_L1 ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_WBINVAL_LA ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , integer , unsigned , CCTL_IDX_READ ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , integer , unsigned , unsigned , CCTL_IDX_WRITE ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uchar , unsigned , integer , DPREF_QW ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_ushort , unsigned , integer , DPREF_HW ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uint , unsigned , integer , DPREF_W ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_ulong , unsigned , integer , DPREF_DW ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , integer , integer , ABS ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , integer , integer , integer , AVE ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BCLR ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BSET ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BTGL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BTST ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , integer , unsigned , CLIP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , integer , integer , unsigned , CLIPS ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , unsigned , CLZ ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , unsigned , CLO ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uint ,


<s> signed int i [ <NUM_LIT> ] ; } aa ; aa . v = ( vector signed int ) ( a ) ; if ( aa . i [ <NUM_LIT> ] > b


<s> DebugLoc dl = N -> getDebugLoc ( ) ; if ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) { if ( Subtarget -> hasAVX2 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; Op = DAG . getVectorShuffle ( <STR_LIT> , dl , Op , DAG . getUNDEF ( <STR_LIT> ) , ShufMask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Undef = DAG . getUNDEF ( VT ) ; OpLo = DAG . getVectorShuffle ( VT , dl , OpLo , Undef , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( VT , dl , OpHi , Undef , ShufMask1 ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , OpLo , OpHi , ShufMask2 ) ; } if ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) { if ( Subtarget -> hasAVX2 ( ) ) { Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: O_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ]


<s> if ( op [ <NUM_LIT> ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ <NUM_LIT> ] ) ; else { op [ <NUM_LIT> ] = copy_to_mode_reg ( Pmode , op [ <NUM_LIT> ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( getTLSReg ( )


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI

) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> if ( Loads . empty ( ) || Loads . size ( ) > NumLoadLimit ) return false ; using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: beforeOrAfterPointer ( ) ; for ( auto Write : Writes ) { for ( auto Read : Loads ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( Write -> comesBefore ( Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { bool BaseFirst = Base -> comesBefore ( Offset ) ; LoadInst * Dominator = BaseFirst ? Base : Offset ; LoadInst * Dominated = BaseFirst ? Offset : Base ; if ( RAWDeps . count ( Dominated ) ) { InstSet & WritesBefore = RAWDeps [ Dominated ] ; for ( auto Before : WritesBefore ) { if ( Dominator -> comesBefore ( Before ) ) return false ; } } return true ; } ; for ( auto *


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) &&


<s> const auto & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . hasMinSize ( ) ) return false ; if ( ! scanFunction ( ) ) return false ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB


<s> IRBuilder < > Builder ( EntryBB ) ; Value * LSDA = emitEHLSDA ( Builder , ParentFunc ) ; Value * CastPersonality = Builder . CreateBitCast ( PersonalityFn , TargetFuncTy -> getPointerTo ( ) ) ; auto AI = Trampoline -> arg_begin ( ) ; Value * Args [ <NUM_LIT> ] = { LSDA , & * AI ++ , & * AI ++ , & * AI ++ , & * AI ++ } ; CallInst * Call = Builder . CreateCall (


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel (


<s> return ( __m64 ) __builtin_arm_wcmpgtsh ( ( __v4hi ) __m1 ,


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseAdrpLabel ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * Expr = nullptr ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> return ( __m64 ) __builtin_arm_wminuh ( ( __v4hi ) __A , ( __v4hi )


<s> case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind


<s> unsigned Opc = MI -> getOpcode ( ) ; bool isPCOk = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isLROk = ( Opc == <STR_LIT> ) ; bool isSPOk = isPCOk || isLROk ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg


<s> bool isLegalMaskedScatter ( Type * Ty ,


<s> int64_t Imm = <NUM_LIT> ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt )


<s> if ( nonindexed_address_p ( x , strict ) ) return true ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( index_term_p ( xfoo0 , mode , strict ) && nonindexed_address_p ( xfoo1 , strict ) ) return true ; if ( index_term_p ( xfoo1 , mode , strict ) && nonindexed_address_p ( xfoo0 , strict )


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) || <ISA_LIT>InstrInfo :: isPreLdSt


<s> SDValue JT = Op . getOperand ( <NUM_LIT> ) ; SDValue Entry = Op . getOperand ( <NUM_LIT> ) ; int JTI = cast < JumpTableSDNode > ( JT . getNode ( ) ) -> getIndex ( ) ; auto * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setJumpTableEntryInfo ( JTI , <NUM_LIT> , nullptr ) ; SDNode * Dest = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , JT , Entry , DAG

. getTargetJumpTable ( JTI , <STR_LIT> ) ) ;


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> int Scale = <NUM_LIT> ; unsigned ImmOp ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ImmOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOp = <NUM_LIT> ; Scale = -


<s> rtx rs6000_return_addr ( int count , rtx frame ) { if ( count != <NUM_LIT> || ( DEFAULT_ABI != ABI_AIX && flag_pic ) ) { cfun -> machine -> ra_needs_full_frame = <NUM_LIT> ; return gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( copy_to_reg ( gen_rtx_MEM ( Pmode

, memory_address ( Pmode , frame ) ) ) , RETURN_ADDRESS_OFFSET ) ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes

( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ;


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_VANILLA ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD ->


<s> bool HasVCTP = false ; SmallVector < MachineInstr * , <NUM_LIT> > DeadInstructions ; for ( MachineInstr & MI : MBB . instrs ( ) ) { if ( isVCTP ( & MI ) ) { HasVCTP = true ; continue ; } if ( ! HasVCTP || MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; ( void ) MIBuilder ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ) ; DeadInstructions . push_back ( & MI ) ; } for ( MachineInstr * DeadInstruction : DeadInstructions ) DeadInstruction -> eraseFromParent ( ) ; return ! DeadInstructions . empty (


<s> } LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { assert ( ( VT . is128BitVector ( ) || Subtarget . hasAVX2 ( ) ) && <STR_LIT> ) ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case <STR_LIT> : case <STR_LIT> : case


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ?


<s> if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) ,


<s> SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT>


<s> getAddrMode3OffsetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Imm = MO1 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; return Imm8 | ( isAdd << <NUM_LIT> ) | (


<s> static void clearHighBits ( const MCOperand & Reg , MCStreamer & Out , const MCSubtargetInfo & STI ) { MCInst Mov ; Mov . setOpcode ( <STR_LIT> ) ; MCOperand Op = MCOperand :: CreateReg ( getReg32 ( Reg


<s> if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; } unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ; return std :: make_pair (


<s> MachineFunction & MF = * MBB . getParent ( ) ; const BasicBlock * BB = MBB . getBasicBlock ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCValid = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LivePhysRegs LiveRegs ( & TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister


<s> return ReservedGPRegisters . count ( )


, int __LX , __m128i __Y , int __LY , const int __M ) {


<s> Instruction * Induction = nullptr ; if ( ! match ( V , m_ICmp ( Pred , m_Instruction ( Induction ) , m_Instruction ( Shuffle ) ) ) || Pred != ICmpInst :: ICMP_ULE || ! L -> isLoopInvariant ( Shuffle ) ) return false ; Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements ) return false ; Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero ( ) ) ) ) return false ; auto * Phi = dyn_cast < PHINode > ( IV ) ; if ( ! Phi ) return false ; Value * OnEntry = Phi -> getIncomingValueForBlock ( L -> getLoopPreheader ( ) ) ; if ( ! match ( OnEntry , m_Zero ( ) ) ) return false ; Value * InLoop = Phi -> getIncomingValueForBlock ( L -> getLoopLatch ( ) ) ; unsigned Lanes = cast < VectorType > ( Insert -> getType ( ) ) -> getNumElements ( ) ; Instruction * LHS = nullptr ; if ( ! match ( InLoop , m_Add ( m_Instruction ( LHS ) , m_SpecificInt ( Lanes ) ) ) ) return false ; return LHS ==