<s> initialize<ISA_LIT>PromoteConstantPass ( * PassRegistry ::


<s> } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( SDLoc ( N ) , OpcodeVT ) , convertTo ( SDLoc ( N ) , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , OpcodeVT , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue ( N ,


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName (


<s> if ( ( getTok ( ) . isNot ( AsmToken :: Identifier ) && getTok ( ) . isNot ( AsmToken :: String ) ) || getParser ( ) . parsePrimaryExpr ( Val , End ) ) return Error ( Start , <STR_LIT> ) ; } else if ( ParseIntelInlineAsmIdentifier ( Val , ID , Info , false , End , true ) ) { return Error ( Start ,


<s> tree op_decl ; if ( ! TARGET_PID ) return PID_NOT_PID ; if ( GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op , <NUM_LIT>

) ) == CONST && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC ) return PID_ENCODED ;


<s> MVT VT = A . getSimpleValueType ( ) ; int NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Pool ; SDValue Cst = Constant ( sh , VT .


<s> static bool isUndefUpperHalf ( ArrayRef <


<s> if ( ! Opcode ) return false ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return


<s> Imm -= ThisVal ; AddDefaultPred ( AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) ) . addImm ( ThisVal ) ) ; if ( Imm > <NUM_LIT> ) emitThumbRegPlusImmediate ( MBB , MBBI , DestReg , DestReg , Imm , TII , MRI , dl ) ; if ( isSub ) { const TargetInstrDesc & TID = TII . get ( <STR_LIT> ) ; AddDefaultPred ( AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TID , DestReg )

) . addReg ( DestReg , RegState :: Kill ) ) ;


<s> switch ( MI . getOperand ( SegOperand ) . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte


<s> return isMem256 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) ->

getType ( ) -> getPrimitiveSizeInBits ( ) ;


<s> name = XSTR ( addr , <NUM_LIT> ) ; if ( name [ strlen ( name ) - <NUM_LIT> ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + <NUM_LIT> ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? <STR_LIT> : <STR_LIT> ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , <NUM_LIT> ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , <NUM_LIT> ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , <NUM_LIT> ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , <NUM_LIT> ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return


<s> unsigned HOST_WIDE_INT v = value ; gcc_assert ( ( align & <NUM_LIT> ) != <NUM_LIT> ) ; nelt_v8 = GET_MODE_NUNITS ( V8QImode ) ; nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 ) { mode = V16QImode ; gen_func = gen_movmisalignv16qi ; } else { mode = V8QImode ; gen_func = gen_movmisalignv8qi ; } nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , <NUM_LIT> ) ) ; mem = adjust_automodify_address ( dstbase , mode , dst , <NUM_LIT> ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_elt = GEN_INT ( v ) ; for ( j = <NUM_LIT> ; j < nelt_mode ; j ++ ) rval [ j ] = val_elt ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_rtx_CONST_VECTOR ( mode , gen_rtvec_v ( nelt_mode , rval ) ) ; emit_move_insn ( reg , val_vec ) ; for ( i = <NUM_LIT> ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { emit_insn ( ( * gen_func ) ( mem , reg ) ) ; if ( i + <NUM_LIT> * nelt_mode <= length ) emit_insn ( gen_add2_insn ( dst , GEN_INT ( nelt_mode ) ) ) ; } gcc_assert ( ( i + nelt_v8 ) > length || mode == V16QImode ) ; if ( i + nelt_v8 < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - i ) ) ) ; if ( ( length & <NUM_LIT> ) != <NUM_LIT> && align >= <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; } else if ( i < length && i + nelt_v8 >= length ) { if ( mode == V16QImode ) { reg = gen_lowpart ( V8QImode , reg ) ; mem = adjust_automodify_address ( dstbase , V8QImode , dst , <NUM_LIT> ) ; } emit_insn ( gen_add2_insn ( dst , GEN_INT ( ( length - i ) + ( nelt_mode - nelt_v8 ) ) ) ) ; if ( ( length & <NUM_LIT> ) != <NUM_LIT> && align >= <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv8qi ( mem , reg ) ) ; } return true


<s> else { Register Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt


<s> if ( newElfFlags & llvm :: ELF :: EF_MIPS_PIC ) newElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; if ( newElfFlags & llvm :: ELF :: EF_MIPS_ARCH_ASE_M16 ) { error ( diag :: error_<ISA_LIT>_m16_unsupported ) << pInput . name ( ) ; return false ; } if ( ! oldElfFlags ) { oldElfFlags = newElfFlags ; return true ; } uint64_t newPic = newElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; uint64_t oldPic = oldElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; if ( ( newPic != <NUM_LIT> ) != ( oldPic != <NUM_LIT> ) ) warning ( diag :: warn_<ISA_LIT>_abicalls_linking ) << pInput . name ( ) ; if ( ! ( newPic & llvm :: ELF :: EF_MIPS_PIC ) ) oldElfFlags &= ~ llvm :: ELF :: EF_MIPS_PIC ; if ( newPic ) oldElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; uint64_t newArch = newElfFlags & llvm :: ELF :: EF_MIPS_ARCH ; uint64_t oldArch = oldElfFlags & llvm :: ELF :: EF_MIPS_ARCH ; if ( ! isIsaMatched (


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( llvm :: <STR_LIT> ( M , <STR_LIT>


<s> return CurDAG -> getTargetConstant ( ( uint64_t )


<s> unsigned Align = MFI -> getObjectAlignment ( FI ) ; assert ( ( - ( Offset + StackSize ) ) % Align == <NUM_LIT> ) ; Align = <NUM_LIT> ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += SlotSize ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> )


<s> const GlobalValue * GV = G ? G -> getGlobal ( ) : nullptr ; return DAG . getTarget ( ) . shouldAssumeDSOLocal ( * Mod , GV ) && ! dyn_cast_or_null < GlobalIFunc > ( GV ) ; } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; if ( GV -> isDeclaration ( ) && ! S -> hasRepresentedCsectSet ( ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ; auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( S -> getSymbolTableName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; S -> setRepresentedCsect ( Sec ) ; } MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV ) ; } return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ; const auto getFunctionEntryPointSymbol = [ & ] ( StringRef SymName ) { auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; return cast < MCSymbolXCOFF > ( Context . getOrCreateSymbol ( Twine ( <STR_LIT> )


<s> Register EntryReg = JumpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator I ( LEAMI ) ; for ( ++ I ; & * I != JumpMI ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == EntryReg ) RemovableAdd = & * I ; } if ( ! RemovableAdd ) return ; MachineBasicBlock :: iterator J ( RemovableAdd ) ; for ( ++ J ; & * J != JumpMI ; ++ J ) { for ( unsigned K = <NUM_LIT> , E = J -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = J -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == EntryReg ) return ; if ( MO . isUse ( ) && MO . getReg ( )


<s> int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; } return Result


<s> addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> CLI . setChain ( CurDAG -> getRoot ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * CurDAG -> getContext ( ) ) , CurDAG -> getExternalSymbol ( <STR_LIT> , TLI -> getPointerTy ( DL ) ) , std :: move ( Args ) ) ; const TargetLowering & TLI = CurDAG


<s> const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl (


<s> break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_core ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , invalid_extension . c_str ( ) , str ) ; aarch64_print_hint_for_extensions ( invalid_extension ) ; break ; default : gcc_unreachable (


<s> static unsigned int aarch64_call_properties ( aarch64_simd_builtin_datum * d ) { unsigned int flags = d -> flags ; if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( d -> mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ; return flags


<s> static SDValue LowerLabelRef ( SDValue HiPart , SDValue LoPart , bool isPIC , SelectionDAG & DAG ) { EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDLoc DL ( HiPart ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiPart , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ; if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DL , PtrVT ) , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> return isThumb ( STI ) && STI . getFeatureBits ( ) [


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT Op1VT = V1 . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned Index = cast < ConstantSDNode > ( V2 ) -> getZExtValue ( ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; if ( NumElts == <NUM_LIT> ) { EVT SubVT = <STR_LIT> ; SDValue SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT ) ; for ( unsigned i = Index , j = <NUM_LIT> ; i < ( Index + NumElts ) ; i ++ , j += <NUM_LIT> ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV1 , DAG . getIntPtrConstant ( i , dl ) ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT , SubVec , Elt , DAG . getConstant ( j , dl , <STR_LIT> ) ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT , SubVec , Elt , DAG . getConstant ( j + <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SubVec , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; } EVT SubVT = <STR_LIT> ( ElType , NumElts ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT ) ; for ( unsigned i = Index , j = <NUM_LIT> ; i < ( Index + NumElts ) ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV1 , DAG . getIntPtrConstant ( i ,


<s> const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; MCOperand MCRegOP = MCOperand :: createReg ( MO . getReg ( ) ) ; if ( ! isPositionIndependent ( ) ) { switch ( TM . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , MCRegOP , OutContext , STI ) ; break ; case CodeModel :: Medium : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand lo = create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , GOTLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , lo , MCRegOP , STI ) ; break ; } case CodeModel :: Large : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , RegO7 , OutContext , STI ) ; EmitADD ( * OutStreamer , MCRegOP , RegO7 , MCRegOP , STI ) ; } } return ; } MCSymbol * StartLabel = OutContext . createTempSymbol ( ) ; MCSymbol * EndLabel = OutContext . createTempSymbol ( ) ; MCSymbol * SethiLabel = OutContext . createTempSymbol ( ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; OutStreamer -> EmitLabel ( StartLabel ) ; MCOperand Callee = createPCXCallOP ( EndLabel , OutContext ) ; EmitCall ( * OutStreamer , Callee , STI ) ; OutStreamer -> EmitLabel ( SethiLabel ) ; MCOperand hiImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 , GOTLabel , StartLabel


<s> return mmix_function_arg_1 ( argsp , mode , type


<s> emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; if ( Imm12 == INT32_MIN ) Imm12 = <NUM_LIT> ; bool isAdd = true ; if ( Imm12 < <NUM_LIT> ) { Imm12 =


<s> SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( hasMFENCE ( Subtarget ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [


<s> MachineInstr & MI = * I ; unsigned FIOperandNum = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands ( )


<s> case 'b' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qidi ( (


<s> MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHSrc . isImm ( ) && MOpMBSrc . isImm ( ) && MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHSrc = MOpSHSrc . getImm ( ) ; uint64_t MBSrc = MOpMBSrc . getImm ( ) ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; uint64_t NewSH = SHSrc + SHMI ; uint64_t NewMB = MBSrc - SHMI ; if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++ ; if ( MRI -> use_nodbg_empty ( SrcReg ) ) { assert ( ! SrcMI -> hasImplicitDef ( ) && <STR_LIT> ) ; SrcMI -> eraseFromParent ( ) ; } return


<s> Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt )


<s> return emitCapFloatLoad < <STR_LIT> , <STR_LIT> > ( Subtarget


<s> return ( __m128i ) __builtin_ia32_expandqi128_maskz ( ( __v16qi ) __B , ( __v16qi ) _mm_setzero_si128 ( ) , ( __mmask16 )


<s> if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> if ( NumElems == <NUM_LIT> ) if ( SVOp -> getMaskElt ( <NUM_LIT> ) != - <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; } if ( HasXMMInt ) { if ( NumElems == <NUM_LIT> || ! <STR_LIT> ( SVOp ) ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; } assert ( VT != <STR_LIT> && <STR_LIT> ) ; return getTargetShuffleNode ( getSHUFPOpcode ( VT ) , dl , VT ,


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N1 . getOpcode ( ) != <STR_LIT> || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Vec0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Vec1 = N1 . getOperand ( <NUM_LIT> ) ; EVT VecVT0 = Vec0 . getValueType ( ) ; EVT VecVT1 = Vec1 . getValueType ( ) ; if ( VecVT0 . getSizeInBits ( ) != VecVT1 . getSizeInBits ( ) || VecVT0 . getScalarSizeInBits ( ) != VecVT1 . getScalarSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned VecOpc = VecVT0 . isFloatingPoint ( ) ? convertIntLogicToFPLogicOpcode ( Opc ) : Opc ; SDValue Result = DAG . getNode ( VecOpc , DL , VecVT0 , Vec0 , DAG . getBitcast ( VecVT0 ,


<s> if ( ! Subtarget . hasLSE ( ) && ! Subtarget . outlineAtomics ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; AtomicSDNode * AN = cast < AtomicSDNode > ( Op . getNode (


<s> char * temp_str ; return_str = ( char * ) xmalloc ( <NUM_LIT> ) ; temp_str = ( char * ) xmalloc ( <NUM_LIT> ) ; memset ( return_str , <NUM_LIT> , <NUM_LIT> ) ; while ( i <= last_reg_to_save ) { mask_str [ <NUM_LIT> ] = <NUM_LIT> ; if ( i <= SP_REGNUM ) { int j = <NUM_LIT> ; while ( j < MAX_COUNT && i <= SP_REGNUM ) { if ( save_regs [ i ] ) { if ( i == RETURN_ADDRESS_REGNUM ) ra_in_bitmask = <NUM_LIT> ; if ( j > <NUM_LIT> ) strcat ( mask_str , <STR_LIT> ) ; strcat ( mask_str , reg_names [ i ] ) ; ++ j ; } ++ i ; } } else { while ( i <= last_reg_to_save ) { if ( save_regs [ i ] ) { strcat ( mask_str , <STR_LIT> ) ; i = last_reg_to_save + <NUM_LIT> ; break ; } ++ i ; } } if ( strlen ( mask_str ) == <NUM_LIT> ) continue ; if ( push_or_pop == <NUM_LIT> ) { if ( crx_interrupt_function_p ( ) ) mpushpop_str ( temp_str , <STR_LIT> , mask_str ) ; else { if ( ra_in_bitmask ) { mpushpop_str ( temp_str , <STR_LIT> , mask_str ) ; ra_in_bitmask = <NUM_LIT> ; } else mpushpop_str ( temp_str , <STR_LIT> , mask_str ) ; } strcat ( return_str , temp_str ) ; } else { if ( crx_interrupt_function_p ( ) ) mpushpop_str ( temp_str , <STR_LIT> , mask_str ) ; else mpushpop_str ( temp_str , <STR_LIT> , mask_str ) ; strcat ( temp_str ,


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( ) const { assert ( GISel && <STR_LIT> ) ; return GISel -> getLegalizerInfo ( )


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> | OpFlags ) ; if ( ! Subtarget -> isTargetILP32 ( ) ) return ResultReg ; Register Result64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( Result64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; return Result64 ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | OpFlags ) . addImm ( <NUM_LIT> ) ; } return ResultReg


<s> Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( * MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta ,


<s> rtx op = PATTERN ( consumer ) ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , <NUM_LIT>


<s> bool mayUseThunk ( const MachineFunction & MF ) { ComdatThunks &= ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsNoComdat ( ) ; return MF . getSubtarget < <ISA_LIT>Subtarget > ( )


<s> return __builtin_mve_vorrq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> static rtx rx_expand_int_builtin_1_arg ( rtx arg , rtx target , rtx ( * gen_func ) ( rtx , rtx ) , bool mem_ok ) { if ( ! REG_P ( arg ) ) if ( ! mem_ok || ! MEM_P ( arg ) ) arg = force_reg ( SImode , arg ) ; if ( target == NULL_RTX || ! REG_P ( target ) ) target = gen_reg_rtx ( SImode ) ; emit_insn ( gen_func ( target


<s> if ( ! RecordVPTBlocks ( MI ) ) { CannotTailPredicate = true ; return ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; uint64_t Flags = MCID .


<s> static void ia64_emit_insn_before ( rtx insn , rtx_insn * before ) { emit_insn_before ( insn , before


<s> TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; default : return false ; } if ( CommuteIdx != - <NUM_LIT> ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: unfoldCallAndJumpLoads ( MachineFunction & MF ) { for ( MachineBasicBlock & MBB : MF ) for ( auto MII = MBB . instr_begin ( ) , MIE = MBB . instr_end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( ! MI . isCall ( ) && ! MI . isBranch ( ) ) continue ; if ( ! MI . mayLoad ( ) ) continue ; switch ( MI . getOpcode ( ) ) { default : { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? <NUM_LIT> : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV (


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs


<s> MIB . addReg ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt ) ; return true


<s> bool <ISA_LIT>ElimCompare :: convertToLoadAndTest ( MachineInstr & MI ) { unsigned Opcode = TII -> getLoadAndTest ( MI . getOpcode ( ) ) ; if ( ! Opcode ) return false ; MI . setDesc ( TII ->


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . addressReg ( <STR_LIT> ) ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx .


<s> return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'N' : case 'G' : case 'L' : case 'M' : return C_Immediate ; case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'Y' : switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass


<s> static const unsigned SpillOffsetTable [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } } ; RegSpillOffsets . grow (


<s> const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; unsigned FrameDestroyOpcode = TII -> getCallFrameDestroyOpcode ( ) ; assert ( I -> getOpcode ( ) == TII -> getCallFrameSetupOpcode ( ) ) ; MachineBasicBlock :: iterator FrameSetup = I ++ ; unsigned int MaxAdjust = FrameSetup -> getOperand ( <NUM_LIT> ) . getImm ( ) / <NUM_LIT> ; if ( ! MaxAdjust ) { Context . NoStackParams = true ; return ; } while ( I -> getOpcode ( ) == <STR_LIT> ) ++ I ; if ( ! I -> isCopy ( ) || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; Context . SPCopy = I ++ ; StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MaxAdjust > <NUM_LIT> ) Context . MovVector . resize ( MaxAdjust , nullptr ) ; do { int Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> &&


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutStreamer . getContext ( )


<s> if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV ) ; return <NUM_LIT>


<s> unsigned NumElems = VTy -> getNumElements ( ) ; unsigned EltSize = VTy -> getScalarSizeInBits ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; InstructionCost VectorCost = NumElems * LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; InstructionCost ScalarCost = NumElems * LT . first + BaseT :: getScalarizationOverhead ( VTy , true , false ) + BaseT :: getScalarizationOverhead ( VTy , false , true ) ; if ( EltSize < <NUM_LIT> || Alignment < EltSize / <NUM_LIT> ) return ScalarCost ; unsigned ExtSize = EltSize ; if ( I != nullptr ) { if ( ( I -> getOpcode ( ) == Instruction :: Load || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && I -> hasOneUse ( ) ) { const User * Us = * I -> users ( ) . begin ( ) ; if ( isa < ZExtInst > ( Us ) || isa < SExtInst > ( Us ) ) { unsigned TypeSize = cast < Instruction > ( Us ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( TypeSize == <NUM_LIT> && ( EltSize == <NUM_LIT> || EltSize == <NUM_LIT> ) ) || ( TypeSize == <NUM_LIT> && EltSize == <NUM_LIT> ) ) && TypeSize * NumElems == <NUM_LIT> ) { ExtSize = TypeSize ; } } } TruncInst * T ; if ( ( I -> getOpcode ( ) == Instruction :: Store || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && ( T = dyn_cast < TruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) { unsigned TypeSize = T -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( EltSize == <NUM_LIT> && TypeSize == <NUM_LIT> ) || ( EltSize == <NUM_LIT> && ( TypeSize == <NUM_LIT> || TypeSize == <NUM_LIT> ) ) ) && TypeSize * NumElems == <NUM_LIT> ) ExtSize = TypeSize ; } } if ( ExtSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( ExtSize == <NUM_LIT> )


<s> bool <ISA_LIT>TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ; if ( ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT

!= <STR_LIT> && ResVT != <STR_LIT> ) return true ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , const Instruction * I ) { return TTI


<s> if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Cond , BranchInstrs [ <NUM_LIT> ] ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) && ( FalseBB == & Dst ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Uncond , BranchInstrs [ <NUM_LIT> ] ) ; return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr


<s> int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) return Error ( EndLoc , <STR_LIT> ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! RC -> contains ( EndReg ) ) return Error ( EndLoc , <STR_LIT> ) ; if ( get<ISA_LIT>RegisterNumbering ( Reg ) > get<ISA_LIT>RegisterNumbering ( EndReg ) ) return Error ( EndLoc , <STR_LIT> ) ; while ( Reg != EndReg ) { Reg = getNextRegister ( Reg ) ; Registers . push_back ( std :: pair < unsigned , SMLoc > ( Reg , RegLoc ) ) ; } continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; const AsmToken RegTok = Parser . getTok ( ) ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; bool isQReg = false ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { Reg = getDRegFromQReg ( Reg ) ; isQReg = true ; } if ( ! RC -> contains ( Reg ) ) return Error ( RegLoc , <STR_LIT> ) ; if ( get<ISA_LIT>RegisterNumbering ( Reg ) < get<ISA_LIT>RegisterNumbering ( OldReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) Warning ( RegLoc , <STR_LIT> ) ; else return Error ( RegLoc , <STR_LIT> ) ; } if ( get<ISA_LIT>RegisterNumbering ( Reg ) == get<ISA_LIT>RegisterNumbering ( OldReg ) ) { Warning ( RegLoc , <STR_LIT> + RegTok . getString ( ) + <STR_LIT> ) ; continue ; } if ( RC != & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] && Reg != OldReg + <NUM_LIT> ) return


<s> if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue HiDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc ) ; DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DescAddr , LoDesc ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , DTPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff , DTPOff ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue HiDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc ) ; DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DescAddr ,


<s> MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( VecVT . getVectorNumElements ( ) < <NUM_LIT> ) { VecVT = <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( VecVT ) ,

Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> return ( __m512i ) __builtin_ia32_pabsq512_mask ( ( __v8di ) __A , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8


<s> const <ISA_LIT>MCExpr * Expr = cast < <ISA_LIT>MCExpr > ( ImmOp . getExpr ( ) ) ; unsigned FixupKind ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOT_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT> ) ; FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT>


<s> if ( P . hasDSPR2 ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMSA ( ) ) ASESet |= <STR_LIT> ; if ( P . inMicro<ISA_LIT>Mode ( ) ) ASESet |= <STR_LIT> ; if ( P . in<ISA_LIT>16Mode ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMT ( ) ) ASESet |= <STR_LIT> ; if ( P . hasCRC ( ) ) ASESet |= <STR_LIT> ; if ( P . hasVirt ( ) )


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , IsThumb ( IsThumb ) { EHReset ( )


<s> void printbytemem ( const MCInst * MI , unsigned OpNo


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , CC ) ) ; } return SDValue ( ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG ) ) return V ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( C -> isAllOnesValue ( ) || C -> isNullValue ( ) ) return SDValue


<s> if ( UserI -> getOperand ( i ) == FoldedValue ) continue ; if ( Instruction * OtherOp = dyn_cast < Instruction > ( UserI -> getOperand ( i ) ) ) { LoadInst * OtherLoad = dyn_cast < LoadInst > ( OtherOp ) ; if ( ! OtherLoad && ( isa < TruncInst > ( OtherOp ) || isa < SExtInst > ( OtherOp ) || isa < ZExtInst > ( OtherOp ) ) ) OtherLoad = dyn_cast < LoadInst > ( OtherOp -> getOperand ( <NUM_LIT> ) ) ; if ( OtherLoad && isFoldableLoad ( OtherLoad , FoldedValue ) ) return i == <NUM_LIT> ; } } return <NUM_LIT> ; } } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ( ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> ) || ST -> hasVectorEnhancements2 ( ) ) && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin (


<s> void <ISA_LIT>AsmPrinter :: customEmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCSubtargetInfo STI = getSubtargetInfo ( ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer -> EmitInstruction ( TmpInst


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , Known2 ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Subtarget -> isTargetILP32 ( ) ) break ; Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero |= APInt ( Known . getBitWidth ( ) , <NUM_LIT> ) ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known .


<s> return __builtin_mve_vrshrq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> return __builtin_aarch64_sqdmlsl_nv2si ( __a ,


<s> gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( get_ix86_builtin ( IX86_BUILTIN_CPU_INIT ) , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = <NUM_LIT> ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority


<s> } BuildMI ( MBB , InsertBefore , DebugLoc ( ) , MCID ) . addReg ( DestReg0 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx0 ) . addReg ( DestReg1 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx1 ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> LoadSDNode * InputLoad = dyn_cast < LoadSDNode > ( Input ) ; if ( InputLoad && InputLoad -> getExtensionType ( ) == <STR_LIT> ) return Input ; ConstantSDNode * InputConst = dyn_cast < ConstantSDNode > ( Input ) ; if ( InputConst || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> ) return Input ;


<s> case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( i ) <= <NUM_LIT> ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else sparc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_CC : default : if ( i == ( int ) CCFPmode || i == ( int ) CCFPEmode ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) CCFP_MODE ; else if ( i == ( int ) CCmode || i == ( int ) CC_NOOVmode || i == ( int ) CCXmode || i == ( int ) CCX_NOOVmode ) sparc_mode_class [ i ] = <NUM_LIT> << ( int ) CC_MODE ; else sparc_mode_class [ i ] = <NUM_LIT> ; break ; } } if ( TARGET_ARCH64 ) hard_regno_mode_classes =


<s> bool isMem80 ( ) const { return Kind == Memory && ( ! Mem .


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegNum ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> )


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY )

, ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } named_section_flags ( section , <NUM_LIT> ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE /


<s> bool isMemUImm12Offset ( ) const { if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> ||

Memory . Alignment != <NUM_LIT> ) return false ;


<s> Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; } uint32_t OtherHalf = <NUM_LIT> ; bool NeedsPair = true ; switch ( Type ) { default : NeedsPair = false ; break ; case MachO :: <ISA_LIT>_RELOC_LO14 : if ( FixedValue & <NUM_LIT> ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> ) ) ; case MachO :: <ISA_LIT>_RELOC_LO16 : OtherHalf = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16 : OtherHalf = FixedValue & <NUM_LIT> ; FixedValue = ( ( FixedValue >> <NUM_LIT> ) + ( ( FixedValue & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HI16 : OtherHalf = FixedValue & <NUM_LIT> ; FixedValue = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; } MachO :: any_relocation_info MRE ; if ( NeedsPair )


<s> State . PrefixSaved = <NUM_LIT> ; State . PrefixPass = false ; State . EmitRaw =


<s> if ( DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1qv16qi && DECL_MD_FUNCTION_CODE ( fndecl ) < ARM_BUILTIN_MVE_BASE


<s> bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = & MF . front ( ) ; bool Changed = false ; for ( MachineBasicBlock * BB : depth_first_ext ( Entry , Processed ) ) Changed |= processBasicBlock ( MF , * BB ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineBasicBlock & BB : MF ) if ( Processed . insert ( & BB ) . second ) Changed


<s> MCAsmBackend * llvm :: create<ISA_LIT>LEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU


<s> const InstrItineraryData * II = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer (


<s> if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeSubeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAddSub = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAddSub = nullptr ; if ( ( AddeSubeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeSubeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAddSub = & AddeSubeOp1 ; else HiAddSub = & AddeSubeOp0 ; if ( AddcSubcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp0 ; LowAddSub = & AddcSubcOp1 ; } if ( AddcSubcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp1 ; LowAddSub = & AddcSubcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( AddcSubcNode == HiAddSub -> getNode ( ) || AddcSubcNode -> isPredecessorOf ( HiAddSub -> getNode ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; if ( Subtarget -> hasV6Ops ( ) && Subtarget -> hasDSP ( ) && Subtarget -> useMulOps ( ) && FinalOpc == <STR_LIT> && ! AddeSubeNode -> hasAnyUseOfValue ( <NUM_LIT> ) && LowAddSub -> getNode ( ) -> getOpcode ( ) == <STR_LIT> && static_cast < ConstantSDNode * > ( LowAddSub -> getNode ( ) ) -> getZExtValue ( ) == <NUM_LIT> ) { Ops . push_back ( * HiAddSub ) ; if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) { FinalOpc = <STR_LIT> ; } else { FinalOpc = <STR_LIT> ; } SDValue NewNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , <STR_LIT> , Ops ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , NewNode ) ; return SDValue ( AddeSubeNode , <NUM_LIT> ) ; } else if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; Ops . push_back ( * LowAddSub ) ; Ops . push_back ( * HiAddSub ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcSubcNode , <NUM_LIT> ) , LoMLALResult ) ; return SDValue ( AddeSubeNode , <NUM_LIT>


<s> void EmitARM64WinCFISaveFRegPX ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT>


<s> AttributeSet FnAttrs = MF -> getFunction ( ) -> getAttributes ( ) ; ChangeTo<ISA_LIT>16 = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; ChangeToNo<ISA_LIT>16 = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( ChangeTo<ISA_LIT>16 & ChangeToNo<ISA_LIT>16 ) && <STR_LIT> ) ; if ( ChangeTo<ISA_LIT>16 ) { if ( PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = <ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = true ; setHelperClasses<ISA_LIT>16 ( ) ; return ; } else if ( ChangeToNo<ISA_LIT>16 ) { if ( ! PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = No<ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = false ; setHelperClasses<ISA_LIT>SE ( ) ; return ; } else { if ( OverrideMode == NoOverride ) return ; OverrideMode = NoOverride ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( in<ISA_LIT>16Mode ( ) && ! PreviousIn<ISA_LIT>16Mode ) { setHelperClasses<ISA_LIT>16 ( ) ; PreviousIn<ISA_LIT>16Mode =


<s> SDValue Bits = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bits ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return FP ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ext64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; MachineMemOperand MO ( PseudoSourceValue :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; SDValue Store = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Ext64 , FIdx , DAG . getMemOperand ( MO ) ) ; SDValue Ld = DAG . getLoad ( <STR_LIT> , dl , Store , FIdx , NULL , <NUM_LIT> ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ld ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return FP


<s> if ( Subtarget . isTargetWin64 ( ) || Subtarget . isTargetPS4 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , false , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; initAsmInfo (


<s> Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . ParseParenExpression ( Disp , ExprEnd ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) return <NUM_LIT> ; if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction &


<s> set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { rtx set ; if ( ! INSN_P ( insn ) ) continue ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return <NUM_LIT> ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; int i ; int retval = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code =


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) && ! Subtarget -> hasAVX512 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode


<s> if ( ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) || ( ix86_function_regparm ( type1 , NULL ) != ix86_function_regparm ( type2 , NULL ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT>

, TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ;


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> static rtx rs6000_expand_mtfsf_builtin ( enum insn_code icode , tree exp ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx


<s> SDLoc DL ( ADDENode ) ; SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoIdx = CurDAG -> getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue LoOut = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , MAdd , LoIdx ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT>


<s> bool isATBitsAsHint ( ) const { return false


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx


<s> if ( SDValue HOp = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return HOp ; return SDValue


<s> if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; APInt Lg2Mask = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , Lg2 ) ; SDValue Pow2MinusOne = DAG . getConstant ( Lg2Mask , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CMov . getNode ( ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CMov

, DAG . getConstant ( Lg2 , DL , <STR_LIT> ) ) ;


<s> MachineBasicBlock :: iterator I = MBB . begin ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned <ISA_LIT>16SPAliasReg = <ISA_LIT>FI ->


<s> Function * Func = <STR_LIT> ( M , Id ) ; return Builder . CreateCall ( Func


<s> static void moxie_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args


<s> label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; if ( flag_rounding_math ) { ix86_sse_copysign_to_positive ( TWO52 , TWO52 , res , mask ) ; xa = res ; } xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) xa = ix86_expand_sse_fabs ( xa , NULL ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label ( label


<s> MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent ( ) ; return JoinMBB


<s> SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 .


<s> else cond = NULL_RTX ; if ( subtargets || code == SET || ( GET_CODE ( target ) == REG && GET_CODE ( source ) == REG && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , <NUM_LIT> , <NUM_LIT> ) > arm_constant_limit + ( code != SET ) ) ) { if ( code == SET ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , GEN_INT ( val ) ) ) ; return <NUM_LIT>


<s> if ( REGNO ( base ) == REGNO ( operands [ <NUM_LIT> ] ) ) reversed = true ; dead = true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) reversed = true ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( in , operands [ <NUM_LIT> ] , reversed , dead ) ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( out , operands [ <NUM_LIT> ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_DEC ) ) \ REG_NOTES ( INSN ) = gen_rtx_EXPR_LIST ( REG_INC , \ XEXP ( XEXP ( EXP , <NUM_LIT> ) , <NUM_LIT> ) , \ REG_NOTES ( INSN ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ <NUM_LIT> ] , in [ <NUM_LIT> ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in


<s> void addRegAsmOperands ( MCInst & Inst , unsigned N ) const { Inst . addOperand ( MCOperand :: CreateReg


<s> EmitValue ( PersonalityRef , <NUM_LIT> ) ; } assert ( ( Opcodes . size ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != Opcodes . size ( ) ; I += <NUM_LIT> ) { uint64_t Intval = Opcodes [ I ] | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> ; EmitIntValue ( Intval , <NUM_LIT> ) ; } if ( NoHandlerData && ! Personality ) EmitIntValue ( <NUM_LIT> ,


<s> double res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT>


<s> mips_rewrite_small_data_1 ( & pattern


<s> void <ISA_LIT>AsmPrinter :: emitCallInstruction ( const MachineInstr * MI ) { assert ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCSubtargetInfo STI = getSubtargetInfo ( ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) , STI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT>


<s> assert ( Op -> Reg . Kind == rk_FloatReg ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return nullptr ; Op -> Reg . RegNum = DoubleRegs [ regIdx / <NUM_LIT>


<s> psrlh_s ( int16x4_t s , uint8_t amount ) { return __builtin_loongson_psrlh_s ( s ,


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && ( op7_4 >= <NUM_LIT> && op7_4 <= <NUM_LIT> ) ) return true ; return false


<s> const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>IndirectThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass (


<s> return ( int16x8_t ) __builtin_neon_vcvtsv8hf (


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain_id ) ; convert_registers ( ) ; EXECUTE_IF_SET_IN_BITMAP ( insns , <NUM_LIT> , id , bi ) { rtx_insn * insn = DF_INSN_UID_GET ( id ) -> insn ; convert_insn_common (


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStandardEncoding ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM


<s> SDLoc dl ( V . getNode ( ) ) ; SDValue VLo = DAG . getAnyExtOrTrunc ( V , dl , <STR_LIT> ) ; SDValue VHi = DAG . getAnyExtOrTrunc ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , dl , <STR_LIT> ) ; SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> , dl ,


<s> if ( Subtarget -> hasInt256 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; return true


<s> if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else { assert ( RC == <STR_LIT> ) ; Opc = <STR_LIT> ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC ,


<s> BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addReg ( SrcReg )


<s> return ( __m128i ) __builtin_ia32_pmovusqd128_mask ( ( __v2di ) __A , ( __v4si )


<s> return ( vector signed int ) __builtin_altivec_vsraw ( ( vector signed int ) a1 ,


<s> static void loongarch_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned int argno ) { tree arg ; rtx value ; arg = CALL_EXPR_ARG ( exp , argno


<s> static MCRelocationInfo * create<ISA_LIT>MCRelocationInfo ( StringRef TT , MCContext & Ctx ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return create<ISA_LIT>MachORelocationInfo ( Ctx ) ; return llvm :: createMCRelocationInfo ( TT , Ctx


<s> SDValue N10Elt = N10 . getOperand ( i ) ; SDValue N11Elt = N11 . getOperand ( i ) ; if ( N00Elt . getOpcode ( ) != <STR_LIT> || N01Elt . getOpcode ( ) != <STR_LIT> || N10Elt . getOpcode ( ) != <STR_LIT> || N11Elt . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * ConstN00Elt = dyn_cast < ConstantSDNode > ( N00Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN01Elt = dyn_cast < ConstantSDNode > ( N01Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN10Elt = dyn_cast < ConstantSDNode > ( N10Elt . getOperand ( <NUM_LIT> ) ) ; auto * ConstN11Elt = dyn_cast < ConstantSDNode > ( N11Elt . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstN00Elt || ! ConstN01Elt || ! ConstN10Elt || ! ConstN11Elt ) return SDValue ( ) ; unsigned IdxN00 = ConstN00Elt -> getZExtValue ( ) ; unsigned IdxN01 = ConstN01Elt -> getZExtValue ( ) ; unsigned IdxN10 = ConstN10Elt -> getZExtValue ( ) ; unsigned IdxN11 = ConstN11Elt -> getZExtValue ( ) ; if ( IdxN00 > IdxN10 ) { std :: swap ( IdxN00 , IdxN10 ) ; std :: swap ( IdxN01 , IdxN11 ) ; } if ( IdxN00 != <NUM_LIT> * i || IdxN10 != <NUM_LIT> * i + <NUM_LIT> || IdxN01 != <NUM_LIT> * i || IdxN11 != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; SDValue N00In = N00Elt . getOperand ( <NUM_LIT> ) ; SDValue N01In = N01Elt . getOperand ( <NUM_LIT> ) ; SDValue N10In = N10Elt . getOperand ( <NUM_LIT> ) ; SDValue N11In = N11Elt . getOperand ( <NUM_LIT> ) ; if ( ! In0 ) { In0 = N00In ; In1 = N01In ; } if ( In0 != N00In ) std :: swap ( N00In , N01In ) ; if ( In0 != N10In ) std :: swap ( N10In , N11In ) ; if ( In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In ) return SDValue ( ) ; } auto PMADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { EVT InVT = Ops [ <NUM_LIT> ] . getValueType ( ) ; assert ( InVT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( InVT == Ops [ <NUM_LIT> ] . getValueType ( ) && <STR_LIT> ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , DL , VT , { In0


<s> for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i +


<s> else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII

-> get ( BtOpc ) ) . addMBB ( target ) ;


<s> setLeastSignificantFirst ( VRegs ) ; if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMImm ( const MCExpr * Val , bool Flag , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MImmOp ) ; Op -> MImm .


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get ( <STR_LIT> ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> || Reg == <STR_LIT> )


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( <STR_LIT>


<s> case <STR_LIT> ## SUFFIX : \ case <STR_LIT> ## SUFFIX : switch ( ReductionID ) { <ISA_LIT>C_VP_CASE ( add ) <ISA_LIT>C_VP_CASE ( and ) <ISA_LIT>C_VP_CASE ( or ) <ISA_LIT>C_VP_CASE ( xor ) <ISA_LIT>C_VP_CASE


<s> for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = Elt . getConstantOperandVal ( <NUM_LIT> ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = ( SrcVector == V1 ) && ( Current . getConstantOperandVal ( <NUM_LIT> ) == i ) ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 =


<s> SDValue <ISA_LIT>TargetLowering :: LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = getPointerTy (


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( TRI -> hasBasePointer ( DAG . getMachineFunction ( ) ) && TRI -> getBaseRegister ( ) == <STR_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src


<s> Desc . Regs . push_back ( op . getReg ( ) ) ; break ; } if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return Optional < BlockBRNZ > ( ) ; } if ( Desc . Regs . size ( ) != <NUM_LIT> ) { return Optional < BlockBRNZ > ( ) ; } const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) { Desc . Regs . push_back ( MI -> getOperand (


<s> const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue ReturnAddress ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } SDNode * St ; if ( Subtarget -> hasPAuth ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else { SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ; St = DAG . getMachineNode ( <STR_LIT> , DL , VT , Chain ) ; } return SDValue ( St , <NUM_LIT>


<s> Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) .

addReg ( Op1Reg ) . addMBB ( FalseMBB ) . addReg ( Op2Reg ) . addMBB ( TrueMBB ) ;


<s> case Instruction :: Ret : return <ISA_LIT>SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL


<s> if ( flag_print_asm_name ) asm_fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( INSN_UID ( insn ) )


<s> static DecodeStatus DecodeAddrMode7Operand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { return DecodeGPRRegisterClass ( Inst , Val


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { VMask , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> )


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( <STR_LIT> ) : ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) ,


<s> uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; const unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) >


<s> unsigned AddrBase = IsStore ; unsigned RegOp = IsStore ? <NUM_LIT> : <NUM_LIT> ; unsigned AddrOp = AddrBase + <NUM_LIT> ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( RegOp ) . isReg ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && ( Inst . getOperand ( AddrOp ) . isExpr ( ) || Inst . getOperand ( AddrOp ) . isImm ( ) ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( RegOp ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) return ; bool Absolute = true ; if ( Inst . getOperand ( AddrOp ) . isExpr ( ) ) { const MCExpr * MCE = Inst . getOperand ( AddrOp ) . getExpr ( ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( MCE ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) Absolute = false ; } if ( Absolute && ( Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return ; MCOperand Saved = Inst . getOperand (


<s> if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerVectorShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerVectorShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , Op1 . getDebugLoc ( ) , VT , Op1 . getOperand ( <NUM_LIT>

) , DAG . getConstant ( ~ XorC , VT ) ) ;


<s> Optional < unsigned > Ret = ELFAttrs :: attrTypeFromString ( Name , <STR_LIT> ( ) ) ; if ( ! Ret . hasValue ( ) ) { Error ( TagLoc , <STR_LIT> + Name ) ; return false ; } Tag = Ret . getValue ( ) ; Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( check ( ! CE , TagLoc , <STR_LIT> ) ) return true ; Tag = CE -> getValue ( ) ; } if ( Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; StringRef StringValue = <STR_LIT> ; bool IsStringValue = false ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = false ; if ( Tag == <STR_LIT> || Tag == <STR_LIT> ) IsStringValue = true ; else if ( Tag == <STR_LIT> ) { IsStringValue = true ; IsIntegerValue = true ; } else if ( Tag < <NUM_LIT> || Tag % <NUM_LIT> == <NUM_LIT> ) IsIntegerValue = true ; else if ( Tag % <NUM_LIT> == <NUM_LIT> ) IsStringValue = true ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } if ( Tag == <STR_LIT> ) { if ( Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; } if ( IsStringValue ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue && IsStringValue ) { assert ( Tag == <STR_LIT> ) ; getTargetStreamer ( ) . emitIntTextAttribute ( Tag , IntegerValue , StringValue ) ; } else if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( IsStringValue ) getTargetStreamer ( ) . emitTextAttribute (


<s> e0 = gen_reg_rtx ( SFmode ) ; e1 = gen_reg_rtx ( SFmode ) ; y1 = gen_reg_rtx ( SFmode ) ; u0 = gen_reg_rtx ( SFmode ) ; v0 = gen_reg_rtx ( SFmode ) ; one = force_reg ( SFmode , CONST_DOUBLE_FROM_REAL_VALUE ( dconst1 , SFmode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( SFmode , gen_rtvec ( <NUM_LIT> , d ) , UNSPEC_FRES ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MINUS ( SFmode , one , gen_rtx_MULT ( SFmode , d , x0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_PLUS ( SFmode , gen_rtx_MULT ( SFmode


<s> if ( TARGET_SIMD && aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2 ) ) return true ; return false


<s> if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT .

getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return <STR_LIT> ;


<s> return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ;


<s> inline vector signed int vec_sra ( vector signed int a1 , vector unsigned int


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory .


<s> if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) return <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && ! ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ) return <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG


<s> SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( )

. getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ;


<s> const char * <ISA_LIT>GNUInfo :: entry


<s> return ( uint32x2x2_t ) { vtrn1_u32 ( a , b ) , vtrn2_u32 (