<s> if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i

!= NumVecs ; ++ i , Offset += NumSubElts ) {


<s> return ( t == TYPE_FMULS ) || ( t == TYPE_FMULD )


<s> return SupportsCU ? generateCompactUnwindEncodingImpl ( Instrs )


<s> tree arg , decl = * node ; init_idents ( ) ; arg = TREE_VALUE ( args ) ; if ( arg == small_ident1 || arg == small_ident2 ) { addr_area = ADDR_AREA_SMALL ; } else { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } switch ( TREE_CODE ( decl ) ) { case VAR_DECL : if ( ( DECL_CONTEXT ( decl ) && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL ) && ! TREE_STATIC ( decl ) ) { error ( <STR_LIT> <STR_LIT> , decl ) ; * no_add_attrs = true ; } area = ia64_get_addr_area (


<s> if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } Base = N ; if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true


<s> int nregs ; if ( arg . mode == BLKmode && arg . type ) size = int_size_in_bytes ( arg . type ) ; else size = GET_MODE_SIZE ( arg . mode ) . to_constant ( ) ; if ( arg . aggregate_type_p ( ) ) size = int_size_in_bytes ( arg . type ) ; if ( size < <NUM_LIT> ) return


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true


<s> static SDValue performSUBECombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> &&

selectMSUB ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> break ; case V16QImode : return expand_vec_perm_even_odd_pack ( d ) ; case V16HImode : case V32QImode : return expand_vec_perm_even_odd_pack ( d ) ; case V4DImode : if ( ! TARGET_AVX2 ) { struct expand_vec_perm_d d_copy = * d ; d_copy . vmode = V4DFmode ; if ( d -> testing_p ) d_copy . target = gen_lowpart ( V4DFmode , d -> target ) ; else d_copy . target = gen_reg_rtx ( V4DFmode ) ; d_copy . op0 = gen_lowpart ( V4DFmode , d -> op0 ) ; d_copy . op1 = gen_lowpart ( V4DFmode , d -> op1 ) ; if ( expand_vec_perm_even_odd_1 ( & d_copy , odd ) ) { if ( ! d -> testing_p ) emit_move_insn ( d -> target , gen_lowpart ( V4DImode , d_copy . target ) ) ; return true ; } return false ; } if ( d -> testing_p ) break ; t1 = gen_reg_rtx ( V4DImode ) ; t2 = gen_reg_rtx ( V4DImode ) ; emit_insn ( gen_avx2_permv2ti ( t1 , d -> op0 , d -> op1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_avx2_permv2ti ( t2 , d -> op0 , d -> op1 , GEN_INT ( <NUM_LIT> ) ) ) ; if ( odd ) t3 = gen_avx2_interleave_highv4di ( d -> target , t1 , t2 ) ; else t3 = gen_avx2_interleave_lowv4di ( d -> target , t1 , t2 ) ; emit_insn ( t3 ) ; break ; case V8SImode : if ( ! TARGET_AVX2 ) { struct expand_vec_perm_d d_copy = * d ; d_copy . vmode = V8SFmode ; if ( d -> testing_p ) d_copy . target = gen_lowpart ( V8SFmode , d -> target ) ; else d_copy . target = gen_reg_rtx ( V8SFmode ) ; d_copy . op0 = gen_lowpart ( V8SFmode , d -> op0 ) ; d_copy . op1 = gen_lowpart ( V8SFmode , d -> op1 ) ; if ( expand_vec_perm_even_odd_1 ( & d_copy , odd ) ) { if ( ! d -> testing_p ) emit_move_insn ( d -> target , gen_lowpart ( V8SImode , d_copy . target ) ) ; return true ; } return false ; } if ( d -> testing_p ) break ; t1 = gen_reg_rtx ( V8SImode ) ; t2 = gen_reg_rtx ( V8SImode ) ; t3 = gen_reg_rtx ( V4DImode ) ; t4 = gen_reg_rtx ( V4DImode ) ; t5 = gen_reg_rtx ( V4DImode ) ; emit_insn ( gen_avx2_permv2ti ( t3 , gen_lowpart ( V4DImode , d -> op0 ) , gen_lowpart ( V4DImode , d -> op1 ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_avx2_permv2ti ( t4 , gen_lowpart ( V4DImode , d -> op0 ) , gen_lowpart ( V4DImode , d -> op1 ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_avx2_pshufdv3 ( t1 , gen_lowpart ( V8SImode , t3 ) , GEN_INT (


<s> SDValue SRL = OR . getOperand ( <NUM_LIT> ) ; SDValue SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) { SRL = OR . getOperand ( <NUM_LIT> ) ; SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) return false ; } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand (


<s> return ( __m128i ) __builtin_ia32_vec_set_v16qi ( ( __v16qi )


<s> MI . addOperand ( MCOperand :: CreateImm ( slice


<s> bool enableMultipleCopyHints ( ) const override { return true


<s> bool isAnyReg ( ) const { return ( isReg ( ) || isImm ( <NUM_LIT>


<s> NumBytesToCreateFrame = <NUM_LIT> ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ ] ( outliner :: Candidate & C ) { return C . LRU . available ( <STR_LIT> ) ; } ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumBytesForCall = <NUM_LIT> ; NumBytesToCreateFrame = <NUM_LIT> ; } if ( std :: any_of ( RepeatedSequenceLocs [ <NUM_LIT> ] . front ( ) , RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumBytesToCreateFrame += <NUM_LIT> ; else if ( FrameID != MachineOutlinerThunk && FrameID != MachineOutlinerTailCall && RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isCall ( ) ) NumBytesToCreateFrame


<s> } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { int SYSmValue = getMClassRegisterMask ( SpecialReg , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops


<s> return __aarch64_vset_lane_any ( * __src


<s> const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass (


<s> for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = InVec [ i ] ; return ; } for ( unsigned j = <NUM_LIT> ; j < VecElems / <NUM_LIT> ; j ++ ) for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i + j * <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ j * <NUM_LIT> + i ] , InVec [ j * <NUM_LIT> + i + <NUM_LIT> ] , makeArrayRef ( Concat , <NUM_LIT> ) ) ; if ( VecElems ==


<s> SectionKind GOKind = getObjFileLowering ( ) . getKindForGlobal ( GO , TM ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GO , GOKind , TM ) ) ; Align GOAlign = getGVAlignment ( GO , GO -> getParent ( ) -> getDataLayout ( ) ) ; if ( GOAlign > Csect -> getAlignment ( ) ) Csect -> setAlignment ( GOAlign ) ; } ; for ( const auto & G : M .

globals ( ) ) setCsectAlignment ( & G ) ;


<s> dbgs ( ) << <STR_LIT> << CurGroupDbg << <STR_LIT> ; dbgs ( ) << <STR_LIT> << CurrGroupSize << <STR_LIT> << ( CurrGroupSize > <NUM_LIT>


<s> EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { if ( useSVEForFixedLengthVectorVT ( VT , Subtarget -> useSVEForFixedLengthVectors ( ) ) ) return LowerFixedLengthVectorStoreToSVE ( Op , DAG ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) && VT == <STR_LIT> && MemVT == <STR_LIT> ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { return LowerStore128 ( Op , DAG ) ; } else if ( MemVT == <STR_LIT> ) { SDValue Value = StoreNode -> getValue ( ) ; assert ( Value -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Chain = StoreNode -> getChain ( ) ; SDValue Base = StoreNode -> getBasePtr ( ) ; EVT PtrVT = Base . getValueType (


<s> bool noreturn_p ; if ( nds32_long_call_p ( symbol ) ) strcpy ( pattern , long_call ) ; else strcpy ( pattern , call ) ; if ( flag_pic && CONSTANT_P ( symbol ) && ! nds32_symbol_binds_local_p ( symbol ) ) strcat ( pattern , <STR_LIT> ) ; if ( align_p ) strcat ( pattern , <STR_LIT> ) ; noreturn_p = find_reg_note ( insn , REG_NORETURN , NULL_RTX


<s> nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 ) { mode = V16QImode ; gen_func = gen_movmisalignv16qi ; } else { mode = V8QImode ; gen_func = gen_movmisalignv8qi ; } nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , <NUM_LIT> ) ) ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_const_vec_duplicate ( mode , GEN_INT ( v ) ) ; emit_move_insn ( reg , val_vec ) ; for ( i = <NUM_LIT> ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { emit_insn ( ( * gen_func ) ( mem , reg ) ) ; if ( i + <NUM_LIT> * nelt_mode <= length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( nelt_mode ) ) ) ; offset += nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; } } gcc_assert ( ( i + nelt_v8 ) > length || mode == V16QImode ) ; if ( i + nelt_v8 < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - i ) ) ) ; offset += length - i ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) != <NUM_LIT> && align >= <NUM_LIT> ) set_mem_align ( mem ,


<s> if ( A == B ) return true ; unsigned common = A -> getCommonDomains ( B -> AvailableDomains ) ; if ( ! common ) return false ; A -> AvailableDomains = common ; A -> Dist = std :: max ( A -> Dist , B -> Dist ) ; A -> Instrs . append ( B -> Instrs . begin ( ) , B -> Instrs . end ( ) ) ; for ( unsigned rx = <NUM_LIT> ; rx != NumRegs ; ++ rx ) if ( LiveRegs


<s> static unsigned int pa_function_arg_boundary ( machine_mode mode , const_tree type ) { bool singleword = ( type ? ( integer_zerop ( TYPE_SIZE ( type ) ) || ! TREE_CONSTANT ( TYPE_SIZE ( type ) )

|| int_size_in_bytes ( type ) <= UNITS_PER_WORD ) : GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; } if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , <STR_LIT> , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , false , true , false ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase

, <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ;


<s> for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth


<s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { for ( uint64_t I = <NUM_LIT> ; I !=


<s> const Type * Tys [ ] = { Ty } ; Module * M = CI -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Constant * Int = <STR_LIT> ( M , <STR_LIT> , Tys , <NUM_LIT> ) ; Value * Op = CI -> getArgOperand ( <NUM_LIT> ) ; Op = CallInst :: Create ( Int , Op , CI -> getName ( ) , CI ) ; CI -> replaceAllUsesWith ( Op


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeList Attrs = MF . getFunction ( ) . getAttributes ( ) ; return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) ->

supportSwiftError ( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return &


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , VT ) ; } break ; } } } <STR_LIT> CondCode = IntCCToA64CC ( CC


<s> const char * nds32_output_smw_single_word ( rtx * operands ) { char buff [ <NUM_LIT> ] ; unsigned regno ; int enable4 ; bool update_base_p ; rtx base_addr = operands [ <NUM_LIT> ] ; rtx base_reg ; rtx otherops [ <NUM_LIT> ] ; if ( REG_P ( XEXP ( base_addr , <NUM_LIT> ) ) ) { update_base_p = false ; base_reg = XEXP ( base_addr , <NUM_LIT> ) ; } else { update_base_p = true ; base_reg = XEXP ( XEXP ( base_addr , <NUM_LIT> ) , <NUM_LIT> ) ; } const char * update_base = update_base_p ? <STR_LIT> : <STR_LIT> ; regno = REGNO ( operands [ <NUM_LIT> ] ) ; otherops [ <NUM_LIT> ] = base_reg ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) ; sprintf ( buff , <STR_LIT> , update_base


<s> static void seh_emit_stackalloc ( FILE * f , struct seh_frame_state * seh , HOST_WIDE_INT offset ) { gcc_assert ( offset < <NUM_LIT> ) ; offset = -


<s> } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr (


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG


<s> MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( MaxAlign ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs


<s> static bool applySwapICmpOperands ( MachineInstr & MI , GISelChangeObserver & Observer ) { auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Observer . changedInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( CmpInst :: getSwappedPredicate ( Pred ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( RHS ) ; MI . getOperand ( <NUM_LIT> ) . setReg


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple &


<s> next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + <NUM_LIT> *

find_insn_regmode_weight ( insn , DFmode ) ;


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( *


<s> static DecodeStatus DecodeT2ShifterImmOperand ( llvm :: MCInst & Inst , uint32_t Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm ( Val )


<s> switch ( NumBytes ) { case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NumBytes -= <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break


<s> break ; case MachineOperand :: MO_GlobalAddress : AddrSym = getSymbol ( Addr . getGlobal ( ) ) ; break ; } if ( ! isPositionIndependent ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } MCOperand RegPLT = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , AddrSym , OutContext ) ; emitLEAzii ( * OutStreamer , cim24 , loImm , MCRegOP , STI ) ; MCOperand ci32 = MCOperand :: createImm ( <NUM_LIT> ) ; emitANDrm0 ( * OutStreamer , MCRegOP , ci32 , MCRegOP , STI ) ; emitSIC ( * OutStreamer , RegPLT , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_HI32 , AddrSym , OutContext


<s> switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( RegNo ) { default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: LParen : if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Op = <STR_LIT> ( EVal , S , E ) ; break ; case AsmToken :: Identifier :


<s> unsigned Opc = SExtIdx == - <NUM_LIT> ? I -> getOpcode ( ) : getMatchingNonSExtOpcode ( I -> getOpcode ( ) ) ; bool IsUnscaled = isUnscaledLdSt ( Opc ) ; int OffsetStride = IsUnscaled ? getMemScale ( I ) : <NUM_LIT> ; bool MergeForward = Flags . getMergeForward ( ) ; unsigned NewOpc = getMatchingPairOpcode ( Opc ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? Paired : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( Paired ) : getLdStBaseOp ( I ) ; MachineInstr * RtMI , * Rt2MI ; if ( getLdStOffsetOp ( I ) . getImm ( ) == getLdStOffsetOp ( Paired ) . getImm ( ) + OffsetStride ) { RtMI = Paired ; Rt2MI = I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( IsUnscaled ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT>


<s> ++ MemOpsEmitted ; return static_cast < uint64_t > ( MO . getImm ( ) ) ; } if ( MO . isExpr ( ) ) { unsigned ByteOffs = MemOpsEmitted ++ == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( ByteOffs , MO . getExpr ( ) , ( MCFixupKind ) Kind , MI . getLoc ( ) ) ) ; assert ( Fixups . size (


<s> bool IsNaCl = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn )


<s> psrlh_u ( uint16x4_t s , uint8_t amount ) { return __builtin_loongson_psrlh_u ( s


<s> for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL , V1 , V2 , LaneMask ) ; LaneShuffle = DAG . getBitcast ( VT , LaneShuffle ) ; SmallVector < int , <NUM_LIT> > NewMask ( ( unsigned ) Size , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) NewMask [ i ] = ( i / LaneSize ) * LaneSize + Mask [ i ] % LaneSize ; assert ( ! is128BitLaneCrossingShuffleMask ( VT , NewMask ) &&


<s> unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn


<s> if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( PrevAddc == nullptr ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDValue MLAL = AddCombineTo64bitMLAL ( PrevAddc , DCI , Subtarget ) ; if ( MLAL != SDValue ( PrevAddc , <NUM_LIT> ) ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDNode * UmlalNode = nullptr ; SDValue AddHi ; if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } auto * Zero = dyn_cast < ConstantSDNode > ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ; if ( ! Zero || Zero -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( AddcNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( ! AddeNode ) return SDValue ( ) ; if ( ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == Zero && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode ) || ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == Zero ) ) { SelectionDAG & DAG = DCI . DAG ; SDValue Ops [ ] = { UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT> ) , AddHi } ; SDValue UMAAL = DAG . getNode ( <STR_LIT> , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , SDValue ( UMAAL . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) , SDValue ( UMAAL . getNode ( ) , <NUM_LIT> ) ) ; return SDValue ( AddcNode ,


<s> ( void ) rs6000_option_override_internal


<s> unsigned <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> :


<s> FeatureBitset getRequiredFeatures ( ) const { return FeaturesRequired


<s> bool IsDirect = ! Info . Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , MF ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI


<s> auto * KeyC = PAI . getKey ( ) ; assert ( isUInt < <NUM_LIT> > ( KeyC -> getZExtValue ( ) ) && <STR_LIT> ) ; <STR_LIT> Key = <STR_LIT> ( KeyC -> getZExtValue ( ) ) ; uint64_t OffsetV = Offset . getSExtValue ( ) ; std :: string Suffix = <STR_LIT> ; if ( OffsetV ) Suffix += utostr ( OffsetV ) + <STR_LIT> ; Suffix += ( Twine ( <STR_LIT> ) + <ISA_LIT>PACKeyIDToString ( Key ) + <STR_LIT> + utostr ( Discriminator ) ) . str ( ) ; if ( PAI . hasAddressDiversity ( ) ) report_fatal_error (


<s> EVT SrcVT = LHS . getValueType ( ) ; assert ( VT . getSizeInBits ( ) == SrcVT . getSizeInBits ( ) && <STR_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( RHS . getNode ( ) ) ; APInt CnstBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; bool IsCnst = BVN && resolveBuildVector ( BVN , CnstBits , UndefBits ) ; bool IsZero = IsCnst && ( CnstBits == <NUM_LIT> ) ; if ( SrcVT . getVectorElementType ( ) . isFloatingPoint ( ) ) { switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Fcmeq ; if ( IsZero ) Fcmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Fcmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fcmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> ,


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) Mask . push_back ( i ) ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 ,


<s> return ( ( __v4sf ) __A ) [ <NUM_LIT>


<s> else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == STACK_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) + GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == FRAME_POINTER_REGNUM || REGNO ( XEXP ( x , <NUM_LIT> ) ) == ARG_POINTER_REGNUM || ( REGNO ( XEXP ( x , <NUM_LIT> ) ) >= FIRST_VIRTUAL_REGISTER && REGNO ( XEXP ( x , <NUM_LIT> ) ) <= LAST_VIRTUAL_POINTER_REGISTER ) ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_SIZE ( mode ) == <NUM_LIT> && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x )

) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( T , TT . getOS (


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF (

createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) {


<s> switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : NeedSwap = true ; case CmpInst :: FCMP_OGT : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : NeedSwap = true ; case CmpInst :: FCMP_OGE : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : NeedSwap = true ; case CmpInst :: FCMP_ULT : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : NeedSwap = true ; case CmpInst :: FCMP_ULE : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : CC = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : CC = <STR_LIT> ;


<s> const MCOperand & Disp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( ! Base . getReg ( ) ) O << '&' ; if ( Disp . isExpr ( ) ) O << * Disp . getExpr ( ) ; else { assert ( Disp . isImm ( ) && <STR_LIT>


<s> return new <ISA_LIT>SpeculationHardening


<s> bool <ISA_LIT>AsmPrinter :: printAsmRegInClass ( const MachineOperand & MO , const TargetRegisterClass * RC , bool isVector , raw_ostream & O ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; const <ISA_LIT>RegisterInfo * RI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo


<s> return ( __m512 ) _mm512_insertf64x4 ( _mm512_setzero_pd ( ) , (


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( unsigned CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return CC_<ISA_LIT>_Win64_C ; else if ( CC == CallingConv :: Fast && isTaillCall ) return CC_<ISA_LIT>_64_TailCall ; else return CC_<ISA_LIT>_64_C ; } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv

:: Fast ) return CC_<ISA_LIT>_32_FastCC ;


<s> assert ( llvm :: all_of ( ShuffleMask , [ & ] ( int i ) { return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) { if ( ST -> hasNEON ( ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; else if ( isLegalMVEShuffleOp ( PFEntry ) ) { unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned PFEntryLHS = PerfectShuffleTable [ LHSID ] ; unsigned PFEntryRHS = PerfectShuffleTable [ RHSID ] ; if ( isLegalMVEShuffleOp ( PFEntryLHS ) && isLegalMVEShuffleOp ( PFEntryRHS ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } } } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG

. getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ;


<s> const Value * Idx = * OI ; if ( auto * StTy = dyn_cast < StructType > ( Ty ) ) { unsigned Field = cast < ConstantInt > ( Idx ) -> getZExtValue ( ) ; if ( Field ) TotalOffs += DL . getStructLayout ( StTy ) -> getElementOffset ( Field ) ; Ty = StTy -> getElementType ( Field ) ; } else { Ty = cast < SequentialType > ( Ty ) -> getElementType ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( Idx ) ) { if ( CI -> isZero ( ) ) continue ; TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , NIsKill


<s> bool <ISA_LIT>FastISel :: finishCall ( CallLoweringInfo & CLI , MVT RetVT , unsigned NumBytes ) { CallingConv :: ID CC = CLI . CallConv ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackUp ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs


<s> void EmitARM64WinCFISaveFRegPX ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg <<


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF


<s> assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) ) && <STR_LIT> ) ; assert ( RegBank -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( )


<s> if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal )


<s> Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } getTargetStreamer ( ) . AnnotateTLSDescriptorSequence ( SRE ) ; return


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle

) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle , Options ) {


<s> for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) ) return false ; return true


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! Subtarget . is64BitELFABI ( ) && ! Subtarget . isAIXABI ( ) ) return false ; if ( PhysReg == Subtarget . getTOCPointerRegister ( ) ) return ( getReservedRegs ( MF ) . test ( PhysReg ) ) ; if ( StackPtrConst && PhysReg == Subtarget . getStackPointerRegister ( ) && ! MFI . hasVarSizedObjects ( ) &&

! MFI . hasOpaqueSPAdjustment ( ) ) return true ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> static bool pa_function_value_regno_p ( const unsigned int regno


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( unsigned i = <NUM_LIT> , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return


<s> void addExtraBytes ( const MachineBasicBlock :: iterator I , unsigned ExtraBytes ) { auto Info = llvm :: find_if ( Insts , [ & ] ( InstInfo & Info ) { return Info


<s> unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ;


<s> if ( SDValue BT = LowerAndToBT ( Op0 , CC , dl , DAG , <ISA_LIT>CondCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( <ISA_LIT>CondCode , dl , <STR_LIT> ) ; return BT ; } } if ( isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) if ( SDValue CmpZ = MatchVectorAllZeroTest ( Op0 , CC , dl , Subtarget , DAG , <ISA_LIT>CC ) ) return CmpZ ; if ( SDValue Test = EmitAVX512Test ( Op0 , Op1 , CC , dl , DAG , Subtarget , <ISA_LIT>CC ) ) return Test ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; <ISA_LIT>CC = Op0 . getOperand ( <NUM_LIT> ) ; if ( Invert ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl ,


<s> const char * p ; symbol_type = mips_classify_symbolic_expression ( op , context ) ; gcc_assert ( relocs [ symbol_type ] ) ; fputs ( relocs [ symbol_type ] , file ) ; output_addr_const ( file , mips_strip_unspec_address ( op ) ) ; for ( p = relocs [ symbol_type ] ; * p != <NUM_LIT> ; p ++ ) if (


<s> return HasCMov || <ISA_LIT>SSELevel >= SSE1 || is64Bit


<s> } auto Terminator = MBB . getFirstTerminator ( ) ; if ( Terminator != MBB . end ( ) && Terminator -> getOpcode ( ) == <STR_LIT> ) { CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; for ( auto Op : Terminator -> implicit_operands ( ) ) { if ( Op . isReg ( ) ) CopyRegs . erase ( Op . getReg ( ) ) ; } } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; auto HiRegToRestore = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToRestore , AllHighRegsEnd ) ; while ( HiRegToRestore != AllHighRegsEnd ) { assert ( ! CopyRegs . empty ( ) ) ; auto CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PopMIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( PopMIB ) ; while ( HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { PopMIB . addReg ( * CopyReg , RegState :: Define ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; MIB . addReg ( * HiRegToRestore , RegState :: Define ) ; MIB . addReg ( * CopyReg , RegState :: Kill ) ; AddDefaultPred ( MIB ) ; CopyReg = findNextOrderedReg ( ++ CopyReg , CopyRegs , AllCopyRegsEnd ) ; HiRegToRestore = findNextOrderedReg ( ++ HiRegToRestore , HiRegsToRestore , AllHighRegsEnd ) ; } } MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) ) continue ; if ( Reg == <STR_LIT> ) { if ( MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( ! STI . hasV5TOps ( ) ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( TII . get ( <STR_LIT> ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( * MI ) ; MI = MBB . erase ( MI ) ; } else continue ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NeedsPop =


<s> bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . add ( MI -> getOperand ( i ) ) ; } MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ Num2Addrs


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> )

, <NUM_LIT> ) ) != <NUM_LIT> ) return true ;


<s> Type * Ty = V -> getType ( ) ; if ( Ty -> isVoidTy ( ) || Ty -> isPointerTy ( ) ) return true ; if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) Ty = cast < PointerType > ( Ld -> getPointerOperandType ( ) ) -> getElementType ( ) ; const IntegerType * IntTy = dyn_cast < IntegerType >


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val &


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand


<s> case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv


<s> unsigned ShuffleSize = ShuffleVT . getVectorNumElements ( ) ; unsigned MaskRatio = ShuffleSize / NumMaskElts ; if ( Depth == <NUM_LIT> && Root . getOpcode ( ) == <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != ShuffleSize ; ++ i ) if ( Mask [ i / MaskRatio ] < <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; SDValue Zero = getZeroVector ( ShuffleVT , Subtarget , DAG , DL ) ; Res = DAG . getBitcast ( ShuffleVT , Input ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Res , Zero , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Res ) , true ) ; return true ; } } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB ) && ( ( VT . is128BitVector ( ) && Subtarget . hasSSSE3 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . hasBWI ( ) ) ) ) { SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ; int NumBytes = VT . getSizeInBits ( ) / <NUM_LIT> ; int Ratio = NumBytes / NumMaskElts ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / Ratio ] ; if ( M == SM_SentinelUndef ) { PSHUFBMask . push_back ( DAG . getUNDEF ( <STR_LIT> ) ) ; continue ; } if ( M == SM_SentinelZero ) { PSHUFBMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; continue ; } M = Ratio * M + i % Ratio ; if ( ( M / <NUM_LIT> ) != ( i / <NUM_LIT> ) ) return false ; PSHUFBMask . push_back ( DAG . getConstant ( M , DL , <STR_LIT> ) ) ; } MVT ByteVT = <STR_LIT> ( <STR_LIT> , NumBytes ) ; Res = DAG . getBitcast ( ByteVT , Input ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; SDValue PSHUFBMaskOp = DAG . getBuildVector ( ByteVT , DL , PSHUFBMask ) ; DCI . AddToWorklist ( PSHUFBMaskOp . getNode ( ) ) ; Res = DAG . getNode ( <STR_LIT> , DL


<s> SItype __ashlsi3 ( SItype a , SItype b ) { word_type i ; if ( b & <NUM_LIT> ) a <<= <NUM_LIT> ; if ( b & <NUM_LIT> )


<s> } } } if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } } else if ( ConstantSDNode * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { ConstantSDNode * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) == Bits ) return DAG . getNode ( Opc , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } return SDValue


<s> static DecodeStatus decodeImmShiftOpValue ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler


<s> MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb , L )


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc (


<s> return __builtin_mve_vshrq_m_n_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __imm ,


<s> SmallVector < SDValue , <NUM_LIT> > pshufbMask ; bool TwoInputs = ! ( V1Only || V2Only ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> || ( TwoInputs && EltIdx >= <NUM_LIT> ) ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; continue ; } pshufbMask . push_back ( DAG . getConstant ( EltIdx , <STR_LIT> ) ) ; } if ( V2Only ) V1 = V2 ; V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( ! TwoInputs ) return V1 ; pshufbMask . clear ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; continue ; } pshufbMask . push_back ( DAG . getConstant ( EltIdx - <NUM_LIT> , <STR_LIT> ) ) ; } V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , V2 ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) ; SDValue NewV = V2Only ? V2 : V1 ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int Elt0 = MaskVals [ i


<s> bool <ISA_LIT>FastISel :: selectSelect ( const Instruction * I ) { assert ( isa < SelectInst > ( I ) && <STR_LIT> ) ; MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; <STR_LIT> CC = <STR_LIT> ; <STR_LIT> ExtraCC = <STR_LIT> ; if ( optimizeSelect ( SI ) ) return true ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; } else if ( isa < CmpInst > ( Cond ) && cast < CmpInst > ( Cond ) -> hasOneUse ( ) && isValueAvailable ( Cond ) ) { const auto * Cmp = cast < CmpInst > ( Cond ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate (


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB ->


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { const RegisterSDNode * R = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( R != NULL && R -> getReg ( ) == <NUM_LIT> ) return CurDAG -> getConstant ( <NUM_LIT> , <STR_LIT> ) ; } return N


<s> if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( ( ! ImmSigned && isUInt < <NUM_LIT> > ( imm ) ) || ( ImmSigned && isInt < <NUM_LIT> > ( imm ) ) ) CmpOpc = CmpiXOpc ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI -> eraseFromParent


<s> MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT> ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT


<s> if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT>


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>TDCPass ( ) ) ; TargetPassConfig :: addIRPasses (


<s> <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , false , OffUndef , Pred , PredReg , TII , isT2 ) ; NewBBI = llvm :: prior ( MBBI ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , false , BaseReg , BaseKill , BaseUndef , OffKill , OffUndef , Pred , PredReg , TII , isT2 ) ; } else { if ( OddReg == EvenReg && EvenDeadKill ) { EvenDeadKill = false ; OddDeadKill = true ; } if ( EvenReg == BaseReg ) EvenDeadKill = false ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , EvenUndef , BaseReg , false , BaseUndef


<s> m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs .


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property ::


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0


<s> unsigned Opcode = MI -> getOpcode ( ) ; int OpNum = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size (


<s> for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) )

TLOF . emitLinkerFlagsForGlobal ( OS , & Alias , * Mang ) ;


<s> uint64_t Disp = ( ( Field << <NUM_LIT> ) & <NUM_LIT> ) | ( ( Field >> <NUM_LIT> ) & <NUM_LIT> ) ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = llvm :: find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPEAlign ( * U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex (


<s> if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl


<s> if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) { if ( SetCCOpcode == <STR_LIT> && RHSC -> isAllOnesValue ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isNullValue ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isNullValue ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> getAPIntValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned add = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = STI . getRegisterInfo ( ) ; if ( ! STI . isTargetLinux ( ) || ! ( Info . CallConv == CallingConv :: C || Info . CallConv == CallingConv :: <ISA_LIT>_64_SysV ) ) return false ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Info . Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : Info . OrigArgs ) { if ( OrigArg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Regs [ <NUM_LIT> ] ) ; } ) ) return false ; } <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = Info . OrigArgs . empty ( ) ? true : Info .


<s> static bool nds32_function_ok_for_sibcall ( tree decl


<s> SDLoc DL ( Op ) ; SDValue Vl = Op . getOperand ( <NUM_LIT> ) ; SDValue ShiftAmt = Op . getOperand ( <NUM_LIT> ) ; if ( ShiftAmt . getOpcode ( ) != <STR_LIT> ) { return ExpandLibCall ( <STR_LIT> , Op , false , DAG ) ; } EVT VT = Vl . getValueType ( ) ; uint64_t ShAmt = cast < ConstantSDNode > ( ShiftAmt . getNode ( ) ) -> getZExtValue ( ) ; for ( uint64_t i = <NUM_LIT> ; i < ShAmt ; i


<s> } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; assert ( OpVT . is128BitVector


<s> } } if ( Writer -> doesSymbolRequireExternRelocation ( * A ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; } MachO :: any_relocation_info MRE ; makeRelocationInfo ( MRE , FixupOffset , Index , IsPCRel , Log2Size


<s> if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) && ( val & <NUM_LIT> ) == <NUM_LIT> ; else return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> - <NUM_LIT> ) ; } else return <NUM_LIT> ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code ==


<s> if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask


<s> case <STR_LIT> : LC = RTLIB :: REM_F64 ; break ; } ArgListTy Args ; Args . reserve ( I -> getNumOperands ( ) ) ; for ( auto & Arg : I -> operands ( ) ) { ArgListEntry Entry ; Entry . Val = Arg ; Entry . Ty = Arg -> getType ( ) ; Args . push_back ( Entry ) ; } CallLoweringInfo CLI


<s> return ( __m512i ) __builtin_ia32_pmovsxwd512_mask ( ( __v16hi ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16 )


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ; O << <STR_LIT>


<s> SDLoc dl ( Op ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; MakeLibCallOptions CallOptions ; std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , LC , VT , In , CallOptions , dl , Chain ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp


<s> O << <STR_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O << utohexstr ( ( Value & ( <NUM_LIT>


<s> return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type )


<s> if ( ! CPEClones . insert ( std :: make_pair ( CPCloneIdx , CPIdx

) ) . second ) assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned <ISA_LIT>FastISel :: Emit_SMULL_rr ( MVT RetVT , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { if ( RetVT != <STR_LIT>


<s> DummyOp = MF . CreateMachineInstr ( TII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; } unsigned NbReg = RegToId . size ( ) ; bool Modified = false ; InstrToInstrs * ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , true , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs ADRPToReachingDefs ; reachedUsesToDefs ( ADRPToReachingDefs , ColorOpToReachedUses , RegToId , true ) ; computeADRP ( ADRPToReachingDefs , * <ISA_LIT>FI , MDT ) ; delete [ ] ColorOpToReachedUses ; ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , false , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs UsesToReachingDefs


<s> bool UseSoftFloat = Subtarget . abiUsesSoftFloat ( ) ; <ISA_LIT>CCInfo . analyzeFormalArguments ( Ins , UseSoftFloat , FuncArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , <ISA_LIT>CCInfo . hasByValArg ( ) ) ; unsigned CurArgIdx = <NUM_LIT> ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; std :: advance ( FuncArg , Ins [ i ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ i ] . OrigArgIndex ; EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( Subtarget . isABI_O32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg

( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> return __builtin_aarch64_usri_nv2di_uuus ( __a ,


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Res . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : unsigned opcode ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Res . setOpcode ( opcode ) ; Res . addOperand ( Inst . getOperand


<s> void rs6000_xcoff_asm_globalize_decl_name ( FILE * stream , tree decl ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; fputs ( GLOBAL_ASM_OP , stream ) ; assemble_name ( stream , name ) ; fputs ( rs6000_xcoff_visibility ( decl ) ,


<s> bool llvm :: isIntS16Immediate ( SDValue Op , int16_t & Imm ) { return isIntS16Immediate ( Op . getNode ( )


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; uint64_t Value = SignExtend64 < N > ( Imm ) * <NUM_LIT> + Address ; if ( ! tryAddingSymbolicOperand ( Value , isBranch , Address , <NUM_LIT> , N / <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand (


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_CondCode , Ctx ) ; Op -> CondCode . Code =


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( )


<s> dbgs ( ) << <STR_LIT> << <STR_LIT> ; for ( MachineInstr * MI : Instrs ) { dbgs ( ) << <STR_LIT> ; MI -> print ( dbgs ( ) ) ; } dbgs ( ) <<


<s> } } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS , Dialect ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange


<s> Regs . push_back ( RegNo ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( parseAnyRegister ( TmpOperands ) != MatchOperand_Success ) return MatchOperand_ParseFail ; Reg = & static_cast < <ISA_LIT>Operand & > ( * TmpOperands . back ( ) ) ; RegNo = isGP64bit ( ) ? Reg -> getGPR64Reg ( ) : Reg -> getGPR32Reg ( ) ; Regs . push_back ( RegNo ) ; Operands . push_back ( <STR_LIT> ( Regs , S ,


<s> void d30v_expand_prologue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; int num_memrefs = ( info -> memrefs_2words + info -> memrefs_1word + info -> memrefs_varargs ) ; if ( TARGET_DEBUG_STACK ) debug_stack_info ( info ) ; if ( info -> total_size ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( - info -> total_size ) ) ) ; if ( num_memrefs > <NUM_LIT> ) { rtx save_tmp = gen_rtx ( REG , Pmode , GPR_STACK_TMP ) ; rtx post_inc = gen_rtx ( POST_INC , Pmode , save_tmp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; emit_insn ( gen_addsi3 ( save_tmp , sp , GEN_INT ( info -> save_offset ) ) ) ; } else if ( num_memrefs == <NUM_LIT> ) { rtx addr = plus_constant ( sp , info -> save_offset ) ; mem_di = gen_rtx ( MEM , DImode , addr ) ; mem_si = gen_rtx ( MEM , SImode , addr ) ; } for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , gen_rtx ( REG , DImode , i ) ) ) ; emit_insn ( gen_movdi ( mem_di , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += <NUM_LIT> ) if ( info -> save_p [ i ] == <NUM_LIT> ) emit_insn ( gen_movdi ( mem_di , gen_rtx ( REG , DImode , i ) ) ) ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == <NUM_LIT> ) emit_insn ( gen_movsi ( mem_si , gen_rtx ( REG , SImode , i ) ) ) ; if ( info -> varargs_p ) { if ( ( info -> memrefs_1word & <NUM_LIT> ) != <NUM_LIT> ) { rtx save_tmp = XEXP ( XEXP ( mem_si ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranch16TargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr (


<s> return ( __m64 ) __builtin_arm_wminsw ( ( __v2si ) __A , (


<s> static bool mips_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_FLOATXX && hard_regno_nregs ( regno , mode ) == <NUM_LIT> && FP_REG_P ( regno

) && ( regno & <NUM_LIT> ) != <NUM_LIT> ) return true ;


<s> Addr = N ; Update = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( false ) , <STR_LIT>


<s> enum machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; enum machine_mode op_mode = GET_MODE ( op0 ) ; int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( op_mode ) ; if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || standard_80387_constant_p ( op1 ) == <NUM_LIT> ) && GET_CODE ( op1 ) != FLOAT ) || ix86_use_fcomi_compare ( code ) ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || ( GET_CODE ( op0 ) == MEM && ! ( standard_80387_constant_p ( op1 ) == <NUM_LIT> || GET_CODE ( op1 ) == MEM ) ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; } if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == <NUM_LIT> ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == <NUM_LIT> ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( GET_CODE ( op1 ) == REG || ! no_new_pseudos ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1


<s> char * attr_str , * assembler_name ; if ( DECL_DECLARED_INLINE_P ( decl ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> <STR_LIT> ) ; if ( DECL_VIRTUAL_P ( decl ) || DECL_VINDEX ( decl ) ) sorry ( <STR_LIT> ) ; version_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( version_attr != NULL_TREE ) ; orig_name = IDENTIFIER_POINTER ( id ) ; version_string = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( version_attr ) ) ) ; if ( strcmp ( version_string , <STR_LIT> ) == <NUM_LIT> ) return id ; attr_str = sorted_attr_string ( TREE_VALUE ( version_attr ) ) ; assembler_name = XNEWVEC ( char , strlen ( orig_name ) + strlen ( attr_str ) + <NUM_LIT> ) ; sprintf ( assembler_name , <STR_LIT> , orig_name , attr_str ) ; if ( DECL_ASSEMBLER_NAME_SET_P ( decl ) ) SET_DECL_RTL ( decl , NULL ) ; tree ret = get_identifier ( assembler_name ) ; XDELETEVEC ( attr_str )


<s> bool hasFP16FML ( ) const { return HasFP16FML


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool isFixed = MFI .


<s> void arm_pr_no_long_calls ( struct cpp_reader


<s> AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; IsCpRestoreSet = false ; CpRestoreOffset = - <NUM_LIT> ; const Triple & TheTriple = sti . getTargetTriple ( ) ; IsLittleEndian = TheTriple . isLittleEndian ( ) ; if ( getSTI ( ) . getCPU ( ) == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && inMicro<ISA_LIT>Mode ( ) )


<s> } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( DAG .

getMachineFunction ( ) , i * <NUM_LIT> ) ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( <NUM_LIT> )


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; unsigned Opc = <NUM_LIT> ; bool Offset = true ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT>


<s> bool HasAnyUndefs ; if ( ! Subtarget . hasMSA ( ) || ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; if ( Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) && SplatBitSize <= <NUM_LIT> ) { if ( SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> ) return SDValue ( ) ; if ( ResTy . isInteger ( ) && ! HasAnyUndefs && SplatValue . isSignedIntN ( <NUM_LIT> ) ) return Op ; EVT ViaVecTy ; switch ( SplatBitSize ) { default : return SDValue ( )