<s> return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ! GV -> isStrongDefinitionForLinker ( ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV


<s> void printlea64_32mem ( const MCInst * MI , unsigned OpNo


<s> bool IsSubAdd ; if ( ! isAddSubOrSubAdd ( BV , Subtarget , DAG , Opnd0 , Opnd1 , NumExtracts , IsSubAdd ) ) return SDValue ( ) ; MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( BV ) ; SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , NumExtracts ) ) { unsigned Opc = IsSubAdd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; } if ( IsSubAdd ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) { SmallVector < int > Mask ; for ( int I = <NUM_LIT> , E = VT . getVectorNumElements ( ) ; I != E ; I += <NUM_LIT> ) { Mask . push_back


<s> PointerElementType = Type :: getInt8Ty ( MemI -> getContext ( ) ) ; if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) { PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> ) { PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } } if ( PtrElementType ) * PtrElementType = PointerElementType ; return


<s> SDValue PICLabel = DAG . getTargetConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; auto * LRWGRS = DAG . getMachineNode ( <STR_LIT> , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; auto LRWADDGRS = DAG . getNode ( <STR_LIT> , DL , Ty , SDValue ( LRWGRS , <NUM_LIT> ) , SDValue ( LRWGRS , <NUM_LIT> ) ) ; Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddressWindows ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> void neon_const_bounds ( rtx operand , HOST_WIDE_INT low ,


<s> return ; } Info . OneUser = true ; if ( isCandidateLoad ( MI ) ) { Info . Type = MCLOH_AdrpLdr ; Info . IsCandidate = true ; Info . MI0 = & MI ; } else if ( isCandidateStore ( MI , MO ) ) { Info . Type = MCLOH_AdrpAddStr ; Info . IsCandidate = true ; Info . MI0 = & MI ; Info . MI1 = nullptr ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Info . Type =


<s> unsigned Opcode = N -> getOpcode ( ) ; assert ( ( <STR_LIT> == Opcode || <STR_LIT> == Opcode || <STR_LIT> == Opcode ) && <STR_LIT> ) ; bool LogicalShift = <STR_LIT> == Opcode || <STR_LIT> == Opcode ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( VT == N0 . getValueType ( ) && ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT>


Mask , Subtarget , DAG ) ) return Result ;


<s> if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success )


<s> O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo + <NUM_LIT> ,


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; UsesELFSectionDirectiveForBSS =


<s> rtl_opt_pass * make_pass_tag_collision_avoidance ( gcc :: context * ctxt ) { return new pass_tag_collision_avoidance ( ctxt


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo


<s> bool hasVFP2Base ( ) const { return hasVFPv2SP (


<s> if ( - <NUM_LIT> == rndMode ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Minus ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; SMLoc End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; const MCExpr * RndModeOp = MCConstantExpr :: create ( rndMode , Parser . getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( RndModeOp , Start , End ) ) ; return false


<s> case InlineAsm :: Constraint_ZC : if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { if ( selectAddrRegImm12 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { if ( selectAddrRegImm9 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( selectAddrRegImm16 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false


<s> Instruction * <ISA_LIT>PromoteConstant :: findInsertionPoint ( Instruction & User , unsigned OpNo ) { if ( PHINode * PhiInst = dyn_cast < PHINode > ( & User ) ) return PhiInst -> getIncomingBlock ( OpNo ) ->


<s> unsigned int regno ; if ( ! TARGET_USE_GOT ) return GLOBAL_POINTER_REGNUM ; if ( mips_cfun_has_inflexible_gp_ref_p ( ) ) return GLOBAL_POINTER_REGNUM ; if ( TARGET_ABSOLUTE_JUMPS && ! mips_cfun_has_flexible_gp_ref_p ( ) ) return INVALID_REGNUM ; if ( TARGET_CALL_SAVED_GP && crtl -> is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM


<s> if ( ( signature_args [ signature ] [ <NUM_LIT> ] & <NUM_LIT> ) && ( ( ( signature_args [ signature ] [ <NUM_LIT> ] & <NUM_LIT> ) && TARGET_SHMEDIA32 ) || ( ( signature_args [ signature ] [ <NUM_LIT> ] & <NUM_LIT> ) && TARGET_SHMEDIA64 ) ) ) continue ; if ( ! TARGET_FPU_ANY && FLOAT_MODE_P ( insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ) ) continue ; type = void_list_node ; for ( i = <NUM_LIT> ; ; i -- ) { int arg = signature_args [ signature ] [ i ] ; int opno = i - <NUM_LIT> + has_result ; if ( arg & <NUM_LIT> )


<s> Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> <<


<s> assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; uint64_t Intval = Opcodes [ <NUM_LIT> ] | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> ; EmitIntValue ( Intval , Opcodes . size ( ) ) ; } SwitchSection ( & FnStart -> getSection ( )


<s> Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi ; if ( IsTLSGDPCREL ) { Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addImm ( <NUM_LIT> ) ; } else { assert ( InReg != <STR_LIT> && <STR_LIT> ) ; Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; } Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; if ( IsTLSGDPCREL ) Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; else Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT>


<s> return CurDAG -> getTargetConstant ( Imm


<s> Register AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB , AddrReg ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , DL . getPointerSize ( ) , Alignment ) ; MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return ResultReg ; } addConstantPoolReference ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , CPI , PICBase , OpFlag ) ; return


<s> case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_CC : mcInst . addOperand ( MCOperand :: createImm ( insn . immediates [ <NUM_LIT> ] ) ) ; return false ; case ENCODING_FP : translateFPRegister ( mcInst , insn . modRM & <NUM_LIT> ) ; return false ; case ENCODING_VVVV : translateRegister ( mcInst , insn . vvvv ) ; return false ; case


<s> return Kind == k_Register && Reg . Kind


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_64Target ( )


<s> if ( CC >= LPCC :: UNKNOWN ) OS << <STR_LIT> ; else if ( CC != LPCC :: ICC_T ) OS << <STR_LIT> << <ISA_LIT>CondCodeToString


<s> ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( LHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , LMask . begin ( ) ) ; } else { if ( ! LHS . isUndef ( ) ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( ! RHS . getOperand ( <NUM_LIT> ) . isUndef ( ) ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( ! RHS . getOperand ( <NUM_LIT> ) . isUndef ( ) ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( ! RHS . isUndef ( ) ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i


<s> unsigned NumConcat = WideNumElts / VecVT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; Ops [ <NUM_LIT> ] = Vec ; SDValue UndefVec = DAG . getUNDEF ( VecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumConcat ; ++ i ) Ops


<s> static inline AMSubMode getAM5SubMode (


<s> using namespace <ISA_LIT> ; if ( isIMUL ( Opcode ) ) return true ; if ( isBSF ( Opcode ) || isBSR ( Opcode ) || isLZCNT ( Opcode ) || isPOPCNT ( Opcode ) || isTZCNT ( Opcode ) ) return true ; if ( isBLCFILL ( Opcode ) || isBLCI ( Opcode ) || isBLCIC ( Opcode ) || isBLCMSK ( Opcode ) || isBLCS ( Opcode ) || isBLSFILL ( Opcode ) || isBLSI ( Opcode ) || isBLSIC ( Opcode ) || isBLSMSK ( Opcode ) || isBLSR ( Opcode ) || isTZMSK ( Opcode ) ) return true ; if ( isBEXTR ( Opcode ) || isBZHI ( Opcode ) ) return true ; if ( isROL ( Opcode ) || isROR ( Opcode ) || isSAR ( Opcode ) || isSHL ( Opcode ) || isSHR ( Opcode ) || isSHLD ( Opcode ) || isSHRD ( Opcode ) ) return true ; if ( isADC ( Opcode ) || isADD ( Opcode ) || isAND ( Opcode ) || isOR ( Opcode ) || isSBB ( Opcode ) || isSUB ( Opcode ) || isXOR ( Opcode ) ) return true ; if ( isADCX ( Opcode ) || isADOX ( Opcode ) || isANDN ( Opcode ) ) return true ; if ( isDEC ( Opcode ) || isINC ( Opcode ) || isNEG ( Opcode ) ) return true ; if ( isNOT ( Opcode ) ) return


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return


<s> static bool pa_commutative_p ( rtx x , int outer_code ) { return ( COMMUTATIVE_P ( x ) && ( TARGET_NO_SPACE_REGS || ( outer_code != UNKNOWN && outer_code != MEM ) || GET_CODE ( x )


<s> Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> auto OpSize = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; auto OriginalResult = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Predicate = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto Libcalls = getFCmpLibcalls ( Predicate , OpSize ) ; if ( Libcalls . empty ( ) ) { assert ( ( Predicate == CmpInst :: FCMP_TRUE || Predicate == CmpInst :: FCMP_FALSE ) && <STR_LIT> ) ; MIRBuilder . buildConstant ( OriginalResult , Predicate == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , std :: string ( CPU )

, std :: string ( FS ) , * this , is64bit ) , is64Bit ( is64bit ) {


<s> int Latency = <ISA_LIT>GenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> int vax_mode_dependent_address_p ( rtx x ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ; if ( GET_CODE ( x ) != PLUS ) return <NUM_LIT> ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( xfoo0 ) && GET_CODE ( xfoo1 ) == REG ) return <NUM_LIT> ; if ( CONSTANT_ADDRESS_P ( xfoo1 ) && GET_CODE (


<s> if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString (


<s> assert ( LdNode && LdNode -> getOffset ( ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned alignment = LdNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64


<s> return ( __m512i ) __builtin_ia32_cvttps2dq512_mask ( ( __v16sf ) __A , ( __v16si )


<s> void <ISA_LIT>InstPrinter :: printImmZeroOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value == <NUM_LIT> && <STR_LIT>


<s> __builtin_aarch64_st1v4hi ( ( __builtin_aarch64_simd_hi * ) a , (


<s> if ( CONST_INT_P ( src ) ) { HOST_WIDE_INT val = INTVAL ( src ) ; emit_set_insn ( dest , GEN_INT ( val & <NUM_LIT> ) ) ; if ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) { emit_set_insn ( gen_rtx_ZERO_EXTRACT ( SImode , dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ; rtx_insn * insn = get_last_insn ( ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( src ) ) ; } return ; } emit_set_insn ( dest , gen_rtx_HIGH ( SImode


<s> split_const ( address , & base , & offset ) ; return loongarch_unspec_address_offset ( base , offset


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get (


<s> if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = ( * LoadMI -> memoperands_begin ( ) ) -> getAlignment ( ) ; else switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) )


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return &


<s> static bool rs6000_keep_leaf_when_profiled ( ) { return TARGET_PROFILE_KERNEL


<s> return ! is64Bit ; case CallingConv :: Fast : case CallingConv :: GHC : case CallingConv :: HiPE : if ( IsVarArg ) return false ; return TailCallOpt


<s> if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; if ( Mid ) return truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; } return SDValue


<s> if ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) return Lower256IntArith ( Op , DAG ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && ! Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getNode ( <STR_LIT> , dl , VT , Evens ) ; Odds = DAG . getNode ( <STR_LIT> , dl , VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT


<s> if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> mask = aarch64_simd_gen_const_vector_dup ( vmode , one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; sel = expand_simple_binop ( vmode , AND , sel , mask , NULL , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) { if ( ! one_vector_p ) mask = aarch64_simd_gen_const_vector_dup


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op


<s> static unsigned getBitExtrOpcode ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> if ( ! match ( BroadcastSplat , m_Shuffle ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElt ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero ( ) ) ) ) return false ; auto * Phi = dyn_cast < PHINode > ( IV ) ; if ( ! Phi ) return false ; Value * OnEntry = Phi -> getIncomingValueForBlock ( L -> getLoopPreheader ( ) ) ; if ( ! match ( OnEntry , m_Zero ( ) ) ) return false ; Value * InLoop = Phi -> getIncomingValueForBlock ( L -> getLoopLatch ( ) ) ; unsigned Lanes = cast < FixedVectorType > ( Insert -> getType ( ) ) ->


<s> inline vector signed int vec_lde ( int a1 , signed int


<s> static rtx_insn * calculate_pic_address_constant ( rtx reg , rtx pic_reg , rtx orig ) { rtx pat ; rtx mem ; pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = <NUM_LIT> ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; return emit_insn ( pat )


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> if ( ! STI . fixCortexA53_835769 ( ) ) return false ; bool Changed = false ; TII = STI . getInstrInfo ( ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock ( MBB


<s> unsigned Reg = I32RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> const IntrinsicData * Data = lower_bound ( IntrinsicsWithChain , IntNo ) ; if ( Data != std :: end ( IntrinsicsWithChain ) && Data -> Id == IntNo


<s> static unsigned maxLongNopLength ( const <ISA_LIT>Subtarget * Subtarget ) { if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] || Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> is32Bit ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) || CPU == <STR_LIT> ) { if ( TargetTriple . getArch ( ) == Triple :: ppc64le ) CPUName = <STR_LIT> ; else if ( TargetTriple . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_spe ) CPUName = <STR_LIT> ; else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE )


<s> const char * arg_regs [ <NUM_LIT> ] ; enum machine_mode arg_mode ; rtx link ; int i , output_flag = <NUM_LIT> ; int regno ; if ( TARGET_64BIT || TARGET_ELF32 ) return ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) arg_regs [ i ] = <NUM_LIT> ; if ( TARGET_PORTABLE_RUNTIME ) { fputs ( <STR_LIT> , asm_out_file ) ; return ; } gcc_assert ( GET_CODE ( call_insn ) == CALL_INSN ) ; for ( link = CALL_INSN_FUNCTION_USAGE ( call_insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use ,


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - <NUM_LIT> : <NUM_LIT> ) ; splat_val = val ; msb_val = val >= <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= copies


<s> if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return


<s> TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , CmpVT ,


<s> } else for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , dest + i ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , src + i ) ; output_asm_insn ( <STR_LIT> , ops ) ; } } } else { gcc_assert ( MEM_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; switch ( GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) { case


<s> return ( uint16x4_t ) ( ( ( ( uint16x4_t ) a )


<s> case E_HImode : return QUAL_TYPE ( HI ) ; case E_SImode : return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI ) ; case E_OImode : return aarch64_simd_intOI_type_node ; case E_CImode : return aarch64_simd_intCI_type_node ; case E_XImode : return aarch64_simd_intXI_type_node ; case


<s> OpBegins . push_back ( <NUM_LIT> ) ; HasPersonality = false


<s> SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue VIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue VMask = Node -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return nullptr ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDLoc DL ( Node ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return ResNode


<s> MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection ) ; emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue (


<s> unsigned RegSize = MF . getRegInfo ( ) . getRegClass ( LoadMI . getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) return true ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) return true ; return


<s> static SDValue LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getValueType ( )


<s> bool <ISA_LIT>FastTileConfig :: fastTileConfig ( ) { bool Changed = false ; for ( MachineBasicBlock & MBB : * MF ) { SmallVector < MachineInstr * , <NUM_LIT> > CFGs ; for ( MachineInstr & MI : MBB ) if ( MI . getOpcode ( ) == <STR_LIT> ) CFGs . push_back ( & MI ) ; for ( auto * MI : CFGs ) materializeTileCfg


<s> for ( auto I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : if ( TLSBaseAddrReg ) I = ReplaceTLSCall ( & * I , TLSBaseAddrReg ) ; else I = SetRegister ( & *


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isGP64 ( ) )

return DecodeGPR64RegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> void setHasPushSequences ( bool HasPush ) { HasPushSequences = HasPush


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( Node -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return NULL ; } switch ( Node -> getOpcode ( )


<s> uint32_t Op1 = ( Bits >> <NUM_LIT> ) & <NUM_LIT> ; uint32_t CRn = ( Bits >> <NUM_LIT> ) & <NUM_LIT> ; uint32_t CRm = ( Bits >> <NUM_LIT> ) & <NUM_LIT> ; uint32_t Op2 = Bits & <NUM_LIT> ; return <STR_LIT> + utostr ( Op0 ) + <STR_LIT> + utostr ( Op1 ) + <STR_LIT> + utostr ( CRn

) + <STR_LIT> + utostr ( CRm ) + <STR_LIT> + utostr ( Op2 ) ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ; return


<s> __rv . __o = __builtin_neon_vld4_dupv4hi ( ( const __builtin_neon_hi * )


<s> return __builtin_mve_vcmpltq_m_n_sv4si ( __a ,


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == <NUM_LIT> ) return AM . Base . Reg ; Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel (


<s> switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case


<s> return ( __m128i ) vec_cmplt ( ( __v4si ) __A ,


<s> bool <ISA_LIT>BaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { if ( STI . isTargetDarwin (


<s> bool use<ISA_LIT>PreRASchedStrategy (


<s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SignBits [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; bool IsPositive [ <NUM_LIT> ] = { false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Opd = N -> getOperand ( i ) ; SignBits [ i ] = DAG . ComputeNumSignBits ( Opd ) ; IsPositive [ i ] = DAG . SignBitIsZero ( Opd ) ; } bool AllPositive = IsPositive [ <NUM_LIT> ] && IsPositive [ <NUM_LIT> ] ; unsigned MinSignBits = std :: min ( SignBits [ <NUM_LIT> ] , SignBits [ <NUM_LIT> ] ) ; if ( MinSignBits >= <NUM_LIT> ) Mode = MULS8 ; else if ( AllPositive && MinSignBits >= <NUM_LIT> ) Mode = MULU8 ; else if ( MinSignBits >= <NUM_LIT> ) Mode = MULS16 ; else if ( AllPositive && MinSignBits >= <NUM_LIT>


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > BasicBlocks ; for ( auto * Dead : Killed ) BasicBlocks . insert ( Dead -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & IT : * MBB ) { if ( IT . getOpcode ( ) != <STR_LIT> ) continue ; RDA . getReachingLocalUses ( & IT , MCRegister :: from ( <STR_LIT> ) , ITBlocks [ & IT ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > RemoveITs ; for ( auto * Dead : Killed ) { if ( MachineOperand * MO = Dead -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA . getMIOperand ( Dead , * MO ) ; RemoveITs . insert ( IT ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( Dead ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ! ModifiedITs . empty ( ) ) return false ; Killed . insert ( RemoveITs . begin ( ) , RemoveITs . end ( ) ) ; return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; if ( ! RDA . isSafeToRemove ( MI , Uses , Ignore ) ) return false ; if ( WontCorruptITs ( Uses , RDA ) ) { ToRemove . insert ( Uses . begin ( ) , Uses . end ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ; for ( auto * Use : Uses ) dbgs ( ) << <STR_LIT> << * Use ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Killed ; RDA . collectKilledOperands ( MI , Killed


<s> int length = get_attr_length ( insn ) ; int xdelay ; if ( branch_to_delay_slot_p ( insn ) ) return <STR_LIT> ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; useskip = ( length == <NUM_LIT> && nullify ) ? use_skip_p ( insn ) : FALSE ; switch ( length ) { case <NUM_LIT> : if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( useskip && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcpy ( buf , <STR_LIT> ) ; else if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcpy ( buf , <STR_LIT> ) ; if ( ( which == <NUM_LIT> && negated ) || ( which == <NUM_LIT> && ! negated ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify && negated ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else if ( nullify && ! negated ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else if ( ! nullify && negated ) strcat ( buf , <STR_LIT> ) ; else if ( ! nullify && ! negated ) strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( ( which == <NUM_LIT> && negated ) || ( which == <NUM_LIT> && ! negated ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( ( which == <NUM_LIT> && negated ) || ( which == <NUM_LIT> && ! negated ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; if ( Opcode == TargetOpcode :: COPY_TO_REGCLASS ) return ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> long int <ISA_LIT>ELFWriterInfo :: getDefaultAddendForRelTy ( unsigned RelTy , long int Modifier ) const { switch ( RelTy ) { case ELF :: R_MIPS_26 : return Modifier ; default : llvm_unreachable ( <STR_LIT> )


<s> if ( using_static_chain_p && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) strategy |= ( ( DEFAULT_ABI == ABI_DARWIN ? <NUM_LIT> : SAVE_INLINE_FPRS ) | SAVE_INLINE_GPRS | SAVE_INLINE_VRS ) ; if ( TARGET_SPE_ABI && info -> spe_64bit_regs_used && info -> cr_save_p ) strategy |= REST_INLINE_GPRS ; if ( ( strategy & SAVE_INLINE_FPRS ) && ! ( strategy & REST_INLINE_FPRS ) ) { int i ; for ( i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( fixed_regs [ i ] || ! save_reg_p ( i ) ) { strategy |= REST_INLINE_FPRS ; break ; } } if ( ( strategy & SAVE_INLINE_VRS ) && ! ( strategy & REST_INLINE_VRS ) ) { int i ; for ( i = info -> first_altivec_reg_save ; i < LAST_ALTIVEC_REGNO + <NUM_LIT> ; i ++ ) if ( fixed_regs [ i ] || ! save_reg_p ( i ) ) { strategy |= REST_INLINE_VRS ; break ; } } bool lr_save_p = ( info -> lr_save_p || ! ( strategy & SAVE_INLINE_FPRS ) || ! ( strategy & SAVE_INLINE_VRS ) || ! ( strategy & REST_INLINE_FPRS ) || ! ( strategy & REST_INLINE_VRS ) ) ; if ( TARGET_MULTIPLE && ! TARGET_POWERPC64 && ! ( TARGET_SPE_ABI && info -> spe_64bit_regs_used ) && info -> first_gp_reg_save < <NUM_LIT> && ! ( flag_shrink_wrap && flag_shrink_wrap_separate &&

optimize_function_for_speed_p ( cfun ) ) ) {


<s> assert ( CPE && <STR_LIT> ) ; if ( -- CPE -> RefCount == <NUM_LIT> ) { removeDeadCPEMI ( CPEMI ) ; CPE -> CPEMI = nullptr ; -- NumCPEs


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT>


<s> if ( isUncondBranchOpcode ( Opc ) ) { MI . setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg


<s> gimple * def = SSA_NAME_DEF_STMT ( op ) ; tree tem ; if ( is_gimple_assign ( def ) && CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( def ) ) && ( ( tem = gimple_assign_rhs1 ( def ) ) , true ) && TREE_CODE ( tem ) == SSA_NAME && tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( def ) ) , TREE_TYPE ( tem ) ) ) def = SSA_NAME_DEF_STMT ( tem ) ; if ( ! is_gimple_assign ( def ) || ( ! gimple_assign_load_p ( def ) && ( gimple_assign_rhs_code ( def ) != BIT_FIELD_REF || ! VECTOR_TYPE_P ( TREE_TYPE ( TREE_OPERAND ( gimple_assign_rhs1 ( def ) , <NUM_LIT> ) ) ) )


<s> return ( uint64x1_t ) __builtin_neon_vsri_ndi ( ( int64x1_t )


<s> RegisterTarget < Triple :: ve , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ,


<s> if ( ShiftExtend . Amount % <NUM_LIT> != <NUM_LIT> || ShiftExtend . Amount > <NUM_LIT>


<s> unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize


<s> Instruction * Induction = nullptr ; if ( ! match ( I , m_ICmp ( Pred , m_Instruction ( Induction ) , m_Instruction ( Shuffle ) ) ) || Pred != ICmpInst :: ICMP_ULE || ! L -> isLoopInvariant ( Shuffle ) ) return false ; Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements ) return false ; Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV


<s> const LegalizerInfo * getLegalizerInfo ( ) const


<s> max = MAX_INSN_PER_IT_BLOCK ; if ( arm_condexec_count ) arm_condexec_count -- ; if ( arm_condexec_count ) return ; if ( GET_CODE ( body ) != COND_EXEC ) return ; if ( JUMP_P ( insn ) ) return ; predicate = COND_EXEC_TEST ( body ) ; arm_current_cc = get_arm_condition_code ( predicate ) ; n = get_attr_ce_count ( insn ) ; arm_condexec_count = <NUM_LIT> ; arm_condexec_mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; arm_condexec_masklen = n ; for ( ; ; ) { insn = next_nonnote_insn ( insn ) ; if ( ! NONJUMP_INSN_P ( insn ) && ! JUMP_P ( insn ) ) break ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == USE || GET_CODE ( body ) == CLOBBER ) continue ; if ( GET_CODE ( body ) != COND_EXEC ) break ; n = get_attr_ce_count ( insn ) ; if ( arm_condexec_masklen + n > max ) break ; predicate = COND_EXEC_TEST ( body ) ; code = get_arm_condition_code ( predicate ) ; mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; if ( arm_current_cc == code ) arm_condexec_mask |= ( mask << arm_condexec_masklen ) ; else if ( arm_current_cc != ARM_INVERSE_CONDITION_CODE ( code ) ) break ; arm_condexec_count ++ ; arm_condexec_masklen += n ; if ( JUMP_P ( insn )


<s> if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT


<s> int intregs , intoffset ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; } } startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; cum -> words += intregs ; if ( ( unsigned ) cum -> words < ( endbit / BITS_PER_WORD ) ) { int pad = ( endbit / BITS_PER_WORD ) - cum


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else { cerr << <STR_LIT> << MO << <STR_LIT> ; abort ( ) ; } return <NUM_LIT>


<s> bool <ISA_LIT>BasicMCBuilder :: RunBuildAfterHook ( bool Status , MCInst & MI , uint32_t insn ) { if ( ! SP ) return Status ; if ( Opcode == <STR_LIT> ) Status = SP -> InitIT ( slice ( insn , <NUM_LIT> ,


<s> static int ix86_reloc_rw_mask ( void ) { return ( flag_pic || ! ix86_direct_extern_access )


<s> } switch ( N -> getOpcode ( ) ) { case <STR_LIT> : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; } SelectCode (


<s> static bool mips_use_anchors_for_symbol_p ( const_rtx symbol ) { switch ( mips_classify_symbol ( symbol , SYMBOL_CONTEXT_MEM ) ) { case SYMBOL_PC_RELATIVE : case SYMBOL_GP_RELATIVE : return


<s> TOut . emitRRX ( <STR_LIT> , ATReg , GPReg , MCOperand :: createExpr ( GotExpr ) , IDLoc , STI ) ; } } else { const MCExpr * HiSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , HiSym , getContext ( ) ) ; if ( isABI_O32 ( ) || isABI_N32 ( ) ) { TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ; } else { const MCExpr * HighestSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HighestExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHEST , HighestSym , getContext ( ) ) ; const MCExpr * HigherSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HigherExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHER , HigherSym , getContext ( ) ) ; TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; } } return


<s> static bool UsesVectorABI ( StringRef CPU , StringRef FS ) { bool VectorABI = true ; if ( CPU . empty ( ) || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) VectorABI = false ; SmallVector < StringRef , <NUM_LIT> > Features ; FS . split ( Features , ',' , - <NUM_LIT> ,


<s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; ABI = <ISA_LIT>ABIInfo ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mipsel || STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mips ? <ISA_LIT>ABIInfo :: O32 ( ) : <ISA_LIT>ABIInfo :: N64 ( ) ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF


<s> EVT SrcVT = SrcVal . getValueType ( ) ; if ( SrcVT . isVector ( ) ) return LowerVectorFP_TO_INT_SAT ( Op , DAG ) ; EVT DstVT = Op . getValueType ( ) ; EVT SatVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; uint64_t SatWidth = SatVT . getScalarSizeInBits ( ) ; uint64_t DstWidth = DstVT . getScalarSizeInBits ( ) ; assert ( SatWidth <= DstWidth && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , SrcVal ) ; SrcVT = <STR_LIT> ; } else if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) && DstVT == SatVT && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return DAG . getNode ( Op . getOpcode (

) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ;


<s> static machine_mode ix86_mpx_bound_mode ( ) { if ( ! TARGET_MPX )


<s> assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; Name = <STR_LIT> ; getNameWithPrefix ( Name , GV ) ; return OutContext . GetOrCreateSymbol ( Name ) ; } else if ( Subtarget -> isTargetELF ( ) ) { return getSymbol (


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt


<s> if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { if ( DarwinDirective == <STR_LIT> || DarwinDirective == <STR_LIT> ) Mode = TargetSubtargetInfo


<s> static machine_mode pa_c_mode_for_suffix ( char suffix ) { if (


<s> return Kind == Register && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ||

<ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ;


<s> I = std :: find_if ( B , E , std :: ptr_fun ( isdigit ) ) ; Prefix = StringRef ( B , I - B ) ; if ( I == E ) return std :: make_pair (


<s> virtual bool requiresVirtualBaseRegisters ( const MachineFunction & MF )


<s> return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register BaseReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return


<s> dbgs ( ) << <STR_LIT> << Msg ; dbgs ( ) << <STR_LIT> ; if ( CurGroupDbg . empty ( ) ) dbgs ( ) << <STR_LIT> ; else { dbgs ( ) << <STR_LIT> << CurGroupDbg <<


<s> return new <ISA_LIT>ToTHMStub ( m_pData , m_Size ,


<s> if ( ! ( target_flags_explicit & MASK_LRA ) ) target_flags |= MASK_LRA ; if ( sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc ) { sparc_fix_b2bst = <NUM_LIT> ; sparc_fix_lost_divsqrt = <NUM_LIT> ; } if ( sparc_fix_ut699 ) target_flags &= ~ MASK_FSMULD ; if ( ! ( target_flags_explicit & MASK_LONG_DOUBLE_128 ) ) target_flags |= MASK_LONG_DOUBLE_128 ; if ( TARGET_DEBUG_OPTIONS ) dump_target_flags ( <STR_LIT> , target_flags ) ; if ( OPTION_SET_P ( sparc_code_model ) ) { if ( TARGET_ARCH32 ) error ( <STR_LIT> ) ; } else { if ( TARGET_ARCH32 ) sparc_code_model = CM_32 ; else sparc_code_model = SPARC_DEFAULT_CMODEL ; } if ( ! OPTION_SET_P ( sparc_memory_model ) ) { enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL ; if ( os_default != SMM_DEFAULT ) sparc_memory_model = os_default ; else if ( TARGET_V9 ) sparc_memory_model = SMM_RMO ; else if ( TARGET_LEON3 ) sparc_memory_model = SMM_TSO ; else if ( TARGET_LEON ) sparc_memory_model = SMM_SC ; else if ( TARGET_V8 ) sparc_memory_model = SMM_PSO ; else sparc_memory_model = SMM_SC ; } if ( flag_align_functions && ! str_align_functions ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 ) str_align_functions = <STR_LIT> ; else if ( sparc_cpu == PROCESSOR_NIAGARA7 || sparc_cpu == PROCESSOR_M8 ) str_align_functions = <STR_LIT> ; } if ( flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN ) flag_pcc_struct_return = ( TARGET_ARCH64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! TARGET_ARCH64 ) targetm . asm_out . unaligned_op . di = NULL ; switch ( sparc_cpu ) { case PROCESSOR_V7 : case PROCESSOR_CYPRESS : sparc_costs = & cypress_costs ; break ; case PROCESSOR_V8 : case PROCESSOR_SPARCLITE : case PROCESSOR_SUPERSPARC : sparc_costs = & supersparc_costs ; break ; case PROCESSOR_F930 : case PROCESSOR_F934 : case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : sparc_costs = & hypersparc_costs ; break ; case PROCESSOR_LEON : sparc_costs = & leon_costs ; break ; case PROCESSOR_LEON3 : case PROCESSOR_LEON3V7 : sparc_costs = & leon3_costs ; break ; case PROCESSOR_LEON5 : sparc_costs = & leon5_costs ; break ; case PROCESSOR_SPARCLET : case PROCESSOR_TSC701 : sparc_costs = & sparclet_costs ; break ; case PROCESSOR_V9 : case PROCESSOR_ULTRASPARC : sparc_costs = & ultrasparc_costs ; break ; case PROCESSOR_ULTRASPARC3 : sparc_costs = & ultrasparc3_costs ; break ; case PROCESSOR_NIAGARA : sparc_costs = & niagara_costs ; break ; case PROCESSOR_NIAGARA2 : sparc_costs = & niagara2_costs ; break ; case PROCESSOR_NIAGARA3 : sparc_costs = & niagara3_costs ; break ; case PROCESSOR_NIAGARA4 : sparc_costs = & niagara4_costs ; break ; case PROCESSOR_NIAGARA7 : sparc_costs = & niagara7_costs ; break ; case PROCESSOR_M8 : sparc_costs = & m8_costs ; break ; case PROCESSOR_NATIVE : gcc_unreachable ( ) ; } ; SET_OPTION_IF_UNSET ( & global_options , & global_options_set , param_simultaneous_prefetches , ( ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 ) ? <NUM_LIT> : ( sparc_cpu == PROCESSOR_ULTRASPARC3 ? <NUM_LIT> : ( ( sparc_cpu ==


<s> DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset += <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRR ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( shouldUseZeroOffsetLdSt ( N


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt


<s> return ( __m512i ) __builtin_ia32_vcvtph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , (


<s> if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; Register ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment ( ) ) ) return false ; updateValueMap ( I ,


<s> void printlea64_32mem ( const MachineInstr * MI , unsigned OpNo ) { printMemReference ( MI , OpNo ,


<s> MachineOperand & Scale = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Index = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Segment = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( ! ( ( Base . isReg ( ) && Base . getReg ( ) != <STR_LIT> ) || Base . isFI ( ) ) ) return false ; if ( ! Disp . isImm ( ) )


<s> assert ( ( OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> || OpdMapper

. getInstrMapping ( ) . getID ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI ->


<s> static bool isZeroImm ( const MachineOperand & op ) { return op . isImm ( ) && op . getImm ( ) ==


<s> return ( __m128i ) __builtin_ia32_expandloadhi128_mask ( ( const __v8hi * ) __C , ( __v8hi ) __A , (


<s> static rtx ia64_unpack_sign ( rtx vec , bool unsignedp ) { machine_mode mode = GET_MODE ( vec ) ; rtx zero = CONST0_RTX ( mode ) ; if ( unsignedp ) return zero ; else { rtx sign = gen_reg_rtx ( mode ) ; bool neg ; neg = ia64_expand_vecint_compare ( LT , mode , sign ,


<s> void <ISA_LIT>TargetAsmStreamer :: emitArchExtension ( unsigned ArchExt


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; for ( unsigned i = MI . getNumOperands ( ) - <NUM_LIT> , NumOps = <NUM_LIT> ; i != NumOps ; -- i ) { const MachineOperand & MO = MI . getOperand ( i ) ; string MO_name = TRI -> getName ( MO . getReg ( ) ) ; SExpr * SP_decr = ctx -> sub ( <NUM_LIT> , ctx -> load ( <NUM_LIT> , <STR_LIT> ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * subtr = ctx -> store ( ctx -> address ( <STR_LIT> ) , SP_decr ) ; alfbb . addStatement ( label + <STR_LIT> + MO_name + <STR_LIT> , <STR_LIT> , subtr ) ; SExpr * SP_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , <STR_LIT> ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * str = ctx -> store ( ctx -> address ( <STR_LIT> , SP_times_8 ) , ctx -> load ( <NUM_LIT> ,


<s> const TargetMachine & TM = MF . getTarget ( ) ; unsigned RegSize = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t StackAlignment = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; uint64_t Offset = RoundUpToAlignment ( MaxCallFrameSize , StackAlignment ) ; GlobalRegFI = MF . getFrameInfo ( ) -> CreateFixedObject ( RegSize , Offset , true ) ; return GlobalRegFI


<s> MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT ) ; SDValue ParentFrameOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , OffsetSymVal ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn


<s> else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> EVT VT = Op . getValueType ( ) ; if ( Op . getResNo ( ) != <NUM_LIT> || VT == <STR_LIT> ) return ; assert ( Known . getBitWidth ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; assert ( ( ! VT . isVector ( ) || ( DemandedElts . getBitWidth ( ) == VT . getVectorNumElements ( ) ) ) && <STR_LIT> ) ; unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { bool IsLogical = false ; unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : computeKnownBitsBinOp ( Op , Known , DemandedElts , DAG , Depth , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : \ if ( Masked ) \ return IsTestN ? <STR_LIT> ## SUFFIX ## k : <STR_LIT> ## SUFFIX ## k ; \ return IsTestN ? <STR_LIT> ## SUFFIX : <STR_LIT> ## SUFFIX ; default : llvm_unreachable ( <STR_LIT> ) ; \ VPTESTM_CASE ( v4i32 , DZ128 ## SUFFIX ) \ VPTESTM_CASE ( v2i64 , QZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i32 , DZ256 ## SUFFIX ) \ VPTESTM_CASE ( v4i64 , QZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i32 , DZ ## SUFFIX ) \ VPTESTM_CASE ( v8i64 , QZ ## SUFFIX ) VPTESTM_BROADCAST_CASES ( SUFFIX ) \ VPTESTM_CASE ( v16i8 , BZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i16 , WZ128 ## SUFFIX ) \ VPTESTM_CASE ( v32i8 , BZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i16 , WZ256

## SUFFIX ) \ VPTESTM_CASE ( v64i8 , BZ ## SUFFIX ) \ VPTESTM_CASE ( v32i16 , WZ ## SUFFIX ) if ( FoldedBCast ) {


<s> break ; case RegisterSeq : OS << <STR_LIT> ; OS << RegName ( getRegSeq ( ) . first ) << <STR_LIT> << RegName ( getRegSeq ( ) . second ) << <STR_LIT> ; break ; case RegisterList : OS << <STR_LIT> ; OS << RegName ( getRegList ( ) . List1From ) << <STR_LIT> << RegName ( getRegList ( ) . List1To ) << <STR_LIT> ; OS << RegName ( getRegList ( ) . List2From ) << <STR_LIT> << RegName ( getRegList ( ) . List2To ) << <STR_LIT> ; OS << RegName ( getRegList ( ) . List3From ) << <STR_LIT>

<< RegName ( getRegList ( ) . List3To ) << <STR_LIT> ;


<s> unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode


<s> case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering :: Acquire : case AtomicOrdering :: AcquireRelease : return Builder . CreateFence ( AtomicOrdering :: Acquire ) ; case AtomicOrdering :: SequentiallyConsistent : return Builder . CreateFence ( AtomicOrdering :: SequentiallyConsistent ) ; } llvm_unreachable ( <STR_LIT>


<s> bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = getLoadStoreRegOp ( * MBBI ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( * MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( * MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub = true ; } if ( InsertSub ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) , true ) . addReg ( Base ) . addImm ( WordOffset * <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ; return ; } if ( MBBI -> killsRegister ( Base ) || MBBI -> definesRegister ( Base ) ) return ; } if ( MBB . succ_size ( ) > <NUM_LIT>


<s> void <ISA_LIT>InstPrinterCommon :: printInstFlags ( const MCInst * MI , raw_ostream & O , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; if ( ( Flags & <STR_LIT> ) || ( TSFlags & <STR_LIT> ) ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> )


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseAddSubImm ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; const MCExpr * Imm ; if ( parseSymbolicImmVal ( Imm ) ) return MatchOperand_ParseFail ; else if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { uint64_t ShiftAmount = <NUM_LIT> ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Imm ) ; if ( MCE ) { int64_t Val = MCE


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering (


<s> HOST_WIDE_INT align ; align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ; return IN_RANGE ( offset , <NUM_LIT>


<s> } SDValue FIPtr = DAG . CreateStackTemporary ( <STR_LIT> ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , FIPtr . getValueType ( ) ) ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , Chain


<s> return isMem512 ( ) && isMemIndexReg


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; } MCE . addRelocation ( GetRelocation ( MO


<s> if ( TARGET_DEBUG_COST ) dbg_cost_ctrl ++ ; if ( reg_classes_intersect_p ( rclass , GENERAL_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else if ( ( reg_classes_intersect_p ( rclass , FLOAT_REGS ) || reg_classes_intersect_p ( rclass , VSX_REGS ) ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else if ( reg_classes_intersect_p ( rclass , ALTIVEC_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_ALTIVEC_REGNO , mode ) ; else ret = <NUM_LIT> + rs6000_register_move_cost (


<s> pasubub ( uint8x8_t s , uint8x8_t t ) { return __builtin_loongson_pasubub ( s ,


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant

, Size , inferAlignFromPtrInfo ( MF , MPO ) ) ;


<s> bool isLegalMaskedGather ( Type * DataType ) { return ST ->


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit

, uint32_t CPUType , uint32_t CPUSubtype ) {


<s> if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; if ( imm != INT32_MIN ) imm <<= shift ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler ::


<s> llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return None ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol


<s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count ) ; return true


<s> location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V4HFmode : gen = gen_neon_vextv4hf ; break ; case V8HFmode : gen = gen_neon_vextv8hf ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> rtx return_reg ; int only_popret_RA = ( save_regs [ RETURN_ADDRESS_REGNUM ] && ( sum_regs == UNITS_PER_WORD ) ) ; return_reg = gen_rtx_REG ( Pmode , RETURN_ADDRESS_REGNUM ) ; if ( frame_pointer_needed ) emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; if ( size_for_adjusting_sp > <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size_for_adjusting_sp ) ) ) ; if ( crx_interrupt_function_p ( ) ) emit_jump_insn ( gen_interrupt_return ( ) ) ; else if ( last_reg_to_save == - <NUM_LIT> ) emit_jump_insn ( gen_indirect_jump_return ( ) ) ; else if ( only_popret_RA ) emit_jump_insn ( gen_popret_RA_return ( ) ) ; else emit_jump_insn ( gen_pop_and_popret_return ( GEN_INT ( sum_regs


<s> void <ISA_LIT>PagerandoOptimizer :: optimizeCalls ( MachineInstr * MI , const Function * Callee ) { auto & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > Queue { MI } ; while ( ! Queue . empty ( ) ) { MI = Queue . pop_back_val ( ) ; if ( ! MI -> isCall ( ) ) { for ( auto & Op : MI -> defs ( ) ) { for ( auto & User : MRI . use_instructions ( Op . getReg ( ) ) ) Queue . push_back ( & User ) ; } MI -> eraseFromParent ( ) ; } else if ( isBXCall ( MI -> getOpcode ( ) ) ) { changeToPCRelativeCall ( MI , Callee ) ; } else


<s> enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , <NUM_LIT> ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return


<s> bool FirstFeature = true ; std :: string Msg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MissingFeatures . size ( ) ; i != e ; ++ i ) { if ( MissingFeatures [ i ] ) { Msg += FirstFeature ? <STR_LIT> : <STR_LIT> ; Msg += getSubtargetFeatureName ( i ) ; FirstFeature = false ; } } return Error ( IDLoc , Msg ) ; } case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS , <NUM_LIT> ) ; return Error ( IDLoc , <STR_LIT> + Suggestion ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2plus1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm15 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm14lsl2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm16 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm16lsl2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) ,


<s> return __builtin_ia32_scalefsh_mask_round ( __A , __B , _mm_setzero_ph ( ) , (


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true


<s> case <STR_LIT> : return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup .


<s> bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> ; bool RHSConst = ( isSplatVector ( N1 . getNode ( ) ) && isa < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) ; if ( ! RHSTrunc && ! RHSConst ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , WideVT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT> ) ; if ( RHSConst ) { N1 = DAG . getNode ( <STR_LIT> , DL , WideVT . getScalarType ( ) , N1 -> getOperand ( <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > C ( WideVT . getVectorNumElements ( ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , DL , WideVT , C ) ; } else if ( RHSTrunc ) { N1 = N1 -> getOperand ( <NUM_LIT> ) ; } SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , WideVT , N0 , N1 ) ; unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : return Op ; case <STR_LIT> : { unsigned InBits = NarrowVT . getScalarType ( ) . getSizeInBits ( ) ; APInt Mask = APInt ::


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; return BB


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> )

. getReg ( ) ) . addImm ( maxCallFrameSize ) ;


<s> HOST_WIDE_INT len , pos ; if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; len = INTVAL ( size ) ; pos = INTVAL ( position ) ; if ( len <= <NUM_LIT> || len >= GET_MODE_BITSIZE ( GET_MODE ( op ) ) || pos < <NUM_LIT> ||

pos + len > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ;


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLSDouble ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; const MachineOperand & BaseOp = MI . getOperand ( <NUM_LIT> ) ; unsigned Base = BaseOp . getReg ( ) ; const MachineOperand & Reg0Op = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Reg1Op = MI . getOperand ( <NUM_LIT> ) ; if ( Reg0Op . getReg ( ) == Base || Reg1Op . getReg ( ) == Base ) return false ; unsigned PredReg ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return


<s> SDValue Flag = <ISA_LIT>_EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Flag } ; return DAG . getNode ( <STR_LIT> , dl


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 (