<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . getOpcode ( ) == <STR_LIT> ) InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getOpcode ( ) == <STR_LIT> ) InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) { if ( ExpectedOpcode == <STR_LIT> ) return SDValue ( ) ; std :: swap ( Op0 , Op1 ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } if ( InVec1 != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; } if ( AddFound && SubFound && InVec0 . getOpcode ( )

!= <STR_LIT> && InVec1 . getOpcode ( ) != <STR_LIT> ) {


<s> SDValue getAddrGlobal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const


<s> unsigned WideBits = getScalarSizeInBits ( Ty ) * Ty -> getVectorNumElements ( ) ; assert ( WideBits > <NUM_LIT> && <STR_LIT> ) ; return ( ( WideBits % <NUM_LIT> ) ? ( ( WideBits / <NUM_LIT> ) +

<NUM_LIT> ) : ( WideBits / <NUM_LIT> ) ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( const


<s> virtual const char * getPassName ( ) const LLVM_OVERRIDE { return


<s> void <ISA_LIT>AsmParser :: EmitInstruction ( MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > &


<s> return ( __m128 ) __builtin_ia32_vpermil2ps ( ( __v4sf ) __X , ( __v4sf )


<s> unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm ::


<s> for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant > ( SE -> getNegativeSCEV ( Offset ) ) ; } std :: swap ( BucketChain . Elements [ j

] , BucketChain . Elements [ <NUM_LIT> ] ) ;


<s> return Flag ? CC_<ISA_LIT>64_ELF_FIS :


<s> void <ISA_LIT>PostRASchedStrategy :: leaveMBB ( ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; ) ; advanceTo ( MBB -> getFirstTerminator ( )


<s> HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( ( off1 <= off2 ) && ( off1 + size1 > off2 ) ) || ( ( off2


<s> if ( RegisterSDNode * RegNode = dyn_cast_or_null < RegisterSDNode > ( Base . Reg . getNode ( ) ) ) return


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT MaskEltVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SmallVector < SDValue , <NUM_LIT> > VPermMask ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) VPermMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( MaskEltVT ) : DAG . getConstant ( Mask [ i ] , DL , MaskEltVT ) ) ; SDValue MaskNode = DAG . getNode ( <STR_LIT> , DL , MaskVecVT , VPermMask ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , MaskNode ,


<s> rtx_code code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT> ) & ~ used ; if ( dead & attempt ) { dead &= attempt ; break ; } if ( code == JUMP_INSN ) { if ( jump_left -- && simplejump_p ( scan ) ) scan = JUMP_LABEL_AS_INSN ( scan ) ; else break ; } } } dead &= <NUM_LIT> ; } else if ( optimize && need_block >= <NUM_LIT> ) { rtx_insn * next = next_active_insn ( as_a < rtx_insn * > ( dest ) ) ; next = next_active_insn ( next ) ; if ( next && JUMP_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SET && recog_memoized ( next ) == CODE_FOR_jump_compact ) { dest = JUMP_LABEL ( next ) ; if ( dest && ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - addr + ( unsigned ) <NUM_LIT> > <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( next , INSN_ADDRESSES ( INSN_UID ( next ) ) , - <NUM_LIT> ) ; } } if ( dead


<s> if ( rclass == GENERAL_REGS && MEM_P ( x ) )


<s> return __builtin_mve_vmlaldavaq_sv8hi ( __a ,


<s> return lowerMSASplatImm ( SDLoc ( Op ) , Op -> getValueType ( <NUM_LIT> ) , Op -> getOperand (


<s> static inline uint8_t encodeAdvSIMDModImmType9 ( uint64_t Imm ) { return ( Imm &


<s> const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; uint32_t Reg = RI -> getRegClass ( <STR_LIT> ) . getRegister (

RI -> getEncodingValue ( getReg ( ) ) ) ;


<s> void <ISA_LIT>InstPrinter :: printVRegOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isReg ( ) &&


<s> static DecodeStatus DecodeSVCROp ( MCInst & Inst , unsigned Imm , uint64_t Address ,


<s> if ( forceFixedWidth ) return false ; return ST -> hasSVE ( )


<s> if ( ISA_HAS_MSA && FP_REG_P ( regno ) && GET_MODE_SIZE ( mode ) > <NUM_LIT> ) return true ; return


<s> inline bool Pred_so_imm ( SDNode * inN ) const { ConstantSDNode * N = cast < ConstantSDNode > ( inN ) ; return is_so_imm ( N -> getZExtValue


<s> static void addPostLoopLiveIns ( MachineBasicBlock * MBB , LivePhysRegs & LiveRegs ) { for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MBB -> addLiveIn (


<s> if ( IntKind == <STR_LIT> ) { MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; unsigned InsPosition = <NUM_LIT> ; unsigned InsSize = <NUM_LIT> ; unsigned SrcReg = <STR_LIT> ; if ( IntKind == <STR_LIT> ) { SrcReg = <STR_LIT> ; InsPosition = <NUM_LIT> ; InsSize = <NUM_LIT>


<s> SDValue SaveSP = Op . getOperand ( <NUM_LIT> ) ; SDValue LoadLinkSP = DAG . getLoad ( PtrVT , dl , Chain , StackPtr , NULL , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( LoadLinkSP . getValue ( <NUM_LIT>


<s> case <STR_LIT> : return FirstOpc == SecondOpc ; case <STR_LIT> : case <STR_LIT> : return SecondOpc == <STR_LIT> || SecondOpc ==


<s> bool result = mep_use_post_modify_p_1 ( insn , reg


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Module & M , const std :: string & FS ) { IsV9 = false ; V8DeprecatedInsts = false ; IsVIS = false ; std :: string CPU = <STR_LIT> ; CPU = <STR_LIT> ; ParseSubtargetFeatures ( FS , CPU ) ; if ( ! EnableV9 ) IsV9 =


<s> return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID , <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; if ( ! Memory . OffsetRegNum ) { <STR_LIT> AddSub = Val < <NUM_LIT>


<s> reg = gen_reg_rtx ( Pmode ) ; } rtx_insn * insn ; if ( ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) && ( SYMBOL_REF_DECL ( orig ) ? ! DECL_WEAK ( SYMBOL_REF_DECL ( orig ) ) : <NUM_LIT> ) ) ) && NEED_GOT_RELOC && arm_pic_data_is_text_relative ) insn = arm_pic_static_addr ( orig , reg ) ; else { rtx pat ; rtx mem ; require_pic_register ( pic_reg , compute_now ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = <NUM_LIT> ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; insn = emit_insn ( pat ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; return orig ; } if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg , pic_reg , compute_now ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg , pic_reg , compute_now ) ; if ( CONST_INT_P ( offset ) ) { if ( ! arm_legitimate_index_p ( mode , offset


<s> Op -> Expr . Val = Val ; Op -> Expr . CRVal = EvaluateCRExpr ( Val ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64


<s> void <ISA_LIT>InstPrinter :: printMRSSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } if ( Val ==


<s> if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MI . setDesc ( TII -> get ( Opcode ) ) ; tieOpsIfNeeded ( MI ) ; return true


<s> const char * mep_emit_bb_trace_ret ( void ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT>


<s> switch ( CM ) { default : break ; case CodeModel :: Default : case CodeModel :: JITDefault : CM = CodeModel :: Small ; break ; } X -> InitMCCodeGenInfo ( RM ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> )


<s> static rtx mips16e_build_save_restore ( bool restore_p , unsigned int * mask_ptr , HOST_WIDE_INT * offset_ptr , unsigned int nargs , HOST_WIDE_INT size ) { rtx pattern , set ; HOST_WIDE_INT offset , top_offset ; unsigned int i , regno ; int n ; gcc_assert ( cfun -> machine -> frame . num_fp == <NUM_LIT> ) ; n = <NUM_LIT> + nargs ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) if ( BITSET_P ( * mask_ptr , mips16e_save_restore_regs [ i ] ) ) n ++ ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( n ) ) ; n = <NUM_LIT> ; set = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , restore_p ? size : - size ) ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; XVECEXP ( pattern , <NUM_LIT> , n ++ ) = set ; top_offset = restore_p ? size


<s> case k_CoprocNum : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case k_CoprocReg : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case k_CoprocOption : OS << <STR_LIT> << CoprocOption . Val << <STR_LIT> ; break ; case k_MSRMask : OS << <STR_LIT> << getMSRMask ( ) << <STR_LIT> ; break ; case k_Immediate : getImm ( ) -> print ( OS ) ; break ; case k_MemBarrierOpt : OS << <STR_LIT> << MemBOptToString ( getMemBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> << <STR_LIT> << Memory . BaseRegNum ; OS << <STR_LIT> ; break ; case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << PostIdxReg . RegNum ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegShiftedReg . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegShiftedReg . ShiftReg << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegShiftedImm . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ; } case


<s> if ( CC == CallingConv :: GHC ) return NULL ; return ( STI . isTargetIOS ( ) && ! STI .


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill


<s> if ( ! MF ) continue ; Changed |= runOnMachineFunction ( * MF ) ; } return Changed


<s> return ( uint8x16_t ) __builtin_neon_vcgtv16qi (


<s> return __builtin_ia32_maxph256_mask ( __A , __B , _mm256_setzero_ph ( ) , (


<s> ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint


<s> case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static bool glibc_supports_ieee_128bit ( void ) { if ( OPTION_GLIBC && ! BYTES_BIG_ENDIAN && ( ( TARGET_GLIBC_MAJOR * <NUM_LIT> ) + TARGET_GLIBC_MINOR ) >=


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) .


<s> return ( __m128i ) __builtin_ia32_phsubsw128 ( ( __v8hi


<s> for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || isa < ConstantExpr > ( Cst ) ) continue ; if ( ! shouldConvert ( * Cst ,


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI


<s> MCSymbol * <ISA_LIT>ELFStreamer :: emitCFILabel ( ) { MCSymbol * Label = getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MCELFStreamer :: emitLabel ( Label ) ; return Label


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isN64 ( ) ) return DecodeGPR64RegisterClass ( Inst , RegNo , Address ,


<s> static __inline vec_ullong2 spu_cmpgt ( vec_double2 a , vec_double2 b ) { return ( ( vec_ullong2 ) ( si_dfcgt ( ( qword ) ( a ) , ( qword ) ( b ) )


<s> bool aarch64_harden_sls_blr_p ( void ) { return aarch64_sls_hardening &


<s> assert ( ( Kind == k_Register || Kind == k_WrappedRegister ) && <STR_LIT> ) ; return Reg


<s> return ( __m128d ) __builtin_ia32_extractf64x2_512_mask ( ( __v8df ) __A , __imm , ( __v2df ) _mm_setzero_pd ( ) ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOneValue ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isNullValue ( ) ) return DAG . getNode ( <STR_LIT> , DL ,

VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ;


<s> inline void vec_mtvscr ( vector unsigned char a1 ) { __builtin_altivec_mtvscr ( ( vector signed int )


<s> if ( AvailableForFeatures && ! ( AvailableForFeatures & FeatureBits ) ) return false ; return Name ==


<s> if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt (


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl


<s> static DecodeStatus DecodeHWRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo


<s> case IES_MULTIPLY : if ( PrevState == IES_INTEGER ) { if ( IndexReg ) { ErrMsg = <STR_LIT> ; return true ; } State = IES_REGISTER ; IndexReg = Reg ; Scale = IC . popOperand ( ) ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . pushOperand (


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> )


<s> return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( )


<s> return ( __m128i ) __builtin_ia32_pmovdw256_mask ( ( __v8si ) __A , (


<s> case <STR_LIT> : case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandSelectCC ( MI , BB


<s> STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> )


<s> unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL (


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock (


<s> inline vector unsigned short vec_vsplth ( vector unsigned short a1


<s> rtx nds32_expand_store_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = <NUM_LIT> ; par_index < count ; par_index ++ ) { offset = par_index * <NUM_LIT> ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET ( mem , reg ) ; } return result


<s> bool isProfitableToUnpredicate ( ) const { return IsProfitableToUnpredicate


<s> static bool isAnyInRange ( ArrayRef < int >


<s> MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SwapVector [ EntryIdx ] . VSEId << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! isVecReg ( Reg ) && !


<s> SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VTs , & Ops [ <NUM_LIT> ] , Ops


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true


<s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Adjust ; break ; } } } else if ( Subtarget . isSwift ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool isSub = <STR_LIT> ( ShOpVal ) == <STR_LIT> ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ! isSub && ( ShImm == <NUM_LIT> || ( ( ShImm == <NUM_LIT> || ShImm == <NUM_LIT> || ShImm == <NUM_LIT> ) && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) ) Adjust -= <NUM_LIT> ; else if ( ! isSub && ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Adjust ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) Adjust -= <NUM_LIT> ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . checkVLDnAccessAlignment ( ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeAddrMode7Operand ( MCInst & Inst , unsigned Val , uint64_t Address


<s> static void arm_elf_asm_destructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol , priority


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Lex ( ) ; MCSymbol * Alias = getContext ( ) . GetOrCreateSymbol ( Name ) ; getTargetStreamer ( ) . emitThumbSet ( Alias , Value ) ; return


<s> arm_simd_polyTI_type_node = build_distinct_type_copy ( unsigned_intTI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyTI_type_node , <STR_LIT> ) ; arm_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; arm_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; arm_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] .


<s> bool <ISA_LIT>PreLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { CombinerHelper Helper ( Observer , B , KB , MDT ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { bool Changed = false ; Changed |= Helper . tryCombineExtendingLoads ( MI ) ; Changed |= Helper . tryCombineIndexedLoadStore ( MI ) ; return Changed ; } case TargetOpcode :: G_STORE : return Helper . tryCombineIndexedLoadStore ( MI ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt


<s> Immed = std :: abs ( Immed ) ; bool IsLegal = ( ( Immed >> <NUM_LIT> ) == <NUM_LIT> || ( ( Immed

& <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) ) ;


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool Result = ( Index * ElSize


<s> auto BuildLoad = [ ] ( MachineIRBuilder & MIRBuilder , MachinePointerInfo & MPO , LLT MemTy , const DstOp & Res , Register Addr ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } ; BuildLoad ( MIRBuilder , MPO , MemTy


<s> case Triple :: MachO : return new <ISA_LIT>AsmBackendDarwin ( T , STI , MRI ) ; case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>AsmBackendWinCOFF ( T , STI . getTargetTriple ( ) . isThumb ( ) ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new <ISA_LIT>AsmBackendELF ( T , STI . getTargetTriple ( ) . isThumb ( ) , OSABI


<s> bool free_insn_info ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg


<s> static DecodeStatus DecodeDFPRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( FuncInfo -> isLeafProc ( ) ) { FrameReg = <STR_LIT> ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ; else FrameReg = <STR_LIT> ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize


<s> SDValue CCVal = N -> getOperand ( <NUM_LIT> ) ; SDValue Cmp = N -> getOperand ( <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( CCVal ) && <STR_LIT> ) ; unsigned CC = cast < ConstantSDNode > ( CCVal ) -> getZExtValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpc = Cmp . getOpcode ( ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) || ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) && <STR_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isNullConstant ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode (


<s> codes [ <NUM_LIT> ] . value = low_part & ~ ( IMM_REACH - <NUM_LIT> ) ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - <NUM_LIT> ) ; if ( iorv != <NUM_LIT> ) { codes [ <NUM_LIT> ] . code = IOR ; codes [ <NUM_LIT> ] . method = METHOD_NORMAL ; codes [ <NUM_LIT> ] . value = iorv ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ <NUM_LIT> ] = { ( value & LU32I_B ) == <NUM_LIT> , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ <NUM_LIT> ] = { ( value & LU52I_B ) == <NUM_LIT> , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> <NUM_LIT> ) << <NUM_LIT> ; return cost + <NUM_LIT> ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( ( value << <NUM_LIT> ) >> <NUM_LIT> ) << <NUM_LIT> ; cost ++ ; if ( ! lu52i [ ( value & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value =


<s> <ISA_LIT>MCTargetExpr * <ISA_LIT>MCTargetExpr :: Create ( const MCSymbol * Sym , VariantKind K , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCTargetExpr (


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { if ( GET_CODE ( XEXP ( link , <NUM_LIT> ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN


<s> static <ISA_LIT>Operand * CreateMSRMask ( unsigned MMask , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( MSRMask ) ; Op -> MMask . Val = MMask ; Op -> StartLoc =


<s> SysAliasReg ( const char * N , uint16_t E , bool R , FeatureBitset F ) : SysAlias


<s> LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else MI . getOperand ( ConstantOpNo ) . ChangeToImmediate ( Imm ) ; } else if ( III . IsCommutative ) { MI . getOperand ( ConstantOpNo ) . ChangeToImmediate ( Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( ! III . ZeroIsSpecialOrig ) { unsigned RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify ,


( <NUM_LIT> << PROCESSOR_SPARCLITE86X ) ) ) return <NUM_LIT> ;


<s> static Optional < Instruction * > instCombineSVESel ( InstCombiner & IC , IntrinsicInst & II ) { IRBuilder < > Builder ( & II ) ; auto Select = Builder . CreateSelect ( II . getOperand ( <NUM_LIT> ) , II .

getOperand ( <NUM_LIT> ) , II . getOperand ( <NUM_LIT> ) ) ;


<s> ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt


<s> KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) KnownZero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( )


<s> } return true ; } rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { for ( int i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , <NUM_LIT> , i ) ) ) return true ; pattern = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( ! REG_P ( SET_DEST ( pattern ) ) || REGNO ( reg )

!= REGNO ( SET_DEST ( pattern ) ) ) return true ;


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex


<s> static DecodeStatus DecodeCPURegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [


<s> EmitSled ( MI , SledKind :: TAIL_CALL


<s> SDValue Ops [ ] = { DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) , Glue } ; return DAG . getNode ( <STR_LIT> , DL


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB


<s> BS . second = AlignExtra ; FuncSize += AlignExtra ; } unsigned BlockSize = <NUM_LIT> ; for ( MachineInstr & MI : * MBB ) { BlockSize += TII -> getInstSizeInBytes ( MI ) ; if ( MI . isInlineAsm ( ) && ( FirstImpreciseBlock < <NUM_LIT> ) ) FirstImpreciseBlock = MBB -> getNumber ( ) ; } BlockSizes [ MBB -> getNumber ( ) ] . first = BlockSize ; FuncSize += BlockSize


<s> if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> Pred = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CRReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ( Pred ) ) . addReg ( CRReg ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> )


<s> if ( Immed == <NUM_LIT> ) return false ; if ( N . getValueType ( ) == <STR_LIT> ) Immed = ~ ( ( uint32_t ) Immed ) + <NUM_LIT> ; else Immed = ~ Immed + <NUM_LIT>


<s> if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && STI


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>EmitIntExt ( MVT SrcVT , unsigned SrcReg , MVT DestVT , bool isZExt ) { if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return <NUM_LIT> ; unsigned Opc ; bool isBoolZext = false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; switch ( SrcVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( ! Subtarget -> hasV6Ops ( ) ) return <NUM_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( isZExt ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasV6Ops ( ) ) return <NUM_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( isZExt ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isZExt ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; isBoolZext = true ; break ; } return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; if ( isBoolZext ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB )


<s> return ( __m128 ) __builtin_ia32_unpckhps ( ( __v4sf ) __A , (


<s> bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( OrigMask , Zeroable , V2IsZero , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , OrigMask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( find ( WidenedMask , SM_SentinelZero ) != WidenedMask . end ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != <STR_LIT> && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) return SDValue ( ) ; SDValue Ext1 = FirstInput . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue


<s> <ISA_LIT>HazardRecognizer970 :: <ISA_LIT>HazardRecognizer970 ( const ScheduleDAG & DAG


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get


<s> MCE . addRelocation ( MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV


<s> unsigned Offset = StackOffset + MFI -> getObjectOffset ( i ) - CalleeSavedAreaSize ; if ( LastOffsetFI == - <NUM_LIT> ) LastOffsetFI = i ; if ( Offset > MFI -> getObjectOffset ( LastOffsetFI ) ) LastOffsetFI = i ; MFI -> setObjectOffset ( i , Offset ) ; } if ( LastOffsetFI >= <NUM_LIT> ) StackOffset = MFI -> getObjectOffset ( LastOffsetFI ) + MFI -> getObjectSize ( LastOffsetFI ) ; StackOffset = ( ( StackOffset + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { if ( CSI [ i ] . getRegClass ( ) != <STR_LIT> ) break ; MFI -> setObjectOffset ( CSI [ i ] . getFrameIdx ( ) , StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += MFI -> getObjectAlignment ( CSI [ i ] . getFrameIdx ( ) ) ; } if ( hasFP ( MF ) || MFI -> hasCalls ( ) ) { MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setFPStackOffset ( StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setRAStackOffset ( StackOffset ) ; StackOffset +=


<s> StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return Error ( L , <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Name ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , getContext ( ) ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst , getSTI (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i32scatter_pd ( void * addr , __mmask8 mask , __m256i index , int scale , int hint ) { __builtin_ia32_scatterpfdpd ( mask , ( __v8si ) index , ( long long const *


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , machine_mode mode ) { return ( mode == CCFPmode ? reverse_condition_maybe_unordered ( code ) : reverse_condition (


<s> newd . target = d -> target ? gen_lowpart ( new_mode , d -> target ) : NULL ; newd . op0 = d -> op0 ? gen_lowpart ( new_mode , d -> op0 ) : NULL ; newd . op1 = d -> op1 ? gen_lowpart ( new_mode , d -> op1 ) : NULL ; newd . testing_p = d -> testing_p ; newd . one_vector_p = d -> one_vector_p ; newd . perm . new_vector ( newpermconst , newd . one_vector_p ? <NUM_LIT> : <NUM_LIT> , nelt / <NUM_LIT> ) ; return aarch64_expand_vec_perm_const_1 ( & newd


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - CE -> getValue


<s> if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else read_only_private_data_section ( )


<s> int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ; return vectorCostAdjustment ( Cost , Opcode , ValTy , nullptr


<s> SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> static void computeCalleeSaveRegisterPairs ( MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI , SmallVectorImpl < RegPairInfo > & RegPairs , bool & NeedShadowCallStackProlog ) { if ( CSI . empty ( ) ) return ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx ,


<s> case FFSig : Parms = <STR_LIT> ; break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> EmitLabel ( Stub ) ; assert ( TM . getRelocationModel ( ) != Reloc :: PIC_ && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig , LE , true ) ; EmitJal ( * STI , MSymbol ) ; EmitSwapFPIntRetval ( * STI , Signature -> RetSig , LE ) ; EmitInstrReg ( * STI , <STR_LIT> , <STR_LIT> ) ; MCSymbol * Tmp = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( Tmp ) ; const MCSymbolRefExpr * E = MCSymbolRefExpr :: create ( Stub , OutContext ) ; const MCSymbolRefExpr * T = MCSymbolRefExpr :: create ( Tmp , OutContext ) ; const MCExpr * T_min_E = MCBinaryExpr :: createSub ( T , E , OutContext ) ; OutStreamer -> emitELFSize ( Stub , T_min_E ) ; TS . emitDirectiveEnd ( x ) ; OutStreamer -> PopSection


<s> case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return mode ; default : gcc_unreachable (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return __aarch64_vget_lane_any ( __a ,


<s> PM . add ( create<ISA_LIT>ISelDag ( * this


<s> static struct machine_function * loongarch_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > (


<s> Optional < int > <ISA_LIT>StackTaggingPreRA :: findFirstSlotCandidate ( ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! ClFirstSlot ) return None ; DenseMap < SlotWithTag , int > RetagScore ; SlotWithTag MaxScoreST { - <NUM_LIT> , - <NUM_LIT> } ; int MaxScore = - <NUM_LIT> ; for ( auto * I : ReTags ) { SlotWithTag ST { * I } ; if ( isSlotPreAllocated ( MFI , ST . FI ) ) continue ; Register RetagReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( RetagReg ) ) continue ; int Score = <NUM_LIT> ; SmallVector < Register , <NUM_LIT> > WorkList ; WorkList . push_back ( RetagReg ) ; while ( ! WorkList . empty ( ) ) { Register UseReg = WorkList . pop_back_val ( ) ; for ( auto & UseI : MRI -> use_instructions ( UseReg ) ) { unsigned Opcode = UseI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) continue ; if ( UseI . isCopy ( ) ) { Register DstReg = UseI . getOperand ( <NUM_LIT> ) . getReg


<s> else cfun -> machine -> call_abi = ix86_function_type_abi


<s> Value * <ISA_LIT>IREmitter :: visitVST2_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_DATA ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REL_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REL_24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_H ; case


<s> tree ovfl , gtop , ftop , goff , foff ; tree t ; int gpr_save_area_size ; int fpr_save_area_size ; int fpr_offset ; cum = & current_function_args_info ; gpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_gprs ) * UNITS_PER_WORD ; fpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_fprs ) * UNITS_PER_FPREG ; f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gtop = TREE_CHAIN ( f_ovfl ) ; f_ftop = TREE_CHAIN ( f_gtop ) ; f_goff = TREE_CHAIN ( f_ftop ) ; f_foff = TREE_CHAIN ( f_goff ) ; ovfl = build ( COMPONENT_REF , TREE_TYPE ( f_ovfl ) , valist , f_ovfl , NULL_TREE ) ; gtop = build ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > <NUM_LIT> ) t = build ( PLUS_EXPR , TREE_TYPE ( ovfl ) , t ,

build_int_cst ( NULL_TREE , cum -> stack_words * UNITS_PER_WORD ) ) ;


<s> tmp = vec_or ( tmp , vec_sld ( tmp , tmp , <NUM_LIT> ) ) ; return ( ( qword ) ( vec_and ( tmp , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB

, MachineBasicBlock :: iterator I ) const {


<s> unsigned i = <NUM_LIT> ; while ( ! MI -> getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale )


<s> return ( __m128 ) __builtin_ia32_vfmaddps ( ( __v4sf ) __A ,


<s> static bool isi32Load ( unsigned Opc


<s> virtual void initializePass ( ) override { pushTTIStack ( this


<s> unsigned UseIdx ; int CommuteIdx = - <NUM_LIT> ; bool TieOps = false ; switch ( UseOpc ) { case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; default : return false ; } if ( CommuteIdx != - <NUM_LIT> ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI .


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AlignmentIsInBytes = false ; COMMDirectiveTakesAlignment = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = NULL ; PrivateGlobalPrefix = <STR_LIT> ; JumpTableDataSection = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; BSSSection = <STR_LIT> ; CStringSection = <STR_LIT> ; if ( ! Subtarget -> hasABICall ( ) ) { JumpTableDirective = <STR_LIT> ; SmallDataSection = getNamedSection ( <STR_LIT> , SectionFlags :: Writeable


<s> LastOpcode = Opcode ; if ( ++ NumMove == <NUM_LIT> ) break ; } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && MemOps . count ( InsertPos ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , OffReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , OffReg , Offset , PredReg , Pred ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; if ( isLd ) { BuildMI ( * MBB , InsertPos , dl , TII -> get ( NewOpc ) ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; ++ NumLDRDFormed


<s> if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ; return NO_REGS


<s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>CC , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , Tmp3


<s> if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } return


<s> if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( CPULoc , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , <STR_LIT> ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension


<s> case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) )


<s> unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> assert ( isa < IntegerType > ( Dst ) && isa < IntegerType > ( Src ) && <STR_LIT> ) ; auto Cost = getVectorInstrCost ( Instruction :: ExtractElement , VecTy , Index ) ; auto VecLT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; auto DstVT = TLI -> getValueType ( DL , Dst ) ; auto SrcVT = TLI -> getValueType ( DL , Src ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; if ( ! VecLT . second . isVector ( ) || ! TLI -> isTypeLegal ( DstVT ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , CostKind ) ; if ( DstVT . getSizeInBits ( ) < SrcVT . getSizeInBits ( ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , CostKind ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SExt


<s> static DecodeStatus DecodeVCVTD ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool hasFullFP16 = featureBits [ <STR_LIT> ] ; unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode (


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < Register , Register > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case <STR_LIT> : Odd = <NUM_LIT> ; break ; case <STR_LIT> : Odd = <NUM_LIT> ; break ; case <STR_LIT> : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; if ( MRI . getRegClass ( VirtReg ) -> contains ( <STR_LIT> ) ) Hints . push_back ( <STR_LIT> ) ; return false ; default : return TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; } Register Paired = Hint . second ; if ( ! Paired ) return false ; Register PairedPhys ; if ( Paired . isPhysical ( ) ) { PairedPhys =


<s> HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false


<s> explicit <ISA_LIT>A57FPLoadBalancing ( ) : MachineFunctionPass (


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode ==


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'v' : if ( Subtarget . hasVector ( ) ) { if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; } } if ( Constraint . size ( ) > <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , &


<s> virtual const TargetRegisterInfo & getRegisterInfo (


<s> static DecodeStatus DecodeT2BROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler ::


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( TLI . getVarArgsFrameOffset ( ) , <STR_LIT> ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op

. getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegPair ( const <ISA_LIT>Operand & MOP , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_RegPair , Parser ) ; Op -> RegIdx . Index = MOP . RegIdx . Index ; Op -> RegIdx . RegInfo = MOP . RegIdx . RegInfo ; Op -> RegIdx . Kind = MOP . RegIdx . Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> SDLoc dl ( Op ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget -> is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , false , false , <NUM_LIT> ) ; return BuildFILD ( Op , SrcVT , Chain ,


<s> void aarch64_asm_output_external ( FILE * stream , tree decl ,


<s> assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = TLI . getPointerTy ( DL ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( DL ) ) ; Register ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; return


<s> DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * EE = dyn_cast < ExtractElementInst > ( & I ) ; if ( ! EE ) continue ; Value * Root = matchAddReduction ( * EE ) ; if ( ! Root ) continue


<s> PrologueBB = DT -> findNearestCommonDominator ( PrologueBB , AI -> getParent ( ) ) ; } assert ( PrologueBB ) ; IRBuilder < > IRB ( & PrologueBB -> front ( ) ) ; Function * IRG_SP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = IRB . CreateCall ( IRG_SP , { Constant :: getNullValue ( IRB . getInt64Ty ( ) ) } ) ; Base -> setName ( <STR_LIT> ) ; return Base


<s> static SDValue lowerShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) )


<s> return ( ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) || ( Op . isImm ( ) &&


<s> if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_RegMask ; else return CSR_<ISA_LIT>_AAPCS_RegMask


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems < <NUM_LIT> || ( NumElems == <NUM_LIT> && Subtarget . canExtendTo512DQ ( ) ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; if ( VT . getScalarType ( ) != <STR_LIT> ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue ByteOp = DAG . getBitcast ( ByteVT , Op0 ) ; SDValue PopCnt8 = DAG . getNode ( <STR_LIT> , DL , ByteVT , ByteOp ) ; return LowerHorizontalByteSum ( PopCnt8 , VT , Subtarget , DAG ) ; } if ( ! Subtarget . hasSSSE3 ( ) ) return


<s> bool ProfitableArch = Subtarget -> isCortexA57 ( ) ; return ProfitableArch && ! Subtarget -> requiresStrictAlign (


<s> else if ( mode == V4SFmode ) stvx = gen_altivec_stvx_v4sf ( src_exp , dest_exp ) ; else if ( mode == V2DImode ) stvx = gen_altivec_stvx_v2di ( src_exp , dest_exp ) ; else if ( mode == V2DFmode ) stvx = gen_altivec_stvx_v2df ( src_exp , dest_exp ) ; else if ( mode == V1TImode ) stvx


<s> MachineInstr * Def = MRI . getVRegDef ( VReg ) ; while ( Def ) { if ( Def -> getOpcode ( ) != TargetOpcode :: COPY ) break ; if ( TargetRegisterInfo :: isPhysicalRegister ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; Def = MRI . getVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } return Def ; } ; auto IsCMN = [ & ] ( MachineInstr * DefMI , const <STR_LIT> & CC ) { if ( ! DefMI || DefMI -> getOpcode ( ) != TargetOpcode :: G_SUB ) return false ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return false ; if ( DefMI -> getOpcode ( ) != TargetOpcode :: G_SUB ) return false ; auto ValAndVReg = getConstantVRegValWithLookThrough ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> ) return false ; return true ; } ; MachineInstr * LHSDef = FindDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * RHSDef = FindDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; bool DidFold = false ; if ( IsCMN ( LHSDef , CC ) ) { I . getOperand ( <NUM_LIT> ) . setReg ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DidFold =


<s> static void ix86_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_AVX512F && ! TARGET_PREFER_AVX256 ) { sizes -> safe_push ( <NUM_LIT> ) ; sizes -> safe_push (


<s> return ( poly64x1_t ) __builtin_neon_vreinterpretdiv2si ( ( int32x2_t )


<s> bool <ISA_LIT>SETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset

, const <ISA_LIT>FunctionInfo & FI ) const {


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectZExt ( const Instruction * I ) { EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! TLI . isTypeLegal ( DstVT ) ) return false ; Register ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT>


<s> ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; VRM = & getAnalysis <


<s> unsigned Emitter < CodeEmitter > :: get<ISA_LIT>RegNum ( unsigned RegNo ) const { return <ISA_LIT>RegisterInfo :: get<ISA_LIT>RegNum ( RegNo )


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx ,


<s> bool isImm0_4095Neg ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm (


uint64_type_node , new_exception_mask ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return MCOperand ( ) ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : return lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , <NUM_LIT> ) ; case MachineOperand :: MO_GlobalAddress : return lowerSymbolOperand ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) , MO


<s> return getBaseOpcodeFor ( & get ( Opcode )


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { llvm_unreachable ( <STR_LIT> )


<s> auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , Name , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned Opt = Mapper . fromString ( Tok . getString ( ) , Valid ) ; if ( ! Valid )


<s> for ( tail = attributes ; attrs ; attrs = TREE_CHAIN ( attrs ) ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) ) warning ( OPT_Wattributes , <STR_LIT> , TREE_PURPOSE ( attrs ) ) ; else { * tail = tree_cons ( TREE_PURPOSE ( attrs ) , NULL_TREE , NULL_TREE ) ; tail = & TREE_CHAIN ( * tail ) ; } } attrs = * attributes ; } } * attributes = attrs ; sh_deferred_function_attributes = NULL_TREE ; sh_deferred_function_attributes_tail = & sh_deferred_function_attributes


<s> vpminnms_f32 ( float32x2_t a ) { return __builtin_aarch64_reduc_smin_scal_v2sf ( a


<s> } break ; case VOID_FTYPE_UINT_UINT_UINT : case VOID_FTYPE_UINT64_UINT_UINT : case UCHAR_FTYPE_UINT_UINT_UINT : case UCHAR_FTYPE_UINT64_UINT_UINT : nargs = <NUM_LIT> ; klass = load ; memory = ARRAY_SIZE ( args ) ; last_arg_constant = true ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( nargs <= ARRAY_SIZE ( args ) ) ; if ( klass == store ) { arg = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op = expand_normal ( arg ) ; gcc_assert ( target == <NUM_LIT> ) ; if ( memory ) { op = ix86_zero_extend_to_Pmode ( op ) ; target = gen_rtx_MEM ( tmode , op ) ; unsigned int align = get_pointer_alignment ( arg ) ; if ( aligned_mem && align < GET_MODE_ALIGNMENT ( tmode ) ) align = GET_MODE_ALIGNMENT ( tmode ) ; if ( MEM_ALIGN ( target ) < align ) set_mem_align ( target , align ) ; } else target = force_reg ( tmode , op ) ; arg_adjust = <NUM_LIT> ; } else { arg_adjust = <NUM_LIT> ; if ( optimize || target == <NUM_LIT> || ! register_operand ( target , tmode ) || GET_MODE ( target ) != tmode ) target = gen_reg_rtx ( tmode ) ; } for ( i = <NUM_LIT> ; i < nargs ; i ++ ) { machine_mode mode = insn_p -> operand [ i + <NUM_LIT> ] . mode ; bool match ; arg = CALL_EXPR_ARG ( exp , i + arg_adjust ) ; op = expand_normal ( arg ) ; match = insn_p -> operand [ i + <NUM_LIT> ] . predicate ( op , mode ) ; if ( last_arg_constant && ( i + <NUM_LIT> ) == nargs ) { if ( ! match ) { if ( icode == CODE_FOR_lwp_lwpvalsi3 || icode == CODE_FOR_lwp_lwpinssi3 || icode == CODE_FOR_lwp_lwpvaldi3 || icode == CODE_FOR_lwp_lwpinsdi3 ) error ( <STR_LIT> ) ; else error ( <STR_LIT> ) ; return const0_rtx ; } } else { if ( i == memory ) { op = ix86_zero_extend_to_Pmode ( op ) ; op = gen_rtx_MEM ( mode , op ) ; unsigned int align = get_pointer_alignment ( arg ) ; if ( aligned_mem && align < GET_MODE_ALIGNMENT ( mode ) ) align = GET_MODE_ALIGNMENT ( mode ) ; if ( MEM_ALIGN ( op ) < align ) set_mem_align ( op , align ) ; } else { if ( VECTOR_MODE_P ( mode ) ) op = safe_vector_operand ( op , mode ) ; op = fixup_modeless_constant ( op , mode ) ; if ( GET_MODE ( op ) == mode || GET_MODE ( op ) == VOIDmode ) op = copy_to_mode_reg ( mode , op ) ; else { op = copy_to_reg ( op ) ; op = simplify_gen_subreg ( mode , op , GET_MODE ( op ) , <NUM_LIT> ) ; } } } args [ i ] . op = op ; args [ i ] . mode = mode ; } switch ( nargs ) { case <NUM_LIT>


<s> if ( ! HasLazyResolverStubs || TM . getRelocationModel ( ) == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration (


<s> unsigned LblOperand = Inst . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; return Addr +


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { --


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , SDLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; MVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getBitcast (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> ,


<s> case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT>


<s> BitVector AllocSet = TRI . getAllocatableSet ( MF ) ; for ( int R = AllocSet . find_first ( ) ; R != - <NUM_LIT> ; R = AllocSet . find_next ( R ) ) for ( MCRegAliasIterator AI ( R , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AllocSet . set ( * AI ) ; AllocSet . set ( <STR_LIT>


<s> assert ( isRegNumber ( ) && <STR_LIT> ) ; return ( unsigned ) Imm .


<s> rtx result ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , <NUM_LIT> ) ; if ( ! multiple_operation_profitable_p ( false , count , <NUM_LIT> ) ) { rtx seq ; start_sequence ( ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( mems [ i ] , gen_rtx_REG ( SImode , regs [ i ] ) ) ; if ( wback_offset != <NUM_LIT> ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode >


<s> if ( TARGET_PORTABLE_RUNTIME ) return <NUM_LIT> ; if ( ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) && ! optimize_size ) return <NUM_LIT> ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) return <NUM_LIT> ; if ( ! flag_pic ) return <NUM_LIT> ; if ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) return <NUM_LIT> ; if ( ! optimize_size ) return <NUM_LIT> ; return


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; unsigned VL = N -> getValueType (

<NUM_LIT> ) . getVectorNumElements ( ) ;


<s> else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg


<s> assert ( VT . isFloatingPoint ( ) && <STR_LIT>


<s> return ( __m256h ) __builtin_ia32_getexpph256_mask ( ( __v16hf ) __A , ( __v16hf ) _mm256_setzero_ph ( ) , ( __mmask16 ) -


<s> APInt KnownZero2 , KnownOne2 ; KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; assert ( ( KnownZero & KnownOne ) == <NUM_LIT> &&


<s> <ISA_LIT>FunctionInfo * AFI = const_cast < MachineFunction * > ( & MF ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getArgRegsSaveSize ( ) ) return true ; bool IsV4PopReturn = false ; for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) -> getCalleeSavedInfo ( ) ) if ( CSI . getReg ( ) == <STR_LIT> ) IsV4PopReturn = true ; return IsV4PopReturn && STI . hasV4TOps ( ) && ! STI


<s> for ( const Instruction & I : instructions ( Callee ) ) { if ( const auto * CB = dyn_cast < CallBase > ( & I ) ) { SmallVector < Type * , <NUM_LIT> > Types ; for ( Value * Arg : CB -> args ( ) ) Types . push_back ( Arg -> getType ( ) ) ; if ( ! CB -> getType ( ) -> isVoidTy ( ) ) Types . push_back ( CB -> getType ( ) ) ; auto IsSimpleTy = [ ] ( Type * Ty ) { return ! Ty -> isVectorTy ( ) && ! Ty -> isAggregateType ( ) ; } ; if ( all_of ( Types , IsSimpleTy ) ) continue ; if ( Function * NestedCallee = CB -> getCalledFunction ( ) ) { if ( NestedCallee -> isIntrinsic ( ) ) continue ; if ( ! areTypesABICompatible ( Caller , NestedCallee , Types ) )


<s> return performAddSubLongCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : { SDValue RV = performSelectCombine ( N , DCI ) ; if ( ! RV . getNode ( ) ) RV = performAcrossLaneMinMaxReductionCombine ( N , DAG , Subtarget ) ; return RV ; } case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : return performAcrossLaneAddReductionCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( int32x4_t ) __builtin_aarch64_saddw2v8hi ( __a ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_32AsmBackend ( T ) ; if ( TheTriple . isOSWindows ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false


<s> unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = <NUM_LIT> * ( Subtarget . isLittle ( ) ? N : ( <NUM_LIT> - N ) ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT> : & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC ) ; TII . storeRegToStack ( MBB , I , SrcReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI , Offset ) ; return true ; } return false