<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success ; } if ( RegNo == <NUM_LIT> ) Check ( S , MCDisassembler :: SoftFail ) ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ) ; return S


<s> int getFPStackOffset ( ) const { return


<s> unsigned <ISA_LIT>BasicBlockUtils :: getOffsetOf ( MachineInstr * MI ) const { const MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes ( *


<s> return ( uint16x8_t ) __builtin_neon_vqshlu_nv8hi (


<s> if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( )


<s> unsigned getThumbCBTargetOpValue ( const MachineInstr & MI , unsigned Op


<s> return __builtin_aarch64_sqrshlv8qi ( __a ,


<s> const MCSymbol * Sym = Ctx . GetOrCreateSymbol ( SymName ) ; const MCSymbolRefExpr * MCSym ; MCInsts . resize ( <NUM_LIT> ) ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , Ctx ) ; MCInsts [ <NUM_LIT> ] . setOpcode ( <STR_LIT> ) ; MCInsts [ <NUM_LIT> ] . addOperand ( RegOpnd ) ; MCInsts [ <NUM_LIT> ] . addOperand ( MCOperand :: CreateExpr ( MCSym ) ) ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , Ctx ) ; MCInsts [ <NUM_LIT> ] .


<s> VariantKind getKind ( ) const { return Kind


<s> static inline <STR_LIT> getArithExtendType


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask


<s> unsigned long long d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d )


<s> virtual bool assignArg ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , const CallLowering :: ArgInfo & Info , CCState & State ) override { if ( Info . IsFixed ) return AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ; return AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Info .


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return *


) _mm_maskz_expandloadu_epi16 ( __mmask8 __A , const void * __B ) {


<s> return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) ) && ! MFI -> hasVarSizedObjects


<s> LLVMContext * Context = DAG . getContext ( ) ; const uint32_t CV0 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Constant * C0 = ConstantDataVector :: get ( * Context , CV0 ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget -> hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue S2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue Shuffle = getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , S2F , <NUM_LIT> , DAG ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT>


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; return


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> int NumInnerElts = NumElts / <NUM_LIT> ; int NumEltsPerLane = NumElts / NumLanes ; int NumInnerEltsPerLane = NumInnerElts / NumLanes ; DemandedLHS = APInt :: getZero ( NumInnerElts ) ; DemandedRHS = APInt :: getZero ( NumInnerElts ) ; for ( int Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( int Elt = <NUM_LIT> ; Elt != NumInnerEltsPerLane


<s> gcc_assert ( REG_P ( reg ) ) ; regno = REGNO ( reg ) ; nregs = REG_NREGS ( reg ) / <NUM_LIT> ; gcc_assert ( VFP_REGNO_OK_FOR_DOUBLE ( regno ) || NEON_REGNO_OK_FOR_QUAD ( regno ) ) ; gcc_assert ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) || VALID_NEON_STRUCT_MODE ( mode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case POST_INC : if ( nregs > <NUM_LIT> ) { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; } else { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; } ops [ <NUM_LIT> ] = reg ; break ; case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> ) templ = <STR_LIT> ; else templ = <STR_LIT>


<s> assert ( ( OffsetOp . isImm ( ) || OffsetOp . isExpr ( ) ) && <STR_LIT> ) ; if ( OffsetOp . isImm ( ) ) { assert ( isInt < SizeInBits > ( OffsetOp . getImm ( ) ) && <STR_LIT> ) ; OS << OffsetOp .


<s> FusionKind getKind ( ) const { return Kd


<s> if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRm ( MI , OpIdx ) ; if ( IsThumb ) Binary = convertNEONDataProcToThumb ( Binary ) ; emitWordLE ( Binary


<s> return std :: make_pair ( true , Result ) ; } case <STR_LIT> : { ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( Node ) ; if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && CN -> isExactlyValue ( + <NUM_LIT> ) ) { if ( Subtarget . has<ISA_LIT>64 ( ) ) { SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; } else { SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Zero ) ; } return std :: make_pair ( true , Result ) ; } break ; } case <STR_LIT> : { const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; unsigned Size = CN -> getValueSizeInBits ( <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) break ; <ISA_LIT>AnalyzeImmediate AnalyzeImm ; int64_t Imm = CN -> getSExtValue ( ) ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , false ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; DebugLoc DL = CN -> getDebugLoc ( ) ; SDNode * RegOpnd ; SDValue ImmOpnd = CurDAG -> getTargetConstant ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) , <STR_LIT> ) ; if ( Inst -> Opc == <STR_LIT> ) RegOpnd = CurDAG -> getMachineNode ( Inst -> Opc , DL , <STR_LIT> , ImmOpnd ) ; else RegOpnd = CurDAG -> getMachineNode ( Inst -> Opc , DL , <STR_LIT> , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , ImmOpnd ) ; for ( ++ Inst ; Inst != Seq . end


<s> return isImm ( <NUM_LIT> , ( <NUM_LIT> <<


<s> } unsigned Opc = OrigMI -> getOpcode ( ) ; ( void ) Opc ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; if ( MO . isDef ( ) && TRI -> isSuperRegisterEq ( OrigDestReg , MO . getReg ( ) ) ) IsDefined = true ; if ( MO . isUse ( ) && ! TRI -> isSubRegisterEq ( OrigDestReg , MO . getReg ( ) ) && TRI -> regsOverlap ( SuperDestReg , MO . getReg ( ) ) ) return false ; } if ( ! IsDefined ) return false ; return


<s> static void EmitSHL ( MCStreamer & OutStreamer , MCOperand & RS1 , MCOperand & Imm

, MCOperand & RD , const MCSubtargetInfo & STI ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty ->


<s> int DeadNZCVIdx = CmpInstr -> findRegisterDefOperandIdx ( <STR_LIT> , true ) ; if ( DeadNZCVIdx != - <NUM_LIT> ) { if ( CmpInstr -> definesRegister ( <STR_LIT> ) || CmpInstr -> definesRegister ( <STR_LIT> ) ) { CmpInstr -> eraseFromParent ( ) ; return true ; } unsigned Opc = CmpInstr -> getOpcode ( ) ; unsigned NewOpc = convertFlagSettingOpcode ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr -> setDesc ( MCID ) ; CmpInstr -> RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr -> getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( CmpInstr , SrcReg , SrcReg2 , MRI , & getRegisterInfo ( ) , this ) ; assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( CmpValue != <NUM_LIT> ||


<s> return __builtin_mve_vdupq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a ,


<s> static bool ia64_vms_valid_pointer_mode ( machine_mode mode


<s> SwitchToEHSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC , SectionKind :: getDataRel


<s> void nds32_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype ATTRIBUTE_UNUSED , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED


<s> MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction (


<s> void DecodeEXTRQIMask ( unsigned NumElts , unsigned EltSize , int Len , int Idx , SmallVectorImpl < int > & ShuffleMask ) { unsigned HalfElts = NumElts / <NUM_LIT> ; Len &= <NUM_LIT> ; Idx &= <NUM_LIT> ; if ( <NUM_LIT> != ( Len % EltSize ) || <NUM_LIT> != ( Idx % EltSize ) ) return ; if ( Len == <NUM_LIT> ) Len = <NUM_LIT> ; if ( ( Len + Idx ) > <NUM_LIT> ) { ShuffleMask . append ( NumElts , SM_SentinelUndef ) ; return ; } Len /= EltSize ; Idx /= EltSize ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + Idx ) ; for ( int i = Len ; i != ( int ) HalfElts ; ++ i ) ShuffleMask . push_back ( SM_SentinelZero ) ; for ( int i = HalfElts ; i != ( int ) NumElts ; ++ i

) ShuffleMask . push_back ( SM_SentinelUndef ) ;


<s> void setVarArgsFrameIndex ( int Index


<s> return ( lookup_attribute ( <STR_LIT> , attrs ) == <NUM_LIT> && lookup_attribute ( <STR_LIT> , attrs


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> break ; case <STR_LIT> : ShiftAmt = <NUM_LIT> ; break ; } unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) . addImm ( ShiftAmt ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( ShiftAmt ) ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , SImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; for ( i = <NUM_LIT> ; i < size ; i ++ ) parts [ i ] = adjust_address ( operand , SImode , <NUM_LIT> * i ) ; } else if ( CONST_DOUBLE_P ( operand ) ) { const REAL_VALUE_TYPE * r ; long l [ <NUM_LIT> ] ; r = CONST_DOUBLE_REAL_VALUE ( operand ) ; switch ( mode ) { case E_TFmode : real_to_target ( l , r , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; break ; case E_XFmode : real_to_target ( l , r , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; break ; case E_DFmode : REAL_VALUE_TO_TARGET_DOUBLE ( * r , l ) ; break ; default : gcc_unreachable ( ) ; } parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; } else gcc_unreachable ( ) ; } } else { if ( mode == TImode ) split_double_mode ( mode , & operand , <NUM_LIT> , & parts [ <NUM_LIT> ] , & parts [ <NUM_LIT> ] ) ; if ( mode == XFmode || mode == TFmode ) { machine_mode upper_mode = mode == XFmode ? SImode : DImode ; if ( REG_P ( operand ) ) { gcc_assert ( reload_completed ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operand ) + <NUM_LIT> ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( upper_mode , REGNO ( operand ) + <NUM_LIT> ) ; } else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , DImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; parts [ <NUM_LIT> ] = adjust_address ( operand , upper_mode , <NUM_LIT> ) ; } else if ( CONST_DOUBLE_P ( operand ) ) { long l [ <NUM_LIT> ] ; real_to_target ( l , CONST_DOUBLE_REAL_VALUE ( operand ) , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) | (

( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) << <NUM_LIT> ) , DImode ) ;


<s> if ( ! MI . mayLoad ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; bool AllDefsAreGPR = llvm :: all_of ( MI . defs ( ) , [ & ] ( MachineOperand & Op ) { return Op . isReg ( ) && ( <STR_LIT> . contains ( Op . getReg ( ) ) || <STR_LIT> . contains ( Op . getReg ( ) ) ) ; } ) ; bool HardenLoadedData = AllDefsAreGPR ; bool HardenAddressLoadedFrom = ! HardenLoadedData ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsAlreadyMasked . reset ( * AI ) ; if ( HardenLoadedData ) for ( auto Def : MI . defs ( ) ) { if ( Def . isDead ( ) ) continue ; Modified |= makeGPRSpeculationSafe ( MBB , NextMBBI , MI , Def . getReg ( ) ) ; } if ( HardenAddressLoadedFrom ) for ( auto Use : MI . uses ( ) ) { if ( ! Use . isReg ( ) ) continue ; unsigned Reg = Use . getReg ( ) ; if ( ! ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains (


<s> addr = gen_lowpart ( SImode , addr ) ; rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , addr , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_andsi3 ( shift , tmp , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX ,


<s> return supportedVectorShiftWithImm ( VT , Subtarget ,


<s> bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= countTrailingZeros ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , DL , <STR_LIT> )

, DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ;


<s> for ( unsigned i = NumElems / <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt (


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint64_t OptimalCount = ( Count < <NUM_LIT> ) ? Count : <NUM_LIT> ; const uint64_t Prefixes = OptimalCount <= <NUM_LIT> ? <NUM_LIT> : OptimalCount - <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = <NUM_LIT> , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i


<s> static void emit_vrsave_prologue ( rs6000_stack_t * info , int save_regno , HOST_WIDE_INT frame_off , rtx frame_reg_rtx ) { rtx reg = gen_rtx_REG ( SImode , save_regno ) ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; if ( TARGET_MACHO ) emit_insn ( gen_get_vrsave_internal ( reg ) ) ; else emit_insn ( gen_rtx_SET ( reg , vrsave ) ) ; int offset = info -> vrsave_save_offset + frame_off ; emit_insn ( gen_frame_store ( reg , frame_reg_rtx , offset ) ) ; emit_insn ( gen_iorsi3 ( reg , reg , GEN_INT ( info


<s> if ( pic_address_needs_scratch ( x ) ) return false ; if ( sparc_tls_referenced_p ( x ) ) return false ; return true


<s> gtop = build ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > <NUM_LIT> ) t = build ( PLUS_EXPR , TREE_TYPE ( ovfl ) , t , build_int_cst ( NULL_TREE , cum -> stack_words * UNITS_PER_WORD ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gtop ) , virtual_incoming_args_rtx ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( gtop ) , gtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( ftop ) , virtual_incoming_args_rtx ) ; fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - <NUM_LIT> ; fpr_offset &= ~ ( UNITS_PER_FPVALUE - <NUM_LIT> ) ; if ( fpr_offset ) t = build ( PLUS_EXPR , TREE_TYPE ( ftop ) , t , build_int_cst ( NULL_TREE , - fpr_offset ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE (


<s> if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( DstVT ) ) { SDLoc dl ( Op ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op . getOperand ( <NUM_LIT> ) , dl ) ; EVT CastVT = <STR_LIT> ( DstVT . getVectorElementType ( ) , DstVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Lo = DAG . getBitcast ( CastVT , Lo ) ; Hi = DAG . getBitcast ( CastVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags .

getByValAlign ( ) , false , false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> switch ( Mode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> bool isTargetWin32 ( ) const { return ! Is64Bit && ( isTargetMingw ( ) || isTargetWindows


<s> bool OutgoingValueHandler :: handle ( ArrayRef < CCValAssign > ArgLocs , ArrayRef < CallLowering :: ArgInfo > Args ) { for ( unsigned i = <NUM_LIT> ; i < Args


<s> if ( ! isUIntN ( <NUM_LIT> , ParamsSize ) ) return Parser . TokError ( <STR_LIT> ) ; if ( parseEOL ( ) ) return true ; MCSymbol * ProcSym = getContext ( ) . getOrCreateSymbol (


<s> if ( TARGET_CHECK_ZERO_DIV ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( s , operands )


<s> void emitInst ( uint32_t Inst ) { char Buffer [ <NUM_LIT> ] ; for ( char & C : Buffer


<s> case ELF :: R_CPU0_HI16 : case ELF :: R_CPU0_LO16 : case ELF :: R_CPU0_32 : return true ; case ELF ::


<s> FINI_SECTION_FUNCTION void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP


<s> while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier


<s> static DecodeStatus DecodeSimm19Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > (


<s> bool <ISA_LIT>TargetLowering :: canCombineStoreAndExtract ( Type * VectorTy , Value * Idx , unsigned & Cost ) const { if ( ! Subtarget -> hasNEON ( ) ) return false ; if ( VectorTy -> isFPOrFPVectorTy ( ) ) return false ; if ( ! isa < ConstantInt > ( Idx ) ) return false ; assert ( VectorTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned BitWidth = cast < VectorType > ( VectorTy ) -> getBitWidth ( ) ; if ( BitWidth == <NUM_LIT>


<s> if ( from == current_frame_info . reg_fp || from == current_frame_info . reg_save_b0 || from == current_frame_info . reg_save_pr || from == current_frame_info . reg_save_ar_pfs || from == current_frame_info . reg_save_ar_unat || from == current_frame_info . reg_save_ar_lc ) return <NUM_LIT> ; if ( OUT_REGNO_P ( to ) && to >= OUT_REG ( current_frame_info


<s> static section * loongarch_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( loongarch_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , <STR_LIT> , <NUM_LIT> ) ; return default_elf_select_rtx_section ( mode ,


<s> void <ISA_LIT>MCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand


<s> switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT>


<s> if ( isa_and_nonnull < StoreInst > ( I ) ) { Value * Ptr = I -> getOperand ( <NUM_LIT> ) ; if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) { return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ; } } return TTI :: TCC_Basic ; } if ( auto * VTy = dyn_cast < FixedVectorType > ( Src ) ) { unsigned NumElem = VTy -> getNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> int length = <NUM_LIT> ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - <NUM_LIT> ; gcc_assert ( CALL_P ( insn ) ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? <NUM_LIT> : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - <NUM_LIT> ; } gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) length += <NUM_LIT> ; else if ( TARGET_64BIT && ! local_call ) length += sibcall ? <NUM_LIT> : <NUM_LIT> ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += <NUM_LIT> ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS &&


<s> if ( ! N -> isNonTemporal ( ) ) return false ; unsigned StoreSize = N -> getMemoryVT ( ) . getStoreSize ( ) ; if ( N -> getAlignment ( ) < StoreSize ) return false ; switch ( StoreSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> void aarch64_emit_approx_rsqrt ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( src ) ; gcc_assert ( mode == SFmode || mode == V2SFmode || mode == V4SFmode || mode == DFmode || mode == V2DFmode ) ; rtx xsrc = gen_reg_rtx ( mode ) ; emit_move_insn ( xsrc , src ) ; rtx x0 = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( x0 , xsrc ) ) ; bool double_mode = ( mode == DFmode || mode == V2DFmode ) ; int iterations = double_mode ? <NUM_LIT> : <NUM_LIT> ; if ( flag_mrecip_low_precision_sqrt ) iterations -- ; for ( int i = <NUM_LIT> ; i < iterations ; ++ i ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx x2 = gen_reg_rtx ( mode ) ; rtx x3 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , x0 , x0 ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x3 , xsrc , x2 ) ) ; emit_set_insn ( x1 , gen_rtx_MULT ( mode , x0 , x3 ) ) ; x0 = x1 ; } emit_move_insn ( dst , x0


<s> static bool isUndefOrEqual ( ArrayRef < int > Mask , int CmpVal ) { return llvm :: all_of ( Mask ,


<s> MachineOperand & LoadBase = getBaseOperand ( LoadInst ) ; MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; if ( LoadBase . isReg ( ) ) { MachineInstr * LastLoad = LoadInst -> getPrevNode ( ) ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) LastLoad = LoadInst -> getPrevNode (


<s> if ( ! Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( DAG . getDataLayout (


<s> EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case DSig : EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case DDSig : EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case DFSig : EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; EmitInstrRegReg ( STI , MovOpc , <STR_LIT> , <STR_LIT> ) ; break ; case


<s> va_start ( ap , format ) ; ( void ) vsnprintf ( buffer , sizeof ( buffer ) ,


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . else_blk ( ) ; } return gen_rtx_REG ( mode ,


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder ,

ArgInfos , RetHandler ) ) return false ;


<s> const MCProcResourceDesc & PRD = * SchedModel -> getProcResource ( PI -> ProcResourceIdx ) ; std :: string FU ( PRD . Name ) ; FU = FU . substr ( FU . find ( <STR_LIT> ) + <NUM_LIT> ) ; FU . resize ( FU . find ( <STR_LIT> ) ) ; OS << <STR_LIT> << FU ; if ( PI -> Cycles > <NUM_LIT> ) OS << <STR_LIT> << PI -> Cycles << <STR_LIT> ; } if ( SC -> NumMicroOps > <NUM_LIT> ) OS << <STR_LIT> << SC -> NumMicroOps << <STR_LIT> ; if ( SC -> BeginGroup && SC -> EndGroup ) OS << <STR_LIT> ; else if ( SC ->


<s> static SDValue constructDup ( SDValue V , int Lane , SDLoc dl , EVT VT , unsigned Opcode , SelectionDAG & DAG ) { auto getScaledOffsetDup = [ ] ( SDValue BitCast , int & LaneC , MVT & CastVT ) { if ( BitCast . getOpcode ( ) != <STR_LIT> || BitCast . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Extract = BitCast . getOperand ( <NUM_LIT> ) ; unsigned ExtIdx = Extract . getConstantOperandVal ( <NUM_LIT> ) ; unsigned SrcEltBitWidth = Extract . getScalarValueSizeInBits ( ) ; unsigned ExtIdxInBits = ExtIdx * SrcEltBitWidth ; unsigned CastedEltBitWidth = BitCast . getScalarValueSizeInBits ( ) ; if ( ExtIdxInBits % CastedEltBitWidth != <NUM_LIT> ) return false ; LaneC += ExtIdxInBits / CastedEltBitWidth ; unsigned SrcVecNumElts = Extract . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) /


<s> for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return MachineOutlinerInstrType :: Legal ; if ( MI . isCall ( ) ) { const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( M && <STR_LIT> ) ; Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isSymbol ( ) ) { Callee = M -> getFunction ( MOP . getSymbolName ( ) ) ; break ; } else if ( MOP . isGlobal ( ) ) { Callee = M -> getFunction ( MOP . getGlobal ( ) -> getGlobalIdentifier ( ) ) ; break ; } } if ( ! Callee ) return MachineOutlinerInstrType :: Illegal ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return MachineOutlinerInstrType :: Illegal ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo (


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } return false


<s> <ISA_LIT>SSELevel = NoMMXSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasADX = false


<s> if ( FTy -> isVarArg ( ) ) return false ; const Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( ! Subtarget -> hasV5TOps ( ) ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( CS . arg_size ( ) ) ; ArgRegs . reserve ( CS . arg_size ( ) ) ; ArgVTs . reserve ( CS . arg_size ( ) ) ; ArgFlags . reserve ( CS . arg_size ( ) ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; const Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned ,


<s> case IES_LPAREN : case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : State = IES_MINUS ; if ( ! ( CurrState == IES_PLUS || CurrState == IES_MINUS || CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||

CurrState == IES_LPAREN || CurrState == IES_LBRAC ) ) IC . pushOperator ( IC_MINUS ) ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return


<s> assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getConstant ( NumBits / <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( Opc , dl , ShVT


<s> static inline AddrOpc getAM3Op ( unsigned


<s> OutStreamer -> EmitInstruction ( Inst , getSubtargetInfo ( ) , EnablePrintSchedInfo ) ; SMShadowTracker . count ( Inst , getSubtargetInfo ( ) , CodeEmitter .


<s> void printCallOperand ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { GlobalValue * GV = MO . getGlobal ( ) ; if ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry


<s> while ( Carry . getOpcode ( ) == <STR_LIT> ) Carry = Carry . getOperand ( <NUM_LIT> ) ; return Carry . getOpcode (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned getT2SORegOpValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> return ( ( qword ) ( vec_ld ( si_to_uint ( a ) & ~ <NUM_LIT> , ( vector unsigned char * ) ( imm )


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( LHS , RHS ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>CC , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>CC = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>CC , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl ,


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { SDValue V = PerformSHLCombine ( N , DAG ) ; if ( V . getNode ( ) ) return V ; } return SDValue (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy (


<s> bool isFloatRoundMode ( ) const { if ( ! isConstantImm ( )


<s> return ( __mmask32 ) __builtin_ia32_vpshufbitqmb256_mask ( ( __v32qi ) __A , ( __v32qi ) __B , (


<s> inline bool isNEONi16splat ( unsigned Value ) { if ( Value > <NUM_LIT>


<s> addr |= Rn << <NUM_LIT> ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler


<s> static bool translateRM ( MCInst & mcInst , const OperandSpecifier & operand , InternalInstruction & insn , const MCDisassembler * Dis ) { switch ( operand . type ) { default : debug ( <STR_LIT> ) ; return true ; case TYPE_R8 : case


<s> dst = operands [ <NUM_LIT> ] ; src = operands [ <NUM_LIT> ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( use_sse ) { rtx mask , use , clob ; mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode || mode == TFmode ) par = gen_rtvec ( <NUM_LIT> , set


<s> int typemap_cmp ( const void * key , const void *


<s> if ( sh_pass_in_reg_p ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & <NUM_LIT> ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ <NUM_LIT> ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + <NUM_LIT> ) ^ <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( <NUM_LIT> , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG


<s> MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( DarwinRefKind != MCSymbolRefExpr :: VK_PAGE && DarwinRefKind != MCSymbolRefExpr :: VK_GOTPAGE && DarwinRefKind != MCSymbolRefExpr :: VK_TLVPPAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_ABS_PAGE_NC && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE_LO15 && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) { Error ( S , <STR_LIT> ) ; return


<s> FnStartLoc = L ; getParser ( ) . getStreamer ( ) . EmitFnStart ( ) ; return false


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <ISA_LIT>AddrNumOperands ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; Load = DAG . getTargetNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , TM ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = <NUM_LIT> ; if ( TID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = TID . OpInfo [ <NUM_LIT> ] . getRegClass ( & RI ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) TID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; std :: copy ( AfterOps . begin ( ) , AfterOps . end ( ) , std :: back_inserter (


<s> x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; x1 = gen_reg_rtx ( mode ) ; b = force_reg ( mode , b ) ; if ( mode == V16SFmode || mode == V8DFmode ) emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP14 ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MULT ( mode , x0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_PLUS ( mode , x0 , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x1 , gen_rtx_MINUS ( mode , e1 , e0 ) )


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! Generated . parseCommandLineOption ( ) ) report_fatal_error


<s> return ( __m256i ) __builtin_ia32_pmovusdw512_mask ( ( __v16si ) __A , ( __v16hi ) _mm256_undefined_si256 ( )


<s> SDValue Hi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlagHi ) ; SDValue Lo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; if ( IsPIC ) Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , getGlobalReg ( DAG , <STR_LIT> ) ) ; return


<s> if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( )


<s> for ( const MachineInstr & MI : MBB ) Size += TII


<s> Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } return Reserved


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case


<s> static SDValue lowerV4F32VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( Subtarget . hasSSE41 ( ) ) { if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleAsInsertPS ( DL , V1 , V2 , Mask , Zeroable , DAG )


<s> return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , false , false , RLI . IsInvariant ,

RLI . Alignment , RLI . AAInfo , RLI . Ranges ) ;


<s> for ( unsigned i = <NUM_LIT> , ie = array_lengthof ( PseudoRegs ) ; i != ie ; ++ i ) { unsigned Reg = PseudoRegs [ i ] ; Mask [ Reg / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( Reg %


<s> assert ( res && <STR_LIT> ) ; ( void ) res ; return encoding


<s> zero = v4sf_const0 ; } else { dest_vecmode = V2DFmode ; zero = gen_rtx_SUBREG ( V2DFmode , v4sf_const0 , <NUM_LIT> ) ; } src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx ( dest_vecmode ) ; set = gen_rtx_SET ( vec , src ) ; set_insn = emit_insn_before ( set , insn ) ; df_insn_rescan ( set_insn ) ; if ( cfun -> can_throw_non_call_exceptions ) { rtx note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) { control_flow_insns . safe_push ( set_insn ) ; add_reg_note ( set_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } } src = gen_rtx_SUBREG ( dest_mode , vec , <NUM_LIT> ) ; set = gen_rtx_SET ( dest ,


<s> else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_HARD_FLOAT_ABI && ! is_stdarg ) { if ( CSKY_VREG_MODE_P ( mode ) && ! TARGET_SINGLE_FPU ) return ( ( CSKY_NUM_WORDS ( size ) + <NUM_LIT> ) / <NUM_LIT> ) ; } return CSKY_NUM_WORDS ( size


<s> int regno ; mode = GET_MODE ( reg ) ; regno = REGNO ( reg ) ; if ( regno >= NDS32_FIRST_FPR_REGNUM && regno <= NDS32_LAST_FPR_REGNUM ) { if ( mode == DFmode || mode == SCmode ) { dwarf_high = gen_rtx_REG ( word_mode , regno ) ; dwarf_low = gen_rtx_REG ( word_mode , regno + <NUM_LIT> ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , dwarf_low ,


<s> BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2 ) { BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addReg (

<NUM_LIT> ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> c = ( __vector signed char ) vec_cmpgt ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_char [ <NUM_LIT> ] = ( m1 . as_char [ <NUM_LIT> ] > m2 . as_char [ <NUM_LIT> ] ) ? - <NUM_LIT> : <NUM_LIT> ; res . as_char [ <NUM_LIT> ] = ( m1 . as_char [ <NUM_LIT> ] > m2 . as_char [ <NUM_LIT> ] ) ? - <NUM_LIT> : <NUM_LIT> ; res . as_char [ <NUM_LIT> ] = ( m1 . as_char [ <NUM_LIT> ] >


<s> return ( vector signed int ) __builtin_altivec_vmsumshs ( ( vector signed short ) a1 , ( vector signed short ) a2 , ( vector signed


<s> static tree rs6000_builtin_reciprocal ( unsigned int fn , bool md_fn , bool sqrt ATTRIBUTE_UNUSED ) { if ( optimize_insn_for_size_p ( ) ) return NULL_TREE ; if ( md_fn ) switch ( fn ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) )


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) ==

Triple :: GNUEABIHF ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG


<s> ScalarTargetTransformInfo :: PopcntHwSupport <ISA_LIT>ScalarTargetTransformImpl :: getPopcntHwSupport ( unsigned TyWidth ) const { assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget


<s> bool isImm0_508s4 ( ) const { return isImmediateS4 < <NUM_LIT> ,


<s> } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff +=


<s> bool Changed = false ; assert ( List . size ( ) > <NUM_LIT> ) ; MachineBasicBlock * MBB = List [ <NUM_LIT> ] -> getParent ( ) ; for ( auto I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr & MI = * I ++ ; unsigned Opcode = MI . getOpcode ( ) ; if ( ! MI . mayLoadOrStore ( ) ) continue ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags , Opcode ) ; if ( MemOpNo < <NUM_LIT> ) continue ; MemOpNo += <STR_LIT> ( Desc ) ; MachineInstr * DefMI ; int64_t


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return


<s> assert ( Align > <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; const TargetRegisterClass * RC = ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else


<s> llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator Start = std :: begin ( ReduceTable ) ; llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator , llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator

> Range = std :: equal_range ( Start , End , Opcode ) ;


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > (


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass (


<s> void <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . hasFP64 ( ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) addUnpredicatedMveVpredROp ( MIB , DestReg ) ; else MIB . add ( predOps ( <STR_LIT> ) ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . hasNEON ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ,


<s> MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm ( ) ) ; assert ( HighOpcode && LowOpcode && <STR_LIT> ) ; EarlierMI -> setDesc ( get ( HighOpcode ) ) ; MI -> setDesc ( get ( LowOpcode


<s> bool is32BitMode ( ) const { return STI -> getFeatureBits (


<s> SDLoc dl ( St ) ; SDValue StoredVal = St -> getValue ( ) ; if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { assert ( StoredVal . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . getTypeAction ( * DAG . getContext ( ) , StoreVT ) != TargetLowering :: TypeWidenVector ) return SDValue ( ) ; MVT WideVT = <STR_LIT> ( StoreVT . getVectorElementType ( ) , StoreVT . getVectorNumElements ( ) * <NUM_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> (


<s> return __builtin_aarch64_sminv4hi ( __a ,


<s> pValue |= ( pImm & <NUM_LIT> ) << <NUM_LIT> ; pValue |= ( pImm & <NUM_LIT> ) << <NUM_LIT> ; pValue |= ( pImm & <NUM_LIT>


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , true ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo (


<s> valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , true , true ) ; if ( valret ) return false ; } if ( rs6000_discover_homogeneous_aggregate ( TYPE_MODE ( type ) , type , NULL , NULL ) ) return false ; if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors


<s> void getAnalysisUsage ( AnalysisUsage


<s> assert ( MCE && <STR_LIT> ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( ! isSPVFP ) Binary |= RegM ; else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) ; Binary |= ( RegM & <NUM_LIT>


<s> gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno


<s> HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; if ( MI -> mayStore ( ) ) { unsigned Reg128UndefImpl = ( Reg128Undef | RegState :: Implicit ) ; MachineInstrBuilder ( MF , EarlierMI ) . addReg ( Reg128 , Reg128UndefImpl ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg128 , ( Reg128UndefImpl | Reg128Killed ) ) ; } MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) .


<s> if ( sh_pass_in_reg_p ( * cum , arg . mode , arg . type ) && ! TARGET_FPU_DOUBLE && ( sh_round_reg ( * cum , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) > NPARM_REGS ( arg . mode ) ) ) words = NPARM_REGS ( arg . mode ) - sh_round_reg ( * cum , arg . mode ) ; return words * UNITS_PER_WORD


<s> MCStreamer :: EmitWinEHHandlerData ( ) ; MCWin64EHUnwindEmitter :: EmitUnwindInfo ( * this , getCurrentWinFrameInfo ( )


<s> if ( Pattern == MachineCombinerPattern :: REASSOC_XMM_AMM_BMM ) { NewVRD = MRI . createVirtualRegister ( RC ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVRD , <NUM_LIT> ) ) ; } auto AdjustOperandOrder = [ & ] ( MachineInstr * MI , Register RegAdd , bool KillAdd , Register RegMul1 , bool KillRegMul1 , Register RegMul2 , bool KillRegMul2 ) { MI -> getOperand ( AddOpIdx ) . setReg ( RegAdd ) ; MI -> getOperand ( AddOpIdx ) . setIsKill ( KillAdd ) ; MI -> getOperand ( FirstMulOpIdx ) . setReg ( RegMul1 ) ; MI -> getOperand ( FirstMulOpIdx ) . setIsKill ( KillRegMul1 ) ; MI -> getOperand ( FirstMulOpIdx + <NUM_LIT> ) . setReg ( RegMul2 ) ; MI -> getOperand ( FirstMulOpIdx + <NUM_LIT> ) . setIsKill ( KillRegMul2 ) ; } ; if ( Pattern == MachineCombinerPattern :: REASSOC_XY_AMM_BMM ) { MachineInstrBuilder MINewB = BuildMI ( * MF , Prev -> getDebugLoc ( ) , get ( FmaOp ) , NewVRB ) . addReg ( RegX , getKillRegState ( KillX ) ) . addReg ( RegM21 , getKillRegState ( KillM21 ) ) . addReg ( RegM22 , getKillRegState ( KillM22 ) ) ; MachineInstrBuilder MINewA = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FmaOp ) , NewVRA ) . addReg ( RegY , getKillRegState ( KillY ) ) . addReg ( RegM31 , getKillRegState ( KillM31 ) ) . addReg ( RegM32 , getKillRegState ( KillM32 ) ) ; if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewA , RegY , KillY , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRA , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ; InsInstrs . push_back ( MINewB


<s> if ( AttributeSection ) { Streamer . SwitchSection ( AttributeSection ) ; } else { AttributeSection = Streamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> static std :: string GetAEABIUnwindPersonalityName ( unsigned Index ) { assert ( Index < <STR_LIT>

:: NUM_PERSONALITY_INDEX && <STR_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSelect ( MachineInstr & MI , MachineBasicBlock * ThisMBB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; <STR_LIT> CC = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineInstr * LastCMOV = & MI ; MachineBasicBlock :: iterator NextMIIt = MachineBasicBlock :: iterator ( MI ) ; if ( isCMOVPseudo ( MI ) ) { while ( NextMIIt != ThisMBB -> end ( ) && isCMOVPseudo ( * NextMIIt ) && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CC || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) ) { LastCMOV = & * NextMIIt ; ++ NextMIIt ; NextMIIt = skipDebugInstructionsForward ( NextMIIt , ThisMBB -> end ( ) ) ; } } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn (


<s> if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU


<s> bool is_store = MEM_P ( dest ) ; rtx addr ; if ( is_store ) addr = XEXP ( dest , <NUM_LIT> ) ; else addr = XEXP ( src , <NUM_LIT> ) ; if ( ! REG_P ( addr ) ) addr


<s> if ( GET_CODE ( addr ) == PLUS && sparc_pic_register_p ( XEXP ( addr , <NUM_LIT> ) ) && symbolic_operand ( XEXP ( addr , <NUM_LIT> ) , VOIDmode ) ) return true ; return


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII

, const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) {


<s> if ( rclass == FLAG_REGS ) return from == to ; return true


<s> if ( EVT . getSizeInBits ( ) * NumElts == <NUM_LIT> ) return false ; if ( NumElts == <NUM_LIT> ) return true ; if ( NumElts == <NUM_LIT> ) { return ( isMOVLMask ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> ) || isCommutedMOVL ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> , true ) || isSHUFPMask ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> ) ||

isCommutedSHUFP ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>JITInfo :: Initialize ( const MachineFunction & MF , bool isPIC ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) { EVT PtrVT = Op . getValueType ( ) ; GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , PtrVT , GSDN -> getOffset ( ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = GSDN -> getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl


<s> } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( Br . MI , DestBB , MaxOffs ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Br . MI ) ; Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; unsigned DestOffset = BBInfo [ DestBB -> getNumber


<s> if ( NumOps != <NUM_LIT> ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; unsigned NumBytes = LinkageSize + <NUM_LIT> * PtrByteSize ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) report_fatal_error ( <STR_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT>


<s> if ( ( flags & VEC_ANY_SVE ) && costs -> sve ) return costs -> sve ; return costs


<s> unsigned EltOffset = SplatVal . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SDLoc DL ( & St ) ; SDValue BasePtr = St . getBasePtr ( ) ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( )


<s> emit_move_insn ( reg , offset_rtx ) ; emit_insn ( gen_addsi3 ( reg , reg , stack_pointer_rtx ) ) ; return


<s> return ( isConstantImm ( ) && isUInt < <NUM_LIT> > (


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned ReturnReg = ( PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; SDValue BlockPtr = DAG . getMCSymbol ( DestMBB -> getSymbol


<s> MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI


<s> wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case V16HImode : case V32QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; else { machine_mode hvmode = ( mode == V16HImode ? V8HImode : V16QImode ) ; rtx x = gen_reg_rtx ( hvmode ) ; ok = ix86_expand_vector_init_duplicate ( false , hvmode , x , val ) ; gcc_assert ( ok ) ; x = gen_rtx_VEC_CONCAT ( mode , x , x ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; case V64QImode : case V32HImode : if ( TARGET_AVX512BW ) return ix86_vector_duplicate_value ( mode , target , val ) ; else { machine_mode hvmode = ( mode == V32HImode ? V16HImode : V32QImode ) ; rtx x = gen_reg_rtx ( hvmode ) ; ok = ix86_expand_vector_init_duplicate ( false , hvmode , x , val ) ; gcc_assert ( ok


<s> F -> setComdat ( M . getOrInsertComdat ( Name ) ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T ) , OSABI ( _OSABI ) { HasReliableSymbolDifference = true


<s> if ( Op == Load . getValue ( <NUM_LIT> ) ) { FoundLoad = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } LoopWorklist . push_back ( Op . getNode ( ) ) ; ChainOps . push_back ( Op ) ; } } if ( ! FoundLoad ) return false ; for ( SDValue Op : StoredVal -> ops ( ) ) if ( Op . getNode ( ) != LoadNode ) LoopWorklist . push_back ( Op . getNode ( ) ) ; if ( SDNode :: hasPredecessorHelper ( Load . getNode ( ) , Visited , LoopWorklist , Max , true ) ) return false ; InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain )


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 ,


<s> if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue , Size ) ; } else getStreamer ( ) . EmitValue ( Value , Size , ExprLoc ) ; return false ; } ; parseMany (


<s> rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < <NUM_LIT> || retval > <NUM_LIT> ) return <NUM_LIT> ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return


<s> int ix86_local_alignment ( tree type , int align ) { if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= <NUM_LIT> || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( TYPE_MODE ( type ) == XCmode && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } return align


<s> for ( unsigned i = <NUM_LIT> , e = MBBs . size ( ) ; i != e ; ++ i ) { if ( IsPIC ) emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> , JTBase ) ; else emitMachineBasicBlock ( MBBs [ i


<s> return CallsEhReturn && ( FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_vpermt2vard512_mask ( ( __v16si ) __I , ( __v16si )


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHUFFLE_VECTOR ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ExtInfo = getExtMask ( MI . getOperand ( <NUM_LIT> ) . getShuffleMask ( ) , MRI . getType ( Dst ) . getNumElements ( ) ) ; if ( ! ExtInfo ) return false ; bool ReverseExt ; uint64_t Imm ; std :: tie ( ReverseExt , Imm ) = * ExtInfo ; Register V1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register V2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ReverseExt ) std :: swap ( V1 , V2 ) ; uint64_t ExtFactor = MRI . getType ( V1 ) . getScalarSizeInBits ( ) / <NUM_LIT> ; Imm *= ExtFactor ; MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , Dst , { V1 , V2 , Imm } ) ; return true


<s> JalrInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; JalrInst . addOperand ( FirstRegOp ) ; } } else if ( Opcode == <STR_LIT> ) { if ( IsCpRestoreSet && inMicro<ISA_LIT>Mode ( ) ) JalrInst . setOpcode ( <STR_LIT> ) ; else JalrInst . setOpcode ( inMicro<ISA_LIT>Mode ( ) ? <STR_LIT> : <STR_LIT> ) ; JalrInst . addOperand ( FirstRegOp ) ; const MCOperand SecondRegOp = Inst . getOperand ( <NUM_LIT> ) ; JalrInst . addOperand ( SecondRegOp ) ; } Out . EmitInstruction ( JalrInst , * STI ) ; const MCInstrDesc & MCID = getInstDesc ( JalrInst . getOpcode ( ) ) ; if ( MCID . hasDelaySlot ( ) && AssemblerOptions . back ( ) -> isReorder ( ) ) TOut . emitEmptyDelaySlot ( hasShortDelaySlot ( JalrInst . getOpcode ( ) ) , IDLoc , STI ) ; return


<s> static void AnalyzeVarArgs ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Ins ) { State . AnalyzeFormalArguments ( Ins


<s> if ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE )

addPass ( createGlobalMergePass ( TM , <NUM_LIT> ) ) ;


<s> SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfOffset , DL ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfOffset ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ch0


<s> Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> unsigned OpFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; EVT DestEVT = TLI . getValueType ( DL , GV -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return <NUM_LIT> ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; unsigned LdrOpc ; if ( Subtarget -> isTargetILP32 ( ) ) { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } else { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress

( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> | OpFlags ) ;


<s> if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setReg ( RegMO -> getReg ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setIsKill ( RegMO -> isKill ( ) ) ; MI . getOperand ( III . ImmOpNo ) . setImm ( Imm ) ; if ( DefMI . getParent ( ) == MI . getParent ( ) ) { auto IsKilledFor = [ & ] ( unsigned Reg ) { MachineBasicBlock :: const_reverse_iterator It = MI ; MachineBasicBlock :: const_reverse_iterator E = DefMI ; It ++ ; for ( ; It != E ; ++ It ) { if ( It -> killsRegister ( Reg ) ) return true ; } return false ; } ; if ( RegMO -> isKill ( ) || IsKilledFor ( RegMO -> getReg ( ) ) ) fixupIsDeadOrKill ( DefMI , MI


<s> static DecodeStatus DecodeMSRMask ( MCInst & Inst , unsigned Val , uint64_t Address


<s> bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; uint8_t OpFlagHi = IsPIC ? <STR_LIT> : <STR_LIT> ; uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , OpFlagHi ) ; SDValue Lo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const uint16_t * AsI = TRI . getOverlaps ( Reg ) ; *

AsI ; ++ AsI ) Uses . insert ( * AsI ) ;


<s> static void adjustForSubtraction ( SelectionDAG & DAG , SDLoc DL , Comparison & C ) { if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> ) { for ( auto I = C . Op0 -> use_begin ( ) , E = C . Op0 -> use_end ( ) ; I != E ; ++ I ) { SDNode * N = * I ; if ( N -> getOpcode ( ) == <STR_LIT> && ( ( N -> getOperand ( <NUM_LIT> ) == C . Op0 && N -> getOperand ( <NUM_LIT> ) == C . Op1 ) || ( N -> getOperand ( <NUM_LIT> ) == C . Op1 && N -> getOperand ( <NUM_LIT> ) ==


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { llvm_unreachable ( <STR_LIT>


<s> const MCExpr * E = MO . getExpr ( ) ; MCFixupKind Kind ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( E ) ) { const int64_t Value = MCE -> getValue ( ) ; if ( Value > UINT32_MAX ) report_fatal_error ( <STR_LIT> ) ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : return ( int32_t ( Value ) & <NUM_LIT> ) >> <NUM_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable (


<s> inline vector unsigned int vec_subc ( vector unsigned int a1


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { enum loongarch_symbol_type pcrel = TARGET_CMODEL_EXTREME ? SYMBOL_PCREL64 : SYMBOL_PCREL ; if ( ! SYMBOL_REF_P ( x ) ) return pcrel ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( ! loongarch_symbol_binds_local_p ( x ) ) return SYMBOL_GOT_DISP ; tree t = SYMBOL_REF_DECL ( x ) ; if ( ! t ) return pcrel ; t = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( t ) ) ; if ( ! t ) return pcrel ; t = TREE_VALUE ( TREE_VALUE ( t ) ) ; gcc_assert ( TREE_CODE ( t ) == STRING_CST ) ; const char * model = TREE_STRING_POINTER ( t ) ; if ( strcmp ( model , <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned Count = CSI . size ( ) ; DebugLoc DL ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) { unsigned idx = Count - i - <NUM_LIT> ; unsigned Reg1 = CSI [ idx ] . getReg ( ) ; unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc =


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case FK_Data_4 :


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI ( ) && <STR_LIT>


<s> else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return aarch64_lookup_simd_builtin_type ( mode ,


<s> rtx drap_vreg ; rtx arg_ptr ; rtx_insn * seq , * insn ; arg_ptr = gen_rtx_REG ( Pmode , regno ) ; crtl -> drap_reg = arg_ptr ; start_sequence ( ) ; drap_vreg = copy_to_reg ( arg_ptr ) ; seq = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_before ( seq , NEXT_INSN ( entry_of_function ( ) ) ) ; if ( ! optimize ) { add_reg_note ( insn , REG_CFA_SET_VDRAP , drap_vreg


<s> MCOp = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm (