<s> getT2SORegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits


<s> MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) { MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } Register ScratchReg = MI . getOperand ( ScratchIdx ) .


<s> machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vspltisb || icode == CODE_FOR_altivec_vspltish || icode == CODE_FOR_altivec_vspltisw || icode == CODE_FOR_spe_evsplatfi || icode == CODE_FOR_spe_evsplati ) { if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> ||


<s> s += strlen ( s ) ; n = XVECLEN ( pattern , <NUM_LIT> ) ; set = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; mips_split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ; last_set = XVECEXP ( pattern , <NUM_LIT> , n - <NUM_LIT> ) ; last_reg = save_p ? SET_SRC ( last_set ) : SET_DEST ( last_set ) ; if ( REGNO ( last_reg ) == <NUM_LIT> ) n -- ; gcc_assert ( n <= <NUM_LIT> ) ; if ( n == <NUM_LIT> ) ; else if ( n == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; else if ( n < <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> + n ] ) ; else if ( n == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; if ( REGNO ( last_reg ) == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; s += sprintf ( s , <STR_LIT> , ( int ) offset , reg_names [ REGNO ( base ) ] ) ; return buffer


<s> StringRef getPassName ( ) const override { return


<s> } MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && V1 . getValueType ( ) . getVectorNumElements ( ) == NumElems / <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getSizeInBits ( ) >= <NUM_LIT> ) return Op ; bool IsZeroV1 = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsZeroV2 = <STR_LIT> ( V2 . getNode ( )


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM -> add ( createGlobalMergePass (


<s> else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT>


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues (


<s> bool isScratchReg ( unsigned RegNo ) { return RegNo > <NUM_LIT> && RegNo


<s> if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) ; return getAIXFuncEntryPointSymbolSDNode ( F -> getName ( ) ,


<s> unsigned <ISA_LIT>ConstantIslands :: getOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> GetInstSizeInBytes ( I ) ; } return


<s> unsigned getReg ( ) const { assert ( isRegBase ( ) &&


<s> const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( )


<s> struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn )


<s> unsigned Sm = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm + <NUM_LIT> ) ) ) ; OpIdx += <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRm ( insn , false ) ) ) ) ; ++ OpIdx ; } return


<s> return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ||


<s> return ( __m128d ) __builtin_ia32_cvtusi2sd32 ( ( __v2df )


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , reg_ok_strict , ( reload_completed ? <STR_LIT> : (

reload_in_progress ? <STR_LIT> : <STR_LIT> ) ) , GET_RTX_NAME ( GET_CODE ( x ) ) ) ;


<s> void <ISA_LIT>InstPrinter :: print<ISA_LIT>SymbolOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isImm (


<s> bool hasMTHC1 ( ) const { return true


<s> if ( GET_CODE ( dest ) == SUBREG ) dest = SUBREG_REG ( dest ) ; if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || aarch64_classify_vector_mode ( GET_MODE ( dest ) ) != VEC_SVE_DATA || aarch64_classify_vector_mode ( GET_MODE ( src ) ) != VEC_SVE_DATA || ( GET_MODE_UNIT_SIZE ( GET_MODE ( dest ) ) == GET_MODE_UNIT_SIZE ( GET_MODE ( src ) ) ) ) return false ; rtx ptrue = aarch64_ptrue_reg


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> if ( mips_tune == PROCESSOR_SB1 ) return <NUM_LIT> ; return <NUM_LIT>


<s> unsigned type = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder )

: DecodeVSTInstruction ( Inst , Insn , Address , Decoder ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SubReg = <STR_LIT> ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) { SubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return


<s> dest_modifies = side_effects_p ( mem_operand ) ; if ( auto_inc_p ( mem_operand ) ) auto_inc_reg_rtx = XEXP ( mem_operand , <NUM_LIT> ) ; dest_volatile = MEM_VOLATILE_P ( dest ) ; if ( dest_volatile ) { dest = copy_rtx ( dest ) ; MEM_VOLATILE_P ( dest ) = <NUM_LIT> ; } } else if ( GET_CODE ( src ) == MEM ) { mem_operand = XEXP ( src , <NUM_LIT> ) ; src_modifies = side_effects_p ( mem_operand ) ; if ( auto_inc_p ( mem_operand ) ) auto_inc_reg_rtx = XEXP ( mem_operand , <NUM_LIT> ) ; src_volatile = MEM_VOLATILE_P ( src ) ; if ( src_volatile ) { src = copy_rtx ( src ) ; MEM_VOLATILE_P ( src ) = <NUM_LIT> ; } } else mem_operand = NULL_RTX ; if ( mem_operand == NULL_RTX ) { if ( GET_CODE ( src ) == REG && GET_CODE ( dest ) == REG && reg_overlap_mentioned_p ( dest , src ) && REGNO ( dest ) > REGNO ( src ) ) direction = - <NUM_LIT> ; } else if ( GET_CODE ( mem_operand ) == PRE_DEC || ( GET_CODE ( mem_operand ) == PLUS && GET_CODE ( XEXP ( mem_operand , <NUM_LIT> ) ) == PRE_DEC ) ) direction = - <NUM_LIT> ; else if ( GET_CODE ( src ) == MEM && reg_overlap_mentioned_p ( dest , src ) ) { int regno ; gcc_assert ( GET_CODE ( dest ) == REG ) ; regno = REGNO ( dest ) ; gcc_assert ( refers_to_regno_p ( regno , regno + num_words , mem_operand , <NUM_LIT> ) ) ; if ( refers_to_regno_p ( regno , regno + <NUM_LIT> , mem_operand , <NUM_LIT> )


<s> static DecodeStatus decodeBDXAddr12Operand ( MCInst & Inst , uint64_t Field , const unsigned * Regs ) { uint64_t Index = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createReg ( Index == <NUM_LIT> ? <NUM_LIT>


<s> Subtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed


<s> static bool xstormy16_can_eliminate ( const int from , const int


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_MASK_MASK ) |


<s> BuildMI ( headMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackProbed ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( headMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( footMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; headMBB -> addSuccessor ( bodyMBB ) ; headMBB -> addSuccessor ( footMBB ) ; } { addRegOffset ( BuildMI ( bodyMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , StackProbeSize ) ; BuildMI ( bodyMBB , DL , TII . get ( SUBOpc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( bodyMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackProbed ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( bodyMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( bodyMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; bodyMBB -> addSuccessor ( bodyMBB ) ; bodyMBB -> addSuccessor ( footMBB ) ; } { BuildMI ( footMBB , DL , TII . get ( TargetOpcode :: COPY ) , StackPtr ) . addReg ( FinalStackProbed ) . setMIFlag ( MachineInstr :: FrameSetup ) ; addRegOffset ( BuildMI ( footMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; footMBB -> addSuccessor ( & MBB ) ; } recomputeLiveIns ( * headMBB ) ; recomputeLiveIns ( *


<s> switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case 'v' : return


<s> auto setVecVal = [ & ] ( int Idx ) { if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal (


<s> bool Thumb2InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( DestRC == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true


<s> static bool aarch64_reads_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI ,

Register BaseReg , int64_t Offset ) const {


<s> case TYPE_DIV : if ( divmod_p ( producer ) ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : if ( ! post_update_insn_p ( producer )


<s> unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = getOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp ) return true ; } else


<s> unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane ) : - <NUM_LIT> ; int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return SDValue ( ) ; } MVT BlendVT = VT ; if ( EltVT == <STR_LIT> || ( EltVT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) { BlendVT = <STR_LIT> ( <STR_LIT> ( EltVT . getSizeInBits ( ) ) , NumElems ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; } SDValue Ret = DAG . getNode ( <STR_LIT> , dl , BlendVT , V1 , V2 , DAG . getConstant ( MaskValue , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> __inline__ static unsigned long long sh_media_MCMPGT_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> (


<s> return ( __m512i ) __builtin_ia32_pternlogd512_maskz ( ( __v16si ) __A , ( __v16si )


<s> bool res = can_be_rotated_to_lowbits ( c , <NUM_LIT> , & rot ) ; return res && rot >


<s> return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( )

== <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx ,


<s> auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; TM . resetSubtarget ( & MF ) ; return


<s> initRegisterClasses ( ) ; initSPUActions ( ) ; initVPUActions ( ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setMinFunctionAlignment ( Align ( <NUM_LIT> )


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr


<s> MachineBasicBlock * splitBlockAfterInstr ( MachineInstr * MI , MachineFunction & MF ) { MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( ( MI -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ( MI -> getParent ( ) ) -> getIterator ( ) ; ( MI -> getParent ( ) ) -> addSuccessor ( NewBB ) ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; MachineBasicBlock :: iterator T = ( MI -> getParent ( ) ) -> instr_end ( ) , E = ( MI -> getParent ( ) ) -> instr_end ( ) ; if ( T != ( MI -> getParent ( ) ) -> instr_begin ( ) ) T -- ; if ( MI != E && MI != T ) NewBB -> splice ( NewBB -> end ( ) , ( MI -> getParent ( ) ) , MI , ( MI -> getParent ( ) ) -> end ( ) ) ; else errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << MI ->

getParent ( ) -> getName ( ) << <STR_LIT> << * MI << <STR_LIT> ;


<s> unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == <NUM_LIT> && ( ! Alignment || Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> && ( ! Alignment

|| Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> ) ;


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; buildLoad ( LoadVReg , Addr , Size , <NUM_LIT> , MPO ) ; MIRBuilder . buildTrunc ( ValVReg , LoadVReg ) ; }


<s> LHSMI = getDefIgnoringCopies ( LHS , MRI ) ; } if ( ! VRegAndVal || VRegAndVal -> Value != <NUM_LIT> ) { MachineInstr * Cmp ; std :: tie ( Cmp , Pred ) = emitIntegerCompare ( CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , MIB ) ; if ( ! Cmp ) return false ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true ; } if ( tryOptAndIntoCompareBranch ( LHSMI , VRegAndVal -> Value , Pred , DestMBB , MIB ) ) { I . eraseFromParent ( ) ; return true ; } const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ; if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else if ( CmpWidth == <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else return false


<s> if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; LoadedOffsetInAT = true ; warnIfNoMacro ( IDLoc ) ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Out , STI ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) TOut . emitAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , STI ) ; } unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t LeftLoadOffset = <NUM_LIT> , RightLoadOffset = <NUM_LIT> ; if ( isLittle ( ) ) { LeftLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : (


<s> <ISA_LIT>LoadStoreOpt ( ) : MachineFunctionPass ( ID


<s> return MFI -> hasVarSizedObjects ( ) && ! hasBasePointer


<s> bool has<ISA_LIT>32r6 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r6 ||


<s> MachineInstr * MI = I ; const DebugLoc & dl = MI -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg ,

RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ;


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI


<s> Value * <ISA_LIT>IREmitter :: visitVTBL2 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> static rtx gen_add3_const ( rtx rt , rtx ra ,


<s> machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return


<s> return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base ,


<s> if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , SN -> getMemOperand


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP_i32 ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT


<s> auto ScaVT = Scalar . getValueType ( ) ; if ( isMaskType ( ResultVT ) ) return getMaskBroadcast ( ResultVT , Scalar , AVL ) ; if ( isPackedVectorType ( ResultVT ) ) { if ( ScaVT == <STR_LIT> )


<s> convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case NEG : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( V2DImode ) ; emit_insn_before ( gen_move_insn ( subreg , CONST0_RTX ( V2DImode ) ) , insn ) ; src = gen_rtx_MINUS ( V2DImode , subreg , src ) ; break ; case NOT : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( V2DImode ) ; emit_insn_before ( gen_move_insn ( subreg , CONSTM1_RTX ( V2DImode ) ) , insn ) ; src = gen_rtx_XOR ( V2DImode , src , subreg ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ; if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode ,


<s> unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; default : return MCDisassembler ::


<s> V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true ; } } if ( ! IsUnary ) { ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return true ; } ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [

i ] % Size ) / LaneSize != i / LaneSize ) return true ;


<s> const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) <ISA_LIT>MCExpr ( Kind ,


<s> Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( Call ) , getPointerTy ( ) ) ; Type * RetTy = Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; bool isTailCall = isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) ; if ( isTailCall ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , false , false , false , false , <NUM_LIT> , getLibcallCallingConv ( Call ) , isTailCall , false , true , Callee , Args , DAG , SDLoc ( Op ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( ! CallInfo . second . getNode ( ) ) return DAG . getRoot ( ) ; return CallInfo


<s> void aarch64_sve_op_count :: dump ( ) const { <STR_LIT> ( ) ; dump_printf_loc ( MSG_NOTE , vect_location , <STR_LIT> , pred_ops


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , Is64Bit , IsLittleEndian


<s> return TRI -> isCalleeSavedPhysReg ( SubOrSuper , MF ) ; } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI ] ( const TargetRegisterClass * C ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ C , TRI ] ( MCPhysReg SubOrSuper ) { return C == TRI -> getMinimalPhysRegClass ( SubOrSuper ) ; } ) ; } ) ; } ; auto * RegClass = TRI -> getMinimalPhysRegClass ( getLdStRegOp ( FirstMI ) . getReg ( ) ) ; for ( const MCPhysReg & PR : * RegClass ) { if ( DefinedInBB . available ( PR ) && UsedInBetween . available ( PR ) && ! RegInfo . isReserved ( PR ) && ! AnySubOrSuperRegCalleePreserved ( PR ) && CanBeUsedForAllClasses ( PR ) ) { DefinedInBB . addReg ( PR ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( PR , TRI ) << <STR_LIT> ) ; return { PR


<s> TD = Fn . getTarget ( ) . getTargetData ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall


<s> return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , RLI .

Alignment , RLI . IsInvariant ? MachineMemOperand :: MOInvariant : MachineMemOperand :: MONone , RLI . AAInfo , RLI . Ranges ) ;


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return Lower256IntArith ( Op


<s> return isTargetELF ( ) || TM . getRelocationModel ( ) ==


<s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { assert ( MBB . getParent ( ) &&


<s> return hasLAHFSAHF64 ( ) || ! is64Bit


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x )


<s> return ( int64x1_t ) __builtin_neon_vshl_ndi (


<s> static TargetLoweringObjectFile * createTLOF ( <ISA_LIT>TargetMachine & TM ) { bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { if ( is64Bit ) return new <ISA_LIT>64_MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } else if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetELF ( ) ) { if ( is64Bit ) return new <ISA_LIT>64_ELFTargetObjectFile ( TM ) ; return new <ISA_LIT>32_ELFTargetObjectFile ( TM ) ; } else if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetCOFF ( ) ) { return new TargetLoweringObjectFileCOFF ( ) ; } llvm_unreachable ( <STR_LIT> )


<s> EVT PtrVT = Op . getValueType ( ) ; if ( isPositionIndependent ( ) ) { auto GlobalN = dyn_cast < GlobalAddressSDNode > ( Op ) ; if ( isa < ConstantPoolSDNode > ( Op ) || isa < JumpTableSDNode > ( Op ) || ( GlobalN && GlobalN -> getGlobal ( ) -> hasLocalLinkage ( ) ) ) { SDValue HiLo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: AddOptionalDefs ( const MachineInstrBuilder & MIB ) { MachineInstr * MI = & * MIB ; if ( TII . isPredicable ( MI ) || is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR )


<s> if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT>


<s> if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B ) break ; } return BestGrowth != ~


<s> return ( ( qword ) ( vec_or ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8

) ( si_from_ushort ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> bool isImm0_65535 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE


<s> MachineInstr * setRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo


<s> MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid (


<s> Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT>

) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ;


<s> unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MaxLoadsInLDM = Subtarget . isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && Subtarget . hasMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; auto getRemainingValueType = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } ; auto getRemainingSize = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> )


<s> SDLoc dl ( Op ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue SrcReg64 = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; SDValue Lo32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; Hi32 = DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Hi32 ) ; SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DstReg64 , Hi32 ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT>


<s> O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs << <STR_LIT> ; O << <STR_LIT>


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return <STR_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context


<s> else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; SDNode * VSt = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VSt ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , VSt ) ; return ; } SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , RegSeq , Pred , Reg0 , Chain } ; SDNode * VStA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , MemAddr . getValueType ( ) , <STR_LIT> , OpsA ) ; cast < MachineSDNode > ( VStA ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VStA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode (


<s> if ( Compare -> isCompare ( ) ) reg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( isLoadAndTestAsCmp ( Compare ) ) reg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( reg ) ; return


<s> DItype __fixsfdi ( SFtype a ) { if ( a < <NUM_LIT> ) return - local_fixunssfdi ( -


<s> base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base


<s> emit_insn ( gen_load_locked_si ( reg , mem


<s> static int mips_fpr_return_fields ( const_tree valtype , tree * fields , bool * has_cxx_zero_width_bf , bool * has_cxx17_empty_base ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return <NUM_LIT> ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return <NUM_LIT> ; i = <NUM_LIT> ; for ( field = TYPE_FIELDS ( valtype ) ; field != <NUM_LIT> ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( cxx17_empty_base_field_p ( field ) ) { * has_cxx17_empty_base = true ; continue ; } if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * has_cxx_zero_width_bf = true ; continue ; } if ( ! SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field )


<s> static bool isDisp8 ( int Value ) { return Value == ( signed char )


<s> return ( __mmask8 ) __builtin_ia32_cmppd512_mask ( ( __v8df ) __X , ( __v8df )


<s> return ( __m256i ) __builtin_ia32_expandloadsi256_mask ( ( __v8si * ) __P , ( __v8si ) __W ,


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , -


<s> From = V2 ; To = V1 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( const int & i ) { return i >= <NUM_LIT> ; } ) - Mask . begin ( ) ; } if ( MayFoldLoad ( From ) ) { SDValue NewLoad = NarrowVectorLoadToElement ( cast < LoadSDNode > ( From ) , DestIndex , DAG ) ; if ( ! NewLoad . getNode ( ) ) return SDValue ( ) ; if ( EVT == <STR_LIT> ) { SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad ) ; SDValue InsertpsMask = DAG . getIntPtrConstant ( DestIndex << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , To , LoadScalarToVector , InsertpsMask ) ; } else


<s> gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT &&


<s> df_ref src_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx and_base = XEXP ( and_operation , <NUM_LIT> ) ; rtx new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( and_base ) , new_reg , XEXP ( and_operation , <NUM_LIT> ) ) ; SET_SRC ( body ) = src_reg ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn


<s> if ( TLI -> isOperationLegalOrCustom ( Opcode , VTy ) ) continue ; else if ( VTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , VTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst > ( J ) ; if ( CI -> getSrcTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || CI -> getDestTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getSrcTy ( ) -> getScalarType ( ) ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getDestTy ( ) -> getScalarType ( ) ) ) return true ; } else if ( isLargeIntegerTy ( TT . isArch32Bit ( ) , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: UDiv || J -> getOpcode ( ) == Instruction :: SDiv || J -> getOpcode ( ) == Instruction :: URem || J -> getOpcode ( ) == Instruction :: SRem ) ) { return true ; } else if ( isa < IndirectBrInst > ( J ) || isa < InvokeInst > ( J ) ) { return true ; } else if ( SwitchInst * SI = dyn_cast < SwitchInst > ( J ) ) { if ( ! TM ) return true ; const TargetLowering * TLI = TM -> getTargetLowering ( ) ; if ( TLI -> supportJumpTables ( ) && SI -> getNumCases ( ) + <NUM_LIT> >= ( unsigned ) TLI -> getMinimumJumpTableEntries ( ) ) return true ; } } return false


<s> if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; bool Changed = false ; int FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; Changed =


<s> if ( SDValue Val = performAddDotCombine ( N , DAG ) ) return Val ; if ( SDValue Val = performAddCSelIntoCSinc ( N ,


<s> pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = <NUM_LIT> ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; return emit_insn ( pat )


<s> const <ISA_LIT>Subtarget & ST = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = ST . in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : ST . isABI_N64 ( )


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTblPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTblPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > SSE42CostTblNoPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTblNoPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( IsPairwise ) { if ( ST -> hasAVX ( ) ) { int Idx = CostTableLookup ( AVX1CostTblPairWise , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTblPairWise [ Idx ] . Cost ; } if ( ST ->


<s> unsigned ByValSizeInBytes = Flags . getByValSize ( ) ; unsigned OffsetInBytes = <NUM_LIT> ; unsigned RegSizeInBytes = CC . regSize ( ) ; unsigned Alignment = std :: min ( Flags . getByValAlign ( ) , RegSizeInBytes ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; if ( ByVal . NumRegs ) { const ArrayRef < MCPhysReg > ArgRegs = CC . intArgRegs ( ) ; bool LeftoverBytes = ( ByVal . NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < ByVal . NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { assert ( ( ByValSizeInBytes > OffsetInBytes ) && ( ByValSizeInBytes < OffsetInBytes + RegSizeInBytes ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes *


<s> assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; PassThru = ExtendToType ( PassThru , WideDataVT , DAG ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , PassThru , N -> getMemoryVT ( ) , N

-> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ;


<s> static inline unsigned getImm2 ( uint32_t insn


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val )


<s> V2 = peekThroughBitcasts ( V2 ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands


<s> bool hasMessageSecurityAssist9 ( ) const { return HasMessageSecurityAssist9


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> SMLoc S , E ; unsigned BaseReg = <NUM_LIT> ; if ( ParseRegister ( BaseReg , S , E ) ) { return MatchOperand_NoMatch ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Comma : case AsmToken :: RBrac : case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( BaseReg , nullptr , S , E ) ) ; return


<s> Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; const bool HasSPE = Subtarget -> hasSPE ( ) ; const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Alignment ) ; unsigned Opc ; if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; }


<s> const char * host_detect_local_cpu ( int argc , const char * * argv ) { const char * cpu = NULL ; const char * cache = <STR_LIT> ; const char * options = <STR_LIT> ; bool arch ; bool assembler ; size_t i ; if ( argc < <NUM_LIT> ) return NULL ; arch = strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ; assembler = ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) ; if ( ! arch && ! assembler && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; if ( ! assembler ) { cache = detect_caches_aix ( ) ; cache = detect_caches_darwin ( ) ; cache = detect_caches_freebsd ( ) ; cache = <STR_LIT> ; cache = detect_caches_linux ( ) ; cache = <STR_LIT> ; cache = <STR_LIT> ; } cpu = detect_processor_aix ( ) ; cpu = detect_processor_darwin ( ) ; cpu = detect_processor_freebsd ( ) ; cpu = detect_processor_linux ( ) ; cpu = <STR_LIT> ; if ( assembler ) { for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( asm_names ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( )

. hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_RegMask ;


<s> ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VSPLTISW0 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW1 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW2 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW3 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSLDOI4 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) , DAG


<s> return ( int32x2_t ) __builtin_neon_vqrdmulhv2si ( __a ,


<s> nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3pop ( Rb , Re , fpr_space ) ; } else { nds32_emit_stack_v3pop ( Rb , Re


<s> if ( CPEs [ J ] . RefCount == <NUM_LIT> && CPEs [ J ] . CPEMI ) { removeDeadCPEMI ( CPEs [ J ] . CPEMI ) ; CPEs [ J ] . CPEMI = nullptr ; MadeChange = true ; } } } return MadeChange


<s> const __v4su shmax = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4su result ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v4su ) __B ,


<s> } if ( Sym && Sym -> isELF ( ) ) { unsigned Type = cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) { if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) return true ; if ( ! Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; } } if ( A && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT>


<s> unsigned getBranchTargetOpValue ( const MachineInstr &


<s> inline vector signed short vec_cmpgtsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vcmpgtsh ( ( vector signed short ) a1 , ( vector


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> static int stackSlotSize ( ) { return <NUM_LIT>


<s> if ( AvoidDupAddrCompute && ! N . hasOneUse ( ) ) { unsigned Opcode = N . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = N . getNode ( ) -> use_begin ( ) , UE = N . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( N , AM ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( N , AM ) ) return false ; MVT VT = N . getValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ; return true


<s> void emitDataMappingSymbol ( ) { if ( LastEMS == EMS_Data ) return ; EmitMappingSymbol ( <STR_LIT> ) ; LastEMS = EMS_Data


<s> static SDValue getLegalSplat ( SelectionDAG & DAG , SDValue V , int EltNo ) { MVT VT = V . getSimpleValueType ( ) ; SDLoc dl ( V ) ; if ( VT . is128BitVector ( ) ) { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else if ( VT . is256BitVector ( ) ) { int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> } ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MCE . addRelocation ( MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , JTI


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( )


<s> static const <ISA_LIT>MCExpr * CreateGOTTPRELLo12 ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_AARCH64_GOTTPREL_LO12 ,


<s> return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ==


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = <NUM_LIT> ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = <NUM_LIT> ; return true ; } if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; return true ; } return false


<s> const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && FrameIndex == RS -> getScavengingFrameIndex ( ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } bool Done = false


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned Opc = DefMI . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; assert ( DefMI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; RegMO = & DefMI . getOperand ( <NUM_LIT> ) ; ImmMO = & DefMI . getOperand ( <NUM_LIT>


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= <NUM_LIT> && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == <NUM_LIT> || DstAlign >= <NUM_LIT> ) && ( SrcAlign == <NUM_LIT> || SrcAlign >= <NUM_LIT> ) ) ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation =


<s> static DecodeStatus DecodeVR128BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ,


<s> case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : Opc = UseUnscaled ? <STR_LIT> : <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; ScaleFactor = <NUM_LIT> ; break ; } if ( ! UseUnscaled ) { int64_t Offset = Addr . getOffset ( ) ; if ( Offset & ( ScaleFactor - <NUM_LIT> ) ) return EmitLoad ( VT , ResultReg , Addr , true ) ; Addr . setOffset ( Offset / ScaleFactor ) ; } if ( ! SimplifyAddress ( Addr , VT , UseUnscaled ? <NUM_LIT> : ScaleFactor , UseUnscaled ) ) return false ; ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOLoad , UseUnscaled ) ; if ( VTIsi1 ) { MRI . constrainRegClass ( ResultReg


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseAdrLabel ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( Parser . getTok ( ) . is ( AsmToken ::


<s> if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ! ByteOk && ! HalfWordOk ) continue ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; CPUser & User = CPUsers [ JumpTableUserIndices [ JTI ] ] ; unsigned DeadSize = <NUM_LIT> ; bool CanDeleteLEA = false ; bool BaseRegKill = false ; bool PreservedBaseReg = preserveBaseRegister ( MI , User . MI , DeadSize , CanDeleteLEA , BaseRegKill ) ; if ( ! jumpTableFollowsTB ( MI , User . CPEMI ) && ! PreservedBaseReg ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstr * CPEMI = User . CPEMI ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock :: iterator MI_JT = MI ; MachineInstr * NewJTMI = BuildMI ( * MBB , MI_JT , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( User . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getKillRegState ( BaseRegKill ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned JTOpc = ByteOk ? <STR_LIT> : <STR_LIT> ; CPEMI -> setDesc ( TII -> get ( JTOpc ) ) ; if ( jumpTableFollowsTB ( MI , User . CPEMI ) ) { NewJTMI -> getOperand ( <NUM_LIT> ) . setReg


<s> static SDValue LowerCTTZ ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; unsigned NumBits = VT . getScalarSizeInBits ( ) ; SDLoc dl ( Op ) ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT>


<s> if ( L && ! L -> isLoopInvariant ( MI ) ) return false ; MachineInstr * MovMI = MRI -> getUniqueVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SubregToRegMI = nullptr ; if ( MovMI -> getOpcode ( ) == TargetOpcode :: SUBREG_TO_REG ) { SubregToRegMI = MovMI ; MovMI = MRI -> getUniqueVRegDef ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MovMI -> getOpcode ( ) != <STR_LIT> && MovMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneUse ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( SubregToRegMI && ! MRI -> hasOneUse ( SubregToRegMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; T UImm = static_cast < T > ( MovMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( SubregToRegMI ) UImm &=


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB ,


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT> )


<s> return ( __m128i ) __builtin_ia32_vpdpwssd_v4si ( ( __v4si ) __A , ( __v4si )


<s> SMLoc SIdx = getLoc ( ) ; if ( parseOptionalToken ( AsmToken :: LBrac ) ) { const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_NoMatch ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; ; } SMLoc E = getLoc ( ) ; if ( parseToken ( AsmToken :: RBrac , <STR_LIT> ) ) return MatchOperand_ParseFail ; ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorIndex ( MCE -> getValue ( ) , SIdx , E ,


<s> static void do_rotl3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_rotldi3 (


<s> bool pru_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { bool in_memory = ( ! pru_arg_in_reg_bysize ( int_size_in_bytes ( type ) ) ||

int_size_in_bytes ( type ) == - <NUM_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * RegNo ; } } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isDFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( bit_cast < double > ( MO . getDFPImm ( ) ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } llvm_unreachable ( <STR_LIT>


<s> MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MF ->


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { DebugLoc dl = Node -> getDebugLoc ( ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( Node -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return NULL ; } switch ( Node -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; return


<s> EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; return


<s> return getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , STI . getFeatureBits ( ) , getContext (


<s> static SDValue carryFlagToValue ( SDValue Flag , EVT VT , SelectionDAG & DAG , bool Invert ) { assert ( Flag . getResNo ( ) == <NUM_LIT> ) ; SDLoc DL ( Flag ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; unsigned Cond = Invert ?


<s> if ( ! isMem ( ) || ! Memory . OffsetRegNum || Memory . Alignment != <NUM_LIT> ) return false ; return true


<s> Inst . addOperand ( MCOperand :: createImm ( ( Imm + Add ) & ( Add -


<s> SDValue NewAdd = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewXor , NewAdd ) ; } if ( SDValue V = combineSubABS ( N , DAG ) ) return V ; if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 -> hasOneUse ( ) && <STR_LIT> ( Op1 . getOperand ( <NUM_LIT> ) ) ) { assert ( ! Op1 -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , Op1 -> getVTList ( ) , Op0 , Op1

. getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ;


<s> break ; case 'z' : { if ( ! isNullConstant ( Op ) ) return ; if ( Op . getValueType ( ) == <STR_LIT> ) Result = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else Result = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; break ; } case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return ; uint64_t CVal = C -> getZExtValue ( ) ; switch ( ConstraintLetter ) { case 'I' : if ( isUInt < <NUM_LIT> > ( CVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( CVal ) ) break ; return ; case 'J' : { uint64_t NVal = - C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( NVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( NVal ) ) { CVal = C -> getSExtValue ( ) ; break ; } return ; } case 'K' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'L' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'M' : { if ( ! isUInt < <NUM_LIT> > ( CVal ) ) return ; if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ ( uint32_t ) CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } case 'N' : { if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal )


<s> void addMemoryRegisterOffsetOperands ( MCInst & Inst , unsigned N , bool DoShift ) { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getXRegFromWReg ( Mem . OffsetRegNum ) ) ) ; unsigned ExtendImm = <STR_LIT> ( Mem . ExtType , DoShift


<s> void setAllIllegal ( ) { LegalDstDomains . clear (


<s> while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ++ MII ; NumNOPBytes -= <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> ; i < NumNOPBytes ; i += <NUM_LIT> ) EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) .


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value < <NUM_LIT>


<s> MVT getScalarShiftAmountTy ( EVT LHSTy )


<s> bool <ISA_LIT>TTIImpl :: useReductionIntrinsic ( unsigned Opcode , Type * Ty ,


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst

. addOperand ( MCOperand :: createImm ( Val << <NUM_LIT> ) ) ;


<s> if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; EVT ExtractVT = Extract -> getValueType ( <NUM_LIT> ) ; if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> BinOp ; SDValue Src = DAG . matchBinOpReduction ( Extract , BinOp , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ; if ( ! Src ) return SDValue ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getScalarType ( ) ; if ( SrcSVT != ExtractVT || ( SrcVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { unsigned NumElts = SrcVT . getVectorNumElements ( ) ; unsigned NumSubElts = NumElts / <NUM_LIT> ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcSVT , NumSubElts ) ; unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT


<s> return ; } if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget . isABI_N32 ( ) ) { const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) .


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFEXP2_D_1 ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; Register Ws1 = RegInfo . createVirtualRegister ( RC ) ; Register Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent


<s> case CortexA73 : case CortexA75 : case CortexA76 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT>


<s> return __builtin_mve_vrshlq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __b ,


<s> return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT PtrTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; auto * MINode = cast < MemIntrinsicSDNode > ( N ) ; SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL


<s> if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getBlockAddress ( AM . BlockAddr , <STR_LIT> , true , <NUM_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM .


<s> } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( ! V . getValueType ( ) . isVector ( ) || V . getValueType ( ) . isScalableVector ( ) ) && <STR_LIT> ) ; Operands . push_back


<s> CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeSet :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets , VReg ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; Success = handleAssignments ( MIRBuilder , AssignFn , SplitArgs , Handler ) ; } MIRBuilder . insertInstr ( MIB ) ; return Success


<s> return __builtin_aarch64_lflooruv2dfv2di_us (


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; if ( BaseReg . getReg ( ) == <STR_LIT> ) { assert ( IndexReg . getReg ( )


<s> if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed =


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else { CmpMask = CmpValue = <NUM_LIT> ; } return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT>


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>XCOFFObjectWriter ( bool Is64Bit ) { return std :: make_unique < <ISA_LIT>XCOFFObjectWriter >


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( )


<s> void addRegF4RCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> static void aarch64_emit_binop ( rtx dest , optab binoptab , rtx op0 , rtx op1 ) { rtx tmp = expand_binop ( GET_MODE ( dest ) , binoptab , op0 , op1 , dest ,


<s> static unsigned getPreIndexedLoadStoreOpcode ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT>


<s> if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ; return getGSVectorCost ( Opcode , SrcVTy , Ptr ,


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && ( ! Alignment || * Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> && (

! Alignment || * Alignment >= <NUM_LIT> ) ) || EltWidth == <NUM_LIT> ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue


<s> const auto & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) && Op .


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case <NUM_LIT> : return gen_rtx_SUBREG ( vmode , gpr , <NUM_LIT> ) ; case <NUM_LIT> : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX


<s> nodeptr -> right = t -> rbt_nil ; nodeptr -> par = NULL ; nodeptr -> color = RBT_RED ; return nodeptr


<s> updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; if ( ! SrcVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SrcVT . is256BitVector ( ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return


<s> FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false


<s> union { vec_uchar16 v ; unsigned int i [ <NUM_LIT> ] ; } x ; unsigned int cnt ; vec_uchar16 mask ; x . v = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; cnt = x . i


<s> int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( ! UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) ) return DAG . getTargetConstant ( ~ <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . isUndef ( ) ) continue ; if ( ! OpVal . getNode ( ) ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( ! OpVal . getNode ( ) ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= RC -> getSize (


<s> int PBPSI = FI -> getPICBasePointerSaveIndex ( ) ; PBPSI = MFI -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx


<s> unsigned ElementWidth = StringSwitch < unsigned > ( Kind . lower ( ) ) . Case ( <STR_LIT> , - <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT>

) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ;


<s> NotRIPRel |= IndexReg . getReg ( ) || BaseReg . getReg ( ) ; if ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) { printOperand ( MI , Op + <NUM_LIT> , <STR_LIT> , NotRIPRel ) ; } else { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; unsigned BaseRegOperand = <NUM_LIT> , IndexRegOperand = <NUM_LIT> ; if ( IndexReg . getReg ( ) == <STR_LIT> || IndexReg . getReg ( ) == <STR_LIT> ) { assert ( ScaleVal == <NUM_LIT> && <STR_LIT> ) ; std :: swap ( BaseReg , IndexReg ) ; std :: swap ( BaseRegOperand , IndexRegOperand ) ; } O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op + BaseRegOperand , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + IndexRegOperand , Modifier ) ; if ( ScaleVal != <NUM_LIT> ) O << ',' << ScaleVal ; } O <<