<s> SDValue Value = StoreNode -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && MemVT . getVectorElementCount ( ) . Min % <NUM_LIT> == <NUM_LIT> && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( MemVT . getVectorElementCount ( ) . Min / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } return SDValue


<s> void <ISA_LIT>MCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const { switch ( getKind ( ) ) { default : return ; case VK_AARCH64_DTPREL_G2 : case VK_AARCH64_DTPREL_G1 : case VK_AARCH64_DTPREL_G1_NC : case VK_AARCH64_DTPREL_G0 : case VK_AARCH64_DTPREL_G0_NC : case VK_AARCH64_DTPREL_HI12


<s> unsigned <ISA_LIT>RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return Is64Bit ? <NUM_LIT>


<s> MachineInstr * PrevMI = <NUM_LIT> ; if ( I != BB . begin ( ) ) PrevMI = prior ( I ) ; ++ NumFP ; DEBUG ( errs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI


<s> case <NUM_LIT> : if ( const_arith_operand ( offset , Pmode ) || GET_CODE ( offset ) == LO_SUM ) return <STR_LIT> ; else return <STR_LIT> ; case <NUM_LIT> : if ( const_arith_operand ( offset , Pmode ) || GET_CODE ( offset ) == LO_SUM ) return <STR_LIT> ; else return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( src_code == HIGH ) { rtx offset , x ; split_const ( XEXP ( src , <NUM_LIT> ) , & x , & offset ) ; enum loongarch_symbol_type type = SYMBOL_PCREL ; if ( UNSPEC_ADDRESS_P ( x ) ) type = UNSPEC_ADDRESS_TYPE ( x ) ; if ( type == SYMBOL_TLS_LE ) return <STR_LIT> ; else return <STR_LIT> ; } if ( src_code == CONST_INT ) { if ( LU12I_INT ( src ) ) return <STR_LIT> ; else if ( IMM12_INT ( src ) ) return <STR_LIT> ; else if ( IMM12_INT_UNSIGNED ( src ) ) return <STR_LIT> ; else if ( LU52I_INT ( src ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } } if ( ! TARGET_EXPLICIT_RELOCS && dest_code == REG && symbolic_operand ( src , VOIDmode ) ) { if ( loongarch_classify_symbol ( src ) == SYMBOL_PCREL ) return <STR_LIT> ; else return <STR_LIT> ; } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? <STR_LIT> : <STR_LIT> ; if ( dest_code == MEM ) { const char * insn = NULL ; insn = loongarch_output_move_index_float ( XEXP ( dest , <NUM_LIT> ) , GET_MODE ( dest ) , false ) ; if ( insn


<s> MCInst BSICInst ; BSICInst . setOpcode ( <STR_LIT> ) ; BSICInst . addOperand ( R1 ) ; BSICInst . addOperand ( R2 )


<s> for ( i = <NUM_LIT> ; i < count - <NUM_LIT> ; i ++ ) XVECEXP ( vector , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT (

( i + <NUM_LIT> ) * UNITS_PER_WORD ) ) ) , gen_rtx_REG ( SImode , high - i ) ) ;


<s> return ( __mmask32 ) __builtin_ia32_cmpw512_mask ( ( __v32hi ) __X , (


<s> else cond = NULL_RTX ; if ( subtargets || code == SET || ( REG_P ( target ) && REG_P ( source ) && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! cfun -> machine -> after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , <NUM_LIT> , <NUM_LIT> ) > ( arm_constant_limit ( optimize_function_for_size_p ( cfun ) ) + ( code != SET ) ) ) ) { if ( code == SET ) { if ( TARGET_USE_MOVT ) arm_emit_movpair ( target , GEN_INT ( val ) ) ; else emit_set_insn ( target , GEN_INT ( val ) ) ; return <NUM_LIT> ; } else { rtx temp = subtargets ? gen_reg_rtx (


<s> unsigned A15SDOptimizer :: createRegSequence ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , DebugLoc DL , unsigned Reg1 , unsigned Reg2 ) { unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Out ) . addReg ( Reg1 ) . addImm ( <STR_LIT> ) . addReg ( Reg2 ) . addImm ( <STR_LIT> ) ; return Out


<s> return & InstrInfo . getRegisterInfo (


<s> if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo <


<s> void <ISA_LIT>SEInstrInfo :: expandERet ( MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator I ) const {


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand


<s> void <ISA_LIT>InstPrinter :: printImmScale ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << '#' << Scale * MI -> getOperand


<s> assert ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) ; int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = - <NUM_LIT> ; continue ; } APInt Index = cast < ConstantInt > ( COp ) -> getValue ( ) ; Index = Index . zextOrTrunc ( <NUM_LIT> ) . getLoBits ( <NUM_LIT> ) ; if ( IsPD ) Index . lshrInPlace ( <NUM_LIT> ) ; Index += APInt ( <NUM_LIT> , ( I / NumLaneElts ) * NumLaneElts ) ; Indexes [ I ] = Index . getZExtValue ( ) ; } auto V1 = II . getArgOperand ( <NUM_LIT> ) ; auto V2 = UndefValue :: get ( V1 ->


<s> static bool arm_return_in_msb ( tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype )

|| TREE_CODE ( valtype ) == COMPLEX_TYPE ) ) ;


<s> bool ToEFLAGS = DestReg == <STR_LIT> ; int Reg = FromEFLAGS ? DestReg : SrcReg ; bool is32 = <STR_LIT> . contains ( Reg ) ; bool is64 = <STR_LIT> . contains ( Reg ) ; if ( ( FromEFLAGS || ToEFLAGS ) && ( is32 || is64 ) ) { int Mov = is64 ? <STR_LIT> : <STR_LIT> ; int Push = is64 ? <STR_LIT> : <STR_LIT> ; int PushF = is64 ? <STR_LIT> : <STR_LIT> ; int Pop = is64 ? <STR_LIT> : <STR_LIT> ; int PopF = is64 ? <STR_LIT> : <STR_LIT> ; int AX = is64 ? <STR_LIT> : <STR_LIT> ; if ( ! Subtarget . hasLAHFSAHF ( ) ) { assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( FromEFLAGS ) { BuildMI ( MBB , MI , DL , get ( PushF ) ) ; BuildMI ( MBB , MI , DL , get ( Pop ) , DestReg ) ; } if ( ToEFLAGS ) { BuildMI ( MBB , MI , DL , get ( Push ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( PopF ) ) ; } return ; } bool AXDead = ( Reg == AX ) || ( MachineBasicBlock :: LQR_Dead == MBB . computeRegisterLiveness ( & getRegisterInfo ( ) , AX , MI ) ) ; if ( ! AXDead ) { BuildMI ( MBB , MI , DL , get ( Push ) ) . addReg ( AX , getKillRegState ( true ) ) ; } if ( FromEFLAGS ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( Mov ) , Reg ) . addReg ( AX ) ; } if ( ToEFLAGS ) { BuildMI ( MBB , MI , DL , get ( Mov ) , AX ) . addReg ( Reg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( INT8_MAX ) ; BuildMI ( MBB , MI , DL , get


<s> D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg


<s> unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; break ; } } if ( VT == <STR_LIT> && Opc == <STR_LIT> ) { unsigned SrcReg = fastEmitInst_i ( Opc , & <STR_LIT> , Imm ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM , this ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) : ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , JITInfo ( ) { initAsmInfo ( )


<s> return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine (


<s> Constant * ZeroVec = Constant :: getNullValue ( II . getType ( ) ) ; if ( isa < ConstantAggregateZero > ( Mask ) ) return IC . replaceInstUsesWith ( II , ZeroVec ) ; if ( Value * BoolMask = getBoolVecFromMask ( Mask ) ) { unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( II . getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ; CallInst * NewMaskedLoad = IC . Builder . CreateMaskedLoad ( PtrCast , Align


<s> bool hasFRInt3264 ( ) const { return


<s> if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS ) ) return <NUM_LIT> ; return


<s> unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegN = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegN ,


<s> SDValue MultLo = SUBCNode -> getOperand ( <NUM_LIT> ) ; SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDLoc DL ( SUBENode ) ; SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , SUBCNode -> getOperand ( <NUM_LIT> ) , SUBENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MSub = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( SUBCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoIdx = CurDAG -> getConstant


<s> Fragment * <ISA_LIT>GOT :: lookupGlobalEntry ( const ResolveInfo * pInfo ) { GotEntryKey key ; key . m_GOTPage = m_CurrentGOTPart ; key . m_pInfo = pInfo ; key . m_Addend = <NUM_LIT> ; GotEntryMapType :: iterator it = m_GotGlobalEntriesMap . find (


<s> unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> )

, RHS , N -> getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ; return false


<s> return ( __m128i ) __builtin_ia32_cvtpd2qq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_di ( )


<s> TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmTargetStreamer (

T , create<ISA_LIT>TargetAsmStreamer ) ;


<s> if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: CreateImm ( simm13 ) ) ; else { status = DecodeIntRegsRegisterClass ( MI , rs2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return


<s> unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ;


<s> bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) { moveToTop ( Reg , I ) ; assert ( StackTop > <NUM_LIT> && <STR_LIT> ) ; -- StackTop ; pushReg ( getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ) ; } else { duplicateToTop ( Reg , getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) , I ) ; } MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> RemoveOperand (


<s> static rtx nds32_expand_builtin ( tree exp , rtx target , rtx subtarget , machine_mode mode , int ignore ) { return nds32_expand_builtin_impl ( exp , target , subtarget ,


<s> return ( uint32x2_t ) __builtin_aarch64_addhnv2di ( ( int64x2_t ) __a , ( int64x2_t )


<s> unsigned <ISA_LIT>Subtarget :: getMispredictionPenalty ( ) const { if ( isCortexA8 ( ) ) return


<s> uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; uint32_t I = <NUM_LIT> ; I |= Sign << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ; I |= Mantissa <<


<s> } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) return <NUM_LIT> ; value = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( value == <NUM_LIT> ) { if ( currently_expanding_to_rtl ) { emit_insn ( gen_cmpgtsi_t ( force_reg ( SImode , CONST0_RTX ( SImode ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_mov_neg_si_t ( operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } emit_insn ( gen_ashrsi2_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } else if ( value >= <NUM_LIT> && value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashrsi2_16 ( wrk , operands [ <NUM_LIT> ] ) ) ; value -= <NUM_LIT> ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ] , wrk ) ; return <NUM_LIT> ; } else if ( value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_move_insn ( wrk , operands [ <NUM_LIT> ] ) ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ] , wrk ) ; return <NUM_LIT> ; } wrk = gen_reg_rtx ( Pmode ) ; emit_move_insn ( gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ; sprintf ( func , <STR_LIT>


<s> Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchRegW = STI -> getRegisterInfo ( ) -> getSubReg ( ScratchReg , <STR_LIT> ) ; Register TableReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register EntryReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int JTIdx = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; int Size = <ISA_LIT>FI -> getJumpTableEntrySize ( JTIdx ) ; auto Label = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getJumpTableEntryPCRelSymbol


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler ( ) const { return needsAggressiveScheduling (


<s> FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9


<s> printThumbAddrModeImm5SOperand ( MI , Op , STI , O


<s> if ( MF . getFrameInfo ( ) -> hasCalls (

) ) MRI . setPhysRegUsed ( <STR_LIT> ) ;


<s> O << <STR_LIT> ; return ; } if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val ) ; if ( Reg && Reg -> Writeable && Reg -> haveFeatures ( STI . getFeatureBits ( ) ) ) O << Reg -> Name ; else O << <STR_LIT>


<s> static unsigned HOST_WIDE_INT aarch64_shift_truncation_mask ( machine_mode mode ) { return ( aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p ( mode ) ) ? <NUM_LIT> : ( GET_MODE_BITSIZE ( mode


<s> if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= VT . getScalarSizeInBits ( ) / <NUM_LIT> ) { if ( Fast ) * Fast = true ; return true


<s> if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , <NUM_LIT> ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT> ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , <NUM_LIT> ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT> ) ) ) return false ; offset = XEXP ( addr , <NUM_LIT> ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref


<s> if ( VT . isFloatingPoint ( ) ) { if ( ScalarSize == <NUM_LIT> ) { Const = ConstantFP :: get ( C , APFloat ( APFloat :: IEEEsingle ( ) , Val ) ) ; } else { assert ( ScalarSize == <NUM_LIT> && <STR_LIT> ) ; Const = ConstantFP :: get ( C , APFloat ( APFloat :: IEEEdouble (


<s> case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor


<s> bool isCK803 ( ) const { return <ISA_LIT>ProcFamily == CK803


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( <NUM_LIT> ) { insn = NEXT_INSN (


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64_8 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64_16 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64_32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64_64 ) . Default ( - <NUM_LIT> ) ; } else


<s> unsigned <ISA_LIT>FastISel :: emitAddSub_rx ( bool UseAdd , MVT RetVT , unsigned LHSReg , bool LHSIsKill , unsigned RHSReg , bool RHSIsKill , <STR_LIT> ExtType , uint64_t ShiftImm , bool SetFlags , bool WantResult ) { assert ( LHSReg && RHSReg && <STR_LIT> ) ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = nullptr ; if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII .


<s> if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) <= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) > - <NUM_LIT> ) return <NUM_LIT> ; else if ( ( outer == IOR || outer == XOR || outer == AND ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( outer == AND ) { int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == INTVAL ( x ) || ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ; case TRUNCATE : return <NUM_LIT> ; case AND : case XOR : case IOR : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MEM : return ( COSTS_N_INSNS ( <NUM_LIT> ) + COSTS_N_INSNS ( <NUM_LIT> ) * ( ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) / UNITS_PER_WORD ) + ( ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) ? COSTS_N_INSNS ( <NUM_LIT> ) : <NUM_LIT> ) ) ; case IF_THEN_ELSE : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC ) return <NUM_LIT> ; return <NUM_LIT> ; case ZERO_EXTEND : switch ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) { case E_QImode


<s> HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow =


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! Subtarget . hasAnyFMA ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue FMAdd = Op0 , FMSub = Op1 ; if ( FMSub . getOpcode ( ) != <STR_LIT> ) std :: swap ( FMAdd , FMSub ) ; if ( FMAdd . getOpcode ( ) != <STR_LIT> || FMSub . getOpcode ( ) != <STR_LIT> || FMAdd . getOperand ( <NUM_LIT> ) != FMSub . getOperand ( <NUM_LIT> ) || ! FMAdd . hasOneUse ( ) || FMAdd . getOperand ( <NUM_LIT> ) != FMSub . getOperand ( <NUM_LIT> ) || ! FMSub . hasOneUse ( ) || FMAdd . getOperand ( <NUM_LIT> ) != FMSub . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; bool Op0Even ; if ( ! isAddSubOrSubAddMask ( Mask , Op0Even ) ) return SDValue ( ) ; SDLoc DL ( N ) ; bool IsSubAdd = Op0Even ? Op0 == FMAdd : Op1 == FMAdd ; unsigned Opcode = IsSubAdd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , VT , FMAdd . getOperand ( <NUM_LIT> ) , FMAdd . getOperand ( <NUM_LIT> ) , FMAdd


<s> return ( __m128i ) __builtin_ia32_cvtmask2d128


<s> if ( ! last_block ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ++ cfun -> machine -> state_num ) ; need_copy_state =


<s> bool isGR128 ( ) const { return isReg ( GR128Reg


<s> memcpy ( reg_alloc_order , arm_reg_alloc_order , sizeof ( reg_alloc_order ) ) ; if ( TARGET_THUMB ) memcpy ( reg_alloc_order , thumb_core_reg_alloc_order

, sizeof ( thumb_core_reg_alloc_order ) ) ;


<s> if ( DefRC -> hasSuperClassEq ( & <STR_LIT> ) && DefSubReg == <NUM_LIT> && SrcRC -> hasSuperClassEq ( & <STR_LIT> ) && SrcSubReg == <STR_LIT> ) return false ; return TargetRegisterInfo :: shouldRewriteCopySrc ( DefRC , DefSubReg , SrcRC , SrcSubReg


<s> EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT != Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ; SDValue OpRHS = Op . getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorNumElements ( ) == ( OpVT . getVectorNumElements ( ) * <NUM_LIT> ) && <STR_LIT> ) ; if ( OpVT . getVectorElementType ( ) . isInteger ( ) && OpVT . getVectorElementType ( ) != <STR_LIT> ) { EVT WideVT = OpVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; OpLHS = DAG . getNode ( <STR_LIT> , dl , WideVT , OpLHS ) ; OpRHS = DAG . getNode ( <STR_LIT> , dl , WideVT , OpRHS ) ; } if ( ( OpLHS -> getOpcode ( ) == <STR_LIT> ) && ( OpRHS -> getOpcode ( ) == <STR_LIT> ) && ( OpLHS -> getOperand ( <NUM_LIT> ) == OpRHS -> getOperand ( <NUM_LIT> ) ) ) { APInt ShiftAmount ; if ( DAG . isConstantIntSplat ( OpLHS -> getOperand ( <NUM_LIT>


<s> SDValue To ; unsigned DestIndex ; if ( FromV1 == <NUM_LIT> ) { From = V1 ; To = V2 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , FromV1Predicate ) - Mask . begin ( ) ; } else { assert ( std :: count_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) == <NUM_LIT> && <STR_LIT> <STR_LIT> <STR_LIT> ) ; From = V2 ; To = V1 ; DestIndex = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , FromV2Predicate ) - Mask . begin ( ) ; } unsigned SrcIndex = Mask [ DestIndex ] % <NUM_LIT> ; if ( MayFoldLoad ( From ) ) { SDValue NewLoad = NarrowVectorLoadToElement ( cast < LoadSDNode > ( From ) , SrcIndex , DAG ) ; if ( ! NewLoad . getNode ( ) ) return SDValue ( ) ; if ( EVT == <STR_LIT> ) { SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad ) ; SDValue InsertpsMask = DAG . getIntPtrConstant ( DestIndex << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , To , LoadScalarToVector , InsertpsMask ) ; } else { return DAG . getNode ( <STR_LIT> , dl , VT , To , NewLoad , DAG . getConstant ( DestIndex , <STR_LIT> ) ) ; } } SDValue InsertpsMask = DAG . getIntPtrConstant ( DestIndex << <NUM_LIT> | SrcIndex << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , To , From ,


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>RepoObjectWriter ( ) { return llvm :: make_unique <


<s> } static unsigned SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; updateValueMap ( I ,


<s> static SDValue LowerFGETSIGN ( SDValue Op , SelectionDAG & DAG ) { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant ( <NUM_LIT> , VT


<s> case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } if ( Subtarget . hasVLX ( ) ) if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return BitBlend ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool OptForSize = DAG . shouldOptForSize ( ) ; if ( ! OptForSize ) { if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; } MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask


<s> static bool doesIgnoreDataTypeSuffix ( StringRef Mnemonic


<s> if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SmallVector < SDValue , <NUM_LIT> > LoMaskElts , HiMaskElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { LoMaskElts . push_back ( DAG . getConstant ( LoLUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; HiMaskElts . push_back ( DAG . getConstant ( HiLUT [ i % <NUM_LIT> ] , DL ,


<s> OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias , * Mang ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; OutStreamer -> EmitBytes ( Flags ) ; } SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) { SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; } OutStreamer -> EmitRawText ( <STR_LIT> ) ; for ( auto function : profiler_function_labels ) { std :: string fname = function . substr ( <NUM_LIT> , <NUM_LIT> ) ; int extra = <NUM_LIT> - fname . length ( ) - <NUM_LIT> ; OutStreamer -> EmitRawText ( <STR_LIT> + fname + <STR_LIT> ) ; if ( extra > <NUM_LIT> ) OutStreamer -> EmitRawText ( <STR_LIT> + std :: to_string ( extra ) + <STR_LIT> ) ; } OutStreamer -> EmitRawText ( <STR_LIT> ) ; for ( auto label : getFunctionMagicLabels ( ) ) { OutStreamer -> EmitRawText ( <STR_LIT> + label ) ; } OutStreamer -> EmitRawText ( <STR_LIT> ) ; for ( auto label : getCallMagicLabels ( ) ) { OutStreamer -> EmitRawText ( <STR_LIT> +


<s> static MCDisassembler * create<ISA_LIT>Disassebler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) ,

Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( <NUM_LIT> ) ) ;


<s> return ( ! rs6000_darwin64_abi && typelist == <NUM_LIT> && TREE_CODE ( TREE_TYPE ( val ) ) == VECTOR_TYPE && ( funcdecl == NULL_TREE || ( TREE_CODE ( funcdecl ) == FUNCTION_DECL && DECL_BUILT_IN_CLASS ( funcdecl )

!= BUILT_IN_MD ) ) ) ? N_ ( <STR_LIT> ) : NULL ;


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , unsigned VarArgsFrameIndex ) { DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy


<s> StringRef getPassName ( ) const override { return


<s> return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable (


<s> case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , Subtarget ) ; case


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { unsigned Opcode = Node -> getOpcode ( ) ; DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return ; } switch ( Opcode ) { case <STR_LIT>


<s> case <STR_LIT> : return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> : case


<s> if ( SrcReg != <STR_LIT> && OpReg != <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , OpReg , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } unsigned Reg = SrcReg == <STR_LIT> ? OpReg : SrcReg ; TOut . emitRRI ( <STR_LIT> , DstReg , Reg , <NUM_LIT> , IDLoc , STI ) ; return


<s> return ( int_size_in_bytes ( type ) > ( TARGET_64BIT ? <NUM_LIT> :

<NUM_LIT> ) || int_size_in_bytes ( type ) <= <NUM_LIT> ) ;


<s> if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool IsNarrowLoad = isNarrowLoad ( MI -> getOpcode ( ) ) ; if ( ! IsNarrowLoad && ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsNarrowLoad || IsPromotableZeroStore ) { if ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else { if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } if ( ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] && ! ( MI -> mayLoad ( ) && UsedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) && ! mayAlias ( MI , MemInsns , TII ) ) { Flags . setMergeForward ( false ) ; return MBBI


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , &


<s> long long d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return d


<s> for ( unsigned l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) for ( unsigned i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) ShuffleMask . push_back


<s> if ( TLI . supportSwiftError ( ) ) { if ( const Argument * Arg = dyn_cast < Argument > ( SV ) ) { if ( Arg -> hasSwiftErrorAttr ( ) ) return false ; } if ( const AllocaInst * Alloca = dyn_cast < AllocaInst > ( SV ) ) { if ( Alloca -> isSwiftError ( ) ) return false ; } } Address Addr ; if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr , I -> getType ( ) ) ) return false ; bool WantZExt = true ; MVT RetVT = VT ; const Value * IntExtVal = nullptr ; if ( I -> hasOneUse ( ) ) { if ( const auto * ZE = dyn_cast < ZExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( ZE -> getType ( ) , RetVT ) ) IntExtVal = ZE ; else RetVT = VT ; } else if ( const auto * SE = dyn_cast < SExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( SE -> getType ( ) , RetVT ) ) IntExtVal = SE ; else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { unsigned Reg = lookUpRegForValue ( IntExtVal


<s> const MCOperand & dispReg = MI -> getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand & dispImm = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( dispReg . getReg ( ) ) { O << '+' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; } if ( dispImm . isImm ( ) ) { if ( dispImm . getImm ( ) ) { O << '+' ; printOperand ( MI , OpNo +


<s> uint64_t encoding = <STR_LIT> ( Val , sizeof ( T ) * <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm (


<s> ASSERT_SORTED ( PopTable ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , array_lengthof ( PopTable ) , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ; }


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( * iter ) &&

KERNEL_REG_P ( REGNO ( * iter ) ) ) return true ;


<s> return TargetTriple . isWindowsCygwinEnvironment (


<s> return ( uint32x2_t ) __builtin_neon_vqrshrnu_nv2di ( ( int64x2_t ) __a ,


<s> static <ISA_LIT>Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf =


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm8S4 ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; assert ( ! RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; int TailCallReturnAddrDelta = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) ; assert ( ! ( TailCallReturnAddrDelta < <NUM_LIT> )


<s> if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) { Feat00Flags |= <NUM_LIT> ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } OutStreamer -> emitSyntaxDirective ( ) ; bool is16 = TT . getEnvironment ( ) == Triple :: CODE16 ; if ( M . getModuleInlineAsm ( ) . empty ( ) && is16 ) OutStreamer ->


<s> if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = <NUM_LIT> ; return FoldMI ; } return


<s> Value * <ISA_LIT>TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getGlobalVariable ( <STR_LIT> ) ; } return TargetLowering :: getSDagStackGuard


<s> else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal , dl ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegPair ( unsigned RegNo , SMLoc S , SMLoc E ,


<s> Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII , this ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; Register PredReg = ( PIdx == - <NUM_LIT> ) ? Register ( ) : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; const TargetRegisterClass * RegClass = TII . getRegClass ( MCID , FIOperandNum , this , * MI . getParent ( ) -> getParent ( ) ) ; if ( Offset == <NUM_LIT> && ( Register :: isVirtualRegister ( FrameReg ) || RegClass -> contains ( FrameReg ) ) ) MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( RegClass ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MMULFX_W ( ( v4hi )


<s> void addGPRMM16AsmRegZeroOperands ( MCInst & Inst , unsigned N


<s> RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg


<s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock &


<s> void setGPRCalleeSavedArea2Size ( unsigned s


<s> getContext ( ) . reportError ( L , <STR_LIT> ) ; return true ; } FPOInstruction Inst ; Inst . Label = emitFPOLabel ( ) ; Inst . Op = FPOInstruction :: StackAlign ; Inst . RegOrOffset = Align ; CurFPOData -> Instructions . push_back


<s> MachineInstrBuilder PicADD = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NotThumb ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( PC_ID ) . addImm (


<s> return __builtin_mve_vcvttq_m_f32_f16v4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return performAddSubLongCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI


<s> if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalSizeLoaded ; else Shamt = ( RegSize - ( TotalSizeLoaded + LoadSize ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; Offset += LoadSize ; TotalSizeLoaded += LoadSize ; Alignment = std :: min ( Alignment , LoadSize ) ; } unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair (


<s> if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) .


<s> return false ; } if ( FirstCond == <NUM_LIT> && ITCounter != <NUM_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } ITState =


<s> assert ( HasSVE && <STR_LIT> ) ; return


<s> if ( ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> ) return false ; if ( Subtarget -> useSVEForFixedLengthVectors ( ) && ( VecSize % Subtarget -> getMinSVEVectorSizeInBits ( ) == <NUM_LIT> || ( VecSize < Subtarget -> getMinSVEVectorSizeInBits ( ) && isPowerOf2_32 ( NumElements ) && VecSize > <NUM_LIT> ) ) ) { UseScalable = true ; return


<s> if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits


<s> if ( hasLEAOffset ( Offset ) ) { if ( OptIncDec && Offset . isImm ( ) && ( Offset . getImm ( ) == <NUM_LIT> || Offset . getImm ( ) == - <NUM_LIT> ) ) { unsigned NewOpc = getINCDECFromLEA ( MI . getOpcode ( ) , Offset . getImm ( ) == <NUM_LIT> ) ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) , DestReg ) . addReg ( DestReg ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } else { unsigned NewOpc = getADDriFromLEA ( MI . getOpcode ( ) , Offset ) ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) , DestReg ) . addReg ( DestReg ) . add ( Offset ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } } MBB . erase ( I ) ; I = NewMI ; return ; } assert ( DestReg != BaseReg && <STR_LIT> ) ; assert ( IsInefficientBase && <STR_LIT> ) ; if ( LEAOpcode == <STR_LIT> ) return ; if ( IsScale1 && ! hasLEAOffset ( Offset ) ) { bool BIK = Base . isKill ( ) && BaseReg != IndexReg ; TII -> copyPhysReg ( MBB , MI , MI . getDebugLoc ( ) , DestReg , BaseReg , BIK ) ; LLVM_DEBUG ( MI . getPrevNode ( ) -> dump ( ) ; ) ; unsigned NewOpc = getADDrrFromLEA ( MI . getOpcode ( ) ) ; NewMI = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) , DestReg ) . addReg ( DestReg ) . add ( Index ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; return ; } NewMI = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( LEAOpcode ) ) . add ( Dest ) . addReg ( <NUM_LIT> ) . add ( Scale ) . add ( Index ) . add ( Offset ) . add ( Segment ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; unsigned NewOpc = getADDrrFromLEA ( MI . getOpcode ( ) ) ; NewMI = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) , DestReg ) . addReg ( DestReg ) . add ( Base ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; MBB . erase ( I )


<s> if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( ! isThumb ) { emitSPUpdate ( MBB , MBBI , - GPRCS1Size , <STR_LIT> , <NUM_LIT> , isThumb , TII , * this , dl ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , STI ) ; } else if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( isThumb ? <STR_LIT> : <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; if ( ! isThumb ) AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( ! isThumb ) { emitSPUpdate ( MBB , MBBI , - GPRCS2Size , <STR_LIT> , <NUM_LIT> , false , TII , * this , dl ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( MBB , MBBI , - DPRCSSize , <STR_LIT> , <NUM_LIT> , false , TII , * this , dl ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset +


<s> Reserved . set ( getBaseRegister ( ) ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { static const uint16_t GPR64 [ ]


<s> return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units


<s> if ( mi . definesRegister ( <STR_LIT> ) ) return false ; } for ( MachineBasicBlock * Succ : BB -> successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) return true ; return


<s> I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; return true ; } case TargetOpcode :: G_ADD : { Register X = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( X ) ; if ( Ty . isVector ( ) || Ty . getSizeInBits ( ) != <NUM_LIT> ) return false ; Register CmpReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Cmp = getOpcodeDef ( TargetOpcode :: G_ICMP , CmpReg , MRI ) ; if ( ! Cmp ) { std :: swap ( X , CmpReg ) ; Cmp = getOpcodeDef ( TargetOpcode :: G_ICMP , CmpReg , MRI ) ; if ( ! Cmp ) return false ; } auto Pred = static_cast < CmpInst :: Predicate > ( Cmp -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; emitIntegerCompare ( Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> getOperand ( <NUM_LIT> ) , MIB ) ; emitCSetForICMP ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , Pred , MIB , X ) ; I . eraseFromParent ( ) ; return true ; } case TargetOpcode :: G_OR : { Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Dst ) ; if ( ! Ty . isScalar ( ) ) return false ; unsigned Size = Ty . getSizeInBits ( ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; Register ShiftSrc ; int64_t ShiftImm ; Register MaskSrc ; int64_t MaskImm ; if ( ! mi_match ( Dst , MRI , m_GOr ( m_OneNonDBGUse ( m_GShl ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) ) , m_OneNonDBGUse ( m_GAnd ( m_Reg ( MaskSrc ) , m_ICst ( MaskImm ) ) ) ) ) ) return false ; if ( ShiftImm > Size || ( ( <NUM_LIT> << ShiftImm ) - <NUM_LIT> ) != uint64_t ( MaskImm ) ) return false ; int64_t Immr = Size - ShiftImm ; int64_t Imms = Size


<s> } Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg )

. addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; unsigned SABIAlignment = TD . getABITypeAlignment ( S -> getValueOperand ( ) -> getType


<s> Register Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return BB


<s> tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , <NUM_LIT> ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo


<s> unsigned stackAlignment ( ) const { return has<ISA_LIT>64 ( ) ?


<s> const AsmToken & Tok = Parser . getTok ( ) ; int64_t OrigDispVal , DotDispVal ; if ( const MCConstantExpr * OrigDisp = dyn_cast < MCConstantExpr > ( Disp ) ) OrigDispVal = OrigDisp -> getValue ( ) ; else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { unsigned DotDisp ; std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , DotDisp ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; DotDispVal = DotDisp


<s> EmitAlignment ( <NUM_LIT> , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( ( TAI -> hasDotTypeDotSizeDirective ( ) ) && Subtarget -> isLinux ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; emitFrameDirective ( MF ) ; printSavedRegsBitmask ( MF


<s> if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) ->

getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_RegMask ;


<s> unsigned getBaseRegister ( ) const { return


<s> LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = <NUM_LIT> ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= <NUM_LIT> && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32

( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> void addMemNoOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum )


<s> if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget -> hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerVectorShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue Unpack = lowerVectorShuffleAsUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget -> hasSSSE3 ( ) ) { bool V1InUse , V2InUse ; return lowerVectorShuffleAsPSHUFB ( DL , <STR_LIT> , V1 , V2 , Mask , DAG , V1InUse ,


<s> return ( __m256i ) __builtin_ia32_movdqa64load256_mask ( ( __v4di * ) __P , ( __v4di ) __W , (


<s> else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc

:: PIC_ ? CodeModel :: Small : CodeModel :: Medium ;


<s> lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const

<ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ;


<s> AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage (


<s> if ( computed != <NUM_LIT> ) { static bool warned ; if ( ! warned && warn_psabi ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , computed


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false


<s> unsigned <ISA_LIT>FastISel :: constrainOperandRegClass ( const MCInstrDesc & II , unsigned Op , unsigned OpNum ) { if ( TargetRegisterInfo :: isVirtualRegister ( Op ) ) { const TargetRegisterClass * RegClass = TII . getRegClass ( II , OpNum , & TRI , * FuncInfo . MF ) ; if ( ! MRI . constrainRegClass ( Op , RegClass )


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue ,


<s> if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New . getNode ( ) ; } if ( ! N -> isMachineOpcode ( ) ) SelectCode ( N ) ; return true ; } } unsigned Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) && RISBG . Start >= <NUM_LIT> && RISBG . End >= RISBG . Start && ( ( RISBG . Start + RISBG . Rotate ) & <NUM_LIT> ) >= <NUM_LIT> && ( ( RISBG . End + RISBG . Rotate ) & <NUM_LIT> ) >= ( ( RISBG . Start + RISBG . Rotate ) & <NUM_LIT> ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( DL , OpcodeVT ) , convertTo ( DL , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , DL , <STR_LIT> ) } ; SDValue New = convertTo ( DL , VT , SDValue ( CurDAG -> getMachineNode ( Opcode , DL , OpcodeVT , Ops ) ,


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm


<s> if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ; } return true


<s> MCSymbol * Label = S . emitCFILabel ( ) ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ; CurFrame -> EpilogMap [ CurrentEpilog ] .


<s> emitConstPoolAddress ( unsigned CPI , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI ,


<s> MCA . getOrCreateSymbolData ( * GP_Disp ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode (


<s> } if ( SDValue V = combineParity ( N , DAG , Subtarget ) ) return V ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , true , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements (


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return


<s> AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > (


<s> r = REAL_VALUE_ATOF ( <STR_LIT> , DFmode ) ; value_fp0 = r ; fp_consts_inited =


<s> if ( ! isShiftExtend ( ) ) return false ; if ( getShiftExtendAmount ( ) >


<s> Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return getDirectBrEncoding ( MI , OpNo


<s> auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; MCInst Noop ; Subtarget -> getInstrInfo ( ) -> getNoopForElfTarget ( Noop ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) { OutStreamer -> EmitInstruction ( Noop , getSubtargetInfo ( ) ) ; } OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , Kind


<s> TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; Type * ResultTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / Factor ) ; unsigned NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; unsigned NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; unsigned NumOfSources =


<s> if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; Register InstrSrcReg = getLoadStoreRegOp ( * MBBI ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( * MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( * MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub =


<s> return ( uint64x1_t ) __builtin_neon_vpaddluv2si ( ( int32x2_t )


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; StringRef Identifier = Token . getIdentifier ( ) ; OperandMatchResultTy ResTy = MatchAnyRegisterNameWithoutDollar ( Operands , Identifier , S ) ; return ResTy ; } else if ( Token . is ( AsmToken :: Integer ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo

( ) , S , Token . getLoc ( ) , * this ) ) ;


<s> emit_move_insn ( scratch , mem ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_addsi3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode , <NUM_LIT> , align_4_label ) ; if ( TARGET_CMOVE ) { rtx reg = gen_reg_rtx ( SImode ) ; rtx reg2 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( reg , tmpreg ) ; emit_insn ( gen_lshrsi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_IF_THEN_ELSE ( SImode , tmp , reg , tmpreg ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , reg2 , gen_rtx_PLUS ( Pmode , out , const2_rtx ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_IF_THEN_ELSE ( Pmode , tmp , reg2 , out ) ) ) ; } else { rtx end_2_label = gen_label_rtx ( ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_NE ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , end_2_label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = end_2_label ; emit_insn ( gen_lshrsi3 ( tmpreg , tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( out , out , const2_rtx ) ) ; else emit_insn ( gen_addsi3 ( out , out , const2_rtx ) ) ; emit_label ( end_2_label ) ; } tmpreg = gen_lowpart ( QImode , tmpreg ) ; emit_insn ( gen_addqi3_cc ( tmpreg , tmpreg , tmpreg ) ) ; cmp = gen_rtx_LTU ( Pmode , gen_rtx_REG ( CCmode , <NUM_LIT> ) ,


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF )


<s> <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( SSFISize , SSFISize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Result , StackSlot , DAG . getValueType ( Op . getValueType ( ) ) , InFlag } ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , SSFISize , SSFISize ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , Op . getValueType ( ) , MMO ) ; Result = DAG . getLoad ( Op . getValueType ( ) , DL , Chain , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc


<s> if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc =


<s> unsigned Opc = LHS . getOpcode ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc


<s> <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , false , Op0 , Op1 , DAG ) ; assert ( CondCode != <STR_LIT> &&


<s> ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs ; i != ie ; ++ i ) { <STR_LIT> Flags = CLI . OutFlags [ i ] ; if ( Flags . isInReg ( ) || Flags . isSRet ( ) || Flags . isNest ( ) || Flags . isByVal ( ) ) return false ; Value * ArgValue = CLI . OutVals [ i ] ; Type * ArgTy = ArgValue -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) || ArgVT == <STR_LIT> ) return false ; Register Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder


<s> if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == <STR_LIT> && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> ) return false ; if ( Opc == <STR_LIT> && VT == <STR_LIT> ) return false ; if ( VT == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false


<s> static bool DisassembleNVecMulScalarFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded ,


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X (


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > (


<s> if ( ! selected_cpu ) { if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , aarch64_cpu_string , aarch64_arch_string ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( aarch64_enable_bti == <NUM_LIT> ) { aarch64_enable_bti = <NUM_LIT> ; aarch64_enable_bti = <NUM_LIT> ; } if ( ! TARGET_ILP32 && accepted_branch_protection_string == NULL ) { aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF ; aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE ; } if ( TARGET_ILP32 ) error ( <STR_LIT> ) ; aarch64_sve_vg = aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32 ) sorry ( <STR_LIT> ) ; if ( ( aarch64_cpu_string && valid_cpu ) || ( aarch64_tune_string && valid_tune ) ) gcc_assert ( explicit_tune_core != aarch64_none ) ; if ( ( aarch64_cpu_string && valid_cpu ) || ( aarch64_arch_string && valid_arch ) ) gcc_assert ( explicit_arch != aarch64_no_arch ) ; if ( aarch64_track_speculation ) flag_shrink_wrap = <NUM_LIT> ; aarch64_override_options_internal ( & global_options ) ; target_option_default_node = target_option_current_node = build_target_option_node ( & global_options ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder


<s> static std :: string computeDataLayout ( const Triple & TT ) { return <STR_LIT> <STR_LIT> <STR_LIT>


<s> return ( int64x1_t ) __builtin_neon_vdup_ndi ( ( __builtin_neon_di


<s> unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . addOperand ( MO ) ; } MIB . addReg ( DstReg , RegState :: ImplicitDefine | getDeadRegState ( DstIsDead )


<s> return ( int16x4_t ) __builtin_aarch64_sqshrn_nv4si ( __a ,


<s> } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) || MFI . getStackSize ( ) > <NUM_LIT> || MFI . getNumObjects ( ) > <NUM_LIT> ) return UnknownCallOutlineType ; return outliner :: InstrType :: Legal ; } if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & getRegisterInfo ( ) ) || MI . modifiesRegister

( <STR_LIT> , & getRegisterInfo ( ) ) ) return outliner :: InstrType :: Illegal ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LDCleanupPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> void addVectorRegLoOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> return ( int32x2_t ) __builtin_neon_vqrshlsv2si (


<s> TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass ( create<ISA_LIT>Os16Pass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloatPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) { addPass ( createCheriLoopPointerDecanonicalize ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; addPass ( createCheriRangeChecker ( ) ) ; addPass ( createCheriBoundAllocasPass (


<s> EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = Has<ISA_LIT>64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return ResNode ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , ValTy ,


<s> const char * name ; while ( <NUM_LIT> ) { switch ( GET_CODE ( x ) ) { case MEM : case CONST : x = XEXP ( x , <NUM_LIT> ) ; break ; case UNSPEC : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; x = XEXP ( x , <NUM_LIT> ) ; break ; default : goto done ; } } done : if ( GET_CODE ( x ) != SYMBOL_REF )


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info ,


<s> unsigned <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands ) { if ( U -> getType ( ) -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue (


<s> bool isMem ( ) const override { if ( Kind != k_Memory ) return false ; if ( Memory . BaseRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . OffsetRegNum ) ) return false ; return true


<s> if ( ! FromVT . isInteger ( ) || ! ToVT . isInteger ( ) ) return false ; unsigned FromBits = FromVT . getFixedSizeInBits


, ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __A , _MM_FROUND_CUR_DIRECTION ) ;