<s> BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; unsigned MaxAlign = MF . getFrameInfo ( ) . getMaxAlignment ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! isThumb ) MIB . add ( condCodeOp ( ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs )


<s> <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int


<s> return ( Reg && ( Read ? Reg -> Readable : Reg -> Writeable )

&& Reg -> haveFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , ret ) ) ; return gen_rtx_fmt_ee ( code , mode , cc_reg , const0_rtx


<s> if ( size == <NUM_LIT> ) { switch ( code ) { case ASHIFT : sprintf ( r , <STR_LIT> , r1 , r0 , r0 ) ; break ; case ASHIFTRT : sprintf ( r , <STR_LIT> , r0 , r1 , r1 ) ; break ; case LSHIFTRT : sprintf ( r , <STR_LIT> , r0 , r1 , r1 ) ; break ; default : gcc_unreachable ( ) ; } return r ; } if ( size > <NUM_LIT> ) { switch ( code ) { case ASHIFT : sprintf ( r , <STR_LIT> , r1 , r0 , r0 , r1 , ( int ) size - <NUM_LIT> ) ; break ; case ASHIFTRT : sprintf ( r , <STR_LIT> , r0 , r1 , r1 , r0 , ( int ) size - <NUM_LIT> ) ; break ; case LSHIFTRT : sprintf ( r , <STR_LIT> , r0 , r1 , r1 , r0 , ( int ) size - <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } return r ; } rt = reg_names [ REGNO ( temp ) ] ; switch ( code ) { case ASHIFT : sprintf ( r , <STR_LIT> , rt , r0 , r0 , ( int ) size , r1 , ( int ) size , rt , ( int ) ( <NUM_LIT> - size ) , r1 , rt ) ; break ; case ASHIFTRT


<s> if ( ! BVN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , true ) || SplatBitSize > <NUM_LIT> ) return SDValue ( ) ; unsigned SplatBits = APSplatBits . getZExtValue ( ) ; unsigned SplatUndef = APSplatUndef . getZExtValue ( ) ; unsigned SplatSize = SplatBitSize / <NUM_LIT> ; if ( SplatBits == <NUM_LIT> ) { if ( Op . getValueType ( ) != <STR_LIT> || HasAnyUndefs ) { SDValue Z = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Z = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Z , Z , Z , Z ) ; Op = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Z ) ; } return Op ; } int32_t SextVal = ( int32_t ( SplatBits << ( <NUM_LIT> - SplatBitSize ) ) >> ( <NUM_LIT> - SplatBitSize ) ) ; if ( SextVal >= - <NUM_LIT> && SextVal <= <NUM_LIT> ) return BuildSplatI ( SextVal , SplatSize , Op . getValueType ( ) , DAG , dl ) ; if ( SextVal >= - <NUM_LIT> && SextVal <= <NUM_LIT> && ( SextVal & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Res = BuildSplatI ( SextVal >> <NUM_LIT> , SplatSize , <STR_LIT> , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , Res . getValueType ( ) , Res , Res ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SplatSize == <NUM_LIT> && SplatBits == ( <NUM_LIT> & ~ SplatUndef ) ) { SDValue OnesV = BuildSplatI ( - <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue Res = BuildIntrinsicOp ( <STR_LIT> , OnesV , OnesV , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , OnesV ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } static const signed char SplatCsts [ ] = { - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( unsigned idx = <NUM_LIT> ; idx < array_lengthof ( SplatCsts ) ; ++ idx ) { int i = SplatCsts [ idx ] ; unsigned TypeShiftAmt = i & ( SplatBitSize - <NUM_LIT> ) ; if ( SextVal == ( i << ( int ) TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ]


<s> if ( get_eit_entry ( ucbp , vrs -> core . r [ R_PC ] ) != _URC_OK ) abort ( ) ; UCB_SAVED_CALLSITE_ADDR ( ucbp ) = vrs -> core . r [ R_PC ] ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( _US_UNWIND_FRAME_STARTING , ucbp , ( _Unwind_Context * ) vrs ) ; } while ( pr_result == _URC_CONTINUE_UNWIND ) ; if ( pr_result != _URC_INSTALL_CONTEXT ) abort ( ) ; restore_core_regs ( & vrs ->


<s> unsigned int __i = ( unsigned short ) __w << <NUM_LIT> | ( unsigned short ) __w ; return _mm_set1_pi32 (


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT>

) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> return In64BitMode && TargetTriple .


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx cr = gen_rtx_REG ( SImode , CR0_REGNO + i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , cr , cfa_restores ) ; } } else if ( info -> cr_save_p ) cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL ,


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , MII ( mii ) , InstInfo ( nullptr ) , Code16GCC ( false ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( )


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( )


<s> if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true


<s> return __builtin_mve_veorq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) ,


<s> if ( ! isMemory ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . ShiftType != <STR_LIT> ||

Memory . ShiftImm != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;


<s> RegisterTarget < Triple :: f2003f > X ( getThe<ISA_LIT>Target ( ) ,


<s> bool isTargetMachO ( const MCSubtargetInfo & STI ) const { const Triple & TT = STI . getTargetTriple


<s> const DataLayout & DL = CurDAG -> getDataLayout ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; if ( FI == <NUM_LIT> || MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } return false ; } if ( MemVT == EVT (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= <NUM_LIT> ) add_int_reg_note (

i , REG_BR_PROB , split_branch_probability ) ;


<s> if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( Hi ) ; } return ResultReg


<s> } unsigned Opc = TailCall . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opc ) ) ; MIB -> addOperand ( TailCall . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB -> addOperand ( BranchCond [ <NUM_LIT> ] ) ; MIB . copyImplicitOps ( TailCall ) ; LivePhysRegs LiveRegs ( & getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MIB , Clobbers ) ; for ( const auto & C : Clobbers ) { MIB . addReg ( C . first , RegState :: Implicit ) ; MIB . addReg ( C . first , RegState :: Implicit | RegState :: Define ) ; } I -> eraseFromParent ( )


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( Modifier && <STR_LIT> ) ; unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( StringRef ( Modifier ) == <STR_LIT> ) { switch ( ( <STR_LIT> ) Code ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT>


<s> void <ISA_LIT>FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNo ) . getImm ( ) ; O << <ISA_LIT>CCToString (


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> rtx rawaddr ; if ( op0 == const0_rtx ) rawaddr = op1 ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; rawaddr = gen_rtx_PLUS ( Pmode , op1 , op0 ) ; } addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , addr ) ; emit_insn ( gen_rtx_SET ( target , addr ) ) ; } else { if ( op0 == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op1 ) ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode ,


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . second ) return R ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


<s> static SDValue PerformVSELECTCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue XOR = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT Type = N -> getValueType ( <NUM_LIT>


<s> static Optional < unsigned > getVVPOpcode ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : \ return


<s> if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU


<s> if ( ! hasBZHI ( Subtarget , VT ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue N = Node -> getOperand ( i ) ; LoadSDNode * Ld = dyn_cast < LoadSDNode > ( N . getNode ( ) ) ; if ( ! Ld ) return SDValue ( ) ; const Value * MemOp = Ld -> getMemOperand ( ) -> getValue ( ) ; if ( ! MemOp ) return SDValue ( ) ; if ( const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( MemOp ) ) { if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( GEP -> getOperand ( <NUM_LIT> ) ) ) { if ( GV -> isConstant ( ) && GV -> hasDefinitiveInitializer ( ) ) { Constant * Init = GV -> getInitializer ( ) ; Type * Ty = Init -> getType ( ) ; if ( ! isa < ConstantDataArray > ( Init ) || ! Ty -> getArrayElementType ( ) -> isIntegerTy ( ) || Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) != VT . getSizeInBits ( ) || Ty -> getArrayNumElements ( ) > Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) ) continue ; uint64_t ArrayElementCount = Init -> getType ( ) -> getArrayNumElements ( ) ; bool ConstantsMatch = true ; for ( uint64_t j = <NUM_LIT> ; j < ArrayElementCount


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym


<s> switch ( GET_MODE ( src ) ) { case V4SFmode : if ( i == <NUM_LIT> ) tem = gen_sse_movhlps ( dest , src , src ) ; else tem = gen_sse_shufps_v4sf ( dest , src , src , const1_rtx , const1_rtx , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ; break ; case V2DFmode : tem = gen_vec_interleave_highv2df ( dest , src , src ) ; break ; case V16QImode : case V8HImode : case V4SImode : case V2DImode : d = gen_reg_rtx ( V1TImode ) ; tem = gen_sse2_lshrv1ti3 ( d , gen_lowpart ( V1TImode , src ) , GEN_INT ( i / <NUM_LIT> ) ) ; break ; case V8SFmode : if ( i == <NUM_LIT> ) tem = gen_avx_vperm2f128v8sf3 ( dest , src , src , const1_rtx ) ; else tem = gen_avx_shufps256 ( dest , src , src , GEN_INT ( i == <NUM_LIT> ? <NUM_LIT> + ( <NUM_LIT> << <NUM_LIT> ) : <NUM_LIT> ) ) ; break ; case V4DFmode : if ( i == <NUM_LIT> ) tem = gen_avx_vperm2f128v4df3 ( dest , src , src , const1_rtx ) ; else tem = gen_avx_shufpd256 ( dest , src , src , const1_rtx ) ; break ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( i == <NUM_LIT> ) { if ( GET_MODE ( dest ) != V4DImode ) d = gen_reg_rtx ( V4DImode ) ; tem = gen_avx2_permv2ti ( d , gen_lowpart ( V4DImode , src ) , gen_lowpart


<s> LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Alignment >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext (

) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) ) ) {


<s> FunctionPass * createCheriRangeChecker ( void ) { return new CheriRangeChecker


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo ( )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> void addMemNoOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory .


<s> void <ISA_LIT>FrameLowering :: replaceFPWithRealFP ( MachineFunction & MF ) const { bool is31 = needsFP ( MF ) ; unsigned FPReg = is31 ? <STR_LIT> : <STR_LIT> ; unsigned FP8Reg = is31 ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FP8Reg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand


<s> return __builtin_ia32_vcvttph2uqq128_mask ( __B , _mm_setzero_si128 ( ) ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( PostIdxReg . RegNum


<s> return createWinCOFFObjectWriter ( std :: move ( MOTW )


<s> return ( uint16x4_t ) __builtin_aarch64_uminpv4hi ( ( int16x4_t )


<s> if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V )


<s> Flags . setNoUnsignedWrap ( true ) ; FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset , Flags ) , MachinePointerInfo ( ) ) ; } else { unsigned LRReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) ,


<s> if ( ! LHSReg ) return <NUM_LIT> ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = C -> getZExtValue ( ) ; ResultReg = emitLogicalOp_ri ( ISDOpc , RetVT , LHSReg , Imm ) ; } if ( ResultReg ) return ResultReg ; if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < ShlOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; MVT VT = std :: max ( <STR_LIT> , RetVT . SimpleTy ) ; ResultReg = fastEmit_rr ( VT , VT , ISDOpc , LHSReg , RHSReg ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ; } return ResultReg


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; uint64_t Value = CE -> getValue (


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI = <NUM_LIT> ) : MCELFObjectTargetWriter ( false , OSABI


<s> void addAlignedMemory64Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst ,


<s> ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; int64_t IntVal ; if ( MatchRegisterName ( RegNo , IntVal ) )


<s> switch ( GET_CODE ( op ) ) { case PLUS : return <STR_LIT> ; case MINUS : return shift_first_arg ? <STR_LIT> :


<s> return ( __m128i ) __builtin_ia32_pcmpeqb128 ( ( __v16qi ) __A , (


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT>

Flags , SelectionDAG & DAG , const SDLoc & dl ) {


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg (


<s> if ( Mnemonic != <STR_LIT> ) return MatchOperand_ParseFail ; if ( parseOptionalToken ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Integer ) ) { const MCExpr * ImmVal ; SMLoc ExprLoc = getLoc ( ) ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Value = MCE -> getValue ( ) ; if ( Value != <NUM_LIT> && Value != <NUM_LIT> && Value != <NUM_LIT> && Value != <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Value ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , DB -> Name , ExprLoc , getContext ( ) , true ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> )


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value


<s> Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT>


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM || GET_CODE ( sum = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != PLUS || GET_CODE ( reg = XEXP ( sum , <NUM_LIT> ) ) != REG || GET_CODE ( offset = XEXP ( sum , <NUM_LIT> ) ) != CONST_INT || ( ( INTVAL ( offset ) < <NUM_LIT> ) && ( INTVAL ( offset ) > - <NUM_LIT> ) ) ) return <STR_LIT> ; output_asm_insn ( <STR_LIT> , & reg ) ; wcgr = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT>


<s> Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL ,


<s> static SDValue combineShiftRightAlgebraic ( SDNode * N , SelectionDAG & DAG ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( ! VT . isInteger ( ) || VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand (


<s> SDNode * VLD = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( VLD -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned NumVecs = <NUM_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned IntNo = cast < ConstantSDNode > ( VLD -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else { return false ; } unsigned VLDLaneNo = cast < ConstantSDNode > ( VLD -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumVecs + <NUM_LIT> ) ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget -> is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && ! LABEL_P ( worker ) && ! JUMP_P ( worker ) ) ; } while ( NOTE_P ( worker ) || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wpat1 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , XEXP ( XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , lab , XEXP ( wpat1 , <NUM_LIT> ) ) ) ; INSN_CODE ( worker ) = - <NUM_LIT> ; target = XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , <NUM_LIT> , <NUM_LIT> ) ; base = gen_rtx_LABEL_REF ( Pmode , lab ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , target , base ) , UNSPEC_SYMOFF ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova ) = -


<s> FunctionPass * llvm :: createAnnotationsInferencePass ( ) { return new AnnotationsInference (


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned ,


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt


<s> SDValue V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Idx128 = Op . getOperand ( <NUM_LIT> ) ; auto * CIdx = dyn_cast < ConstantSDNode > ( Idx128 ) ; if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SDValue SV = DAG . getNode ( <STR_LIT>


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , <NUM_LIT> > & cil ) { return <STR_LIT> ( mf , mmo , dw , vm , bm ,


<s> void addRegOperands ( MCInst & Inst ,


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512

) return CSR_64_Intel_OCL_BI_AVX512_RegMask ;


<s> __builtin_ia32_pmovqw512mem_mask ( ( __v8hi * ) __P , (


<s> tree vectype = abi_vector_types [ type ] ; tree id = get_identifier ( vector_types [ type ] . acle_name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls .


<s> if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI

. getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ;


<s> OperandMatchResultTy parseFP128 ( SmallVectorImpl < MCParsedAsmOperand


<s> FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( new <ISA_LIT>CallLowering ( * I


<s> unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Dst , Src ) ) return expandCopyACC ( MBB , I , Dst ,


<s> return ( __m256i ) __builtin_ia32_vgf2p8affineqb_v32qi ( ( __v32qi ) __A , ( __v32qi )


<s> if ( ! funcInfo . MF -> getTarget ( ) . Options . EnableFastISel ) return TargetLowering :: createFastISel


<s> return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList ) : ( Subtarget . hasAltivec ( ) ?


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSelect ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineInstr * CascadedCMOV = nullptr ; MachineInstr * LastCMOV = MI ; <STR_LIT> CC = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock :: iterator NextMIIt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; if ( isCMOVPseudo ( MI ) ) { while ( NextMIIt != BB -> end ( ) && isCMOVPseudo ( NextMIIt ) && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CC || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) ) { LastCMOV = & * NextMIIt ; ++ NextMIIt ; } } if ( LastCMOV == MI && NextMIIt != BB -> end ( ) && NextMIIt -> getOpcode ( ) == MI -> getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { CascadedCMOV = & * NextMIIt ; } MachineBasicBlock * jcc1MBB = nullptr ; if ( CascadedCMOV ) { jcc1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , jcc1MBB ) ; jcc1MBB -> addLiveIn ( <STR_LIT> ) ; } MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; MachineInstr * LastEFLAGSUser = CascadedCMOV ? CascadedCMOV :


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand (


<s> const unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPEAlign ) ; unsigned NextBlockOffset ; Align NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockAlignment = NextBlock -> getAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size ; if ( CPEEnd > NextBlockOffset ) { Growth = CPEEnd - NextBlockOffset ; Growth += offsetToAlignment ( CPEEnd , NextBlockAlignment ) ; if ( CPEOffset < UserOffset ) UserOffset += Growth + UnknownPadding ( MF -> getAlignment ( )


<s> SDLoc dl ( Op ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl

, <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , ++ Vd , Address ,


<s> assert ( CPE && <STR_LIT> ) ; if ( -- CPE -> RefCount == <NUM_LIT> ) { RemoveDeadCPEMI ( CPEMI ) ; CPE -> CPEMI = NULL ; --


<s> bool <ISA_LIT>Subtarget :: useMovt ( const


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) && shouldTransformMulToShiftsAddsSubs ( C -> getAPIntValue ( ) , VT , DAG , Subtarget ) ) { assert ( VT . isInteger ( ) ) ; return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ; } return SDValue ( N , <NUM_LIT>


<s> gimple * fold ( gimple_folder & f ) const OVERRIDE { poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; poly_uint64 base = m_base * exact_div ( nelts , <NUM_LIT> ) ; vec_perm_builder builder ( nelts , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f , builder


<s> SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } bool AllContants = true ; uint64_t Immediate = <NUM_LIT> ; int NonConstIdx = - <NUM_LIT> ; bool IsSplat = true ; unsigned NumNonConsts = <NUM_LIT> ; unsigned NumConsts = <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) { AllContants = false ; NonConstIdx = idx ; NumNonConsts ++ ; } else { NumConsts ++ ; if ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) ) Immediate |= ( <NUM_LIT> << idx ) ; } if ( In != Op . getOperand ( <NUM_LIT> ) ) IsSplat = false ; } if ( AllContants


<s> SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getNode ( useSSE ? <STR_LIT> : <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset


<s> return getExtractVEXTRACTImmediate ( N ,


<s> static SDValue combineSVEReductionInt ( SDNode * N , unsigned Opc , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Pred = N -> getOperand ( <NUM_LIT> ) ; SDValue VecToReduce = N -> getOperand ( <NUM_LIT> ) ; EVT ReduceVT = getPackedSVEVectorVT ( N -> getValueType ( <NUM_LIT> ) ) ; SDValue Reduce = DAG . getNode ( Opc , DL , ReduceVT


<s> Addr . Base . Reg = getRegForValue ( Obj ) ; return Addr . Base . Reg !=


<s> if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; return MI . getOperand ( OpNo ) . getReg (


<s> static SDValue performSHLCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( Ty != <STR_LIT> ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N , Ty ,


<s> MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType ( ) != <STR_LIT> ) { Curr = DAG . getNode ( <STR_LIT> , dl , CurrVT , DAG . getUNDEF ( CurrVT ) , Curr ) ; MVT CurrSVT = <STR_LIT> ( CurrVT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; CurrVT = <STR_LIT> ( CurrSVT , CurrVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Curr = DAG . getBitcast ( CurrVT , Curr ) ; } SDValue SignExt = Curr ; if ( CurrVT != InVT ) { unsigned SignExtShift = CurrVT . getVectorElementType ( ) . getSizeInBits ( ) - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr , DAG . getConstant ( SignExtShift , dl , <STR_LIT> ) ) ; } if ( CurrVT == VT ) return SignExt ; if ( VT == <STR_LIT> && CurrVT == <STR_LIT> ) { SDValue Sign = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr ,

DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects

( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> assert ( Vec . getValueType ( ) . is512BitVector (


<s> return ( __m128bh ) __builtin_ia32_cvtneps2bf16_v8sf


<s> MachineFunction * MF = CurBB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy (


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask


<s> CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { if ( ! VA . isRegLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; EVT RegVT = VA . getLocVT ( ) ; if ( RegVT != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } const unsigned VReg = RegInfo . createVirtualRegister (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> assert ( ! Subtarget . has<ISA_LIT>32r6 ( ) ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode ( <STR_LIT> , DL , Ty , Mult ) ; if ( HasHi ) Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Mult ) ; if ( ! HasLo || ! HasHi ) return HasLo ? Lo : Hi ; SDValue Vals [ ] = { Lo ,


<s> TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( )


<s> if ( res == AARCH_PARSE_INVALID_ARG ) error ( <STR_LIT> , str ) ; else if ( res == AARCH_PARSE_MISSING_ARG )


<s> unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { printImm ( MI , OpNo , STI , O ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print (


<s> if ( ( NewOp = tryAdvSIMDModImm64 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm8 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImmFP ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = UndefBits ; if ( ( NewOp = tryAdvSIMDModImm64 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm8 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImmFP ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = ~ UndefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; } return SDValue (


<s> Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; return Options ; } ( ) ; return & Options


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> static bool isSignExtended ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG ,


<s> return new <ISA_LIT>InstructionSelector ( TM , STI


<s> unsigned Opcode = MI . getOpcode ( ) ; const unsigned * OpcodesForSpill = getLoadOpcodesForSpillArray ( ) ; const unsigned * End = OpcodesForSpill + SOK_LastOpcodeSpill ; if ( End != std :: find ( OpcodesForSpill , End , Opcode ) ) { if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> )


<s> return ( bit_count ( ARM_FSET_CPU1 ( * set ) ) + bit_count


<s> SDValue <ISA_LIT>TargetLowering :: LowerFNEG ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( )


<s> EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM


<s> void addImm7Shift0Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> return selectMVIAddr ( <STR_LIT> , Addr , Base ,


<s> return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : { int NumVecs = <NUM_LIT> ; SDValue WideVec = Op . getOperand ( <NUM_LIT> ) ; if ( IntrinsicID == <STR_LIT> ) { NumVecs = <NUM_LIT> ; WideVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , WideVec ) ; } SmallVector < SDValue , <NUM_LIT> > RetOps ; for ( int VecNo = <NUM_LIT> ; VecNo < NumVecs ; VecNo ++ ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , WideVec , DAG . getConstant ( Subtarget . isLittleEndian ( ) ? NumVecs - <NUM_LIT> - VecNo : VecNo , dl , <STR_LIT> ) ) ; RetOps . push_back ( Extract ) ; } return DAG . getMergeValues ( RetOps , dl ) ; } } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; } Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> - ( <NUM_LIT> - BitNo ) , dl , <STR_LIT> ) ) ; Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( InvertBit ) Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags


<s> emitFrameDirective ( ) ; printSavedRegsBitmask (


<s> SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction (


<s> if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } if ( pConfig . targets ( ) .


<s> const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Ws1 = RegInfo . createVirtualRegister ( RC ) ; unsigned Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI -> eraseFromParent ( ) ; return BB


<s> arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = <NUM_LIT> , num_regs = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { gcc_assert ( ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) ; if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getConstant ( getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { MVT ValVT = ValToCopy . getValueType ( ) ; if ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) == <NUM_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; FuncInfo -> setSRetReturnReg ( Reg ) ; } SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue


<s> static const char * isa_str ( const struct loongarch_isa * isa , char separator ) { APPEND_STRING ( loongarch_isa_base_strings [ isa -> base ] ) APPEND1 ( separator ) if ( isa -> fpu == ISA_EXT_NOFPU ) { APPEND_STRING ( <STR_LIT> OPTSTR_ISA_EXT_FPU ) } else { APPEND_STRING ( OPTSTR_ISA_EXT_FPU ) APPEND_STRING ( loongarch_isa_ext_strings [ isa -> fpu ] ) } APPEND1 ( '\0' ) return XOBFINISH ( & msg_obstack , const char


<s> return ( __m128i ) __builtin_ia32_expandloadsi128_mask ( ( __v4si * ) __P ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << I . first << <STR_LIT> ) ; for ( const auto & VI : I . second ) DEBUG ( dbgs ( ) << <STR_LIT> ; VI ->


<s> unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) ,


<s> unsigned OffsetOperandNo = ( FIOperandNum == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( )

) OffsetOperandNo = FIOperandNum - <NUM_LIT> ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> vpaddq_u64 ( uint64x2_t a , uint64x2_t b ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> const MCExpr * Expr = nullptr ; SMLoc L = getParser ( ) . getTok ( ) . getLoc ( ) ; if ( check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) ) return true ; const MCConstantExpr * Value = dyn_cast_or_null < MCConstantExpr > ( Expr ) ; if ( check ( ! Value , L , <STR_LIT> ) ) return true ; Out = Value -> getValue ( ) ; return false


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze ( const_tree type ) { gcc_assert ( pieces . is_empty ( ) ) ; if ( type == error_mark_node ) return NO_ABI_IDENTITY ; if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p = {


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) :

ScalarTy -> getPrimitiveSizeInBits ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != <NUM_LIT> ) return false ; if ( ! N -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; } else if ( Copy -> getOpcode


<s> if ( LastEMS == EMS_Data ) return ; emitMappingSymbol ( <STR_LIT> )


<s> unsigned MaxSize = Size * <NUM_LIT> ; if ( ! Arg . IsFixed ) MaxSize = <NUM_LIT> ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ <NUM_LIT> ] , VA , MaxSize ) : Arg


<s> BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB )


<s> Res = DAG . getNode ( <STR_LIT> , DL , { WideVT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , V } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , WideVT , V ) ; } Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , DL ) ; return Res ; } if ( Subtarget . hasAVX ( ) && VecIntVT == <STR_LIT> && Op -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue ZExtIn = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; Constant * Bias = ConstantFP :: get ( * DAG . getContext ( ) , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; auto PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx = DAG . getConstantPool ( Bias , PtrVT , Align ( <NUM_LIT> ) ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , CPIdx } ; SDValue VBias = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ZExtIn , DAG . getBitcast ( <STR_LIT> , VBias ) ) ; Or = DAG . getBitcast ( <STR_LIT> , Or ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Or , VBias } ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Or , VBias ) ; } bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT ,


<s> auto I = llvm :: lower_bound ( ShapeBBs [ MBB ] , MIR ) ; if ( I == ShapeBBs [ MBB ] . end ( ) || * I != MIR ) ShapeBBs [ MBB ] . insert ( I , MIR ) ; } ; SmallVector < Register , <NUM_LIT> > WorkList ( { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; while ( ! WorkList . empty ( ) ) { Register R = WorkList . pop_back_val ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( R ) ; assert ( DefMI && <STR_LIT> ) ; MachineBasicBlock * DefMBB = DefMI -> getParent ( ) ; if ( DefMI -> isMoveImmediate ( ) || ! DefVisited . insert ( DefMI ) .


<s> EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl ,

ResultVT , Vec -> op_begin ( ) + NormalizedIdxVal , ElemsPerChunk ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue RetAddrFI = getReturnAddrFrameIndex (


<s> Optional < int64_t > Const ; if ( ( Const = getIfConst ( Add -> getOperand ( <NUM_LIT> ) ) ) ) Summand = Add -> getOperand ( <NUM_LIT> ) ; else if ( ( Const = getIfConst ( Add -> getOperand ( <NUM_LIT> ) ) ) ) Summand = Add -> getOperand ( <NUM_LIT> ) ; else return ReturnFalse ; int64_t Immediate = Const . getValue ( ) <<


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) , true ) ; case <STR_LIT> : return emitSEL_D ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; int64_t SVal = std :: make_signed_t < T > (


<s> AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > (


<s> <ISA_LIT>HazardRecognizer970 :: <ISA_LIT>HazardRecognizer970 ( const ScheduleDAG & DAG ) : DAG ( DAG ) { EndDispatchGroup ( )


<s> static DecodeStatus DecodeACCRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst ,


<s> <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; OwningPtr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = <NUM_LIT> ; if ( getParser ( ) . ParseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT>


<s> ResVT = <STR_LIT> ; TruncVT = <STR_LIT> ; Opc = <STR_LIT> ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDValue Res = DAG . getNode ( Opc , dl , ResVT , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , IsSigned , false ) ; SDValue FIST = Vals . first , StackSlot = Vals .


<s> Patterns . push_back ( Pattern ) ; return true ; } return false ; } ; typedef MachineCombinerPattern MCP ; switch ( Root . getOpcode ( ) ) { default : return false ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i32_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i32_indexed_OP2 ) ; break ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i64_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i64_indexed_OP2 ) ; break ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv4i16_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv4i16_indexed_OP2


<s> return __builtin_mve_vrshrq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __imm ,


<s> if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Modified


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; } } MachineRelocation R ; if ( MO . isGlobal ( ) ) { R = MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getGlobal ( ) , <NUM_LIT> , isa < Function > ( MO . getGlobal ( ) ) ) ; } else if ( MO . isSymbol ( ) ) { R = MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , <NUM_LIT> ) ; } else if ( MO . isCPI ( ) ) { R = MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } else { assert ( MO . isJTI ( ) ) ; R = MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && Reloc != <STR_LIT> ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; R . setConstantVal ( - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ) ; } MCE . addRelocation ( R ) ; } else if ( MO .


<s> int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( V1Only && ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; if ( V2Only && ( Elt0 == i * <NUM_LIT> + <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src

, DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ;


<s> Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( )


<s> unsigned <ISA_LIT>TTIImpl :: getRegisterClassForType ( bool Vector , Type * Ty ) const { if ( Vector ) return ST -> hasVSX


<s> case <STR_LIT> : case <STR_LIT> : CheckCPSRDef = true ; case <STR_LIT> : break ; } if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ; return CheckCPSRDef ? ! definesCPSR ( MI ) :


<s> return ( uint8x16_t ) __builtin_aarch64_uhaddv16qi ( ( int8x16_t ) __a , (


<s> bool isInArgFI ( int FI ) const { return FI <= InArgFIRange . first && FI >=


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_OP ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { unsigned MinSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Opcode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst MCI ; MCI . setOpcode ( Opcode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) MCI . addOperand ( MaybeOperand . getValue ( ) ) ; SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT>


<s> static DecodeStatus DecodeThumbBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler ::


<s> if ( Op1 -> isUndef ( ) ) return Op0 ; if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; APInt Op1DemandedElts = APInt :: getSplat ( NumElts , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt Op0DemandedElts = IsTop ? Op1DemandedElts : APInt :: getSplat ( NumElts , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedVectorElts ( Op0 , Op0DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( TLI . SimplifyDemandedVectorElts ( Op1 , Op1DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue


<s> builtin_define ( <STR_LIT> ) ; } if ( TARGET_HARD_FLOAT ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT_ABI ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_SINGLE_FPU ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } } else { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( CSKY_ISA_FEATURE ( fpv2_sf ) ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_SUPPORT_FPV3 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_ELRW ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_ISTACK ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_MP ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_CP ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_CACHE ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_SECURITY ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_TRUST ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_DSP ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_EDSP ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_VDSP ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT>


<s> unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget -> hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; MVT ExtVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue One = DAG . getConstant ( APInt ( ExtVT . getScalarSizeInBits ( ) , <NUM_LIT> )


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ; } else { static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOTOFF , <STR_LIT> } , { MO_POT , <STR_LIT> } , { MO_SEC , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE ->


<s> return ( __m512i ) __builtin_ia32_pmovsxbq512_mask ( ( __v16qi ) __A , ( __v8di ) _mm512_setzero_si512 ( )


<s> match = <NUM_LIT> ; phdr = info -> dlpi_phdr ; load_base = info -> dlpi_addr ; p_unwind = NULL ; p_dynamic = NULL ; seg_base = ~ ( Elf64_Addr ) <NUM_LIT> ; for ( n = info -> dlpi_phnum ; -- n >= <NUM_LIT> ; phdr ++ ) { if ( phdr -> p_type == PT_LOAD ) { Elf64_Addr vaddr = phdr -> p_vaddr + load_base ; if ( data -> pc >= vaddr && data -> pc < vaddr + phdr -> p_memsz ) match = <NUM_LIT> ; if ( vaddr < seg_base ) seg_base = vaddr ; } else if ( phdr -> p_type == PT_IA_64_UNWIND ) p_unwind = phdr ; else if ( phdr -> p_type == PT_DYNAMIC ) p_dynamic = phdr ; } if ( ! match || ! p_unwind ) return <NUM_LIT> ; f_base = ( struct unw_table_entry * ) ( p_unwind -> p_vaddr + load_base ) ; lo = <NUM_LIT> ; hi = p_unwind -> p_memsz / sizeof ( struct unw_table_entry ) ; while ( lo < hi ) { size_t mid = ( lo + hi ) / <NUM_LIT> ; f = f_base + mid ; if ( data -> pc < f -> start_offset + seg_base ) hi = mid ; else if ( data -> pc >= f -> end_offset + seg_base ) lo = mid + <NUM_LIT> ; else goto found ; } return <NUM_LIT> ; found : * data -> segment_base = seg_base ; * data -> gp = <NUM_LIT> ; data -> ret = f ; if ( p_dynamic ) { Elf64_Dyn * dyn = ( Elf64_Dyn * ) ( p_dynamic ->


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rd == Rm || Rm == Rn || Rd == Rn ) return MCDisassembler :: Fail ; if ( ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || !

DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rm , Addr , Decoder ) ) return MCDisassembler :: Fail ;


<s> switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( <ISA_LIT>SubTarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && <ISA_LIT>SubTarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT>


<s> Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gprmask , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO ,

ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) , <NUM_LIT> , <STR_LIT> ) ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg (


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand ::


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( <STR_LIT> ( TT ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo


<s> bool ImmediateOffsetNeedsLowering = false ; bool RegisterOffsetNeedsLowering = false ; int64_t Offset = Addr . getOffset ( ) ; if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . isRegBase ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ImmediateOffsetNeedsLowering && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> ,

Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , true ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= II -> getRegisterInfo ( ) . getEncodingValue ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; emitConstPoolAddress ( MI . getOperand ( <NUM_LIT> ) . getIndex ( )


<s> case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N


<s> unsigned <ISA_LIT>CodeEmitter :: getS16ImmEncoding ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ; unsigned RelocID ; switch ( MO . getTargetFlags ( ) & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; case <STR_LIT> : RelocID = <STR_LIT> ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __rord ( unsigned int __X , int __C ) { __C &= <NUM_LIT> ; return ( __X >> __C ) | ( __X << ( -


<s> if ( isNegative ) RealVal . changeSign ( ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; if ( RealVal . isPosZero ( ) ) { Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; return MatchOperand_Success ; } else if ( Val == - <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( ! Hash ) return MatchOperand_NoMatch ; TokError ( <STR_LIT> ) ; return


<s> if ( ( EmittedAddr & <NUM_LIT> ) != <NUM_LIT> ) Hi ++ ; int Lo = ( int ) ( EmittedAddr & <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Hi ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Lo ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT>


<s> case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break


<s> const MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasSwiftAsyncContext ( ) ) return !


<s> STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI -> hasAVX512 ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg


<s> unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second


<s> if ( CurrVT != InVT ) { unsigned SignExtShift = CurrVT . getVectorElementType ( ) . getSizeInBits ( ) - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr , DAG . getConstant ( SignExtShift , dl , <STR_LIT> ) ) ; } if ( CurrVT == VT ) return SignExt ; if ( VT == <STR_LIT> && CurrVT == <STR_LIT> ) { SDValue Sign = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext = DAG . getVectorShuffle ( CurrVT , dl , SignExt , Sign , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return DAG . getBitcast ( VT , Ext ) ; } return SDValue ( )


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) , DL ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> <STR_LIT> : ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows


<s> bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM


<s> return DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } APInt VP1 = Value + <NUM_LIT> ; if ( VP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VP1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } } else { APInt VNP1 = - Value + <NUM_LIT> ; if ( VNP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNP1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , ShiftedVal ) ; } APInt VNM1 = - Value - <NUM_LIT> ; if ( VNM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNM1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Add ) ; } } } return SDValue