<s> else sh_divsi3_libfunc = <STR_LIT> ; if ( sh_branch_cost == - <NUM_LIT> ) { sh_branch_cost = <NUM_LIT> ; } if ( ! OPTION_SET_P ( TARGET_ZDCBRANCH ) && TARGET_HARD_SH4 ) TARGET_ZDCBRANCH = <NUM_LIT> ; if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( flag_pic && ! TARGET_PREFERGOT ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && OPTION_SET_P ( flag_schedule_insns ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! OPTION_SET_P ( flag_schedule_insns ) ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && ! TARGET_ACCUMULATE_OUTGOING_ARGS ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; TARGET_ACCUMULATE_OUTGOING_ARGS = <NUM_LIT> ; } if ( flag_unsafe_math_optimizations ) { if ( OPTION_SET_P ( TARGET_FSCA ) == <NUM_LIT> && ( TARGET_SH4A_FP || TARGET_FPU_SH4_300 ) ) TARGET_FSCA = <NUM_LIT> ; if ( OPTION_SET_P ( TARGET_FSRRA ) == <NUM_LIT> && ( TARGET_SH4A_FP || TARGET_FPU_SH4_300 ) ) TARGET_FSRRA = <NUM_LIT> ; } TARGET_FSRRA = TARGET_FSRRA && flag_unsafe_math_optimizations && flag_finite_math_only ; if ( ! OPTION_SET_P ( TARGET_IEEE ) ) TARGET_IEEE = ! flag_finite_math_only ; if ( sh_fixed_range_str ) sh_fix_range ( sh_fixed_range_str ) ; if ( flag_strict_volatile_bitfields < <NUM_LIT> && abi_version_at_least ( <NUM_LIT> ) ) flag_strict_volatile_bitfields = <NUM_LIT> ; sh_override_options_after_change ( ) ; selected_atomic_model_ = parse_validate_atomic_model_option ( sh_atomic_model_str ) ; register_sh_passes (


<s> static DecodeStatus DecodeThumbTableBranch ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { const FeatureBitset & FeatureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn


<s> } ; auto IsFMS = [ & ] ( Instruction * I ) { if ( match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) || match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) ) return true ; return false ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return ! IsFMS ( I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; Instruction * Shuffle = Op ; if ( Shuffle -> getOpcode ( ) == Instruction :: BitCast ) Shuffle = dyn_cast < Instruction > ( Shuffle -> getOperand ( <NUM_LIT> ) ) ; if ( ! Shuffle || ! match ( Shuffle , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; for ( Use & U : Op -> uses


<s> if ( ! LiveRegs . contains ( SuperDestReg ) ) { if ( SubRegIdx != <STR_LIT> ) return true ; if ( ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ) && ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( SuperDestReg , <NUM_LIT> , true ) ) ) return true ; } unsigned Opc = OrigMI -> getOpcode ( ) ; ( void ) Opc ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) )


<s> return ( vector signed short ) __builtin_altivec_vupkhsb ( ( vector


<s> return ( __m128d ) __builtin_ia32_cvtuqq2pd128_mask ( ( __v2di ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 )


<s> in . d [ <NUM_LIT> ] = a ; in . d [ <NUM_LIT> ] = a ; return ( in .


<s> rtx c = gen_int_mode ( val , GET_MODE_INNER


<s> if ( Subtarget . hasBMI2 ( ) && VT . isScalarInteger ( ) ) { switch ( VT . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : return Subtarget . is64Bit ( ) ? true : false ; case <NUM_LIT> : return


<s> void addMemoryIndexedOperands ( MCInst & Inst , unsigned N , unsigned Scale ) const { Inst . addOperand ( MCOperand :: CreateReg ( Mem . BaseRegNum ) ) ; if ( ! Mem . OffsetImm ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ) { assert ( CE -> getValue ( ) % Scale == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) / Scale ) ) ; } const MCExpr * Expr =


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( mask ) > <NUM_LIT> && UINTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( UINTVAL ( mask ) >> UINTVAL ( shft_amnt ) ) + <NUM_LIT> ) >= <NUM_LIT> && ( UINTVAL ( mask ) & ( ( HOST_WIDE_INT_1U <<

UINTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return


<s> createUnpackShuffleMask ( <STR_LIT> , Unpckhwd , false , false ) ; bool IsUnpackwdMask = ( isTargetShuffleEquivalent ( Mask , Unpcklwd ) || isTargetShuffleEquivalent ( Mask


<s> FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb , insn ) { if ( single_set ( insn ) && nds32_symbol_load_store_p ( insn ) ) { rtx pattern = PATTERN ( insn ) ; rtx mem ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; if ( GET_CODE ( SET_SRC ( pattern ) ) == REG ) mem = SET_DEST ( pattern ) ; else mem = SET_SRC ( pattern ) ; if ( GET_CODE ( mem ) == MEM ) symbol_count ++ ; } } } return


<s> if ( strstr ( argv [ i ] , <STR_LIT> ) ) target_ilp32 = true ; else if ( ! strstr ( argv [ i ] , <STR_LIT> ) ) fatal_error ( input_location , <STR_LIT> ) ; break ; } const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; unsigned new_argc = <NUM_LIT> ; const char * new_argv [ <NUM_LIT> ] ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = <STR_LIT> ; if ( target_ilp32 ) new_argv [ new_argc ++ ] = <STR_LIT> ; else new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = host_descr_filename ; new_argv [ new_argc ++ ] = target_so_filename ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = out_obj_filename ; new_argv [ new_argc ++ ] = NULL ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , false ) ; new_argv [ <NUM_LIT> ] = <STR_LIT> ; new_argv [ <NUM_LIT> ] = <STR_LIT> ; new_argv [ <NUM_LIT> ] = symbols [ <NUM_LIT> ] ; new_argv [ <NUM_LIT> ] = <STR_LIT> ; new_argv [ <NUM_LIT> ] = symbols


<s> if ( basic_align < <NUM_LIT> ) return


<s> llvm :: StringRef getPassName ( ) const


<s> static SDValue getTargetVShiftNode ( unsigned Opc , SDLoc dl , EVT VT , SDValue SrcOp , SDValue ShAmt , SelectionDAG & DAG ) { assert ( ShAmt . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShOps [ <NUM_LIT> ] , <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits ( ) ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , ShVT , ShAmt ) ; return DAG . getNode ( Opc , dl


<s> inline bool isImmSExti32i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value


<s> enum machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intCI_type_node ) ; TYPE_NAME ( arm_simd_intCI_type_node


<s> RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( <STR_LIT> ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != <STR_LIT> ) for ( auto & MO : MRI -> use_nodbg_operands ( <STR_LIT>


<s> } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ; } else if ( const StoreInst * SI = dyn_cast < StoreInst > ( I ) ) { const Value * StoredVal = SI -> getValueOperand (


<s> if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , SDLoc ( Ptr ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask


<s> bool isPtrReg ( ) const { return Kind ==


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; assert ( ( MF . getRegInfo ( ) . use_empty ( <STR_LIT> ) || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUsingPCRelativeCalls ( ) ) && <STR_LIT> ) ; if ( skipFunction ( MF . getFunction (


<NUM_LIT> , XEXP ( m_tramp , <NUM_LIT> ) , Pmode ) ;


<s> static __inline qword si_clgt ( qword a , qword b


<s> void ia64_start_function ( FILE * file , const char * fnname , tree decl ATTRIBUTE_UNUSED ) { vms_start_function ( fnname ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , fnname ) ; fputc ( '\n' ,


<s> assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MVT PtrMemVT = getPointerMemTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( PtrMemVT , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , PtrMemVT . getSizeInBits ( ) / <NUM_LIT> , MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; FuncTLVGet = DAG . getZExtOrTrunc ( FuncTLVGet , DL , PtrVT ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getTLSCallPreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask

( DAG . getMachineFunction ( ) , & Mask ) ;


<s> return ( vector signed int ) __builtin_altivec_vavgsw ( ( vector signed int ) a1


<s> for ( SDNode * N : GN -> uses ( ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; MinOffset = std :: min ( MinOffset , C -> getZExtValue ( ) ) ; } uint64_t Offset = MinOffset +


<s> virtual const <ISA_LIT>TargetLowering *


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) <STR_LIT> ::

write < uint32_t > ( OS , <NUM_LIT> , Endian ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> <ISA_LIT>DisassemblerBase ( const MCSubtargetInfo & STI , const MCRegisterInfo * Info , bool bigEndian ) : MCDisassembler ( STI ) , RegInfo ( Info ) , IsN64 ( STI . getFeatureBits ( ) &

<STR_LIT> ) , isBigEndian ( bigEndian ) {


<s> * cost = <NUM_LIT> ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = <NUM_LIT> ; return false


<s> if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD -


<s> if ( ( FirstMI == nullptr || ( FirstMI -> getOpcode ( ) == <STR_LIT> && FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) && ( SecondMI . getOpcode ( ) == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; return


<s> __builtin_mve_vst4qv8hi ( ( __builtin_neon_hi * ) __addr ,


<s> case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveSetNoAt ( ) ; Parser . Lex ( ) ; return


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> bool <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand


<s> if ( MemOpIndex + <NUM_LIT> >= Desc . getNumOperands ( ) ) return None ; const MCOperand & MO1 = Inst . getOperand ( MemOpIndex ) ; const MCOperand & MO2 = Inst . getOperand ( MemOpIndex + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) || MO1 . getReg ( ) != <STR_LIT> || ! MO2 . isImm ( ) ) return None ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; <STR_LIT> Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Op == <STR_LIT> ) return Addr -


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) && Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier (


<s> IsFixed . resize ( Ins . size ( ) , true ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn


<s> MCTargetStreamer * llvm :: create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; if ( TT . isOSBinFormatCOFF ( ) ) return

new <ISA_LIT>TargetWinCOFFStreamer ( S ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass (


<s> fprintf ( stream , <STR_LIT> , power ) ; fprintf ( stream , <STR_LIT> , <NUM_LIT> << power , (


<s> bool arm_vector_mode_supported_p ( enum machine_mode mode ) { if ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) return true ; return false


<s> void ix86_split_ashl ( rtx * operands , rtx scratch , machine_mode mode ) { rtx ( * gen_ashl3 ) ( rtx , rtx , rtx ) ; rtx ( * gen_shld ) ( rtx , rtx , rtx ) ; int half_width = GET_MODE_BITSIZE ( mode ) >> <NUM_LIT> ; rtx low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ; int count ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) { split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; count = INTVAL ( operands [ <NUM_LIT> ] ) & ( GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) ; if ( count >= half_width ) { emit_move_insn ( high [ <NUM_LIT> ] , low [ <NUM_LIT> ] ) ; emit_move_insn ( low [ <NUM_LIT> ] , const0_rtx ) ; if ( count > half_width ) ix86_expand_ashl_const ( high [ <NUM_LIT> ] , count - half_width , mode ) ; } else { gen_shld = mode == DImode ? gen_x86_shld : gen_x86_64_shld ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shld ( high [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; ix86_expand_ashl_const ( low [ <NUM_LIT> ] , count , mode ) ; } return ; } split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; gen_ashl3 = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; if ( operands [ <NUM_LIT> ] == const1_rtx ) { if ( ANY_QI_REG_P ( low [ <NUM_LIT> ] ) && ANY_QI_REG_P ( high [ <NUM_LIT> ] ) ) { rtx s , d , flags = gen_rtx_REG ( CCZmode , FLAGS_REG ) ; ix86_expand_clear ( low [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; emit_insn ( gen_testqi_ccz_1 ( operands [ <NUM_LIT> ] , GEN_INT ( half_width ) ) ) ; d = gen_lowpart ( QImode , low [ <NUM_LIT> ] ) ; d = gen_rtx_STRICT_LOW_PART ( VOIDmode ,


<s> SmallVectorImpl < VPTState > & getVPTBlocks (


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformADDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSUBCombine ( N ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerFSINCOS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo


<s> auto & DL = MI -> getDebugLoc ( ) ; Register Reg = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( DstOpcode ) , <NUM_LIT> , MRI -> getTargetRegisterInfo ( ) , * MBB -> getParent ( ) ) ) ; MachineInstrBuilder Bld = BuildMI ( * MBB , MI , DL , TII -> get ( DstOpcode ) , Reg ) ; for ( unsigned Idx = <NUM_LIT> , End = MI -> getNumOperands ( ) ; Idx < End ; ++ Idx ) Bld . add ( MI -> getOperand ( Idx ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( Reg ) ; return true


<s> return __builtin_mve_vcaddq_rot90_fv4sf ( __a ,


<s> static bool IsShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I


<s> if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT>

) . cloneMemRefs ( * MI ) . add ( predOps ( <STR_LIT> ) ) ;


<s> RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; if ( i % <NUM_LIT> == <NUM_LIT> ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; dwarf = NULL_RTX ; } XVECEXP ( par , <NUM_LIT> , ( i % <NUM_LIT> ) ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; if ( ( i % <NUM_LIT> ) == <NUM_LIT> ) { par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; RTX_FRAME_RELATED_P ( par ) = <NUM_LIT> ; } i ++ ; } tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( ! return_in_pc ) { arm_add_cfa_adjust_cfa_note ( tmp , UNITS_PER_WORD * i , stack_pointer_rtx , stack_pointer_rtx ) ; } dwarf = NULL_RTX ; if ( ( ( num_regs % <NUM_LIT> ) == <NUM_LIT> && ! return_in_pc ) || ( ( num_regs % <NUM_LIT> ) == <NUM_LIT> && return_in_pc ) ) { for ( ; ( saved_regs_mask & ( <NUM_LIT> << j


<s> auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( all_fpus ) ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] .


<s> if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } if ( Subtarget -> useMovt ( * MF ) ) return


<s> if ( ! isa < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ) return false ; const auto * II = cast < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ; MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; const Value * LHS = II -> getArgOperand ( <NUM_LIT> ) ; const Value * RHS = II -> getArgOperand ( <NUM_LIT> ) ; if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) && isCommutativeIntrinsic ( II ) ) std :: swap ( LHS , RHS ) ; <STR_LIT> IID = II -> getIntrinsicID ( ) ; switch ( IID ) { default : break ; case <STR_LIT> : if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) if ( C -> getValue ( ) == <NUM_LIT> ) IID = <STR_LIT> ; break ; case <STR_LIT> : if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) if ( C -> getValue ( ) == <NUM_LIT> ) IID = <STR_LIT> ; break ; } <STR_LIT> TmpCC ; switch ( IID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false


<s> if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , <NUM_LIT> ) ) ||

! REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) return false ;


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP ( insn , <NUM_LIT> , i ) = clobs [ i ] ; return insn


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( )

) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ;


<s> vld4_s8 ( const int8_t * __a ) { int8x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t )


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I )


<s> PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return true


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t TargetAddress ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( TargetAddress ) ) { O << formatHex ( TargetAddress ) ; } else


<s> int BytesCalleePops = ( CallConv == CallingConv :: Fast && GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc ==


<s> return ( __m512 ) __builtin_ia32_scalefps512_mask ( ( __v16sf ) __A , ( __v16sf ) __B , ( __v16sf ) _mm512_undefined_ps ( ) ,


<s> FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) F . getRegInfo ( )


<s> if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val =


<s> bool <ISA_LIT>InstrSema :: translateTargetInst ( ) { unsigned Opcode = CurrentInst -> Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> bool hasBitPreservingFPLogic ( EVT VT ) const override { return VT == <STR_LIT> || VT == <STR_LIT> || VT . isVector


<s> SDValue NewN0 = DCI . DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DCI . DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DCI . DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ; return DCI . DAG . getLogicalNOT ( DL , And ,


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> ) return EmitTest ( Op0 , <ISA_LIT>CC , DAG ) ; DebugLoc dl = Op0


<s> } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; break ; } } MVT VecTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! ( MMO -> getAlignment ( ) % <NUM_LIT> ) && VecTy . getScalarSizeInBits ( ) <= <NUM_LIT> ) { return SDValue ( ) ; } SDValue LoadOps [ ] = { Chain , Base } ; SDValue Load = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LoadOps , <STR_LIT> , MMO ) ; DCI . AddToWorklist ( Load . getNode ( ) ) ; Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Swap = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Load ) ; DCI . AddToWorklist ( Swap . getNode ( ) ) ; if ( VecTy != <STR_LIT> ) { SDValue N = DAG . getNode ( <STR_LIT> ,


<s> void <ISA_LIT>AsmPrinter :: customEmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this


<s> static SDValue performSVEAndCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { SDValue UnpkOp = Src -> getOperand ( <NUM_LIT> ) ; SDValue Dup = N -> getOperand ( <NUM_LIT> ) ; if ( Dup . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Dup -> getOperand ( <NUM_LIT> ) ) ; uint64_t ExtVal = C -> getZExtValue ( ) ; EVT EltTy = UnpkOp -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; else if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; default : break ; } if ( ! Opc ) return false ; MatchInfo . first =


<s> unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg


<s> static DecodeStatus decodeS32ImmOperand ( MCInst & Inst , uint64_t Imm ,

uint64_t Address , const MCDisassembler * Decoder ) {


<s> switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } return


<s> Value * <ISA_LIT>IREmitter :: visitVTRN ( const SDNode *


<s> } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo )


<s> if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n'


<s> OS << <STR_LIT> << S -> getSymbol ( )


<s> bool isISAFuture ( ) const { return IsISAFuture


<s> Value * <ISA_LIT>IREmitter :: visitRBIT ( const SDNode * N


<s> reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) .


<s> void \ rdata_section ( ) \ { \ if ( in_section != in_rdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , RDATA_SECTION_ASM_OP ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI


<s> if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , Ld -> getBasePtr (

) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ;


<s> return Kind == k_VectorIndex && VectorIndex . Val


<s> if ( AOp1 . getRegEqualityTy ( ) == EqualsSuperReg ) return getXRegFromWReg ( Op1 . getReg ( ) ) == Op2 . getReg ( ) ; if ( AOp1 . getRegEqualityTy ( ) == EqualsSubReg ) return getWRegFromXReg ( Op1 . getReg ( ) ) == Op2 . getReg ( ) ; if ( AOp2 . getRegEqualityTy ( ) == EqualsSuperReg ) return getXRegFromWReg ( Op2 . getReg ( ) ) == Op1 . getReg ( ) ; if ( AOp2 . getRegEqualityTy ( ) == EqualsSubReg ) return getWRegFromXReg ( Op2 . getReg ( ) ) == Op1 . getReg


<s> assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; populateThunk ( MF , <STR_LIT> ) ; } else { if ( MF . getName ( ) == EAXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == ECXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDIThunkName ) populateThunk ( MF , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> if ( split_cost < <NUM_LIT> ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } struct recog_data_d recog_data_save = recog_data ; dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; recog_data = recog_data_save ; if ( dist_define < <NUM_LIT> || dist_define


<s> std :: string Src = <STR_LIT> . contains ( SrcReg ) ? <STR_LIT> : <STR_LIT> ; dbgs ( ) << <STR_LIT> << Src << <STR_LIT>


<s> case V4HImode : case V2SImode : case V1DImode : case V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case DFmode : case DDmode : case DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case TFmode : case IFmode : case KFmode : if ( TARGET_E500_DOUBLE ) return ( SPE_CONST_OFFSET_OK ( offset ) && SPE_CONST_OFFSET_OK ( offset + <NUM_LIT> ) ) ; case TDmode : case TImode : case PTImode : extra = <NUM_LIT> ; if ( ! worst_case


<s> unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB ) ; return


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = ( __vector signed short ) vec_cmpeq ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_short [ <NUM_LIT> ] = ( m1 . as_short [ <NUM_LIT> ] == m2 . as_short [ <NUM_LIT> ]


<s> void <ISA_LIT>TargetAsmStreamer :: emitInst ( uint32_t Inst , char Suffix ) { OS << <STR_LIT> ; if ( Suffix ) OS


<s> return ( int16x4_t ) __builtin_neon_vbslv4hi ( ( int16x4_t


<s> if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute


<s> vmla_u16 ( uint16x4_t a , uint16x4_t b , uint16x4_t c ) { uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> static const uint32_t CV0 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Constant * C0 = ConstantDataVector :: get ( * Context , CV0 ) ; auto PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , PtrVT , Align ( <NUM_LIT> ) ) ; SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , Align ( <NUM_LIT> ) ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) && shouldUseHorizontalOp ( true , DAG , Subtarget ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; }


<s> Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } Res = Inst ; Res . setOpcode (


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rs , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case


<s> static void reorderSubVector ( MVT VT , SmallVectorImpl < Value * > & TransposedMatrix , ArrayRef < Value * > Vec , ArrayRef < int > VPShuf , unsigned VecElems , unsigned Stride , IRBuilder < > & Builder ) { if ( VecElems == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , UndefValue :: get ( Vec [ i ] -> getType ( ) ) , VPShuf ) ; return ; } SmallVector < int , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; } if ( VecElems == <NUM_LIT> ) { std :: copy ( Temp , Temp + Stride


<s> return decodeSImmOperand < <NUM_LIT> > ( Inst


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorList ( unsigned RegNum , unsigned Count , unsigned NumElements , unsigned ElementWidth , RegKind RegisterKind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_VectorList , Ctx ) ; Op -> VectorList .


<s> auto & MMI = getAnalysis < MachineModuleInfoWrapperPass >


<s> return ( __m512d ) __builtin_ia32_getmantpd512_mask ( ( __v8df ) __A , ( __C << <NUM_LIT> ) | __B , _mm512_undefined_pd ( ) ,


<s> if ( Ty -> isVectorTy ( ) && ! IsVectorAllowed ) return false ; if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> )


<s> unsigned <ISA_LIT>CodeEmitter :: getAbsDirectBrEncoding ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand (


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> )

. addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ <NUM_LIT> ) return true ; for ( unsigned i = <NUM_LIT> ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; unsigned Opcode = InstrInfo ->


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) &&


<s> const MCInstrDesc & MCID = TII -> get ( ConvOpcode ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MCID ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( OldOffset - Offset ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . cloneMemRefs ( * MI ) ; MI -> eraseFromParent ( )


<s> static SDValue MaterializeSETB ( SDLoc DL , SDValue EFLAGS , SelectionDAG & DAG , MVT VT ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; assert ( VT == <STR_LIT>


<s> if ( CFP -> isNullValue ( ) ) return fastMaterializeFloatZero ( CFP ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const APFloat Val = CFP -> getValueAPF ( ) ; bool Is64Bit = ( VT == <STR_LIT> ) ; int Imm = Is64Bit ? <STR_LIT> ( Val ) : <STR_LIT> ( Val ) ; if ( Imm != - <NUM_LIT> ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; return fastEmitInst_i ( Opc , TLI . getRegClassFor ( VT ) , Imm ) ; } if ( TM . getCodeModel ( ) == CodeModel :: Large ) { unsigned Opc1 = Is64Bit ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc1 ) , TmpReg ) . addImm ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; return ResultReg ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; Register ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT


<s> CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( CPEBB -> begin ( ) ) ) ; adjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB


<s> if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( C -> getZExtValue ( ) , N , DAG , VT , DL ) ; if ( ! NewMul ) { assert ( C -> getZExtValue ( ) != <NUM_LIT> && C -> getZExtValue ( ) != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; if ( isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL

, VT , N -> getOperand ( <NUM_LIT> ) , NewMul ) ;


<s> return MI . getDesc ( ) . isBranch ( ) && ! MI . getDesc ( ) .


<s> static SDValue emitConjunction ( SelectionDAG & DAG , SDValue Val , <STR_LIT> & OutCC ) { bool DummyCanNegate ; bool


<NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ;


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo ( ) const { return &


<s> void arm_output_multireg_pop ( rtx * operands , bool return_pc , rtx cond , bool reverse , bool update ) { int i ; char pattern [ <NUM_LIT> ] ; int offset ; const char * conditional ; int num_saves = XVECLEN ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; unsigned int regno ; unsigned int regno_base = REGNO ( operands [ <NUM_LIT> ] ) ; bool interrupt_p = IS_INTERRUPT ( arm_current_func_type ( ) ) ; offset = <NUM_LIT> ; offset += update ? <NUM_LIT> : <NUM_LIT> ; offset += return_pc ? <NUM_LIT> : <NUM_LIT> ; for ( i = offset ; i < num_saves ; i ++ ) { regno = REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , i ) , <NUM_LIT> ) ) ; gcc_assert ( ( regno != SP_REGNUM ) || ( regno_base == SP_REGNUM ) ) ; if ( regno == regno_base ) gcc_assert ( ! update ) ; } conditional = reverse ? <STR_LIT> : <STR_LIT> ; if ( ( regno_base == SP_REGNUM ) && update && ! ( interrupt_p && return_pc ) ) sprintf ( pattern , <STR_LIT> , conditional ) ; else { if ( regno_base == SP_REGNUM ) sprintf ( pattern , <STR_LIT> , conditional ) ; else if ( update ) sprintf ( pattern , <STR_LIT> , conditional ) ; else sprintf ( pattern , <STR_LIT> , conditional ) ; strcat ( pattern , reg_names [ regno_base ] ) ; if ( update ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern , <STR_LIT>


<s> BuildMI ( * MI . getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Mod ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; insertEmulatedTimings ( MBB , MI , Dst , Mod ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MI . removeFromParent ( ) ; return true


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return


<s> if ( Inputs [ i ] . isUndef ( ) ) for ( int & M : Mask ) if ( ( lo <= M ) && ( M < hi ) ) M = SM_SentinelUndef ; if ( none_of ( Mask , [ lo , hi ] ( int i ) { return ( lo <= i ) && ( i < hi ) ; } ) ) { for ( int & M : Mask ) if ( lo <= M ) M -= MaskWidth ; continue ; } bool IsRepeat = false ; for ( int j = <NUM_LIT> , ue = UsedInputs . size ( ) ; j != ue ; ++ j ) { if ( UsedInputs [ j ] != Inputs


<s> if ( SDValue BT = LowerAndToBT ( Op0 , CC , dl , DAG , <ISA_LIT>CC ) ) return BT ; } if ( isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) if ( SDValue CmpZ = MatchVectorAllZeroTest ( Op0 , CC , dl , Subtarget , DAG , <ISA_LIT>CC ) ) return CmpZ ; if ( SDValue Test = EmitAVX512Test ( Op0 , Op1 , CC , dl , DAG , Subtarget , <ISA_LIT>CC ) ) return Test ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; <ISA_LIT>CC = Op0 . getOperand ( <NUM_LIT> ) ; if ( Invert ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , false , Op0 ,


<s> return static_cast < MCELFStreamer & > ( Streamer


<s> MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( RHS ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return &


<s> ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt ) ; AmtVT = <STR_LIT> ; IsMasked = true ; } else if ( ShAmt . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue > MaskElts ( AmtVT . getVectorNumElements ( ) , DAG . getConstant ( <NUM_LIT> , dl , AmtVT . getScalarType ( ) ) ) ; MaskElts [ <NUM_LIT> ] = DAG . getAllOnesConstant ( dl , AmtVT . getScalarType ( ) ) ; SDValue Mask = DAG . getBuildVector ( AmtVT , dl , MaskElts ) ; if ( ( Mask = DAG . FoldConstantArithmetic ( <STR_LIT> , dl , AmtVT , { ShAmt . getOperand ( <NUM_LIT> ) , Mask } ) ) ) { ShAmt = DAG . getNode ( <STR_LIT> , dl , AmtVT , ShAmt . getOperand ( <NUM_LIT> ) , Mask ) ; IsMasked = true ; } } } if ( AmtVT . getSizeInBits ( ) > <NUM_LIT> ) { ShAmt = extract128BitVector ( ShAmt , <NUM_LIT> , DAG , dl ) ; AmtVT = ShAmt . getSimpleValueType ( ) ; } if ( ! IsMasked && AmtVT . getScalarSizeInBits ( ) < <NUM_LIT> ) { if ( AmtVT == <STR_LIT> && ( ShAmt . getOpcode ( ) == <STR_LIT> || ShAmt . getOpcode ( ) == <STR_LIT> ) ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; } else if ( Subtarget . hasSSE41 ( ) ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; } else { SDValue ByteShift = DAG . getTargetConstant ( ( <NUM_LIT> - AmtVT . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast ( <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; } } Opc = getTargetVShiftUniformOpcode ( Opc , true ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits (


<s> static bool rs6000_discover_homogeneous_aggregate ( machine_mode mode , const_tree type , machine_mode * elt_mode , int * n_elts ) { if ( TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > <NUM_LIT> ) { int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE ( field_mode ) ? <NUM_LIT> : <NUM_LIT> ; int field_size = ROUND_UP ( GET_MODE_SIZE ( field_mode ) , reg_size ) ; if ( field_count * field_size <= AGGR_ARG_NUM_REG * reg_size ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode =


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; if ( ! Subtarget -> useConstIslands ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> :


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot

, MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> RegisterMCAsmInfoFn A ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( TheThumbTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbTarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbTarget


<s> if ( ( BitWidth % <NUM_LIT> ) != <NUM_LIT> ) return ; int Scale = BitWidth / <NUM_LIT> ; int NumBytes = NumElts * Scale ; ShuffleMask . reserve ( NumBytes ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue > ( COp ) ) { ShuffleMask . append ( Scale , SM_SentinelUndef ) ; continue ; } APInt APElt = cast < ConstantInt > ( COp ) -> getValue ( ) ; for ( int j = <NUM_LIT> ; j != Scale ; ++ j ) { int Base = ( ( i * Scale ) + j


<s> return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) ==


<s> static bool getTargetShuffleMask ( SDNode * N , MVT VT , bool AllowSentinelZero , SmallVectorImpl < SDValue > & Ops , SmallVectorImpl


<s> SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( VT == <STR_LIT> && InputVector . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( EltIdx ) && isa < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t InputValue = InputVector . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t Res = ( InputValue >> ExtractedElt ) & <NUM_LIT> ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineHorizontalMinMaxResult ( N , DAG , Subtarget ) ) return MinMax ; if ( SrcVT != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << Extract -> getConstantOperandVal ( <NUM_LIT> ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( )


<s> int GPRIdx = <NUM_LIT> ; if ( GPRSaveSize != <NUM_LIT> ) { GPRIdx = MFI -> CreateStackObject ( GPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , wb , Address , Decoder ) ) )


<s> EVT OpVT = N0 . getValueType ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } if ( ! DCI . isBeforeLegalizeOps ( ) ) return


<s> void addImmTLSOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( get<ISA_LIT>TargetMachine (


<s> assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; const TargetRegisterClass * rc = getRegClassFor ( VecVT ) ; if ( ! Subtarget . hasDQI ( ) && ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> ) ) rc = getRegClassFor ( <STR_LIT> ) ; unsigned MaxSift = rc -> getSize ( ) * <NUM_LIT> - <NUM_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( MaxSift - IdxVal , dl , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( MaxSift


<s> SDValue Cond = createFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue True = DAG . getConstant


<s> Address ( ) : BaseType ( RegBase ) , Offset ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , PlusReg ( <NUM_LIT> ) { Base . Reg =


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget ->


<s> if ( insn . mode == MODE_64BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else if ( insn . mode == MODE_32BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else { assert ( insn . mode == MODE_16BIT ) ; baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; } MCOperand baseReg = MCOperand :: CreateReg


<s> unsigned SType = <NUM_LIT> ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> )

, DAG . getConstant ( SType , <STR_LIT> ) ) ;


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } } return


<s> return isInt < <NUM_LIT> > ( Value ) || ( isUInt < <NUM_LIT> > ( Value

) && isInt < <NUM_LIT> > ( static_cast < int16_t > ( Value ) ) ) ;


<s> if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } )


<s> cc_fusion ( ) . execute ( ) ; return <NUM_LIT>


<s> CurFPOData -> PrologueEnd = emitFPOLabel ( ) ; return


<s> unsigned OpWidth = MemType -> getPrimitiveSizeInBits ( ) ; if ( OpWidth == <NUM_LIT> ) return Subtarget . hasCmpxchg8b ( ) && ! Subtarget . is64Bit ( ) ; if ( OpWidth == <NUM_LIT> ) return Subtarget . hasCmpxchg16b ( ) ; return false


<s> int32_t OffImm = ( int32_t ) MO . getImm ( ) << scale ; O << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> <<


<s> bool hasBitCount ( ) const { return HasBitCount


<s> const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } if ( RegInfo -> requiresRegisterScavenging ( MF ) ) if (


<s> bool isMovZSymbolG2 ( ) const { return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G2 , <ISA_LIT>MCExpr :: VK_ABS_G2_S , <ISA_LIT>MCExpr

:: VK_TPREL_G2 , <ISA_LIT>MCExpr :: VK_DTPREL_G2 } ) ;


<s> int64_t StDispImm = getDispOperand ( StoreInst ) . getImm ( ) ; int64_t LMMOffset = <NUM_LIT> ; int64_t SMMOffset = <NUM_LIT> ; int64_t LdDisp1 = LdDispImm ; int64_t LdDisp2 = <NUM_LIT> ; int64_t StDisp1 = StDispImm ; int64_t StDisp2 = <NUM_LIT> ; unsigned Size1 = <NUM_LIT> ; unsigned Size2 = <NUM_LIT> ; int64_t LdStDelta = StDispImm - LdDispImm ; for ( auto DispSizePair : BlockingStoresDispSizeMap ) { LdDisp2 = DispSizePair . first ; StDisp2 = DispSizePair . first + LdStDelta ; Size2 = DispSizePair . second ; if ( LdDisp2 < LdDisp1 ) { int OverlapDelta = LdDisp1 - LdDisp2 ; LdDisp2 += OverlapDelta ; StDisp2 += OverlapDelta ; Size2 -= OverlapDelta ; } Size1 = std :: abs ( std :: abs ( LdDisp2 ) - std :: abs ( LdDisp1 ) ) ; buildCopies ( Size1 , LoadInst , LdDisp1 , StoreInst , StDisp1 , LMMOffset , SMMOffset ) ; buildCopies ( Size2 , LoadInst , LdDisp2 , StoreInst , StDisp2 , LMMOffset + Size1 , SMMOffset + Size1 ) ; LdDisp1 = LdDisp2


<s> AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; if ( isThumb2 ) { MRI . constrainRegClass ( destlo , & <STR_LIT> ) ; MRI . constrainRegClass ( desthi , & <STR_LIT> ) ; MRI . constrainRegClass ( ptr , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( <NUM_LIT> , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( ldrOpc ) ) ; if ( isThumb2 ) { MIB . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } AddDefaultPred ( MIB ) ; MI -> eraseFromParent ( ) ; return BB


<s> if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue (


<s> bool Result = AsmPrinter :: doInitialization ( M ) ; if ( TAI -> doesSupportDebugInformation ( ) ) { MMI = getAnalysisIfAvailable < MachineModuleInfo >


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isRegMask ( ) ) { bool ClobbersFP0 = Op . clobbersPhysReg ( <STR_LIT> ) ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) assert ( Op . clobbersPhysReg ( <STR_LIT> + i ) == ClobbersFP0 && <STR_LIT> ) ; if ( ClobbersFP0 ) ClobbersFPStack = true ; } if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } assert ( ( ClobbersFPStack || STReturns == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! ClobbersFPStack ) return ; unsigned N = countTrailingOnes ( STReturns


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand (


<s> PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumVectorRegs ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost


<s> static DecodeStatus DecodeCASI64 ( MCInst & MI , uint64_t insn , uint64_t Address


<s> if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) { if ( getRelocationModel ( ) == Reloc ::


) _mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , <NUM_LIT> ) ; rtx_insn * insn ; int distance ; for ( distance = <NUM_LIT> , insn = NEXT_INSN ( branch1 ) ; insn && distance < <NUM_LIT> ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } for ( distance = <NUM_LIT> , insn


<s> if ( ST -> hasAVX512 ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( ) ) return


<s> if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( !

argsp || ! argsp -> lib ) ) return true ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( M1 ( <NUM_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SubTmp , getKillRegState ( true ) ) ; MIB . getInstr ( ) -> addRegisterKilled ( TmpReg , TRI , true ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { const unsigned SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned int NumSubRegs = <NUM_LIT> ; copyPhysSubRegs ( MBB , I , DL , DestReg , SrcReg , KillSrc , get ( <STR_LIT> ) , NumSubRegs


<s> return Create ( VK_<ISA_LIT>_LO , Expr , isDarwin


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: FPTOSINT_F128_I64 : RTLIB :: FPTOUINT_F128_I64 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> : { assert ( Subtarget -> hasLeonCycleCounter ( ) ) ; SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getCopyFromReg ( Lo , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Lo , Hi } ; SDValue Pair = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; Results . push_back ( Pair ) ; Results . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: SINTTOFP_I64_F128 : RTLIB :: UINTTOFP_I64_F128 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> :


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode


<s> SDValue Cond = createFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return createCMovFP ( DAG , Cond , True ,


<s> if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; OutStreamer -> EmitBytes ( Flags ) ; } SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF (


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; assert ( ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && ! DisableMMX ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return Op ; if ( DstVT == <STR_LIT> && SrcVT . isVector ( ) )


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset )


<s> if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack (


<s> assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBCCR = getRegBank ( <STR_LIT> ) ; ( void ) RBCCR ; assert ( RBCCR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBCCR . getSize ( )


<s> static unsigned int iq2000_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( type != NULL_TREE ? ( TYPE_ALIGN ( type ) <= PARM_BOUNDARY ? PARM_BOUNDARY : TYPE_ALIGN ( type ) ) : ( GET_MODE_ALIGNMENT ( mode ) <= PARM_BOUNDARY ? PARM_BOUNDARY : GET_MODE_ALIGNMENT (


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) !=

<STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) .


<s> static SDValue LowerTruncateVecI1 ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; if ( InVT . getScalarSizeInBits ( ) <= <NUM_LIT> ) { if ( Subtarget . hasBWI ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue ShiftNode = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; ShiftNode = DAG . getBitcast ( InVT , ShiftNode ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ShiftNode ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT .


<s> const MCSymbolRefExpr * A = Target . getSymA ( ) ; if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if ( A ) { const MCSymbol & Sym = A -> getSymbol ( ) . AliasedSymbol ( ) ; if ( Asm . isThumbFunc ( & Sym


<s> int32_t NumBytes = AFI -> getFramePtrSpillOffset ( ) ; unsigned FramePtr = RI . getFrameRegister ( MF ) ; assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) llvm :: emitT2RegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , * AII ) ; else if ( AFI -> isThumbFunction ( ) ) llvm :: emitThumbRegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , * AII , RI ) ; else llvm :: emit<ISA_LIT>RegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , * AII ) ; if ( ! RI . needsStackRealignment ( MF ) ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ; unsigned bicOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MBBI , MI -> getDebugLoc ( ) , TII -> get ( bicOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill )


<s> void <ISA_LIT>TargetStreamer :: emitFPU (


<s> <STR_LIT> Kind = ( <STR_LIT> ) RegKind ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { if ( searchSymbolAlias ( Operands , Kind ) ) return MatchOperand_Success ; return MatchOperand_NoMatch ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; op -> setRegKind ( Kind ) ; return


<s> if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return <NUM_LIT> ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && ( XEXP ( x , <NUM_LIT> ) == virtual_stack_vars_rtx || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return <NUM_LIT> ; if ( mode != TFmode && mode != TDmode && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode !=

DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ;


<s> static unsigned getDepthOfOptCmov ( unsigned TrueOpDepth , unsigned FalseOpDepth ) { return std :: max ( divideCeil ( TrueOpDepth * <NUM_LIT> + FalseOpDepth , <NUM_LIT> ) , divideCeil ( FalseOpDepth * <NUM_LIT> +


<s> static SDValue combineAndnp ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT>


<s> unsigned Opc = <NUM_LIT> ; bool Signed = true ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc )


<s> auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) &&


<s> if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo , <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> if ( REG_P ( * x ) ) mips_sim_wait_reg ( data , mips_sim_insn , * x ) ; return


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & , const MCTargetOptions & ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable


<s> EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = <STR_LIT> ; const GlobalValue * GV = N -> getGlobal ( ) ; return DAG . getTargetGlobalAddress ( GV , DL ,


<s> int regno ; int tr0_used ; if ( ! crtl -> is_leaf ) return - <NUM_LIT> ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - <NUM_LIT> ; if ( sh_cfun_interrupt_handler_p ( ) ) return


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT>


<s> rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { int arg_mode , regno ; rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( use , <NUM_LIT> ) ) ; if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) { if ( arg_mode == SFmode ) length += <NUM_LIT> ; else length


<s> SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex ( ) ; return


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( )


<s> MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? <NUM_LIT> : next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (