<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) { return Op ; } RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & Ops [ <NUM_LIT> ] , Ops . size ( )


<s> bool <ISA_LIT>BaseTargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt

:: Level OptLevel , JITCodeEmitter & JCE ) {


<s> rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } return


<s> if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt (


<s> break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return NULL ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty


<s> <STR_LIT> AluOperator = static_cast < <STR_LIT> > ( Addr . getOpcode ( ) ) ; LPAC :: AluCode AluCode = LPAC :: isdTo<ISA_LIT>AluCode ( AluOperator ) ; if ( AluCode != LPAC :: UNKNOWN ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand (


<s> static inline unsigned UnknownPadding ( unsigned LogAlign , unsigned KnownBits ) { if ( KnownBits < LogAlign ) return ( <NUM_LIT> << LogAlign ) - ( <NUM_LIT> << KnownBits ) ; return


<s> if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) return new TargetLoweringObjectFileCOFF ( ) ; llvm_unreachable ( <STR_LIT> )


<s> return ( poly64x2_t ) __builtin_neon_vreinterpretv2div8hi ( ( int16x8_t )


<s> __o = __builtin_aarch64_ld3rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; return


<s> if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; unsigned char OpFlags = <NUM_LIT> ; if ( Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc ::


<s> Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { StringRef Flags = <STR_LIT> , Reg = SpecialReg ; if ( Reg . endswith ( <STR_LIT> ) ) { Flags = <STR_LIT> ; Reg = Reg . drop_back ( <NUM_LIT> ) ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N


<s> static SDValue combineFaddFsub ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; bool IsFadd = N -> getOpcode (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask (


<s> void <ISA_LIT>InstPrinter :: printBDLAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { unsigned Base = MI -> getOperand ( OpNum ) .


<s> return ( __m512i ) __builtin_ia32_cvttps2qq512_mask ( ( __v8sf ) __A , ( __v8di ) _mm512_setzero_si512 ( )


<s> return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return


<s> bool <ISA_LIT>AsmParser :: ErrorMissingFeature ( SMLoc IDLoc , uint64_t ErrorInfo , bool MatchingInlineAsm ) { assert ( ErrorInfo && <STR_LIT> ) ; ArrayRef < SMRange > EmptyRanges = None ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseDirective<ISA_LIT>HackELFFlags ( ) { int64_t Flags = <NUM_LIT> ; if ( Parser . parseAbsoluteExpression ( Flags ) ) return TokError ( <STR_LIT> ) ; getTargetStreamer ( ) . emit<ISA_LIT>HackELFFlags


<s> bool <ISA_LIT>AsmParser :: ParseRegisterList ( OwningPtr < <ISA_LIT>Operand > & Op ) { SMLoc S , E ; assert ( Parser . getTok ( ) . is ( AsmToken :: LCurly ) && <STR_LIT> ) ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & RegTok = Parser . getTok ( ) ; SMLoc RegLoc = RegTok . getLoc ( ) ; if ( RegTok . isNot ( AsmToken :: Identifier ) ) return Error ( RegLoc , <STR_LIT> ) ; int RegNum = MatchRegisterName ( RegTok . getString ( ) ) ; if ( RegNum == - <NUM_LIT> ) return Error ( RegLoc , <STR_LIT> ) ; Parser . Lex ( ) ; unsigned RegList = <NUM_LIT> << RegNum ; int HighRegNum


<s> return isInt < <NUM_LIT> > ( MFI . getMaxCallFrameSize ( ) ) && !


<s> return DAG . getTargetConstant ( getV4<ISA_LIT>ShuffleImm ( Mask


<s> UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false


<s> const char * fnname ; HOST_WIDE_INT tsize = cfun -> machine -> frame . total_size ; if ( debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG ) SDB_OUTPUT_SOURCE_LINE ( file , DECL_SOURCE_LINE ( current_function_decl ) ) ; if ( TARGET_MIPS16 && ! TARGET_SOFT_FLOAT && current_function_args_info . fp_code != <NUM_LIT> ) build_mips16_function_stub ( file ) ; if ( ! FUNCTION_NAME_ALREADY_DECLARED ) { fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! flag_inhibit_size_directive ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , fnname ) ; fputs ( <STR_LIT> , file ) ; } assemble_name ( file , fnname


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm0_1020s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg (


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op


<s> add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , retreg ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -= <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_REG ( DImode , <NUM_LIT> ) , gen_rtx_REG ( DImode , MMIX_rO_REGNUM ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ; offset -= <NUM_LIT> ; } offset -= ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = ( stack_space_to_allocate > ( <NUM_LIT> - offset - <NUM_LIT> ) ? ( <NUM_LIT> - offset - <NUM_LIT> ) : stack_space_to_allocate ) ; mmix_emit_sp_add ( -


<s> unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize


<s> void <ISA_LIT>AsmParser :: getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode = false


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; return *


<s> return getImm34Encoding ( MI , OpNo , Fixups ,


<s> if ( TARGET_SHMEDIA ) sh_media_init_builtins


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Word0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( LoIdx , <STR_LIT> ) ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue And0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> __builtin_ia32_storedqusi128_mask ( ( int * ) __P , ( __v4si


<s> if ( config ( ) . options ( ) . hasNow ( ) ) { if ( pFormat . hasGOT ( ) ) reserveOne ( llvm :: ELF :: DT_PLTGOT ) ; } else


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const { return nullptr


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { unsigned Opc ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else assert ( <NUM_LIT>


<s> if ( ! TARGET_AAPCS_BASED ) return ; if ( ! TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT ( decl ) ) DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; else DECL_VISIBILITY ( decl ) =


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack (


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm (

SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> void <ISA_LIT>FastISel :: <ISA_LIT>SimplifyAddress ( Address & Addr , MVT VT , bool & UseOffset , unsigned & IndexReg ) { if ( ! isInt < <NUM_LIT> > ( Addr . Offset ) ) UseOffset = false ; if ( ! UseOffset && Addr . BaseType == Address :: FrameIndexBase ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( ! UseOffset ) { IntegerType * OffsetTy = ( ( VT == <STR_LIT> ) ? Type :: getInt32Ty ( * Context ) : Type :: getInt64Ty ( * Context ) ) ; const ConstantInt * Offset = ConstantInt :: getSigned ( OffsetTy , ( int64_t ) ( Addr . Offset ) ) ; IndexReg = <ISA_LIT>MaterializeInt ( Offset , <STR_LIT> ) ; assert ( IndexReg && <STR_LIT>


<s> static TargetLoweringObjectFile * createTLOF ( <ISA_LIT>TargetMachine & TM ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool is64Bit = Subtarget -> is64Bit ( ) ; if ( Subtarget -> isTargetMacho ( )


<s> void addFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getFPImm ( )


<s> void add ( MachineInstr * MI , unsigned Idx , Color C ) { LastInst = MI ; LastInstIdx = Idx ; LastColor = C ; assert ( ( KillInstIdx == <NUM_LIT> || LastInstIdx < KillInstIdx ) && <STR_LIT> <STR_LIT> ) ; Insts . insert ( MI )


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Align ( Size ) ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; const Align RestAlign = std :: min ( Alignment , Align ( Size ) ) ; for ( auto & It : PendingMembers ) { It . convertToMem ( State . AllocateStack ( Size , Alignment ) ) ; State . addLoc (


<s> RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; return false ; } else if ( Name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = is<ISA_LIT>64 ( ) ? XRegs [ IntVal ] : RRegs [ IntVal ] ; return false ; } else if ( Name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = FRegs [ IntVal ]


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CSel , DAG . getConstant ( Lg2


<s> case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count ? count : sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count


<s> return ( __m512i ) __builtin_ia32_vpopcountq_v8di ( ( __v8di


<s> default : gcc_unreachable ( ) ; } if ( is_sse ) { if ( TARGET_AVX ) { strcpy ( buf , ssep ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , ssep + <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } return buf ; } strcpy ( buf , p ) ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case MULT : case PLUS : if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; } if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; case MINUS : case DIV : if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p


<s> if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> ) { AM . IndexReg


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> Imm = N ; Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT>


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem


<s> bool <ISA_LIT>InstrInfo :: SafeInForbiddenSlot ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) return


<s> tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DImode , & regset ) ; if ( tmp != NULL_RTX ) { operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; } else { SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno % <NUM_LIT> == <NUM_LIT> ? regno + <NUM_LIT> : regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ regno % <NUM_LIT> == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] = tmp ; } } gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) % <NUM_LIT> == <NUM_LIT> ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; } } if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( align [ <NUM_LIT> ] , align [ <NUM_LIT> ] ) ; if ( const_store ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; } if ( gap != <NUM_LIT> ) return false ; if ( ! align_ok_ldrd_strd ( align [ <NUM_LIT> ] , offset ) ) return false ; if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load ) )


<s> void <ISA_LIT>SEInstrInfo :: expandPseudoMTLoHi ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned LoOpc , unsigned HiOpc , bool HasExplicitDef ) const { DebugLoc DL = I -> getDebugLoc ( ) ; const MachineOperand & SrcLo = I -> getOperand ( <NUM_LIT> ) , & SrcHi = I -> getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LoInst = BuildMI ( MBB , I , DL , get ( LoOpc ) ) ; MachineInstrBuilder HiInst = BuildMI ( MBB , I , DL , get ( HiOpc ) ) ; LoInst . addReg ( SrcLo . getReg ( ) , getKillRegState ( SrcLo . isKill ( ) ) ) ; HiInst . addReg ( SrcHi . getReg ( ) , getKillRegState ( SrcHi . isKill ( ) ) ) ; if ( HasExplicitDef ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> )


<s> static bool selectCopy ( MachineInstr & I , const TargetInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } return


<s> if ( insn_type != TYPE_SETCC && insn_type != TYPE_ICMOV && insn_type != TYPE_FCMOV && insn_type != TYPE_IBR ) return false ; if ( ( set = single_set ( dep_insn ) ) != <NUM_LIT> ) { set = SET_DEST ( set ) ; set2 = NULL_RTX ; } else if ( GET_CODE ( PATTERN ( dep_insn ) ) == PARALLEL && XVECLEN ( PATTERN ( dep_insn ) , <NUM_LIT> ) == <NUM_LIT> && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) == SET ) { set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; } else return false ; if ( ! REG_P ( set ) || REGNO ( set ) != FLAGS_REG ) return false ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return false ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) ) ) return false ; return true


<s> const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: aarch64 > X ( The<ISA_LIT>Target ,


<s> poly_int64 final_adjust = cfun -> machine -> frame . final_adjust ; poly_int64 callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx cfi_ops = NULL ; rtx_insn * insn ; HOST_WIDE_INT guard_size = <NUM_LIT> << PARAM_VALUE ( PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE ) ; HOST_WIDE_INT guard_used_by_caller = STACK_CLASH_CALLER_GUARD ; bool can_inherit_p = ( initial_adjust . is_constant ( ) && final_adjust . is_constant ( ) ) && ( ! flag_stack_clash_protection || known_lt ( initial_adjust , guard_size - guard_used_by_caller ) ) ; bool need_barrier_p = maybe_ne ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size , <NUM_LIT> ) ; if ( maybe_gt ( final_adjust , crtl -> outgoing_args_size ) || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } rtx tmp0_rtx = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; rtx tmp1_rtx = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( frame_pointer_needed && ( maybe_ne ( final_adjust , <NUM_LIT> ) || cfun -> calls_alloca ) ) aarch64_add_offset ( Pmode , stack_pointer_rtx , hard_frame_pointer_rtx , - callee_offset , tmp1_rtx , tmp0_rtx , callee_adjust == <NUM_LIT> ) ; else aarch64_add_sp ( tmp1_rtx , tmp0_rtx , final_adjust , true ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( aarch64_simd_decl_p ( cfun -> decl ) ) aarch64_restore_callee_saves ( TFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; else aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || maybe_gt ( initial_adjust , <NUM_LIT> ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( tmp0_rtx , tmp1_rtx , initial_adjust , ( ! can_inherit_p || ! crtl -> is_leaf || df_regs_ever_live_p ( EP0_REGNUM ) ) ) ; if ( cfi_ops


<s> void * _Unwind_GetLanguageSpecificData ( struct _Unwind_Context * context ) { return context


<s> void setHasDynAlloca ( bool v ) { HasDynAlloca = v


<s> if ( CI -> doesNotThrow ( ) ) continue ; insertStateNumberStore ( ParentRegNode , CI , BaseState ) ; } else if ( auto * II = dyn_cast < InvokeInst > ( & I ) ) { LandingPadInst * LPI = II -> getUnwindDest (


<s> while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return nullptr ; } UseIdx = Idx ; return & * II


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) && pred ( subinsn ) ) { * cache = true ; break ; } pop_topmost_sequence (


<s> bool i386_pe_type_dllimport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && ( DECL_DECLARED_INLINE_P ( decl ) || DECL_TEMPLATE_INSTANTIATION ( decl ) || DECL_ARTIFICIAL ( decl ) ) ) return false ; else if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE && DECL_VIRTUAL_P ( decl ) ) { if ( DECL_INITIAL ( decl ) ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , decl ) ; if ( decl == CLASSTYPE_KEY_METHOD ( DECL_CONTEXT ( decl ) ) ) warning (


<s> MCAsmBackend * llvm :: createThumbLEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple

& TT , StringRef CPU , const MCTargetOptions & Options ) {


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned


<s> if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT>


<s> unsigned ATIndex = AssemblerOptions . back ( ) -> getATRegNum ( ) ; if ( ATIndex == <NUM_LIT> ) { reportParseError ( Loc , <STR_LIT> ) ; return <NUM_LIT>


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << ( unsigned ) ( Binary >> <NUM_LIT>


<s> if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && !

GV -> hasCommonLinkage ( ) ) ) return false ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF .


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . isAIXABI ( ) ) return LowerGlobalTLSAddressAIX ( Op , DAG ) ; return LowerGlobalTLSAddressLinux ( Op


<s> bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEsingle , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( IntVal , getContext ( ) ) , S , Parser . getTok ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val = Tok . getIntVal ( ) ; Parser . Lex ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } double RealVal = <STR_LIT> ( Val ) ; Val = APFloat ( APFloat :: IEEEdouble , RealVal ) . bitcastToAPInt ( ) . getZExtValue ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , Parser . getTok ( ) . getLoc


<s> const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> ,


<s> TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_PURE ) != <NUM_LIT> ) { DECL_PURE_P ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_FP ) != <NUM_LIT> ) { TREE_NOTHROW ( t ) = <NUM_LIT> ; if ( flag_rounding_math ) { DECL_PURE_P ( t ) = <NUM_LIT> ; DECL_IS_NOVOPS ( t )


<s> if ( Function * F = CI -> getCalledFunction ( ) ) { unsigned Opcode ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : case LibFunc :: copysignl : continue ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc :: ceil : case LibFunc :: ceilf : case LibFunc :: ceill : Opcode = <STR_LIT> ; break ; case LibFunc :: rint : case LibFunc :: rintf : case LibFunc :: rintl : Opcode = <STR_LIT> ; break ; case LibFunc :: trunc : case LibFunc :: truncf : case LibFunc :: truncl : Opcode = <STR_LIT> ; break ; } MVT VTy = TLI -> getSimpleValueType ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( VTy ==


<s> case Instruction :: Add : return ScalarBits * Ty -> getVectorNumElements ( ) >= <NUM_LIT> ; case Instruction :: ICmp : return ( ScalarBits < <NUM_LIT> ) && ( ScalarBits * Ty -> getVectorNumElements ( ) >= <NUM_LIT> ) ; case Instruction :: FCmp : return Flags . NoNaN ; default : llvm_unreachable ( <STR_LIT> ) ; } return false


<s> <ISA_LIT>PLT :: <ISA_LIT>PLT ( LDSection & pSection , <ISA_LIT>GOT & pGOTPLT ) : PLT ( pSection ) , m_GOT (


<s> TOut . emitRRI ( FinalOpcode , DReg , SReg , ShiftValue , Inst . getLoc ( ) , STI ) ; return false ; } if ( has<ISA_LIT>64 ( ) ) { if ( ImmValue == <NUM_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , <NUM_LIT> , Inst . getLoc ( ) , STI ) ; return false ; } switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ( ImmValue >= <NUM_LIT> ) && ( ImmValue <= <NUM_LIT> ) ) { FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; } if ( ImmValue == <NUM_LIT> ) { FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; } if ( ( ImmValue >= <NUM_LIT> ) && ( ImmValue <= <NUM_LIT> ) ) { FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; } break ; case <STR_LIT> : if ( ( ImmValue >= <NUM_LIT> ) && ( ImmValue <= <NUM_LIT> ) ) { FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; } if ( ImmValue == <NUM_LIT> ) { FirstShift = <STR_LIT> ; SecondShift =


<s> static bool isFMA3 ( unsigned Opcode ) { return getFMA3Group ( Opcode ) !=


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) )


<s> unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; } switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; } unsigned NumOps = Desc -> getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc -> getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MachineOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) { VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; CurOp ++ ; } if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( )


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == <STR_LIT> ) || ( FlagSfiStore && N -> getOpcode ( ) == <STR_LIT> ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N )


<s> static bool arm_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode ,


<s> TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , <STR_LIT> , true ) ; return


<s> vmlal_high_u8 ( uint16x8_t a , uint8x16_t b , uint8x16_t c ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { MRI -> constrainRegClass ( NewReg , MRI -> getRegClass ( ( * I ) -> getReg ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << PrintReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> ,


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( x


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T


<s> Inst . addOperand ( MCOperand :: CreateReg ( getGPRMM16Reg


<s> for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use . getReg ( ) , ForwardedReg ) ; } ) ) continue ; MIRBuilder . buildCopy ( ForwardedReg , Register ( F . VReg ) ) ; MIB . addReg ( ForwardedReg , RegState :: Implicit ) ; } } if ( ! IsSibCall ) { MIB -> getOperand ( <NUM_LIT> ) . setImm ( FPDiff ) ; CallSeqStart . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; MF . getFrameInfo ( )


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( )


<s> } auto InsertPt = Pred -> getFirstTerminator ( ) ; unsigned TargetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { auto AddrI = BuildMI ( * Pred , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , TargetReg ) . addMBB ( & MBB ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { auto AddrI = BuildMI ( * Pred , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , TargetReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } TargetAddrSSA . AddAvailableValue ( Pred , TargetReg ) ; } unsigned TargetReg = TargetAddrSSA . GetValueInMiddleOfBlock ( & MBB ) ; MBB . setHasAddressTaken ( ) ; auto InsertPt = MBB . SkipPHIsLabelsAndDebug ( MBB . begin ( ) ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addMBB ( & MBB ) ; ++ NumInstsInserted ; ( void ) CheckI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CheckI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { unsigned AddrReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto AddrI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , AddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addReg ( AddrReg , RegState :: Kill ) ; ++ NumInstsInserted


<s> if ( Src . getValueType ( ) . getScalarSizeInBits ( ) < <NUM_LIT> ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Src . getValueType ( ) ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) { if ( BitNo . getOpcode ( ) == <STR_LIT> && BitNo -> hasOneUse ( ) ) BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo . getOperand ( <NUM_LIT> ) ) ) ; else BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , NumSubElts ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( SI -> getPointerOperand ( ) , Int8Ptr ) ) ; Type * Tys [ ] = { Int8Ptr , SubVecTy } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , getSequentialMask ( Builder , NumSubElts * i , NumSubElts ) ) ) ; Ops . push_back ( Builder . getInt32 ( SI -> getAlignment ( ) ) ) ; Builder . CreateCall ( VstNFunc ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( Subtarget . getFrameLowering ( ) -> getReturnSaveOffset ( ) , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG


<s> Changed = true ; const TargetRegisterClass * SrcRC = IsVRReg ( SrcMO . getReg ( ) , MRI ) ? & <STR_LIT> : & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVRReg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( IsVRReg ( SrcMO . getReg ( ) , MRI ) ? <STR_LIT> : <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = IsVRReg ( DstMO . getReg ( ) , MRI ) ? & <STR_LIT> : & <STR_LIT>


<s> int Lo = ( int ) ( EmittedAddr & <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Hi ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Lo ) ; JCE . emitWordLE ( <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , nullptr , Name ) ; assert ( GV -> getType ( ) == GVTy &&


<s> static bool isUNPCKL_v_undef_Mask ( ArrayRef < int > Mask , EVT VT , bool HasInt256 ) { unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; if ( NumElts == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = l * NumLaneElts ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j


<s> SDValue TrueOpnd = N -> getOperand ( <NUM_LIT> ) ; SDValue FalseOpnd = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Cond . getOpcode ( ) != <STR_LIT> || TrueOpnd . getOpcode ( ) != <STR_LIT> || FalseOpnd . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Cond . hasOneUse ( ) || TrueOpnd . hasOneUse ( ) || FalseOpnd . hasOneUse ( ) ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TrueOpnd , FalseOpnd ) ; break ; } SDValue CmpOpnd1 = Cond . getOperand ( <NUM_LIT> ) ; SDValue CmpOpnd2 = Cond . getOperand ( <NUM_LIT> ) ; if ( TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 && TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 ) { return DAG . getNode ( <STR_LIT> , dl , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ,

CmpOpnd1 , CmpOpnd2 , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return


<s> void <ISA_LIT>InstPrinter :: printImmSVE ( T Value , raw_ostream & O ) { std :: make_unsigned_t < T > HexValue = Value ; if ( getPrintImmHex ( ) ) O << '#' << formatHex ( ( uint64_t ) HexValue ) ; else O << '#' << formatDec ( Value ) ; if ( CommentStream


<s> machine = ggc_cleared_alloc < machine_function > ( ) ; return


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ &&

! IsN64 ) return getAddrNonPIC ( Op , DAG ) ;


<s> break ; case <NUM_LIT> : d . op1 = op0 ; d . one_vector_p = true ; break ; } d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? <NUM_LIT> : <NUM_LIT> , nelt ) ; if ( ! d . testing_p ) return arm_expand_vec_perm_const_1 ( & d ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence (


<s> bool <ISA_LIT>AIXAsmPrinter :: doFinalization ( Module & M ) { for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return <ISA_LIT>AsmPrinter :: doFinalization ( M


<s> if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType


<s> MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue FPOdd = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; SDValue FPEven = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Offset0 ) ) Offset1 = CurDAG -> getTargetConstant ( C -> getSExtValue ( ) + <NUM_LIT> , <STR_LIT> ) ; else return NULL ; if ( TM . getTargetData ( ) -> isBigEndian ( ) ) std :: swap ( Offset0 , Offset1 ) ; SDValue Ops0 [ ] = { FPEven , Offset0 , Base , Chain } ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops0 , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Chain . getNode ( ) ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; SDValue Ops1 [ ] = { FPOdd , Offset1 , Base , Chain } ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops1 , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Chain . getNode ( ) ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Chain ) ; return Chain .


<s> gcc_assert ( LABEL_P ( operands [ <NUM_LIT> ] ) ) ; length = get_attr_length ( insn ) ; if ( length <= <NUM_LIT> ) { return branch_if_true ; } rtx_code_label * not_taken = gen_label_rtx ( ) ; taken = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] =


<s> unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register


<s> return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case


<s> const ArrayRef < MCPhysReg > ArgRegs = ABI . GetVarArgRegs ( ) ; unsigned Idx = State . getFirstUnallocated ( ArgRegs ) ; unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; MVT RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = RoundUpToAlignment ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC


<s> bool isArgumentHandler ( ) const override { return


<s> unsigned T9 = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , RA ) . addReg ( TargetReg )


<s> auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Subtarget . isLittleEndian ( ) ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( *


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_extractsubreg ( MVT RetVT , unsigned Op0 , bool Op0IsKill , uint32_t Idx ) { unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( Op0 ) && <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg )

. addReg ( Op0 , getKillRegState ( Op0IsKill ) , Idx ) ) ;


<s> unsigned inc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg (


<s> int64_t CallTarget = Opers . getMetaOper ( PatchPointOpers :: TargetPos ) . getImm ( ) ; if ( CallTarget ) { assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; unsigned ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> isELFv2ABI ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; } } else if ( CalleeMO . isGlobal ( ) ) { const GlobalValue * GValue = CalleeMO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create ( MOSymbol , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( SymVar ) ) ; EncodedBytes +=


<s> void addBarrierOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG ,


<s> if ( MO . isReg ( ) ) { if ( MO . isUse ( ) ) { CurrentReads . insert ( MO . getReg ( ) ) ; } if ( MO . isDef ( ) ) { CurrentWrites . insert ( MO . getReg ( ) ) ; OrigWrites . insert ( MO . getReg ( ) ) ; } } } set_intersect ( CurrentReads , PendingRegWrites ) ; set_intersect ( CurrentWrites , PendingRegWrites ) ; if ( ! ( CurrentReads . empty ( ) && CurrentWrites . empty ( ) ) ) { CurrentInsn = BuildMI ( MBB , CurrentInsn , CurrentInsn -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) , <NUM_LIT> ) ; PendingRegWrites = OrigWrites ; Changed = true ; StopBitsAdded ++ ; } else { set_union ( PendingRegWrites , OrigWrites ) ; } } return Changed


<s> virtual bool EmitValueToOffset ( const MCExpr * Offset , unsigned char Value = <NUM_LIT> ) {


<s> vec_uint4 mask ; neg_b = ( vec_uint4 ) vec_sub ( vec_splat_s32 ( <NUM_LIT> ) , ( vec_int4 ) ( b ) ) ; mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_andc ( vec_sr ( ( vec_uint4 ) (


<s> if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugInstr ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock * S : MBB . successors ( ) ) if ( S -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugInstr ( ) ) -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand


<s> SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , dl , DAG ) ; SDValue CCVal = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue FalseValLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueValLo = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , TrueValLo , FalseValLo , CCVal , Cmp ) ; SDValue FalseValHi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue TrueValHi = Opc == <STR_LIT> ? DAG . getNode ( Opc , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , dl , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , TrueValHi , FalseValHi , CCVal , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> return __builtin_loongson_paddh_u ( s , t


<s> return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const


<s> auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Code , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( Op ) , Node -> getVTList ( )

, Ops , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ;


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned CurByValIndex = CCInfo . getInRegsParamsProcessed ( ) ; ByValStoreOffset = RoundUpToAlignment ( ByValStoreOffset , Flags . getByValAlign ( ) ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , CurOrigArg , CurByValIndex , Ins [ VA . getValNo ( ) ] . PartOffset , VA . getLocMemOffset ( ) , Flags . getByValSize ( ) , true , ByValStoreOffset , TotalArgRegsSaveSize ) ; ByValStoreOffset += Flags . getByValSize ( ) ; ByValStoreOffset = std :: min ( ByValStoreOffset , <NUM_LIT> ) ; InVals . push_back ( DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ) ; CCInfo . nextInRegsParam ( ) ; } else { unsigned FIOffset = VA . getLocMemOffset ( ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , FIOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } lastInsIndex = index ; } } } if ( isVarArg ) VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , CCInfo . getNextStackOffset ( ) , TotalArgRegsSaveSize ) ; AFI -> setArgumentStackSize ( CCInfo .


<s> else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex (


<s> bool mips_store_by_pieces_p ( unsigned HOST_WIDE_INT size , unsigned int align ) { if ( align <= BITS_PER_UNIT ) return size <


<s> assert ( SrcReg . isValid ( ) && <STR_LIT> ) ; assert ( To && <STR_LIT> ) ; assert ( SubReg && <STR_LIT> ) ; MachineIRBuilder MIB ( I ) ; auto SubRegCopy = MIB . buildInstr ( TargetOpcode :: COPY , { To } , { } ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( SubRegCopy . getReg ( <NUM_LIT>


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG


<s> if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( AllowModify && isUncondBranchOpcode ( LastOpc ) && MBB . isLayoutSuccessor ( getBranchDestBlock ( * LastInst ) ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { assert ( ! isUncondBranchOpcode ( LastOpc ) && <STR_LIT> ) ; if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I


<s> bool check ( function_checker & c ) const override { return c . require_immediate_range ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> if ( BaseOp1 . getType ( ) != BaseOp2 . getType ( ) ) return false ; assert ( ( BaseOp1 . isReg ( ) || BaseOp1 . isFI ( ) ) && <STR_LIT> ) ; if ( BaseOp1 . isReg ( ) && BaseOp1 . getReg ( ) != BaseOp2 . getReg ( ) ) return false ; if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) { assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 >= Offset2 ) && <STR_LIT> ) ; const MachineFrameInfo & MFI = FirstLdSt . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; return shouldClusterFI ( MFI , BaseOp1 . getIndex ( ) , Offset1 , FirstOpc , BaseOp2 . getIndex ( ) , Offset2 , SecondOpc ) ; } assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 <= Offset2 ) &&


<s> static SDValue performSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( SDValue Split = splitStores ( N , DCI , DAG , Subtarget ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; if ( SDValue Store = foldTruncStoreOfExt ( DAG , N ) ) return Store ; return SDValue (


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_64AsmBackend ( const Target &


<s> } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg


<s> bool isMem ( ) const override { return false


<s> VFPThumb2PostEncoder ( const MCInst & MI , unsigned EncodedValue ) const { if ( isThumb2 ( )


<s> void <ISA_LIT>CompilationCallbackC ( intptr_t StubAddr ) { intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) StubAddr ) ; int Hi = ( ( unsigned ) NewVal & <NUM_LIT> ) >> <NUM_LIT> ; if ( ( NewVal & <NUM_LIT> ) != <NUM_LIT> ) Hi ++ ; int Lo = ( int ) ( NewVal & <NUM_LIT> ) ; * ( intptr_t * ) ( StubAddr ) = <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Hi ; * ( intptr_t * ) ( StubAddr + <NUM_LIT> ) = <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> | Lo ; * ( intptr_t * ) ( StubAddr + <NUM_LIT> ) = <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ; * ( intptr_t * ) ( StubAddr +


<s> switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } return Opc


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ST -> hasNEON ( ) && ValTy ->


<s> if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::

createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ;


Zeroable , Subtarget , DAG ) ) return Blend ;


<s> EVT ValVT ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset (


<s> if ( ! Subtarget -> hasFPARMv8 ( ) ) return <STR_LIT> ; if ( ConstraintVT . isFloatingPoint ( ) )


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N


<s> <ISA_LIT>Subtarget :: ~ <ISA_LIT>Subtarget ( ) { delete getSpecialRegisters (


<s> int uses_TOC ( ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ) == UNSPEC && XINT (

XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> bool isMovKSymbolG3 ( ) const { static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G3 } ; return isMovWSymbol ( Variants )


<s> if ( generateSignBits ( V ) ) return false ; auto * I = cast < Instruction > ( V ) ; if ( I -> hasOneUse ( ) && isSink ( * I -> use_begin ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return true


<s> } SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT>


<s> if ( ST . in<ISA_LIT>16Mode ( ) ) RC = ( const TargetRegisterClass * ) & <STR_LIT> ; else RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * )


<s> HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & <NUM_LIT> ; if ( ( value != <NUM_LIT> ) && ( ( value & ( value - <NUM_LIT> ) ) ==


<s> if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; return true ; } return false


<s> InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI , AA ) ; MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register (


<s> for ( MCSubRegIterator SubRegIt ( Reg , MCRegInfo , true ) ; SubRegIt . isValid ( ) ; ++ SubRegIt ) { unsigned CurrentSubReg = * SubRegIt ; unsigned EncVal = MCRegInfo -> getEncodingValue ( CurrentSubReg ) ; Value |= <NUM_LIT> << EncVal ; if ( GPR32RegClass -> contains ( CurrentSubReg ) || GPR64RegClass -> contains ( CurrentSubReg ) ) ri_gprmask |= Value ; else if ( COP0RegClass -> contains ( CurrentSubReg ) )


<s> return parseMSARegs ( Operands , ( int ) <STR_LIT>


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & Ctx_

, const MCSubtargetInfo & sti , bool IsLittle ) :


<s> return new <ISA_LIT>PostSelectOptimize (


<s> if ( ! MemOp . isUnordered ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlign ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlign ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD


<s> bool hasFastHorizontalOps ( ) const { return HasFastHorizontalOps


<s> break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; CondReg = <STR_LIT> ; break ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> ) return false ; unsigned Arg2 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg2 == <NUM_LIT> ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( Arg1 ) . addReg ( Arg2 ) ) ; if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned MovCCOpc = isThumb ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant (


<s> off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM + local_cum . aapcs_nvrn ; for ( i = <NUM_LIT> ; i < vr_saved ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , vr_start + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) +


<s> if ( optimize > <NUM_LIT> && TREE_CONSTANT ( decl ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , <NUM_LIT> )


<s> } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> , false , true ) , DAG . getConstant ( End , DL , <STR_LIT> , false , true ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> MCSymbol * <ISA_LIT>TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine ( ) . getMCAsmInfo


<s> bool Modified = false ; ( void ) std :: initializer_list < int > { Modified |= std :: get < ThunkInserterT > ( ThunkInserters ) . run (


<s> void setGlobalBaseReg ( unsigned Reg ) { GlobalBaseReg =


<s> bool InITBlock ( ) { if ( SP ) return SP -> ITCounter > <NUM_LIT> ; return false


<s> static unsigned getReg ( const MCDisassembler * D


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; operand = <STR_LIT> + LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; } unsigned mfNum = MI -> getParent ( ) -> getParent ( ) -> getFunctionNumber ( ) ; unsigned bbNum = MI -> getParent ( ) -> getNumber ( ) ; O << '\n' << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> ; O << <STR_LIT> << mfNum << '_' << bbNum <<


<s> case 'u' : if ( type -> isFloatingPointTy ( ) ) weight = CW_SpecificReg ; break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget -> hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'x' : case 'Y' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasFp256 ( ) ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) { machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) mode = MIN_MODE_VECTOR_FLOAT ; else mode = MIN_MODE_VECTOR_INT ; for ( ; mode != VOIDmode ; mode = GET_MODE_WIDER_MODE ( mode ) ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) { if ( size == <NUM_LIT> && ! TARGET_AVX512F ) { static bool warnedavx512f ; static bool warnedavx512f_ret ; if ( cum && cum -> warn_avx512f && ! warnedavx512f ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f = true ; } else if ( in_return && ! warnedavx512f_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f_ret = true ; } return TYPE_MODE ( type ) ; } else if ( size == <NUM_LIT> && ! TARGET_AVX ) { static bool warnedavx ; static bool warnedavx_ret ; if ( cum && cum -> warn_avx && ! warnedavx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx = true ; } else if ( in_return && ! warnedavx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx_ret = true ; } return TYPE_MODE ( type ) ; } else if ( ( ( size == <NUM_LIT> && TARGET_64BIT ) || size == <NUM_LIT> ) && ! TARGET_SSE ) { static bool warnedsse ; static bool warnedsse_ret ; if ( cum && cum -> warn_sse && ! warnedsse ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse = true ; } else if ( ! TARGET_64BIT && in_return && ! warnedsse_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse_ret = true ; } } else if ( ( size == <NUM_LIT> && ! TARGET_64BIT ) && ! TARGET_MMX ) { static bool


<s> default_globalize_label ( stream , name ) ; if ( ! strcmp ( name , <STR_LIT> ) ) arm_main_function =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode (


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; int Idx = ConvertCostTableLookup < MVT > ( NEONVectorSelectTbl , array_lengthof ( NEONVectorSelectTbl ) , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return NEONVectorSelectTbl [ Idx ] . Cost ; std :: pair < unsigned , MVT >

LT = TLI -> getTypeLegalizationCost ( ValTy ) ;


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isBundle ( ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) &&


<s> __inline__ static unsigned long long sh_media_MSUB_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName


<s> void <ISA_LIT>FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog


<s> <ISA_LIT>RedundantCopyElimination ( ) :