<s> if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; MBB . addSuccessor ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG


<s> MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } } if ( MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } } } else { if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Offset = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true , Offset ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } } if ( MBBI != MBB . end ( )


<s> switch ( mode ) { case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) )


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = <ISA_LIT>FrameLowering :: getFramePointerSaveOffset ( is<ISA_LIT>64


<s> if ( Subtarget . has<ISA_LIT>3 ( ) && Subtarget .


<s> insn_op = & insn_data [ icode ] . operand [ nopnds ] ; if ( TREE_CODE ( arg ) == ADDR_EXPR && MEM_P ( DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ) ) opnd = DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ; else opnd = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( opnd , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { if ( ! CONST_INT_P ( opnd ) ) error ( <STR_LIT> , nopnds ) ; else error ( <STR_LIT> <STR_LIT> , nopnds ) ; return const0_rtx ; } opnd = copy_to_mode_reg ( insn_op -> mode , opnd ) ; } if ( ! void_func && nopnds == <NUM_LIT> && ! strcmp ( insn_op -> constraint , <STR_LIT> ) && insn_op -> mode == tmode && REG_P ( opnd ) && ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( opnd , tmode ) ) target = op [ <NUM_LIT> ] = opnd ; op [ nopnds ++ ] =


<s> else if ( Subtarget . usesFunctionDescriptors ( ) ) prepareDescriptorIndirectCall ( DAG , Callee , Glue , Chain , CallSeqStart , CS , dl , hasNest , Subtarget ) ; else prepareIndirectCall ( DAG , Callee , Glue , Chain , dl ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; buildCallOperands ( Ops , CallConv , dl , isTailCall , isVarArg , isPatchPoint , hasNest , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget , isIndirect ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ; Chain = DAG . getNode ( CallOpc


<s> SDValue Callee = DAG . getTargetExternalFunctionSymbol ( <STR_LIT> , <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getWindowsStackProbePreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> ,


<s> RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { if ( ValVT . isVector ( ) && ValVT . getVectorElementType ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getBitcast ( VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget . is64Bit ( ) ) { if ( ValVT == <STR_LIT>


<s> using namespace TargetOpcode ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0


<s> return Opc != <STR_LIT> && Opc != TargetOpcode :: EXTRACT_SUBREG && Opc

!= <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ;


<s> machine_mode mode = GET_MODE ( x ) ; return VOIDmode == mode ? x : simplify_gen_subreg ( int_mode_for_mode ( mode ) . require


<s> else if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; if ( Flags . isByVal ( ) ) { unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > PtrByteSize ) { if ( BVAlign % PtrByteSize != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; Align = BVAlign ; } } if ( Flags . isInConsecutiveRegs ( ) ) { if ( Flags . isSplit ( ) && OrigVT != <STR_LIT> ) Align = OrigVT . getStoreSize ( ) ; else Align = ArgVT . getStoreSize (


<s> return ( __m128 ) __builtin_ia32_movss ( ( __v4sf ) __A , (


<s> static const unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler ::


<s> int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy


<s> else { char buf [ <NUM_LIT> ] ; const char * label_name ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , label_name


<s> const <ISA_LIT>_64RelType Type = getType64 ( Kind , Modifier , IsPCRel ) ; return getRelocType64 ( Ctx , Fixup . getLoc ( )


<s> uint64_t Val = - MaxAlign ; unsigned AndOp = getANDriOpcode ( Uses64BitFramePtr , Val ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Reg ) . addReg ( Reg ) . addImm ( Val ) . setMIFlag (


<s> unsigned BitSize ; bool HasAnyUndefs ; if ( BV -> isConstantSplat ( APVal , APUndef , BitSize , HasAnyUndefs , <NUM_LIT> ) ) if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return CFP -> getValueAPF ( ) . isNegZero ( ) ; return false


<s> SDValue Value = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT TheVT = Value . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , Align ( MemSize ) , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; EVT ResVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) ; SDValue Cmp ; if ( IsStrict ) { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> , SDNodeFlags ( ) , Chain , true ) ; Chain = Cmp . getValue ( <NUM_LIT> ) ; } else


<s> for ( re = rs + <NUM_LIT> ; re < <NUM_LIT> && ! call_used_regs [ PR_REG ( re ) ] ; re ++ ) continue ; if ( out_state == <NUM_LIT> ) { fputs ( <STR_LIT> , asm_out_file ) ; out_state = <NUM_LIT> ; } else fputc ( ',' , asm_out_file ) ; if ( re == rs + <NUM_LIT> ) fprintf ( asm_out_file


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> Write32


<s> CheriAddressingModeFolder ( <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) { InstrInfo = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; UseCapTable = TM . getSubtargetImpl ( ) -> useCheriCapTable (


<s> void ix86_override_options_after_change ( void ) { ix86_default_align ( & global_options ) ; ix86_recompute_optlev_based_flags ( & global_options , &


<s> return parseRegister ( Operands , RegGR ,


<s> return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( (

Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == INT32_MIN ;


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState (


<s> bool <ISA_LIT>FastISel :: SelectIToFP ( const Instruction * I , bool IsSigned ) { MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ,


<s> switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool


<s> unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; bool IsPic = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode (

) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ;


<s> inline unsigned even128 ( bool Is32bit


<s> unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( TID . getNumOperands ( ) > OpIdx && ! TID . OpInfo [ OpIdx ] . isPredicate ( ) && ! TID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; emitWordLE ( Binary )


<s> assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg ,


<s> inline vector signed int vec_vcmpgtsw ( vector signed int a1 , vector signed


<s> unsigned <ISA_LIT>ScalarTargetTransformImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! Subtarget ->


<s> case SUBREG : if ( REG_P ( SUBREG_REG ( x ) ) ) { if ( REGNO ( SUBREG_REG ( x ) ) < FIRST_PSEUDO_REGISTER && global_regs [ subreg_regno ( x ) ] ) return true ; return false ; } break ; case REG : regno = REGNO ( x ) ; if ( regno < FIRST_PSEUDO_REGISTER && global_regs [ regno


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b ) ; return __ev_mwumiaa ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> } )


<s> static const MachineInstrBuilder & AddSubReg ( const MachineInstrBuilder & MIB , unsigned Reg , unsigned SubIdx , unsigned State , const TargetRegisterInfo * TRI ) { if ( ! SubIdx ) return MIB . addReg ( Reg ,


<s> case CCValAssign :: AExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) { OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( i + <NUM_LIT> < RVLocs . size ( ) && RVLocs [ i + <NUM_LIT> ] . getLocReg ( ) == VA . getLocReg ( ) ) { SDValue NV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVals [ i + <NUM_LIT> ] ) ; OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , NV ) ; ++ i ; } } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVal , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] =


<s> SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TopPart , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { unsigned Rn = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; return ( Rn << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = get<ISA_LIT>RegisterNumbering ( MO1 . getReg (


<s> unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ; return MI . getOperand (


<s> Triple TT ( TM . getTargetTriple ( ) ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; bool isThumb = TT . getArch ( ) == Triple :: thumb || TT . getArch ( ) == Triple :: thumbeb || TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_v7m || TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_v6m ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) && isThumb )

OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ;


<s> return ( AMSubMode ) ( Mode & <NUM_LIT>


<s> } ; LoadInst * DomLoad = DT -> dominates ( Base , Offset ) ? Base : Offset ; IRBuilder < NoFolder > IRB ( DomLoad -> getParent ( ) , ++ BasicBlock :: iterator ( DomLoad ) ) ; const unsigned AddrSpace = DomLoad -> getPointerAddressSpace ( ) ; Value * VecPtr = IRB . CreateBitCast ( Base -> getPointerOperand ( ) , LoadTy -> getPointerTo ( AddrSpace ) ) ; LoadInst * WideLoad = IRB . CreateAlignedLoad ( LoadTy , VecPtr , Base -> getAlignment ( ) ) ; MoveBefore ( Base -> getPointerOperand ( ) , VecPtr ) ; MoveBefore ( VecPtr , WideLoad ) ; Value * Bottom = IRB . CreateTrunc ( WideLoad , Base -> getType ( ) ) ; BaseSExt -> setOperand ( <NUM_LIT> , Bottom ) ; IntegerType * OffsetTy = cast < IntegerType > ( Offset -> getType ( ) ) ; Value * ShiftVal = ConstantInt :: get ( LoadTy , OffsetTy -> getBitWidth ( ) ) ; Value * Top = IRB . CreateLShr ( WideLoad , ShiftVal ) ; Value * Trunc = IRB . CreateTrunc ( Top , OffsetTy


<s> return ( int64x2_t ) __builtin_neon_vqdmlsl_nv2si ( __a , __b , (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF (


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( const GlobalValue


<s> if ( I . getOpcode ( ) != TargetOpcode :: G_UADDE ) return false ; const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned CarryOutReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Def = MRI . getVRegDef ( CarryInReg ) ; } unsigned Opcode ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_UADDE ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CarryInReg ) ; if ( ! RBI . constrainGenericRegister ( CarryInReg , <STR_LIT> , MRI ) ) return false ; Opcode = <STR_LIT> ; } else if ( auto val = getConstantVRegVal ( CarryInReg , MRI ) ) { if ( * val != <NUM_LIT> ) return false ; Opcode = <STR_LIT> ; } else return


<s> int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par , insn ; offset = <NUM_LIT> ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - <NUM_LIT> ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? <NUM_LIT> : ( sel & SAVRES_REG ) == SAVRES_FPR ? <NUM_LIT> : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + <NUM_LIT> : - <NUM_LIT> ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( <NUM_LIT> + ( ( sel & SAVRES_LR ) ? <NUM_LIT> : <NUM_LIT> ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? <NUM_LIT> : <NUM_LIT> ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG (


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV ,


<s> if ( I . getType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return false ; } ; auto IsHardwareLoopIntrinsic = [ ] ( Instruction & I ) { if ( auto * Call = dyn_cast < IntrinsicInst > ( & I ) ) { switch ( Call -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } return false ; } ; auto ScanLoop = [ & ] ( Loop * L ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( MaybeCall ( I ) || IsHardwareLoopIntrinsic ( I ) ) return false ; } } return true ; } ; for ( auto Inner : * L ) if ( ! ScanLoop ( Inner ) ) return false ; if ( ! ScanLoop ( L ) ) return false ; LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CounterInReg = true ; HWLoopInfo . IsNestingLegal = false ; HWLoopInfo . CountType = Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , <NUM_LIT>


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : continue ; case LibFunc :: copysignl : return true ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc :: ceil : case LibFunc :: ceilf : case LibFunc :: ceill : Opcode = <STR_LIT> ; break ; case LibFunc :: rint : case LibFunc :: rintf : case LibFunc :: rintl : Opcode = <STR_LIT> ; break ; case LibFunc :: round : case LibFunc :: roundf : case LibFunc :: roundl : Opcode = <STR_LIT> ; break ; case LibFunc :: trunc : case LibFunc :: truncf : case LibFunc :: truncl : Opcode = <STR_LIT> ; break ; case LibFunc :: fmin : case LibFunc :: fminf : case LibFunc :: fminl : Opcode = <STR_LIT> ; break ; case LibFunc :: fmax : case LibFunc :: fmaxf : case LibFunc :: fmaxl : Opcode = <STR_LIT> ; break ; } } if ( Opcode ) { auto & DL = CI -> getModule ( ) -> getDataLayout ( ) ; MVT VTy = TLI -> getSimpleValueType ( DL , CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( VTy == <STR_LIT> ) return true ; if ( TLI -> isOperationLegalOrCustom ( Opcode , VTy ) ) continue ; else if ( VTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , VTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst


<s> return createMachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object ::


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn << <NUM_LIT>


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , <STR_LIT>


<s> MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ! Subtarget -> isDarwin ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCSymbolRefExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue = MO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create ( MOSymbol , VK , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT>

) . addExpr ( TlsRef ) . addExpr ( SymVar ) ) ;


<s> MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , <NUM_LIT> , TRI , * ( MBB -> getParent ( ) ) ) ) ; MachineInstr * NewLoad = BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LoadDisp ) . addReg ( <STR_LIT> ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; if ( LoadBase . isReg ( ) ) getBaseOperand ( NewLoad ) . setIsKill ( false ) ; LLVM_DEBUG ( NewLoad -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; auto PrevInstrIt = skipDebugInstructionsBackward ( std :: prev ( MachineBasicBlock :: instr_iterator ( StoreInst ) ) , MBB -> instr_begin ( ) ) ; if ( PrevInstrIt . getNodePtr ( ) ==


<s> const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ! ConstExpr ) return false ; int64_t Value = ConstExpr -> getValue (


<s> PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return false


<s> return ( ( qword ) ( vec_cmpeq ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4

) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> x = gen_reg_rtx ( mode ) ; emit_insn ( gen_iwmmxt_clrdi ( mode == DImode ? x : gen_rtx_SUBREG ( DImode , x


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsADDiu ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { GetInstSeqLs ( ( Imm + <NUM_LIT> ) & <NUM_LIT> , RemSize , SeqLs ) ; AddInstr ( SeqLs , Inst ( ADDiu


) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] =


<s> for ( unsigned i = <NUM_LIT> , e = PushPopMIs . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = PushPopMIs [ i ] ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveFReg ( Reg


<s> Entry . IsSExt = shouldSignExtendTypeInLibCall ( Op . getValueType ( ) , IsSigned ) ; Entry . IsZExt = ! shouldSignExtendTypeInLibCall ( Op . getValueType ( ) , IsSigned ) ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( CalleeName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = RetVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; bool SignExtend = shouldSignExtendTypeInLibCall ( RetVT , IsSigned ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallConv , RetTy , Callee , std :: move ( Args ) ) . setNoReturn ( DoesNotReturn ) . setDiscardResult ( ! IsReturnValueUsed ) . setSExtResult ( SignExtend ) . setZExtResult ( ! SignExtend ) ; return LowerCallTo ( CLI


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; } return Ctx . GetOrCreateTemporarySymbol ( Name . str ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) { unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ,

FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; } if ( Res . getNode ( ) ) Results . push_back (


<s> MI . setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ; if ( IsHigh && ConvertHigh ) MI . getOperand ( <NUM_LIT> ) . setImm ( uint32_t ( MI

. getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T , OSABI


<s> bool <ISA_LIT>AsmParser :: cvtLdrdPre ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst ,


<s> if ( T -> isStructTy ( ) ) { auto StructT = cast < StructType > ( T ) ; for ( unsigned i = <NUM_LIT> , e = StructT -> getNumElements ( ) ; i != e ; ++ i ) if ( StructT -> getElementType ( i ) != StructT -> getElementType ( <NUM_LIT> ) ) return false ; return isSupportedType ( DL , TLI , StructT -> getElementType ( <NUM_LIT> ) ) ; } EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ; unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return VT .


<s> if ( Subtarget . isAIXABI ( ) ) { assert ( ! Subtarget . hasAltivec ( ) && <STR_LIT> ) ; return TM . is<ISA_LIT>64 ( ) ? CSR_AIX64_RegMask : CSR_AIX32_RegMask ; } if ( CC == CallingConv :: Cold ) { return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec (

) ? CSR_SVR32_ColdCC_Altivec_RegMask : CSR_SVR32_ColdCC_RegMask ) ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock & FMBB ,

unsigned NumCyclesF , unsigned ExtraPredCyclesF , const BranchProbability & Probability ) const {


<s> else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) ) return true ; return false


<s> if ( flags & SectionFlags :: Code ) Flags += 'x' ; if ( flags & SectionFlags ::


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( JT ) , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget


<s> neg = ! neg ; } res = udivmodsi4 ( a , b , <NUM_LIT> ) ; if ( neg ) res = - res ; return res


<s> static bool MSA3OpIntrinsicToGeneric ( MachineInstr & MI , unsigned Opcode , MachineIRBuilder & MIRBuilder , const <ISA_LIT>Subtarget & ST ) { assert ( ST . hasMSA ( ) && <STR_LIT> ) ; MIRBuilder . buildInstr ( Opcode ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add (


<s> void function_builder :: register_function_group (


<s> if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ; DwarfFDESymbolsUseAbsDiff = T . isMacOSX ( ) && ! T . isMacOSXVersionLT


<s> int mmix_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ATTRIBUTE_UNUSED ) { return


<s> assert ( RegNo < N && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Regs [ RegNo ] ) ) ; return MCDisassembler


<s> auto & LoadStoreBuilder = getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s1 , p0 , <NUM_LIT> , <NUM_LIT> } , { s8 , p0 , <NUM_LIT> , <NUM_LIT> } , { s16 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . unsupportedIfMemSizeNotPow2 ( ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PTR_ADD ) . legalFor ( { { p0 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2Base ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalForTypesWithMemDesc ( { { s64 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . maxScalar ( <NUM_LIT> , s32 ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } , Lower ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . customFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . customForCartesianProduct ( { s1 } , { s32 , s64 } ) ; if ( AEABI ( ST ) )


<s> case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return


<s> const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; bool MatchExact = ( CallerBits & ~ InlineFeatureWhitelist ) == ( CalleeBits


<s> SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) )

Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg


<s> int Index = matchCPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchACRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128RegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128CtrlRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) .


<s> void <ISA_LIT>InstrInfo :: replaceBranchWithTailCall ( MachineBasicBlock & MBB , SmallVectorImpl < MachineOperand > & BranchCond , const MachineInstr & TailCall ) const { assert ( canMakeTailCallConditional ( BranchCond , TailCall ) ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; assert ( BranchCond . size ( ) ==


<s> return ( ( vec_double2 ) ( si_rotqmby ( ( qword ) (


<s> Imm &= ( <NUM_LIT> << Bits ) - <NUM_LIT> ; Imm += Offset ; Imm += AdjustOffset ; Inst . addOperand ( MCOperand :: createImm ( Imm


<s> LLVMContext & Ctx = PN -> getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( PN ) ; PHINode * NPN = Builder . CreatePHI ( RequiredType , PN -> getNumIncomingValues ( ) ) ; Worklist . push_back ( PN ) ; for ( unsigned I = <NUM_LIT> ; I < PN -> getNumIncomingValues ( ) ; I ++ ) { auto * Reinterpret = cast < Instruction > ( PN -> getIncomingValue ( I ) ) ; NPN -> addIncoming ( Reinterpret -> getOperand ( <NUM_LIT> ) , PN -> getIncomingBlock ( I ) ) ; Worklist . push_back ( Reinterpret ) ; } return IC . replaceInstUsesWith ( II , NPN


<s> case V2SFmode : case V2SImode : if ( mmx_ok ) { tmp = gen_reg_rtx ( GET_MODE_INNER ( mode ) ) ; ix86_expand_vector_extract ( true , tmp , target , <NUM_LIT> - elt ) ; if ( elt == <NUM_LIT> ) tmp = gen_rtx_VEC_CONCAT ( mode , tmp , val ) ; else tmp = gen_rtx_VEC_CONCAT ( mode , val , tmp ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; return ; } break ; case V2DFmode : case V2DImode : { rtx op0 , op1 ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( <NUM_LIT> - elt ) ) ) ; tmp = gen_rtx_VEC_SELECT ( inner_mode , target , tmp ) ; if ( elt == <NUM_LIT> ) op0 = val , op1 = tmp ; else op0 = tmp , op1 = val ; tmp = gen_rtx_VEC_CONCAT ( mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , tmp ) ) ; } return ; case V4SFmode : switch ( elt ) { case <NUM_LIT> : use_vec_merge = true ; break ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; emit_insn ( gen_sse_unpcklps ( target , target , target ) ) ; ix86_expand_vector_set ( false , target , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; ix86_expand_vector_set ( false , tmp , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; case <NUM_LIT> : tmp = copy_to_reg ( target ) ; ix86_expand_vector_set ( false , tmp , val , <NUM_LIT> ) ; emit_insn ( gen_sse_shufps_1 ( target , target , tmp , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> + <NUM_LIT> ) ) ) ; return ; default : gcc_unreachable ( ) ; } break ; case V4SImode : if ( elt == <NUM_LIT> ) { use_vec_merge = true ; break ; } if ( TARGET_SSE2 ) { rtx order [ <NUM_LIT> ] ; order [ <NUM_LIT> ] = GEN_INT ( elt ) ; order [ <NUM_LIT> ] = const1_rtx ; order [ <NUM_LIT> ] = const2_rtx ; order [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; order [ elt ] = const0_rtx ; emit_insn ( gen_sse2_pshufd_1 ( target , target , order [ <NUM_LIT> ] , order [ <NUM_LIT> ] , order [ <NUM_LIT> ] , order [


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> V = ConstantExpr :: getICmp ( CmpInst :: ICMP_SGT , Constant :: getNullValue ( IntTy )


<s> insertDefsUses ( Slot , RegDefs , RegUses ) ; bool SawLoad = false ; bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) )


<s> const unsigned DivMulSeqCost = <NUM_LIT> ; const unsigned SDivPow2Cost = <NUM_LIT> ; bool SignedDivRem = Opcode == Instruction :: SDiv || Opcode == Instruction :: SRem ; bool UnsignedDivRem = Opcode == Instruction :: UDiv || Opcode == Instruction :: URem ; bool DivRemConst = false ; bool DivRemConstPow2 = false ; if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( ! Ty -> isVectorTy ( ) ) { if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) return <NUM_LIT> ; if ( Opcode == Instruction :: FRem ) return LIBCALL_COST ; if ( Args . size ( ) == <NUM_LIT> && ST -> hasMiscellaneousExtensions3 ( ) ) { if ( Opcode == Instruction :: Xor ) { for ( const Value * A : Args ) { if ( const Instruction * I = dyn_cast < Instruction > ( A ) ) if ( I -> hasOneUse ( ) && ( I -> getOpcode ( ) == Instruction :: And || I -> getOpcode ( ) == Instruction :: Or || I -> getOpcode ( ) == Instruction :: Xor ) ) return <NUM_LIT> ; } } else if ( Opcode == Instruction :: Or || Opcode == Instruction :: And ) { for ( const Value * A : Args ) { if ( const Instruction * I = dyn_cast < Instruction > ( A ) ) if ( I

-> hasOneUse ( ) && I -> getOpcode ( ) == Instruction :: Xor ) return <NUM_LIT> ;


<s> unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = SelectPairHalf ( NumElts , M , i ) ; unsigned Idx = WhichResult *


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg


<s> if ( parseRegister ( Operands ) == MatchOperand_Success ) return false ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) if ( parseBaseRegImm ( Operands ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) return false ; Error ( getLoc ( ) , <STR_LIT>


<s> call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) length += <NUM_LIT> ; else if ( TARGET_64BIT && ! local_call ) length += <NUM_LIT> ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += <NUM_LIT> ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && local_call ) ) { length += <NUM_LIT> ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += <NUM_LIT> ; } else { length += <NUM_LIT> ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += <NUM_LIT> ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += <NUM_LIT> ; if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += <NUM_LIT> ; } } return


<s> return convReg ( BusyRegs [ REG_OFFSET_SHADOW


<s> } } else { Ops [ I ] = getGeneralPermuteNode ( DAG , DL , SubOps , NewBytes ) ; for ( unsigned J = <NUM_LIT> ; J < <STR_LIT> ; ++ J ) if ( NewBytes [ J ] >= <NUM_LIT> ) Bytes [ J ] = I * <STR_LIT> + J ; } } } if ( Stride > <NUM_LIT> ) { Ops [ <NUM_LIT> ] = Ops [ Stride ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= int ( <STR_LIT> ) ) Bytes [ I ] -= ( Stride - <NUM_LIT> ) * <STR_LIT> ; } unsigned OpNo0 , OpNo1 ; SDValue Op ; if ( const Permute * P = matchPermute ( Bytes , OpNo0 , OpNo1 ) ) Op = getPermuteNode ( DAG , DL , * P , Ops [ OpNo0 ] , Ops [ OpNo1 ] ) ; else Op = getGeneralPermuteNode ( DAG , DL ,


<s> void Emitter < CodeEmitter > :: emitWordLE ( unsigned Binary ) { DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; llvm :: dbgs ( ) . write_hex ( Binary ) <<


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; RegDefMaps [ TargetRegisterInfo :: isVirtualRegister ( Reg ) ] [ Reg ] = & MI ; } unsigned Latency = TSchedModel . computeInstrLatency ( & MI ) ; DepthMap [ & MI ] = { MIDepth += Latency , MIDepthOpt += Latency } ; MaxDepth . Depth = std :: max ( MaxDepth . Depth , MIDepth ) ; MaxDepth . OptDepth = std :: max ( MaxDepth . OptDepth , MIDepthOpt ) ; } } } unsigned Diff [ LoopIterations ] = { LoopDepth [ <NUM_LIT> ] . Depth - LoopDepth [ <NUM_LIT> ] . OptDepth , LoopDepth [ <NUM_LIT> ] . Depth - LoopDepth [ <NUM_LIT> ] . OptDepth } ; if ( Diff [ <NUM_LIT> ] < GainCycleThreshold ) return false ; bool WorthOptLoop = false ; if ( Diff [ <NUM_LIT> ] == Diff [ <NUM_LIT> ] ) WorthOptLoop = Diff [ <NUM_LIT> ] * <NUM_LIT> >= LoopDepth [ <NUM_LIT> ] . Depth ; else if ( Diff [ <NUM_LIT> ] > Diff [ <NUM_LIT> ] ) WorthOptLoop = ( Diff [ <NUM_LIT> ] - Diff [ <NUM_LIT> ] ) * <NUM_LIT> >= ( LoopDepth [ <NUM_LIT> ] . Depth - LoopDepth [ <NUM_LIT> ] . Depth ) && ( Diff [ <NUM_LIT> ] * <NUM_LIT> >= LoopDepth [ <NUM_LIT> ] . Depth ) ; if ( ! WorthOptLoop ) return false ; ++ NumOfLoopCandidate ; unsigned MispredictPenalty = TSchedModel . getMCSchedModel ( ) -> MispredictPenalty ; CmovGroups TempGroups ; std :: swap ( TempGroups , CmovInstGroups


<s> if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i ) break ; ++ SubvecElts ; } assert ( SubvecElts != NumElts && <STR_LIT> ) ; SubvecElts = PowerOf2Floor ( SubvecElts ) ; if ( Zeroable . countLeadingOnes ( ) >= ( NumElts - SubvecElts ) ) { MVT ExtractVT = <STR_LIT> ( <STR_LIT> , SubvecElts ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , Extract , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( NumElts >= <NUM_LIT> || ( Subtarget . hasDQI ( ) && NumElts == <NUM_LIT> ) ) { unsigned Offset = <NUM_LIT> ; for ( SDValue V : { V1 , V2 } ) { unsigned Opcode ; int ShiftAmt = match1BitShuffleAsKSHIFT ( Opcode , Mask , Offset , Zeroable ) ; if ( ShiftAmt >= <NUM_LIT> ) return DAG . getNode ( Opcode , DL , VT , V , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; Offset += NumElts ; } } MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc )


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this


<s> if ( count == <NUM_LIT> ) { rtvec p = rtvec_alloc ( <NUM_LIT> ) ; rtvec r = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( r , <NUM_LIT> ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ <NUM_LIT> ] ) ; RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> -


<s> return NextI ; } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . add ( StMO ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> __builtin_ia32_movdqa64store256_mask ( ( __v4di * ) __P , ( __v4di ) __A , (


<s> bool hasTBM ( ) const { return HasTBM


<s> for ( unsigned l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) for ( unsigned i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { int M = SM_SentinelZero ; if ( i >= Imm ) M = i - Imm + l ; ShuffleMask . push_back


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * AI ) { return AI &&


<s> if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = size & - PROBE_INTERVAL


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerCALL ( Op , DAG , <ISA_LIT>SubTarget , getTargetMachine ( ) ) ; case <STR_LIT> : return LowerRET ( Op , DAG


<s> SDValue Opnd0 , Opnd1 ; bool IsSubAdd ; if ( ! isAddSubOrSubAdd ( N , Subtarget , DAG , Opnd0 , Opnd1 , IsSubAdd ) ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , <NUM_LIT> ) ) { unsigned Opc = IsSubAdd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; } if ( IsSubAdd ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL ,


V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups


<s> bool FixupBWInstPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! FixupBWInsts || skipFunction ( MF . getFunction ( ) ) ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; LiveRegs . init ( TII -> getRegisterInfo ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; }


<s> static void or1k_tls_call ( rtx dest ,


<s> return ( __m128d ) __builtin_ia32_haddpd ( ( __v2df ) __X ,


<s> StringRef Kind ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ParseSuffix && Kind . empty ( )


<s> static void mips_add_cfa_restore ( rtx reg ) { mips_epilogue . cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg


<s> static unsigned toCallerWindow ( unsigned Reg ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return Reg -


<s> if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool IsNarrowLoad = isNarrowLoad ( MI -> getOpcode ( ) ) ; if ( ! IsNarrowLoad && ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsNarrowLoad || IsPromotableZeroStore ) { if ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else { if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } if ( ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] && ! ( MI -> mayLoad ( ) && UsedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) && ! mayAlias ( MI , MemInsns , TII ) ) { Flags . setMergeForward ( false ) ; return MBBI ; } if ( ! ModifiedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] && ! ( MayLoad && UsedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] ) && ! mayAlias ( FirstMI , MemInsns , TII ) ) { Flags . setMergeForward ( true ) ; return MBBI ; } } } if ( MI -> isCall ( ) ) return E ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return E ; if ( MI -> mayLoadOrStore ( ) ) MemInsns .


<s> Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( ) , nullptr , <STR_LIT> , Info . AI ) ; NewAI -> takeName ( Info . AI ) ; NewAI -> setAlignment ( Info . AI -> getAlignment ( ) ) ; NewAI -> setUsedWithInAlloca ( Info . AI -> isUsedWithInAlloca ( ) ) ; NewAI -> setSwiftError ( Info . AI ->


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRrr ( SDValue Addr , SDValue & R1 , SDValue & R2 ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) ==


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case


<s> rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != <NUM_LIT> && info -> first_gp_reg_save != <NUM_LIT> ) ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx ,


<s> MachineBasicBlock * OrigBB = MI -> getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSetFP ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( check ( ! UC . hasFnStart ( ) , L , <STR_LIT> ) || check ( UC . hasHandlerData ( ) , L , <STR_LIT> ) ) return true ; SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( check ( FPReg == - <NUM_LIT> , FPRegLoc , <STR_LIT> ) || Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( check ( SPReg == - <NUM_LIT> , SPRegLoc , <STR_LIT> ) || check ( SPReg != <STR_LIT> && SPReg != UC . getFPReg ( ) , SPRegLoc , <STR_LIT> ) ) return true ; UC . saveFPReg ( FPReg ) ; int64_t Offset = <NUM_LIT> ; if ( Parser . parseOptionalToken ( AsmToken :: Comma ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( check ( ! CE ,


<s> } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( RegNum ) ; O <<


<s> addPass ( create<ISA_LIT>StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass


<s> } else if ( isUInt < <NUM_LIT> > ( StackAdj ) ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addImm ( StackAdj ) ; } else { assert ( ! STI -> is64Bit ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; } for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) MIB . addOperand ( MBBI -> getOperand ( I ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MBB . getParent ( ) -> getFunction ( ) -> getPersonalityFn ( ) ) ) ; <ISA_LIT>FL -> restoreWin32EHStackPointers ( MBB , MBBI , DL , IsSEH ) ; MBBI -> eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MachineOperand & InArg = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned SaveRbx = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ActualInArg = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; TII -> copyPhysReg ( MBB , MBBI , DL , ActualInArg , InArg . getReg ( ) , InArg . isKill ( ) ) ; unsigned ActualOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewInstr = BuildMI ( MBB , MBBI , DL , TII -> get ( ActualOpc ) ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) NewInstr -> addOperand (


<s> if ( Compare . hasOneUse ( ) ) return true ; for ( auto CompareUse : Compare . getNode ( ) -> uses ( ) ) if ( CompareUse -> getOpcode ( ) != <STR_LIT> && CompareUse -> getOpcode ( ) != <STR_LIT>

&& CompareUse -> getOpcode ( ) != <STR_LIT> && ! isLogicOp ( CompareUse -> getOpcode ( ) ) ) {


<s> return ( int16x4_t ) __builtin_aarch64_sqaddv4hi (


<s> case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op


<s> for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG .


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ; } assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> if ( ( ( MaskVT . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( MaskVT . getScalarSizeInBits ( ) == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && FloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT>


<s> static StringRef select<ISA_LIT>ArchFeature ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: cpu0 || TT . getArch ( ) == Triple :: cpu0el ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( CPU == <STR_LIT> ) { <ISA_LIT>ArchFeature =


<s> static unsigned getPostIndexedLoadStoreOpcode ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) )

Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - <NUM_LIT> ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : { uint64_t Region = Addr & ~ uint64_t ( <NUM_LIT> ) ; Target = Region + Inst . getOperand ( NumOps - <NUM_LIT> ) .


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) NewMI = MakeM0Inst ( * this , <STR_LIT> , MOs , MI ) ; if ( NewMI ) return NewMI ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( i == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( i == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } if ( OpcodeTablePtr ) { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = OpcodeTablePtr -> find ( MI -> getOpcode ( ) ) ; if ( I != OpcodeTablePtr -> end ( ) ) { unsigned Opcode = I -> second . first ; unsigned MinAlign = ( I -> second . second & TB_ALIGN_MASK ) >> TB_ALIGN_SHIFT ; if ( Align < MinAlign ) return NULL ; bool NarrowToMOV32rm = false ; if ( Size ) { unsigned RCSize = getRegClass ( MI -> getDesc ( ) , i , & RI , MF ) -> getSize ( ) ; if ( Size < RCSize ) { if ( Opcode != <STR_LIT> || RCSize != <NUM_LIT> || Size != <NUM_LIT> ) return NULL ; if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return NULL ; Opcode = <STR_LIT> ; NarrowToMOV32rm = true ; } } if ( isTwoAddrFold ) NewMI = FuseTwoAddrInst ( MF , Opcode , MOs , MI , * this ) ; else NewMI = FuseInst ( MF , Opcode , i , MOs , MI , * this ) ; if (


<s> ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; return


<s> int mask = <NUM_LIT> ; HOST_WIDE_INT size ; rtx insn ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) mask |= <NUM_LIT> << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; vax_add_reg_cfa_offset ( insn , <NUM_LIT> , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , <NUM_LIT> ,


<s> unsigned RegMask = getMatrixTileListRegMask ( ) ; assert ( RegMask <= <NUM_LIT> &&


<s> const MCRegisterClass & XRegClass = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; bool isXReg = XRegClass . contains ( FirstReg ) , isWReg = WRegClass . contains ( FirstReg ) ; if ( ! isXReg && ! isWReg ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned FirstEncoding = RI -> getEncodingValue ( FirstReg ) ; if ( FirstEncoding & <NUM_LIT> ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc M = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( M , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; SMLoc E = getLoc ( ) ; int SecondReg = tryParseRegister ( ) ; if ( SecondReg == - <NUM_LIT> ) { return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( SecondReg ) != FirstEncoding + <NUM_LIT> || ( isXReg && ! XRegClass . contains ( SecondReg ) ) || ( isWReg && ! WRegClass . contains ( SecondReg ) ) ) { Error ( E , <STR_LIT> <STR_LIT> ) ; return


<s> const SDNodeFlags * Flags = & cast < BinaryWithFlagsSDNode > ( N ) -> Flags ; if ( Flags -> hasVectorReduction ( ) ) { if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG


<s> static inline bool is<ISA_LIT>Area2Register ( unsigned Reg , bool isIOS ) { using namespace


<s> case TYPE_DIV : if ( get_attr_size ( insn ) == SIZE_32 ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER7 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MTCR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return


<s> bool LE = Subtarget . isLittle ( ) ; LLVMContext & Context = M -> getContext ( ) ; std :: string Name = F -> getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; std :: string LocalName = <STR_LIT> + Name ; Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> +


<s> if ( tree attr = lookup_attribute ( <STR_LIT> , attrs ) ) { tree mangled_name = TREE_VALUE ( TREE_VALUE ( attr


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Has<ISA_LIT>64 ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> hasDSP ( ) ) { <STR_LIT> VecTys [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < array_lengthof ( VecTys ) ; ++ i ) { addRegisterClass ( VecTys [ i ] , & <STR_LIT> ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , VecTys [ i ] , Expand ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; } unsigned FirstVT = ( unsigned ) <STR_LIT> ; unsigned LastVT = ( unsigned ) <STR_LIT> ; for ( unsigned VT0 = FirstVT ; VT0 <= LastVT ; ++ VT0 ) { for ( unsigned VT1 = FirstVT ; VT1 <= LastVT ; ++ VT1 ) setTruncStoreAction ( ( <STR_LIT> ) VT0 , ( <STR_LIT> ) VT1 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; } setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( Subtarget -> hasDSPR2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget -> hasMSA ( ) ) { addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; } if ( ! Subtarget -> mipsSEUsesSoftFloat ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Subtarget -> isFP64bit ( ) ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ; return ; } assert ( Op . isExpr ( )


<s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Arg . getValueSizeInBits ( ) / <NUM_LIT> , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return DAG . getStore ( Chain , DL , Arg , FIN , MachinePointerInfo

( ) , MaybeAlign ( ) , MachineMemOperand :: MOVolatile ) ;


<s> if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default &&


<s> LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize < <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( uint32_t ( ~ <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ) ; else if ( BitSize == <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( ~ uint32_t ( <NUM_LIT> ) ) ; else { unsigned Tmp2 = MRI .


<s> __builtin_ia32_pmovuswb128mem_mask ( ( unsigned long long * ) __P ,


<s> ScopedHT . insert ( Entry , std :: make_pair ( P . first


<s> enum mode_class mclass ; if ( mode == FCCmode ) return FCC_REG_P ( regno ) ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) ) return ( ( regno - GP_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) ) { if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT )


<s> SDValue Magnitude = DAG . getNode ( <STR_LIT> , DL , IntVT , InvSignMask , getSVESafeBitCast ( IntVT , In1 , DAG ) ) ; SDValue IntResult = DAG . getNode ( <STR_LIT> , DL , IntVT , Sign , Magnitude ) ; return getSVESafeBitCast ( VT , IntResult , DAG ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; if ( SrcVT . bitsLT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 ) ; else if ( SrcVT . bitsGT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; EVT VecVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; auto setVecVal = [ & ] ( int Idx ) { if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT>


<s> if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onEq ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onNE ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onLT ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onLE ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onGT (