<s> SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; } else { if ( Subtarget -> useMovt ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; const MCOperand BranchMO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isExpr ( ) ) { assert ( BranchMO . isExpr ( ) ) ; const MCExpr * DiffExpr = MCBinaryExpr :: createSub ( MO . getExpr ( ) , BranchMO . getExpr ( ) , CTX ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( llvm :: MCFixup :: create ( <NUM_LIT> , DiffExpr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT>


<s> unsigned <ISA_LIT>BaseInstrInfo :: getLDMVariableDefsSize ( const MachineInstr & MI ) const { return MI . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getNumOperands


<s> } if ( Op . getResNo ( ) == <NUM_LIT> && ! NeedOF && ! NeedCF ) { unsigned Opcode = <NUM_LIT> ; unsigned NumOperands = <NUM_LIT> ; switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands =


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> bif_order = ( int * ) malloc ( ( curr_bif + <NUM_LIT>


<s> pinsrh_3_u ( uint16x4_t s , uint16x4_t t ) { return __builtin_loongson_pinsrh_3_u ( s , t )


<s> OutStreamer . SwitchSection ( S ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CP . size ( ) ; i != e ; ++ i ) { const MachineConstantPoolEntry & CPE = CP [ i ] ; unsigned Align = CPE . getAlignment ( ) ; unsigned AlignMask = CPE . getAlignment ( ) - <NUM_LIT> ; unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( NewOffset - Offset ) OS << <STR_LIT> << ( NewOffset - Offset ) << <STR_LIT> ; Type * Ty = CPE . getType ( ) ; Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ; MCSymbol * Symbol = GetCPISymbol ( i ) ; OS << <STR_LIT> << * Symbol ; HackStreamer ( OutStreamer ) << OS . str ( ) ; if ( CPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( CPE . Val .


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> )

|| ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) return true ;


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == nullptr ) return AM . Base . Reg ; unsigned ResultReg = createResultReg ( RC ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static && TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addGlobalAddress ( cast < GlobalValue > ( C ) ) ; } else { Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; } return ResultReg ; } return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOT_PREL = ! ( GV -> hasHiddenVisibility ( ) || GV -> hasLocalLinkage ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; }


<s> static DecodeStatus DecodeMem ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( ( Insn & <NUM_LIT> ) >> <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> if ( ! Subtarget -> isTargetLinux ( ) ) return false ; if ( ForceGlobalVarStackProtectorCookie ) return false ; if ( Subtarget -> is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT> ; } else { Offset = <NUM_LIT> ; AddressSpace = <NUM_LIT>


<s> auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT


<s> for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) while ( expandRxSBG ( RxSBG [ I ] ) ) if ( RxSBG [ I ] . Input . getOpcode ( ) != <STR_LIT> ) Count [ I ] += <NUM_LIT> ; if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return nullptr ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return nullptr ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { convertTo ( SDLoc ( N ) , <STR_LIT> , Op0 ) , convertTo ( SDLoc ( N ) , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue ( N , <NUM_LIT> ) )


<s> if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back (


<s> rtx note , expr ; note = find_reg_note ( insn , REG_FRAME_RELATED_EXPR , <NUM_LIT> ) ; expr = ( note != <NUM_LIT> ? XEXP ( note , <NUM_LIT> ) : copy_rtx ( PATTERN ( insn ) ) ) ; RTX_FRAME_RELATED_P ( expr ) = <NUM_LIT> ; return


<s> if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) )


<s> static SDValue emitConditionalComparison ( SDValue LHS , SDValue RHS , <STR_LIT> CC , SDValue CCOp , SDValue Condition , unsigned NZCV , SDLoc DL , SelectionDAG & DAG ) { unsigned Opcode = <NUM_LIT> ; if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) Opcode = <STR_LIT> ; else if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = RHS . getOperand ( <NUM_LIT> ) ; if ( const ConstantSDNode * SubOp0C = dyn_cast < ConstantSDNode > ( SubOp0 ) ) if ( SubOp0C -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode =


<s> if ( SubVec . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SubVec . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { uint64_t Idx2Val = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( IdxVal + Idx2Val , dl ) ) ; } if ( SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> && isNullConstant ( SubVec . getOperand ( <NUM_LIT> ) ) && SubVec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Ins = SubVec . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Ins . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( Ins . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Ins . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) <= SubVecVT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , Ins . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( IsI1Vector ) return SDValue ( ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == OpVT && ( IdxVal != <NUM_LIT> || ! Vec . isUndef ( ) ) ) { int ExtIdxVal = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; if ( ExtIdxVal != <NUM_LIT> ) { int VecNumElts = OpVT . getVectorNumElements ( ) ; int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( VecNumElts ) ; for ( int i = <NUM_LIT> ; i != VecNumElts ; ++ i ) Mask [ i ] = i ; for ( int i = <NUM_LIT> ; i != SubVecNumElts ; ++ i ) Mask [ i + IdxVal ] = i + ExtIdxVal + VecNumElts ; return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } SmallVector < SDValue , <NUM_LIT> > SubVectorOps ; if ( collectConcatOps ( N , SubVectorOps ) ) { if ( SDValue Fold = combineConcatVectorOps ( dl , OpVT , SubVectorOps , DAG , DCI , Subtarget ) ) return Fold ; if ( SubVectorOps . size ( ) == <NUM_LIT> && <STR_LIT> ( SubVectorOps [ <NUM_LIT> ] . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl ,

OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVectorOps [ <NUM_LIT> ] , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return Insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; assert ( OpVT . is128BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AnyExt


<s> if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( <NUM_LIT> ) ) ) ; rtx cond = gen_reg_rtx (


<s> static inline MachineOperand t1CondCodeOp ( bool


<s> const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; if ( OpFlags != <STR_LIT> ) assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , OpFlags ) ; } else { Result = getAddr ( GN , DAG , OpFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( OpFlags & ( <STR_LIT> | <STR_LIT> ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result


<s> virtual unsigned int execute ( function * ) { func_fma_steering * fma_steering = new func_fma_steering ; fma_steering -> execute_fma_steering (


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit ( ) ; assert ( Subtarget -> isTargetNaCl ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end


<s> if ( ! decompose_csky_address ( XEXP ( op , <NUM_LIT> ) , & addr ) ) return false ; if ( ! is_csky_address_register_rtx_p ( addr . base , <NUM_LIT> ) ) return false ; if ( addr . index && ( constraint [ <NUM_LIT> ] == 'Q' || constraint [ <NUM_LIT> ] == 'W' ) ) { if ( ! is_csky_address_register_rtx_p ( addr . index , <NUM_LIT> ) ) return false ; if ( addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> ) return true ; return false ; } else if ( addr . disp && constraint [ <NUM_LIT> ] == 'Q' ) { rtx disp = addr


<s> case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { unsigned CC0 , CC1 ; unsigned CombineOpc ; if ( SetCCOpcode == <STR_LIT> ) { CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } else { assert ( SetCCOpcode == <STR_LIT> ) ; CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } SDValue Cmp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC0 , <STR_LIT> ) ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC1 , <STR_LIT> ) ) ; return DAG . getNode ( CombineOpc , dl , VT , Cmp0 , Cmp1 ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( VT . is256BitVector ( ) && ! Subtarget -> hasAVX2 ( ) ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; FlipSigns = true


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ?

FSAttr . getValueAsString ( ) . str ( ) : TargetFS ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , false ) ; if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( RegNum == <NUM_LIT> ) return - <NUM_LIT> ; Parser . Lex ( ) ; return RegNum


<s> if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; if ( ! isOneConstant ( N1 ) ) return SDValue ( ) ; SDValue Shift = N0 . getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> || ! Shift . hasOneUse ( ) ) return SDValue ( ) ; EVT ShiftTy = Shift . getValueType ( ) ; if ( ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) || Shift . getConstantOperandVal ( <NUM_LIT> ) != ShiftTy . getSizeInBits ( ) - <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue ShiftOp = Shift . getOperand ( <NUM_LIT> ) ; EVT ShiftOpTy = ShiftOp . getValueType ( ) ; SDValue Cond = DAG . getSetCC ( DL , <STR_LIT> , ShiftOp , DAG . getConstant (

- <NUM_LIT> , DL , ShiftOpTy ) , <STR_LIT> ) ;


<s> void aarch64_asm_file_end ( ) { aarch64_sls_emit_shared_blr_thunks ( asm_out_file ) ; TARGET_ASM_FILE_END ( )


<s> } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , <NUM_LIT> ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case E_V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case E_V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case E_V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ElemVT = VT . getScalarType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerToScalableOp ( Op , DAG ) ; switch ( ElemVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { if ( auto * ConstVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( ConstVal -> isZero ( ) ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , VT ) , <NUM_LIT> ) ; if ( ConstVal -> isOne ( ) ) return getPTrue ( DAG , dl , VT , <STR_LIT> ) ; } SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : report_fatal_error ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * SymToPrint ; else O << '(' << * SymToPrint << '(' ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> << * MF -> getPICBaseSymbol ( ) << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' << * MF -> getPICBaseSymbol ( ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ;


<s> if ( for_return != <NUM_LIT> || GET_MODE_SIZE ( mode ) >= <NUM_LIT> || COMPLEX_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) || VECTOR_TYPE_P ( type ) || GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return mode ; return


<s> MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_ABIFLAGS , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; OS . SwitchSection ( Sec ) ; OS <<


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return &


<s> int16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> for ( auto & Terminator : Preheader -> terminators ( ) ) { if ( Terminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LoopExit = Terminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! LoopExit -> getPrevNode ( ) ) continue ; if ( blockIsBefore ( Preheader , LoopExit ) ) continue ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << Preheader -> getFullName ( ) << <STR_LIT> << LoopExit -> getFullName ( ) << <STR_LIT> ) ; bool CanMove = true ; for ( auto & LoopExitTerminator : LoopExit -> terminators ( ) ) { if ( LoopExitTerminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LoopExit2 = LoopExitTerminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! blockIsBefore ( LoopExit2 , LoopExit ) && ( LoopExit2 == Preheader || blockIsBefore ( LoopExit2 , Preheader ) ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } if ( CanMove ) { for ( auto It = LoopExit -> getIterator ( ) ; It != Preheader -> getIterator ( ) ; It ++ ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( Terminator . getOpcode ( ) != <STR_LIT> && Terminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LETarget = Terminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LETarget == LoopExit ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } } if ( ! CanMove ) break ; } if ( CanMove ) { moveBasicBlock ( LoopExit


<s> void rs6000_xcoff_declare_function_name ( FILE * file , const char * name , tree decl ) { char * buffer = ( char * ) alloca ( strlen ( name ) + <NUM_LIT> ) ; char * p ; int dollar_inside = <NUM_LIT> ; struct declare_alias_data data = { file , false } ; strcpy ( buffer , name ) ; p = strchr ( buffer , '$' ) ; while ( p ) { * p = '_' ; dollar_inside ++ ; p = strchr ( p + <NUM_LIT> , '$' ) ; } if ( TREE_PUBLIC ( decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( decl ) ) { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; putc ( '\n' , file ) ; } } else { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; putc ( '\n' , file ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; in_section =


<s> Context = & funcInfo . Fn -> getContext ( ) ; TargetSupported = ( ( Subtarget -> getRelocationModel ( ) == Reloc :: PIC_ ) && ( Subtarget

-> has<ISA_LIT>32r2 ( ) && ( Subtarget -> isABI_O32 ( ) ) ) ) ;


<s> Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . One &=


<s> void \ sdata_section ( void ) \ { \ if ( in_section != in_sdata ) \ { \ in_section = in_sdata ; \ fprintf ( asm_out_file , <STR_LIT>


<s> if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'U' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'X' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'W' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'Z' : fprintf ( stream , <STR_LIT> , nds32_dpref_names [ op_value ] ) ; return ; default : output_operand_lossage ( <STR_LIT> ) ; break ; } switch ( GET_CODE ( x ) ) { case LABEL_REF : output_addr_const ( stream , x ) ; break ; case SYMBOL_REF : output_addr_const ( stream , x ) ; if ( ! TARGET_LINUX_ABI && nds32_indirect_call_referenced_p ( x ) ) fprintf ( stream , <STR_LIT> ) ; break ; case REG : if ( ( GET_MODE ( x ) == DImode || GET_MODE ( x ) == DFmode ) && NDS32_IS_FPR_REGNUM ( REGNO ( x ) ) ) { regno = REGNO ( x ) ; if ( ! NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ) { output_operand_lossage ( <STR_LIT> , code ) ; break ; } fprintf ( stream , <STR_LIT> , ( regno - NDS32_FIRST_FPR_REGNUM ) >> <NUM_LIT> ) ; break ; } if ( ( GET_MODE ( x ) == DImode || GET_MODE ( x ) == DFmode ) && NDS32_IS_GPR_REGNUM ( REGNO ( x ) ) ) { if ( ( pick_lsb_p && WORDS_BIG_ENDIAN ) || ( pick_msb_p && ! WORDS_BIG_ENDIAN ) ) { regno = REGNO ( x ) ; regno ++ ; fputs ( reg_names [ regno ] , stream ) ; break ; } } if ( TARGET_REDUCED_REGS && REGNO ( x ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; fputs ( reg_names [ REGNO ( x ) ] , stream ) ; break ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) ) ; break ; case HIGH : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_DOUBLE ) { const REAL_VALUE_TYPE * rv ; long


<s> return ( int8x8_t ) __builtin_aarch64_sqnegv8qi


<s> if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . getOpcode ( ) == <STR_LIT> ) InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getOpcode ( ) == <STR_LIT> ) InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) { if ( ExpectedOpcode == <STR_LIT> ) return SDValue


<s> MachineBasicBlock * target = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI . eraseFromParent ( ) ; return


<s> if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link ->


<s> uint64_t StoreVal = ByteVal ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) StoreVal |= ByteVal << ( I


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , IsLittleEndian ( LittleEndian ) { if ( CPUString . empty ( ) ) CPUString =


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MI -> isCall ( ) && MO . isRegMask ( ) && ! clobbersAllYmmRegs ( MO ) ) return true ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDebug ( ) ) continue ; if ( isYmmReg ( MO . getReg ( ) ) ) return true ; } return


<s> unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue ( ) ) ; ITBlockMIs [ ITBlockSize - <NUM_LIT> - i ] = & * I ; } } PostRAHazardRecognizer :: EmitInstruction ( SU )


<s> SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; LaneMask [ i ] = ( SrcLane * NumEltsPerLane ) +


<s> for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx ] <= ProcResCostLim ) ) CriticalResourceIdx = UINT_MAX ; LLVM_DEBUG ( dumpState ( ) ;


<s> BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBInfo . front ( ) . KnownBits = MF -> getAlignment ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF -> front ( ) ) ; for ( MachineBasicBlock & MBB : * MF ) { if ( ! BBHasFallthrough ( & MBB ) ) WaterList . push_back ( & MBB ) ; for ( MachineInstr & I : MBB ) { if ( I . isDebugInstr ( ) ) continue ; unsigned Opc = I . getOpcode ( ) ; if ( I . isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits =


<s> } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForSize ( ) ; if ( ConstSplatVal && ( Subtarget . hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget . hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI

. getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> return __builtin_altivec_vcmpgtfp_p ( __CR6_LT ,


<s> DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |=


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> SDValue FVal = Op -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( Ty . isScalableVector ( ) ) { SDValue TruncCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCVal ) ; MVT PredVT = <STR_LIT> ( <STR_LIT> , Ty . getVectorElementCount ( ) ) ; SDValue SplatPred = DAG . getNode ( <STR_LIT> , DL , PredVT , TruncCC ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , SplatPred , TVal , FVal ) ; } if ( useSVEForFixedLengthVectorVT ( Ty ) ) { MVT SplatValVT = <STR_LIT> ( Ty . getScalarSizeInBits ( ) ) ; MVT PredVT = <STR_LIT> ( SplatValVT , Ty . getVectorElementCount ( ) ) ; SDValue SplatVal = DAG . getSExtOrTrunc ( CCVal , DL , SplatValVT ) ; SDValue SplatPred = DAG . getNode ( <STR_LIT> , DL , PredVT , SplatVal ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , SplatPred , TVal , FVal ) ; } if ( <STR_LIT> ( CCVal ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( CCVal -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , CCVal . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( OFCC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( )


<s> __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector signed short


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_MUL : case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_SITOFP :


<s> } Options . setNoreorder ( ) ; Parser . Lex ( ) ; return


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA ,

MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT (


<s> return ( uint64_t ) __builtin_aarch64_reduc_plus_scal_v2di ( ( int64x2_t )


<s> SDValue MFFSreg , InFlag ; EVT NodeTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl


<s> dbgs ( ) << <STR_LIT> << ( IsPrimed ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsRestore ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; MBB . dump ( )


<s> static unsigned char aarch64_class_max_nregs ( reg_class_t regclass , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; unsigned int nregs ; switch ( regclass ) { case TAILCALL_ADDR_REGS : case POINTER_REGS : case GENERAL_REGS : case


<s> case 'y' : O << <STR_LIT> ; printOperand ( MI , OpNo , O ) ; return false ; case 'U' : case 'X' : assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false ; } } assert ( MI -> getOperand ( OpNo


<s> assert ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OpCmode = <NUM_LIT> ; Imm = SplatBits ; VT = is128Bits ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |=


<s> if ( Opcode != <STR_LIT> ) return ; SDValue Chain = Results [ <NUM_LIT> ] ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Glue ) ; Results [ <NUM_LIT> ] =


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { int byte = ( op1 >> ( <NUM_LIT> * ( <NUM_LIT> - i ) ) ) & <NUM_LIT> ; if ( byte ) { emit_set_insn ( op0 , mov_done_p ? gen_rtx_PLUS ( SImode , op0 , GEN_INT ( byte ) ) : GEN_INT ( byte ) ) ; mov_done_p = true ; } if ( mov_done_p ) emit_set_insn ( op0 , gen_rtx_ASHIFT ( SImode , op0 , GEN_INT ( <NUM_LIT> ) ) ) ; } if ( ! mov_done_p ) emit_set_insn ( op0 , GEN_INT ( op1 & <NUM_LIT> ) ) ; else if ( op1 & <NUM_LIT> ) emit_set_insn ( op0 , gen_rtx_PLUS ( SImode , op0 , GEN_INT


<s> const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( IsThreadLocal ) return <NUM_LIT> ; EmitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { unsigned TempReg = createResultReg ( RC ) ; EmitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; DestReg = TempReg ; } return DestReg


<s> if ( ! CSD ) return false ; ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal > <NUM_LIT> ) return false ; Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else { Ext = getExtendTypeForNode ( N ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand


<s> EVT VT = Vec . getValueType ( ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; int Factor = VT . getSizeInBits ( ) / <NUM_LIT> ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> ,


<s> bool aarch64_sve_vector_inc_dec_immediate_p ( rtx


<s> uint64_t NumBytes = MFI . getStackSize ( ) ; emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true


<s> case <NUM_LIT> : NumVecs = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( IsLoad ) { switch ( NumVecs ) { case <NUM_LIT> : Is128BitVec ? DecodeFPR128RegisterClass ( Inst , Rt , Address , Decoder ) : DecodeFPR64RegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQPairRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDPairRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQTripleRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDTripleRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQQuadRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDQuadRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; } } DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( NumVecs * ( Is128BitVec ? <NUM_LIT> : <NUM_LIT> ) ) ) ; else DecodeGPR64noxzrRegisterClass ( Inst , Rm , Address , Decoder ) ; if ( ! IsLoad


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv8hi ( __a )


<s> return new ScheduleDAGMI ( C , llvm :: make_unique < <ISA_LIT>PostRASchedStrategy >


<s> AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightAlgebraic ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ; return SDValue ( )


<s> Relocator :: Result none ( Relocation & pReloc , <ISA_LIT>Relocator


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base


<s> WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; if ( ! is64Bit ) ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> :


<s> case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectMergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_UDIV : case TargetOpcode :: G_SREM : case TargetOpcode :: G_UREM : return selectDivRem ( I , MRI


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri =


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str


<s> const <ISA_LIT>Subtarget & Subtarget = FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) return new <ISA_LIT>FastISel ( FuncInfo


<s> for ( size_t i = <NUM_LIT> , e = SFVals . size ( ) ; i != e ; ++ i ) SFVals [ i ] = <NUM_LIT> ; for ( size_t i = <NUM_LIT> , e = CCVals . size ( ) ; i != e ; ++ i ) CCVals [ i ] = <NUM_LIT> ; LastEFLAGSChangingDef = <NUM_LIT>


<s> else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return false


<s> if ( VT == <STR_LIT> ) return Subtarget . hasSSE1 ( ) ; if ( VT == <STR_LIT> ) return Subtarget . hasSSE2 ( ) ; return true


<s> Parser . Lex ( ) ; return false ; } else if ( getLexer ( ) . is ( AsmToken :: Equal ) ) { getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo > <NUM_LIT> ) { reportParseError ( <STR_LIT>


<s> <ISA_LIT>beTargetMachine :: <ISA_LIT>beTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM

, CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> if ( offset >= insn -> bytes . size ( ) ) return true ; byte = insn -> bytes [ offset


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> unsigned indexOffset = CheckEven ? <NUM_LIT> : <NUM_LIT> ; if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else return


<s> Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { Register Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX (

) && ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; ArrayRef < int > LoMask = Mask . slice ( <NUM_LIT> , Mask . size ( ) / <NUM_LIT> ) ; ArrayRef < int > HiMask = Mask . slice ( Mask . size ( ) / <NUM_LIT> ) ; int NumElements = VT . getVectorNumElements ( ) ; int SplitNumElements = NumElements / <NUM_LIT> ; MVT ScalarVT = VT . getScalarType ( ) ; MVT SplitVT = <STR_LIT> ( ScalarVT , NumElements / <NUM_LIT> ) ; SDValue LoV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue HiV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( SplitNumElements ) ) ; SDValue LoV2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue HiV2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V2 , DAG . getIntPtrConstant ( SplitNumElements ) ) ; auto HalfBlend = [ & ] ( ArrayRef < int > HalfMask ) { bool UseLoV1 = false , UseHiV1 = false


<s> union { vec_double2 v ; double d [ <NUM_LIT> ] ; } in ; in . v =


<s> return __builtin_mve_vmulltq_int_m_sv8hi ( __arm_vuninitializedq_s32 ( ) , __a , __b ,


<s> if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) .


<s> } else if ( ! TREE_PUBLIC ( node -> decl ) ) { if ( TARGET_AVX2 ) clonei -> vecsize_mangle = 'd' ; else if ( TARGET_AVX ) clonei -> vecsize_mangle = 'c' ; else clonei -> vecsize_mangle = 'b' ; ret = <NUM_LIT> ; } else { clonei -> vecsize_mangle = <STR_LIT> [ num ] ; ret = <NUM_LIT> ; } switch ( clonei -> vecsize_mangle ) { case 'b' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'c' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen /= GET_MODE_BITSIZE ( TYPE_MODE ( base_type )


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> ,


<s> if ( const MCSymbol * Group = FnSection . getGroup ( ) ) { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags | ELF :: SHF_GROUP , Kind , FnSection . getEntrySize ( ) , Group -> getName ( ) ) ; } else { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , Kind ) ; } assert ( EHSection


<s> virtual const MandarinSelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; unsigned e = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ e + i ] , i ) ) return false ; return true


<s> Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token


<s> static SDValue combineVectorShiftVar ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) ,


<s> bool <ISA_LIT>FrameLowering :: canUseLEAForSPInEpilogue ( const MachineFunction & MF ) const { return ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI


<s> unsigned <ISA_LIT>FastISel :: emitSubs_rs ( MVT RetVT , unsigned LHSReg , bool LHSIsKill , unsigned RHSReg , bool RHSIsKill , <STR_LIT> ShiftType , uint64_t ShiftImm , bool WantResult ) { return emitAddSub_rs ( false , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftType , ShiftImm , true


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ (


<s> static __inline__ double __fnmadd ( double x , double y , double z


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . GVIsIndirectSymbol ( GV , RM ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; } MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) ,


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: mips > X ( The<ISA_LIT>Target ,


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst


<s> else if ( SUBREG_P ( operands [ <NUM_LIT> ] ) ) { op1 = operands [ <NUM_LIT> ] ; op2 = operands [ <NUM_LIT> ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( SUBREG_P ( op2 ) || GET_CODE ( op2 ) == CONST_VECTOR ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == <NUM_LIT> && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == <NUM_LIT> ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case V4SFmode : case V8SFmode : case V16SFmode : case


<s> return ( __m64 ) __builtin_arm_wsrahi ( ( __v4hi )


<s> if ( LI -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( LI -> getType ( ) , VT , true ) ) return false ; const Value * Ptr = LI -> getPointerOperand ( ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg


<s> break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLD ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MCSymbol * sym = MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) ; const MCSymbolRefExpr * symRef = MCSymbolRefExpr :: create ( sym , SRVK , context ) ; MCInst LEA ; if ( is64Bits ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } EmitAndCountInstruction ( LEA


<s> return ; case MCAF_Code16 : IsThumb = true ; return ; case MCAF_Code32 : IsThumb = false ; return ; case MCAF_Code64 : return ; case


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; auto Mapper = <STR_LIT> ( ) ; std :: string Name = Mapper . toString ( Val , STI . getFeatureBits ( ) ) ; O << StringRef ( Name )


<s> AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc = getLeaOP ( Ty , STI ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF


<s> rtx base , offset ; split_const ( address , & base , & offset ) ; return mips_unspec_address_offset ( base , offset


<s> static inline bool isSVEMaskOfIdenticalElements ( int64_t Imm ) { auto Parts = bit_cast < std :: array < T , sizeof ( int64_t


<s> pa_asm_output_aligned_local ( FILE , NAME , SIZE , ALIGN ) { rtx addr = ADDR ; \ switch ( GET_CODE ( addr ) ) \ { \ case REG : \ fprintf ( FILE , <STR_LIT> , reg_names [ REGNO ( addr ) ] ) ; \ break ; \ case PLUS : \ gcc_assert ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) ; \ fprintf ( FILE , <STR_LIT> , ( int ) INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , \ reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; \ break ; \ case LO_SUM : \ if ( ! symbolic_operand ( XEXP ( addr , <NUM_LIT> ) , VOIDmode ) )

\ fputs ( <STR_LIT> , FILE ) ; \ else if ( flag_pic == <NUM_LIT> ) \ fputs ( <STR_LIT> , FILE ) ; \ else \ fputs ( <STR_LIT> , FILE ) ; \ pa_output_global_address ( FILE , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ output_operand ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ break ; \ case CONST_INT : \ fprintf ( FILE , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( addr ) ) ; \ break ; \ default : \ output_addr_const ( FILE , addr ) ; \ } }


<s> Stub * <ISA_LIT>CA53Erratum843419Stub :: doClone ( ) { return new <ISA_LIT>CA53Erratum843419Stub ( getData ( ) , size ( ) ,

<STR_LIT> , fixup_begin ( ) , fixup_end ( ) ) ;


<s> const struct processor * cpu ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == <NUM_LIT> ) { uint64_t isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return


<s> MachineInstr * Def = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! Def || ( Def -> getOpcode ( ) != <STR_LIT> && Def -> getOpcode ( ) != <STR_LIT> ) || ! Def -> getOperand ( <NUM_LIT> ) .


<s> unsigned <ISA_LIT>FastISel :: emitSubs_rs ( MVT RetVT , unsigned LHSReg , unsigned RHSReg , <STR_LIT> ShiftType , uint64_t ShiftImm , bool WantResult ) { return emitAddSub_rs ( false , RetVT , LHSReg , RHSReg , ShiftType , ShiftImm ,


<s> LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ,


<s> static const Constant * getTargetConstantFromNode (


<s> TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( cfun -> va_list_fpr_size ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( fpr ) , fpr , build_int_cst ( NULL_TREE , n_fpr ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( call_ABI_of_interest ( cfun -> decl ) ) rs6000_passes_float = true ; } t = make_tree ( TREE_TYPE ( ovf ) , crtl -> args . internal_arg_pointer ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * MIN_UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size && n_gpr < GP_ARG_NUM_REG && n_fpr < FP_ARG_V4_MAX_REG ) return ; t = make_tree ( TREE_TYPE ( sav ) , virtual_stack_vars_rtx ) ; if ( cfun -> machine -> varargs_save_offset ) t = fold_build_pointer_plus_hwi ( t , cfun -> machine -> varargs_save_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( sav ) , sav , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL


<s> if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; } } printOperand ( MI , OpNo ) ; return false


<s> } if ( mode == Pmode || mode == ptr_mode ) { rtx op0 = operands [ <NUM_LIT> ] ; rtx op1 = operands [ <NUM_LIT> ] ; rtx opc ; if ( GET_CODE ( op1 ) == CONST && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == PLUS && ( tls_symbolic_operand ( XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) , Pmode ) != TLS_MODEL_NONE ) ) { opc = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; op1 = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; } else opc = NULL_RTX ; enum tls_model tls_kind ; if ( ! reload_in_progress && ! reload_completed && ( tls_kind = tls_symbolic_operand ( op1 , Pmode ) ) != TLS_MODEL_NONE ) { rtx tga_op1 , tga_ret , tmp , tmp2 ; if ( ! flag_pic && ( tls_kind == TLS_MODEL_GLOBAL_DYNAMIC || tls_kind == TLS_MODEL_LOCAL_DYNAMIC || tls_kind == TLS_MODEL_INITIAL_EXEC ) ) { static int got_labelno ; if ( flag_schedule_insns ) emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_GOTaddr2picreg ( GEN_INT ( ++ got_labelno ) ) ) ; emit_use ( gen_rtx_REG ( SImode , PIC_REG ) ) ; if ( flag_schedule_insns ) emit_insn ( gen_blockage ( ) ) ; } switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : tga_ret = gen_rtx_REG ( Pmode , R0_REG ) ; if ( TARGET_FDPIC ) emit_move_insn ( gen_rtx_REG ( Pmode , PIC_REG ) , sh_get_fdpic_reg_initial_val ( ) ) ; emit_call_insn ( gen_tls_global_dynamic ( tga_ret , op1 ) ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , tga_ret ) ; op1 = tmp ; break ; case TLS_MODEL_LOCAL_DYNAMIC : tga_ret = gen_rtx_REG ( Pmode , R0_REG ) ; if ( TARGET_FDPIC ) emit_move_insn ( gen_rtx_REG ( Pmode , PIC_REG ) , sh_get_fdpic_reg_initial_val ( ) ) ; emit_call_insn ( gen_tls_local_dynamic ( tga_ret , op1 ) ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , tga_ret ) ; if ( register_operand ( op0 , Pmode ) ) tmp2 = op0 ; else tmp2 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symDTPOFF2reg ( tmp2 , op1 , tmp ) ) ; op1 = tmp2 ; break ; case TLS_MODEL_INITIAL_EXEC : tga_op1 = ! can_create_pseudo_p ( ) ? op0 : gen_reg_rtx ( Pmode ) ; tmp = gen_sym2GOTTPOFF ( op1 ) ; if ( TARGET_FDPIC ) emit_move_insn ( gen_rtx_REG ( Pmode , PIC_REG ) , sh_get_fdpic_reg_initial_val ( ) ) ; emit_insn ( gen_tls_initial_exec ( tga_op1 , tmp ) ) ; op1 = tga_op1 ; break ; case TLS_MODEL_LOCAL_EXEC : tmp2 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_store_gbr ( tmp2 ) ) ; tmp = gen_reg_rtx ( Pmode


<s> bool isHWRegsAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_HWRegs &&


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) )


<s> else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( <NUM_LIT> ) . getReg


<s> rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = <NUM_LIT> ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > <NUM_LIT> ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp ) ; frame_rtx = operands [ <NUM_LIT> ]


<s> else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp


<s> bool HasDef = false ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; if ( MO . getReg ( )


<s> static DecodeStatus DecodeDDDRegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Addr , const MCDisassembler * Decoder ) {


<s> void <ISA_LIT>CodeEmitter :: emitLoadStoreMultipleInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI .


<s> return :: direct_optab_handler ( op ,


<s> if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } } return SDValue ( )


<s> typename __altivec_bool_ret < vec_step ( T ) > :: __ret \ NAME ( T a1 , U a2 ) \ { \ return


<s> static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT>


<s> formatted_raw_ostream & HackStreamer ( MCStreamer & OutStreamer ) { HackMCAsmStreamer & hack = * ( HackMCAsmStreamer * )


<s> SDValue SetCC = DAG . getSetCC ( dl , <STR_LIT> , NegatedPlus32 , Zero , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShOpHi , ShAmt ) ; Hi = DAG . getSelect ( dl , <STR_LIT> , SetCC , Zero , Hi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShOpLo , ShAmt ) ; Lo = DAG . getSelect ( dl , <STR_LIT> , SetCC , Hi , Lo ) ; SDValue CarryBits = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShOpHi , NegatedPlus32 ) ; SDValue ShiftIsZero = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , Zero , <STR_LIT> ) ; Lo = DAG . getSelect ( dl , <STR_LIT> , ShiftIsZero , Lo , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , CarryBits ) ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineHorizontalMinMaxResult ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineReductionToHorizontal ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG ) ) return V ; if ( CIdx && SrcVT . getScalarType ( ) == <STR_LIT> ) { SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; auto IsBoolExtract = [ & BoolExtracts ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Use -> getOperand ( <NUM_LIT> ) ) && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BoolExtracts . push_back ( Use ) ; return true ; } return false ; } ; if ( all_of ( InputVector -> uses ( ) , IsBoolExtract ) && BoolExtracts . size ( ) > <NUM_LIT> ) { unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; EVT BCVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumSrcElts ) ; if ( SDValue BC = combineBitcastvxi1 ( DAG , BCVT , InputVector , dl , Subtarget ) ) { for ( SDNode * Use : BoolExtracts ) { unsigned MaskIdx = Use -> getConstantOperandVal ( <NUM_LIT> ) ; APInt MaskBit = APInt :: getOneBitSet ( NumSrcElts , MaskIdx ) ; SDValue Mask = DAG . getConstant ( MaskBit , dl , BCVT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , BCVT , BC , Mask ) ; Res = DAG . getSetCC ( dl , <STR_LIT> , Res , Mask , <STR_LIT> ) ; DCI . CombineTo ( Use , Res ) ; } return SDValue ( N


<s> if ( OpMI -> getOpcode ( ) != TargetOpcode :: G_BUILD_VECTOR ) return None ; int64_t ImmVal = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < OpMI -> getNumOperands ( ) ; ++ Idx ) { auto VRegAndVal = getConstantVRegValWithLookThrough ( OpMI -> getOperand ( Idx


<s> DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd ; } if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && ( EltVT . getSizeInBits ( ) == <NUM_LIT> ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , false , true , false ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , ResNode ) ; } return SDValue


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg


<s> return ( isCombineInstrCandidate32 ( Opc ) || isCombineInstrCandidate64


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } } if ( VT . isVector ( ) && VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ; if ( R . getNode ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool IsVPRDefinedOrKilledByBlock ( MachineBasicBlock :: iterator Iter , MachineBasicBlock :: iterator End ) { for ( ; Iter != End ; ++ Iter ) if ( Iter -> definesRegister ( <STR_LIT>

) || Iter -> killsRegister ( <STR_LIT> ) ) return true ;


<s> if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( Opc , DL , Ty , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( SplatValue . getZExtValue ( ) ,


<s> return __builtin_loongson_pmovmskb_u ( s


<s> break ; case CCValAssign :: AExtUpper : UseUpperBits = true ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>LEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { return create<ISA_LIT>AsmBackend ( T , MRI , TT ,


<s> __rv . __o = __builtin_neon_vld2_dupv4hi ( ( const __builtin_neon_hi * )


<s> void addVectorIndexHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address + <NUM_LIT> ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ; while ( ftmp ) { if ( ! BARRIER_P ( ftmp -> insn ) && ( ( ftmp -> minipool = add_minipool_backward_ref ( ftmp ) ) == NULL ) ) break ; ftmp = ftmp -> next ; } for ( this_fix = fix ; this_fix && ftmp != this_fix ; this_fix = this_fix -> next ) if ( ! BARRIER_P ( this_fix -> insn ) ) { rtx addr = plus_constant ( Pmode , gen_rtx_LABEL_REF ( VOIDmode ,

minipool_vector_label ) , this_fix -> minipool -> offset ) ;


<s> case CC_DGTUmode : code = ARM_HI ; goto dominance ; case CC_DLEUmode : code = ARM_LS ; goto dominance ; case CC_DLTUmode : code = ARM_CC ; dominance : gcc_assert ( comp_code == EQ || comp_code == NE ) ; if ( comp_code == EQ ) return ARM_INVERSE_CONDITION_CODE ( code ) ; return code ; case CC_NOOVmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_PL ; case LT : return ARM_MI ; default : gcc_unreachable ( ) ; } case CC_Zmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; default : gcc_unreachable ( ) ; } case CC_Nmode : switch ( comp_code ) { case NE : return ARM_MI ; case EQ : return ARM_PL ; default : gcc_unreachable ( ) ; } case CCFPEmode : case CCFPmode : switch ( comp_code ) { case GE : return ARM_GE ; case GT : return ARM_GT ; case LE : return ARM_LS ; case LT : return ARM_MI ; case NE : return ARM_NE ; case EQ : return ARM_EQ ; case ORDERED : return ARM_VC ; case UNORDERED : return ARM_VS ; case UNLT : return ARM_LT ; case UNLE : return ARM_LE ; case UNGT : return ARM_HI ; case UNGE : return ARM_PL ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } case CC_SWPmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_LE ; case GT : return ARM_LT ; case LE : return ARM_GE ; case LT : return ARM_GT ; case GEU : return ARM_LS ; case GTU : return ARM_CC ; case LEU : return ARM_CS ; case LTU : return ARM_HI ; default : gcc_unreachable ( ) ; } case CC_Cmode : switch ( comp_code ) { case LTU : return ARM_CS ; case GEU : return ARM_CC ; default : gcc_unreachable ( ) ; } case CCmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_GE ; case GT : return ARM_GT ; case LE : return ARM_LE ; case LT :


<s> const MCOperand Op1 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand Op2 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand AluOp = Inst . getOperand ( OpNo + <NUM_LIT> ) ; assert ( Op1 . isReg ( ) && <STR_LIT> ) ; assert ( ( Op2 . isImm ( ) || Op2 . isExpr ( ) ) && <STR_LIT> ) ; assert ( ( LPAC :: getAluOp ( AluOp . getImm ( ) ) == LPAC :: ADD ) && <STR_LIT> ) ; Encoding = ( get<ISA_LIT>RegisterNumbering ( Op1 . getReg ( ) ) << <NUM_LIT> ) ; if ( Op2 . isImm ( ) ) { assert ( isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) && <STR_LIT> ) ; Encoding |= ( Op2 . getImm ( ) & <NUM_LIT> ) ; if ( Op2 . getImm ( ) != <NUM_LIT> ) { if ( LPAC :: isPreOp ( AluOp . getImm ( ) ) ) Encoding |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( LPAC :: isPostOp ( AluOp . getImm ( ) ) ) Encoding


<s> <ISA_LIT>AddressingMode AM ( <STR_LIT> , DR ) ; if ( ! selectAddress ( Addr , AM ) || AM . Index . getNode ( ) ) return false ; getAddressOperands ( AM , Addr . getValueType ( ) , Base , Disp ) ; return


<s> int dest_regno = REGNO ( dest ) ; int src_regno ; if ( src == pc_rtx ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; return ; } src_regno = REGNO ( src ) ; switch ( src_regno ) { case PR_REG ( <NUM_LIT> ) : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_pr ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; break ; case AR_UNAT_REGNUM : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_ar_unat ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; break ; case AR_LC_REGNUM


<s> unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex


<s> if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return nullptr ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return nullptr ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask


<s> return getTM < <ISA_LIT>TargetMachine


<s> insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { if ( TARGET_USE_PIC_FN_ADDR_REG && ! TARGET_MIPS16 && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( MIPS_CALL_SIBCALL , temp1 , fnaddr ) ; if ( TARGET_USE_PIC_FN_ADDR_REG && REGNO ( temp1 ) != PIC_FUNCTION_ADDR_REGNUM ) mips_emit_move ( gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) , temp1 ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; mips16_lay_out_constants ( true ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( ) ; reload_completed = <NUM_LIT>


<s> if ( MI . getOperand ( OpndIdx ) . isImm ( ) && ! isShiftedInt < Width , Scale > ( MI . getOperand ( OpndIdx ) . getImm ( ) ) ) { ErrInfo = <STR_LIT>


<s> unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR ,


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; SunStyleELFSectionSwitchSyntax = true


<s> for ( auto * MI : C . instructions ( ) ) Cost += Converters . find ( { DstDomain , MI -> getOpcode ( ) } ) -> second -> getExtraCost ( MI , MRI ) ; return


<s> bool has<ISA_LIT>32r2 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r2 ||


<s> No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing =


<s> for ( ; I != E ; ++ I ) { if ( * I != i ) return false ; i ++ ; } return true ; } ; SelectionDAG & DAG = DCI . DAG ; EVT VT = SVN -> getValueType ( <NUM_LIT> ) ; if ( ! isTypeLegal ( VT ) || ! Subtarget . isLittleEndian ( ) || ! Subtarget . hasVSX ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasP9Vector ( ) ) return SDValue ( ) ; if ( ! IsElementReverse ( SVN ) ) return SDValue ( ) ; if ( LSBase -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: use_iterator UI = LSBase -> use_begin ( ) , UE = LSBase -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( LSBase ) ; SDValue LoadOps [ ] = { LSBase -> getChain ( ) , LSBase -> getBasePtr ( ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , LoadOps , LSBase -> getMemoryVT ( ) , LSBase -> getMemOperand ( ) ) ; } if ( LSBase -> getOpcode ( ) == <STR_LIT>


<s> if ( Subtarget . hasVectorEnhancements2 ( ) ) if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return false


<s> ++ NumADRPSimpleCandidate ; } if ( Info . IsCandidate ) { switch ( Info . Type ) { case MCLOH_AdrpAdd : { const MachineInstr * AddMI = Info . MI0 ; int DefIdx = mapRegToGPRIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LOHInfo DefInfo = LOHInfos [ OpIdx ] ; if ( DefIdx != OpIdx && ( DefInfo . OneUser || DefInfo . MultiUsers ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAdd , { & MI , Info . MI0 } ) ; ++ NumADRSimpleCandidate ; break ; } case MCLOH_AdrpLdr : if ( supportLoadFromLiteral ( * Info . MI0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdr , { & MI , Info . MI0 } ) ; ++ NumADRPToLDR


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _lzcnt_u64 ( unsigned long long __X ) { return __builtin_ia32_lzcnt_u64 ( __X


<s> if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < <NUM_LIT>


<s> return ( __m64 ) __builtin_ia32_pmulhw ( ( __v4hi ) __m1 , ( __v4hi )


<s> if ( IsStackReg ( MemOp . getMemBaseReg ( ) ) || IsStackReg ( MemOp . getMemIndexReg ( ) ) ) return ; if ( AccessSize < <NUM_LIT> ) InstrumentMemOperandSmallImpl ( MemOp , AccessSize , IsWrite , Ctx ,


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI (


<s> TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Addr , DemandedMask , Known , TLO ) ) { DCI . CommitTargetLoweringOpt


<s> if ( cfun -> machine -> global_pointer == regno ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ( ) ) return true ; if ( cfun -> machine -> interrupt_handler_p && ! crtl -> is_leaf && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return false


<s> return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects (


<s> SDValue Src1 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpc0 = Src0 . getOpcode ( ) ; unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = Src0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , SrcVT0 , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , Res ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : if ( SrcVT0 == <STR_LIT> ) { uint64_t Mask = Src0 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask & <NUM_LIT> ) != ( ( Mask >> <NUM_LIT> ) & <NUM_LIT> ) ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp


<s> case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT>


<s> FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr


<s> static bool isEqual ( const TOCKey & A , const TOCKey & B ) { return A == B


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { addPass ( create<ISA_LIT>OptimizePICCallPass