<s> int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII -> get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr ) . addImm ( HighOffset ) . addReg ( <NUM_LIT> ) ; else { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( BasePtr , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } MI -> setDesc ( TII -> get ( OpcodeForOffset ) ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) .


<s> return ( __m128i ) __builtin_ia32_cvtpd2dq128_mask ( ( __v2df ) __A , ( __v4si ) _mm_setzero_si128 ( ) , (


<s> gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) !=


<s> if ( DestVT == <STR_LIT> ) DestVT = Op0 . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant

( IID , <STR_LIT> ) , Op0 , Op1 , Op2 ) ;


<s> bool IsNakedFunction = MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) { TS . emitDirectiveSetNoReorder


<s> return STI . getFeatureBits ( ) [ <STR_LIT>


<s> if ( isThumb ( ) ) return <STR_LIT> ; if ( hasV4TOps ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( )


<s> if ( VecTy -> getNumElements ( ) == <NUM_LIT> ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != <NUM_LIT> && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits (


<s> rtx condition , cmp_result ; int cmp_value ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = gen_rtx_REG ( CCDSPmode , CCDSP_PO_REGNUM ) ; if ( builtin_type == MIPS_BUILTIN_BPOSGE32 ) cmp_value = <NUM_LIT> ; else gcc_assert ( <NUM_LIT> ) ; condition = gen_rtx_GE ( VOIDmode , cmp_result , GEN_INT


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle

, RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> :


<s> NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasMMA = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove =


<s> MCSymbol * Label = S . emitCFILabel ( ) ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label ,


<s> case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , SExtVT , Src ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Src . getOpcode ( ) , DL , SExtVT , signExtendBitcastSrcVector ( DAG , SExtVT , Src . getOperand ( <NUM_LIT> ) , DL ) , signExtendBitcastSrcVector ( DAG , SExtVT , Src . getOperand ( <NUM_LIT> ) , DL ) ) ; } llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode6 ( SDNode * Op , SDValue N , SDValue & Addr , SDValue & Align ) { Addr = N ; Align = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bextr_u32 ( unsigned int __X , unsigned int __P , unsigned int __L ) { return ( ( __X << ( <NUM_LIT> - ( __L + __P


<s> OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D1 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D2 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 (


<s> static bool sh_return_in_memory ( const_tree type , const_tree fndecl ) { return TYPE_MODE ( type ) == BLKmode || ( ( TARGET_HITACHI || sh_attr_renesas_p (

fndecl ) ) && TREE_CODE ( type ) == RECORD_TYPE ) ;


<s> if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > (


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok (


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return true


<s> const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op


<s> SDValue New<ISA_LIT> = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT> , Size ) ; Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , New<ISA_LIT> , DAG . getConstant (


<s> switch ( src_mode ) { case E_DFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_df ; break ; case E_SFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( src_mode ) ) cvt = sext_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IEEE_P ( src_mode ) ) { if ( src_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( src_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( dest_mode ) { case E_DFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_df ; break ; case E_SFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode


<s> <ISA_LIT>PreLegalizerCombiner :: <ISA_LIT>PreLegalizerCombiner ( ) : MachineFunctionPass (


<s> rtx dst = operands [ <NUM_LIT> ] ; rtx src = operands [ <NUM_LIT> ] ; unsigned int size = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned int pos = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( SUBREG_P ( dst ) ) { if ( SUBREG_BYTE ( dst ) > <NUM_LIT> ) return false ; dst = SUBREG_REG ( dst ) ; } if ( SUBREG_P ( src ) ) { pos += SUBREG_BYTE ( src ) * BITS_PER_UNIT ; src = SUBREG_REG ( src ) ; } switch ( GET_MODE ( src ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx d , pat ; dstmode = mode_for_size ( size , MODE_INT , <NUM_LIT> ) ; switch ( dstmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V16QImode ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; srcmode = V8HImode ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V4SImode ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; srcmode = V2DImode ; break ; default : return false ; } if ( pos & ( size - <NUM_LIT>


<s> DebugLoc DL ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ <STR_LIT> ] ; MachineInstrBuilder MIB ; unsigned Opc = ( ( FrameSize <= <NUM_LIT> ) && ! SaveS2 ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; addSaveRestoreRegs ( MIB , CSI ) ; if ( SaveS2 ) MIB . addReg ( <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) MIB . addImm ( FrameSize ) ; else { int Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; MIB . addImm ( Base


<s> BaseKind getKind ( ) const { return Kind


<s> if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand (

<NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint ; if ( isa < Instruction > ( OffsSecondOperand ) ) InsertionPoint = & cast < Instruction > ( OffsSecondOperand ) -> getParent ( ) -> back ( ) ; else InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( StartIndex ) -> back ( ) ) ; Instruction * NewIndex = BinaryOperator :: Create ( Instruction :: Add , Phi -> getIncomingValue

( StartIndex ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( ! IsPIC && ! IsN64 ) { JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; HiPart = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI ) ; JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; } else { unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OfstFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , GOTFlag ) ; JTI = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI ) ; HiPart = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OfstFlag ) ; } SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest ) return ; other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; other_root_iter ++ ) ( * other_root_iter ) ->


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { llvm :: RegisterTarget < llvm :: Triple :: mina32 > X (

llvm :: getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> DominatorTree * DT = nullptr ; if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ; if ( DT == nullptr && ( NumInterestingAllocas > <NUM_LIT> || ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) ) { DeleteDT = std :: make_unique < DominatorTree > ( * F ) ; DT = DeleteDT . get ( ) ; } std :: unique_ptr < PostDominatorTree > DeletePDT ; PostDominatorTree * PDT = nullptr ; if ( auto * P = getAnalysisIfAvailable < PostDominatorTreeWrapperPass > ( ) ) PDT = & P -> getPostDomTree ( ) ; if ( PDT == nullptr && ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) { DeletePDT = std :: make_unique < PostDominatorTree > ( * F ) ; PDT = DeletePDT . get ( ) ; } SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = insertBaseTaggedPointer ( Allocas , DT ) ; for ( auto & I : Allocas ) { const AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( Info . Tag < <NUM_LIT> ) continue ; IRBuilder < > IRB ( Info . AI -> getNextNode ( ) ) ; Function * TagP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> , { Info . AI -> getType ( ) } ) ; Instruction * TagPCall = IRB . CreateCall ( TagP , { Constant :: getNullValue ( Info . AI -> getType ( ) ) , Base , ConstantInt :: get ( IRB . getInt64Ty ( ) , Info . Tag ) } ) ; if ( Info . AI -> hasName ( ) ) TagPCall -> setName ( Info . AI -> getName ( ) + <STR_LIT> ) ; Info . AI -> replaceAllUsesWith ( TagPCall ) ; TagPCall -> setOperand ( <NUM_LIT> , Info . AI ) ; if ( UnrecognizedLifetimes . empty ( ) && Info . LifetimeStart . size ( ) == <NUM_LIT> && Info . LifetimeEnd . size ( ) == <NUM_LIT> ) { IntrinsicInst * Start = Info . LifetimeStart [ <NUM_LIT> ] ; IntrinsicInst * End = Info . LifetimeEnd [ <NUM_LIT> ] ; uint64_t Size = cast < ConstantInt > ( Start -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Size = alignTo ( Size , kTagGranuleSize ) ; tagAlloca ( AI , Start -> getNextNode ( ) , Start -> getArgOperand ( <NUM_LIT> ) , Size ) ; if ( PDT != nullptr && postDominates ( PDT , End , Start ) ) { untagAlloca ( AI , End , Size ) ; } else { SmallVector < Instruction * , <NUM_LIT> > ReachableRetVec ; unsigned NumCoveredExits = <NUM_LIT> ; for ( auto & RI : RetVec ) { if ( ! isPotentiallyReachable ( Start , RI , nullptr , DT ) ) continue ; ReachableRetVec . push_back (


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> __ev64_opaque__ t ; t = __ev_mwhsmi (


<s> StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( MachineBasicBlock * BB : depth_first_ext ( Entry , Processed ) ) Changed |= processBasicBlock ( MF , * BB ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) if ( Processed . insert ( BB ) . second ) Changed |= processBasicBlock ( MF , * BB ) ; LiveBundles . clear (


<s> MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand (

<NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) ) break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranch26TargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO


<s> std :: string Ret ; if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ; } ; MVT KeptBitsVT = <STR_LIT> ( KeptBits ) ; return VTIsOk ( XVT ) && VTIsOk ( KeptBitsVT


<s> OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; recordSled ( CurSled , MI , SledKind


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << -


<s> SVEPostVectorize ( ) : FunctionPass ( ID ) { initializeSVEPostVectorizePass ( * PassRegistry :: getPassRegistry (


<s> if ( IsCmpxchg ) { contBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; cont2BB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; } MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; if ( IsCmpxchg ) { MF -> insert ( It , contBB ) ; MF -> insert ( It , cont2BB ) ; } MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned storesuccess = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( ptr ) ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( <STR_LIT> ) ; if ( IsCmpxchg ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( i == <NUM_LIT> ? destlo : desthi ) . addReg ( i == <NUM_LIT> ? vallo : valhi ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( exitMBB ) ; BB -> addSuccessor ( i == <NUM_LIT> ? contBB : cont2BB ) ; BB = ( i == <NUM_LIT> ?


<s> if ( ET == <STR_LIT> && ( ValidFPToUint || Op . getOpcode ( ) == <STR_LIT> ) && isOperationLegalOrCustom ( Op . getOpcode ( ) , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return true ; } LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op ) ; if ( ! LD || LD -> getExtensionType ( ) != ET || LD -> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ; if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr


<s> bool isSVEPreferredLogicalImm ( ) const { return isLogicalImm < T > ( ) && ! isSVECpyImm


<s> if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return <NUM_LIT> ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm


<s> case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT>


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost (


<s> StringRef Name = <STR_LIT> ; return MCSymbolRefExpr :: Create ( Context . GetOrCreateSymbol (

Name ) , MCSymbolRefExpr :: VK_PLT , Context ) ;


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV2I64VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV2F64VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( DL , Mask , Zeroable ,


<s> } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; } } } if ( ! isa < ConstantSDNode > ( RHS ) || ! isLegalArithImmed ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ) ) { SDValue TheLHS = isCMN ( LHS , CC ) ? LHS . getOperand ( <NUM_LIT> ) : LHS ; if ( getCmpOperandFoldingProfit ( TheLHS ) > getCmpOperandFoldingProfit ( RHS ) ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } } SDValue Cmp ; <STR_LIT>


<s> EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ;


<s> static const SDValue * getNormalLoadInput ( const SDValue & Op , bool & IsPermuted ) { const SDValue * InputLoad = & Op ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> || InputLoad -> getOpcode ( ) == <STR_LIT> ) { IsPermuted = InputLoad -> getOpcode ( ) == <STR_LIT> ; InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; } if ( InputLoad -> getOpcode ( )


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective =


<s> uint64_t getPC16DBLTLSEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT>


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Align ( Size ) ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; const Align RestAlign = std :: min ( Alignment , Align ( Size ) ) ; for ( auto & It : PendingMembers ) { It . convertToMem ( State . AllocateStack ( Size , Alignment ) ) ; State . addLoc (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( Op . getValueType ( ) ) ) return LowerFixedLengthInsertVectorElt ( Op , DAG ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ||

VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: cvtLdWriteBackRegT2AddrModeImm8 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > &


<s> const char * getPassName ( ) const override { return


<s> const MCExpr * Disp ; if ( parseAddress ( Base , Disp , Index , Regs , RegKind , HasIndex ) ) return MatchOperand_ParseFail ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createMem ( RegKind , Base , Disp , Index ,


<s> break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr :: create ( ME , Kind , Ctx ) ; return MCOperand :: createExpr (


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getValueSizeInBits ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ) { SDValue N00 = N0 .


<s> EVT CmpVT = OpSize == <NUM_LIT> ? <STR_LIT> : VecVT ; SDValue Cmp ; if ( IsOrXorXorCCZero ) { SDValue A = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue D = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp1 = DAG . getSetCC ( DL , CmpVT , A , B , <STR_LIT> ) ; SDValue Cmp2 = DAG . getSetCC ( DL , CmpVT , C , D , <STR_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , Cmp1 , Cmp2 ) ; } else { SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } if ( OpSize == <NUM_LIT> ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; SDValue MovMsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cmp ) ; SDValue FFFFs = DAG . getConstant ( OpSize == <NUM_LIT> ? <NUM_LIT> :


<s> void \ switch_to_section ( enum in_section section , tree decl ) \ { \ switch ( section ) \ { \ case in_text : text_section ( ) ; break ; \ case in_unlikely_executed_text : unlikely_text_section ( ) ; break ; \ case in_data : data_section ( ) ; break ; \ case in_readonly_data : readonly_data_section ( ) ; break ; \ case in_named : named_section ( decl , NULL , <NUM_LIT> ) ; break

; \ case in_drectve : drectve_section ( ) ; break ; \ default : abort ( ) ; break ; \ } \ }


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_ICMP ) ; LLT WideTy = MRI . getType ( WideReg ) ; Builder . setInstrAndDebugLoc ( MI ) ; auto WideZero = Builder . buildConstant ( WideTy , <NUM_LIT> ) ; Observer . changingInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( WideReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( WideZero


<s> case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op ,


<s> if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset = PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else return <NUM_LIT> ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( <NUM_LIT> ) . getCFIIndex (


<s> return ( __m128i ) __builtin_ia32_phsubw128 ( ( __v8hi ) __X ,


<s> } if ( ( Flags & ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) == <NUM_LIT> && any_of ( M , [ ] ( const Function & F ) { return F . hasFnAttribute ( <STR_LIT> ) ; } ) ) { errs ( ) << <STR_LIT> <STR_LIT> << <STR_LIT> ; } if ( any_of ( M , [ ] ( const Function & F ) { if ( F . isDeclaration ( ) ) return false ; Attribute A = F . getFnAttribute ( <STR_LIT> ) ; return ! A . isStringAttribute ( ) || A . getValueAsString ( ) == <STR_LIT> ; } ) ) { Flags &= ~ ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; } if ( Flags == <NUM_LIT> ) return ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> * <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> emitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( Flags


<s> } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Lex ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( L , <STR_LIT> ) ; return


<s> SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutLo = DAG . getSelectCC ( dl , Tmp5 , DAG . getConstant ( <NUM_LIT> , AmtVT ) , Tmp4 , Tmp6 ,


<s> SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> ,


<s> SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; return RetAddr


<s> if ( auto Splat = getVectorSplat ( MI , MRI ) ) return Splat ; if ( MI . getOpcode ( ) != <STR_LIT> ) return None ; Register Src = MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>AsmParser :: expandMem9Inst ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI , bool IsLoad ) { unsigned NumOp = Inst . getNumOperands ( ) ; assert ( ( NumOp == <NUM_LIT> || NumOp == <NUM_LIT> ) && <STR_LIT> ) ; unsigned StartOp = NumOp == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; const MCOperand & DstRegOp = Inst . getOperand ( StartOp ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & BaseRegOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; assert ( BaseRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned OpCode = Inst . getOpcode ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned BaseReg = BaseRegOp . getReg ( ) ; unsigned TmpReg = DstReg ; const MCInstrDesc & Desc = getInstDesc ( OpCode ) ; int16_t DstRegClass = Desc . OpInfo [ StartOp ] . RegClass ; unsigned DstRegClassID = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( DstRegClass ) . getID ( ) ; bool IsGPR = ( DstRegClassID == <STR_LIT> ) || ( DstRegClassID == <STR_LIT> ) ; if ( ! IsLoad || ! IsGPR || ( BaseReg == DstReg ) ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return ; } auto emitInst = [ & ] ( ) { if ( NumOp == <NUM_LIT> ) TOut . emitRRX ( OpCode , DstReg , TmpReg , MCOperand :: createImm ( <NUM_LIT> ) , IDLoc , STI ) ; else TOut . emitRRRX ( OpCode , DstReg , DstReg , TmpReg , MCOperand :: createImm ( <NUM_LIT> ) , IDLoc , STI ) ; } ; if ( OffsetOp .


<s> static <STR_LIT> getAdjustedCmp ( <STR_LIT> Cmp ) { switch ( Cmp ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { if ( LHSDef -> getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHSDef -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res ,


<s> if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) -> getVectorElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode ==

Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ;


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; EVT CarryVT = Carry . getValueType ( ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getAllOnesConstant ( DL , CarryVT ) ) ; bool IsAdd = Opc == <STR_LIT> || Opc == <STR_LIT> ; SDValue Sum = DAG . getNode ( IsAdd ? <STR_LIT> : <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; bool IsSigned = Opc == <STR_LIT> || Opc == <STR_LIT> ; SDValue SetCC = getSETCC ( IsSigned ? <STR_LIT> : <STR_LIT> , Sum . getValue ( <NUM_LIT> ) , DL , DAG ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SDLoc dl ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; if ( ! Fn -> hasPersonalityFn ( ) ) return EntryEBP ; MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT


<s> if ( SignReturnAddressAll ) return true ; return SpillsLR


<s> rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > <NUM_LIT> ) if ( ( i


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT>


<s> void emitLocalEntry ( MCSymbolELF * S ,


<s> bool <ISA_LIT>InstructionSelector :: selectVectorASHR ( MachineInstr & I , MachineRegisterInfo & MRI ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_ASHR ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; unsigned NegOpc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto Neg = MIB . buildInstr ( NegOpc , { RC } , { Src2Reg } ) ; constrainSelectedInstRegOperands ( * Neg , TII , TRI , RBI ) ; auto SShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Neg } ) ; constrainSelectedInstRegOperands ( * SShl , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_PAIRED ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_SPE ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) ==

RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name ) ;


<s> void printi128mem ( const MachineInstr * MI , unsigned OpNo ) { printMemReference ( MI , OpNo


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MVT SrcVT = N0 . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( DstVT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getUINTTOFP ( SrcVT , DstVT ) ) ; if ( DstVT . isVector ( ) ) return lowerUINT_TO_FP_vec ( Op , DAG , Subtarget ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( Subtarget . hasAVX512 ( ) && isScalarFPTypeInSSEReg ( DstVT ) && ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) ) { return Op ; } if ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , N0 ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot ,


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , DL

, DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> else if ( sizeof ( HOST_WIDE_INT ) == sizeof ( int64_t ) ) fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_HEX_PURE , ( HOST_WIDE_INT ) value ) ; else fprintf ( stream , <STR_LIT> PRIu64 , value ) ; if ( do_begin_end ) fprintf ( stream ,


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( )


<s> for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( isSwiftDuplicatable ( I ) ) { MachineInstr * slaveinst = MF . CloneMachineInstr ( & * I ) ; slaveinst -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { if ( I -> getOperand ( opcount ) . isReg ( ) ) { slaveinst -> getOperand ( opcount ) . setReg ( getSlaveReg ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; } } MBB -> insert ( I


<s> MachineIRBuilder MIB ( I ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . buildInstr ( <STR_LIT> , { TargetReg , ScratchReg } , { JTAddr , Index } ) . addJumpTableIndex ( JTI ) ; MIB . buildInstr ( <STR_LIT> , { } , { TargetReg } ) ; I . eraseFromParent ( ) ; return true


<s> static inline bool Thumb2SaturateOpcode ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ; if ( ! FalseBlock


<s> Inst . addOperand ( MCOperand :: CreateReg (


) ) _mm_load1_ps ( float const * __P ) {


<s> for ( unsigned Form = <NUM_LIT> ; Form < <NUM_LIT> ; Form ++ ) if ( Opcode == RegOpcodes [


<s> SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & Mtc1Tdd = get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg


<s> void addUImm6Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast <


<s> __arm_vldrbq_gather_offset_s32 ( int8_t const *


<s> if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return <NUM_LIT> ; if ( ( REG_P ( XEXP ( a , <NUM_LIT> ) ) || ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) && ( REG_P ( XEXP ( b , <NUM_LIT> ) ) || ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) { HOST_WIDE_INT val0 = <NUM_LIT> , val1 = <NUM_LIT> ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ; val0 = INTVAL ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg0 = XEXP ( a , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ; val1 = INTVAL ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg1 = XEXP ( b , <NUM_LIT> ) ; if ( ! const_ok_for_op ( val0 , PLUS ) || ! const_ok_for_op ( val1 , PLUS ) ) return <NUM_LIT> ; if ( arm_eliminable_register ( reg0 ) ) return <NUM_LIT> ; val_diff = val1 - val0 ; if ( arm_ld_sched )


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate , S , E ) ; Op -> Imm . Val = Val ; return Op


<s> case <STR_LIT> : Pos = Lsb ; Size = Msbd + <NUM_LIT> - Pos ; break ; case <STR_LIT> : Pos = Lsb ; Size = Msbd + <NUM_LIT> - Pos ; break ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> - Pos ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } InsnType Rs = fieldFromInstruction ( Insn


<s> FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else IAH . Out ( <STR_LIT> + Name ) ; swapFPIntParams ( PV , M , IAH , LE , false ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( LocalName + <STR_LIT>


<s> MachineFunction & MF = * MBB . getParent ( ) ; unsigned FramePtr = TRI -> getFrameRegister ( MF ) ; unsigned BasePtr = TRI -> getBaseRegister ( ) ; WinEHFuncInfo & FuncInfo = * MF . getWinEHFuncInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI -> getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned


<s> static void parseCondBranch ( MachineInstr * LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT>


<s> return OriginalArgWasFloatVector [ ValNo


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initAsmInfo (


<s> static <ISA_LIT>Operand * CreateVectorList ( unsigned RegNum , unsigned Count , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_VectorList ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> void printMemRegReg ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { const MachineOperand & MO = MI ->


<s> aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + <NUM_LIT> ) ; bitmap_clear ( components ) ; for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM )

bitmap_clear_bit ( components , reg2 ) ;


<s> y3 = gen_reg_rtx ( DFmode ) ; u0 = gen_reg_rtx ( DFmode ) ; v0 = gen_reg_rtx ( DFmode ) ; one = force_reg ( DFmode , CONST_DOUBLE_FROM_REAL_VALUE ( dconst1 , DFmode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( DFmode , gen_rtvec ( <NUM_LIT> , d ) , UNSPEC_FRES ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MINUS ( DFmode , one , gen_rtx_MULT ( SFmode , d , x0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y1 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e0 , x0 ) , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( DFmode


<s> if ( ! AMI || AMI -> isPseudo ( ) || AMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , nullptr , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , nullptr ) ) ) return false ; for ( SDep & BDep : APreds ) { if ( BDep . isWeak ( ) ) continue ; SUnit * BSU = BDep . getSUnit ( ) ; const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ; if ( Preds ) DAG -> addEdge ( ASU , SDep ( BSU , SDep :: Cluster ) ) ; else DAG -> addEdge ( BSU , SDep ( ASU , SDep :: Cluster ) ) ; for ( SDep & Dep : APreds ) if ( Dep . getSUnit ( ) == BSU ) Dep . setLatency ( <NUM_LIT> ) ; auto & BSuccs = Preds ? BSU -> Succs : BSU -> Preds ; for ( SDep & Dep : BSuccs ) if ( Dep . getSUnit ( ) == ASU ) Dep . setLatency ( <NUM_LIT> ) ; ++ NumFused ; DEBUG ( { SUnit * LSU = Preds ? BSU : ASU ; SUnit * RSU = Preds ? ASU : BSU ; const MachineInstr * LMI = Preds ? BMI : AMI ; const MachineInstr * RMI = Preds ? AMI :


<s> MVT SVT = In . getValueType ( ) . getSimpleVT ( ) ; if ( Subtarget -> hasFp256 ( ) ) { SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; } if ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) return SDValue ( ) ; assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & Mask [ <NUM_LIT> ] ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo


<s> if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI , MII , MRI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI , MII , MRI ) ; return


<s> const DataLayout & DL = MF . getDataLayout ( ) ; return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + Twine ( MF . getFunctionNumber ( ) )


<s> static void addSavedGPR ( MachineBasicBlock & MBB , MachineInstrBuilder & MIB , unsigned GPR64 , bool IsImplicit ) { const TargetRegisterInfo * RI = MBB . getParent ( ) -> getTarget (


<s> else error ( <STR_LIT> <STR_LIT> , type ) ; } return <NUM_LIT> ; } return <NUM_LIT> ; } if ( ! decl ) return <NUM_LIT> ; cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && ( target_opts_for_fn ( target -> decl ) -> x_ix86_fpmath & FPMATH_SSE ) && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { if ( ! TARGET_SSE && warn ) { error ( <STR_LIT> <STR_LIT> , decl ) ; return <NUM_LIT> ; } return TARGET_SSE2_P ( target_opts_for_fn ( target -> decl ) -> x_ix86_isa_flags


<s> assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; SDValue Glue ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( auto * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( IsTailCall ) { Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Callee , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Callee = DAG . getRegister ( <STR_LIT> , Callee . getValueType ( ) ) ; } for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) Ops . push_back ( DAG . getRegister ( RegsToPass [ I ] . first , RegsToPass [ I ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( IsTailCall ) return DAG . getNode ( <STR_LIT> ,


<s> bool isUImm ( ) const { if ( ! isImm ( ) ) return false ; int64_t


<s> void <ISA_LIT>InstPrinter :: printExtendedRegister ( const MCInst * MI , unsigned OpNum ,


<s> mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp ,


<s> unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl == NULL_TREE && ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> || strncmp (

name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) flags |= SECTION_BSS ;


<s> TransposedMatrix . resize ( <NUM_LIT> ) ; static constexpr int IntMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = makeArrayRef ( IntMask1 , <NUM_LIT> ) ; Value * IntrVec1 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec2 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask2 , <NUM_LIT> ) ; Value * IntrVec3 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec4 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask3 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask3 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec3 , IntrVec4 , Mask ) ; static constexpr int IntMask4 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask4 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector (


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSubOrFMAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( SDValue LD = combineToConsecutiveLoads ( VT , SDValue ( N , <NUM_LIT> ) , dl , DAG , Subtarget , true ) ) return LD ; if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG


<s> const MCFixupKind FK = Fixup . getKind ( ) ; const unsigned Log2Size = getFixupKindLog2Size ( FK ) ; const bool IsPCRel = Writer -> isFixupKindPCRel ( Asm , FK ) ; const unsigned RelocType = getRelocType ( Target , FK , IsPCRel ) ; if ( Target . getSymB ( ) && RelocType != MachO :: <ISA_LIT>_RELOC_BR24 && RelocType != MachO :: <ISA_LIT>_RELOC_BR14 ) { recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } const MCSymbol * A = nullptr ; if ( Target . getSymA ( ) ) A = & Target . getSymA ( ) -> getSymbol ( ) ; const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; unsigned Index = <NUM_LIT> ; unsigned Type = RelocType ; const MCSymbol * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( A -> isVariable ( ) ) { int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( * A ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout .


<s> if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ; ScaledConstant /= Scale


<s> while ( MBIter != EndIter ) { MachineInstr * MI = & * MBIter ; Register PredReg ; DebugLoc DL = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI


<s> ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; for ( SUnit & ISU : DAG -> SUnits ) scheduleAdjacentImpl ( DAG ,


<s> bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; uint8_t OpFlagHi = IsPIC ? <STR_LIT> : <STR_LIT> ; uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getBlockAddress ( BA , <STR_LIT> , true , OpFlagHi ) ; SDValue Lo = DAG . getBlockAddress ( BA , <STR_LIT> , true , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> ,


<s> rtx base , index ; bool something_reloaded = false ; base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! REG_OK_FOR_BASE_STRICT_P ( base ) ) { push_reload ( base , NULL_RTX , & XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; something_reloaded = true ; } index = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_OK_FOR_INDEX_STRICT_P ( index )


<s> if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_SMALL ) * f ++ = 's' ; if ( flags & SECTION_MEP_VLIW ) * f ++ = 'v' ; * f = '\0' ; if ( flags & SECTION_BSS ) type


<s> MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg128 = LowRegOp . getReg ( ) ; unsigned Reg128Killed = getKillRegState ( LowRegOp . isKill ( ) ) ; unsigned Reg128Undef = getUndefRegState ( LowRegOp . isUndef ( ) ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; if ( MI -> mayStore ( ) ) { unsigned Reg128UndefImpl = ( Reg128Undef | RegState :: Implicit ) ; MachineInstrBuilder ( MF , EarlierMI ) . addReg ( Reg128 , Reg128UndefImpl ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg128 , ( Reg128UndefImpl | Reg128Killed ) ) ; } MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i !=


<s> static <ISA_LIT>Operand * CreateVectorIndex ( unsigned Idx , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_VectorIndex , Ctx ) ; Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc =


<s> rtx parts [ <NUM_LIT> ] ; int i , words ; unsigned regno = REGNO ( reg ) ; machine_mode mode = GET_MODE ( reg ) ; if ( TARGET_SPE && regno < <NUM_LIT> && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SFmode && mode != SDmode && mode != SCmode ) ) ) ; else return NULL_RTX ; regno = REGNO ( reg ) ; words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - <NUM_LIT> ) / UNITS_PER_FP_WORD ; gcc_assert ( words <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < words ; i ++ , regno ++ ) { if ( BYTES_BIG_ENDIAN ) { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno ) ; } else { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; } } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( words *


<s> if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && neon_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( ( target = neon_vdup_constant ( vals ) ) != NULL_RTX


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo (


<s> unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; return ResultReg


<s> SDValue SRL ( int sh , SDValue A ) { MVT VT = A . getSimpleValueType ( ) ; int NumElts = VT . getVectorNumElements


<s> unsigned FromSz = LdVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( Mld -> getSrc0 ( ) . getOpcode ( ) != <STR_LIT> ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat =


<s> EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin (


<s> if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT> : NumVectors ) ; case TargetTransformInfo :: SK_Broadcast : return NumVectors - <NUM_LIT> ; default : return NumVectors


<s> } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor ( TgtMBB ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) ) ; assert ( LongBrMBB -> size ( ) == LongBranchSeqSize ) ; } if ( I . Br -> isUnconditionalBranch ( ) ) { assert ( I . Br -> getDesc ( ) . getNumOperands ( ) ==


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; return ResultReg ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg

( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ;


<s> return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned CPI = getCombinedIndex ( CPEMI ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [ CPI


<s> if ( ! Store -> isSimple ( ) ) return SDValue ( ) ; EVT StoreVT = StoredVal . getValueType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned HalfSize = StoredVal . getValueSizeInBits ( ) / <NUM_LIT> ; unsigned HalfAlign = ( <NUM_LIT> == HalfSize ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Store ) ; SDValue Value0 = extractSubVector ( StoredVal , <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Value1 = extractSubVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swapt1qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swapt1hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swapt1si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swapt1di_1 ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swap32qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swap32hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swap32si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swap32di_1 ; break ; default : gcc_unreachable ( ) ; } } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ <NUM_LIT> ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst ,


<s> if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO ) ; else printOperand ( MI , OpNo ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo ) ; return false ; } return true ; case 'b' : case 'h'


<s> if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { SReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( TargetRegisterInfo :: isVirtualRegister ( SReg ) ) { if ( MO -> getSubReg ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> if ( ! IsTailCall ) { SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( Arg . getValueSizeInBits (


<s> int _U_Qfunle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD | QCMP_EQ |


<s> AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> Inst . addOperand ( MCOperand :: createReg (


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getResNo ( ) == <NUM_LIT> && N0 . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDLoc dl ( N ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , VT ) ; SDValue R = DAG . getNode ( <STR_LIT> , dl , NodeTys , N0 . getOperand (

<NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ;


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PAGE , <STR_LIT> } , { MO_PAGEOFF , <STR_LIT> } , { MO_G3 , <STR_LIT> } , { MO_G2 , <STR_LIT> } , { MO_G1 , <STR_LIT> } , { MO_G0 , <STR_LIT> } , { MO_HI12 , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; SET_HARD_REG_BIT ( full_reg_clobbers , R0_REGNUM ) ; SET_HARD_REG_BIT ( full_reg_clobbers , CC_REGNUM ) ; for ( int regno = P0_REGNUM ; regno <= P15_REGNUM ; ++ regno ) SET_HARD_REG_BIT ( full_reg_clobbers , regno ) ; tlsdesc_abi . initialize ( ARM_PCS_TLSDESC , full_reg_clobbers ) ; } return tlsdesc_abi . id


<s> MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects (


<s> if ( ! get<ISA_LIT>Subtarget ( ) . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass


<s> SDValue Chain = HasChainIn ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HasI64In ) { SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InLo , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InHi , Chain . getValue ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . append ( Op -> op_begin ( ) + HasChainIn + <NUM_LIT> , Op -> op_end ( ) ) ; Ops . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } else { Ops . push_back (


<s> return decodeBDXAddr20Operand ( Inst , Field ,


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) .


<s> Value * <ISA_LIT>IREmitter :: visitHADD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return mode


<s> virtual bool check ( MachineBasicBlock & BB , const MachineInstr & MI ) const { return MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOpcode ( ) ==


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_PC32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_32S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_64 ; case <STR_LIT> : default : llvm_unreachable ( <STR_LIT>


<s> return parsePKHImm ( O , <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable ; else InstTable = ReverseSTiTable ; } int Opcode = Lookup ( InstTable , MI -> getOpcode ( ) ) ; assert ( Opcode != - <NUM_LIT> && <STR_LIT> ) ; unsigned NotTOS = ( TOS == Op0 ) ? Op1 : Op0 ; MBB -> remove ( I ++ ) ; I = BuildMI ( * MBB , I , dl , TII -> get ( Opcode ) ) . addReg ( getSTReg ( NotTOS ) ) ; if ( KillsOp0 && KillsOp1 && Op0 != Op1 ) { assert ( ! updateST0 && <STR_LIT> ) ; popStackAfter ( I ) ; } unsigned UpdatedSlot = getSlot ( updateST0 ? TOS : NotTOS ) ; assert ( UpdatedSlot < StackTop && Dest < <NUM_LIT> ) ; Stack [ UpdatedSlot ] = Dest ; RegMap [ Dest ] = UpdatedSlot ; MBB -> getParent ( ) ->


<s> SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getBitcast ( VT ,


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT

. isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) {


<s> EVT SVT = VT . getScalarType ( ) ; EVT InVT = In . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( InVT ) && TLI . isTypeLegal ( VT ) && isSATValidOnAVX512Subtarget ( InVT , VT , Subtarget ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( )

, <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSORegRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Binary = get<ISA_LIT>RegisterNumbering ( MO


<s> return TM . getRelocationModel ( ) == Reloc ::


<s> SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddTOC , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , Glue ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; Glue = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , Glue ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; Glue = EnvVal . getValue


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { printS16ImmOperand ( MI , OpNo ) ; } else { if ( Subtarget . isDarwin ( ) ) O << <STR_LIT> ; printOp ( MI -> getOperand ( OpNo ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_

) O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ;


<s> if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; if ( PPC405_ERRATUM77 ) emit_insn


<s> int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ( TARGET_HARD_FLOAT && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return <NUM_LIT> ; else if ( FLOAT128_VECTOR_P ( mode ) ) return <NUM_LIT> ; else if ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> && int_size_in_bytes ( type ) < <NUM_LIT> ) return <NUM_LIT> ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) || DEFAULT_ABI == ABI_ELFv2 ) && type && TYPE_ALIGN ( type ) > <NUM_LIT> ) { if ( AGGREGATE_TYPE_P ( type ) && ! SCALAR_FLOAT_MODE_P ( elt_mode ) )


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) { Subtarget = & funcInfo . MF -> getSubtarget <


<s> if ( call_cookie & CALL_SHORT ) return <NUM_LIT> ; if ( TARGET_LONG_CALLS ) { if ( flag_function_sections || DECL_SECTION_NAME ( current_function_decl ) ) return <NUM_LIT> ; } if ( current_file_function_operand ( sym_ref ) ) return <NUM_LIT> ; return ( call_cookie & CALL_LONG ) || ENCODED_LONG_CALL_ATTR_P ( XSTR

( sym_ref , <NUM_LIT> ) ) || TARGET_LONG_CALLS ;


<s> SItype __umodsi3 ( SItype a , SItype b ) { return udivmodsi4 ( a , b ,