<s> static SDValue combineVPMADD ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( LHS . getNode ( ) ) || <STR_LIT> ( RHS . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; return SDValue ( )


<s> uint64_t <ISA_LIT>PLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = <NUM_LIT> ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < <ISA_LIT>PLT0 > ( ( * it ) ) . getValue ( ) , <ISA_LIT>PLT0 :: EntrySize ) ; result += <ISA_LIT>PLT0 :: EntrySize ; ++ it ; <ISA_LIT>PLTA * plta = <NUM_LIT> ; for ( iterator ie = end ( ) ; it !=


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand (

MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? Subtarget -> getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( *


<s> <ISA_LIT>StackTagging ( bool IsOptNone = false ) : FunctionPass ( ID ) , MergeInit ( ClMergeInit . getNumOccurrences ( ) ? ClMergeInit : ! IsOptNone ) , UseStackSafety ( ClUseStackSafety . getNumOccurrences ( )


<s> curr_state = state -> dfa_state ; state -> time ++


<s> unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits - <NUM_LIT> ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL , <NUM_LIT> ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst TC ; TC . setOpcode ( OpCode ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( TC , getSubtargetInfo ( )


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: EmitWinEHHandlerData


<s> bool hasReservedCallFrame ( MachineFunction & MF


<s> FunctionPass * llvm :: create<ISA_LIT>PostRewritePass ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>PostRewrite


<s> NumRegs = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , NumRegs , PendingHAMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingHAMembers . begin ( ) ; It != PendingHAMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingHAMembers . clear ( ) ; return true ; } for ( unsigned regNo = <NUM_LIT> ; regNo < <NUM_LIT> ; ++ regNo ) State . AllocateReg ( SRegList [ regNo ] ) ; unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned Align = Size ; if ( LocVT . SimpleTy == <STR_LIT> || LocVT . SimpleTy == <STR_LIT> ) { Align = <NUM_LIT> ; } for ( auto It : PendingHAMembers ) { It . convertToMem ( State . AllocateStack ( Size , Align ) ) ; State . addLoc ( It ) ; Align =


<s> static tree aarch64_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == <NUM_LIT> ) return float_type_node ; return NULL_TREE


<s> O << <STR_LIT> ; printSrcIdx ( MI , OpNo


<s> HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } SDValue Chain = HI . getValue ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , HI . getValue ( <NUM_LIT> ) ) ; Chain = DAG . getStore ( ecx . getValue ( <NUM_LIT> ) , DL , ecx , N -> getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } if ( Subtarget . is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI

, DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> MVT getVectorIdxTy ( const DataLayout & DL ) const override { return


<s> FixedVectorType * Ty ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; else Ty = cast < FixedVectorType > ( I -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Loop * L = LI -> getLoopFor ( I -> getParent ( ) ) ; if ( L == nullptr ) return nullptr ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = decomposeGEP ( Offsets , Ty , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DataLayout DT = I -> getParent ( ) -> getParent ( ) -> getParent ( ) -> getDataLayout ( ) ; int TypeScale = computeScale ( DT . getTypeSizeInBits ( GEP -> getOperand ( <NUM_LIT> ) -> getType ( ) ) , DT . getTypeSizeInBits ( GEP -> getType ( ) ) / cast < FixedVectorType > ( GEP -> getType ( ) ) -> getNumElements ( ) ) ; if ( TypeScale == - <NUM_LIT>


<s> rtx src = DECL_RTL ( fpscr_values ) ; if ( ! can_create_pseudo_p ( ) ) { emit_move_insn ( scratch , XEXP ( src , <NUM_LIT> ) ) ; if ( index != <NUM_LIT> ) emit_insn ( gen_addsi3 ( scratch , scratch , GEN_INT ( index * <NUM_LIT> ) ) ) ; src = adjust_automodify_address ( src , SImode , scratch ,


<s> assert ( ! RegInfo -> needsStackRealignment ( MF ) && <STR_LIT> ) ; return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( )


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ElemVT = VT . getScalarType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; switch ( ElemVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign


<s> RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs ] , VReg ) ; ArgValue = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( GPRArgRegs [ NumGPRs + <NUM_LIT> ] , VReg ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Root , dl , VReg , <STR_LIT> ) ; assert ( ObjectVT != <STR_LIT> && <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } NumGPRs += ObjGPRs ; if ( ObjSize ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( ObjGPRs == <NUM_LIT> ) ArgValue = DAG . getLoad ( ObjectVT , dl , Root , FIN , NULL , <NUM_LIT> ) ; else { SDValue ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , NULL , <NUM_LIT> ) ; assert ( ObjectVT != <STR_LIT> && <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl ,


<s> assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset / <NUM_LIT> ; assert ( ( RPI . Offset >= - <NUM_LIT> && RPI . Offset <= <NUM_LIT> ) && <STR_LIT> ) ; RegPairs . push_back ( RPI ) ; if ( RPI . isPaired ( )


<s> if ( CstMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) return true ; unsigned Amount = CstMI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; assert ( MRI . getType ( AmtReg ) . getSizeInBits ( ) == <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const { return ! Subtarget -> hasMinSize ( ) || Subtarget -> isTargetWindows (


<s> return ( TARGET_SVE && ( mode == VNx16BImode || mode == VNx8BImode || mode == VNx4BImode || mode ==


<s> return ; } if ( value >= - <NUM_LIT> && value <= <NUM_LIT> ) { insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , GEN_INT ( value ) ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return ; } hi = trunc_int_for_mode ( value & <NUM_LIT> , SImode ) ; lo = value & <NUM_LIT> ; insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT


<s> if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) || MI . isImplicitDef ( ) ) return outliner :: InstrType :: Invisible ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return outliner :: InstrType :: Illegal ; const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t MIFlags = MCID . TSFlags ; if ( ( MIFlags & <STR_LIT> ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) ) { if ( isPredicated ( MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee )


<s> if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> const MCExpr * LHS = fixupVariantKind ( BE -> getLHS ( ) ) ; const MCExpr * RHS = fixupVariantKind ( BE -> getRHS ( ) ) ; if ( LHS == BE -> getLHS ( ) && RHS == BE -> getRHS ( ) ) return E ; return MCBinaryExpr :: create ( BE -> getOpcode (


<s> EHStreamer . EmitUnwindInfo ( * this


<s> assert ( MBB -> getParent ( ) -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ) ; return MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , MCSymbolRefExpr ::


<s> if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return


<s> return ( __m256i ) __builtin_ia32_pmovsxwd256_mask ( ( __v8hi ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8


<s> if ( ++ NextI == Update ) ++ NextI ; int Value = Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = getPreIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( Update -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( ! IsPCREL ) { InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; OrigRegs . push_back ( InReg ) ; } DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc1 , Opc2 ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : assert ( IsPCREL && <STR_LIT> ) ; Opc1 = <STR_LIT> ; Opc2 = MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi ; if ( IsPCREL ) { Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addImm ( <NUM_LIT> ) ; } else { assert ( InReg != <STR_LIT>


<s> Relocator :: Result adr_prel_lo21 ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: Address S = pReloc . symValue ( ) ; if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } Relocator :: DWord A =


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter >


<s> MaskCV [ i ] = Builder . getInt32 ( NumElts ) ; } else if ( Mask [ i ] == SM_SentinelUndef ) MaskCV [ i ] = UndefValue :: get ( EltTy ) ; else MaskCV [ i ] = Builder . getInt32 ( Mask [ i ] ) ; } assert ( ( ! V1IsZero ||


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; assert ( ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF


<s> bool isTargetMingw ( ) const { return TargetTriple . getOS ( ) == Triple :: MinGW32 || TargetTriple . getOS


<s> static unsigned char * unw_decode_b1 ( unsigned char * dp


<s> unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( EvenReg , TRC ) ; MRI -> constrainRegClass ( OddReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> , EvenReg ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) { MachineInstr * Op = Ops . back ( ) ; Ops . pop_back ( ) ; MBB -> splice ( InsertPos , MBB , Op ) ; } } NumLdStMoved += NumMove


<s> return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalBase , HiLo ) ; } SDValue HiLo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalBase , HiLo ) ; return DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG .


<s> return ( GET_CODE ( disp ) == UNSPEC && XINT ( disp ,

<NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) ;


<s> bool isUnconditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT>

) . getImm ( ) == <STR_LIT> ) return true ;


<s> loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( OldVal ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( loop1MBB ) ; MI . eraseFromParent (


<s> <ISA_LIT>ConstantPoolConstant :: <ISA_LIT>ConstantPoolConstant ( const GlobalVariable * GV , const Constant * C ) : <ISA_LIT>ConstantPoolValue ( ( Type * ) C -> getType ( )

, <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> , false ) , CVal ( C ) {


<s> const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; unsigned OffsetMask ; switch ( AddrMode ) { case <STR_LIT> : NumBits = <NUM_LIT> ; OffsetMask = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; OffsetMask = <NUM_LIT> ; break ; default : NumBits = <NUM_LIT> ; OffsetMask = <NUM_LIT> ; break ; } Scale = <NUM_LIT> ; assert ( ( Offset & OffsetMask ) == <NUM_LIT> && <STR_LIT> ) ; ( void ) OffsetMask ; } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; NumBits = <NUM_LIT> + <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale && ( Register :: isVirtualRegister ( FrameReg ) || RegClass -> contains ( FrameReg ) ) ) { if ( Register :: isVirtualRegister ( FrameReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> constrainRegClass ( FrameReg , RegClass ) ) llvm_unreachable ( <STR_LIT> ) ; } MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else ImmedOffset = - ImmedOffset ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> )


<s> return true ; case ELF :: R_<ISA_LIT>_GOT16 : return true ; case ELF :: R_<ISA_LIT>_HI16 : case ELF :: R_<ISA_LIT>_LO16 : case ELF :: R_<ISA_LIT>_32 : return true ; case ELF :: R_<ISA_LIT>_GPREL16 : return


<s> InsnType Imm = <NUM_LIT> ; bool HasRs = false ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT>


<s> } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; bool IsISRRegFI = <ISA_LIT>FI -> isISRRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI || IsISRRegFI ) FrameReg = ABI . GetStackPtr ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( MFI . hasVarSizedObjects ( ) && ! MFI . isFixedObjectIndex ( FrameIndex ) ) FrameReg = ABI . GetBasePtr ( ) ; else if ( MFI . isFixedObjectIndex ( FrameIndex ) ) FrameReg = getFrameRegister ( MF ) ; else FrameReg = ABI . GetStackPtr ( ) ; } else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) , MI . getOperand ( OpNo - <NUM_LIT> ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt <


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( A1 , A2 ) ) ) , Tmp ) ; } llvm_unreachable ( <STR_LIT> ) ; return SDValue ( )


<ISA_LIT>WinCOFFObjectWriter > ( Is64Bit ) ;


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S = MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: matchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false


<s> CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC


<s> if ( * CM != CodeModel :: Small && * CM != CodeModel :: Tiny && * CM != CodeModel :: Large ) { if ( ! TT . isOSFuchsia ( ) ) report_fatal_error ( <STR_LIT> ) ; else if ( * CM != CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else if ( * CM == CodeModel :: Tiny && ! TT . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; return *


<s> assert ( Opc == TargetOpcode :: G_FADD && <STR_LIT> ) ; LLT Ty = std :: get < <NUM_LIT> > ( MatchInfo ) ; Register Src = std :: get < <NUM_LIT> > ( MatchInfo ) ; LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; B . setInstrAndDebugLoc ( MI ) ; auto Elt0 = B . buildExtractVectorElement ( Ty , Src , B .


<s> return ; } calculate_dominance_info ( CDI_DOMINATORS ) ; protected_bbs = sbitmap_alloc ( last_basic_block_for_fn ( cfun ) ) ; bitmap_clear ( protected_bbs ) ; rev_post_order = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n = pre_and_rev_post_order_compute ( NULL , rev_post_order , false ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , rev_post_order [ i ] ) ; if ( r10k_protected_bb_p ( bb , protected_bbs ) ) unprotected_region = NULL_RTX ; else unprotected_region = pc_rtx ; end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( unprotected_region && USEFUL_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_mips_cache ) unprotected_region = NULL_RTX ; else { if ( unprotected_region == pc_rtx ) unprotected_region = insn ; if ( r10k_needs_protection_p ( insn ) ) { emit_insn_before ( gen_r10k_cache_barrier ( )


<s> reg_1 = operands [ <NUM_LIT> ] ; mem_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) && REG_P ( reg_3 ) && REG_P ( reg_4 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) || REGNO ( reg_3 ) == REGNO ( reg_4 ) ) return false ; } else { mem_1 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; } if ( ! MEM_P ( mem_1 ) || aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) || MEM_VOLATILE_P ( mem_3 ) || MEM_VOLATILE_P ( mem_4 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3


<s> return ( __m128h ) __builtin_ia32_vfmulcsh_round ( ( __v8hf ) __A ,


<s> HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; DeprecatedMFTB = false ; DeprecatedDST =


<s> bool <ISA_LIT>AsmParser :: ParseIntelMemoryOperandSize ( unsigned & Size ) { Size = StringSwitch < unsigned > ( getTok ( ) . getString ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( Size ) { const AsmToken & Tok = Lex


<s> switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return val >= <NUM_LIT> && val < <NUM_LIT> ; case <NUM_LIT> : return val >= <NUM_LIT> && val < <NUM_LIT> && (


<s> } E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( E , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , Align , false , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; E = Parser . getTok ( ) . getLoc ( ) ; bool isNegative = getParser ( ) . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * Offset ; if ( getParser ( ) . ParseExpression ( Offset ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Offset ) ; if ( ! CE ) return Error ( E , <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) CE = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( E , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , CE , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , false , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; } E = Parser . getTok ( ) . getLoc ( ) ; int OffsetRegNum = tryParseRegister ( ) ; if ( OffsetRegNum == - <NUM_LIT> ) return Error ( E , <STR_LIT> ) ; <STR_LIT> ShiftType


<s> void printi8mem ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , <NUM_LIT> ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( ( code == LTU ) == ( operands [ <NUM_LIT> ] == constm1_rtx ) ) { switch ( mode ) { case E_QImode : insn = gen_subqi3_carry ; break ; case E_HImode : insn = gen_subhi3_carry ; break ; case E_SImode : insn = gen_subsi3_carry


<s> bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } if ( VT . isInteger ( ) && VT . getScalarSizeInBits ( ) < <NUM_LIT> && areAdjacentMasksSequential ( Mask ) ) { SmallVector < int , <NUM_LIT> > NewMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) NewMask . push_back ( Mask [ i ] / <NUM_LIT> ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , NewVT , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , NewMask ) ) ; } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; } BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS << '\x90' ; return true ; } uint64_t MaxNopLength = <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ; return true


<s> static bool isVFRegister ( unsigned Reg ) { return Reg >= <STR_LIT> &&


<s> TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo (


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified


<s> bool arm_current_function_pac_enabled_p ( void ) { return ( aarch_ra_sign_scope == AARCH_FUNCTION_ALL || ( aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF &&


<s> bool <ISA_LIT>BasicBlockUtils :: isBBInRange ( MachineInstr * MI , MachineBasicBlock * DestBB , unsigned MaxDisp ) const { unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = getOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp ) return true ; }


<s> bool SoftFloat = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSoftFloat ( ) ; if ( HasPackedStackAttr && BackChain && ! SoftFloat


<s> bool IsSplat = true ; bool Is32Bit = FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> ; EVT SrcVT = FirstInput . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; EVT TargetVT = N -> getValueType ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NextConversion = N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( NextConversion != FirstConversion ) return SDValue ( ) ; if ( N -> getOperand ( i ) != FirstInput ) IsSplat = false ; } if ( IsSplat ) return SDValue ( ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue In = N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( Is32Bit ) { if ( In . isUndef ( ) ) Ops . push_back ( DAG . getUNDEF ( SrcVT ) ) ; else { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , In . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Ops . push_back ( Trunc ) ; } } else Ops . push_back ( In . isUndef ( ) ? DAG . getUNDEF ( SrcVT ) : In . getOperand ( <NUM_LIT> ) ) ; } unsigned


<s> Parser . Lex ( ) ; Parser . Lex ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , S , getLoc ( ) , getContext ( ) ) ) ; StringRef value = TokE . getString ( ) ; const char * extTypeName = getGPROffsetExtTypeName ( value ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( extTypeName , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; SMLoc SSS = getLoc ( ) ; const AsmToken & TokH = Parser . getTok ( ) ; if ( TokH . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; const AsmToken & TokI = Parser . getTok ( ) ; if ( TokI . isNot ( AsmToken :: Integer ) ) { Error ( SSS ,


<s> s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE


<s> Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue >


<s> OS << <STR_LIT> << Size << <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo .


<s> SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getNode ( <STR_LIT> , DL ,

MaskVT , V1Mask ) , DAG . getNode ( <STR_LIT> , DL , MaskVT , V2 ) ) ) ;


<s> bool IsImm8 = int8_t ( Imm ) == Imm ; bool IsImm16 = int16_t ( Imm & ~ <NUM_LIT> ) == Imm ; if ( std :: is_same < int8_t , typename std :: make_signed < T > :: type > :: value ) return IsImm8 || uint8_t ( Imm ) == Imm ; if ( std :: is_same < int16_t , typename std :: make_signed < T > :: type > :: value ) return IsImm8 || IsImm16 || uint16_t ( Imm & ~ <NUM_LIT> ) == Imm ; return IsImm8 ||


<s> MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI . getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; addOperands ( MIB , MOs ) ; unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . add ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI .


<s> unsigned int cnt ; vec_uchar16 mask ; x . v = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; cnt = x . i [ <NUM_LIT>


<s> if ( GV -> isConstant ( ) && GV -> hasDefinitiveInitializer ( ) ) { Constant * Init = GV -> getInitializer ( ) ; Type * Ty = Init -> getType ( ) ; if ( ! isa < ConstantDataArray > ( Init ) || ! Ty -> getArrayElementType ( ) -> isIntegerTy ( ) || Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) != VT . getSizeInBits ( ) || Ty -> getArrayNumElements ( ) > Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) ) continue ; uint64_t ArrayElementCount = Init -> getType ( ) -> getArrayNumElements ( ) ; bool ConstantsMatch = true ; for ( uint64_t j = <NUM_LIT> ; j < ArrayElementCount ; j ++ ) { auto * Elem = cast < ConstantInt > ( Init -> getAggregateElement ( j ) ) ; if ( Elem -> getZExtValue ( ) != ( ( ( uint64_t ) <NUM_LIT> << j ) - <NUM_LIT> ) ) { ConstantsMatch = false ; break ; } } if ( ! ConstantsMatch ) continue ; SDValue Inp = ( i == <NUM_LIT> ) ? Node -> getOperand ( <NUM_LIT> )


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetWindows ( ) || Subtarget -> isTargetMingw ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetMingw ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol


<s> } else { if ( ! TRI -> isPhysicalRegister ( defReg ) ) temp_set . erase ( defReg ) ; else for ( MCRegAliasIterator alias ( defReg , TRI , true ) ; alias . isValid ( ) ; ++ alias ) temp_set . erase ( * alias ) ; } } } if ( MI -> isCall ( ) && ! ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) ) { unsigned clear_set [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( int i = <NUM_LIT> ; i < sizeof ( clear_set ) / sizeof ( clear_set [ <NUM_LIT> ] ) ; i ++ ) { for ( MCRegAliasIterator alias ( clear_set [ i ] , TRI , true ) ; alias . isValid ( ) ; ++ alias ) temp_set . insert ( * alias ) ; } } if ( OMI == MI . getInstrIterator ( ) . getNodePtrUnchecked ( ) ) { if ( temp_set . find ( OReg ) == temp_set . end ( ) ) { return_taint = <NUM_LIT> ; } else { return_taint = <NUM_LIT> ; } } } return temp_set


<s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) return ExtractBitFromMaskVector ( Op , DAG ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { return SDValue ( ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) ,


<s> if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasFP64 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Opc ; case <STR_LIT> : return <STR_LIT>


<s> for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = <NUM_LIT> ; return Estimate


<s> vqtbx4q_s8 ( int8x16_t r , int8x16x4_t tab , uint8x16_t idx ) { __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT>


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } Base =


<s> return ( __m128i ) __builtin_ia32_prold128_mask ( ( __v4si ) __A , __B , (


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter


<s> } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) { DOUT ( llvm :: dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i


<s> if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { NumStores ++ ; Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( ( MemAccessTy -> isIntegerTy ( ) || MemAccessTy -> isFloatingPointTy ( ) ) && ( getDataLayout ( ) . getTypeSizeInBits ( MemAccessTy ) == <NUM_LIT> ) ) NumStores ++ ; } } unsigned const Max = ( NumStores ? ( <NUM_LIT> / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = <NUM_LIT> ; return ; } UP . MaxCount =


<s> return ( __m256 ) __builtin_ia32_sqrtps256 ( ( __v8sf )


__C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> Register DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; int64_t SrcImm = IsMoveImm ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! MRI -> isReserved ( DefReg ) && ( ( IsCopy && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) || IsMoveImm ) ) { for ( RegImm & KnownReg : KnownRegs ) { if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI .


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2


<s> else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains


<s> else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> getZExtValue ( ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { const DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const TargetInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( MBB , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const Value * Op1 = I . getOperand ( <NUM_LIT> ) ; const Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value )


<s> } ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT> ) ; if ( TLI . isOperationLegalOrPromote ( Opcode , VT ) && ( Op0 == Op1 || IsFreeTruncation ( Op0 ) || IsFreeTruncation ( Op1 ) ) ) return TruncateArithmetic ( Op0 , Op1 ) ; break ; } case <STR_LIT> : if ( SrcVT . getScalarType ( ) == <STR_LIT> && TLI . isOperationLegal ( Opcode , VT ) && ! TLI . isOperationLegal ( Opcode , SrcVT ) ) return TruncateArithmetic ( Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT>


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind )


<s> qword q ; long long l [ <NUM_LIT> ] ; } x ; x . q = q ; return ( x . l [ <NUM_LIT> ]


<s> EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else


<s> case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) return <NUM_LIT> ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < <NUM_LIT> && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = <NUM_LIT> ; } if ( l ) return


<s> else FS = <STR_LIT> ; if ( TheTriple . getOS ( ) == Triple :: NativeClient ) FS += <STR_LIT> ; else FS += <STR_LIT> ; return FS


<s> intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) StubAddr ) ; int Hi = ( ( unsigned ) NewVal & <NUM_LIT> ) >> <NUM_LIT> ; if ( ( NewVal & <NUM_LIT> ) != <NUM_LIT> ) Hi ++ ; int Lo = ( int ) (


<s> else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++


<s> vabdl_high_s16 ( int16x8_t a , int16x8_t b ) { int32x4_t result


<s> MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent (


<s> unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > <NUM_LIT> ) return TyAlign ; return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , true


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA )


<s> static bool getVShiftImm ( SDValue Op , unsigned ElementBits , int64_t & Cnt ) { while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElementBits ) || SplatBitSize > ElementBits ) return false ; Cnt = SplatBits . getSExtValue ( ) ; return true


<s> unsigned char <ISA_LIT>Subtarget :: ClassifyBlockAddressReference ( ) const { if ( isPICStyleGOT ( ) ) return


<s> if ( DAG . isConstantIntBuildVectorOrConstantInt ( LHS ) && ! DAG . isConstantIntBuildVectorOrConstantInt ( RHS ) ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , RHS , LHS ) ; if ( <STR_LIT> ( RHS . getNode ( ) ) ) return RHS ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; APInt DemandedMask ( APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; KnownBits


<s> MachineInstr & MI = * MBBI ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( DstReg == <STR_LIT> || DstReg == <STR_LIT> ) { MI . eraseFromParent ( ) ; return true ; } SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT> > Insn ; <ISA_LIT>_IMM :: expandMOVImm ( Imm , BitSize , Insn ) ; assert ( Insn . size ( ) != <NUM_LIT> ) ; SmallVector < MachineInstrBuilder , <NUM_LIT> > MIBS ; for ( auto I = Insn . begin ( ) , E = Insn . end ( ) ; I != E ; ++ I ) { bool LastItem = std :: next ( I ) == E ; switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addReg ( DstReg ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ; } break ; } } transferImpOps ( MI , MIBS . front ( ) , MIBS . back ( ) ) ; MI . eraseFromParent ( ) ; return true


<s> const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI ->

hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ;


<s> unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal , dl ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src


<s> rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> ,


<s> unsigned getT2SOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned SoImm = MI . getOperand ( Op ) . getImm ( ) ; unsigned Encoded = <STR_LIT> ( SoImm


<s> bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG


<s> Pos = CN -> getZExtValue ( ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; Opc = <STR_LIT> ; NewOperand = FirstOperand . getOperand ( <NUM_LIT> ) ; } else if ( FirstOperandOpc == <STR_LIT> && Subtarget . hasCn<ISA_LIT> ( ) ) { if ( ! ( CN = dyn_cast < ConstantSDNode > ( FirstOperand . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; Pos = CN -> getZExtValue ( ) ; if ( SMPos != Pos || Pos >= ValTy . getSizeInBits ( ) || SMSize >= <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; NewOperand = FirstOperand . getOperand ( <NUM_LIT> ) ; SMSize -- ; Opc = <STR_LIT>


__B [ <NUM_LIT> ] , const void * __P ) {


<s> FOR_EACH_BB_FN ( bb , cfun ) { rtx dest , src ; rtx pat , op0 , set = NULL ; rtx_insn * prev , * insn = BB_END ( bb ) ; bool insn_clobbered = false ; while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; pat = PATTERN ( insn ) ; op0 = XEXP ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered ) continue ; if ( ! set ) continue ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( ! low_register_operand ( dest , SImode ) || ! low_register_operand ( src , SImode ) ) continue ; if ( REGNO ( op0 ) == REGNO ( src ) || REGNO ( op0 ) == REGNO ( dest ) ) { dest = copy_rtx ( dest ) ; src = copy_rtx ( src ) ; src = gen_rtx_MINUS ( SImode , src , const0_rtx ) ; PATTERN ( prev ) = gen_rtx_SET ( VOIDmode , dest ,


<s> if ( <ISA_LIT>16SPAliasReg ) return <ISA_LIT>16SPAliasReg ; const TargetRegisterClass * RC


<s> Op = N . getOperand ( <NUM_LIT> ) ; return ! WasTruncated ; } auto * GA = cast < GlobalAddressSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; Optional < ConstantRange > CR = GA -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR || CR -> getUnsignedMax ( ) . uge ( <NUM_LIT> << VT . getSizeInBits ( ) ) ) return false ; Op = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( N ) , VT , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; return true


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * <NUM_LIT>


<s> LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; } } return false


<s> assert ( N == <NUM_LIT> && isMemoryIndexed32 ( ) && <STR_LIT> ) ; addMemoryIndexedOperands ( Inst ,


<s> return ( __m128 ) __builtin_ia32_cvtsi642ss ( (


<s> if ( IsO32 ( ) ) return CC != CallingConv :: Fast ? <NUM_LIT> : <NUM_LIT> ; if ( IsN32 ( ) || IsN64 ( ) )


<s> return CurDAG -> getTargetConstant ( Imm , dl , <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool IsPrologue ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset (


<s> } strong = ( model == MEMMODEL_ACQ_REL || model == MEMMODEL_SEQ_CST ) ; if ( val & IX86_HLE_ACQUIRE && ! ( model == MEMMODEL_ACQUIRE || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST | IX86_HLE_ACQUIRE ; } if ( val & IX86_HLE_RELEASE && ! ( model == MEMMODEL_RELEASE || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST |


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC


<s> for ( unsigned int pi = <NUM_LIT> ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) if ( group . types [ <NUM_LIT> ] [ <NUM_LIT> ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( mode32 != MODE_none && mode64 != MODE_none ) ; build_one ( b , signature , group , mode32 , <NUM_LIT> , pi , force_direct_overloads ) ; build_one ( b , signature , group , mode64 , <NUM_LIT> , pi , force_direct_overloads ) ; } else for ( unsigned int ti = <NUM_LIT> ; group . types [ ti ] [ <NUM_LIT> ] != NUM_TYPE_SUFFIXES ; ++ ti ) { unsigned int bits = type_suffixes [ group . types [ ti ]


<s> case 'G' : case 'L' : case 'M' : return C_Immediate ; case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'Y' : switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } else if ( parseConstraintCode ( Constraint )


<s> return ( uint16x8_t ) __builtin_neon_vcltzv8hf (


<s> unsigned getStackEntry ( unsigned STi ) const { assert ( STi < StackTop


<s> SupportsDebugInformation = false ; Data16bitsDirective = <NUM_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective = <NUM_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; PrivateGlobalPrefix =


<s> SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExtElt ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( ExtElt . getNode ( ) ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , V , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) , St -> getAAInfo ( ) ) ; } if ( <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo

( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ;


<s> assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> return ( m_SectionData -> size ( ) > <ISA_LIT>GOTPLT0Num


<s> return ( __m512 ) __builtin_ia32_cvtdq2ps512_mask ( ( __v16si ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16


<s> std :: make_unique < PostGenericScheduler > ( C ) , true ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createPowerPCMacroFusionDAGMutation ( ) ) ; return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return


<s> static bool sparc_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mfpu


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdseed64_step ( unsigned long long * p ) { return __builtin_ia32_rdseed_di_step ( p )


<s> if ( matchADDRri ( Addr , Base , Offset ) ) return true ; Base = Addr


<s> d -> perm . rotate_inputs ( <NUM_LIT> ) ; std :: swap ( d -> op0 , d -> op1 ) ; } if ( ( d -> vec_flags == VEC_ADVSIMD || d -> vec_flags == VEC_SVE_DATA || d -> vec_flags == VEC_SVE_PRED ) && known_gt ( nelt , <NUM_LIT> ) ) { if ( aarch64_evpc_rev_local ( d ) ) return true ; else if ( aarch64_evpc_rev_global (


<s> if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTPLT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTTPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_DTPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_TPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PLT || XINT ( x , <NUM_LIT> ) == UNSPEC_PCREL || XINT ( x , <NUM_LIT> ) == UNSPEC_SYMOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PCREL_SYMOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTFUNCDESC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFFFUNCDESC ) ) return false ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >=


<s> if ( MFI . adjustsStack ( ) && TFL . hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) .

addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( NumBytes ) ;


<s> if ( L -> getMemoryVT ( ) . getStoreSizeInBits ( ) <= C . Op0 . getValueType ( ) . getSizeInBits ( ) ) { unsigned Type = L -> getExtensionType ( ) ; if ( ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) || ( Type == <STR_LIT>


<s> if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign ,


<s> case EQ : case NE : return CCZmode ; case GEU : case LTU : if ( GET_CODE ( op0 ) == PLUS && ( rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) || rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCCmode ; else return CCmode ; case GTU : case LEU : return CCmode ; case GE : case LT : if ( op1 == const0_rtx ) return CCGOCmode ; else return CCGCmode ; case GT


<s> const unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned Imm12 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned TypeT3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned S = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( sign1 != sign2 ) return MCDisassembler :: Fail ; DecodeStatus DS = MCDisassembler :: Success ; if ( ( ! Check ( DS , DecodeGPRspRegisterClass ( Inst , Rd , Address , Decoder ) ) ) || ( ! Check ( DS , DecodeGPRspRegisterClass ( Inst , Rn , Address , Decoder ) ) ) ) return MCDisassembler :: Fail ; if ( TypeT3 ) { Inst . setOpcode ( sign1 ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm12 ) ) ; } else { Inst . setOpcode ( sign1 ? <STR_LIT> : <STR_LIT>


<s> std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; assert ( Prefix == <STR_LIT> ) ; RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) + Reg )


<s> for ( auto & PredMBB : MBB -> predecessors ( ) ) for ( auto & TermI : PredMBB -> terminators ( ) ) if ( TermI . isIndirectBranch ( ) ) return true ; return


<s> addPass ( create<ISA_LIT>FiMalkrzPass (


<s> case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; default : llvm_unreachable (


<s> case CmpInst :: FCMP_TRUE : { ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( <NUM_LIT> ) ; break ; } } if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; } const Value * LHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * RHS = CI -> getOperand ( <NUM_LIT> ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * RHSC = dyn_cast < ConstantFP > ( RHS ) ; if ( RHSC && RHSC -> isNullValue ( ) ) RHS = LHS ; } static const uint16_t SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) .


<s> if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCSymbolRefExpr * SymbolRefExpr = dyn_cast < MCSymbolRefExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr

-> getKind ( ) == MCSymbolRefExpr :: VK_None ;


<s> Value * <ISA_LIT>IREmitter :: visitSELECT ( const SDNode


<s> if ( ! MI . isPHI ( ) ) break ; for ( int OpIdx = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; OpIdx < NumOps ; OpIdx += <NUM_LIT> ) if ( ! Preds . insert ( MI . getOperand ( OpIdx + <NUM_LIT> ) . getMBB ( ) ) . second ) DupIndices . push_back ( OpIdx ) ; while ( ! DupIndices . empty (


<s> } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) { unsigned Idx = RMask [ i ] ; if ( Idx < N ) RMask [ i ] += N ; else if ( Idx < <NUM_LIT> * N ) RMask [ i ] -= N ; } for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) { unsigned LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx >= <NUM_LIT> * N || RIdx >= <NUM_LIT> * N || ( ! A . getNode ( ) && ( LIdx < N || RIdx < N ) ) || ( ! B . getNode ( ) && ( LIdx >= N || RIdx >= N ) ) ) continue ; if ( ! ( LIdx == <NUM_LIT> * i && RIdx == <NUM_LIT> * i + <NUM_LIT> ) && ! ( isCommutative && LIdx == <NUM_LIT> * i + <NUM_LIT> && RIdx == <NUM_LIT> * i ) ) return false ; } LHS = A . getNode ( ) ? A : B ; RHS = B . getNode ( ) ?


<s> return ( uint64x2_t ) __builtin_neon_vqshluv2di ( ( int64x2_t )


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( )


<s> return FI <= OutArgFIRange . first && FI >=


<s> bool <ISA_LIT>_MC :: is16BitMemOperand ( const MCInst & MI , unsigned Op , const MCSubtargetInfo & STI ) { const MCOperand & Base = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & Index = MI . getOperand ( Op + <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && Base . isReg ( ) && Base . getReg ( ) == <NUM_LIT> && Index . isReg ( ) && Index . getReg ( ) == <NUM_LIT> ) return true ; return isMemOperand ( MI , Op


<s> MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get (

CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ;


<s> case 'b' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'q' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , P . getSubtarget ( ) . is64Bit ( ) ?


<s> SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC ) return SDValue ( ) ; APInt Comparison = CmpRHSC -> getAPIntValue ( ) ; if ( Comparison == - Addend ) { auto * AN = cast < AtomicSDNode > ( CmpLHS . getNode ( ) ) ; auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpLHS . getValueType ( ) , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - Addend , SDLoc ( CmpRHS ) , CmpRHS . getValueType ( ) ) , AN -> getMemOperand ( ) ) ; auto LockOp = lowerAtomicArithWithLOCK ( AtomicSub , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , DAG . getUNDEF ( CmpLHS . getValueType ( ) ) ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , LockOp . getValue ( <NUM_LIT> ) ) ; return LockOp ; } if ( ! Comparison . isNullValue ( ) ) return SDValue ( ) ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT>


<s> void addRegVSRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( VSRegs [ getVSReg ( )


<s> case <STR_LIT> : case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : return false ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGE21 ) ; return true ; } return true ; case <STR_LIT> : case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; RelocType = unsigned ( MachO :: ARM64_RELOC_BRANCH26 ) ; return true


<s> if ( RepeatedSequenceLocs . empty ( ) ) return outliner :: OutlinedFunction ( ) ; unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerTailCall , <NUM_LIT> ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerThunk , <NUM_LIT> ) ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ ] ( outliner :: Candidate & C ) { return C . LRU . available ( <STR_LIT> ) ; } ) ) { FrameID = MachineOutlinerNoLRSave ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; } else { FrameID = MachineOutlinerDefault ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; } if ( std :: any_of ( RepeatedSequenceLocs [ <NUM_LIT> ] . front ( ) , RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) , [ ]

( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumBytesToCreateFrame += <NUM_LIT> ;


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord P = pReloc . place ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; uint16_t upper_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) ; uint16_t lower_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) ; Relocator :: DWord val = ( ( upper_inst ) << <NUM_LIT> ) | ( lower_inst ) ; Relocator :: DWord A = helper_extract_thumb_movw_movt_addend ( val ) + pReloc . addend


<s> static void mep_move_ready_insn ( rtx_insn * * ready , int nready , rtx_insn * insn ) { int i ; for ( i = <NUM_LIT> ; i < nready ; ++ i ) if ( ready [ i ] == insn ) { for ( ; i < nready - <NUM_LIT> ; ++ i )


<s> bool noBTIAtReturnTwice ( ) const { return


<s> <ISA_LIT>XCOFFMCAsmInfo :: <ISA_LIT>XCOFFMCAsmInfo ( bool Is64Bit , const Triple & T ) { if ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ) report_fatal_error ( <STR_LIT> ) ; CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; Data64bitsDirective = Is64Bit ?


<s> if ( IS_CMSE_ENTRY ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , ( HOST_WIDE_INT ) crtl -> args . size , crtl -> args . pretend_args_size , ( HOST_WIDE_INT ) get_frame_size ( ) ) ; asm_fprintf ( f , <STR_LIT> , frame_pointer_needed , cfun -> machine -> uses_anonymous_args ) ; if ( cfun -> machine -> lr_save_eliminated ) asm_fprintf ( f , <STR_LIT> ) ; if ( crtl -> calls_eh_return ) asm_fprintf (


<s> else if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ; else if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ; llvm_unreachable (


<s> void emitLocalEntry ( MCSymbolELF * S , const MCExpr * LocalOffset ) override { llvm_unreachable ( <STR_LIT> )


<s> return __builtin_ia32_vcvttph2qq128_mask ( __A , _mm_setzero_si128 ( )


<s> getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( ! SC -> EndGroup ) return <NUM_LIT> ; else return


<s> if ( ! isIntS34Immediate ( N . getOperand ( <NUM_LIT> ) , Imm ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSKnown . Zero . getZExtValue ( ) | ~ ( uint64_t ) Imm ) != ~ <NUM_LIT> ) return false ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( Imm , dl , N . getValueType ( ) ) ; return true ; } if ( isIntS34Immediate ( N , Imm ) ) { Disp = DAG . getTargetConstant ( Imm , dl


<s> GotEntryMapType :: iterator it = m_GotLocalEntriesMap . find ( key ) ; if ( it == m_GotLocalEntriesMap . end ( ) ) return NULL ; return it ->