<s> SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } LLVM_DEBUG ( { MachineBasicBlock :: iterator PrevI = PrevMI ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) ) ; while ( ++ Start != std :: next ( I


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; assert ( VT == <STR_LIT> &&


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned


<s> StringRef getToken ( ) const { assert ( isToken ( ) && <STR_LIT>


<s> while ( insn && GET_CODE ( insn ) == NOTE ) insn = PREV_INSN ( insn ) ; if ( insn && ( ( GET_CODE ( insn ) == CALL_INSN && get_attr_type ( insn ) != TYPE_DYNCALL ) || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( g . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRrAllowed ) ; } PBQP :: Matrix costs ( g . getEdgeCosts ( edge ) ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; PBQP :: PBQPNum sameParityMax = std :: numeric_limits < PBQP :: PBQPNum > :: min ( ) ; for ( unsigned j = <NUM_LIT> , je = vRrAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRrAllowed ) [ j ] ; if ( ! haveSameParity ( pRd , pRa ) ) if ( costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] != std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) && costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] > sameParityMax ) sameParityMax = costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ; } for ( unsigned j = <NUM_LIT> , je = vRrAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRrAllowed ) [ j ] ; if ( haveSameParity ( pRd , pRa ) ) if ( sameParityMax > costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ) costs [ i + <NUM_LIT> ] [ j

+ <NUM_LIT> ] = sameParityMax + <NUM_LIT> ;


<s> if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( V2 . isUndef ( ) && ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { SDValue VPermMask = getConstVector ( Mask , <STR_LIT> , DAG , DL , true ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [


<s> for ( unsigned i = <NUM_LIT> ; i < Op . getNumOperands ( ) ; i ++ ) if ( ! <STR_LIT> ( Op . getOperand ( i )


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this , PM , Subtarget . is64Bit (


<s> static SDValue lowerUINT_TO_FP_vXi32 ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( Op ) ; SDValue V = Op -> getOperand ( <NUM_LIT> ) ; EVT VecIntVT = V . getValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; EVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getValueType ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned NumElts = VecIntVT . getVectorNumElements ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; SDValue CstLow = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue CstLowArray [ ] = { CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow } ; SDValue VecCstLow = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstLowArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstHigh = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue CstHighArray [ ] = { CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh } ; SDValue VecCstHigh = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstHighArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstShift = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue CstShiftArray [ ] = { CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift } ; SDValue VecCstShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstShiftArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { EVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { SDValue CstMask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue VecCstMask = DAG . getNode ( <STR_LIT> , DL , VecIntVT , CstMask , CstMask , CstMask , CstMask ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL


<s> if ( TARGET_ALTIVEC && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( computed != <NUM_LIT> ) { static bool


<s> if ( ! loongarch_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; loongarch_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == <NUM_LIT> ) { rtx inv_target ; inv_target = loongarch_force_binary ( GET_MODE ( target ) , inv_code , cmp0


<s> DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF .


<s> return ( float32x4_t ) __builtin_neon_vcvtsv4si (


<s> case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: UIToFP : return <ISA_LIT>SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; Register Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == <STR_LIT> || DstVT .

getVectorElementType ( ) == <STR_LIT> ) return false ;


<s> <ISA_LIT>MCAsmInfoGNUCOFF :: <ISA_LIT>MCAsmInfoGNUCOFF ( const Triple & Triple ) { assert ( Triple . isOSWindows ( ) && <STR_LIT> ) ; if ( Triple . getArch ( ) == Triple


<s> TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; Register RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; Register RD2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD2 ) . addReg ( <STR_LIT> )


<s> printSOImm ( O , V1 , isVerbose ( ) , MAI ) ; O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printSOImm ( O , V2 , isVerbose ( ) ,


<s> static DecodeStatus DecodeCASI32 ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeCAS ( MI , insn , Address ,

Decoder , false , false , DecodeI32RegisterClass ) ;


<s> const DigitalSubtarget * getSubtargetImpl ( ) const { return &


<s> return TargetIRAnalysis ( [ this ] ( Function


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList


<s> __builtin_ia32_movntdq ( ( __v2di * ) __A , ( __v2di )


<s> if ( ! RegNum ) { if ( auto RegNum = StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ) return Kind == RegKind :: Scalar ? RegNum : <NUM_LIT> ; auto Entry = RegisterReqs . find ( Name . lower ( ) ) ; if ( Entry == RegisterReqs . end ( ) ) return <NUM_LIT> ; if ( Kind == Entry -> getValue ( ) . first ) RegNum = Entry -> getValue ( ) . second ; } return


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8


<s> TII . loadRegFromStack ( MBB , I , VR0 , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , Desc , Lo ) . addReg ( VR0 , RegState :: Kill ) ; TII . loadRegFromStack ( MBB , I , VR1 , FI , RC , & RegInfo , RegSize ) ; BuildMI ( MBB , I , DL , Desc , Hi ) . addReg (


<s> return ( __m128i ) __builtin_ia32_pmovsxdq128_mask ( ( __v4si ) __X ,


<s> const TargetInstrInfo * TII = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; if ( Subtarget -> isTargetCygMing ( ) ) { unsigned CallOp = Subtarget -> is64Bit ( ) ? <STR_LIT>


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( needsStackRealignment ( MF ) && MFI ->


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add


<s> JUMP_LABEL ( jump ) = bp -> far_label ; ok = invert_jump ( insn , label , <NUM_LIT> ) ; gcc_assert ( ok ) ; if ( bp -> far_label ) ( emit_insn_after ( gen_stuff_delay_slot ( GEN_INT ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( jump ) ) , <NUM_LIT> ) ) ) , GEN_INT ( recog_memoized ( insn ) == CODE_FOR_branch_false )


<s> { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; } case TLS_MODEL_LOCAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , <NUM_LIT> , <NUM_LIT> , OPTAB_DIRECT ) ; break ; } case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL


<s> std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp


<s> return emit_insn ( gen_rtx_SET ( x , y


<s> } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits


<s> for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear (


<s> return ( pst_info . num_zr ( ) <= NUM_FP_ARG_REGS && pst_info . num_pr ( ) <= NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( return_type ) ) ; return false ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info ::


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( SDValue Lane : Op -> ops ( ) ) { if ( auto * CstLane = dyn_cast < ConstantSDNode > ( Lane ) ) { APInt LowBits ( EltTy . getSizeInBits ( ) , CstLane -> getZExtValue ( ) ) ; Lane = DAG . getConstant ( LowBits . getZExtValue (


<s> int WsIdx = <NUM_LIT> ; int WtIdx = ResTy . getVectorNumElements ( ) + <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Indices . size ( ) ; i += <NUM_LIT> ) { if ( Indices [ i ] != - <NUM_LIT> && Indices [ i ] != WsIdx ) return SDValue ( ) ; if ( Indices [ i + <NUM_LIT> ] != - <NUM_LIT> && Indices [ i + <NUM_LIT> ] != WtIdx ) return SDValue ( ) ; WsIdx += <NUM_LIT> ; WtIdx += <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ResTy , Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand (


<s> if ( fs -> curr . reg [ UNW_REG_PSP ] . where == UNW_WHERE_NONE ) context -> psp = context -> psp + fs -> curr . reg [ UNW_REG_PSP ] . val ; else uw_update_reg_address ( context , fs , UNW_REG_PSP ) ; } { int i ; if ( fs -> when_target < fs -> curr . reg [ UNW_REG_PRI_UNAT_GR ] . when ) i = UNW_REG_PRI_UNAT_MEM ; else if ( fs -> when_target < fs -> curr . reg [ UNW_REG_PRI_UNAT_MEM ] . when ) i = UNW_REG_PRI_UNAT_GR ; else if ( fs -> curr . reg [ UNW_REG_PRI_UNAT_MEM ] . when > fs -> curr . reg [ UNW_REG_PRI_UNAT_GR ] . when ) i = UNW_REG_PRI_UNAT_MEM ; else i = UNW_REG_PRI_UNAT_GR ; uw_update_reg_address ( context , fs , i ) ; } for ( i = UNW_REG_BSP ; i < UNW_NUM_REGS ; ++ i ) uw_update_reg_address ( context , fs , i ) ; if ( ! ( fs -> no_reg_stack_frame ) ) { unsigned long pfs = * context -> pfs_loc ; unsigned long sol = ( pfs >> <NUM_LIT> ) & <NUM_LIT> ; context -> bsp = ( unsigned long ) ia64_rse_skip_regs ( (

unsigned long * ) context -> bsp , - sol ) ;


<s> unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( TD . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { MachineOperand & op = MI . getOperand ( <NUM_LIT> ) ; if ( op . isMBB ( ) ) { MachineBasicBlock * dst = op . getMBB ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addMBB ( dst ) ; } else


<s> error ( <STR_LIT> , rs6000_builtin_info [ ( size_t ) fcode ] . bifname ) ; return const0_rtx ; } if ( fcode == RS6000_BIF_CPU_IS ) { const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . bifname ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx address = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ; rtx tcbmem = gen_const_mem ( SImode , address ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BIF_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask = NULL_RTX ; int


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin


<s> unsigned getMatrixReg ( ) const { assert ( Kind == k_MatrixRegister && <STR_LIT>


<s> if ( CondCodes ) { unsigned TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg1 , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC = getCompareCC ( Predicate ) ; assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; <STR_LIT> invertedCC = getInvertedCondCode ( CC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) )

. addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( invertedCC ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl


<s> static __inline void * _mm_malloc ( size_t size , size_t alignment ) { void * ptr ; if ( alignment == <NUM_LIT> ) return malloc ( size ) ; if ( alignment == <NUM_LIT> || ( sizeof ( void * ) == <NUM_LIT> && alignment == <NUM_LIT> ) ) alignment = sizeof ( void * ) ; if ( posix_memalign ( & ptr , alignment , size ) == <NUM_LIT> ) return ptr ; else return


<s> rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) ) ; } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P ( insn ) =


<s> static poly_int64 aarch64_vl_bytes ( machine_mode mode , unsigned int vec_flags ) { if ( vec_flags & VEC_PARTIAL ) return GET_MODE_SIZE ( mode ) ; if ( vec_flags & VEC_SVE_DATA ) return BYTES_PER_SVE_VECTOR ; gcc_assert ( vec_flags & VEC_SVE_PRED ) ; return BYTES_PER_SVE_PRED


fntype ATTRIBUTE_UNUSED , int for_return ) {


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm (

<NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


<s> if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , <NUM_LIT> ) ; rtx op2 = XEXP ( src , <NUM_LIT> ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , <NUM_LIT> ) ; op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != <NUM_LIT> || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != <NUM_LIT> || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ; if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1


<s> return ( ( ( insn ) & <NUM_LIT> ) ==


<s> } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return


<s> return ( vector unsigned char ) __builtin_altivec_vsububs ( ( vector signed char ) a1 , ( vector signed


<s> case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; } return MI . isAsCheapAsAMove (


<s> rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , <NUM_LIT> ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp


<s> static __inline qword si_sf ( qword a , qword b ) { return ( ( qword ) ( vec_sub ( ( vec_uint4 ) ( b ) ,


<s> else if ( write_symbols == DBX_DEBUG ) return ; else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ; fprintf ( stream , <STR_LIT> , num_source_filenames ) ; output_quoted_string ( stream , name ) ; putc ( '\n' ,


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg


<s> if ( SelectRegShifterOperand ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT>


<s> CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; if ( isABI_N32 ( ) || isABI_N64 ( ) ) { if ( <NUM_LIT> <= CC && CC <=


<s> tree clipper_build_va_list ( ) { tree record , ap , reg , num ; record = make_node ( RECORD_TYPE ) ; num = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( num ) = record ; reg = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , build_array_type ( ptr_type_node , build_index_type ( build_int_2 ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; DECL_FIELD_CONTEXT ( reg ) = record ; TREE_CHAIN ( reg


<s> if ( ! VT . isVector ( ) || Op0 . getOpcode ( ) != <STR_LIT> || DAG . ComputeNumSignBits ( Op0 . getOperand ( <NUM_LIT> ) ) != NumEltBits || VT . getSizeInBits ( ) != Op0 . getValueSizeInBits ( ) ) return SDValue ( ) ; if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst ; if ( IsStrict ) SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , SDValue ( BV , <NUM_LIT> ) } ) ; else SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> } auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( isa < CondCodeSDNode > ( V ) || V . getValueType ( ) . isScalableVector ( ) ) && <STR_LIT> ) ; Operands . push_back


<s> uint64_t Add1Imm ; if ( isIntImmediate ( Add1 , Add1Imm ) && ( Add1Imm % Size == <NUM_LIT> ) ) NewShiftAmt = Add0 ; else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isIntImmediate ( Add0 , Add0Imm ) && Add0Imm != <NUM_LIT> && ( Add0Imm % Size == <NUM_LIT> ) ) { unsigned NegOpc ; unsigned ZeroReg ; EVT SubVT = ShiftAmt -> getValueType ( <NUM_LIT> ) ; if ( SubVT == <STR_LIT> ) { NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( SubVT == <STR_LIT> ) ; NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , ZeroReg , SubVT ) ; MachineSDNode * Neg = CurDAG -> getMachineNode ( NegOpc , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = SDValue ( Neg , <NUM_LIT> ) ; } else return false ; } else { uint64_t MaskImm ; if ( ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) && ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) ) return false ; if ( countTrailingOnes ( MaskImm ) < Bits ) return false ; NewShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) NewShiftAmt = narrowIfNeeded ( CurDAG , NewShiftAmt ) ; else if ( VT == <STR_LIT> && NewShiftAmt -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; MachineSDNode * Ext = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewShiftAmt , SubReg ) ; NewShiftAmt = SDValue (


<s> if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldVectorLoad ( V2 ) ) CanFoldLoad = false ; if ( CanFoldLoad ) { if ( HasSSE2 && NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; if ( NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; } ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( HasSSE2 && NumElems == <NUM_LIT> ) || ! <STR_LIT> ( SVOp ) ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; else if ( HasSSE2 ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; return getTargetShuffleNode ( <STR_LIT> , dl , VT , V2


<s> VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo (


<s> <STR_LIT> Cond = <STR_LIT> ( SetCCI ) ; unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; if ( ! SetCCI . mayStore ( ) ) { assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MRI -> replaceRegWith ( SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI . memoperands (


<s> <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( AsmOp ) ; if ( Op -> isImm ( ) && Op

-> getImm ( ) == ImmVal ) return Match_Success ;


<s> switch ( N . getOpcode ( ) ) { case <STR_LIT> : IsDUPLANE = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsDUPLANE = true ; break ; default : return SDValue ( ) ; } MVT NarrowTy = N . getSimpleValueType ( ) ; if ( ! NarrowTy . is64BitVector ( ) ) return SDValue ( ) ; MVT ElementTy = NarrowTy . getVectorElementType (


<s> return DecodeVecShiftRImm ( Inst , Imm


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , PtrVT , Result ) ; if ( Offset


<s> TargetJITInfo :: StubLayout <ISA_LIT>JITInfo :: getStubLayout (


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: Create (


<s> return thumb1_base_register_rtx_p ( x , QImode


<s> } } else if ( JUMP_P ( from ) && ! TARGET_SH2 && ! optimize_size ) new_align = <NUM_LIT> ; if ( JUMP_P ( from ) && get_attr_type ( from ) == TYPE_CBRANCH && ! sequence_insn_p ( from ) ) inc += <NUM_LIT> ; if ( found_si ) { count_si += inc ; if ( new_align > si_align ) { si_limit -= ( count_si - <NUM_LIT> ) & ( new_align - si_align ) ; si_align = new_align ; } count_si = ( count_si + new_align - <NUM_LIT> ) & - new_align ; } if ( found_hi ) { count_hi += inc ; if ( new_align > hi_align ) { hi_limit -= ( count_hi - <NUM_LIT> ) & ( new_align - hi_align ) ; hi_align = new_align ; } count_hi = ( count_hi + new_align - <NUM_LIT> ) & - new_align ; } from = NEXT_INSN ( from ) ; } if ( num_mova ) { if ( leading_mova ) { fixup_mova ( mova ) ; return find_barrier ( <NUM_LIT> , <NUM_LIT> , mova ) ; } else { from = mova ; good_barrier = found_barrier = barrier_before_mova ; } } if ( found_barrier ) { if ( good_barrier && next_real_insn ( found_barrier ) ) found_barrier = good_barrier ; } else { rtx_code_label * label = gen_label_rtx ( ) ; if ( last_symoff ) from = last_symoff ; if ( PREV_INSN ( from ) != orig && ( count_hi > hi_limit || count_si > si_limit ) ) from = PREV_INSN ( PREV_INSN ( from ) ) ; else from = PREV_INSN ( from ) ; if ( last_got && last_got != orig ) from = PREV_INSN ( last_got ) ; if ( flag_exceptions && CALL_P ( from ) && find_reg_note ( from , REG_EH_REGION , NULL_RTX ) ) from = PREV_INSN ( from ) ; while ( NOTE_P ( from ) || JUMP_P ( from ) || LABEL_P ( from ) ) from = PREV_INSN ( from ) ; if ( CALL_P ( from ) ) { bool sibcall_p = SIBLING_CALL_P ( from ) ; if ( sibcall_p ) return emit_barrier_after ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , from ) ; JUMP_LABEL ( from ) = label ; LABEL_NUSES ( label ) = <NUM_LIT> ; found_barrier = emit_barrier_after ( from ) ; emit_label_after ( label


<s> unsigned Opc = MI -> getOpcode ( ) ; return isNarrowStore ( Opc ) || Opc


<s> unsigned Basereg = is64BitMode ( ) ? <STR_LIT> : ( Parse32 ? <STR_LIT> : <STR_LIT> ) ; const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext (


<s> uint64_t TrueWeight = <NUM_LIT> , FalseWeight = <NUM_LIT> ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( <NUM_LIT> ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . is<ISA_LIT>64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType


<s> case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( TARGET_AVX ) break ; if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE


<s> return MEM_P ( x ) && ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || ! misaligned_operand ( x , TImode )


<s> tree decl = SYMBOL_REF_DECL ( symbol ) ; if ( decl && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) return false ; return default_use_anchors_for_symbol_p ( symbol


<s> SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDValue Lo = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc (


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering (


<s> bool <ISA_LIT>FastISel :: SelectLoad ( const Instruction * I ) { if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT>


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && can_use_mov_pic_label_ref ( operands [ <NUM_LIT> ] ) ) { if ( mode == SImode ) { emit_insn ( gen_movsi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( mode == DImode ) { gcc_assert ( TARGET_ARCH64 ) ; emit_insn ( gen_movdi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } } if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = sparc_legitimize_pic_address ( operands [ <NUM_LIT> ] , reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && ( const_zero_operand ( operands [ <NUM_LIT> ] , mode ) || const_all_ones_operand ( operands [ <NUM_LIT> ] , mode ) ) ) return false ; if ( REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG && ( mode == SFmode || ( mode == DFmode && ! can_create_pseudo_p ( ) ) ) ) return false ; operands [ <NUM_LIT> ] = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ; if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = validize_mem ( operands [ <NUM_LIT> ] ) ; return false ; } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; switch ( mode ) { case QImode : break ; case HImode : case SImode : sparc_emit_set_const32 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ;


<s> MachineOperand & Op1 = Def -> getOperand ( <NUM_LIT> ) ; if ( ! Op1 . isCImm ( ) || Op1 . getCImm ( ) -> getBitWidth ( ) > <NUM_LIT> ) return None ; Immed = Op1 . getCImm ( ) -> getZExtValue ( ) ; } else return None ; unsigned ShiftAmt ; if ( Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; } else if ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; Immed = Immed >> <NUM_LIT> ; } else return None ; unsigned ShVal = <STR_LIT> ( <STR_LIT> ,


<s> void <ISA_LIT>RegisterInfo :: adjustStackMapLiveOutMask ( uint32_t * Mask ) const { assert ( ! ( Mask [ <STR_LIT> / <NUM_LIT> ] & ( <NUM_LIT> << ( <STR_LIT> %


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg (


<s> return <NUM_LIT> ; } if ( in ) return MAX ( ix86_cost -> mmx_load [ index ] , ix86_cost -> mmx_store [ index ] ) ; return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : if ( Q_CLASS_P ( regclass ) || TARGET_64BIT ) { if ( ! in ) return ix86_cost -> int_store [ <NUM_LIT> ] ; if ( TARGET_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p ( cfun ) ) cost = ix86_cost -> movzbl_load ; else cost = ix86_cost -> int_load [ <NUM_LIT> ] ; if ( in == <NUM_LIT> ) return MAX ( cost , ix86_cost -> int_store [ <NUM_LIT> ] ) ; return cost ; } else { if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> movzbl_load , ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ) ; if ( in ) return ix86_cost -> movzbl_load ; else return ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ; } break ; case <NUM_LIT> : if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> int_load [ <NUM_LIT> ] , ix86_cost ->


<s> expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op


<s> if ( ! isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , And_mask ) ) return false ; Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; unsigned BitWide = <NUM_LIT> - CountLeadingOnes_64 ( ~ ( And_mask >> Srl_imm ) ) ; if ( BitWide && isMask_64 ( And_mask >> Srl_imm ) ) { if ( N -> getValueType ( <NUM_LIT>


<s> return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> ) { O <<


<s> if ( ! can_create_pseudo_p ( ) ) return false ; set_of_reg t_before_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , prev_nonnote_nondebug_insn_bb ) ; set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_nondebug_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! modified_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p ( PATTERN (

t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) {


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false


<s> case FP_LO_REGS : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_VREG - <NUM_LIT> ) / UNITS_PER_VREG ; default : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT>


<s> if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ; return CheckCPSRDef ? ! definesCPSR ( MI


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) Binary |= encodeVFPRn ( MI , OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( ) || MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { emitWordLE ( Binary )


<s> water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP , CloserWater ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const Align Alignment = isThumb ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( NewMBB -> getAlignment ( ) < Alignment ) NewMBB -> setAlignment ( Alignment ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark =


<s> unsigned FrameDestroyOpcode = TII -> getCallFrameDestroyOpcode ( ) ; for ( MachineBasicBlock & BB : MF ) { bool InsideFrameSequence = false ; for ( MachineInstr & MI : BB ) { if ( MI . getOpcode ( ) == FrameSetupOpcode ) { if ( InsideFrameSequence ) return false ; InsideFrameSequence = true ; } else if ( MI . getOpcode ( ) ==


<s> case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return TT . isOSDarwin ( ) || ReserveX18 ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin


<s> const char * p = getenv ( <STR_LIT> ) ; val = p && strlen ( p ) ; } return ! val


<s> unsigned QuotientReg ; unsigned DividentRegUpper ; unsigned DividentRegLower ; unsigned OpSignExtend ; unsigned OpCopy ; unsigned OpDiv ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } } ; if ( RegRB . getID ( ) != <STR_LIT> ) return false ; auto SDivEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ RegTy ] ( const SDivEntry & El ) { return El . SizeInBits == RegTy . getSizeInBits ( ) ; } ) ; if ( SDivEntryIt == std :: end ( OpTable ) ) return false ; const TargetRegisterClass * RegRC = getRegClass ( RegTy , RegRB ) ; if ( ! RBI . constrainGenericRegister ( DividentReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DiviserReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * RegRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpCopy ) , SDivEntryIt -> DividentRegLower ) . addReg ( DividentReg ) ; if ( SDivEntryIt -> DividentRegUpper != <STR_LIT> ) BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpSignExtend ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpDiv ) ) . addReg ( DiviserReg ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY

) , DstReg ) . addReg ( SDivEntryIt -> QuotientReg ) ;


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetNoMsa (


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [


<s> return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { auto * NewMaskTy = FixedVectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy ,


<s> std :: unique_ptr < const <ISA_LIT>CallEntry > & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = llvm :: make_unique < <ISA_LIT>CallEntry > ( Val ) ; return MachinePointerInfo ( E . get


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ; if ( Opc == <STR_LIT> ) AddDefaultPred ( MIB


<s> void <ISA_LIT>CodeEmitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset (


<s> Inst . addOperand ( MCOperand :: createImm ( JumpOffset ) ) ; return MCDisassembler


<s> bool <ISA_LIT>TTIImpl :: areTypesABICompatible ( const Function * Caller , const Function * Callee , const ArrayRef < Type * > & Types ) const { if ( ! BaseT :: areTypesABICompatible ( Caller , Callee


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lc2200 > X ( The<ISA_LIT>Target ,


<s> break ; case <STR_LIT> : Changed |= shortenFusedFPOp ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenFusedFPOp ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn001AddCC ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn001AddCC ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; default : { int TwoOperandOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( TwoOperandOpcode == - <NUM_LIT> ) break ; if ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ( ! MI . isCommutable ( ) || MI . getOperand (

<NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) || ! TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) ) break ;


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT>

, Is32BitImm , false , IDLoc , Instructions ) ) return true ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>TDCPass ( ) ) ; addPass ( createLoopDataPrefetchPass (


<s> bool <ISA_LIT>DAGToDAGISel :: isWorthFolding ( SDValue V


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( getTheThumbLETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( getTheThumbBETarget


<s> gcc_assert ( ptr -> arch < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> arch , processor_names [ ptr -> arch ] ) ; gcc_assert ( ptr -> tune < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> tune , processor_names [ ptr -> tune ] ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> branch_cost ) ; if ( target_string )


<s> bool isFPImm ( ) const { return Kind


<s> InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector


<s> ggc_add_rtx_root ( & mips_load_reg , <NUM_LIT> ) ; ggc_add_rtx_root ( & mips_load_reg2 , <NUM_LIT> ) ; ggc_add_rtx_root ( & mips_load_reg3 , <NUM_LIT> ) ; ggc_add_rtx_root ( & mips_load_reg4 , <NUM_LIT> ) ; ggc_add_rtx_root ( branch_cmp , sizeof ( branch_cmp ) / sizeof ( rtx ) ) ; ggc_add_rtx_root ( & embedded_pic_fnaddr_rtx ,


<s> return ( CallCC == CallingConv :: Fast && TailCallOpt ) || CallCC ==

CallingConv :: Tail || CallCC == CallingConv :: SwiftTail ;


<s> bool <ISA_LIT>CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TFL = STI -> getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , * BB , I , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( auto CC : CallSeqVector ) if ( CC . UsePush ) Changed |= adjustCallSequence ( MF , CC ) ; return


<s> static SDValue performDivRemCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; unsigned LO = <STR_LIT> ; unsigned HI = <STR_LIT> ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue DivRem = DAG . getNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO , Ty ,


<s> else FullFS = <STR_LIT> ; } if ( OL >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OL != CodeGenOpt :: None ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( TT . isOSAIX ( ) ) { if ( ! FullFS . empty ( ) ) FullFS


<s> if ( MaskTySize != <NUM_LIT> && MaskTySize != <NUM_LIT> ) return ; if ( ! MaskTy -> isVectorTy ( ) ) return ; Type * VecEltTy = MaskTy -> getVectorElementType ( ) ; if ( ! VecEltTy -> isIntegerTy ( ) ) return ; unsigned EltTySize = VecEltTy -> getIntegerBitWidth ( ) ; if ( EltTySize < <NUM_LIT> || EltTySize > ElSize ) return ; unsigned NumElements = MaskTySize / ElSize ; assert ( ( NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleMask . reserve ( NumElements ) ; unsigned NumElementsPerLane = <NUM_LIT> / ElSize ; unsigned Factor = ElSize / EltTySize ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { Constant * COp = C -> getAggregateElement ( i * Factor ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue > ( COp ) ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Selector = cast < ConstantInt > ( COp ) -> getZExtValue ( ) ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; if ( ( M2Z & <NUM_LIT> ) != <NUM_LIT> && MatchBit != ( M2Z & <NUM_LIT>


<s> if ( Subtarget . isCortexA8 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else { DefCycle = RegNo + <NUM_LIT> ; } return DefCycle


<s> break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , dl , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N ,


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Type = ELF :: R_<ISA_LIT>64_ADDR16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO : Type = ELF :: R_<ISA_LIT>_GOT16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI : Type = ELF :: R_<ISA_LIT>_GOT16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HA : Type = ELF :: R_<ISA_LIT>_GOT16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC : Type = ELF :: R_<ISA_LIT>64_TOC16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO : Type = ELF :: R_<ISA_LIT>64_TOC16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_HI : Type = ELF :: R_<ISA_LIT>64_TOC16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; case MCSymbolRefExpr :: VK_TPREL : Type = ELF :: R_<ISA_LIT>_TPREL16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : Type = ELF :: R_<ISA_LIT>_TPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGH : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGH ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHER : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHERA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHEST : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHESTA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_DTPREL : Type = ELF :: R_<ISA_LIT>64_DTPREL16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGH : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGH ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHER : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHERA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHEST : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHESTA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSGD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSLD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO


<s> if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; uint16_t upper_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) ; uint16_t lower_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) ; Relocator :: DWord val = ( ( upper_inst ) << <NUM_LIT> ) | ( lower_inst ) ; Relocator :: DWord A = helper_extract_thumb_movw_movt_addend ( val ) +


<s> Value * <ISA_LIT>IREmitter :: visitVCGTZ ( const SDNode *


<s> return __builtin_sh_media_LDLO_Q ( ( char * ) p + s


<s> else VA . convertToReg ( <STR_LIT> ) ; } } } if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) ( MMO ) ; return


<s> bool function_resolver :: scalar_argument_p ( unsigned int i ) { tree type = get_argument_type ( i ) ; return ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P


<s> if ( ! use_vfp_abi ( pcum -> pcs_variant , false ) ) return false ; return aapcs_vfp_is_call_or_return_candidate ( pcum -> pcs_variant , mode , type , & pcum -> aapcs_vfp_rmode


<s> case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Call : if ( dyn_cast < IntrinsicInst > ( I ) ) return false ; return SelectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I


<s> OutStreamer . EmitLabel ( JTISymbol ) ; const char * JTEntryDirective = MAI -> getData32bitsDirective ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool UseSet = MAI -> hasSetDirective ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JTSets ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; bool isNew = JTSets . insert ( MBB ) ; if ( UseSet && isNew


<s> BitVector CallerSavedRegs ( TRI . getNumRegs ( ) , true ) ; CallerSavedRegs . reset ( <STR_LIT> ) ; CallerSavedRegs . reset ( <STR_LIT> ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( ) ; * R ; ++ R ) for ( MCRegAliasIterator AI ( * R , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) CallerSavedRegs . reset ( * AI ) ; Defs |=


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) .

addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> SDValue getAddrGPRel ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN64 ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue GPRel = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( IsN64 ? <STR_LIT> : <STR_LIT> , Ty ) , DAG . getNode ( <STR_LIT> ,

DL , DAG . getVTList ( Ty ) , GPRel ) ) ;


<s> bool sh_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return ( !


<s> MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI ->


<s> case AsmToken :: Dot : break ; } const MCExpr * DestValue ; if ( getParser ( ) . parseExpression ( DestValue ) ) return MatchOperand_NoMatch ; bool IsPic = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; <ISA_LIT>MCExpr :: VariantKind Kind = IsPic ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 : <ISA_LIT>MCExpr :: VK_Sparc_WDI<ISA_LIT>30 ; const MCExpr * DestExpr = <ISA_LIT>MCExpr :: create ( Kind , DestValue , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( DestExpr , S ,


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; narrowShuffleMaskElts ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) )


<s> return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ; const auto getExternalFunctionEntryPointSymbol = [ & ] ( StringRef SymName ) { auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( ( Twine ( <STR_LIT> ) + Twine ( SymName ) ) . str ( ) , SectionKind :: getMetadata ( ) , XCOFF :: CsectProperties ( XCOFF :: XMC_PR , XCOFF :: XTY_ER ) ) ; return Sec -> getQualNameSymbol ( ) ; } ; SymName = getExternalFunctionEntryPointSymbol ( SymName ) -> getName ( ) . data ( ) ; } return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> :


<s> break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; while ( <NUM_LIT> ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRI5Operand ( const MCInst * MI , unsigned Op , raw_ostream & O , unsigned Scale ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO3 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( MO3 . getReg ( ) ) ; else if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs * Scale ; O <<


<s> MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt : { llvm_unreachable ( <STR_LIT> ) ; break ; } } unsigned ArgReg ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { ArgReg = NextFPR ++ ; if ( CC != CallingConv :: Fast ) ++ NextGPR ; } else ArgReg = NextGPR ++ ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .

get ( TargetOpcode :: COPY ) , ArgReg ) . addReg ( Arg ) ;


<s> virtual const <ISA_LIT>RegisterInfo &


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT , DAG . getRegister ( is64Bit ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Base , NULL , <NUM_LIT> ) ; unsigned char OperandFlags = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT>


<s> if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , <NUM_LIT> ) , VOIDmode , ZERO_EXTRACT , <NUM_LIT> , speed ) ; else * cost += rtx_cost ( inner , VOIDmode , cmpcode , <NUM_LIT> , speed ) ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == COMPARE ) { if ( XEXP ( op1 , <NUM_LIT> ) == const0_rtx ) * cost += <NUM_LIT> ; if ( speed ) { machine_mode mode = GET_MODE ( XEXP ( op1 , <NUM_LIT> ) ) ; const struct cpu_cost_table * extra_cost = aarch64_tune_params . insn_extra_cost ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) * cost += extra_cost -> alu . arith ; else * cost += extra_cost -> fp [ mode == DFmode ] . compare ; } return true ; } if ( GET_CODE ( op1 ) == NEG || GET_CODE ( op1 ) == NOT || ( GET_CODE ( op1 ) == PLUS && XEXP ( op1 , <NUM_LIT> ) == const1_rtx ) ) op1 = XEXP ( op1 , <NUM_LIT> ) ; else if ( GET_CODE ( op1 ) == ZERO_EXTEND && GET_CODE ( op2 ) == ZERO_EXTEND ) { op1 = XEXP ( op1 , <NUM_LIT> ) ; op2 = XEXP ( op2 , <NUM_LIT> ) ; } * cost += rtx_cost ( op1 , VOIDmode , IF_THEN_ELSE , <NUM_LIT> , speed ) ; * cost += rtx_cost ( op2 , VOIDmode , IF_THEN_ELSE , <NUM_LIT> , speed ) ; return true ; } return


<s> if ( ( Index == <NUM_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || Op0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( Index ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Index , DL , <STR_LIT> ) ) ; } GeneralShuffle GS ( VT ) ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { int Elt = VSN ->


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; if ( BitSize > <NUM_LIT> ) return TTI :: TCC_Free ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < <NUM_LIT> > ( Imm . getSExtValue (


<s> static __inline vec_double2 spu_rlmaskqw ( vec_double2 a , int count ) { return ( ( vec_double2 ) ( si_rotqmbi ( ( qword ) ( a


<s> BlockISELList & CurrentISELList = BlockList . second ; auto I = CurrentISELList . begin ( ) ; auto E = CurrentISELList . end ( ) ; while ( I != E ) { assert ( isISEL ( * * I ) && <STR_LIT> ) ; MachineOperand & Dest = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; if ( useSameRegister ( Dest , TrueValue ) && useSameRegister ( Dest , FalseValue ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumRemoved ++ ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( useSameRegister ( TrueValue , FalseValue ) ) { MachineBasicBlock * MBB = ( * I ) -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * I ) , dl , TII -> get ( isISEL8 ( * * I ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( FalseValue ) ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( ExpandISELEnabled ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; BlockISELList SubISELList ; SubISELList . push_back ( * I ++ ) ; while ( I != E && canMerge ( SubISELList . back ( ) , * I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; SubISELList . push_back ( * I ++ ) ; } expandMergeableISELs ( SubISELList ) ; } else { I ++


<s> } if ( op1 == <NUM_LIT> && slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { DEBUG ( showBitVector ( errs ( ) , insn ) ) ; setSlice ( insn , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return decodeInstruction ( insn ) ; } if ( op1 == <NUM_LIT> && slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) ==

<NUM_LIT> ) return T2Morph2LoadLiteral ( decodeThumbInstruction ( insn ) ) ;


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) || TheTriple . isWindowsCoreCLREnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ?


<s> return ( __m128i ) __builtin_ia32_pmaxsw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> int64_t Size ; if ( parseImmExpr ( Size ) ) return


<s> bool NotCC = ( Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback && Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback_SSE ) ; bool NotCC = Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback ; if ( NotCC ) { JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) ; return JCE . finishGVStub ( F ) ; } JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) ; JCE . emitByte


<s> unsigned Imm = <STR_LIT> ( ET , getShiftExtendAmount ( ) ) ; Inst . addOperand ( MCOperand ::


<s> assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget -> is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( RestoreMBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB ) ; auto RestoreMBBI = RestoreMBB -> begin


<s> InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; if ( ! getLexer ( ) . is ( AsmToken :: LBrac ) ) return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ; Parser . Lex ( ) ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } const MCExpr * Disp = MCConstantExpr :: Create ( SM . getImm ( ) , getContext


<s> return ( __m256i ) __builtin_ia32_pavgw256 ( ( __v16hi


<s> unsigned Opc = U -> getOpcode ( ) ; if ( Opc == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) . getNode ( ) == N ) return false ; if ( Opc == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) . getNode ( ) == N ) return false ; if ( isTargetShuffle ( Opc ) ) return


<s> if ( TT . isOSDarwin ( ) ) return Reloc :: PIC_ ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple


<s> while ( Size > <NUM_LIT> ) { if ( ( Size - MOV128SZ >= <NUM_LIT> ) && isYMMLoadOpcode ( LoadInst -> getOpcode ( ) ) ) { Size = Size - MOV128SZ ; buildCopy ( LoadInst , getYMMtoXMMLoadOpcode ( LoadInst -> getOpcode ( ) ) , LdDisp , StoreInst , getYMMtoXMMStoreOpcode ( StoreInst -> getOpcode ( ) ) , StDisp , MOV128SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV128SZ ; StDisp += MOV128SZ ; LMMOffset += MOV128SZ ; SMMOffset += MOV128SZ ; continue ; } if ( Size - MOV64SZ >= <NUM_LIT> ) { Size = Size - MOV64SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV64SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV64SZ ; StDisp += MOV64SZ ; LMMOffset += MOV64SZ ; SMMOffset += MOV64SZ ; continue ; } if ( Size - MOV32SZ >= <NUM_LIT> ) { Size = Size - MOV32SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV32SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV32SZ ; StDisp += MOV32SZ ; LMMOffset += MOV32SZ ; SMMOffset += MOV32SZ ; continue ; } if ( Size - MOV16SZ >=


<s> else return Changed ; if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & MBBN ) { ++ NumDelJmp ; MBB . erase ( I ) ; Changed = true ; } return


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Enable<ISA_LIT>TailCalls && ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall (


<s> if ( T -> isIntegerTy ( ) && T -> getScalarSizeInBits ( ) == <NUM_LIT> ) return true ; return false


<s> gcc_assert ( MEM_P ( mem_rtx ) ) ; rtx addr_rtx = XEXP ( mem_rtx , <NUM_LIT> ) ; if ( REG_P ( addr_rtx ) ) return true ; if ( GET_CODE ( addr_rtx ) == PLUS && GET_CODE ( XEXP (

addr_rtx , <NUM_LIT> ) ) == CONST_INT ) return true ;


<s> const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB (


<s> create_input_operand ( & ops [ <NUM_LIT> ] , src , mode ) ; temporary_volatile_ok v ( true ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , <NUM_LIT> ,


<s> static const uint16_t ReservedCPURegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getTarget ( ) . getFrameLowering ( )


<s> Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , OutContext ) ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOT ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateDTPREL_G1 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateDTPREL_G0_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTTPREL ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTTPRELLo12 ( Expr ,


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorElementCount ( ) . getKnownMinValue ( ) >= <NUM_LIT> ) return true ; return false


<s> if ( RegMask > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( RegMask )


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> static const unsigned short permute_selectors [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __m64_union t ; __vector unsigned long long a , p , r ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_10 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_32 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_54 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_76