<s> if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { unsigned NumBytes = getFixupKindInfo ( Fixup . getKind ( ) ) . TargetSize / <NUM_LIT> ; Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <=


<s> uint64_t getPC16DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > &

Fixups , const MCSubtargetInfo & STI ) const {


<s> void <ISA_LIT>InsertPrefetch :: getAnalysisUsage (


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned NumElems = VecVT . getVectorNumElements ( ) ; MVT WideVecVT = VecVT ; if ( ( ! Subtarget . hasDQI ( ) && NumElems == <NUM_LIT> ) || NumElems < <NUM_LIT> ) { WideVecVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , DAG . getUNDEF ( WideVecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Vec , DAG .

getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ;


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; if ( MO . isDef ( ) && TRI -> isSuperRegisterEq ( OrigDestReg , MO . getReg ( ) ) ) IsDefined = true ; if ( MO . isUse ( ) && ! TRI -> isSubRegisterEq ( OrigDestReg , MO . getReg ( ) ) && TRI -> regsOverlap ( SuperDestReg , MO . getReg ( ) ) ) return false ; } if ( ! IsDefined )


<s> MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << PrintReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRight32Imm ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op


<s> } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO ) ; } MIB . addReg ( DstReg , RegState :: ImplicitDefine | getDeadRegState ( DstIsDead ) ) ; TransferImpOps ( MI , MIB ,


<s> EVT NewVT = getExtensionTo64Bits ( OrigTy ) ; return DAG . getNode ( ExtOpcode , SDLoc ( N ) ,


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) Binary


<s> while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff , false , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff +


<s> if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( Register :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsVFReg = ( MI . getNumOperands ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! ConvertibleImmForm && ! instrHasImmForm ( Opc , IsVFReg , III , true ) ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { Register Reg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * DefMI = getDefMIPostRA ( Reg , MI , SeenIntermediateUse ) ; if ( DefMI ) { switch ( DefMI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpNoForForwarding = i ; return DefMI ; } } } } } return OpNoForForwarding == ~ <NUM_LIT> ? nullptr


<s> Mnode * mp ; minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset


<s> EndBB -> splice ( EndBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB


<s> void <ISA_LIT>SETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee


<s> EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getScalarSizeInBits ( ) ; unsigned FromSz = LdVT . getScalarSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask


<s> if ( ISD == <STR_LIT> && Index == ( ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return Cost ; } else if ( Val -> getScalarType ( ) -> isIntegerTy ( ) && Index != - <NUM_LIT> ) { if ( ST -> hasP9Altivec ( ) ) { if ( ISD == <STR_LIT> ) return vectorCostAdjustment ( <NUM_LIT> , Opcode , Val , nullptr ) ; unsigned EltSize = Val -> getScalarSizeInBits ( ) ; if ( EltSize == <NUM_LIT> ) { unsigned MfvsrdIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrdIndex ) return <NUM_LIT> ; } else if ( EltSize == <NUM_LIT> ) { unsigned MfvsrwzIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrwzIndex ) return <NUM_LIT> ; } return vectorCostAdjustment ( <NUM_LIT> , Opcode , Val , nullptr ) ; } else if ( ST -> hasDirectMove ( ) ) return


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; unsigned char GVFlags = <ISA_LIT>SubTarget


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg


<s> gcc_assert ( ! altivec_indexed_or_indirect_operand ( dest , mode ) ) ; gcc_assert ( ! altivec_indexed_or_indirect_operand ( source , mode ) ) ; if ( FLOAT128_VECTOR_P ( mode ) ) { dest = gen_lowpart ( V1TImode , dest ) ; source = gen_lowpart ( V1TImode , source ) ; mode =


<s> return new <ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std ::


<s> void i386_pe_asm_lto_end ( void ) { debug_info_level = saved_debug_info_level


<s> static const char * getRegisterName ( unsigned RegNo ) { return <ISA_LIT>InstPrinter :: getRegisterName (


<s> void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( <NUM_LIT> ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; } virtual const char * getPassName ( ) const { return <STR_LIT> ; } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ; virtual void EmitFunctionBodyEnd (


<s> Value * <ISA_LIT>IREmitter :: visitSUB ( const SDNode * N


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) : ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> )


<s> if ( align > BIGGEST_ALIGNMENT && VAR_OR_FUNCTION_DECL_P ( decl ) ) { resolve_unique_section ( decl , reloc , true ) ; if ( IN_NAMED_SECTION ( decl ) ) return get_named_section ( decl , NULL , reloc ) ; } if ( decl_readonly_section ( decl , reloc ) ) { if ( TREE_PUBLIC ( decl ) ) return read_only_data_section ; else return read_only_private_data_section ; } else { if ( TREE_CODE ( decl ) == VAR_DECL && DECL_THREAD_LOCAL_P ( decl ) ) { if ( bss_initializer_p ( decl


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x16_t ) __builtin_aarch64_qtbl4v16qi ( __o , ( int8x16_t )


<s> if ( RegNo != <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg


<s> return CreateReg ( Index , RegKind_GPR , RegInfo ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , StoreAddrReg , StoreAddr ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( StoreAddrReg ,


<s> for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = nullptr ; if ( I -> getOpcode ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! Dest ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT>


<s> Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getTargetData ( ) -> getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = true ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset =


<s> int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } ( void ) MIB ; if ( IsPreIdx ) { ++ NumPreFolded ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { ++ NumPostFolded ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Update -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( )


<s> initialize<ISA_LIT>PreEmitPeepholePass ( * PassRegistry :: getPassRegistry


<s> for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll (


<s> int <ISA_LIT>FrameLowering :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( )


<s> DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2


<s> u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ] = c ; u . i [ <NUM_LIT> ]


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> bool Found = SelectAddrModeIndexed ( N , Size , Base , OffImm ) ; if ( Found ) { if ( auto * CI = dyn_cast < ConstantSDNode > ( OffImm ) ) { int64_t C = CI -> getSExtValue ( ) ; if ( C <= Max ) return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc


<s> HOST_WIDE_INT hi = i ^ lo ; rtx subtarget = op0 ; if ( ! cse_not_expected && can_create_pseudo_p ( ) ) subtarget = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( subtarget , GEN_INT ( hi ) ) ) ; emit_insn ( gen_iorsi3 ( op0 , subtarget , GEN_INT ( lo ) ) ) ; return ; } break ; case CONST : case SYMBOL_REF : case LABEL_REF : op1 = or1k_legitimize_address_1 ( op1


<s> MBB -> insert ( MI , Ear1MI ) ; Ear1MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear1MI ) . addReg ( <STR_LIT> ) ; MachineInstr * SllgMI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , SllgMI ) ; SllgMI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , SllgMI ) . addReg ( Reg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Ear2MI = MF


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF , false ) ) . addSym ( Sym , <STR_LIT> ) ; return DestReg


<s> MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , ScratchFPReg , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode (


<s> } for ( const auto & Extension : Extensions ) { if ( Extension . Name != Name ) continue ; if ( ! Extension . Features ) report_fatal_error ( <STR_LIT> + Name ) ; if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) { Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; return false ; } uint64_t ToggleFeatures = EnableFeature ? ( ~ STI . getFeatureBits ( ) & Extension . Features ) : ( STI . getFeatureBits ( )


<s> return ( GET_CODE ( x ) != REG || REGNO ( x


<s> Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned Count = <NUM_LIT> ; unsigned FirstReg = Reg ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { FirstReg = Reg = getDRegFromQReg ( Reg ) ; ++ Reg ; ++ Count ; } if ( parseVectorLane ( LaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg > EndReg ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } VectorLaneTy NextLaneKind ; if ( parseVectorLane ( NextLaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getLoc ( ) ; Count += EndReg - Reg ; Reg = EndReg ; continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { Reg = getDRegFromQReg ( Reg ) ; if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind


<s> static SDValue LowerLabelRef ( SDValue HiPart , SDValue LoPart , bool isPIC , SelectionDAG & DAG ) { EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc DL = HiPart . getDebugLoc ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiPart , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ; if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG .

getNode ( <STR_LIT> , DL , PtrVT ) , Hi ) ;


<s> bool isCheapToSpeculateCtlz ( ) const


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize )


<s> } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> )


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl


<s> virtual bool ShouldShrinkFPConstant ( MVT VT ) const { return ! <ISA_LIT>ScalarSSEf64 || VT ==


<s> const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = TM . getRegisterInfo ( ) -> getSubReg ( SrcReg , SubIdx ) ; BuildMI ( MBB , I , dl , Mfc1Tdd , DstReg ) . addReg


<s> const TargetRegisterClass * RC2 = FP64 ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . storeRegToStack ( MBB , I , HiReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI ,


<s> emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue (


<s> auto IsZeroInit = [ ] ( MachineInstr * Def ) { return ! isVectorPredicated ( Def ) && Def -> getOpcode ( ) == <STR_LIT> && Def -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } ; bool AllowScalars = isHorizontalReduction ( MI ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( ! isRegInClass ( MO , QPRs ) && AllowScalars ) continue ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Defs ; RDA . getGlobalReachingDefs ( & MI , MO . getReg ( ) , Defs ) ; for ( auto * Def : Defs ) { if ( Def == & MI || FalseLanesZero . count ( Def ) || IsZeroInit ( Def ) ) continue ; if ( MO . isUse ( ) && isPredicated ) continue ; return false ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return true


<s> bool ix86_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class regclass ) { if ( from == to ) return false ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return true ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P


<s> uint64_t SextImm = SignExtend64 ( Imm , MinSize ) ; SDValue SDImm = CurDAG -> getTargetConstant ( SextImm , dl , <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( SextImm ) ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> auto Addrs = FirstGather -> getOperand ( <NUM_LIT> ) ; auto FirstAddr = Builder . CreateExtractElement ( Addrs , Builder . getInt32 ( <NUM_LIT> ) ) ; auto PtrType = VecTy -> getPointerTo ( ) ; auto Ptr = Builder . CreateBitCast ( FirstAddr , PtrType ) ; CallInst * LdN , * LdN2 ; if ( ! IsNativeStride ) { Value * Pred = FirstGather -> getOperand ( <NUM_LIT> ) ; Value * ZipPredLo , * ZipPredHi ; std :: tie ( ZipPredLo , ZipPredHi ) = getZip ( Pred , Pred , Builder ) ; Value * Ops [ ] = { ZipPredLo , Ptr } ; LdN = Builder . CreateCall ( LdNFunc , Ops , <STR_LIT> ) ; auto Ptr2 = Builder . CreateGEP ( Ptr , Builder . getInt64 ( Factor / <NUM_LIT> ) ) ; Value * Ops2 [ ] = { ZipPredHi , Ptr2 } ; LdN2 = Builder . CreateCall ( LdNFunc , Ops2 , <STR_LIT> ) ; } else { Value * Ops [ ] = { FirstGather -> getOperand ( <NUM_LIT> ) , Ptr } ; LdN = Builder . CreateCall ( LdNFunc , Ops , <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < Gathers . size ( ) ; i ++ ) { if ( ! IsNativeStride && i >= Factor / <NUM_LIT> ) break ; auto Gather1 = Gathers [ i ] ; auto Gather2 = IsNativeStride ? nullptr : Gathers [ Factor / <NUM_LIT> + i ] ; auto ActiveGather = Gather1 ? Gather1 : Gather2 ; if ( ! ActiveGather ) continue ; auto II = cast < IntrinsicInst > ( ActiveGather ) ; assert ( ( II -> getOperand ( <NUM_LIT> ) == FirstGather -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; Value * SubVec = Builder . CreateExtractValue ( LdN , i ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , II -> getType ( ) ) ; if ( IsNativeStride ) ActiveGather -> replaceAllUsesWith ( SubVec ) ; else { auto SubVec2 = Builder . CreateExtractValue ( LdN2 , i ) ; if ( EltTy -> isPointerTy ( ) ) SubVec2 = Builder . CreateIntToPtr ( SubVec2 , II -> getType ( ) ) ; Value * Even , * Odd ; std :: tie ( Even , Odd ) = getUnzip ( SubVec , SubVec2 , Builder ) ; if ( Gather1 ) Gather1 -> replaceAllUsesWith ( Even ) ; if ( Gather2 ) Gather2 -> replaceAllUsesWith ( Odd ) ; } } return


<s> int i ; extract_insn_cached ( use_insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { rtx addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ; return modified_in_p ( addr , set_insn ) != <NUM_LIT> ; } return false


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl


<s> return ( __m256i ) __builtin_ia32_vgf2p8mulb_v32qi_mask ( ( __v32qi ) __C , (


<s> } else if ( CONST_INT_P ( * op ) ) { rtx vec_cst ; rtx tmp = gen_rtx_SUBREG ( vmode , gen_reg_rtx ( smode ) , <NUM_LIT> ) ; if ( constm1_operand ( * op , GET_MODE ( * op ) ) ) vec_cst = CONSTM1_RTX ( vmode ) ; else { unsigned n = GET_MODE_NUNITS ( vmode ) ; rtx * v = XALLOCAVEC ( rtx , n ) ; v [ <NUM_LIT> ] = * op ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) v [ i ] = const0_rtx ; vec_cst = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( n , v ) ) ; } if ( ! standard_sse_constant_p ( vec_cst , vmode ) ) { start_sequence ( ) ; vec_cst = validize_mem ( force_const_mem (


<s> static void do_restore ( rtx ( * move_fn ) ( rtx , rtx , rtx ) , rtx reg , HOST_WIDE_INT cfa_off ) { int iter = spill_fill_data . next_iter ; rtx_insn * insn ; insn = emit_insn ( ( * move_fn ) ( reg , spill_restore_mem ( reg , cfa_off ) , GEN_INT (


<s> return false ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return


<s> Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( Offset ) { assert ( Offset > <NUM_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , * Ctx ) , * Ctx ) ; } if ( TargetKind != <ISA_LIT>MCExpr :: CEK_None ) Expr = <ISA_LIT>MCExpr :: create ( TargetKind , Expr , * Ctx ) ; return MCOperand :: createExpr ( Expr


<s> rtx_insn * sh_peephole_emit_move_insn ( rtx dst , rtx src ) { return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc


<s> BBI . Size += TII -> GetInstSizeInBytes ( I ) ; if ( I -> isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) == <STR_LIT> ) { BBI . PostAlign


<s> } if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride )


<s> return & InstrInfo . getRegisterInfo (


<s> return ( __m128 ) __builtin_ia32_mulps ( ( __v4sf ) __A , (


<s> void emitConstant ( uint64_t Val , unsigned Size , unsigned & CurByte , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { emitByte ( Val & <NUM_LIT> ,


<s> static bool invertFPCondCode ( <STR_LIT> CC ) { if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return false ; assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ; return true


<s> unsigned firstRegToSaveIndex , lastRegToSaveIndex ; unsigned RBegin , REnd ; if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; firstRegToSaveIndex = RBegin - <STR_LIT> ; lastRegToSaveIndex = REnd - <STR_LIT> ; } else { firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , array_lengthof ( GPRArgRegs ) ) ; lastRegToSaveIndex = <NUM_LIT> ; } unsigned ArgRegsSize , ArgRegsSaveSize ; computeRegArea ( CCInfo , MF , InRegsParamRecordIdx , ArgSize , ArgRegsSize , ArgRegsSaveSize ) ; if ( ArgRegsSaveSize ) { unsigned Padding = ArgRegsSaveSize - ArgRegsSize ; if ( Padding ) { assert ( AFI -> getStoredByValParamsPadding ( ) == <NUM_LIT> && <STR_LIT> ) ; AFI -> setStoredByValParamsPadding ( Padding ) ; } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back (


<s> if ( ! MBB . isLiveIn ( <STR_LIT> ) ) return true ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ! TRI -> needsStackRealignment ( MF ) && ! <ISA_LIT>FI -> hasSwiftAsyncContext


<s> SDLoc DL ( & St ) ; SDValue BasePtr = St . getBasePtr ( ) ; uint64_t BaseOffset = <NUM_LIT> ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; if ( BasePtr -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) ) { BaseOffset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; BasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; } unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( BaseOffset + Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( )


<s> void <ISA_LIT>AIXAsmPrinter :: ValidateGV ( const GlobalVariable * GV ) { if ( GV -> isThreadLocal ( ) ) report_fatal_error (


<s> uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ; uint32_t lsb_mask = ( <NUM_LIT> << lsb ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( ~ ( msb_mask ^ lsb_mask ) ) ) ; return S


<s> return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getElementCount ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; MMO . setType ( NewTy ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ; }


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirective<ISA_LIT> ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return

parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ;


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle , Options ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI ::


<s> const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ||


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest


<s> return expandLoadImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadImm ( Inst , false , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc ,


<s> for ( auto & I : MBB ) { if ( IsLoopStart ( I ) ) Starts . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Decs . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Ends . push_back ( & I ) ; } if ( Starts . empty ( ) && Decs . empty ( ) && Ends . empty ( ) ) continue ; Changed =


<s> UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; const TargetRegisterClass * RC ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT>


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++

i ) MBB . insert ( MI , NewMIs [ i ] ) ;


<s> bool NoFloat = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth (


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) ->


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> use_fast_prologue_epilogue_nregs = - <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass (


<s> SDValue ExtLoad = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , N0 . getValueType ( ) , LN0 -> getMemOperand ( ) ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( N0 . getNode ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , ExtLoad , DAG .

getIntPtrConstant ( <NUM_LIT> , SDLoc ( N0 ) ) ) , ExtLoad . getValue ( <NUM_LIT> ) ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT> <<


<s> } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM , createTLOF ( Triple ( TM . getTargetTriple ( ) ) ) ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2


<s> } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count ?


<s> inline void _Unwind_SetIP ( struct _Unwind_Context * context , _Unwind_Ptr


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> cpp_assert ( parse_in , <STR_LIT> ) ; } else { cpp_assert ( parse_in , <STR_LIT> ) ; cpp_assert ( parse_in , <STR_LIT> ) ; } if ( TARGET_VIS4 ) { cpp_define ( parse_in , <STR_LIT> ) ; cpp_define ( parse_in , <STR_LIT> ) ; } else if (


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( getThe<ISA_LIT>Target (


<s> unsigned tgt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; tgt <<= <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( tgt + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: CreateImm


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return IsINC ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsINC ? <STR_LIT> : <STR_LIT>


<s> case TargetOpcode :: G_ADD : case TargetOpcode :: G_OR : { assert ( ( OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> || OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return applyDefaultMapping ( OpdMapper )


<s> const auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsWin64 = Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; unsigned FixedObject = IsWin64 ? alignTo ( AFI -> getVarArgsGPRSize


<s> for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock


<s> if ( ! isSysReg ( ) || isSystemPStateFieldWithImm0_1 ( ) ) return false ; return SysReg . PStateField != -


<s> rtx condition_rtx , loc_ref ; if ( ! reg_or_0_operand ( op0 , SImode ) ) op0 = copy_to_mode_reg ( SImode , op0 ) ; if ( ! reg_or_0_operand ( op1 , SImode ) ) op1 = copy_to_mode_reg ( SImode , op1 ) ; condition_rtx = mt_generate_compare ( code , op0 , op1


<s> Target & llvm :: getThe<ISA_LIT>Target (


<s> if ( ! MRI . reg_nodbg_empty ( * i ) ) { YmmOrZmmUsed = true ; break ; } } } } if ( ! YmmOrZmmUsed ) return false ; assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) processBasicBlock ( MBB ) ; if ( FnHasLiveInYmmOrZmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH


<s> RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ; RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z ( TheARM64Target ) ; auto PR = PassRegistry :: getPassRegistry


<s> Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( GP0Regs


<s> const DataLayout * getDataLayout ( )


<s> case NE : return <NUM_LIT> ; case AND : { rtx op0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; rtx op1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == CONST_INT ) return INTVAL ( op1 ) >= <NUM_LIT> ; if ( GET_CODE ( op0 ) != REG ) return <NUM_LIT> ; if ( sparc_check_64 ( op0 , insn ) == <NUM_LIT> ) return <NUM_LIT> ; return ( GET_CODE ( op1 ) == REG && sparc_check_64 ( op1 , insn ) == <NUM_LIT> ) ; } case IOR : case XOR : { rtx op0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; rtx op1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) != REG || sparc_check_64 ( op0 , insn ) <= <NUM_LIT>


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; BasicBlock * Header = TheLoop -> getHeader ( ) ; if ( ! Header ) return false ; if ( Header != TheLoop -> getLoopLatch ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } Function & F = * Header -> getParent ( ) ; M = F . getParent


<s> rtx last_two_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; if ( last_two_def_reg == NULL_RTX ) return false ; return n13_consumed_by_e1_dep_p ( consumer


<s> if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm )


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 ,


<s> static Value * UseTlsOffset ( IRBuilder < > & IRB , unsigned Offset ) { Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> virtual bool EmitDwarfFileDirective ( unsigned FileNo , StringRef Directory , StringRef Filename

, unsigned CUID = <NUM_LIT> ) { return true ; }


<s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI )


<s> SDValue <ISA_LIT>TargetLowering :: lowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , Align ( <NUM_LIT> ) , false ,

false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> bool Valid ; StringRef Name ; if ( Opcode == <STR_LIT> ) Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; else Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O <<


<s> if ( re == rs + <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , rs ) ; else fprintf ( asm_out_file , <STR_LIT> , rs , re - <NUM_LIT> ) ; rs = re + <NUM_LIT> ; } if ( out_state ) fputc ( '\n' , asm_out_file


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) ==


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < NumVecs ; ++ Idx ) { SDValue Load = DAG . getLoad ( <STR_LIT> , dl , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * <NUM_LIT> ) , commonAlignment ( Alignment , Idx * <NUM_LIT> ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , BasePtr . getValueType ( ) ) ) ; Loads . push_back ( Load ) ; LoadChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isLittleEndian ( ) ) { std :: reverse ( Loads . begin ( ) , Loads . end ( ) ) ; std :: reverse ( LoadChains . begin ( ) , LoadChains . end ( ) ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadChains ) ; SDValue Value = DAG . getNode ( VT == <STR_LIT> ?

<STR_LIT> : <STR_LIT> , dl , VT , Loads ) ;


<s> static inline tree def_builtin_pure ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , mask2 , name , tcode ,


<s> baseReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT } } else { indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } scaleAmount = MCOperand :: CreateImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) { pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; } else baseReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; break ; case EA_BASE_BX_SI : baseReg = MCOperand :: CreateReg ( <STR_LIT>


<s> case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitEHSjLjSetJmp ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return emitEHSjLjLongJmp ( MI , BB


<s> EmitAlignment ( <NUM_LIT> ) ; MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * Anon = MCSymbolRefExpr :: Create ( AnonSymbol , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; const MCExpr * Sub = MCBinaryExpr :: CreateSub ( LazyPtrExpr , Anon , OutContext ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: CreateHa16 ( Sub , OutContext ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: CreateLo16 ( Sub , OutContext ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; MCSymbol * DyldStubBindingHelper = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } else { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; OutStreamer . SwitchSection ( StubSection )


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex


<s> return ( ( CCMask & <STR_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> :

<NUM_LIT> ) | ( CCMask & <STR_LIT> ) ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; auto BuildPMADDWD = [ & ] ( SDValue Mul ) { SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , Mul . getOperand ( <NUM_LIT> ) ) ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Madd , DAG . getConstant ( <NUM_LIT> , DL , MAddVT ) ) ; } ; Op0 = BuildPMADDWD ( Op0 ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && canReduceVMulWidth ( Op1 . getNode ( ) , DAG ,


<s> break ; } const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this


<s> case E_V8HFmode : case E_V16HFmode : case E_V32HFmode : case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , <NUM_LIT> )


<s> static MCRelocationInfo * create<ISA_LIT>ElfRelocation ( const Triple & TheTriple ,


<s> if ( regno == PR_REG ( <NUM_LIT> ) && mode == DImode ) return <NUM_LIT> ; if ( PR_REGNO_P ( regno ) && ( mode ) == BImode ) return <NUM_LIT> ; if ( ( PR_REGNO_P ( regno ) || GR_REGNO_P ( regno ) ) && mode == CCImode ) return <NUM_LIT> ; if ( FR_REGNO_P ( regno ) && mode == XFmode ) return <NUM_LIT> ; if ( FR_REGNO_P ( regno ) && mode == RFmode ) return <NUM_LIT> ; if ( FR_REGNO_P ( regno ) && mode == XCmode )


<s> if ( ! VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( VT , <NUM_LIT> / VT . getSizeInBits ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VecVT , In ) ; Res = DAG . getNode ( <STR_LIT> , DL , VecVT , Res ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } int NumElts = VT . getVectorNumElements ( ) ; int ScalarSizeInBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( VT . is256BitVector ( ) ) return splitVectorIntUnary ( Op , DAG ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MaskElts ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { for ( int j = ScalarSizeInBytes - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { int SourceByte = <NUM_LIT> + ( i


<s> bool useIndirectThunkCalls ( ) const { return useRetpolineIndirectCalls ( ) || useLVIControlFlowIntegrity (


<s> bool SelectPCRelForm ( SDNode * Parent , SDValue N , SDValue & Disp , SDValue & Base ) { return <ISA_LIT>Lowering -> SelectOptimalAddrMode ( Parent , N , Disp , Base , * CurDAG


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; if ( KnownZero == <NUM_LIT> && KnownOne == <NUM_LIT> ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , KnownZeroRHS , KnownOneRHS , Depth + <NUM_LIT> ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType (


<s> void dimode_scalar_chain :: mark_dual_mode_def ( df_ref def ) { gcc_assert ( DF_REF_REG_DEF_P ( def ) ) ; if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( def ) ) ) return ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , DF_REF_REGNO ( def ) , DF_REF_INSN_UID ( def )


<s> if ( MI -> isCopy ( ) ) CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) return CopySrcReg ; SrcReg =


<s> assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA ==


<s> static const <ISA_LIT>RegisterBankInfo :: ValueMapping * getFprbMapping (


<s> std :: vector < MachineInstr * > intersectionSet ; auto __first1 = liveInstrs . begin ( ) ; auto __first2 = LR -> liveInstrs . begin ( ) ; while ( __first1 != liveInstrs . end ( ) && __first2 != LR -> liveInstrs . end ( ) ) if ( * __first1 < * __first2 ) ++ __first1 ; else if ( * __first2 < *


<s> limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab )


<s> MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI . getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI . RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI . readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = CurReg == DSrc && ! MI . readsRegister ( CurReg , TRI ) ; MIB . addReg ( CurReg ,


<s> i1 = gen_reg_rtx ( DImode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0


<s> static bool isPerfectIncrement ( SDValue Inc , EVT VecTy , unsigned NumVecs ) { auto C = dyn_cast < ConstantSDNode > ( Inc ) ; return C && C -> getZExtValue ( ) == VecTy . getSizeInBits ( )


<s> for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * TargetBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == <STR_LIT>


<s> return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI , MCID


<s> return __builtin_mve_vcaddq_rot270_m_sv16qi ( __arm_vuninitializedq_s8 ( ) ,


<s> RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Instr -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) return false ; return true


<s> return true ; } if ( BaseReg == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( BaseReg != <NUM_LIT> && IndexReg != <NUM_LIT> ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return


<s> StringRef getPassName ( ) const override { return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> if ( TM . is<ISA_LIT>64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; } if ( TM . is<ISA_LIT>64 ( ) )


<s> int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc ,

SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ;


<s> for ( result = i = <NUM_LIT> ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i %


<s> bool <ISA_LIT>InstrInfo :: getMemOperandsWithOffset ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , const TargetRegisterInfo *


<s> unsigned getHWRegsReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const <ISA_LIT>Subtarget & Subtarget = FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget >


<s> if ( N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt >= <NUM_LIT> && Elt != <NUM_LIT> ) return false ; } bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N ->


<s> const MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this


<s> return parseSetNoAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFpDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> )


<s> static void core2i7_first_cycle_multipass_fini ( void * _data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; if ( data -> ready_try_change ) { sbitmap_free ( data -> ready_try_change ) ; data -> ready_try_change


<s> std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn ) ; if ( HasMultipleSuccs ) { IM . reset ( new


<s> <STR_LIT> ) ; } else { if ( STI . hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP3 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( ! STI . hasVFP2 ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . allowsUnalignedMem ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( STI . isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFP16 ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasMPExtension ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasDivideIn<ISA_LIT>Mode ( ) && ! STI . hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( MMI ) { if ( const Module * SourceModule = MMI -> getModule ( ) ) { if ( auto WCharWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag (


<s> if ( parseRegister ( Operands ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) return false ; Error ( getLoc ( ) , <STR_LIT> ) ; return true


<s> static struct machine_function * mt_init_machine_status ( void ) { struct machine_function * f ; f = ggc_alloc_cleared ( sizeof (


<s> case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) ; SpillsKnownBit = true ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addImm ( - <NUM_LIT> ) ; SpillsKnownBit = true ; break ; default : if ( Subtarget . isISA3_1 ( ) ) { BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , RegState :: Undef ) ; break ; } if ( Subtarget . isISA3_0 ( ) ) { if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) { BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) ; break ; } } BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; Register Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm (

getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmBackend :: MayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) )

== Inst . getOpcode ( ) ) return false ;


<s> if ( flag_stack_clash_protection ) return ( HOST_WIDE_INT_1U << PARAM_VALUE


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; }


<s> if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( OpVT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , OpVT ) ; return getOnesVector ( OpVT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( OpVT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , OpVT .


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI ) ; return <NUM_LIT>


<s> if ( I -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * I ) ) break ; assert ( ( ! I -> isCall ( ) && ! I -> isReturn ( ) && ! I -> isBranch ( ) ) && <STR_LIT> ) ; if ( delayHasHazard ( * I , RegDU , IM ) ) continue ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( I -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( I -> getOperand ( AddrIdx

) . getReg ( ) ) ) || I -> modifiesRegister ( <STR_LIT> , TM . getRegisterInfo ( ) ) ) continue ;


<s> static __inline qword si_xswd ( qword a ) { vec_int4 av ; av = ( vec_int4 ) ( a ) ; return ( ( qword ) ( vec_perm ( av , vec_sra ( av , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; bool ValidNamed ; ( void ) <STR_LIT> ( STI . getFeatureBits ( ) ) . toString ( Imm , ValidNamed ) ; return ValidNamed ? Success


<s> LLT Ty = MRI . getType ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned ValSize = Ty . getSizeInBits ( ) ; if ( ValSize == <NUM_LIT> ) { if ( TII . getSubtarget ( ) . useNEONForSinglePrecisionFP ( ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { assert ( ValSize == <NUM_LIT> && <STR_LIT>


<s> static __inline qword si_nor ( qword a , qword


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT


<s> unsigned SPReg ; int Offset = getFrameIndexReferenceFromSP ( MF , Info . PSPSymFrameIdx , SPReg ) ; assert ( Offset >=


<s> if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI

. getRegClass ( AssignedReg ) : nullptr ;


<s> convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , op11 , op12 ) , UNSPEC_PTEST ) ; } else { convert_op ( & op1 , insn ) ; src = op1 ; } if ( ! REG_P ( src ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } if ( vmode == V2DImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( tmp , src , src ) , insn ) ; src = tmp ; } else if ( vmode == V4SImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_sse2_pshufd ( tmp , src , const0_rtx ) , insn ) ; src = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , src


<s> unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT>


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> void relaxInstruction ( const MCInst & Inst


<s> DebugLoc dl = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII . getCallFrameDestroyOpcode ( ) ; unsigned CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; int PIdx = I -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) I -> getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = TII . getFramePred ( * I ) ; if ( ! hasReservedCallFrame ( MF ) ) { if ( IsDestroy && CalleePopAmount != <NUM_LIT> ) return MBB . erase ( I ) ; unsigned Amount = TII . getFrameSize ( * I ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } } } else if ( CalleePopAmount != <NUM_LIT> ) { emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - CalleePopAmount , MachineInstr :: NoFlags ,


<s> bool isUpperSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT> CC , const SDValue K ) { return ( isGTorGE ( CC ) && ( ( K == RHS && K == TrueVal ) || ( K == LHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == LHS && K

== TrueVal ) || ( K == RHS && K == FalseVal ) ) ) ;


<s> } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits ) { ZeroElts . setBit ( i ) ; continue ; } ConstantElts . setBit ( i ) ; ConstantBitData [ i ] = Bits ; } assert ( ( UndefElts | ZeroElts | ConstantElts ) . isAllOnesValue ( ) ) ; if ( ( UndefElts | ZeroElts ) . isAllOnesValue ( ) ) return getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; MVT MaskSVT ; if ( VT . isFloatingPoint ( ) && ( MaskSizeInBits == <NUM_LIT> || MaskSizeInBits

== <NUM_LIT> ) ) MaskSVT = <STR_LIT> ( MaskSizeInBits ) ;


<s> return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; case TargetOpcode :: G_ROTR : return