<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>CallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; if ( TFI -> hasFP ( MF ) ) for ( MCRegAliasIterator AI

( Regs -> getFramePointerRegister ( ) , this , true ) ;


<s> CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( Value == <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> auto VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! VRegAndVal ) { std :: swap ( ConstantReg , TestReg ) ; VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) { if ( HasZext ) C = VRegAndVal -> Value . getZExtValue ( ) ; else C = VRegAndVal -> Value . getSExtValue ( ) ; } break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit + * C ; } break ; case TargetOpcode :: G_XOR : if ( ( * C >> Bit ) & <NUM_LIT>


<s> RetVal1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; RetVal2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return ; } if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) { SDValue Ptr = Ld -> getBasePtr ( ) ; RetVal1 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( )


<s> S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: create ( std :: numeric_limits < int32_t > :: min ( ) , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } LLVM_FALLTHROUGH ; case AsmToken :: Colon : { S = Parser . getTok ( ) . getLoc ( ) ; <ISA_LIT>MCExpr :: VariantKind RefKind


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm (


<s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx mem , a_tramp ; int pool = TRAMPOLINE_SIZE - <NUM_LIT> ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp ,


<s> } Result = DAG . getTargetConstant ( CVal , Op . getValueType ( ) ) ; break ; } case 'S' : { if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) { Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , Op . getDebugLoc ( ) , GA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) { Result = DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , BA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) { Result = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) ) ; } else return ; break ; } case 'Y' : if ( const ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { if ( CFP -> isExactlyValue ( <NUM_LIT> ) ) { Result = DAG . getTargetConstantFP ( <NUM_LIT> , CFP -> getValueType ( <NUM_LIT> ) ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint ,


<s> static TargetLoweringObjectFile * createTLOF ( TargetMachine & TM ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) ) return new TargetLoweringObjectFileMachO ( ) ; return new <ISA_LIT>ElfTargetObjectFile (


<s> if ( ! Subtarget . hasSSE2 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( Subtarget . hasSSE41 ( ) ) { if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerShuffleAsInsertPS ( DL , V1 , V2 , Mask


<s> void <ISA_LIT>MCAsmStreamer :: EmitWeakReference ( MCSymbol * Alias


<s> if ( Ty . getSizeInBits ( ) == TRI . getRegSizeInBits ( RC ) ) return Reg ; auto Copy = MIB . buildCopy ( { & RC } , { Reg } ) ; selectCopy ( * Copy , TII , MRI , TRI , RBI


<s> return ( ( type == <NUM_LIT> || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + sh_hard_regno_nregs (

BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ;


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; bool UseUpperBits = false ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: AExtUpper : UseUpperBits = true ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL


<s> static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned SrcReg ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SrcReg = GPR32ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : SrcReg = GPR64ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : LLVM_FALLTHROUGH ; case <STR_LIT> : SrcReg = XMMArgRegs [ FPRIdx ++ ] ; break ; } unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg


<s> bool hasAnyFloatExt ( ) const { return hasFPUv2 ( ) || hasFPUv3


<s> } else if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is64BitVector ( ) ) { Vec = b . Constant ( - <NUM_LIT> , <STR_LIT> ) ; } else if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is128BitVector ( ) ) { Vec = b . ConstantVector (


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , isLittle


<s> Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( int ) imm & <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = DAG . getTargetFrameIndex


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign (


<s> assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS


<s> if ( TARGET_XCOFF ) fputs ( <STR_LIT> , stream ) ; if ( TARGET_XCOFF ) fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ; fputs ( <STR_LIT> , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ; } if ( TARGET_XCOFF ) fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ; fputc ( '\n' , stream ) ; if ( val ) { ASM_OUTPUT_DEF ( stream , name , val ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS ) { fputs ( <STR_LIT> , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ; fputs ( <STR_LIT> , stream ) ; RS6000_OUTPUT_BASENAME ( stream , val ) ; fputc ( '\n' ,


<s> for ( unsigned Reg : RegClassInfo . getOrder ( & RegClass ) ) if ( LiveRegs . available ( MF -> getRegInfo ( ) , Reg ) ) return Reg ; return <NUM_LIT>


<s> return ( ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >=


<s> const TargetRegisterClass * FirstInstrOperandRC = TII -> getRegClass ( TII -> get ( Opcode . first ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * SecondInstrDstRC = ( Opcode . first == Opcode . second ) ? FirstInstrDstRC : TII -> getRegClass ( TII -> get ( Opcode . second ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * SecondInstrOperandRC = ( Opcode . first == Opcode . second ) ? FirstInstrOperandRC : TII -> getRegClass ( TII -> get ( Opcode . second ) , <NUM_LIT> , TRI , * MF ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewTmpReg = MRI -> createVirtualRegister ( FirstInstrDstRC ) ; Register NewDstReg = DstReg . isVirtual ( ) ? MRI -> createVirtualRegister ( SecondInstrDstRC ) : DstReg ; MRI -> constrainRegClass ( SrcReg , FirstInstrOperandRC ) ; MRI -> constrainRegClass ( NewTmpReg , SecondInstrOperandRC ) ; if ( DstReg != NewDstReg ) MRI -> constrainRegClass ( NewDstReg , MRI -> getRegClass ( DstReg ) ) ; BuildInstr ( MI , Opcode , Imm0 , Imm1 , SrcReg , NewTmpReg , NewDstReg ) ; if ( DstReg != NewDstReg ) { MRI -> replaceRegWith ( DstReg , NewDstReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstReg ) ; } ToBeRemoved . insert ( & MI ) ; if ( SubregToRegMI ) ToBeRemoved . insert ( SubregToRegMI ) ; ToBeRemoved . insert ( MovMI ) ; return true


<s> unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) || ( OffReg && TRI -> regsOverlap ( EvenReg , OffReg ) ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) && ( ! OffReg || ! TRI -> regsOverlap ( OddReg , OffReg ) ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } else { InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } if ( isLd ) ++ NumLDRD2LDR ; else ++ NumSTRD2STR ; } MBBI = prior


<s> aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL


<s> MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue Base ; if ( is64Bit ) { Base = GetTLSADDR ( DAG , DAG . getEntryNode ( ) , GA , NULL , PtrVT , <STR_LIT> , <STR_LIT> , true ) ; } else { SDValue InFlag ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Base = GetTLSADDR ( DAG , Chain , GA , &

InFlag , PtrVT , <STR_LIT> , <STR_LIT> , true ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetFrameLowering & TFI = * Subtarget -> getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_ushort ( b )


<s> return ( uint16x8_t ) __builtin_aarch64_combinev4hi ( ( int16x4_t ) __a ,


<s> Is32BitAddress = false ; } if ( ! Is32BitAddress && ! ABI . ArePtrs64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } if ( ! Offset . isImm ( ) ) return loadAndAddSymbolAddress ( Offset .

getExpr ( ) , DstReg , BaseReg , Is32BitAddress , IDLoc , Instructions ) ;


<s> static void emitSPUpdate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr

:: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG , int VarArgsFrameIndex , int VarArgsStackOffset , unsigned VarArgsNumGPR , unsigned VarArgsNumFPR , const <ISA_LIT>Subtarget & Subtarget ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue


<s> write_decls ( ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; return <NUM_LIT>


<s> FinalSize += sizeGlobalAddress ( false ) ; } else if ( RelocOp -> isCPI ( ) ) { FinalSize += sizeConstPoolAddress ( false ) ; } else if ( RelocOp -> isJTI


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str =


<s> SmallVector < SDNode * , <NUM_LIT> > Queue ( <NUM_LIT> , Chain . getNode ( ) ) ; SmallSet < SDNode * , <NUM_LIT> > Visited ; while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) ) continue ; if ( MemSDNode * ChainLD = dyn_cast < MemSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear (


<s> unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node =


<s> uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New


<s> sparc_emit_set_symbolic_const64 ( temp1 , XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) , NULL_RTX ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp1 , temp2 ) ) ) ; return ; } if ( temp && GET_MODE ( temp ) == TImode ) { ti_temp = temp ; temp = gen_rtx_REG ( DImode , REGNO ( temp ) ) ; } switch ( sparc_cmodel ) { case CM_MEDLOW : if ( temp ) temp1 = temp ; else temp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( temp1 , gen_rtx_HIGH ( DImode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_LO_SUM ( DImode , temp1 , op1 ) ) ) ; break ; case CM_MEDMID : if ( temp ) { temp1 = op0 ; temp2 = op0 ; temp3 = temp ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; temp3 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_seth44 ( temp1 , op1 ) ) ; emit_insn ( gen_setm44 ( temp2 , temp1 , op1 ) ) ; emit_insn ( gen_rtx_SET ( temp3 , gen_rtx_ASHIFT ( DImode , temp2 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_setl44 ( op0 , temp3 , op1 ) ) ; break ; case CM_MEDANY : if ( temp ) { if ( rtx_equal_p ( temp , op0 ) ) { gcc_assert ( ti_temp ) ; temp = gen_rtx_REG ( DImode , REGNO ( temp ) + <NUM_LIT> ) ; } temp1 = op0 ; temp2 = temp ; temp3 = op0 ; temp4 = op0 ; temp5 = op0 ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; temp3 = gen_reg_rtx ( DImode ) ; temp4 = gen_reg_rtx ( DImode ) ; temp5 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_sethh ( temp1 , op1 ) ) ; emit_insn ( gen_setlm ( temp2 , op1 ) ) ; emit_insn ( gen_sethm ( temp3 , temp1 , op1 ) ) ; emit_insn ( gen_rtx_SET ( temp4 , gen_rtx_ASHIFT ( DImode , temp3 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( temp5 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; emit_insn ( gen_setlo ( op0 , temp5 , op1 ) ) ; break ; case CM_EMBMEDANY : if ( data_segment_operand ( op1 , GET_MODE ( op1 ) ) ) { if ( temp ) { temp1 = temp ; temp2 = op0 ; } else { temp1 = gen_reg_rtx (


<s> if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { unsigned NumElts = StoredVal . getValueType ( ) . getVectorNumElements ( ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; if ( NumElts < <NUM_LIT> ) StoredVal = DAG . getZeroExtendInReg ( StoredVal , dl , EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) || ( ( StoreVT == <STR_LIT> || StoreVT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue


<s> if ( code == CONST_INT || code == CONST_DOUBLE )


<s> if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; if ( SrcVT . getVectorNumElements ( ) == NumDstElts ) Shuffle = unsigned ( <STR_LIT> ) ; else Shuffle = unsigned ( <STR_LIT> ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( ! Subtarget . hasAVX2 ( ) && isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector (


<s> using namespace TargetOpcode ; using namespace MIPatternMatch ; auto * InsMI = getOpcodeDef ( G_INSERT_VECTOR_ELT , I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! InsMI ) return false ; auto * UndefMI = getOpcodeDef ( G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! UndefMI ) return false ; Register ScalarReg = InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * ScalarRB = RBI . getRegBank ( ScalarReg , MRI , TRI ) ; int64_t Index = <NUM_LIT> ; if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Index ) ) || Index ) return false ; auto * ZeroVec = getOpcodeDef ( G_BUILD_VECTOR , I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! ZeroVec ) return false ; int64_t Zero = <NUM_LIT> ; if ( ! mi_match ( ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Zero ) ) || Zero ) return false ; for ( unsigned i = <NUM_LIT> , e = ZeroVec -> getNumOperands ( ) ; i < e ; ++ i ) { if ( ZeroVec -> getOperand ( i ) . getReg ( ) != ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; } LLT VecTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT EltTy = VecTy . getElementType ( ) ; if ( VecTy . getSizeInBits ( ) != <NUM_LIT> || EltTy . getSizeInBits ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg , MIB ) ; if ( ! Widen ) return false ; ScalarReg = Widen -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { ScalarReg } ) ; if ( IsFP ) Dup . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Dup , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true


<s> if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasDSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! has8MSecExt ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal < <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; if ( ! hasV8MMainline ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal <= <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal


<s> if ( ! <ISA_LIT>FI -> getLOHRelated ( ) . empty ( ) )


<s> if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'v' && TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' ) canonical += <NUM_LIT> ; else if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' && TOLOWER ( canonical [ <NUM_LIT> ] ) == 'm' ) canonical += <NUM_LIT> ; else if ( TOLOWER ( canonical [ <NUM_LIT> ]


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; return getInt64 ( CurDAG ,


<s> uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , SDLoc ( N ) , <STR_LIT> ) ; return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand


<s> if ( isFloatingPointZero ( Op ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , SDLoc ( Op ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld ->

isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ;


<s> static bool ix86_frame_pointer_required ( void ) { if ( cfun -> machine -> accesses_prev_frame ) return true ; if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return


<s> assert ( WaitingQueues . count ( MI ) && <STR_LIT> ) ; WaitingQueues . find ( MI ) -> getSecond ( ) .


<s> MCTargetStreamer & TS = * getTargetStreamer ( ) ; <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer


<s> break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( <STR_LIT> ( Vec . getNode ( ) ) ) { if ( <STR_LIT> ( SubVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , dl ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SubVec . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { unsigned Idx2Val = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( IdxVal + Idx2Val , dl ) ) ; } if ( SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> && SubVec . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && SubVec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Ins = SubVec . getOperand ( <NUM_LIT> ) ; if ( Ins . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ( Ins . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Ins . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) <= SubVecVT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , Ins . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } if ( ! IsI1Vector && SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> ) { MVT CastVT = SubVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; unsigned NumElems = OpVT . getSizeInBits ( ) / CastVT . getScalarSizeInBits ( ) ; MVT NewVT = <STR_LIT> ( CastVT . getVectorElementType ( ) , NumElems ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , dl , NewVT , DAG . getBitcast ( NewVT , Vec ) , SubVec . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( OpVT , Insert ) ; } } if ( IsI1Vector ) return SDValue ( ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == OpVT && ( IdxVal != <NUM_LIT> || ! Vec . isUndef ( ) ) ) { int ExtIdxVal = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; if ( ExtIdxVal != <NUM_LIT> ) { int VecNumElts = OpVT . getVectorNumElements ( ) ; int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const <ISA_LIT>RegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - RegInfo -> getSlotSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; Offset = MaxOffset - Offset + saveAreaOffset ; if ( HasFP && FramePtr == Reg ) continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( Label , DwarfReg


<s> } , [ & TII = TII ] ( MachineInstr & MI , OpcodePair Opcode , unsigned Imm0 , unsigned Imm1 , Register SrcReg , Register NewTmpReg , Register NewDstReg ) { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode . first ) , NewTmpReg ) . addReg ( SrcReg ) . addImm ( Imm0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode . second ) , NewDstReg

) . addReg ( NewTmpReg ) . addImm ( Imm1 ) . addImm ( <NUM_LIT> ) ;


<s> insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) )


<s> return ( __mmask8 ) __builtin_ia32_ucmpq128_mask ( ( __v2di ) __A ,


<s> else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , true ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> } else if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is256BitVector ( ) ) { Vec = b . ConstantVector ( <STR_LIT> , <NUM_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; return b . BITCAST ( Vec ,


<s> op1 = operands [ <NUM_LIT> ] ; mask = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , <NUM_LIT> ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest


<s> int ShiftRegBytes = TRI -> getRegSizeInBits ( ShiftRC ) / <NUM_LIT> ; unsigned DefSubRegImm = SubRegImms [ Log2_32 ( DefRegBytes ) ] ; unsigned StateReg = GetStateRegInRC ( ShiftRC ) ; unsigned TmpReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( TmpReg ) ; unsigned ShiftInputReg = TmpReg ; if ( DefRegBytes != ShiftRegBytes ) { unsigned UndefReg = MRI -> createVirtualRegister ( & ShiftRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , UndefReg ) ; ShiftInputReg = MRI -> createVirtualRegister ( & ShiftRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ShiftInputReg ) . addReg ( UndefReg ) . addReg ( TmpReg ) . addImm ( DefSubRegImm ) ; } unsigned ShiftedReg = MRI -> createVirtualRegister ( & ShiftRC ) ; auto Shift1I = BuildMI ( MBB , InsertPt , Loc , TII -> get ( ShiftOpCode ) , ShiftedReg ) . addReg ( ShiftInputReg ) . addReg ( StateReg ) ; ( void ) Shift1I ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Shift1I -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( DefRegBytes == ShiftRegBytes ) { ShiftInputReg = ShiftedReg ; auto Shift2I = BuildMI ( MBB , InsertPt , Loc , TII -> get ( ShiftOpCode ) , OldDefReg ) . addReg ( ShiftInputReg ) . addReg ( StateReg ) ; ( void ) Shift2I


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM -> getTargetLowering (


<s> NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } const Align Align = MF -> getAlignment ( ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << Log2 ( Align ) << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= Align .


<s> static void emitThumb1LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF .


<s> OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer -> SwitchSection ( getObjFileLowering (


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return false


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( N ) ; Base = Mgs -> getBasePtr ( ) ; Index = Mgs -> getIndex ( ) ; unsigned ScalarSize = Mgs -> getValue ( ) . getValueType ( ) . getScalarSizeInBits ( ) ; Scale = getI8Imm ( ScalarSize / <NUM_LIT> , DL ) ; if ( isa < ConstantSDNode > ( Base


<s> <ISA_LIT>64ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine

( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT


<s> return ( int32x4_t ) __builtin_neon_vaddwsv4hi ( __a ,


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; Out . EmitBundleLock ( true


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups , STI ) ; isAdd = <STR_LIT> ( Imm8 ) == <STR_LIT> ; } uint32_t Binary = <STR_LIT> (


<s> __builtin_ia32_storedqudi512_mask ( ( long long * ) __P , ( __v8di ) __A , ( __mmask8 )


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass >


<s> temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = sparc_tls_got ( ) ; emit_insn ( gen_tie_hi22 ( temp1 , addr ) ) ; emit_insn ( gen_tie_lo10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_ld32 ( temp3 , got , temp2 , addr ) ) ; else emit_insn ( gen_tie_ld64 ( temp3 , got , temp2 , addr ) ) ; if ( TARGET_SUN_TLS ) { ret = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_add32 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; else emit_insn ( gen_tie_add64 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; } else ret = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 ) ; break ; case TLS_MODEL_LOCAL_EXEC : temp1 = gen_reg_rtx ( Pmode ) ; temp2 = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) { emit_insn ( gen_tle_hix22_sp32 ( temp1 , addr ) ) ; emit_insn ( gen_tle_lox10_sp32 ( temp2 , temp1 , addr ) ) ; } else { emit_insn ( gen_tle_hix22_sp64 ( temp1 , addr ) ) ; emit_insn ( gen_tle_lox10_sp64 ( temp2 , temp1 , addr ) ) ; } ret = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> )


<s> return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { llvm_unreachable (


<s> return MFI . hasVarSizedObjects ( ) && ! hasBasePointer (


<s> static SDNode * findFlagUse ( SDNode * N ) { unsigned FlagResNo = N -> getNumValues ( ) - <NUM_LIT> ; for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) { SDUse & Use = I . getUse


) ) _mm_loadu_epi64 ( void const * __P ) {


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; if ( Subtarget -> hasMVEIntegerOps

( ) ) return MVEMaxSupportedInterleaveFactor ;


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg (


<s> return ( __m64 ) __builtin_ia32_psradi ( ( __v2si ) __m ,


<s> bool <ISA_LIT>PassConfig :: addPreISel (


<s> unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , SD , FixedValue ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsExtern << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup .


<s> Imm = o . Imm ; break ; case k_ShiftedImm : ShiftedImm = o . ShiftedImm ; break ; case k_CondCode : CondCode = o . CondCode ; break ; case k_FPImm : FPImm = o . FPImm ; break ; case k_Barrier : Barrier = o . Barrier ; break ; case k_Register : Reg = o . Reg ; break ; case k_VectorList : VectorList = o .


<s> bool <ISA_LIT>DAGToDAGISel :: SelectLogicalImm ( SDValue N , SDValue & Imm ) { uint32_t Bits ; uint32_t RegWidth = N . getValueType ( ) . getSizeInBits ( ) ; ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ; if ( ! CN ) return false ; if ( ! A64Imms :: isLogicalImm ( RegWidth , CN -> getZExtValue ( ) , Bits ) ) return false ; Imm = CurDAG -> getTargetConstant ( Bits , <STR_LIT>


<s> void build ( function_builder & b , const function_group_info & group ) const OVERRIDE { b . add_overloaded_functions ( group , MODE_none ) ; build_all ( b , <STR_LIT> , group , MODE_none


<s> case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries


<s> unsigned <ISA_LIT>MCCodeEmitter :: adjustPqBitsSpls ( const MCInst & Inst , unsigned Value , const MCSubtargetInfo & STI ) const { return adjustPqBits ( Inst , Value , <NUM_LIT> ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( getExtend ( )


<s> if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory


<s> return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand ::


<s> const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> if ( TARGET_VIS ) switch ( mode ) { case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode


<s> static DecodeStatus DecodePCRel24BranchTarget ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { int32_t Offset = SignExtend32 < <NUM_LIT> >


<s> unsigned Op ; SDVTList VTs = CurDAG -> getVTList ( AN -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; if ( VT == <STR_LIT> ) Op = Op8 ; else if ( VT == <STR_LIT> ) Op = Op16 ; else if ( VT == <STR_LIT> ) Op = Op32 ; else if ( VT == <STR_LIT> ) { Op = Op64 ; VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ; Ops . push_back ( AN -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> SelectNodeTo ( Node , Op , VTs , & Ops [ <NUM_LIT> ] , Ops . size (


<s> __vector unsigned char vc16 ; __vector unsigned short vs8 ; __vector unsigned int vi4 ; __vector float vf1 ; vc16 = ( __vector unsigned char ) __builtin_pack_vector_int128 ( __A , __A ) ; vs8 = ( __vector unsigned short ) vec_vmrglb ( vc16 , zero ) ; vi4 = ( __vector unsigned int ) vec_vmrghh ( vs8 , ( __vector unsigned short ) zero ) ; vf1 = ( __vector float ) vec_ctf ( vi4 , <NUM_LIT> ) ; return ( __m128 )


<s> LoLoop . ToRemove . insert ( End ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec


<s> unsigned getFI ( ) const { assert ( isFIBase ( )


<s> if ( ! warned && warn_psabi ) { const char * url = CHANGES_ROOT_URL <STR_LIT> ; warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; } } else return MIN (


<s> } in ; in . v = a ; return ( in . d [


<s> inline vector float vec_max ( vector float a1 , vector float


<s> emitFrameDirective ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> )


<s> dfa_state_size = state_size ( ) ; temp_dfa_state = xmalloc ( dfa_state_size ) ; prev_cycle_state = xmalloc ( dfa_state_size ) ; } dfa_pre_cycle_insn = make_insn_raw ( gen_pre_cycle ( )


<s> else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( ! decl && ! TARGET_64BIT ) { tree type ; type = TREE_OPERAND ( exp , <NUM_LIT> ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; if ( ix86_function_regparm ( type , NULL ) >= <NUM_LIT> ) { return false ; } } if ( decl && DECL_DLLIMPORT_P ( decl ) && ix86_function_regparm ( TREE_TYPE ( decl ) , NULL


<s> uint64_t NumBytes = <NUM_LIT> ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( TargetMBB ) { unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( TargetMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; } TargetMBB -> setHasAddressTaken


<s> return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction


<s> swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= <NUM_LIT> ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && ( GET_CODE ( SET_DEST ( new_body ) ) == MEM


<s> tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret


<s> } if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = <STR_LIT> ; EVT Ty = <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ]

. first , RegsToPass [ i ] . second , InFlag ) ;


<s> assert ( Kind == k_SVCR && <STR_LIT> ) ; return StringRef ( SVCR . Data , SVCR .


<s> assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution


<s> rtx mode_mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ; shift = expand_binop ( SImode , and_optab , gen_lowpart ( SImode , addr ) , mode_mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( <NUM_LIT> ) , shift , <NUM_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return


<s> if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 ) return Reloc :: PIC_ ; return Reloc ::


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitStore ( EVT VT , unsigned Val , const <ISA_LIT>AddressMode & AM ) { unsigned Opc = <NUM_LIT> ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : default : return false ; case <STR_LIT> : { unsigned AndResult = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , AndResult ) . addReg ( Val ) . addImm ( <NUM_LIT> ) ; Val = AndResult ; } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc


<s> case LTU : case GT : case GTU : inverted_p = ! inverted_p ; case LE : case LEU : case GE : case GEU : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else { switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case LE : case LEU : case GT : case GTU : case LT : case LTU : case GE : case GEU : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } } else { switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case LEU : case GTU : case LTU : case GEU : case LE : case GT : case LT : case GE : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; break ; default : gcc_unreachable ( )


<s> if ( RegNo == <NUM_LIT> || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ) ; return


<s> unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += <NUM_LIT>


<s> assert ( Kind == k_SysReg && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg . Length


<s> rtx ix86_tls_module_base ( void ) { if ( ! ix86_tls_module_base_symbol


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N


<s> if ( rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT ) { error ( <STR_LIT> <STR_LIT> ) ; return const0_rtx ; } if ( arg0 == error_mark_node ) return const0_rtx ; if ( ! u5bit_cint_operand ( op0 , VOIDmode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } pat = GEN_FCN ( icode ) ( op0


<s> vtst_p64 ( poly64x1_t a , poly64x1_t b ) { return ( uint64x1_t ) ( ( a & b )


<s> if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , dl , <STR_LIT> ) ; return true


<s> case D22 : return <NUM_LIT> ; case D23 : return <NUM_LIT> ; case D24 : return <NUM_LIT> ; case D25 : return <NUM_LIT> ; case D26 : return <NUM_LIT> ; case D27 : return <NUM_LIT> ; case D28 : return <NUM_LIT> ; case D29 : return <NUM_LIT> ; case D30 : return <NUM_LIT> ; case D31 : return <NUM_LIT> ; case S0 : case S1 : case S2 : case S3 : case S4 : case S5 : case S6 : case S7 : case S8 : case S9 : case S10 : case S11 : case S12 : case S13 : case S14 : case S15 : case S16 : case S17 : case S18 : case S19 : case S20 : case S21 : case S22 : case S23 : case S24 : case S25 : case S26 : case S27 : case S28 : case S29 : case S30 : case S31 : { if ( isSPVFP ) * isSPVFP = true ; switch ( RegEnum ) { default : return <NUM_LIT> ; case S0 : return <NUM_LIT> ; case S1 : return <NUM_LIT> ; case S2 : return <NUM_LIT> ; case S3 : return <NUM_LIT> ; case S4 : return <NUM_LIT> ; case S5 : return <NUM_LIT> ; case S6 : return <NUM_LIT> ; case S7 : return <NUM_LIT> ; case S8 : return <NUM_LIT> ; case S9 : return <NUM_LIT> ; case S10 : return <NUM_LIT> ; case S11 : return <NUM_LIT> ; case S12 : return <NUM_LIT> ; case S13 : return <NUM_LIT> ; case S14 : return <NUM_LIT> ; case S15 : return <NUM_LIT> ; case S16 : return <NUM_LIT> ; case S17 : return <NUM_LIT> ; case S18 : return <NUM_LIT> ; case S19 : return <NUM_LIT> ; case S20 : return <NUM_LIT> ; case S21 : return <NUM_LIT> ; case S22 : return <NUM_LIT> ; case S23 : return <NUM_LIT> ; case S24 : return <NUM_LIT> ; case S25 : return <NUM_LIT>


<s> switch ( mode ) { case E_V8QImode : case E_V4HImode : case E_V2SImode : return true ; case E_V2SFmode : return true


<s> static const MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target & T ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>_32Disassembler


<s> if ( * code == LEU && CONST_INT_P ( * op1 ) ) { * op1 = gen_int_mode ( INTVAL ( * op1 ) + <NUM_LIT> ,


<s> int getAddressOfCalleeRegister ( ) { return <STR_LIT>


<s> } else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI


<s> return __builtin_mve_vrev64q_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a ,


<s> assert ( std :: is_sorted ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) && std :: is_sorted ( std ::

begin ( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain ) ) && <STR_LIT> ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false


<s> bool tDest = <STR_LIT> . contains ( DestReg ) ; bool tSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <STR_LIT> ; if ( tDest && tSrc ) Opc = <STR_LIT> ; else if ( tSrc ) Opc = <STR_LIT> ; else if ( tDest ) Opc = <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg )

. addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> assert ( m_pRelaDyn != NULL && <STR_LIT> ) ; return * m_pRelaDyn


<s> static bool sparc_can_follow_jump ( const rtx_insn * follower , const rtx_insn * followee ) { if ( CROSSING_JUMP_P ( followee ) && ! CROSSING_JUMP_P ( follower ) ) return false ; return true


<s> SDLoc DL ( Op ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = TLI . getPointerTy ( MF . getDataLayout ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned Depth = Op . getConstantOperandVal ( <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_vphaddbq ( ( __v16qi )


<s> assert ( ApplyFunctions . find ( pType ) != ApplyFunctions . end ( ) ) ; return ApplyFunctions [ pType ] .


<s> static bool rs6000_real_tls_symbol_ref_p (


<s> auto Attr = Caller -> getFnAttribute ( <STR_LIT> ) ; if ( Attr . getValueAsString ( ) == <STR_LIT> ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv


<s> Inst . addOperand ( MCOperand :: createImm ( CE ->


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT>


<s> return ( __m256 ) __builtin_ia32_cvtdq2ps256_mask ( ( __v8si ) __A , ( __v8sf )


<s> SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueOp = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; unsigned CCValid , CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCValid , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCValid , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) ,


<s> case NON_PREFIXED_D : switch ( result_form ) { case INSN_FORM_X : case INSN_FORM_D : case INSN_FORM_DS : case INSN_FORM_BASE_REG : return true ; default : return false ; } break ; case NON_PREFIXED_DS : switch ( result_form ) { case INSN_FORM_X : case INSN_FORM_DS : case INSN_FORM_BASE_REG : return true ; default : return false ; } break ; default : break ; } return


<s> FunctionPass * llvm :: createNEONMoveFixPass ( ) { return new NEONMoveFixPass (


<s> return Subtarget . hasVLX ( ) || Subtarget . canExtendTo512DQ ( )


<s> for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d ->


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static inline int getFP64Imm ( const APFloat


<s> if ( VT == <STR_LIT> && C ) return Op ; if ( Subtarget . isISA3_1 ( ) ) { if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; } if ( ! C ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue Mtvsrz = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned InsertAtElement = C ->


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasStackAlignmentAttr ( ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF


<s> if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( V ) ) return true ; return false


<s> case <STR_LIT> : { assert ( VT . getScalarType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; Known . Zero . setBitsFrom ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } if ( isTargetShuffle ( Opc ) ) { bool IsUnary ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask , IsUnary ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; Known . Zero . setAllBits ( ) ; Known . One . setAllBits ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { Known . resetAll ( ) ; break ; } else if ( M == SM_SentinelZero ) { Known . One . clearAllBits ( ) ; continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { Known . resetAll ( ) ; break ; } DemandedOps [ OpIdx ] . setBit (


<s> else if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . insert ( Inst . begin ( ) , MCOperand :: CreateReg ( GP0Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT>


<s> <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo

( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) {


UseSoftFloat && ! In<ISA_LIT>16HardFloat ;


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_mode_ok_p [ mode ]


<s> int thumb_shiftable_const ( unsigned HOST_WIDE_INT val ) { unsigned HOST_WIDE_INT mask = <NUM_LIT> ; int i ; val = val & ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; if ( val == <NUM_LIT> ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( val & ( mask << i ) ) == val ) return <NUM_LIT> ; return


<s> AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation =


<s> return target ; case IA64_BUILTIN_FLUSHRS : emit_insn ( gen_flushrs ( ) ) ; return const0_rtx ; case IA64_BUILTIN_INFQ : case IA64_BUILTIN_HUGE_VALQ : { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = CONST_DOUBLE_FROM_REAL_VALUE ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ : case IA64_BUILTIN_COPYSIGNQ : return expand_call ( exp , target , ignore ) ; default : gcc_unreachable (


<s> VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getVectorElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( VecSize != <NUM_LIT> && VecSize % <NUM_LIT> != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isHalfTy ( ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( i & Mask ) != <NUM_LIT> && EltIdx != - <NUM_LIT> ) return SDValue ( ) ; if ( ( i & Mask ) == <NUM_LIT> && ( unsigned ) EltIdx != ( i >> Shift ) ) return SDValue ( ) ; } LLVMContext * Context = DAG . getContext ( ) ; unsigned NBits = VT . getVectorElementType ( ) . getSizeInBits ( ) << Shift ; EVT NeVT = EVT :: getIntegerVT ( * Context , NBits ) ; EVT NVT = EVT :: getVectorVT ( * Context , NeVT , NumElems >> Shift ) ; if ( ! isTypeLegal ( NVT ) ) return SDValue ( ) ; unsigned SignificantBits = NVT . getSizeInBits ( ) >> Shift ; if ( V1 . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == SignificantBits ) { SDValue V = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CIdx && CIdx -> getZExtValue ( ) == <NUM_LIT> && ( ! <STR_LIT> ( V . getNode ( ) ) || ! V . hasOneUse ( ) ) ) { if ( V . getValueSizeInBits ( ) > V1 . getValueSizeInBits ( ) ) { unsigned Ratio = V . getValueSizeInBits ( ) / V1 . getValueSizeInBits ( ) ; EVT FullVT = V . getValueType ( ) ; EVT SubVecVT = EVT :: getVectorVT ( * Context , FullVT . getVectorElementType ( ) , FullVT .


<s> SDValue Extract = Cast . getOperand ( <NUM_LIT> ) ; MVT DestVT = Cast . getSimpleValueType ( ) ; if ( Extract . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Extract . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue VecOp = Extract . getOperand ( <NUM_LIT> ) ; MVT FromVT = VecOp . getSimpleValueType ( ) ; unsigned NumEltsInXMM = <NUM_LIT> / FromVT . getScalarSizeInBits ( ) ; MVT Vec128VT = <STR_LIT> ( FromVT . getScalarType ( ) , NumEltsInXMM ) ; MVT ToVT = <STR_LIT> ( DestVT , NumEltsInXMM ) ; if ( ! useVectorCast ( Cast . getOpcode ( ) , Vec128VT , ToVT , Subtarget ) ) return SDValue ( ) ; SDLoc DL ( Cast ) ; if ( ! isNullConstant ( Extract . getOperand ( <NUM_LIT> ) )


<s> const MCExpr * <ISA_LIT>MCAsmInfoDarwin :: getExprForPersonalitySymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { MCContext & Context = Streamer .


<s> static bool sh_pass_in_reg_p ( const CUMULATIVE_ARGS & cum , machine_mode mode , const_tree type ) { return ( ( type == <NUM_LIT> || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS

( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + HARD_REGNO_NREGS ( BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ;


<s> if ( Reg != - <NUM_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } <STR_LIT> mapper ; bool IsValidSpecialReg ; Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits


<s> const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget -> isABI_N32


<s> SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI


<s> rtx use_body = PATTERN ( use_insn ) ; if ( GET_CODE ( use_body ) != SET || GET_CODE ( SET_SRC ( use_body ) ) != UNSPEC || XINT ( SET_SRC ( use_body ) ,

<NUM_LIT> ) != UNSPEC_VSX_XXSPLTW || XEXP ( XEXP ( SET_SRC ( use_body ) , <NUM_LIT> ) , <NUM_LIT> ) != const0_rtx ) return <NUM_LIT> ;


<s> ( void ) State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ; } return false ; } if ( ! ArgFlags . isHva ( ) || ArgFlags . isHvaStart ( ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_64_VectorCallGetGPRs ( ) ) ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! ArgFlags . isHva ( )


<s> unsigned char OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) ,


<s> unsigned getITMaskEncoding ( ) { assert ( inITBlock ( ) ) ; unsigned Mask = ITState . Mask ; unsigned TZ = countTrailingZeros


<s> return TargetTriple . getOS ( ) == Triple


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . LookupSymbol ( Name ) ; if ( Sym ) return reportParseError


<s> StoreSDNode * S = cast < StoreSDNode > ( N ) ; if ( S -> isVolatile ( ) ) return SDValue ( ) ; if ( ! Subtarget -> isMisaligned128StoreSlow ( ) ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT

. getVectorElementType ( ) , NumElts ) ;


<s> if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT>

) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> return Op . getOpcode ( ) == <STR_LIT> || cast < ConstantSDNode > ( Op ) -> getZExtValue ( )


<s> ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType ( ) ; EVT ExtrTy = WideTy . getVectorElementType ( ) ; if ( ExtrTy == <STR_LIT> || ExtrTy ==


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useDwarfDirectory , MCInstPrinter * InstPrint ,

MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> MCSubtargetInfo & STI = copySTI ( ) ; auto FB = ComputeAvailableFeatures ( STI . ToggleFeature ( <STR_LIT> ) ) ; setAvailableFeatures ( FB


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset


<s> bool isThumbOne ( ) const { return isThumb ( ) && ! STI .


<s> void setOutliningStyle ( std :: string Style ) { OutliningStyle = Style


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) Opc


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( )


<s> SDValue <ISA_LIT>DAGToDAGISel :: createDTuple ( ArrayRef < SDValue > Regs ) { static unsigned RegClassIDs [ ] = { <STR_LIT> ,


<s> if ( ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg0 ) || ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg1 ) ) return NULL ; if ( m_eq_p ? known_gt ( arg0 , arg1 ) : known_ge ( arg0 , arg1 ) ) return f . fold_to_pfalse ( ) ; if ( m_eq_p ? maybe_gt ( arg0 , arg1 ) :

maybe_ge ( arg0 , arg1 ) ) return NULL ;


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , DL ( computeDataLayout (

Triple ( TT ) , TargetABI , isLittle ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) {


<s> static DecodeStatus DecodeMVE_MEM_1_pre ( MCInst & Inst , unsigned Val , uint64_t

Address , const MCDisassembler * Decoder ) {


<s> crtl -> uses_pic_offset_table = <NUM_LIT> ; return pic_offset_table_rtx ; } if ( TARGET_SUN_TLS && TARGET_ARCH32 ) { load_got_register ( ) ; return


<s> case MachineOperand :: MO_ConstantPoolIndex : return AP . GetCPISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return AP . GetJTISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_BlockAddress : return AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; default : llvm_unreachable ( <STR_LIT> )


<s> if ( ! GV ) return false ; if ( ! GV -> hasAttribute ( <STR_LIT> ) ) return false ; assert ( PointerSize == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( PointerSize >= GV -> getAlign ( ) . valueOrOne ( ) . value ( ) && <STR_LIT> <STR_LIT> ) ; Type * PtrType = GV -> getType ( ) ; assert ( PtrType -> isPointerTy ( ) && <STR_LIT> ) ; Type * GVType = dyn_cast < PointerType > ( PtrType ) -> getElementType ( ) ; assert ( GVType -> isSized ( ) && <STR_LIT> <STR_LIT> ) ; if ( GVType -> isVectorTy ( ) ) report_fatal_error (