<s> bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream

& O , const char * Modifier = nullptr ) ;


<s> if ( needsStackRealignment ( MF ) && MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) )


<s> if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base .


<s> if ( ST -> hasSlowLoadDSubregister ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; if ( ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return std :: max ( BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) , <NUM_LIT> ) ; } return BaseT :: getVectorInstrCost ( Opcode ,


<s> virtual void initializePass ( ) { pushTTIStack ( this


<s> uint64_t Target = Address + Imm ; if ( ! TT . is<ISA_LIT>64 ( ) ) Target &= <NUM_LIT> ; O << formatHex ( Target ) ; } else { if ( ! TT . isOSAIX ( ) ) O << <STR_LIT> ; else O


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; assert ( ! ArchFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> +


<s> static __inline int _mm_cvtsi64_si32 (


<s> void <ISA_LIT>Relocator :: addCopyReloc ( ResolveInfo & pSym ) { Relocation & rel_entry = * getTarget ( ) . getRelDyn ( ) . create ( ) ; rel_entry . setType ( llvm :: ELF


<s> tree field = NULL_TREE , field_chain = NULL_TREE ; int i ; tree type = make_node ( RECORD_TYPE ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ i ] ) , unsigned_type_node ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; } field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ <NUM_LIT> ] ) , build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; finish_builtin_struct ( type , <STR_LIT> ,


<s> static unsigned int arm_autovectorize_vector_sizes (


<s> if ( ( * o ) -> isStore ( ) && ( * o ) -> getValue ( ) ) if ( const FixedStackPseudoSourceValue * Value = dyn_cast < const FixedStackPseudoSourceValue > ( ( * o ) -> getValue ( ) ) ) { FrameIndex = Value -> getFrameIndex ( ) ; MMO = * o ; return true ; } } return false


<s> if ( Op0 . isReg ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . Reg = Op0 . getReg ( ) ; } else { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = Op0 . getIndex ( ) ; } const MachineOperand & Op1 = MI -> getOperand ( Operand + <NUM_LIT> ) ; AM . Scale = Op1 . getImm ( ) ; const MachineOperand & Op2 = MI -> getOperand ( Operand + <NUM_LIT> ) ; AM . IndexReg = Op2 . getReg ( ) ; const MachineOperand & Op3 = MI -> getOperand ( Operand + <NUM_LIT> ) ; if ( Op3 . isGlobal ( ) ) AM . GV = Op3 . getGlobal


<s> if ( auto Value = stripModuloOnShift ( * this , N , DCI


<s> MIB = BuildMI ( MBB , llvm :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg (


<s> unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , dl , SPDiff , isTailCall , RegsToPass , Ops , NodeTys , <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) , <ISA_LIT>SubTarget . isSVR4ABI ( ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo

( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


<s> if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm ,


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false


<s> assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef OptStr = Tok . getString ( ) ; unsigned Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( )


<s> return lowerATOMIC_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op


<s> void <ISA_LIT>AsmParser :: getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic ==

<STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ;


<s> explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ,


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) ->


<s> case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ; break ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB (


<s> unsigned stackAlignment ( ) const { return isFP64bit ( ) ? <NUM_LIT>


<s> <ISA_LIT>LongBranchStub :: <ISA_LIT>LongBranchStub ( const uint32_t * pData , size_t pSize , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : m_pData ( pData ) , m_Name ( <STR_LIT> ) , m_Size ( pSize ) { for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ;


<s> rtx xfoo0 ; if ( GET_CODE ( x ) == REG ) { extern rtx * reg_equiv_mem ; if ( ! reload_in_progress || reg_equiv_mem [ REGNO ( x ) ] == <NUM_LIT> || indirectable_address_p ( reg_equiv_mem [ REGNO ( x ) ] , strict ) ) return <NUM_LIT> ; } if ( indirectable_constant_address_p ( x ) ) return <NUM_LIT> ; if ( indirectable_address_p ( x , strict ) ) return <NUM_LIT> ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == MEM && indirectable_address_p (


<s> <ISA_LIT>COFFTargetAsmInfo :: <ISA_LIT>COFFTargetAsmInfo ( const Triple & Triple ) { AsmTransCBE = x86_asm_table ; AssemblerDialect =


<s> static const char * rs6000_debug_vector_unit ( enum rs6000_vector v ) { const char * ret ; switch ( v ) { case VECTOR_NONE : ret = <STR_LIT> ; break ; case VECTOR_ALTIVEC : ret = <STR_LIT> ; break ; case VECTOR_VSX : ret = <STR_LIT> ; break ; case VECTOR_P8_VECTOR : ret = <STR_LIT> ; break ; case VECTOR_PAIRED : ret = <STR_LIT> ; break ; case VECTOR_SPE : ret = <STR_LIT> ; break ; case VECTOR_OTHER : ret = <STR_LIT> ; break ; default : ret = <STR_LIT> ; break ; } return ret


<s> case VMALLE1IS : case ALLE2IS : case ALLE3IS : case ALLE1IS : case VMALLS12E1IS : case VMALLE1


<s> RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackendEB ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackendEL ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64Target , create<ISA_LIT>AsmBackendEB ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64elTarget , create<ISA_LIT>AsmBackendEL ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>elTarget ,


<s> unsigned i = <NUM_LIT> ; while ( ! MI -> getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits


<s> unsigned Dcpu16RegisterInfo :: getEHHandlerRegister (


<s> SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ; SDValue HighBitcast = DAG . getBitcast


<s> unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = <ISA_LIT>FrameInfo :: getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max (


<s> assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O <<


<s> static int function_arg_advance_ms_64 ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bytes , HOST_WIDE_INT words ) { gcc_assert ( bytes == <NUM_LIT> || bytes == <NUM_LIT> || bytes == <NUM_LIT> || bytes == <NUM_LIT> ) ; cum -> words += words ; if ( cum -> nregs > <NUM_LIT> ) { cum -> nregs


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB

, unsigned uid , MCContext & Ctx ) const {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return true ; break ; case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = true ; break ; } Register FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg = SwapOps ? TrueReg : FalseReg ; if ( MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) || MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) ) { const TargetRegisterClass * FirstRC = MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register OldFirstReg = FirstReg ; FirstReg = MRI . createVirtualRegister


<s> unsigned RegNo = Stack [ i ] ; if ( ! ( Defs & ( <NUM_LIT> << RegNo ) ) ) Kills |= ( <NUM_LIT> << RegNo ) ; else Defs &= ~ ( <NUM_LIT> << RegNo ) ; } assert ( ( Kills & Defs ) == <NUM_LIT> && <STR_LIT> ) ; while ( Kills && Defs ) { unsigned KReg = countTrailingZeros ( Kills ) ; unsigned DReg = countTrailingZeros ( Defs ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> << DReg << <STR_LIT> ) ; std :: swap ( Stack [ getSlot ( KReg ) ] , Stack [ getSlot ( DReg ) ] ) ; std :: swap ( RegMap [ KReg ] ,


<s> rtx aarch64_load_tp ( rtx target ) { if ( ! target || GET_MODE ( target ) != Pmode || ! register_operand ( target , Pmode ) ) target = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_aarch64_load_tp_hard ( target ) ) ; return


<s> const uint32_t * RegMask = Subtarget . getRegisterInfo ( ) -> getCallPreservedMask ( * MF , CallingConv :: C ) ; if ( IsLP64 ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } if ( ! Is64Bit ) BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( TargetOpcode :: COPY ) , mallocPtrVReg ) . addReg ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; BB -> addSuccessor ( bumpMBB ) ; BB -> addSuccessor ( mallocMBB ) ; mallocMBB -> addSuccessor ( continueMBB ) ; bumpMBB -> addSuccessor ( continueMBB


<s> bool mep_expand_binary_intrinsic ( int ATTRIBUTE_UNUSED immediate , int ATTRIBUTE_UNUSED immediate3 , int

ATTRIBUTE_UNUSED reg , int ATTRIBUTE_UNUSED reg3 , rtx * operands ATTRIBUTE_UNUSED ) {


<s> static DecodeStatus decodeU2ImmOperand ( MCInst & Inst , uint64_t Imm

, uint64_t Address , const void * Decoder ) {


<s> if ( BaseShAmt && BaseShAmt . getOpcode ( ) == <STR_LIT> ) BaseShAmt = SDValue ( ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = dyn_cast < ShuffleVectorSDNode > ( Amt ) ; if ( SVN && SVN -> isSplat ( ) ) { unsigned SplatIdx = ( unsigned ) SVN -> getSplatIndex ( ) ; SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { assert ( ( SplatIdx < InVec . getValueType ( ) . getVectorNumElements ( ) ) && <STR_LIT> ) ; BaseShAmt = InVec . getOperand ( SplatIdx ) ; } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( ! BaseShAmt ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , InVec , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; } } if ( BaseShAmt . getNode ( ) ) { assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , DAG ) ; } } if ( ! Subtarget -> is64Bit ( ) && VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [

j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ;


<s> bool invert = InvertFPCondCode ( ( <STR_LIT> ) cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ) ; return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True .

getValueType ( ) , True , False , Cond ) ;


<s> return <NUM_LIT> ; } } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ( ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> ) || ST -> hasVectorEnhancements2 ( ) ) && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ; } else if ( const StoreInst * SI = dyn_cast < StoreInst > (


<s> static void register_sh_passes ( void ) { if ( ! TARGET_SH1 ) return ; register_pass ( make_pass_sh_treg_combine ( g , true , <STR_LIT> ) , PASS_POS_INSERT_AFTER , <STR_LIT> , <NUM_LIT> ) ; register_pass ( make_pass_sh_treg_combine ( g , true , <STR_LIT> ) , PASS_POS_INSERT_AFTER , <STR_LIT> , <NUM_LIT> ) ; register_pass ( make_pass_sh_optimize_sett_clrt ( g , <STR_LIT> )


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> >


<s> switch ( mode ) { case TFmode : real_to_target ( l , r , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; break ; case XFmode : real_to_target ( l , r , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; break ; case DFmode : REAL_VALUE_TO_TARGET_DOUBLE ( * r , l ) ; break ; default : gcc_unreachable ( ) ; } parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; } else gcc_unreachable ( ) ; } } else { if ( mode == TImode ) split_double_mode ( mode , & operand , <NUM_LIT> , & parts [ <NUM_LIT> ] , & parts [ <NUM_LIT> ] ) ; if ( mode == XFmode || mode == TFmode ) { machine_mode upper_mode = mode == XFmode ? SImode : DImode ; if ( REG_P ( operand ) ) { gcc_assert ( reload_completed ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operand ) + <NUM_LIT> ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( upper_mode , REGNO ( operand ) + <NUM_LIT> ) ; } else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , DImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; parts [ <NUM_LIT> ] = adjust_address ( operand , upper_mode , <NUM_LIT> ) ; } else if ( CONST_DOUBLE_P ( operand ) ) { long l [ <NUM_LIT> ] ; real_to_target ( l , CONST_DOUBLE_REAL_VALUE ( operand ) , mode ) ; parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) | ( ( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) << <NUM_LIT> ) , DImode ) ; if ( upper_mode == SImode ) parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; else parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) | ( ( l [ <NUM_LIT> ] & HOST_WIDE_INT_C ( <NUM_LIT> ) ) << <NUM_LIT> ) , DImode ) ; } else gcc_unreachable ( ) ; } } return


<s> return __builtin_mve_vrev32q_m_uv8hi ( __arm_vuninitializedq_u16 ( )


<s> Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Args [ ] = { I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) } ; CallInst * Call = Builder . CreateCall ( DSPInst , Args ) ; ReplaceAllUsersOfWith ( I , Call ) ; InstsToRemove . push_back ( I ) ; NewInsts . insert ( Call ) ; TruncTysMap [ Call ] = OrigTy ; } ; auto InsertZExt = [ & ] ( Value * V , Instruction * InsertPt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; Builder . SetInsertPoint ( InsertPt ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; auto * ZExt = cast < Instruction > ( Builder . CreateZExt ( V , ExtTy ) ) ; if ( isa < Argument > ( V ) ) ZExt -> moveBefore ( InsertPt ) ; else ZExt -> moveAfter ( InsertPt ) ; ReplaceAllUsersOfWith ( V , ZExt ) ; NewInsts . insert ( ZExt ) ; TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I


<s> break ; default : return true ; } return printAsmRegInClass ( MO , RC , <STR_LIT> , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; unsigned AltName = <STR_LIT> ; const TargetRegisterClass * RegClass ; if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else { RegClass = & <STR_LIT> ; AltName = <STR_LIT> ; } return printAsmRegInClass ( MO , RegClass , AltName


<s> struct mips_arg_info info ; mips_get_arg_info ( & info , cum , mode , type , named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < <NUM_LIT> && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? <NUM_LIT> : <NUM_LIT> ) << ( cum -> arg_number * <NUM_LIT> ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > <NUM_LIT> ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > <NUM_LIT> ) cum ->

stack_words = info . stack_offset + info . stack_words ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReductionToSVE ( unsigned Opcode , SDValue ScalarOp , SelectionDAG & DAG ) const { SDLoc DL ( ScalarOp ) ; SDValue VecOp = ScalarOp . getOperand ( <NUM_LIT> ) ; EVT SrcVT = VecOp . getValueType ( ) ; if ( useSVEForFixedLengthVectorVT ( SrcVT , Subtarget -> useSVEForFixedLengthVectors ( ) ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , SrcVT ) ; VecOp = convertToScalableVector ( DAG , ContainerVT , VecOp ) ; } EVT ResVT = ( Opcode == <STR_LIT> ) ? <STR_LIT> : SrcVT . getVectorElementType ( ) ; EVT RdxVT = SrcVT ; if ( SrcVT . isFixedLengthVector ( ) || Opcode == <STR_LIT> ) RdxVT = getPackedSVEVectorVT ( ResVT ) ; SDValue Pg = getPredicateForVector ( DAG


<s> } case <STR_LIT> : { EVT T = N -> getValueType ( <NUM_LIT> ) ; assert ( ( T == <STR_LIT> || T == <STR_LIT> ) && <STR_LIT> ) ; bool Regs64bit = T == <STR_LIT> ; EVT HalfT = Regs64bit ? <STR_LIT> : <STR_LIT> ; SDValue cpInL , cpInH ; cpInL = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; cpInH = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; cpInL = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , cpInL , SDValue ( ) ) ; cpInH = DAG . getCopyToReg ( cpInL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , cpInH , cpInL . getValue ( <NUM_LIT> ) ) ; SDValue swapInL , swapInH ; swapInL = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; swapInH = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , HalfT ) ) ; swapInL = DAG . getCopyToReg ( cpInH . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , swapInL , cpInH . getValue ( <NUM_LIT> ) ) ; swapInH = DAG . getCopyToReg ( swapInL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , swapInH , swapInL . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { swapInH . getValue ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , swapInH . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; unsigned Opcode = Regs64bit ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getMemIntrinsicNode ( Opcode , dl , Tys , Ops , <NUM_LIT> , T , MMO ) ; SDValue cpOutL = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , HalfT , Result . getValue ( <NUM_LIT> ) ) ; SDValue cpOutH = DAG . getCopyFromReg ( cpOutL . getValue ( <NUM_LIT> ) , dl , Regs64bit ? <STR_LIT> : <STR_LIT> , HalfT , cpOutL . getValue ( <NUM_LIT> ) ) ; SDValue OpsF [ ] = { cpOutL . getValue ( <NUM_LIT> ) , cpOutH . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , T , OpsF , <NUM_LIT> ) ) ; Results . push_back ( cpOutH . getValue ( <NUM_LIT> ) ) ; return ; } case <STR_LIT>


<s> assert ( Reg0 != Reg1 && <STR_LIT> ) ; if ( Reg0 < Reg1 ) return ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Reg0 >= Reg1 ) return ; } else llvm_unreachable ( <STR_LIT> )


<s> extern tree ix86_bf16_type_node ; if ( ! TARGET_SSE2 ) { gcc_checking_assert ( ! float16_type_node && ! bfloat16_type_node ) ; float16_type_node = ix86_float16_type_node ; bfloat16_type_node = ix86_bf16_type_node ; callback ( float16_type_node ) ; callback ( bfloat16_type_node ) ; float16_type_node = NULL_TREE ; bfloat16_type_node = NULL_TREE


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF


<s> if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; } else { if ( Subtarget -> useMovt ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV ,


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . isX32 ( )


<s> const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; if ( GV -> isDeclaration ( ) && ! S -> hasRepresentedCsectSet ( ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ; auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( S -> getSymbolTableName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; S -> setRepresentedCsect ( Sec ) ; } MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV ) ; } return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode >


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( VT == N0 . getValueType ( ) && ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( N0 . isUndef ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; unsigned ShiftVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( ! LogicalShift && <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( - <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == N0 . getOpcode ( ) ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NewShiftVal = ShiftVal + ShiftVal2 ; if ( NewShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op ,


<s> if ( simple_sets_p && ( aarch64_tune_params -> fuseable_ops & AARCH64_FUSE_MOVK_MOVK ) ) { if ( GET_CODE ( SET_DEST ( prev_set ) ) == ZERO_EXTRACT && GET_CODE ( SET_DEST ( curr_set ) ) == ZERO_EXTRACT && REG_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && REG_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == REGNO ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) == <NUM_LIT> && CONST_INT_P ( SET_SRC ( prev_set ) ) && CONST_INT_P ( SET_SRC ( curr_set ) ) ) return true ; } if ( simple_sets_p && ( aarch64_tune_params -> fuseable_ops & AARCH64_FUSE_ADRP_LDR ) ) { if ( satisfies_constraint_Ush ( SET_SRC ( prev_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && REG_P ( SET_DEST ( curr_set ) ) ) { rtx curr_src = SET_SRC ( curr_set ) ; if ( GET_CODE ( curr_src ) == ZERO_EXTEND ) curr_src = XEXP ( curr_src , <NUM_LIT> ) ; if ( MEM_P ( curr_src ) && GET_CODE ( XEXP ( curr_src , <NUM_LIT> ) ) == LO_SUM && REG_P ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) && rtx_equal_p ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( SET_SRC ( prev_set ) , <NUM_LIT> ) ) ) return true ; } } if ( ( aarch64_tune_params -> fuseable_ops & AARCH64_FUSE_CMP_BRANCH ) && any_condjump_p


<s> else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return MIDDLE_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return HIGH_REGS ; else if ( regno == <NUM_LIT> ) return R15_TA_REG ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return MIDDLE_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return HIGH_REGS ; else if ( regno == <NUM_LIT> || regno == <NUM_LIT> ) { return GENERAL_REGS ; } else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return FP_REGS ; else return NO_REGS


<s> for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; Changed =


<s> return ( __m128i ) __builtin_ia32_pmulhrsw128_mask ( ( __v8hi ) __X , ( __v8hi ) __Y , (

__v8hi ) _mm_setzero_hi ( ) , ( __mmask8 ) __U ) ;


<s> rtx r1 , r3 , r5 , r7 ; switch ( mode ) { case DFmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 ) ) ; case DCmode : case TFmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno +


<s> Instruction * OffsetSExt = dyn_cast < SExtInst > ( Offset -> user_back ( ) ) ; assert ( ( BaseSExt && OffsetSExt ) && <STR_LIT> ) ; std :: function < void ( Value * , Value * ) > MoveBefore = [ & ] ( Value * A , Value * B ) -> void { if ( ! isa < Instruction > ( A ) || ! isa < Instruction > ( B ) ) return ; auto * Source = cast < Instruction > ( A ) ; auto * Sink = cast < Instruction > ( B ) ; if ( DT -> dominates ( Source , Sink ) || Source -> getParent ( ) != Sink -> getParent ( ) || isa < PHINode > ( Source ) || isa < PHINode > ( Sink ) ) return ; Source -> moveBefore ( Sink ) ; for ( auto & U : Source -> uses ( ) ) MoveBefore ( Source , U . getUser ( ) ) ; } ; LoadInst * DomLoad = DT -> dominates ( Base ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setManipulatesSP


<s> MachineBasicBlock :: const_reverse_iterator It = MI ; MachineBasicBlock :: const_reverse_iterator E = MI . getParent ( ) -> rend ( ) ; It ++ ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It )


<s> static bool classof ( const <ISA_LIT>MCExpr * ) { return true


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; return


<s> return const_cast < <ISA_LIT>TargetLowering * > (


<s> } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; MaxAlign = std :: max ( Align , MaxAlign ) ; } if ( MFI -> adjustsStack ( ) && TFI -> hasReservedCallFrame ( MF ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( MF ) && MFI -> getObjectIndexEnd ( ) != <NUM_LIT> ) ) StackAlign = TFI -> getStackAlignment ( ) ; else StackAlign = TFI -> getTransientStackAlignment ( ) ; StackAlign = std :: max ( StackAlign , MaxAlign ) ; unsigned AlignMask = StackAlign - <NUM_LIT> ; Offset = ( Offset + AlignMask )


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Regs [ <NUM_LIT> ] ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = OrigArgs . empty ( ) ? true : OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( OrigRet . Regs . size ( ) > <NUM_LIT> ) return false ; SplitArgs . clear ( ) ; SmallVector < Register , <NUM_LIT> > NewRegs ; if ( ! splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { NewRegs . assign ( Regs . begin ( ) , Regs . end ( ) ) ; } ) ) return false ; CallReturnHandler Handler ( MIRBuilder , MRI , RetCC_<ISA_LIT> , MIB ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! NewRegs . empty ( ) ) MIRBuilder . buildMerge ( OrigRet . Regs [ <NUM_LIT>


<s> bool DoShift = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; printMemExtendImpl ( SignExtend , DoShift , Width , SrcRegKind , O


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( )


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; unsigned LowGPR = <NUM_LIT> ; int LowOffset = INT32_MAX ; unsigned HighGPR = LowGPR ; int HighOffset = - <NUM_LIT> ; unsigned RegSP = Regs . getStackPointerRegister ( ) ; auto & GRRegClass = <STR_LIT> ; const unsigned RegSize = <NUM_LIT> ; auto ProcessCSI = [ & ] ( std :: vector < CalleeSavedInfo > & CSIList ) { for ( auto & CS : CSIList ) { unsigned Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= <NUM_LIT> ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ; CS . setFrameIdx


<s> unsigned Opc = <NUM_LIT> ; switch ( Orig -> getOpcode ( ) ) { default : break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) ; Emitted = true ; } break ; } } if ( ! Emitted ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } if ( ChangeSubIdx


<s> ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair << MachineMemOperand


<s> return ( uint64_t ( <NUM_LIT> ) << Count )


<s> regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner ,


<s> const unsigned char JMP64r = <NUM_LIT> ; const unsigned char MOV64ri = <NUM_LIT> ; const unsigned char N86R10 = TRI -> getEncodingValue ( <STR_LIT> ) & <NUM_LIT> ; const unsigned char N86R11 = TRI -> getEncodingValue ( <STR_LIT> ) & <NUM_LIT> ; const unsigned char REX_WB = <NUM_LIT> | <NUM_LIT> | <NUM_LIT> ; unsigned OpCode = ( ( MOV64ri | N86R11 ) << <NUM_LIT> ) | REX_WB ; SDValue Addr = Trmp ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , FPtr , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( ( MOV64ri | N86R10 ) << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( JMP64r << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; unsigned char ModRM = N86R11 | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( ModRM , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; } else { const Function * Func = cast < Function > ( cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT>


<s> <ISA_LIT>ELFStreamer * S = static_cast < <ISA_LIT>ELFStreamer * > (


<s> SDValue <ISA_LIT>TargetLowering :: LowerVSCALE ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; assert ( VT != <STR_LIT> &&


<s> static unsigned negativeOffsetOpcode ( unsigned opcode ) { switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SmallVector < const Value * , <NUM_LIT> > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } unsigned UnrollCount = <NUM_LIT> ; if ( ST -> isThumb1Only ( ) ) { unsigned ExitingValues = <NUM_LIT> ; SmallVector < BasicBlock * , <NUM_LIT> > ExitBlocks ; L -> getExitBlocks ( ExitBlocks ) ; for ( auto * Exit : ExitBlocks ) { unsigned LiveOuts = count_if ( Exit -> phis ( ) , [ ] ( auto & PH ) { return PH . getNumOperands ( ) != <NUM_LIT> || ! isa < GetElementPtrInst > ( PH . getOperand ( <NUM_LIT> ) ) ; } ) ; ExitingValues = ExitingValues < LiveOuts ? LiveOuts : ExitingValues ; } if ( ExitingValues ) UnrollCount /= ExitingValues ; if ( UnrollCount <= <NUM_LIT> ) return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UnrollCount << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = UnrollCount ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold = <NUM_LIT> ; if ( Cost < <NUM_LIT> ) UP


<s> assert ( isImm ( ) && <STR_LIT> ) ; return Imm . Value


<s> Inst . addOperand ( MCOperand :: createReg ( FPR32DecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2siv8qi ( ( int8x8_t


<s> case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } default : bool IsIntrinOpcode ; if ( isFMA3 ( MI . getOpcode ( ) , IsIntrinOpcode ) ) return findFMA3CommutedOpIndices

( MI , IsIntrinOpcode , SrcOpIdx1 , SrcOpIdx2 ) ;


<s> if ( ! ( I -> isBranch ( ) ) && ! ( I -> mayLoad ( ) ) && ! ( I -> mayStore ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { MachineInstr * slaveinst1 = MF . CloneMachineInstr ( & * I ) ; MachineInstr * slaveinst2 = MF . CloneMachineInstr ( & * I ) ; slaveinst1 -> setFlags ( <NUM_LIT> ) ; slaveinst2 -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { if ( I -> getOperand ( opcount ) . isReg ( ) ) { slaveinst1 -> getOperand ( opcount ) . setReg ( getSlaveReg1 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; slaveinst2 -> getOperand ( opcount ) . setReg ( getSlaveReg2 ( I


<s> OS << <STR_LIT> ; break ; case CEK_GOT_CALL : OS << <STR_LIT> ; break ; case CEK_GOT_DISP : OS << <STR_LIT> ; break ; case CEK_GOT_HI16 : OS << <STR_LIT> ; break ; case CEK_GOT_LO16 : OS << <STR_LIT> ; break ; case CEK_GPREL : OS << <STR_LIT> ; break ; case CEK_ABS_HI : OS << <STR_LIT> ; break ; case CEK_ABS_LO : OS << <STR_LIT> ; break ; case CEK_TLSLDM : OS << <STR_LIT> ; break ; case CEK_TP_HI : OS << <STR_LIT> ; break ; case CEK_TP_LO : OS << <STR_LIT> ; break ; } OS << '(' ; if ( Expr -> evaluateAsAbsolute ( AbsVal ) ) OS << AbsVal ; else Expr -> print ( OS , MAI


<s> rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return NULL_RTX ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return NULL_RTX ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; pat = GEN_FCN ( icode ) ( op0 ,


<s> unsigned IID = getIntrinsicID ( N1 . getNode ( ) ) ; if ( IID == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> || IID == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> ) return N0 . getOpcode ( ) != <STR_LIT> ; return true


<s> MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; const DebugLoc & DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; const MachineOperand & PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case <STR_LIT> : case <STR_LIT> : { Register Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> slowTwoMemOps ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush


<s> if ( insn && CALL_P ( insn ) ) { fputs ( <STR_LIT> , file ) ; extra_nop = true ; } else extra_nop = false ; fputs ( <STR_LIT> , file ) ; if ( TARGET_SOM && TARGET_GAS ) { in_section = NULL ; cfun -> machine -> in_nsubspa = <NUM_LIT> ; } if ( cfun -> is_thunk ) return ; if ( INSN_ADDRESSES_SET_P ( ) ) { last_address = extra_nop ? <NUM_LIT> : <NUM_LIT> ; insn = get_last_nonnote_insn ( ) ; if ( insn ) { last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; } last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) ) ; } else last_address =


<s> bool isVectorIndexH ( ) const { return Kind == k_VectorIndex && VectorIndex .


<s> enum { COFF = ( <NUM_LIT> << MCObjectFileInfo :: IsCOFF ) , ELF = ( <NUM_LIT> << MCObjectFileInfo :: IsELF ) , MACHO = ( <NUM_LIT> << MCObjectFileInfo :: IsMachO ) , WASM = ( <NUM_LIT> << MCObjectFileInfo :: IsWasm ) , } ; static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } uint8_t CurrentFormat ; switch ( getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ) { case MCObjectFileInfo :: IsMachO : CurrentFormat = MACHO ; break ; case MCObjectFileInfo :: IsELF : CurrentFormat = ELF ; break ; case MCObjectFileInfo :: IsCOFF : CurrentFormat = COFF ; break ; case MCObjectFileInfo :: IsWasm : CurrentFormat = WASM ; break ; case MCObjectFileInfo :: IsXCOFF : llvm_unreachable ( <STR_LIT> ) ; break ; } if ( ~ Prefix -> SupportedFormats & CurrentFormat


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ; return false


<s> inline static CondCode getInvertedCondCode ( CondCode Code


<s> } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT &&

( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ;


<s> virtual MVT getShiftAmountTy ( EVT LHSTy


<s> static const char * const suffix [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( flags & SECTION_EXCLUDE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_DEBUG ) { fprintf ( asm_out_file , <STR_LIT> , name ) ; return ; } else if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_TLS ) { if ( flags & SECTION_BSS ) smclass = <NUM_LIT> ; else smclass = <NUM_LIT> ; } else if ( flags &


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator


<s> SDValue FPSCR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return TFI -> hasFP ( MF )


<s> static bool isExtendedBUILD_VECTOR ( SDNode * N , SelectionDAG & DAG , bool isSigned ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ; ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ; if ( ! Lo0 || ! Hi0 || ! Lo1


<s> unsigned postKnownBits ( unsigned LogAlign = <NUM_LIT> ) const { return std :: max ( std :: max ( unsigned ( PostAlign )

, LogAlign ) , internalKnownBits ( ) ) ;


<s> MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; MIB . addUse ( PhysReg , RegState ::


<s> if ( P . hasDSPR2 ( ) ) ASESet |= AFL_ASE_DSPR2 ; if ( P . hasMSA (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Instr . getOpcode ( ) ; ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB

, MachineBasicBlock :: iterator MBBI ) const {


<s> static SDValue LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG , const


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG

. getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CalleeCC ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallerCC ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( Outs . empty ( )


<s> static bool csky_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return csky_tls_referenced_p ( x


<s> if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , Vec -> op_begin ( ) + NormalizedIdxVal , ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , ResultVT , Vec ,


<s> switch ( IID ) { default : break ; case <STR_LIT> : case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>RegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) .

createVirtualRegister ( LP64 ? G8RC : GPRC ) ;


<s> if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant (


<s> printOperand ( MI , OpNo , O ) ; return false ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; case 'U' : case 'X' : assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false


<s> const BinaryOperator * BinOp = dyn_cast < BinaryOperator > ( Inst ) ; if ( BinOp && isa < OverflowingBinaryOperator > ( BinOp ) && ( BinOp -> hasNoUnsignedWrap ( ) || BinOp -> hasNoSignedWrap ( ) ) ) return true ; if ( isa < TruncInst > ( Inst ) && isa < SExtInst > ( Inst -> getOperand ( <NUM_LIT> ) ) ) { const Instruction * Opnd = cast < Instruction > ( Inst -> getOperand ( <NUM_LIT> ) ) ; if ( Inst -> getType ( ) -> getIntegerBitWidth ( ) >= Opnd -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getIntegerBitWidth ( ) && Inst -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getIntegerBitWidth ( ) <= ConsideredSExtType -> getIntegerBitWidth ( ) ) return true ; } return


<s> break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm =


<s> bool UseLoV1 = false , UseHiV1 = false , UseLoV2 = false , UseHiV2 = false ; SmallVector < int , <NUM_LIT> > V1BlendMask , V2BlendMask , BlendMask ; for ( int i = <NUM_LIT> ; i < SplitNumElements ; ++ i ) { int M = HalfMask [ i ] ; if ( M >= NumElements ) { if ( M >= NumElements + SplitNumElements ) UseHiV2 = true ; else UseLoV2 = true ; V2BlendMask . push_back ( M - NumElements ) ; V1BlendMask . push_back ( - <NUM_LIT> ) ; BlendMask . push_back ( SplitNumElements + i ) ; } else if ( M >= <NUM_LIT> ) { if ( M >= SplitNumElements ) UseHiV1 = true ; else UseLoV1 = true ; V2BlendMask . push_back ( - <NUM_LIT> ) ; V1BlendMask . push_back ( M ) ; BlendMask . push_back ( i ) ; } else { V2BlendMask . push_back ( - <NUM_LIT> ) ; V1BlendMask . push_back ( - <NUM_LIT> ) ; BlendMask . push_back ( - <NUM_LIT> ) ; } } if ( ! UseLoV1 && ! UseHiV1 && ! UseLoV2 && ! UseHiV2 ) return DAG . getUNDEF ( SplitVT ) ; if ( ! UseLoV2 && ! UseHiV2 ) return DAG . getVectorShuffle ( SplitVT , DL , LoV1 , HiV1 , V1BlendMask ) ; if ( ! UseLoV1 && ! UseHiV1 ) return DAG . getVectorShuffle ( SplitVT , DL , LoV2 , HiV2 , V2BlendMask ) ; SDValue V1Blend , V2Blend ; if ( UseLoV1 && UseHiV1 ) { V1Blend = DAG . getVectorShuffle ( SplitVT , DL , LoV1 , HiV1 , V1BlendMask ) ; } else { V1Blend = UseLoV1 ? LoV1 : HiV1


<s> break ; case E_DImode : cmp_mode = DImode ; icode = CODE_FOR_cmpdi ; break ; case E_SFmode : cmp_mode = SFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf ; break ; case E_DFmode : cmp_mode = DFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence (


<s> poly8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT>


<s> return ( int16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi


<s> case CallingConv :: SwiftTail : case CallingConv :: Tail : case CallingConv :: Fast : case CallingConv


<s> case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( StrOpc ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOStore ) ; return true


<s> unsigned char perm2 [ MAX_VECT_LEN ] ; unsigned i ; bool ok ; if ( d -> vmode != V8HImode || ! d -> one_operand_p ) return false ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] >= <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] < <NUM_LIT> ) return false ; if ( d -> testing_p ) return true ; memcpy ( perm2 , d -> perm , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> op0 , perm2 , <NUM_LIT> , d -> testing_p ) ; gcc_assert ( ok ) ; memcpy ( perm2 + <NUM_LIT> , d -> perm + <NUM_LIT> , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> target , perm2 , <NUM_LIT> ,


<s> if ( S1 && S2 && strcmp ( S1 , S2 ) == <NUM_LIT> ) return true ; return false


<s> static const uint16_t ScratchRegs [ ] =


<s> IRBuilder < > Builder ( L -> getLoopPreheader ( ) -> getTerminator ( ) ) ; Module * M = L -> getHeader ( ) -> getModule ( ) ; Type * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; unsigned VectorWidth = cast < FixedVectorType > ( ActiveLaneMask -> getType ( ) ) -> getNumElements ( ) ; Builder . SetInsertPoint ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( ActiveLaneMask -> getOperand ( <NUM_LIT> ) , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( ActiveLaneMask ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VectorWidth ) ; <STR_LIT> VCTPID ; switch ( VectorWidth ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * VCTPCall = Builder . CreateCall ( VCTP , Processed


<s> static SDValue combine<ISA_LIT>SetCC ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( )


<s> return ( CallerCC == CallingConv :: Fast || CallerCC == CallingConv


<s> unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode ,


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; <ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage


<s> bool isImmTLS ( ) const { return Kind ==


<s> return ( __m128i ) __builtin_ia32_vpcomgew ( ( __v8hi ) __A , (


<s> else if ( size > <NUM_LIT> ) loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; loongarch_emit_stack_tie ( ) ; } if ( size > <NUM_LIT>


<s> int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } return Error ( S , <STR_LIT> ) ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Identifier : case AsmToken :: Dot : case AsmToken :: Dollar : if ( ! getParser ( ) . parseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( EVal ) ) Op = <ISA_LIT>Operand :: CreateImm ( CE -> getValue ( ) , S , E , is<ISA_LIT>64 ( ) ) ; else Op = <ISA_LIT>Operand :: CreateExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; if ( MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) return Error ( S , <STR_LIT> ) ; Parser . Lex ( ) ; break ; case AsmToken :: Integer : if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) || IntVal <

<NUM_LIT> || IntVal > <NUM_LIT> ) return Error ( S , <STR_LIT> ) ;


<s> if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , <NUM_LIT> )

) == REGNO ( SET_DEST ( prev_set ) ) ) return true ;


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI

( TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ) {


<s> DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getThumbAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return MO . getImm


<s> void <ISA_LIT>InstPrinter :: printThumbLdrLabelOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; if ( MO1 . isExpr ( ) ) O << * MO1 . getExpr ( ) ; else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstLoad ( Opc , ResultReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; unsigned Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( FI

) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , SDLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ,


<s> return ia64_function_arg_1 ( cum , arg ,


<s> RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , CmpVT . getVectorElementType ( ) , RHS , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SetCC = DAG . getSetCC ( SDLoc ( N ) , <STR_LIT> , LHS , RHS , cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get


<s> const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg (


<s> else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; X -> initMCCodeGenInfo ( RM , CM


<s> initializeWinEHStatePassPass ( * PassRegistry :: getPassRegistry ( )


<s> break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer . AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer . PushSection ( ) ; const MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( M , nullptr ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbol * Stub = OutContext . GetOrCreateSymbol ( StringRef ( x ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer . EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer . EmitLabel ( Stub ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) llvm_unreachable ( <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( Signature -> ParamSig , LE , true ) ; EmitJal ( MSymbol ) ; EmitSwapFPIntRetval ( Signature -> RetSig , LE ) ; EmitInstrReg ( <STR_LIT> , <STR_LIT> ) ; MCSymbol * Tmp = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( Tmp ) ; const MCSymbolRefExpr * E = MCSymbolRefExpr :: Create ( Stub , OutContext ) ; const MCSymbolRefExpr * T = MCSymbolRefExpr :: Create ( Tmp , OutContext ) ; const MCExpr * T_min_E = MCBinaryExpr :: CreateSub ( T , E , OutContext ) ; OutStreamer . EmitELFSize ( Stub


<s> void <ISA_LIT>AsmPrinter :: emitFrameDirective ( MachineFunction & MF ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI .


<s> void <ISA_LIT>ELFDynamic :: applyTargetEntries ( const ELFFileFormat & pFormat ) { if ( pFormat . hasGOTPLT ( ) ) applyOne ( llvm :: ELF :: DT_PLTGOT

, pFormat . getGOTPLT ( ) . addr ( ) ) ;


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; } else { ++ Result ; } if ( ! Shift ) return Result ; if ( Imm ) ++ Result ; if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) ++ Result ; if ( ( Lo = Remainder & <NUM_LIT> ) ) ++ Result ; return Result


<s> if ( MO . isReg ( ) ) return get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI


<s> for ( auto & I : * Tail ) { if ( ! I . isPHI ( ) ) break ; for ( unsigned oi = I . getNumOperands ( ) ; oi > <NUM_LIT> ; oi -= <NUM_LIT> ) { if ( I . getOperand ( oi - <NUM_LIT> ) . getMBB ( ) == CmpBB ) { I . removeOperand ( oi - <NUM_LIT> ) ; I . removeOperand ( oi


<s> static std :: unique_ptr < <ISA_LIT>Operand > createFGRReg ( unsigned Index , StringRef Str , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , Str , RegKind_FGR , RegInfo


<s> return __builtin_ia32_vcvttph2qq512_mask_round ( __A , _mm512_setzero_si512 ( ) , ( __mmask8


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ) return false ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) return false ; return true


<s> void emitARM64WinCFISetFP ( ) override { OS <<


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( isByVal ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> ,


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Neg , DAG . getConstant ( <STR_LIT>

, DL , <STR_LIT> ) , Cmp . getValue ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; } CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB =


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns

, C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ;


<s> unsigned ArgSizeInBytes = TD . getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( alignTo ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL , VAList . getValueType ( ) ) ) ; Chain = DAG . getStore ( VAListLoad . getValue ( <NUM_LIT> ) , DL , Tmp3 , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; if ( ! Subtarget . isLittle ( ) && ArgSizeInBytes < ArgSlotSizeInBytes ) { unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes ; VAList = DAG . getNode ( <STR_LIT> , DL , VAListPtr . getValueType ( ) , VAList

, DAG . getIntPtrConstant ( Adjustment , DL ) ) ;


<s> if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind -


<s> return ( __mmask16 ) __builtin_ia32_ucmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ; } else { SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; SDValue CS1 = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , CC1Val , Cmp ) ; SDValue CC2Val = DAG . getConstant ( CC2 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TVal , CS1 ,


<s> int64_t ImmVal = Imm ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> )

) Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ;


<s> if ( rs6000_vector_unit [ m ] != VECTOR_NONE || rs6000_vector_mem [ m ] != VECTOR_NONE || ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) || ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) || reg_addr [ m ] . scalar_in_vmx_p ) { fprintf ( stderr , <STR_LIT> , rs6000_debug_vector_unit ( rs6000_vector_unit [ m ] ) , rs6000_debug_vector_unit ( rs6000_vector_mem [ m ] ) , ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) ? 's' : '*' , ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ? 'l' : '*' , ( reg_addr [ m