<s> <ISA_LIT>ELFFrameLowering :: <ISA_LIT>ELFFrameLowering ( ) : <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align

( <NUM_LIT> ) , false ) , RegSpillOffsets ( <NUM_LIT> ) {


<s> for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ )


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { return LowerStore128 ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerF128Call ( SDValue Op , SelectionDAG & DAG , RTLIB :: Libcall Call ) const { SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , Call , <STR_LIT> , Ops , CallOptions


<s> DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; int br_code ; SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG , br_code ) ; EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT>


<s> case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A


<s> return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBITCASTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine (


<s> default : break ; case <STR_LIT> : return PerformADDECombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformUMLALCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformAddcSubcCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddeSubeCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( vector unsigned int ) __builtin_altivec_vspltisw


<s> if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && ( NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION || NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION


<s> emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , <NUM_LIT> ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , <NUM_LIT> ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp ,


<s> SDLoc dl ( N ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , Op -> getOperand ( <NUM_LIT> ) . getValueType (


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Bits = getBinaryCodeForInstr ( MI


<s> assert ( MBBI != Entry -> end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; bool RemovedAllMTVRSAVEs = true ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &= FoundIt


<s> SDLoc DL ( Op ) ; SDVTList VTs = DAG . getVTList ( VT0 , VT1 ) ; SDValue Sum = DAG . getNode ( Opcode , DL , DAG . getVTList ( VT0 , <STR_LIT> ) , OpLHS , OpRHS , OpCarryIn ) ; SDValue OutFlag = IsSigned ? overflowFlagToValue ( Sum . getValue ( <NUM_LIT> ) , VT1 , DAG ) : carryFlagToValue ( Sum . getValue ( <NUM_LIT> ) ,


<s> static const char * GetArchDefaultCPUName ( unsigned ID ) { switch (


<s> if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode ==

V4HImode ) || ( mode == V2SImode ) ) ) return true ;


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB


<s> emitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols


<s> if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger


<s> while ( Len ) { MVT VT ; if ( Len >= <NUM_LIT> && i64Legal ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else VT = <STR_LIT> ; unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , nullptr , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , DestAM ) ; assert ( RV && <STR_LIT> ) ; ( void ) RV ; unsigned Size = VT . getSizeInBits ( )


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_extract_pi16 ( __m64 const __A , int const __N ) { const int shiftr = ( __N & <NUM_LIT> ) * <NUM_LIT> ; return ( ( __A >> shiftr ) &


<s> SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SplatVal ) ; case <STR_LIT> : { SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case


<s> unsigned EltsPerReg = ( IsDarwinILP32 && LocVT . SimpleTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned RegResult = State . AllocateRegBlock ( RegList , alignTo ( PendingMembers . size ( ) , EltsPerReg ) / EltsPerReg ) ; if ( RegResult && EltsPerReg == <NUM_LIT> ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } else if ( RegResult ) { assert ( EltsPerReg == <NUM_LIT> && <STR_LIT> ) ; bool UseHigh = false ; CCValAssign :: LocInfo Info ; for ( auto & It : PendingMembers ) { Info = UseHigh ? CCValAssign :: AExtUpper : CCValAssign :: ZExt ; State . addLoc ( CCValAssign :: getReg ( It . getValNo ( ) , <STR_LIT> , RegResult , <STR_LIT> , Info ) ) ; UseHigh = ! UseHigh ; if ( ! UseHigh ) ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } if ( LocVT . isScalableVector ( ) )


<s> addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; addPass ( create<ISA_LIT>LowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass (


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI (


<s> assert ( Mask . empty ( ) && <STR_LIT> ) ; int NumElts = VT . getVectorNumElements ( ) ; int NumEltsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned LaneStart = ( i / NumEltsInLane ) * NumEltsInLane ; int Pos = ( i % NumEltsInLane ) /


<s> MachineBasicBlock * FBB = nullptr ; <STR_LIT> CondCode ; if ( ! endsWithCondControlFlow ( MBB , TBB , FBB , CondCode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { <STR_LIT> InvCondCode = <STR_LIT> ( CondCode ) ; MachineBasicBlock * SplitEdgeTBB = MBB . SplitCriticalEdge ( TBB , * this ) ; MachineBasicBlock * SplitEdgeFBB = MBB . SplitCriticalEdge ( FBB , * this ) ; assert ( SplitEdgeTBB != nullptr ) ; assert ( SplitEdgeFBB != nullptr ) ; DebugLoc DL ; if ( MBB . instr_end ( ) != MBB . instr_begin ( ) ) DL = ( -- MBB . instr_end ( ) ) -> getDebugLoc ( ) ; insertTrackingCode ( * SplitEdgeTBB , CondCode , DL ) ; insertTrackingCode ( * SplitEdgeFBB , InvCondCode , DL ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeTBB << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeFBB << <STR_LIT> ) ; Modified = true ; } SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > ReturnInstructions ; SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > CallInstructions ; bool TmpRegisterNotAvailableEverywhere = false ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; I ++ ) { MachineInstr & MI = * I ; if ( ! MI . isReturn ( ) && ! MI . isCall ( ) ) continue ; if ( I != MBB . begin ( ) ) RS . forward ( std :: prev ( I ) ) ; unsigned TmpReg = RS . FindUnusedReg ( & <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ( TmpReg == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( TmpReg != <NUM_LIT> ) dbgs ( ) << printReg ( TmpReg , TRI ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MI ) ; if ( TmpReg == <NUM_LIT> ) TmpRegisterNotAvailableEverywhere = true ; if ( MI . isReturn ( ) ) ReturnInstructions . push_back ( { & MI , TmpReg } ) ; else if ( MI . isCall ( ) ) CallInstructions . push_back ( { & MI , TmpReg } ) ; } if ( TmpRegisterNotAvailableEverywhere ) { insertFullSpeculationBarrier ( MBB , MBB . begin ( ) , ( MBB . begin ( ) ) -> getDebugLoc ( ) ) ; UsesFullSpeculationBarrier = true ; Modified = true ; } else { for ( auto MI_Reg : ReturnInstructions ) { assert ( MI_Reg . second != <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MI_Reg . second , TRI ) << <STR_LIT> << * MI_Reg . first ) ; insertRegToSPTaintPropagation ( MBB , MI_Reg . first , MI_Reg . second ) ; Modified = true ; } for ( auto MI_Reg : CallInstructions )


<s> rtx_insn * load = <NUM_LIT> , * store = <NUM_LIT> ; bool fed_by_load = <NUM_LIT> ; bool feeds_store = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { link = DF_REF_CHAIN ( use ) ; load = DF_REF_INSN ( link -> ref ) ; if ( insn_is_load_p ( load ) && insn_is_swap_p ( load ) ) fed_by_load = <NUM_LIT> ; } FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { link = DF_REF_CHAIN ( def ) ; store = DF_REF_INSN ( link -> ref ) ; if ( insn_is_store_p ( store ) && insn_is_swap_p ( store ) ) feeds_store = <NUM_LIT> ; } return fed_by_load && feeds_store


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> if ( ! BigStack ) return ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; MCPhysReg ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) { ExtraReg = CSRegs [ i ] ; break ; } } if ( ExtraReg != <NUM_LIT> ) { MF . getRegInfo ( ) . setPhysRegUsed (


<s> SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl , <STR_LIT> ) ) ; SDValue EXT = DAG . getNode ( <STR_LIT> , dl


<s> else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else llvm_unreachable ( <STR_LIT> )


<s> EmitAlignment ( MF . getAlignment ( ) , F ) ; O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true


<s> void <ISA_LIT>LongBranch :: replaceBranch ( MachineBasicBlock & MBB , Iter Br , DebugLoc DL , MachineBasicBlock * MBBOpnd ) { unsigned NewOpc = TII -> GetOppositeBranchOpc ( Br -> getOpcode ( ) ) ; const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB


<s> return true ; } MachineInstr * Prev = VCTPs . back ( ) ; if ( ! Prev -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( MI -> getOperand ( <NUM_LIT> ) ) || ! RDA . hasSameReachingDef ( Prev , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } VCTPs . push_back ( MI ) ; return


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveNext (


<s> SmallVector < std :: pair < unsigned , std :: string > , <NUM_LIT> > MapAndConstraints ; unsigned MatchResult = MatchInstructionImpl ( Operands , Kind , Inst , MapAndConstraints , ErrorInfo , false ) ; switch ( MatchResult ) { default : break ; case Match_Success : { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> )


<s> const aarch_branch_protect_type * subtype = type -> subtypes ; while ( str && subtype && subtype -> name && ! found_subtype && res == AARCH_PARSE_OK ) { if ( strcmp ( str , subtype -> name ) == <NUM_LIT> ) { found_subtype = true ; res = subtype -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , <STR_LIT> , & token_save ) ; } else subtype ++ ; } } } else if ( ! found ) res = AARCH_PARSE_INVALID_ARG ; } } if ( last_str ) { if ( str ) strcpy ( * last_str , str ) ; else * last_str = NULL ; } if ( res == AARCH_PARSE_OK ) { if ( ! accepted_branch_protection_string ) accepted_branch_protection_string = ( char * ) xmalloc ( BRANCH_PROTECT_STR_MAX + <NUM_LIT> ) ; strncpy ( accepted_branch_protection_string , const_str , BRANCH_PROTECT_STR_MAX + <NUM_LIT> ) ; accepted_branch_protection_string [ BRANCH_PROTECT_STR_MAX ] =


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint ; if ( isa < Instruction > ( OffsSecondOperand ) ) InsertionPoint = & cast < Instruction > ( OffsSecondOperand ) -> getParent ( ) -> back ( ) ; else InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( Instruction :: Mul , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand ,


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) { Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) <<


<s> struct machine_function * m = cfun -> machine ; unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( word_mode , regno ) ; rtx insn , mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( word_mode , mem ) ; insn = emit_move_insn ( reg , mem ) ; if ( m -> fs . cfa_reg == crtl -> drap_reg && regno ==


<s> if ( Const -> getAPInt ( ) != - VF -> getValue ( ) ) return nullptr ; } else return nullptr ; return dyn_cast < SCEVMulExpr > ( S -> getOperand ( <NUM_LIT> ) ) ; } ; auto VisitMul = [ & ] ( const SCEVMulExpr * S ) -> const SCEVUDivExpr * { if ( auto * Const = dyn_cast < SCEVConstant > ( S -> getOperand ( <NUM_LIT> ) ) ) { if ( Const -> getValue ( ) != VF ) return nullptr ; } else return nullptr ; return dyn_cast < SCEVUDivExpr > ( S -> getOperand ( <NUM_LIT> ) ) ; } ; auto VisitDiv = [ & ] ( const SCEVUDivExpr * S ) -> const SCEV * { if ( auto * Const = dyn_cast < SCEVConstant > ( S -> getRHS ( ) ) ) { if ( Const -> getValue ( ) != VF ) return nullptr ; } else return nullptr ; if ( auto * RoundUp = dyn_cast < SCEVAddExpr > ( S -> getLHS ( ) ) ) { if ( auto * Const = dyn_cast < SCEVConstant > ( RoundUp -> getOperand ( <NUM_LIT> ) ) ) { if ( Const -> getAPInt ( ) != ( VF -> getValue ( ) - <NUM_LIT> ) ) return nullptr ; } else return nullptr ; return RoundUp -> getOperand ( <NUM_LIT> ) ; } return nullptr ; } ; const SCEV * Elems = nullptr ; if ( auto * TC = dyn_cast < SCEVAddExpr > ( TripCountSE ) ) if ( auto * Div = dyn_cast < SCEVUDivExpr > ( TC -> getOperand ( <NUM_LIT> ) ) ) if ( auto * Add = dyn_cast < SCEVAddExpr > ( Div -> getLHS ( ) ) ) if ( auto * Mul = VisitAdd ( Add ) ) if ( auto * Div = VisitMul ( Mul ) ) if ( auto * Res = VisitDiv ( Div ) ) Elems = Res ; if ( ! Elems ) return false ; Instruction * InsertPt = L -> getLoopPreheader ( ) -> getTerminator ( ) ; if ( ! isSafeToExpandAt ( Elems , InsertPt , * SE ) ) return false ; auto DL = L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; SCEVExpander Expander ( * SE , DL , <STR_LIT> ) ; TCP . NumElements = Expander . expandCodeFor ( Elems , Elems -> getType ( ) , InsertPt ) ; if ( ! MatchElemCountLoopSetup ( L , TCP . Shuffle , TCP . NumElements ) )


<s> if ( optimize > <NUM_LIT> && selected_cpu -> tune -> max_case_values != <NUM_LIT> ) return

selected_cpu -> tune -> max_case_values ;


<s> } SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { SmallVector < std :: string ,


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>_64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_32Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_64Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_32Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>_32Target , create<ISA_LIT>MCRelocationInfo


<s> <STR_LIT> InstrType = GetInstrType ( Node -> getOpcode ( ) , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return NoHazard ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( NumIssued != <NUM_LIT> && ( isFirst || isSingle ) ) return Hazard ; if ( isCracked && NumIssued > <NUM_LIT> ) return Hazard ; switch ( InstrType ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( NumIssued == <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : if ( NumIssued >= <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : break ; } if ( HasCTRSet && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) return NoopHazard ; if ( isLoad && NumStores ) { unsigned LoadSize ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static inline void w32_error ( const char * function , const char * file , int line , const char * my_msg ) { LPSTR w32_msgbuf ; FormatMessageA ( FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS | FORMAT_MESSAGE_MAX_WIDTH_MASK , NULL , GetLastError ( ) , MAKELANGID ( LANG_NEUTRAL , SUBLANG_DEFAULT ) , ( LPSTR ) & w32_msgbuf , <NUM_LIT> , NULL ) ; fprintf ( stderr , <STR_LIT> , function , trim_filename ( file ) , line , my_msg , w32_msgbuf ) ; LocalFree ( ( HLOCAL ) w32_msgbuf


<s> if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I8 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I16 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I32 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I64 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I128 ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT>


<s> uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> ,


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant (

size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ;


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet )


<s> const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true


<s> static SDValue lowerV64I8Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2


<s> assert ( std :: is_sorted ( std :: begin ( Groups ) , std :: end ( Groups ) ) && std :: is_sorted ( std :: begin ( RoundGroups ) , std :: end ( RoundGroups ) ) &&

std :: is_sorted ( std :: begin ( BroadcastGroups ) , std :: end ( BroadcastGroups ) ) && <STR_LIT> ) ;


<s> static bool reg_dead_after_insn ( const_rtx reg , const_rtx insn


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal %


<s> Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder )


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) val .


<s> SDValue Tmp2 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp3 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Chain = Tmp1 . getOperand ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * DAG . getTarget ( ) . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI ,


<s> ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; return ret


<s> char * aarch64_output_sve_addvl_addpl ( rtx dest , rtx base , rtx offset ) { static char buffer [ sizeof ( <STR_LIT> ) + <NUM_LIT> * sizeof ( int ) ] ; poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( aarch64_sve_addvl_addpl_immediate_p ( offset_value ) ) ; if ( rtx_equal_p ( dest , base ) && GP_REGNUM_P ( REGNO ( dest ) ) ) { if ( aarch64_sve_cnt_immediate_p ( offset_value ) ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , <STR_LIT> , offset_value . coeffs [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( aarch64_sve_cnt_immediate_p ( - offset_value ) ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , <STR_LIT> , - offset_value . coeffs [


<s> return Len <= ( Subtarget -> is64Bit (


<s> SmallBitVector Undefs ( NumDstElts , false ) ; SmallVector < APInt , <NUM_LIT> > Vals ( NumDstElts , APInt ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumDstElts ; ++ i ) { SDValue OpElt = Op . getOperand ( i ) ; if ( OpElt . getOpcode ( ) == <STR_LIT> ) { Undefs [ i ] = true ; continue ; } APInt Cst = cast < ConstantSDNode > ( OpElt . getNode ( ) ) -> getAPIntValue ( ) ; Vals [ i ] = Opcode == <STR_LIT> ? Cst . zextOrTrunc ( SVT . getSizeInBits ( ) ) : Cst . sextOrTrunc ( SVT . getSizeInBits ( ) ) ; } return getConstVector ( Vals , Undefs , VT , DAG , DL ) ; } SDValue V = peekThroughBitcasts ( Op ) ; if ( Opcode == <STR_LIT> && V != Op && V . getOpcode ( ) == <STR_LIT> ) { MVT InnerVT = V . getSimpleValueType ( ) ; MVT InnerEltVT = InnerVT . getVectorElementType ( ) ; if ( OpEltVT == InnerEltVT ) { assert ( OpVT == InnerVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V . getOperand ( <NUM_LIT> ) ) ; } if ( InnerEltVT . getSizeInBits ( ) < InputBits ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( OpVT , V ) ) ; } if ( Opcode == <STR_LIT> && V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == InputBits ) { SDValue ExtractedV = V . getOperand ( <NUM_LIT> ) ; SDValue OrigV = ExtractedV . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( ExtractedV . getOperand ( <NUM_LIT> ) ) ) { MVT OrigVT = OrigV . getSimpleValueType ( ) ; if ( OrigVT . getSizeInBits ( ) > OpVT


<s> enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return <NUM_LIT> ; paired_emit_vector_compare ( rcode , dest , op1 ,


<s> tree arg0 , arg1 , arg2 ; tree rtype = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; if ( ignore && DECL_FUNCTION_CODE ( fndecl ) != CODE_FOR_alignaddrsi_vis && DECL_FUNCTION_CODE ( fndecl ) != CODE_FOR_alignaddrdi_vis ) return build_int_cst ( rtype , <NUM_LIT> ) ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case CODE_FOR_fexpand_vis : arg0 = TREE_VALUE ( arglist ) ; STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; tree elts = TREE_VECTOR_CST_ELTS ( arg0 ) ; tree n_elts = NULL_TREE ; for ( ; elts ; elts = TREE_CHAIN ( elts ) ) { unsigned int val = TREE_INT_CST_LOW ( TREE_VALUE ( elts ) ) << <NUM_LIT> ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } return build_vector ( rtype , nreverse ( n_elts ) ) ; } break ; case CODE_FOR_fmul8x16_vis : case CODE_FOR_fmul8x16au_vis : case CODE_FOR_fmul8x16al_vis : arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; tree elts0 = TREE_VECTOR_CST_ELTS ( arg0 ) ; tree elts1 = TREE_VECTOR_CST_ELTS ( arg1 ) ; tree n_elts = sparc_handle_vis_mul8x16 ( DECL_FUNCTION_CODE ( fndecl ) , inner_type , elts0 , elts1 ) ; return build_vector ( rtype , n_elts ) ; } break ; case CODE_FOR_fpmerge_vis : arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree elts0 = TREE_VECTOR_CST_ELTS ( arg0 ) ; tree elts1 = TREE_VECTOR_CST_ELTS ( arg1 ) ; tree n_elts = NULL_TREE ; for ( ; elts0 && elts1 ; elts0 = TREE_CHAIN ( elts0 ) , elts1 = TREE_CHAIN ( elts1 ) ) { n_elts = tree_cons ( NULL_TREE , TREE_VALUE ( elts0 ) , n_elts ) ; n_elts = tree_cons ( NULL_TREE , TREE_VALUE ( elts1 ) , n_elts ) ; } return build_vector ( rtype , nreverse ( n_elts ) ) ; } break ; case CODE_FOR_pdist_vis : arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST && TREE_CODE ( arg2 ) == INTEGER_CST ) { int overflow = <NUM_LIT> ; unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW ( arg2 ) ; HOST_WIDE_INT high = TREE_INT_CST_HIGH ( arg2 ) ; tree elts0 = TREE_VECTOR_CST_ELTS ( arg0 ) ; tree elts1 = TREE_VECTOR_CST_ELTS (


<s> <ISA_LIT>Relocator :: Result unsupported ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { return Relocator


<s> int Iterations = <ISA_LIT>SubTarget . hasRecipPrec ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( VT . getScalarType ( ) == <STR_LIT> ) ++ Iterations ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( Op ) ; SDValue FPOne = DAG . getConstantFP ( <NUM_LIT> , VT . getScalarType ( ) ) ; if ( VT . isVector ( ) ) { assert ( VT . getVectorNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; FPOne = DAG . getNode ( <STR_LIT> , dl , VT , FPOne , FPOne , FPOne , FPOne ) ; } SDValue Est = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ; for ( int i = <NUM_LIT> ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this ,


<s> SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0 ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck2 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; int ShufMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Sub ,

DAG . getUNDEF ( <STR_LIT> ) , ShufMask ) ;


<s> void changeRecordedTypeForInstr ( const MachineInstr * MI , InstType InstTy ) { assert ( wasVisited ( MI ) && <STR_LIT> ) ; Types . find ( MI ) ->


<s> if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { return <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ; } } return <STR_LIT> ( Disp , Start , End ) ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( )


<s> static bool loongarch_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp


<s> inline vector signed char vec_splat_s8 ( const char a1


<s> void processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { switch ( ( <STR_LIT> ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary


<s> case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , static_cast < EVT > ( <STR_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return DAG . getBitcast ( VT , CallInfo .


<s> uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; Register SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF ) ) { NewSP = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , OldSP , NeededSpace ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; } else { NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; } SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result


<s> if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr (


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! <STR_LIT> ( V1 ) && ! isScalarLoadToVector ( V1 ) ) return false ; if ( <STR_LIT> ( V2 ) || WillBeConstantPoolLoad ( V2 ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual (

Op -> getMaskElt ( i ) , i + NumElems ) ) return false ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lzcnt64 ( unsigned


<s> else FullFS = <STR_LIT> ; } if ( OL >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OL != CodeGenOpt :: None ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT>


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op


<s> if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= <NUM_LIT> << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % <NUM_LIT> ) != <NUM_LIT> ) { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( ( save_reg_mask & ( <NUM_LIT> << reg ) ) == <NUM_LIT> ) break ; if ( reg <= <NUM_LIT> ) save_reg_mask |= ( <NUM_LIT> << reg ) ; else { cfun -> machine -> sibcall_blocked = <NUM_LIT> ; save_reg_mask |= ( <NUM_LIT> << <NUM_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( RV ) ) { CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( CI , <STR_LIT> , VA . getLocInfo ( ) == CCValAssign :: SExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode

:: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ;


<s> inline tree tuple_type_field ( tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field )


<s> <ISA_LIT>PostRASchedStrategy :: ~ <ISA_LIT>PostRASchedStrategy ( ) { for ( auto I


<s> static unsigned adjustFixupValue ( const MCFixup & Fixup , uint64_t Value , MCContext * Ctx = nullptr ) { unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { default : return <NUM_LIT> ; case FK_Data_2 : case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> t = build2 ( PLUS_EXPR , TREE_TYPE ( off ) , off , build_int_cst ( TREE_TYPE ( off ) , <NUM_LIT> ) ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( off ) , t , build_int_cst ( TREE_TYPE ( off ) , - <NUM_LIT> ) ) ; roundup = build2 ( MODIFY_EXPR , TREE_TYPE ( off ) , off , t ) ; } else roundup = NULL ; t = build2 ( PLUS_EXPR , TREE_TYPE ( off ) , off , build_int_cst ( TREE_TYPE ( off ) , rsize ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( f_off ) , unshare_expr ( f_off ) , t ) ; if ( roundup ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , roundup , t ) ; u = build2 ( GT_EXPR , boolean_type_node , unshare_expr ( f_off ) , build_int_cst ( TREE_TYPE ( f_off ) , <NUM_LIT> ) ) ; cond2 = build3 ( COND_EXPR , ptr_type_node , u , NULL_TREE , NULL_TREE ) ; t = build2 ( COMPOUND_EXPR , TREE_TYPE ( cond2 ) , t , cond2 ) ; COND_EXPR_ELSE ( cond1 ) = t ; arg = get_initialized_tmp_var ( stack , pre_p , NULL ) ; if ( align > <NUM_LIT> ) { t = fold_build_pointer_plus_hwi ( arg , <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> ) ) ; roundup = build2 ( MODIFY_EXPR , TREE_TYPE ( arg ) , arg , t ) ; } else roundup = NULL ; t = fold_build_pointer_plus_hwi ( arg , size + <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , unshare_expr ( stack ) , t ) ; if ( roundup ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , roundup , t ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , t , arg ) ; if ( BLOCK_REG_PADDING ( mode , type , <NUM_LIT> ) == PAD_DOWNWARD && size < UNITS_PER_WORD ) { t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( arg ) , arg , size_int ( UNITS_PER_WORD - size ) ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , on_stack , t ) ; } COND_EXPR_THEN ( cond1 ) = unshare_expr ( on_stack ) ; COND_EXPR_THEN ( cond2 ) =


<s> int32_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MF . getFrameInfo ( ) -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) &&


<s> uint64_t getStackSizeSVE ( ) const { return StackSizeSVE


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReferencePreferSP ( const MachineFunction & MF , int FI , Register & FrameReg , bool IgnoreSPUpdates ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( IgnoreSPUpdates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg = <STR_LIT> ; return MFI . getObjectOffset ( FI


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { return <STR_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getBoolVecToIntConversionCost ( unsigned Opcode , Type * Dst , const Instruction * I ) { assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = cast < VectorType > ( Dst ) -> getNumElements ( ) ; unsigned Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = DPairSpacedDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( rtx shifts = aarch64_convert_mult_to_shift ( operands [ <NUM_LIT> ] , code ) ) { rtx product = expand_binop ( mode , vashl_optab , operands [ <NUM_LIT> ] , shifts , NULL_RTX , true , OPTAB_DIRECT ) ; force_expand_binop ( mode , code == PLUS ? add_optab : sub_optab , operands [ <NUM_LIT> ] , product , operands [ <NUM_LIT> ] , true , OPTAB_DIRECT ) ; return true ; } operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; return false


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg ,


<s> NodeTys . push_back ( <STR_LIT> ) ; unsigned CallOpc = isSVR4ABI ? <STR_LIT> : <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , Callee . getValueType ( ) ) ; else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) ) ; else if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) Callee = SDValue ( Dest , <NUM_LIT> ) ; else { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = isSVR4ABI ? <STR_LIT> : <STR_LIT> ; Callee . setNode ( <NUM_LIT> ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; } if ( Callee . getNode ( ) ) { Ops . push_back ( Chain ) ; Ops . push_back ( Callee


<s> basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple * stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = loop_vinfo -> lookup_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs ) ; density_pct = ( vec_cost * <NUM_LIT> ) /


<s> MovZ -> getOperand ( <NUM_LIT> ) . setTargetFlags ( OpFlags | <STR_LIT> | <STR_LIT> ) ; MovZ -> addOperand ( MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; constrainSelectedInstRegOperands ( * MovZ , TII , TRI , RBI ) ; auto BuildMovK = [ & ] ( unsigned SrcReg , unsigned char Flags , unsigned Offset , unsigned ForceDstReg ) { unsigned DstReg = ForceDstReg ? ForceDstReg : MRI . createVirtualRegister ( & <STR_LIT> ) ; auto MovI = MIB . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( SrcReg ) ; if ( auto * GV = dyn_cast < GlobalValue > ( V ) ) { MovI -> addOperand ( MF , MachineOperand :: CreateGA ( GV , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } else { MovI -> addOperand ( MF , MachineOperand :: CreateBA ( cast < BlockAddress > ( V ) , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } MovI -> addOperand ( MF , MachineOperand :: CreateImm ( Offset ) ) ; constrainSelectedInstRegOperands ( * MovI , TII , TRI , RBI ) ; return DstReg ; } ; unsigned DstReg = BuildMovK ( MovZ . getReg ( <NUM_LIT> ) , <STR_LIT> |


<s> return ( __mmask8 ) __builtin_ia32_fpclasspd512_mask ( ( __v8df ) __A , __imm , (


<s> unsigned OldSlot = getSlot ( FPRegNo ) ; unsigned TopReg = Stack [ StackTop - <NUM_LIT> ] ; Stack [ OldSlot ] = TopReg ; RegMap [ TopReg ] = OldSlot ; RegMap [ FPRegNo ] = ~ <NUM_LIT> ; Stack [ -- StackTop ] =


__C , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> getAddrModeImm12OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm12 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; isAdd = false ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset ; } } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups ) ; uint32_t Binary = Imm12 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg <<


<s> return __builtin_mve_vcmpltq_n_sv4si ( __a ,


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( MI , DeadInstrs , UpdatedDefs , Observer ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent (


<s> <STR_LIT> llvm :: getVPTInstrPredicate ( const MachineInstr & MI , Register & PredReg ) { int PIdx = findFirstVPTPredOperandIdx ( MI ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> ) MI . getOperand (


<s> void addImm1_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> int count ATTRIBUTE_UNUSED ; machine_mode ag_mode ATTRIBUTE_UNUSED ; if ( ! use_vfp_abi ( pcs_variant , false ) ) return false ; return aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode ,


<s> unsigned RegSize ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; Register ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> &&


<s> if ( MemVT . getScalarSizeInBits ( ) <= IndexVT . getScalarSizeInBits ( ) ) { IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; } else { MemVT = getContainerForFixedLengthVector ( DAG , MemVT ) ; IndexVT = MemVT . changeTypeToInteger ( ) ; } InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getScatterVecOpcode ( IsScaled , IsSigned , NeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , false , DAG ) ; if ( IsFixedLength ) { if ( Index . getSimpleValueType ( ) . isFixedLengthVector ( ) ) Index = convertToScalableVector ( DAG , IndexVT , Index ) ; if ( BasePtr . getSimpleValueType ( ) . isFixedLengthVector ( ) ) BasePtr =

convertToScalableVector ( DAG , IndexVT , BasePtr ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) { if ( PromotedGlobals . count ( GV ) ) return ; AsmPrinter :: EmitGlobalVariable (


<s> rtx xops [ <NUM_LIT> ] ; unsigned int regno ; if ( indirect_return_needed ) output_indirect_thunk_function ( indirect_thunk_prefix_none , INVALID_REGNUM , true ) ; if ( indirect_return_bnd_needed ) output_indirect_thunk_function ( indirect_thunk_prefix_bnd , INVALID_REGNUM , true ) ; if ( indirect_return_via_cx ) output_indirect_thunk_function ( indirect_thunk_prefix_none , CX_REG , true ) ; if ( indirect_return_via_cx_bnd ) output_indirect_thunk_function ( indirect_thunk_prefix_bnd , CX_REG , true ) ; if ( indirect_thunk_needed ) output_indirect_thunk_function ( indirect_thunk_prefix_none , INVALID_REGNUM , false ) ; if ( indirect_thunk_bnd_needed ) output_indirect_thunk_function ( indirect_thunk_prefix_bnd , INVALID_REGNUM , false ) ; for ( regno = FIRST_REX_INT_REG ; regno <= LAST_REX_INT_REG ; regno ++ ) { unsigned int i = regno - FIRST_REX_INT_REG + LAST_INT_REG + <NUM_LIT> ; if ( ( indirect_thunks_used & ( <NUM_LIT> << i ) ) ) output_indirect_thunk_function ( indirect_thunk_prefix_none , regno , false ) ; if ( ( indirect_thunks_bnd_used & ( <NUM_LIT> << i ) ) ) output_indirect_thunk_function ( indirect_thunk_prefix_bnd , regno , false ) ; } for ( regno = FIRST_INT_REG ; regno <= LAST_INT_REG ; regno ++ ) { char name [ <NUM_LIT> ] ; tree decl ; if ( ( indirect_thunks_used & ( <NUM_LIT> << regno ) ) ) output_indirect_thunk_function ( indirect_thunk_prefix_none , regno , false ) ; if ( ( indirect_thunks_bnd_used & ( <NUM_LIT> << regno ) ) ) output_indirect_thunk_function ( indirect_thunk_prefix_bnd , regno , false ) ; if ( ! ( pic_labels_used & ( <NUM_LIT> << regno ) ) ) continue ; get_pc_thunk_name ( name , regno ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( TARGET_MACHO )


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int MRSReg , MSRReg ; auto SysReg = <STR_LIT> ( Tok . getString ( ) ) ; if ( SysReg && SysReg -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { MRSReg = SysReg -> Readable ? SysReg -> Encoding : - <NUM_LIT> ; MSRReg = SysReg -> Writeable ? SysReg -> Encoding : - <NUM_LIT> ; } else MRSReg = MSRReg = <STR_LIT> ( Tok . getString ( ) ) ; auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc

( ) , MRSReg , MSRReg , PStateImm , getContext ( ) ) ) ;


<s> if ( ! Load ) return nullptr ; SDValue Ptr = Load -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) == <STR_LIT> ) Ptr = Ptr -> getOperand ( <NUM_LIT> ) ; auto * CNode = dyn_cast < ConstantPoolSDNode


<s> MachineOperand & AccMO = MI . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( DstMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( LHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( RHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( AccMO . getReg ( ) ) < <NUM_LIT> && DstMO . getReg ( ) == AccMO . getReg ( ) ) { MachineOperand Lhs ( LHSMO )


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target ) ; RegisterAsmInfoFn C ( The<ISA_LIT>32Target


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend


<s> return ( __m512i ) __builtin_ia32_loaddqudi512_mask ( ( const __v8di * ) __P ,


<s> case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; case <STR_LIT> : FinalOpcode = <STR_LIT> ; break ; } if ( FinalDstReg == <STR_LIT> ) TOut . emitRRR ( FinalOpcode , DstReg , DstReg , SrcReg ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; unsigned NewReg = <NUM_LIT> ; int NewImm = <NUM_LIT> ; bool ATUsed ; unsigned RegSize = STI . isGP32bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned StackAlign = getStackAlignment ( ) ; unsigned LocalVarAreaOffset = <ISA_LIT>FI -> needGPSaveRestore ( ) ? ( MFI -> getObjectOffset ( <ISA_LIT>FI -> getGPFI ( ) ) + RegSize ) : <ISA_LIT>FI -> getMaxCallFrameSize ( ) ; unsigned StackSize = AlignOffset ( LocalVarAreaOffset , StackAlign ) + AlignOffset ( MFI -> getStackSize ( ) , StackAlign ) ; MFI -> setStackSize ( StackSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; ATUsed = expandRegLargeImmPair ( <STR_LIT> , - StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( )


<s> static rtx nds32_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return

gen_rtx_REG ( mode , NDS32_FPR_RET_FIRST_REGNUM ) ;


<s> if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> ( InOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < InNumElts ; ++ i ) Ops . push_back ( InOp . getOperand ( i ) ) ; EVT EltVT = InOp . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , EltVT ) : DAG . getUNDEF ( EltVT ) ; for ( unsigned i = <NUM_LIT> ; i < WidenNumElts - InNumElts ; ++ i ) Ops . push_back ( FillVal ) ; return DAG . getBuildVector ( NVT , dl , Ops ) ; } SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , NVT ) : DAG . getUNDEF (


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef (


<s> if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { convertTo ( DL , <STR_LIT> , Op0 ) , convertTo ( DL , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , DL , <STR_LIT> ) } ; SDValue New = convertTo ( DL , VT , SDValue ( CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) , <NUM_LIT> ) ) ; ReplaceNode ( N , New . getNode


<s> int DstLSB , Width ; if ( isBitfieldExtractOp ( CurDAG , OrOpd0 , BFXOpc , Src , ImmR , ImmS , NumberOfIgnoredLowBits , BiggerPattern ) ) { if ( ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) || ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) ) continue ; DstLSB = <NUM_LIT> ; Width = ImmS - ImmR + <NUM_LIT> ; if ( Width <= <NUM_LIT> ) continue ; } else if ( isBitfieldPositioningOp ( CurDAG , SDValue ( OrOpd0 , <NUM_LIT> ) , BiggerPattern , Src , DstLSB , Width ) ) { ImmR = ( VT . getSizeInBits ( ) - DstLSB ) % VT . getSizeInBits ( ) ; ImmS = Width - <NUM_LIT> ; } else continue ; EVT VT = OrOpd1 -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; APInt KnownZero , KnownOne ; CurDAG -> computeKnownBits ( OrOpd1Val , KnownZero , KnownOne ) ; APInt BitsToBeInserted = APInt :: getBitsSet ( KnownZero . getBitWidth ( ) , DstLSB , DstLSB + Width ) ; if ( ( BitsToBeInserted & ~ KnownZero ) != <NUM_LIT> ) continue ; uint64_t Imm ; if ( isOpcWithIntImmediate ( OrOpd1 , <STR_LIT> , Imm ) && isBitfieldDstMask ( Imm , BitsToBeInserted , NumberOfIgnoredHighBits , VT ) ) Dst = OrOpd1 -> getOperand ( <NUM_LIT> ) ; else Dst = OrOpd1Val ; return true ; } return false


<s> auto & TPC = getAnalysis < TargetPassConfig > ( ) ; M = F . getParent ( ) ; DL = & M -> getDataLayout ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return


<s> } getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalFor ( { { s64 , p0 } } ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } , Lower ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . customFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . customForCartesianProduct ( { s1 } , { s32 , s64 } ) ; if ( AEABI ( ST ) ) setFCmpLibcallsAEABI ( ) ; else setFCmpLibcallsGNU ( ) ; getActionDefinitionsBuilder ( G_FPEXT ) . libcallFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . libcallFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . libcallForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . libcallForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } if ( ! ST . useSoftFloat ( ) && ST . hasVFP4 ( ) ) getActionDefinitionsBuilder ( G_FMA ) . legalFor ( { s32 , s64 } ) ; else getActionDefinitionsBuilder ( G_FMA ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FREM , G_FPOW } ) . libcallFor ( { s32 , s64 } ) ; computeTables ( ) ; verify ( * ST .


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) )


<s> return StringRef ( Tok . Data , Tok . Length


<s> } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == <STR_LIT> || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; -- I


<s> else if ( which_alternative == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else if ( which_alternative == <NUM_LIT> ) return <STR_LIT> ; else return <STR_LIT> ; } if ( reverse_comparison ) PUT_CODE ( operands [ <NUM_LIT> ] , reverse_condition ( GET_CODE ( operands [ <NUM_LIT> ] ) ) ) ; if ( which_alternative == <NUM_LIT> ) { int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; switch ( length ) { case <NUM_LIT> : if ( nullify ) return <STR_LIT> ; else return <STR_LIT> ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p

( insn ) && nullify ) return <STR_LIT> ;


<s> if ( spill_fill_data . prev_addr [ iter ] ) { if ( CONST_OK_FOR_N ( disp ) ) { * spill_fill_data . prev_addr [ iter ] = gen_rtx_POST_MODIFY ( DImode , spill_fill_data . iter_reg [ iter ] , gen_rtx_PLUS ( DImode , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) = gen_rtx_EXPR_LIST ( REG_INC , spill_fill_data . iter_reg [ iter ] , REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) ) ; } else { if ( ! CONST_OK_FOR_I ( disp ) ) { rtx tmp = gen_rtx_REG ( DImode , next_scratch_gr_reg ( ) ) ; emit_move_insn ( tmp , disp_rtx ) ; disp_rtx = tmp ; } emit_insn ( gen_adddi3 ( spill_fill_data . iter_reg [ iter ] , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; } } else if ( disp == <NUM_LIT> && spill_fill_data . init_reg [ iter ] == stack_pointer_rtx && frame_pointer_needed ) { mem = gen_rtx_MEM ( GET_MODE ( reg ) , hard_frame_pointer_rtx ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; return mem ; } else { rtx seq


<s> if ( isMClass ( ) && hasMinSize ( ) ) return false ; return useMachineScheduler ( )


<s> unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign , MaxMaxAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( auto * EltTy : STy -> elements ( ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( EltTy ,


<s> } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature +=


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ?


<s> Replacements . clear ( ) ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { for ( MachineBasicBlock :: iterator MI = MFI -> begin ( ) , ME = MFI -> end ( ) ; MI != ME ; ) { Modified |= runOnInstruction ( MI ++ ) ; } } for ( std :: set < MachineInstr * > :: iterator I = DeadInstr . begin


<s> static inline bool is_fast_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , <STR_LIT>


<s> Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( GetPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( GetPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) && MAI . hasSetDirective ( ) ) { MCSymbol * Label = Ctx . CreateTempSymbol ( ) ; AsmPrinter . OutStreamer . EmitAssignment (


<s> case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ,


<s> static const Function * getCallee ( const MachineConstantPoolEntry & E ) { auto * CPC = static_cast < <ISA_LIT>ConstantPoolConstant * > ( E


<s> LLVM_DEBUG ( DAG -> dumpNode ( * SU ) ) ; unsigned NSlots ; bool MustBeFirst = mustComeFirst ( MCID , NSlots ) ; if ( MustBeFirst && CurSlots ) { CurSlots = CurBranches = <NUM_LIT> ; CurGroup . clear ( ) ; } CurSlots += NSlots ; CurGroup . push_back ( SU ) ; if ( MCID -> isBranch ( ) ) ++ CurBranches ; } } return ScoreboardHazardRecognizer :: EmitInstruction (


<s> switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case <STR_LIT> : case <STR_LIT> : case


<s> return ( int32x2_t ) __builtin_neon_vmul_lanev2si ( __a ,


<s> if ( ( mode ) == DImode || ( mode ) == DFmode ) return gen_rtx_MEM ( mode , gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ) ; if ( valtype ) mode = TYPE_MODE


<s> const char * output_mov_double_fpa_from_arm ( rtx * operands ) { int arm_reg0 = REGNO ( operands [ <NUM_LIT> ] ) ; rtx ops [ <NUM_LIT> ] ; gcc_assert ( arm_reg0 != IP_REGNUM ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode ,


<s> int __aeabi_uwrite4 ( int data , void * ptr ) { ( ( struct u4 * ) ptr ) -> data = data ; return data


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : ++ NumLDMGened ; return <STR_LIT> ; case <STR_LIT> : ++ NumSTMGened ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; return <STR_LIT> ; case <STR_LIT>


<s> const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( )


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionBodyEnd ( ) { if ( Subtarget -> is<ISA_LIT>64 ( )


<s> static bool isOpcWithIntImmediate ( SDNode * N , unsigned Opc


<s> return new <ISA_LIT>InsertPrefetch ( PrefetchHintsFile )


<s> case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerEXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerExtendedLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op ,


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { Opcode = N1 . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return SDValue ( ) ; std :: swap ( N0 , N1 ) ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL (


<s> Value * <ISA_LIT>IREmitter :: visitRET_FLAG ( const SDNode * N ) { return IRB -> CreateRetVoid


<s> MCE . addRelocation ( MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , JTIndex , <NUM_LIT> , true


<s> SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) ,


<s> const TargetRegisterClass * <ISA_LIT>SERegisterInfo :: intRegClass ( unsigned Size ) const { if ( Size == <NUM_LIT> ) return &


<s> AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry


<s> if ( ! I ) return false ; if ( I -> getSrcTy ( ) -> getIntegerBitWidth ( ) != BitWidth


<s> assert ( getLexer ( ) . is ( AsmToken :: Colon ) && <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOT ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC_LO12 ) . Default ( <ISA_LIT>MCExpr :: VK_AARCH64_None ) ; if ( RefKind == <ISA_LIT>MCExpr