<s> return Kind == Register && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( )

) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo , Address


<s> case TYPE_R64 : case TYPE_Rv : case TYPE_MM : case TYPE_MM32 : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M16INT : case TYPE_M32INT : case TYPE_M64INT : case TYPE_M1616 : case TYPE_M1632 : case TYPE_M1664


<s> CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI


<s> static unsigned int compute_vrsave_mask ( void ) { unsigned int i , mask = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == <NUM_LIT> ) return mask ; for ( i = cfun -> args_info . vregno - <NUM_LIT> ; i >=

ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ;


<s> MF = MBB -> getParent ( ) ; MRI = & MF -> getRegInfo ( )


<s> if ( Desc . getOperandConstraint ( MaskOp , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ MaskOp ; const char * MaskRegName = getRegName ( MI -> getOperand ( MaskOp ) . getReg ( ) ) ; OS << <STR_LIT> << MaskRegName << <STR_LIT> ; if ( MaskWithZero )


<s> StackOffset <ISA_LIT>FrameLowering :: resolveFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg , bool PreferFP , bool ForSimm ) const { const auto & MFI = MF . getFrameInfo ( ) ; int ObjectOffset = MFI . getObjectOffset ( FI ) ; bool isFixed = MFI .


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } return MCConstantExpr :: create ( Val , getContext ( ) ) ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( <ISA_LIT>MCExpr :: isSupportedBinaryExpr ( VK , BE ) ) return <ISA_LIT>MCExpr :: create ( VK , Expr , getContext


<s> SDValue <ISA_LIT>TargetLowering :: getTargetNode ( BlockAddressSDNode * N , EVT Ty , SelectionDAG &


<s> static SDValue getGatherNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Src , SDValue Mask , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( Op ) ; auto * C = cast < ConstantSDNode > ( ScaleOp ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( VMask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ,


<s> for ( const unsigned * Regs = TID . ImplicitDefs ; * Regs ; ++ Regs ) if


<s> addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else


<s> return true ; } unsigned Pow2MinusOne = ( <NUM_LIT> << Lg2 ) - <NUM_LIT> ; unsigned AddReg = emitAddSub_ri ( true , VT , Src0Reg , false , Pow2MinusOne ) ; if ( ! AddReg ) return false ; if ( ! emitICmp_ri ( VT , Src0Reg , false , <NUM_LIT> ) ) return false ; unsigned SelectOpc ; const TargetRegisterClass * RC ; if ( VT == <STR_LIT> ) { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned SelectReg = fastEmitInst_rri ( SelectOpc , RC , AddReg , true , Src0Reg , Src0IsKill , <STR_LIT> ) ; if ( ! SelectReg ) return false ; unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg ; if ( C . isNegative ( ) ) ResultReg = emitAddSub_rs ( false , VT , ZeroReg , true , SelectReg , true , <STR_LIT> , Lg2 ) ; else ResultReg = emitASR_ri ( VT , VT , SelectReg


<s> void ApplyFixup ( const MCFixup & Fixup , char *

Data , unsigned DataSize , uint64_t Value ) const {


<s> return Is<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; case <STR_LIT> : return HasP8Vector ? & <STR_LIT> : & <STR_LIT> ; case <STR_LIT> : return HasVSX ? & <STR_LIT> : & <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn ) { IsFixed . resize ( Outs . size ( )


<s> cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire ||


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> void addRegF4RCOperands ( MCInst & Inst , unsigned


<s> inline vector signed char vec_srl ( vector signed char a1 , vector unsigned char a2 ) { return ( vector signed char ) __builtin_altivec_vsr ( ( vector signed int )


<s> static SDValue PerformZExtCombine ( SDNode * N , SelectionDAG & DAG ) { DebugLoc dl = N -> getDebugLoc ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) .


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_2 : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO10 ; case <STR_LIT> : return ELF ::


<s> Expected < StringRef > SymNameOrErr = SymI -> getName ( ) ; if ( Error E = SymNameOrErr . takeError ( ) ) return std :: move ( E ) ; StringRef SymName = * SymNameOrErr ; Expected < uint64_t > SymAddrOrErr = SymI -> getAddress ( ) ; if ( Error E = SymAddrOrErr . takeError ( ) ) return std :: move ( E ) ; const uint64_t SymAddr = * SymAddrOrErr ; uint64_t SymSize = SymI -> getSize ( ) ; int64_t Addend = * ELFRelocationRef ( Rel ) . getAddend ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( SymName ) ; if ( ! Sym -> isVariable ( ) ) Sym -> setVariableValue ( MCConstantExpr :: create ( SymAddr , Ctx ) ) ; const MCExpr * Expr = nullptr ; bool hasAddend = false ; switch ( RelType ) { case R_<ISA_LIT>_64_NONE : case R_<ISA_LIT>_64_COPY : break ; case R_<ISA_LIT>_64_64 : case R_<ISA_LIT>_64_16 : case R_<ISA_LIT>_64_8 : case R_<ISA_LIT>_64_32 : case R_<ISA_LIT>_64_32S : case R_<ISA_LIT>_64_PC32 : case R_<ISA_LIT>_64_PC16 : case R_<ISA_LIT>_64_PC8 : case R_<ISA_LIT>_64_PC64 : hasAddend = true ; Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOT32 : case R_<ISA_LIT>_64_GOT64 : case R_<ISA_LIT>_64_GOTPC32 : case R_<ISA_LIT>_64_GOTPC64 : case R_<ISA_LIT>_64_GOTPLT64 : hasAddend = true ; Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case R_<ISA_LIT>_64_PLT32 : hasAddend = true ; Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; break ; case R_<ISA_LIT>_64_GLOB_DAT : case R_<ISA_LIT>_64_JUMP_SLOT : Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOTPCREL : case R_<ISA_LIT>_64_GOTPCREL64 : hasAddend = true ; Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; break ; case R_<ISA_LIT>_64_GOTOFF64 : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ; break ; case R_<ISA_LIT>_64_PLTOFF64 : break ; case R_<ISA_LIT>_64_SIZE32 : case R_<ISA_LIT>_64_SIZE64 : Expr = MCConstantExpr :: create ( SymSize , Ctx ) ; break ; default : Expr = MCSymbolRefExpr :: create (


<s> if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT .


<s> EmitULEB128 ( Rx ) ; if ( odd ) { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> )


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> return new <ISA_LIT>PassConfig ( this ,


<s> } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBW_OP1 ) ; Found = true ; } if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBW_OP2 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBX_OP1 ) ; Found = true ; } if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBX_OP2 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULADDWI_OP1 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULADDXI_OP1 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBWI_OP1 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Pattern . push_back ( MachineCombinerPattern :: MC_MULSUBXI_OP1


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrModeImm12Operand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) )


<s> static bool r10k_needs_protection_p ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) return r10k_needs_protection_p_call ( PATTERN ( insn ) ) ; if ( mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE ) { note_stores ( PATTERN ( insn ) , r10k_needs_protection_p_store , &


<s> bool isToken ( ) const { return Kind == k_Token


<s> static bool registerDefinedBetween ( unsigned Reg , MachineBasicBlock :: iterator From , MachineBasicBlock

:: iterator To , const TargetRegisterInfo * TRI ) {


<s> static rtx nds32_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { if ( nds32_tls_referenced_p ( x ) ) x = nds32_legitimize_tls_address ( x ) ; else if ( flag_pic && SYMBOLIC_CONST_P ( x ) ) x = nds32_legitimize_pic_address ( x ) ; else if ( TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p ( x ) ) x


<s> if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef ATTRIBUTE_UNUSED SymbolName = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; return


<s> unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if ( UsedReg == BasePtr ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI -> getSEHFramePtrSaveIndex ( ) , UsedReg ) ; assert ( UsedReg == BasePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) , UsedReg , true , Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }


<s> case FK_Data_4 : Type = ELF :: R_MIPS_32 ; break ; case FK_GPRel_4 : Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case


<s> return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , & global_options_set , existing_options ) ; } else cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & global_options_set , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret


<s> int64_t SignedValue = static_cast < int64_t > ( Value ) ; switch ( Kind ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return AdrImmBits ( Value & <NUM_LIT> ) ; case <STR_LIT> : return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadedCst -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << '\n' ) ; for ( auto Use : IPI . second ) { assert ( DT . dominates ( LoadedCst , findInsertionPoint ( * Use . first , Use . second ) ) && <STR_LIT> ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << Use . second << <STR_LIT> ; Use . first -> print ( dbgs ( ) ) ; dbgs ( ) << '\n' ; }


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> fprintf ( dump_file , <STR_LIT> , INTVAL ( t ) ) ; for ( unsigned i = <NUM_LIT> ; i < insn_info . length ( ) ; i ++ ) dump_insn_slim (


<s> switch ( REG_NOTE_KIND ( link ) ) { default : dep = <STR_LIT> ; break ; case REG_DEP_TRUE : dep = <STR_LIT> ; break ; case REG_DEP_OUTPUT : dep = <STR_LIT> ; break ; case REG_DEP_ANTI : dep = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> <STR_LIT> ,


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) return


<s> return CreateReg ( Index , RegKind_MSACtrl , RegInfo , S , E , Parser


<s> static bool unsupportedBinOp ( const MachineInstr & I , const <ISA_LIT>RegisterBankInfo & RBI , const MachineRegisterInfo & MRI , const <ISA_LIT>RegisterInfo & TRI ) { if ( ! I . getType ( ) . isSized ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } const RegisterBank * PrevOpBank = nullptr ; for ( auto & MO : I . operands ( ) ) { if ( ! MO . isReg ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } const RegisterBank * OpBank = RBI . getRegBank ( MO . getReg ( ) , MRI , TRI ) ; if ( ! OpBank ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( PrevOpBank && OpBank != PrevOpBank


<s> SDLoc dl ( N ) ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; else if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ; SDVTList SDTys = DAG . getVTList ( N -> getValueType


<s> if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , <STR_LIT> , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm ,


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc


<s> if ( TARGET_MIPS16 && reg_class_subset_p ( rclass , M16_REGS ) ) rclass = M16_REGS ; else if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass


<s> StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: PPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; assert ( ( ! NeedsWinCFI || ! ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOStore , Size , Alignment ) ) ; } MIB . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOStore , Size , Alignment ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB , TII , MachineInstr :: FrameSetup ) ; MachineFrameInfo & MFI = MF


<s> if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_BASE || XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_UNIFIED


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; VecLd0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; VecLd1 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CreateLoadIns ( Builder , Acc , &


<s> applyOne ( llvm :: ELF :: DT_MIPS_RLD_VERSION , <NUM_LIT> ) ; applyOne ( llvm :: ELF :: DT_MIPS_FLAGS , llvm :: ELF :: RHF_NOTPOT ) ; applyOne ( llvm :: ELF :: DT_MIPS_BASE_ADDRESS , getBaseAddress ( ) ) ; applyOne ( llvm :: ELF :: DT_MIPS_LOCAL_GOTNO , getLocalGotNum (


<s> uint32_t getAddrMode3OpValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> return DecodeVecShiftRImm ( Inst , Imm |


<s> if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> FnStoreVarArgs . push_back ( <ISA_LIT>FIHolder ( FI


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) ==


<s> RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCObjectStreamer (

The<ISA_LIT>Target , createMCStreamer ) ;


<s> Op . setTokenValue ( Base ) ; } } } if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfo ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( UnsizedMemOp && NumSuccessfulMatches > <NUM_LIT> && UnsizedMemOp -> getMemFrontendSize ( ) ) { UnsizedMemOp -> Mem . Size = UnsizedMemOp -> getMemFrontendSize ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( M == Match_Success ) NumSuccessfulMatches = <NUM_LIT> ; InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , UnsizedMemOp -> getStartLoc ( ) , <NUM_LIT> , UnsizedMemOp -> getMemFrontendSize ( ) ) ; } if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; return Error ( UnsizedMemOp -> getStartLoc ( ) , <STR_LIT> + Mnemonic + <STR_LIT> , UnsizedMemOp -> getLocRange ( ) ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MissingFeature )


<s> SDLoc DL ( N0 ) ; SDValue Ops [ ] = { DAG . getConstant ( TrueOp -> getZExtValue ( ) , DL , VT ) , DAG . getConstant ( FalseOp -> getZExtValue ( ) , DL , VT ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) } ; SDValue NewSelect = DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; if ( ! N0 . hasOneUse ( ) ) { SDValue TruncSelect = DAG . getNode ( <STR_LIT> , DL , N0 . getValueType ( ) , NewSelect ) ; DCI . CombineTo ( N0 . getNode (


<s> unsigned getCheriReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >= <STR_LIT> &&

RegIdx . RealRegister <= <STR_LIT> ) ) ;


<s> instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( target ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( base . getReg ( ) != target . getReg ( ) ) ; two_instructions = true ; MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( base ) ; instr3 . addOperand ( adj_name ) ; break ; } default : assert ( <NUM_LIT> && <STR_LIT> ) ; } MCInsts . push_back ( instr1 )


<s> return m16_check_op ( op , - <NUM_LIT> , <NUM_LIT> ,


<s> } Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask ->

getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) , Input , Mask } ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { unsigned ResultReg ; ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg1 = ResultReg ; if ( ! UseImm ) { ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg2 = ResultReg ; } } if ( ! UseImm ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB


<s> register int i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = i ; if ( TARGET_MIPS16 ) { reg_alloc_order [ <NUM_LIT> ]


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) == <STR_LIT> ) && std :: next ( I ) != E && I != MBB -> begin ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MachineBasicBlock * newBB = splitBlockAfterInstr ( I , MF ) ; MBB -> setHasAddressTaken ( ) ; break ; } if ( ( I -> getOpcode ( ) == <STR_LIT> ) && std :: next ( I ) == E && I != MBB -> begin ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MachineBasicBlock * newBB = MF . CreateMachineBasicBlock ( ( I -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; if ( It != MF . end ( ) ) MF . insert ( It , newBB ) ; else MF . push_back


<s> Register Reg = Register :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . test ( Idx ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures ) { LLVM_DEBUG ( C . dump ( MRI ) ) ; if ( isReassignmentProfitable ( C ,


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) != <STR_LIT> ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & <NUM_LIT> ) == <NUM_LIT> ) { RHSC >>= <NUM_LIT> ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true


<s> if ( PHINode * PhiInst = dyn_cast < PHINode > ( User ) ) return PhiInst -> getIncomingBlock ( Use . getOperandNo ( ) ) -> getTerminator ( ) ; return User


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> return getParser ( ) . Note ( L , Msg ,


<s> MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } int MaskLO = Mask [ <NUM_LIT> ] ; if ( MaskLO == SM_SentinelUndef ) MaskLO = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; int MaskHI = Mask [ <NUM_LIT> ] ; if ( MaskHI == SM_SentinelUndef ) MaskHI = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; unsigned PermMask = MaskLO / <NUM_LIT> | ( MaskHI / <NUM_LIT> ) << <NUM_LIT> ; if ( IsV1Zero ) { V1 = DAG . getUNDEF (


<s> return arm_coproc_mem_operand_wb ( op


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( )


<s> transferMemOperands ( N , LoadInst ) ; } if ( HasWriteback ) ResultTys = { DataTy , <STR_LIT> , <STR_LIT> } ; SDValue Ops [ ] = { Data , N -> getOperand ( PtrOperand ) , Chain } ; auto LoadInst = CurDAG -> getMachineNode ( OurOpcodes [ NumVecs - <NUM_LIT> ] , Loc , ResultTys , Ops ) ; transferMemOperands ( N , LoadInst ) ; unsigned i ; for ( i = <NUM_LIT> ; i < NumVecs ; i ++ ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , Loc , VT , SDValue ( LoadInst , <NUM_LIT> ) ) ) ; if ( HasWriteback ) ReplaceUses ( SDValue ( N , i ++ ) , SDValue ( LoadInst , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , i ) , SDValue ( LoadInst , HasWriteback ? <NUM_LIT> : <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> rtx scratch ; scratch = plus_constant ( stack_pointer_rtx , gp_offset ) ; emit_move_insn ( gen_rtx_MEM ( GET_MODE ( address ) ,


<s> unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } Register ResultReg = fastEmitInst_r ( Opc , TLI . getRegClassFor ( DestVT


<s> sigstk . ss_sp = ( char * ) xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; sigemptyset ( & sact . sa_mask ) ; sact . sa_flags = SA_ONSTACK | SA_SIGINFO ; sact . sa_sigaction = segv_handler ; if ( sigaction ( SIGSEGV , & sact , <NUM_LIT> ) < <NUM_LIT> ) fatal_error ( input_location


<s> return ( MI && MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ==

Base && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == Bytes && getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> if ( Model == TLSModel :: LocalDynamic ) Model = TLSModel :: GeneralDynamic ; } SDValue TPOff ; EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue TPWithOff_lo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , ThreadBase , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue TPWithOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPWithOff_lo , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return TPWithOff ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL ,


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) )


<s> bool isPositionIndependent ( ) const { return TM . getRelocationModel ( )


<s> break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : break ; } return


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg (


<s> It ++ ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) return false ; else if ( It -> killsRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) IsFwdFeederRegKilled = true ; if ( ( & * It ) == & DefMI ) break ; } assert ( ( & * It ) == & DefMI && <STR_LIT> ) ; if ( DefMI . modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) return KillDefMI ; return true


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerCALL ( Op , DAG , <ISA_LIT>SubTarget , getTargetMachine ( ) ) ; case <STR_LIT> : return LowerRET ( Op , DAG , getTargetMachine ( ) ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG , Op . getDebugLoc ( ) ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS (


<s> if ( VMVT == <STR_LIT> ) return <NUM_LIT> ; if ( ( VMVT == <STR_LIT> ) || ( VMVT == <STR_LIT> ) ) { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitIntExt ( VMVT , VReg , <STR_LIT>

, TempReg , IsUnsigned ) ) return <NUM_LIT> ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ,


<s> std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back (


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) .


<s> if ( NotCC ) { JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) ; return JCE . finishGVStub ( F ) ; } JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE


<s> if ( ! reload_completed ) return <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] || profile_flag ) return <NUM_LIT> ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size == <NUM_LIT> ; return compute_frame_size ( get_frame_size ( )


<s> const uint32_t * <ISA_LIT>RegisterInfo ::


<s> if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = <NUM_LIT> ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastOpc == UncondBrOpc ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( LastOpc != UncondBrOpc ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB


<s> bool <ISA_LIT>BasicMCBuilder :: RunBuildAfterHook ( bool Status , MCInst & MI , uint32_t insn ) { if ( ! SP ) return Status ; if ( Opcode == <STR_LIT> ) Status = SP -> InitIT ( slice ( insn

, <NUM_LIT> , <NUM_LIT> ) ) ? Status : false ;


<s> setupBlockStack ( ) ; for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { MachineInstr & MI = * I ; uint64_t Flags = MI . getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI . isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI . isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI . isImplicitDef ( ) && <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( MI . isCall ( ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = nullptr ; if ( I != BB . begin ( ) ) PrevMI = & * std :: prev ( I ) ; ++ NumFP ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } LLVM_DEBUG ( { MachineBasicBlock :: iterator PrevI = PrevMI ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) ) ; while ( ++ Start != std :: next ( I ) ) { } } dumpStack ( ) ; } ) ; ( void ) PrevMI ; Changed = true ; } finishBlockStack ( ) ; return


<s> } if ( ExtraToken != <STR_LIT> && ( isThumb ( ) || ExtraToken != <STR_LIT> ) ) { SMLoc Loc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Start ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExtraToken , Loc ) ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; if ( ! CarrySetting && shouldOmitCCOutOperand ( Mnemonic , Operands ) ) { <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; delete Op ; } if ( ! isThumb ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) { <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; delete Op ; } if ( ! isThumb ( ) && Operands . size ( ) > <NUM_LIT> && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) { bool isLoad = ( Mnemonic == <STR_LIT> ) ; unsigned Idx = isLoad ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>Operand * Op1 = static_cast < <ISA_LIT>Operand * > ( Operands [ Idx ] ) ; <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ Idx + <NUM_LIT> ] ) ; const MCRegisterClass & MRC = MRI -> getRegClass ( <STR_LIT> ) ; if ( Op1 -> isReg ( ) && Op2 -> isReg ( ) && MRC . contains ( Op1 -> getReg ( ) ) && MRC . contains ( Op2 -> getReg ( ) ) ) { unsigned Reg1 = Op1 -> getReg ( ) ; unsigned Reg2 = Op2 -> getReg ( ) ; unsigned Rt = MRI -> getEncodingValue ( Reg1 ) ; unsigned Rt2 = MRI ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerSVEStructLoad ( unsigned Intrinsic , ArrayRef < SDValue > LoadOps , EVT VT , SelectionDAG & DAG , const SDLoc & DL ) const { assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; unsigned N , Opcode ; static std :: map < unsigned , std :: pair < unsigned , unsigned >> IntrinsicMap = { { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } } ; std :: tie ( N , Opcode ) = IntrinsicMap [ Intrinsic ] ; assert ( VT . getVectorElementCount ( ) . getKnownMinValue ( ) % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / N ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back (


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT (


<s> void <ISA_LIT>AsmPrinter :: EmitXXStructor ( const Constant * CV ) { uint64_t Size = TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( CV -> getType ( ) ) ; assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT>


<s> if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT .


<s> int64_t <ISA_LIT>FrameLowering :: determineSVEStackSize ( MachineFrameInfo & MFI , unsigned & MaxAlign ) const { int64_t Offset = <NUM_LIT> ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFI . getStackID ( I ) == TargetStackID :: SVEVector ) { int64_t FixedOffset = - MFI . getObjectOffset (


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; Register mainDstReg = MRI . createVirtualRegister ( RC ) ; Register fallDstReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( fallMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( fallMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( fallMBB , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( fallMBB , DL , TII -> get ( TargetOpcode :: COPY ) , fallDstReg ) . addReg ( <STR_LIT> ) ; fallMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) . addReg ( fallDstReg ) . addMBB ( fallMBB ) ; MI . eraseFromParent


<s> bool isTargetCygMing ( ) const { return ( TargetType == isMingw || TargetType == isCygwin


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; SDValue Chain = DAG . getTruncStore ( Node -> getChain ( ) , SDLoc ( Op ) , Node -> getVal ( ) , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ; if ( Node -> getSuccessOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Chain ) , <NUM_LIT> ) ; return Chain


<s> if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( ! RegInfo . isPhysicalRegister ( Reg ) ) continue ; if ( RegInfo . regsOverlap ( Reg , RegInfo . getStackRegister ( ) ) ) return Exit ; if ( MO . isDef ( )


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>_32Target (


<s> void <ISA_LIT>BranchFixup :: verify ( ) { for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , E = MF -> end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; unsigned MBBId = MBB ->


<s> if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return Align


<s> EVT ToVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT FromVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT == <STR_LIT> && ToVT == <STR_LIT> && FromVT == <STR_LIT> ) return Op ; if ( VT == <STR_LIT> && ToVT == <STR_LIT> && FromVT == <STR_LIT> ) return Op ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return


<s> <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) { SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; if ( ! isLittle ) LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( <NUM_LIT> - LoadSize * <NUM_LIT> , <STR_LIT> ) ) ; Offset += LoadSize ; RemainingSize -= LoadSize ; if ( RemainingSize != <NUM_LIT> ) { assert ( RemainingSize == <NUM_LIT> && <STR_LIT> ) ; LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue Subword = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> , false , false , Alignment ) ; MemOpChains . push_back ( Subword . getValue ( <NUM_LIT> ) ) ; unsigned ShiftAmt = isLittle ? <NUM_LIT> : <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Subword , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , Shift ) ; } unsigned DstReg = O32IntRegs [ LocMemOffset / <NUM_LIT> ] ; RegsToPass . push_back ( std :: make_pair ( DstReg , LoadVal ) ) ; return ; } SDValue Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; LastFI = MFI -> CreateFixedObject ( RemainingSize , LocMemOffset , true ) ; SDValue Dst = DAG . getFrameIndex ( LastFI ,


<s> case <STR_LIT> : { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true ; } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset (


<s> SDValue Stack = DAG . getFrameIndex ( FuncInfo -> getVariadicStackIdx ( ) , getPointerTy ( ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ) ; int GPRSize = FuncInfo -> getVariadicGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVariadicGPRIdx ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; } int FPRSize = FuncInfo ->


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned HintNum = <NUM_LIT> ; if ( CouldCall ) HintNum |= <NUM_LIT> ; if ( CouldJump ) HintNum |= <NUM_LIT> ; assert ( HintNum != <NUM_LIT> && <STR_LIT> ) ; auto MBBI = MBB . begin ( ) ; for ( ; MBBI != MBB . end ( ) && MBBI -> isMetaInstruction ( ) ; ++ MBBI ) ; if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) return ; BuildMI ( MBB , MBB . begin ( ) , MBB . findDebugLoc ( MBB . begin ( ) ) ,

TII -> get ( <STR_LIT> ) ) . addImm ( HintNum ) ;


<s> TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node =


<s> void addLegalFPImmediate ( const APFloat & Imm ) { LegalFPImmediates . push_back ( Imm


<s> for ( SDNode :: use_iterator UI = Op -> use_begin ( ) , UE = Op -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( )


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; FpFormatTy Format = getFpFormat ( ) ; if ( Format == FP_FORMAT_S || Format == FP_FORMAT_W ) return getReg ( <STR_LIT> , IntVal ) ; if ( Format == FP_FORMAT_D ) { if ( isFP64 ( ) ) { return getReg ( <STR_LIT> , IntVal ) ; } if ( ( IntVal > <NUM_LIT> ) || ( IntVal % <NUM_LIT> != <NUM_LIT> ) ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , IntVal


<s> bool IsRIPRel = N . getOpcode ( ) == <STR_LIT> ; CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) && ( M == CodeModel :: Large || ( M == CodeModel :: Medium && ! IsRIPRel ) ) ) return true ; if ( IsRIPRel && AM . hasBaseOrIndexReg ( ) ) return true ; <ISA_LIT>ISelAddressMode Backup = AM ; int64_t Offset = <NUM_LIT> ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; Offset = BA -> getOffset ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( foldOffsetIntoAddress ( Offset , AM ) ) { AM = Backup ; return true ; } if ( IsRIPRel ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false


<s> SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V ) return SDValue ( ) ; SDValue VMask = DAG . getBuildVector ( VT , DL , VMaskOps


<s> JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) ptr ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) ptr ) >> <NUM_LIT> ) ) ; JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) ptr ) ; return JCE . finishGVStub


<s> if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ <NUM_LIT> ] ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine

( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;


<s> return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , Align ( <NUM_LIT> ) , false , false , false , MachinePointerInfo (

DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII


<s> __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v4si ( ( __builtin_aarch64_simd_si * )


<s> bool hasFSQRT ( ) const { return HasFSQRT


<s> if ( Name . endswith ( <STR_LIT> ) ) { Mnemonic = Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; IsBRR = true ; } if ( Mnemonic [ <NUM_LIT> ] == 'b' || ( Mnemonic [ <NUM_LIT> ] == 's' && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ) ) { LPCC :: CondCode CondCode = LPCC :: suffixTo<ISA_LIT>CondCode ( Mnemonic . substr ( <NUM_LIT> , Next ) ) ; if ( CondCode != LPCC :: UNKNOWN ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , <NUM_LIT> ) ; Operands -> push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; Operands -> push_back ( <STR_LIT> ( MCConstantExpr :: create ( CondCode , getContext ( ) ) , NameLoc , NameLoc ) ) ; if (


<s> initialize<ISA_LIT>A53Fix835769Pass ( * PassRegistry :: getPassRegistry (


<s> bool <ISA_LIT>TargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex


<s> if ( N00 . getOpcode ( ) == <STR_LIT> && N01 . getOpcode ( ) == <STR_LIT> && N10 . getOpcode ( ) == <STR_LIT> && N11 . getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( N00 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N01 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N10 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N11 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && N00 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N01 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N10 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N11 . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && DAG . isSplatValue ( N00 . getOperand ( <NUM_LIT> ) ) && DAG . isSplatValue ( N01 . getOperand ( <NUM_LIT> ) ) && DAG . isSplatValue ( N10 . getOperand ( <NUM_LIT> ) ) && DAG . isSplatValue ( N11 . getOperand ( <NUM_LIT> ) ) ) { SDValue S00 = N00 . getOperand ( <NUM_LIT> ) ; SDValue S01 = N01 . getOperand ( <NUM_LIT> ) ; SDValue S10 = N10 . getOperand ( <NUM_LIT> ) ; SDValue S11 = N11 . getOperand ( <NUM_LIT> ) ; if ( S10 . getOpcode ( ) == <STR_LIT> && S11 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( S00 , S10 ) ; std :: swap ( S01 , S11 ) ; std :: swap ( N00 , N10 ) ; std :: swap ( N01 , N11 ) ; } if ( S00 . getOpcode ( ) == <STR_LIT> && S01 . getOpcode ( ) == <STR_LIT> ) { if ( S00 . getOperand ( <NUM_LIT> ) == S10 && S01 . getOperand ( <NUM_LIT> ) == S11 ) { Mask17 = <NUM_LIT> ; N0 = S10 ; N1 = S11


<s> void LLVMInitialize<ISA_LIT>AsmPrinter (


<s> return ( __m256 ) __builtin_ia32_cvtpd2ps512_mask ( ( __v8df ) __A , ( __v8sf ) _mm256_undefined_ps ( ) , (


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S4 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> if ( Bytes != <NUM_LIT> ) { unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs


<s> return makeArrayRef ( Nodes . get ( ) , NodesSize


<s> if ( GET_CODE ( addr_rtx ) == PLUS && GET_CODE ( XEXP ( addr_rtx , <NUM_LIT> ) ) == CONST_INT ) return true ; return


<s> static machine_mode sparc_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VIS ) switch ( mode ) { case E_SImode : return V2SImode


<s> auto SrcVT = TLI -> getValueType ( DL , Src ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; if ( ! VecLT . second . isVector ( ) || ! TLI -> isTypeLegal ( DstVT ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; if ( DstVT . getFixedSizeInBits ( ) < SrcVT . getFixedSizeInBits ( ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SExt : return Cost ; case Instruction :: ZExt : if ( DstVT . getSizeInBits ( ) != <NUM_LIT> ||

SrcVT . getSizeInBits ( ) == <NUM_LIT> ) return Cost ;


<s> if ( ! Root . isReg ( ) ) return None ; MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * ShiftInst = MRI . getVRegDef ( Root . getReg ( ) ) ; <STR_LIT> ShType = getShiftTypeForInst ( * ShiftInst ) ; if ( ShType == <STR_LIT> ) return None ; if ( ShType == <STR_LIT> && ! AllowROR ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * ShiftInst , MRI ) ) return None ; MachineOperand & ShiftRHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; auto Immed = getImmedFromMO ( ShiftRHS ) ; if ( ! Immed ) return None ; MachineOperand & ShiftLHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; Register ShiftReg = ShiftLHS . getReg ( ) ; unsigned NumBits = MRI . getType ( ShiftReg ) . getSizeInBits ( ) ; unsigned Val = * Immed & ( NumBits - <NUM_LIT> ) ; unsigned ShiftVal = <STR_LIT> (


, V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , computeFSAdditions ( FS , OL , TT

) , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , TargetFS , * this ) {


<s> default : return <NUM_LIT> ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . ParseExpression ( EVal ) ) return <NUM_LIT> ; int64_t ans ; EVal -> EvaluateAsAbsolute ( ans ) ; return <STR_LIT> ( EVal , S ,


<s> char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total +=


<s> case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; } return true


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHPOINT ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) { MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } Register ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes


<s> static void ATTRIBUTE_USED <ISA_LIT>CompilationCallback2 ( intptr_t * StackPtr , intptr_t RetAddr ) { intptr_t * RetAddrLoc = & StackPtr [ <NUM_LIT> ] ; assert ( * RetAddrLoc == RetAddr && <STR_LIT> ) ; bool isStub = ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] == <NUM_LIT> ; RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( errs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; if ( ! isStub ) * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) =


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> ) !=


<s> static SDValue combineShift ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightArithmetic ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightLogical ( N , DAG ) ) return V ; return SDValue ( )


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; bool CallsEHReturn = MF -> callsEHReturn ( ) ; CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; if ( MF -> getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) CC = CallingConv :: <ISA_LIT>_INTR ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList


<s> tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ShiftAmount ) ) ; tmpInst . setLoc ( IDLoc ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; } if ( Operand . isImm ( ) && Operand . getImm ( ) ==


<s> <STR_LIT> Opc = ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned ShAmt = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ShAmt == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) ShAmt = <NUM_LIT> ; else Opc = <STR_LIT> ; } MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Opc , ShAmt ) ) ) ; } return


<s> if ( Constraint . size ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 's' && tolower ( Constraint [ <NUM_LIT> ] ) == 't' && Constraint [ <NUM_LIT> ] == '(' && ( Constraint [ <NUM_LIT> ] >= '0' && Constraint [ <NUM_LIT> ] <= '7' ) && Constraint [ <NUM_LIT> ] == ')' && Constraint [ <NUM_LIT> ] == '}' ) { Res . first = <STR_LIT> + Constraint [ <NUM_LIT> ] - '0' ; Res . second = & <STR_LIT> ; return Res ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } if ( Constraint == <STR_LIT> ) { Res . first = <STR_LIT> ; Res . second = & <STR_LIT> ; return Res ; } return Res ; } if ( Res . second -> hasType ( VT ) || VT == <STR_LIT> ) return Res ; const TargetRegisterClass * Class = Res . second ; if ( isGRClass ( * Class ) ) { unsigned Size = VT . getSizeInBits ( ) ; if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; unsigned DestReg = get<ISA_LIT>SubSuperRegisterOrZero ( Res . first , Size ) ; if ( DestReg > <NUM_LIT> ) { Res . first = DestReg ; Res . second = Size == <NUM_LIT> ? & <STR_LIT> : Size == <NUM_LIT> ? & <STR_LIT> : Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; assert ( Res . second -> contains ( Res . first ) && <STR_LIT> ) ; } else { Res . first = <NUM_LIT> ; Res . second = nullptr ; } } else if ( isFRClass ( * Class ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) Res . second = & <STR_LIT> ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else if ( <STR_LIT> . hasType ( VT ) ) Res . second = & <STR_LIT> ; else { Res . first =


<s> if ( ! flag_unwind_tables && ( ! flag_exceptions || USING_SJLJ_EXCEPTIONS )


<s> int i ; for ( i = <NUM_LIT> ; i < size ; ++ i ) if ( desc [ i ] . code == start ) break ; if ( i ==


<s> SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; if ( AnalyzeBranchImpl ( MBB , MBP . TrueDest , MBP . FalseDest , Cond , CondBranches , AllowModify ) ) return true ; if ( Cond . size ( ) != <NUM_LIT> ) return true ; assert ( MBP . TrueDest && <STR_LIT> ) ; if ( ! MBP . FalseDest ) MBP . FalseDest = MBB . getNextNode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( auto I = std :: next ( MBB . rbegin ( ) ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) { ConditionDef = & * I ; break ; } if ( I -> readsRegister ( <STR_LIT> , TRI ) )


<s> StringRef Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; if ( Valid ) O << StringRef ( Name . str ( ) ) . upper ( ) ; else O << <STR_LIT> <<


<s> bool getNoBTIAtReturnTwice ( ) const { return NoBTIAtReturnTwice


<s> bool isTargetWin32 ( ) const { return ! In64BitMode && ( isTargetCygMing (


<s> if ( cast < FixedVectorType > ( Op -> getType ( ) ) -> getNumElements ( ) < <NUM_LIT> ) return false ; if ( ! cast < VectorType > ( Op -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; auto * Mul = dyn_cast < BinaryOperator > ( Op ) ; if ( ! Mul || Mul -> getOpcode ( ) != Instruction :: Mul ) return false ; Value * LHS = Mul -> getOperand ( <NUM_LIT> ) ; Value * RHS = Mul -> getOperand ( <NUM_LIT> ) ; if ( ST -> hasSSE41 ( ) ) { if ( LHS == RHS ) { if ( ! isa < Constant > ( LHS ) && ! LHS -> hasNUses ( <NUM_LIT> ) ) return false ; } else { if ( ! isa < Constant > ( LHS ) && ! LHS -> hasOneUse ( ) ) return false ; if ( ! isa < Constant > ( RHS ) && ! RHS -> hasOneUse ( ) ) return false ; } } auto CanShrinkOp = [ & ] ( Value * Op ) { auto IsFreeTruncation = [ & ] ( Value * Op ) { if ( auto * Cast = dyn_cast < CastInst > ( Op ) ) { if ( Cast -> getParent ( ) == Mul -> getParent ( ) && ( Cast -> getOpcode ( ) == Instruction :: SExt || Cast -> getOpcode ( ) == Instruction :: ZExt ) && Cast -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return true ; } return isa < Constant > (


<s> } gcc_assert ( src == stack_pointer_rtx ) ; gcc_assert ( seh -> cfa_reg == stack_pointer_rtx ) ; dest_regno = REGNO ( dest ) ; if ( dest_regno == STACK_POINTER_REGNUM ) seh_emit_stackalloc ( f , seh , reg_offset ) ; else if ( dest_regno == HARD_FRAME_POINTER_REGNUM ) { HOST_WIDE_INT offset ; seh -> cfa_reg = dest ; seh -> cfa_offset -= reg_offset ; offset = seh -> sp_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT>


<s> } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ) cost = <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return shift_insns


<s> const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand :: CreateImm ( Op , IdVal , S , E ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op ) ; case AsmToken :: LCurly : return ParseRegisterList ( Op ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { bool IsUndef = Values [ i ] < <NUM_LIT> && IsMask ; SDValue OpNode = IsUndef ? DAG . getUNDEF ( EltVT ) : DAG . getConstant ( Values [ i ] , dl , EltVT ) ; Ops . push_back ( OpNode ) ; if ( Split ) Ops . push_back ( IsUndef


<s> tree nds32_builtin_decl_impl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= NDS32_BUILTIN_COUNT ) return error_mark_node ; return nds32_builtin_decls [


<s> int64_t Offset = MFI -> getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) + saveAreaOffset ; if ( HasFP && ( FramePtr == Reg || Reg == <STR_LIT> ) ) { TotalSkipped += stackGrowth ; continue ; } unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , Offset - TotalSkipped ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> static inline bool isTOCSaveRestoreRequired ( const <ISA_LIT>Subtarget


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , T . createMCInstrInfo


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) .


getScalarSizeInBits ( ) < <ISA_LIT>CodeGenPrepare :: TypeSize ;


<s> SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , Const31 , Const1 , X ) ; } else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31


<s> SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; if ( N1 -> getOpcode ( ) != <STR_LIT> || ! N1 -> hasOneUse ( ) ) return SDValue ( ) ; SDLoc DL ( Node ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = foldMaskedMergeImpl ( N00 , N01 ,

N10 , N11 , DL , DAG ) ) return Result ;


<s> CC = o . CC ; break ; case Token : Tok = o . Tok ; break ; case CCOut : case Register : Reg = o . Reg ; break ; case RegisterList : case


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 .

NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ;


<s> if ( VT == <STR_LIT> ) return ! Subtarget -> hasFP64 ( ) ; if ( VT == <STR_LIT> ) return ! Subtarget -> hasFullFP16 ( ) ; return


<s> return decodeRegisterClass ( Inst , RegNo


<s> vtrn_s32 ( int32x2_t a , int32x2_t b ) { return ( int32x2x2_t ) { vtrn1_s32 ( a , b ) ,


<s> static bool rs6000_aix_precompute_tls_p ( machine_mode mode


<s> if ( auto COff = getIConstantVRegSExtVal ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { int64_t Imm = * COff ; if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I . getOperand ( <NUM_LIT> )