<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) ) return


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn


<s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD (


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction &


<s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT


<s> if ( riscv_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return


<s> return PhysReg == <STR_LIT> || PhysReg


<s> } if ( ! isInt < <NUM_LIT> > ( Offset . getFixed ( ) ) ) { unsigned Opc ; unsigned ImmOpc ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) { Opc = <STR_LIT> ; ImmOpc = <STR_LIT> ; } else { Opc = <STR_LIT> ; ImmOpc = <STR_LIT> ; } TII -> movImm ( MBB , II , DL , ScratchReg , Offset . getFixed ( ) ) ; if ( MI . getOpcode ( ) == ImmOpc && ! Offset . getScalable ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register DestReg = ScratchReg ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) { DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } BuildMI ( MBB , II , DL , TII -> get ( Opc ) , DestReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = StackOffset :: get ( <NUM_LIT> , Offset . getScalable ( ) ) ; FrameReg = DestReg ; FrameRegIsKill = true ; } if ( ! Offset . getScalable ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; else { if ( Offset . getFixed ( ) ) { Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT>


<s> if ( TT . isArch64Bit ( ) ) { return <STR_LIT> ; } else { assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT>


<s> void th_mempair_order_operands ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) { int mem_op = load_p ? <NUM_LIT> : <NUM_LIT> ; bool reversed


<s> else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) ) { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) Offset += RVFI -> getVarArgsSaveSize ( ) ; else Offset += MF . getFrameInfo (


<s> bool hasStdExtZvqmac ( ) const { return


<s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> const MCTargetOptions & getTargetOptions ( ) const


<s> assert ( ! InstrInfo . SEWLMULRatioOnly && <STR_LIT> ) ; if ( isUnknown ( ) || InstrInfo . isUnknown ( ) ) return false ; if ( SEWLMULRatioOnly ) return false ; if ( ! Strict && InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ; bool Res = compressInst ( CInst , Inst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; AsmPrinter :: EmitToStreamer ( * OutStreamer , Res ? CInst : Inst


<s> static SDValue lowerFP_TO_INT_SAT ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT DstVT = Op . getValueType ( ) ; EVT SatVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; bool IsSigned = Op . getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , DstVT , Src , DAG . getTargetConstant ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , DL , DstVT


<s> void setVarArgsFrameIndex ( int Index )


<s> abi = <STR_LIT> ; break ; case ABI_ILP32D : case ABI_LP64D : abi = <STR_LIT> ; break ; default : abi = <STR_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getSpliceCost ( VectorType * Tp , int Index ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; unsigned Cost = <NUM_LIT> ; return Cost * LT .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSetVL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSPILL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> rtl_opt_pass * make_pass_shorten_memrefs ( gcc :: context * ctxt ) { return new pass_shorten_memrefs ( ctxt


<s> if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) ) return true ; unsigned OldCond = Cond [ <NUM_LIT> ] . getImm


<s> return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK ==


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VT . isVector ( ) ) { MVT SplatCondVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue CondSplat = VT . isScalableVector ( ) ? DAG . getSplatVector ( SplatCondVT , DL , CondV ) : DAG . getSplatBuildVector ( SplatCondVT , DL , CondV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , CondSplat , TrueV , FalseV ) ; } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType


<s> return IsConstantImm && Imm >= INT64_C ( <NUM_LIT> ) && Imm <= INT64_C ( <NUM_LIT> ) && VK ==


<s> assert ( ISD && <STR_LIT> ) ; if ( ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ; unsigned VL = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VTy ) ; if ( TTI :: requiresOrderedReduction ( FMF ) ) return ( LT . first - <NUM_LIT>


<s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs ( MF ) ; if ( ! ReservedRegs . test ( Reg ) && ! Subtarget . isRegisterReservedByUser ( Reg ) ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; return Reg


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O << Value ; } else printOperand ( MI , OpNum , O


<s> const char * riscv_output_return ( ) { if ( cfun -> machine -> naked_p )


<s> return getRelaxedOpcode ( Inst . getOpcode


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( TM . isPositionIndependent ( ) || STI . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & LuiMI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScratchReg ) . addMBB ( & DestBB , <STR_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addMBB (


<s> bool hasStdExtZkr ( ) const { return


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch


<s> rvv_switcher rvv ; if ( ! TARGET_VECTOR ) return ; register_builtin_types (


<s> } MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc =


<s> x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec


<s> bool supportsScalableVectors ( ) const { return ST -> hasVInstructions


<s> rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type


<s> } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; if ( XLenVT == <STR_LIT> && IndexVT . getVectorElementType ( ) . bitsGT ( XLenVT ) ) { IndexVT = IndexVT . changeVectorElementType ( XLenVT ) ; SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , Mask . getValueType ( ) , VL ) ; Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ; } unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT ,


<s> if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else { SDValue StepVal = lowerScalarSplat ( SDValue ( ) , DAG . getConstant ( StepValImm , DL , VT . getVectorElementType ( ) ) , VL , VT , DL , DAG , Subtarget ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } } return StepVec


<s> <ISA_LIT>RedundantCopyElimination ( ) : MachineFunctionPass (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } if ( XLen == <NUM_LIT> ) { switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst ::


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SpecialCapReg . Encoding )


<s> bool selectShiftMask32 ( SDValue N , SDValue & ShAmt ) { return selectShiftMask ( N , <NUM_LIT> ,


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , SDValue ( ) , Lo , Hi , VL , DAG ) ; return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Lo , DAG . getRegister


<s> return isImm ( - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> <<


<s> MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( Info . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) )


<s> leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; riscv_block_move_straight ( dest , src , bytes_per_iter ) ; riscv_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; riscv_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg


<s> Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Lo , VL ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ,


<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( <NUM_LIT> ) , Attr ) ) return SDValue ( N , <NUM_LIT> ) ; assert ( ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . hasStdExtZbt ( ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> || Lg2 >= <NUM_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , VT , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add .


<s> unsigned getSEWLMULRatio ( ) const { assert ( isValid ( ) && !


<s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> ,


<s> if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p ( mode ) ; return


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { const bool SrcIsCheri = isCheriPointer (


<s> MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; bool is<ISA_LIT>Vector = false ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector =


<s> if ( DstVT != XLenVT ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Src . getValueType ( ) ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return SDValue ( ) ; EVT SatVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; <STR_LIT> FRM = matchRoundingOp ( Src ) ; if ( FRM == <STR_LIT> ) return SDValue ( ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SDLoc DL (


<s> auto UseMask = [ Mask , Op , VT , & TLO ] ( const APInt & NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ; } ; if ( ShrunkMask . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( Subtarget . hasStdExtZbb ( ) || Subtarget . hasStdExtZbp ( ) ) { APInt NewMask = APInt ( Mask . getBitWidth ( ) , <NUM_LIT> ) ; if ( IsLegalMask ( NewMask ) ) return UseMask ( NewMask ) ; } if ( VT == <STR_LIT> ) { APInt NewMask = APInt ( <NUM_LIT> , <NUM_LIT> ) ; if ( IsLegalMask ( NewMask ) ) return UseMask ( NewMask ) ; } if ( ! ExpandedMask . isNegative ( ) ) return false ; unsigned MinSignedBits = ExpandedMask . getMinSignedBits ( ) ; APInt NewMask = ShrunkMask ; if ( MinSignedBits <= <NUM_LIT> ) NewMask . setBitsFrom


<s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ; return combineSelectAndUseCommutative ( N , DAG


<s> const MCFixup * AUIPCFixup ; const MCFragment * AUIPCDF ; MCValue AUIPCTarget ; switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : AUIPCFixup = & Fixup ; AUIPCDF = DF ; AUIPCTarget = Target ; break ; case <STR_LIT> : case <STR_LIT> : { AUIPCFixup = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( & AUIPCDF ) ; if ( ! AUIPCFixup ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return true ; } const MCExpr * AUIPCExpr = AUIPCFixup -> getValue ( ) ; if ( ! AUIPCExpr -> evaluateAsRelocatable ( AUIPCTarget , & Layout , AUIPCFixup ) ) return true ; break ; } } if ( ! AUIPCTarget . getSymA ( ) || AUIPCTarget . getSymB ( ) ) return false ; const MCSymbolRefExpr * A = AUIPCTarget . getSymA ( ) ; const MCSymbol & SA = A -> getSymbol ( ) ; if ( A -> getKind ( ) != MCSymbolRefExpr :: VK_None || SA . isUndefined ( ) ) return false ; auto * Writer = Asm . getWriterPtr ( ) ; if ( ! Writer ) return false ; bool IsResolved = Writer -> isSymbolRefDifferenceFullyResolvedImpl ( Asm , SA , * AUIPCDF , false , true ) ; if ( ! IsResolved ) return false ; Value = Layout . getSymbolOffset ( SA ) + AUIPCTarget . getConstant ( ) ; Value -= Layout . getFragmentOffset ( AUIPCDF


<s> static bool different_mask_policy_p ( const vector_insn_info & info1 , const vector_insn_info


<s> It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( M . getNamedValue (

MF . getName ( ) ) , <NUM_LIT> , <STR_LIT> ) ) ;


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> bool match_cond_p ( const bool * dems1 , const bool * dems2 ) const { for ( unsigned i = <NUM_LIT> ; i < NUM_DEMAND ; i ++ ) { if ( first [ i ] != DEMAND_ANY && first [ i ] != dems1 [


<s> bool hasVInstructionsF64 ( ) const { return HasStdExtV && hasStdExtD


<s> case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; OffsettingOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; OffsettingOpcode = <STR_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != OffsettingOpcode ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA


<s> if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ; return


<s> return std :: tie ( VLMul , SEW , TailAgnostic , MaskAgnostic ) == std :: tie

( Other . VLMul , Other . SEW , Other . TailAgnostic , Other . MaskAgnostic ) ;


<s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ; return combineSelectAndUseCommutative ( N , DAG


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( *


<s> MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT


<s> auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( C1 && C2 ) { const APInt & C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) )


<s> TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB


<s> return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK


<s> if ( ! SeqStepNum ) SeqStepNum = ValDiff ; else if ( ValDiff != SeqStepNum ) return None ; if ( ! SeqStepDenom ) SeqStepDenom = IdxDiff ; else if ( IdxDiff != * SeqStepDenom ) return None ; } } if ( SeqStepNum && SeqStepDenom ) { uint64_t ExpectedVal = ( int64_t ) ( Idx * ( uint64_t ) * SeqStepNum ) / * SeqStepDenom ; int64_t Addend = SignExtend64 ( Val - ExpectedVal , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return None ; } if ( ! PrevElt || PrevElt -> first != Val ) PrevElt = std ::


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt ::


<s> static void mapping ( IO & YamlIO , <ISA_LIT>MachineFunctionInfo & MFI ) { YamlIO . mapOptional ( <STR_LIT> , MFI


<s> static unsigned second_ratio ( const vector_insn_info & , const vector_insn_info & info2 ) { return info2 . get_ratio


<s> bool isImmZero ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm (


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> typeForCapabilities ( ) ) ; return true ; } } return false


<s> return m_state == VALID || m_state == DIRTY ||


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg

, getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDNode * Op0 = Node -> getOperand ( <NUM_LIT> ) . getNode ( ) ; uint64_t Mask ; if ( isa < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) && isConstantMask ( Op0 , Mask ) ) { uint64_t ShAmt = Node -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 -> getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : assert ( ! Subtarget -> is64Bit ( ) && <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ) ; return ; case <STR_LIT> : { LoadSDNode * Load = cast < LoadSDNode > ( Node ) ; if ( Load -> getAddressingMode ( ) != <STR_LIT> ) break ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Node -> getOperand ( <NUM_LIT> ) ; bool simm12 = false ; bool signExtend = Load -> getExtensionType ( ) == <STR_LIT> ; if ( auto ConstantOffset = dyn_cast < ConstantSDNode > ( Offset ) ) { int ConstantVal = ConstantOffset -> getSExtValue ( ) ; simm12 = isInt < <NUM_LIT> > ( ConstantVal ) ; if ( simm12 ) Offset = CurDAG -> getTargetConstant ( ConstantVal , SDLoc ( Offset ) , Offset . getValueType ( ) ) ; } unsigned Opcode = <NUM_LIT> ; switch ( Load -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ; else if ( simm12 && ! signExtend ) Opcode = <STR_LIT> ; else if ( ! simm12 && signExtend ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; break ; case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ; else if ( simm12 && ! signExtend


<s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( * MF , CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall ) { MachineBasicBlock :: iterator NewMI = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( RestoreLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( MI != MBB . end ( ) && MI -> getOpcode


<s> DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo


<s> auto_vec < size_t > available_list ; for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( ) ; i ++ ) if ( info . available_p ( * vector_exprs [ i ]


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : return true


<s> return reload_completed && cfun -> machine -> frame .


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm

, int64_t Address , const void * Decoder ) {


<s> SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) || ! ( N -> getMachineOpcode ( ) == <STR_LIT> ) ) continue ; SDValue F64Val = N -> getOperand ( <NUM_LIT> ) ; if ( F64Val . isMachineOpcode ( ) && F64Val . getMachineOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump (


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) ,


<s> void <ISA_LIT>InstPrinter :: printBDXAddrOperand ( const MCInst * MI , int OpNum ,


<s> MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr


<s> bool riscv_legitimize_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { riscv_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { riscv_legitimize_const_move ( mode , dest


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) && Op1 . hasOneUse ( ) && Op1 . getOperand ( <NUM_LIT> ) == Mask

&& Op1 . getOperand ( <NUM_LIT> ) == VL ) {


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ; SDValue IdentitySplat = lowerScalarSplat ( NeutralElem , DAG . getConstant ( <NUM_LIT> , DL ,

XLenVT ) , M1VT , DL , DAG , Subtarget ) ;


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> uint64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Value < <NUM_LIT> &&


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X


<s> case VK_<ISA_LIT>_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_HI20 : return


<s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr , FALSE ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) { rtx base = XEXP ( x , <NUM_LIT> ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; if ( optimize_function_for_size_p ( cfun ) && ( strcmp ( current_pass -> name , <STR_LIT> ) == <NUM_LIT> ) && mode == SImode ) addr = riscv_shorten_lw_offset ( base , offset ) ; else addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr ,


<s> return CallsEhReturn && ( FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT>


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) ,


<s> void setIncomingArgSize ( unsigned Size ) { IncomingArgSize = Size


<s> int get_ma ( rtx ma ) { if ( INTVAL ( ma ) == MASK_ANY


<s> emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false


<s> void <ISA_LIT>TargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; auto ParseResult = <STR_LIT> ( STI . hasFeature ( <STR_LIT> ) , STI . getFeatureBits ( ) ) ; if ( ! ParseResult ) { report_fatal_error ( ParseResult . takeError ( ) ) ; } else { auto & ISAInfo = * ParseResult ; emitTextAttribute ( <STR_LIT> , ISAInfo -> toString ( )


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerToScalableOp ( Op , DAG , MaskOpc , false ) ; return lowerToScalableOp ( Op , DAG ,


<s> * loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ; * loop_mem = change_address ( mem ,


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case


<s> if ( Width == <NUM_LIT> ) return getSCForRMW16 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getSCForRMW32 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return


<s> unsigned getCallEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true


<s> return MatchOperand_Success ; } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) .


<s> SDValue Val = Parts [ <NUM_LIT> ] ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) { assert ( PartVTBitSize >= ValueVTBitSize ) ; EVT SameEltTypeVT = ValueVT ; if ( ValueEltVT != PartEltVT ) { unsigned Count = PartVTBitSize / ValueEltVT . getFixedSizeInBits ( ) ; assert ( Count != <NUM_LIT> && <STR_LIT> ) ; SameEltTypeVT = EVT :: getVectorVT ( Context , ValueEltVT , Count , true ) ; Val = DAG . getNode ( <STR_LIT> , DL , SameEltTypeVT , Val ) ; } Val = DAG . getNode ( <STR_LIT> , DL , ValueVT , Val , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; return Val ; } } return SDValue (


<s> break ; default : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? <STR_LIT> : <STR_LIT> ; string = ACONCAT ( ( linkonce , prefix , <STR_LIT> , name , NULL ) ) ; set_decl_section_name ( decl


<s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = Log2_32 ( SEW ) - <NUM_LIT> ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits


<s> setAttributeItem ( Attribute , String ,


<s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ; return true


<s> assert ( hasSEWOp ( TSFlags ) ) ; unsigned Offset = <NUM_LIT> ; if ( hasVecPolicyOp ( TSFlags ) ) Offset = <NUM_LIT> ; return Desc . getNumOperands


<s> bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * DestOp ; if ( ! TII -> isBranch ( I , Cond , DestOp ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> AnalyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; TII -> ReverseBranchCondition ( Cond ) ; TII -> InsertConstBranchAtInst ( MBB , I , <NUM_LIT> , Cond , dl ) ; I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += <NUM_LIT> ; MBBStartOffset += <NUM_LIT> ; ++ NumExpanded ; MadeChange = true ; } } EverMadeChange |= MadeChange ; } BlockSizes . clear (


<s> return isImm ( - ( <NUM_LIT> << <NUM_LIT> ) ,


<s> if ( pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ) return gen_int_mode ( TAIL_UNDISTURBED , Pmode ) ; return gen_int_mode ( get_prefer_tail_policy ( )


<s> int reg_op = load_p ? <NUM_LIT> : <NUM_LIT> ; int mem_op = load_p ? <NUM_LIT> : <NUM_LIT> ; rtx mem1 = plus_constant ( mode , stack_pointer_rtx , offset ) ; mem1 = gen_frame_mem ( mode , mem1 ) ; rtx mem2 = plus_constant ( mode , stack_pointer_rtx , offset2 ) ; mem2 = gen_frame_mem ( mode , mem2 ) ; operands [ reg_op ] = gen_rtx_REG ( mode , regno ) ; operands [ mem_op ] = mem1 ; operands [ <NUM_LIT> + reg_op ] = gen_rtx_REG ( mode ,


<s> static bool riscv_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return riscv_const_insns ( x )


<s> fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPU . empty (


<s> MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Val , Mask , VL ; if ( const auto * VPStore = dyn_cast < VPStoreSDNode > ( Op ) ) { Val = VPStore -> getValue ( ) ; Mask = VPStore -> getMask ( ) ; VL = VPStore -> getVectorLength ( ) ; } else { const auto * MStore = cast < MaskedStoreSDNode > ( Op ) ; Val = MStore -> getValue ( ) ; Mask = MStore -> getMask ( ) ; } bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Val . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT =


<s> MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; SDValue L = DAG . getLoad ( NewVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getOriginalAlign ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getMergeValues ( { DAG . getBitcast ( VT , L ) , L . getValue


<s> void dump ( ) { errs ( ) << <STR_LIT> << this << '\n' ; errs ( ) << <STR_LIT> ; if ( Base . getNode ( ) != <NUM_LIT> ) Base . getNode (


<s> MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMOLo = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineMemOperand * MMOHi = MF . getMachineMemOperand ( MPI . getWithOffset ( <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOLo ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOHi ) ; MI . eraseFromParent ( ) ; return


<s> Inst . addOperand ( MCOperand :: createImm


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS ,

Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType (


<s> case VK_<ISA_LIT>_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI20 : return


<s> return new <ISA_LIT>TargetStreamer (


<s> static unsigned getAbsoluteReloc ( unsigned Kind ) { switch ( Kind )


<s> static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI , MachineBasicBlock * BB ) { assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill


<s> auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getArgOperand


<s> inline unsigned int function_base :: call_properties ( const function_instance & instance ) const { unsigned int flags =


<s> static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target


<s> bool TailAgnostic = true ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) InstrInfo . setAVLImm ( VLOp . getImm


<s> switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT ( ) ,


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue ThreadPointer = DAG . getRegister ( Subtarget . isRV64 (


<s> SDValue Src = DAG . getFreeze ( Op . getOperand ( <NUM_LIT> ) ) ; MVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Src ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; MVT SetccVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ) ; SDValue NeedAdjust = DAG . getSetCC ( DL , SetccVT , Truncated , Src , <STR_LIT> ) ; Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ) ; SDValue NeedAdjust = DAG . getSetCC ( DL , SetccVT , Truncated , Src , <STR_LIT> ) ; Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP ( MaxVal , DL , VT ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src


<s> return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == <NUM_LIT> ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) ,


<s> case Instruction :: Add : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( Imm . getMinSignedBits ( ) <= <NUM_LIT> && getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) { return TTI :: TCC_Free ; } } return getIntImmCost ( Imm , Ty ,


<s> assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( MGN -> getBasePtr ( ) . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( MGN -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( !


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK


<s> if ( auto * CVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; if ( isNullConstant ( Hi ) ) return Lo ; Hi = DAG . getNode ( <STR_LIT> , DL , VecVT , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VecVT , Hi , ThirtyTwoV ) ; return DAG . getNode ( <STR_LIT> , DL


<s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType


<s> else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ; else if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( )


<s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; } if ( Inst . getOpcode (


<s> addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSPILL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , Value , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; else assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; return Value


<s> if ( XLen == <NUM_LIT> ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; }


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> <STR_LIT> ; return Ret


<s> for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { bool handle_reg = TRUE ; if ( epilogue && ! maybe_eh_return && crtl -> calls_eh_return ) { unsigned int i , regnum ; for ( i = <NUM_LIT> ; ( regnum = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( regno == regnum ) { handle_reg = FALSE ; break ; } } if ( handle_reg ) riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P (

cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) {


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef

< ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const {


<s> case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF )


<s> MVT IntVT = VecVT . changeVectorElementTypeToInteger ( ) ; if ( ( MaxVLMAX == <NUM_LIT> || MaxVLMAX > <NUM_LIT> ) && EltSize == <NUM_LIT> ) { if ( MinSize == ( <NUM_LIT> * <STR_LIT> ) ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VecVT ) ; Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , HiVT , Hi ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Hi , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Res , Lo , DAG . getIntPtrConstant ( LoVT . getVectorMinNumElements ( ) , DL ) ) ; } IntVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; GatherOpc = <STR_LIT> ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultScalableVLOps ( VecVT , DL , DAG , Subtarget ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; SDValue VLMinus1 = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && IntVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatVL ; if ( ! IsRV32E64 ) SplatVL = DAG . getSplatVector ( IntVT , DL , VLMinus1 ) ; else SplatVL = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , VLMinus1 , DAG . getRegister


<s> if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB . end ( ) ; MachineInstr & MI = * BuildMI ( MBB , II , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addMBB ( & DestBB , <STR_LIT> ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MI . getIterator ( ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( ScratchReg , Scav


<s> int PlatRegSize = IsRV64 ? <NUM_LIT> : <NUM_LIT> ; int Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq ; generateInstSeq ( Chunk . getSExtValue ( )


<s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_TLS_TPREL32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_TLS_TPREL64 ; } llvm_unreachable ( <STR_LIT>


<s> int getEhDataRegFI ( unsigned Reg ) const { return


<s> } } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) .


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; if ( Kind == KindTy :: Immediate ) { <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; ( void ) IsConstantImm ; assert ( IsConstantImm


<s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C )


<s> static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( ! riscv_v_ext_vector_mode_p ( GET_MODE ( x ) ) && GET_MODE_SIZE ( GET_MODE ( x ) ) . to_constant ( ) == UNITS_PER_WORD * <NUM_LIT> ) return COSTS_N_INSNS ( double_insns ) ; return COSTS_N_INSNS (


<s> std :: unique_ptr < <ISA_LIT>Operand > OptionalImmOp ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { int64_t ImmVal ; SMLoc ImmStart = getLoc ( ) ; if ( getParser ( ) . parseIntToken ( ImmVal , <STR_LIT> ) ) return MatchOperand_ParseFail ; SMLoc ImmEnd = getLoc ( ) ; OptionalImmOp = <ISA_LIT>Operand :: createImm ( MCConstantExpr :: create ( ImmVal , getContext ( ) ) , ImmStart , ImmEnd , isRV64 ( ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , OptionalImmOp ? <STR_LIT> : <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot


<s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> Register Reg = FPR32DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg (


<s> unsigned <ISA_LIT>VType :: encodeVTYPE ( <STR_LIT> VLMUL , unsigned SEW , bool TailAgnostic , bool MaskAgnostic ) { assert ( isValidSEW ( SEW ) && <STR_LIT>


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord

) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;


<s> static rtx riscv_force_binary ( enum machine_mode mode , enum rtx_code code , rtx x , rtx y ) { return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x , y


<s> if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT>


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT>


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( )


<s> bool isLegalMaskedStore ( Type * DataType


<s> offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { enum machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode )


<s> uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; movImm ( MBB , II , DL , N , NumOfVReg , Flag ) ; if ( ! STI . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; } return VL


<s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL

|| VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;


<s> * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : case LTGT : * code = fp_code == LTGT ? GTU : EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; default : gcc_unreachable (


<s> if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ; return true


<s> bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( )


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK ==


<s> void <ISA_LIT>MergeBaseOffsetOpt :: foldOffset ( MachineInstr & HiLUI , MachineInstr & LoADDI , MachineInstr & Tail , int64_t Offset ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; LoADDI . getOperand ( <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG .


<s> assert ( VecVT . isVector ( ) ) ; ElementCount EC = VecVT . getVectorElementCount ( ) ; return <STR_LIT> ( <STR_LIT>


<s> auto * RVFI = MI -> getMF ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> isHwlpBasicBlock ( MBB ) ) AsmPrinter :: EmitToStreamer ( * OutStreamer


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm

) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg -


<s> for ( auto UI = Node -> use_begin ( ) , UE = Node -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : if ( Bits < ( <NUM_LIT> - countLeadingZeros ( User -> getConstantOperandVal ( <NUM_LIT> ) ) ) ) return false ; break ; case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits <


<s> if ( Width == <NUM_LIT> ) return getLRForRMW32 ( Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW64 ( Ordering ) ; llvm_unreachable ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue Addr ; switch ( Model ) { case TLSModel :: LocalExec : Addr = getStaticTLSAddr ( N , DAG , false ) ; break ; case TLSModel :: InitialExec : Addr = getStaticTLSAddr ( N , DAG , true ) ; break ; case TLSModel :: LocalDynamic


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32 ) ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; for ( auto & Arg : Outs ) { if ( ! Arg . Flags . isByVal ( ) ) continue ; report_fatal_error ( <STR_LIT> ) ; } Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } } SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } if ( isa < GlobalAddressSDNode > ( Callee ) ) { Callee = lowerGlobalAddress ( Callee , DAG ) ; } else if ( isa < ExternalSymbolSDNode > ( Callee ) ) { Callee = lowerExternalSymbol ( Callee , DAG ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT>


<s> case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } } return TargetLowering :: getConstraintType (


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > sizeof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> static void doMaskedAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm (


<s> static Align getPrefTypeAlign ( EVT VT


<s> bool <ISA_LIT>Subtarget :: useRVVForFixedLengthVectors ( )


<s> if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI ->

getCallPreservedMask ( MF , CalleeCC ) ;


<s> } else if ( AVLInt >= <NUM_LIT> * MaxVLMAX ) { <STR_LIT> Lmul = <ISA_LIT>TargetLowering :: getLMUL ( I32VT ) ; SDValue LMUL = DAG . getConstant ( Lmul , DL , XLenVT ) ; unsigned Sew = <ISA_LIT>VType :: encodeSEW ( I32VT . getScalarSizeInBits ( ) ) ; SDValue SEW = DAG . getConstant ( Sew , DL , XLenVT ) ; SDValue SETVLMAX = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , SETVLMAX , SEW , LMUL ) ; } else { } } if ( ! I32VL ) { <STR_LIT> Lmul = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SDValue LMUL = DAG . getConstant ( Lmul , DL , XLenVT ) ; unsigned Sew = <ISA_LIT>VType :: encodeSEW ( VT . getScalarSizeInBits ( ) ) ; SDValue SEW = DAG . getConstant ( Sew , DL , XLenVT ) ; SDValue SETVL = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , SETVL , AVL , SEW , LMUL ) ; I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } SDValue I32Mask = getAllOnesMask ( I32VT , I32VL , DL , DAG ) ; SDValue Passthru ; if ( IsMasked ) Passthru = DAG . getUNDEF ( I32VT ) ; else Passthru = DAG . getBitcast ( I32VT , Operands [ <NUM_LIT> ] ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarHi , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarLo , I32Mask , I32VL ) ; } else { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarLo , I32Mask , I32VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Passthru , Vec , ScalarHi , I32Mask , I32VL ) ; } Vec = DAG . getBitcast ( VT , Vec ) ; if ( ! IsMasked ) return Vec ; SDValue Mask = Operands [ NumOps - <NUM_LIT> ] ; SDValue MaskedOff = Operands [


<s> if ( Imm > <NUM_LIT> ) { Imm = ( SignExtend64 < <NUM_LIT> > ( Imm ) & <NUM_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> void add_vundef_operand ( machine_mode mode ) { add_input_operand ( RVV_VUNDEF ( mode ) ,


<s> MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; Register SavedFFlags = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , SavedFFlags ) ; auto MIB = BuildMI ( * BB , MI , DL , TII . get ( RelOpcode ) , DstReg ) . addReg ( Src1Reg ) . addReg ( Src2Reg ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) MIB -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( SavedFFlags , RegState :: Kill ) ; auto MIB2 = BuildMI ( * BB , MI , DL , TII . get ( EqOpcode ) , <STR_LIT> ) . addReg ( Src1Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( Src2Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) MIB2 -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; MI . eraseFromParent ( ) ; return BB


<s> return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT>


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP


<s> bool getManipulatesSP ( ) const { return ManipulatesSP


<s> for ( int i = <NUM_LIT> ; i < n ; i ++ ) if ( !

SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return <NUM_LIT> ;


<s> emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT>


<s> return ( major * <NUM_LIT> ) + ( minor *


<s> addPass ( new RegBankSelect ( ) ) ; return false


<s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ; return combineSelectAndUseCommutative ( N , DAG


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ) return false ; Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ; return Res . getSymB ( ) ?

getKind ( ) == VK_<ISA_LIT>_None : true ;


<s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = encodeSEW ( SEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ; if ( MaskAgnostic )


<s> StringRef getPassName ( ) const override { return


<s> bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM


<s> <STR_LIT> FRM = <STR_LIT> ( SE -> getSymbol ( ) . getName ( ) ) ; assert ( FRM != <STR_LIT> &&


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; if ( Subtarget . hasStdExtA ( )


<s> assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return


<s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : <NUM_LIT> * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode


<s> ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; return getAddr ( N , Ty , DAG


<s> InstructionCost <ISA_LIT>TTIImpl :: getSpliceCost ( VectorType * Tp , int Index ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost (


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . getReturnType ( ) -> isVoidTy ( ) ) report_fatal_error ( <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction (


<s> return info1 . get_ratio ( ) != info2


<s> void pushFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ; FeatureBitStack . push_back ( getSTI ( ) .


<s> if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> )


<s> StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ; Prev = c ; } return


<s> <STR_LIT> ABI = Subtarget . getTargetABI ( ) ; if ( ( ABI == <STR_LIT> || ABI == <STR_LIT> )

&& ( Type == <STR_LIT> ) ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> return isMem ( RegKind , HasIndex ) && inRange ( Mem