<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumDstElts = VT . getVectorNumElements ( ) ; unsigned DstBitsPerElt = VT . getScalarSizeInBits ( ) ; unsigned SrcBitsPerElt = <NUM_LIT> * DstBitsPerElt ; assert ( N0 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && N1 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && <STR_LIT> ) ; bool IsSigned = ( <STR_LIT> == Opcode ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ( N0 . isUndef ( ) || N -> isOnlyUserOf ( N0 . getNode ( ) ) ) && ( N1 . isUndef ( ) || N -> isOnlyUserOf ( N1 . getNode ( ) ) ) && getTargetConstantBitsFromNode ( N0 , SrcBitsPerElt , UndefElts0 , EltBits0 ) && getTargetConstantBitsFromNode ( N1 , SrcBitsPerElt , UndefElts1 , EltBits1 ) ) { unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSrcElts = NumDstElts / <NUM_LIT> ; unsigned NumDstEltsPerLane = NumDstElts / NumLanes ; unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes ; APInt Undefs ( NumDstElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > Bits ( NumDstElts , APInt :: getNullValue ( DstBitsPerElt ) ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( unsigned Elt = <NUM_LIT> ; Elt != NumDstEltsPerLane ; ++ Elt ) { unsigned SrcIdx = Lane * NumSrcEltsPerLane + Elt % NumSrcEltsPerLane ; auto & UndefElts = ( Elt >= NumSrcEltsPerLane ? UndefElts1 : UndefElts0 ) ; auto & EltBits = ( Elt >= NumSrcEltsPerLane ? EltBits1 : EltBits0 ) ; if ( UndefElts [ SrcIdx ] ) { Undefs . setBit ( Lane * NumDstEltsPerLane + Elt ) ; continue ; } APInt & Val = EltBits [ SrcIdx ] ; if ( IsSigned ) { if ( Val . isSignedIntN ( DstBitsPerElt ) ) Val = Val . trunc ( DstBitsPerElt ) ; else if ( Val . isNegative ( ) ) Val = APInt :: getSignedMinValue ( DstBitsPerElt ) ; else Val = APInt :: getSignedMaxValue ( DstBitsPerElt ) ; } else { if ( Val . isIntN ( DstBitsPerElt ) ) Val = Val . trunc ( DstBitsPerElt ) ; else if ( Val . isNegative ( ) ) Val = APInt :: getNullValue ( DstBitsPerElt ) ; else Val = APInt :: getAllOnesValue ( DstBitsPerElt


<s> rtx reg ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode ,


<s> if ( ShrunkMask == <NUM_LIT> ) return false ; if ( ExpandedMask == ~ <NUM_LIT> ) return TLO . CombineTo ( Op , Op . getOperand ( <NUM_LIT> ) ) ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( unsigned Mask ) -> bool { return ( ShrunkMask & Mask ) == ShrunkMask && ( ~ ExpandedMask & Mask ) == <NUM_LIT> ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( unsigned NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ; } ; if ( IsLegalMask ( <NUM_LIT> ) ) return UseMask ( <NUM_LIT> ) ; if ( IsLegalMask ( <NUM_LIT> ) ) return UseMask ( <NUM_LIT>


<s> return ( int ) __builtin_ia32_vcvtsh2usi32_round ( __A


<s> const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ?


<s> void <ISA_LIT>TargetLowering :: addTypeForNEON ( MVT VT , MVT PromotedLdStVT , MVT PromotedBitwiseVT ) { if ( VT != PromotedLdStVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedLdStVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedLdStVT ) ; } MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ElemTy == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT


<s> return new <ISA_LIT>ExpandPseudo ( )


<s> bool isLegalMaskedLoadStore ( Type * DataType , MaybeAlign Alignment ) { if ( ! isa < VectorType > ( DataType ) || ! ST -> hasSVE ( ) ) return false ; Type * Ty = DataType -> getVectorElementType ( ) ; if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty ->

isIntegerTy ( <NUM_LIT> ) ) return true ;


<s> } if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) return


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( MachineFunction & MF ,


<s> bool WriteNopData ( uint64_t Count , MCObjectWriter *


<s> MachineBasicBlock * NewDest = BMI -> getOperand ( BMITargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MI -> setDesc ( TII -> get ( OppositeBranchOpcode ) ) ; BMI -> getOperand ( BMITargetOperand ) . setMBB ( DestBB ) ; MI -> getOperand ( TargetOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( * MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) .


<s> Register BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int Offset = getLdStOffsetOp ( MemMI ) . getImm ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( ! isTagStore ( MemMI ) ) { bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT .


<s> if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( Opcode , DL , { LoadVT , <STR_LIT> } , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( VT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load , LoadChain }


<s> MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNode ( <STR_LIT> , dl , VT , A ,


<s> AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV


<s> unsigned rD = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rS = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int imm14 = SignExtend32 < <NUM_LIT> > ( ( Insn >> <NUM_LIT> ) & <NUM_LIT> ) ; rD = get<ISA_LIT>RegisterFromNumbering ( rD ) ; rS = get<ISA_LIT>RegisterFromNumbering ( rS ) ; Inst . addOperand ( MCOperand ::


<s> SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg (


<s> bool <ISA_LIT>InstPrinter :: printAlias ( const MCInst * MI ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get


<s> unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >=


<s> MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; const int InitialVectorSize ( <NUM_LIT> ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst


<s> SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew ; if ( Data . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , N -> getOperand (


<s> SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; <STR_LIT> ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> :: INVALID ) return Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement ) )


<s> bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return


<s> rtx loongarch_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( TM . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( <STR_LIT> ) ; else Reserved . reset ( <STR_LIT> ) ; } } if ( TFI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . is<ISA_LIT>64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( <STR_LIT> ) ; else Reserved . set ( <STR_LIT>


<s> return ( poly16x8x2_t ) { vtrn1q_p16 ( a , b


<s> MVT getLegalVectorType ( Packing P , MVT ElemVT ) { return <STR_LIT> ( ElemVT , P == Packing :: Normal ? StandardVectorWidth :


<s> if ( ( is2Addr && Entry . PredCC2 == <NUM_LIT> ) || ( ! is2Addr && Entry . PredCC1 == <NUM_LIT> ) ) { if ( Pred == <STR_LIT> ) { if ( ! HasCC ) { if ( ! LiveCPSR ) { HasCC = true ; CCDead = true ; return true ; } return false ; } } else { if ( HasCC ) return


<s> inline vector signed int vec_sl ( vector signed int a1 , vector unsigned int a2


<s> if ( TARGET_64BIT ) return xstrdup ( <STR_LIT> ) ; else return xstrdup


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand (


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return &


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned


<s> TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; } TS . emitDirectiveEnd ( CurrentFnSym -> getName ( ) ) ; if ( ! InConstantPool ) return ; InConstantPool = false ; OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd


<s> inline int vec_any_ge ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgefp_p ( __CR6_EQ_REV , a1 ,


<s> void <ISA_LIT>SEInstrInfo :: expandEhReturn ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { <ISA_LIT>ABIInfo ABI = Subtarget . getABI ( ) ; unsigned ADDU = ABI . GetPtrAdduOp ( ) ; unsigned SP = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned RA = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned T9 = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; if ( TM . isPositionIndependent ( ) ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , T9 ) . addReg ( TargetReg


<s> } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; } setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT ,


<s> MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; } MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI (


<s> if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , true , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG .


<s> return ( ( ( mode == HFmode || mode == BFmode ) && TARGET_SSE2 ) ? true


<s> * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . load + extra_cost -> ldst . load_unaligned ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true ; case UNSPEC_UNALIGNED_STORE : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE (


<s> bool ExpandPseudo :: expandCopyACC ( MachineBasicBlock & MBB , Iter I , unsigned MFHiOpc , unsigned MFLoOpc ) { unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = RegInfo . getMinimalPhysRegClass ( Dst ) ; unsigned VRegSize = RegInfo . getRegSizeInBits ( * DstRC ) / <NUM_LIT> ; const TargetRegisterClass * RC = RegInfo . intRegClass ( VRegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc ) , VR0 ) . addReg ( Src ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , DstLo ) . addReg ( VR0


<s> StringRef getPassName ( ) const override { return


<s> return ( Attributes & <ISA_LIT>FMA3KZeroMasked ) !=


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = llvm :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( VR2 ) . addMBB ( FBB ) . addReg ( VR1 ) . addMBB ( TBB ) ; MI -> eraseFromParent


<s> if ( mode == CCFPmode ) code = reverse_condition_maybe_unordered ( code ) ; else code = reverse_condition ( code ) ; } if ( ( ! TARGET_FPRS && TARGET_HARD_FLOAT ) && mode == CCFPmode ) { switch ( code ) { case EQ : code = GT ; break ; case NE : code = UNLE ; break ; default : gcc_unreachable ( ) ; } } switch ( code ) { case NE : case LTGT : ccode = <STR_LIT> ; break ; case EQ : case UNEQ : ccode = <STR_LIT> ; break ; case GE : case GEU : ccode = <STR_LIT> ; break ; case GT : case GTU : case UNGT : ccode = <STR_LIT> ; break ; case LE : case LEU : ccode = <STR_LIT> ; break ; case LT : case LTU : case UNLT : ccode = <STR_LIT> ; break ; case UNORDERED : ccode = <STR_LIT> ; break ; case ORDERED : ccode = <STR_LIT> ; break ; case UNGE : ccode = <STR_LIT> ; break ; case UNLE : ccode = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } pred = <STR_LIT> ; note = find_reg_note ( insn , REG_BR_PROB , NULL_RTX ) ; if ( note != NULL_RTX ) { int prob = XINT ( note , <NUM_LIT> ) - REG_BR_PROB_BASE / <NUM_LIT> ; if ( rs6000_always_hint || ( abs ( prob ) > REG_BR_PROB_BASE / <NUM_LIT> * <NUM_LIT> && br_prob_note_reliable_p ( note ) ) ) { if ( abs ( prob ) > REG_BR_PROB_BASE / <NUM_LIT> && ( ( prob > <NUM_LIT> ) ^ need_longbranch ) ) pred = <STR_LIT> ; else pred = <STR_LIT> ; } } if ( label == NULL ) s += sprintf ( s , <STR_LIT> , ccode , pred ) ; else s += sprintf ( s , <STR_LIT> , ccode ,


<s> static section * aarch64_select_rtx_section ( machine_mode mode ATTRIBUTE_UNUSED , rtx x


<s> assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT>


<s> static DecodeStatus DecodeMRSOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { return DecodeSysRegOperand ( <STR_LIT> ( ) , Inst


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize32 : ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT>


<s> } unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( ! Subtarget -> useConstIslands ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align ==


<s> return Kind == Immediate && isUInt < <NUM_LIT> >


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned LOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; unsigned CSOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigOldVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned CmpVal = MRI . createVirtualRegister ( RC ) ; unsigned SwapVal = MRI . createVirtualRegister ( RC ) ; unsigned StoreVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryOldVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryCmpVal = MRI . createVirtualRegister ( RC ) ; unsigned RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) .

addReg ( RetryOldVal ) . addMBB ( SetMBB ) ;


<s> { std :: make_tuple ( false , false , false ) , <STR_LIT> } , { std :: make_tuple ( false , false , true ) , <STR_LIT> } , { std :: make_tuple ( false , true , false ) , <STR_LIT> } , { std :: make_tuple ( false , true , true ) , <STR_LIT> } , { std :: make_tuple ( true , false , false ) , <STR_LIT> } , { std :: make_tuple ( true , false , true ) , <STR_LIT> } , { std :: make_tuple (

true , true , false ) , <STR_LIT> } , { std :: make_tuple ( true , true , true ) , <STR_LIT> } , } ;


<s> static inline <STR_LIT> getMemExtendType ( unsigned Imm ) { return getExtendType ( ( Imm >> <NUM_LIT> ) &


<s> BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm ) ; } else { Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( StoreVal ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; } MI . eraseFromParent (


<s> Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> static bool arm_cxx_guard_mask_bit ( void ) { return TARGET_AAPCS_BASED


<s> static void rs6000_xcoff_file_end ( void ) { switch_to_section ( text_section ) ; if ( xcoff_tls_exec_model_detected


<s> while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name


<s> } LoadSDNode * LD = cast < LoadSDNode > ( Base ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList Tys = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) } ; SDValue ResNode = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG ) ; TLO . CombineTo ( SDValue ( Base , <NUM_LIT> )


<s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> } case <STR_LIT> :: offset16_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset16_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset16_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_64 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_64 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: SSECC : case <STR_LIT> :: u8imm : case <STR_LIT> :: i1imm : case <STR_LIT> :: i8imm : case <STR_LIT> :: i16imm : case <STR_LIT> :: i16i8imm : case <STR_LIT> :: i32imm : case <STR_LIT> :: i32i8imm : case <STR_LIT> :: i32u8imm : case <STR_LIT> :: i64i8imm : case <STR_LIT> :: i64i32imm : case <STR_LIT> :: i64imm : { Res = ConstantInt :: get ( cast < IntegerType > ( getResultTy ( <NUM_LIT> ) ) , getImmOp ( MIOpNo ) ) ; break ; } case <STR_LIT> :: i64i32imm_pcrel : case <STR_LIT> :: brtarget : case <STR_LIT> :: brtarget8 : case <STR_LIT> :: brtarget16 : case <STR_LIT> ::


<s> unsigned Offset ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; Offset = DotDisp . getZExtValue ( ) ; } else if ( isParsingMSInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { std :: pair < StringRef , StringRef > BaseMember = DotDispStr .


<s> getHazardType ( SUnit * SU , int Stalls ) { return ( fitsIntoCurrentGroup ( SU ) ? NoHazard : Hazard


<s> { <STR_LIT> , winnt_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers


<s> if ( DECL_BUILT_IN_CLASS ( fndecl ) == BUILT_IN_MD ) { enum ix86_builtins fn_code = ( enum ix86_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; if ( fn_code == IX86_BUILTIN_CPU_IS || fn_code == IX86_BUILTIN_CPU_SUPPORTS ) { gcc_assert ( n_args == <NUM_LIT> ) ; return fold_builtin_cpu ( fndecl , args ) ; } } return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE


<s> one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) { if ( do_floor && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( tmp , tmp , res , mask ) ; } emit_move_insn ( res , tmp ) ; emit_label ( label


<s> LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( )

, RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op2 = MI . getOperand ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || Register :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op = & Op1 ; if ( Op && Op -> isReg ( ) && Op -> getReg ( ) == Op2 . getReg ( ) && Coef > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( Coef + <NUM_LIT> ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg <


<s> virtual bool isFMAFasterThanMulAndAdd (


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> emitRRI ( <STR_LIT> , DstReg , SrcReg , ShiftAmount - <NUM_LIT> , IDLoc , Instructions ) ; return ; } emitRRI ( <STR_LIT> , DstReg , SrcReg ,


<s> if ( isa < PointerType > ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return true ; return EqualTypeSize ( I -> getOperand ( <NUM_LIT> ) ) ; case Instruction :: Call : { auto * Call = cast < CallInst > ( I ) ; return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; } } } else if ( isa < Constant > ( V ) && ! isa < ConstantExpr > ( V ) ) { return isSupportedType ( V ) ; } else if ( isa < Argument > ( V ) ) return isSupportedType ( V ) ; return isa < BasicBlock > ( V


<s> Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment ( ) ) ) return false ; UpdateValueMap ( I ,


<s> bool <ISA_LIT>FastISel :: IsMemCpySmall ( uint64_t Len , unsigned Alignment


<s> SDValue <ISA_LIT>TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> return sh_media_LDHI_L ( p , <NUM_LIT> ) | sh_media_LDLO_L ( p , <NUM_LIT> ) ; return sh_media_LDLO_L ( p , <NUM_LIT> ) | sh_media_LDHI_L


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc StartLoc , SMLoc EndLoc , bool NeedRewrite = true ) { <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Immediate , StartLoc , EndLoc ) ; Res -> Imm . Val = Val ; Res -> Imm . NeedAsmRewrite = NeedRewrite ; return Res


<s> APInt ImmVal = Imm ; if ( BitSize % <NUM_LIT> != <NUM_LIT> ) ImmVal = Imm . sext ( alignTo ( BitSize , <NUM_LIT> ) ) ; InstructionCost Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < BitSize ; ShiftVal += <NUM_LIT> ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( <NUM_LIT> ) ; int64_t Val = Tmp . getSExtValue (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getMemOffset ( ) ; addExpr ( Inst ,


<s> bool require_stack_frame = false ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { require_stack_frame = true ; if ( check_stack_slot ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , * iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) { unsigned int alignment = MEM_ALIGN ( * iter ) ; if ( alignment > stack_alignment


<s> return __builtin_aarch64_smaxv2df ( __a ,


<s> } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT>


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken ) { return true


<s> newstr [ <NUM_LIT> ] = '@' ; strcpy ( newstr + <NUM_LIT> , str ) ; XSTR ( XEXP ( rtl , <NUM_LIT> ) , <NUM_LIT> ) = ggc_alloc_string ( newstr , len + <NUM_LIT> ) ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CONSTANT ( decl ) || ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl )

&& ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , <NUM_LIT> ) ) = <NUM_LIT> ;


<s> EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { VT = VT . changeVectorElementTypeToInteger ( ) ; ElementCount EC = VT . getVectorElementCount ( ) ; auto ScalarIntVT = <STR_LIT> ( <STR_LIT> / EC . getKnownMinValue ( ) ) ; PassThru = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ScalarIntVT , EC ) , PassThru ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru . getSimpleValueType ( ) , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode ,


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root


<s> case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; assert ( ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Inst . getOperand ( <NUM_LIT> ) . isExpr ( ) ) && <STR_LIT> ) ; return expandLoadAddress ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Inst . getOperand ( <NUM_LIT> ) , Inst . getOpcode ( ) == <STR_LIT> , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandBranchImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } Register ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ]


<s> if ( isa < FrameIndexSDNode > ( Addr ) ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { ; } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr . getOperand ( <NUM_LIT> ) ; Index = Addr . getOperand ( <NUM_LIT>


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg


<s> static unsigned getRegOperandNumElts ( const MCInst * MI , unsigned ScalarSize , unsigned


<s> fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i <= curr_ovld ; i ++ ) { fprintf ( init_file , <STR_LIT> , ovlds [ i ] . ovld_id_name ) ; fprintf ( init_file , <STR_LIT> , ovlds [ i ] . proto . bifname ) ; fprintf ( init_file , <STR_LIT> , ovlds [ i ] . bif_id_name ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; if ( i < curr_ovld && ! strcmp ( ovlds [ i + <NUM_LIT> ] . proto . bifname , ovlds [ i ] . proto . bifname ) ) fprintf ( init_file , <STR_LIT>

, ovlds [ i + <NUM_LIT> ] . ovld_id_name ) ;


<s> MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand MMO ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , MFI . getObjectOffset ( FI ) + Offset , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) .


<s> unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } unsigned ResultReg = <NUM_LIT> ; if ( Subtarget -> useMovt ( * FuncInfo . MF ) ) ResultReg = fastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; if ( ResultReg ) return ResultReg ; if ( VT != <STR_LIT> ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .

get ( <STR_LIT> ) , ResultReg ) . addConstantPoolIndex ( Idx ) ) ;


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const { if ( ! getSubExpr ( ) -> EvaluateAsRelocatable ( Res , Layout ) ) return false ; Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) ,


<s> if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ; In = DAG . getNode ( Op . getOpcode ( ) , dl , CastVT , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { unsigned CastOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CastVT = VT . changeVectorElementTypeToInteger (


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : BytesInStackArgArea ( <NUM_LIT> ) , ArgumentStackToRestore ( <NUM_LIT> ) , HasStackFrame ( false ) , NumLocalDynamicTLSAccesses ( <NUM_LIT> ) , VarArgsStackIndex ( <NUM_LIT> ) , VarArgsGPRIndex ( <NUM_LIT> ) , VarArgsGPRSize ( <NUM_LIT> ) , VarArgsFPRIndex ( <NUM_LIT> ) , VarArgsFPRSize ( <NUM_LIT> ) , IsSplitCSR ( false ) , StackRealigned ( false ) , CalleeSaveStackHasFreeSpace ( false ) { ( void ) MF


<s> EVT Op1VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ResVT = Val . getValueType ( ) ; if ( ResVT . getScalarSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; bool ValidTypeForStoreFltAsInt = ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> || ( Subtarget . hasP9Vector ( ) && ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> ) ) ) ; if ( ResVT == <STR_LIT> || ! Subtarget . hasP8Vector ( ) || cast < StoreSDNode > ( N ) -> isTruncatingStore ( ) || ! ValidTypeForStoreFltAsInt ) return SDValue ( ) ; if ( ResVT . getScalarSizeInBits ( ) == <NUM_LIT> ) { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; } unsigned ConvOpcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( ConvOpcode , dl , ResVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; unsigned ByteSize = Op1VT . getScalarSizeInBits ( )


<s> MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB )


<s> const <ISA_LIT>GOTPLT & <ISA_LIT>GNULDBackend :: getGOTPLT ( ) const { assert ( m_pGOTPLT != NULL


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue


<s> if ( isa < FixedVectorType > ( DataType ) || ! ST -> hasSVE ( ) ) return false ; return isLegalElementTypeForSVE ( DataType -> getScalarType ( )


<s> PermuteImm = ( unsigned ) ShiftAmt ; return true ; } } if ( ContainsZeros ) return false ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return SM_SentinelUndef <= M && M < ( int ) NumMaskElts ; } ) && <STR_LIT> ) ; unsigned InputSizeInBits = MaskVT . getSizeInBits ( ) ; unsigned MaskScalarSizeInBits = InputSizeInBits / Mask . size ( ) ; MVT MaskEltVT = <STR_LIT> ( MaskScalarSizeInBits ) ; if ( MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } return false ; } return false ; } if ( MaskScalarSizeInBits != <NUM_LIT> && MaskScalarSizeInBits != <NUM_LIT> ) return false ; if ( ( AllowFloatDomain && ! AllowIntDomain ) && ! Subtarget . hasAVX ( ) ) return false ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) { AllowFloatDomain = true ; AllowIntDomain =


<s> break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: MEK_CALL_LO16 ; break ; case <STR_LIT> : return MCOperand ( ) ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = AsmPrinter . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_MCSymbol : Symbol = MO . getMCSymbol ( ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( Offset ) { assert ( Offset > <NUM_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , * Ctx ) , * Ctx ) ; } if ( IsGpOff ) Expr = <ISA_LIT>MCExpr :: createGpOff ( TargetKind , Expr , * Ctx ) ; else if ( TargetKind != <ISA_LIT>MCExpr :: MEK_None ) Expr = <ISA_LIT>MCExpr :: create ( TargetKind , Expr


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) ,


<s> if ( WlsInstr ) return WlsInstr ; if ( Predecessor -> pred_size ( ) == <NUM_LIT> ) return findWLSInBlock ( * Predecessor -> pred_begin ( ) ) ; return nullptr


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX512 ( ) ) { int Idx = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT .


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv ( Context


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , TargetLowering :: CallLoweringInfo & CLI ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> , CLI ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( VA . isUpperBitsInLoc ( ) ) { unsigned ValSizeInBits = Ins [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits


<s> MachineInstr * PrevMI = std :: prev ( MBBI ) ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> ) && <STR_LIT> ) ; PrevMI -> setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; PrevMI -> copyImplicitOps ( * MBB . getParent ( ) , & * MBBI


<s> return __builtin_mve_vnegq_fv4sf ( __a )


<s> bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return


<s> int <ISA_LIT>ABIInfo :: EhDataRegSize ( ) const { if ( ThisABI == <STR_LIT> ) return <NUM_LIT> ; else return <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II ,

const DebugLoc & DL , unsigned & NewImm ) const {


<s> for ( insn = NEXT_INSN ( as_a < rtx_insn * > ( x ) ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , <NUM_LIT> ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4 : case UNSPECV_CONST8 : XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) = const1_rtx ; break ; case UNSPECV_WINDOW_END : if ( XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) == x ) return lab ; break ; case UNSPECV_CONST_END


<s> static SDValue LowerVectorIntUnary ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned SrcNumElems = Src . getSimpleValueType ( ) . getVectorNumElements ( ) ; SDValue Lo = extractSubVector ( Src , <NUM_LIT> , DAG , dl , SizeInBits / <NUM_LIT> ) ; SDValue Hi = extractSubVector ( Src , SrcNumElems / <NUM_LIT> , DAG , dl , SizeInBits / <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType (


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return ResNode


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo (


<s> if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode


<s> if ( Features & <STR_LIT> ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features & <STR_LIT> || Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; <ISA_LIT>ELFStreamer & MEF = static_cast < <ISA_LIT>ELFStreamer & > ( Streamer ) ; MEF . Emit<ISA_LIT>OptionRecords ( )


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ~ ( ~ ImmValue & ~ ( ~ ImmValue + <NUM_LIT> ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue . countPopulation ( ) , EltTy ) ; return true ; } } return false


<s> NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( MaskVal >> ShiftVal != <NUM_LIT> ) && ( ( CmpVal >> ShiftVal ) << ShiftVal ) == CmpVal && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( MaskVal << ShiftVal != <NUM_LIT> ) && ( ( CmpVal << ShiftVal ) >> ShiftVal ) == CmpVal && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; }


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI = <NUM_LIT> ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true


<s> if ( Size >= <NUM_LIT> && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) { return <STR_LIT> ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget . is64Bit ( ) &&


<s> case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HA : OS << <STR_LIT> ; break ; } OS << '(' ; getSubExpr ( ) -> print ( OS ) ; OS << ')' ; } else { getSubExpr ( ) -> print ( OS ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; return ret


<s> if ( type != <NUM_LIT> ? INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_INT ) return false ; if ( mips_abi == ABI_O64 ) if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi !=


<s> case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; case <STR_LIT> : NegateOperand = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; } LoadSDNode * LoadNode = nullptr ; SDValue InputChain ; if ( ! isFusableLoadOpStorePattern ( StoreNode , StoredVal , CurDAG , LoadNode , InputChain ) ) return false ; SDValue Operand = StoredVal . getOperand ( <NUM_LIT> ) ; auto * OperandC = dyn_cast < ConstantSDNode > ( Operand ) ; if ( ! OperandC ) return false ; auto OperandV = OperandC -> getAPIntValue ( ) ; if ( NegateOperand ) OperandV = - OperandV ; if ( OperandV . getMinSignedBits ( ) > <NUM_LIT> ) return false ; Operand = CurDAG -> getTargetConstant ( OperandV , DL , MemVT ) ; SDValue Base , Disp ; if ( ! selectBDAddr20Only ( StoreNode -> getBasePtr ( ) , Base , Disp ) ) return false ; SDValue Ops [ ] = { Base , Disp , Operand , InputChain } ; MachineSDNode * Result = CurDAG -> getMachineNode ( NewOpc , DL


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , MCAssembler & A ) { return new <ISA_LIT>AsmBackend ( T


<s> inline static <STR_LIT> A64StringToCondCode ( StringRef CondStr ) { return StringSwitch < <STR_LIT> > ( CondStr . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> void aarch64_sve_op_count :: dump ( ) const { <STR_LIT> (


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target &


<s> if ( <STR_LIT> ( SrcReg ) ) SrcRegNum |= <NUM_LIT> ; return ( ~ SrcRegNum


<s> const char * pa_output_mul_insn ( int unsignedp ATTRIBUTE_UNUSED , rtx_insn


<s> break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ; ImmMask <<=


<s> Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t Offset = EltSize * i ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue OffsetVal = DAG . getConstant ( Offset , dl , PtrVT ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , OffsetVal ) ; Vals [ i ] = DAG . getLoad ( ElementType , dl , Ch , ScalarAddr , MachinePointerInfo ( ) ) ; } } for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; uint64_t IdxVal = cast < ConstantSDNode > ( Idx )


<s> MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( )


<s> mode = GET_MODE ( reg ) ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return NULL_RTX ; if ( register_no_elim_operand ( reg , mode ) ) return reg ; } return NULL_RTX


<s> unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; return ; } BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps (


<s> NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) &


<s> else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , <NUM_LIT> ) ; } else { if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold


ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) {


<s> Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; if ( Subtarget -> isTargetWindows ( ) && Addr . getGlobalValue ( ) && Addr . getGlobalValue ( ) -> hasExternalWeakLinkage ( ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( Addr . getGlobalValue ( ) ) CallReg = materializeGV ( Addr . getGlobalValue ( ) ) ; else if ( Addr . getReg ( ) ) CallReg = Addr . getReg ( ) ; if ( ! CallReg ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; CallReg = constrainOperandRegClass ( II , CallReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( CallReg ) ; } for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrRegImm11 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> )


<s> if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) .


<s> if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 ) ; else pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return


<s> static int FindInTable ( const <ISA_LIT>CostTblEntry * Tbl , unsigned len , int ISD , MVT Ty ) { for ( unsigned int i = <NUM_LIT> ; i < len ; ++ i ) if ( Tbl [ i ] . ISD == ISD && Tbl [ i ] . Type == Ty ) return i ; return -


<s> int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU )


<s> if ( ! TARGET_SSE ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; } if ( ! TARGET_MPX ) for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) fixed_regs [


<s> static reg_class_t ix86_spill_class ( reg_class_t rclass , machine_mode mode ) { if ( <NUM_LIT> && TARGET_GENERAL_REGS_SSE_SPILL && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_INTER_UNIT_MOVES_FROM_VEC && ( mode == SImode || ( TARGET_64BIT && mode

== DImode ) ) && INTEGER_CLASS_P ( rclass ) ) return ALL_SSE_REGS ;


<s> if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) error ( <STR_LIT> , <STR_LIT> , csky_active_target . arch_pp_name ) ; else if ( csky_fpu_index == TARGET_FPU_auto ) error ( <STR_LIT> ) ; else { csky_selected_fpu = & all_fpus [ csky_fpu_index ] ; sbitmap fpu_bits = sbitmap_alloc ( CSKY_ISA_FEATURE_GET ( max ) ) ; csky_initialize_isa ( fpu_bits , csky_selected_fpu -> isa_bits ) ; bitmap_ior ( csky_active_target . isa , csky_active_target . isa , fpu_bits ) ; sbitmap_free ( fpu_bits ) ; } } else { if ( TARGET_DOUBLE_FLOAT > <NUM_LIT> ) warning ( <NUM_LIT> , <STR_LIT> ) ; TARGET_DOUBLE_FLOAT = <NUM_LIT> ; if ( TARGET_FDIVDU > <NUM_LIT> ) warning ( <NUM_LIT> , <STR_LIT> ) ; TARGET_FDIVDU = <NUM_LIT> ; } { \ csky_arch_isa_features [ CSKY_ISA_FEATURE_GET ( IDENT ) ] = \ bitmap_bit_p ( csky_active_target . isa , CSKY_ISA_FEATURE_GET ( IDENT ) ) ; \ } if ( TARGET_ELRW == - <NUM_LIT> ) TARGET_ELRW = CSKY_TARGET_ARCH ( CK801 ) ; if ( ! TARGET_DSP ) TARGET_DSP = CSKY_ISA_FEATURE ( dsp ) ; if ( TARGET_DIV == - <NUM_LIT> ) TARGET_DIV = CSKY_ISA_FEATURE ( div ) ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && ! TARGET_CONSTANT_POOL ) error ( <STR_LIT> , <STR_LIT> , csky_active_target . arch_pp_name ) ; else if ( TARGET_CONSTANT_POOL == - <NUM_LIT> ) TARGET_CONSTANT_POOL = ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) ; if ( TARGET_MINI_REGISTERS > <NUM_LIT> && TARGET_HIGH_REGISTERS > <NUM_LIT> ) error ( <STR_LIT> ) ; else if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ||


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement


<s> paddh_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_paddh_s ( s , t


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrModePC ( SDValue N , SDValue &


<s> if ( IsFP && ! Subtarget . hasSSE3 ( ) ) return Op ; if ( ! IsFP && ! Subtarget . hasSSSE3 ( ) ) return Op ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> || LHS . getOperand ( <NUM_LIT> ) != RHS . getOperand ( <NUM_LIT> ) || ! isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) || ! shouldUseHorizontalOp ( true , DAG , Subtarget ) ) return Op ; unsigned HOpcode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned LExtIndex = LHS . getConstantOperandVal ( <NUM_LIT> ) ; unsigned RExtIndex = RHS . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( LExtIndex & <NUM_LIT> ) == <NUM_LIT> && ( RExtIndex & <NUM_LIT> ) == <NUM_LIT> && ( HOpcode == <STR_LIT> || HOpcode == <STR_LIT> ) ) std :: swap ( LExtIndex , RExtIndex ) ; if ( ( LExtIndex & <NUM_LIT> ) != <NUM_LIT> || RExtIndex != ( LExtIndex + <NUM_LIT> ) ) return Op ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; EVT VecVT = X . getValueType ( ) ; unsigned BitWidth = VecVT . getSizeInBits ( ) ; unsigned NumLanes = BitWidth / <NUM_LIT> ; unsigned NumEltsPerLane = VecVT . getVectorNumElements ( ) / NumLanes ; assert ( ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> )


<s> return ( __m512 ) __builtin_ia32_vcvtph2ps512_mask ( ( __v16hi ) __A , (


<s> void <ISA_LIT>FlagsCopyLoweringPass :: rewriteCopy ( MachineInstr & MI , MachineOperand & FlagUse , MachineInstr & CopyDefI ) { MRI -> replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , CopyDefI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent (


<s> assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Context , MCAsmBackend & MAB

, raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) {


<s> SDValue Ops [ ] = { DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( CCValid , DL , <STR_LIT> ) , DAG . getTargetConstant ( CCMask , DL , <STR_LIT> ) , CCReg } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> } } if ( LogicOp And = interpretAndImmediate ( Opcode ) ) { uint64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == <NUM_LIT> ) { NewOpcode = <STR_LIT> ; if ( STI . hasMiscellaneousExtensions ( ) ) NewOpcode = <STR_LIT> ; } else { NewOpcode = <STR_LIT> ; Start &= <NUM_LIT> ; End &= <NUM_LIT> ; } MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( NewOpcode ) ) . addOperand ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg (

) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> void setCPR1SizeFromPredicates ( const PredicateLibrary & P ) { if ( P . abiUsesSoftFloat ( ) ) CPR1Size = AFL_REG_NONE ; else if ( P . hasMSA ( ) ) CPR1Size = AFL_REG_128 ; else CPR1Size = P . isFP64bit ( ) ? AFL_REG_64 :


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { assert ( ! Val == ! VReg && <STR_LIT> ) ; auto Ret = AddDefaultPred ( MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr (


<s> BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( & * I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) { if ( NewTBB != ( FBB ? FBB : getFallThroughMBB ( & MBB , TBB ) ) ) return true ; BranchCode = <STR_LIT>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( <NUM_LIT>


<s> unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( )


<s> if ( TARGET_ARCH64 ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_global_or_fp_reg_p ( i , <NUM_LIT> ) ) n_global_fp_regs += <NUM_LIT> ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( save_global_or_fp_reg_p ( i , <NUM_LIT> ) || save_global_or_fp_reg_p ( i + <NUM_LIT> , <NUM_LIT> ) ) n_global_fp_regs += <NUM_LIT> ; } if ( TARGET_FLAT ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = <NUM_LIT> ; i < ( TARGET_V9 ? <NUM_LIT> : <NUM_LIT> ) ; i += <NUM_LIT> ) if ( save_global_or_fp_reg_p ( i , <NUM_LIT> ) || save_global_or_fp_reg_p ( i + <NUM_LIT> , <NUM_LIT> ) ) n_global_fp_regs += <NUM_LIT> ; if ( size == <NUM_LIT> && n_global_fp_regs == <NUM_LIT> && args_size == <NUM_LIT> && ! save_local_in_regs_p ) frame_size = apparent_frame_size = <NUM_LIT> ; else { apparent_frame_size = ROUND_UP ( size - STARTING_FRAME_OFFSET , <NUM_LIT> ) ; apparent_frame_size += n_global_fp_regs * <NUM_LIT> ; frame_size = apparent_frame_size + ROUND_UP ( args_size , <NUM_LIT> ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val )


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage (


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ; int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm


<s> std :: unique_ptr < MCObjectWriter > <ISA_LIT>AsmBackend :: createObjectWriter (


<s> if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; SDLoc dl ( InputVector ) ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InputVector ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT ElementType = InputVector . getValueType ( ) .


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X =


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg =


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr & MI ) const { return


<s> Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> SDValue VecOp = ScalarOp . getOperand ( <NUM_LIT> ) ; EVT SrcVT = VecOp . getValueType ( ) ; if ( useSVEForFixedLengthVectorVT ( SrcVT , true ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , SrcVT ) ; VecOp = convertToScalableVector ( DAG , ContainerVT , VecOp ) ; } EVT ResVT = ( Opcode == <STR_LIT> ) ? <STR_LIT> : SrcVT . getVectorElementType ( ) ; EVT RdxVT = SrcVT ; if ( SrcVT . isFixedLengthVector ( ) || Opcode == <STR_LIT> ) RdxVT = getPackedSVEVectorVT ( ResVT ) ; SDValue Pg = getPredicateForVector ( DAG , DL ,


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ; return


<s> return new <ISA_LIT>PassConfig ( this ,


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizePICCallPass (


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ) ; return IsConstantImm && isUInt < num >


<s> AM . Scale = <NUM_LIT> ; } switch ( TM . getCodeModel ( ) ) { default : break ; case CodeModel :: Small : case CodeModel :: Kernel : if ( Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr && AM . IndexReg . getNode ( ) == nullptr && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg =

CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type


<s> } else Opc = <STR_LIT> ; } else { if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } else { if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { Opc = <STR_LIT> ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } else { Opc = <STR_LIT> ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } break ; } DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; if ( isInc || isDec ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Chain } ; SDValue Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Ret ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SDValue RetVals [ ] = { Undef , Ret } ; return CurDAG -> getMergeValues ( RetVals , <NUM_LIT> , dl ) . getNode ( ) ; } else { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Val , Chain } ; SDValue Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Ret ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SDValue RetVals [ ] = { Undef ,


<s> Register <ISA_LIT>MachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( &


<s> if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return SDValue ( ) ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt ==


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & TuneCPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , ReserveXRegister ( <STR_LIT> . getNumRegs ( ) ) , CustomCallSavedXRegs ( <STR_LIT> . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , InstrInfo (

initializeSubtargetDependencies ( FS , CPU , TuneCPU ) ) , TLInfo ( TM , * this ) {


<s> case E_V16HImode : mode = V8SImode ; break ; case E_V32HImode : mode = V16SImode ; break ; case E_V4SImode : mode = V2DImode ; break ; case E_V8SImode : mode = V4DImode ; break ; case E_V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = <NUM_LIT> ; i < d -> nelt ; i += <NUM_LIT> ) if ( ( d -> perm [ i ] & <NUM_LIT> ) || d -> perm [ i + <NUM_LIT> ] != d -> perm [ i ] + <NUM_LIT> ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ <NUM_LIT> * i ] / <NUM_LIT> ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart ( nd -> vmode , d -> op0 ) ; else { nd -> op0 = gen_lowpart ( nd -> vmode , d -> op0 ) ; nd -> op1 = gen_lowpart ( nd -> vmode , d -> op1 ) ; } if ( d -> testing_p ) nd -> target = gen_raw_REG ( nd -> vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; else nd -> target = gen_reg_rtx ( nd -> vmode ) ; } return true


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> static __inline unsigned int _mm_getcsr ( void ) { return __builtin_ia32_stmxcsr


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addPostIdxRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return


<s> shiftr = <NUM_LIT> - shiftr ; return ( ( __A >> ( shiftr * <NUM_LIT> )


<s> unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count


<s> return selectAddrRiSpls ( Addr , Base , Offset , AluOp ,


<s> SmallPtrSet < BasicBlock * , <NUM_LIT> > ExceptBlocks ; for ( BasicBlock & BB : F ) { for ( auto I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ++ I ) { if ( auto * CI = dyn_cast < CallInst > ( I ) ) { auto * Intrin = dyn_cast < IntrinsicInst > ( CI ) ; if ( Intrin ) { continue ; } insertStateNumberStore ( RegNode , CI , - <NUM_LIT> ) ; } else if ( auto * II = dyn_cast < InvokeInst > ( I ) ) { LandingPadInst * LPI = II -> getUnwindDest ( ) -> getLandingPadInst ( ) ; auto InsertionPair = FuncInfo . EHPadStateMap . insert ( std :: make_pair ( LPI , CurState ) ) ; auto Iter = InsertionPair . first ; int & State = Iter


<s> const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> :


<s> return ( uint16x8_t ) __builtin_neon_vcagev8hf ( __a ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>