<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return <NUM_LIT> ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == <NUM_LIT> && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx


<s> int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + (


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I ) { if ( selectImpl ( I , * CoverageInfo ) ) return true ; return


<s> if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) == - <NUM_LIT> ) return <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) || DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; SrcOpNum = <NUM_LIT> ; Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned ZReg = removeCopies ( MRI , DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ZReg != <STR_LIT> && ZReg != <STR_LIT> ) return <NUM_LIT> ; SrcOpNum = <NUM_LIT> ; Opc = Is64Bit ?


<s> return ggc_cleared_alloc < machine_function > ( )


<s> EVT TruncVT = Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! ( Subtarget . hasSSE2 ( ) && ( TruncVT == <STR_LIT> || TruncVT == <STR_LIT> || TruncVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue OpToSaturate ; if ( MinLHS . getOpcode ( ) == <STR_LIT> && MinLHS . getOperand ( <NUM_LIT> ) == Op0 ) OpToSaturate = MinRHS ; else if ( MinRHS . getOpcode ( ) == <STR_LIT> && MinRHS . getOperand ( <NUM_LIT> ) == Op0 ) OpToSaturate = MinLHS ; else return SDValue ( ) ; SDLoc DL ( N ) ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( TruncVT . getScalarSizeInBits ( ) , VT . getScalarSizeInBits ( ) ) , DL , TruncVT ) ; SDValue UMin = DAG . getNode ( <STR_LIT> , DL , TruncVT , OpToSaturate , SaturationConst ) ; SubusRHS = DAG . getNode ( <STR_LIT> , DL , VT , UMin ) ; } else return SDValue ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; KnownBits Known = DAG . computeKnownBits ( SubusLHS ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( NumZeros < ( VT . getScalarSizeInBits ( ) - <NUM_LIT> ) ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT ==


<s> static DecodeStatus DecodeBranchTarget21 ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset


<s> unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getSizeInBits ( ) < <NUM_LIT> && ( InVT . getScalarType ( ) == <STR_LIT> || InVT . getScalarType ( ) == <STR_LIT> || ! Subtarget -> hasVLX ( ) ) ) { assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } SDValue ShiftNode = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant ( ShiftInx , DL , InVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> EVT VT = Op . getValueType ( ) ; SDValue AllocaCall = makeExternalCall ( Chain , DAG , <STR_LIT> , VT , makeArrayRef ( NeededSpace ) , CallingConv :: C , IsSigned , DL , DoesNotReturn , IsReturnValueUsed ) . first ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; Register SPReg = Regs . getStackPointerRegister ( ) ; Chain = AllocaCall . getValue ( <NUM_LIT> ) ; SDValue Glue = AllocaCall . getValue ( <NUM_LIT> ) ; SDValue NewSPRegNode = DAG . getCopyFromReg ( Chain , DL , SPReg , PtrVT , Glue ) ; Chain = NewSPRegNode . getValue ( <NUM_LIT> ) ; MVT PtrMVT = getPointerMemTy ( MF . getDataLayout ( ) ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , PtrMVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL


<s> <ISA_LIT>Operand Op = static_cast < <ISA_LIT>Operand & > ( * Operands . back ( ) ) ; Operands . pop_back ( ) ; Operands . push_back ( <STR_LIT> ( Op , S , E ,


<s> MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return <NUM_LIT> ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; Register ResultReg = createResultReg (


<s> __arm_mcr2 ( const unsigned int __coproc , const unsigned int __opc1 , uint32_t __value , const unsigned int

__CRn , const unsigned int __CRm , const unsigned int __opc2 ) {


<s> FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; OutChains . push_back ( Store


<s> } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> return TypeSize :: getFixed ( <NUM_LIT> ) ; case TargetTransformInfo :: RGK_FixedWidthVector : if ( ST -> hasSVE ( ) ) return TypeSize :: getFixed ( std :: max ( ST -> getMinSVEVectorSizeInBits ( ) , <NUM_LIT> ) ) ; return TypeSize :: getFixed ( ST -> hasNEON ( ) ? <NUM_LIT> : <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( ST -> hasSVE ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } llvm_unreachable ( <STR_LIT> )


<s> if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , <STR_LIT> , XINT ( XVECEXP ( PATTERN ( insn

) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , FALSE ) ;


<s> const MCOperand & ImmMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( ImmMO . getImm ( ) >= <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegMO , Fixups , STI ) << <NUM_LIT> ) ; Bits |= ( unsigned ) ImmMO . getImm


<s> case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , op1 ) ) ; mask = GEN_INT ( - <NUM_LIT> ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( <NUM_LIT> , mask , mask ) ) ; mask = force_reg ( V2SImode , mask ) ; t2 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_andv2si3 ( t2 , op0 , mask ) ) ; x = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_xorv2si3 ( x , t1 , t2 ) ) ; code = GT ; op0 = x ; op1 = CONST0_RTX ( mode ) ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , op0 , op1 )


<s> OptLEA = ST . LEAusesAG ( ) || ST . slowLEA ( ) || ST . slow3OpsLEA ( ) ; if ( ! OptLEA && ! OptIncDec ) return false ; TII = ST . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; auto & DL = DAG . getDataLayout ( ) ; const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SDValue SRet = DAG . getFrameIndex ( FrameIdx , getPointerTy ( DL ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> :


<s> static const uint16_t ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , ShadowRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ] && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ]


<s> Triple Triple ( TT ) ; if ( Triple . isOSBinFormatMachO ( ) ) return <STR_LIT> ; if ( LittleEndian )


<s> switch ( esize ) { case ESize16 : return ( ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) ; case ESize32 : return ( insn >> <NUM_LIT> ) & <NUM_LIT> ; default : assert ( <NUM_LIT> && <STR_LIT>


<s> gcc_assert ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ; long_jump_p = ( insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) { case GT : case GE : case LT : case LE : output_cond_branch_compare_zero ( code , <STR_LIT> , long_jump_p , operands , false ) ; break ; default : gcc_unreachable ( ) ; } return


<s> if ( ST -> isAtom ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; assert ( insn -> numImmediatesConsumed < <NUM_LIT> && <STR_LIT> ) ; insn -> immediateSize = size ; insn -> immediateOffset = insn -> readerCursor - insn -> startLocation ; switch ( size ) { case <NUM_LIT> : if ( consume ( insn , imm8 ) ) return - <NUM_LIT> ; insn -> immediates [ insn -> numImmediatesConsumed ] = imm8 ; break ; case <NUM_LIT> : if ( consume ( insn , imm16 ) ) return -


<s> bool <ISA_LIT>TargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { int16_t imm = <NUM_LIT> ; if ( N . getOpcode ( ) == <STR_LIT> ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm


<s> ElementCount EC = VT . getVectorElementCount ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumVecs ; ++ I ) assert ( VT == EVT :: getEVT ( CI . getArgOperand ( I ) -> getType ( ) ) && <STR_LIT> ) ; Info . memVT = EVT :: getVectorVT ( CI . getType ( ) -> getContext ( ) , VT . getScalarType ( ) , EC * NumVecs ) ; Info . ptrVal = CI . getArgOperand ( CI . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore


<s> } } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( ( ! Is64BitMode || DispForReloc || BaseReg != <NUM_LIT> ) && IndexReg . getReg ( ) == <NUM_LIT> && ( BaseReg == <NUM_LIT> || get<ISA_LIT>RegNum ( BaseReg ) != N86 :: ESP ) ) { if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj ) ; } else { unsigned BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; } else if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj ) ; } } } else { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> ,


<s> __builtin_ia32_pmovusdb128mem_mask ( ( unsigned int * ) __P , ( __v4si )


<s> unsigned iflags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { int imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm > <NUM_LIT> ) return


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI -> getZExtValue (


<s> <ISA_LIT>TargetMachine :: registerAsmPrinter ( create<ISA_LIT>CodePrinterPass )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Subtarget . hasPOPCNTFalseDeps (


<s> if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( TwoRepStos


<s> if ( ! TARGET_64BIT ) return <NUM_LIT> ; if ( FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return <NUM_LIT> ; else if ( cum -> words + offset >= max_arg_words ) return <NUM_LIT> ; else return ( max_arg_words - cum -> words - offset ) *


<s> if ( value != <NUM_LIT> ) return <NUM_LIT> ; if ( ! REG_P ( addr ) ) return <NUM_LIT> ; if ( REGNO ( addr ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( ( TARGET_THUMB || ! frame_pointer_needed ) && REGNO ( addr ) == SP_REGNUM ) return <NUM_LIT> ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && REGNO ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == REGNO ( addr ) && GET_CODE ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM && CONST_INT_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) { value = INTVAL ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; } } if ( value == <NUM_LIT> )


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { for ( unsigned i = <NUM_LIT> , e = LegalFPImmediates . size


<s> code = ROTATERT ; * amountp = <NUM_LIT> - INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; mnem = <STR_LIT> ; break ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : mnem = arm_shift_nmem ( code ) ; if ( CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) { * amountp = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; } else if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) ) { * amountp = - <NUM_LIT> ; return mnem ; } else { output_operand_lossage ( <STR_LIT> ) ; return NULL ; } break ; case MULT : if ( ! CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) { output_operand_lossage ( <STR_LIT> ) ; return NULL ; } * amountp = INTVAL ( XEXP ( op , <NUM_LIT> ) ) & <NUM_LIT> ; if ( * amountp & ( * amountp - <NUM_LIT> ) ) { output_operand_lossage ( <STR_LIT> ) ; return NULL ; } * amountp = int_log2 ( * amountp


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false ,


<s> void <ISA_LIT>InstPrinter :: printFCCOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand


<s> FunctionPass * llvm :: create<ISA_LIT>IndirectThunksPass ( ) { return new <ISA_LIT>IndirectThunks ( )


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , LHS , RHS } ; SDValue Lo = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , dl , VTs


<s> const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , is64Bit ? <STR_LIT> : <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I -> eraseFromParent (


<s> static MCRegisterInfo * createDcpu16MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; InitDcpu16MCRegisterInfo ( X , <STR_LIT>


<s> fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( REGNO ( x1 ) ) ] ) ; if ( REG_P ( x2 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( REGNO ( x2 ) ) ] ) ; return ; } else if ( satisfies_constraint_I


<s> if ( TARGET_MACHO && rs6000_darwin64_abi && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , true , true ) ; if ( valret ) return false ; } if ( rs6000_discover_homogeneous_aggregate ( TYPE_MODE ( type ) , type , NULL , NULL ) ) return false ; if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return


<s> extract_insn_cached ( insn ) ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( REG_P ( recog_data . operand [ i ] ) && REGNO ( recog_data . operand [ i ]


<s> SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , <STR_LIT> ) ; SDValue EndDest = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Dest , Src , DAG . getConstant ( <NUM_LIT> ,


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return * RM


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) .


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address ,


<s> } else if ( IsThumb1 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ; MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( AddrIn ) . addImm ( StSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data

) . addReg ( AddrIn ) . addImm ( StSize ) ) ;


<s> EmitSled ( MI , SledKind :: FUNCTION_EXIT


<s> return ( int16x8_t ) __builtin_neon_vaddlsv8qi


<s> int regno ; if ( TARGET_LINUX_ABI ) fixed_regs [ TP_REGNUM ] = <NUM_LIT> ; if ( TARGET_HARD_FLOAT ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) { fixed_regs [ regno ] = <NUM_LIT> ; if ( regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS ) call_used_regs [ regno ] = <NUM_LIT> ; else if ( regno >= NDS32_FIRST_FPR_REGNUM + <NUM_LIT> && regno < NDS32_FIRST_FPR_REGNUM + <NUM_LIT> ) call_used_regs [ regno ] = <NUM_LIT> ; else call_used_regs [ regno ] = <NUM_LIT> ; } } else if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM


<s> CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; ArgRegsSize = NumGPRs


<s> } else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) != <NUM_LIT> ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGEOFF ; else llvm_unreachable ( <STR_LIT> ) ; } else { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> )

RefKind = MCSymbolRefExpr :: VK_PAGEOFF ;


<s> return __builtin_aarch64_sqrdmulh_lanev2si ( __a ,


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>FrameLowering :: create ( <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & ST ) { if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm :: create<ISA_LIT>16FrameLowering ( ST ) ; return llvm :: create<ISA_LIT>SEFrameLowering ( ST


<s> tmp = fold_build_pointer_plus ( unshare_expr ( next_fp_tmp ) , tmp ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , tmp , pre_p ) ; } if ( is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_MODE ( eff_type ) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN ) { tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ; tmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_o ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; if ( size > <NUM_LIT> && ! ( TARGET_SH4 || TARGET_SH2A ) ) gimplify_assign ( unshare_expr ( next_o ) , unshare_expr ( next_o_limit ) , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; } if ( ! result ) { tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; } } tmp = std_gimplify_va_arg_expr ( valist , type , pre_p , NULL ) ; if ( result ) { gimplify_assign ( result , tmp , pre_p ) ; result = build1 ( NOP_EXPR , TREE_TYPE


<s> bool <STR_LIT> ( SDNode * N ) { return isVEXTRACTIndex ( N , <NUM_LIT>


<s> unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; EVT VT64 ; if ( is64BitVector ) { VT64 = VT ; VT = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) * <NUM_LIT> ) ; } unsigned OpcodeIndex ; switch ( VT . getScalarType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < EVT , <NUM_LIT> > ResTys ; if ( IsLoad ) { if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc

= getVLDSTRegisterUpdateOpcode ( Opc ) ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegCustomCalleeSaved ( i ) ) { UpdatedCSRs . push_back ( <STR_LIT> . getRegister ( i ) ) ; } } UpdatedCSRs . push_back ( <NUM_LIT>


<s> static __inline qword si_shufb ( qword a , qword b , qword pattern ) { vec_uchar16 pat ; pat = vec_sel ( ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , vec_sr ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) ) ; return ( ( qword ) ( vec_perm ( vec_perm ( a , b , pattern ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator


<s> bool isMem ( ) const override { return false


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups ,


<s> SecondLastInst = & * I ; SecondLastOpc = GetAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( SecondLastInst ) && ! SecondLastOpc ) return true ; } if ( ! SecondLastOpc ) { if ( LastOpc == UncondBrOpc ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return true ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; return false ; } if ( LastOpc != UncondBrOpc ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) .


<s> bit <<= <NUM_LIT> ; } while ( bit ) { if ( num >= den ) { num -= den ; res |= bit ; } bit >>=


<s> unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = RegOpsNum ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; unsigned Op2Reg = MI . getOperand ( CommutableOpIdx2 ) . getReg ( ) ; for ( CommutableOpIdx1 = RegOpsNum ; CommutableOpIdx1 > <NUM_LIT> ; CommutableOpIdx1 -- ) { if ( Op2Reg != MI . getOperand ( CommutableOpIdx1 ) . getReg ( ) )


<s> return parseAddress ( Operands , <STR_LIT> ,

<ISA_LIT>Operand :: ADDR32Reg , false ) ;


<s> bool useSqrtEst ( ) const { return UseSqrtEst


<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( ) << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask ) ; O << <STR_LIT> << <ISA_LIT>FI


<s> if ( ! cfun ) return <NUM_LIT> ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl )


<s> SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue MaskNot = DAG . getNode ( <STR_LIT> , dl , OpVT , Mask , DAG . getNode ( <STR_LIT> , dl , OpVT , AllOnes ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 , Mask ) , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 , MaskNot ) ) ; if ( VT == <STR_LIT> ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } return Res ; } if ( SrcVT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Tmp1 , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; SDValue Mask1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Mask2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 , Mask1 ) ; if ( VT == <STR_LIT> ) { Tmp0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return


<s> int V2Idx = M < Size ? ZeroMask : ( M - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } MVT ShufVT = <STR_LIT> ( <STR_LIT> , NumBytes ) ; if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , ShufVT , DAG . getBitcast ( ShufVT , V1 ) , DAG . getBuildVector ( ShufVT , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , ShufVT , DAG . getBitcast ( ShufVT , V2 ) , DAG . getBuildVector ( ShufVT , DL , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode (


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return ( float32_t ) __builtin_neon_vget_lanev2sf ( __a ,


<s> char ConstraintLetter = Constraint [ <NUM_LIT> ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode (


<s> Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , SrlImm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; } else if ( isOpcWithIntImmediate ( Op0 , <STR_LIT> , SrlImm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) ; ClampMSB = ( VT == <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ! BiggerPattern && ( SrlImm <= <NUM_LIT> || SrlImm >= VT . getSizeInBits ( ) ) ) { LLVM_DEBUG ( ( dbgs ( ) <<


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( DstReg != SrcMO . getReg ( ) ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcMO . getReg ( ) ) ; SrcMO . setReg ( DstReg ) ; MemFoldCopies ++ ; } return


<s> } case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << *


<s> add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i )


<s> bool isU4Imm ( ) const { return isImm ( <NUM_LIT> , <NUM_LIT>


<s> getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB


<s> return ( unsigned short ) __builtin_loongarch_iocsrrd_h ( ( unsigned int


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int


<s> static bool isZeroVector ( SDValue N ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( auto * Op = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return Op -> getZExtValue ( ) == <NUM_LIT> ; return <STR_LIT> ( N . getNode


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , true ,


<s> return ( __m128i ) __builtin_ia32_pmovsqw256_mask ( ( __v4di ) __A , (


<s> bool <ISA_LIT>InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Subtarget -> isFPOnlySP ( ) && <STR_LIT> ) ; RTLIB :: Libcall LC


<s> for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) return


<s> static DecodeStatus decodeBDAddr32Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) { return decodeBDAddr12Operand ( Inst , Field


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! <STR_LIT> ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT>


<s> SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Lane ) ) return SDValue ( ) ; Op . dump ( ) ; Op . getOperand ( <NUM_LIT> )


<s> void addImm0_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm (


<s> static __inline void _mm_empty ( void ) { __builtin_ia32_emms ( )


<s> if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return true ; } else { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumedToken ) ) ; if ( std :: unique_ptr < <ISA_LIT>Operand > Op = ParseOperand ( ) ) { Operands . push_back ( std :: move ( Op ) ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> ,


<s> ++ Count ; break ; case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; default : { unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB ( TBB ) ; ++ Count ; } } if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB


<s> unsigned char brmask = ( code & <NUM_LIT> ) ; UNW_DEC_BR_MEM ( P1 , brmask


<s> if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ) ) { return true ; } } return


<s> case <STR_LIT> : ResultPtr = ( ResultPtr & <NUM_LIT> ) >> <NUM_LIT> ; * ( ( unsigned * ) RelocPos ) |= ( unsigned ) ResultPtr ; break ; case <STR_LIT> : ResultPtr = ResultPtr >> <NUM_LIT> ; if ( ( ( ( intptr_t ) ( MR -> getResultPointer ( ) ) & <NUM_LIT> ) >> <NUM_LIT> ) == <NUM_LIT> ) { ResultPtr += <NUM_LIT> ; } * ( ( unsigned * ) RelocPos ) |= ( unsigned ) ResultPtr ; break ; case <STR_LIT> : { int Addend = * ( ( unsigned * ) RelocPos ) & <NUM_LIT> ; ResultPtr = ( ResultPtr + Addend ) & <NUM_LIT> ; * ( ( unsigned * ) RelocPos


<s> tree vectype ; unsigned int num_zr = <NUM_LIT> , num_pr = <NUM_LIT> ; if ( eltype == boolean_type_node ) { vectype = build_truth_vector_type_for_mode ( BYTES_PER_SVE_VECTOR , VNx16BImode ) ; gcc_assert ( TYPE_MODE ( vectype ) == VNx16BImode && TYPE_MODE ( vectype ) == TYPE_MODE_RAW ( vectype ) && TYPE_ALIGN ( vectype ) == <NUM_LIT> && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BYTES_PER_SVE_VECTOR ) ) ; num_pr = <NUM_LIT> ; } else { scalar_mode elmode = SCALAR_TYPE_MODE ( eltype ) ; unsigned int elbytes = GET_MODE_SIZE ( elmode ) ; poly_uint64 nunits = exact_div ( BYTES_PER_SVE_VECTOR , elbytes ) ; machine_mode mode = aarch64_sve_data_mode ( elmode , nunits ) . require ( ) ; vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) == <NUM_LIT> && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BITS_PER_SVE_VECTOR ) ) ; num_zr = <NUM_LIT> ; } vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = <NUM_LIT> ; TYPE_INDIVISIBLE_P ( vectype ) = <NUM_LIT> ; add_sve_type_attribute ( vectype , num_zr , num_pr , vector_types [ i ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ i


<s> static SDValue LowerShiftParts ( SDValue Op , SelectionDAG & DAG ) { SDValue Lo , Hi ; DAG . getTargetLoweringInfo ( ) . expandShiftParts ( Op . getNode ( ) ,


<s> return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) ) || isSHUFPMask ( Mask , VT , Subtarget ->


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , OffsetPtr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ; } if ( InDouble . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( InDouble . getOperand ( <NUM_LIT> ) ) ) { SDValue BV = InDouble . getOperand ( <NUM_LIT> ) ; bool BVSwap = BV . getOpcode ( ) == <STR_LIT> ; while ( ( BV . getOpcode ( ) == <STR_LIT> || BV . getOpcode ( ) == <STR_LIT> ) && ( BV . getValueType ( ) == <STR_LIT> || BV . getValueType ( ) == <STR_LIT> ) ) { BVSwap = BV . getOpcode ( ) == <STR_LIT> ; BV = BV . getOperand ( <NUM_LIT> ) ; } if ( BV . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned Offset = InDouble . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( BV . getOpcode ( ) == <STR_LIT> ) { SDValue Op0 = BV . getOperand ( Offset ) ; SDValue Op1 = BV . getOperand ( Offset + <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) && BVSwap ) std :: swap ( Op0 , Op1 ) ; return DCI . DAG . getMergeValues ( { Op0 , Op1 } , SDLoc ( N ) ) ; } SDValue Op0 , Op1 ; while ( BV . getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( BV . getOperand ( <NUM_LIT>


<s> if ( CSKY_FUNCTION_TYPE ( cfun -> machine -> func_type ) == CSKY_FT_UNKNOWN ) { unsigned long type = CSKY_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) type |= CSKY_FT_NORMAL ; else type |= get_csky_isr_type ( TREE_VALUE ( a ) ) ; cfun -> machine -> func_type = type


<s> if ( ! TPC ) return false ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I :


<s> if ( CSel . getOpcode ( ) != <STR_LIT> || ! CSel -> hasOneUse ( ) ) return SDValue ( ) ; SDValue N0 = CSel . getOperand ( <NUM_LIT> ) ; SDValue N1 = CSel . getOperand ( <NUM_LIT> ) ; if ( ! isNegatedInteger ( N0 ) && ! isNegatedInteger ( N1 ) ) return SDValue ( ) ; SDValue N0N = getNegatedInteger ( N0 , DAG ) ; SDValue N1N = getNegatedInteger ( N1 , DAG ) ; SDLoc DL ( N )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR (


<s> SmallSet < unsigned , <NUM_LIT> > RegDefs ; SmallSet < unsigned , <NUM_LIT> > RegUses ; bool sawLoad = false ; bool sawStore = false ; if ( slot == MBB . begin ( ) ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator J = slot ; -- J ; if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode (


<s> if ( CannotReserveFrame ) return true ; Align StackAlign = TFL -> getStackAlign ( ) ; int64_t Advantage = <NUM_LIT> ; for ( const auto & CC : CallSeqVector ) { if ( CC . NoStackParams ) continue ; if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( ! isAligned ( StackAlign , CC

. ExpectedDist ) ) Advantage -= <NUM_LIT> ;


<s> return static_cast < <ISA_LIT>DCModule & > ( DCFunction :: getParent (


<s> MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? <NUM_LIT> : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious


<s> uint64_t NumBytes = MFI . getStackSize ( ) ; NumBytes = STI . getAdjustedFrameSize ( NumBytes ) ; NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; emitSPAdjustment ( MF , MBB , MBBI , - ( int64_t ) NumBytes , RuntimeAlign ) ; if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } emitSPExtend ( MF , MBB , MBBI ) ; Register RegFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RegFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION )


<s> void sgxCallMagicReset ( ) { sgx_call_magic_labels_index = <NUM_LIT>


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind -


<s> case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else { AM . GVOpFlags = Subtarget -> classifyLocalReference ( nullptr ) ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; } } return


<s> unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) return <NUM_LIT> ; if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . ParseAbsoluteExpression ( Value ) ) return <NUM_LIT> ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } SMLoc MemEnd = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , MemStart ,


<s> const EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; assert ( SrcVT . isScalableVector ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; MVT SrcElVT = SrcVT . getVectorElementType ( ) . getSimpleVT ( ) ; if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; if ( SrcElVT . isFloatingPoint ( ) ) if ( ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) ) return SDValue ( ) ; const SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Offset . getValueType ( ) ) ) return SDValue ( ) ; EVT HwSrcVt = getSVEContainerType ( SrcVT ) ; SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt ,


<s> return __builtin_aarch64_reduc_smin_scal_v8hi (


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue (


<s> case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) && isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue N000 = N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue FPConst = DAG . getBitcast ( VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( FPOpcode , SDLoc ( N0 ) , VT , N000 , FPConst ) ; } return SDValue


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; } Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget >


<s> if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getLoad ( ResTy , DL , ChainIn , Address , MachinePointerInfo ( )


<s> static void checkIs32 ( MCContext & Ctx , SMLoc


<s> bool UseMovt = STI . useMovt ( MF ) ; unsigned Size = TM . getPointerSize ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; auto addOpsForConstantPoolLoad = [ & MF , Alignment , Size ] ( MachineInstrBuilder & MIB , const GlobalValue * GV , bool IsSBREL ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; auto ConstPool = MF . getConstantPool ( ) ; auto CPIndex = IsSBREL ? ConstPool -> getConstantPoolIndex ( <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) , Alignment ) : ConstPool -> getConstantPoolIndex ( GV , Alignment ) ; MIB . addConstantPoolIndex ( CPIndex , <NUM_LIT> , <NUM_LIT> ) . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( Indirect ? <STR_LIT> : <STR_LIT> ) : ( Indirect ? <STR_LIT> : <STR_LIT> ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags (


<s> bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr ,

MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> return DecodeMVE_MEM_pre ( Inst , Val , Address , Decoder , fieldFromInstruction ( Val , <NUM_LIT>

, <NUM_LIT> ) , DecoderGPRRegisterClass , DecodeT2AddrModeImm7 < shift , <NUM_LIT> > ) ;


<s> break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; op [ nopnds ++ ] = gen_rtx_REG ( mode , htm_spr_regno ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; if ( attr & RS6000_BTC_CR ) { if ( fcode == HTM_BUILTIN_TBEGIN ) { rtx scratch = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_EQ ( SImode , cr , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_XOR ( SImode , scratch , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { rtx scratch1 = gen_reg_rtx ( SImode ) ; rtx scratch2 = gen_reg_rtx ( SImode ) ; rtx subreg = simplify_gen_subreg ( CCmode , scratch1 , SImode , <NUM_LIT> ) ; emit_insn ( gen_movcc ( subreg ,


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , getTargetLowering ( ) -> getPointerTy ( ) ) ; return


<s> static bool aarch64_vect_struct_mode_p ( machine_mode mode ) { return mode == OImode || mode == CImode ||


<s> for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) MCI . addOperand ( MaybeOperand . getValue ( ) ) ; SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT> ) { MCI . setOpcode ( <STR_LIT> ) ; } else { unsigned NopSize = EmitNop ( * OutStreamer , MinSize , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; assert ( NopSize == MinSize && <STR_LIT> ) ; ( void


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( )


<s> SDLoc dl ( Op ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , dl , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , dl ,


<s> MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand ::


<s> unsigned EltBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; EVT EltVT = EVT :: getIntegerVT ( * DAG . getContext (


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; bool Modified = false ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) { MachineInstr * FirstTerminator = nullptr ; bool PrevInstIsLFENCE = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { PrevInstIsLFENCE = true ; continue ; } if ( MI . mayLoadOrStore ( ) && ! MI . isTerminator ( ) ) { if ( ! PrevInstIsLFENCE ) { BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; NumLFENCEsInserted ++ ; Modified = true ; } if ( OneLFENCEPerBasicBlock ) break ; } if ( MI . isTerminator ( ) && FirstTerminator == nullptr ) FirstTerminator = & MI ; if ( ! MI . isBranch ( ) || OmitBranchLFENCEs ) { PrevInstIsLFENCE = false ; continue ; } if ( OnlyLFENCENonConst && hasConstantAddressingMode ( MI ) ) { PrevInstIsLFENCE = false ; continue ; } if ( ! PrevInstIsLFENCE ) { assert ( FirstTerminator && <STR_LIT> ) ; BuildMI ( MBB , FirstTerminator , DebugLoc ( ) , TII -> get ( <STR_LIT>


TYPE_MAIN_VARIANT ( ctype ) ) , attr_name ) ;


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , false


<s> } break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII

. get ( StrOpc ) ) . addReg ( SrcReg ) ;


<s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const { if ( ! Subtarget . hasBMI ( ) ) return


<s> NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~ AlignMask ; } return NumBytes


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg


<s> BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; } else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) sinkMBB -> addSuccessor ( * i ) ; while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF ,


<s> if ( ! InstrConverterBase :: isLegal ( MI , TII ) ) return false ; for ( auto & MO : MI -> implicit_operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) && ! MO . isDead ( ) && ! TII -> get ( DstOpcode ) . hasImplicitDefOfPhysReg ( MO . getReg ( ) ) ) return false ; return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; BBUtils -> computeAllBlockSizes ( )


<s> unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == <STR_LIT> ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new <ISA_LIT>FastISel ( funcInfo , libInfo ) ; } return <NUM_LIT>


<s> MVT WideVecVT = VecVT ; if ( ( ! Subtarget . hasDQI ( ) && NumElems == <NUM_LIT> ) || NumElems < <NUM_LIT> ) { WideVecVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , DAG . getUNDEF ( WideVecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec ,


<s> return ( __m128i ) __builtin_ia32_pmovusqb512_mask ( ( __v8di ) __A , ( __v16qi ) _mm_undefined_si128 ( )


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream


<s> if ( load ) { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; } else { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; } extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; if ( offval_1 > offval_2 ) { std :: swap ( operands [ <NUM_LIT> ] , operands


<s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer ( ) { return static_cast < <ISA_LIT>TargetStreamer & > (

* OutStreamer . getTargetStreamer ( ) ) ;


<s> bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Name , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned prfop = Mapper . fromString ( Tok . getString ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Tok . getString ( ) , S , getContext (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this ,


<s> return int64_t ( Value ) != int64_t ( int8_t ( Value


<s> bool <ISA_LIT>InterleavedAccessGroup :: isSupported ( ) const { VectorType * ShuffleVecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; uint64_t ShuffleVecSize = DL . getTypeSizeInBits ( ShuffleVecTy ) ; Type * ShuffleEltTy = ShuffleVecTy -> getVectorElementType (


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false


<s> MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder


<s> case <NUM_LIT> : return AllocOperands { Malloc -> getArgOperand ( <NUM_LIT> ) , nullptr , Src , cheri :: SetBoundsPointerSource :: Heap } ; case <NUM_LIT> : return AllocOperands { Malloc -> getArgOperand ( <NUM_LIT> ) , Malloc -> getArgOperand ( <NUM_LIT> ) , Src , cheri :: SetBoundsPointerSource :: Heap } ; } } else if ( AllocaInst * AI = dyn_cast < AllocaInst > ( Src . Base ) ) { PointerType * AllocaTy = AI -> getType ( ) ; Value * ArraySize = AI -> getArraySize ( ) ; Type * AllocationTy = AllocaTy -> getElementType ( ) ; unsigned ElementSize = TD ->


<s> getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( Disable<ISA_LIT>DomainReassignment ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MF . print ( dbgs ( ) ) ) ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI -> hasAVX512 ( ) || ! STI -> hasBWI ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = Register :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures ) { LLVM_DEBUG ( C . dump ( MRI )


<s> if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( const BasicBlock * SuccBB : IB -> successors ( ) ) FuncInfo . MBB

-> addSuccessor ( FuncInfo . MBBMap [ SuccBB ] ) ;


<s> bv = vec_splat ( ( vec_ushort8 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( bv , vec_splat_u16 ( <NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ; return ( ( qword ) ( vec_andc ( vec_sl ( ( vec_ushort8 ) (


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = <NUM_LIT> ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; emit_update = ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ? <NUM_LIT> : <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> ,


<s> bool <ISA_LIT>AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) && MatchRegisterName ( Parser . getTok ( ) . getString ( ) ) ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; if ( ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Res = <STR_LIT> ( RegNo , Parser . getContext ( ) ) ; return false


<s> void <ISA_LIT>InstPrinter :: printBDVAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum

+ <NUM_LIT> ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> return ( __m128d ) __builtin_ia32_loadupd128_mask ( ( __v2df * ) __P , ( __v2df ) __W ,


<s> PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return false


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { <ISA_LIT>SSELevel = NoSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasX87 = false ; HasNOPL = false ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasVAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasVPCLMULQDQ = false ; HasGFNI = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasVBMI2 = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false ; HasSHA = false ; HasPREFETCHWT1 = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; HasRDPID = false ; UseRetpoline = false ; UseRetpolineExternalThunk = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false


<s> MachineFunction * MF = BB -> getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; MachineBasicBlock * TargetMBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( RestoreMBB ) ; MI . getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB


<s> unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = nullptr ; if ( UseLEA


<s> uint32x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o ,


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , <NUM_LIT> > & cil ) { return <STR_LIT> ( mf , mmo , dw , vm , bm , am


<s> fma_forest :: ~ fma_forest ( ) { delete this ->


<s> EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT>


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> )


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm


<s> return ( __m128d ) __builtin_ia32_cmpunordpd ( ( __v2df ) __A , (


<s> getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx


<s> uint64_t OffsetVal = Offset -> getZExtValue ( ) ; unsigned ScalarSizeInBytes = MemVT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( OffsetVal % ScalarSizeInBytes || OffsetVal / ScalarSizeInBytes > <NUM_LIT> ) return ; Opcode = IsGather ? <STR_LIT> :


<s> } } else { size_t i ; bool invert = false ; char * r = q ; error_p = true ; if ( strncmp ( r , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { invert = true ; r += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_masks ) ; i ++ ) if ( strcmp ( r , rs6000_opt_masks [ i ] . name ) == <NUM_LIT> ) { HOST_WIDE_INT mask = rs6000_opt_masks [ i ] . mask ; if ( ! rs6000_opt_masks [ i ] . valid_target ) not_valid_p = true ; else { error_p = false ; rs6000_isa_flags_explicit |= mask ; if ( mask == OPTION_MASK_VSX && ! invert ) mask |= OPTION_MASK_ALTIVEC ; if ( rs6000_opt_masks [ i ] . invert ) invert = ! invert ; if ( invert ) rs6000_isa_flags &= ~ mask ; else rs6000_isa_flags |= mask ; } break ; } if ( error_p && ! not_valid_p ) { for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_vars ) ; i ++ ) if ( strcmp ( r , rs6000_opt_vars [ i ] . name ) == <NUM_LIT> ) { size_t j = rs6000_opt_vars [ i ] . global_offset ; * ( ( int * ) ( ( char * ) & global_options + j ) ) = ! invert ; error_p = false ; break ; } } } if ( error_p ) { const char * eprefix , * esuffix ; ret =


<s> return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty


<s> MVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; MVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi } ; return DAG . getMergeValues ( OutOps , <NUM_LIT> , dl


<s> if ( ST -> hasSVE ( ) ) return std :: max ( ST -> getMinSVEVectorSizeInBits ( ) , <NUM_LIT> ) ; if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return


<s> return ( __m128d ) __builtin_ia32_reducepd128_mask ( ( __v2df ) __A , __B , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 )


<s> EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType == <STR_LIT> ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Disp , Index ) ; return true


<s> Value * getAccumulator ( ) { return Acc


<s> if ( RefSec . getSegmentName ( ) == <STR_LIT> && RefSec . getSectionName ( ) == <STR_LIT> ) return false ; if ( RefSec . getSegmentName ( ) == <STR_LIT> && RefSec . getSectionName ( ) == <STR_LIT> ) return false ; return true


<s> static <ISA_LIT>Operand * CreateBarrier ( unsigned Val , SMLoc S , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_CCR ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> vec_ushort8 neg_b ; vec_ushort8 mask ; neg_b = vec_splat ( ( vec_ushort8 ) ( si_from_int ( - b ) ) , <NUM_LIT> ) ; mask = vec_sra ( vec_sl ( neg_b , vec_splat_u16 ( <NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ; return ( ( qword ) ( vec_sra ( ( vec_short8 ) ( a ) , ( vec_ushort8 ) vec_or (


<s> static SDValue performSignExtendInRegCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned SOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ExtOp = Src -> getOperand ( <NUM_LIT> ) ; auto VT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; ( void ) EltTy ; assert ( ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) && <STR_LIT> ) ; EVT ExtVT = VT . getDoubleNumVectorElementsVT ( * DAG . getContext ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , ExtOp . getValueType ( ) , ExtOp , DAG . getValueType ( ExtVT ) ) ; return DAG . getNode ( SOpc , DL , N -> getValueType ( <NUM_LIT> ) , Ext ) ; } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( ! EnableCombineMGatherIntrinsics ) return SDValue ( ) ; unsigned NewOpc ; unsigned MemVTOpNum = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; MemVTOpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT>


<s> return ( ( CCMask & <STR_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask &

<STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ) ) ;


<s> if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) ||

VECTOR_ALIGNMENT_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ;


<s> return ( __m256i ) __builtin_ia32_cvtmask2b256


<s> static DecodeStatus DecodeSimm4 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> >


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op .


<s> bool hasEnhancedSort ( ) const { return


<s> PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; } if ( PendingMembers . empty ( ) ) { if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } return false ; } assert ( ArgFlags . isSplitEnd ( ) ) ; unsigned FirstFree = State . getFirstUnallocated ( RegList