<s> isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( isThumb2 && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } if ( ! isThumb1 ) MF -> EnsureAlignment ( <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear ( ) ; PushPopMIs . clear


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; <STR_LIT> Cond ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( Cond , Op , DAG ) ; SDValue SetCC = getSETCC ( Cond , Overflow , DL ,


<s> if ( ++ ITState . CurPosition == <NUM_LIT> - TZ && ITState . IsExplicit


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseIntelSegmentOverride ( unsigned SegReg , SMLoc Start , unsigned Size ) { MCAsmParser & Parser = getParser ( ) ; assert ( SegReg != <NUM_LIT> && <STR_LIT> ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; int64_t ImmDisp = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { ImmDisp = Tok . getIntVal ( ) ; AsmToken ImmDispToken = Parser .


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ! VT . isFloatingPoint ( ) ) setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( ! VT . isFloatingPoint ( ) && VT != <STR_LIT> && VT != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT>


<s> assert ( ( ( ! isGP64bit ( ) && isABI_O32 ( ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( isFP64bit ( ) && ! has<ISA_LIT>64 ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( inAbs2008Mode ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; assert ( inAbs2008Mode ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( )


<s> const rtx * operands_2 = ( const rtx * ) y ; rtx mem_1 , mem_2 , base , offset_1 , offset_2 ; if ( MEM_P ( operands_1 [ <NUM_LIT> ] ) ) mem_1 = operands_1 [ <NUM_LIT> ] ; else mem_1 = operands_1 [ <NUM_LIT> ] ; if ( MEM_P ( operands_2 [ <NUM_LIT> ] )


<s> Source = & MI . getOperand ( <NUM_LIT> ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Destination = & MI . getOperand (


<s> if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MI . setDesc ( TII -> get ( Opcode ) ) ; return true


<s> void <ISA_LIT>ELFStreamer :: emitLabel ( MCSymbol *


<s> unsigned FI1 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( MFI . getObjectSize ( FI1 ) != Length || MFI . getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex =


<s> void <ISA_LIT>InstrInfo :: expandRetLR ( MachineBasicBlock & MBB

, MachineBasicBlock :: iterator I ) const {


<s> if ( ! isTypeLegal ( CFP -> getType ( ) , VT ) ) return <NUM_LIT> ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; bool Is64Bit = ( VT == <STR_LIT> ) ; unsigned ZReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; return fastEmitInst_r ( Opc , TLI . getRegClassFor ( VT


<s> static unsigned int sparc_min_arithmetic_precision ( void ) { return


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK2 : \ case TYPE_VK4 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ case TYPE_VK32 : \ case TYPE_VK64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case

TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_BNDR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ } \ }


<s> TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( isDiv && Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( isRem && ( RdReg == <STR_LIT> || RdReg == <STR_LIT> ) ) { TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; return false ; } MCContext & Context = TOut . getStreamer ( ) . getContext ( ) ; MCSymbol * BrTarget ; MCOperand LabelOp ; if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; } else { BrTarget = Context . createTempSymbol ( ) ; LabelOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( BrTarget , Context ) ) ; TOut . emitRRX ( <STR_LIT> , RtReg , ZeroReg , LabelOp , IDLoc , STI ) ; } TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; if ( ! UseTraps ) TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; if ( ! Signed ) { if ( ! UseTraps ) TOut . getStreamer ( ) . EmitLabel ( BrTarget ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; if ( parseEOL ( ) ) return true ; getTargetStreamer ( ) . emitDirectiveVariantPCS ( getContext ( ) . getOrCreateSymbol ( Name


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShiftAmtNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt


<s> void <ISA_LIT>TargetStreamer :: emitThumbSet ( MCSymbol * Symbol , const MCExpr * Value


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) )


<s> ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; if ( need_prefix == indirect_thunk_prefix_bnd ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; if ( regno != INVALID_REGNUM ) { rtx xops [ <NUM_LIT> ] ; xops [ <NUM_LIT> ] = gen_rtx_MEM ( word_mode , stack_pointer_rtx ) ; xops [ <NUM_LIT> ] = gen_rtx_REG ( word_mode , regno


<s> if ( darwin_emit_branch_islands && GET_CODE ( operands [ dest_operand_number ] ) == SYMBOL_REF && ( INTVAL ( operands [ cookie_operand_number ] ) & CALL_LONG ) ) { tree labelname ; tree funname = get_identifier ( XSTR ( operands [ dest_operand_number ] , <NUM_LIT> ) ) ; if ( no_previous_def ( funname ) ) { rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , <STR_LIT> , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ <NUM_LIT> ] == '*' ? temp_buf + <NUM_LIT> : temp_buf ; labelname = get_identifier ( label_buf


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; }


<s> unsigned StackReg = getStackRegister ( ) ; if ( Subtarget . isTarget64BitILP32 ( ) ) StackReg = get<ISA_LIT>SubSuperRegister ( StackReg , <NUM_LIT> ) ; return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int half_elts = n_elts / <NUM_LIT> ; rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i , j ; for ( i = <NUM_LIT> , j = half_elts ; i < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; for ( i = half_elts , j = <NUM_LIT> ; j < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; rtx sel = gen_rtx_VEC_SELECT ( mode , mem_op , par


<s> Value * <ISA_LIT>IREmitter :: visitSUBUS ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> void \ common_section ( ) \ { \ if ( in_section != in_common ) \ { \ in_section = in_common ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( Ty -> getVectorNumElements ( ) == Offsets -> getType ( ) -> getVectorNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( Offsets -> getType ( ) -> getVectorNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getScalarSizeInBits ( ) < Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr


<s> reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; offset = - ( num_use_regs * <NUM_LIT>


<s> ModulePass * llvm :: create<ISA_LIT>16HardFloatPass ( <ISA_LIT>TargetMachine &


<s> else FullFS = <STR_LIT> ; } } if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead = <NUM_LIT> ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit ) PreferVectorWidth = <NUM_LIT> ; else if ( Prefer256Bit ) PreferVectorWidth


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; assert ( getMemOffsetReg ( ) != <NUM_LIT> && <STR_LIT>


<s> const fltSemantics & Sem = Val . getSemantics ( ) ; unsigned FracBits = APFloat :: semanticsPrecision ( Sem ) - <NUM_LIT> ; uint32_t ExpMask ; switch ( FracBits ) { case <NUM_LIT> : ExpMask = <NUM_LIT> ; break ; case <NUM_LIT> : ExpMask = <NUM_LIT> ; break ; case <NUM_LIT> : ExpMask = <NUM_LIT> ; break ; case <NUM_LIT> : return false ; default : llvm_unreachable ( <STR_LIT> ) ; } uint32_t ExpStart = FracBits ; uint64_t FracMask = ( <NUM_LIT> << FracBits ) - <NUM_LIT> ; uint32_t Sign = Val . isNegative ( ) ; uint64_t Bits = Val . bitcastToAPInt ( ) . getLimitedValue ( ) ; uint64_t Fraction = Bits & FracMask ; int32_t Exponent = ( ( Bits >> ExpStart ) & ExpMask ) ; Exponent -= ExpMask >> <NUM_LIT> ; uint64_t A64FracStart = FracBits - <NUM_LIT> ; uint64_t A64FracMask = <NUM_LIT> ; if ( Fraction & ~ ( A64FracMask << A64FracStart ) ) return


<s> for ( int i = <NUM_LIT> ; i < LaneSize ; ++ i ) { int MaskElt = SVOp -> getMaskElt ( i + ( l * LaneSize ) ) ; if ( MaskElt < <NUM_LIT> ) continue ; if ( MaskElt >= LaneSize ) MaskElt -= LaneSize ; Mask |= MaskElt << ( i * <NUM_LIT> ) ; } } return Mask


<s> rtx mmix_function_arg ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming ) { if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode ,

( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ;


<s> return __builtin_aarch64_simd_bslv2df_suss ( __a ,


<s> static bool nds32_rtx_costs ( rtx x , int code , int outer_code , int opno , int * total , bool speed ) { return nds32_rtx_costs_impl ( x , code , outer_code , opno ,


<s> unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char XOP = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( TSFlags & <STR_LIT> ) VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) XOP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp =


<s> inline bool isHLASMAlpha ( char C ) { return isAlpha ( C ) || llvm :: is_contained ( <STR_LIT> ,


<s> static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask1 ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask2 ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpLo , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> , DL , OpHi , OpHi , ShufMask1 ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue res = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpHi , ShufMask2 ) ; return DAG . getBitcast ( <STR_LIT> , res ) ; } if ( VT == <STR_LIT> && InVT


<s> MIB . buildInstr ( NewOpc , { MI . getOperand ( <NUM_LIT> ) } , { MI . getOperand ( <NUM_LIT> ) , ImmDef } ) ; MI . eraseFromParent ( ) ; return true


<s> if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ; LLVM_DEBUG ( AM . dump ( CurDAG


<s> case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_M44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_L44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HH22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HM10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_HIX22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_LOX10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LDX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LE_HIX22 ; case <STR_LIT> : return ELF


<s> int p ; int base ; int i ; rtx addr_reg = REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ? XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) : XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; bool push_p = REGNO ( addr_reg ) == SP_REGNUM ; if ( push_p ) strcpy ( pattern , <STR_LIT> ) ; else strcpy ( pattern , <STR_LIT> ) ; p = strlen ( pattern


<s> const char * <ISA_LIT>ConstantPoolValue :: getModifierText ( ) const { switch ( Modifier ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; MachineOperand & OffsetMO = MI -> getOperand ( <NUM_LIT> ) ; uint64_t Offset = ( MFFrame . getMaxCallFrameSize ( ) + <STR_LIT> + OffsetMO . getImm ( ) ) ; unsigned NewOpcode = getOpcodeForOffset ( <STR_LIT> , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode


<s> assert ( ValVT . getFixedSizeInBits ( ) < LocVT . getFixedSizeInBits ( ) ) ; if ( Flags . isSExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType


<s> llvm :: make_early_inc_range ( MRI -> use_instructions ( TaggedReg ) ) ) { if ( isUncheckedLoadOrStoreOpcode ( UseI . getOpcode ( ) ) ) { unsigned OpIdx = TII -> getLoadStoreImmIdx ( UseI . getOpcode ( ) ) - <NUM_LIT> ; if ( UseI . getOperand ( OpIdx ) . isReg ( ) && UseI . getOperand ( OpIdx ) . getReg ( )


<s> if ( M >= <NUM_LIT> && M < NumElts ) { V1Mask [ i ] = M ; FinalMask [ i ] = i ; IsAlternating &= ( i & <NUM_LIT> ) == <NUM_LIT> ; } else if ( M >= NumElts ) { V2Mask [ i ] = M - NumElts ; FinalMask [ i ] = i + NumElts ; IsAlternating &= ( i & <NUM_LIT> ) == <NUM_LIT> ; } } auto canonicalizeBroadcastableInput = [ DL , VT , & Subtarget , & DAG ] ( SDValue & Input , MutableArrayRef < int > InputMask ) { unsigned EltSizeInBits = Input . getScalarValueSizeInBits ( ) ; if ( ! Subtarget . hasAVX2 ( ) && ( ! Subtarget . hasAVX ( ) || EltSizeInBits < <NUM_LIT> || ! <STR_LIT> ( Input , Subtarget ) ) ) return ; if ( isNoopShuffleMask ( InputMask ) ) return ; assert ( isBroadcastShuffleMask ( InputMask ) && <STR_LIT> ) ; Input = DAG . getNode ( <STR_LIT> , DL , VT , Input ) ; for ( auto I : enumerate ( InputMask ) ) { int & InputMaskElt = I . value ( ) ; if ( InputMaskElt >= <NUM_LIT> ) InputMaskElt = I . index ( ) ; } } ; if ( isNoopOrBroadcastShuffleMask ( V1Mask ) && isNoopOrBroadcastShuffleMask ( V2Mask ) ) { canonicalizeBroadcastableInput ( V1 , V1Mask ) ; canonicalizeBroadcastableInput ( V2 , V2Mask ) ; } if ( ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) { if ( SDValue BlendPerm = lowerShuffleAsBlendAndPermute ( DL , VT , V1 , V2 , Mask , DAG , true ) ) return BlendPerm ; if ( SDValue UnpackPerm = lowerShuffleAsUNPCKAndPermute ( DL , VT , V1 , V2 , Mask , DAG ) ) return UnpackPerm ; if ( SDValue RotatePerm = lowerShuffleAsByteRotateAndPermute ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return RotatePerm ; if ( SDValue BlendPerm = lowerShuffleAsBlendAndPermute ( DL , VT , V1 , V2 , Mask , DAG ) ) return BlendPerm ; } if ( IsAlternating && VT . getScalarSizeInBits ( ) < <NUM_LIT> ) { V1Mask . assign ( NumElts , - <NUM_LIT> ) ; V2Mask . assign ( NumElts , - <NUM_LIT>


<s> return Types . find ( MI ) -> getSecond (


<s> if ( FP_REGNUM_P ( regno ) ) return FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; return


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return FrameLowering . get (


<s> MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; unsigned access = MO . getTargetFlags ( ) & <STR_LIT> ; switch ( access ) { case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol ,


<s> static int already_reported_p [ ARRAY_SIZE ( cgen_intrinsics ) ] ; if ( already_reported_p [ intrinsic ] ) return ; if ( mep_intrinsic_insn [ intrinsic ] < <NUM_LIT> ) error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; else if ( CGEN_CURRENT_GROUP == GROUP_VLIW ) error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; else error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; already_reported_p [ intrinsic ] =


<s> const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock * thisMBB = MBB ; if ( MF -> getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ) { thisMBB = emitLongJmpShadowStackFix ( MI , thisMBB ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin ,


<s> SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; } } if ( I < SaveCount ) { Saved [ I ++ ] = Inst ; if ( I < SaveCount ) return true ; } if ( SaveCount > <NUM_LIT> ) { assert ( I == SaveCount && <STR_LIT> ) ; SaveCount = <NUM_LIT> ; RecurseGuard = true ; switch ( Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( I , Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( I , Saved ,


<s> static inline unsigned getAM3IBit ( uint32_t insn ) { return ( insn >> <STR_LIT> ) & <NUM_LIT>


<s> if ( ImplicitRd ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand


<s> if ( callee == dont_care ) return true ; if ( caller == dont_care ) return true ; return ( callee == caller || callee ==


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , nullptr , Name ) ; assert ( GV -> getType ( )


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveAlign ( SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return true ; const MCSection * Section = getStreamer ( ) . getCurrentSection ( ) . first ; assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return


<s> void printi8mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI ,


<s> case FrameHelperType :: Epilog : for ( auto NextMI = NextMBBI ; NextMI != MBB . end ( ) ; NextMI ++ ) { if ( NextMI -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } for ( const MachineBasicBlock * SuccMBB : MBB . successors ( ) ) { if ( SuccMBB -> isLiveIn ( <STR_LIT> ) || SuccMBB -> isLiveIn ( <STR_LIT> ) ) return false ; } break ; case FrameHelperType :: EpilogTail : { if ( NextMBBI == MBB . end


<s> unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) :


<s> bool useRetpolineIndirectBranches ( ) const { return


<s> if ( I != Table + N && I -> from == Opcode ) return I -> to ; return -


<s> vrev32_p16 ( poly16x4_t a ) { return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { llvm_unreachable ( <STR_LIT> ) ; return


<s> machine_mode mode ; rtx op0 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; rtx op1 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( operands [ <NUM_LIT> ] != const1_rtx && operands [ <NUM_LIT> ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , <NUM_LIT> ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveRegX ( unsigned Reg , int Offset ) { EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveRegX , Reg ,


<s> unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , St . getPointerInfo ( ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ; Offset += EltOffset


<s> auto LoopBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopBB ) ; MF -> insert ( ++ LoopBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoopBB , DL , TII -> get ( OpCode ) ) . addDef ( AddressReg ) . addReg ( AddressReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) . setMIFlags ( MI . getFlags ( ) ) ; BuildMI ( LoopBB , DL , TII -> get ( <STR_LIT> ) ) . addDef ( SizeReg ) . addReg ( SizeReg ) . addImm ( <NUM_LIT> * <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( SizeReg ) . addMBB ( LoopBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs


<s> n = expand_binop ( SImode , lshr_optab , n , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_move_insn ( o , gen_lowpart ( mode , n )


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( RHS . getNode ( ) ) ; APInt CnstBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; bool IsCnst = BVN && resolveBuildVector ( BVN , CnstBits , UndefBits ) ; bool IsZero = IsCnst && ( CnstBits == <NUM_LIT> ) ; if ( SrcVT . getVectorElementType ( ) . isFloatingPoint ( ) ) { switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Fcmeq ; if ( IsZero ) Fcmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Fcmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fcmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> Inst . addOperand ( MCOperand :: createImm ( ( ( int64_t ) Imm << ( <NUM_LIT> - sz ) ) >> ( <NUM_LIT>


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> fprintf ( stream , <STR_LIT> ) ; OUTPUT_QUOTED_STRING ( stream , name ) ; fprintf ( stream , <STR_LIT>


<s> return ( __m128d ) __builtin_ia32_mulsd ( ( __v2df ) __A , (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoLoop . VCTP ) ; LoLoop . VCTP -> eraseFromParent ( ) ; for ( auto * MI : LoLoop . VPTUsers ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent (


<s> int nds32_fp_as_gp_check_available (


<s> AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI


<s> EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isCall ( ) ) continue ; if ( IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } return


<s> getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( ( type -> isVectorTy ( ) || type -> isFloatingPointTy ( ) ) && Subtarget . hasVector ( ) ) weight = CW_Register ; break ; case 'I'


<s> unsigned <ISA_LIT>FastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! TargetSupported ) return <NUM_LIT> ; assert ( TLI . getValueType ( DL , AI -> getType ( ) , true ) == <STR_LIT> && <STR_LIT> ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) ; return ResultReg ; } return <NUM_LIT>


<s> val = operands [ <NUM_LIT> ] ; model = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , <NUM_LIT> ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model


<s> HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; if ( MI -> mayStore ( ) ) { unsigned Reg128UndefImpl = ( Reg128Undef | RegState :: Implicit ) ; MachineInstrBuilder ( MF , EarlierMI ) . addReg ( Reg128 , Reg128UndefImpl ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg128 , ( Reg128UndefImpl | Reg128Killed ) ) ; } MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; if ( EarlierMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && EarlierMI -> getOperand ( <NUM_LIT> ) . isUse ( ) ) EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm ( ) ) ; assert ( HighOpcode && LowOpcode && <STR_LIT> ) ; EarlierMI -> setDesc ( get ( HighOpcode ) ) ; MI -> setDesc ( get ( LowOpcode )


<s> void addFGR64AsmRegOperands ( MCInst & Inst , unsigned


<s> if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry


<s> return ( __mmask16 ) __builtin_ia32_ptestnmd512 ( ( __v16si ) __A , ( __v16si )


<s> if ( Result == MatchOperand_ParseFail ) { Parser . eatToEndOfStatement ( ) ; return Result ; } std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( ! Op ) Op = parseImmediate ( ) ; if ( ! Op ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return MatchOperand_ParseFail


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> if ( I -> getNumUses ( ) != <NUM_LIT> ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) ==


<s> Value * <ISA_LIT>IREmitter :: visitFMAXC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls (

) ) Offset -= getOffsetOfLocalArea ( ) ;


<s> return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> )

, INTVAL ( tocrel_offset ) , mode ) ) ) ;


<s> bool hasV7Ops ( ) const { return getSTI ( ) . getFeatureBits ( ) [


<s> { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , } ; MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned TypeIndex , OpIndex ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; if ( ! Subtarget -> is64Bit ( ) ) return false ; break ; } switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SDiv : OpIndex = <NUM_LIT> ; break ; case Instruction :: SRem : OpIndex = <NUM_LIT> ; break ; case Instruction :: UDiv : OpIndex = <NUM_LIT> ; break ; case Instruction :: URem : OpIndex = <NUM_LIT> ; break ; } const DivRemEntry & TypeEntry = OpTable [ TypeIndex ] ; const DivRemEntry :: DivRemResult & OpEntry = TypeEntry . ResultTable [ OpIndex ] ; Register Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; Register Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( OpEntry . OpCopy ) , TypeEntry . LowInReg ) . addReg ( Op0Reg ) ; if ( OpEntry . OpSignExtend ) { if ( OpEntry . IsOpSigned ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( OpEntry . OpSignExtend ) ) ; else { Register Zero32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII


<s> FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE


<s> unsigned NumArgs = Outs . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; if ( IsRet ) { if ( RetCC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr )


<s> void printROROperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O


<s> Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB -> copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg (


<s> EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; assert ( OpVT == <STR_LIT> || ( OpVT == <STR_LIT> ) ) ; EVT floatVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Op . getValueType ( ) == <STR_LIT> && ( ! hasHardQuad || ! TLI . isTypeLegal ( OpVT ) ) ) { const char * libName = TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: SINTTOFP_I32_F128 : RTLIB :: SINTTOFP_I64_F128 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( OpVT ) ) return SDValue ( ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , floatVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned opcode = ( OpVT == <STR_LIT>


<s> SDNodeTreeBuilder b ( V , & DAG ) ; MVT VT = V . getSimpleValueType ( ) ; if ( VT . bitsLT ( ToVT ) ) return b . ZERO_EXTEND ( V


<s> unsigned <ISA_LIT>ELFObjectWriter :: GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { if ( ! IsPCRel ) { llvm_unreachable ( <STR_LIT> ) ; } unsigned Type = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> MachineInstr * DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return <NUM_LIT> ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; FalseReg . setImplicit


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo ->

getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ;


<s> return getSubtargetImpl ( ) -> getRegisterInfo


<s> bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , STI . getFeatureBits ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Name , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned prfop = Mapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Tok . getString ( ) , S , getContext


<s> return ( CONST_INT_P ( op1 ) && satisfies_constraint_eI ( op1 ) && ! satisfies_constraint_I ( op1 ) && ! satisfies_constraint_L ( op1 ) ) ; } if ( ! TARGET_PCREL || GET_MODE ( dest ) != Pmode ) return false ; if ( ! SYMBOL_REF_P ( src ) && ! LABEL_REF_P ( src ) && GET_CODE ( src ) != CONST


<s> for ( i = <NUM_LIT> ; VEC_iterate ( extern_symbol , extern_symbols , i , p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> )

) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ;


<s> else { emit_move_insn ( scratch1 , GEN_INT ( delta ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch1 ) ) ; } if ( vcall_offset ) { rtx offset_addr ; if ( ! did_load ) emit_load_ptr ( scratch0 , this_rtx ) ; offset_addr = plus_constant ( Pmode , scratch0 , vcall_offset ) ; if ( strict_memory_address_p ( ptr_mode , offset_addr ) ) ; else if ( ! TARGET_SH5 && scratch0 != scratch1 ) { emit_move_insn ( scratch1 , GEN_INT ( vcall_offset ) ) ; offset_addr = gen_rtx_PLUS ( Pmode , scratch0 , scratch1 ) ; } else if ( CONST_OK_FOR_ADD ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch0 , GEN_INT ( vcall_offset ) ) ) ; offset_addr = scratch0 ; } else if ( scratch0 != scratch1 ) { emit_move_insn ( scratch1 , GEN_INT ( vcall_offset ) ) ; emit_insn ( gen_add2_insn ( scratch0 , scratch1 ) ) ; offset_addr = scratch0 ; } else gcc_unreachable ( ) ; emit_load_ptr ( scratch0 , offset_addr ) ; if ( Pmode != ptr_mode ) scratch0 = gen_rtx_TRUNCATE ( ptr_mode , scratch0 ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch0 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( TARGET_SH1 && ! flag_weak ) sibcall = gen_sibcalli_thunk ( funexp , const0_rtx ) ; else if ( TARGET_SH2 && flag_pic ) { if ( TARGET_FDPIC ) { sibcall = gen_sibcall_pcrel_fdpic ( funexp , const0_rtx ) ; XEXP ( XVECEXP ( sibcall , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) = scratch2 ; } else { sibcall = gen_sibcall_pcrel ( funexp , const0_rtx ) ; XEXP ( XVECEXP ( sibcall , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) = scratch2 ; } } else { if ( TARGET_SHMEDIA && flag_pic ) { funexp = gen_sym2PIC ( funexp ) ; PUT_MODE ( funexp , Pmode ) ; } emit_move_insn ( scratch2 , funexp ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , scratch2 ) ; sibcall = gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ; } sibcall = emit_call_insn ( sibcall ) ; SIBLING_CALL_P ( sibcall ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( sibcall ) , this_rtx ) ; emit_barrier ( ) ; insns = get_insns ( ) ; if ( optimize > <NUM_LIT> ) { if ( ! cfun -> cfg ) init_flow ( cfun ) ; split_all_insns_noflow (


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase


<s> EVT VT = Op . getValueType ( ) ; SDValue V = Op . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) . isVector ( ) ) { assert ( V . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; <STR_LIT> Pred = cast < TestCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ( Pred == <STR_LIT> ) || ( Pred == <STR_LIT> ) ) { V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V ) ; Pred = ( Pred == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } SDValue Pg = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; <STR_LIT> CC = changeTestCCTo<ISA_LIT>CC ( Pred ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Pg , V ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget . getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal -


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent (


<s> if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , DB ? DB -> Name : <STR_LIT> , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! DB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Mnemonic == <STR_LIT> && DB -> Encoding != <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , Tok . getString ( ) , getLoc ( ) , getContext (


<s> rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( VOIDmode , target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn )


<s> if ( ! TARGET_USE_SAHF && ! optimize_size ) return <NUM_LIT> ; ix86_fp_comparison_codes ( code , & bypass_code , &


<s> if ( AM . hasBaseOrIndexReg ( ) ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( G -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || M == CodeModel :: Small || M == CodeModel :: Kernel ) { assert ( N . getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP ->


<s> const int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Ty -> isVectorTy ( ) && Ty -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( Ty -> getVectorNumElements (


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> skipInterleaving = true ; break ; } } if ( skipInterleaving ) continue ; std :: list < MachineInstr * > InstrsM ; std :: list < MachineInstr * > InstrsS1 ; std :: list < MachineInstr * > InstrsS2 ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> isTerminator ( ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_5Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( std :: next ( I ) == E ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I


<s> void <ISA_LIT>TargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef Value ) { setAttributeItem ( Attribute , Value ,


<s> bool isLegalMaskedGather ( Type * DataType


<s> assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> *


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL ,

TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != <STR_LIT> && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true


<s> if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ; return


<s> bool isVectorIndexH ( ) const { return Kind == k_VectorIndex && VectorIndex .


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { O << '%' ; unsigned Reg = MO . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : O << '$' << MO . getImm ( ) ; return ; case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : { O << '$' ; printSymbolOperand ( MO ,


<s> const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( LEAOpcode , Offset ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( IsScale1 && ( DstR == BaseR || DstR == IndexR ) ) { const MachineOperand & Src = DstR == BaseR ? Index : Base ; MachineInstr * NewMI = BuildMI ( MBB , MI , DL , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( MBB , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } return NewMI ; } if ( ! IsInefficientBase || ( ! IsInefficientIndex && IsScale1 ) ) { MachineInstr * NewMI = BuildMI ( MBB , MI , DL , TII -> get ( LEAOpcode ) ) . add ( Dst ) . add ( IsInefficientBase ? Index : Base ) . add ( Scale ) . add ( IsInefficientBase ? Base : Index ) . addImm ( <NUM_LIT> ) . add ( Segment ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; if ( hasLEAOffset ( Offset ) ) { NewMI = BuildMI ( MBB , MI , DL , ADDri , DstR ) . addReg ( DstR ) . add ( Offset ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } return NewMI ; } assert ( SSDstR != BaseR && <STR_LIT> ) ; assert ( IsInefficientBase && <STR_LIT> ) ; if ( IsScale1 && ! hasLEAOffset ( Offset ) ) { bool BIK = Base . isKill ( ) && BaseR != IndexR ; TII -> copyPhysReg ( MBB , MI , DL , DstR , BaseR , BIK ) ; LLVM_DEBUG ( MI . getPrevNode ( ) -> dump ( ) ; ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DL , ADDrr , DstR ) . addReg ( DstR ) . add ( Index ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; return NewMI ; } MachineInstr * NewMI = BuildMI ( MBB , MI , DL , TII -> get ( LEAOpcode ) ) . add ( Dst ) . addReg ( <NUM_LIT> ) . add ( Scale ) . add ( Index ) . add ( Offset ) . add ( Segment ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; NewMI = BuildMI ( MBB , MI , DL , ADDrr , DstR ) . addReg ( DstR ) . add ( Base ) ; LLVM_DEBUG ( NewMI -> dump (


<s> TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; unsigned RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned RD2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( RD1 ) . addMBB ( FBB ) . addReg ( RD2 ) . addMBB ( TBB ) ; MI -> eraseFromParent (


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ unreachable ( <STR_LIT> ) ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_MM64 : \ case TYPE_MM32 : \ case TYPE_MM : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _MM0 + index ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ if ( index > <NUM_LIT> ) \ * valid =

<NUM_LIT> ; \ return prefix ## _DR0 + index ; \ case TYPE_CR32 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ECR0 + index ; \ case TYPE_CR64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _RCR0 + index ; \ } \ }


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const mips_lo_sum_offset * entry ) { return mips_hash_base ( entry -> base


<s> bool ClobbersEFLAGS = false ; for ( const MachineOperand & MO : Orig . operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { ClobbersEFLAGS = true ; break ; } } if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig . getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig . getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; } if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftLeftFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT>


<s> for ( regno = GR_REG ( <NUM_LIT> ) ; regno <= GR_REG ( <NUM_LIT> ) ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) { current_frame_info . gr_used_mask |= <NUM_LIT> << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; if ( regno < ( <NUM_LIT> - frame_pointer_needed


<s> } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; CreateNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; return getTargetShuffleNode ( <STR_LIT> , dl , VT ,


<s> if ( DestReg == SrcReg && Offset == <NUM_LIT> ) return ; bool isSub = Offset < <NUM_LIT> ; if ( isSub ) Offset = - Offset ; unsigned Opc ; if ( SetNZCV ) Opc = isSub ? <STR_LIT> : <STR_LIT> ; else Opc = isSub ? <STR_LIT> : <STR_LIT> ; const unsigned MaxEncoding = <NUM_LIT> ; const unsigned ShiftSize = <NUM_LIT> ; const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; while ( ( ( unsigned ) Offset ) >= ( <NUM_LIT> << ShiftSize ) ) { unsigned ThisVal ; if ( ( ( unsigned ) Offset ) > MaxEncodableValue ) { ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -=


<s> void <ISA_LIT>InstrInfo :: expandZExtPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned Size ) const { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size , MI .

getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ;


<s> if ( ! FullRegNamesWithPercent || TT . getOS ( ) == Triple :: AIX ) return false ; switch ( RegName [ <NUM_LIT> ] ) { default : return false ; case 'r' : case 'f' : case 'q' : case 'v'


<s> reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveInsn ( ) ; getParser ( ) . Lex ( ) ; return false


<s> bool <ISA_LIT>LoadStoreOpt :: findMatchingStore ( MachineBasicBlock :: iterator I , unsigned Limit , MachineBasicBlock :: iterator & StoreI ) { MachineBasicBlock :: iterator B = I -> getParent ( ) -> begin ( ) ; MachineBasicBlock :: iterator MBBI = I ; MachineInstr & LoadMI = * I ; Register BaseReg = getLdStBaseOp ( LoadMI ) . getReg ( ) ; if ( MBBI == B ) return false ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { MBBI = prev_nodbg ( MBBI , B ) ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) ) return false ; if ( MI . mayStore ( ) && LoadMI . mayAlias ( AA , MI , false ) ) return false ; } while ( MBBI != B


<s> else if ( checkDenormalAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , DenormalMode :: getPositiveZero ( ) ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else { if ( ! STI . hasVFP2Base ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3Base ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . NoTrappingFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( STI . isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( MMI ) { if ( const Module * SourceModule = MMI -> getModule ( ) ) { if ( auto WCharWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ) { int WCharWidth = WCharWidthValue -> getZExtValue ( ) ; assert ( ( WCharWidth == <NUM_LIT> || WCharWidth == <NUM_LIT> ) && <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , WCharWidth ) ; } if ( auto EnumWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ) { int EnumWidth = EnumWidthValue -> getZExtValue ( ) ; assert ( ( EnumWidth == <NUM_LIT> || EnumWidth == <NUM_LIT> ) && <STR_LIT> ) ; int EnumBuildAttr = EnumWidth == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; ATS . emitAttribute ( <STR_LIT> , EnumBuildAttr ) ; } auto * PACValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ; if ( PACValue && PACValue -> getZExtValue ( ) == <NUM_LIT> ) { if ( ! STI . hasPACBTI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } auto * BTIValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT>


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getTLSCallPreservedMask (


<s> case 'Y' : if ( StringRef ( constraint ) . size ( ) != <NUM_LIT> ) break ; switch ( constraint [ <NUM_LIT> ] ) { default : return CW_Invalid ; case 'z' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) ) return CW_SpecificReg ; return CW_Invalid ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) return CW_Register ; return CW_Invalid ; case 'm' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget . hasMMX ( ) ) return weight ; return CW_Invalid ; case 'i' : case 't' : case '2' : if ( ! Subtarget . hasSSE2 ( ) ) return CW_Invalid ; break ; } break ; case 'v' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; LLVM_FALLTHROUGH ; case 'x' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) ) weight = CW_Register ; break ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> bool WordInt = Src . getSimpleValueType ( ) . SimpleTy == <STR_LIT> ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned MovOpc = ( WordInt && ! Signed ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( MovOpc , dl , <STR_LIT> ,


<s> else { if ( size >= <NUM_LIT> ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= <NUM_LIT> ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = <NUM_LIT> ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , <NUM_LIT> ) ; destmem = offset_address ( destmem , GEN_INT ( - <NUM_LIT> * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , <NUM_LIT> ) ; srcmem = offset_address ( srcmem , GEN_INT ( - <NUM_LIT> * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = <NUM_LIT> ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label (


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem .


<s> auto Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; auto Op2 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; auto Pg = getPredicateForFixedLengthVector ( DAG , DL , InVT ) ; EVT CmpVT = Pg . getValueType ( ) ; auto Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , { Pg , Op1 , Op2 , Op . getOperand ( <NUM_LIT> ) } ) ; EVT PromoteVT = ContainerVT . changeTypeToInteger ( ) ; auto Promote = DAG . getBoolExtOrTrunc ( Cmp , DL , PromoteVT ,


<s> if ( MO . getReg ( ) == <STR_LIT> ) { if ( MO . isUse ( ) ) return false ; SeenDef = true ; } } if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugValue ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugValue ( ) ) -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) SawKill = true ; if ( MO . isReg ( ) && MO . getReg (


<s> getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = get<ISA_LIT>RegisterNumbering ( MO1 . getReg (


<s> CodeModel :: Model CModel = TM . getCodeModel ( ) ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; unsigned char GVFlags = <ISA_LIT>SubTarget -> classifyGlobalReference ( GV ) ; if ( GVFlags


<s> static const char * const ABICalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , nullptr } ; for ( const char * const * I = ABICalls ; * I != nullptr ; ++ I ) if ( strcmp ( CalleeName , * I ) == <NUM_LIT> ) return true ; return false