<s> return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( ConstantSDNode * CN = cast < ConstantSDNode > ( Addr ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; Index = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc (


<s> } const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> isBarrier ( ) ) { clearStack ( ) ; Skip = <NUM_LIT> ; ++ MII ; continue ; } unsigned Domain = MCID . TSFlags & <STR_LIT> ; if ( Domain == <STR_LIT> ) { if ( ++ Skip == <NUM_LIT> ) pushStack ( <NUM_LIT> ) ; } else { Skip = <NUM_LIT> ; unsigned MulOpc , AddSubOpc ; bool NegAcc , HasLane ; if ( ! TII -> isFpMLxInstruction ( MCID . getOpcode ( ) , MulOpc , AddSubOpc , NegAcc , HasLane ) || ! FindMLxHazard ( MI ) ) pushStack ( MI ) ; else { ExpandFPMLxInstruction ( MBB , MI , MulOpc , AddSubOpc , NegAcc , HasLane ) ; E = MBB . rend ( ) ; Changed = true ; continue ; } } ++ MII ; } return


<s> struct ShuffleSourceInfo { SDValue Vec ; unsigned MinElt ; unsigned MaxElt ; SDValue ShuffleVec ; int WindowBase ; int WindowScale ; bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src .


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ; return SDValue


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ; } EmitToStreamer ( * OutStreamer


<s> SDValue V = insert128BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot


<s> EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned DestReg = createResultReg (


<s> bool KillSrc0 = false , KillSrc1 = false ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( MOSrc0 ) { Src0 = MOSrc0 -> getReg ( ) ; KillSrc0 = MOSrc0 -> isKill ( ) ; MOSrc0 -> setIsKill ( false ) ; if ( MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) { assert ( MOSrc0 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( MOSrc1 ) { Src1 = MOSrc1 -> getReg ( ) ; KillSrc1 = MOSrc1 -> isKill ( ) ; MOSrc1 -> setIsKill ( false ) ; if ( MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) { assert ( MOSrc1 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } } if ( ! Src0 ) { SubReg0 = <NUM_LIT> ; Src0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src0 , OrigSrc0 , KillSrc0 ) ; KillSrc0 =


<s> return static_cast < MCELFStreamer & > ( Streamer


<s> static SDValue lowerFABS32 ( SDValue Op , SelectionDAG & DAG , bool HasExtractInsert ) { SDLoc DL ( Op ) ; SDValue Res , Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasExtractInsert ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true


<s> SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_32AsmBackend ( T , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T


<s> bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! Subtarget . hasFastHorizontalOps ( ) && ! OptForSize ) return SDValue ( ) ; unsigned HorizOpcode = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) ) || ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSE3 ( ) ) ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; SDValue Hi = extract128BitVector ( Rdx , NumElts / <NUM_LIT> , DAG , DL ) ; SDValue Lo = extract128BitVector ( Rdx , <NUM_LIT> , DAG , DL ) ; Rdx = DAG . getNode ( HorizOpcode , DL , Lo . getValueType ( ) , Hi , Lo ) ; VecVT = Rdx . getValueType ( ) ; } if ( ! ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) ) && ! ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSE3 ( ) ) ) return SDValue ( ) ; unsigned ReductionSteps = Log2_32 ( VecVT . getVectorNumElements ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != ReductionSteps ; ++ i ) Rdx = DAG . getNode ( HorizOpcode , DL , VecVT , Rdx , Rdx ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> bool isVecListFourQWordIndexed ( ) const { if ( ! isDoubleSpacedVectorIndexed ( ) ) return


<s> void addRegCRBITRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> if ( ! insn ) return false ; type = get_attr_type ( insn ) ; if ( is_microcoded_insn ( insn ) ) return true ; if ( which_group == current_group ) { if ( is_branch_slot_insn ( insn ) ) return true ; return false ; } else if ( which_group == previous_group ) { if ( is_dispatch_slot_restricted ( insn ) )


<s> addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) )


<s> if ( ! isSequentialOrUndefInRange ( Mask , ZeroLo , Len , Mask [ ZeroLo ] ) ) return SDValue ( ) ; unsigned Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; ArrayRef < int > StubMask = Mask . slice ( ZeroLo , Len ) ; if ( ! isUndefOrInRange ( StubMask , <NUM_LIT> , NumElts ) && ! isUndefOrInRange ( StubMask , NumElts , <NUM_LIT> * NumElts ) ) return SDValue ( ) ; SDValue Res = Mask [ ZeroLo ] < ( int ) NumElts ? V1 : V2 ; Res = DAG . getBitcast ( <STR_LIT> , Res ) ; if ( ZeroLo == <NUM_LIT> ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * ZeroHi , DL , <STR_LIT> ) ) ; } else if ( ZeroHi == <NUM_LIT> ) { unsigned Shift = Mask [ ZeroLo ] % NumElts ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift , DL , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * ZeroLo , DL , <STR_LIT> ) ) ; } else if ( ! Subtarget . hasSSSE3 ( ) ) { unsigned Shift = ( NumElts - <NUM_LIT> ) - ( Mask [ ZeroLo + Len - <NUM_LIT> ] % NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getTargetConstant ( Scale * Shift ,


<s> const TypeSize & TySize = Ty -> getPrimitiveSizeInBits ( ) ; if ( TySize . isScalable ( ) && TySize . getKnownMinSize ( ) > <NUM_LIT> ) return true ; return false


<s> if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( <NUM_LIT> ) , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_binop ( SImode , ashl_optab , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pmask =


<s> return ( __m256d ) __builtin_ia32_vpermilvarpd256_mask ( ( __v4df ) __A , ( __v4di ) __C , ( __v4df ) _mm256_setzero_pd ( ) ,


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; const static MCFixupKindInfo InfosBE [ <STR_LIT>


<s> MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) MRI . setPhysRegUsed ( <STR_LIT> [ I ] ) ; if ( HasFP ) MRI . setPhysRegUsed ( <STR_LIT> ) ; if ( MFFrame -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; const uint16_t * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) { DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , NULL , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> return parseRegister ( Operands , RegGR , <STR_LIT>


<s> if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> ) return false ; return TLI . isTypeLegal


<s> break ; case CmpInst :: FCMP_FALSE : ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) ; break ; case CmpInst :: FCMP_TRUE : ResultReg = fastEmit_i ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; break ; } if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; } if ( ! emitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; static unsigned CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned * CondCodes = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_ONE : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } if ( CondCodes ) { Register TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg

( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ;


<s> if ( ! F || ! canReuseBoundaryAlignFragment ( * F ) ) { F = new MCBoundaryAlignFragment ( AlignBoundary ) ; OS . insert ( F


<s> if ( Cond . size ( ) != <NUM_LIT> ) return true ; assert ( MBP . TrueDest && <STR_LIT> ) ; if ( ! MBP . FalseDest ) MBP . FalseDest = MBB . getNextNode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( auto I = std :: next ( MBB . rbegin ( ) ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) { ConditionDef = & * I ; break ; } if ( I -> readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == <NUM_LIT> && ConditionDef -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( ConditionDef -> getOperand ( <NUM_LIT> ) ) && ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) ) { MBP . LHS = ConditionDef -> getOperand (


<s> bool <ISA_LIT>AsmParser :: mnemonicIsValid ( StringRef Mnemonic , unsigned VariantID ) { const MatchEntry * Start , * End ; switch ( VariantID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Start = std :: begin ( MatchTable0 ) ; End = std :: end ( MatchTable0 ) ; break ; } auto MnemonicRange = std :: equal_range ( Start , End , Mnemonic , LessOpcode ( ) ) ; return MnemonicRange . first !=


<s> if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getSetCC ( DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , <STR_LIT> ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> ,


<s> BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; unsigned RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned RD2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) )

. addReg ( RD1 ) . addMBB ( FBB ) . addReg ( RD2 ) . addMBB ( TBB ) ;


<s> auto r = insn -> bytes ; uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret =


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) context -> ireg [ i - <NUM_LIT> ] . loc = & sc -> sc_gr [ i ] ; } context -> pfs_loc = & ( sc -> sc_ar_pfs ) ; context -> lc_loc = & ( sc -> sc_ar_lc ) ; context -> unat_loc = & ( sc -> sc_ar_unat ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> pr = sc -> sc_pr ; context -> gp = sc -> sc_gr [ <NUM_LIT> ] ; fs -> no_reg_stack_frame = <NUM_LIT> ; if ( sc -> sc_rbs_base ) { long ndirty , loadrs = sc -> sc_loadrs >> <NUM_LIT> ; unsigned long alt_bspstore = context -> bsp - loadrs ; unsigned long bspstore ; unsigned long * ar_bsp = ( unsigned long * ) ( sc -> sc_ar_bsp ) ; ndirty = ia64_rse_num_regs ( ( unsigned long * ) alt_bspstore , ( unsigned long * ) context -> bsp ) ; bspstore = ( unsigned long ) ia64_rse_skip_regs ( ar_bsp , - ndirty ) ; ia64_copy_rbs ( context , bspstore , alt_bspstore , loadrs , sc -> sc_ar_rnat ) ; } { unsigned long sof = sc -> sc_cfm &


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitMappingSymbol ( <STR_LIT> ) ; MCELFStreamer :: emitInstruction ( Inst ,


<s> if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , ( ( is64Bit ) ? <STR_LIT> : <STR_LIT> ) , <NUM_LIT> ) ; return Op


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , A


<s> if ( Pic ) <ISA_LIT>TargetStreamer :: emitDirectiveCpLocal ( RegNo


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ) return true ; return MCInstrAnalysis :: isUnconditionalBranch


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( )

== Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> u . f [ <NUM_LIT> ] = a ; u . f [ <NUM_LIT>


<s> const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind )


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) EmitAlignment ( <NUM_LIT> ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI ,


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return new ScheduleDAGMI ( C , std :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C )


<s> if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , <NUM_LIT> ) ; size_t len = strlen ( XSTR ( sym_ref , <NUM_LIT> ) ) ; char * str = XALLOCAVEC ( char , len +


<s> unsigned <ISA_LIT>CodeEmitter :: getMemEncodingMMImm12 ( const MachineInstr & MI , unsigned OpNo


<s> static struct bundle_state * get_free_bundle_state ( void ) { struct bundle_state * result ; if ( free_bundle_state_chain != NULL ) { result = free_bundle_state_chain ; free_bundle_state_chain = result -> next ; } else { result = XNEW ( struct bundle_state ) ; result -> dfa_state = xmalloc ( dfa_state_size ) ; result -> allocated_states_chain


<s> const SmallVectorImpl < unsigned > & RegList = Op . getRegList ( ) ; uint32_t Mask = <NUM_LIT> ; for ( size_t i = <NUM_LIT> ; i < RegList . size ( ) ; ++ i ) { unsigned Reg = MRI -> getEncodingValue ( RegList [ i ] ) ; assert ( Reg < <NUM_LIT> && <STR_LIT> ) ; unsigned Bit = ( <NUM_LIT> << Reg ) ; Mask |= Bit ; } if ( Mask == <NUM_LIT> ) return Error ( L , <STR_LIT> ) ; unsigned First = <NUM_LIT> ; while ( ( Mask & <NUM_LIT> ) == <NUM_LIT> ) { First ++ ; Mask >>= <NUM_LIT> ; } if ( ( ( Mask + <NUM_LIT> ) & Mask ) != <NUM_LIT> ) return Error ( L , <STR_LIT> ) ; unsigned Last = First ; while ( ( Mask & <NUM_LIT> ) != <NUM_LIT> ) { Last ++


<s> if ( Sec . getKind ( ) . isExecuteOnly ( ) && ! TextSection -> hasInstructions ( ) && ! TextSection -> hasData ( ) ) { TextSection -> setFlags ( TextSection -> getFlags ( ) | ELF ::


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; unsigned Opcode = Cond [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; MachineOperand LHS = Cond [ <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerUINT_TO_FP_vec ( SDValue Op , SelectionDAG & DAG ) const { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; switch ( SVT . SimpleTy ) { default : llvm_unreachable (


<s> static bool isV8M ( const <ISA_LIT>Subtarget * Subtarget ) { return ( Subtarget -> hasV8MBaselineOps ( ) && ! Subtarget ->

hasV6T2Ops ( ) ) || Subtarget -> hasV8MMainlineOps ( ) ;


<s> if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner RetAssigner ( AssignFn ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; return determineAndHandleAssignments ( RetHandler , RetAssigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( ) ,


<s> static bool hasMFENCE ( const <ISA_LIT>Subtarget & Subtarget


<s> void <ISA_LIT>DAGToDAGISel :: PreprocessISelDAG ( ) { SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = -- Position ; if ( N -> use_empty ( ) ) continue ; SDValue Res ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : Res = combineToCMPB ( N ) ; break ; } if ( ! Res ) foldBoolExts ( Res ,


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF .


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT


<s> for ( unsigned int i = <NUM_LIT> ; i < __TYPE_FINAL ; ++ i ) if ( arm_simd_types [ i ] . eltype == eltype && GET_MODE_SIZE ( arm_simd_types [ i ] . mode ) == <NUM_LIT> ) return arm_simd_types [ i ] . itype ; gcc_unreachable (


<s> Add = MCConstantExpr :: Create ( SymbolicOp . AddSymbol . Value , * Ctx ) ; } } const MCExpr * Sub = NULL ; if ( SymbolicOp . SubtractSymbol . Present ) { if ( SymbolicOp . SubtractSymbol . Name ) { StringRef Name ( SymbolicOp . SubtractSymbol . Name ) ; MCSymbol * Sym = Ctx -> GetOrCreateSymbol ( Name ) ; Sub = MCSymbolRefExpr :: Create ( Sym , * Ctx ) ; } else { Sub = MCConstantExpr :: Create ( SymbolicOp . SubtractSymbol . Value , * Ctx ) ; } } const MCExpr * Off = NULL ; if ( SymbolicOp . Value != <NUM_LIT> ) Off = MCConstantExpr :: Create ( SymbolicOp . Value , * Ctx ) ; const MCExpr * Expr ; if ( Sub ) { const MCExpr * LHS ; if ( Add ) LHS = MCBinaryExpr :: CreateSub ( Add , Sub , * Ctx ) ; else LHS = MCUnaryExpr :: CreateMinus ( Sub , * Ctx ) ; if ( Off != <NUM_LIT> ) Expr = MCBinaryExpr :: CreateAdd ( LHS , Off , * Ctx ) ; else Expr =


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterMCAsmParser < <ISA_LIT>ATTAsmParser > Y ( The<ISA_LIT>_64Target


<s> SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant


<s> assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) { MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else { NumStoreSPILLVSRRCAsGpr ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; } return true ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) MI . setDesc ( get ( <STR_LIT> ) ) ; else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get


<s> MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl , VTList


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <STR_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm


<s> MachineInstr * getLast ( ) const { return LastInst


<s> if ( ! ( Ty -> getNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT>


<s> if ( ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || ! isImmSExti64i8Value ( Inst . getOperand ( <NUM_LIT>


<s> static const CostTblEntry CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT>

* FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ;


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitPCMPEQM ( const SDNode *


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast <


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue V ( <NUM_LIT> , <NUM_LIT> ) ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , true , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt = LastElt ; if ( ThisElt . getNode ( ) ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , ThisElt , DAG . getIntPtrConstant ( i / <NUM_LIT> ) ) ; } } return DAG . getNode ( <STR_LIT> , dl


<s> SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain , NegSize , FPSIdx } ; SDVTList VTs = DAG . getVTList (


<s> } if ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) ) Immediate |= ( <NUM_LIT> << idx ) ; } if ( AllContants ) { SDValue FullMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Immediate , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FullMask , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( ! isSplatVector ( Op . getNode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDValue EFLAGS , <ISA_LIT>CC ; if ( In . getOpcode ( ) == <STR_LIT> ) { SDValue Op0 = In . getOperand ( <NUM_LIT> ) ; SDValue Op1 = In . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( In . getOperand ( <NUM_LIT> ) ) -> get ( ) ; bool isFP = Op1 . getValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CCVal = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; assert ( <ISA_LIT>CCVal != <STR_LIT> && <STR_LIT> ) ; <ISA_LIT>CC = DAG . getConstant ( <ISA_LIT>CCVal , <STR_LIT> ) ; EFLAGS = EmitCmp ( Op0 , Op1 , <ISA_LIT>CCVal , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; } else if ( In . getOpcode ( ) == <STR_LIT> ) { <ISA_LIT>CC = In . getOperand ( <NUM_LIT> ) ; EFLAGS = In . getOperand ( <NUM_LIT> ) ; } else { MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; SDValue Bit1 = DAG . getNode ( <STR_LIT> , dl , InVT , In , DAG . getConstant ( <NUM_LIT> , InVT ) ) ; EFLAGS = EmitTest ( Bit1 , <STR_LIT> , DAG ) ; <ISA_LIT>CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; } if ( VT == <STR_LIT> )


<s> bool i386_pe_type_dllimport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && ( DECL_DECLARED_INLINE_P ( decl ) || DECL_TEMPLATE_INSTANTIATION ( decl ) || DECL_ARTIFICIAL ( decl ) ) ) return false ; return


<s> Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , FSZero ) ; Builder . CreateStore ( Next , Builder . CreateStructGEP


<s> if ( min_offset < <NUM_LIT> || max_offset >= <NUM_LIT> ) return SImode ; else { if ( max_offset >= <NUM_LIT> ) return


<s> DebugLoc dl = Node -> getDebugLoc ( ) ; EVT VT = cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , VT , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Zero , Zero , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ; Results . push_back ( Swap . getValue


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle +=


<s> int RegNodeEscapeIndex = escapeRegNode ( F ) ; Function * FrameRecover = <STR_LIT> ( TheModule , <STR_LIT> ) ; Function * FrameAddress = <STR_LIT> ( TheModule , <STR_LIT> ) ; Constant * FI8 = ConstantExpr :: getBitCast ( & F , Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ) ; for ( auto P : FuncInfo . HandlerBaseState ) { Function * Handler = const_cast < Function * > ( P . first ) ; int BaseState = P . second ; IRBuilder < > Builder ( & Handler -> getEntryBlock ( ) , Handler -> getEntryBlock ( ) . begin ( ) ) ; Value * ParentFP = Builder . CreateCall ( FrameAddress , { Builder . getInt32 ( <NUM_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm )


<s> bool useAA ( ) const override { return UseAA


<s> Relocator :: DWord target = pReloc . target ( ) ; Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord A = helper_sign_extend ( target , <NUM_LIT> ) + pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; Relocator :: Address S = pReloc .


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; ArgInfo ArgRetInfo ( VRegs , * Val , <NUM_LIT> ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , RetInfos , DL , F . getCallingConv ( ) ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) ,


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> void <ISA_LIT>InstPrinter :: printLogicalImm32 ( const MCInst * MI , unsigned OpNum , const

MCSubtargetInfo & STI , raw_ostream & O ) {


<s> if ( inverted ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , mask ,

operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> int pa_shadd_constant_p ( int val ) { if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT>


<s> assert ( m_pRelDyn != NULL && <STR_LIT>


<s> std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ; if ( ! LRU . available ( <STR_LIT> ) ) Flags |= MachineOutlinerMBBFlags :: LRUnavailableSomewhere ; return


<s> static SDValue LowerF128_FPROUND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return Op ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F64 ) , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F32 ) , <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue ( )


<s> return ( __a + ( __b * __aarch64_vget_lane_any


<s> int64_t Value = ConstExpr -> getValue ( ) ; return Value != <NUM_LIT> && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; return


<s> float f [ <NUM_LIT> ] ; } d ; union { vec_double2 v ; double d [ <NUM_LIT> ] ; } in ; in . v = ( vec_double2 ) ( a ) ; d . v = ( vec_float4 ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * From << <STR_LIT> << * To << <STR_LIT> ) ; for ( Use & U : From -> uses ( ) ) { auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( InstTo && User -> isIdenticalTo ( InstTo ) ) { ReplacedAll = false ; continue ; } Users . push_back ( User


<s> void <ISA_LIT>InstPrinter :: printExactFPImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; unsigned Half = NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += Half ) { unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ; Idx +=


<s> return mep_lookup_pragma_flag ( funcname ,


<s> unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ; auto & CMovRC = * MRI -> getRegClass ( CMovI . getOperand ( <NUM_LIT> ) . getReg


<s> auto * Store = dyn_cast < StoreInst > ( I ) ; if ( ! Store || ! Store -> isSimple ( ) ) return false ; if ( Store -> getOperand ( <NUM_LIT> ) -> getType ( ) != FixedPredType ) return false ; auto * IntrI = dyn_cast < IntrinsicInst > ( Store -> getOperand ( <NUM_LIT> ) ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; if ( ! cast < ConstantInt > ( IntrI -> getOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return false ; auto * BitCast = dyn_cast < BitCastInst > ( IntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! BitCast ) return false ; if ( BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) != PredType ) return false ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; auto * PtrBitCast = Builder . CreateBitCast ( Store -> getPointerOperand ( ) , PredType -> getPointerTo ( Store -> getPointerAddressSpace ( ) ) ) ; Builder . CreateStore ( BitCast -> getOperand ( <NUM_LIT> ) , PtrBitCast ) ; Store -> eraseFromParent ( ) ; if ( IntrI -> getNumUses ( ) == <NUM_LIT> ) IntrI -> eraseFromParent ( ) ; if ( BitCast -> getNumUses ( ) == <NUM_LIT>


<s> return ( __m512i ) __builtin_ia32_vcvtph2dq512_mask_round ( __C , (


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo


<s> return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O <<


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass

( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> static DecodeStatus DecodeThumbBLTargetOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT>


<s> static tree fully_fold_convert ( tree type , tree expr ) { tree result = fold_convert (


<s> if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( )


<s> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT .


<s> bool isMemoryRegisterOffset64 ( ) const { return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal

== <NUM_LIT> || Mem . ShiftVal == <NUM_LIT> ) ;


<s> if ( isPositionIndependent ( ) ) { SDValue HiLo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT10 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , VT ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , DL , VT , GlobalBase , HiLo ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setHasCalls ( true ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : return makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ; case CodeModel :: Medium : { SDValue H44 = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , DAG ) ; H44 = DAG . getNode ( <STR_LIT> , DL , VT , H44 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue L44 = withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , DAG ) ; L44 = DAG . getNode ( <STR_LIT> , DL , VT , L44 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , H44 , L44 ) ; } case CodeModel :: Large : { SDValue Hi = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , DAG ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Lo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) -> getCallingConv ( ) ) ) return LowerWin64_VASTART ( Op


<s> return <STR_LIT> ; } return <STR_LIT> ; } } if ( TARGET_ALTIVEC ) { rtx splat_vec ; gcc_assert ( ALTIVEC_REGNO_P ( REGNO ( dest ) ) ) ; if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; if ( all_ones_constant ( vec , mode ) ) return <STR_LIT> ; shift = vspltis_shifted ( vec ) ; if ( shift != <NUM_LIT> ) return <STR_LIT> ; splat_vec = gen_easy_altivec_constant ( vec ) ; gcc_assert ( GET_CODE ( splat_vec ) == VEC_DUPLICATE ) ; operands [ <NUM_LIT> ] = XEXP ( splat_vec , <NUM_LIT> ) ; if ( ! EASY_VECTOR_15 ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) return <STR_LIT> ; switch ( GET_MODE ( splat_vec ) ) { case V4SImode : return <STR_LIT> ; case V8HImode : return <STR_LIT> ; case V16QImode


<s> case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K'


<s> Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) ,


<s> static tree arm_mve_type_for_scalar_type ( tree eltype ) { for ( unsigned int i = <NUM_LIT> ; i < __TYPE_FINAL ; ++ i ) if ( arm_simd_types [ i ] . eltype == eltype && GET_MODE_SIZE ( arm_simd_types [ i ] . mode ) == <NUM_LIT> )


<s> MVT VT ; if ( Len >= <NUM_LIT> && i64Legal ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> ) ; VT = <STR_LIT> ; } unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT ,


<s> switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: LParen : { const AsmToken Tok1 = Parser . getTok ( ) ; Parser . Lex ( ) ; unsigned RegNo1 ; SMLoc S1 , E1 ; if ( tryParseRegister ( RegNo1 , S1 , E1 ) != MatchOperand_Success ) { getLexer ( ) . UnLex ( Tok1 ) ; return MatchOperand_NoMatch ; } if ( ! Parser . getTok ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; unsigned RegNo2 ; SMLoc S2 , E2 ; if ( tryParseRegister ( RegNo2 , S2 , E2 ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( ! Parser . getTok ( ) . is ( AsmToken :: RParen ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( Tok1 . getString ( ) , Tok1 . getLoc ( ) ) ) ; Operands . push_back ( <STR_LIT> ( RegNo1 , S1 , E1 ) ) ; Operands . push_back ( <STR_LIT> ( RegNo2 , S2 , E2 ) ) ; Operands . push_back ( <STR_LIT> ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; break ; } default : { std :: unique_ptr < <ISA_LIT>Operand > Op ; ResTy = parse<ISA_LIT>AsmOperand (


<s> void <ISA_LIT>InstPrinterCommon :: printInstFlags ( const MCInst * MI , raw_ostream & O ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT>


<s> if ( LastEMSInfo -> State == EMS_<ISA_LIT> )


<s> union { unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( GetCpuIDAndInfo ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) HasCMov = true ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; HasCLMUL = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasFMA3 = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasAES = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; DetectFamilyModel ( EAX , Family , Model ) ; IsBTMemSlow = IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ; if ( Family == <NUM_LIT> && Model == <NUM_LIT> ) IsUAMemFast = true ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; Has<ISA_LIT>_64 = ( EDX >> <NUM_LIT> ) & <NUM_LIT> ; HasSSE4A = IsAMD && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasFMA4 = IsAMD && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT>


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> return __builtin_mve_vrev64q_m_fv4sf ( __arm_vuninitializedq_f32 ( ) ,


<s> static DecodeStatus DecodeLoadQFP ( MCInst & Inst , unsigned insn , uint64_t Address , const MCDisassembler


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo


<s> opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts ->

x_aarch64_branch_protection_string , NULL ) ;


<s> static __inline void si_stqa ( qword a , unsigned int imm ) { vec_st ( ( vec_uchar16 ) ( a ) , <NUM_LIT> , ( vector unsigned


<s> return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isDataRel ( ) || Kind . isBSS ( ) || Kind . isCommon (


<s> VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if (


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; }


<s> assert ( Op . isImm ( ) && <STR_LIT> ) ; int64_t Res ; if ( ! Op . getImm ( ) -> evaluateAsAbsolute ( Res ) || Res > <NUM_LIT> ) { Error ( Op . getStartLoc ( ) , <STR_LIT> ) ; return false ; } return true ; } llvm_unreachable (


<s> static void getPackDemandedElts ( EVT VT , const APInt & DemandedElts , APInt & DemandedLHS , APInt & DemandedRHS ) { int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumElts = DemandedElts . getBitWidth ( ) ; int NumInnerElts = NumElts / <NUM_LIT> ; int NumEltsPerLane = NumElts / NumLanes ; int NumInnerEltsPerLane =


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( )


<s> default : MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return EmitF128CSEL ( MI , BB ) ; case TargetOpcode :: STACKMAP : case TargetOpcode ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) && <STR_LIT> ) ; MachineOperand & Imm = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; int64_t ImmVal = Imm . getImm ( ) ; Imm . setImm ( <NUM_LIT> | ( ( ImmVal & <NUM_LIT> ) << <NUM_LIT> ) | ( ImmVal & <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> __builtin_ia32_pmovdw256mem_mask ( ( __v8hi * ) __P , (


<s> return getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT>


<s> unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) { MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * CmpMI << <STR_LIT> << * Br . MI ) ; MachineInstr * NewBR = BuildMI ( * MBB , CmpMI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg ) . addMBB ( DestBB , Br . MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ; CmpMI -> eraseFromParent ( ) ; Br . MI -> eraseFromParent ( ) ; Br . MI


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op ,


<s> if ( TARGET_EXPLICIT_RELOCS ) return false ; mips_split_const ( x , & x , & offset ) ; return global_got_operand ( x ,


<s> if ( ! SecondLastOpc ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return true ; if ( SecondLastOpc == <STR_LIT> ) { if ( ! AllowModify ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; return


<s> void setGISelAccessor ( GISelAccessor & GISel ) { this -> GISel . reset


<s> break ; case PLUS : { int base ; rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) && pru_get_ctable_exact_base_index ( INTVAL ( op1 ) ) >= <NUM_LIT> ) { base = pru_get_ctable_exact_base_index ( INTVAL ( op1 ) ) ; fprintf ( file , <STR_LIT> , base , pru_asm_regname ( op0 ) ) ; return ; } else if ( REG_P ( op1 ) && CONST_INT_P ( op0 ) && pru_get_ctable_exact_base_index ( INTVAL ( op0 ) ) >= <NUM_LIT> ) { gcc_unreachable ( ) ; } else if ( REG_P ( op0 ) && CONSTANT_P ( op1 ) ) { fprintf ( file , <STR_LIT> , pru_asm_regname ( op0 ) ) ; output_addr_const ( file , op1 ) ; return ; } else if ( REG_P ( op1 ) && CONSTANT_P ( op0 ) ) { gcc_unreachable ( ) ; } else if ( REG_P ( op1 ) && REG_P (


<s> rtx condition_rtx , loc_ref ; if ( ! reg_or_0_operand ( op0 , SImode ) ) op0 = copy_to_mode_reg ( SImode , op0 ) ; if ( ! reg_or_0_operand ( op1 , SImode ) ) op1 = copy_to_mode_reg ( SImode , op1 ) ; condition_rtx = mt_generate_compare ( code , op0 , op1


<s> static DecodeStatus DecodeFixedPointScaleImm64 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr


<s> static inline uint64_t decodeAdvSIMDModImmType12 ( uint8_t Imm ) { uint64_t EncVal = <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; else EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |=


<s> if ( OldMI -> registerDefIsDead ( <STR_LIT> ) ) { MachineOperand * CCDef = NewMI -> findRegisterDefOperand (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_psrav8si_mask ( ( __v8si ) __X , ( __v8si ) __Y , ( __v8si ) _mm256_setzero_si256 ( ) ,


<s> <ISA_LIT>MCExpr :: VariantKind ExprKind = McExpr -> getKind ( ) ; switch ( ExprKind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO : return


<s> } else { if ( ! HasFP || ( needsStackRealignment ( MF ) && FrameIndex >= <NUM_LIT> ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; FrameReg = getFrameRegister ( MF ) ; if ( FrameIndex >= <NUM_LIT> ) { if ( hasBasePointer ( MF ) ) FrameReg = getBaseRegister ( ) ; else if ( needsStackRealignment ( MF ) ) FrameReg = <STR_LIT> ; } } if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! Reg ) Reg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( Reg && <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( ( uint32_t ) Offset >> <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( Offset & <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> void printf64mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( TwoRepStos ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; Count = Size ; EVT CVT = Count . getValueType ( ) ; SDValue Left = DAG . getNode ( <STR_LIT> , dl , CVT , Count , DAG . getConstant ( ( AVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , CVT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , ( CVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , Left , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( <STR_LIT> ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; } else if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT AddrVT = Dst . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Chain = DAG . getMemset ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , AddrVT , Dst , DAG . getConstant ( Offset , AddrVT ) ) , Src , DAG . getConstant ( BytesLeft , SizeVT ) , Align , isVolatile , DstPtrInfo . getWithOffset ( Offset ) ) ; } return Chain


<s> int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) { if ( SDValue V = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue V = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } switch ( VT .


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> __v4di src = __extension__ ( __v4di ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4di mask = __extension__ ( __v4di ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m256i ) __builtin_ia32_gatherdiv4di ( src , base , ( __v4di ) index


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE41 ( ) { if ( ! Subtarget . hasSSE41 ( ) ) return ; const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; LegacyInfo . setAction ( { G_MUL , v4s32 }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> HARD_REG_SET left ; size = <NUM_LIT> ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( ST_REG_FIRST , mode ) ) size = MIN ( size , <NUM_LIT> ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size , UNITS_PER_FPREG


<s> if ( Inst -> getOperand ( ImmOpPosition ) . getImm ( ) == <NUM_LIT> && Inst -> getOperand ( BaseOpPosition ) . getReg ( ) == <NUM_LIT> ) { Inst -> getOperand ( BaseOpPosition ) . setReg ( IndexReg ) ; Inst -> getOperand ( IndexOpPosition ) . setReg ( <NUM_LIT>


<s> Value * CurrentRow = & * RowLoopHeader -> begin ( ) ; Value * CurrentCol = & * ColLoopHeader -> begin ( ) ; Type * EltTy = B . getInt32Ty ( ) ; FixedVectorType * V256I32Ty = FixedVectorType :: get ( EltTy , <NUM_LIT> ) ; B . SetInsertPoint ( ColBody -> getTerminator ( ) ) ; Value * CurrentRowZExt = B . CreateZExt ( CurrentRow , Stride -> getType ( ) ) ; Value * CurrentColZExt = B . CreateZExt ( CurrentCol , Stride -> getType ( ) ) ; Value * Offset = B . CreateAdd ( B . CreateMul ( CurrentRowZExt , Stride ) , CurrentColZExt ) ; unsigned AS = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; Value * EltBasePtr = B . CreatePointerCast ( Ptr , PointerType :: get ( EltTy , AS ) ) ; Value * EltPtr = B . CreateGEP ( EltTy , EltBasePtr , Offset ) ; Value * Idx = B . CreateAdd ( B . CreateMul ( CurrentRow , B . getInt16 ( <NUM_LIT> ) ) , CurrentCol ) ; if ( IsTileLoad ) { B . SetInsertPoint ( RowLoopHeader -> getTerminator ( ) ) ; Value * VecZero = Constant :: getNullValue ( V256I32Ty ) ; PHINode * VecCPhiRowLoop = B . CreatePHI ( V256I32Ty , <NUM_LIT> , <STR_LIT> ) ; VecCPhiRowLoop -> addIncoming ( VecZero , Start ) ; B . SetInsertPoint ( ColLoopHeader -> getTerminator ( ) ) ; PHINode * VecPhi = B . CreatePHI ( V256I32Ty , <NUM_LIT> , <STR_LIT> ) ; VecPhi -> addIncoming ( VecCPhiRowLoop , RowBody ) ; B . SetInsertPoint ( ColBody -> getTerminator ( ) ) ; Value * Elt = B . CreateLoad ( EltTy , EltPtr ) ; Value * ResVec = B . CreateInsertElement ( VecPhi , Elt , Idx ) ; VecPhi -> addIncoming ( ResVec , ColLoopLatch ) ; VecCPhiRowLoop -> addIncoming ( ResVec , RowLatch ) ; return ResVec ; } else { auto * BitCast = cast < BitCastInst >


<s> assert ( Amount > - <NUM_LIT> && Amount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , Amount , TII ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , - CalleePopAmount , TII ) ; } MBB . erase (


<s> return ( ! TARGET_EXPLICIT_RELOCS && TARGET_USE_GOT && GET_CODE ( x

) == SYMBOL_REF && mips_global_symbol_p ( x ) ) ;


<s> OperandMatchResultTy parseVF128 ( OperandVector &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Align MemAlign = getKnownAlignment ( II . getArgOperand ( <NUM_LIT> ) , IC . getDataLayout ( ) , & II , & IC . getAssumptionCache ( ) , & IC . getDominatorTree ( ) ) ; unsigned AlignArg = II . getNumArgOperands ( ) - <NUM_LIT> ; Value * AlignArgOp = II . getArgOperand ( AlignArg ) ; MaybeAlign Align = cast < ConstantInt > ( AlignArgOp ) -> getMaybeAlignValue ( ) ; if ( Align && * Align < MemAlign ) { return IC . replaceOperand ( II , AlignArg , ConstantInt :: get ( Type :: getInt32Ty ( II . getContext ( ) ) , MemAlign . value ( ) , false ) ) ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } Constant * XorMask ; if ( match ( Arg , m_Xor ( PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) , PatternMatch :: m_Constant ( XorMask ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { if ( auto * CI = dyn_cast < ConstantInt > ( XorMask ) ) { if ( CI -> getValue ( ) . trunc ( <NUM_LIT> ) . isAllOnesValue ( ) ) { auto TrueVector = IC . Builder . CreateVectorSplat ( cast < FixedVectorType > ( II . getType ( ) ) -> getNumElements ( ) , IC . Builder . getTrue ( ) ) ; return BinaryOperator :: Create ( Instruction :: Xor , ArgArg , TrueVector ) ; } } } KnownBits ScalarKnown ( <NUM_LIT> ) ; if ( IC . SimplifyDemandedBits ( & II , <NUM_LIT> , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) , ScalarKnown , <NUM_LIT> ) ) { return & II ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } if ( ! II . getMetadata ( LLVMContext


<s> return flag_pic != <NUM_LIT> ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != <NUM_LIT> ; case CONST : return sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) || sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) ; case


<s> tree aarch64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ]


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveReg ( unsigned Reg , int Offset ) { assert ( Offset >= <NUM_LIT> && Offset <= <NUM_LIT>


<s> unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FPReg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ; break ; case <STR_LIT> : MO . setReg ( BPReg ) ; break ; case <STR_LIT>


<s> static bool sparc_vector_mode_supported_p ( enum machine_mode mode ) { return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true


<s> bool insertVZEROUPPER ( ) const { return InsertVZEROUPPER


<s> bool <ISA_LIT>InstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { return TargetInstrInfo :: verifyInstruction ( MI ,


<s> if ( RM . hasValue ( ) ) return * RM ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . isOSAIX ( ) ) return Reloc


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( Invert ) CCode = <STR_LIT> ( CCode


<s> MRI = & MF . getRegInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ; return


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; Type * RetTy = I -> getType ( ) ; if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc =


<s> MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator I = mf . begin ( ) , E = mf . end ( ) ; I != E

; ++ I ) if ( processMachineBasicBlock ( I ) ) Changed = true ;


<s> int OffsetStride = IsUnscaled ? getMemScale ( FirstMI ) : <NUM_LIT> ; bool IsPromotableZeroStore = isPromotableZeroStoreInst ( FirstMI ) ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits


<s> unsigned Opcode = Instruction :: UserOp1 ; if ( const Instruction * I = dyn_cast < Instruction > ( Obj ) ) { if ( FuncInfo . MBBMap [ I -> getParent ( ) ] != FuncInfo . MBB ) return false ; Opcode = I -> getOpcode ( ) ; U = I ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } if ( const PointerType * Ty = dyn_cast < PointerType > ( Obj -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: Alloca : { assert ( false && <STR_LIT> ) ; return false ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( Obj ) ) { ( void ) GV ; return false ; } Reg = getRegForValue ( Obj ) ; if ( Reg == <NUM_LIT> ) return false ; if ( Offset != <NUM_LIT> ) { <STR_LIT> Pred = <STR_LIT> ; unsigned PredReg = <NUM_LIT> ; if ( ! isThumb ) emit<ISA_LIT>RegPlusImmediate ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , Reg , Reg , Offset , Pred , PredReg , static_cast <

const <ISA_LIT>BaseInstrInfo & > ( TII ) ) ;


<s> OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D1 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D2 ) ; OutStreamer . AddComment ( <STR_LIT>


<s> static unsigned getCompareSourceReg ( MachineInstr * Compare ) { unsigned reg = <NUM_LIT> ; if ( Compare -> isCompare ( ) ) reg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( isLoadAndTestAsCmp ( Compare ) ) reg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( reg ) ; return reg


<s> } auto * Sub = dyn_cast < BinaryOperator > ( LHS ) ; if ( ! Sub || Sub -> getOpcode ( ) != Instruction :: Sub ) return false ; auto getZeroExtendedVal = [ ] ( Value * Op ) -> Value * { if ( auto * ZExt = dyn_cast < ZExtInst > ( Op ) ) if ( cast < VectorType > ( ZExt -> getOperand ( <NUM_LIT> ) -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return ZExt -> getOperand ( <NUM_LIT> ) ; return nullptr ; } ; Value * Op0 = getZeroExtendedVal ( Sub -> getOperand ( <NUM_LIT> ) ) ; Value * Op1 = getZeroExtendedVal ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 ) return false ; IRBuilder < > Builder ( Op ) ; auto * OpTy = cast < FixedVectorType > ( Op -> getType ( ) ) ; unsigned NumElts = OpTy -> getNumElements ( ) ; unsigned IntrinsicNumElts ; <STR_LIT> IID ; if ( ST -> hasBWI ( ) && NumElts >= <NUM_LIT> ) { IID = <STR_LIT> ; IntrinsicNumElts = <NUM_LIT> ; } else if ( ST -> hasAVX2 ( ) && NumElts >= <NUM_LIT> ) { IID = <STR_LIT> ; IntrinsicNumElts = <NUM_LIT> ; } else { IID = <STR_LIT> ; IntrinsicNumElts = <NUM_LIT> ; } Function * PSADBWFn = <STR_LIT> ( Op -> getModule ( ) , IID ) ; if ( NumElts < <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ConcatMask ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ConcatMask [ i ] = i ; for ( unsigned i = NumElts ; i != <NUM_LIT> ; ++ i ) ConcatMask [ i ] = ( i % NumElts ) + NumElts ; Value * Zero = Constant :: getNullValue ( Op0 -> getType ( ) ) ; Op0 = Builder . CreateShuffleVector ( Op0 , Zero , ConcatMask ) ; Op1 = Builder . CreateShuffleVector ( Op1 , Zero , ConcatMask ) ; NumElts = <NUM_LIT> ; } auto * I32Ty = FixedVectorType :: get ( Builder . getInt32Ty ( ) , IntrinsicNumElts / <NUM_LIT> ) ; assert ( NumElts % IntrinsicNumElts == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSplits = NumElts / IntrinsicNumElts ; SmallVector < Value * , <NUM_LIT> > Ops ( NumSplits ) ; for ( unsigned i = <NUM_LIT> ; i != NumSplits ; ++ i ) { SmallVector < int , <NUM_LIT> > ExtractMask ( IntrinsicNumElts ) ; std :: iota ( ExtractMask . begin ( ) , ExtractMask . end ( ) , i * IntrinsicNumElts ) ; Value * ExtractOp0 = Builder . CreateShuffleVector ( Op0 , Op0 , ExtractMask ) ; Value * ExtractOp1 = Builder . CreateShuffleVector ( Op1 , Op0 , ExtractMask ) ; Ops [ i ] = Builder . CreateCall ( PSADBWFn , { ExtractOp0 ,


<s> if ( ( GET_CODE ( op ) == ASHIFT || GET_CODE ( op ) == ASHIFTRT || GET_CODE ( op ) == LSHIFTRT || GET_CODE ( op ) == ROTATERT || GET_CODE ( op ) == ROTATE ) && CONST_INT_P ( XEXP ( op , <NUM_LIT> )


<s> MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; const int InitialVectorSize ( <NUM_LIT> ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses


<s> int64_t PrevDisp = DispSizeStack . back ( ) . first ; unsigned PrevSize = DispSizeStack . back ( ) . second ; if ( CurrDisp + CurrSize > PrevDisp + PrevSize ) break ; DispSizeStack . pop_back ( ) ; } DispSizeStack . push_back ( DispSizePair


<s> if ( reg == ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ? pr_live : interrupt_handler ? ( ( regs_ever_live [ reg ] || ( call_really_used_regs [ reg ] && ( ! fixed_regs [ reg ] || reg == MACH_REG || reg == MACL_REG || reg == PIC_OFFSET_TABLE_REGNUM ) && has_call ) || ( TARGET_SHMEDIA && has_call && REGISTER_NATURAL_MODE ( reg ) == SImode && ( GENERAL_REGISTER_P ( reg ) || TARGET_REGISTER_P ( reg ) ) ) ) && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM && reg != RETURN_ADDRESS_POINTER_REGNUM && reg != T_REG && reg != GBR_REG && ( reg != FPSCR_REG || TARGET_FPU_ANY ) ) : ( ( TARGET_SHCOMPACT && flag_pic && current_function_args_info . call_cookie && reg == PIC_OFFSET_TABLE_REGNUM ) || ( regs_ever_live [ reg ] && ( ! call_really_used_regs [ reg ] || ( trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY ) ) ) || ( current_function_calls_eh_return && ( reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ) ) || ( ( reg == MACL_REG || reg == MACH_REG ) && regs_ever_live [ reg ] && sh_cfun_attr_renesas_p ( ) ) ) ) { SET_HARD_REG_BIT ( * live_regs_mask , reg ) ; count += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ) ) ; if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5 ) && TARGET_FMOVD && GET_MODE_CLASS ( REGISTER_NATURAL_MODE ( reg ) ) == MODE_FLOAT ) { if ( FP_REGISTER_P ( reg ) ) { if ( ! TARGET_FPU_SINGLE && ! regs_ever_live [ reg ^ <NUM_LIT> ] ) { SET_HARD_REG_BIT ( * live_regs_mask , ( reg ^ <NUM_LIT> ) ) ; count += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ^


<s> return false ; case ELF :: R_<ISA_LIT>_REL24 : unsigned Other = cast < MCSymbolELF > ( Sym ) . getOther ( ) << <NUM_LIT> ; return ( Other & ELF :: STO_<ISA_LIT>64_LOCAL_MASK )


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII , this ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> )

== <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , <STR_LIT> ) ; return true ; } } Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> getJumpTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr =


<s> MachineLocation FPSrc ( FramePtr ) ; Moves . push_back ( MachineMove ( FrameLabelId , FPDst , FPSrc ) ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , FramePtr ) . addReg ( StackPtr ) ; if ( needsFrameMoves ) { unsigned FrameLabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( FrameLabelId ) ; MachineLocation FPDst ( FramePtr ) ; MachineLocation FPSrc ( MachineLocation :: VirtualFP ) ; Moves . push_back ( MachineMove ( FrameLabelId , FPDst , FPSrc ) ) ; } for ( MachineFunction :: iterator I = next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( FramePtr ) ; if ( needsStackRealignment ( MF ) ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - MaxAlign ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } else { NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; } bool PushedRegs = false ; int StackOffset = <NUM_LIT> * stackGrowth ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { PushedRegs = true ; ++ MBBI ; if ( ! HasFP && needsFrameMoves ) { unsigned LabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( LabelId ) ; unsigned Ptr = StackSize ? MachineLocation :: VirtualFP : StackPtr ; MachineLocation SPDst ( Ptr ) ; MachineLocation SPSrc ( Ptr , StackOffset ) ; Moves . push_back ( MachineMove ( LabelId , SPDst , SPSrc ) ) ; StackOffset += stackGrowth ; } } if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes >= <NUM_LIT> && Subtarget -> isTargetCygMing ( ) ) { bool isEAXAlive = false ; for ( MachineRegisterInfo :: livein_iterator II = MF . getRegInfo ( ) . livein_begin ( ) , EE = MF . getRegInfo ( ) . livein_end ( ) ; ( II != EE ) && ! isEAXAlive ; ++ II ) { unsigned Reg = II -> first ; isEAXAlive = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; } if ( ! isEAXAlive ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get (

<STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ;


<s> if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return