<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ( <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ( <STR_LIT> , Size ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_BITCAST : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ( true , true , Size ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ( false , false , Size ) , <NUM_LIT> ) ; InstructionMapping GPRToFPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , <STR_LIT> ( false , true , Size ) , <NUM_LIT> ) ; InstructionMapping FPRToGPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , <STR_LIT> ( true , false , Size ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( GPRToFPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRToGPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_LOAD : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) } ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) } ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings


<s> } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; bool UseOpcodeThatLoads = Indirect && ! STI . isThumb ( ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . MOV_ga_pcrel ) : ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . LDRLIT_ga_pcrel ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) { if ( ! UseOpcodeThatLoads ) { auto ResultReg = MIB . getReg ( <NUM_LIT> ) ; auto AddressReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( AddressReg ) ; auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto MIBLoad = BuildMI ( MBB , InsertBefore , MIB -> getDebugLoc ( ) , TII . get ( Opcodes . LOAD32 ) ) . addDef ( ResultReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; addGOTMemOperand ( MIBLoad ) ; if ( ! constrainSelectedInstRegOperands ( * MIBLoad , TII , TRI , RBI ) ) return false ; } else { addGOTMemOperand ( MIB ) ; } } return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? Opcodes . MOV_ga_pcrel : Opcodes . LDRLIT_ga_pcrel ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if (


<s> static const char * sh_check_pch_target_flags ( int old_flags ) { if ( ( old_flags ^ target_flags ) & ( MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH4 ) ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_HITACHI ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_LITTLE_ENDIAN ) return _ (


<s> RegisterAsmLexer < ThumbAsmLexer > Y ( TheThumbTarget )


<s> char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_REG (


<s> bool IsF8Reg ( unsigned Reg , MachineRegisterInfo & MRI ) { return IsRegInClass ( Reg , &


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } Register ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ; bool ValKill = hasTrivialKill (


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * Subtarget . getRegisterInfo ( ) ; LivePhysRegs LiveRegs ( TRI ) ; LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; const MachineRegisterInfo & MRI =


<s> static void arm_asm_emit_except_personality ( rtx personality ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n'


<s> void DecodePSWAPMask ( MVT VT , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumHalfElts = NumElts


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const


<s> const char * pa_output_indirect_call ( rtx_insn * insn , rtx call_dest ) { rtx xoperands [ <NUM_LIT> ] ; if ( TARGET_64BIT ) { xoperands [ <NUM_LIT> ] = call_dest ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; return <STR_LIT> ; } if ( TARGET_FAST_INDIRECT_CALLS ) return <STR_LIT> ; if ( pa_attr_length_indirect_call ( insn ) == <NUM_LIT> ) { if ( TARGET_PA_20 && ! TARGET_SOM ) return <STR_LIT> ; else return <STR_LIT> ; } if ( pa_attr_length_indirect_call ( insn ) == <NUM_LIT> ) return <STR_LIT> ; if ( pa_attr_length_indirect_call ( insn ) == <NUM_LIT> ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = NULL_RTX ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrMSA ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT> ) ; return false


<s> if ( mips_expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) perm2 [ i ] = ( d -> perm [ i ] + nelt ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; if ( mips_expand_vselect_vconcat ( d -> target , d -> op1 , d -> op0 , perm2 , nelt ) ) return true ; } if ( mips_expand_vpc_loongson_even_odd ( d ) ) return true ; if ( mips_expand_vpc_loongson_pshufh ( d ) ) return true ; if ( mips_expand_vpc_loongson_bcast ( d ) ) return true ; if ( mips_expand_msa_shuffle ( d ) ) return true ; return


<s> getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( newval ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addMBB ( loop1MBB ) ; BB -> addSuccessor ( loop1MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB ; MI -> eraseFromParent


<s> Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; NumVecs = <NUM_LIT> ; } for ( unsigned Idx = <NUM_LIT> ; Idx < NumVecs ; ++ Idx ) { unsigned VecNum = Subtarget . isLittleEndian ( ) ? NumVecs - <NUM_LIT> - Idx : Idx ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( VecNum , dl , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Store = DAG . getStore ( StoreChain , dl , Elt , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * <NUM_LIT> ) , commonAlignment ( Alignment , Idx * <NUM_LIT> ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , BasePtr . getValueType ( ) ) ) ; Stores . push_back ( Store ) ; } SDValue TF = DAG . getTokenFactor


<s> if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op )


<s> return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DCI ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ; case


<s> DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( needsStackRealignment ( MF ) ) { if ( CSSize ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; MBBI = prior ( LastCSPop ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust


<s> int LaneIdx = ( Idx / NumEltsPerLane ) * NumEltsPerLane ; int LocalIdx = Idx % NumEltsPerLane ; if ( LocalIdx < HalfEltsPerLane ) { DemandedLHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; DemandedLHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; } else { LocalIdx -= HalfEltsPerLane ; DemandedRHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; DemandedRHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx


<s> case MachineOperand :: MO_GlobalAddress : return lowerSymbolOperand ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_ExternalSymbol : { StringRef Name = MO . getSymbolName ( ) ; return lowerSymbolOperand ( MO , AsmPrinter . GetExternalSymbolSymbol ( Name ) , MO . getOffset ( ) ) ; } case MachineOperand :: MO_JumpTableIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) , <NUM_LIT> ) ; case MachineOperand :: MO_ConstantPoolIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_BlockAddress : { const BlockAddress * BA = MO . getBlockAddress (


<s> bool isUnary = TID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI , TID , MO , OpIdx ) ) ; return ; } if ( MO . isReg (


<s> void RetpolineThunkInserter :: populateThunk ( MachineFunction & MF ) { bool Is64Bit = MF . getTarget ( ) . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; Register ThunkReg ; if ( Is64Bit ) { assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; ThunkReg = <STR_LIT> ; } else { if ( MF . getName ( ) == EAXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == ECXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == EDXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == EDIRetpolineName ) ThunkReg = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; while ( MF . size ( ) > <NUM_LIT> ) MF . erase ( std :: next ( MF . begin ( ) ) ) ; MachineBasicBlock * CaptureSpec = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MachineBasicBlock * CallTarget = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MCSymbol * TargetSym = MF . getContext ( ) . createTempSymbol ( ) ; MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ; const unsigned CallOpc = Is64Bit


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ; if ( ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) ) return


<s> return __builtin_mve_vrev16q_m_sv16qi ( __arm_vuninitializedq_s8 ( )


<s> static void constant_int_to_128bit_vector ( rtx op , machine_mode mode , size_t byte_num , vec_const_128bit_type * info ) { unsigned HOST_WIDE_INT uvalue = UINTVAL ( op ) ; unsigned bitsize = GET_MODE_BITSIZE (


<s> bool hasCapabilitySetAddress ( ) const override { return true


<s> else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I32 : RTLIB :: UDIV_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I64 : RTLIB :: UDIV_I64 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I128 : RTLIB :: UDIV_I128 ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL &&


<s> if ( isSVEMaskOfIdenticalElements < int32_t > ( Imm ) && isSVECpyImm ( Vec . S [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int16_t > ( Imm ) && isSVECpyImm ( Vec . H [ <NUM_LIT> ] )


<s> assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .

hasSVE ( ) || AFI -> hasCalculatedStackSizeSVE ( ) ) && <STR_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO .


<s> if ( ! Is64Bit && SubIdx == <STR_LIT> ) { A = <ISA_LIT>GenRegisterInfo :: getSubClassWithSubReg ( A , <STR_LIT> ) ; if ( ! A


<s> <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame . getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA +=


<s> void addVectorIndex16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( )


<s> if ( sign1 != sign2 ) return MCDisassembler :: Fail ; unsigned Val = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= sign1 << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler


<s> union { uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT>


<s> RegisterTarget < Triple :: ve , false > X ( getThe<ISA_LIT>Target

( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToRegister ( RegMO -> getReg ( ) , false , false , RegMO -> isKill ( ) ) ; if ( ImmMO -> isImm ( ) ) { replaceInstrOperandWithImm ( MI , III . ZeroIsSpecialOrig , Imm ) ; } else { if ( DefMI . getOpcode ( ) == <STR_LIT> ) ImmMO -> setTargetFlags ( <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > MOps ; for ( unsigned i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= III . ZeroIsSpecialOrig ; i -- ) { MOps . push_back ( MI . getOperand ( i ) ) ; MI . RemoveOperand ( i ) ; } MOps . pop_back ( ) ; MI . addOperand ( * ImmMO ) ; for ( auto & MO : MOps ) MI . addOperand ( MO ) ; } MI . setDesc ( get ( III . ImmOpcode ) ) ; LLVM_DEBUG ( dbgs (


<s> const MCExpr * Disp = MCConstantExpr :: create ( ImmDisp , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , ImmDispToken . getEndLoc ( ) , Size ) ; } } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; const MCExpr * Val ; SMLoc End ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( getPointerWidth ( ) , Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>

, Start , End , Size , Identifier , Info ) ;


<s> FixICalls ( MF ) ; FixDCalls ( MF ) ; } else { Changed |= applyCoarseIBT ( MF ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next (


<s> static SDValue lowerV2I64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [


<s> const MCPhysReg * <ISA_LIT>TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [


<s> unsigned Align = DstTy . getSizeInBits ( ) ; const DebugLoc & DbgLoc = I . getDebugLoc ( ) ; unsigned Opc = getLoadStoreOp ( DstTy , RegBank , TargetOpcode :: G_LOAD , Align ) ; const ConstantFP * CFP = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; unsigned CPI = MF . getConstantPool ( ) -> getConstantPoolIndex ( CFP , Align ) ; MachineInstr * LoadInst = nullptr ; unsigned char OpFlag = STI . classifyLocalReference ( nullptr ) ; if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { Register AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Align ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit


<s> Register Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator KillMI = Br . MI ; bool RegKilled = false ; do { -- KillMI ; if ( KillMI -> killsRegister ( Reg , TRI ) ) { KillMI -> clearRegisterKills ( Reg , TRI ) ; RegKilled = true ; break ; } } while ( KillMI != CmpMI ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * CmpMI << <STR_LIT> << * Br . MI ) ; MachineInstr * NewBR = BuildMI ( * MBB , Br . MI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getKillRegState ( RegKilled ) ) . addMBB ( DestBB , Br . MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ; CmpMI -> eraseFromParent ( ) ; Br . MI -> eraseFromParent ( ) ; Br . MI = NewBR ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; BBUtils -> adjustBBOffsetsAfter ( MBB ) ; ++ NumCBZ ; MadeChange =


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base )


<s> if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) Ty = cast < PointerType > ( Ld -> getPointerOperandType ( ) ) -> getElementType ( ) ; const IntegerType * IntTy = dyn_cast < IntegerType > ( Ty ) ; if ( ! IntTy ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return IntTy -> getBitWidth ( ) == <ISA_LIT>CodeGenPrepare ::


<s> return ( int8x16_t ) __builtin_neon_vcntv16qi ( __a )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm16 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op ) . getImm (


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i

!= e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; } AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize


<s> static void vax_option_override ( void ) { if ( TARGET_G_FLOAT ) REAL_MODE_FORMAT (


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue X , Y ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { X = N0 . getOperand ( <NUM_LIT> ) ; Y =


<s> case <STR_LIT> : break ; case <STR_LIT> : if ( ! ST . hasP8Vector ( ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! ST . hasP9Vector ( ) ) return false ; break ; default : return false ; } SDValue LoadedVal ( N , <NUM_LIT> ) ; if ( ! LoadedVal . hasOneUse


<s> arch = strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ; if ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) != <NUM_LIT> && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) goto not_found ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) goto not_found ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) { if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { int i ; for ( i = <NUM_LIT> ; vendors [ i ] . vendor_no != NULL ; i ++ ) if ( strstr ( buf , vendors [ i ] . vendor_no ) != NULL ) { cpu_table = vendors [ i ] . vendor_parts ; break ; } } if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { int i ; if ( cpu_table == NULL ) goto not_found ; for ( i = <NUM_LIT> ; cpu_table [ i ] . part_no != NULL ; i ++ ) if ( strstr ( buf , cpu_table [ i ] . part_no ) != NULL ) { val = arch ? cpu_table [ i ] . arch_name : cpu_table [ i ] . cpu_name ; break ; } break ; } } if ( val ) { fclose ( f ) ; return concat ( <STR_LIT> , argv [ <NUM_LIT> ] , <STR_LIT> , val , NULL ) ; } not_found : { unsigned int i ; unsigned int opt ; const char * search [ ] = { NULL , <STR_LIT> } ; if ( f ) fclose ( f ) ; search [ <NUM_LIT> ] = argv [ <NUM_LIT> ] ; for ( opt = <NUM_LIT> ; opt < ARRAY_SIZE ( search ) ; opt ++ ) for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( configure_default_options ) ; i ++ ) if ( strcmp ( configure_default_options [ i ] . name , search [ opt ] ) == <NUM_LIT> ) return concat ( <STR_LIT> , search [ opt ] , <STR_LIT> , configure_default_options [ i ] . value , NULL ) ; return


<s> SDValue ExtResult = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getSVEContainerType ( ArgVT ) , Op . getOperand ( <NUM_LIT> ) ) ; return getSVESafeBitCast ( OpVT , ExtResult , DAG ) ; } return getSVESafeBitCast ( OpVT , Op . getOperand ( <NUM_LIT> ) , DAG ) ; } if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( ArgVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand


<s> static const uint16_t CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const uint16_t * CURegs = ( Is64Bit ? CU64BitRegs : CU32BitRegs ) ; uint32_t RegEnc = <NUM_LIT> ; for ( int I = CU_NUM_SAVED_REGS - <NUM_LIT> , Idx = <NUM_LIT> ; I != - <NUM_LIT> ; -- I ) { unsigned Reg = SavedRegs [ I ] ; if ( Reg == <NUM_LIT> ) continue ; int CURegNum = getCompactUnwindRegNum ( CURegs


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) .


<s> bool <ISA_LIT>AsmParser :: HandleAVX512Operand ( OperandVector & Operands , const MCParsedAsmOperand & Op ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { const SMLoc consumedToken = consumeToken ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return TokError ( <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return TokError ( <STR_LIT> ) ; Parser . Lex (


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return Subtarget . getJITInfo


<s> if ( REG_P ( src ) && REG_P ( dest ) && reg_overlap_mentioned_p ( dest , src ) && REGNO ( dest ) > REGNO ( src ) ) direction = - <NUM_LIT> ; } else if ( GET_CODE ( mem_operand ) == PRE_DEC || ( GET_CODE ( mem_operand ) == PLUS && GET_CODE ( XEXP ( mem_operand , <NUM_LIT> ) ) == PRE_DEC ) ) direction = - <NUM_LIT> ; else if ( MEM_P ( src ) && reg_overlap_mentioned_p ( dest , src ) ) { int regno ; gcc_assert ( REG_P ( dest ) ) ; regno = REGNO ( dest ) ; gcc_assert ( refers_to_regno_p ( regno , regno + num_words , mem_operand , <NUM_LIT> ) ) ; if ( refers_to_regno_p ( regno , mem_operand ) ) direction = - <NUM_LIT> ; else if ( refers_to_regno_p ( regno + num_words - <NUM_LIT> , regno + num_words , mem_operand , <NUM_LIT> ) ) direction = <NUM_LIT> ; else gcc_unreachable ( ) ; } end = direction < <NUM_LIT> ? - <NUM_LIT> : num_words ; for ( i = direction < <NUM_LIT> ? num_words - <NUM_LIT> : <NUM_LIT> ; i != end ; i += direction ) { rtx w_src , w_dest , insn ; if ( src_modifies ) w_src = gen_rtx_MEM ( word_mode , mem_operand ) ; else w_src = simplify_gen_subreg ( word_mode , src , mode , i * UNITS_PER_WORD ) ; if ( src_volatile ) MEM_VOLATILE_P ( w_src ) = <NUM_LIT> ; if ( dest_modifies ) w_dest = gen_rtx_MEM ( word_mode , mem_operand ) ; else w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; if ( dest_volatile ) MEM_VOLATILE_P ( w_dest ) = <NUM_LIT> ; gcc_assert ( GET_CODE ( w_src ) != SUBREG && GET_CODE ( w_dest ) != SUBREG ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode ,


<s> static DecodeStatus DecodeIT ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mask = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) { pred = <NUM_LIT> ; S = MCDisassembler :: SoftFail ; } if ( mask == <NUM_LIT>


<s> BuildVectorSDNode * Node = dyn_cast < BuildVectorSDNode > ( N . getNode ( ) ) ; if ( Node == NULL ) return false ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize


<s> if ( find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) return


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>BranchSelectionPass ( ) ) ; return false


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT>


<s> static HOST_WIDE_INT loongarch_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , reg_class_names [ from_class ] ,

reg_class_names [ to_class ] , GET_MODE_NAME ( mode ) ) ;


<s> if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> && Subtarget . hasP8Vector ( ) ) return


<s> return ( __m64 ) __builtin_ia32_psrld ( ( __v2si ) __m , ( __v2si )


<s> sbitmap protected_bbs ; rtx_insn * insn , * end ; rtx unprotected_region ; if ( TARGET_MIPS16 ) { sorry ( <STR_LIT> , <STR_LIT> ) ; return ; } calculate_dominance_info ( CDI_DOMINATORS ) ; protected_bbs = sbitmap_alloc ( last_basic_block_for_fn ( cfun ) ) ; bitmap_clear ( protected_bbs ) ; rev_post_order = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n = pre_and_rev_post_order_compute ( NULL , rev_post_order , false ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , rev_post_order [ i ] ) ; if ( r10k_protected_bb_p ( bb , protected_bbs ) ) unprotected_region = NULL_RTX ; else unprotected_region = pc_rtx ; end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( unprotected_region && USEFUL_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_mips_cache ) unprotected_region = NULL_RTX ; else { if ( unprotected_region == pc_rtx ) unprotected_region = insn ; if ( r10k_needs_protection_p ( insn ) ) { emit_insn_before ( gen_r10k_cache_barrier ( ) , as_a < rtx_insn * > ( unprotected_region ) ) ; unprotected_region =


<s> char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest + <NUM_LIT> ) return


<s> BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI . eraseFromParent ( ) ; return


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> unsigned Limit = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! I -> getOperand ( i ) . isFI ( ) ) continue ; const TargetInstrDesc & Desc = TII . get ( I -> getOpcode ( ) ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; if ( AddrMode == <STR_LIT> && hasFP ( MF )


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2siv4hi (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> else crtl -> args . info . call_cookie |= CALL_COOKIE_STACKSEQ ( pushregs ) ; crtl -> args . pretend_args_size += <NUM_LIT> * n_intregs ; } if ( TARGET_SHCOMPACT ) return const0_rtx ; } if ( ! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5 ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( TARGET_SHMEDIA ) n_floatregs = <NUM_LIT> ; bufsize = ( n_intregs * UNITS_PER_WORD ) + ( n_floatregs * UNITS_PER_WORD ) ; if ( TARGET_SHMEDIA ) regbuf = gen_frame_mem ( BLKmode , gen_rtx_REG ( Pmode , ARG_POINTER_REGNUM ) ) ; else if ( n_floatregs & <NUM_LIT> ) { rtx addr ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , XEXP ( regbuf , <NUM_LIT> ) ) ; emit_insn ( gen_iorsi3 ( addr , addr , GEN_INT ( UNITS_PER_WORD ) ) ) ; regbuf = change_address ( regbuf , BLKmode , addr ) ; } else if ( STACK_BOUNDARY < <NUM_LIT> && TARGET_FPU_DOUBLE && n_floatregs ) { rtx addr , mask ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , plus_constant ( Pmode , XEXP ( regbuf , <NUM_LIT> ) , <NUM_LIT> ) ) ; mask = copy_to_mode_reg ( Pmode , GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( addr , addr , mask


<s> for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { const MCInstrDesc & Desc = I -> getDesc ( ) ; emitInstruction ( * I


<s> InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> ; bool HasRs = false ; bool HasRt = false ; if ( Rt == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRt = true ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs =


<s> static inline void desc_rp_br ( unsigned char dst


<s> continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( isO32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Load = DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; InVals . push_back ( Load ) ; OutChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( isN64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg


<s> if ( TargetRegisterInfo :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; for ( ; It != E ;


<s> case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; MachineInstr * NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; Align Alignment ( DAG . getEVTAlign ( Tmp . getValueType ( ) ) ) ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; Alignment = Align ( <NUM_LIT> ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Alignment ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , Alignment ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI =


<s> void <ISA_LIT>TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI ::


<s> const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < <STR_LIT> > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx =


<s> unsigned getAddrMode6DupAddressOpValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> const <ISA_LIT>RegisterInfo & TRI = * static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = <NUM_LIT> * ( Subtarget . isLittle ( ) ? N : ( <NUM_LIT> - N ) ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT>


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> return ( __m256d ) __builtin_ia32_blendmpd_256_mask ( ( __v4df ) __A ,


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , Is64Bit , IsLittleEndian


<s> assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) )


<s> insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; return dest ; case TLS_MODEL_LOCAL_DYNAMIC : insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> ,


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < <NUM_LIT> > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) .


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon =


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindToken , Loc , Loc ) ; Op -> Token . Data = Str . data (


<s> EVT AddrVT = StNode -> getBasePtr ( ) . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , DL , AddrVT , StNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , AddrVT ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , DL , SDValue ( Hi64 , <NUM_LIT> ) , HiPtr , MachinePointerInfo ( ) , Alignment , StNode -> isVolatile ( ) ? MachineMemOperand :: MOVolatile : MachineMemOperand :: MONone ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getDarwinTLSCallPreservedMask ( ) const { return


<s> else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex (


<s> case CmpInst :: Predicate :: BAD_FCMP_PREDICATE : ExtraCost = <NUM_LIT> ; break ; default : break ; } } } static const CostTblEntry SLMCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE41CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE2CostTbl [ ] =


<s> unsigned Class = Desc . getSchedClass ( ) ; int ItinUOps = ItinData -> getNumMicroOps ( Class ) ; if ( ItinUOps >= <NUM_LIT> ) { if ( Subtarget . isSwift ( ) && ( Desc . mayLoad ( ) || Desc . mayStore ( ) ) ) return getNumMicroOpsSwiftLdSt ( ItinData , MI ) ; return ItinUOps ; } unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool cheapPredicableCPSRDef ( ) const { return


<s> InsnType Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm )


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; } Inst . addOperand ( MCOperand :: CreateImm


<s> if ( ( REGNO ( reg ) % <NUM_LIT> ) == <NUM_LIT>

&& mem_min_alignment ( mem , <NUM_LIT> ) ) return <NUM_LIT> ;


<s> const char * name = rs6000_builtin_info [ uns_fncode ] . name ; HOST_WIDE_INT fnmask = rs6000_builtin_info [ uns_fncode ] . mask ; gcc_assert ( name != NULL ) ; if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 )


<s> if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , LHS , ShiftLHS , LHSFromHi ) ) return SDValue ( ) ; SDValue RHS ; uint32_t ShiftRHS = <NUM_LIT> ; bool RHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , RHS , ShiftRHS , RHSFromHi ) ) return SDValue ( ) ; if ( LHSFromHi == RHSFromHi ) return SDValue ( ) ; if ( ShiftLHS + ShiftRHS != VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( LHSFromHi ) { std :: swap ( LHS


<s> if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ) return


<s> for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Gathers . push_back ( II ) ; } } if ( Gathers . empty ( ) ) return false ; for ( IntrinsicInst * I : Gathers ) lowerGather ( I ) ; return true


<s> void getAnalysisUsage ( AnalysisUsage & AU


<s> int AltOpc = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( AltOpc == - <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; SrcOpIdx1 = <NUM_LIT> ; SrcOpIdx2 = <NUM_LIT> ; return true


<s> uint64_t <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { Align TyAlign = DL . getABITypeAlign ( Ty ) ; if ( TyAlign > <NUM_LIT> ) return TyAlign . value ( ) ; return <NUM_LIT> ; } Align Alignment ( <NUM_LIT> ) ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty ,


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified =


<s> bool hasVPCLMULQDQ ( ) const { return HasVPCLMULQDQ


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC ) ) return


<s> MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter (


<s> return ( __m128i ) __builtin_ia32_vpshldv_v2di ( ( __v2di ) __A , ( __v2di ) __B , (


<s> Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op


<s> return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) .

Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> unsigned getSize ( ) const { return CurType .


<s> } if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define )

. addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return std :: any_of ( std :: begin ( GPRArgRegs ) , std :: end ( GPRArgRegs ) , [ this , & MF ] (

MCPhysReg r ) { return isReservedReg ( MF , r ) ; } ) ;


<s> return ( ( DataWidth == <NUM_LIT> || DataWidth == <NUM_LIT> ) && ST -> hasAVX ( ) ) ||

( ( DataWidth == <NUM_LIT> || DataWidth == <NUM_LIT> ) && ST -> hasBWI ( ) ) ;


<s> unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; unsigned Kind = ( unsigned ) Fixup . getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : Type = ELF :: R_MIPS_32 ; break ; case FK_GPRel_4 : Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF


[ tid ] <STR_LIT> ( __rdtime . timeid ) : ) ;


<s> printSysRegOperand ( <STR_LIT> ( ) , MI ,


<s> fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } else { regs_off = <NUM_LIT> + <NUM_LIT> ; fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } this_cfa = ( int ) context -> cfa ; new_cfa = * ( int * ) ( ( context -> cfa ) + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ) ) ; fpu_save = * ( int * ) ( ( this_cfa ) + ( fpu_save_off ) ) ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = <NUM_LIT> ; fs -> cfa_offset = new_cfa - ( int ) context -> cfa ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) continue ; fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = this_cfa + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( i * <NUM_LIT> ) ) - new_cfa ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { fs -> regs . reg [ i + <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i + <NUM_LIT> ] . loc . offset = this_cfa + ( i * <NUM_LIT> ) - new_cfa ; } if ( fpu_save ) { for ( i = <NUM_LIT> ; i < <NUM_LIT>


<s> void <ISA_LIT>InstPrinterCommon :: printOptionalSegReg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getReg ( ) ) { printOperand ( MI , OpNo , O ) ; O <<


<s> return type && TREE_CODE ( TYPE_SIZE ( type )


<s> bool <ISA_LIT>GNULDBackend :: finalizeTargetSymbols ( ) { return


<s> if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget -> hasAVX2 ( ) ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts

. push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;


<s> bool IsLegal = ( C >> <NUM_LIT> == <NUM_LIT> ) || ( ( C & <NUM_LIT> ) == <NUM_LIT> && C >> <NUM_LIT> == <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << C << <STR_LIT> << ( IsLegal


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear


<s> rtx dwarf = NULL_RTX ; rtx tmp , mem ; gcc_assert ( ! ( ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ) ) ; j = <NUM_LIT> ; while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( <NUM_LIT> << j ) ) { if ( ( j % <NUM_LIT> ) == <NUM_LIT> && ( saved_regs_mask & ( <NUM_LIT> << ( j + <NUM_LIT> ) ) ) && ( j + <NUM_LIT> ) != PC_REGNUM ) { if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + <NUM_LIT> ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else if ( j != PC_REGNUM ) { if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else j ++


<s> Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeItem :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue ) ; break ; case AttributeItem :: TextAttribute : Streamer . EmitBytes ( item . StringValue


<s> static bool isPSHUFHWMask ( const SmallVectorImpl < int > & Mask , MVT VT ) { if ( VT != <STR_LIT> ) return false ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] !=


<s> if ( ( flags & OPTION_MASK_PPC_GPOPT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_PPC_GFXOPT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FPRND ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MFPGPR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p


<s> if ( ! MO . isReg ( ) ) continue ; Register OpReg = MO . getReg ( ) ; const RegisterBank * RB = MRI . getRegBankOrNull ( OpReg ) ; if ( RB != DstRB ) { auto * OpDef = MRI . getVRegDef ( OpReg ) ; const LLT & Ty = MRI . getType ( OpReg ) ; MachineBasicBlock & OpDefBB = * OpDef -> getParent ( ) ; MachineBasicBlock :: iterator InsertPt = std :: next ( OpDef -> getIterator ( ) ) ; if ( InsertPt != OpDefBB . end ( ) && InsertPt -> isPHI ( ) ) InsertPt = OpDefBB . getFirstNonPHI ( ) ; MIB . setInsertPt ( * OpDef -> getParent ( ) , InsertPt ) ; auto Copy = MIB . buildCopy ( Ty , OpReg ) ; MRI . setRegBank ( Copy . getReg ( <NUM_LIT> ) , *


<s> unsigned <ISA_LIT>CodeEmitter :: getSizeExtEncoding ( const MachineInstr & MI , unsigned OpNo ) const { return getMachineOpValue ( MI , MI . getOperand ( OpNo ) ) -


<s> bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsELF32_ABI = Subtarget . isELF32_ABI ( ) ; bool IsMachoABI = Subtarget . isMachoABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && IsELF32_ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , IsMachoABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( PerformTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { int AddFPOffsetAmount = IsELF32_ABI ? - <NUM_LIT> : <NUM_LIT> ; MF . getFrameInfo ( ) -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , AddFPOffsetAmount + TCSPDelta ) ; } if ( EnableRegisterScavenging ) if ( needsFP ( MF ) || spillsCR ( MF ) ) { const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = Is<ISA_LIT>64


<s> Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) { SM . serializeToStackMapSection


<s> const __vector unsigned int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned short result ; a = ( __vector unsigned char ) __builtin_pack_vector_int128 ( <NUM_LIT> , __A ) ; b = ( __vector unsigned char ) __builtin_pack_vector_int128 ( <NUM_LIT> , __B ) ; vmin = vec_min ( a , b ) ; vmax = vec_max ( a , b ) ; vabsdiff = vec_sub ( vmax , vmin


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ?


<s> getParser ( ) . getStreamer ( ) . emitDTPRel32Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( )


<s> return SelectShiftedRegister ( N , true ,


<s> BinOpChain ( Instruction * I , ValueList & lhs , ValueList & rhs ) : OpChain ( I , lhs ) , LHS ( lhs ) , RHS


<s> if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; } bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegArg = TLI . getNegatedExpression ( Arg , DAG , LegalOperations , CodeSize ) ) return


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI ,


<s> bool <ISA_LIT>InstructionSelector :: preISelLower ( MachineInstr & I ) { MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : { Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ShiftReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ShiftTy = MRI . getType ( ShiftReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy . isVector ( ) ) return false ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; auto * AmtMI = MRI . getVRegDef ( ShiftReg ) ; assert ( AmtMI && <STR_LIT> ) ; if ( AmtMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { MachineIRBuilder MIB ( I ) ; auto Trunc = MIB . buildInstr ( TargetOpcode :: COPY , { SrcTy } , { } ) . addReg ( ShiftReg , <NUM_LIT> , <STR_LIT> ) ; MRI . setRegBank ( Trunc . getReg ( <NUM_LIT> )


<s> break ; case GE : if ( mep_imm4_operand ( op1 , SImode ) ) break ; tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op0 , op1 ) ) ; code = EQ ; op0 = tmp ; op1 = const0_rtx ; break ; case EQ : case NE : if ( ! mep_reg_or_imm4_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : case GT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) { op1 = GEN_INT ( INTVAL ( op1 ) + <NUM_LIT> ) ; code = ( code == LE ? LT : GE ) ; goto restart ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op1 , op0 ) ) ; code = ( code == LE ? EQ : NE ) ; op0 = tmp ; op1 = const0_rtx ; break ; case LTU : if ( op1 == const1_rtx ) { code =


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSizeExtEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup


<s> function_instance instance ( <STR_LIT> , functions :: svlsl , shapes :: binary_uint_opt_n , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , <NUM_LIT> , amount ) ; return call ; } int element_bits = f . type_suffix (


<s> ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal =


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; const TargetFrameLowering & TFI = * MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIdx = MFI -> CreateFixedObject ( SlotSize , - ( int ) SlotSize + TFI . getOffsetOfLocalArea ( ) + TailCallReturnAddrDelta , true ) ; assert ( FrameIdx == MFI -> getObjectIndexBegin ( ) && <STR_LIT> ) ; ( void )


<s> bool <ISA_LIT>TargetLowering :: isAccessedAsGotIndirect ( SDValue GA ) const { if ( Subtarget . is32BitELFABI ( ) ) return true ; if ( Subtarget . isAIXABI ( ) ) return true ; CodeModel :: Model CModel = getTargetMachine ( )


<s> if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ABI . IsO32 ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) Ret += <STR_LIT> ; Ret +=


<s> return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc ( (


<s> bool nds32_valid_CVhi_p ( rtx op ) { HOST_WIDE_INT ival = const_vector_to_hwint (


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true


<s> if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; }


<s> switch ( MBBI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( )


<s> MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ! CmpTy . isVector ( ) && <STR_LIT> ) ; unsigned Size = CmpTy . getSizeInBits ( ) ; ( void ) Size ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( auto FoldCmp = tryFoldIntegerCompare ( LHS ,

RHS , Predicate , MIRBuilder ) ) return FoldCmp ;


<s> static SDValue LowerCTLZ ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; if ( VT . isVector ( ) && Subtarget -> hasAVX512 ( ) ) return LowerVectorCTLZ_AVX512 ( Op , DAG ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT>


<s> return ( vector unsigned short ) __builtin_altivec_vsrh ( ( vector signed short ) a1 , ( vector signed


<s> __inline__ static unsigned long long sh_media_MMULFX_W ( unsigned long


<s> RegionFragment * getExIdxFragment ( ) const { return m_pExIdxFragment


<s> return ( __m512i ) __builtin_ia32_pmovzxwq512_mask ( ( __v8hi ) __A , ( __v8di )

_mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( is64Bit ( ) ) { ArrayRef < MCPhysReg > ArgGPRs = get64BitArgumentGPRs ( CallConv , Subtarget ) ; ArrayRef < MCPhysReg > ArgXMMs = get64BitArgumentXMMs ( TheMachineFunction , CallConv , Subtarget ) ; unsigned NumIntRegs = CCInfo . getFirstUnallocated ( ArgGPRs ) ; unsigned NumXMMRegs = CCInfo . getFirstUnallocated ( ArgXMMs ) ; assert ( ! ( NumXMMRegs && ! Subtarget . hasSSE1 ( ) ) && <STR_LIT> ) ; if ( isWin64 ( ) ) { int HomeOffset = FrameLowering . getOffsetOfLocalArea ( ) + <NUM_LIT> ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , NumIntRegs * <NUM_LIT> + HomeOffset , false ) ) ; if ( NumIntRegs < <NUM_LIT> ) FuncInfo -> setVarArgsFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) ) ; } else { FuncInfo -> setVarArgsGPOffset ( NumIntRegs * <NUM_LIT> ) ; FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms


<s> bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange


<s> bool <ISA_LIT>TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , ElementCount NumElements ) const { return ST -> hasSSE3 ( ) && ! NumElements . isScalable ( ) && NumElements . getFixedValue ( ) == <NUM_LIT> &&

ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerThreadPointer ( const SDLoc & DL , SelectionDAG & DAG ) const { SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TPHi = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT ,


<s> MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else


<s> } if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; MVT MulVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( Subtarget . hasSSE41 ( ) && DAG . ComputeNumSignBits ( A ) > <NUM_LIT> && DAG . ComputeNumSignBits ( B ) > <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getBitcast ( MulVT , A ) , DAG . getBitcast ( MulVT , B ) ) ; } APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = DAG . MaskedValueIsZero ( A , LowerBitsMask ) ; bool BLoIsZero = DAG . MaskedValueIsZero ( B , LowerBitsMask ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = DAG . MaskedValueIsZero ( A , UpperBitsMask ) ; bool BHiIsZero = DAG . MaskedValueIsZero ( B , UpperBitsMask ) ; SDValue Alo = DAG . getBitcast ( MulVT , A ) ; SDValue Blo = DAG . getBitcast ( MulVT , B ) ; SDValue Zero = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , Alo , Blo ) ; SDValue AloBhi = Zero ; if ( ! ALoIsZero && ! BHiIsZero ) { SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; Bhi = DAG . getBitcast ( MulVT , Bhi ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , Alo , Bhi ) ; } SDValue AhiBlo = Zero ; if ( ! AHiIsZero && ! BLoIsZero ) { SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; Ahi = DAG . getBitcast ( MulVT


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = LHS . getValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { if ( ! hasHardQuad && LHS . getValueType (


<s> return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg )

|| <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ;


<s> rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( <NUM_LIT> + ( regno - <NUM_LIT> ) ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode ,


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int , unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > <NUM_LIT> && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > <NUM_LIT>

&& ! FLOAT128_2REG_P ( mode ) ) return true ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( XRegs [ getReg (


<s> return ( __m64 ) __builtin_ia32_punpckhwd ( ( __v4hi ) __m1 , (


<s> case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs =


<s> offset < VECTOR_128BIT_BYTES ; offset += size ) memcpy ( ( void * ) & info -> bytes [ offset ] , ( void * ) & info -> bytes [ <NUM_LIT> ] , size ) ; } info -> original_size = size ; unsigned char first_byte = info -> bytes [ <NUM_LIT> ] ; info -> all_bytes_same = true ; for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_BYTES ; i ++ ) if ( first_byte != info -> bytes [ i ] ) { info -> all_bytes_same = false ; break ; } for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_HALF_WORDS ; i ++ ) info -> half_words [ i ] = ( ( info -> bytes [ i * <NUM_LIT> ] << <NUM_LIT> ) | info -> bytes [ ( i * <NUM_LIT> ) + <NUM_LIT> ] ) ; unsigned short first_hword = info -> half_words [ <NUM_LIT> ] ; info -> all_half_words_same = true ; for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_HALF_WORDS ; i ++ ) if ( first_hword != info -> half_words [ i ] ) { info -> all_half_words_same = false ; break ; } for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_WORDS ; i ++ ) info -> words [ i ] = ( ( info -> bytes [ i * <NUM_LIT> ] << <NUM_LIT> ) | ( info -> bytes [ ( i * <NUM_LIT> ) + <NUM_LIT> ] << <NUM_LIT> ) | ( info -> bytes [ ( i * <NUM_LIT> ) + <NUM_LIT> ] << <NUM_LIT> ) | info -> bytes [ ( i * <NUM_LIT> ) + <NUM_LIT> ] ) ; info -> all_words_same = ( info -> words [ <NUM_LIT> ] == info -> words [ <NUM_LIT> ] && info -> words [ <NUM_LIT> ] == info -> words [ <NUM_LIT> ] && info -> words [ <NUM_LIT> ] == info -> words [ <NUM_LIT> ] && info -> words [ <NUM_LIT> ] == info -> words [ <NUM_LIT> ] ) ; for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_DOUBLE_WORDS ; i ++ ) { unsigned HOST_WIDE_INT d_word = <NUM_LIT> ; for ( size_t j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) d_word = ( d_word << <NUM_LIT> ) | info -> bytes


<s> uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , Bytes ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return MCDisassembler


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; HasE1 = false ; HasE2 = false


<s> static unsigned PromoteRegTo64 ( unsigned RegIn ) { if ( RegIn == <NUM_LIT> ) return <NUM_LIT> ; unsigned RegOut = get<ISA_LIT>SubSuperRegister ( RegIn , <STR_LIT> , false ) ; assert ( RegOut != <NUM_LIT> ) ; return