<s> memset ( sc -> rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; sc -> first_instruction = <NUM_LIT> ; sc -> pending_data_specs = <NUM_LIT> ; sc -> current_cycle = <NUM_LIT> ; memset ( sc -> mem_ops_in_group , <NUM_LIT> , sizeof ( mem_ops_in_group ) ) ; } else { memcpy ( sc -> prev_cycle_state , prev_cycle_state , dfa_state_size ) ; sc -> last_scheduled_insn = last_scheduled_insn ; memcpy ( sc -> rws_sum , rws_sum , sizeof ( rws_sum ) ) ; memcpy ( sc -> rws_insn , rws_insn , sizeof ( rws_insn ) ) ; sc -> first_instruction = first_instruction ; sc -> pending_data_specs =


<s> static const unsigned StoreRels [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * LoadOps , * StoreOps ; if ( Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ) LoadOps = LoadAcqs ; else LoadOps = LoadBares ; if ( Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ) StoreOps = StoreRels ; else StoreOps = StoreBares


<s> uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc ) ; EVT VT = N -> getValueType (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool hasSymbolicDisplacement ( ) const { return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; return LowerGlobalAddress ( GV , Op . getDebugLoc ( ) , Offset


<s> if ( ! Store -> isSimple ( ) ) return SDValue ( ) ; EVT StoreVT = StoredVal . getValueType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned HalfSize = StoredVal . getValueSizeInBits ( ) / <NUM_LIT> ; unsigned HalfAlign = ( <NUM_LIT> == HalfSize ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Store ) ; SDValue Value0 = extractSubVector ( StoredVal , <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Value1 = extractSubVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset

( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> NTOperator = is64BitFP ? <STR_LIT> : <STR_LIT> ; unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue OnesOrZeroesF = DAG . getNode ( NTOperator , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , <STR_LIT> ) ) ; SDValue OnesOrZeroesI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT>


<s> } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , isMachoABI ) ) ; if ( CC == CallingConv :: Fast && PerformTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask )


<s> Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ) ) ; } else


<s> void addMEMriOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst , Expr )


<s> bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; return


<s> assert ( KnownUndef . getBitWidth ( ) == NumElts && KnownZero . getBitWidth ( ) == NumElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( KnownUndef [ i ] ) Mask [ i ] = SM_SentinelUndef ; else if ( KnownZero [ i ] ) Mask [ i ] =


<s> } if ( TARGET_VFP ) return ( TARGET_BIG_END ? <NUM_LIT>


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII

-> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ;


<s> unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) Opc = HasAVX512 ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg


<s> errs ( ) << <STR_LIT> << this << '\n' ; if ( BaseType == RegBase && Base . Reg . getNode ( ) != <NUM_LIT> ) { errs ( ) << <STR_LIT> ; Base . Reg . getNode ( ) -> dump ( ) ; } else if ( BaseType == FrameIndexBase ) { errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } errs ( ) << <STR_LIT> << Disp << '\n' ; if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ; } else if (


<s> SDValue B ; if ( ExtOpcode == <STR_LIT> ) { A = Op0 . getOperand ( <NUM_LIT> ) ; B = Op0 . getOperand ( <NUM_LIT> ) ; if ( A . getOpcode ( ) != B . getOpcode ( ) || A . getOperand ( <NUM_LIT> ) . getValueType ( ) != B . getOperand ( <NUM_LIT> ) . getValueType ( ) ) return SDValue ( ) ; ExtOpcode = A . getOpcode ( ) ; } if ( ExtOpcode != <STR_LIT> && ExtOpcode != <STR_LIT> ) return SDValue ( ) ; EVT Op0VT = A . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Op0VT != <STR_LIT> && Op0VT !=


<s> return ( __m128i ) __builtin_ia32_gathersiv2di ( ( __v2di ) src , base , (

__v4si ) index , ( __v2di ) mask , scale ) ;


<s>
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_InvalidImmUnsignedi4
:
{
SMLoc
ErrorLoc
=
(
(
<ISA_LIT>Operand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
return
Error
(
ErrorLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
}
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
MissingFeatures
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
case
Match_MnemonicFail
:
case
Match_Unsupported
:
break
;
}
if
(
Op
.
getToken
(
)
.
empty
(
)
)
{
Error
(
IDLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
return
true
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
const
char
*
MemSize
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
FeatureBitset
ErrorInfoMissingFeatures
;
unsigned
Match
[
<NUM_LIT>
]
;
bool
HasVectorReg
=
false
;
<ISA_LIT>Operand
*
MemOp
=
nullptr
;
for
(
const
auto
&
Op
:
Operands
)
{
<ISA_LIT>Operand
*
<ISA_LIT>Op
=
static_cast
<
<ISA_LIT>Operand
*
>
(
Op
.
get
(
)
)
;
if
(
<ISA_LIT>Op
->
isVectorReg
(
)
)
HasVectorReg
=
true
;
else
if
(
<ISA_LIT>Op
->
isMem
(
)
)
{
MemOp
=
<ISA_LIT>Op
;
assert
(
MemOp
->
Mem
.
Size
==
<NUM_LIT>
&&
<STR_LIT>
)
;
break
;
}
}
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
if
(
MemOp
&&
HasVectorReg
)
MemOp
->
Mem
.
Size
=
MemSize
[
I
]
;
Match
[
I
]
=
Match_MnemonicFail
;
if
(
MemOp
||
!
HasVectorReg
)
{
Match
[
I
]
=
MatchInstruction
(
Operands
,
Inst
,
ErrorInfoIgnore
,
MissingFeatures
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
if
(
Match
[
I
]
==
Match_MissingFeature
)
ErrorInfoMissingFeatures
=
MissingFeatures
;
}
}
Op
.
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
std
::
count
(
std
::
begin
(
Match
)
,
std
::
end
(
Match
)
,
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
if
(
!
MatchingInlineAsm
&&
validateInstruction
(
Inst
,
Operands
)
)


<s> case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( ! Size ) llvm_unreachable (


<s> int <ISA_LIT>RegisterInfo :: getSEHRegNum (


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! hasHardQuad ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: SINTTOFP_I32_F128 ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType


<s> auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; bool Auth = OF . Candidates . front ( ) . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ; saveLROnStack ( MBB , It , true , Auth ) ; assert ( OF . FrameConstructionID !=


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 ,


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T


<s> else if ( First <= <NUM_LIT> ) emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_SaveFRegD0D15 , First , Last ) ; else emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_SaveFRegD16D31 ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16SP ( SDValue Addr , SDValue & Base , SDValue & Offset ) { llvm_unreachable (


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg (


<s> Fragment * <ISA_LIT>64GOT :: createEntry ( uint64_t pValue


<s> static MCOperand LowerSymbolOperand ( const MachineInstr * MI , const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter & AP ) { <ISA_LIT>MCExpr :: VariantKind Kind = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , AP . OutContext ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , AP . OutContext ) , AP . OutContext ) ; Expr = <ISA_LIT>MCExpr :: create ( Kind , Expr , AP . OutContext ) ; return MCOperand :: createExpr (


<s> break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C ->


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; SDValue Glue = emitCmp ( DAG , DL , C ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( C . CCValid , DL , <STR_LIT> )

, DAG . getConstant ( C . CCMask , DL , <STR_LIT> ) , Dest , Glue ) ;


<s> unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT>


<s> assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; if ( ! isLegalInterleavedAccessType ( Factor , VecTy , DL ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI


<s> return ChooseMask ( PredBlockMask :: TTT , PredBlockMask :: TTE ) ; case PredBlockMask :: TE : return ChooseMask ( PredBlockMask :: TET , PredBlockMask :: TEE ) ; case PredBlockMask :: TTT : return ChooseMask ( PredBlockMask :: TTTT , PredBlockMask :: TTTE ) ; case PredBlockMask :: TTE : return ChooseMask ( PredBlockMask :: TTET , PredBlockMask :: TTEE ) ; case PredBlockMask :: TET : return ChooseMask ( PredBlockMask :: TETT , PredBlockMask :: TETE ) ; case PredBlockMask :: TEE : return ChooseMask ( PredBlockMask :: TEET , PredBlockMask :: TEEE ) ; default : llvm_unreachable (


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( ShAmtOp ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , DL , VT , ValOp ,


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>_64Disassembler ( STI


<s> bool isTargetNaCl ( ) const { return TargetTriple . getOS ( ) ==


<s> machine_mode mode , orig_mode ; orig_mode = TYPE_MODE ( valtype ) ; mode = type_natural_mode ( valtype , NULL , true ) ; return ix86_function_value_1 ( valtype , fntype_or_decl ,


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; return TargetLowering :: getInlineAsmMemConstraint (


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc


<s> MVT VT = V . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > NewVecC ; SDLoc DL ( V ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { auto * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ; const APInt & EltC = Elt


<s> last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( )


<s> break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Align ( Size ) ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear


<s> void DecodePUNPCKLBWMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts ) , ShuffleMask


<s> Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ; return MCDisassembler ::


<s> SDValue Conv = convertFPToInt ( Op , DAG , Subtarget ) ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( CondCode ) ) ; return MCDisassembler ::


<s> int64_t <ISA_LIT>FrameLowering :: assignSVEStackObjectOffsets ( MachineFrameInfo & MFI , int & MinCSFrameIndex


<s> uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT>

] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> if ( TARGET_SHMEDIA ) return false ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT>


<s> result = ( __vector __m64 ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char ) perm_mask ) ; return result [ <NUM_LIT>


<s> continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , & SVOps [ <NUM_LIT> ] , SVOps . size ( ) ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) : Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] %


<s> if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg


<s> if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpDWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDataDirective ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; if ( IDVal == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) .


<s> unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ; } return false


<s> if ( Parser . ParseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } } return true


<s> static DecodeStatus DecodeThumbBROperand ( MCInst & Inst , unsigned Val , uint64_t Address


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind , const MCExpr *


<s> const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg


<s> case CallingConv :: WebKit_JS : return CC_<ISA_LIT>_WebKit_JS ; case CallingConv :: GHC : return CC_<ISA_LIT>_GHC ; case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: PreserveMost : case CallingConv :: CXX_FAST_TLS : case CallingConv :: Swift : if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; return IsVarArg ? CC_<ISA_LIT>_DarwinPCS_VarArg :


<s> static DecodeStatus DecodeDSPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler *


<s> break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget . hasInt256 ( ) ) return SDValue ( ) ; SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> ) { V = DAG . getBitcast ( <STR_LIT> , V ) ; V = DAG . getVectorShuffle ( <STR_LIT> , DL , V , DAG . getUNDEF ( <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) ,

static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ;


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG .

getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>AsmParser :: searchSymbolAlias ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , unsigned RegKind ) { MCSymbol * Sym = getContext ( ) . LookupSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; if ( Sym ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * Expr ; if ( Sym -> isVariable ( ) ) Expr = Sym -> getVariableValue ( ) ; else return false ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { <STR_LIT> Kind = ( <STR_LIT> ) RegKind ; const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { int RegNum = - <NUM_LIT> ; APInt IntVal ( <NUM_LIT> , - <NUM_LIT> ) ; if ( ! DefSymbol . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) RegNum = matchRegisterByNumber ( IntVal . getZExtValue ( ) , is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; else { switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : default : RegNum = matchCPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; } if ( RegNum > - <NUM_LIT> ) RegNum = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; } if ( RegNum > - <NUM_LIT> ) { Parser . Lex ( ) ; <ISA_LIT>Operand * op = <STR_LIT> ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( Kind ) ; Operands . push_back ( op ) ; return true ; } } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) { Parser . Lex ( ) ; const MCConstantExpr * Const = static_cast < const MCConstantExpr * > ( Expr ) ; <ISA_LIT>Operand * op = <STR_LIT> ( Const , S , Parser . getTok ( ) . getLoc (


<s> } } case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) { ValueList LHS ; ValueList RHS ; if ( IsNarrowSequence < <NUM_LIT> > ( MulOp0 , LHS ) && IsNarrowSequence < <NUM_LIT> > ( MulOp1 , RHS ) ) { R . InsertMul ( I , LHS , RHS ) ; return true ; } } return false ; } case Instruction :: SExt : return Search ( I -> getOperand ( <NUM_LIT> ) , BB , R ) ; } return false ; } ; bool Changed = false ; for ( auto & BB : F ) { SmallPtrSet < Instruction * , <NUM_LIT> > AllAdds ; if ( ! RecordMemoryOps ( & BB ) ) continue ; for ( Instruction & I : reverse ( BB ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , & BB , R ) ) continue ; if ( ! CreateParallelPairs ( R ) ) continue ; InsertParallelMACs ( R ) ; Changed = true ; AllAdds . insert ( R . getAdds ( ) . begin ( ) , R . getAdds ( ) . end ( ) ) ; } } return


<s> if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Value = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; Value -= Offset ; return


<s> getSubExpr ( ) -> print ( OS ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HA : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHERA : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : OS <<


<s> static const uint16_t HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , ShadowRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) { Reg = State . AllocateReg ( GPRArgRegs , <NUM_LIT> ) ; assert ( ( ! Reg || Reg == <STR_LIT> ) && <STR_LIT> ) ; if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned


<s> } Ops . push_back ( IsAndN ? N1 : N0 ) ; return true ; } case <STR_LIT> : { SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT || ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) || NumElts <= N0 . getConstantOperandVal ( <NUM_LIT> ) || ! N -> isOnlyUserOf ( N0 . getNode ( ) ) ) return false ; Ops . push_back ( N0 . getOperand ( <NUM_LIT> ) ) ; Mask . push_back ( N0 . getConstantOperandVal ( <NUM_LIT> ) ) ; Mask . append ( NumElts - <NUM_LIT> , SM_SentinelUndef ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { SDValue InVec = N . getOperand ( <NUM_LIT> ) ; SDValue InScl = N . getOperand ( <NUM_LIT> ) ; uint64_t InIdx = N . getConstantOperandVal ( <NUM_LIT> ) ; assert ( InIdx < NumElts && <STR_LIT> ) ; if ( <STR_LIT> ( InScl ) ) { Ops . push_back ( InVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Mask . push_back ( i == InIdx ? SM_SentinelZero : ( int ) i ) ; return true ; } unsigned ExOp = ( <STR_LIT> == Opcode ? <STR_LIT> : <STR_LIT> ) ; if ( InScl . getOpcode ( ) != <STR_LIT> || InScl . getOperand ( <NUM_LIT> ) . getOpcode ( ) != ExOp ) return false ; SDValue ExVec = InScl . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; uint64_t ExIdx = InScl . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; assert ( ExIdx < NumElts && <STR_LIT> ) ; Ops . push_back ( InVec ) ; Ops . push_back ( ExVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Mask . push_back ( i == InIdx ? NumElts + ExIdx : i ) ; return


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const


<s> if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && Constants [ i ] . getAlign ( ) >= Alignment ) { auto * CPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( Constants [ i ] . Val . MachineCPVal ) ; if ( Derived * APC = dyn_cast < Derived > ( CPV ) ) if ( cast < Derived > ( this ) -> equals ( APC ) ) return i ; } } return - <NUM_LIT>


<s> ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type )

( unsigned_intTI_type_node , <STR_LIT> ) ;


<s> case k_CCOut : case k_Register : Reg = o . Reg ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : Registers = o . Registers ; break ; case k_VectorList : case k_VectorListAllLanes : case k_VectorListIndexed : VectorList = o . VectorList ; break ; case k_CoprocNum : case k_CoprocReg : Cop = o . Cop ; break ; case k_CoprocOption : CoprocOption = o . CoprocOption ; break ; case k_Immediate : Imm = o . Imm ; break ; case k_MemBarrierOpt : MBOpt = o . MBOpt ; break ; case k_InstSyncBarrierOpt : ISBOpt = o . ISBOpt ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask : MMask = o . MMask ; break ; case k_BankedReg : BankedReg = o . BankedReg ; break ; case k_ProcIFlags : IFlags = o . IFlags ; break ; case k_ShifterImmediate : ShifterImm = o . ShifterImm ; break ; case k_ShiftedRegister : RegShiftedReg = o


<s> return __builtin_arm_mrrc2 ( __coproc ,


<s> bool <ISA_LIT>TargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypePaddedSize (


<s> static __inline qword si_or ( qword a , qword b ) { return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) (


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16 ( SDNode * Parent , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Alias ) { llvm_unreachable ( <STR_LIT>


<s> } else if ( B == & <STR_LIT> || B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return


<s> __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ; return __ev_mwsmian ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> } )


<s> return addLeaOffset ( MIB , Offset ) . addReg (


<s> static inline bool setBranchProb ( MachineBasicBlock * MBB , MachineBasicBlock * SuccMBB , BranchProbability Prob ) { auto MBBI = std :: find ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) , SuccMBB ) ; if ( MBBI == MBB -> succ_end ( ) ) return false ; MBB -> setSuccProbability ( MBBI , Prob


<s> bool NextIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( ! ThisIsNonZero && ! NextIsNonZero ) continue ; SDValue Elt ; if ( ThisIsNonZero ) { if ( NumZero || NextIsNonZero ) Elt = DAG . getZExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; else Elt = DAG . getAnyExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; } if ( NextIsNonZero ) { SDValue NextElt = Op . getOperand ( i + <NUM_LIT> ) ; if ( i == <NUM_LIT> && NumZero ) NextElt = DAG . getZExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; else NextElt = DAG . getAnyExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; NextElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( ThisIsNonZero ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , Elt ) ; else Elt = NextElt ; } if ( ! V


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Prefetch , Ctx ) ; Op -> Prefetch . Val = Val ; Op -> Barrier . Data = Str . data ( ) ; Op -> Barrier . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> fpu_name = ( ptr -> x_arm_fpu_index == TARGET_FPU_auto ? <STR_LIT> : all_fpus [ ptr -> x_arm_fpu_index ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags ) ? <STR_LIT> : TARGET_THUMB_P ( flags


<s> static inline <STR_LIT> getMemExtendType ( unsigned Imm ) { return getExtendType ( ( Imm >> <NUM_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> &&


<s> if ( OpSize == <NUM_LIT> ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } else if ( OpSize == <NUM_LIT> ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return <STR_LIT> ; case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT>


<s> static DecodeStatus DecodeShiftRight16Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> if ( ! getTargetShuffleMask ( InVec . getNode ( ) , VT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; if ( HasShuffleIntoBitcast ) { unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = TLI . getDataLayout ( ) -> getABITypeAlignment ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; } SDLoc dl ( N ) ; SDValue Shuffle = ( UnaryShuffle ) ? DAG . getUNDEF ( VT ) : InVec . getOperand ( <NUM_LIT> ) ; Shuffle = DAG . getVectorShuffle ( InVec . getValueType ( ) , dl , InVec . getOperand ( <NUM_LIT> ) , Shuffle , & ShuffleMask [ <NUM_LIT> ] ) ; Shuffle = DAG . getNode ( <STR_LIT> , dl , VT , Shuffle


<s> if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ; return false


<s> switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , MaybeAlign ( Alignment ) , AddressSpace ) ; Cost += Factor * ( LT . first - <NUM_LIT> ) ; return Cost


<s> bool <ISA_LIT>PassConfig :: addIRTranslator


<s> } return StringSwitch < <ISA_LIT>ABIInfo > ( CPU ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case

( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Default ( <ISA_LIT>ABIInfo :: Unknown ( ) ) ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup


<s> vst2_u32 ( uint32_t * __a , uint32x2x2_t val ) { __builtin_aarch64_simd_oi __o ; uint32x4x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ]


<s> unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : return VTBits ; case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case <STR_LIT> : { unsigned SrcBits = Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ; unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Tmp = std :: min ( Tmp0 ,


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { if ( AFI -> isThumbFunction ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; if ( Subtarget -> isTargetDarwin ( ) ) O << '\t' << *


<s> sgx_call_magic_labels_index ++ ; return <STR_LIT> + std :: to_string ( sgx_call_magic_labels_index -


<s> if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc (


<s> case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG : return true ; default : break ; } return false


<s> Type * ValTy = cast < PointerType > ( AlignedAddr -> getType ( ) ) -> getElementType ( ) ; assert ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) ; Function * IntCmpXchg = <STR_LIT> ( M , <STR_LIT> ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , <STR_LIT> ) ; Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , <STR_LIT> ) ; Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext


<s> for ( reg = * regp ; reg <= lim ; ++ reg ) { if ( reg ->


<s> bool isNotTargetNaCl ( ) const { return ! TargetTriple .


<s> if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps (


<s> if ( opts -> x_flag_align_labels && ! opts -> x_str_align_labels ) opts -> x_str_align_labels = processor_cost_table [ ix86_tune ] -> align_label ; if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = processor_cost_table [ ix86_tune


<s> int flags = ptr -> x_target_flags ; const struct arm_fpu_desc * fpu_desc = & all_fpus [ ptr -> x_arm_fpu_index ] ; fprintf ( file , <STR_LIT> , indent , <STR_LIT>

, TARGET_THUMB2_P ( flags ) ? <STR_LIT> :


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ,


<s> const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledValue ( ) ; if ( isa < InlineAsm > ( Callee )


<s> } if ( IsBigEndian ) { Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } else { Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT>


<s> return ( uint16x4_t ) __builtin_neon_vcvtu_nv4hf


<s> if ( IntImm . getActiveBits ( ) > <NUM_LIT> ) return false ; bool Success = TII -> isRxSBGMask ( IntImm . getZExtValue ( ) , BitWidth , Start , End ) ; if ( ! Success ) return false ; Start -= <NUM_LIT> - BitWidth ; End -= <NUM_LIT> -


<s> } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection )


<s> case Instruction :: SIToFP : return SelectSIToFP ( I ) ; case Instruction :: FPToSI : return SelectFPToSI ( I ) ; case Instruction :: FAdd : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: SDiv : return SelectSDiv ( I ) ; case Instruction :: SRem : return SelectSRem ( I ) ; case Instruction :: Call : if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) return SelectIntrinsicCall ( * II ) ; return SelectCall ( I ) ; case Instruction :: Select : return SelectSelect ( I ) ; case Instruction ::


<s> static MCStreamer * createMachOStreamer ( MCContext & Ctx , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter

, bool RelaxAll , bool DWARFMustBeAtTheEnd ) {


<s> assert ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Legalized ) && <STR_LIT> ) ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis >


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 )

|| TT . isPS4 ( ) ) this -> Options . TrapUnreachable = true ;


<s> bool isNEONi16splatNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue


<s> return false ; } if ( ! ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( opval , VOIDmode ) ) { error ( <STR_LIT> , name ) ; return


<s> bool <ISA_LIT>ReduceCRLogicals :: handleCROp ( unsigned Idx ) { bool Changed = false ; CRLogicalOpInfo CRI = AllCRLogicalOps [ Idx ] ; if ( CRI . IsBinary && CRI . ContainedInBlock && CRI . SingleUse && CRI . FeedsBR &&


<s> ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( )


<s> if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( type == vector_pair_type_node ) return <STR_LIT> ; if ( type == vector_quad_type_node )


<s> if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT>


<s> if ( TOCEntry == <NUM_LIT> ) TOCEntry = OutContext . GetOrCreateTemporarySymbol ( StringRef ( MAI -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( LabelID ++ ) ) ; O << * TOCEntry


<s> MachineInstr * MI = & * MBBI ; <STR_LIT> CC = getPredicate ( MI , TII ) ; if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos ) { <STR_LIT> NCC = getPredicate ( & * MBBI , TII ) ; if ( NCC == OCC ) { Mask |= ( <NUM_LIT> << Pos ) ; } else if ( NCC != CC ) break ; -- Pos ; ++ MBBI ; } Mask |= ( <NUM_LIT> << Pos ) ; MIB . addImm ( Mask ) ; Modified = true ; ++


<s> return ( __A [ <NUM_LIT> ] >= __B [ <NUM_LIT> ]


<s> static SDValue LowerANY_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In .


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; SDValue Swap = DAG . getAtomicCmpSwap ( <STR_LIT> , dl , VT , VTs , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Zero , Zero , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast <

AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const DataLayout & DL = getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; <ISA_LIT>MCExpr :: VariantKind TF = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isCPI ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( ) )


<s> case R2 : case S2 : case D2 : case Q2 : return <NUM_LIT> ; case R3 : case S3 : case D3 : case Q3 : return <NUM_LIT> ; case R4 : case S4 : case D4 : case Q4 : return <NUM_LIT> ; case R5 : case S5 : case D5 : case Q5 : return <NUM_LIT> ; case R6 : case S6 : case D6 : case Q6 : return <NUM_LIT> ; case R7 : case S7 : case D7 : case Q7 : return <NUM_LIT> ; case R8 : case S8 : case D8 : case Q8 : return <NUM_LIT> ; case R9 : case S9 : case D9 : case Q9 : return <NUM_LIT> ; case R10 : case S10 : case D10 : case Q10 : return <NUM_LIT> ; case R11 : case S11 : case D11 : case Q11 : return <NUM_LIT> ; case R12 : case S12 : case D12 : case Q12 : return <NUM_LIT> ; case SP : case S13 : case D13 : case Q13 : return <NUM_LIT> ; case LR : case S14 : case D14 : case Q14 : return <NUM_LIT> ; case PC : case S15 : case D15 : case Q15


<s> MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ++ OpIdx ; } if ( OpIdx + <NUM_LIT> >= NumOps ) return false ; assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && ( OpInfo [ OpIdx + <NUM_LIT> ] . RegClass == <STR_LIT> ) && ( OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> ) && <STR_LIT> ) ; unsigned Rs = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( Rs ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( ShOp , <NUM_LIT> ) ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn ,


<s> ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm

( Offset ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlag ( Flag ) ;


<s> vrshrn_n_u16 ( uint16x8_t __a , const int __b ) { return ( uint8x8_t ) __builtin_neon_vrshrn_nv8hi ( (


<s> static const char * rs6000_call_template_1 ( rtx * operands , unsigned int funop , bool sibcall ) { gcc_assert ( funop <= MAX_RECOG_OPERANDS ) ; char arg [ <NUM_LIT> ] ; arg [ <NUM_LIT> ] = <NUM_LIT> ; if ( GET_CODE ( operands [ funop + <NUM_LIT> ] ) == UNSPEC ) { if ( XINT ( operands [ funop + <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSGD ) sprintf ( arg , <STR_LIT> , funop + <NUM_LIT> ) ; else if ( XINT ( operands [ funop + <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) sprintf ( arg , <STR_LIT> ) ; } char z [ <NUM_LIT> ] ; sprintf ( z , <STR_LIT> , funop , ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT &&


<s> static unsigned int rs6000_elf_section_type_flags ( tree decl , const char * name , int reloc ) { return default_section_type_flags_1 ( decl , name , reloc , flag_pic || DEFAULT_ABI ==


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( TLS_GDCALL ) ; OPCODE ( TLS_LDCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( POPCNT ) ; OPCODE ( SMUL_LOHI ) ; OPCODE ( UMUL_LOHI ) ; OPCODE ( SDIVREM ) ; OPCODE ( UDIVREM ) ; OPCODE ( SADDO ) ; OPCODE ( SSUBO ) ; OPCODE ( UADDO ) ; OPCODE ( USUBO ) ; OPCODE ( ADDCARRY ) ; OPCODE ( SUBCARRY ) ; OPCODE ( GET_CCMASK ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE (


<s> case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg (

<STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ) ;


<s> MCInst Inst ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { case Match_Success : ProcessInstruction ( Inst , Operands ) ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc


<s> return isExtImm < <NUM_LIT> > ( true ,


<s> if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCFPmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _directstoreu_u32 ( void * __P , unsigned int __A ) { __builtin_ia32_directstoreu_u32 ( ( unsigned int * ) __P ,


<s> } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE


<s> LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } return


<s> return aarch64_output_sve_cnt_immediate ( prefix , operands , value . coeffs


<s> regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset


<s> if ( Idx . sge ( - <NUM_LIT> ) && Idx . slt ( <NUM_LIT> / Ty .

getVectorElementType ( ) . getSizeInBits ( ) ) ) return Op ;


<s> if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return <NUM_LIT> ; else if ( from == HIGH_REGS || to == HIGH_REGS ) return optimize_size ? <NUM_LIT> : <NUM_LIT> ; else return <NUM_LIT>


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ( ! MFI -> hasVarSizedObjects (


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > (


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand TrueReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * FalseClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; const TargetRegisterClass * TrueClass = MRI . getRegClass ( TrueReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , FalseClass ) ) return nullptr ; if ( ! MRI . constrainRegClass ( DestReg , TrueClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI .

getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


, ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> return __builtin_mve_vqrshlq_m_n_sv8hi ( __a ,


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * Gep = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! Gep || Gep -> getOpcode ( ) != TargetOpcode :: G_GEP ) return None ; if ( ! MRI . hasOneUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Gep -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Gep -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] (

MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , } } ;


<s> void aarch64_cpu_cpp_builtins ( cpp_reader * pfile ) { aarch64_define_unconditional_macros ( pfile ) ; aarch64_update_cpp_builtins ( pfile )


<s> char * opt2 = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + strlen ( target_offloadend_filename ) ) ; sprintf ( opt1 , <STR_LIT> , target_descr_filename ) ; sprintf ( opt2 , <STR_LIT> , target_offloadend_filename ) ; const char * target_so_filename = make_temp_file ( <STR_LIT> ) ; temp_files [ num_temps ++ ] = target_so_filename ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , target_compiler ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt1 ) ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) { if ( ! strcmp ( argv [ i ] , <STR_LIT> ) && i + <NUM_LIT> != argc ) out_obj_filename = argv [ ++ i ] ; else obstack_ptr_grow ( & argv_obstack , argv [ i ] ) ; } if ( ! out_obj_filename ) fatal_error ( input_location , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt2 ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; compile_for_target ( & argv_obstack ) ; char * rename_section_opt = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + strlen ( image_section_name ) ) ; sprintf ( rename_section_opt , <STR_LIT> , image_section_name ) ; const char * objcopy_argv [ <NUM_LIT> ] ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; if ( target_ilp32 ) objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; else objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = target_so_filename ; objcopy_argv [ <NUM_LIT> ] = <STR_LIT> ; objcopy_argv [ <NUM_LIT> ] = rename_section_opt ; objcopy_argv [ <NUM_LIT> ] = NULL ; fork_execute ( objcopy_argv [ <NUM_LIT> ] , CONST_CAST ( char


<s> uint64_t encoding = <STR_LIT> ( Val , sizeof ( T ) * <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm (


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> EmitInstruction ( Ret , getSubtargetInfo ( ) ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( )


<s> if ( getStubFactory ( ) == NULL ) return false ; getStubFactory ( ) -> addPrototype ( new <ISA_LIT>LA25Stub ( * this ) ) ; return true


<s> int64_t Value = ConstExpr -> getValue ( ) ; return ( Value != <NUM_LIT> ) && ( (


<s> ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } } if ( std :: any_of ( StartInsertPt , StartInsertBB -> end ( ) , shouldInspect ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MachineBasicBlock * MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( Subtarget -> isTargetELF ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTLSModel ( GV , getTargetMachine ( ) . getRelocationModel ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args


<s> uint64_t StackSize = MFFrame . getStackSize ( ) ; if ( ZFI -> getRestoreGPRRegs ( ) . LowGPR ) { -- MBBI ; unsigned Opcode = MBBI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned AddrOpNo = <NUM_LIT> ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; uint64_t Offset = StackSize + MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . getImm ( ) ; unsigned NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes


<s> static bool aarch64_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { if ( op == STORE_BY_PIECES


<s> fprintf ( stderr , <STR_LIT> , ( name1 ) ? name1 : <STR_LIT> , fcode , ( name2 ) ? name2 : <STR_LIT> , ( int ) icode , name3 , func_valid_p ? <STR_LIT> : <STR_LIT> ) ; } if ( ! func_valid_p ) { rs6000_invalid_builtin ( fcode ) ; return expand_call ( exp , target , ignore ) ; } switch ( fcode ) { case RS6000_BUILTIN_RECIP : return rs6000_expand_binop_builtin ( CODE_FOR_recipdf3 , exp , target ) ; case RS6000_BUILTIN_RECIPF : return rs6000_expand_binop_builtin ( CODE_FOR_recipsf3 , exp , target ) ; case RS6000_BUILTIN_RSQRTF : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtsf2 , exp , target ) ; case RS6000_BUILTIN_RSQRT : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtdf2 , exp , target ) ; case POWER7_BUILTIN_BPERMD : return rs6000_expand_binop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_bpermd_di : CODE_FOR_bpermd_si ) , exp , target ) ; case RS6000_BUILTIN_GET_TB : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_get_timebase , target ) ; case RS6000_BUILTIN_MFTB : return rs6000_expand_zeroop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_rs6000_mftb_di : CODE_FOR_rs6000_mftb_si ) , target ) ; case RS6000_BUILTIN_MFFS : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_mffs , target ) ; case RS6000_BUILTIN_MTFSF : return rs6000_expand_mtfsf_builtin ( CODE_FOR_rs6000_mtfsf , exp ) ; case ALTIVEC_BUILTIN_MASK_FOR_LOAD : case ALTIVEC_BUILTIN_MASK_FOR_STORE : { int icode = ( BYTES_BIG_ENDIAN ? ( int ) CODE_FOR_altivec_lvsr_direct : ( int ) CODE_FOR_altivec_lvsl_direct ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; tree arg ; rtx op , addr , pat ; gcc_assert ( TARGET_ALTIVEC ) ; arg = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; gcc_assert ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) ) ; op = expand_expr ( arg , NULL_RTX , Pmode , EXPAND_NORMAL ) ; addr = memory_address ( mode , op ) ; if ( fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE ) op = addr ; else { op = gen_reg_rtx ( GET_MODE ( addr ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op , gen_rtx_NEG ( GET_MODE ( addr ) , addr ) ) ) ; } op = gen_rtx_MEM ( mode , op ) ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target , op ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ; } case ALTIVEC_BUILTIN_VCFUX : case ALTIVEC_BUILTIN_VCFSX : case ALTIVEC_BUILTIN_VCTUXS : case ALTIVEC_BUILTIN_VCTSXS : if ( call_expr_nargs ( exp ) == <NUM_LIT> ) { exp = build_call_nary ( TREE_TYPE ( exp ) , CALL_EXPR_FN ( exp ) , <NUM_LIT> , CALL_EXPR_ARG ( exp , <NUM_LIT> ) , integer_zero_node ) ; } break ; default : break ; } if ( TARGET_ALTIVEC ) { ret = altivec_expand_builtin ( exp , target , & success ) ; if ( success


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) { SDValue CPHi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ?


<s> SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue M = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , R , M ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , M , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , R , M , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Op ) ; C = ConstantVector :: get ( CVM2 ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; M = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , R , M ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ,


<s> if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return


<s> void <ISA_LIT>InstPrinter :: printU7ImmOperand ( const MCInst * MI , unsigned OpNo ,


<s> * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { * base = XEXP ( addr


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue (


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT> ) . getImm


<s> static inline bool MemBarrierInstr ( uint32_t insn ) { unsigned op7_4 = slice ( insn , <NUM_LIT> ,


<s> add_output_operand ( icode ) ; add_input_operand ( icode , args [ <NUM_LIT> ] ) ; for ( unsigned int i = <NUM_LIT> ; i < nops ; ++ i ) { add_input_operand ( icode , args [ i + <NUM_LIT> ] ) ; if ( FLOAT_MODE_P ( GET_MODE ( args [ i + <NUM_LIT> ] ) ) ) has_float_operand_p = true ; } if ( has_float_operand_p ) { rtx pred = m_ops [ <NUM_LIT> ] . value ; if ( flag_trapping_math && pred != CONST1_RTX ( GET_MODE ( pred ) ) ) add_integer_operand ( SVE_STRICT_GP ) ; else add_integer_operand ( SVE_RELAXED_GP )


<s> if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( N , <NUM_LIT> ) ; SDLoc DL (


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { return MBB . erase


<s> } Parser . Lex ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal (


<s> MVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , NULL , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , NULL , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut .


<s> SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; SDVTList VTs = DAG . getVTList ( LHS .


<s> static unsigned getNumOfConsecutiveZeros ( SDValue Op , SDValue Mask , unsigned NumElems , bool Low , SelectionDAG & DAG ) { unsigned NumZeros = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { unsigned Index = Low ? i : NumElems - i - <NUM_LIT> ; SDValue Idx = Mask . getOperand ( Index ) ; if ( Idx . getOpcode ( ) == <STR_LIT> ) { ++ NumZeros ; continue ; } SDValue Elt = DAG . getShuffleScalarElt ( Op . getNode ( ) , Index ) ; if ( Elt . getNode ( ) && isZeroNode ( Elt ) ) ++ NumZeros ; else