<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF )


<s> right . i [ <NUM_LIT> ] = <NUM_LIT> - count ; return ( ( qword ) ( vec_or ( vec_slo ( ( vec_uchar16 ) ( a ) , left . v ) , vec_sro ( ( vec_uchar16 ) ( a


<s> static bool CheckTy0Ty1MemSizeAlign ( const LegalityQuery & Query , std :: initializer_list < TypesAndMemOps > SupportedValues ) { unsigned QueryMemSize = Query . MMODescrs [ <NUM_LIT> ] . SizeInBits ; if ( ! isPowerOf2_64 ( QueryMemSize ) ) return false ; for ( auto & Val : SupportedValues ) { if ( Val . ValTy != Query . Types [ <NUM_LIT> ] ) continue ; if ( Val . PtrTy != Query . Types


<s> static bool CC_<ISA_LIT>64Byval ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { unsigned Align = std :: max ( ArgFlags . getByValAlign ( ) , ( unsigned ) <NUM_LIT> ) ; unsigned Size = ( ArgFlags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> ; unsigned FirstIdx = State . getFirstUnallocated ( <ISA_LIT>64IntRegs , <NUM_LIT> ) ; assert ( Align <= <NUM_LIT> && <STR_LIT> ) ; if ( ( Align == <NUM_LIT> ) && (


<s> bool <ISA_LIT>MCCodeEmitter :: isPrefixedInstruction ( const MCInst & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; const <ISA_LIT>InstrInfo * InstrInfo = static_cast < const <ISA_LIT>InstrInfo * > ( & MCII ) ; return InstrInfo -> isPrefixed ( Opcode


<s> if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return isInt < <NUM_LIT> > ( Value ) ; } return false


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { llvm_unreachable ( <STR_LIT>


<s> getContext ( ) . getOrCreateSymbol ( Name ) ; return false ; } MCSymbol * Sym ; const MCExpr * Value ; if ( MCParserUtils :: parseAssignmentExpression ( Name , true , Parser , Sym , Value ) ) return true ; Sym -> setVariableValue


<s> static int l2_size_name [ <NUM_LIT> ] = { CTL_HW , HW_L2CACHESIZE } ; sysctl ( l1_size_name , <NUM_LIT> , & l1_sizekb , & len , NULL , <NUM_LIT> ) ; sysctl ( l1_line_name , <NUM_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; sysctl ( l2_size_name , <NUM_LIT> , & l2_sizekb , & len , NULL , <NUM_LIT> ) ; l1_assoc = <NUM_LIT> ; return describe_cache ( l1_sizekb / <NUM_LIT> , l1_line ,


<s> assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT . is512BitVector ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; unsigned PermMask = <NUM_LIT> , Imm = <NUM_LIT> ; unsigned ControlBitsNum = WidenedMask . size ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { if ( WidenedMask [ i ] == SM_SentinelZero ) return SDValue ( ) ; Imm = ( WidenedMask [ i ] == SM_SentinelUndef ) ? <NUM_LIT> : WidenedMask [ i ] ; PermMask |= ( Imm % WidenedMask . size (


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue Tlsgd = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TGA ) ; SDValue GP = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GP , Tlsgd ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( DAG . getEntryNode ( ) , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; return CallResult . first ; } SDValue Offset ; if ( GV -> isDeclaration ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl


<s> type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = arm_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ fcode ] = fndecl ; } if ( TARGET_CRYPTO && TARGET_HARD_FLOAT ) { tree V16UQI_type_node = arm_simd_builtin_type ( V16QImode , true , false ) ; tree V4USI_type_node = arm_simd_builtin_type ( V4SImode , true , false ) ; tree v16uqi_ftype_v16uqi = build_function_type_list ( V16UQI_type_node , V16UQI_type_node , NULL_TREE ) ; tree v16uqi_ftype_v16uqi_v16uqi = build_function_type_list ( V16UQI_type_node , V16UQI_type_node , V16UQI_type_node , NULL_TREE ) ; tree v4usi_ftype_v4usi = build_function_type_list ( V4USI_type_node , V4USI_type_node , NULL_TREE ) ; tree v4usi_ftype_v4usi_v4usi = build_function_type_list ( V4USI_type_node , V4USI_type_node , V4USI_type_node , NULL_TREE ) ; tree v4usi_ftype_v4usi_v4usi_v4usi = build_function_type_list ( V4USI_type_node , V4USI_type_node


<s> static tree arm_handle_cmse_nonsecure_call ( tree * node , tree name , tree , int , bool * no_add_attrs ) { tree decl = NULL_TREE , fntype = NULL_TREE ; tree type ; if ( ! use_cmse ) { * no_add_attrs = true ; warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; return NULL_TREE ; } if ( TREE_CODE ( * node ) == VAR_DECL || TREE_CODE ( * node ) == TYPE_DECL ) { decl = * node ; fntype = TREE_TYPE ( decl ) ; } while ( fntype != NULL_TREE && TREE_CODE ( fntype ) == POINTER_TYPE ) fntype = TREE_TYPE ( fntype ) ; if ( ! decl || TREE_CODE ( fntype ) != FUNCTION_TYPE ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } * no_add_attrs |= cmse_func_args_or_return_in_stack ( NULL , name


<s> if ( SYMBOL_REF_P ( addr ) ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind


<s> else x = gen_lowpart ( half_mode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( high [ <NUM_LIT> ] , x ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( bits ) ) ) ; emit_insn ( gen_and3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , const1_rtx ) ) ; emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; emit_insn ( gen_xor3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , const1_rtx ) ) ; } emit_insn ( gen_ashl3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashl3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return ; } if ( operands [ <NUM_LIT> ] == constm1_rtx ) { emit_move_insn ( low [ <NUM_LIT> ] , constm1_rtx ) ; if ( optimize_insn_for_size_p ( ) ) emit_move_insn ( high [ <NUM_LIT> ] , low [ <NUM_LIT> ] ) ; else emit_move_insn ( high [ <NUM_LIT> ] , constm1_rtx ) ; } else { gen_shld = mode == DImode ? gen_x86_shld : gen_x86_64_shld ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; emit_insn ( gen_shld ( high [ <NUM_LIT> ] , low [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; } emit_insn ( gen_ashl3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { rtx ( * gen_x86_shift_adj_1 ) ( rtx , rtx , rtx , rtx ) = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1 ; ix86_expand_clear (


<s> RC = & <STR_LIT> ; } if ( Subtarget -> isPICStyleRIPRel ( ) || GVFlags == <STR_LIT> || GVFlags == <STR_LIT> ) StubAM . Base . Reg = <STR_LIT> ; LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue (


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>FrameLowering :: create (


<s> Register ImplicitDefReg = createResultReg ( VR128X ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned MovOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned MovReg = fastEmitInst_rrrr ( MovOpcode , VR128X , RHSReg , CmpReg , ImplicitDefReg , LHSReg ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( MovReg ) ; } else if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpRHSReg , CC ) ; Register VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , LHSReg , CmpReg ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { static const uint16_t OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default :


<s> SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; }


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> OS << <STR_LIT> << getFPImm ( ) << <STR_LIT> << <STR_LIT> ( getFPImm ( ) ) << <STR_LIT> ; break ; case k_Barrier : { StringRef Name = getBarrierName ( ) ; if ( ! Name . empty ( ) ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getBarrier ( ) << <STR_LIT> ; break ; } case k_Immediate : OS << * getImm ( ) ; break ; case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; OS << * getShiftedImmVal ( ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_SysCR


<s> if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill


<s> <ISA_LIT>Operand * ErrorOperand ( SMLoc Loc , StringRef Msg ) { Error ( Loc , Msg


<s> <ISA_LIT>AbiFlags pElfFlags = { } ; if ( ! <ISA_LIT>AbiFlags :: fillByElfFlags ( pInput , elfFlags , pElfFlags ) ) return false ; const LDContext * ctx = pInput . context ( ) ; for ( auto it = ctx -> sectBegin ( ) , ie = ctx -> sectEnd ( ) ; it != ie ; ++ it ) if ( ( * it ) -> type ( ) == llvm :: ELF :: SHT_MIPS_ABIFLAGS ) { if ( ! <ISA_LIT>AbiFlags :: fillBySection ( pInput , * * it , pFlags ) ) return false ; if ( ! <ISA_LIT>AbiFlags :: isCompatible ( pInput , pElfFlags , pFlags ) ) return false ; hasFlags =


<s> bool <ISA_LIT>FrameLowering :: targetHandlesStackFrameRounding


<s> bool SelectAddrImm ( SDValue N , SDValue


<s> return <ISA_LIT>Lowering . SelectAddressRegReg ( N , Base , Index , *


<s> static DecodeStatus DecodeVecShiftR16ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT>


<s> rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low )

+ <NUM_LIT> ) * UNITS_PER_WORD ) , gen_rx_store_vector ( low , high ) ) ) ;


<s> return ! any_of ( M , [ & ] ( const Function & F ) { return F . getFnAttribute ( Attr ) . getValueAsString ( ) !=


<s> insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return <NUM_LIT> ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>16InstrInfo :: getRegisterInfo (


float const * base , __m256i index , __m256 mask , const int scale ) {


<s> case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv ::


<s> if ( ET == <STR_LIT> && ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && isOperationLegalOrCustom ( Op . getOpcode ( ) , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return true ; } LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op ) ; if ( ! LD || LD -> getExtensionType ( ) != ET || LD -> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ; if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsDereferenceable = LD -> isDereferenceable ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD


<s> printInstruction ( MI , O ) ; printAnnotation ( O


<s> auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } <STR_LIT> RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < <NUM_LIT> > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( <NUM_LIT> ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState


<s> nregs = XVECLEN ( p , <NUM_LIT> ) - <NUM_LIT> ; reg = REGNO ( XEXP ( XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( reg < <NUM_LIT> ) { if ( nregs * <NUM_LIT> == offset - <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> ) ; offset -= <NUM_LIT> ; } reg_size = <NUM_LIT> ; } else if ( IS_VFP_REGNUM ( reg ) ) { offset -= <NUM_LIT> ; reg_size = <NUM_LIT> ; } else if ( reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , reg , nregs ) ; return ; } else abort ( ) ; if ( offset != nregs * reg_size ) abort ( ) ; fprintf ( asm_out_file , <STR_LIT> ) ; offset = <NUM_LIT> ; lastreg = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= nregs ; i ++ ) { e = XVECEXP ( p , <NUM_LIT> , i ) ; if ( GET_CODE ( e ) != SET || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != MEM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG ) abort ( ) ; reg = REGNO ( XEXP ( e , <NUM_LIT> ) ) ; if ( reg < lastreg ) abort ( ) ; if ( i != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( asm_out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( asm_out_file , <STR_LIT> , reg ) ; e = XEXP ( XEXP ( e , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) { offset += reg_size ; if ( GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG || REGNO ( XEXP ( e , <NUM_LIT> ) ) != SP_REGNUM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != CONST_INT || offset != INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) abort ( ) ; } else if ( i != <NUM_LIT> || GET_CODE ( e ) != REG || REGNO (


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum )


<s> inline vector unsigned char vec_vpkuhum ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned char ) __builtin_altivec_vpkuhum ( ( vector signed

short ) a1 , ( vector signed short ) a2 ) ;


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) { MachineOperand & MO = MI . getOperand ( UseOpIdx ) ; if ( MO . isImplicit ( ) ) MI . removeOperand


<s> Register Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DestIsHigh = isHighReg ( DestReg ) ; bool Src1IsHigh = isHighReg ( Src1Reg ) ; bool Src2IsHigh = isHighReg ( Src2Reg ) ; if ( DestReg != Src1Reg && DestReg != Src2Reg ) { if ( DestIsHigh != Src1IsHigh ) { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , Src1Reg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Src1Reg = DestReg ; Src1IsHigh = DestIsHigh ; } else if ( DestIsHigh != Src2IsHigh ) { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , Src2Reg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Src2Reg = DestReg ; Src2IsHigh = DestIsHigh ; } } if ( DestReg != Src1Reg && DestReg == Src2Reg ) { commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ; std :: swap ( Src1Reg , Src2Reg ) ; std :: swap ( Src1IsHigh , Src2IsHigh ) ; } if ( ! DestIsHigh && ! Src1IsHigh && ! Src2IsHigh ) MI . setDesc ( get ( LowOpcode ) ) ; else if ( DestIsHigh && Src1IsHigh && Src2IsHigh ) MI . setDesc ( get ( HighOpcode ) ) ; else { assert ( DestReg == Src1Reg ) ; MI . setDesc ( get ( MixedOpcode ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: combineBSWAP ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) && ! cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> isVolatile ( ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getValueType ( N -> getValueType ( <NUM_LIT> ) ) } ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SDValue ResVal = BSLoad ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ResVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSLoad ) ; DCI . CombineTo ( N , ResVal ) ; DCI . CombineTo ( Load . getNode ( ) , ResVal


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VecVT ) { SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ext0 , Ext1 , Ext2 ) ; } switch ( Vec . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDLoc DL ( ExtElt ) ; SmallVector < SDValue , <NUM_LIT> > ExtOps ; for ( SDValue Op : Vec -> ops ( ) ) ExtOps . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , Op , Index ) ) ; return DAG . getNode ( Vec . getOpcode ( ) , DL , VT , ExtOps ) ; } default : return SDValue (


<s> bool SelectMOVWAddressRef ( SDValue N , SDValue & Imm , SDValue & Shift ) { Imm = N ; Shift = CurDAG -> getTargetConstant ( LogShift , <STR_LIT> ) ; return true


<s> InConstantPool = true ; } OutStreamer -> EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MF -> getDataLayout ( ) , MCPE . Val . ConstVal ) ; return ; } switch ( Opc ) { case <STR_LIT> : LowerPATCHABLE_FUNCTION_ENTER ( * MI ) ; return ; case <STR_LIT> : LowerPATCHABLE_FUNCTION_EXIT ( * MI ) ; return ; case <STR_LIT> : LowerPATCHABLE_TAIL_CALL ( * MI ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle


<s> return needsCmpXchgNb ( SI -> getValueOperand ( ) ->


<s> if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , true ) && SplatBitSize <= <NUM_LIT> ) { uint64_t SplatBitsZ = SplatBits . getZExtValue ( ) ; uint64_t SplatUndefZ = SplatUndef . getZExtValue ( ) ; uint64_t Lower = ( SplatUndefZ & ( ( uint64_t ( <NUM_LIT> ) << findFirstSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Upper = ( SplatUndefZ & ~ ( ( uint64_t ( <NUM_LIT> ) << findLastSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Value = SplatBitsZ | Upper | Lower ; SDValue Op = tryBuildVectorReplicate ( DAG , TII , DL , VT , Value , SplatBitSize ) ; if ( Op . getNode ( ) ) return Op ; uint64_t Middle = SplatUndefZ & ~ Upper & ~ Lower ; Value = SplatBitsZ | Middle


<s> punpcklbh_u ( uint8x8_t s , uint8x8_t t ) { return __builtin_loongson_punpcklbh_u ( s , t


<s> static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( std :: is_sorted ( std :: begin ( NEONLdStTable ) , std :: end ( NEONLdStTable ) ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } auto I = llvm :: lower_bound ( NEONLdStTable ,


<s> bool isABI_FPXX ( ) const { return isABI_O32 (


<s> } if ( simple_sets_p && ( aarch64_tune_params . fusible_ops & AARCH64_FUSE_MOVK_MOVK ) ) { if ( GET_CODE ( SET_DEST ( prev_set ) ) == ZERO_EXTRACT && GET_CODE ( SET_DEST ( curr_set ) ) == ZERO_EXTRACT && REG_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && REG_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == REGNO ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) == <NUM_LIT> && CONST_INT_P ( SET_SRC ( prev_set ) ) && CONST_INT_P ( SET_SRC ( curr_set ) ) ) return true ; } if ( simple_sets_p && ( aarch64_tune_params . fusible_ops & AARCH64_FUSE_ADRP_LDR ) ) { if ( satisfies_constraint_Ush ( SET_SRC ( prev_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && REG_P ( SET_DEST ( curr_set ) ) ) { rtx curr_src = SET_SRC ( curr_set ) ; if ( GET_CODE ( curr_src ) == ZERO_EXTEND ) curr_src = XEXP ( curr_src , <NUM_LIT> ) ; if ( MEM_P ( curr_src ) && GET_CODE ( XEXP ( curr_src , <NUM_LIT> ) ) == LO_SUM && REG_P ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) && rtx_equal_p ( XEXP ( XEXP ( curr_src , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( SET_SRC ( prev_set ) , <NUM_LIT> ) ) ) return true ; } } if ( ( aarch64_tune_params . fusible_ops & AARCH64_FUSE_AES_AESMC ) && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( ( aarch64_tune_params . fusible_ops & AARCH64_FUSE_CMP_BRANCH ) && any_condjump_p ( curr ) ) { enum attr_type prev_type = get_attr_type ( prev ) ; if ( prev_type == TYPE_ALUS_SREG || prev_type == TYPE_ALUS_IMM || prev_type

== TYPE_LOGICS_REG || prev_type == TYPE_LOGICS_IMM ) return true ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , tree type , int named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = <NUM_LIT> , kbase = <NUM_LIT> ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= <NUM_LIT> * BITS_PER_WORD && ( cum -> words % <NUM_LIT> ) != <NUM_LIT> ) cum -> words ++ ; cum -> intoffset = <NUM_LIT> ; cum -> use_stack = <NUM_LIT> ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , <NUM_LIT> , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = <NUM_LIT> ; rvec [ <NUM_LIT> ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > <NUM_LIT> || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v (


<s> if ( ! VCTPs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; for ( auto * MI : VCTPs ) dbgs ( ) << <STR_LIT> << * MI ; } if ( ! FoundAllComponents ( ) )


<s> return ( __m128 ) __builtin_ia32_loadss (


<s> if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else MO . getExpr ( ) -> print ( O , & MAI ) ; O <<


<s> const bool CanUseBFC = AST . hasV6T2Ops ( ) || AST . hasV7Ops ( ) ; const unsigned AlignMask = Alignment - <NUM_LIT> ; const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) { if ( CanUseBFC ) { AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm

( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ;


<s> bool <ISA_LIT>FastISel :: SelectIndirectBr ( const Instruction * I ) { unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > (


<s> static const unsigned GPREven3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairEven ( HintReg , MF ) == <NUM_LIT> ) return std :: make_pair ( RC -> allocation_order_begin ( MF ) , RC -> allocation_order_end ( MF ) ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven1 , GPREven1 + ( sizeof ( GPREven1 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven4 , GPREven4 + ( sizeof ( GPREven4 ) / sizeof ( unsigned ) ) ) ; } else if ( FramePtr == <STR_LIT> ) { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven2 , GPREven2 + ( sizeof ( GPREven2 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven5 , GPREven5 + ( sizeof ( GPREven5 ) / sizeof ( unsigned ) ) ) ; } else { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven3 , GPREven3 + ( sizeof ( GPREven3 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven6 , GPREven6 + ( sizeof (


<s> CombinerHelper Helper ( Observer , B , KB , MDT , LI ) ; return Generated . tryCombineAll ( Observer ,


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> case ESize16 : Imm64 = Imm8 << <NUM_LIT> * ( cmode >> <NUM_LIT> & <NUM_LIT> ) ; break ; case ESize32 : { if ( cmode == <NUM_LIT> ) Imm64 = ( Imm8 << <NUM_LIT> ) | <NUM_LIT> ; else if ( cmode == <NUM_LIT> ) Imm64 = ( Imm8 << <NUM_LIT> ) | <NUM_LIT> ; else { Imm64 = Imm8 << <NUM_LIT> * ( cmode >> <NUM_LIT> & <NUM_LIT> ) ; } break ; } case ESize64


<s> if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode ,


<s> if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getNumOperands ( ) != <NUM_LIT> || Op1 . getNumOperands ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Concat0Op1 . getOpcode ( ) != <STR_LIT> || Concat1Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements (


<s> int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( STI , Out , <STR_LIT> ,


<s> static int current_file_function_operand ( rtx sym_ref ) { if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( sym_ref == XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT>

) && ! DECL_WEAK ( current_function_decl ) ) return <NUM_LIT> ;


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbol * Stub = OutContext . GetOrCreateSymbol ( StringRef ( x ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer . EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer . EmitLabel ( Stub ) ; if ( Subtarget -> getRelocationModel ( ) == Reloc :: PIC_ ) llvm_unreachable ( <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( Signature -> ParamSig , LE , true ) ; EmitJal ( MSymbol ) ; EmitSwapFPIntRetval ( Signature -> RetSig , LE ) ; EmitInstrReg ( <STR_LIT> , <STR_LIT> ) ; MCSymbol * Tmp = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( Tmp ) ; const MCSymbolRefExpr * E = MCSymbolRefExpr :: Create ( Stub , OutContext ) ; const MCSymbolRefExpr * T = MCSymbolRefExpr :: Create ( Tmp , OutContext ) ; const MCExpr * T_min_E = MCBinaryExpr :: CreateSub ( T , E , OutContext ) ; OutStreamer . EmitELFSize ( Stub , T_min_E ) ; TS . emitDirectiveEnd ( x ) ; OutStreamer . PopSection (


<s> } if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall

( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ;


<s> if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned CC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get (

SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ;


<s> void pushOperator ( InfixCalculatorTok Op ) { if ( InfixOperatorStack . empty ( ) ) { InfixOperatorStack . push_back ( Op ) ; return ; } unsigned Idx = InfixOperatorStack . size ( ) - <NUM_LIT> ; InfixCalculatorTok StackOp = InfixOperatorStack [ Idx ] ; if ( OpPrecedence [ Op ] > OpPrecedence [ StackOp


<s> } if ( incoming ) { tree parm ; for ( parm = DECL_ARGUMENTS ( fun ) ; parm && parm != void_list_node ; parm = TREE_CHAIN ( parm ) ) if ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( parm ) ) ) return true ; } else { function_args_iterator args_iter ; tree arg_type ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) if (

rs6000_parm_needs_stack ( args_so_far , arg_type ) ) return true ;


<s> VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; IsMasked = true ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT ,

isSEXTLoad , Base , Offset , isInc , DAG ) ;


<s> void <ISA_LIT>CCState :: PreAnalyzeFormalArgumentsForF128 ( const SmallVectorImpl < <STR_LIT> > & Ins ) { const MachineFunction & MF = getMachineFunction ( ) ; for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) { Function :: const_arg_iterator FuncArg = MF . getFunction ( ) -> arg_begin ( ) ; if ( Ins [ i ] . Flags . isSRet ( ) ) { OriginalArgWasF128 . push_back ( false ) ; OriginalArgWasFloat . push_back ( false ) ; continue ; } assert ( Ins [ i ] . getOrigArgIndex ( ) < MF . getFunction ( ) -> arg_size ( ) ) ; std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) ) ; OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArg -> getType ( ) , nullptr ) ) ; OriginalArgWasFloat . push_back ( FuncArg -> getType ( )


<s> bool SpecialShift32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SpecialShift64 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SetCR = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool RightShift = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding


<s> break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize =


<s> unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; if ( Type == - <NUM_LIT> ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind +


<s> Chain ( MachineInstr * MI , unsigned Idx , Color C ) : StartInst ( MI ) , LastInst ( MI ) , KillInst ( nullptr ) , StartInstIdx ( Idx ) , LastInstIdx ( Idx ) , KillInstIdx ( <NUM_LIT> ) , LastColor ( C ) { Insts . insert


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { unsigned NewImm = Imm ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT>


<s> getActionDefinitionsBuilder ( { G_UADDO , G_UADDE , G_USUBO , G_USUBE , G_UMULO } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( G_UMULH ) . legalFor ( { s32 } ) . maxScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) .


<s> unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize ,


<s> return ( __m256i ) __builtin_ia32_expandqi256_maskz ( ( __v32qi ) __B , ( __v32qi ) _mm256_setzero_si256 ( )


<s> SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N ,


<s> if ( Invert ) { Register Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { Register Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ; } } else if ( BinOpcode ) BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; else if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> - BitSize ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor


<s> __inline__ static unsigned long long sh_media_MSUBS_W ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) ,


<s> Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT>


<s> return ( __mmask8 ) __builtin_ia32_cmpb256_mask ( ( __v32qi ) __X , (


<s> return MatchOperand_ParseFail ; } const MCExpr * Lane = MCConstantExpr :: Create ( Parser . getTok ( ) . getIntVal ( ) , getContext ( ) ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Lane , S , E ) ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) .


<s> static __inline qword si_fsmh ( qword a ) { vec_uchar16 in ; vec_short8 mask ; in = ( vec_uchar16 ) ( a ) ; mask = ( vec_short8 ) ( vec_splat ( in , <NUM_LIT> ) ) ; return ( ( qword ) ( vec_sra ( vec_sl ( mask , ( ( vec_ushort8 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }


<s> case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB =


<s> if ( Desc . getOpcode ( ) == <STR_LIT> ) { Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; } return Size


<s> return ( __m256i ) __builtin_ia32_expandsi256_mask ( ( __v8si ) __A , ( __v8si )


<s> HasCC = true ; CCDead = true ; return true ; } return false ; } } else { if ( HasCC ) return false ; } } else if ( ( is2Addr && Entry . PredCC2 == <NUM_LIT> ) || ( ! is2Addr && Entry . PredCC1 == <NUM_LIT> ) ) { if ( HasCC ) return true ; if ( ! HasImplicitCPSRDef ( MI -> getDesc ( ) ) ) return false ; HasCC = true ; } else { if ( HasCC ) return


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstr ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateDXReg


<s> Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - imm )


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return &


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getSIMDShift64OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - ( MO . getImm (


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div8hi ( ( int16x8_t


<s> } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'e' && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' &&

TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ;


<s> static DecodeStatus DecodeFCCRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> uint64_t <ISA_LIT>GNULDBackend :: emitSectionData ( const LDSection & pSection , MemoryRegion & pRegion ) const { assert ( pRegion . size ( ) && <STR_LIT> ) ; const ELFFileFormat * file_format = getOutputFormat ( ) ; if ( file_format -> hasPLT ( ) && ( & pSection == & ( file_format -> getPLT ( ) ) ) ) { uint64_t result = m_pPLT -> emit ( pRegion ) ; return result ; } if ( file_format -> hasGOT ( ) && ( & pSection == & ( file_format -> getGOT ( ) ) ) ) { uint64_t result = m_pGOT -> emit ( pRegion ) ; return result


<s> void printS32ImmOperand ( const MachineInstr * MI , int OpNum ) { O << ( int32_t ) MI -> getOperand ( OpNum


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) || ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf32 ) || ( VT == <STR_LIT>


<s> default : return false ; case <STR_LIT> : { EVT PtrTy = TLI . getPointerTy ( ) ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const AllocaInst * Slot = cast < AllocaInst > ( I . getArgOperand ( <NUM_LIT> ) ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Slot , AM ) ) return false ; if ( ! <ISA_LIT>FastEmitStore ( PtrTy , Op1 , AM ) ) return false ; return true ; } case <STR_LIT> : { ConstantInt * CI = dyn_cast < ConstantInt > ( I . getArgOperand ( <NUM_LIT> ) ) ; const Type * Ty = I . getCalledFunction ( ) -> getReturnType ( ) ; assert ( CI && <STR_LIT> ) ; MVT VT ; if ( ! isTypeLegal ( Ty , VT ) ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> isZero ( ) ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { const DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress


<s> else if ( GET_CODE ( sub_mem ) == POST_MODIFY ) { rtx post_mem = XEXP ( sub_mem , <NUM_LIT> ) ; rtx plus_op = XEXP ( sub_mem , <NUM_LIT> ) ; rtx post_val = XEXP ( plus_op , <NUM_LIT> ) ; low_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , post_mem , gen_rtx_PLUS ( Pmode , post_mem , post_val ) ) ) ; high_part [ mem ] = gen_frame_mem ( SImode , plus_constant ( Pmode , post_mem , <NUM_LIT> ) ) ; } else { low_part [ mem ] = adjust_address ( mem_rtx , SImode , <NUM_LIT> ) ; high_part [ mem ] = adjust_address ( mem_rtx , SImode , <NUM_LIT> ) ; } if ( ( load_p && reg_overlap_mentioned_p ( low_part [ <NUM_LIT> ] , high_part [ <NUM_LIT> ] ) )

|| GET_CODE ( sub_mem ) == POST_MODIFY ) {


<s> if ( Alloca -> isSwiftError ( ) ) return false ; } } unsigned SrcReg = <NUM_LIT> ; if ( const auto * CI = dyn_cast < ConstantInt > ( Op0 ) ) { if ( CI -> isZero ( ) ) SrcReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else if ( const auto * CF = dyn_cast < ConstantFP > ( Op0 ) ) { if ( CF -> isZero ( ) && ! CF -> isNegative ( ) ) { VT = <STR_LIT> ( VT . getSizeInBits ( ) ) ; SrcReg = ( VT == <STR_LIT> )


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasD32 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC


<s> printAnnotation ( OS , Annot ) ; EmitAny<ISA_LIT>InstComments ( MI , * CommentStream


<s> gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base == stack_pointer_rtx && m -> fs . sp_realigned && cfa_offset >= m -> fs . sp_realigned_offset ) { gcc_checking_assert ( stack_realign_fp ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs .


<s> return ( __m128i ) __builtin_ia32_pmuludq128 ( ( __v4si ) __A , ( __v4si )


<s> auto * ShuffleTy = cast < FixedVectorType > ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( isa < LoadInst > ( Inst ) ) { auto * ShuffleEltTy = cast < FixedVectorType > ( Inst -> getType ( ) ) ; unsigned NumSubVecElems = ShuffleEltTy -> getNumElements ( ) / Factor ; switch ( NumSubVecElems ) { default : return false ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ShuffleTy -> getNumElements ( ) != NumSubVecElems ) return false ; break ; } decompose ( Inst , Factor , ShuffleTy , DecomposedVectors ) ; if ( NumSubVecElems == <NUM_LIT> ) transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; else deinterleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , FixedVectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( Factor == <NUM_LIT> ) interleave8bitStride4 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; if ( Factor == <NUM_LIT> ) interleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; break ; default : return false ; } Value * WideVec = concatenateVectors ( Builder ,


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) { HasScatteredSymbols = true ; HasReliableSymbolDifference =


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [ RegNo


<s> rtx e0 ; rtx e1 ; unsigned reg ; e0 = XEXP ( p , <NUM_LIT> ) ; e1 = XEXP ( p , <NUM_LIT> ) ; switch ( GET_CODE ( e0 ) ) { case MEM : if ( GET_CODE ( XEXP ( e0 , <NUM_LIT> ) ) != PRE_DEC || ! REG_P ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) || REGNO ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) != SP_REGNUM ) abort ( ) ; asm_fprintf ( out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( REGNO ( e1 ) ) ) asm_fprintf ( out_file , <STR_LIT> , ( REGNO ( e1 ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( out_file , <STR_LIT> , REGNO ( e1 ) ) ; break ; case REG : if ( REGNO ( e0 ) == SP_REGNUM ) { if ( GET_CODE ( e1 ) != PLUS || ! REG_P ( XEXP ( e1 , <NUM_LIT> ) ) || REGNO ( XEXP ( e1 , <NUM_LIT> ) ) != SP_REGNUM || ! CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) abort ( ) ; asm_fprintf ( out_file , <STR_LIT> , - INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else if ( REGNO ( e0 ) == HARD_FRAME_POINTER_REGNUM ) { HOST_WIDE_INT offset ; if ( GET_CODE ( e1 ) == PLUS ) { if ( ! REG_P ( XEXP ( e1 , <NUM_LIT> ) ) || ! CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) abort ( ) ; reg = REGNO ( XEXP ( e1 , <NUM_LIT> ) ) ; offset = INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ; asm_fprintf ( out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg , offset ) ; } else if ( REG_P ( e1 ) ) { reg = REGNO ( e1 ) ; asm_fprintf ( out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg ) ; } else abort ( ) ; } else if ( REG_P ( e1 ) && REGNO ( e1 ) == SP_REGNUM ) { asm_fprintf ( out_file , <STR_LIT> , REGNO ( e0 ) ) ; } else if ( GET_CODE ( e1 ) == PLUS && REG_P ( XEXP ( e1 , <NUM_LIT> ) ) && REGNO ( XEXP ( e1 , <NUM_LIT> ) ) == SP_REGNUM && CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) { asm_fprintf ( out_file , <STR_LIT> , REGNO ( e0 ) , ( int ) INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else abort


<s> std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } return


<s> SmallVector < int , <NUM_LIT> > EvenMask ( NumElts / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > OddMask ( NumElts / <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i != e ; ++ i ) { EvenMask [ i ] = i * <NUM_LIT> ; OddMask [ i ] = i * <NUM_LIT> + <NUM_LIT> ; } Value * EvenElts = Builder . CreateShuffleVector ( BO , BO , EvenMask ) ; Value * OddElts = Builder . CreateShuffleVector ( BO , BO , OddMask ) ; Value * MAdd = Builder . CreateAdd ( EvenElts , OddElts ) ; SmallVector < int , <NUM_LIT> > ConcatMask ( NumElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Value * Zero = Constant :: getNullValue ( MAdd -> getType ( ) ) ; Value * Concat = Builder . CreateShuffleVector ( MAdd , Zero , ConcatMask ) ; Add -> replaceUsesOfWith ( BO , Concat ) ; Add -> setHasNoSignedWrap ( false ) ; Add -> setHasNoUnsignedWrap ( false ) ; return true


<s> CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; break ; case ExynosM1 : PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Kryo


<s> MachineFunction :: iterator MBBI = MBB ; if ( std :: next ( MBBI ) == MBB -> getParent ( ) ->


<s> if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getTargetConstant ( IncVal , <STR_LIT> ) ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ?


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { return true


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( )

, FrameAddr , MachinePointerInfo ( ) ) ;


<s> SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp ) ; return


<s> const char * arg ; if ( TREE_VALUE ( attr ) == NULL_TREE || TREE_CODE ( TREE_VALUE (

attr ) ) != STRING_CST ) return ARM_PCS_UNKNOWN ;


<s> static MCSymbolizer * create<ISA_LIT>ExternalSymbolizer ( StringRef TT , LLVMOpInfoCallback GetOpInfo , LLVMSymbolLookupCallback SymbolLookUp , void * DisInfo , MCContext * Ctx , MCRelocationInfo * RelInfo ) { return new llvm :: <ISA_LIT>ExternalSymbolizer ( * Ctx , std :: unique_ptr < MCRelocationInfo > ( RelInfo ) , GetOpInfo , SymbolLookUp


<s> case CmpInst :: FCMP_UNE : NeedExtraBranch = true ; Predicate = CmpInst :: FCMP_ONE ; break ; } bool SwapArgs ; unsigned BranchOpc ; std :: tie ( CC , SwapArgs ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; BranchOpc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( CmpLHS , CmpRHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , VT ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BranchOpc ) ) . addMBB ( TrueMBB ) ; if ( NeedExtraBranch ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; } uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; FastEmitBranch ( FalseMBB , DbgLoc ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && isTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) { unsigned TestOpc = <NUM_LIT> ; switch ( SourceVT . SimpleTy ) { default : break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; } if ( TestOpc ) { unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TestOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; unsigned JmpOpc = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TrueMBB ) ) { std :: swap ( TrueMBB , FalseMBB ) ; JmpOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( JmpOpc ) ) . addMBB ( TrueMBB ) ; FastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight =


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) RegDefs . insert (


<s> assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> || ( Op . getMemDisp ( ) && Op . getMemDisp ( ) -> getKind ( ) != MCExpr :: Constant ) ) { * Residue = Displacement ; return <STR_LIT> ( Op . getMemModeSize ( ) , Op . getMemSegReg ( ) , Op . getMemDisp ( ) , Op . getMemBaseReg ( ) , Op . getMemIndexReg ( ) , Op . getMemScale ( ) , SMLoc ( ) , SMLoc ( ) ) ; } int64_t OrigDisplacement = static_cast < const MCConstantExpr * > ( Op . getMemDisp ( ) ) -> getValue ( ) ; CheckDisplacementBounds ( OrigDisplacement ) ; Displacement += OrigDisplacement ; int64_t NewDisplacement = ApplyDisplacementBounds ( Displacement ) ; CheckDisplacementBounds ( NewDisplacement ) ; * Residue = Displacement - NewDisplacement ; const MCExpr * Disp = MCConstantExpr :: Create ( NewDisplacement , Ctx ) ; return <STR_LIT> ( Op . getMemModeSize ( ) , Op . getMemSegReg ( ) , Disp , Op . getMemBaseReg ( ) , Op . getMemIndexReg ( ) , Op . getMemScale ( )


<s> bool isMemDisp12Len8 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange (

Mem . Length , <NUM_LIT> , <NUM_LIT> ) ;


<s> bool isTargetAEABI ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF ) && !

isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> static unsigned getShufflePSHUFHWImmediate ( ShuffleVectorSDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i + <NUM_LIT> ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << ( i


<s> case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( SYMBOL_REF_P ( x ) ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( ! aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return


<s> if ( ! getParamsForOneTrueMaskedElt ( MS , DAG , Addr , VecIndex , Alignment , Offset ) ) return SDValue ( ) ; SDLoc DL ( MS ) ; EVT VT = MS -> getValue ( ) . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , MS -> getValue (


<s> SDValue LoadAddr = Addr . getOperand ( <NUM_LIT> ) ; if ( LoadAddr . getOpcode ( ) != <STR_LIT> ) return false ; SDValue BaseOp = LoadAddr . getOperand ( <NUM_LIT> ) ; SDValue IndexReg = LoadAddr . getOperand ( <NUM_LIT> ) ; if ( BaseOp . getOpcode ( ) != <STR_LIT> ) { BaseOp = LoadAddr . getOperand ( <NUM_LIT> ) ; IndexReg = LoadAddr . getOperand ( <NUM_LIT> ) ; } if ( BaseOp . getOpcode ( ) != <STR_LIT> ) return false ; SDValue JT = BaseOp . getOperand ( <NUM_LIT> ) ; const SDNode * N = JT . getNode ( ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned I = cast < JumpTableSDNode > ( N ) -> getIndex ( ) ; const MachineJumpTableInfo * JTInfo = CurDAG -> getMachineFunction ( ) . getJumpTableInfo ( ) ; auto Size = JTInfo -> getJumpTables ( ) [ I ] . MBBs . size ( ) ; if ( Size >= <NUM_LIT> ) Size = <NUM_LIT> ; Count = CurDAG -> getTargetConstant ( Size , <STR_LIT> ) ; Index = IndexReg ; Base =


( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI


<s> unsigned int i ; state = data ; if ( REG_P ( x ) ) for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS ( REGNO ( x ) , GET_MODE ( x ) ) ; i ++ ) { state -> last_set [ REGNO ( x ) +


<s> static bool ExpandMOVImmSExti8 ( MachineInstrBuilder & MIB , const TargetInstrInfo & TII , const <ISA_LIT>Subtarget & Subtarget ) { MachineBasicBlock & MBB = * MIB -> getParent ( ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; int64_t Imm = MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Imm != <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; int StackAdjustment ; if ( Subtarget . is64Bit ( ) ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> || MIB -> getOpcode ( ) == <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getUsesRedZone ( ) ) { MIB -> setDesc ( TII . get ( MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( )


<s> if ( ! AddOp1 ) return SDValue ( ) ; bool HasLEAPotential = false ; for ( auto * User : Ext -> uses ( ) ) { if ( User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> ) { HasLEAPotential = true ; break ; } } if ( ! HasLEAPotential ) return SDValue ( ) ; int64_t AddConstant = Sext ? AddOp1 -> getSExtValue ( ) : AddOp1 -> getZExtValue ( ) ; SDValue AddOp0 = Add . getOperand ( <NUM_LIT> ) ; SDValue NewExt = DAG . getNode ( Ext -> getOpcode ( ) , SDLoc ( Ext ) , VT , AddOp0 ) ; SDValue NewConstant = DAG . getConstant ( AddConstant , SDLoc ( Add ) , VT ) ; SDNodeFlags Flags


<s> bitmap_xor ( cpu_isa , cpu_isa , target -> isa ) ; bitmap_and_compl ( cpu_isa , cpu_isa , isa_quirkbits ) ; bitmap_and_compl ( cpu_isa , cpu_isa , isa_all_fpubits ) ; if ( ! bitmap_empty_p ( cpu_isa ) ) { if ( warn_compatible ) warning ( <NUM_LIT> , <STR_LIT> , arm_selected_cpu -> name , arm_selected_arch -> name ) ; if ( ! arm_selected_tune ) arm_selected_tune = arm_selected_cpu ; arm_selected_cpu = arm_selected_arch ; target -> arch_name = arm_selected_arch -> name ; } else { arm_selected_arch = NULL ; target -> core_name = arm_selected_cpu -> name ; } } else { arm_selected_cpu = arm_selected_arch ; target -> arch_name = arm_selected_arch -> name ; } } else if ( arm_selected_cpu ) { target -> core_name = arm_selected_cpu -> name ; arm_initialize_isa ( target -> isa , arm_selected_cpu -> isa_bits ) ; } else { const struct processors * sel ; auto_sbitmap sought_isa ( isa_num_bits ) ; bitmap_clear ( sought_isa ) ; auto_sbitmap default_isa ( isa_num_bits ) ; arm_selected_cpu = & all_cores [ TARGET_CPU_DEFAULT ] ; gcc_assert ( arm_selected_cpu -> name ) ; sel = arm_selected_cpu ; arm_initialize_isa ( default_isa , sel -> isa_bits ) ; if ( TARGET_INTERWORK || TARGET_THUMB ) { bitmap_set_bit ( sought_isa , isa_bit_thumb ) ; bitmap_set_bit ( sought_isa , isa_bit_mode32 ) ; bitmap_clear_bit ( default_isa , isa_bit_mode26 ) ; } if ( ! bitmap_empty_p ( sought_isa ) && ! bitmap_subset_p ( sought_isa , default_isa ) ) { auto_sbitmap candidate_isa ( isa_num_bits ) ; bitmap_ior ( default_isa , default_isa , sought_isa ) ; for ( sel = all_cores ; sel -> name != NULL ; sel ++ ) { arm_initialize_isa ( candidate_isa , sel -> isa_bits ) ; if ( bitmap_equal_p ( default_isa , candidate_isa ) ) break ; } if ( sel -> name == NULL ) { unsigned current_bit_count = isa_num_bits ; const struct processors * best_fit = NULL ; for ( sel = all_cores ; sel -> name != NULL ;


<s> gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > <NUM_LIT> && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , StringRef FS ) { bool VectorABI = UsesVectorABI ( CPU , FS ) ; std :: string Ret ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( VectorABI || TT . isOSzOS ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT>


<s> void <ISA_LIT>SEInstrInfo :: loadRegFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC )


<s> static __inline void __attribute__ ( ( __always_inline__ )


<s> Relaxable . clear ( ) ; if ( FirstChangedFragment ) { Layout . invalidateFragmentsFrom ( FirstChangedFragment ) ; } if ( F . getKind ( ) == MCFragment :: FT_BoundaryAlign ) cast < MCBoundaryAlignFragment > ( F ) . setSize ( RemainingSize ) ; const uint64_t FinalOffset = Layout . getFragmentOffset ( & F ) ; const uint64_t FinalSize = Asm . computeFragmentSize ( Layout , F ) ; assert ( OrigOffset + OrigSize == FinalOffset + FinalSize && <STR_LIT> ) ; assert ( FinalSize == RemainingSize && <STR_LIT> ) ; if ( auto * BF = dyn_cast < MCBoundaryAlignFragment > ( & F ) ) { const MCFragment * LastFragment = BF -> getLastFragment ( ) ; if ( ! LastFragment ) continue ; while ( & * I != LastFragment ) ++ I ; } } } for ( unsigned int i = <NUM_LIT> , n = Layout . getSectionOrder ( ) . size ( ) ; i != n ; ++ i ) { MCSection & Section = * Layout . getSectionOrder ( ) [ i ] ; Layout . getFragmentOffset ( & * Section . getFragmentList


<s> SDLoc DL ( Op ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = getSETCC ( <STR_LIT> , EFLAGS , DL , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , EFLAGS . getValue ( <NUM_LIT> ) ) ; return SDValue (


<s> for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { DebugLoc dl = I -> getDebugLoc ( ) ; MachineInstr * MI = I ; if ( MI -> getFlag ( MachineInstr :: FrameSetup ) ) continue ; bool isControlFlow = MI -> isCall ( ) || MI -> isReturn ( ) ; if ( ! isControlFlow && CurState == ST_DIRTY ) continue ; if ( hasYmmReg ( MI ) ) { CurState = ST_DIRTY ; continue ; } if ( ! isControlFlow ) continue ; BBHasCall = true ; if ( CurState == ST_DIRTY ) { if ( EntryState != ST_UNKNOWN ) { BuildMI ( BB , I , dl , TII -> get ( <STR_LIT> ) ) ; ++ NumVZU ; } CurState = ST_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << BBNum << <STR_LIT> <<


<s> static inline unsigned decodeRd ( uint32_t insn ) { return ( insn >> <STR_LIT>


<s> <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry ( <NUM_LIT> , NULL ) ; m_GOTPLT . push_back ( entry ) ; return entry


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl ,

DAG . getEntryNode ( ) , FrameAddr , NULL , <NUM_LIT> ) ;


<s> bool hasRASv8_4 ( ) const { return HasRASv8_4


<s> SDLoc dl ( N ) ; MVT IntScalar = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT IntVT = <STR_LIT> ( IntScalar , VT . getVectorNumElements ( ) ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; } SDValue IntOp = DAG . getNode ( IntOpcode , dl , IntVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IntOp ) ; } return SDValue (


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg


<s> assert ( InstMaskEnd >= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { Base , V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart - <NUM_LIT> , dl ) , getI32Imm ( InstMaskEnd - <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { Base , V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart ; unsigned RLAmt1 = ( <NUM_LIT> + RLAmt - RLAmt2 ) % <NUM_LIT> ; if ( RLAmt1 ) V = SelectRotMask64 ( V , dl , RLAmt1 , false , <NUM_LIT> , <NUM_LIT> ) ; return SelectRotMaskIns64 ( Base , V , dl , RLAmt2 , false , MaskStart


<s> if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return


<s> if ( ! Root . getParent ( ) -> getParent ( ) ->

getTarget ( ) . Options . UnsafeFPMath ) return false ;


<s> static SDValue PerformLOADCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; bool IsAligned = Alignment == <NUM_LIT> || Alignment >= MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue (


<s> cfun -> machine -> next_fcc += - cfun -> machine -> next_fcc & ( count - <NUM_LIT> ) ; if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = <NUM_LIT> ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ; cfun -> machine ->


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T , OSABI , CPU


<s> bool FixupLEAPass :: processBasicBlock ( MachineFunction & MF , MachineFunction :: iterator MFI ) { for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I != MFI -> end ( ) ; ++ I ) { if ( OptIncDec ) if ( fixupIncDec ( I , MFI ) ) continue ; if ( OptLEA )


<s> if ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) { if ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) RegIdx = <NUM_LIT> ; if ( static_cast < <ISA_LIT>Operand * > ( Operands [ RegIdx ] ) -> isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( static_cast < <ISA_LIT>Operand * > ( Operands [ RegIdx ] ) -> getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains

( static_cast < <ISA_LIT>Operand * > ( Operands [ RegIdx ] ) -> getReg ( ) ) ) ) return true ;


DarwinCalleeSavedRegs : CalleeSavedRegs ;