<s> getStreamer ( ) . emitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( GPReg ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( GPReg ) ) ; const MCExpr * LoSym = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_None , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( LoSym ) ) ; getStreamer ( ) . emitInstruction ( TmpInst , STI ) ; TmpInst . clear


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: mips || TT . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU =


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_None : case VK_<ISA_LIT>_ADDR : return <STR_LIT> ; case VK_<ISA_LIT>_ADDR_HI16 : return <STR_LIT> ; case VK_<ISA_LIT>_ADDR_LO16 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_IMM18_BY4 : case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_IMM18_BY4 : case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TLSLE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSIE : return <STR_LIT>


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB )

Changed |= CompressEvexToVexImpl ( MI ) ;


<s> if ( V1 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; } if ( V1 . getOpcode ( ) == <STR_LIT> ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) if ( V1 . getOperand ( i ) . getOpcode ( ) != <STR_LIT> && i != ( unsigned ) Lane ) { IsScalarToVector = false ; break ; } if ( IsScalarToVector ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( Lane ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , V1 , DAG . getConstant ( Lane , <STR_LIT> ) ) ; } int Length = ShuffleMask . size ( ) ; int V1EltNum = V1 . getValueType ( ) . getVectorNumElements ( ) ; if ( V1EltNum == Length ) { bool IsSequential = true ; int CurMask = ShuffleMask [ <NUM_LIT> ] ; for ( int I = <NUM_LIT> ; I < Length ; ++ I ) { if ( ShuffleMask [ I ] != CurMask ) { IsSequential = false ; break ; } CurMask ++ ; } if ( IsSequential ) { assert ( ( EltSize % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned VecSize = EltSize * V1EltNum ; unsigned Index = ( EltSize / <NUM_LIT> ) * ShuffleMask [ <NUM_LIT> ] ; if ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Index , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > NV1Elt ; SmallVector < int , <NUM_LIT> > N1Index ; SmallVector < int , <NUM_LIT> > NV2Elt ; SmallVector < int , <NUM_LIT> > N2Index ; for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != I ) { NV1Elt . push_back ( ShuffleMask [ I ] ) ; N1Index . push_back ( I ) ; } } for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != ( I + V1EltNum ) ) { NV2Elt . push_back ( ShuffleMask [


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = MBB ; ++ I ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( RC -> hasType ( <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg

( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ;


<s> return ( __mmask16 ) __builtin_ia32_kortestchi ( ( __mmask16 ) __A ,


<s> raw_svector_ostream ( Name ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Printer . MF -> getContext ( ) . GetOrCreateSymbol ( Name .


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG .

getEntryNode ( ) , FrameAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsr_u32 ( unsigned int __X ) { return __blsr_u32 (


<s> uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> static void core2i7_first_cycle_multipass_issue ( void * _data , signed char * ready_try , int n_ready , rtx_insn * insn , const void * _prev_data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; const_ix86_first_cycle_multipass_data_t prev_data = ( const_ix86_first_cycle_multipass_data_t ) _prev_data ; int insn_size = ix86_min_insn_size ( insn ) ; data -> ifetch_block_len = prev_data -> ifetch_block_len + insn_size ; data -> ifetch_block_n_insns = prev_data -> ifetch_block_n_insns + <NUM_LIT> ; gcc_assert ( data -> ifetch_block_len <= core2i7_ifetch_block_size && data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; if ( ! data -> ready_try_change ) { data -> ready_try_change = sbitmap_alloc


<s> if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - <NUM_LIT> ; emit_insn ( gen_andqi3 ( tag , tag , GEN_INT ( and_imm ) ) ) ; } tag = expand_simple_binop ( Pmode , ASHIFT , tag , GEN_INT ( IX86_HWASAN_SHIFT ) , NULL_RTX


<s> if ( regno < <NUM_LIT> ) return LO_REGS ; return HI_REGS ; } if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GENERAL_REGS ; if ( regno == CC_REGNUM ||

regno == VFPCC_REGNUM ) return NO_REGS ;


<s> return getTM < <ISA_LIT>TargetMachine >


<s> return __builtin_ia32_aesdecwide256kl_u8 ( ( __v2di * ) __A , (


<s> Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII ,


<s> unsigned Alignment = LN -> getAlignment ( ) ; if ( Alignment >= MemVT . getStoreSize ( ) ) return Op ; EVT ScalarVT = Op . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Vals [ <NUM_LIT> ] , LoadChains [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Load ; if ( ScalarVT != ScalarMemVT ) Load = DAG . getExtLoad ( LN -> getExtensionType ( ) , dl , ScalarVT , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> isInvariant ( ) , MinAlign ( Alignment , Idx * Stride ) , LN -> getAAInfo ( ) ) ; else Load = DAG . getLoad ( ScalarVT , dl , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> isInvariant ( ) , MinAlign ( Alignment , Idx * Stride ) , LN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && LN -> isIndexed ( ) ) { assert ( LN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Load = DAG . getIndexedLoad ( Load , dl , BasePtr , LN -> getOffset ( ) , LN -> getAddressingMode ( ) ) ; } Vals [ Idx ] = Load ; LoadChains [ Idx ] = Load . getValue (


<s> void <ISA_LIT>InstPrinter :: printMSRSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val


<s> addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; } computeRegisterProperties ( ) ; setShiftAmountType ( <STR_LIT> ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: RegPressure ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> rtx_insn * sh_treg_combine :: make_inv_ccreg_insn ( void ) const { start_sequence ( ) ; rtx_insn * i = emit_insn ( gen_rtx_SET ( m_ccreg , gen_rtx_fmt_ee ( XOR , GET_MODE ( m_ccreg )


<s> bool ComplexPatternFuncMutatesDAG ( ) const override { return true


<s> const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVLX ( ) && Super -> getSize (


<s> tree arg0 ; enum machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_altivec_lvx_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_altivec_lvx_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_altivec_lvx_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_altivec_lvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg (


<s> bool hasFPUv2DoubleFloat ( ) const { return HasFPUv2DoubleFloat


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> bool ia64_can_eliminate ( const int from ATTRIBUTE_UNUSED


<s> unsigned Imm16 = FullImm & <NUM_LIT> ; unsigned Shift = FullImm >> <NUM_LIT> ; if ( RegWidth == <NUM_LIT> && Shift > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( Imm16 ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Shift )


<s> bool <ISA_LIT>TargetLowering :: IsInSmallSection ( unsigned


<s> static DecodeStatus DecodeFPRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> )


<s> return isLegalMaskedLoadStore ( DataType , Alignment


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI


<s> for ( int i = <NUM_LIT> ; i != NumElts / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , <NUM_LIT> ) ) return false ; for ( int i = NumElts / <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , NumElts / <NUM_LIT> ) ) return false ; return true


<s> } if ( CONSTANT_P ( address ) || LABEL_P ( address ) ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( CONST_INT_P ( XEXP ( address , <NUM_LIT> ) ) ) ; offset = INTVAL ( XEXP ( address , <NUM_LIT> ) ) ; address = XEXP ( address , <NUM_LIT> ) ; } else offset = <NUM_LIT> ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , <NUM_LIT> ) ; gcc_assert ( REG_P ( address ) ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( <STR_LIT> , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( <STR_LIT> , file ) ; if ( offset != <NUM_LIT> ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file )


<s> bool IsFPSetCC = CmpOpVT . isFloatingPoint ( ) && CmpOpVT != <STR_LIT> ; return ! IsFPSetCC || ! Subtarget . isTarget64BitLP64 ( ) || ! Subtarget


<s> bool is32BitMode ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> unsigned int align ; unsigned int parm_offset ; align = function_arg_boundary ( mode , type ) / PARM_BOUNDARY - <NUM_LIT> ; parm_offset = DEFAULT_ABI == ABI_V4 ? <NUM_LIT>


<s> unsigned NumElts = SrcVT . getVectorNumElements ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; SDValue Mid , SplitLo , SplitHi , ExtLo , ExtHi ; EVT MidVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts ) ; EVT SplitVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts / <NUM_LIT> ) ; EVT ExtVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , DestEltSize ) , NumElts / <NUM_LIT> ) ; Mid = DAG . getNode ( N -> getOpcode ( ) , dl , MidVT , Op ) ; SplitLo = DAG . getNode ( <STR_LIT> , dl , SplitVT , Mid , DAG . getIntPtrConstant ( <NUM_LIT>


<s> if ( ! isInt < <NUM_LIT> > ( Addr . getOffset ( ) ) ) { unsigned TempReg = materialize32BitInt ( Addr . getOffset ( ) , & <STR_LIT> ) ; Register DestReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addReg ( Addr . getReg ( ) ) ; Addr . setReg (


<s> if ( AM . BaseType == <STR_LIT> ) MIB . addReg ( AM . Base . Reg ) ; else if ( AM . BaseType == <STR_LIT> ) MIB . addFrameIndex ( AM . Base . FrameIndex ) ; else assert ( <NUM_LIT> ) ; MIB . addImm ( AM . Scale ) . addReg ( AM . IndexReg ) ; if ( AM . GV ) return MIB . addGlobalAddress ( AM . GV , AM .


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16RegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16ZeroRegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; } if ( DecodeGPRMM16RegisterClass ( Inst , Base , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : if ( Offset == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset << <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset << <NUM_LIT> ) ) ; break ; } return MCDisassembler


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR3 ( ( v8qi ) mm , ( v8qi


<s> static DecodeStatus DecodeSPERCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser (


<s> vmlsq_u16 ( uint16x8_t a , uint16x8_t b , uint16x8_t c ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> void printi32mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> void emitARM64WinCFISaveLRPair ( unsigned Reg , int Offset )


<s> void <ISA_LIT>ELFStreamer :: EmitHandlerData ( ) { FlushUnwindOpcodes (


<s> if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <=


<s> return ( __m128 ) __builtin_ia32_movlhps ( ( __v4sf ) __A ,


<s> LastCommutableVecOp ++ ; } else if ( IsIntrinsic ) { FirstCommutableVecOp = <NUM_LIT> ; } if ( isMem ( MI , LastCommutableVecOp ) ) LastCommutableVecOp -- ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = LastCommutableVecOp ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; Register Op2Reg = MI . getOperand ( CommutableOpIdx2 ) . getReg ( ) ; unsigned CommutableOpIdx1 ; for ( CommutableOpIdx1 = LastCommutableVecOp ; CommutableOpIdx1 >= FirstCommutableVecOp ; CommutableOpIdx1 -- ) { if ( CommutableOpIdx1 == KMaskOp ) continue ; if ( Op2Reg != MI . getOperand ( CommutableOpIdx1 ) . getReg ( ) ) break ; } if ( CommutableOpIdx1 < FirstCommutableVecOp ) return


<s> int reg ; static int next_fcc_reg = <NUM_LIT> ; static rtx prev_args [ <NUM_LIT> ] [ <NUM_LIT> ] ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( prev_args [ reg ] [ <NUM_LIT> ] == x && prev_args [ reg ] [ <NUM_LIT> ] == y ) break ; if ( reg == <NUM_LIT> ) { reg = next_fcc_reg ; prev_args [ reg ] [ <NUM_LIT> ] = x ; prev_args [ reg ] [ <NUM_LIT> ] = y ; next_fcc_reg = ( next_fcc_reg + <NUM_LIT> ) & <NUM_LIT> ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return ( __m128i ) __builtin_ia32_vpcomltuw ( ( __v8hi


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; assert ( ! ArchFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; std :: string CPUName = std :: string (


<s> return ( __m512i ) __builtin_ia32_cvtpd2uqq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 ) -


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getMcpu ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode =


<s> unsigned ShiftCountMask = ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI -> getOperand ( ShiftAmtOperandIdx ) . getImm ( ) ; return Imm &


<s> unsigned OffsetInBytes = <NUM_LIT> ; unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; Align Alignment = std :: min ( Flags . getNonZeroByValAlign ( ) , Align ( RegSizeInBytes ) ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment . value ( ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes

/ <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ;


<s> int Imm ; unsigned Opc ; <STR_LIT> Cmp ; std :: tie ( Imm , Opc , Cmp ) = Info ; MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ; MachineInstr * BrMI = MBB -> getFirstTerminator ( ) ; BuildMI ( * MBB , BrMI , BrMI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( Cmp ) . addOperand ( BrMI -> getOperand ( <NUM_LIT> ) ) ; BrMI -> eraseFromParent ( ) ; MBB -> updateTerminator (


<s> bool isUnaryOperator ( const InfixCalculatorTok Op ) { return Op == IC_NEG


<s> static bool CC_<ISA_LIT>O32_FP32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign ::

LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) {


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( Register MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( ) ) Ref . Def = true ; } } } } return Ref


<s> if ( getUnderlyingObjects ( MI , Objs ) ) { for ( ValueType VT : Objs ) HasHazard |= updateDefsUses ( VT , MI . mayStore ( ) ) ; return HasHazard ; } HasHazard = MI . mayStore ( ) && ( OrigSeenLoad || OrigSeenStore ) ; HasHazard |= MI . mayLoad ( ) || OrigSeenStore ; SeenNoObjLoad |= MI . mayLoad (


<s> x . s [ <NUM_LIT> ] = s ; return ( x .


<s> F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } unsigned MOVOpc = Subtarget -> hasAVX ( )


<s> case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } const bool IsWrite = MII . get ( Inst . getOpcode ( ) ) . mayStore ( ) ; for ( unsigned Ix = <NUM_LIT> ; Ix < Operands . size ( ) ; ++


<s> MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr


<s> return ( int32x2_t ) __builtin_neon_vqnegv2si (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( <STR_LIT> ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp2Reg ) . addReg ( TmpDestReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp3Reg ) . addReg ( TmpReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp4Reg ) . addReg ( Tmp3Reg ) . addReg ( Tmp2Reg ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( Tmp4Reg ) . addReg ( <STR_LIT> ) . addReg ( PtrReg ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB


<s> ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o


<s> } else if ( RegSpc == SingleHighTSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT>


<s> MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsDwarfCFI = ! IsWin64Prologue && ( MF . getMMI ( ) . hasDebugInfo ( ) || MF .

getFunction ( ) . needsUnwindTableEntry ( ) ) ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ; assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return splitVectorIntBinary ( Op , DAG


<s> assert ( ! Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; O << <STR_LIT> << * JTISymbol << <STR_LIT> ; const char * JTEntryDirective = MAI -> getData32bitsDirective ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT =


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> return ( __m128 ) __builtin_ia32_cmpunordss ( ( __v4sf ) __A , ( __v4sf )


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , DAG , Subtarget , IsFadd ) ) return DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ; return SDValue (


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this

-> Options . FloatABIType = FloatABI :: Soft ;


<s> return MatchOperand_Success ; } Index = matchMSA128RegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128CtrlRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } return MatchOperand_NoMatch


<s> else if ( GET_CODE ( addr ) == PLUS ) { rtx addends [ <NUM_LIT> ] , op ; int n = <NUM_LIT> , i ; op = addr ; do { if ( n >= <NUM_LIT> ) return <NUM_LIT> ; addends [ n ++ ] = XEXP ( op , <NUM_LIT> ) ; op = XEXP ( op , <NUM_LIT> ) ; } while ( GET_CODE ( op ) == PLUS ) ; if ( n >= <NUM_LIT> ) return <NUM_LIT> ; addends [ n ] = op ; for ( i = n ; i >= <NUM_LIT> ; -- i ) { op = addends [ i ] ; switch ( GET_CODE ( op ) ) { case MULT : if ( index ) return <NUM_LIT> ; index = XEXP ( op , <NUM_LIT> ) ; scale_rtx = XEXP ( op , <NUM_LIT> ) ; break ; case ASHIFT : if ( index ) return <NUM_LIT> ; index = XEXP ( op , <NUM_LIT> ) ; tmp = XEXP ( op , <NUM_LIT> ) ; if ( ! CONST_INT_P ( tmp ) ) return <NUM_LIT> ; scale = INTVAL ( tmp ) ; if ( ( unsigned HOST_WIDE_INT ) scale > <NUM_LIT> ) return <NUM_LIT> ; scale = <NUM_LIT> << scale ; break ; case ZERO_EXTEND : op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != UNSPEC ) return <NUM_LIT> ; case UNSPEC : if ( XINT ( op , <NUM_LIT> ) == UNSPEC_TP && TARGET_TLS_DIRECT_SEG_REFS && seg == ADDR_SPACE_GENERIC ) seg = DEFAULT_TLS_SEG_REG ; else return <NUM_LIT> ; break ; case SUBREG : if ( ! REG_P ( SUBREG_REG ( op ) ) ) return <NUM_LIT> ; case REG : if ( ! base ) base = op ; else if ( ! index ) index = op ; else return


<s> if ( ! Sub ) return <NUM_LIT> ; const PtrToIntOperator * SubLHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return <NUM_LIT> ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return <NUM_LIT> ; const GlobalVariable * GVLHS = dyn_cast < GlobalVariable > ( SubLHS -> getPointerOperand ( ) ) ; const GlobalVariable * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GVLHS || !


<s> assert ( ( Binary & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned UBit = ( Binary


<s> return ( __m128 ) __builtin_ia32_cmpeqss ( ( __v4sf ) __A , (


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; bool ValidName ; std :: string Name = Mapper . toString ( MO . getImm ( ) , ValidName ) ; if ( ValidName ) { O <<


<s> const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool hasD32 = featureBits [ <STR_LIT> ] ; if ( RegNo > <NUM_LIT> || ( ! hasD32 && RegNo > <NUM_LIT> ) ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo


<s> void <ISA_LIT>WinCOFFStreamer :: FinishImpl ( ) { EmitFrames ( nullptr ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } bool WasThumb = isThumb ( ) ; Triple T


<s> void printlea32mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> int sparc_split_regreg_legitimate ( rtx reg1 , rtx reg2 ) { int regno1 , regno2 ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return <NUM_LIT> ; regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; regno2 = REGNO ( reg2


<s> return MatchOperand_ParseFail ; } int64_t LSB = CE -> getValue ( ) ; if ( LSB < <NUM_LIT> || LSB > <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; SMLoc EndLoc


<s> return <STR_LIT> ; case EQ : return <STR_LIT> ; case GE : return <STR_LIT> ; case GT : return <STR_LIT> ; case LE : return <STR_LIT> ; case LT : return <STR_LIT> ; case GEU : return <STR_LIT> ; case GTU : return <STR_LIT> ; case LEU


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc


<s> static unsigned getSETFromCond ( <STR_LIT> CC , bool HasMemoryOperand ) { static const unsigned Opc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; assert ( CC < <NUM_LIT> && <STR_LIT> ) ; return Opc [ CC ] [ HasMemoryOperand ? <NUM_LIT> :


<s> case <STR_LIT> : if ( InVT == <STR_LIT> && In . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return N -> getOperand ( <NUM_LIT> ) ; break ; } } if ( N -> getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . isUndef ( ) && isNullConstant ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue In = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Movl = DAG . getNode ( <STR_LIT> , dl , In . getValueType ( ) , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , dl ) , Movl , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; } if ( N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDVTList Tys = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , VT . getVectorElementType ( ) , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , MachineMemOperand :: MOLoad ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) ,


<s> if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags .


<s> using namespace <ISA_LIT> ; switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> expandLoadStackGuard ( MI ) ; MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI . RemoveOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsKill (


<s> unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize


<s> return new <ISA_LIT>_MC :: <ISA_LIT>MCInstrAnalysis ( Info


<s> static bool MayFoldLoad ( SDValue Op ) { return Op . hasOneUse ( ) && <STR_LIT> (


<s> return ( uint8x8_t ) __builtin_neon_vshl_nv8qi ( (


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned BaseOp = <NUM_LIT> ; unsigned CCValid = <NUM_LIT> ; unsigned CCMask = <NUM_LIT> ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ! isAddCarryChain ( Carry ) ) return SDValue ( ) ; BaseOp = <STR_LIT> ; CCValid = <STR_LIT> ; CCMask = <STR_LIT> ; break ; case <STR_LIT> : if ( ! isSubBorrowChain ( Carry ) ) return SDValue ( ) ; BaseOp = <STR_LIT> ; CCValid = <STR_LIT> ; CCMask = <STR_LIT> ; break ; } Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Carry , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT>


<s> return MF -> getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) && MF

-> getFunction ( ) . needsUnwindTableEntry ( ) ;


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; switch ( Opcode


<s> if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( <NUM_LIT> ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( TIP . first ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; } ThumbIndirectPads . clear


<s> if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; return ; } bool isSub = NumBytes < <NUM_LIT> ; if ( isSub ) NumBytes


<s> bool isMSA128WAsm ( ) const { return Kind == k_Register && Reg .


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success


<s> static MachineBasicBlock * EmitMonitor ( MachineInstr * MI , MachineBasicBlock * BB , const TargetInstrInfo * TII , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned MemOpc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps + <NUM_LIT> ) . getReg


<s> if ( ! SrcReg ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = emitIntExt ( SrcVT . getSimpleVT ( ) , SrcReg , <STR_LIT> , ! Signed ) ; if ( ! SrcReg ) return false ; } unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT ==


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; SpillSlotOffset -= SlotSize ; } Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; I . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; assert ( SpillSlotOffset < <NUM_LIT> && <STR_LIT> ) ; SpillSlotOffset = - alignTo (


<s> if ( ! arm_get_set_operands ( producer , consumer , & value , & addr ) ) return <NUM_LIT> ; return reg_overlap_mentioned_p ( value , addr


<s> } case <STR_LIT> : { Register Tmp = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachinePointerInfo MPO ; MIRBuilder . buildLoad ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; MIRBuilder . buildStore ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } default : break ; } return


<s> UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> hasStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset


<s> unsigned Register = DPairDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , Parser ( _Parser


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT

) return Op -> getOperand ( <NUM_LIT> ) ;


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVecShiftL64OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo


<s> static inline uint8_t encodeAdvSIMDModImmType1 ( uint64_t Imm )


<s> Value * Operand2 = getReg ( getRegOp ( <NUM_LIT> ) ) ; Value * OldPair = Builder . CreateAtomicCmpXchg ( PointerOperand , CmpVal , Operand2 , AtomicOrdering :: Monotonic , AtomicOrdering :: Monotonic ) ; Value * OldVal = Builder . CreateExtractValue ( OldPair , <NUM_LIT> ) ; Value * Success = Builder . CreateExtractValue ( OldPair , <NUM_LIT> ) ; setReg ( CmpReg , Builder . CreateSelect ( Success , CmpVal , OldVal ) ) ; Value * Result = Builder . CreateBinOp ( Instruction :: Sub , CmpVal , OldVal ) ; getParent ( ) . updateEFLAGS (


<s> Info . OneUser = false ; Info . MultiUsers = false ; Info . LastADRP =


<s> int FIOffset ; Register BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! needsStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) . getFixed ( ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) . getFixed ( ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } Register MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr


<s> StringRef AsmTokStr = Tok . getString ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOffsetOfOperator ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( <ISA_LIT>Operand * Err = ParseIntelExpression ( SM , End ) ) return Err ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Idx1 = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , Idx0 , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , Idx1 , DAG


<s> else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I32 : RTLIB :: UDIV_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I64 : RTLIB :: UDIV_I64 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SDIV_I128 : RTLIB :: UDIV_I128 ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; return <ISA_LIT>EmitLibcall ( I


<s> bool <ISA_LIT>InstrInfo :: isPreLdSt (


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : if ( Subtarget -> hasBWI ( ) ) return lowerV32I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; break ; case <STR_LIT> : if ( Subtarget -> hasBWI ( ) ) return lowerV64I8VectorShuffle ( Op , V1 ,


<s> for ( i = <NUM_LIT> ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target


<s> if ( ! IsConstantImm ) return false ; int uimm4 = Imm & <NUM_LIT> ; return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm )


<STR_LIT> ) , STI ( sti ) , BasePtr ( <STR_LIT> ) {


<s> mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> +


<s> SDLoc DL ( N ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N ,


<s> Value * <ISA_LIT>IREmitter :: visitVCLTZ ( const SDNode


<s> for ( unsigned i = <NUM_LIT> ; i < WideNumElts ; ++ i ) ShuffV . push_back ( i + WideNumElts ) ; int Stride = FourEltRes ? WideNumElts / <NUM_LIT> : WideNumElts / <NUM_LIT> ; int SaveElts = FourEltRes ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . isLittleEndian ( ) ) for ( int i = <NUM_LIT> ; i < SaveElts ; i ++ ) ShuffV [ i * Stride ] = i ; else for ( int i = <NUM_LIT> ; i <= SaveElts ; i ++ ) ShuffV [ i * Stride - <NUM_LIT> ] = i - <NUM_LIT> ; SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; SDValue Arrange = DAG . getVectorShuffle ( WideVT , dl , Wide , ShuffleSrc2 , ShuffV ) ; SDValue Extend ; if ( SignedConv ) { Arrange = DAG . getBitcast ( IntermediateVT , Arrange ) ; EVT ExtVT = Src . getValueType ( ) ; if ( Subtarget . hasP9Altivec ( ) ) ExtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WideVT . getVectorElementType ( ) , IntermediateVT . getVectorNumElements ( ) ) ; Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT , Arrange , DAG . getValueType (


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; SDValue Part0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Part1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part0 , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part1 , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > (


<s> case Match_SImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_N1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm7_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm11_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm16 : case Match_SImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm19_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm20_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm26_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm32 : case Match_SImm32_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm32_Coerced : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm9 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm10 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) ,


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & Loc = MI . getDebugLoc (


<s> rtx arm_gen_load_multiple ( int * regs , int count , rtx basereg ,

int write_back , rtx basemem , HOST_WIDE_INT * offsetp ) {


<s> case Instruction :: FRem : case Instruction :: FPToUI : case Instruction :: FPToSI : case Instruction :: UIToFP : case Instruction :: SIToFP : case Instruction :: FPTrunc : case Instruction :: FPExt : case Instruction :: FCmp : return true ; default : ; } if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Function & F_ = * CI -> getCalledFunction ( ) ; if ( needsFPFromSig ( F_ ) ) return true ; } } return false


<s> EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> )


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction


<s> int DataWidth = ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= <NUM_LIT> &&


<s> if ( needsAggressiveScheduling ( DarwinDirective ) ) { Policy . OnlyTopDown =


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1

, V2 , Mask , Subtarget , DAG ) ) return Blend ;


<s> Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , <STR_LIT> ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = <NUM_LIT>


<s> return ( * registered_functions ) [ code ]


<s> const MCOperand & MemOffsetOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( MemOffsetOp . isImm ( ) || MemOffsetOp . isExpr ( ) ) && <STR_LIT> ) ; unsigned OpCode = <NUM_LIT> ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : OpCode = <STR_LIT> ; break ; case <STR_LIT> : OpCode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } int64_t ImmValue = ImmOp . getImm ( ) ; if ( ImmValue == <NUM_LIT> ) emitRRX ( OpCode , DstRegOp . getReg ( ) , <STR_LIT> , MemOffsetOp , IDLoc , Instructions ) ; else { warnIfNoMacro ( IDLoc ) ; unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , ! isGP64bit ( ) , true , IDLoc , Instructions ) ) return true ; emitRRX ( OpCode , DstRegOp . getReg ( ) , ATReg , MemOffsetOp , IDLoc , Instructions


<s> for ( auto & MBB : * MF ) splitMBB ( & MBB ) ; MF -> RenumberBlocks ( ) ; MBBInfos . clear ( ) ; MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I


<s> void addImm1_32Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> if ( N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue N0 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpcode = N0 . getOpcode ( ) ; if ( TLI . isBinOp ( SrcOpcode ) && N1 . getOpcode ( ) == SrcOpcode && IsSafeToMoveShuffle ( N0 , SrcOpcode ) && IsSafeToMoveShuffle ( N1 , SrcOpcode ) ) { SDValue Op00 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op10 = peekThroughOneUseBitcasts ( N1 . getOperand ( <NUM_LIT> ) ) ; SDValue Op01 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op11 = peekThroughOneUseBitcasts ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ( ( IsMergeableWithShuffle ( Op00 ) && IsMergeableWithShuffle ( Op10 ) ) || ( IsMergeableWithShuffle ( Op01 ) && IsMergeableWithShuffle ( Op11 ) ) ) || ( ( IsMergeableWithShuffle ( Op00 ) || IsMergeableWithShuffle ( Op10 ) ) && ( IsMergeableWithShuffle ( Op01 ) || IsMergeableWithShuffle ( Op11 ) ) ) ) { SDValue LHS , RHS ; Op00 = DAG . getBitcast ( ShuffleVT , Op00 ) ; Op10 = DAG . getBitcast ( ShuffleVT , Op10 ) ; Op01 = DAG . getBitcast ( ShuffleVT , Op01 ) ; Op11 = DAG . getBitcast ( ShuffleVT , Op11 ) ; if ( N . getNumOperands ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 , Op10 , N . getOperand ( <NUM_LIT> ) ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 , Op11 , N . getOperand ( <NUM_LIT> ) ) ; } else { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 , Op10 ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 , Op11 ) ; } EVT OpVT = N0 .


<s> if ( isa < const InsertValueInst > ( Instr ) && OpIdx > <NUM_LIT> ) return false ; if ( isa < const AllocaInst > ( Instr ) && OpIdx > <NUM_LIT> ) return false ; if ( isa < const LoadInst > ( Instr ) && OpIdx > <NUM_LIT> ) return false ; if ( isa < const StoreInst > ( Instr ) && OpIdx > <NUM_LIT> ) return false ; if ( isa < const GetElementPtrInst > ( Instr ) && OpIdx > <NUM_LIT> ) return false ; if ( isa < const LandingPadInst > ( Instr ) ) return false ; if ( isa < const SwitchInst > ( Instr ) ) return false ; if ( isa < const IndirectBrInst > ( Instr ) ) return false ; if ( isa < const IntrinsicInst > ( Instr ) ) return false ; const CallInst * CI = dyn_cast < const


<s> if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target (


<s> bool NZCVKilled = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; if ( ! NZCVKilled ) { TrueBB -> addLiveIn ( <STR_LIT> ) ; EndBB -> addLiveIn (


<s> if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( mode ) ) { if ( GET_MODE_SIZE ( inner_mode ) == <NUM_LIT> ) { emit_move_insn ( gen_lowpart ( SImode , target ) , gen_lowpart ( SImode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; } else if ( GET_MODE_SIZE ( inner_mode ) == <NUM_LIT> ) { emit_move_insn ( gen_lowpart ( DImode , target ) , gen_lowpart ( DImode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; } } else if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( word_mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> * GET_MODE_SIZE ( word_mode ) ) { emit_move_insn ( gen_highpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; emit_move_insn ( gen_lowpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; } if ( all_same && GET_MODE_SIZE ( mode


<s> return ( float32x2_t ) __builtin_neon_vrsqrtev2sf


<s> Move . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Move . addOperand ( MCOperand :: CreateReg ( ToReg ) ) ; Move . addOperand ( MCOperand :: CreateReg ( FromReg ) ) ; Out . EmitInstruction (


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT>


<s> return ( __m512 ) __builtin_ia32_getexpps512_mask ( ( __v16sf ) __A , ( __v16sf )

_mm512_setzero_ps ( ) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> int Case = getThreeSrcCommuteCase ( TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; if ( Case < <NUM_LIT> ) return false ; static const uint8_t SwapMasks [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; uint8_t Imm = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; uint8_t NewImm = Imm & ~ ( SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] ) ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ]


<s> break ; } case <STR_LIT> : { auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm


<s> if ( transformBitcast ( Bitcast ) ) DeadInsts . push_back ( Bitcast ) ; continue ; } combineLoadBitcast ( LD , Bitcast ) ; DeadInsts . push_back ( Bitcast ) ; if ( LD -> hasOneUse ( ) ) DeadInsts . push_back ( LD ) ; } else if ( Src -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { if ( Bitcast -> user_empty ( ) ) { DeadInsts . push_back ( Bitcast ) ; continue ; } StoreInst * ST = nullptr ; for ( auto UI = Bitcast -> use_begin ( ) , UE = Bitcast -> use_end ( ) ; UI != UE


<s> if ( prologue ) fputs ( <STR_LIT> , f ) ; else { if ( ! ( flag_unwind_tables || crtl -> uses_eh_lsda ) && ( TREE_NOTHROW ( current_function_decl ) || crtl -> all_throwers_are_sibcalls ) ) fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> ,


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> )


<s> MachineInstr * MI = Arguments -> MI ; const ReduceEntry & Entry = Arguments -> Entry ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI , Entry


<s> emit_note ( NOTE_INSN_DELETED ) ; rs6000_emit_prologue ( ) ; emit_note ( NOTE_INSN_DELETED ) ; { rtx insn ; unsigned addr = <NUM_LIT> ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = NEXT_INSN ( insn ) ) { INSN_ADDRESSES_NEW ( insn , addr ) ; addr += <NUM_LIT> ; } } if ( TARGET_DEBUG_STACK ) debug_rtx_list ( get_insns ( ) , <NUM_LIT> ) ; final ( get_insns ( ) , file , FALSE ) ; end_sequence ( ) ; } rs6000_pic_labelno ++


<s> const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . in<ISA_LIT>16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { if ( IsInstrVSel ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , TM , LowGPR , false ) ; addSavedGPR ( MBB , MIB , TM , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , TM , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , TM , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CSI [ I ] . getFrameIdx ( ) ,


<s> static int mep_multiple_address_regions ( tree list , bool check_section_attr ) { tree a ; int count_sections = <NUM_LIT> ; int section_attr_count = <NUM_LIT> ; for ( a = list ; a ; a = TREE_CHAIN


<s> return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : <NUM_LIT> ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : <NUM_LIT> ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : <NUM_LIT> ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM )


<s> static int matchShuffleAsRotate ( SDValue & V1 , SDValue & V2 , ArrayRef < int > Mask ) { int NumElts = Mask . size ( ) ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { int M = Mask [ i ] ; assert ( ( M == SM_SentinelUndef || ( <NUM_LIT> <= M && M < ( <NUM_LIT> * NumElts ) ) ) && <STR_LIT> ) ; if ( M < <NUM_LIT> ) continue ; int StartIdx = i - ( M % NumElts ) ; if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; SDValue MaskV = M < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return - <NUM_LIT> ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; V1 = Lo ; V2 =


<s> if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI .


<s> bool <ISA_LIT>LongBranch :: mustRelaxBranch ( const TerminatorInfo & Terminator , uint64_t Address ) { if ( ! Terminator . Branch || Terminator . ExtraRelaxSize == <NUM_LIT> ) return false ; const MBBInfo & Target = MBBs [ Terminator . TargetBlock ] ; if ( Address >= Target . Address ) { if ( Address - Target . Address <= MaxBackwardRange ) return false ; } else { if ( Target . Address - Address <= MaxForwardRange ) return false ; } return


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) &&


<s> len = <NUM_LIT> ; for ( m = <NUM_LIT> ; m < NUM_MACHINE_MODES ; ++ m ) if ( rs6000_hard_regno_mode_ok_p [ m ] [ r ] && rs6000_hard_regno_nregs [ m ] [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } if ( rs6000_hard_regno_nregs [ m ] [ r ] > <NUM_LIT> ) len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) , rs6000_hard_regno_nregs [ m ] [ r ] ) ; else len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) ) ; comma = <STR_LIT> ; } if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerSTACKMAP ( MCStreamer & OutStreamer , StackMaps & SM , const MachineInstr & MI ) { unsigned NumNOPBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SM . recordStackMap ( MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> &&


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return create<ISA_LIT>XCOFFStreamer ( Context , std :: move ( MAB ) , std ::

move ( OW ) , std :: move ( Emitter ) ) ;


<s> far = <NUM_LIT> ; jump = <STR_LIT> <STR_LIT> <STR_LIT> ; } else { far = <NUM_LIT> ; if ( flag_pic ) { if ( TARGET_SH2 ) jump = <STR_LIT> <STR_LIT> <STR_LIT> ; else jump = <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ; } else jump = <STR_LIT> <STR_LIT> <STR_LIT> ; } if ( NONJUMP_INSN_P ( ( prev = prev_nonnote_insn ( insn ) ) ) && INSN_CODE ( prev ) == CODE_FOR_indirect_jump_scratch ) { this_jmp . reg = SET_DEST ( XVECEXP ( PATTERN ( prev ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( REGNO ( this_jmp . reg ) == R0_REG && flag_pic && ! TARGET_SH2 ) jump = <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ; output_asm_insn ( jump , & this_jmp . lab ) ; if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; this_jmp . reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( jump , & this_jmp . lab ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( far && flag_pic && TARGET_SH2 ) { braf_base_lab = gen_label_rtx ( ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file

, <STR_LIT> , CODE_LABEL_NUMBER ( braf_base_lab ) ) ;


<s> if ( OddSPReg ) Value |= ( uint32_t ) <STR_LIT> ; return


, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool isMemoryIndexed64 ( ) const { return isMemoryIndexed (


<s> if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I


<s> } if ( TT . isOSBinFormatCOFF ( ) ) return <STR_LIT> ; std :: string Endian = LittleEndian ? <STR_LIT> : <STR_LIT> ; std :: string Ptr32 = TT . getEnvironment ( ) == Triple ::


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasVSX ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) { MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else { NumStoreSPILLVSRRCAsGpr ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; } return true ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) MI . setDesc ( get ( <STR_LIT> ) ) ; else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get (


<s> return CreateReg ( Index , Str , RegKind_MSA128 , RegInfo


<s> Register Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Lane == <NUM_LIT> ) { unsigned Wt = Ws ; if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { Register Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( Lane ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return


<s> return DecodeMem ( Inst , insn , Address , Decoder , true ,


<s> getAddrMode6OffsetOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand (


<s> Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseParensForSymbolVariant = true ; UseIntegratedAssembler = true ; DwarfRegNumForCFI = false


<s> static bool nds32_naked_function_p ( tree func ) { tree t ; if ( TREE_CODE ( func ) != FUNCTION_DECL )


<s> if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case


<s> Value * BaseBasePtr = foldGEP ( BaseGEP , Offsets , Builder ) ; if ( ! BaseBasePtr ) return nullptr ; Offsets = CheckAndCreateOffsetAdd ( Offsets , GEP -> getOperand ( <NUM_LIT> ) , GEP , Builder ) ; if ( Offsets == nullptr ) return nullptr ; return BaseBasePtr ; } return GEPPtr


<s> bool isAligned = ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg )


<s> default : return true ; case ELF :: R_<ISA_LIT>_PREL31 : case ELF :: R_<ISA_LIT>_ABS32 : return false


<s> xor_constant = <NUM_LIT> << ( <NUM_LIT> - shift_amount - <NUM_LIT> ) ; and_constant = ( code == ASHIFT ? <NUM_LIT> - ( <NUM_LIT> << shift_amount ) : ( <NUM_LIT> << ( <NUM_LIT> - shift_amount ) ) - <NUM_LIT> ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , <NUM_LIT> ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ; emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode (


<s> MachineInstr & AllocWithProbe = * MBBI ; uint64_t Offset = AllocWithProbe . getOperand ( <NUM_LIT> ) . getImm ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; assert ( ! ( STI . is64Bit ( ) && STI . isTargetWindowsCoreCLR ( ) ) && <STR_LIT> ) ; const uint64_t StackProbeSize = TLI . getStackProbeSize ( MF ) ; uint64_t ProbeChunk = StackProbeSize * <NUM_LIT> ; uint64_t MaxAlign = TRI -> needsStackRealignment ( MF ) ? calculateMaxStackAlign ( MF ) : <NUM_LIT> ; if ( Offset > ProbeChunk ) { emitStackProbeInlineGenericLoop ( MF , MBB , MBBI , DL , Offset , MaxAlign % StackProbeSize ) ; } else