<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_broadcasti64x2_256_mask ( ( __v2di ) __A , ( __v4di ) _mm256_setzero_si256 ( )


<s> return DisassembleLdStFrm ( MI , Opcode , insn ,


<s> } MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( Arg . getValueSizeInBits ( ) / <NUM_LIT> , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy (


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return TT . isOSBinFormatMachO ( ) ? Reloc :: PIC_ : Reloc :: Static ; if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return * RM


<s> SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; break ; } } return DAG . getNode ( <STR_LIT> , DL ,


<s> bool isDPRCalleeSavedAreaFrame ( int fi ) const { if ( fi < <NUM_LIT> || fi >= ( int ) DPRCSFrames


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI ) { EmitSled ( MI , SledKind


<s> case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_REL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT>


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfaRegister ( nullptr


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType ( ) , Subtarget -> useSVEForFixedLengthVectors (


<s> split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( TheThumbTarget ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> unsigned int needed_reg_count ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; cum = get_cumulative_args ( ca ) ; if ( TARGET_HARD_FLOAT ) return <NUM_LIT> ; if ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS ) return <NUM_LIT> ; needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG ( arg . mode


<s> SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand ( <NUM_LIT> ) ; if ( NegC ) C = C . getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( ! NegMul ) Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( ! NegC ) ? <STR_LIT>


<s> const DataLayout * getDataLayout ( ) const override { return &


<s> if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm :: create<ISA_LIT>16TargetLowering ( TM ) ; return llvm :: create<ISA_LIT>SETargetLowering


<s> return __builtin_mve_vmulq_sv16qi ( __a ,


<s> return ( vector signed int ) __builtin_altivec_vmulosh ( ( vector signed short ) a1 , ( vector signed


<s> return ( __m512i ) __builtin_ia32_vpshldv_v8di ( ( __v8di ) __A , ( __v8di )


<s> } else { errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } if ( ! isRI ) { errs ( ) << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else errs ( ) <<


<s> Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt


<s> static SDValue combineFAnd ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N ->


<s> note_stores ( PATTERN ( vr4130_last_insn ) , vr4130_true_reg_dependence_p_1 , & insn ) ; return insn


<s> const MCExpr * getMemShiftAmount ( ) const { assert ( Mem . OffsetIsReg && Mem . OffsetRegShifted && <STR_LIT> ) ; return Mem . ShiftAmount


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char


<s> bool Modified = false ; MfIterator End = MF . end ( ) ; for ( MfIterator MFI = MF . begin ( ) ; MFI != End ;


<s> PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumberOfParts ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost


<s> case <STR_LIT> : \ if ( Masked ) \ return IsTestN ? <STR_LIT> ## SUFFIX ## k : <STR_LIT> ## SUFFIX ## k ; \ return IsTestN ? <STR_LIT> ## SUFFIX : <STR_LIT> ## SUFFIX ; default : llvm_unreachable ( <STR_LIT> ) ; \ VPTESTM_CASE ( v4i32 , DZ128 ## SUFFIX ) \ VPTESTM_CASE ( v2i64 , QZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i32 , DZ256 ## SUFFIX ) \ VPTESTM_CASE ( v4i64 , QZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i32 , DZ ## SUFFIX ) \ VPTESTM_CASE ( v8i64 , QZ ## SUFFIX ) VPTESTM_BROADCAST_CASES ( SUFFIX ) \ VPTESTM_CASE ( v16i8 , BZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i16 , WZ128 ## SUFFIX ) \ VPTESTM_CASE ( v32i8 , BZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i16 , WZ256 ## SUFFIX ) \ VPTESTM_CASE ( v64i8 , BZ ## SUFFIX ) \ VPTESTM_CASE ( v32i16 , WZ ## SUFFIX ) if ( FoldedBCast ) { switch ( TestVT . SimpleTy ) { VPTESTM_BROADCAST_CASES (


<s> unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( Mask ) { APInt AllBits = APInt :: getAllOnesValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts


<s> unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue CombineBFI = FindBFIToCombineWith ( N ) ; if ( CombineBFI == SDValue ( ) ) return SDValue ( ) ; APInt ToMask1 , FromMask1 ; SDValue From1 = ParseBFI ( N , ToMask1 , FromMask1 ) ; APInt ToMask2 , FromMask2 ; SDValue From2 = ParseBFI ( CombineBFI . getNode ( ) , ToMask2 , FromMask2 ) ; assert ( From1 == From2 ) ; ( void ) From2 ; DCI . DAG . ReplaceAllUsesWith ( CombineBFI , CombineBFI . getOperand ( <NUM_LIT> ) ) ; APInt NewFromMask = FromMask1 | FromMask2 ; APInt NewToMask =


<s> unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpcode = SecondMI . getOpcode ( ) ; if ( ST . hasFuseAES ( ) ) switch (


<s> bool isThumb ( const MCSubtargetInfo & STI ) const { return ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> std :: fill ( LastMIs , LastMIs + <NUM_LIT> , nullptr ) ; MIIdx =


<s> emit_insn ( gen_zero_extendqisi2 ( reg [ <NUM_LIT> ] , sub_reg ) ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( temp_sub_reg , mem [ <NUM_LIT> ] ) ; emit_insn ( gen_ashlsi3 ( temp_reg , temp_reg , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( reg [ <NUM_LIT> ] , reg [ <NUM_LIT> ] , temp_reg ) ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ; shift = <NUM_LIT>


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = P . OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = P . OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym -> print ( O , P . MAI ) ; else { O << '(' ; GVSym -> print ( O , P . MAI ) ; O << ')' ; } P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ; } const MCExpr * Expr = Op . getExpr ( ) ; if ( const MCUnaryExpr * UnExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) { if ( UnExpr -> getOpcode ( ) == MCUnaryExpr :: Minus ) { Inst . addOperand ( MCOperand :: CreateExpr ( UnExpr -> getSubExpr ( ) ) ) ; return ; } } else if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) { if ( BinExpr -> getOpcode ( ) == MCBinaryExpr :: Sub ) { const MCExpr * NE = MCBinaryExpr :: CreateSub ( BinExpr -> getRHS ( ) , BinExpr -> getLHS ( )


<s> bool Changed = false ; for ( auto * F : Functions ) { for ( auto & BB : * F ) { SmallSetVector < IntrinsicInst * , <NUM_LIT> > SVAllPTrues ; SmallSetVector < IntrinsicInst * , <NUM_LIT> > SVPow2PTrues ; for ( Instruction & I : BB ) { if ( I . use_empty ( ) ) continue ; auto * IntrI = dyn_cast < IntrinsicInst > ( &


<s> extern __inline __rdtime_t __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __rdtimel_w ( void ) { __rdtime_t __rdtime ; __asm__ volatile ( <STR_LIT> : [ val ] <STR_LIT> ( __rdtime . value ) , [ tid ] <STR_LIT> ( __rdtime . timeid ) : ) ; return


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AssemblerOptions . push_back ( std :: make_unique < <ISA_LIT>AssemblerOptions > ( AssemblerOptions . back ( ) . get ( ) ) ) ; getTargetStreamer ( ) . emitDirectiveSetPush ( )


<s> DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default : break ; case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : case


<s> if ( ! tryAddingSymbolicOperand ( Insn + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand


<s> if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ) ) ; } if ( SDValue Cmp = foldVectorXorShiftIntoCmp ( N , DAG , Subtarget ) )


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > Y ( The<ISA_LIT>V9Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target


<s> static bool expandDisp ( <ISA_LIT>AddressingMode & AM , bool IsBase , SDValue Op0 , ConstantSDNode * Op1 ) { int64_t TestDisp = AM . Disp + Op1 -> getSExtValue ( ) ; if ( selectDisp ( AM . DR , TestDisp ) ) { changeComponent ( AM , IsBase , Op0 ) ; AM . Disp = TestDisp ; return true


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; Relocator :: DWord X =


<s> const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue ( unsigned SYSm ) { return lookupMClassSysRegByM1Encoding12 ( SYSm


<s> return ( __mmask8 ) __builtin_ia32_cvtw2mask128 ( (


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; if ( MI -> getOperand ( OpNo ) . isReg ( ) )


<s> BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ EntryIdx ] . VSEId ) ) ; DEBUG ( MI -> dump ( ) ) ; MI -> eraseFromParent (


<s> } } else { if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && local_call ) ) { xoperands [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; xoperands [ <NUM_LIT> ] = xoperands [ <NUM_LIT> ] ; pa_output_pic_pcrel_sequence ( xoperands ) ; } else { xoperands [ <NUM_LIT> ] = pa_get_deferred_plabel ( call_dest ) ; xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; if ( TARGET_SOM ) copy_fp_args ( insn ) ; if ( flag_pic ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( ! sibcall && ! TARGET_PA_20 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_NO_SPACE_REGS || ( local_call && ! flag_pic ) ) output_asm_insn ( <STR_LIT> , xoperands ) ; else output_asm_insn ( <STR_LIT> , xoperands ) ; } } if ( TARGET_PA_20 ) { if ( sibcall ) output_asm_insn ( <STR_LIT> , xoperands ) ; else { if ( indirect_call ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; seq_length = <NUM_LIT> ; } else output_asm_insn ( <STR_LIT> , xoperands ) ; } } else { if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) output_asm_insn ( <STR_LIT> , xoperands ) ; if ( sibcall ) { if ( TARGET_NO_SPACE_REGS || ( local_call && ! flag_pic ) ) output_asm_insn ( <STR_LIT> , xoperands ) ; else output_asm_insn ( <STR_LIT> , xoperands ) ; } else { if ( TARGET_NO_SPACE_REGS || ( local_call && ! flag_pic ) ) output_asm_insn ( <STR_LIT> , xoperands ) ; else output_asm_insn ( <STR_LIT> , xoperands ) ; if ( indirect_call ) output_asm_insn ( <STR_LIT> , xoperands ) ; else output_asm_insn ( <STR_LIT> , xoperands ) ; seq_length =


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple


<s> Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) ,


<s> static unsigned bitmap_popcount ( const sbitmap bmap ) { unsigned int count = <NUM_LIT> ; unsigned int n = <NUM_LIT> ; sbitmap_iterator sbi


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * Gep = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! Gep || Gep -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return None ; if ( ! MRI . hasOneUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> )


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister

( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + NumElems )


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPR32RegisterClass ( Inst , RegNo


<s> unsigned ScratchRegW = STI -> getRegisterInfo ( ) -> getSubReg ( ScratchReg , <STR_LIT> ) ; unsigned TableReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned EntryReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int JTIdx = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool IsByteEntry = MI . getOpcode ( ) == <STR_LIT> ; auto Label = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getJumpTableEntryPCRelSymbol ( JTIdx ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addExpr ( MCSymbolRefExpr :: create ( Label , MF


<s> bool hasFMA4 ( ) const { return HasFMA4


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; getTargetStreamer ( ) .


<s> void <ISA_LIT>ATTAsmPrinter :: printMachineInstruction ( const MachineInstr * MI ) { ++ EmittedInsts


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill


<s> if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true


<s> else if ( Instruction * LogicI = dyn_cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( CmpInst * CI0 = dyn_cast < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) if ( isa < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI0 -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy != nullptr ) { if ( VF == <NUM_LIT>


<s> const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI .


<s> FunctionPass * create<ISA_LIT>PreLegalizeCombiner


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return false ; return


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { llvm_unreachable ( <STR_LIT> )


<s> if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 )


<s> const TargetFrameLowering * TFI = MF . getTarget (


<s> else if ( CSKY_TARGET_ARCH ( CK802 ) ) return ck802_legitimate_index_p ( mode , index , strict_p ) ; else return ck810_legitimate_index_p ( mode ,


<s> rtx half [ <NUM_LIT> ] ; rtvec v ; int i , j ; switch ( n ) { case <NUM_LIT> : switch ( mode ) { case E_V32HFmode : half_mode = V16HFmode ; break ; case E_V32BFmode : half_mode = V16BFmode ; break ; case E_V16SImode : half_mode = V8SImode ; break ; case E_V16SFmode : half_mode = V8SFmode ; break ; case E_V8DImode : half_mode = V4DImode ; break ; case E_V8DFmode : half_mode = V4DFmode ; break ; case E_V16HFmode : half_mode = V8HFmode ; break ; case E_V16BFmode : half_mode = V8BFmode ; break ; case E_V8SImode : half_mode = V4SImode ; break ; case E_V8SFmode : half_mode = V4SFmode ; break ; case E_V4DImode : half_mode = V2DImode ; break ; case E_V4DFmode : half_mode = V2DFmode ; break ; case E_V4SImode : half_mode = V2SImode ; break ; case E_V4SFmode : half_mode = V2SFmode ; break ; case E_V2DImode : half_mode = DImode ; break ; case E_V2SImode : half_mode = SImode ; break ; case E_V2DFmode : half_mode = DFmode ; break ; case E_V2SFmode : half_mode = SFmode ; break ; default : gcc_unreachable ( ) ; } if ( ! register_operand ( ops [ <NUM_LIT> ] , half_mode ) ) ops [ <NUM_LIT> ] = force_reg ( half_mode , ops [ <NUM_LIT> ] ) ; if ( ! register_operand ( ops [ <NUM_LIT> ] , half_mode ) ) ops [ <NUM_LIT> ] = force_reg ( half_mode , ops [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ) ; break ; case <NUM_LIT> : switch ( mode ) { case E_V4DImode : half_mode =


<s> case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasDQI ( ) ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( NumOperands == <NUM_LIT> && RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case


<s> base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( aarch64_nopcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , <NUM_LIT> ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable (


<s> const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . CreateTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: Create (


<s> uint32_t S = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J1 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J2 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; J1 = ( ~ J1 & <NUM_LIT> ) ; J2 = ( ~ J2 & <NUM_LIT> ) ; J1 ^= S ; J2 ^= S ; offset &= ~


<s> unsigned ArgSize = NextVA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , NextVA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else


<s> void <ISA_LIT>InstPrinter :: printPostIdxRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << ( MO2 . getImm ( ) ?


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , MaskVT ) ; else MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode (


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> public : <ISA_LIT>MCInstLower ( MCContext & CTX , Mangler & Mang , AsmPrinter & AP ) : Ctx ( CTX ) , Printer ( AP ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> APInt BitImm = APInt ( ResTy . getVectorElementType ( ) . getSizeInBits ( ) , <NUM_LIT> ) << cast

< ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ;


<s> if ( MEM_P ( mem ) ) { if ( ( MEM_EXPR ( mem ) && MEM_OFFSET_KNOWN_P ( mem ) && r10k_safe_mem_expr_p ( MEM_EXPR ( mem ) , MEM_OFFSET ( mem ) ) )

|| r10k_safe_address_p ( XEXP ( mem , <NUM_LIT> ) , insn ) ) iter . skip_subrtxes ( ) ;


<s> PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling :: DwarfCFI ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT>


<s> if ( SDValue Sel = foldSelectWithIdentityConstant ( N , DAG , false ) ) return Sel ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isCommutativeBinOp ( N -> getOpcode ( ) ) ) if ( SDValue Sel = foldSelectWithIdentityConstant ( N , DAG ,


<s> const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT

= STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ;


<s> MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNode ( <STR_LIT> , dl , VT


<s> const char * standard_sse_constant_opcode ( rtx_insn * insn , rtx * operands ) { machine_mode mode ; rtx x = operands [ <NUM_LIT> ] ; gcc_assert ( TARGET_SSE ) ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) { switch ( get_attr_mode ( insn ) ) { case MODE_TI : if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; case MODE_XI : case MODE_OI : if ( EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; return <STR_LIT> ; case MODE_V2DF : if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; case MODE_V8DF : case MODE_V4DF : if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else if ( TARGET_AVX512DQ ) return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; else return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; case MODE_V4SF : if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; case MODE_V16SF : case MODE_V8SF : if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else if ( TARGET_AVX512DQ ) return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; else return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; default : gcc_unreachable ( ) ; } } else if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) || ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT && float_vector_all_ones_operand ( x , mode ) ) ) { enum attr_mode insn_mode = get_attr_mode ( insn ) ; switch ( insn_mode ) { case MODE_XI : case MODE_V8DF : case MODE_V16SF : gcc_assert ( TARGET_AVX512F ) ; return <STR_LIT> ; case MODE_OI : case MODE_V4DF : case MODE_V8SF : gcc_assert ( TARGET_AVX2 ) ; case MODE_TI : case MODE_V2DF : case MODE_V4SF : gcc_assert ( TARGET_SSE2 ) ; if ( ! EXT_REX_SSE_REG_P ( operands [ <NUM_LIT> ] ) ) return ( TARGET_AVX ? <STR_LIT> : <STR_LIT> ) ; else if ( TARGET_AVX512VL ) return <STR_LIT> ; else return <STR_LIT> ; default : gcc_unreachable ( )


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node =


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>MachObjectWriter ( OS , false , MachO :: CPU_TYPE_<ISA_LIT> , Subtype


<s> if ( ! isMVEMem ( ) || Memory . OffsetImm != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . OffsetRegNum ) ) return false ; if ( shift == <NUM_LIT> && Memory . ShiftType !=


<s> if ( INTVAL ( in0_idx0 ) == INTVAL ( in1_idx0 ) && INTVAL ( in0_idx1 ) == INTVAL ( in1_idx1 ) && INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) ) return false ; if ( INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) && INTVAL ( in1_idx0 ) != INTVAL ( in1_idx1 ) ) return false ; return true


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits (


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ; bool ValKill = hasTrivialKill (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __popcntq ( unsigned long long


<s> assert ( Kind == k_VectorList && <STR_LIT> ) ; return VectorList .


<s> unsigned getModImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & ST ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType , CPUSubtype ) , OS


<s> __o = __builtin_aarch64_set_qregciv2di_ssps ( __o , ( poly64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2di_ssps ( __o , ( poly64x2_t ) val . val


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return Lower256IntArith ( Op , DAG


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this


<s> static inline SlotWithTag getTombstoneKey (


<s> if ( ! IsData ) return Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; bool IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Code = IsWrite ? <STR_LIT> : <STR_LIT> ; auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Code , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Node -> getVTList ( ) ,

Ops , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ;


<s> void EmitARM64WinCFIClearUnwoundToCall (


<s> if ( loadImmediate ( ImmOp64 , FirstReg , <STR_LIT> , false , false , IDLoc , Out , STI ) ) return true ; } else { if ( loadImmediate ( Hi_32 ( ImmOp64 ) , FirstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; if ( loadImmediate ( <NUM_LIT> , nextReg ( FirstReg ) , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; getStreamer ( ) . EmitIntValue (


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> adjustsStack ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( )


<s> if ( ! tryAddingSymbolicOperand ( Value , isBranch , Address , <NUM_LIT> , N / <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegSet ( ) const { return GlobalBaseReg


<s> if ( MO . isExpr ( ) ) return getAddressWithFixup ( MO , fixupDesired , Fixups ) ; assert ( MO . isImm ( )


<s> MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) CalleeSavedAreaSize += MFI -> getObjectAlignment ( CSI [ i ] . getFrameIdx ( ) ) ; unsigned StackOffset = HasGP ? ( <ISA_LIT>FI -> getGPStackOffset ( ) + RegSize ) : ( STI . isABI_O32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; int LastOffsetFI = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( i >= MinCSFI && i <= MaxCSFI ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; unsigned Offset = StackOffset + MFI -> getObjectOffset ( i ) - CalleeSavedAreaSize ; if ( LastOffsetFI == - <NUM_LIT> ) LastOffsetFI = i ; if ( Offset > MFI -> getObjectOffset ( LastOffsetFI ) ) LastOffsetFI = i ; MFI -> setObjectOffset ( i , Offset ) ; } if ( LastOffsetFI >= <NUM_LIT> ) StackOffset = MFI -> getObjectOffset ( LastOffsetFI ) + MFI -> getObjectSize ( LastOffsetFI ) ; StackOffset = ( ( StackOffset + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> -> contains ( Reg ) ) break ; MFI -> setObjectOffset ( CSI [ i ] . getFrameIdx ( ) , StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += MFI -> getObjectAlignment ( CSI [ i ] . getFrameIdx ( ) ) ; } if ( hasFP ( MF ) || MFI -> adjustsStack ( ) ) { MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setFPStackOffset ( StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setRAStackOffset ( StackOffset ) ; StackOffset += RegSize ; if ( MFI -> adjustsStack ( ) ) TopCPUSavedRegOff


<s> vshll_n_u32 ( uint32x2_t __a , const int __b ) { return ( uint64x2_t ) __builtin_neon_vshllu_nv2si ( (


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv16qi ( ( int8x16_t )


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( Invert ) CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } bool isFP = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ; SDValue Cond = EmitCmp ( Op0 , Op1


<s> bool <ISA_LIT>ConstantIslands :: OptimizeThumb2Branches ( MachineFunction & MF ) { bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) { ImmBranch & Br = ImmBranches [ i ] ; unsigned Opcode = Br . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( Br . MI , DestBB , MaxOffs ) ) { Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBSizes [ MBB -> getNumber ( ) ] -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , - <NUM_LIT> ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = GetOffsetOf ( Br . MI ) + <NUM_LIT> -


<s> return sizeof ( Elf<ISA_LIT>AbiFlags )


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes =


<s> MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; Divisor . setIsKill ( false ) ; return & MBB


<s> static bool DisassembleThumb2SRS ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo

( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> return ( ( qword ) ( vec_sll ( ( vec_uchar16 ) ( a ) , x )


<s> int Scale ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Scale = <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : Scale = - <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = - <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; CheckCPSRDef = false ; break ; case <STR_LIT> : Scale = - <NUM_LIT> ; CheckCPSRDef = false ; break ; default :


<s> getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , Bytes ) ; int First ; if ( ! getShuffleInput ( Bytes , Index * BytesPerElement , BytesPerElement , First ) ) break ; if ( First < <NUM_LIT> ) return DAG . getUNDEF ( ResVT ) ; unsigned Byte = unsigned ( First ) % Bytes . size ( ) ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte = Byte % ExtBytesPerElement ; unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement ; if ( SubByte < MinSubByte || SubByte + BytesPerElement > ExtBytesPerElement ) break ; Byte = Byte / ExtBytesPerElement * OpBytesPerElement ; Byte += SubByte - MinSubByte ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( <NUM_LIT>


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case


<s> static bool unknown_for_bundling_p ( rtx_insn * insn ) { return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) == ITANIUM_CLASS_UNKNOWN && GET_CODE ( PATTERN ( insn )

) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ;


<s> EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> (


<s> if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: get<ISA_LIT>_FP80Ty ( LLVMBB -> getContext ( ) ) || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPointTy ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: getDoubleTy ( LLVMBB -> getContext ( ) ) ) ) { ContainsFPCode = true


<s> void incNumLocalDynamicTLSAccesses ( ) { ++


<s> return new <ISA_LIT>CodeEmitter ( TM ,


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectUIToFP ( const Instruction *


<s> assert ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg


<s> default : return true ; case AsmToken :: Integer : case AsmToken :: Minus : case AsmToken :: Plus : return ( getParser ( ) . ParseExpression ( Res ) ) ; case AsmToken :: Percent : return parseRelocOperand ( Res ) ; case AsmToken :: LParen


<s> SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , Load . getDebugLoc ( ) , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; bool IsGlued = Call . getOperand ( <NUM_LIT> ) . getNode ( ) -> getGluedUser ( ) == Call . getNode ( ) ; unsigned NumOps = Call . getNode ( ) -> getNumOperands ( ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT>


<s> SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , dl , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , dl , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> static SDValue canonicalizeBitSelect ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Subtarget . hasXOP ( ) || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ! getTargetConstantBitsFromNode ( N0 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts0 , EltBits0 , false , false ) ) return SDValue ( ) ; if ( ! getTargetConstantBitsFromNode ( N1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts1 , EltBits1 , false , false ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> , e = EltBits0 . size ( ) ; i != e ; ++ i ) { if ( UndefElts0 [ i ] || UndefElts1


<s> water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , NewBB , CompareMBBNumbers ) ; WaterList . insert ( IP , NewBB


<s> return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= <NUM_LIT> && recog_memoized ( dep ) >= <NUM_LIT> ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr & MemMI = * I ; MachineBasicBlock :: iterator MBBI = I ; Register BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * TII -> getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; if ( ! isTagStore ( MemMI ) && MemMI . getOpcode ( ) != <STR_LIT> ) { bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , UnscaledOffset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI ,

ModifiedRegUnits , UsedRegUnits , TRI ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , MII ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( sti . getTargetTriple ( ) ) , sti . getCPU ( ) , Options ) ) { MCAsmParserExtension :: Initialize ( parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits


<s> auto & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( ! Subtarget . hasLSE ( ) && ! Subtarget . outlineAtomics ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue RHS = Op . getOperand


<s> regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ; regs = std :: min ( <NUM_LIT> , regs ) ; S = MCDisassembler :: SoftFail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd


<s> return ( __m512i ) __builtin_ia32_pmaddubsw512_mask ( ( __v64qi ) __X , ( __v64qi ) __Y , (


<s> ElementCount ResEC = VT . getVectorElementCount ( ) ; if ( InVT . getVectorElementCount ( ) != ( ResEC * <NUM_LIT> ) ) return ; auto * CIndex = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CIndex ) return ; unsigned Index = CIndex -> getZExtValue ( ) ; if ( ( Index != <NUM_LIT> ) && ( Index != ResEC . getKnownMinValue ( ) ) ) return ; unsigned Opcode = ( Index == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT ExtendedHalfVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; SDValue Half = DAG . getNode ( Opcode , DL , ExtendedHalfVT , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT


<s> static int try_issue_insn ( struct bundle_state *


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { return Outs . size ( ) <=


<s> bool shouldInsertFencesForAtomic ( const Instruction * I )


<s> return ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 !=


<s> Register CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent ( ) ; return EndMBB


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getMVEPairVectorIndexOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget )


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false

, true , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> unsigned opcode ; if ( Subtarget -> hasSSE2 ( ) && isAndOrOfSetCCs ( SDValue ( N , <NUM_LIT> ) , opcode ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue CMP0 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP1 = N1 -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( CMP0 . getOpcode ( ) != <STR_LIT> || CMP0 != CMP1 ) return SDValue ( ) ; SDValue CMP00 = CMP0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP01 = CMP0 -> getOperand ( <NUM_LIT> ) ; EVT VT = CMP00 . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { bool ExpectingFlags = false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ! ExpectingFlags && UI != UE ; ++ UI ) switch ( UI -> getOpcode ( ) ) { default : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ExpectingFlags = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> NTOperator = is64BitFP ? <STR_LIT> : <STR_LIT> ; unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue OnesOrZeroesF = DAG . getNode ( NTOperator , DL , <STR_LIT> , CMP00

, CMP01 , DAG . getConstant ( x86cc , <STR_LIT> ) ) ;


<s> void addMemThumbRIs1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAndOp ( ) const { return ArePtrs64bit ( ) ? <STR_LIT>


<s> bool <ISA_LIT>GNULDBackend :: mergeSection ( Module & pModule , const Input & pInput ,


<s> if ( getOptLevel ( ) != CodeGenOpt :: None )

addPass ( create<ISA_LIT>PostSelectOptimize ( ) ) ;


<s> static unsigned int ix86_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GENERAL_REGNO_P ( regno ) ) { if ( mode == XFmode ) return TARGET_64BIT ? <NUM_LIT>


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand


<s> SDValue InsVal = Op . getOperand ( <NUM_LIT> ) ; if ( ! InsVector . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegInsVal = isFNEG ( DAG , InsVal . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegInsVal . getValueType ( ) == VT . getVectorElementType ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , InsVector , NegInsVal , Op . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op1 , ScalarSize , UndefElts , EltBits , true , false ) ) { for ( unsigned I = <NUM_LIT> , E = EltBits . size ( ) ; I < E ; I ++ ) if ( ! UndefElts [ I ] && ! EltBits [ I ] . isSignMask ( ) ) return SDValue ( ) ; Op0 = peekThroughBitcasts ( Op0 ) ; if ( Op0 . getScalarValueSizeInBits ( ) ==


<s> DECL_EXTERNAL ( dispatch_decl ) = <NUM_LIT> ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( )


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeList A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: NoInline ) ; FunctionCallee F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ; F . addFnAttr ( <STR_LIT>


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit

( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> } ; const AsmToken & PercentTok = Parser . getTok ( ) ; StartLoc = PercentTok . getLoc ( ) ; if ( ! isParsingIntelSyntax ( ) && PercentTok . is ( AsmToken :: Percent ) ) { Tokens . push_back ( PercentTok ) ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; EndLoc = Tok . getEndLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { OnFailure ( ) ; if ( isParsingIntelSyntax ( ) ) return true ; return Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( Tok . getString ( ) . lower ( ) ) ; if ( isParsingMSInlineAsm ( ) && isParsingIntelSyntax ( ) && ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) ) RegNo = <NUM_LIT> ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) { StringRef RegName = Tok . getString ( ) ; OnFailure ( ) ; if ( ! RestoreOnFailure ) { Parser . Lex ( ) ; } return Error ( StartLoc , <STR_LIT> + RegName + <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } } if ( RegNo == <STR_LIT> ) { Tokens . push_back ( Tok ) ; Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: LParen ) ) return false ; Tokens . push_back ( Parser . getTok ( ) ) ; Parser . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) { OnFailure ( ) ; return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : OnFailure ( ) ; return Error ( IntTok . getLoc (


<s> ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { auto * First = dyn_cast < User > ( Pair . first ) ; auto * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; auto * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set ( BackToBool ) ; return true


<s> return __builtin_mve_vmvnq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __imm ,


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __B , ( __v32hi ) _mm512_setzero_si512 ( )


<s> unsigned ShiftAmt = Shift . getConstantOperandVal ( <NUM_LIT> ) ; unsigned AMShiftAmt = countTrailingZeros ( Mask ) ; if ( AMShiftAmt <= <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; MVT VT = N . getSimpleValueType ( ) ; SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewMask = DAG . getConstant ( Mask >> AMShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewMask ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSRLAmt ) ; insertDAGNode ( DAG , N , NewSRL ) ; insertDAGNode ( DAG , N , NewMask ) ; insertDAGNode ( DAG , N , NewAnd ) ; insertDAGNode ( DAG , N , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSHL


<s> default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue ( ) ; } SDValue Result = DAG . getConstant ( SplatValue , ViaVecTy ) ; if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return Result ; } else if ( isSplatVector ( Node ) ) return Op ; else if ( ! isConstantOrUndefBUILD_VECTOR ( Node ) ) { EVT ResTy = Node -> getValueType ( <NUM_LIT> ) ; assert ( ResTy . isVector ( ) ) ; unsigned NumElts = ResTy . getVectorNumElements ( ) ; SDValue Vector = DAG . getUNDEF ( ResTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { Vector = DAG . getNode ( <STR_LIT> , DL , ResTy , Vector , Node -> getOperand ( i ) , DAG . getConstant ( i , <STR_LIT> ) ) ; } return Vector


<s> unsigned Opcode = CurrentInst -> Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>


<s> vmlsl_high_s8 ( int16x8_t a , int8x16_t b , int8x16_t c ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c )


<s> rtx loop_label , tmp ; if ( optimize_size || optimize < <NUM_LIT> ) return false ; gcc_assert ( MEM_P ( str ) ) ; gcc_assert ( CONST_INT_P ( target_char ) || REG_P ( target_char ) ) ; base_reg = copy_to_mode_reg ( SImode , XEXP ( str , <NUM_LIT> ) ) ; loop_label = gen_label_rtx ( ) ; ffb_result = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( SImode ) ; backup_base_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( backup_base_reg , base_reg ) ; emit_label ( loop_label ) ; emit_insn ( gen_unaligned_load_update_base_w ( base_reg , tmp , base_reg ) ) ; emit_insn ( gen_unspec_ffb ( ffb_result , tmp , target_char ) ) ; emit_cmp_and_jump_insns ( ffb_result , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , loop_label ) ; target_char_ptr = expand_binop ( Pmode , add_optab , base_reg , ffb_result , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; length = expand_binop ( Pmode , sub_optab , target_char_ptr , backup_base_reg , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( result , length


<s> for ( unsigned VT1 = FirstVT ; VT1 <= LastVT ; ++ VT1 ) setTruncStoreAction ( ( <STR_LIT> ) VT0 , ( <STR_LIT> ) VT1 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; } } if ( Subtarget -> hasDSP ( ) ) { <STR_LIT> VecTys [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < array_lengthof ( VecTys ) ; ++ i ) { addRegisterClass ( VecTys [ i ] , & <STR_LIT> ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , VecTys [ i ] , Expand ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; } setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( Subtarget -> hasDSPR2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget -> hasMSA ( ) ) { addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( ! Subtarget -> mipsSEUsesSoftFloat ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Subtarget -> isFP64bit ( ) ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; } return


<s> SDLoc DL ( Addr ) ; EVT ValTy = Addr . getValueType ( ) ; if ( SPAllowed ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( SPAllowed ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ; } } Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL ,


<s> return lookupFoldTableImpl ( MemoryFoldTable2Addr


<s> void <ISA_LIT>64CompilationCallback ( ) { assert ( <NUM_LIT> && <STR_LIT> ) ; abort (


<s> } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getITInstrPredicate (


<s> static const unsigned EhDataReg [ ] = { <STR_LIT> , <STR_LIT> } ; return EhDataReg [


<s> bool <ISA_LIT>AsmParser :: validatetSTMRegList ( const MCInst & Inst , const OperandVector & Operands , unsigned ListNo ) { const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op


<s> MachineBasicBlock :: iterator MI = mi ; MachineBasicBlock * MBB = mbbi ; ++ mi ; if ( MI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { expandLoadImm ( * MBB , MI , TII ) ; MBB -> erase ( MI ) ; ++ ExpandPseudo ; continue ; } if ( MI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { expandIJmp ( * MBB , MI , TII ) ; MBB -> erase ( MI


<s> static SDValue combineVEXTRACT_STORE ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { auto * St = cast < MemIntrinsicSDNode > ( N ) ; SDValue StoredVal = N -> getOperand ( <NUM_LIT> ) ; MVT VT = StoredVal . getSimpleValueType ( ) ; EVT MemVT = St -> getMemoryVT ( ) ; unsigned StElts = MemVT . getSizeInBits ( ) / VT . getScalarSizeInBits ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( VT . getVectorNumElements ( ) , StElts ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedVectorElts ( StoredVal , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } return SDValue ( )


<s> if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ; int NewElt = -


<s> return ( __m128i ) __builtin_ia32_psrldi128_mask ( ( __v4si ) __A , __imm , (


<s> auto & OldSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; unsigned NewSrcReg = get<ISA_LIT>SubSuperRegister ( OldSrc . getReg ( ) , <NUM_LIT> ) ; auto * TRI = & TII -> getRegisterInfo ( ) ; if ( TRI -> getSubRegIndex ( NewSrcReg , OldSrc . getReg ( ) ) != TRI -> getSubRegIndex ( NewDestReg , OldDest . getReg ( ) ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewDestReg )

. addReg ( NewSrcReg , RegState :: Undef ) . addReg ( OldSrc . getReg ( ) , RegState :: Implicit ) ;


<s> TargetRegistry :: RegisterTarget ( getTheARM64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; TargetRegistry :: RegisterTarget ( getTheARM64_32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: aarch64 , true > Z ( getThe<ISA_LIT>leTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: aarch64_be , true > W ( getThe<ISA_LIT>beTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: aarch64_32 , true > X ( getThe<ISA_LIT>_32Target (


<s> return DFmode ; case <NUM_LIT> : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; case <NUM_LIT> : return VOIDmode ; default : gcc_unreachable ( ) ; } } else { switch (


<s> MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( <STR_LIT> , ( <STR_LIT> + <STR_LIT> ( ID ) ) . str ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF .


<s> if ( P . useSoftFloat ( ) ) CPR1Size = <STR_LIT> ; else if ( P . hasMSA ( ) ) CPR1Size = <STR_LIT> ; else CPR1Size = P . isFP64bit ( )


<s> fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl


<s> unsigned EvenRegNum = TRI -> getDwarfRegNum ( EvenReg , false ) ; unsigned OddRegNum = TRI -> getDwarfRegNum ( OddReg , false ) ; bool Errata602117 = EvenReg == BaseReg && STI -> isCortexM3 ( ) ; if ( ! Errata602117 && ( ( EvenRegNum & <NUM_LIT> ) == <NUM_LIT> && ( EvenRegNum + <NUM_LIT> ) == OddRegNum ) ) return false ; MachineBasicBlock :: iterator NewBBI = MBBI ; bool isT2 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isLd = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool EvenDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool EvenUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; }


<s> MCDisassembler ( STI ) , RegInfo ( Info ) , IsN64 ( STI . getFeatureBits ( ) & <STR_LIT>


<s> return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return legalizeSVEGatherPrefetchOffsVec ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ; case <STR_LIT> : return performLD1RQCombine ( N , DAG ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performST1Combine ( N , DAG ) ; case <STR_LIT> : return performSTNT1Combine ( N , DAG ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case


<s> assert ( dv -> hasDomain ( domain ) && <STR_LIT> ) ; while ( ! dv -> Instrs . empty ( ) ) TII -> SetSSEDomain ( dv -> Instrs .