<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) ,


<s> for ( insn = LABEL_REFS ( lab ) ; insn ; insn = LABEL_REFS ( insn ) ) INSN_DELETED_P ( insn ) = <NUM_LIT> ; for ( insn = NEXT_INSN ( x ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) != INSN ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , <NUM_LIT> ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4


<s> ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o


<s> int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return false ; return ( Val >= - ( <NUM_LIT> << <NUM_LIT> ) && Val <= ( <NUM_LIT> <<


<s> const char * p = getenv ( <STR_LIT> ) ; val = p && strlen ( p ) ; } return ! val


<s> MVT VT = N -> getValueType ( <NUM_LIT> ) ; MVT EVT = VT . getVectorElementType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT == <STR_LIT> ) { SDValue In [ <NUM_LIT> ] ; In [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; In [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; int Idx0 = SVN -> getMaskElt ( <NUM_LIT> ) ; int Idx1 = SVN -> getMaskElt ( <NUM_LIT> ) ; if ( Idx0 >= <NUM_LIT> && Idx1 >= <NUM_LIT> && In [ Idx0 / <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && In [ Idx1 / <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * InsertVecIdx = dyn_cast < ConstantSDNode > ( In [ Idx0 / <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) ; if ( InsertVecIdx && InsertVecIdx -> getZExtValue ( ) == ( unsigned ) ( Idx0 % <NUM_LIT> ) && isZeroNode ( In [ Idx1 / <NUM_LIT> ] . getOperand ( Idx1 % <NUM_LIT> ) ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , In [ Idx0 / <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , In [ Idx1 / <NUM_LIT> ] . getOperand ( Idx1 % <NUM_LIT> ) ) ; } } } MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDNode * Base = NULL ; if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EVT , Base , DAG , MFI , TLI ) ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Base ) ; if ( isBaseAlignmentOfN ( <NUM_LIT> , Base -> getOperand ( <NUM_LIT> ) . getNode ( ) , TLI ) ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD ->

getSrcValueOffset ( ) , LD -> isVolatile ( ) ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> )


<s> inline vector unsigned int vec_vminuw ( vector unsigned int a1 , vector unsigned int


( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ;


<s> return ( __m256 ) __builtin_ia32_andnps256 ( ( __v8sf ) __A ,


<s> const unsigned ShiftAmt = ChunkIdx * <NUM_LIT> ; uint64_t Encoding ; if ( <STR_LIT> ( OrrImm , <NUM_LIT> , Encoding ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( Encoding ) ; const unsigned Imm16 = getChunk ( UImm , ChunkIdx ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; transferImpOps ( MI , MIB , MIB1 ) ; MI . eraseFromParent


<s> assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSRLAmt ) ; insertDAGNode ( DAG , N , NewSRL ) ; insertDAGNode ( DAG , N , NewSHLAmt ) ; insertDAGNode ( DAG , N


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) *


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx ,


<s> unsigned <ISA_LIT>ABIInfo :: GetGlobalCapability ( ) const { return <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Flags ) ;


<s> return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx op0_word , op1_word ; rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = <NUM_LIT> ; i < num_words - <NUM_LIT> ; i ++ ) { op0_word = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; op1_word = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , op0_word , op1_word , code == EQ ? lab : loc ) ; } op0_word = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; op1_word = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , op0_word , op1_word , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode


<s> return __builtin_neon_vfmsl_lowv2sf ( __r ,


<s> r = sr -> curr . reg + decode_abreg ( abreg , <NUM_LIT> ) ; r -> where = UNW_WHERE_SPREL ; r -> when = sr -> region_start + MIN ( ( int


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitMOVHLPS ( const


<s> const char * getPassName ( ) const override { return


<s> SrcVT = TLI . getValueType ( Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT


<s> if ( ! ( * insn_data [ icode ] . operand [ opno ] . predicate ) ( op [ argc ] , mode [ argc ] ) ) error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> <STR_LIT> , argc + <NUM_LIT> ) ; break ; case NEON_ARG_MEMORY : if ( op [ argc ] == const0_rtx ) { va_end ( ap ) ; return <NUM_LIT> ; } gcc_assert ( MEM_P ( op [ argc ] ) ) ; PUT_MODE ( op [ argc ] , mode [ argc ] ) ; set_mem_alias_set ( op [ argc ] , <NUM_LIT> ) ; if ( ! ( * insn_data [ icode ] . operand [ opno ] . predicate ) ( op [ argc ] , mode [ argc ] ) ) op [ argc ] = ( replace_equiv_address ( op [ argc ] , force_reg ( Pmode , XEXP ( op [ argc ] , <NUM_LIT> ) ) ) ) ; break ; case NEON_ARG_STOP : gcc_unreachable ( ) ; } argc ++ ; } } va_end ( ap ) ; if ( have_retval ) switch ( argc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } else switch ( argc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( BitExtMI ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setReorder ( ) ; getTargetStreamer ( ) . emitDirectiveSetReorder ( ) ; Parser . Lex ( ) ; return


<s> unsigned VReg = getRegForValue ( V ) ; if ( VReg == <NUM_LIT> ) return <NUM_LIT> ; MVT VMVT = TLI . getValueType ( DL , V -> getType ( )


<s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , <NUM_LIT> ) ) ) { offset = XEXP ( y , <NUM_LIT> ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , <NUM_LIT> ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP (


<s> MBB -> addLiveIn ( <STR_LIT> + i - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( i - <NUM_LIT> ) << <STR_LIT> << unsigned ( Bundle . FixStack [ i - <NUM_LIT> ] ) << '\n' ) ; pushReg ( Bundle . FixStack [ i - <NUM_LIT> ] ) ; } adjustLiveRegs ( calcLiveInMask ( MBB ) , MBB -> begin ( ) ) ; DEBUG ( MBB -> dump


<s> if ( ! VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( VT , <NUM_LIT> / VT . getSizeInBits ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VecVT , In ) ; Res = DAG . getNode ( <STR_LIT> , DL , VecVT , Res ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT SVT = VT . getVectorElementType ( ) ; int NumElts = VT . getVectorNumElements ( ) ; int ScalarSizeInBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( VT . is256BitVector ( ) ) { SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , NumElts / <NUM_LIT> , DAG , DL ) ; MVT HalfVT = <STR_LIT> ( SVT , NumElts / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , HalfVT , Lo ) , DAG . getNode ( <STR_LIT> , DL , HalfVT , Hi ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MaskElts ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { for ( int j = ScalarSizeInBytes - <NUM_LIT> ; j >= <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT ->


<s> if ( featureBits [ <STR_LIT> ] && ! ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler ::


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return Imm == ( int32_t


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { return


<s> MandarinGenSubtargetInfo ( TT , CPU , FS ) { ParseSubtargetFeatures ( CPU ,


<s> double d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) :


<s> else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI


<s> if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLSDouble ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; const MachineOperand & BaseOp = MI . getOperand ( <NUM_LIT> ) ; Register Base = BaseOp . getReg ( ) ; const MachineOperand & Reg0Op = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Reg1Op = MI . getOperand ( <NUM_LIT> ) ; if ( Reg0Op . getReg ( ) == Base || Reg1Op . getReg ( ) == Base ) return false ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( MergeInstr == MBB . end ( ) ) return false ; NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isLegalAddressImm ( NewOpc , Offset , TII ) ) return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr ) ; DebugLoc DL = MI


<s> void addUImm2Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_InstSyncBarrierOpt ) ; Op -> ISBOpt .


<s> getAssembler ( ) . setIsThumbFunc ( Func ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Func ) ; SD . setFlags ( SD . getFlags ( )


<s> else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_3 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; else if ( Features [ <STR_LIT> ] ) EFlags


<s> rtx rval , mem , oldval , newval , neg_bval , mod_s_rtx ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s_rtx = operands [ <NUM_LIT> ] ; mod_s = memmodel_from_int ( INTVAL ( mod_s_rtx ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ <NUM_LIT> ] : operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && aarch_mm_needs_acquire ( mod_s_rtx ) ; bool use_release = TARGET_HAVE_LDACQ && aarch_mm_needs_release ( mod_s_rtx ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; if ( TARGET_32BIT ) { cond = arm_gen_compare_reg ( NE , rval , oldval , neg_bval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_NE ( VOIDmode , rval , oldval ) ; if ( thumb1_cmpneg_operand ( oldval , SImode ) ) { rtx src = rval ; if ( ! satisfies_constraint_L ( oldval ) ) { gcc_assert ( satisfies_constraint_J ( oldval ) ) ; emit_move_insn ( neg_bval , rval ) ; src = neg_bval ; } emit_unlikely_jump ( gen_cbranchsi4_neg_late ( neg_bval , src , oldval , label2 , cond ) ) ; } else { emit_move_insn ( neg_bval , const1_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4_insn ( cond , rval , oldval , label2 ) ) ; } } arm_emit_store_exclusive ( mode , neg_bval , mem , newval , use_release ) ; if ( TARGET_32BIT ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , neg_bval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , neg_bval , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , neg_bval , const0_rtx , label1 )


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( DAG . getConstant ( i , BaseVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , MaskVT , & MaskVec [ <NUM_LIT> ] , MaskVec . size


<s> EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ I ] . OrigArgIndex ; assert ( Ins [ I ] . PartOffset == <NUM_LIT> ) ; while ( I + <NUM_LIT> != E && Ins [ I + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ I + <NUM_LIT> ] ; unsigned PartOffset = Ins [ I + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ I ; } } else InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA


<s> CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , IsFP , Op0 , Op1 , DAG ) ; if ( CondCode == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , CondCode , dl , DAG , Chain , IsSignaling ) ; if ( Chain ) Chain = EFLAGS . getValue ( <NUM_LIT> ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CondCode , dl , <STR_LIT> ) ; return


<s> static void ReplaceREADCYCLECOUNTER ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc DL ( N ) ; SDValue Cycles32 , OutChain ; if ( Subtarget -> hasPerfMon ( ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; OutChain = Cycles32 . getValue ( <NUM_LIT> ) ; } else { Cycles32 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; OutChain = DAG . getEntryNode ( ) ; } SDValue Cycles64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Results . push_back ( Cycles64 ) ; Results . push_back (


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { if ( const MCSymbolRefExpr * SRE = dyn_cast_or_null < MCSymbolRefExpr > ( Value ) ) { if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL && ! ( Size == <NUM_LIT> ) ) { getContext ( ) . reportError ( Loc , <STR_LIT> ) ; return ; } getOrCreateDataFragment ( ) ; } emitDataMappingSymbol ( ) ; MCELFStreamer :: emitValueImpl ( Value , Size , Loc


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setCallsEhReturn ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = IsN64 ? <STR_LIT> : <STR_LIT>


<s> __builtin_ia32_storedquqi512_mask ( ( __v64qi * ) __P , ( __v64qi )


<s> unsigned OrigSrc0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OrigSrc1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0 = <NUM_LIT> , SubReg0 ; unsigned Src1 = <NUM_LIT> , SubReg1 ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( Src0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) { assert ( Src0 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( Src1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) { assert ( Src1 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } if ( ! Src0 ) { SubReg0 = <NUM_LIT> ; Src0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src0 , OrigSrc0 , true ) ; } if ( ! Src1 ) { SubReg1 = <NUM_LIT> ; Src1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src1 , OrigSrc1 , true ) ; } unsigned Dst = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) , Dst ) . addReg ( Src0 , getKillRegState ( true ) , SubReg0 ) . addReg ( Src1 , getKillRegState ( true ) , SubReg1 ) ; insertCopy ( TII , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , Dst , true ) ; MI -> eraseFromParent ( ) ; ++ NumScalarInsnsUsed


<s> ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregciv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t


<s> unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal


<s> bool <ISA_LIT>BaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags


<s> Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB -> copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT>


<s> void <ISA_LIT>Subtarget :: overrideSchedPolicy ( MachineSchedPolicy &

Policy , unsigned NumRegionInstrs ) const {


<s> case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; } return false


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Cond , getZeroVector ( VT , Subtarget , DAG , dl ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getSelect ( dl , VT , Mask , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 (


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get


<s> if ( COMPARISON_P ( x ) && GET_MODE ( x ) == VOIDmode ) PUT_MODE ( x , SImode ) ; int insn_code = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; if ( insn_code < <NUM_LIT> && COMPARISON_P ( x ) ) { machine_mode cmp_mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; if ( cmp_mode == VOIDmode ) cmp_mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; PUT_CODE ( x , reverse_condition ( GET_CODE ( x ) ) ) ; insn_code = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; append_nott = true ; } gcc_assert ( insn_code >= <NUM_LIT> ) ; } std :: pair < rtx_insn * , rtx_insn * > insnlist = sh_try_split_insn_simple ( i , curr_insn ) ; recog_data = prev_recog_data ; rtx_insn * nott_insn = sh_is_nott_insn ( insnlist . second ) ? insnlist . second :


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode ==


<s> bool SelectAddrIdxOnly ( SDValue N , SDValue & Base , SDValue & Index ) { return <ISA_LIT>Lowering -> SelectAddressRegRegOnly ( N , Base , Index , *


<s> } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O


<s> <ISA_LIT>GNULDBackend :: initTargetSections ( pModule , pBuilder ) ; if ( LinkerConfig :: Object == config ( ) . codeGenType ( ) ) return ; ELFFileFormat * fileFormat = getOutputFormat ( ) ; LDSection & got = fileFormat -> getGOT ( ) ; m_pGOT = new <ISA_LIT>64GOT ( got ) ; LDSection & gotplt = fileFormat -> getGOTPLT


<s> int arm_no_early_store_addr_dep ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET


<s> unsigned getAddrMode6AddressOpValue ( const MachineInstr & MI ,


<s> return true ; } if ( ( mode_sz == <NUM_LIT> || mode_sz == <NUM_LIT> ) && ! ( TARGET_SH4 && mode == DFmode ) && adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = gen_rtx_PLUS ( Pmode , XEXP ( * p , <NUM_LIT> ) , adj . offset_adjust ) ; * p = gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; push_reload ( sum , NULL_RTX , & XEXP ( * p , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ; } } if ( GET_CODE ( * p ) == PLUS && ( mode_sz == <NUM_LIT> || mode_sz == <NUM_LIT> ) && GET_CODE ( XEXP ( * p , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( * p , <NUM_LIT> ) , <NUM_LIT> ) ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( XEXP (

* p , <NUM_LIT> ) , <NUM_LIT> ) , true ) && CONST_INT_P ( XEXP ( * p , <NUM_LIT> ) ) && ! ( TARGET_SH2E && mode == SFmode ) ) {


<s> const char * getPassName ( ) const override { return AARCH64_ADVSIMD_NAME


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C ,

RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ;


<s> unsigned get<ISA_LIT>RegNum ( const MCOperand


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; AFI -> setVarArgsFrameIndex (


<s> static DecodeStatus decodeShiftImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Offset = ( Insn &


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT>

<< getRegisterName ( MO2 . getReg ( ) ) << <STR_LIT> ;


<s> uint64_t EncVal = <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; else EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |=


<s> ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; } unsigned ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( Subtarget -> hasAVX ( ) ) MIB . addReg ( ImplicitDefReg ) ; MIB . addReg (


<s> bool isImm8s4 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . hasVarSizedObjects (


<s> MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase ( MBBI


<s> static MCStreamer * createWinCOFFStreamer ( MCContext & Ctx , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool IncrementalLinkerCompatible ) { return create<ISA_LIT>WinCOFFStreamer ( Ctx , TAB , OS

, Emitter , RelaxAll , IncrementalLinkerCompatible ) ;


<s> return ( __m128i ) __builtin_ia32_movdqa64load128_mask ( ( __v2di * ) __P , (


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI


<s> virtual const TargetData * getTargetData ( ) const { return & DataLayout


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel ::


<s> bool isVecListThreeQAllLanes ( ) const { if ( ! isDoubleSpacedVectorAllLanes (


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize

( FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle


<s> } startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; cum -> words += intregs ; if ( ( unsigned ) cum -> words < ( endbit / BITS_PER_WORD ) ) { int pad = ( endbit /


<s> return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> llvm :: cast < <ISA_LIT>_64GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin (


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: loongarch32 , false > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: loongarch64 , false > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT>


<s> Stub * <ISA_LIT>LA25Stub :: doClone ( ) { return new <ISA_LIT>LA25Stub ( m_Target , m_pData , m_Size , fixup_begin ( ) , fixup_end


<s> if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) ==


<s> assoc = associated_type ( decl ) ; if ( assoc && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( assoc ) ) && TREE_CODE ( decl ) == VAR_DECL && TREE_STATIC ( decl ) && TREE_PUBLIC ( decl ) && ! DECL_EXTERNAL ( decl ) && ! DECL_VIRTUAL_P ( decl ) )


<s> addMSAFloatType ( <STR_LIT> Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; if ( Ty !=


<s> return __builtin_ia32_ucomige ( ( __v4sf ) __A ,


<s> static SDValue LowerAVXExtend ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo ,


<s> if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId ( ) > Pos -> getNodeId ( ) ) { DAG -> RepositionNode ( Pos , N . getNode ( ) ) ; N . getNode ( ) -> setNodeId ( Pos -> getNodeId


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt


<s> if ( TARGET_32BIT ) { if ( TARGET_HARD_FLOAT_ABI && TARGET_VFP ) size +=


<s> if ( ! CE ) return false ; return isImmUnsignedi4Value ( CE -> getValue (


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo


<s> if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? <NUM_LIT> : <NUM_LIT> ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( zero_constant ( op , mode ) ) return <NUM_LIT> ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; } else if ( mode == V1TImode ) return <NUM_LIT> ; step = GET_MODE_NUNITS ( mode ) / <NUM_LIT> ; copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( vspltis_shifted ( op ) != <NUM_LIT> ) return GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; return <NUM_LIT>


<s> case E_V4QImode : case E_V2HQmode : case E_V2UHQmode : case E_V2HAmode : case E_V2UHAmode : case E_V4QQmode : case


<s> Target & llvm :: getThe<ISA_LIT>Target (


<s> assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT . is512BitVector ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; SDValue Ops [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; int MaxOp1Index = VT . getVectorNumElements ( ) / <NUM_LIT> - <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { if ( WidenedMask [ i ] == SM_SentinelZero ) return SDValue ( ) ; if ( WidenedMask [ i ] == SM_SentinelUndef ) continue ; SDValue Op = WidenedMask [ i ] > MaxOp1Index ? V2 : V1 ; unsigned OpIndex = ( i < Size / <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Ops [ OpIndex ] . isUndef ( ) ) Ops [ OpIndex ] = Op ; else if ( Ops [ OpIndex ] != Op ) return SDValue ( ) ; } unsigned PermMask = <NUM_LIT> , Imm = <NUM_LIT> ; unsigned ControlBitsNum = WidenedMask . size ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { Imm = ( WidenedMask [ i ] == SM_SentinelUndef ) ? <NUM_LIT> : WidenedMask [ i ] ; PermMask |= ( Imm % WidenedMask . size ( ) ) << ( i * ControlBitsNum ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , DAG . getConstant ( PermMask , DL ,


<s> unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg


<s> } EVT VecVT ; EVT EltVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( errs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB ->


<s> static __inline qword si_dfs ( qword a , qword b ) { union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] -


<s> return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> )


<s> const char * libName = TLI . getLibcallName ( VT == <STR_LIT> ? RTLIB :: FPTOSINT_F128_I32 : RTLIB :: FPTOSINT_F128_I64 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { unsigned Opc = MI . getOpcode ( ) ; const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; assert ( Opc == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( )

) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel (


<s> getAddrMode2OffsetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Imm = MO1 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isReg = MO . getReg ( ) != <NUM_LIT> ; uint32_t Binary = <STR_LIT> ( Imm ) ; if ( isReg ) { <STR_LIT> ShOp = <STR_LIT> ( Imm ) ; Binary <<= <NUM_LIT> ; Binary |= getShiftOp ( ShOp


<s> return ( vector signed int ) __builtin_altivec_vcmpgtuw ( ( vector signed


<s> <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue


<s> int32x4x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t )


<s> for ( unsigned i = OpNum + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; O << getRegisterName ( MI -> getOperand ( i ) . getReg ( ) ) ; } O <<


<s> if ( parseToken ( AsmToken :: Comma ) || check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer * TStreamer = static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ) ; if ( TStreamer != nullptr ) TStreamer -> emitLocalEntry ( Sym , Expr ) ; return


<s> __m128 a , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> static __inline qword si_fsm ( qword a ) { vec_uchar16 in ; vec_int4 mask ; in = ( vec_uchar16 ) ( a ) ; mask = ( vec_int4 ) ( vec_splat ( in , <NUM_LIT> ) ) ; return ( ( qword ) ( vec_sra ( vec_sl ( mask , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> bool SelectAddrImmShift ( SDValue N , SDValue & Disp , SDValue &


<s> return ( unsigned char ) __builtin_ia32_vec_ext_v16qi ( (


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass (


<s> switch ( Opc ) { case G_ADD : case G_SEXT : case G_ZEXT : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_LOAD : OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : assert ( ( Ty . getSizeInBits ( ) == <NUM_LIT> || Ty . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_SEQUENCE : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT> ) return InstructionMapping { } ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] ,

nullptr , & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ;


<s> return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , STI , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUX32 ) return new ELF<ISA_LIT>_X32AsmBackend ( T ,


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) switch ( N -> getOperand ( i ) . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT>


<s> return selectBDAddr ( <STR_LIT> , Addr , Base


<s> Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && Alignment > Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } } else if ( Alignment == Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } else { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT AddrVT = Dst . getValueType


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; continue ; } switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) { unsigned NewOpc ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } SDValue Res = CurDAG -> getNode ( NewOpc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; continue ; } } if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> useRetpolineIndirectCalls ( ) && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> slowTwoMemOps ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT>


<s> NumDataVectors = <NUM_LIT> ; NumPredicateVectors = Offset . getScalable ( ) / <NUM_LIT> ; if ( NumPredicateVectors % <NUM_LIT> == <NUM_LIT> || NumPredicateVectors < - <NUM_LIT> || NumPredicateVectors > <NUM_LIT> ) { NumDataVectors = NumPredicateVectors / <NUM_LIT> ; NumPredicateVectors -= NumDataVectors


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( matchAddress ( N , AM ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg

= CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> NumOpsAdded = <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; getImmShiftSE ( ShOp , ShImm ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( AddrOpcode ,


<s> const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static enum attr_itanium_class ia64_safe_itanium_class ( rtx_insn * insn ) { if ( recog_memoized ( insn ) >= <NUM_LIT> ) return get_attr_itanium_class ( insn ) ; else if ( DEBUG_INSN_P ( insn ) ) return


<s> static bool is_prefetch ( rtx insn ) { return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN


<s> if ( ! selectBDXAddr ( <STR_LIT> , <STR_LIT> , Op , Base , Disp , Index ) ) return true ; OutOps . push_back


<s> if ( ! isa < ExtractValueInst > ( Cond ) ) return false ; const auto * EV = cast < ExtractValueInst > ( Cond ) ; if ( ! isa < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ) return false ; const auto * II = cast < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ; MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start = I ; BasicBlock :: const_iterator End = II ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return false ; const auto * EVI = cast < ExtractValueInst > ( Itr ) ; if ( EVI -> getAggregateOperand ( )


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( ! is128BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) return - <NUM_LIT> ; int Rotation = matchShuffleAsElementRotate ( V1 , V2


<s> return ( CC == CallingConv :: Fast && GuaranteeTailCalls ) || CC

== CallingConv :: Tail || CC == CallingConv :: SwiftTail ;


<s> case AARCH64_BUILTIN_RSQRT_DF : gen = gen_rsqrtdf2 ; break ; case AARCH64_BUILTIN_RSQRT_SF : gen = gen_rsqrtsf2 ; break ; case AARCH64_BUILTIN_RSQRT_V2DF : gen = gen_rsqrtv2df2 ; break ; case AARCH64_BUILTIN_RSQRT_V2SF : gen = gen_rsqrtv2sf2 ; break ; case AARCH64_BUILTIN_RSQRT_V4SF : gen = gen_rsqrtv4sf2 ; break ; default : gcc_unreachable ( ) ; } if ( ! target ) target = gen_reg_rtx ( GET_MODE (


<s> const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if (


<s> if ( Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback ) { if ( IsPIC ) { intptr_t LazyPtr = getIndirectSymAddr ( Fn ) ; if ( ! LazyPtr ) { LazyPtr = ( intptr_t ) emitGlobalValueIndirectSym ( ( GlobalValue * ) F , Fn , JCE ) ; DEBUG ( if ( F ) errs ( ) << <STR_LIT> << LazyPtr << <STR_LIT> << F -> getName ( ) << <STR_LIT> ; else errs ( ) << <STR_LIT> << LazyPtr << <STR_LIT> << Fn << <STR_LIT> ) ; } JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( LazyPtr - ( intptr_t ( Addr ) + <NUM_LIT> + <NUM_LIT> ) ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } else { JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } } else { JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) <ISA_LIT>CompilationCallback ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } return


<s> static bool expand_vec_perm_identity ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i ) return false ; if ( ! d -> testing_p ) emit_move_insn (


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII

. get ( Opc ) , DestReg ) . addReg ( FPReg ) ;


<s> else if ( REG_P ( src ) && MEM_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_store [ <NUM_LIT> ] - ix86_cost -> sse_store [ <NUM_LIT> ] ; else if ( MEM_P ( src ) && REG_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_load [ <NUM_LIT> ] - ix86_cost -> sse_load [ <NUM_LIT> ] ; else if ( GET_CODE ( src ) == ASHIFT || GET_CODE ( src ) == LSHIFTRT ) { gain += ix86_cost -> shift_const ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && INTVAL ( XEXP ( src , <NUM_LIT> ) ) >= <NUM_LIT> ) gain -= COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( GET_CODE ( src ) == PLUS || GET_CODE ( src ) == MINUS || GET_CODE ( src ) == IOR || GET_CODE ( src ) == XOR || GET_CODE ( src ) == AND ) { gain += ix86_cost -> add


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * TFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> adjustsStack ( ) ) { TFI -> setRAStackOffset ( <NUM_LIT> ) ; MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; } if ( hasFP ( MF ) ) { TFI -> setFPStackOffset ( <NUM_LIT> ) ; MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true


<s> unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] .


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; float FPImm = MO . isDFPImm ( ) ? bit_cast < double > ( MO . getDFPImm ( ) ) : <STR_LIT> ( MO


<s> Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX =


<s> SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , PtrVT ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , GRTop , DAG . getConstant ( GPRSize , DL , PtrVT ) ) ; GRTop = DAG . getZExtOrTrunc ( GRTop , DL , PtrMemVT ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , Offset ) , Align ( PtrSize ) ) ) ; } Offset += PtrSize ; int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop , VRTopAddr ; VRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; VRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsFPRIndex ( ) , PtrVT ) ; VRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , VRTop , DAG . getConstant ( FPRSize , DL , PtrVT ) ) ; VRTop = DAG . getZExtOrTrunc ( VRTop , DL , PtrMemVT ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , VRTop , VRTopAddr , MachinePointerInfo ( SV , Offset ) , Align ( PtrSize ) ) ) ; } Offset += PtrSize ; SDValue GROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - GPRSize , DL , <STR_LIT> ) , GROffsAddr , MachinePointerInfo ( SV , Offset ) , Align ( <NUM_LIT> ) ) ) ; Offset += <NUM_LIT> ; SDValue VROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - FPRSize , DL , <STR_LIT> ) , VROffsAddr , MachinePointerInfo ( SV , Offset ) , Align ( <NUM_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> __v2du rshift ; __v2di result = { <NUM_LIT> , <NUM_LIT> } ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) { if ( __B < <NUM_LIT> ) rshift = ( __v2du ) vec_splat_s32 ( __B ) ; else rshift = ( __v2du ) vec_splats ( ( unsigned long long ) __B ) ; } else rshift = ( __v2du ) vec_splats ( ( unsigned int ) __B


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case


<s> BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( GPRSaveLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( GPRSaveLabel , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , SPOffsetFromCFA + Delta ) ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MCSymbol * SetFPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( SetFPLabel ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( SetFPLabel , HardFP ) ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } MCSymbol * FPRSaveLabel = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT>


<s> while ( -- numregs ) ; ca -> call_cookie |= CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - <NUM_LIT> , <NUM_LIT> ) ; } else if ( dwords > numregs ) { int pushregs = numregs ; if ( TARGET_SHCOMPACT ) ca -> stack_regs += numregs ; while ( pushregs < NPARM_REGS ( SImode ) - <NUM_LIT> && ( CALL_COOKIE_INT_REG_GET ( ca -> call_cookie , NPARM_REGS ( SImode ) - pushregs ) == <NUM_LIT> ) ) { ca -> call_cookie &= ~ CALL_COOKIE_INT_REG ( NPARM_REGS ( SImode ) - pushregs , <NUM_LIT> ) ; pushregs ++ ; } if ( numregs == NPARM_REGS ( SImode ) ) ca -> call_cookie |= CALL_COOKIE_INT_REG ( <NUM_LIT> , <NUM_LIT> ) | CALL_COOKIE_STACKSEQ ( numregs - <NUM_LIT> ) ; else ca -> call_cookie |= CALL_COOKIE_STACKSEQ ( numregs ) ; } } if ( GET_SH_ARG_CLASS ( mode2 ) == SH_ARG_FLOAT && ( named || ! ca -> prototype_p ) ) { if ( mode2 == SFmode && ca -> free_single_fp_reg ) ca -> free_single_fp_reg = <NUM_LIT> ; else if ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { int numfpregs = MIN ( ( GET_MODE_SIZE ( mode2 ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> , NPARM_REGS ( SFmode ) - ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; ca -> arg_count [ ( int ) SH_ARG_FLOAT ] += numfpregs ; if ( TARGET_SHCOMPACT && ! ca -> prototype_p ) { if ( ca -> outgoing && numregs > <NUM_LIT> ) do { ca -> call_cookie |= ( CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - numregs + ( ( numfpregs - <NUM_LIT> ) / <NUM_LIT> ) , <NUM_LIT> + ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] - numfpregs ) / <NUM_LIT> ) ) ; } while ( numfpregs -= <NUM_LIT> ) ; } else if ( mode2 == SFmode && ( named ) && ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) ) ca -> free_single_fp_reg = FIRST_FP_PARM_REG - numfpregs + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] + <NUM_LIT> ; } } return ; } if ( ( TARGET_HITACHI || ca -> renesas_abi


<s> static __inline vec_double2 spu_slqw ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbi ( ( qword ) ( a ) , si_from_uint ( count


<s> if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class !=


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . getReg ( ) == <NUM_LIT>


<s> return 'w' ; case <NUM_LIT> : return 'h' ; case <NUM_LIT> : return 'b'


<s> static void ix86_emit_move_max ( rtx dst


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG

-> getDataLayout ( ) ) ) . getNode ( ) ;


<s> x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == UNSPEC_VOLATILE && XINT ( x , <NUM_LIT> ) == VUNSPEC_POOL_LABEL ) { ASM_GENERATE_INTERNAL_LABEL ( buf , CSKY_CONSTPOOL_LABEL_PREFIX , INTVAL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ) ; assemble_name ( stream , buf


<s> int maximum_bytes ; if ( TARGET_REDUCED_REGS ) maximum_bytes = <NUM_LIT> ; else maximum_bytes = <NUM_LIT> ; if ( GET_CODE ( total_bytes ) != CONST_INT || GET_CODE ( alignment ) != CONST_INT || INTVAL ( total_bytes ) > maximum_bytes || INTVAL ( total_bytes ) & <NUM_LIT> || INTVAL ( alignment ) & <NUM_LIT> ) return <NUM_LIT> ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , <NUM_LIT> ) ) ; out_words = in_words = INTVAL ( total_bytes ) /


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ?


<s> arm_configure_build_target ( & arm_active_target , ptr , opts_set , false


<s> return isSImm < <NUM_LIT> > ( ) && ! isUImm12Offset < Width / <NUM_LIT> > (


<s> return ( float32x4_t ) __builtin_neon_vmul_lanev4sf ( __a ,


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && IsComplex ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> const DataLayout * getDataLayout ( ) const override { return & DL


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( getRelocationModel ( ) == Reloc :: Default ) setRelocationModel ( Reloc ::


<s> const InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector


<s> const <ISA_LIT>Subtarget * ST = TPC . getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( F ) ; if ( ST -> getProcFamily ( ) != <ISA_LIT>Subtarget :: Falkor ) return false ; if ( skipFunction ( F ) ) return false ; LoopInfo & LI = getAnalysis < LoopInfoWrapperPass


<s> bool IsRightShift ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; } if ( IsRightShift && ShiftAmount <= - <NUM_LIT> && ShiftAmount >= - ( int ) ElemBits ) { SDLoc dl ( N ) ; return DAG . getNode ( Opcode , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - ShiftAmount , dl , <STR_LIT> ) ) ; } else if ( ! IsRightShift && ShiftAmount >= <NUM_LIT> && ShiftAmount


<s> rtx_insn * insn ; if ( optimize_size ) return <NUM_LIT> ; insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> &&


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } SDValue Pred = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( is64BitVector ) { unsigned Opc = DOpcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; std :: vector < EVT > ResTys ( NumVecs , VT ) ; ResTys . push_back ( <STR_LIT> ) ; return CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; } EVT RegVT = GetNEONSubregVT ( VT ) ; if ( NumVecs <= <NUM_LIT> ) { unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; std :: vector < EVT > ResTys ( <NUM_LIT> * NumVecs , RegVT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; Chain = SDValue ( VLd , <NUM_LIT> * NumVecs ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDNode * Q = PairDRegs ( VT , SDValue ( VLd , <NUM_LIT> * Vec ) , SDValue ( VLd , <NUM_LIT> * Vec + <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , Vec ) , SDValue ( Q , <NUM_LIT> ) ) ; } } else { std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( MemAddr


<s> if ( Kind == TTI :: SK_Broadcast ) { static const CostTblEntry NEONDupTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONDupTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; } if ( Kind == TTI :: SK_Reverse ) { static const CostTblEntry NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ) return


<s> if ( ! Splat ) return false ; if ( Splat -> isReg ( ) ) return true ; int64_t Cst = Splat -> getCst ( ) ; return ( Cst != <NUM_LIT> && Cst != -


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) .


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind ::


<s> if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else if ( TARGET_64BIT ) arg = function_arg_64 ( cum , mode , omode , type , named ) ; else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; return arg


<s> MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } else llvm_unreachable


) == MODE_FLOAT || GET_MODE_CLASS ( mode2 ) == MODE_COMPLEX_FLOAT ) ) ;


<s> for ( int i = NumElems / <NUM_LIT> , j = <NUM_LIT> ; i < NumElems ; ++ i , ++ j ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , j ) || SVOp -> getMaskElt ( j ) >= <NUM_LIT> ) return false ; return


<s> unsigned HOST_WIDE_INT df_mantissa = value & ( ( HOST_WIDE_INT_1U << <NUM_LIT> ) - HOST_WIDE_INT_1U ) ; if ( df_exponent == <NUM_LIT> && df_mantissa != <NUM_LIT> ) return <NUM_LIT> ; if ( df_exponent == <NUM_LIT> && df_mantissa != <NUM_LIT> ) return <NUM_LIT> ; } long df_words [ <NUM_LIT> ] = { vsx_const -> words [ <NUM_LIT> ] , vsx_const -> words [ <NUM_LIT> ] } ; if ( ! BYTES_BIG_ENDIAN ) std :: swap ( df_words [ <NUM_LIT> ] , df_words [ <NUM_LIT>


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI

. getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> OS << ABIFlagsSection . getFpABIString ( ABIFlagsSection . getFpABI


<s> return ( __mmask8 ) __builtin_ia32_cmpd128_mask ( ( __v4si ) __X , ( __v4si )


<s> return __builtin_mve_vcmpcsq_n_uv16qi ( __a ,


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> RegisterTargetMachine < <ISA_LIT>32TargetMachine > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = *


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> int constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; int align ; int bytes ; int offset ; int move_bytes ; rtx stores [ MAX_MOVE_REG ] ; int num_reg = <NUM_LIT> ; if ( ! constp ) return <NUM_LIT> ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( bytes > rs6000_block_move_inline_limit ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += move_bytes , bytes -= move_bytes ) { union { rtx ( * movmemsi ) ( rtx , rtx , rtx , rtx ) ; rtx ( * mov ) ( rtx , rtx ) ; } gen_func ; machine_mode mode = BLKmode ; rtx src , dest ; if ( TARGET_ALTIVEC && bytes >= <NUM_LIT> && align >= <NUM_LIT> ) { move_bytes = <NUM_LIT> ; mode = V4SImode ; gen_func . mov = gen_movv4si ; } else if ( TARGET_SPE && bytes >= <NUM_LIT> && align >= <NUM_LIT> ) { move_bytes = <NUM_LIT> ; mode = V2SImode ; gen_func . mov = gen_movv2si ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_8reg ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_6reg ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_4reg ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = DImode ; gen_func . mov


<s> rtx_insn * first_insn ( void ) const


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; NumCBrFixed ++ ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DOUT ( llvm :: dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBSizes [ MI -> getParent ( ) -> getNumber ( ) ] -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent