<s> } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) CommuteVectorShuffleMask ( RMask , NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; unsigned Src = ( i / HalfLaneElts ) % <NUM_LIT> ; unsigned LaneStart = ( i / NumLaneElts ) * NumLaneElts ; int Index = <NUM_LIT> * ( i % HalfLaneElts ) + NumElts * Src + LaneStart ; if ( ! ( LIdx == Index && RIdx == Index + <NUM_LIT> ) && ! ( IsCommutative && LIdx == Index + <NUM_LIT> && RIdx == Index ) ) return false ; } LHS = A . getNode ( ) ? A : B ; RHS = B . getNode (


<s> SDLoc dl ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return Op ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; unsigned SubVecNumElems = SubVecVT . getVectorNumElements ( ) ; assert ( IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( OpVT ) ; SDValue WideSubVec = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; if ( Vec . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , WideSubVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( <STR_LIT> ( Vec . getNode ( ) ) ) { unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; WideSubVec = DAG . getNode ( <STR_LIT> , dl , OpVT , WideSubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; return ShiftRight ? DAG . getNode ( <STR_LIT> , dl , OpVT , WideSubVec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) : WideSubVec ; } if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( SubVecNumElems


<s> deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> )

&& ix86_builtins_isa [ i ] . set_and_not_built_p ) {


<s> bool hasMessageSecurityAssist3 ( ) const


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useDwarfDirectory

, MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> void <ISA_LIT>MachObjectWriter :: RecordTLVPRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { assert ( Target . getSymA ( ) -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP && ! is64Bit ( ) && <STR_LIT> ) ; unsigned Log2Size = getFixupKindLog2Size ( Fixup . getKind ( ) ) ; uint32_t Value = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel =


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val & <NUM_LIT>


<s> const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( N ) ; <ISA_LIT>ISelAddressMode AM ; AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , N . getValueType ( ) ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> ) { AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; }


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> if ( ! TARGET_QUAD_MEMORY ) ret = false ; else if ( REG_P ( op0 ) && MEM_P ( op1 ) ) ret = ( quad_int_reg_operand ( op0 , GET_MODE ( op0 ) ) && quad_memory_operand ( op1 , GET_MODE ( op1 ) ) && ! reg_overlap_mentioned_p ( op0 , op1 ) ) ; else if ( MEM_P ( op0 ) && REG_P ( op1 ) ) ret = ( quad_memory_operand ( op0 , GET_MODE

( op0 ) ) && quad_int_reg_operand ( op1 , GET_MODE ( op1 ) ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) { MCInst I ; I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: createReg (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> static void matchLDPSTPAddrMode ( Register Root , Register & Base , int & Offset , MachineRegisterInfo & MRI ) { Base = Root


<s> rtx x ; cmp_op0 = force_reg ( mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , mode ) ) cmp_op1 = force_reg ( mode , cmp_op1 ) ; if ( optimize || reg_overlap_mentioned_p ( dest , op_true ) || reg_overlap_mentioned_p ( dest , op_false ) ) dest = gen_reg_rtx ( mode ) ; x = gen_rtx_fmt_ee ( code , mode , cmp_op0


<s> static bool scalar_to_vector_candidate_p ( rtx_insn * insn


<s> return Opcode == Instruction :: Load ? SVEGatherOverhead :


<s> unsigned LastLoadedElt ; if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EltVT , LD , LastLoadedElt , DAG , MFI , TLI ) ) return SDValue ( ) ; if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LD -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LD -> getChain


<s> bool <ISA_LIT>AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand


<s> TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( DotExpr ) ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( PICBase , OutContext ) ) ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: createImm ( <NUM_LIT> ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; OutStreamer -> EmitLabel ( PICBase ) ; return ; } } if ( MI -> isInsideBundle ( ) ) OutStreamer -> AddComment ( <STR_LIT> ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && ( ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) ) OutStreamer -> AddComment ( <STR_LIT> ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI ,


<s> return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Ty -> isVectorTy ( ) && cast < VectorType > ( Ty ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) < ProfitableNumElements ) { unsigned NumVecElts = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts * <NUM_LIT> ; return NumVectorizableInstsToAmortize * NumVecElts * <NUM_LIT> ; } } return LT .


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt ::


<s> SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode ( <STR_LIT> ,


<s> assert ( MIa . mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB =


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i

] . Tag == Attribute ) return & Contents [ i ] ;


<s> bool isReorder ( ) const { return Reorder


<s> return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ,


<s> unsigned ZReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; return FastEmitInst_r ( Opc , TLI . getRegClassFor ( VT )


<s> } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind =


<s> return ( __m256i ) __builtin_ia32_psrlv8si ( ( __v8si ) __X , ( __v8si )


<s> return ( __m512 ) __builtin_ia32_loadups512_mask ( ( const float * ) __P ,


<s> } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return nullptr ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; Done = true ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; LoadedVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , LoadedVal , SubReg ) , <NUM_LIT> ) ; } ReplaceUses ( SDValue ( N , <NUM_LIT>


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT>

) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: printAddrMode3OffsetOperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm


<s> return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo

< <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> else bss_data = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_data , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size ( ) + size ) ; ResolveInfo :: Binding binding = ( ResolveInfo :: Binding ) pSym . binding ( ) ; if ( binding == ResolveInfo :: Weak ) binding = ResolveInfo :: Global ; LDSymbol * cpy_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( pSym . name ( ) , ( ResolveInfo :: Type ) pSym . type ( ) , ResolveInfo :: Define , binding , pSym . size ( ) , <NUM_LIT> , FragmentRef :: Create ( * frag , <NUM_LIT> ) , ( ResolveInfo :: Visibility ) pSym . other ( ) ) ; return * cpy_sym


<s> BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; BranchTargetNoTraps = <NUM_LIT> ; TOut . emitRRI ( <STR_LIT> , RtReg , ZeroReg , BranchTargetNoTraps , IDLoc , STI ) ; } TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; if ( ! UseTraps ) TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; if ( ! Signed ) { TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TOut . emitRRI ( <STR_LIT> , ATReg , ZeroReg , - <NUM_LIT> , IDLoc , STI ) ; if ( Is<ISA_LIT>64 ) { TOut . emitRRI ( <STR_LIT> , RtReg , ATReg , BranchTarget , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; } else { TOut . emitRRI ( <STR_LIT> , RtReg , ATReg , BranchTarget , IDLoc , STI ) ; TOut . emitRI ( <STR_LIT> , ATReg , ( uint16_t ) <NUM_LIT> , IDLoc , STI ) ; } if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , RsReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , RsReg , ATReg , BranchTargetNoTraps , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; } TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF

, const MCAsmLayout & Layout ) const override {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT>


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl


<s> unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_expandloadsi512_mask ( ( const __v16si * ) __P , ( __v16si


<s> rtx_insn * insn = DF_INSN_UID_GET ( insn_uid ) -> insn ; rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( REG_P ( src ) && REG_P ( dst ) ) gain += COSTS_N_INSNS ( <NUM_LIT> ) - ix86_cost -> xmm_move ; else if ( REG_P ( src ) && MEM_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_store [ <NUM_LIT> ] - ix86_cost -> sse_store [ <NUM_LIT> ] ; else if ( MEM_P ( src ) && REG_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_load [ <NUM_LIT> ] - ix86_cost -> sse_load [ <NUM_LIT> ] ; else if ( GET_CODE ( src ) == ASHIFT || GET_CODE ( src ) == ASHIFTRT || GET_CODE ( src ) == LSHIFTRT ) { if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; gain += ix86_cost -> shift_const ; if ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) >= <NUM_LIT> ) gain -= COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( GET_CODE ( src ) == PLUS || GET_CODE ( src ) == MINUS || GET_CODE ( src ) == IOR || GET_CODE ( src ) == XOR || GET_CODE ( src ) == AND ) { gain += ix86_cost -> add ; if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == NOT && ! TARGET_BMI ) gain += <NUM_LIT> * ix86_cost -> add ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; } else if ( GET_CODE ( src ) == NEG || GET_CODE ( src ) == NOT ) gain += ix86_cost -> add - COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_CODE ( src ) == COMPARE ) { } else if ( CONST_INT_P ( src ) ) { if ( REG_P ( dst ) ) gain += COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( MEM_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_store [ <NUM_LIT> ] - ix86_cost -> sse_store [ <NUM_LIT> ] ; gain -= vector_const_cost ( src ) ; } else gcc_unreachable ( ) ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , gain ) ; EXECUTE_IF_SET_IN_BITMAP ( defs_conv , <NUM_LIT> , insn_uid , bi ) cost += DF_REG_DEF_COUNT ( insn_uid ) * ix86_cost -> mmxsse_to_integer ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , cost ) ; gain -= cost ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ,


<s> virtual const <ISA_LIT>ELFWriterInfo * getELFWriterInfo ( ) const { return &


<s> std :: swap ( d -> op0 , d -> op1 ) ; location = d -> perm . length ( ) . to_constant ( ) - location ; } offset = GEN_INT ( location ) ; emit_set_insn ( d -> target , gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d ->

op0 , d -> op1 , offset ) , UNSPEC_EXT ) ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , AFI ( NULL ) , MCP ( NULL ) { Subtarget = & TM . getSubtarget <


<s> MaskNode = peekThroughBitcasts ( MaskNode ) ; MVT VT = MaskNode . getSimpleValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; auto SplitElementToMask = [ & ] ( APInt Element ) { int Split = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; for ( int i = <NUM_LIT> ; i < Split ; ++ i ) { APInt RawElt = Element . getLoBits ( MaskEltSizeInBits ) ; Element = Element . lshr ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; } } ; if ( MaskNode . getOpcode ( ) == <STR_LIT> ) { if ( VT . getScalarSizeInBits ( ) != MaskEltSizeInBits ) return false ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskNode . getOperand ( <NUM_LIT> ) ) ) { APInt MaskElement = CN -> getAPIntValue ( ) ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { APInt RawElt = MaskElement . getLoBits ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; } } return false ; } if ( MaskNode . getOpcode ( ) == <STR_LIT> && MaskNode . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; SDValue MaskOp = MaskNode . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskOp ) ) { SplitElementToMask ( CN -> getAPIntValue


<s> const MachineFrameInfo * MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != <STR_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; int64_t Length = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( <NUM_LIT> ) .


<s> unsigned Width ; return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset ,


<s> if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) )


<s> SDValue SelectOp2 = Select -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) std :: swap ( SelectOp1 , SelectOp2 ) ; if ( ! ( SelectOp2 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SelectOp2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) && SelectOp2 . getOperand ( <NUM_LIT> ) == SelectOp1 ) ) return false ; if ( SetCC . getOperand ( <NUM_LIT> ) != SelectOp1 ) return false ; APInt SplatVal ; if ( ( CC == <STR_LIT> ) && ! ( ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal , false ) && SplatVal

. isOneValue ( ) ) || ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ) return false ;


<s> BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ; } } else if ( BinOpcode ) BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; else if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> - BitSize ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal

) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitFMSTAT (


<s> for ( int regnum = <NUM_LIT> ; regnum < <NUM_LIT> ; ++ regnum ) { tree decl = aarch64_sls_shared_thunks [ regnum ] ; if ( ! decl ) continue ; const char * name = indirect_symbol_names [ regnum ] ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; ASM_OUTPUT_ALIGN ( out_file , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( out_file , name , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( out_file , name ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; asm_fprintf ( out_file


<s> unsigned RegNo = TRI -> getEncodingValue ( MO . getReg ( ) ) ; UsedRegMask &= ~ ( <NUM_LIT> << ( <NUM_LIT> - RegNo ) ) ; } } if ( UsedRegMask == <NUM_LIT> ) { RemoveVRSaveCode ( MI ) ; return ; } unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) .


<s> if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( Disp ) ; else MCE . emitWordLE ( ( int32_t ) Disp


<s> bool IsPositionIndependent = isPositionIndependent ( ) || Subtarget -> isROPI ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , Align ( <NUM_LIT> ) ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV ,


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID :

& MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ;


<s> tree ix86_handle_shared_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != VAR_DECL ) { warning ( OPT_Wattributes , <STR_LIT> ,


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain ,


<s> EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , InVT ) ; SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; auto ScalableRes = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return convertFromScalableVector ( DAG , VT , ScalableRes


<s> const MachineOperand & ValReg = I -> getOperand ( <NUM_LIT> ) ; unsigned LoReg = TRI . getSubReg ( ValReg . getReg ( ) , <STR_LIT> ) ; unsigned HiReg = TRI . getSubReg ( ValReg . getReg ( ) , <STR_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ) std :: swap ( LoReg , HiReg ) ; MachineInstrBuilder MIB = genInstrWithNewOpc ( OpcS , I ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( LoReg ) ; MIB = genInstrWithNewOpc ( OpcS , I ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg (


<s> MachineInstr & MI = * I ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++


<s> uint64_t Selector = cast < ConstantInt > ( COp ) -> getZExtValue ( ) ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; if ( ( M2Z & <NUM_LIT> ) != <NUM_LIT> && MatchBit != ( M2Z & <NUM_LIT> ) ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } int Index = i & ~ ( NumElementsPerLane - <NUM_LIT> ) ; if ( ElSize == <NUM_LIT> ) Index += ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; else Index += Selector & <NUM_LIT> ; int Src = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; Index += Src * NumElements ; ShuffleMask . push_back ( Index )


<s> static void concatenateMemOperands ( MachineInstr * MI , MachineInstr * Op0 , MachineInstr * Op1 ) { assert ( MI -> memoperands_empty ( ) && <STR_LIT> ) ; size_t numMemRefs = ( Op0 -> memoperands_end ( ) - Op0 -> memoperands_begin ( ) ) + ( Op1 -> memoperands_end ( ) - Op1 -> memoperands_begin ( ) ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineSDNode :: mmo_iterator MemBegin = MF -> allocateMemRefsArray ( numMemRefs ) ; MachineSDNode :: mmo_iterator MemEnd = std :: copy ( Op0 -> memoperands_begin ( ) , Op0 -> memoperands_end ( ) , MemBegin ) ; MemEnd = std :: copy ( Op1 -> memoperands_begin ( ) , Op1 -> memoperands_end ( ) ,


<s> static __inline qword si_iohl ( qword a , unsigned short imm ) { return ( ( qword ) ( vec_or ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) (

si_from_uint ( ( unsigned int ) ( imm ) ) ) , <NUM_LIT> ) ) ) ) ;


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , MemIntr -> getMemoryVT


<s> if ( GET_CODE ( const_vector ) == SYMBOL_REF ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; rtx new_mem ; enum machine_mode mode = GET_MODE ( const_vector ) ; if ( mode == V1TImode ) return ; else if ( mode == V16QImode ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V8HImode ) || ( mode == V8HFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V4SImode ) || ( mode == V4SFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V2DImode ) || ( mode == V2DFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else { gcc_unreachable (


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; return splitAndLowerVectorShuffle ( DL , <STR_LIT> , V1 , V2 ,


<s> static const LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; const unsigned NumClasses = llvm :: array_lengthof (


<s> SDValue <ISA_LIT>DAGToDAGISel :: createZTuple ( ArrayRef < SDValue > Regs ) { static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs ,


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( auto * Op = dyn_cast < ConstantSDNode > (

N -> getOperand ( <NUM_LIT> ) ) ) return Op -> getZExtValue ( ) == <NUM_LIT> ;


<s> if ( REG_P ( x ) && ( mode == TFmode || mode == TImode ) && mode == GET_MODE ( x ) && FP_REGNUM_P ( REGNO ( x ) ) && ! TARGET_SIMD && reg_class_subset_p ( rclass , FP_REGS ) ) { if ( mode == TFmode ) sri -> icode = CODE_FOR_aarch64_reload_movtf ; else if ( mode == TImode ) sri -> icode


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> bool DestIsHigh = isHighReg ( DestReg ) ; bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get ( LowOpcode ) ) ; else if ( DestIsHigh && SrcIsHigh ) MI .


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler


<s> } mode = GET_MODE ( XEXP ( comparison , <NUM_LIT> ) ) ; op0 = force_reg ( mode , op0 ) ; if ( ! ( ISA_HAS_COND_TRAPI ? arith_operand ( op1 , mode ) : reg_or_0_operand ( op1

, mode ) ) ) op1 = force_reg ( mode , op1 ) ;


<s> return isImmScaled < Bits , Scale > (


<s> int64_t ImmVal ; if ( SignedCmp ) ImmVal = ( short ) MO . getImm ( ) ; else ImmVal = MO . getImm ( ) ; const MachineInstr * IV_DefInstr = MRI -> getVRegDef ( IV_Opnd -> getReg ( ) ) ; assert ( L -> contains ( IV_DefInstr -> getParent ( ) ) && <STR_LIT> ) ; int64_t iv_value = ( short ) IV_DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InitialValue -> isReg ( ) && <STR_LIT> ) ; unsigned InitialValueReg = InitialValue -> getReg ( ) ; MachineInstr * DefInstr = MRI -> getVRegDef ( InitialValueReg ) ; if ( DefInstr && ( DefInstr -> getOpcode ( ) == <STR_LIT> || DefInstr -> getOpcode ( ) == <STR_LIT> ) ) { int64_t start = ( short ) DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * DefInstr2 = MRI -> getVRegDef ( DefInstr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DefInstr2 && ( DefInstr2 -> getOpcode ( ) == <STR_LIT> || DefInstr2 -> getOpcode ( ) == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr2 ) ; start |= int64_t ( short ( DefInstr2 -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) << <NUM_LIT> ; int64_t count = ImmVal - start ; if ( ( count % iv_value ) != <NUM_LIT> ) { return <NUM_LIT> ; } OldInsts . push_back ( DefInstr ) ; OldInsts . push_back ( DefInstr2 ) ; if ( Int64Cmp ) return new CountValue ( count / iv_value ) ; else return new CountValue ( uint32_t ( count / iv_value ) ) ; } } else if ( DefInstr && ( DefInstr -> getOpcode ( ) == <STR_LIT> || DefInstr -> getOpcode ( ) == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr ) ; int64_t count = ImmVal - int64_t ( short ( DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; if ( ( count % iv_value ) !=


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSizeInsEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo - <NUM_LIT> ) . isImm ( ) ) ; assert ( MI . getOperand ( OpNo ) . isImm


<s> EVT VT = Op . getValueType ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; EVT LoVT ,


<s> void printSrcIdx8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printSrcIdx ( MI , OpNo , O


<s> oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; if ( ! TARGET_SYNC_HI_QI ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; oldval = expand_simple_binop ( SImode , ASHIFT , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; if ( mode != TImode && ! reg_or_short_operand ( oldval , mode ) ) oldval = copy_to_mode_reg ( mode , oldval ) ; if ( reg_overlap_mentioned_p ( retval , newval ) ) newval = copy_to_reg ( newval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; cond = gen_reg_rtx (


<s> bool hasInterlockedAccess1 ( ) const { return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ; } if ( Subtarget . hasAltivec ( )


<s> bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; Imm = SplatValue ; return


<s> pcmpeqw_s ( int32x2_t s , int32x2_t t ) { return __builtin_loongson_pcmpeqw_s ( s


<s> bool Thumb1RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF )


<s> MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br


<s> return ( __m512i ) __builtin_ia32_vpmadd52huq512_mask ( ( __v8di ) __X , ( __v8di )


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand (


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , const TargetOptions & Options ) { return <STR_LIT>


<s> assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent ( ) ; return true


<s> bool isZExt = isa < ZExtInst > ( I ) ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT


<s> else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |= <STR_LIT> ( AM2Opc ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO2 . getReg ( ) ) ) ; Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( AM2Opc ) ) { Binary |= getShiftOp ( AM2Opc ) << <STR_LIT> ; Binary |= ShImm << <STR_LIT>


<s> MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return <NUM_LIT> ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( &


<s> switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt (


<s> auto * STy = dyn_cast < StructType > ( Val -> getType ( ) ) ; IRBuilder < > Builder ( & * II ) ; Ptr = Builder . CreateBitCast ( Ptr , STy -> getElementType ( <NUM_LIT> ) -> getPointerTo ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < STy ->


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true


<s> return __builtin_mve_vrshlq_sv16qi ( __a ,


<s> if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode )


<s> static inline uint8_t encodeAdvSIMDModImmType6 ( uint64_t Imm ) { return ( Imm & <NUM_LIT> )


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool TwoReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool NoDstReg = ( decodeRs ( insn ) == <NUM_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , NoDstReg ? decodeRn ( insn ) : decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm ( imm12 ) ) ) ; ++


<s> } else { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) .


<s> std :: map < unsigned , IntrinsicData > :: const_iterator

itr = IntrWithChainMap . find ( IntNo ) ;


<s> bool <ISA_LIT>GOT :: dynSymOrderCompare ( const LDSymbol * pX , const LDSymbol * pY ) const { SymbolOrderMapType :: const_iterator itX = m_SymbolOrderMap . find ( pX ) ; SymbolOrderMapType :: const_iterator itY = m_SymbolOrderMap . find ( pY ) ; if ( itX != m_SymbolOrderMap . end ( ) && itY != m_SymbolOrderMap . end ( ) ) return


<s> getAddrModeImm12OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm12 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; isAdd = false ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset ; } } else isAdd = EncodeAddrModeOpValues ( MI ,


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Value = CE -> getValue ( ) ; if ( Inv ) Value = ~ Value ; unsigned B = Value & <NUM_LIT> ; B |=


<s> case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case


<s> unsigned Opc = N -> getMachineOpcode ( ) ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static SDValue LowerCTLZ_ZERO_UNDEF ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; EVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_M44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_L44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HH22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HM10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_HIX22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_LOX10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LD ; case <STR_LIT> : return ELF


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return false ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return false ; if ( Opc [ i % <NUM_LIT> ] != <NUM_LIT> && Opc [ i % <NUM_LIT> ] != Opcode ) return false ; Opc [ i % <NUM_LIT> ] = Opcode ; if ( InVec0 . isUndef ( ) ) { InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec0 . getSimpleValueType ( ) != VT )


<s> return ( __m128 ) __builtin_ia32_movsldup128_mask ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) ,


<s> return ST -> isPICStyleGOT ( ) && TM .

getRelocationModel ( ) == Reloc :: PIC_ ;


<s> if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( const MachineFunction & MF ,


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base ,


<s> case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else


<s> if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF ::


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> )


<s> } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ; } else


<s> Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = std :: max ( ArgSize , MinSlotSize ) ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; VANext = DAG . getZExtOrTrunc ( VANext , DL , PtrMemVT ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) ) ; SDValue NarrowFP = DAG . getNode ( <STR_LIT> , DL , VT , WideFP . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Ops [ ] = { NarrowFP ,


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel ( )


<s> get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( global_offset_table_rtx , sparc_got ( ) , got_helper_rtx , GEN_INT ( GLOBAL_OFFSET_TABLE_REGNUM


<s> unsigned FrameSizeMinusRBP = RoundUpToAlignment ( CSSize + MaxCallSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP


<s> if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l + NumLaneElts / <NUM_LIT> ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [


<s> if ( CurrentArgIndex == Args [ i ] . OrigArgIndex ) { Out . back ( ) ++ ; } else { Out . push_back ( <NUM_LIT> ) ; CurrentArgIndex ++


<s> case CallingConv :: Win64 : case CallingConv :: <ISA_LIT>_64_SysV : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv ::


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT> ; break ; } if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( OpcodeSelect , dl , VT , VMask , Op


<s> const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success


<s> Triple TheTriple ( TT ) ; return create<ISA_LIT>ELFStreamer ( Ctx , MAB , _OS , _Emitter


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineZERO_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineMERGE ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : case <STR_LIT>


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( * MF ) ; return TFI -> hasFP ( *


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; i ++ ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( i ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( i ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; } SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getAtomic ( Node -> getOpcode ( ) , dl , <STR_LIT> , Tys , Ops . data ( ) , Ops . size ( ) , cast < MemSDNode > ( Node ) -> getMemOperand ( ) , AN -> getOrdering ( ) , AN -> getSynchScope ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF


<s> int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) return false ; else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base


<s> bool MatchEvenMask = true ; bool MatchOddMask = true ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] ) ) MatchOddMask = false ; } if ( ! MatchEvenMask && ! MatchOddMask ) return SDValue ( ) ; SDValue UndefNode = DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Op0 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = SVOp -> getOperand ( <NUM_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Results ; SDLoc DL ( Op ) ; getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( & Results [ <NUM_LIT> ]


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( rs6000_gnu_attr && symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE


<s> } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT>


<s> if ( ! MBB -> empty ( ) && MBB -> begin ( ) -> getOpcode ( ) == <STR_LIT> ) assert ( ( BBOffsets [ MBB -> getNumber ( ) ] % <NUM_LIT> == <NUM_LIT> && BBSizes [ MBB -> getNumber ( ) ] % <NUM_LIT> == <NUM_LIT> ) || ( BBOffsets

[ MBB -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> && BBSizes [ MBB -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitATOMADD64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> <STR_LIT> Cond = StringSwitch < <STR_LIT> > ( Constraint ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return Cond


<s> bool isTargetLinux ( ) const { return TargetTriple . isOSLinux


<s> gcc_assert ( ! VECTOR_MODE_P ( mode ) ) ; vmode = aarch64_simd_container_mode (


<s> unsigned Opcode = Val -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( Val -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; CanNegate = true ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue O0 = Val -> getOperand ( <NUM_LIT> ) ; SDValue O1 = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; if ( ! isConjunctionDisjunctionTree ( O0 , CanNegateL , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; if ( ! isConjunctionDisjunctionTree ( O1 , CanNegateR , Depth + <NUM_LIT> ) ) return false ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL && ! CanNegateR ) return false ; CanNegate = CanNegateL && CanNegateR ; } else { bool NeedsNegOutL = O0 -> getOpcode ( ) == <STR_LIT> ; bool NeedsNegOutR = O1 -> getOpcode ( ) == <STR_LIT> ; if ( NeedsNegOutL && NeedsNegOutR ) return false ; CanNegate = false ; } return


<s> assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( TLI . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } return DAG . getMaskedStore ( Mst -> getChain ( ) , dl , TruncatedVal , Mst -> getBasePtr ( ) ,

NewMask , StVT , Mst -> getMemOperand ( ) , false ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : { std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { GVStubs [ Name ] = Name + <STR_LIT> ; Name += <STR_LIT> ; } O << Name ; return ; } case MachineOperand :: MO_GlobalAddress


<s> int ia64_depz_field_mask ( rtx rop , rtx rshift ) { unsigned HOST_WIDE_INT op = INTVAL ( rop ) ; unsigned HOST_WIDE_INT shift = INTVAL ( rshift ) ; op >>= shift ; return exact_log2 ( op + <NUM_LIT>


<s> CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; switch ( TheTriple . getOS ( ) ) { case Triple :: NetBSD : ExceptionsType = ExceptionHandling :: DwarfCFI ; break ; default : ExceptionsType = ExceptionHandling :: <ISA_LIT> ; break ; } UseParensForSymbolVariant = true ; UseIntegratedAssembler = true


<s> __inline__ static void sh_media_FTRV_S ( const void * mtrxg , const void * fvh ,


<s> bool IsPCRel = ( MO . getTargetFlags ( ) & ~ access ) == <STR_LIT> ; RefKind = IsPCRel ? MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_PCREL : MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_TPREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ; const MachineInstr * MI = MO . getParent ( ) ; const MachineFunction * MF = MI -> getMF ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; unsigned MIOpcode = MI -> getOpcode ( ) ; assert ( ( Subtarget -> isUsingPCRelativeCalls ( ) || MIOpcode != <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget -> isUsingPCRelativeCalls ( ) ) { if ( MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> ) { RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr


<s> return ; } unsigned NewOpc = convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; MI -> setDesc ( TII -> get ( NewOpc ) ) ; } unsigned ccOutIdx = MCID . getNumOperands ( ) - <NUM_LIT> ; if ( ! MCID . hasOptionalDef ( ) || ! MCID . OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID . getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( <NUM_LIT> ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || JUMP_TABLE_DATA_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER &&

INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ;


<s> bool isImm ( ) const override { return Kind == k_Immediate


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { return <NUM_LIT>


<s> unsigned <ISA_LIT>ELFObjectWriter :: GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { return getRelocTypeInner ( Target , Fixup ,


<s> StringRef Kind ; int64_t Reg = tryMatchVectorRegister ( Kind , false ) ; if ( Reg == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , true , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type != <NUM_LIT> && AGGREGATE_TYPE_P ( type


<s> if ( terminateSearch ( * CurrI ) ) break ; assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; if ( IsReverseIter && I != End ) I = CurrI ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> GetInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode

== <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ;


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool


<s> rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) ) continue ; if ( ++ cmov_cnt > <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! IsTailCall ) return IsIndirect ? getBLRCallOpcode ( CallerF ) : ( unsigned ) <STR_LIT> ; if ( ! IsIndirect ) return <STR_LIT> ; if ( CallerF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return <STR_LIT> ; return <STR_LIT>


<s> rtx_code_label * label ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR ,


<s> vabd_s16 ( int16x4_t a , int16x4_t b ) { int16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { if ( isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) return <STR_LIT> ; return Subtarget . isTarget64BitLP64 ( ) ?


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple ::

GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) ;


<s> if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'p' : fprintf ( stream , <STR_LIT> , cfun -> machine -> highest_saved_stack_register + <NUM_LIT> ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT> : break ; default : internal_error ( <STR_LIT> , code ) ; } switch ( GET_CODE ( modified_x ) ) { case REG : regno = REGNO ( modified_x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) internal_error ( <STR_LIT> , regno ) ; fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( regno ) ] ) ; return ; case MEM : output_address ( GET_MODE ( modified_x ) , XEXP ( modified_x , <NUM_LIT> ) ) ; return ; case CONST_INT


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB


<s> if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; return


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( LibCall , PtrVT ) ; Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT>


<s> if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( GET_MODE ( op0 ) == mode0 && GET_MODE ( op1 ) == mode1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op .

getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> static DecodeStatus DecodeADDR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT>


<s> void addACC64DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> return __builtin_mve_vcmpneq_m_sv4si ( __a ,


<s> MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } unsigned ScratchReg = MI . getOperand ( ScratchIdx ) . getReg


<s> bool skipSIG = false ; for ( std :: list < MachineBasicBlock * > :: iterator iter = intSkipBlock . begin ( ) ; iter != intSkipBlock . end ( ) ; ++ iter ) { if ( * iter == & ( * MBB ) ) { skipSIG = true ; break ; } } if ( skipSIG ) continue ; DebugLoc DL3 = MBB -> begin ( ) -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator startPoint = MBB -> begin ( ) ; MachineBasicBlock :: iterator firstTerminator ; MachineBasicBlock :: iterator I = MBB -> begin ( ) ; for ( MachineBasicBlock :: iterator E = MBB -> end ( ) ; I != E ; ++ I ) { unsigned int opcode = I -> getOpcode ( ) ; if ( I -> isBranch ( ) && ! ( opcode > <NUM_LIT> && opcode < <NUM_LIT> ) ) { break ; } else if ( opcode == <STR_LIT> || opcode == <STR_LIT> || opcode == <STR_LIT> ) { break ; } } firstTerminator = I ; unsigned int count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; I != firstTerminator ; ++ I ) { count


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , STTI (


<s> SMLoc getEndLoc ( ) const override { return


<s> aarch64_simd_types [ Poly8x8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly8x16_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly16x4_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly16x8_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly64x1_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Poly64x2_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Float32x2_t ] . eltype = float_type_node ; aarch64_simd_types [ Float32x4_t ] . eltype = float_type_node ; aarch64_simd_types [ Float64x1_t ] . eltype = double_type_node ; aarch64_simd_types [ Float64x2_t ] . eltype = double_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = aarch64_simd_types [ i ] . eltype ; enum machine_mode mode = aarch64_simd_types [ i ] . mode ; if ( aarch64_simd_types [ i ] . itype == NULL ) aarch64_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( aarch64_simd_types [ i ] . name , aarch64_simd_types [ i ] . itype ) ; TYPE_NAME ( aarch64_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( aarch64_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; aarch64_simd_intOI_type_node = AARCH64_BUILD_SIGNED_TYPE ( OImode ) ; aarch64_simd_intEI_type_node = AARCH64_BUILD_SIGNED_TYPE ( EImode


<s> if ( nargs == <NUM_LIT> ) { if ( ! POINTER_TYPE_P ( TREE_VALUE ( current_arg_type ) ) ) error ( <STR_LIT> <STR_LIT> ) ; } else if ( nargs == <NUM_LIT> ) { if ( TREE_CODE ( TREE_VALUE ( current_arg_type ) ) != INTEGER_TYPE || TYPE_MODE ( TREE_VALUE ( current_arg_type ) ) != word_mode ) error ( <STR_LIT> <STR_LIT> , TARGET_64BIT ? ( TARGET_X32 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; } nargs ++


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholePass ( ) { return new <ISA_LIT>MIPeephole


<s> break ; case 'd' : if ( ! TARGET_AVX2 ) str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , <NUM_LIT> ) ; gcc_assert ( ok ) ; pop_cfun (


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; uint64_t encoding = <STR_LIT> ( Val


<s> SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return createCMovFP ( DAG , Cond , True , False ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST


<s> return getImm34Encoding ( MI , OpNo , Fixups , STI , ( MCFixupKind )


<s> else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode


<s> ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_MMX_REG ; else if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( mode == HFmode ) regno = FIRST_SSE_REG ; if ( mode == HCmode ) { rtx ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( ret , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , FIRST_SSE_REG ) , GEN_INT ( <NUM_LIT> ) ) ; return ret ; } if ( ( fn || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , fn ,


<s> Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 = false ; IsISA3_0 =


<s> Inst . addOperand ( MCOperand :: CreateImm ( ( Imm + Add ) & ( Add - <NUM_LIT> ) ) ) ; return


<s> SDValue Offset = N -> getOperand ( OffsetPos ) ; if ( Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; Ops [ OffsetPos ] = Offset ; return DAG . getNode ( N -> getOpcode ( ) , DL , DAG . getVTList ( <STR_LIT> )