<s> if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( INT64_C ( <NUM_LIT> ) << <NUM_LIT> )


<s> bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; if ( TLI -> allowsMisalignedMemoryAccesses ( LT . second , <NUM_LIT> ) ) return Cost ; assert ( Alignment ) ; Cost += LT . first * ( ( SrcBytes / Alignment -> value


<s> const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int Align = Subtarget . getStackAlignment ( ) . value ( ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , Align ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex

( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; assert ( ! IsTailCall && <STR_LIT> ) ; passByValArg ( Chain , DL , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , <ISA_LIT>CCInfo , * ByValArg , Flags , Subtarget . isLittle ( ) ) ; ++ ByValArg ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; continue ; } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; bool IsPICCall = ( Subtarget . isABI_N64 ( ) || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false ; SDValue CalleeLo ; EVT Ty = Callee . getValueType ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { const GlobalValue * Val = G -> getGlobal ( ) ; InternalLinkage = Val -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( G , Ty , DAG , Subtarget .

isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> split_double ( x , & low , & high ) ; putc ( '$' , file ) ; output_addr_const ( file , high ) ; return ; } case REG : if ( REGNO ( x ) + <NUM_LIT> >= FIRST_PSEUDO_REGISTER ) abort ( ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) + <NUM_LIT> ] ) ; return ; case MEM : { rtx adj_mem = x ; adj_mem = adjust_address ( adj_mem , GET_MODE ( adj_mem ) , <NUM_LIT> ) ; output_memory_reference_mode = GET_MODE ( adj_mem ) ; output_address ( XEXP ( adj_mem , <NUM_LIT> ) ) ; return ; } default : abort ( ) ; } case 'L' : switch ( GET_CODE ( x ) ) { case CONST_DOUBLE : if ( GET_MODE ( x ) == SFmode ) abort ( ) ; if ( GET_MODE ( x ) == DFmode ) { REAL_VALUE_TYPE r ; long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , l ) ; fprintf ( file , <STR_LIT> , l [ <NUM_LIT> ] ) ; return ; } case CONST_INT : { rtx high , low ; split_double ( x , & low , & high ) ; putc ( '$' , file ) ; output_addr_const ( file , low ) ; return ; } case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; case MEM : output_memory_reference_mode = GET_MODE ( x ) ; output_address ( XEXP ( x , <NUM_LIT> ) ) ; return ; default : abort ( ) ; } case <NUM_LIT> : switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; case MEM : output_memory_reference_mode = GET_MODE ( x ) ; output_address ( XEXP ( x , <NUM_LIT> ) ) ; return ; case CONST_DOUBLE : { REAL_VALUE_TYPE r ; long l ; gcc_assert ( GET_MODE ( x ) == SFmode ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; fprintf ( file , <STR_LIT> , l ) ; return ; } default : putc ( '$' , file ) ; output_addr_const ( file , x ) ; return ; } default : output_operand_lossage ( <STR_LIT>


<s> if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II


<s> return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIEPseudo ( MI , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : { bool DestIsHigh = isHighReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; bool SrcIsHigh = isHighReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( SrcIsHigh == DestIsHigh ) MI -> setDesc ( get ( DestIsHigh ? <STR_LIT> : <STR_LIT> ) ) ; else { MI -> setDesc ( get ( DestIsHigh ? <STR_LIT> : <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ^ <NUM_LIT> ) ; } return true ; } case <STR_LIT> : splitAdjDynAlloc ( MI ) ; return true ; case TargetOpcode :: LOAD_STACK_GUARD : expandLoadStackGuard ( MI ) ; return true ; default : return false


<s> if ( ! R . first ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; bool IsF64On<ISA_LIT> = VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ; if ( IsF64On<ISA_LIT> ) ArgValue = unpack64 ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { const unsigned XLenInBytes = <NUM_LIT> ; const MVT XLenVT = <STR_LIT> ; ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; unsigned Idx = CCInfo .


<s> unsigned NumRegs = CC . numIntArgRegs ( ) ; const uint16_t * ArgRegs = CC . intArgRegs ( ) ; const CCState & CCInfo = CC . getCCInfo ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs , NumRegs ) ; unsigned RegSize = CC . regSize ( ) ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex (


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE

| ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> static SDValue combineFP_EXTEND ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasF16C ( ) || Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; Src = DAG . getBitcast ( IntVT , Src ) ; if ( NumElts < <NUM_LIT> ) { unsigned NumConcats = <NUM_LIT> / NumElts ; SDValue Fill = NumElts == <NUM_LIT> ? DAG . getUNDEF ( IntVT ) : DAG . getConstant ( <NUM_LIT> , dl , IntVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcats


<s> break ; case COMPLEX_TYPE : mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( ! SCALAR_FLOAT_MODE_P ( mode ) ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case VECTOR_TYPE : if ( ! TARGET_ALTIVEC_ABI || ! TARGET_ALTIVEC ) return - <NUM_LIT> ; size = int_size_in_bytes ( type ) ; switch ( size ) { case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = rs6000_aggregate_candidate ( TREE_TYPE ( type ) , modep , empty_base_seen , zero_width_bf_seen ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * zero_width_bf_seen = <NUM_LIT> ; continue ; } if ( DECL_FIELD_ABI_IGNORED ( field ) ) { if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( field ) ) ) * empty_base_seen |= <NUM_LIT> ; else * empty_base_seen |= <NUM_LIT> ; continue ; } sub_count = rs6000_aggregate_candidate ( TREE_TYPE ( field ) , modep , empty_base_seen , zero_width_bf_seen ) ; if ( sub_count < <NUM_LIT> )


<s> unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned SllRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( ShiftAmt ) . addReg ( MaskUpper ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2 ) . addReg ( ShiftAmt ) .


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( create<ISA_LIT>BranchTargetsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt ::

None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ;


<s> int cmov_cnt = <NUM_LIT> ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; enum machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) ) continue ; if ( ++ cmov_cnt > <NUM_LIT> ) return


<s> if ( ! REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return false ; if ( mode_supports_vsx_dform_quad ( mode ) ) return quad_address_p ( x , mode , strict ) ; if ( ! reg_offset_addressing_ok_p ( mode ) ) return virtual_stack_registers_memory_p ( x ) ; if ( legitimate_constant_pool_address_p ( x , mode , strict || lra_in_progress ) ) return true ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; extra = <NUM_LIT>


<s> if ( arg . type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) return <NUM_LIT> ; passed_in_gprs = false ; if ( cum -> fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + <NUM_LIT> ) { int fpr = ( ( FP_ARG_MAX_REG + <NUM_LIT> - cum -> fregno ) * MIN ( <NUM_LIT> , GET_MODE_SIZE ( elt_mode ) ) ) ; int fpr_words = fpr / ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( align_words + fpr_words < GP_ARG_NUM_REG ) passed_in_gprs = true ; else ret = fpr ; } } if ( passed_in_gprs && align_words < GP_ARG_NUM_REG && GP_ARG_NUM_REG < align_words + rs6000_arg_size ( arg . mode , arg . type ) ) ret = ( GP_ARG_NUM_REG - align_words ) * ( TARGET_32BIT


<s> return false ; case <STR_LIT> : lowerLongBranchLUi ( MI , OutMI ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: CEK_ABS_LO


<s> m_InputTLSGdSymbols . insert ( & pInfo ) ; m_MultipartList . back ( ) . m_TLSNum += <NUM_LIT> ; m_MultipartList . back ( ) . m_TLSDynNum += <NUM_LIT> ; return true


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG


<s> MVT F32VT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , F32VT , SrcVal ) ; SrcVT = F32VT ; SrcElementVT = <STR_LIT> ; SrcElementWidth = <NUM_LIT> ; } else if ( SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT . getScalarType ( ) ) ) ; if ( SrcElementWidth < SatWidth || SrcElementVT == <STR_LIT> ) return SDValue ( ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , IntVT , SrcVal , DAG . getValueType ( IntVT . getScalarType ( ) ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sextOrSelf ( SrcElementWidth ) , DL , IntVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , IntVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sextOrSelf ( SrcElementWidth ) , DL , IntVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , IntVT , Min , MaxC ) ; } else { SDValue MinC = DAG . getConstant ( APInt :: getAllOnesValue ( SatWidth ) . zextOrSelf ( SrcElementWidth ) , DL ,


<s> if ( ! PInfo . Visited ) { continue ; } if ( PInfo . HighLatencyCPSR ) { HighLatencyCPSR = true ; break ; } } bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = std :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } if ( MI -> isDebugValue ( ) ) continue ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; bool NextInSameBundle = NextMII != E && NextMII ->


<s> Inst . addOperand ( MCOperand :: createImm ( getCondCode (


<s> void addConstantSImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT>


<s> if ( SVOp -> isSplat ( ) ) { SDValue Broadcast = LowerVectorBroadcast ( Op , Subtarget , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , Subtarget , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( VT . is128BitVector ( ) && Subtarget -> hasSSE2 ( ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getSimpleValueType ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp .


<s> if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , <NUM_LIT> ) ) return <NUM_LIT> ; } if ( saved_int_regs & <NUM_LIT> ) return <NUM_LIT> ; } if ( TARGET_INTERWORK && saved_int_regs != <NUM_LIT> && ! IS_INTERRUPT ( func_type ) ) return <NUM_LIT> ; if ( iscond && arm_tune_strongarm


<s> unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) + MFI -> getStackSize ( ) + SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( AFI -> isDPRCalleeSavedAreaFrame ( FrameIndex ) ) Offset -= AFI -> getDPRCalleeSavedAreaOffset ( ) ; else if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } if ( ! AFI -> isThumbFunction ( ) ) Offset = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Offset = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Offset == <NUM_LIT> ) return ; assert ( Offset && <STR_LIT> ) ; unsigned ScratchReg = findScratchRegister ( RS , & <STR_LIT> , AFI ) ; if ( ScratchReg == <NUM_LIT> ) ScratchReg = RS -> scavengeRegister ( & <STR_LIT> , II


<s> auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID


<s> return ( __m256 ) __builtin_ia32_roundps256 ( ( __v8sf ) __V ,


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitMappingSymbol ( <STR_LIT> ) ; MCELFStreamer :: emitInstruction ( Inst ,


<s> break ; case k_MemoryZeroRegImm : assert ( getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << getMemIndexReg ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case k_MemoryZeroImmImm : assert ( getMemIndex ( ) != nullptr && getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << * getMemIndex ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case k_MemoryRegImm : assert ( getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << getMemBase ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case k_MemoryZeroImm : assert ( getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case k_CCOp : OS << <STR_LIT> << getCCVal ( ) << <STR_LIT> ; break ; case k_RDOp


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , raw_pwrite_stream & OS , MCCodeEmitter * CE , bool RelaxAll ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S


<s> static SDValue getShuffleVectorZeroOrUndef ( SDValue V2 , unsigned Idx , bool isZero , bool HasSSE2 , SelectionDAG & DAG ) { MVT VT = V2 . getValueType ( ) ; SDValue V1 = isZero ? getZeroVector ( VT , HasSSE2 , DAG , V2 . getDebugLoc


<s> if ( DataVT . isFloatingPoint ( ) ) Data = DAG . getNode ( <STR_LIT> , DL , DataVT . changeTypeToInteger ( ) , Data ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBTIHint ( unsigned Val , StringRef Str , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_BTIHint , Ctx ) ; Op -> BTIHint . Val = Val << <NUM_LIT> | <NUM_LIT> ; Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> if ( GET_CODE ( body ) != SET ) return false ; rtx src = SET_SRC ( body ) ; if ( GET_CODE ( src ) != SUBREG ) return false ; rtx inner = XEXP ( src , <NUM_LIT> ) ; return ( GET_CODE ( inner ) ==


<s> if ( Op == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; continue ; } int LoadId = LoadNode -> getNodeId ( ) ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = UI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getNodeId ( ) > LoadId ) return false ; } ChainOps . push_back ( Op ) ; } if ( ChainCheck ) InputChain = CurDAG -> getNode ( <STR_LIT> , Chain . getDebugLoc ( ) , <STR_LIT> , & ChainOps [ <NUM_LIT> ] , ChainOps . size ( ) ) ; } if ( ! ChainCheck ) return false ; return


<s> MachineInstr & SubRegMI = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; Register SubToRegDef2 = MRI . createVirtualRegister ( DstRC ) ; MachineInstr & SubRegMI2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MachineInstr & BFM = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( SubToRegDef ) . addUse ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( SubRegMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( SubRegMI2 , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( BFM , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true


<s> if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget -> getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( TRI -> hasBasePointer ( DAG . getMachineFunction ( ) ) && TRI -> getBaseRegister ( ) == <STR_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue


<s> static SDValue GenForSextInreg ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , EVT SrcVT , EVT DestVT , EVT SubRegVT , const int * Mask , SDValue Src ) { SelectionDAG & DAG = DCI . DAG ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , SrcVT , Src ) ; SDValue Sext = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DestVT , Bitcast ) ; SDValue ShuffleVec = DAG . getVectorShuffle ( DestVT , SDLoc ( N ) , Sext , DAG . getUNDEF ( DestVT ) , Mask ) ; SDValue ExtractSubreg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SDLoc ( N ) , SubRegVT ,

ShuffleVec , DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> static SDValue PerformOrCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode (

<STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ;


<s> case 'r' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case


<s> const TargetRegisterClass * RC = getPointerRegClass ( MF ) ; Register BaseReg = MRI . createVirtualRegister ( RC ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex


<s> return ( uint32x2_t ) __builtin_aarch64_sqrshrun_nv2di ( __a ,


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; return true


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return


<s> if ( ud2 != <NUM_LIT> ) emit_move_insn ( copy_rtx ( temp ) , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud2 ) ) ) ; emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_ASHIFT ( DImode , copy_rtx ( temp ) , GEN_INT ( <NUM_LIT> ) ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud1 ) ) ) ; } else { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; emit_move_insn ( copy_rtx ( temp ) , GEN_INT ( ( ( ud4 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; if ( ud3 != <NUM_LIT> ) emit_move_insn ( copy_rtx ( temp ) , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud3 ) ) ) ; emit_move_insn ( ud2 != <NUM_LIT> || ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_ASHIFT ( DImode , copy_rtx ( temp ) , GEN_INT ( <NUM_LIT> ) ) ) ; if ( ud2 != <NUM_LIT> ) emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_IOR ( DImode

, copy_rtx ( temp ) , GEN_INT ( ud2 << <NUM_LIT> ) ) ) ;


<s> if ( ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) || ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) ) { EVT TempValLoc = ValVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ValToCopy = DAG . getBitcast ( TempValLoc , ValArg ) ; if ( ValLoc == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , Dl , ValLoc , ValToCopy ) ; return ValToCopy ; } else if ( ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) || ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) ) { return DAG . getBitcast ( ValLoc , ValArg


<s> void <ISA_LIT>InstPrinter :: printUImm12Offset ( const MCInst * MI , unsigned OpNum , unsigned Scale , raw_ostream & O ) { const MCOperand MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { O << <STR_LIT> << formatImm ( MO . getImm ( ) * Scale ) ; } else { assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O


<s> if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; struct cl_target_option * opts = target_opts_for_fn ( fndecl


<s> InstructionCost <ISA_LIT>TTIImpl :: getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT>


<s> return __builtin_loongson_packsswh ( s , t


<s> if ( DCI . isBeforeLegalize ( ) || ! Subtarget -> hasNEON ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( N0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = N0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ; } SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , TLI . getPointerTy ( ) ) ) ; Ops . push_back ( Vec )


<s> return ( N . getOpcode ( ) == <STR_LIT> || isValidPCRelNode < ConstantPoolSDNode > ( N ) || isValidPCRelNode < GlobalAddressSDNode > ( N ) || isValidPCRelNode < JumpTableSDNode

> ( N ) || isValidPCRelNode < BlockAddressSDNode > ( N ) ) ;


<s> if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode ==


<s> if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [ REGNO ( got_register_rtx ) ] + <NUM_LIT> ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> , REGNO ( got_register_rtx ) ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; SDLoc DL ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT>


<s> static SDValue combineVPMADD ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( LHS . getNode ( ) ) || <STR_LIT> ( RHS . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; return SDValue


<s> const __GCC_FV * g = mtrxg , * h = mtrxh ; __GCC_FV * f = mtrxf ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) sh_media_FVADD_S ( & g [ i ] , & h [ i ] , & f [ i ] ) ; sh_media_FVADD_S ( & g [ <NUM_LIT> ] , & h [ <NUM_LIT> ] , & f [ <NUM_LIT> ] ) ; sh_media_FVADD_S ( & g [ <NUM_LIT> ] , & h [ <NUM_LIT>


<s> if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg ,


<s> return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex


<s> return ( ( vec_int4 ) ( si_cg ( ( qword ) ( a


<s> __arm_ldc2l ( const unsigned int __coproc , const unsigned


<s> if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return


<s> case MCContext :: IsMachO : CurrentFormat = MACHO ; break ; case MCContext :: IsELF : CurrentFormat = ELF ; break ; case MCContext :: IsCOFF : CurrentFormat = COFF ; break ; case MCContext :: IsWasm : CurrentFormat = WASM ; break ; case MCContext :: IsGOFF : case MCContext :: IsSPIRV : case MCContext :: IsXCOFF : case MCContext :: IsDXContainer : llvm_unreachable ( <STR_LIT> ) ; break ; } if ( ~ Prefix -> SupportedFormats & CurrentFormat ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } RefKind = Prefix -> VariantKind ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex


<s> else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else if ( Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI (


<s> unsigned rv = MatchInstructionImpl ( Operands , Inst , ErrorInfo , matchingInlineAsm , VariantID ) ; if ( Code16GCC ) SwitchMode ( <STR_LIT>


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( )


<s> Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT>


<s> SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> return ( Is64Bit && ( TargetType == isMingw || TargetType ==


<s> if ( TARGET_ARM ) lowbit &= ~ <NUM_LIT> ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << lowbit ) ) == <NUM_LIT> ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= <NUM_LIT> && ( ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> ) ) return TRUE ; } else if ( TARGET_THUMB2 ) { HOST_WIDE_INT v ; v = i & <NUM_LIT> ; v |= v << <NUM_LIT> ; if ( i == v || i == ( v | ( v << <NUM_LIT> ) ) ) return TRUE ; v = i & <NUM_LIT> ; v |= v << <NUM_LIT> ; if ( i == v


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> bool isMemWithUimmOffsetSP ( ) const { return isMem ( ) && isConstantMemOff ( ) && isUInt < Bits > ( getConstantMemOff ( ) ) && getMemBase ( ) -> isRegIdx ( ) && ( getMemBase


<s> DebugLoc DL ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } SmallVector < int , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; } if ( VecElems == <NUM_LIT> ) { std :: copy ( Temp , Temp + Stride , TransposedMatrix . begin ( ) ) ; return ; } else for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Temp [ <NUM_LIT> * i ] , Temp [ <NUM_LIT>


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> } } APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Idx = SHFIndices [ i ] ; if ( Idx == - <NUM_LIT> ) Idx = <NUM_LIT> ; Imm <<= <NUM_LIT> ; Imm |= Idx & <NUM_LIT> ; } SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getTargetConstant ( Imm , DL ,

<STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>CondBrFoldingPass :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget


<s> uws . next = ptr + <NUM_LIT> ; uws . bytes_left = <NUM_LIT> ; uws . words_left = ( ( * ptr


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs


<s> if ( TRI -> getEncodingValue ( SrcReg ) < <NUM_LIT> ) { MIB -> setDesc ( StoreDesc ) ; } else { MIB -> setDesc ( ExtractDesc ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , SubIdx , &


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> else { if ( GET_CODE ( base_addr ) == POST_INC && REG_P ( XEXP ( base_addr , <NUM_LIT> ) ) ) return true ; } return false


<s> return ( __m128i ) __builtin_ia32_pminuw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op ) ; Parser . Lex (


<s> const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID


<s> vmovn_u16 ( uint16x8_t a ) { uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) :


<s> assert ( ShAmt . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( isa < ConstantSDNode > ( ShAmt ) ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ; } } switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm64 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ThisStoreSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ThisStoreSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ThisStoreSize = <NUM_LIT> ; break ; } StoreSize [ NumStores ] = ThisStoreSize ; StorePtr1 [ NumStores ] = Node -> getOperand ( <NUM_LIT> ) ; StorePtr2 [ NumStores ] = Node -> getOperand ( <NUM_LIT> ) ; ++ NumStores ; } if ( InstrType == <STR_LIT> || isSingle ) NumIssued = <NUM_LIT> ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == <NUM_LIT> ) EndDispatchGroup (


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; assert ( TPC && <STR_LIT> <STR_LIT> ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; TM = & TPC -> getTM < TargetMachine > ( ) ; Is64Bit = TM -> getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; if ( ! llvm :: any_of ( M , [ & ] ( const Function & F ) { STI = & TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return STI -> useRetpoline ( ) && ! STI -> useRetpolineExternalThunk ( ) ; } ) ) return false ; TII = STI -> getInstrInfo ( ) ; if ( Is64Bit ) { createThunk ( M , <STR_LIT> , <STR_LIT> ) ; } else { createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> ) ; } return true


<s> CurrGroupSize = Incoming -> CurrGroupSize ; LLVM_DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming ->


<s> SDValue V0 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( PairDRegs ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( QuadDRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else { return false ; } MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return


<s> SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand (


<s> bool supportSwiftError ( ) const override { return true


<s> void <ISA_LIT>AnalyzeImmediate :: ReplaceADDiuSLLWithLUi ( InstSeq & Seq ) { if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SLL ) || ( Seq [ <NUM_LIT> ] . ImmOpnd < <NUM_LIT> ) ) return ; int64_t Imm = ( ( ( int64_t ) Seq [ <NUM_LIT> ] . ImmOpnd ) << <NUM_LIT>


<s> void addImmOperands ( MCInst & Inst ,


<s> void <ISA_LIT>RetpolineThunks :: populateThunk ( MachineFunction & MF , unsigned Reg ) { MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; while ( MF . size ( ) > <NUM_LIT> ) MF . erase ( std :: next ( MF . begin ( ) ) ) ; MachineBasicBlock * CaptureSpec = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MachineBasicBlock * CallTarget = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MCSymbol * TargetSym = MF . getContext ( ) . createTempSymbol ( ) ; MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ; const unsigned CallOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const unsigned RetOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; Entry -> addLiveIn (


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg


<s> static void rs6000_xcoff_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) { const char


<s> unsigned Delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . add ( predOps ( <STR_LIT> ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( MF , UserMBB , BBInfo [ UserMBB -> getNumber ( ) ] ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [


<s> assemble_external ( decl ) ; SET_SYMBOL_REF_DECL ( x , NULL ) ; } } if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; result = true ; } else result = default_assemble_integer ( x ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( -


<s> MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setNumAlignedDPRCS2Regs ( <NUM_LIT> ) ; if ( ! SpillAlignedNEONRegs ) return ; if ( MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ) return ; if ( ! MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget (


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static int rs6000_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ; if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && FP_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ) || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) ; if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( XER_REGNO_P ( regno ) ) return mode == PSImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return


<s> MCSymbol * TlsGetAddr = OutContext . getOrCreateSymbol ( Name ) ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ! Subtarget -> isDarwin ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue = MO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition = ~ <NUM_LIT> ; VPTState . CurPosition = ~ <NUM_LIT> ; NextSymbolIsThumb = false


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReferencePreferSP ( const MachineFunction & MF , int FI , Register & FrameReg , bool IgnoreSPUpdates ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; if ( ! IgnoreSPUpdates && ! hasReservedCallFrame ( MF ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; assert ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) >= <NUM_LIT> && <STR_LIT> ) ; return getFrameIndexReferenceSP ( MF , FI , FrameReg ,


<s> unsigned <ISA_LIT>FastISel :: materializeExternalCallSym ( MCSymbol * Sym ) { const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addSym ( Sym , <STR_LIT> ) ; return DestReg


<s> if ( ! aarch64_classify_address ( & addr , op , mode , false ) )


<s> for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ]


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i


<s> const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; for ( unsigned Op : { G_LOAD , G_STORE } ) { for ( auto Ty : { s1 , s8 , s16 , s32 , p0 } ) setAction ( { Op , Ty } , Legal ) ; setAction ( { Op , <NUM_LIT> , p0 } , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 , s32 } ) setAction ( { G_ADD , Ty } , Legal ) ; for ( unsigned Op : { G_SEXT , G_ZEXT } ) { setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_CONSTANT , s32 } , Legal ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal


<s> bool isVecListFourDWordIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> &&


<s> return CallConv != CallingConv :: Fast


<s> if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) { if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( &


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask =


<s> unsigned getRelocationInfo ( ) const


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Op = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Op ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq


<s> static unsigned getSubOpcode ( bool Is64Bit , int64_t Amount ) { if ( Is64Bit ) return isInt < <NUM_LIT> > ( Amount ) ?


<s> LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State .


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue rd = DAG . getNode ( Opcode , DL , Tys , N -> getOperand ( <NUM_LIT> ) ) ; SDValue LO , HI ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } SDValue Chain = HI . getValue ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ,


<s> const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) setAction


<s> bool isT2SOImm ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; return ( ! <ISA_LIT>16Expr || ( <ISA_LIT>16Expr -> getKind ( ) != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 && <ISA_LIT>16Expr -> getKind ( )

!= <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ) ) ;


<s> static inline unsigned createNEONModImm ( unsigned OpCmode , unsigned Val ) { return ( OpCmode << <NUM_LIT> )


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF , DAG ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT ,

withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; Register RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg (


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) )


<s> SmallVector < std :: pair < MachineInstr * , MachineInstr * > , <NUM_LIT> > MIReplacements ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * NewMI = nullptr ; MachineInstr * MI = & * I ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize

) NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ;


<s> if ( Info . MI1 != nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info .


<s> assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = getOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI =


<s> } if ( TREE_PUBLIC ( decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( decl ) ) { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( rs6000_xcoff_visibility ( decl ) , file ) ; putc ( '\n' , file ) ; } } else { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; putc ( '\n' , file ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; in_section = NULL


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS


<s> unsigned VF = cast < FixedVectorType > ( SrcTy ) -> getNumElements ( ) ; for ( unsigned P = <NUM_LIT> ; P < Log2Diff ; ++ P ) { if ( NumParts > <NUM_LIT> ) NumParts /= <NUM_LIT> ; Cost += NumParts ; } if ( VF == <NUM_LIT> && SrcTy -> getScalarSizeInBits ( ) == <NUM_LIT> && DstTy ->

getScalarSizeInBits ( ) == <NUM_LIT> ) Cost -- ;


<s> bool checkRegisterEqual ( const TargetRegisterInfo * TRI , unsigned Reg1 , unsigned Reg2 ) { if ( ! TRI -> isPhysicalRegister ( Reg1 ) ||

! TRI -> isPhysicalRegister ( Reg2 ) ) {


<s> bool isToken ( ) const { return Kind ==


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT> ) LastMI = nullptr ; ScoreboardHazardRecognizer :: AdvanceCycle (


<s> SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; PassThru = getSVESafeBitCast ( PassThruVT , PassThru , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru . getSimpleValueType ( ) , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , true , DAG ) ; if ( ResNeedsSignExtend ) Opcode = getSignExtendedGatherOpcode


<s> return MFI . getNumFixedObjects ( ) && needsStackRealignment


<s> unsigned Domain = TID . TSFlags & <STR_LIT> ; if ( TID . mayStore ( ) ) return false ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode ==


<s> insnp = e_ready ; while ( insnp -- > ready + deleted ) while ( insnp >= ready + deleted ) { rtx_insn * insn = * insnp ; if ( ! safe_group_barrier_needed ( insn ) ) break ; memmove ( ready + <NUM_LIT> , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; deleted ++ ; } n_ready -= deleted ; ready += deleted ; } current_cycle = clock_var ; if ( reload_completed && mem_ops_in_group [ clock_var % <NUM_LIT> ] >= ia64_max_memory_insns ) { int moved = <NUM_LIT> ; insnp = e_ready ; while ( insnp -- > ready + moved ) while ( insnp >= ready + moved ) { rtx_insn * insn = * insnp ; if ( ! is_load_p ( insn ) ) break ; memmove ( ready + <NUM_LIT> , ready , ( insnp - ready )


<s> SDLoc DL ( N ) ; RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) ==


<s> for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned FirstReg = <NUM_LIT> , SecondReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , FirstReg , SecondReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( FirstReg , TRC ) ; MRI -> constrainRegClass ( SecondReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg , RegState :: Define ) . addReg ( SecondReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg ) . addReg ( SecondReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++


<s> OpBegins . push_back ( OpBegins . back (


<s> switch ( I -> getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : if ( TFI -> hasFP ( MF ) && AFI -> hasStackFrame ( ) ) Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ; ImmMask <<=


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> return this -> m_insn_fma_head_map -> put ( node


<s> bool hasV6Ops ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return


<s> case SFmode : return gen_aarch64_rsqrts_sf3 ; case V2DFmode : return gen_aarch64_rsqrts_v2df3 ; case V2SFmode : return


<s> bool isThumbMemPC ( ) const { int64_t Val = <NUM_LIT> ; if ( isImm ( ) ) { if ( isa < MCSymbolRefExpr > ( Imm . Val ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) return false ; Val = CE -> getValue (


<s> if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) &&


<s> static bool canUseSiblingCall ( CCState ArgCCInfo , SmallVectorImpl < CCValAssign > & ArgLocs ) { for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = VA . getLocReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return false ; } return true


<s> return Reductions ; } for ( PHINode & Phi : Header -> phis ( ) ) { const auto * Ty = Phi . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; const bool IsReduction = RecurrenceDescriptor :: AddReductionVar ( & Phi , RecurrenceDescriptor :: RK_IntegerAdd , TheLoop , HasFnNoNaNAttr , RecDesc ) ; if ( ! IsReduction ) continue ; Instruction * Acc = dyn_cast < Instruction > ( Phi . getIncomingValueForBlock ( Latch ) ) ; if ( ! Acc ) continue ; Reductions . push_back ( Reduction ( & Phi , Acc ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto R : Reductions ) { dbgs ( ) << <STR_LIT> ; R . Phi


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> static DecodeStatus DecodeGPRSeqPairsClassRegisterClass ( MCInst & Inst , unsigned RegClassID , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Reg = <ISA_LIT>MCRegisterClasses [ RegClassID ] . getRegister (


<s> return getSubtargetImpl ( ) -> getTargetLowering (


<s> default : return <NUM_LIT> ; case <STR_LIT> : Opc = HasAVX512 ? <STR_LIT> : HasSSE1 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = HasAVX512 ? <STR_LIT> : HasSSE2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter (


<s> if ( is<ISA_LIT>64 ) BuildMI ( PrologMBB , { MI } , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( FPReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - Log2 ( MaxAlign ) ) ; else BuildMI ( PrologMBB , { MI } , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( FPReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - Log2 ( MaxAlign ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( PrologMBB , { MI } , DL , TII . get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) , SPReg ) . addReg ( ScratchReg ) . addReg ( SPReg ) ; } if ( NegResidualSize ) { bool ResidualUseDForm = CanUseDForm ( NegResidualSize ) ; if ( ! ResidualUseDForm ) MaterializeImm ( PrologMBB , { MI } , NegResidualSize , ScratchReg ) ; allocateAndProbe ( PrologMBB , { MI } , NegResidualSize , ScratchReg , ResidualUseDForm ) ; } bool UseDForm = CanUseDForm ( NegProbeSize ) ; if ( NumBlocks < <NUM_LIT> ) { if ( ! UseDForm ) MaterializeImm ( PrologMBB , { MI } , NegProbeSize , ScratchReg ) ; for ( int i = <NUM_LIT> ; i < NumBlocks ; ++ i ) allocateAndProbe ( PrologMBB , { MI } , NegProbeSize , ScratchReg , UseDForm ) ; if ( needsCFI ) { buildDefCFAReg ( PrologMBB , { MI } , SPReg ) ; } } else { MaterializeImm ( PrologMBB , { MI } , NumBlocks , ScratchReg ) ; BuildMI ( PrologMBB , { MI } , DL , TII . get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) ; if ( ! UseDForm ) MaterializeImm ( PrologMBB , { MI } , NegProbeSize , ScratchReg ) ; MachineFunction :: iterator MBBInsertPoint = std :: next ( PrologMBB . getIterator ( ) ) ; MachineBasicBlock * LoopMBB = MF . CreateMachineBasicBlock ( ProbedBB ) ; MF . insert ( MBBInsertPoint , LoopMBB ) ; MachineBasicBlock * ExitMBB = MF . CreateMachineBasicBlock ( ProbedBB ) ; MF . insert ( MBBInsertPoint , ExitMBB ) ; allocateAndProbe ( * LoopMBB , LoopMBB -> end ( ) , NegProbeSize , ScratchReg , UseDForm ) ; BuildMI ( LoopMBB , DL , TII . get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( LoopMBB ) ; LoopMBB -> addSuccessor ( ExitMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; ExitMBB -> splice ( ExitMBB -> end ( ) , & PrologMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , PrologMBB . end ( ) ) ; ExitMBB -> transferSuccessorsAndUpdatePHIs ( & PrologMBB ) ; PrologMBB . addSuccessor ( LoopMBB ) ; if ( needsCFI ) { buildDefCFAReg ( * ExitMBB , ExitMBB -> begin ( ) , SPReg ) ; } recomputeLiveIns ( * LoopMBB ) ; recomputeLiveIns ( * ExitMBB


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( Cond . empty ( ) && ! FBB && TBB


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; } switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( offset ) ) ; if ( IsLoad && Rt == Rt2


<s> const TargetRegisterClass * GPRRC = IsFGR64on<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; unsigned MFC1Opc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : ( IsFGR64on<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ; unsigned FILLOpc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; Register Rtemp = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( MFC1Opc ) , Rtemp ) . addReg ( Fs ) ; BuildMI ( * BB , MI , DL , TII -> get ( FILLOpc ) , Wtemp ) . addReg ( Rtemp ) ; unsigned WPHI = Wtemp ; if ( IsFGR64on<ISA_LIT>32 ) { Register Rtemp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Rtemp2 ) . addReg ( Fs ) ; Register Wtemp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register Wtemp3 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( Wtemp ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp3 ) . addReg ( Wtemp2 ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; WPHI = Wtemp3 ; } if ( IsFGR64 ) { Register Wtemp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( WPHI ) . addReg ( WPHI ) ; WPHI = Wtemp2


<s> if ( ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { const unsigned AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return VectorSelectTbl [ Idx ] .


<s> __builtin_sh_media_STLO_L ( p + <NUM_LIT> , k ) ; __builtin_sh_media_STHI_L ( p ,


<s> return ( uint16x8_t ) __builtin_neon_vcgtv8hi ( __a ,


<s> bool OptimizeLEAPass :: isIdenticalOp ( const MachineOperand & MO1 , const MachineOperand & MO2 ) { return MO1 . isIdenticalTo ( MO2 ) && ( ! MO1 . isReg ( ) || ! TargetRegisterInfo

:: isPhysicalRegister ( MO1 . getReg ( ) ) ) ;


<s> for ( long i = <NUM_LIT> ; i < __builtin_popcountl ( __M ) ; i ++ ) { c = __builtin_clzl ( m ) ; p = ( p << <NUM_LIT> ) | c ; m ^= ( mask >> c ) ; } result = __builtin_bpermd ( p , __X ) ; } else { p = <NUM_LIT> - __builtin_popcountl ( __M ) ; result = <NUM_LIT> ; while ( m != <NUM_LIT> ) { unsigned long t ; c = __builtin_clzl ( m ) ; t = ( __X & ( mask >> c ) ) >> ( p - c ) ; m ^= ( mask >> c ) ; result |= ( t ) ; p


<s> static DecodeStatus DecodeCRRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t


<s> return opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> &&

opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> && opcode != <STR_LIT> ;