<s> FuncInfo -> setVarArgsStackOffset ( MFI -> CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateStackObject ( Depth , <NUM_LIT> , false ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; for ( unsigned GPRIndex = <NUM_LIT> ; GPRIndex != NumGPArgRegs ; ++ GPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( GPArgRegs [ GPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( GPArgRegs [ GPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , PtrVT ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } for ( unsigned FPRIndex = <NUM_LIT> ; FPRIndex != NumFPArgRegs ; ++ FPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( FPArgRegs [ FPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( FPArgRegs [ FPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> ,


<s> bool useAlternateSExtLoadCVTF32Pattern ( ) const { return


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmpgt ( a , b ) ; return ( __m128d ) _mm_setr_pd ( c [ <NUM_LIT> ] , __A [ <NUM_LIT>


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; if ( CPU . empty ( ) ) CPU = <STR_LIT> ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU ,


<s> addPass ( new InstructionSelect ( ) )


<s> rtx scratch = NULL_RTX ; if ( comparison == LAST_AND_UNUSED_RTX_CODE ) comparison = GET_CODE ( operands [ <NUM_LIT> ] ) ; else scratch = operands [ <NUM_LIT> ] ; sh_canonicalize_comparison ( comparison , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , mode , false ) ; rtx op1 = operands [ <NUM_LIT> ] ; if ( can_create_pseudo_p ( ) ) operands [ <NUM_LIT> ] = force_reg ( mode , op1 ) ; if ( ! REG_P ( operands [ <NUM_LIT> ] ) && ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) || ( mode == SImode && operands [ <NUM_LIT> ] != CONST0_RTX ( SImode ) && ( ( comparison != EQ && comparison != NE ) || ( REG_P ( op1 ) && REGNO ( op1 ) != R0_REG ) || ! satisfies_constraint_I08 ( operands [ <NUM_LIT> ] ) ) ) ) ) { if ( scratch && GET_MODE ( scratch ) == mode ) { emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = scratch ; } else if ( can_create_pseudo_p ( ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; } return


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; if ( NumDefs && ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx >= NumOps ) return false ; if ( SaturateOpcode ( Opcode ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeSaturatePos ( Opcode , insn ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { OpIdx += <NUM_LIT> ; return true ; } unsigned ShAmt = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ShAmt == <NUM_LIT> ) ShAmt = <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( ShAmt ) ) ; OpIdx += <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Opcode == <STR_LIT> ? <NUM_LIT> : getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; uint32_t mask = <NUM_LIT> ; if ( ! getBFCInvMask ( insn , mask ) ) return false ; MI . addOperand ( MCOperand :: CreateImm ( mask ) ) ; OpIdx += <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ) ) ; OpIdx += <NUM_LIT> ; return true ; } bool RmRn = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( ! isUnary ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , RmRn ? decodeRm ( insn ) : decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( isUnary && ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT>


<s> if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> )

, N0 , DAG . getConstant ( Log2_64 ( C ) , <STR_LIT> ) ) ;


<s> return ( ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> && RegNo


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand (


<s> if ( CONST_INT_P ( size ) ) return nds32_expand_cpymemsi_loop_known_size ( dstmem , srcmem , size , alignment


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { SDValue Broadcast = LowerVectorBroadcast ( Op , Subtarget , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , Subtarget , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getSimpleValueType ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getSimpleValueType


<s> bool Filler :: delayHasHazard ( MachineBasicBlock :: iterator candidate , bool & sawLoad , bool & sawStore , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { if ( candidate -> isImplicitDef ( ) || candidate -> isKill ( ) ) return true ; if ( candidate -> mayLoad ( ) ) { if ( sawStore ) return true ; sawLoad = true ; } if ( candidate -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } assert ( ( ! candidate -> isCall ( ) && ! candidate -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg )


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > C ( The<ISA_LIT>64LETarget ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR


<s> static bool isUnalignedMemmoryAccess ( uint64_t MemSize , uint64_t AlignInBits ) { assert ( isPowerOf2_64 ( MemSize ) && <STR_LIT> ) ; assert ( isPowerOf2_64 ( AlignInBits ) && <STR_LIT> ) ; if ( MemSize >


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , MachineInstr :: mmo_iterator MMOBegin , MachineInstr :: mmo_iterator MMOEnd , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget


<s> return __builtin_aarch64_sshll_nv8qi ( __a ,


<s> t2 = REGNO ( rt2 ) ; n = REGNO ( rn ) ; if ( ( TARGET_THUMB2 ) && ( ( wback && ( n == t || n == t2 ) ) || ( t == SP_REGNUM ) || ( t == PC_REGNUM ) || ( t2 == SP_REGNUM ) || ( t2 == PC_REGNUM ) || ( ! load && ( n == PC_REGNUM ) ) || ( load && ( t == t2 ) ) || ( ! wback && load && fix_cm3_ldrd && ( n == t ) ) ) ) return false ; if ( ( TARGET_ARM ) && ( ( wback && ( n == t || n == t2 ) ) || ( t2 == PC_REGNUM ) || ( t % <NUM_LIT>

!= <NUM_LIT> ) || ( t2 != t + <NUM_LIT> ) || ( n == PC_REGNUM ) ) ) return false ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler ( STI , T


<s> auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( Bitcast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> ,


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( Subtarget . hasSSE41 ( ) ) { if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 ,

Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> static DecodeStatus DecodeBranchTarget10MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> rtx addr , mem ; addr = gen_rtx_PLUS ( Pmode , frame_reg , GEN_INT ( offset ) ) ; mem = gen_frame_mem ( GET_MODE ( reg


<s> computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; if ( RPI . IsGPR ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> )


<s> string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I * <NUM_LIT> ) ; SExpr * add = ctx -> add ( <NUM_LIT> , ctx -> load ( <NUM_LIT> , SP )


<s> DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl ) = <NUM_LIT> ; resolve_unique_section ( decl , <NUM_LIT> , flag_function_sections ) ; allocate_struct_function ( decl , true ) ; cfun -> is_thunk = <NUM_LIT> ; current_function_decl = decl ; init_varasm_status ( ) ; assemble_start_function ( decl , name ) ; } else { const int align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; switch_to_section ( text_section ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } do_cfi = dwarf2out_do_cfi_asm ( ) ; if ( do_cfi ) output_asm_insn ( <STR_LIT> , NULL ) ; if ( flag_delayed_branch ) { output_asm_insn ( <STR_LIT> , NULL ) ; output_asm_insn ( <STR_LIT> , &


<s> SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget

( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> ) return InsertBitToMaskVector ( Op , DAG ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; auto * N2C = cast < ConstantSDNode > ( N2 ) ; unsigned IdxVal = N2C -> getZExtValue ( ) ; if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget -> hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc =


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; break ; } } if ( VT == <STR_LIT> && Opc == <STR_LIT> ) { unsigned SrcReg = fastEmitInst_i ( Opc ,


<s> const Constant * C = N -> getConstVal ( ) ; SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo ( ) , false , false ,


<s> ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> )


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! IMM12_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE

( mode ) - UNITS_PER_WORD ) ) return false ;


<s> tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; SET_TYPE_ALIGN ( type , boundary ) ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop


<s> SDValue getAddrNonPICSym64 ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Highest = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , <STR_LIT> ) ) ; SDValue Higher = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue HigherPart = DAG . getNode ( <STR_LIT> , DL , Ty , Highest , DAG . getNode ( <STR_LIT> , DL , Ty , Higher ) ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , Ty , HigherPart , Cst ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , Ty , Shift , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) ) ; SDValue Shift2 = DAG . getNode ( <STR_LIT> , DL , Ty , Add , Cst ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Shift2 , DAG

. getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> void emitLocalEntry ( MCSymbolELF * S , const MCExpr


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment (


<s> for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ;


<s> if ( verbose ) fprintf ( stream , <STR_LIT> , more , r ) ; return


<s> unsigned CalleeSavedFrameSize = <NUM_LIT> ; unsigned XMMCalleeSavedFrameSize = <NUM_LIT> ; auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int64_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , Align ( SlotSize ) ) ; <ISA_LIT>FI -> setHasSEHFramePtrSave ( true ) ; <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; SpillSlotOffset -= SlotSize ; } Register FPReg = TRI -> getFrameRegister ( MF


<s> FunctionPass * llvm :: create<ISA_LIT>LowOverheadLoopsPass ( )


<s> if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; const TargetLowering & TLI = DAG


<s> if ( ! ST -> isThumb2 ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial =


<s> return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op


<s> unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , SrcVT ) ) , DAG . getConstant ( BytesLeft , SizeVT ) , Align , isVolatile , AlwaysInline , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> } else break ; case V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , <NUM_LIT> ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case V16QImode


<s> case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( TARGET_FP_F16INST ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ; default : gcc_unreachable (


<s> assert ( Subtarget -> is64Bit ( ) ) ; if ( Subtarget -> isCallingConvWin64 ( CallConv ) ) { return None ; } const Function * Fn = MF . getFunction ( ) ; bool NoImplicitFloatOps = Fn -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ; assert ( ! ( MF . getTarget ( ) . Options . UseSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( MF . getTarget ( ) . Options . UseSoftFloat || NoImplicitFloatOps || ! Subtarget -> hasSSE1 (


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O


<s> Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ; res = DAG . getLoad ( getPointerTy ( ) , dl , Chain , res , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , res , Offset


<s> set_optab_libfunc ( sdiv_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , XFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , XFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode


<s> return ( Reg == <STR_LIT> || Reg == <STR_LIT> || ( Reg == <STR_LIT> && RestrictR15


<s> static SDValue combineUIntToFP ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext

( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ;


<s> } if ( MI . isDebugValue ( ) ) continue ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : { int Immed = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Immed != <NUM_LIT> ) { unsigned TrueReg1 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned TrueReg2 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TrueReg1 == TrueReg2 && TargetRegisterInfo :: isVirtualRegister ( TrueReg1 ) ) { MachineInstr * DefMI = MRI -> getVRegDef ( TrueReg1 ) ; if ( DefMI && DefMI -> getOpcode ( ) == <STR_LIT> ) { unsigned FeedImmed = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FeedReg1 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned FeedReg2 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ( FeedImmed == <NUM_LIT> || FeedImmed == <NUM_LIT> ) && FeedReg1 == FeedReg2 ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; ToErase = & MI ; Simplified = true ; } else if ( ( Immed == <NUM_LIT> || Immed == <NUM_LIT> ) && FeedImmed == <NUM_LIT> && FeedReg1 == FeedReg2 ) { DEBUG ( dbgs ( ) << <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) { initAsmInfo ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc


<s> if ( ! isShiftedImm ( ) && ! isImm ( ) ) return false ; const MCExpr * Expr ; if ( isShiftedImm ( ) ) { unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else Expr = getImm ( ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> void mips_declare_common_object ( FILE * stream , const char * name , const char * init_string ,

unsigned HOST_WIDE_INT size , unsigned int align , bool takes_alignment_p ) {


<s> const bool UseZeroBasedSandbox = FlagUseZeroBasedSandbox ; if ( ! UseZeroBasedSandbox ) { MCInst Tmp ; Tmp . setOpcode ( <STR_LIT> ) ; Tmp . addOperand ( MCOperand :: CreateReg ( Reg64 ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( Reg64


<s> return CreateReg ( Index , RegKind_FCC , RegInfo


<s> AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal =


<s> unsigned char CCBits = static_cast < unsigned char > ( Firstcond & <NUM_LIT> ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = NumTZ + <NUM_LIT> ; Pos <= <NUM_LIT> ; ++ Pos ) { unsigned Else = ( Mask >> Pos ) & <NUM_LIT> ; ITStates . push_back ( CCBits ^ Else ) ; } ITStates . push_back


<s> if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } Regs . clear ( )


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1

, InverseMask , Subtarget , DAG ) ) return Insertion ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; SDLoc dl ( Op ) ; unsigned Opc ; switch ( Op . getOpcode


<s> if ( isGPRAsmReg ( ) && RegIdx . Index == <NUM_LIT> ) return true ; return Kind


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill


<s> bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( IntField ) ; } assert ( AllIntFields && <STR_LIT> ) ; return ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | (

Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] ) ;


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Table , Index ) ; if ( Subtarget -> isThumb2 ( ) || ( Subtarget -> hasV8MBaselineOps ( ) && Subtarget -> isThumb ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) || Subtarget -> isPIP ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Table , Addr ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr ,


<s> switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT>


<s> auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildPtrMask ( PtrTy , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrSize ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Kind = VK_<ISA_LIT>_HIGHEST ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return new ( Ctx ) <ISA_LIT>MCExpr (


<s> cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode


<s> SDValue getAddrGlobal ( NodeTy * N , EVT Ty , SelectionDAG & DAG , unsigned

Flag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const {


<s> Instr ( unsigned Opcode , Register Def , Register LHS , Register RHS ) : Opcode ( Opcode ) , Def ( Def ) , LHS


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return true ; } if ( DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOT_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 ||

ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) {


<s> static SDValue PerformFADDCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , LHS , RHS ) ; return SDValue (


<s> bool <ISA_LIT>AsmBackend :: canPadBranches ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( ! OS . getCurrentSectionOnly ( ) -> getKind ( ) . isText ( ) ) return false ; if ( OS . getAssembler ( ) . isBundlingEnabled ( ) ) return false ; if ( ! ( STI . hasFeature ( <STR_LIT> ) || STI . hasFeature ( <STR_LIT> ) ) )


<s> static inline void __ev_clr_spefscr_field ( int mask ) { int i ; i = __builtin_spe_mfspefscr ( )


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( DL , Ty , true ) ; if ( Evt == <STR_LIT> || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT )


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; assert ( EnableSegmentedStacks ) ; unsigned TlsReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TlsOffset = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineBasicBlock * mallocMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * bumpMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * continueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * AddrRegClass = getRegClassFor ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned mallocPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , bumpSPPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , tmpSPVReg = MRI . createVirtualRegister ( AddrRegClass ) , SPLimitVReg = MRI . createVirtualRegister ( AddrRegClass ) , sizeVReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , physSPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineFunction :: iterator MBBIter = BB ; ++ MBBIter ; MF -> insert ( MBBIter , bumpMBB ) ; MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> )

, SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ;


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineFunction * F = MBB -> getParent ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * newMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * nextMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , newMBB ) ; F -> insert ( MBBIter , nextMBB ) ; nextMBB -> splice ( nextMBB -> begin ( ) , thisMBB , llvm :: next ( MachineBasicBlock :: iterator ( bInstr ) ) , thisMBB -> end ( ) ) ; nextMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; assert ( bInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; MachineOperand & dest1Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & dest2Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> + <STR_LIT> ; ++ i ) { argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; if ( argOpers [ i ] -> isReg ( ) && argOpers [ i ] -> isUse ( ) ) argOpers [ i ] -> setIsKill ( false ) ; } int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t2 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx - <NUM_LIT> ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MachineOperand newOp3 = * (


<s> SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / ElSize ; unsigned NumEltsPerLane = <NUM_LIT> / ElSize ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef )


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>EmitLoad ( EVT VT , unsigned & ResultReg , Address & Addr , unsigned Alignment , bool isZExt , bool allocReg ) { assert ( VT . isSimple ( ) && <STR_LIT> ) ; unsigned Opc ; bool useAM3 = false ; bool needVMOV = false ; TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr ,


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2siv8qi ( (


<s> const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo (


<s> unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDLoc dl ( Op ) ; LLVMContext * Context = DAG . getContext ( ) ; static const uint32_t CV0 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Constant * C0 = ConstantDataVector :: get ( * Context , CV0 ) ; auto PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , PtrVT , Align ( <NUM_LIT> ) ) ; SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , Align ( <NUM_LIT> ) ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( OpNo ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub ; SDValue Chain ; if ( IsStrict ) { Sub = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , XR2F , CLod1 } ) ; Chain = Sub . getValue ( <NUM_LIT> ) ; } else Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( ! IsStrict && Subtarget . hasSSE3 ( ) && shouldUseHorizontalOp ( true , DAG , Subtarget ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue Shuffle = DAG . getVectorShuffle ( <STR_LIT> , dl , Sub , Sub , { <NUM_LIT> , - <NUM_LIT> } ) ; if ( IsStrict ) { Result = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Shuffle , Sub } ) ; Chain = Result . getValue ( <NUM_LIT> ) ; } else Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ; if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ; } return FALSE


<s> SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; SDValue BP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Ops [ <NUM_LIT> ] = { BP , Hi . getValue


<s> ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; return ret


<s> icode = CODE_FOR_ccmpdi ; break ; case SFmode : cmp_mode = SFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf ; break ; case DFmode : cmp_mode = DFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; target = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; aarch64_cond = aarch64_get_condition_code_1 ( cc_mode , ( rtx_code ) cmp_code ) ; if ( bit_code != AND ) { prev = gen_rtx_fmt_ee ( REVERSE_CONDITION ( GET_CODE ( prev ) , GET_MODE ( XEXP ( prev , <NUM_LIT> ) )

) , VOIDmode , XEXP ( prev , <NUM_LIT> ) , const0_rtx ) ;


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitExtend ( <STR_LIT> Opc , EVT DstVT , unsigned Src , EVT SrcVT


<s> if ( ! isa < Instruction > ( V ) ) return true ; const auto * I = cast < Instruction > ( V ) ; if ( FuncInfo . MBBMap [ I -> getParent ( ) ] ==


<s> unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! ValAndVReg ) return None ; uint64_t C = ValAndVReg -> Value ; if ( isLegalArithImmed ( C ) ) return None ; switch ( P ) { default : return None ; case CmpInst :: ICMP_SLT : case CmpInst :: ICMP_SGE : if ( ( Size == <NUM_LIT> && static_cast < int64_t > ( C ) == INT64_MIN ) || ( Size == <NUM_LIT> && static_cast < int32_t > ( C ) == INT32_MIN ) ) return None ; P = ( P == CmpInst :: ICMP_SLT ) ? CmpInst :: ICMP_SLE : CmpInst :: ICMP_SGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_ULT : case CmpInst :: ICMP_UGE : if ( C == <NUM_LIT> ) return None ; P = ( P == CmpInst :: ICMP_ULT ) ? CmpInst :: ICMP_ULE : CmpInst :: ICMP_UGT ; C -= <NUM_LIT> ; break ; case CmpInst :: ICMP_SLE : case CmpInst


<s> assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; } } return MadeChange


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true


<s> MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B ) break ; } return BestGrowth != ~ <NUM_LIT>


<s> const char ( * Nops ) [ <NUM_LIT> ] = STI . getFeatureBits ( ) [ <STR_LIT> ] ? Nops16Bit : Nops32Bit ; uint64_t MaxNopLength = ( uint64_t ) getMaximumNopSize ( ) ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr & MI )


<s> unsigned Directive = Subtarget . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } DebugLoc DL


<s> } if ( SDValue LD = combineToConsecutiveLoads ( VT , SDValue ( N , <NUM_LIT> ) , dl , DAG , Subtarget , true ) ) return LD ; if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG , DCI , Subtarget ) ) return Shuffle ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; APInt KnownUndef , KnownZero ; APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( Op , DemandedElts , KnownUndef , KnownZero , DCI ) ) return


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isDataRel ( ) || Kind . isBSS ( ) || Kind . isCommon (


<s> int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( MI . isPredicable ( ) ) MIB . add ( predOps (


<s> assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; } const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc


<s> case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT ,


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return CE -> getValue ( ) >= <NUM_LIT> && CE -> getValue (


<s> static __inline vec_double2 spu_slqwbytebc ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbybi ( ( qword ) (


<s> bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; switch ( STI . getRegisterInfo ( ) -> getSpillSize ( * RC ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( STI . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; V1 = Base ; V2 = Insert ; return true ; } } return


<s> Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; PtrInOperand = true ; } Start = Tok . getLoc ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) { return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; } return <STR_LIT> ( RegNo , Start , End ) ; } return ParseIntelSegmentOverride ( RegNo , Start , Size ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( <NUM_LIT> , Start , <NUM_LIT> , false , Size ) ; AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; bool isSymbol = SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) != MCExpr :: Constant ; int64_t Imm = SM . getImm ( ) ; if ( SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) == MCExpr :: Constant ) SM . getSym ( ) -> evaluateAsAbsolute ( Imm ) ; if ( StartTok . isNot ( AsmToken :: Identifier ) && StartTok . isNot ( AsmToken :: String ) && isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Start ) ; else InstInfo -> AsmRewrites -> emplace_back ( AOK_Imm , Start , Len , Imm ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac


<s> const GlobalValue * <ISA_LIT>ConstantPoolConstant :: getGV ( )


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; APInt BitImm = APInt ( ResTy . getVectorElementType ( ) . getSizeInBits ( ) , <NUM_LIT> ) << cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; SDValue BitMask = DAG . getConstant ( ~ BitImm , DL , ResTy ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy

, Op -> getOperand ( <NUM_LIT> ) , BitMask ) ;


<s> auto & Ctx = MIRBuilder . getMF ( ) . getFunction ( ) -> getContext ( ) ; assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < unsigned , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size (


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetVirt


<s> for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ( isReservedReg ( MF , <STR_LIT> ) || isReservedReg ( MF , <STR_LIT> ) ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return isReservedReg ( MF , <STR_LIT> ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return isReservedReg ( MF , <STR_LIT> ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static void mips_sim_init ( struct mips_sim * state , state_t dfa_state ) { state -> issue_rate = mips_issue_rate


<s> if ( * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) != ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) return <NUM_LIT> ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; StackAdjust = <NUM_LIT> ; SavedRegIdx = <NUM_LIT> ; MinAbsOffset = std :: numeric_limits < int > :: max ( ) ; InstrOffset += MoveInstrSize ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { StackSize = Inst . getOffset ( ) / StackDivide ; ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; SavedRegs [ SavedRegIdx ++ ] = Reg ; StackAdjust += OffsetSize ; MinAbsOffset = std :: min ( MinAbsOffset , abs ( Inst . getOffset ( ) ) ) ; InstrOffset += PushInstrSize ( Reg ) ; break ; } } } StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; if ( SavedRegIdx != <NUM_LIT> && MinAbsOffset != <NUM_LIT> * ( int ) OffsetSize ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { SubtractInstrIdx += InstrOffset ; ++ StackAdjust ; if ( ( StackSize & <NUM_LIT> ) == StackSize ) { CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IMMD ; CompactUnwindEncoding |= ( StackSize & <NUM_LIT> ) << <NUM_LIT> ; } else { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IND ; CompactUnwindEncoding |= ( SubtractInstrIdx & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; } std :: reverse ( & SavedRegs [ <NUM_LIT> ] , & SavedRegs


<s> int Split = Size / Delta ; int TruncatedVectorStart = SwappedOps ? Size : <NUM_LIT> ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Split , TruncatedVectorStart , Delta ) ) return false ; if ( isAnyInRange ( Mask . slice ( Split , Size - Split ) , TruncatedVectorStart

, TruncatedVectorStart + Size ) ) return false ;


<s> if ( ! blockIsBefore ( LoopExit2 , LoopExit ) && ( LoopExit2 == Preheader || blockIsBefore ( LoopExit2 , Preheader ) ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } if ( CanMove ) { for ( auto It = LoopExit -> getIterator ( ) ; It != Preheader -> getIterator ( ) ; It ++ ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( Terminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LETarget = Terminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LETarget == LoopExit ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } } if ( ! CanMove ) break ; } if ( CanMove ) { moveBasicBlock ( LoopExit , Preheader ) ; Changed = true ; break ; } } } return


<s> if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) if ( auto * CI = dyn_cast < CallInst > ( I ) ) if ( auto * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return true ; return


<s> return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN


<s> for ( Use & U : I -> uses ( ) ) { User * V = U . getUser ( ) ; if ( isa < PHINode > ( V ) || V == Store ) continue ; replaceWithTileLoad ( U , I8Ptr )


<s> if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return AddRequiredExtensionForVMULL ( N -> getOperand ( <NUM_LIT> ) , DAG , N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , N -> getOpcode ( ) ) ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) return SkipLoadExtensionForVMULL ( LD , DAG ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType (


<s> if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( featureBits [ <STR_LIT> ] && ( ( Num & <NUM_LIT> ) == <NUM_LIT> ||

( Num & <NUM_LIT> ) == <NUM_LIT> ) ) return false ;


<s> set_reg ( sr -> curr . reg + reg , UNW_WHERE_SPREL , sr -> region_start + sr -> region_len


<s> if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , true ) ; else if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , false ) ; else ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) ) ; } if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffsetReg ( <NUM_LIT> ) ; Addr . setShift ( <NUM_LIT> ) ; Addr . setExtendType (


<s> bool isActive ( ) const { return Active


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg )


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const


<s> } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass (


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI


<s> return __builtin_ia32_vcvtqq2ph128_mask ( ( __v2di ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) -


<s> save_mask = & cfun -> machine -> save_mask ; CLEAR_HARD_REG_SET ( * save_mask ) ; var_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) get_frame_size ( ) ) ; out_args_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) crtl -> outgoing_args_size ) ; total_size = var_size + out_args_size ; save_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= LAST_GP_REGNUM ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { SET_HARD_REG_BIT ( * save_mask , regno ) ; save_reg_size += <NUM_LIT> ; } save_reg_size = PRU_STACK_ALIGN ( save_reg_size ) ; total_size += save_reg_size


<s> bool <ISA_LIT>PostSelectOptimize :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; assert ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties ::


<s> static __inline qword si_xshw ( qword a ) { vec_short8 av ; av = ( vec_short8 ) ( a ) ; return ( ( qword ) ( vec_unpackh ( vec_perm ( av , av , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> if ( JT . MBBs . empty ( ) ) return false ; int MaxOffset = std :: numeric_limits < int > :: min ( ) , MinOffset = std :: numeric_limits < int > :: max ( ) ; MachineBasicBlock * MinBlock = nullptr ; for ( auto * Block : JT . MBBs ) { int BlockOffset = BlockInfo [ Block -> getNumber ( ) ] ; assert ( BlockOffset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; MaxOffset = std :: max ( MaxOffset , BlockOffset ) ; if ( BlockOffset <= MinOffset ) { MinOffset = BlockOffset ; MinBlock = Block ; } } assert ( MinBlock && <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( MinOffset - Offset ) ) { ++ NumJT32 ; return false ; } int Span = MaxOffset -


<s> return ( Subtarget -> isThumb1Only ( ) ? <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { unsigned SType


<s> void final_prescan_insn ( rtx_insn * insn , rtx * opvec ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( TARGET_DUMPISIZE ) fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( TARGET_RELAX ) { if ( rtx note = find_reg_note ( insn , REG_LABEL_OPERAND , NULL_RTX ) ) { rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , <NUM_LIT>


<s> if ( ABI . IsN64 ( ) && isPositionIndependent ( )

) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ;


<s> Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; if ( IsPIC ) Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , getGlobalReg ( DAG , <STR_LIT> ) ) ; return Result


<s> dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( layout . locals_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp != layout


<s> MulPairs . push_back ( std :: make_pair


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; if ( llvm :: ELF :: R_AARCH64_PREL64 != pReloc . type ( ) ) A += pReloc . target ( ) & get_mask ( pParent . getSize ( pReloc . type ( ) ) ) ; else A += pReloc . target ( ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( <NUM_LIT> != ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) ) { if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } } } Relocator :: DWord X = S + A


<s> HasERI = false ; HasCDI = false ; HasPFI = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false


<s> if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost +


<s> case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ; } case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ?


<s> bool <ISA_LIT>SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo (


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF


<s> unsigned RelaxedOp = getRelaxedOpcode ( IF -> getInst ( ) . getOpcode ( ) ) ; if ( RelaxedOp == IF -> getInst ( ) . getOpcode ( ) ) { SmallString < <NUM_LIT>


<s> static __inline unsigned long long sh_media_LDLO_L ( void * p ,


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const LLVM_OVERRIDE { return


<s> TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo (


<s> void x86_output_aligned_bss ( FILE * file , tree decl ATTRIBUTE_UNUSED , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) named_section ( decl , <STR_LIT> , <NUM_LIT> ) ; else bss_section ( ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl =


<s> if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) .


<s> Inst . addOperand ( MCOperand :: createReg ( XRegs [ getReg (


<s> CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * CurArgReg = ArgRegs , * ArgRegEnd = ArgRegs + <NUM_LIT> ; unsigned ArgOffset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT ObjectVT = VA . getValVT ( ) ; switch ( ObjectVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ins [ i ] . Used ) { if ( CurArgReg < ArgRegEnd ) ++ CurArgReg ; InVals . push_back ( DAG . getUNDEF ( ObjectVT ) ) ; } else if ( CurArgReg < ArgRegEnd ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MF . getRegInfo ( ) . addLiveIn ( * CurArgReg ++ , VReg ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; if ( ObjectVT != <STR_LIT> ) { unsigned AssertOp = <STR_LIT> ; Arg = DAG . getNode ( AssertOp , dl , <STR_LIT> , Arg , DAG . getValueType ( ObjectVT ) ) ; Arg = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; } InVals . push_back ( Arg ) ; } else { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , ArgOffset ) ; SDValue FIPtr = DAG . getFrameIndex ( FrameIdx , <STR_LIT> ) ; SDValue Load ; if ( ObjectVT == <STR_LIT> ) { Load = DAG . getLoad ( <STR_LIT> , dl , Chain , FIPtr , NULL , <NUM_LIT> ) ; } else { <STR_LIT> LoadOp = <STR_LIT> ; unsigned Offset = <NUM_LIT> - std :: max ( <NUM_LIT> , ObjectVT . getSizeInBits ( ) / <NUM_LIT> ) ; FIPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FIPtr , DAG . getConstant ( Offset , <STR_LIT> ) ) ; Load = DAG . getExtLoad ( LoadOp , dl , <STR_LIT> , Chain , FIPtr , NULL , <NUM_LIT> , ObjectVT ) ; Load = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Load ) ; } InVals . push_back ( Load ) ; } ArgOffset +=


<s> else if ( <STR_LIT> ( Op1 . getNode ( ) ) ) NotOp = Op0 ; else return SDValue ( ) ; if ( NotOp -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Ty , NotOp -> getOperand

( <NUM_LIT> ) , NotOp -> getOperand ( <NUM_LIT> ) ) ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG


<s> StringRef getPassName ( ) const override { return


<s> RelEntry ( const ELFRelocationEntry & R , const MCSymbol * S , int64_t O ) : Reloc ( R ) , Sym (


<s> unsigned Shift = getShiftExtendAmount ( ) ; return getShiftExtendType ( ) == <STR_LIT> && ( Shift == <NUM_LIT> || Shift == <NUM_LIT> || Shift ==


<s> static SDValue performSUBCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) { if ( Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . in<ISA_LIT>16Mode ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return performMADD_MSUBCombine ( N , DAG , Subtarget ) ; return SDValue (


<s> unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned Offset = BBInfo [ i - <NUM_LIT> ] . Offset + BBInfo [ i - <NUM_LIT> ] . Size ; BBInfo [ i ]


<s> int includes_lshift_p ( rtx shiftop , rtx andop ) { unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT )


<s> return __builtin_mve_vsubq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N ,


<s> MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> ,


<s> MCSection * <ISA_LIT>MCExpr :: findAssociatedSection (


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue


<s> SDLoc dl ( Op ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue SafeShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , SafeShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl


<s> if ( NextElement == - <NUM_LIT> ) { NextElement = Mask [ i ] != <NUM_LIT> ? VectorType . getVectorNumElements ( ) : <NUM_LIT> ; IsZeroSideLeft = NextElement != <NUM_LIT> ; } if ( NextElement != Mask [ i ] ) return false ; NextElement ++