<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( SDValue Not = IsNOT ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( VT , Not ) , N -> getOperand ( <NUM_LIT> ) ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } return SDValue (


<s> unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > <NUM_LIT> && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a =


<s> if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } return SDValue (


<s> SMLoc S = getLoc ( ) ; SMLoc E ; const MCExpr * Res ; if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return MatchOperand_Success


<s> inline int vec_all_ge ( vector float a1 ,


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , StringRef FS ) { bool VectorABI = UsesVectorABI ( CPU , FS ) ; std :: string Ret = <STR_LIT> ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( VectorABI ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT>


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { unsigned NewImm = Imm ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT>


<s> BitGroups . erase ( std :: remove_if ( BitGroups . begin ( ) , BitGroups . end ( ) ,


<s> NewBase = findFreeReg ( isThumb1 ? <STR_LIT> : <STR_LIT> ) ; if ( NewBase == <NUM_LIT> ) return nullptr ; } int BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Base == <STR_LIT> ) ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . add ( predOps ( Pred , PredReg ) ) ; Base = NewBase ; KillOldBase = true ; } if ( BaseOpc == <STR_LIT> ) { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset / <NUM_LIT> ) . add ( predOps ( Pred , PredReg ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . add ( t1CondCodeOp ( true ) ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) ; } else { BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) ; } Base =


<s> if ( AFI -> isThumbFunction ( ) ) { OutStreamer . EmitAssemblerFlag (


<s> __o = __builtin_aarch64_set_qregoiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2df ( ( __builtin_aarch64_simd_df * ) __a ,


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case <NUM_LIT> :


<s> return create<ISA_LIT>MachObjectWriter ( OS , false ,

MachO :: CPU_TYPE_<ISA_LIT> , Subtype ) ;


<s> return __builtin_mve_vorrq_n_uv4si ( __a ,


<s> switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg (


<s> void Thumb1InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI , Reloc :: Model RM ) const { if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase (


<s> return true ; } if ( DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOT_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOT_PAGE_LO15 ) { return true ; } else if ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF || DarwinRefKind

== MCSymbolRefExpr :: VK_TLVPPAGEOFF ) {


<s> if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_PAGE_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE_LO15 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( parseToken ( AsmToken :: Colon , <STR_LIT> ) ) return true ; } if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; if ( HasELFModifier ) ImmVal = <ISA_LIT>MCExpr :: create ( ImmVal , RefKind , getContext (


<s> tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else { CmpMask = CmpValue = <NUM_LIT> ; } return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( VarArgsNumGPR , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( VarArgsNumFPR , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( VarArgsStackOffset , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset


<s> SDValue getAddrNonPIC ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG ) const { SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG ,


<s> const MCSection * <ISA_LIT>MCAsmInfo :: getNonexecutableStackSection ( MCContext &


<s> return contractCrossBankCopyIntoStore ( I , MRI ) ; case TargetOpcode :: G_PTR_ADD : return convertPtrAddToAdd ( I , MRI ) ; case TargetOpcode :: G_LOAD : { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( ! DstTy . isPointer ( ) ) return false ; MRI . setType ( DstReg , LLT :: scalar ( <NUM_LIT> ) ) ; return true ; } case <STR_LIT> : { LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! DstTy . getElementType ( ) . isPointer ( ) ) return false ; MachineIRBuilder MIB ( I ) ; auto NewSrc = MIB . buildCopy ( LLT :: scalar ( <NUM_LIT> ) , I . getOperand


<s> const MCInstrDesc & OR = TII -> get ( <STR_LIT> ) ; const MCInstrDesc & XOR = TII -> get ( <STR_LIT> ) ; if ( Dest0 == Src1 && Dest1 == Src0 ) { BuildMI ( MBB , MBBI , DL , XOR , Dest0 ) . addReg ( Dest0 ) . addReg ( Dest1 ) ; BuildMI ( MBB , MBBI , DL , XOR , Dest1 ) . addReg ( Dest0 ) . addReg ( Dest1 ) ; BuildMI ( MBB , MBBI , DL , XOR , Dest0 ) . addReg ( Dest0 ) . addReg ( Dest1 ) ; } else if ( Dest0 != Src0 || Dest1 != Src1 ) { if ( Dest0 == Src1 || Dest1 != Src0 ) { BuildMI ( MBB , MBBI , DL , OR , Dest1 ) . addReg ( Src1 ) . addReg ( Src1 ) ; BuildMI ( MBB , MBBI , DL , OR , Dest0 ) . addReg ( Src0 ) . addReg ( Src0 ) ; } else


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; uint64_t Position = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) , Fixups , STI ) ; uint64_t Size = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ,


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && IsLegalToFold ( N , P , P , OptLevel )

) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ;


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value

>> ( ( <NUM_LIT> - i - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> return new <ISA_LIT>LowerMASSVEntries (


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , dl , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return BB


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue RegSeq = createQTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( isExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs +


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; case


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI -> eraseFromParent ( ) ; return


<s> result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char ) perm_mask ) ) ; return result [ <NUM_LIT>


<s> group_end = ( can_issue_more == <NUM_LIT> || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; can_issue_more = force_new_group ( sched_verbose , dump , group_insns , next_insn , & group_end , can_issue_more , & group_count ) ; if ( group_end ) { group_count ++ ; can_issue_more = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } if ( GET_MODE ( next_insn ) == TImode && can_issue_more ) PUT_MODE ( next_insn , VOIDmode


<s> Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset = State . AllocateStack ( SizeInBytes , OrigAlign ) ; if ( ! Reg ) State . addLoc ( CCValAssign :: getMem ( ValNo

, ValVT , Offset , LocVT , LocInfo ) ) ;


<s> static SDValue LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & , const Triple & TheTriple , StringRef ) { if ( ! TheTriple . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return new <ISA_LIT>AsmBackend ( T , TheTriple . getOS (


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOneValue ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc

( N ) , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ;


<s> return false ; case FK_Data_1 : Log2Size = Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_2 : Log2Size = Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_4 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case FK_Data_8 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : return false ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr ::


<s> <ISA_LIT>JITInfo :: <ISA_LIT>JITInfo ( <ISA_LIT>Subtarget & STI ) : Subtarget ( STI ) , is64Bit ( STI . is<ISA_LIT>64 ( ) ) { useGOT =


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory


<s> if ( ! Subtarget . hasSSE41 ( ) || ! Op -> hasOneUse ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > VecIns ; if ( ! matchScalarReduction ( Op , <STR_LIT> , VecIns ) ) return SDValue ( ) ; EVT VT = VecIns [ <NUM_LIT> ] . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; MVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = VecIns . size ( ) ; i < e ; ++ i ) VecIns [ i ] = DAG . getBitcast ( TestVT , VecIns [ i ] ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [


<s> auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount ::

getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ;


<s> if ( FrameRegUpdate && * FrameRegUpdate ) LoopSize -= LoopSize % <NUM_LIT> ; MachineInstr * LoopI = BuildMI ( * MBB , InsertI , DL , TII -> get ( ZeroData ? <STR_LIT> : <STR_LIT> ) ) . addDef ( SizeReg ) . addDef ( BaseReg ) . addImm ( LoopSize ) . addReg ( BaseReg ) . setMemRefs ( CombinedMemRefs ) ; if ( FrameRegUpdate ) LoopI -> setFlags ( FrameRegUpdateFlags ) ; int64_t ExtraBaseRegUpdate = FrameRegUpdate ? ( * FrameRegUpdate - FrameRegOffset . getBytes ( ) - Size ) : <NUM_LIT> ; if ( LoopSize < Size ) { assert ( FrameRegUpdate ) ; assert ( Size - LoopSize == <NUM_LIT>


<s> assert ( isImm ( ) && <STR_LIT> ) ; if ( ! isa < MCConstantExpr > ( getImm ( ) ) ) { Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; return ; } const MCConstantExpr * CE = cast < MCConstantExpr


<s> void emitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT>


<s> Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; if ( NeedExtend ) LHSReg = emitIntExt ( SrcVT , LHSReg , RetVT , IsZExt ) ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = IsZExt ? C -> getZExtValue ( ) : C -> getSExtValue ( ) ; if ( C -> isNegative ( ) ) ResultReg = emitAddSub_ri ( ! UseAdd , RetVT , LHSReg , - Imm , SetFlags , WantResult ) ; else ResultReg = emitAddSub_ri ( UseAdd , RetVT , LHSReg , Imm , SetFlags , WantResult ) ; } else if ( const auto * C = dyn_cast < Constant > ( RHS ) ) if ( C -> isNullValue ( ) ) ResultReg = emitAddSub_ri ( UseAdd , RetVT , LHSReg , <NUM_LIT> , SetFlags , WantResult ) ; if ( ResultReg ) return ResultReg ; if ( ExtendType != <STR_LIT> && RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) if ( ( SI -> getOpcode ( ) == Instruction :: Shl ) && ( C -> getZExtValue ( ) < <NUM_LIT> ) ) { Register RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , RHSReg , ExtendType , C -> getZExtValue ( ) , SetFlags , WantResult ) ; } Register RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , RHSReg , ExtendType , <NUM_LIT> , SetFlags , WantResult ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; Register RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitAddSub_rs ( UseAdd , RetVT , LHSReg , RHSReg , <STR_LIT> , ShiftVal , SetFlags , WantResult ) ; if ( ResultReg


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ) ; OutStreamer -> EmitSymbolValue ( DotSym , <NUM_LIT> ) ; OutStreamer -> PopSection ( ) ; OutStreamer -> EmitLabel ( DotSym ) ; } if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { EmitNop ( Ctx , * OutStreamer , <NUM_LIT> , getSubtargetInfo ( ) ) ; return ; } MCSymbol * fentry = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; const MCSymbolRefExpr * Op = MCSymbolRefExpr :: create ( fentry , MCSymbolRefExpr :: VK_PLT , Ctx ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr (


<s> return __builtin_mve_vldrdq_gather_base_sv2di ( __addr ,


<s> SDLoc DL ( Op ) ; SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand


<s> case Triple :: Darwin : return new Darwin<ISA_LIT>AsmBackend ( T ) ; default : return <NUM_LIT>


<s> static __inline unsigned long long sh_media_MMUL_W ( unsigned long


<s> pavgb ( uint8x8_t s , uint8x8_t t ) { return __builtin_loongson_pavgb ( s ,


<s> __m64_union res ; res . as_int [ <NUM_LIT> ] = __i0 ; res . as_int [ <NUM_LIT> ]


<s> case AsmToken :: Minus : case AsmToken :: Integer : if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Op = <STR_LIT> ( EVal , S , E ) ; break ; case AsmToken :: Identifier : { StringRef Identifier ; if ( ! getParser ( ) . parseIdentifier ( Identifier ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; if ( isCall && getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) Res = <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 , Res , getContext ( ) ) ; Op = <STR_LIT> ( Res , S , E ) ; } break ; } } return ( Op ) ?


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModeImm12OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Reg = <NUM_LIT> , Imm12 = <NUM_LIT> ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isReg ( ) ) { const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( MO1 . isImm ( ) ) { isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups , STI ) ; } else if ( MO1 . isExpr ( ) ) { assert ( ! isThumb ( STI ) && ! isThumb2 ( STI ) && <STR_LIT> ) ; Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; isAdd = false ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO1 . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; } } else if ( MO . isExpr ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; }


<s> } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_blendmw_512_mask ( ( __v32hi ) __A , ( __v32hi )


<s> if ( check ( getTok ( ) . isNot ( AsmToken :: Comma ) , getLoc ( ) , <STR_LIT> ) ) return true ; Lex (


<s> static bool is<ISA_LIT>LogicalCmp ( SDValue Op ) { unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> ) return true ;


<s> for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand :: CreateReg ( Regs [ i ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> )


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> return ( __m128i ) __builtin_ia32_movdquqi128_mask ( ( __v16qi ) __A , ( __v16qi ) _mm_setzero_hi ( ) , ( __mmask16


<s> static void rs6000_xcoff_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( decl_readonly_section_1 ( decl , reloc , <NUM_LIT> ) ) { if ( TREE_PUBLIC ( decl ) ) read_only_data_section ( ) ; else read_only_private_data_section ( ) ; } else { if ( TREE_PUBLIC ( decl )


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && ! hasHardQuad ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB


<s> DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! NeverUseSaveRestore ) { if ( isUInt < <NUM_LIT> > ( FrameSize ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; else { int Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; if ( isInt < <NUM_LIT> > ( Remainder ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Remainder ) ; else adjustStackPtrBig ( SP , Remainder , MBB , I , <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Base ) ; } } else { adjustStackPtrBig ( SP , FrameSize , MBB , I , <STR_LIT> , <STR_LIT> ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB1 . addReg ( <STR_LIT> ) ; MIB1 . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB0 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB0 . addReg ( <STR_LIT> ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB2 . addReg ( <STR_LIT> ) ; MIB2 . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB3 = BuildMI ( MBB , I , DL ,


<s> MachineFunctionProperties getRequiredProperties ( )


<s> return ( __m128d ) __builtin_ia32_addsubpd ( ( __v2df


<s> static rtx pa_trampoline_adjust_address ( rtx addr ) { if ( ! TARGET_64BIT ) addr = memory_address ( Pmode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) ; return addr


<s> I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; return true ; } return false


<s> if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } uint32_t other_half = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : other_half = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF : other_half = FixedValue & <NUM_LIT> ; FixedValue = ( ( FixedValue >> <NUM_LIT> ) + ( ( FixedValue & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF : other_half = FixedValue & <NUM_LIT> ; FixedValue = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MachO :: any_relocation_info MRE ; makeScatteredRelocationInfo ( MRE , other_half , MachO :: GENERIC_RELOC_PAIR , Log2Size , IsPCRel , Value2 ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) return false ; } MachO :: any_relocation_info MRE ; makeScatteredRelocationInfo ( MRE , FixupOffset , Type , Log2Size , IsPCRel , Value ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; return


<s> index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SPFI ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MPI , Align ( <NUM_LIT> ) ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . IsSExt = false ; Entry . IsZExt =


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( scan ) , ( unsigned long ) minipool_barrier -> address , align64 ? <NUM_LIT> : <NUM_LIT> ) ; scan = emit_label_after ( gen_label_rtx ( ) , scan ) ; scan = emit_insn_after ( align64 ? gen_align_8 ( ) : gen_align_4 ( ) , scan ) ; scan = emit_label_after ( minipool_vector_label , scan ) ; for ( mp = minipool_vector_head ; mp != NULL ; mp = nmp ) { if ( mp -> refcount > <NUM_LIT> ) { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , ( unsigned ) mp -> offset , ( unsigned long ) mp -> min_address , ( unsigned long ) mp -> max_address ) ; arm_print_value ( dump_file , mp -> value ) ; fputc ( '\n' , dump_file ) ; } switch ( mp -> fix_size ) { case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_1 ( mp -> value ) , scan ) ; break ; case


<s> mips_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named ) ; if ( info . reg_offset == MAX_ARGS_IN_REGISTERS ) return NULL ; if ( TARGET_NEWABI && TARGET_HARD_FLOAT && arg . named && arg . type != <NUM_LIT> && TREE_CODE ( arg . type ) == RECORD_TYPE && TYPE_SIZE_UNIT ( arg . type ) && tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( arg . type ) ) ) { tree field ; for ( field = TYPE_FIELDS ( arg . type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD && tree_fits_shwi_p ( bit_position ( field ) ) && int_bit_position ( field ) % BITS_PER_WORD == <NUM_LIT> ) break ; if ( field != <NUM_LIT> ) { unsigned int i ; HOST_WIDE_INT bitpos ; rtx ret ; ret = gen_rtx_PARALLEL ( arg . mode , rtvec_alloc ( info . reg_words ) ) ; bitpos = <NUM_LIT> ; field = TYPE_FIELDS ( arg . type ) ; for ( i = <NUM_LIT> ; i < info . reg_words ; i ++ ) { rtx reg ; bool zero_width_field_abi_change = false ; for ( ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) continue ; if ( DECL_SIZE ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) { zero_width_field_abi_change = true ; continue ; } if ( int_bit_position ( field ) >= bitpos ) break ; } if ( field && int_bit_position ( field ) == bitpos && SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD ) reg = gen_rtx_REG ( DFmode , FP_ARG_FIRST + info . reg_offset + i ) ; else { reg = gen_rtx_REG ( DImode , GP_ARG_FIRST + info . reg_offset + i ) ; zero_width_field_abi_change = false ; } if ( zero_width_field_abi_change && warn_psabi ) { static unsigned last_reported_type_uid ; unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( arg . type ) ) ; if ( uid != last_reported_type_uid ) { static const char * url = CHANGES_ROOT_URL <STR_LIT> ; inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , url ) ; last_reported_type_uid = uid ; } } XVECEXP ( ret , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT


<s> static void emitLEASLrri ( MCStreamer & OutStreamer , MCOperand & RS1 , MCOperand & RS2 , MCOperand & Imm , MCOperand & RD ,


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>TargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ,


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT>


<s> if ( platform != NULL ) return platform ; else return


<s> return ( __m128i ) __builtin_ia32_psrlv8hi_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_hi ( ) ,


<s> if ( Insert . second ) { PreallocatedStackSizes . push_back ( <NUM_LIT> ) ; PreallocatedArgOffsets . emplace_back ( ) ; } return Insert .


<s> return DAG . getMaskedStore ( MINode -> getChain ( ) , DL , Data , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) ,

MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , false , false ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL


<s> bool <ISA_LIT>BaseRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC ) const { auto MBB = MI -> getParent ( ) ; auto MF = MBB -> getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( ! DstSubReg ) return true ; if ( NewRC -> getSize ( ) < <NUM_LIT> && DstRC -> getSize ( ) < <NUM_LIT> && SrcRC -> getSize ( ) < <NUM_LIT> ) return true ; auto NewRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( NewRC ) ; auto SrcRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( SrcRC ) ; auto DstRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( DstRC ) ; if ( SrcRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; if ( DstRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto It = AFI -> getCoalescedWeight ( MBB ) ; DEBUG ( dbgs ( ) << <STR_LIT> << It -> second << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NewRCWeight . RegWeight << <STR_LIT> ) ; unsigned SizeMultiplier = MBB -> size ( ) / <NUM_LIT> ; SizeMultiplier = SizeMultiplier ? SizeMultiplier : <NUM_LIT> ; if ( It -> second < NewRCWeight . WeightLimit


<s> if ( ! CONST_INT_P ( x ) ) fputs ( <STR_LIT> , asm_out_file ) ; fputc ( '\n' , asm_out_file


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; }


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div8hi (


<s> return Kind == Immediate && isInt < <NUM_LIT> >


<s> if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == <NUM_LIT> && Ty -> getStructElementType ( <NUM_LIT> ) -> isFP128Ty ( ) ) return true ; const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( CallNode ) ; return ( ES && Ty -> isIntegerTy ( <NUM_LIT> ) &&

isF128SoftLibCall ( ES -> getSymbol ( ) ) ) ;


<s> } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ; CC =


<s> return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , ( vec_float4


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( )


<s> if ( Ins . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) || IsMCU


<s> SmallVector < MachineInstr * , <NUM_LIT> > DBGInstructions ; for ( auto I = First -> getIterator ( ) , E = Last -> getIterator ( ) ; I != E ; I ++ ) { if ( I -> isDebugInstr ( ) ) DBGInstructions . push_back


<s> unsigned getNumFixupKinds ( ) const override { return


<s> return new <ISA_LIT>FastPreTileConfig


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects

( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> EVT HalfVT = VT . getHalfNumVectorElementsVT ( Ctx ) ; Type * HalfTy = HalfVT . getTypeForEVT ( Ctx ) ; LoadInst * Lo , * Hi ; std :: tie ( Lo , Hi ) = LoadMap [ ST -> getValueOperand ( ) ] ; Value * Ptr = ST -> getPointerOperand ( ) ; PointerType * HalfPtrTy = HalfTy -> getPointerTo ( ST -> getPointerAddressSpace (


<s> } } for ( auto * MI : Phis ) { bool HasGPROp = false , HasFPROp = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) { if ( ! MO . isReg ( ) ) continue ; const LLT & Ty = MRI . getType ( MO . getReg ( ) ) ; if ( ! Ty . isValid ( ) || ! Ty . isScalar ( ) ) break ; if ( Ty . getSizeInBits ( ) >= <NUM_LIT> ) break ; const RegisterBank * RB = MRI . getRegBankOrNull ( MO . getReg ( ) ) ; if ( ! RB ) break


<s> if ( invertCondCode ) CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S , getLoc ( ) , getContext ( ) ) ) ; return


<s> bool isLittleEndian ( ) const { return IsLittleEndian


<s> bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsLowZero ) && ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsHighZero ) && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo ( ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewLoad2 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( NewLoad1 . getNode ( ) , <NUM_LIT> ) , SDValue ( NewLoad2 . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> )


<s> } else { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; } if ( ! Shift ) return Result ; if ( ( unsigned ) ( Imm & <NUM_LIT> ) == Remainder ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Hi ) ) ; } if ( ( Lo = Remainder & <NUM_LIT> )


<s> PrivateLabelPrefix = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize =


<s> if ( AI -> use_empty ( ) ) return AtomicExpansionKind :: None ; auto * C1 = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ; Instruction * I = AI -> user_back ( ) ; if ( ! C1 || ! AI -> hasOneUse ( ) || I -> getOpcode ( ) != Instruction :: And || AI -> getParent ( ) != I -> getParent ( ) ) return AtomicExpansionKind :: CmpXChg ; auto * C2 = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Bits = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ! C2 || Bits == <NUM_LIT> || ! isPowerOf2_64 ( C2 ->

getZExtValue ( ) ) ) return AtomicExpansionKind :: CmpXChg ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MoveToFPReg ( MVT SrcVT , unsigned SrcReg , bool IsSigned ) { if ( SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( <STR_LIT> , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return <NUM_LIT> ; SrcReg = TmpReg ; } Address Addr ; Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject


<s> __extension__ static __inline void vst4_s8 ( int8_t * __a , int8x8x4_t val ) { __builtin_aarch64_simd_xi __o ; int8x16x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C (


<s> assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; for ( MCSuperRegIterator Supers ( Reg , TRI , true ) ; Supers . isValid ( ) ; ++ Supers ) { if ( * Supers == MO . getReg ( ) ) { if ( MO . isDef ( ) ) IsDefined = true ; else return true ; } } } if ( ! IsDefined


<s> static void free_label_state ( struct unw_labeled_state * ls ) { labeled_state_alloced -- ; if ( PTR_IN ( emergency_labeled_state , ls ) ) atomic_free ( & emergency_labeled_state_free , emergency_labeled_state - ls ) ; else free ( ls


<s> SDLoc dl ( N ) ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( N -> getValueType ( <NUM_LIT> ) ) ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( N , <NUM_LIT> ) ; SDValue InterVal = DAG . getNode ( InterOp , dl , LoVT


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; assert ( ! isVarArg && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; assert ( RegVT . getSimpleVT ( ) . SimpleTy == <STR_LIT> && <STR_LIT> ) ; const unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; InVals . push_back ( ArgIn ) ; continue ; } assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; const unsigned Offset = VA . getLocMemOffset ( ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , Offset , true ) ; SDValue FIPtr ; assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Load ; InVals . push_back ( Load ) ; } return Chain


<s> const TargetRegisterClass & RC = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; EhDataRegFI [ I ] = MF . getFrameInfo ( ) . CreateStackObject ( TRI .

getSpillSize ( RC ) , TRI . getSpillAlign ( RC ) , false ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; return Reserved


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast <

MCConstantExpr > ( Memory . OffsetImm ) ) {


<s> unsigned <ISA_LIT>AsmParser :: getATReg ( ) { unsigned Reg = Options . getATRegNum ( ) ; if ( is<ISA_LIT>64 ( ) ) return getReg ( <STR_LIT> , Reg ) ; return getReg ( <STR_LIT> , Reg


<s> memset ( insn , <NUM_LIT> , sizeof ( struct InternalInstruction ) ) ; insn -> reader = reader ; insn -> readerArg = readerArg ; insn -> dlog = logger ; insn -> dlogArg = loggerArg ; insn -> startLocation = startLoc ; insn -> readerCursor = startLoc ; insn -> mode = mode ; insn -> numImmediatesConsumed


<s> const MCExpr * Expr = Fixup . getValue ( ) ; if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; switch ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_ABS : case <ISA_LIT>MCExpr :: VK_SECREL : break ; default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A64E -> getVariantKindName ( ) + <STR_LIT> ) ; return COFF :: IMAGE_REL_ARM64_ABSOLUTE ; } } switch ( FixupKind ) { default : { if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A64E -> getVariantKindName ( ) + <STR_LIT> ) ; } else { const MCFixupKindInfo & Info = MAB . getFixupKindInfo ( Fixup . getKind ( ) ) ; Ctx . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> ) + Info . Name + <STR_LIT> ) ; } return COFF :: IMAGE_REL_ARM64_ABSOLUTE ; } case FK_PCRel_4 : return COFF :: IMAGE_REL_ARM64_REL32 ; case FK_Data_4 : switch ( Modifier ) { default : return COFF :: IMAGE_REL_ARM64_ADDR32 ; case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_ARM64_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_ARM64_SECREL ; } case FK_Data_8 : return COFF :: IMAGE_REL_ARM64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_ARM64_SECTION ; case


<s> SDLoc dl ( Op ) ; SDNodeFlags Flags ; Flags . setNoFPExcept ( Op -> getFlags ( ) . hasNoFPExcept ( ) ) ; bool IsSingle = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasFPCVT ( ) ; unsigned ConvOpc = IsSingle ? ( IsSigned ? <STR_LIT> : <STR_LIT> ) : ( IsSigned ? <STR_LIT> : <STR_LIT> ) ; EVT ConvTy = IsSingle ? <STR_LIT> : <STR_LIT> ; if ( Op -> isStrictFPOpcode ( ) ) { if ( ! Chain ) Chain = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( get<ISA_LIT>StrictOpcode ( ConvOpc ) , dl , DAG . getVTList ( ConvTy , <STR_LIT> ) , { Chain , Src } , Flags ) ; } else return DAG . getNode ( ConvOpc , dl , ConvTy


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Rt == <NUM_LIT> ) Inst . setOpcode ( <STR_LIT> ) ; else Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( ! load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) )


<s> fprintf ( f , <STR_LIT> ) ; fprintf ( f


<s> bool is_weak ; boolval = operands [ <NUM_LIT> ] ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; orig_mode = mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( mode == QImode || mode == HImode ) { oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; if ( ! TARGET_SYNC_HI_QI ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; oldval = expand_simple_binop ( SImode , ASHIFT , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) { x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } cond = gen_reg_rtx ( CCmode


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MF . print ( dbgs ( ) ) ) ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI -> hasAVX512 ( ) || ! STI -> hasBWI ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = Register :: index2VirtReg ( Idx


<s> static MCDisassembler * createThumbDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new ThumbDisassembler ( STI ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> ggc_add_rtx_root ( & hppa_compare_op0 , <NUM_LIT> ) ; ggc_add_rtx_root ( & hppa_compare_op1 , <NUM_LIT> ) ; ggc_add_root ( & deferred_plabels , <NUM_LIT> , sizeof ( & deferred_plabels ) , &


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> * loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ; * loop_mem = change_address ( mem ,


<s> case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op ,


<s> return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc , false ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = STI . hasVector ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState (


<s> Register Lo = Unmerge . getReg ( <NUM_LIT> ) ; Register Hi = Unmerge . getReg ( <NUM_LIT> ) ; Arg . OrigRegs . assign ( Arg . Regs . begin ( ) , Arg . Regs . end ( ) ) ; Arg . Regs = { Lo , Hi } ; if ( ! STI . isLittle ( ) ) std :: swap ( Lo , Hi ) ; MIRBuilder . buildCopy ( VALo . getLocReg ( ) , Lo ) ; MIRBuilder . buildCopy ( VAHi . getLocReg ( ) , Hi ) ; return <NUM_LIT>


<s> extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = <NUM_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( signExtend && extendOpc ) { oldval = MRI . createVirtualRegister ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( extendOpc ) , oldval ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( oldval ) . addReg ( incr ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) , scratch2 ) . addReg ( oldval ) . addReg ( incr ) . addImm ( Cond ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( frame_pointer_needed ) { emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; amount = offsets -> locals_base - offsets -> saved_regs ; } amount -= <NUM_LIT> * thumb1_extra_regs_pushed ( offsets , false ) ; gcc_assert ( amount >= <NUM_LIT> ) ; if ( amount ) { emit_insn ( gen_blockage ( ) ) ; if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP ) ;


<s> } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue


<s> void <ISA_LIT>MCCodeEmitter :: LowerCompactBranch ( MCInst & Inst ) const { unsigned RegOp0 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegOp1 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg0 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( RegOp0 ) ; unsigned Reg1 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( RegOp1 ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { assert ( Reg0 != Reg1 && <STR_LIT> ) ; if ( Reg0 < Reg1 ) return ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Reg0 >= Reg1


<s> EVT MemVT = LdNode -> getMemoryVT ( ) ; if ( MemVT == <STR_LIT> ) return LowerF128Load ( Op , DAG ) ; return Op


, ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> static __inline qword si_eqv ( qword a , qword b ) { vec_uchar16 d ; d = vec_xor ( ( vec_uchar16 ) ( a


<s> bool <ISA_LIT>TargetLowering :: SelectAddressEVXRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { for ( SDNode * U : N -> uses ( ) ) { if ( MemSDNode * Memop = dyn_cast < MemSDNode > ( U ) ) { if ( Memop -> getMemoryVT ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true


<s> Value * <ISA_LIT>IREmitter :: visitFMSUBADD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> bool IsSpls = isSpls ( MemInstr -> getOpcode ( ) ) ; MbbIterator First = MemInstr ; MbbIterator Last = Decrement ? BB -> begin ( ) : BB -> end ( ) ; while ( First != Last ) { Decrement ? -- First : ++ First ; if ( First == Last ) break ; if ( First -> isDebugInstr ( ) ) continue ; if ( isSuitableAluInstr ( IsSpls , First , * Base ,


<s> replace_with_subreg ( single_set ( insn ) , reg , new_reg


<s> Expr = <ISA_LIT>MCExpr :: CreateTPREL_G0_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateABS_G3 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateABS_G2_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateABS_G1_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateABS_G0_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create

( MO . getOffset ( ) , OutContext ) , OutContext ) ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> virtual <ISA_LIT>JITInfo * getJITInfo ( ) { return &


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( GV -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue (


<s> if ( ( Type != ELF :: STT_FUNC ) || ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> <NUM_LIT> ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; MCELF :: setOther ( SymbolData , ELF :: STO_MIPS_MICROMIPS


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get


<s> if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const MVT BlockType = getOptimalRepmovsType ( Subtarget , Align ) ; const uint64_t BlockBytes = BlockType . getSizeInBits ( ) / <NUM_LIT> ; const uint64_t BlockCount = Size / BlockBytes ; const uint64_t BytesLeft = Size % BlockBytes ; SDValue RepMovs = emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , DAG . getIntPtrConstant ( BlockCount , dl ) , BlockType ) ; if ( BytesLeft == <NUM_LIT> ) return RepMovs ; assert ( BytesLeft && <STR_LIT> ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return emitRepmovsB ( Subtarget , DAG , dl , Chain , Dst , Src , Size ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; unsigned Offset = Size - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , dl , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , dl , SrcVT ) ) , DAG . getConstant ( BytesLeft , dl , SizeVT ) , Align , isVolatile , true , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x8_t ) __builtin_aarch64_tbx4v8qi ( ( int8x8_t ) r , __o , (


<s> case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT


<s> SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , A , ShAmt ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , B , ShAmt ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum

) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , true , NULL ,


<s> if ( ! optimize_size && optimize > <NUM_LIT> ) return nds32_expand_movmemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ; return


<s> void addImm1_64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> struct decl_chain * warned = ( struct decl_chain * )


<s> unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset )


<s> MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ) . Case ( <STR_LIT>

, MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) . Default ( MCSymbolRefExpr :: VK_None ) ;


<s> unsigned RegOffsetInSet = getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ RegLargestSuper ] ; Value * Idx [ ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( RegOffsetInSet ) } ; Builder . CreateStore ( Val , Builder . CreateInBoundsGEP ( RegSet , Idx ) ) ; } ; InitRegTo ( <STR_LIT> , RSP ) ; InitRegTo ( <STR_LIT> , Builder . CreateZExt ( ArgC , Builder . getInt64Ty ( ) ) ) ; InitRegTo ( <STR_LIT> , Builder . CreatePtrToInt ( ArgV , Builder . getInt64Ty ( )


<s> if ( inst -> mayLoad ( ) || inst -> isBranch ( ) || inst -> mayStore ( ) || inst -> isCall ( ) || inst -> isReturn ( ) || inst -> isCompare ( ) || ( inst -> getOpcode ( ) == <STR_LIT> ) || ( inst -> getOpcode ( ) > <NUM_LIT> && inst -> getOpcode ( ) < <NUM_LIT> ) ) return false ; inst -> dump


<s> unsigned int getSlaveReg2 ( unsigned int regNUM ) { std :: unordered_map < unsigned int , unsigned int > :: const_iterator got = GPRregistersMap2 . find ( regNUM ) ; if ( got == GPRregistersMap2 . end ( ) ) { return regNUM


<s> Value * <ISA_LIT>IREmitter :: visitCMP ( const SDNode * N ) { return IREmitter :: visitSUB (


<s> return ( __mmask64 ) __builtin_ia32_kunpckdi ( ( __mmask64 )


<s> for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI . getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( )

, CSRegs ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ;


<s> __builtin_ia32_maskstored ( ( __v4si * ) __X , ( __v4si )


<s> static DecodeStatus DecodeMemBarrierOption ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val & ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch


<s> return new <ISA_LIT>TargetELFStreamer (


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode


<s> bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT ) ) return SDValue ( ) ; if ( TValIsAllOnes ) { SDValue CastRHS = DAG . getBitcast ( CondVT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastRHS ) ; return DAG . getBitcast ( VT , Or ) ; } if ( FValIsAllZeros


<s> switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision ==


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; value = helper_get_page_offset ( S + A


<s> const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . is64Bit ( ) ) return <NUM_LIT> ; return


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O


<s> Value *= Scale ; Inst . addOperand ( MCOperand :: createImm (


<s> if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM


<s> static <STR_LIT> getPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode


<s> return new <ISA_LIT>64Disassembler (


<s> static void nds32_asm_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED , tree function ) { int this_regno ; final_start_function ( emit_barrier ( ) , file , <NUM_LIT> ) ; this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( delta != <NUM_LIT> ) { if ( satisfies_constraint_Is15 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> , this_regno , this_regno , delta ) ; } else if ( satisfies_constraint_Is20 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } else { fprintf ( file , <STR_LIT> , delta


<s> return ( code == SYMBOL_REF || code == LABEL_REF || code == CONST


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { assert ( ! Val == ! VReg && <STR_LIT> ) ; auto Ret = AddDefaultPred ( MIRBuilder .


<s> const char * getPassName ( ) const override


<s> static const char * stripRegisterPrefix ( const char * RegName ) { if ( FullRegNames ) return RegName ; switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,

Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ;


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) )


<s> addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>ExpandPseudoPass ( * this )


<s> bool isTargetMachO ( ) const { return TargetTriple . isOSBinFormatMachO (


<s> return __aarch64_vget_lane_any ( __a ,


<s> uint64_t idx = cast < ConstantSDNode > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { if ( Op0 -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != idx && idx != <NUM_LIT> ) return SDValue ( ) ; } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ; if ( SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) * <NUM_LIT> ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc dl ( N ) ; unsigned NumElements = VT . getVectorNumElements (


<s> fputc ( <STR_LIT> [ truth * <NUM_LIT> + ST_REG_P ( REGNO ( XEXP ( op , <NUM_LIT> ) ) ) ] , file ) ; } break ; case 'Y' : if ( code == CONST_INT && UINTVAL ( op ) < ARRAY_SIZE ( mips_fp_conditions ) ) fputs ( mips_fp_conditions [ UINTVAL ( op ) ] , file ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'Z' : if ( ISA_HAS_8CC || ISA_HAS_CCF ) { mips_print_operand ( file , op , <NUM_LIT> ) ; fputc ( ',' , file ) ; } break ; case 'q' : if ( code == REG && MD_REG_P ( REGNO ( op ) ) ) fprintf ( file , <STR_LIT> ) ; else if ( code == REG && DSP_ACC_REG_P ( REGNO ( op ) ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] [ <NUM_LIT> ] ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; default : switch ( code ) { case REG : { unsigned int regno = REGNO ( op ) ; if ( ( letter == 'M' && TARGET_LITTLE_ENDIAN ) || ( letter == 'L' && TARGET_BIG_ENDIAN ) || letter == 'D' ) regno ++ ; else if ( letter && letter != 'z' && letter != 'M' && letter != 'L' ) output_operand_lossage ( <STR_LIT> , letter ) ; if ( COP0_REG_P ( regno ) ) fprintf ( file , <STR_LIT> , & reg_names [ regno ] [ <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ regno ] ) ; } break ; case MEM : if ( letter == 'D' ) output_address ( GET_MODE ( op ) , plus_constant ( Pmode , XEXP ( op , <NUM_LIT> ) ,


<s> int i ; enum machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case V16QImode : mode = V8HImode ; break ; case V32QImode : mode = V16HImode ; break ; case V64QImode : mode = V32HImode ; break ; case V8HImode : mode = V4SImode ; break ; case V16HImode : mode = V8SImode ; break ; case V32HImode : mode = V16SImode ; break ; case V4SImode : mode = V2DImode ; break ; case V8SImode : mode = V4DImode ; break ; case V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = <NUM_LIT> ; i < d -> nelt ; i += <NUM_LIT> ) if ( ( d -> perm [ i ] & <NUM_LIT> ) || d -> perm [ i + <NUM_LIT> ] != d -> perm [ i ] + <NUM_LIT> ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ <NUM_LIT> * i ] / <NUM_LIT> ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart


<s> return create ( VK_<ISA_LIT>_HI16 , Expr , Ctx


<s> cxt = force_reg ( Pmode , cxt ) ; if ( TARGET_ARCH64 ) sparc64_initialize_trampoline ( m_tramp , fnaddr , cxt ) ; else sparc32_initialize_trampoline ( m_tramp , fnaddr ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) FromHi = false ; else if ( N . getOpcode ( ) == <STR_LIT> ) FromHi = true ; else return false ; if ( ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; ShiftAmount = N -> getConstantOperandVal ( <NUM_LIT> ) ; Src = N -> getOperand ( <NUM_LIT> ) ; return true


<s> MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; assert ( MIB . getReg ( <NUM_LIT> ) == Reg && MIB . getReg ( <NUM_LIT> ) == Reg && <STR_LIT> ) ; return true


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCostAVX512 ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; MVT LegalVT = getTLI ( ) -> getTypeLegalizationCost ( DL , VecTy ) . second ; unsigned VecTySize = DL . getTypeStoreSize ( VecTy ) ; unsigned LegalVTSize = LegalVT . getStoreSize ( ) ; unsigned NumOfMemOps = ( VecTySize + LegalVTSize - <NUM_LIT> ) / LegalVTSize ; auto * SingleMemOpTy = FixedVectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; unsigned VF = cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ) ; unsigned NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; unsigned NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl


<s> vld1_s64 ( const int64_t * __a ) { return ( int64x1_t ) { * __a


<s> Inst . addOperand ( MCOperand :: createReg ( SPERegs [ getReg ( )


<s> Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = <NUM_LIT> ; return


<s> bool Filler :: searchSuccBBs ( MachineBasicBlock & MBB , Iter Slot ) const { if ( DisableSuccBBSearch ) return false ; MachineBasicBlock * SuccBB = selectSuccBB ( MBB ) ; if ( ! SuccBB ) return false ; RegDefsUses RegDU ( TM ) ; bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * *

PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ;


<s> SDValue MTCTROps [ ] = { Chain , Callee , Glue } ; EVT ReturnTypes [ ] = { <STR_LIT> , <STR_LIT> } ; Chain = DAG . getNode ( <STR_LIT> , dl , makeArrayRef ( ReturnTypes , <NUM_LIT> ) , makeArrayRef ( MTCTROps , Glue .

getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ;


<s> return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] =


<s> split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset ,


<s> ggc_add_root ( & deferred_plabels , <NUM_LIT> , sizeof ( & deferred_plabels ) , &


<s> <ISA_LIT>DisassemblerBase ( STI , Info


<s> return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc ( ) ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR (


<s> Op -> Mem . Base = <NUM_LIT> ; Op -> Mem . IndexReg = <NUM_LIT> ; Op -> Mem . Index = Index ; Op -> Mem . Offset =


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; return TargetLowering :: getInlineAsmMemConstraint


<s> int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv ::


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> SmallVector < SDValue , <NUM_LIT> > OutChains ; unsigned OffsetScaled = <NUM_LIT> ; while ( OffsetScaled < ObjSizeScaled ) { if ( ObjSizeScaled - OffsetScaled >= <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode2 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> * <NUM_LIT> ) ) ; OffsetScaled += <NUM_LIT> ; OutChains . push_back ( St ) ; continue ; } if ( ObjSizeScaled - OffsetScaled > <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode1 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> ) ) ; OffsetScaled += <NUM_LIT> ; OutChains . push_back ( St ) ; } } SDValue Res = DAG . getNode ( <STR_LIT>