<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; OwningPtr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = <NUM_LIT> ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> )


<s> switch ( prefix ) { case <NUM_LIT> : case <NUM_LIT> : if ( lookAtByte ( insn , & nextByte ) ) break ; if ( isREX ( insn , nextByte ) || nextByte == <NUM_LIT> || nextByte == <NUM_LIT> ) insn -> mandatoryPrefix = prefix ; insn -> repeatPrefix = prefix ; break ; case <NUM_LIT> : if ( lookAtByte ( insn ,


<s> return false ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT>


<s> const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; assert ( DstRB . getID ( ) == SrcRB . getID ( ) && <STR_LIT> ) ; assert ( DstTy . getSizeInBits ( ) > SrcTy . getSizeInBits ( ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( canTurnIntoCOPY ( SrcRC , DstRC ) ) return selectTurnIntoCOPY ( I , MRI , SrcReg , SrcRC , DstReg , DstRC ) ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) ||

! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) {


<s> if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumVLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } case <STR_LIT> : ++ NumVSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } case <STR_LIT> : ++ NumVLDMGened ; switch ( Mode )


<s> return new <ISA_LIT>PassConfig ( * this , PM


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( JIT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , isLittle ( isLittle ) , TLOF ( std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( TT , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle ,

* this , MaybeAlign ( Options . StackAlignmentOverride ) ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Results . push_back ( LowerVECREDUCE ( SDValue ( N , <NUM_LIT> ) , DAG ) ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT>


<s> const char * <ISA_LIT>TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint (


<s> if ( TARGET_MIPS16 && mips16_hard_float && ! aggregate_value_p ( DECL_RESULT ( current_function_decl ) ) && ( GET_MODE_CLASS ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) == MODE_FLOAT ) && ( ! TARGET_SINGLE_FLOAT || ( GET_MODE_SIZE ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) <= <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( current_frame_info . initialized ) return current_frame_info


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; ResultVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } ResultVals . push_back (


<s> SmallVector < int , <NUM_LIT> > M ; N -> getMask (


<s> basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale


<s> if ( isShiftedImm ( ) ) { Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> ) return false ; } else { Shift =


<s> poly8x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT>


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MI ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT>


<s> if ( ! isMem ( ) || ! Memory . OffsetRegNum

|| Memory . Alignment != <NUM_LIT> ) return false ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY )

, ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> unsigned getReg ( ) const override { assert ( Kind == Register


<s> switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_GE ; case GT : return AARCH64_GT ; case LE : return AARCH64_LE ; case LT : return AARCH64_LT ; case GEU : return AARCH64_CS ; case GTU : return AARCH64_HI ; case LEU : return AARCH64_LS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_SWPmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_LE ; case GT : return AARCH64_LT ; case LE : return AARCH64_GE ; case LT : return AARCH64_GT ; case GEU : return AARCH64_LS ; case GTU : return AARCH64_CC ; case LEU : return AARCH64_CS ; case LTU : return AARCH64_HI ; default : return - <NUM_LIT> ; } break ; case E_CC_NZmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_PL ; case LT : return AARCH64_MI ; default : return - <NUM_LIT> ; } break ; case E_CC_Zmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; default : return - <NUM_LIT> ; } break ; case E_CC_Cmode : switch ( comp_code ) { case LTU : return AARCH64_CS ; case GEU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_ADCmode : switch ( comp_code ) { case GEU : return AARCH64_CS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_Vmode : switch ( comp_code ) { case NE : return AARCH64_VS ; case EQ :


<s> if ( VRI . RLAmt ) { NeedsRotate = true ; } else if ( VRI . Repl32 ) { for ( auto & BG : BitGroups ) { if ( BG . V != VRI . V || BG . RLAmt != VRI . RLAmt || BG . Repl32 != VRI . Repl32 ) continue ; if ( BG . StartIdx < <NUM_LIT> && BG . EndIdx < <NUM_LIT> && BG . StartIdx < BG . EndIdx ) continue ; NeedsRotate = true ; break ; } } if ( NeedsRotate ) Res = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , InstCnt ) ; else Res = VRI . V ; if ( Res ) eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt && BG . Repl32 == VRI . Repl32 ; } ) ; } if ( ! Res ) for ( auto I = BitGroups . begin ( ) , IE = BitGroups . end ( ) ; I != IE ; ++ I ) { if ( SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , false ) < SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , true ) ) { if ( I != BitGroups . begin ( ) ) { BitGroup BG = * I ; BitGroups . erase ( I ) ; BitGroups . insert ( BitGroups . begin ( ) , BG ) ; } break ; } } for ( auto & BG : BitGroups ) { if ( ! Res ) Res = SelectRotMask64 ( BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; else Res = SelectRotMaskIns64 ( Res , BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; } if ( LateMask


<s> unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode ==


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue (


<s> if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ; return <STR_LIT>


<s> static bool asmClobbersCTR ( InlineAsm * IA ) { InlineAsm :: ConstraintInfoVector CIV = IA -> ParseConstraints ( ) ; for ( unsigned i = <NUM_LIT> , ie = CIV . size ( ) ; i < ie ; ++ i ) { InlineAsm :: ConstraintInfo & C = CIV [ i ] ; if ( C . Type != InlineAsm :: isInput ) for ( unsigned j = <NUM_LIT> , je = C . Codes . size ( ) ; j < je ; ++ j ) if ( StringRef ( C . Codes [ j ] ) . equals_lower ( <STR_LIT> ) ) return true ; } return


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move (


<s> static bool combineRestoreOR ( MachineBasicBlock :: iterator RestoreMI , MachineBasicBlock :: iterator OrMI , const TargetInstrInfo * TII ) { unsigned reg = OrMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( reg < <STR_LIT> || reg > <STR_LIT> ) return false ; if ( OrMI -> getOpcode ( ) == <STR_LIT> && OrMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && OrMI -> getOperand ( <NUM_LIT> ) . getReg


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB


<s> SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> )

, AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> void createdInstr ( MachineInstr & MI ) override { InstList . insert (


<s> static inline unsigned getThumbImmNonShiftedVal ( unsigned V


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ) return false ; return MCInstrAnalysis :: isConditionalBranch


<s> static int ck801_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( index ) ; if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return ( code == CONST_INT && INTVAL ( index ) < CSKY_LD16_MAX_OFFSET ( SImode ) && INTVAL ( index ) >= <NUM_LIT> && ( INTVAL

( index ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , <NUM_LIT> ) ; * offset = XEXP ( addr , <NUM_LIT> ) ; return ( REG_P ( * base )


<s> assert ( FnStart == nullptr ) ; FnStart = getContext ( ) . CreateTempSymbol


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseCoprocNumOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S )


<s> bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ^ is_swapped ] ; high = nelt / <NUM_LIT> ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i +


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) .


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn


<s> virtual const DataLayout * getDataLayout ( )


<s> std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString (


<s> if ( ! matchVectorShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG .

getConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; unsigned StoreAddrReg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame ,

DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ;


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize (


<s> fatal_error ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> ) ; return const0_rtx ; } if ( fcode == ARM_BUILTIN_NEON_LANE_CHECK ) { tree nlanes = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; gcc_assert ( TREE_CODE ( nlanes ) == INTEGER_CST ) ; rtx lane_idx = expand_normal ( CALL_EXPR_ARG ( exp ,


<s> bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) { Changed |= runOnMachineBasicBlock ( * FI ) ; <ISA_LIT>TextSectOffset += FI -> size ( ) ; } return


<s> L = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Value = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; getTargetStreamer ( ) . emitAttribute ( Tag , Value ) ; return


<s> FixupLEAPass :: RegUsageState FixupLEAPass :: usesRegister ( MachineOperand & p , MachineBasicBlock :: iterator I ) { RegUsageState RegUsage = RU_NotUsed ; MachineInstr & MI = * I ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) == p . getReg ( ) ) { if ( MO . isDef ( ) ) return RU_Write ; RegUsage = RU_Read ; } } return


<s> if ( ! ATReg ) return true ; bool LoadedOffsetInAT = false ; if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { LoadedOffsetInAT = true ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg ; unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg ; unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t FirstLbuOffset = <NUM_LIT> , SecondLbuOffset


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; <STR_LIT> Ty = getRegTy ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MF ) ; unsigned Reg = Ty == <STR_LIT> ?


<s> assert ( Ops . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ) ; return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; Ops = { N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true


<s> if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case E_HFmode : return <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { O << <STR_LIT> << * CurrentFnSym << '\n' ; OutStreamer . EmitLabel (


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS <<


<s> static unsigned int arm_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) { modes -> safe_push ( V16QImode ) ; modes -> safe_push ( V8QImode


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } MachineBasicBlock :: iterator Update = findMatchingUpdateInsnForward ( MBBI , ScanLimit , <NUM_LIT> ) ; if ( Update != E ) { MBBI = mergePostIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPostFolded ; break ; } if ( isUnscaledLdst ( Opc ) ) { ++ MBBI ; break ; } Update = findMatchingUpdateInsnBackward ( MBBI , ScanLimit ) ; if ( Update != E ) { MBBI = mergePreIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPreFolded ; break ; } int Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * TII -> getRegClass ( MI -> getDesc ( ) , <NUM_LIT> , TRI , * ( MBB . getParent ( ) ) ) -> getSize ( ) ; Update = findMatchingUpdateInsnForward ( MBBI , ScanLimit , Value ) ; if ( Update != E ) { MBBI = mergePreIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPreFolded ; break ; } ++ MBBI


<s> static bool LessOrEqualTypeSize ( Value


<s> if ( j == <NUM_LIT> ) break ; if ( ! BucketChain . Elements [ j ] . Offset || BucketChain . Elements [ j ] . Offset -> isZero ( ) ) break ; const SCEV * Offset = BucketChain . Elements [ j ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant > ( SE -> getNegativeSCEV ( Offset ) ) ; } std :: swap ( BucketChain . Elements [ j ] , BucketChain . Elements [ <NUM_LIT>


<s> bool hasV6MOps ( ) const { return STI . getFeatureBits ( ) & <STR_LIT>


<s> case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Value -= <NUM_LIT> ; break ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >>


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .


<s> EVT InVT = PackedOp . getValueType ( ) ; unsigned ToBits = OutVT . getScalarSizeInBits ( ) ; unsigned FromBits = InVT . getScalarSizeInBits ( ) ; do { FromBits *= <NUM_LIT> ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( FromBits ) , <STR_LIT> / FromBits ) ; PackedOp = DAG . getNode ( <STR_LIT> , SDLoc ( PackedOp ) , OutVT , PackedOp ) ; } while ( FromBits !=


<s> unsigned rotate = slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> if ( RegSpc == SingleSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ; } MIB = AddDefaultPred ( MIB


<s> } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; if ( Match1 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match2 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match3 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match4 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( ( Match1 == Match_MnemonicFail ) && ( Match2 == Match_MnemonicFail ) && ( Match3 == Match_MnemonicFail ) && ( Match4 == Match_MnemonicFail ) ) { if ( ! WasOriginallyInvalidOperand ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op -> getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRanges , MatchingInlineAsm ) ; <ISA_LIT>Operand * Operand = ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ; if ( Operand -> getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand -> getLocRange ( ) ; return Error ( Operand -> getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRanges , MatchingInlineAsm ) ; } if ( ( Match1 == Match_MissingFeature ) + ( Match2 == Match_MissingFeature ) + ( Match3 == Match_MissingFeature ) + ( Match4 == Match_MissingFeature ) == <NUM_LIT> ) { std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfoMissingFeature ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfoMissingFeature & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfoMissingFeature & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg , EmptyRanges , MatchingInlineAsm ) ; } if ( ( Match1 == Match_InvalidOperand ) + ( Match2 == Match_InvalidOperand ) + ( Match3 ==

Match_InvalidOperand ) + ( Match4 == Match_InvalidOperand ) == <NUM_LIT> ) {


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CCOut ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> } while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , unsigned ExpectedVecWidth ) { unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = <NUM_LIT> ; break ; } return MI -> getOperand ( ImmOpIdx ) . getImm ( ) == ExpectedVecWidth ; } ; MBB = VCTP -> getParent ( ) ; if ( MachineInstr * Def = RDA . getReachingMIDef ( & MBB -> back ( ) , NumElements ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { VCTP } ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; if ( RDA . isSafeToRemove ( Def , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) { if ( FoundSub || ! IsValidSub ( MI ,


<s> BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI

-> getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ;


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ; return MCDisassembler :: Success


<s> for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; int ei = INTVAL ( e ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT>


<s> if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! emitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment ( ) ) ) return false ; updateValueMap ( I , ResultReg ) ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTTZ_ZERO_UNDEF ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; SDValue ff1 = DAG . getNode ( <STR_LIT> , dl , VT


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( ST -> hasNEON ( ) ) { if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SVI -> getType ( )

-> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB


<s> getBitfieldInvertedMaskOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v


<s> if ( symbolic ) { if ( move_needs_splitting ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , SImode ) ) return true ; return false ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) return false ; if ( constraint_satisfied_p ( operands [ <NUM_LIT> ] , CONSTRAINT_I ) || constraint_satisfied_p ( operands [ <NUM_LIT> ] , CONSTRAINT_J ) || constraint_satisfied_p ( operands [ <NUM_LIT> ] , CONSTRAINT_O ) ) return false ; if ( ( ( ! reload_completed && ! reload_in_progress ) || ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) ) &&

constraint_satisfied_p ( operands [ <NUM_LIT> ] , CONSTRAINT_K ) ) return false ;


<s> while ( V1 . getOpcode ( ) == <STR_LIT> ) V1 = V1 -> getOperand ( <NUM_LIT> ) ; while ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V2 -> getOperand ( <NUM_LIT> ) ; bool V1IsZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsZero = <STR_LIT> ( V2 . getNode ( ) ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> || ( M >= <NUM_LIT> && M < Size && V1IsZero ) || ( M >= Size && V2IsZero ) ) { Zeroable [ i ] = true ; continue ; } SDValue V = M < Size ? V1 : V2 ; if ( V . getOpcode ( ) != <STR_LIT> || Size !=

( int ) V . getNumOperands ( ) ) continue ;


<s> int NumElts = Mask . size ( ) ; ScaledMask . assign ( NumElts * Scale , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale *


<s> int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + FL -> getReturnSaveOffset ( ) ; int NewRetAddr = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( MF , NewRetAddr ) ) ; if ( Subtarget . isDarwinABI ( ) ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex (


<s> if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && Alignment >= <NUM_LIT> ) || ( EltWidth == <NUM_LIT> && Alignment

>= <NUM_LIT> ) || EltWidth == <NUM_LIT> ) ;


<s> <ISA_LIT>VSXCopyCleanup ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>VSXCopyCleanupPass ( * PassRegistry ::


<s> if ( regno == GP_REG_FIRST + <NUM_LIT> && regs_ever_live [ regno ] ) return true ; if ( TARGET_MIPS16 ) { tree return_type ; return_type = DECL_RESULT ( current_function_decl ) ; if ( regno == GP_REG_FIRST + <NUM_LIT> && regs_ever_live [ regno ] ) return true ; if ( regno == GP_REG_FIRST + <NUM_LIT> && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return true ; } return false


<s> if ( MSA_SUPPORTED_MODE_P ( mode ) && ! mips_signed_immediate_p ( INTVAL ( x ) ,

<NUM_LIT> , mips_ldst_scaled_shift ( mode ) ) ) return false ;


<s> static SDValue ExpandBIT_CONVERT ( SDNode * N , SelectionDAG & DAG ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue (


<s> void addImm32_63Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> static void rx_function_arg_advance ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { * get_cumulative_args ( cum ) += rx_function_arg_size (


<s> assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; if ( MaskEltTy != <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) , Mask ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , Src0 , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract ,


<s> if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = GPR64x8DecoderTable [ RegNo >> <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , false ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs


<s> bool Filler :: searchRange ( MachineBasicBlock & MBB , IterTy Begin , IterTy End , RegDefsUses & RegDU , InspectMemInstr & IM , IterTy & Filler , Iter Slot ) const { for ( IterTy I = Begin ; I != End ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * I ) ) break ; assert ( ( ! I -> isCall ( ) && ! I -> isReturn ( ) && ! I -> isBranch ( ) ) && <STR_LIT> ) ; if ( delayHasHazard ( * I , RegDU , IM ) ) continue ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { unsigned AddrIdx


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) { SDValue Cond = Op . getOperand ( SplatIdx ) ; assert ( Cond . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getSelect ( dl , VT , Cond , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast ( <STR_LIT> , ImmL ) ; ImmH = DAG . getBitcast ( <STR_LIT> , ImmH ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ImmL ,


<s> Op -> Prefetch . Val = Val ; Op -> Barrier . Data = Str . data ( ) ; Op -> Barrier . Length = Str . size ( ) ; Op -> StartLoc


<s> if ( SDValue V = combineTruncatedArithmetic ( N , DAG , Subtarget , DL ) ) return V ; if ( SDValue Avg = detectAVGPattern ( Src , VT , DAG , Subtarget , DL ) ) return Avg ; if ( Src . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ; if ( BCSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BCSrc ) ; } if ( SDValue V = combineVectorSignBitsTruncation ( N , DL , DAG , Subtarget ) ) return V ; return combineVectorTruncation ( N ,


<s> for ( auto & Reg : functionCallArgs ) { MachineBasicBlock * lastCheck = NULL ; newBB = insertVoting ( MF , MI ,


<s> static SDValue BuildIntrinsicOp ( unsigned IID , SDValue Op0 , SDValue Op1 , SDValue Op2 , SelectionDAG & DAG , const SDLoc & dl , EVT DestVT = <STR_LIT> ) { if ( DestVT == <STR_LIT> ) DestVT = Op0 .


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm ) { if ( ! isUInt < N > ( Imm ) )


<s> int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset <<


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { return false


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) )


<s> unsigned NewOpc = convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI . setDesc ( * MCID ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI . hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI . getNumOperands ( ) ;


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri , const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) , TII ( tii ) , TRI ( tri ) , STI


<s> if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; if ( Mid ) return truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } } return SDValue


<s> return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , A1 , b . OR ( b . AND ( A1 , b . NOT ( A2 ) ) , b . AND ( A2 , b . SRL < <NUM_LIT> > ( A1 ) ) ) ) ; } llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> default : break ; case 'v' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType (


<s> raw_string_ostream TempStream ( Name ) ; Symbol -> print ( TempStream , MAI ) ; } LabelToEmit . append ( <STR_LIT> ) ; LabelToEmit . append


<s> int i ; rtx src , dst , srcbase , dstbase ; rtx part_bytes_reg = NULL ; rtx mem ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT || GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT || INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> || INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) return <NUM_LIT> ; dstbase = operands [ <NUM_LIT> ] ; srcbase = operands [ <NUM_LIT> ] ; dst = copy_to_mode_reg ( SImode , XEXP ( dstbase , <NUM_LIT> ) ) ; src = copy_to_mode_reg ( SImode , XEXP ( srcbase , <NUM_LIT> ) ) ; in_words_to_go = ARM_NUM_INTS ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; out_words_to_go = INTVAL ( operands [ <NUM_LIT> ] ) / <NUM_LIT> ; last_bytes = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; dstoffset = srcoffset = <NUM_LIT> ; if ( out_words_to_go != in_words_to_go && ( ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) part_bytes_reg = gen_rtx_REG ( SImode , ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) ; for ( i = <NUM_LIT> ; in_words_to_go >= <NUM_LIT> ; i += <NUM_LIT> ) { if ( in_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , <NUM_LIT> , src , TRUE , TRUE , srcbase , & srcoffset ) ) ; else emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , in_words_to_go , src , TRUE , FALSE , srcbase , & srcoffset ) ) ; if ( out_words_to_go ) { if ( out_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , <NUM_LIT> , dst , TRUE , TRUE , dstbase , & dstoffset ) ) ; else if ( out_words_to_go != <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , out_words_to_go , dst , TRUE , ( last_bytes == <NUM_LIT> ? FALSE : TRUE ) , dstbase , & dstoffset ) ) ; else { mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; if ( last_bytes != <NUM_LIT> ) { emit_insn ( gen_addsi3 ( dst , dst , GEN_INT ( <NUM_LIT> ) ) ) ; dstoffset += <NUM_LIT> ; } } } in_words_to_go -= in_words_to_go < <NUM_LIT> ? in_words_to_go : <NUM_LIT> ; out_words_to_go -= out_words_to_go < <NUM_LIT> ? out_words_to_go : <NUM_LIT> ; } if ( out_words_to_go ) { rtx sreg ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; sreg = copy_to_reg ( mem ) ; mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , sreg ) ; in_words_to_go -- ; gcc_assert ( ! in_words_to_go ) ; } if ( in_words_to_go ) { gcc_assert ( in_words_to_go > <NUM_LIT> ) ; mem = adjust_automodify_address ( srcbase , SImode


<s> <ISA_LIT>CondBrTuning ( ) : MachineFunctionPass (


<s> if ( ! Mst -> isTruncatingStore ( ) ) return reduceMaskedStoreToScalarStore ( Mst , DAG ) ; EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG

. getUNDEF ( WideVecVT ) , ShuffleVec ) ;


<s> return ( __m256i ) __builtin_ia32_pmovzxbw256_mask ( ( __v16qi ) __A , (


<s> return CreateReg ( Index , RegKind_ACC , RegInfo , S , E


<s> DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( offset ) ) ; if ( IsLoad && Rt == Rt2 ) return SoftFail ; if ( NeedsDisjointWritebackTransfer && Rn != <NUM_LIT> && ( Rt == Rn || Rt2 == Rn ) ) return SoftFail ; return Success


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return


<s> return __builtin_mve_vqrdmulhq_n_sv16qi ( __a ,


<s> for ( unsigned Idx = <NUM_LIT> ; Idx != NumOperands ; ++ Idx ) { LLT OpTy = MRI . getType ( MI . getOperand ( Idx ) . getReg ( ) ) ; assert ( <ISA_LIT>GenRegisterBankInfo :: getRegBankBaseIdxOffset ( RBIdx , OpTy . getSizeInBits ( ) ) == <ISA_LIT>GenRegisterBankInfo :: getRegBankBaseIdxOffset ( RBIdx , Size ) && <STR_LIT> ) ; bool OpIsFPR = OpTy . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ; ( void ) OpIsFPR ; assert ( IsFPR ==


<s> if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef (


<s> MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return


<s> vec_uint4 bsel = ( vec_uint4 ) vec_sra ( ( vec_int4 ) ( b ) , ( vec_uint4 ) vec_splat ( ( ( vec_uint4 ) si_from_int ( <NUM_LIT> ) ) , <NUM_LIT> ) ) ; bsel = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) bsel , ( vec_uchar16 ) bsel , splat_hi ) ; vec_uint4 abor = vec_subc ( ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) , aabs ) ; vec_uchar16 pat = vec_sel ( ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , vec_sr ( borrow_shuffle , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( borrow_shuffle , vec_splat_u8 ( <NUM_LIT> ) ) ) ; abor = ( vec_uint4 ) ( vec_perm ( vec_perm ( ( vec_uchar16 ) abor , ( vec_uchar16 ) abor , borrow_shuffle ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ; vec_uint4 aneg = vec_add ( vec_add ( vec_splat_u32 ( <NUM_LIT> ) , vec_nor ( aabs , aabs ) ) , vec_and ( abor , vec_splat_u32 ( <NUM_LIT> ) ) ) ; vec_int4 aval = ( vec_int4 ) vec_sel ( ( vec_uchar16 ) aabs , ( vec_uchar16 ) aneg , ( vec_uchar16 ) asel ) ; vec_uint4 bbor = vec_subc ( ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) , babs ) ; bbor = ( vec_uint4 ) ( vec_perm ( vec_perm ( ( vec_uchar16 ) bbor , ( vec_uchar16 ) bbor , borrow_shuffle ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ; vec_uint4 bneg = vec_add ( vec_nor ( babs , babs ) , vec_and ( bbor , vec_splat_u32 ( <NUM_LIT> ) ) ) ; vec_int4 bval = ( vec_int4 ) vec_sel ( ( vec_uchar16 ) babs , ( vec_uchar16 ) bneg , ( vec_uchar16 ) bsel ) ; vec_uint4 gt_hi = ( vec_uint4 ) vec_cmpgt ( aval , bval ) ; vec_uint4 gt_lo = ( vec_uint4 ) vec_cmpgt ( ( vec_uint4 ) aval , ( vec_uint4 ) bval ) ; vec_uint4 eq = ( vec_uint4 ) vec_cmpeq ( aval , bval ) ; vec_uint4 eqgt = vec_and ( eq , vec_slo ( gt_lo , x


<s> static parse_codes parse_bif ( void ) { parse_codes result ; diag = & bif_diag ; if ( ! advance_line ( bif_file ) ) return PC_OK ; do result = parse_bif_stanza ( ) ; while ( result == PC_OK ) ; if ( result == PC_EOFILE ) return PC_OK


<s> assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > (


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const { <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> static std :: vector < std :: pair < uint64_t , uint64_t >> find<ISA_LIT>PltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA ) { std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = <NUM_LIT> , End = PltContents . size ( ) ; Byte + <NUM_LIT> < End ; ) { if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data ( ) + Byte + <NUM_LIT> ) ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , GotPltSectionVA + Imm ) ) ; Byte += <NUM_LIT> ; } else if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data ( ) + Byte + <NUM_LIT> ) ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte ,


<s> case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv


<s> ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> switch ( type ) { case ONEBYTE : decision = & ONEBYTE_SYM ; break ; case TWOBYTE : decision = & TWOBYTE_SYM ; break ; case THREEBYTE_38 : decision = & THREEBYTE38_SYM ; break ; case THREEBYTE_3A : decision = & THREEBYTE3A_SYM ; break ; case THREEBYTE_A6 : decision = & THREEBYTEA6_SYM ; break ; case THREEBYTE_A7 : decision = & THREEBYTEA7_SYM ; break ; case XOP8_MAP : decision = & XOP8_MAP_SYM ; break ; case


<s> assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset / <NUM_LIT> ; assert ( ( RPI . Offset >= - <NUM_LIT> && RPI . Offset <= <NUM_LIT> ) && <STR_LIT> ) ; RegPairs . push_back ( RPI )


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) return false ; return


, V1 , V2 , DAG , Subtarget ) ) return V ;


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = nullptr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * )


<s> unsigned <ISA_LIT>SEFrameLowering :: ehDataReg ( unsigned I ) const { static const unsigned EhDataReg [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned EhDataReg64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> uint64_t Value = CE -> getValue ( ) ; if ( Value % Angle == Remainder && Value

<= <NUM_LIT> ) return DiagnosticPredicateTy :: Match ;


<s> MachineInstr * DefMI = getAccDefMI ( MI ) ; if ( TII -> isFpMLxInstruction ( DefMI -> getOpcode ( ) ) ) { IgnoreStall . insert ( DefMI ) ; return true ; } if ( IgnoreStall . count ( MI ) ) return false ; unsigned Limit1 = isA9 ? <NUM_LIT> : <NUM_LIT> ; unsigned Limit2 = isA9 ? <NUM_LIT>


<s> static SDValue foldADCToCINC ( SDNode * N , SelectionDAG & DAG ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue CC = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> if ( AfterMI != MBB . end ( ) && isX87Instruction ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ MI ; Changed =


<s> inline vector float vec_expte ( vector


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_supported_cpu_names ) ; i ++ ) if ( ! strcmp ( cpu , rs6000_supported_cpu_names [ i ] ) ) return cpu ; for ( i = <NUM_LIT> ; linux_cpu_translation_table [ i ] [ <NUM_LIT> ] != NULL ; i ++ ) { const char * canonical = linux_cpu_translation_table [ i ] [ <NUM_LIT> ] ; for ( j = <NUM_LIT> ; linux_cpu_translation_table [ i ] [ j ] != NULL ; j ++ ) if ( ! strcmp ( cpu , linux_cpu_translation_table [ i ] [ j ] ) ) { cpu =


<s> rtx jmp , tmp ; enum attr_type attr ; gcc_assert ( INSN_P ( insn ) && ! INSN_DELETED_P ( insn ) ) ; for ( next = NEXT_INSN ( insn ) ; next ; next = NEXT_INSN ( next ) ) { if ( ! INSN_P ( next ) ) continue ; if ( GET_CODE ( PATTERN ( next ) ) != USE ) break ; } jmp = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) jmp = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ; attr = recog_memoized ( jmp ) >= <NUM_LIT> ? get_attr_type ( jmp ) : TYPE_UNKNOWN ; if ( next && attr == TYPE_LOAD ) { tmp = PATTERN ( next ) ; if ( GET_CODE ( tmp ) == SEQUENCE ) tmp = PATTERN ( XVECEXP ( tmp , <NUM_LIT> , <NUM_LIT> ) ) ; note_stores ( PATTERN ( insn ) , insn_dependent_p_1 , & tmp ) ; if ( ! tmp ) emit_insn_after ( gen_nop ( ) , insn ) ; } if ( attr == TYPE_CALL ) { int nops = <NUM_LIT> ; int count ; rtx prev = insn ; rtx rescan = NULL_RTX ; for ( count = <NUM_LIT> ; count && ! nops ; ) { int type ; prev = PREV_INSN ( prev ) ; if ( ! prev ) { nops = count ; break ; } if ( BARRIER_P ( prev ) ) break ; if ( LABEL_P ( prev ) ) { label_info * label ; branch_info * branch ; for ( label = mt_labels ; label ; label = label -> next ) if ( label -> label == prev ) { for ( branch = label -> branches ; branch ; branch = branch -> next


<s> int16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> LowOverheadLoop ( MachineLoop & ML , MachineLoopInfo & MLI , ReachingDefAnalysis & RDA , const TargetRegisterInfo & TRI , const <ISA_LIT>BaseInstrInfo & TII ) : ML ( ML ) , MLI ( MLI )

, RDA ( RDA ) , TRI ( TRI ) , TII ( TII ) , TPNumElements ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) {


<s> offsets = arm_get_frame_offsets ( ) ; return offsets ->


<s> if ( ToVT . getScalarType ( ) == <STR_LIT> ) return LowerTruncatei1 ( N , DAG , Subtarget ) ; if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return


<s> public : <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; private : MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand &


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoVirt


<s> return ( __m128i ) __builtin_ia32_pmovwb256_mask ( ( __v16hi ) __A , ( __v16qi )


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { assert ( ApplyFunctions . find ( pType )


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm &


<s> unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerTailCall , <NUM_LIT> ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerThunk , <NUM_LIT> ) ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ ] ( outliner :: Candidate & C ) { return C . LRU . available ( <STR_LIT> ) ; } ) ) { FrameID = MachineOutlinerNoLRSave ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; } else { if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ this ] ( outliner :: Candidate & C ) { return findRegisterToSaveLRTo ( C ) ; } ) ) { FrameID = MachineOutlinerRegSave ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerRegSave ,


<s> return Kind == k_FPImm && <STR_LIT> ( getFPImm ( )


<s> bool has<ISA_LIT>3 ( ) const { return <ISA_LIT>ArchVersion >=


<s> return ( __m512 ) __builtin_ia32_broadcastf32x8_512_mask ( ( __v8sf ) __A , _mm512_undefined_ps ( ) ,


<s> void <ISA_LIT>TargetStreamer :: emitAttribute ( unsigned


<s> SDValue AN = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , AD , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { AN , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; Op = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) ; } } } } bool Inv ; int OtherCondIdx ; unsigned Idx = getCRIdxForSetCC ( CC , Inv , OtherCondIdx ) ; SDValue CCReg = SelectCC ( N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CC , dl ) ; SDValue IntCR ; SDValue CR7Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; CCReg = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , CR7Reg , CCReg , InFlag ) . getValue ( <NUM_LIT> ) ; if ( <ISA_LIT>SubTarget . isGigaProcessor ( ) && OtherCondIdx == - <NUM_LIT> ) IntCR = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , CR7Reg , CCReg ) , <NUM_LIT> ) ; else IntCR = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , CCReg ) , <NUM_LIT> ) ; SDValue Ops [ ] = { IntCR , getI32Imm ( ( <NUM_LIT> - ( <NUM_LIT> - Idx ) ) & <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; if ( OtherCondIdx == - <NUM_LIT> && ! Inv ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; SDValue Tmp = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; if ( Inv ) { assert ( OtherCondIdx == - <NUM_LIT> && <STR_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Tmp , getI32Imm ( <NUM_LIT>


<s> static SDValue combineMulSpecial ( uint64_t MulAmt , SDNode * N , SelectionDAG & DAG , EVT VT , SDLoc DL ) { auto combineMulShlAddOrSub = [ & ] ( int Mult , int Shift , bool isAdd ) { SDValue Result = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mult , DL , VT ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( Shift , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( isAdd ? <STR_LIT> : <STR_LIT> , DL , VT , Result , N -> getOperand ( <NUM_LIT> ) ) ; return Result ; } ; auto combineMulMulAddOrSub = [ & ] ( bool isAdd ) { SDValue Result = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; Result = DAG . getNode ( isAdd ? <STR_LIT> : <STR_LIT> , DL , VT , Result , N -> getOperand ( <NUM_LIT> ) ) ; return Result ; } ; switch ( MulAmt ) { default : break ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , false ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> ,


<s> Stub * <ISA_LIT>To<ISA_LIT>Stub :: doClone


<s> return __arm_vhcaddq_rot270_x_s32 ( __a ,


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return true ; return TARGET_ELF && tls_referenced_p


<s> } if ( Opcode == Instruction :: FRem ) { unsigned Cost = ( VF * LIBCALL_COST ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> && ScalarBits == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } } else { if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) return <NUM_LIT> ; if ( Opcode == Instruction :: FRem ) return LIBCALL_COST ; if ( Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) return ( ScalarBits >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: Or ) return <NUM_LIT> ; if ( Opcode == Instruction :: Xor && ScalarBits == <NUM_LIT> ) return <NUM_LIT> ; if ( UDivPow2 ) return <NUM_LIT> ; if ( SDivPow2 ) return SDivCostEstimate ; if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: SRem ) ) return ( ScalarBits < <NUM_LIT> ? <NUM_LIT> : ( ScalarBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( Opcode == Instruction :: UDiv || Opcode == Instruction :: URem ) return ( ScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo


<s> DebugLoc dl = Lower . getDebugLoc ( ) ; assert ( Lower . getValueType ( ) == Upper . getValueType ( ) && <STR_LIT> ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , Lower . getValueType ( ) . getVectorElementType ( ) , Lower . getValueType ( ) . getVectorNumElements ( ) * <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Vec = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , Upper , DAG . getConstant ( Lower . getValueType ( ) . getVectorNumElements ( ) , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( Vec , Lower , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return


<s> return ( uint32x4_t ) ( vabsq_f32 ( __a ) < vabsq_f32 ( __b ) ) ; return ( uint32x4_t ) __builtin_neon_vcagtv4sf (


<s> const MCExpr * E = getImm ( ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( E ) ) { uint64_t Value = CE -> getValue ( )


<s> int Bytes = TRI -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; Register StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; assert ( ( Bytes == <NUM_LIT> || Bytes == <NUM_LIT> || Bytes == <NUM_LIT> || Bytes == <NUM_LIT> ) && <STR_LIT> ) ; if ( Bytes != <NUM_LIT> ) { unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC


<s> CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; switch ( TheTriple . getOS ( ) ) { case Triple :: Bitrig : case Triple :: NetBSD : case Triple :: NaCl : ExceptionsType = ExceptionHandling :: DwarfCFI ; break ; default : ExceptionsType = ExceptionHandling ::


<s> return ( vector unsigned int ) __builtin_altivec_vmrglw ( ( vector signed int )


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ) ; if ( ! IsConstantImm ) return


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_cvttps2dq256 ( ( __v8sf


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( getTLSReg (


<s> static const uint16_t F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State


<s> ConstantInt * OverflowConst = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; bool NegImm = OverflowConst -> isNegative ( ) ; bool IsDecreasing = ( ( Opc == Instruction :: Sub ) && ! NegImm ) || ( ( Opc == Instruction :: Add ) && NegImm ) ; if ( ! IsDecreasing ) return false ; auto * CI = cast < ICmpInst > ( * I -> user_begin ( ) ) ; if ( CI -> isSigned ( ) || CI -> isEquality ( ) ) return false ; ConstantInt * ICmpConst = nullptr ; if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else return false ; APInt Total = ICmpConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? ICmpConst -> getValue ( ) . zext ( <NUM_LIT> ) : ICmpConst -> getValue ( ) ; Total += OverflowConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? OverflowConst -> getValue ( ) . abs ( ) . zext ( <NUM_LIT> ) : OverflowConst -> getValue ( ) . abs ( ) ; APInt Max = APInt :: getAllOnesValue ( <ISA_LIT>CodeGenPrepare ::


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs


<s> case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT>


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , <STR_LIT> , <STR_LIT> , DAG ) ) { SDLoc dl ( N ) ; if ( IsStrict ) { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , { <STR_LIT> , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , DAG . getBitcast ( <STR_LIT> , VZLoad ) } ) ; DCI . CombineTo ( N , Convert , Convert . getValue ( <NUM_LIT> ) ) ; } else


<s> APInt DefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( resolveBuildVector ( BVN , DefBits , UndefBits ) ) { SDValue NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) ) return NewOp ; UndefBits = ~ UndefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) || (

NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) ) return NewOp ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . reserve ( NumOps - <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) Ops . push_back ( Op . getOperand ( I ) ) ; if ( Op -> getNumValues ( ) == <NUM_LIT> ) return DAG . getNode ( Opcode , SDLoc ( Op ) ,


<s> Preheader -> getParent ( ) -> insert ( ++ Preheader -> getIterator ( ) , NewBlock ) ; Br -> removeFromParent ( ) ; NewBlock -> insert ( NewBlock -> end ( ) , Br ) ; Preheader -> replaceSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) , NewBlock ) ; NewBlock -> addSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * NewBlock , Br , WLS -> getDebugLoc ( ) , TII -> get ( WLS -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MIB . add ( WLS -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( WLS -> getOperand ( <NUM_LIT> ) ) ; if ( WLS -> getOpcode ( ) == <STR_LIT> ) MIB . add (


<s> virtual const char * getPassName ( ) const { return


<s> getActionDefinitionsBuilder ( { G_ADD , G_SUB } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_UADDE , G_USUBO , G_USUBE } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( {


<s> bool use_simple_return_p ( void ) { arm_stack_offsets *


<s> argtype = TREE_TYPE ( argtype ) ; if ( TYPE_READONLY ( argtype ) ) parmtype = build_qualified_type ( parmtype , TYPE_QUAL_CONST ) ; } return lang_hooks . types_compatible_p ( parmtype , argtype


<s> break ; case CODE_FOR_doloop_end_internal : insn_extract ( insn ) ; loop = & loops [ INTVAL ( recog_data . operand [ <NUM_LIT> ] ) ] ; end = ( struct mep_doloop_end * ) alloca ( sizeof ( struct mep_doloop_end ) ) ; end -> insn = insn ; end -> fallthrough = next_real_insn ( insn ) ; end -> counter = recog_data . operand [ <NUM_LIT> ] ; end -> label = recog_data . operand [ <NUM_LIT> ] ; end -> scratch = recog_data . operand [ <NUM_LIT> ] ; if ( loop -> end != <NUM_LIT> && simplejump_p ( end -> fallthrough ) ) { end -> next = loop -> end -> next ; loop -> end -> next = end ; } else { end -> next = loop -> end ; loop -> end = end ; } break ; } for ( loop = loops ; loop < loops + cfun -> machine -> doloop_tags ; loop ++ ) if ( mep_repeat_loop_p ( loop ) ) { rtx_code_label * repeat_label ; rtx label_ref ; repeat_label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , repeat_label ) ; emit_insn_before ( gen_repeat ( loop -> begin -> counter , label_ref ) , loop -> begin -> insn ) ; delete_insn ( loop -> begin -> insn ) ; mep_insert_repeat_label_last ( loop -> end -> insn , repeat_label , false , loop -> end -> next != <NUM_LIT> ) ; emit_insn_before ( gen_repeat_end ( ) , loop -> end -> insn ) ; delete_insn ( loop -> end -> insn ) ; for ( end = loop -> end -> next ; end != <NUM_LIT> ; end = end -> next ) { emit_jump_insn_before ( gen_jump ( repeat_label ) , end -> insn ) ; delete_insn ( end -> insn ) ; delete_insn ( end ->


<s> assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitIndirectBranch ( Inst . getOperand ( <NUM_LIT> ) , true , false , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitRet ( NULL , false , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitRet ( NULL , true , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitRet ( & Inst . getOperand ( <NUM_LIT> ) , false , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPArith ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPArith ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPArith ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPArith ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPArith ( <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT> ) ; EmitSPAdj ( Inst . getOperand ( <NUM_LIT> ) , Out ) ; return true ; case <STR_LIT> : assert ( State . PrefixSaved == <NUM_LIT>


<s> bool enableMachineScheduler ( ) const


<s> GISelAccessor * <ISA_LIT>GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * <ISA_LIT>GISel = new <ISA_LIT>GISelActualAccessor ( ) ; <ISA_LIT>GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; <ISA_LIT>GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; <ISA_LIT>GISel -> InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ; <ISA_LIT>GISel -> RegBankInfo . reset ( RBI ) ; setGISelAccessor ( * <ISA_LIT>GISel


<s> bool <ISA_LIT>FrameLowering :: hasGOT ( const MachineFunction


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm


<s> gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return <NUM_LIT> ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return <NUM_LIT>


<s> if ( ! Modifier || MO . getType ( ) != MachineOperand :: MO_Register ) return PrintOperand ( MI , OpNo , O ) ; if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_ATT ) O << '%' ; Register Reg = MO . getReg ( ) ; if ( strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT>


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE


<s> } } emit_insn ( gen_force_register_use ( stack_pointer_rtx ) ) ; if ( crtl -> profile || ! TARGET_SCHED_PROLOG ) emit_insn ( gen_blockage ( ) ) ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) emit_clobber ( gen_rtx_REG ( SImode , regno ) ) ; if ( ! df_regs_ever_live_p ( LR_REGNUM ) ) emit_use ( gen_rtx_REG ( SImode , LR_REGNUM ) ) ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( )


<s> unsigned <ISA_LIT>AsmParser :: getReg ( int


<s> assert ( Kind == RegisterList && <STR_LIT> ) ; return RegList


<s> Inst . addOperand ( MCOperand :: createReg ( QFRegs [ getReg ( ) ]


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> default : return false ; case TargetOpcode :: G_VAARG : return legalizeVaArg ( MI , MRI , MIRBuilder ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return legalizeShlAshrLshr ( MI , MRI , MIRBuilder


<s> gcc_assert ( arm_reg0 != IP_REGNUM ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , ops ) ; return <STR_LIT>


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ?


<s>
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
CSStackSize
+=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
bool
CanEliminateFrame
=
SavedRegs
.
count
(
)
==
<NUM_LIT>
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPRPaired
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;
int
FI
=
MFI
.
CreateStackObject
(
Size
,
Align
,