<s> if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero |= Mask ; } else if ( VT == <STR_LIT> || VT ==


<s> void setFormalArgInfo ( unsigned Size , bool


<s> bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , MF , RVLocs , C ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e


<s> if ( ! Subtarget . isTargetLinux ( ) ) return false ; Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; AddressSpace = getAddressSpace ( ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedCF = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { switch ( Op -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getNode ( ) -> getFlags ( ) . hasNoSignedWrap ( ) ) break ; LLVM_FALLTHROUGH ; default : NeedOF = true ; break ; } break ; } } if ( Op . getResNo ( ) != <NUM_LIT> || NeedOF || NeedCF ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , Op . getValueType ( ) ) ) ; } unsigned Opcode = <NUM_LIT> ; unsigned NumOperands = <NUM_LIT> ; SDValue ArithOp = Op ; switch ( ArithOp . getOpcode ( ) ) { case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! isProfitableToUseFlagOp ( Op ) ) break ; switch ( ArithOp . getOpcode


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned RegEnum = <NUM_LIT> ; switch ( OpInfo [ <NUM_LIT> ] . RegClass ) { case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , false ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , true ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return false


<s> if ( ! VCTPs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; for ( auto * MI : VCTPs ) dbgs ( ) << <STR_LIT> << * MI ; } if ( ! FoundAllComponents ( ) ) dbgs ( ) << <STR_LIT> ; else if ( ! ( Start && Dec && End ) ) dbgs (


<s> return ( ( NoFramePointerElim && MFI -> hasCalls ( ) ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI ->


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr (


<s> case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_I : return translateFPRegister ( mcInst , insn . opcodeModifier ) ; case ENCODING_Rv


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_<ISA_LIT>_AllRegs_Vector_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError

) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF ::


<s> unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize == <NUM_LIT> ) ) return Factor ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor ,


<s> assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return


<s> Parser . addAliasForDirective ( <STR_LIT> , is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( is64Bit ( ) ) Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT>


<s> if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT>


<s> static unsigned toDirectCall ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ?


<s> case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; return false ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; if ( RegNo == <NUM_LIT> && Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo = <STR_LIT> ; break ; case '7' : RegNo =


<s> Value * <ISA_LIT>IREmitter :: visitVORRIMM (


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , <NUM_LIT> ) , adj . offset_adjust , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return


<s> ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p


<s> return ( vector float ) __builtin_altivec_vrsqrtefp (


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Subtarget . hasMSA ( ) || ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; if ( Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) && SplatBitSize <= <NUM_LIT> ) { if ( SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> ) return SDValue ( ) ; if ( ResTy . isInteger ( ) && ! HasAnyUndefs && SplatValue . isSignedIntN ( <NUM_LIT> ) ) return Op ; EVT ViaVecTy ; switch ( SplatBitSize ) { default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue ( ) ; } SDValue Result = DAG . getConstant ( SplatValue , DL , ViaVecTy ) ; if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return Result ; } else if ( isSplatVector ( Node ) ) return Op ; else if ( ! isConstantOrUndefBUILD_VECTOR ( Node ) ) { EVT ResTy = Node ->


<s> bool HasFP = hasFP ( MF ) ; DebugLoc DL ; if ( ForceStackAlign ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ; } int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) <ISA_LIT>FI -> setCalleeSavedFrameSize ( <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) - TailCallReturnAddrDelta ) ; if ( Is64Bit && ! Fn -> hasFnAttr ( Attribute :: NoRedZone ) && ! needsStackRealignment ( MF ) && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! Subtarget -> isTargetWin64 ( ) ) { uint64_t MinSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; if ( HasFP ) MinSize += SlotSize ; StackSize = std :: max ( MinSize , StackSize > <NUM_LIT> ? StackSize - <NUM_LIT> : <NUM_LIT> ) ; MFI -> setStackSize ( StackSize ) ; } else if ( Subtarget -> isTargetWin64 ( ) ) { StackSize += <NUM_LIT> ; MFI -> setStackSize ( StackSize ) ; } if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( getSUBriOpcode ( Is64Bit , - TailCallReturnAddrDelta ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - TailCallReturnAddrDelta ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = MF . getTarget ( ) . getTargetData ( ) ; uint64_t NumBytes = <NUM_LIT> ; int stackGrowth = - TD -> getPointerSize ( ) ; if ( HasFP ) { uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FramePtr , RegState :: Kill ) ; if ( needsFrameMoves ) { MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; if ( StackSize ) { MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , <NUM_LIT> * stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } else { MachineLocation SPDst ( StackPtr ) ; MachineLocation SPSrc ( StackPtr , stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabel ,


<s> return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI (


<s> uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , TargetMachine & TM , unsigned SyntaxVariant , const MCAsmInfo & MAI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( TM , MAI ) ; return <NUM_LIT>


<s> bool Error ( SMLoc L , const Twine & Msg ) { return getParser ( ) . Error (


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && ( Inst . getOperand ( ImmOp ) . isImm ( ) || Inst . getOperand ( ImmOp ) . isExpr ( ) ) && ( ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Inst . getNumOperands ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT>


<s> static bool ix86_ms_bitfield_layout_p ( tree record_type ) { return ( TARGET_MS_BITFIELD_LAYOUT && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ) || lookup_attribute ( <STR_LIT>


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SDValue Extract = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NarrowVT = Extract . getValueType ( ) ; if ( ( VT != <STR_LIT> || NarrowVT != <STR_LIT> ) && ( VT != <STR_LIT> || NarrowVT != <STR_LIT> )


<s> bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return


<s> if ( ctrl == <NUM_LIT> ) { unsigned byte = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( byte ) { case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | imm ) ) ; break ; case


<s> if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT>

) || Ty -> isIntegerTy ( <NUM_LIT> ) ) return true ;


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p = strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \ putc ( '\n' ,

FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * >


<s> uws -> bytes_left = <NUM_LIT> ; } else uws -> bytes_left -- ; b = ( uws -> data >> <NUM_LIT> ) & <NUM_LIT> ; uws -> data <<= <NUM_LIT> ; return


<s> TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand (

OpNum + <NUM_LIT> ) , Fixups , STI ) - <NUM_LIT> ;


<s> static bool isUNPCKLMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 , bool V2IsSplat = false ) { assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts /


<s> return GET_CODE ( p ) == SET && arith_reg_dest ( XEXP ( p , <NUM_LIT> ) , SImode ) && negt_reg_operand ( XEXP ( p , <NUM_LIT> ) , VOIDmode ) ? XEXP ( p ,


<s> if ( nregs == <NUM_LIT> && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) { if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return mode ; else return SImode ; } else return choose_hard_reg_mode ( regno , nregs ,


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand &


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Value &= ~ ( <NUM_LIT> << QBitShift ) ; if ( LPAC :: modifiesOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) ) ) Value |= ( <NUM_LIT> << QBitShift ) ; return Value


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS


<s> case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: UIToFP : return <ISA_LIT>SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; MVT SVT = SrcVT . getSimpleVT ( ) ; MVT DVT = DstVT . getSimpleVT ( ) ; if ( ! SVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SVT . is256BitVector ( ) ) && ! ( Subtarget -> hasAVX512 ( ) && SVT . is512BitVector ( ) &&

( Subtarget -> hasBWI ( ) || ( SVT . getScalarSizeInBits ( ) >= <NUM_LIT> && DVT . getScalarSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return false ;


<s> int64_t AddrDispShift ; int Dist ; if ( ! chooseBestLEA ( LEAs [ getMemOpKey ( MI , MemOpNo ) ] , MI , DefMI , AddrDispShift , Dist ) ) continue ; if ( Dist < <NUM_LIT> ) { DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; InstrPos [ DefMI ] = InstrPos [ & MI ] - <NUM_LIT> ; assert ( ( ( InstrPos [ DefMI ] == <NUM_LIT> && DefMI == MBB -> begin ( ) ) || InstrPos [ DefMI ] > InstrPos [ std :: prev ( MachineBasicBlock :: iterator ( DefMI ) ) ] ) && <STR_LIT> ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isPseudo ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; OutStreamer -> EmitInstruction ( TmpInst0 , getSubtargetInfo (


<s> EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; auto * MINode = cast < MemIntrinsicSDNode > ( N ) ; SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } return L


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <STR_LIT> , false ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ;


<s> bool isImm0_65535Expr ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> bool <ISA_LIT>TargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , FixedVectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> ) return false ; if ( VecTy -> getNumElements ( ) < <NUM_LIT> )


<s> NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT>


<s> void setGlobalBaseReg ( Register Reg


<s> } Info . OneUser = true ; if ( isCandidateLoad ( MI ) ) { Info . Type = MCLOH_AdrpLdr ; Info . IsCandidate = true ; Info . MI0 = & MI ; } else if ( isCandidateStore ( MI , MO ) ) { Info . Type = MCLOH_AdrpAddStr ; Info . IsCandidate = true ; Info . MI0 = & MI ; Info . MI1


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_load_epi32 ( void const * __P ) { return ( __m256i ) ( * ( __v8si * ) __P


<s> const Type * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; LoadInst * NewLd0 = CreateLoadIns ( Builder , VecLd0 [ <NUM_LIT> ] , Ty ) ; LoadInst * NewLd1 = CreateLoadIns ( Builder , VecLd1 [ <NUM_LIT> ] , Ty ) ; Value * Args [ ] = { NewLd0 , NewLd1 , Acc } ; Function * SMLAD = nullptr ; if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; CallInst * Call = Builder . CreateCall ( SMLAD , Args ) ; NumSMLAD


<s> const <ISA_LIT>RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; bool NeedsStackRealignment = RegInfo . shouldRealignStack ( MF ) ; DebugLoc DL ; if ( NeedsStackRealignment && ! RegInfo . canRealignStack ( MF ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; uint64_t NumBytes = MFI . getStackSize ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { NumBytes = STI . getAdjustedFrameSize ( NumBytes ) ; } NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; if ( ! FuncInfo -> isLeafProc ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; assert ( ( RuntimeAlign == None || ! FuncInfo ->


<s> if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is64BitVector ( ) ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is128BitVector ( ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( RegVT == Ins [ i ] . VT && <STR_LIT> ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ArgOffset = VA . getLocMemOffset ( ) ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint32_t BEAlign


<s> error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } tree new_sve_type_args = copy_list ( TREE_VALUE ( attr ) ) ; tree mangled_name_node = chain_index ( <NUM_LIT> , new_sve_type_args ) ; const char * old_mangled_name = IDENTIFIER_POINTER ( TREE_VALUE ( mangled_name_node ) ) ; char * new_mangled_name = xasprintf ( <STR_LIT> , old_mangled_name , ( int ) value ) ; TREE_VALUE ( mangled_name_node ) = get_identifier ( new_mangled_name ) ; free ( new_mangled_name ) ; tree new_type ; tree base_type = TYPE_MAIN_VARIANT ( type ) ; if ( lang_GNU_C ( ) && VECTOR_BOOLEAN_TYPE_P ( type ) ) new_type = build_variant_type_copy ( base_type ) ; else new_type = build_distinct_type_copy ( base_type ) ; tree acle_name_node = TREE_CHAIN


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand MMO ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , MFI . getObjectOffset ( FI ) + Offset , MFI . getObjectSize ( FI )


<s> if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return false ; for ( int i = <NUM_LIT> , j = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j + NumElts / <NUM_LIT> ) ) return false ; if ( V2IsSplat ) { if ( isUndefOrEqual ( BitI1 , NumElts ) ) return false ; } else { if ( ! isUndefOrEqual ( BitI1 , j + NumElts / <NUM_LIT> + NumElts ) ) return false ; } } return


<s> static const char * ia64_invalid_binary_op ( int op ATTRIBUTE_UNUSED , const_tree type1 , const_tree type2 ) { if ( TYPE_MODE ( type1 ) == RFmode || TYPE_MODE ( type2


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> void setFormalArgInfo ( unsigned Offset , bool HasByval ) { NextStackOffset = Offset ; HasByvalArg = HasByval


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; } return Modified


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op


<s> case <STR_LIT> : TestOpc = <STR_LIT> ; break ; } if ( TestOpc ) { unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TestOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; unsigned JmpOpc = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TrueMBB ) ) { std :: swap ( TrueMBB , FalseMBB ) ; JmpOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( JmpOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } } } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , BI , BI -> getCondition ( ) ) ) { unsigned TmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( TmpReg == <NUM_LIT> ) return false ; unsigned BranchOpc = <STR_LIT> ( CC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BranchOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } unsigned OpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor (


<s> MachineBasicBlock * target = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned CmpOpc ; if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiXOpc ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( CmpOpc )


<s> EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static && ! DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , Group , Regs


<s> if ( frame_off != <NUM_LIT> ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else if ( REGNO ( frame_reg_rtx ) != updt_regno

) return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ;


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) .

addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; case ORDERED : case UNORDERED : case UNGT : case UNLT : case UNEQ : case UNGE : case UNLE : case LTGT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_ARCH64 ) { if ( MEM_P ( x ) ) { tree expr = MEM_EXPR ( x ) ; if ( expr ) mark_addressable ( expr ) ; slot0 = x ; } else { slot0 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot0 , x ) ; } if ( MEM_P ( y ) ) { tree expr = MEM_EXPR ( y ) ; if ( expr ) mark_addressable ( expr ) ; slot1 = y ; } else { slot1 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot1 , y ) ; } libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , DImode , XEXP ( slot0 , <NUM_LIT> ) , Pmode , XEXP ( slot1 , <NUM_LIT> ) , Pmode ) ; mode = DImode ; } else { libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , SImode , x , TFmode , y , TFmode ) ; mode = SImode ; } result = gen_reg_rtx ( mode ) ; emit_move_insn ( result , hard_libcall_value ( mode , libfunc ) ) ; switch ( comparison ) { default : return gen_rtx_NE ( VOIDmode , result , const0_rtx ) ; case ORDERED : case UNORDERED : new_comparison = ( comparison == UNORDERED ? EQ : NE ) ; return gen_rtx_fmt_ee ( new_comparison , VOIDmode , result , GEN_INT ( <NUM_LIT> ) ) ; case UNGT : case UNGE : new_comparison = ( comparison == UNGT ? GT : NE ) ; return gen_rtx_fmt_ee ( new_comparison , VOIDmode , result , const1_rtx ) ; case UNLE : return gen_rtx_NE ( VOIDmode , result , const2_rtx ) ; case UNLT : tem = gen_reg_rtx ( mode ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_andsi3 ( tem , result , const1_rtx ) ) ; else emit_insn ( gen_anddi3 ( tem , result , const1_rtx ) ) ; return gen_rtx_NE ( VOIDmode , tem , const0_rtx ) ; case


<s> return mips_return_fpr_pair ( mode , TYPE_MODE ( TREE_TYPE ( fields [ <NUM_LIT> ] ) ) , int_byte_position ( fields [ <NUM_LIT> ] ) , TYPE_MODE ( TREE_TYPE ( fields [ <NUM_LIT> ] ) ) , int_byte_position ( fields [ <NUM_LIT> ] ) ) ; } if ( mips_return_in_msb ( valtype ) ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; if ( size % UNITS_PER_WORD != <NUM_LIT> ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , <NUM_LIT> ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ! TARGET_MIPS16 ) { if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , <NUM_LIT> , DImode , GET_MODE_SIZE ( mode ) / <NUM_LIT> ) ; if ( mips_return_mode_in_fpr_p (


<s> APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; EVT ResVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) ; SDValue Cmp ; if ( IsStrict ) { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> , Chain , true ) ; Chain = Cmp . getValue ( <NUM_LIT> ) ; } else { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> ) ; } Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue FltOfs = DAG . getSelect ( DL , TheVT , Cmp , DAG . getConstantFP ( <NUM_LIT> , DL , TheVT ) , ThreshVal ) ; if ( IsStrict ) { Value = DAG . getNode ( <STR_LIT> , DL , { TheVT , <STR_LIT> } , { Chain , Value , FltOfs } ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } else Value = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , FltOfs ) ; } MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; if ( isScalarFPTypeInSSEReg (


<s> case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : break ; } const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression

( Expr ) ) return MatchOperand_ParseFail ;


<s> static tree arm_lookup_simd_builtin_type ( machine_mode mode , enum arm_type_qualifiers q ) { int i ; int nelts = ARRAY_SIZE ( arm_simd_types ) ; if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode ) ) return arm_simd_builtin_std_type


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const


<s> SDNode * InNode = InDouble . getNode ( ) ; if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode > ( InNode ) -> isVolatile ( ) ) { LoadSDNode * LD = cast < LoadSDNode > ( InNode ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( LD ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; DCI . RemoveFromWorklist ( LD ) ; DAG . DeleteNode ( LD ) ; return Result ; } return SDValue ( )


<s> State = IES_ERROR ; break ; case IES_LPAREN : setType ( Type )


<s> return ( __m512i ) __builtin_ia32_pabsw512_mask ( ( __v32hi ) __A , ( __v32hi ) _mm512_setzero_hi ( ) ,


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; assert ( ! RegInfo -> needsStackRealignment (


<s> SpillsKnownBit = true ; break ; default : if ( Subtarget . isISA3_0 ( ) ) { if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) { BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) ; break ; } } BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; bool KillsCRBit = MI . killsRegister ( SrcReg , TRI ) ; MBB . erase ( II ) ; if ( SpillsKnownBit && KillsCRBit &&


<s> if ( isAMXCast ( dyn_cast < Instruction > ( V ) ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; OpNo = U . getOperandNo ( ) ; V = U . getUser ( ) ; } else if ( isAMXInstrinsic ( V ) ) { return getShape ( cast < IntrinsicInst > ( V ) , OpNo ) ; } else if ( isa < PHINode > ( V ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; V = U . getUser ( ) ; } else { break ; } } return std :: make_pair (


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalBaseRegPass (


<s> setUsesTOCBasePtr ( DAG . getMachineFunction ( )


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst


<s> unsigned ImmS = Width - <NUM_LIT> ; SDLoc DL ( N ) ; SDValue Ops [ ] = { Op0 , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; return CurDAG -> SelectNodeTo ( N , Opc


<s> case MODE_VECTOR_FLOAT : if ( TARGET_HAVE_MVE_FLOAT ) emit_insn ( gen_mve_vcmpq_f ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; else gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } } else emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , op1 ) ) ; return inverted ; case GEU : case GTU : if ( TARGET_HAVE_MVE ) emit_insn ( gen_mve_vcmpq ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; else emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; return inverted ; case LEU : case LTU : if ( TARGET_HAVE_MVE ) emit_insn ( gen_mve_vcmpq ( swap_condition ( code ) , cmp_mode , target , force_reg ( cmp_mode , op1 ) , op0 ) ) ; else emit_insn ( gen_neon_vc ( swap_condition ( code ) , cmp_mode , target , force_reg ( cmp_mode , op1 ) , op0 ) ) ; return inverted ; case LTGT : case ORDERED


<s> static SDValue lowerFPToIntToFP ( SDValue CastToFP , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue CastToInt = CastToFP . getOperand ( <NUM_LIT> ) ; MVT VT = CastToFP . getSimpleValueType ( ) ; if ( CastToInt . getOpcode ( ) != <STR_LIT> || VT . isVector ( ) ) return SDValue ( ) ; MVT IntVT = CastToInt . getSimpleValueType ( ) ; SDValue X = CastToInt . getOperand ( <NUM_LIT> ) ; MVT SrcVT = X . getSimpleValueType ( ) ; if ( SrcVT != <STR_LIT> && SrcVT !=


<s> const IntegerType * IntTy = dyn_cast < IntegerType > ( V -> getType ( ) ) ; if ( ! IntTy ) return false ; if ( IntTy -> getBitWidth ( ) == <NUM_LIT> ) return false ; if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) return isSupportedType ( ZExt ->


<s> MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I -> eraseFromParent ( ) ; return Copy


<s> auto * CI0 = C0 ? dyn_cast_or_null < ConstantInt > ( C0 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; if ( CILength && CIIndex ) { APInt APIndex = CIIndex -> getValue ( ) . zextOrTrunc ( <NUM_LIT> ) ; APInt APLength = CILength -> getValue ( ) . zextOrTrunc ( <NUM_LIT> ) ; unsigned Index = APIndex . getZExtValue ( ) ; unsigned Length = APLength == <NUM_LIT> ? <NUM_LIT> : APLength . getZExtValue ( ) ; unsigned End = Index + Length ; if ( End > <NUM_LIT> ) return UndefValue :: get ( II . getType ( ) ) ; if ( ( Length % <NUM_LIT> ) == <NUM_LIT> && ( Index % <NUM_LIT> ) == <NUM_LIT> ) { Length /= <NUM_LIT> ; Index /= <NUM_LIT> ; Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; auto * ShufTy = FixedVectorType :: get ( IntTy8 , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; for ( int i = <NUM_LIT> ; i != ( int ) Length ; ++ i ) ShuffleMask . push_back ( i + Index ) ; for ( int i = Length ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i + <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( - <NUM_LIT> ) ; Value * SV = Builder . CreateShuffleVector ( Builder . CreateBitCast ( Op0 , ShufTy ) , ConstantAggregateZero :: get ( ShufTy ) , ShuffleMask ) ; return Builder . CreateBitCast ( SV , II . getType ( ) ) ; } if ( CI0 ) { APInt Elt = CI0 ->


<s> } else if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ZeroReg = <STR_LIT> ; } if ( ! DstReg ) return false ; for ( MachineRegisterInfo :: use_iterator U = MRI -> use_begin ( DstReg ) , E = MRI -> use_end ( ) ; U != E ; ) { MachineOperand & MO = * U ; unsigned OpNo = U . getOperandNo ( ) ; MachineInstr * MI = MO . getParent ( ) ; ++ U ; if ( MI -> isPHI ( ) || MI -> isRegTiedToDefOperand ( OpNo ) || MI -> isPseudo ( ) ) continue ; MO . setReg ( ZeroReg ) ; } return


<s> unsigned NumOperands = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Dest = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; unsigned Op0 = getFPReg ( MI -> getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI -> getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned TOS = getStackEntry ( <NUM_LIT> ) ; if ( Op0 != TOS && Op1 != TOS ) { if ( KillsOp0 ) { moveToTop ( Op0 , I ) ; TOS = Op0 ; } else if ( KillsOp1 ) { moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable ; else InstTable = ReverseSTiTable ; } int Opcode = Lookup ( InstTable , MI -> getOpcode ( ) ) ; assert ( Opcode != - <NUM_LIT> && <STR_LIT> ) ; unsigned NotTOS = ( TOS == Op0 ) ? Op1 : Op0 ; MBB -> remove ( I ++ ) ; I = BuildMI ( * MBB , I , dl , TII -> get ( Opcode ) ) . addReg ( getSTReg ( NotTOS ) ) ; if ( KillsOp0 && KillsOp1 && Op0 != Op1 ) { assert ( ! updateST0 && <STR_LIT> ) ; popStackAfter ( I ) ; } unsigned UpdatedSlot = getSlot ( updateST0 ? TOS : NotTOS


<s> case XOR : { rtx op0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; rtx op1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) != REG || sparc_check_64 ( op0 , insn ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) == CONST_INT ) return INTVAL ( op1 ) >= <NUM_LIT> ; return ( GET_CODE ( op1 ) == REG && sparc_check_64 ( op1 , insn ) == <NUM_LIT> ) ; } case LSHIFTRT : return GET_MODE ( SET_SRC ( pat ) ) == SImode ; case CONST_DOUBLE : return ! ( CONST_DOUBLE_LOW ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case CONST_INT : return ! ( INTVAL ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case ASHIFTRT : case SIGN_EXTEND : return - ( GET_MODE ( SET_SRC ( pat ) ) == SImode ) ; case REG


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts


<s> switch ( SF ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable (


<s> inline SDValue getI32Imm ( uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm ,


<s> if ( ! Subtarget -> hasSSE3orAVX ( ) ) return false ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i

) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ;


<s> unsigned getNumLocalDynamicTLSAccesses (


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>GVSymbol ( const GlobalValue * GV ) { bool isIndirect = Subtarget -> isTargetDarwin ( ) && Subtarget -> GVIsIndirectSymbol ( GV , TM . getRelocationModel ( ) ) ; if ( ! isIndirect ) return Mang -> getSymbol ( GV ) ; MCSymbol * MCSym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym =


<s> __inline__ static unsigned long long sh_media_SWAP_Q ( void * mm , long long mn , unsigned long long mw ) { unsigned long long res ; unsigned long long * addr = ( unsigned long long * ) ( ( char * ) mm + mn ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) , <STR_LIT> ( * addr ) : <STR_LIT>


<s> if ( GV -> isThreadLocal ( ) ) return false ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return false ; auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Cst ) return false ; MinOffset = std :: min ( MinOffset , Cst -> Value . getZExtValue ( ) ) ; } uint64_t CurrOffset = GlobalOp . getOffset


<s> static SDValue combineFAnd ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( SDValue V = getNullFPConstForNullVal ( N -> getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ) return V ; if ( SDValue V = getNullFPConstForNullVal ( N -> getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ) return V ; if ( SDValue V = combineFAndFNotToFAndn ( N ,


<s> case <STR_LIT> : if ( ! I -> getOperand ( <NUM_LIT> ) . isSymbol ( ) || strcmp ( I -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , <STR_LIT> ) ) break ; if ( TLSBaseAddrReg ) I = replaceTLSBaseAddrCall ( I , TLSBaseAddrReg ) ; else I = setRegister ( I , & TLSBaseAddrReg ) ; Changed = true ; break ; default : break ; } } for ( MachineDomTreeNode * N


<s> for ( MachineInstr :: const_mop_iterator Mop = Instr -> operands_begin ( ) ; Mop != Instr -> operands_end ( ) ; ++ Mop ) { if ( isSameOperand ( * Mop , * Reg


<s> return isXMMLoadOpcode ( Opcode ) || isYMMLoadOpcode ( Opcode


<s> TargetTransformInfo <ISA_LIT>BaseTargetMachine :: getTargetTransformInfo ( const Function &


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; PopMI -> setDesc ( get


<s> bool isVecListFourQWordIndexed ( ) const { if ( ! isDoubleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex <=


<s> arm_builtin_datum * d = & acle_builtin_data [ fcode - ARM_BUILTIN_ACLE_PATTERN_START ] ; return arm_expand_builtin_1 ( fcode , exp ,


<s> for ( const Use & U : SExt -> uses ( ) ) { if ( isa < GetElementPtrInst > ( * U )


<s> return ( MI && MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && <STR_LIT> ( MI

-> getOperand ( <NUM_LIT> ) . getImm ( ) ) == Bytes && getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> else if ( AFI -> isDPRCalleeSavedAreaFrame ( FI ) ) return Offset - AFI -> getDPRCalleeSavedAreaOffset ( ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( MFI -> hasVarSizedObjects ( ) && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( )

, IndexVT . getVectorNumElements ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , getDataLayoutString ( Triple ( TT ) ) , TT , CPU , computeFSAdditions ( FS

, OL , TT ) , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , TargetABI ( computeTargetABI ( Triple ( TT ) , Options ) ) {


<s> BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( )


<s> Value * <ISA_LIT>IREmitter :: visitVMULLs ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> } if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; warned_for_return_big_vectors = true ; } return true ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE ( type )


<s> void <ISA_LIT>InstrInfo :: expandRXYPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned HighOpcode ) const { Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx / Scale ; if ( ( V0Opc != <STR_LIT> || V0BroadcastIdx != <NUM_LIT> ) && V0Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Scalar = V0 . getOperand ( V0BroadcastIdx ) ; if ( const int OffsetIdx = BroadcastIdx % Scale ) Scalar = DAG . getNode ( <STR_LIT> , DL , Scalar . getValueType ( ) , Scalar , DAG . getConstant ( OffsetIdx * EltSize , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode


<s> if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) std :: swap ( LHS , RHS ) ; if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDLoc DL ( N ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = LHS . getValueType ( ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Register :: isPhysicalRegister ( Cond [ <NUM_LIT> ] . getReg ( ) ) ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC )

&& ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ;


<s> rs6000_gen_section_name ( & xcoff_read_only_section_name , main_input_filename , <STR_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_quoted_string ( asm_out_file , main_input_filename ) ; fputc ( '\n' , asm_out_file ) ; if ( write_symbols != NO_DEBUG ) private_data_section


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; return SDValue (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ; return combineAddOrSubToADCOrSBB ( N , DAG


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


( float const * base , __m256i index , const int scale ) {


<s> if ( ! isSysReg ( ) ) return false ; return SysReg . PStateField ==


<s> if ( STI . isDarwinABI ( ) || STI . isAIXABI ( )

) return STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) )

) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ;


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasV4TOps = false ; HasV5TOps = false ; HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false


<s> PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrMode2OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI


<s> SmallVector < uint32_t , <NUM_LIT> > VPShuf ; SmallVector < uint32_t , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < uint32_t , <NUM_LIT> > VPAlign2 ; SmallVector < uint32_t , <NUM_LIT> > VPAlign3 ; SmallVector < uint32_t , <NUM_LIT> > GroupSize ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; createShuffleStride ( VT , <NUM_LIT> , VPShuf ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> - i ] , VPAlign [ i ] , false ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , true , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec ,


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { return NumCycles


<s> getImm ( ) -> print ( OS ) ; break ; case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; getShiftedImmVal ( ) -> print ( OS ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token


<s> unsigned getSlotSize ( ) const { return SlotSize


<s> bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: GHC ; bool BackChain = MF . getFunction ( ) .


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst

. addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( isa < LSBaseSDNode > ( MemN ) || ( ( MemN -> getOpcode ( ) == <STR_LIT> || MemN -> getOpcode ( ) == <STR_LIT> ) && MemN -> getConstantOperandVal ( MemN -> getNumOperands ( ) - <NUM_LIT> ) == <NUM_LIT> ) ) { unsigned MMOAlign = MemN -> getAlignment ( ) ; unsigned MemSize = MemN -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( MMOAlign >= MemSize && MemSize > <NUM_LIT> ) Alignment = MemSize ; } else


<s> rtx cmp_op1 = * op1 ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) == MODE_INT ) { if ( ! need_eq_ne_p && * op1 == const0_rtx ) ; else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; } else * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_op0 ) ) ; mips_emit_int_order_test ( * code , & invert , * op0 , cmp_op0 , cmp_op1 ) ; * code = ( invert ? EQ : NE ) ; * op1 = const0_rtx ; } } else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc


) return CSR_<ISA_LIT>_AllRegs_RegMask ;


<s> SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , A ) , DAG . getBitcast ( <STR_LIT> , B ) ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Aodds ) , DAG . getBitcast ( <STR_LIT> , Bodds ) ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; KnownBits AKnown = DAG . computeKnownBits ( A ) ; KnownBits BKnown = DAG . computeKnownBits ( B ) ; APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = LowerBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BLoIsZero = LowerBitsMask . isSubsetOf ( BKnown . Zero ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = UpperBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BHiIsZero = UpperBitsMask . isSubsetOf ( BKnown . Zero ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = Zero ; if ( ! ALoIsZero && ! BHiIsZero ) { SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; } SDValue AhiBlo = Zero ; if ( ! AHiIsZero && ! BLoIsZero ) { SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> } auto CanPair = [ & ] ( Reduction & R , BinOpChain * PMul0 , BinOpChain * PMul1 ) { if ( ! PMul0 -> AreSymmetrical ( PMul1 ) ) return false ; for ( unsigned x = <NUM_LIT> ; x < PMul0 -> LHS . size ( ) ; x += <NUM_LIT> ) { auto * Ld0 = dyn_cast < LoadInst > ( PMul0 -> LHS [ x ] ) ; auto * Ld1 = dyn_cast < LoadInst > ( PMul1 -> LHS [ x ] ) ; auto * Ld2 = dyn_cast < LoadInst > ( PMul0 -> RHS [ x ] ) ; auto * Ld3 = dyn_cast < LoadInst > ( PMul1 -> RHS [ x ] ) ; if ( ! Ld0 || ! Ld1 || ! Ld2 || ! Ld3 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * Ld0 << <STR_LIT> << <STR_LIT> << * Ld1 << <STR_LIT> << <STR_LIT> << * Ld2 << <STR_LIT> << <STR_LIT> << * Ld3 << <STR_LIT> ) ; if ( AreSequentialLoads ( Ld0 , Ld1 , PMul0 -> VecLd ) ) { if ( AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } else if ( AreSequentialLoads ( Ld3 , Ld2 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul1 -> Exchange = true ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul0 -> Exchange = true ; R . AddMulPair ( PMul1 , PMul0 ) ; return true ; } } return false ; } ; OpChainList & Muls = R . getMuls ( ) ; const unsigned Elems = Muls . size ( ) ; SmallPtrSet < const Instruction * , <NUM_LIT> > Paired ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { BinOpChain * PMul0 = static_cast < BinOpChain * > ( Muls [ i ] . get ( ) ) ; if ( Paired . count ( PMul0 ->


<s> return m_DtpOffsetMap . lookup ( & pInput


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size ( ) ) ) ; } SwitchSection ( & FnStart -> getSection (


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Op = N . getOperand ( <NUM_LIT> ) ; EVT FromVT = Op . getValueType ( ) ; SDLoc DL ( N ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , FromVT , Op , DAG . getConstant ( <NUM_LIT> , DL , FromVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , And , DAG . getConstant ( <NUM_LIT>

, DL , FromVT ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> bool aarch64_symbolic_address_p ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return GET_CODE ( x ) == SYMBOL_REF || GET_CODE (


<s> ( to == STACK_POINTER_REGNUM && frame_pointer_needed ) ? false : ( to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB ) ?


<s> SDValue Lo = getTargetNode ( Op , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT>


<s> __rv . __o = __builtin_neon_vld4v8hi ( ( const


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . addOperand ( MCOperand :: createReg


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; if ( State . isVarArg ( ) ) { unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; for ( unsigned j = <NUM_LIT> ; j < ArgsParts [ i ] ; j ++ ) { if ( i == <NUM_LIT> && j == <NUM_LIT> ) State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; } } return ; } unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT ,

LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ;


<s> static SDValue splitStores ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { StoreSDNode * S = cast < StoreSDNode > ( N ) ; if ( S -> isVolatile ( ) || S -> isIndexed ( ) ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isFixedLengthVector ( ) ) return SDValue ( ) ; if ( SDValue ReplacedZeroSplat = replaceZeroVectorStore ( DAG , * S ) ) return ReplacedZeroSplat ; if ( ! Subtarget -> isMisaligned128StoreSlow ( ) ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL (


<s> tree expected = acle_vector_types [ <NUM_LIT> ] [ type ] ; tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return false ; if ( ! matches_type_p ( expected , actual ) ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , expected ) ; return false


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( )


<s> static unsigned getMatchingNonSExtOpcode ( unsigned Opc , bool * IsValidLdStrOpc = nullptr ) { if ( IsValidLdStrOpc ) * IsValidLdStrOpc = true ; switch ( Opc ) { default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static rtx mmix_function_incoming_arg ( cumulative_args_t argsp , machine_mode mode ,


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( (

( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ;


<s> static void computeKnownBitsBinOp ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth , unsigned OpNo ) { APInt Src0DemE = getDemandedSrcElements ( Op , DemandedElts , OpNo ) ; APInt Src1DemE = getDemandedSrcElements ( Op , DemandedElts , OpNo + <NUM_LIT> ) ; unsigned SrcBitWidth = Op . getOperand ( OpNo ) . getScalarValueSizeInBits (


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef


<s> const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_INSERT , Ty } , Legal ) ; setAction ( { G_EXTRACT , <NUM_LIT> , Ty } ,


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; uint64_t AlignVal = ( RealignOpt ? dyn_cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) : <NUM_LIT> ) ; uint64_t StackAlign = TFI -> getStackAlignment ( ) ; uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ~ ( RequiredAlign - <NUM_LIT> ) , DL , <STR_LIT> ) ) ; } if ( StoreBackchain ) Chain = DAG . getStore ( Chain , DL , Backchain , NewSP , MachinePointerInfo ( ) ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> static bool rs6000_offsettable_memref_p ( rtx op , machine_mode reg_mode ) { bool worst_case ; if ( ! MEM_P ( op ) ) return false ; if ( offsettable_address_p ( true , GET_MODE ( op ) , XEXP ( op


<s> op [ nop ++ ] = target ; } else target = NULL_RTX ; for ( int i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ , nop ++ ) { if ( ! signature_args [ signature ] [ i ] ) break ; tree arg = CALL_EXPR_ARG ( exp , i - <NUM_LIT> ) ; if ( arg == error_mark_node ) return const0_rtx ; machine_mode opmode ; tree optype ; if ( signature_args [ signature ] [ i ] & <NUM_LIT> ) { opmode = ptr_mode ; optype = ptr_type_node ; } else { opmode = insn_data [ icode ] . operand [ nop ] . mode ; optype = ( * lang_hooks . types . type_for_mode ) ( opmode , <NUM_LIT> ) ; } machine_mode argmode = TYPE_MODE ( TREE_TYPE ( arg ) ) ; if ( argmode != opmode ) arg = build1 ( NOP_EXPR , optype , arg ) ; op [ nop ] = expand_expr ( arg , NULL_RTX , opmode , EXPAND_NORMAL ) ; if ( ! ( * insn_data [ icode ] . operand [ nop ] . predicate ) ( op [ nop ] , opmode ) ) op [ nop ] = copy_to_mode_reg ( opmode , op [ nop ] ) ; } rtx pat = NULL_RTX ; switch ( nop ) { case <NUM_LIT> : pat = ( * insn_data [ d -> icode ] . genfun ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = ( * insn_data [ d -> icode ] . genfun ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = ( * insn_data [ d -> icode ] . genfun ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = ( * insn_data [ d -> icode ] . genfun ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op


<s> machine_mode move_mode ; int piece_size , i ; piece_size = <NUM_LIT> << floor_log2 ( size_to_move ) ; while ( ! int_mode_for_size ( piece_size * BITS_PER_UNIT , <NUM_LIT> ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { gcc_assert ( piece_size > <NUM_LIT> ) ; piece_size >>= <NUM_LIT> ; } if ( GET_MODE_SIZE ( move_mode ) > GET_MODE_SIZE ( word_mode ) ) { int nunits = GET_MODE_SIZE ( move_mode ) / GET_MODE_SIZE ( word_mode ) ; if ( ! mode_for_vector ( word_mode , nunits ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { move_mode = word_mode ; piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; } } gcc_assert ( code != CODE_FOR_nothing ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , <NUM_LIT> ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , <NUM_LIT> ) ; gcc_assert ( size_to_move % piece_size == <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < size_to_move


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && GRRegClassContains ( SrcReg


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; switch ( TM . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol (


<s> char * curr_range_str , * next_range_str ; int i = <NUM_LIT> , n = <NUM_LIT> ; if ( is_memset ) default_algs = & ix86_cost -> memset [ TARGET_64BIT != <NUM_LIT> ] ; else default_algs = & ix86_cost -> memcpy [ TARGET_64BIT != <NUM_LIT> ] ; curr_range_str = strategy_str ; do { int maxs ; char alg_name [ <NUM_LIT> ] ; char align [ <NUM_LIT> ] ; next_range_str = strchr ( curr_range_str , ',' ) ; if ( next_range_str ) * next_range_str ++ = '\0' ; if ( <NUM_LIT> != sscanf ( curr_range_str , <STR_LIT> , alg_name , & maxs , align ) ) { error ( <STR_LIT> , curr_range_str , is_memset ? <STR_LIT> : <STR_LIT> ) ; return ; } if ( n > <NUM_LIT> && ( maxs < ( input_ranges [ n - <NUM_LIT> ] . max + <NUM_LIT> ) && maxs != - <NUM_LIT> ) ) { error ( <STR_LIT> , is_memset ? <STR_LIT> :


<s> return __builtin_mve_vmulltq_int_uv4si ( __a ,


<s> bool ViableForN [ <NUM_LIT> ] = { true , true , true } ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; bool IsAnyViable = false ; for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) { uint64_t N = j + <NUM_LIT> ; if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t ) i << N ) & ModMask ) )


<s> const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E -> getSymbol ( ) ; CalleeFn = M -> getFunction ( CalleeName ) ; if ( ! CalleeFn && isFP128ABICall ( CalleeName ) ) return <NUM_LIT> ; } if ( ! CalleeFn )


<s> bool <ISA_LIT>BlockPlacement :: processPostOrderLoops ( MachineLoop * ML ) { bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ; return Changed | fixBackwardsWLS ( ML


<s> AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base_Reg = N


<s> SDLoc dl ( Op ) ; assert ( MaskVT . isSimple ( ) && <STR_LIT> ) ; if ( isAllOnes ( Mask ) ) return Op ; SDValue VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getNode ( <STR_LIT> , dl , BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case


<s> std :: vector < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) ,


<s> return ( type == TYPE_TEST || type == TYPE_ICMP || type == TYPE_FCMP || GET_CODE ( PATTERN ( insn ) ) ==


<s> } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt =


<s> return ( SVT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256

( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) ) ;


<s> void addRegVRRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } const MCSymbol * Symbol ; unsigned Offset = <NUM_LIT> ; switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Mang . getSymbol ( MO . getGlobal ( ) ) ; Offset = MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset = MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> inline int getFP32Imm ( const APFloat &