<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA


<s> const MCPhysReg ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal , dl ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , dl , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , dl , SrcVT ) ) , DAG . getConstant ( BytesLeft , dl , SizeVT ) , Align , isVolatile , AlwaysInline , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } int LoMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int * MaskPtr = LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; MaskPtr [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; MaskPtr [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; int MaskOps [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Locs [ i ] . first != - <NUM_LIT> ) MaskOps [ i ] = Locs [ i ] . first * <NUM_LIT> +


<s> std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Op , DAG ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FVal , TVal , CCVal , Overflow ) ; SDVTList VTs = DAG . getVTList ( Op


<s> inline vector signed int vec_cmplt ( vector float a1 , vector float a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float ) a1 ,


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> inline vector unsigned short vec_vmrghh ( vector unsigned short a1 , vector unsigned


<s> auto MBBStart = MBB -> instr_rend ( ) ; for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op . isDef ( ) ) ) return & * MI ; return nullptr


<s> inline vector float vec_abs ( vector float a1 ) { return __builtin_altivec_abs_v4sf ( a1


<s> const RegisterBank & RBFPR = getRegBank ( <STR_LIT> ) ; ( void ) RBFPR ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBCCR = getRegBank ( <STR_LIT> ) ; ( void ) RBCCR ; assert ( RBCCR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBCCR . getSize ( ) == <NUM_LIT> &&


<s> uint8_t BitA = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitB = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitC = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitD = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitE = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitF = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT>


<s> static SDValue canonicalizeBitSelect ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; bool UseVPTERNLOG = ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) || Subtarget . hasVLX ( ) ; if ( ! ( Subtarget . hasXOP ( ) || UseVPTERNLOG || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ; APInt UndefElts0 ,


<s> RegisterAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterAsmParser < <ISA_LIT>AsmParser > Y ( TheThumbTarget ) ; LLVMInitialize<ISA_LIT>AsmLexer (


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg


<s> unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> if ( MBB -> begin ( ) -> getOpcode ( ) == <STR_LIT> ) { unsigned OldOffset = BBOffsets [ i ] - delta ; if ( ( OldOffset % <NUM_LIT> ) == <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta += <NUM_LIT> ; } else if ( ( OldOffset % <NUM_LIT> ) != <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } } MachineInstr * ThumbJTMI = prior ( MBB -> end ( ) ) ; if ( ThumbJTMI -> getOpcode ( ) == <STR_LIT> ) { unsigned NewMIOffset = GetOffsetOf ( ThumbJTMI ) ; unsigned OldMIOffset = NewMIOffset - delta ; if ( ( OldMIOffset % <NUM_LIT> ) == <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } else if ( ( OldMIOffset % <NUM_LIT> ) != <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta +=


<s> return <ISA_LIT>16SPAliasReg = MF . getRegInfo ( ) . createVirtualRegister


<s> if ( Enabled == ReciprocalEstimate :: Enabled ) if ( SDValue Estimate = getEstimate ( Subtarget , <STR_LIT> , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > <NUM_LIT>


<s> if ( SCS ) report_fatal_error ( <STR_LIT> ) ; return getDarwinCallPreservedMask ( MF , CC ) ; } if ( CC == CallingConv :: <ISA_LIT>_VectorCall ) return SCS ? CSR_<ISA_LIT>_AAVPCS_SCS_RegMask : CSR_<ISA_LIT>_AAVPCS_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return SCS ? CSR_<ISA_LIT>_SVE_AAPCS_SCS_RegMask : CSR_<ISA_LIT>_SVE_AAPCS_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_<ISA_LIT>_CFGuard_Check_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return


<s> float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y )


<s> } else { NumLanes = <NUM_LIT> ; NumOf256BitLanes = <NUM_LIT> ; } unsigned NumEltsInStride = NumElts / NumOf256BitLanes ; unsigned NumLaneElts = NumEltsInStride / NumLanes ; for ( unsigned l256 = <NUM_LIT> ; l256 < NumOf256BitLanes ; l256 += <NUM_LIT> ) { for ( unsigned l = <NUM_LIT> ; l != NumEltsInStride ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l256 * NumEltsInStride + l + i ] ; int BitI1 = Mask [ l256 * NumEltsInStride + l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j + l256 * NumElts ) ) return false ; if ( V2IsSplat && ! isUndefOrEqual ( BitI1 ,


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , Is64Bit , IsLittleEndian


<s> return ( __m512 ) __builtin_ia32_movaps512_mask ( ( __v16sf ) __A , (


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const


<s> void Emitter < CodeEmitter > :: emitRegModRMByte ( unsigned ModRMReg


<s> bool matchAsmImpl ( StringRef s , ArrayRef < const StringRef * > args ) { s = s . substr ( s . find_first_not_of ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = args . size ( ) ; i != e ; ++ i ) { StringRef piece ( * args [ i ] ) ; if ( ! s . startswith ( piece ) ) return false ; s = s . substr ( piece . size ( ) ) ; StringRef :: size_type pos = s . find_first_not_of ( <STR_LIT> ) ; if ( pos == <NUM_LIT> ) return false ; s = s . substr (


<s> bool isBDAddr32Disp12 ( ) const { return isMemDisp12 ( ADDR32Reg , false


<s> if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems <= <NUM_LIT> ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op


<s> case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { Register MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT>


<s> op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const

MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { OS << ( char ) ( Bits >> <NUM_LIT> ) ; Bits <<= <NUM_LIT> ; } unsigned tlsOpNo = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( op == <NUM_LIT> && <STR_LIT> ) ; ( void


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( Subtarget -> useMovt ( ) ) ++ NumMovwMovt ; unsigned Wrapper = isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result


<s> if ( TARGET_IWMMXT_ABI && ! TARGET_IWMMXT ) error ( <STR_LIT> ) ; if ( TARGET_INTERWORK && ! TARGET_BPABI && ! bitmap_bit_p ( arm_active_target . isa , isa_bit_thumb ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; target_flags &= ~ MASK_INTERWORK ; } if ( TARGET_SOFT_FLOAT ) arm_fpu_attr = FPU_NONE ; else arm_fpu_attr = FPU_VFP ; if ( TARGET_AAPCS_BASED ) { if ( TARGET_CALLER_INTERWORKING ) error ( <STR_LIT> ) ; else if ( TARGET_CALLEE_INTERWORKING ) error ( <STR_LIT> ) ; } if ( ! arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE ) sorry ( <STR_LIT> ) ; if ( use_cmse && ! arm_arch_cmse ) error ( <STR_LIT> ) ; if ( use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM ) error ( <STR_LIT> ) ; if ( TARGET_AAPCS_BASED


<s> static SDValue getOnesVector ( MVT VT , bool HasInt256 , SelectionDAG & DAG , SDLoc dl ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( ~ <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Vec ; if ( VT . is256BitVector ( ) ) { if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else


<s> enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return <NUM_LIT> ; if ( code == GE || code == GT


<s> return Opc == <STR_LIT> || isT2i32Store


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MO . clobbersPhysReg ( reg


<s> if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsFP ) ) { validDomains = <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ; validDomains = <NUM_LIT> ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = <NUM_LIT> ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512

( opcode , domain , ReplaceableInstrsAVX512DQ ) ) {


<s> static SDValue lowerShuffleWithUNPCK256 ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createSplat2ShuffleMask ( VT , Unpckl , true ) ; createSplat2ShuffleMask ( VT , Unpckh , false ) ; unsigned UnpackOpcode ; if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) UnpackOpcode


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumBits = VT . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( Subtarget -> isTargetILP32 ( ) && Ty ->


<s> int64_t PrevReg = FirstReg ; unsigned Count = <NUM_LIT> ; if ( parseOptionalToken ( AsmToken :: Minus ) ) { SMLoc Loc = getLoc ( ) ; StringRef NextKind ; unsigned Reg ; ParseRes = ParseVector ( Reg , NextKind , getLoc ( ) , true ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( Kind != NextKind ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned Space = ( PrevReg < Reg ) ? ( Reg - PrevReg ) : ( Reg + <NUM_LIT> - PrevReg ) ; if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += Space ; } else { while ( parseOptionalToken ( AsmToken :: Comma ) ) { SMLoc Loc = getLoc ( ) ; StringRef NextKind ; unsigned Reg ; ParseRes = ParseVector ( Reg , NextKind , getLoc ( ) , true ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( Kind != NextKind ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( )

-> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) {


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext &


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case


<s> -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! I -> isBranch ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( I -> getOpcode ( ) ) ; assert ( BranchCond . size ( ) == <NUM_LIT> ) ; if ( CC != BranchCond [ <NUM_LIT> ] . getImm ( ) ) continue ; break ; } unsigned Opc = TailCall . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opc ) ) ; MIB -> addOperand ( TailCall . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB -> addOperand ( BranchCond [ <NUM_LIT> ] ) ; MIB . copyImplicitOps ( TailCall ) ; LivePhysRegs LiveRegs ( getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MIB , Clobbers ) ; for ( const auto & C : Clobbers ) { MIB . addReg ( C . first , RegState


<s> NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumResultVecs + <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; for ( unsigned i = AddrOpIdx + <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemIntrinsicSDNode * MemInt = cast < MemIntrinsicSDNode > ( N ) ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOpc , N -> getDebugLoc ( ) , SDTys , Ops . data ( ) , Ops . size ( ) , MemInt -> getMemoryVT ( ) , MemInt -> getMemOperand ( ) ) ; std :: vector < SDValue > NewResults ; for ( unsigned i = <NUM_LIT> ; i < NumResultVecs ; ++ i ) { NewResults . push_back ( SDValue ( UpdN . getNode ( )


<s> bool isVectorIndex1 ( ) const { return Kind == k_VectorIndex && VectorIndex . Val


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable (


<s> assert ( KnownUndef . getBitWidth ( ) == NumElts && KnownZero . getBitWidth ( ) == NumElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts


<s> return DAG . getNode ( <STR_LIT> , dl , getFullRegisterType ( VT ) , Op


<s> MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDefaultPred ( MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; } break ; case <STR_LIT> : { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: Define , TRI ) ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> case <STR_LIT> : lowerGETGOTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case <STR_LIT> : lowerGETFunPLTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case <STR_LIT> : lowerGETTLSAddrAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle


<s> const char * getPassName ( ) const override


<s> Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C

, false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> rtx x1 , x2 ; mips_emit_move_or_split ( mem , reg , SPLIT_IF_NECESSARY ) ; x1 = mips_frame_set ( mips_subword ( mem , false ) , mips_subword ( reg , false ) ) ; x2 = mips_frame_set ( mips_subword ( mem , true ) , mips_subword ( reg , true ) ) ; mips_set_frame_expr ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , x1 , x2 ) ) ) ; } else mips_emit_save_slot_move ( mem , reg , MIPS_PROLOGUE_TEMP ( GET_MODE


<s> return supportedVectorShiftWithImm ( VT , Subtarget


<s> MCWin64EHUnwindEmitter :: EmitUnwindInfo ( * this , getCurrentW64UnwindInfo


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; return Value >= MinValue &&


<s> assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; case <STR_LIT> : lowerABS ( N , Results , DAG ) ; return ; case <STR_LIT> : LowerLOAD ( N , Results ,


<s> SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>CC ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>CC = DAG . getConstant (


<s> bool <ISA_LIT>FastTileConfig :: isTileStore ( MachineInstr & MI ) { return MI . getOpcode


<s> static inline const MachineInstrBuilder & addLeaRegOffset ( const MachineInstrBuilder & MIB , unsigned Reg , bool isKill , int Offset ) { return addLeaOffset ( MIB . addReg ( Reg , getKillRegState (


<s> static void emitByte ( uint8_t C , raw_ostream & OS ) { OS << static_cast < char >


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i32scatter_pd ( void * addr ,

__m256i index , int scale , int hint ) {


<s> static unsigned GetAnalyzableBrOpc ( unsigned Opc ) { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> REAL_VALUE_TYPE r ; if ( TARGET_VFP ) fp_consts_inited = <NUM_LIT> ; else fp_consts_inited = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < fp_consts_inited


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int idx = Mask [ i ] ; if ( idx < <NUM_LIT> ) continue ; else if ( idx < ( int ) NumElems ) Mask [ i ] = idx + NumElems ; else Mask [ i ] =


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm


<s> const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> ME = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) ; return true ; } else { Val = ~ Val ; if ( isShiftedMask_64 ( Val ) ) { ME = countLeadingZeros ( Val ) - <NUM_LIT> ; MB = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) + <NUM_LIT> ; return


<s> if ( Subtarget . hasAVX ( ) ) return SDValue ( ) ; SDValue ULEOp1 = ChangeVSETULTtoVSETULE ( dl , Op1 , DAG ) ; if ( ! ULEOp1 ) return SDValue ( ) ; Op1 = ULEOp1 ; break ; } case <STR_LIT> : std :: swap ( Op0 , Op1 ) ; break ; case <STR_LIT> : break ; } SDValue Result = DAG . getNode ( <STR_LIT> , dl


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; RHSSwap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHSSwap ) ; SDValue LoProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; SDValue HiProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHSSwap , Zero , DAG , dl , <STR_LIT> ) ; HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ,


<s> assert ( Subtarget -> isTargetDarwin ( ) && Subtarget -> is64Bit ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , NULL ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue CosVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first


<s> ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = i * <NUM_LIT> + <NUM_LIT> ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = i / <NUM_LIT> + NumElts * ( i % <NUM_LIT> ) ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = ( NumElts + i ) / <NUM_LIT> + NumElts * ( i % <NUM_LIT> ) ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv ::


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement


<s> SelectionDAG & DAG = DCI . DAG ; if ( ! isS16 ( OpS16 , DAG ) && ! isSRA16 ( OpS16 ) ) { OpS16 = OpS32 ; OpS32 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } SDLoc dl ( OR ) ; unsigned Opcode = <NUM_LIT> ; if ( isS16 ( OpS16 , DAG ) ) Opcode = <STR_LIT> ; else if ( isSRA16 ( OpS16 ) ) { Opcode = <STR_LIT> ; OpS16 = OpS16 -> getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; SDValue Res = DAG . getNode ( Opcode , dl , <STR_LIT> , OpS32 , OpS16 ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( OR , <NUM_LIT> ) , Res ) ; return SDValue ( OR ,


<s> static const MCSymbol * GetLazyPtr ( const MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) - <NUM_LIT> ) ; TmpStr += <STR_LIT> ; return Ctx . GetOrCreateSymbol ( TmpStr . str ( )


<s> for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI ,


<s> if ( auto * Call = dyn_cast < CallInst > ( I ) ) { for ( unsigned i = <NUM_LIT> ; i < Call -> getNumArgOperands ( ) ; ++ i ) { Value * Arg = Call -> getArgOperand ( i ) ; TruncTysMap [ Call ] . push_back ( Arg -> getType ( ) ) ; } } else if ( auto * Switch = dyn_cast < SwitchInst > ( I ) ) TruncTysMap [ I ] . push_back ( Switch -> getCondition ( ) -> getType ( ) ) ; else { for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) TruncTysMap [ I ] . push_back ( I -> getOperand ( i ) -> getType ( ) ) ; } } for ( auto * V : Visited ) { if ( ! isa < TruncInst > ( V ) || Sources . count ( V ) ) continue ; auto * Trunc = cast < TruncInst > ( V ) ; TruncTysMap [ Trunc ] . push_back ( Trunc -> getDestTy ( ) ) ; } PrepareWrappingAdds ( ) ; ExtendSources (


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << ( int ) MI -> getOperand ( OpNo


<s> SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( DestVT . bitsGT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isImm ( )


<s> SDLoc DL ( N ) ; int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> PMapper ; bool IsValidSpecialReg ; Reg = PMapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) { assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> )


<s> } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask ,


<s> EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT>


<s> } Mask >>= <NUM_LIT> ; if ( ITMask [ i - <NUM_LIT> ] == 't' ) Mask |= <NUM_LIT> ; } Operands . push_back ( <ISA_LIT>Operand :: CreateITMask ( Mask , Loc ) ) ; } bool CanAcceptCarrySet , CanAcceptPredicationCode ; getMnemonicAcceptInfo ( Mnemonic , CanAcceptCarrySet , CanAcceptPredicationCode ) ; if ( ! CanAcceptCarrySet && CarrySetting ) { Parser . eatToEndOfStatement ( ) ; return Error ( NameLoc , <STR_LIT> + Mnemonic + <STR_LIT> ) ; } if ( ! CanAcceptPredicationCode && PredicationCode != <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return Error ( NameLoc , <STR_LIT> + Mnemonic + <STR_LIT> ) ; } if ( CanAcceptCarrySet ) { SMLoc Loc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Mnemonic . size ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCCOut ( CarrySetting ? <STR_LIT> : <NUM_LIT> , Loc ) ) ; } if ( CanAcceptPredicationCode ) { SMLoc Loc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Mnemonic . size ( ) + CarrySetting ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( <STR_LIT> ( PredicationCode ) , Loc ) ) ; } if ( ProcessorIMod ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( ProcessorIMod , getContext ( ) ) , NameLoc , NameLoc ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; StringRef ExtraToken = Name . slice ( Start , Next ) ; if ( isDataTypeToken ( ExtraToken ) && doesIgnoreDataTypeSuffix ( Mnemonic , ExtraToken ) ) continue ; if ( ExtraToken != <STR_LIT> ) { SMLoc Loc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Start ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExtraToken , Loc ) ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Mnemonic


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> assert ( Kind == k_MatrixRegister && <STR_LIT> ) ; return MatrixReg .


<s> SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b ,


<s> default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg ,


<s> case <STR_LIT> : return instCombineConvertFromSVBool ( IC , II ) ; case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> : return instCombineSVEDupX ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorFAdd ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorBinOp ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; case <STR_LIT> : return instCombineSVETupleGet ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEZip ( IC , II ) ; case <STR_LIT> : return instCombineLD1GatherIndex ( IC , II ) ; case <STR_LIT> : return instCombineST1ScatterIndex ( IC , II ) ; case <STR_LIT> : return instCombineSVELD1 ( IC ,


<s> bool SelectAddrIdxOnly ( SDValue N , SDValue &


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI -> CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; SDValue InArgsAddr = DAG . getFrameIndex ( FI , ValTy ) ; SDLoc DL ( Op


<s> uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ,


<s> if ( ExprLen ) InstInfo -> AsmRewrites -> emplace_back ( AOK_Skip , Loc , ExprLen ) ; return ; } } StringRef BaseRegStr ; StringRef IndexRegStr ; StringRef OffsetNameStr ; if ( SM . getBaseReg ( ) ) BaseRegStr = <ISA_LIT>IntelInstPrinter :: getRegisterName ( SM . getBaseReg ( ) ) ; if ( SM . getIndexReg ( ) ) IndexRegStr = <ISA_LIT>IntelInstPrinter :: getRegisterName ( SM . getIndexReg ( ) ) ; if ( SM . isOffsetOperator ( ) ) OffsetNameStr = SM .


<s> void <ISA_LIT>InstPrinter :: printAM3PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) O << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs ; O <<


<s> gcc_assert ( JUMP_P ( insn ) ) ; add_int_reg_note ( insn , REG_BR_PROB ,


<s> assemble_name_raw ( asm_out_file , end_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xops ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name_raw ( asm_out_file ,


<s> void <ISA_LIT>CodeEmitter :: emitNEON2RegInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec )

, DAG . getIntPtrConstant ( WordIdx , dl ) ) ;


<s> unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; if ( ! LHSReg || !


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Mask = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = dyn_cast < ConstantSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ; if ( ! SplatVal ) return false ; if ( SplatVal -> getZExtValue ( )


<s> if ( GET_CODE ( x ) == MINUS ) return symbol_mentioned_p ( XEXP ( x , <NUM_LIT> ) ) && label_mentioned_p ( XEXP ( x , <NUM_LIT> ) ) ; return FALSE


<s> do { Value >>= <NUM_LIT> ; Size += sizeof


<s> static inline ShiftOpc getAM2ShiftOpc ( unsigned


<s> MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || !


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPredicationCost ( const MachineInstr * MI ) const { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return <NUM_LIT> ; if ( MI -> isBundle (


<s> case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case


<s> return ( int64x2_t ) __builtin_neon_vld1v2di ( ( const __builtin_neon_di


<s> Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( VT . is128BitVector ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable (


<s> addPass ( new InstructionSelect ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>PostSelectOptimize (


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_SHORT ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_LONG ; if ( call_type == CALL_LONG && ( flag_pic || ! TREE_ASM_WRITTEN ( decl ) ) ) return false ; if ( TARGET_INTERWORK && TREE_PUBLIC ( decl ) &&

! TREE_ASM_WRITTEN ( decl ) ) return false ;


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false


<s> case <NUM_LIT> : OS << StringRef ( getRegisterName ( regInfo -> getSubReg ( reg , <STR_LIT> ) ) ) . lower ( ) ; break ; case <NUM_LIT> : OS << StringRef ( getRegisterName ( regInfo -> getSubReg ( reg , <STR_LIT> ) ) ) . lower ( ) ; break ; case <NUM_LIT> : OS << StringRef ( getRegisterName ( regInfo -> getSubReg ( reg , <STR_LIT> ) ) ) . lower ( ) ; break ; } } else if ( <STR_LIT> . contains ( reg ) ) { switch ( N


<s> case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op ,


<s> static bool ix86_macro_fusion_p ( ) { return TARGET_FUSE_CMP_AND_BRANCH


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; SDLoc DL (


<s> return ( ( vec_int4 ) ( si_orx ( ( qword


<STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info


<s> <STR_LIT> ) : ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , JITInfo ( ) { initAsmInfo (


<s> Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) ->


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; Value * Op1 = I -> getOperand ( <NUM_LIT> ) ; if ( IsExtendingLoad < SExtInst , <NUM_LIT> > ( Op0 ) && IsExtendingLoad < SExtInst , <NUM_LIT> > ( Op1 ) ) { ValueList LHS = { cast < SExtInst > ( Op0 ) -> getOperand ( <NUM_LIT> ) , Op0 } ; ValueList RHS = { cast < SExtInst > ( Op1 ) -> getOperand ( <NUM_LIT> ) , Op1 } ; Candidates . push_back ( make_unique < BinOpChain > ( I , LHS , RHS ) ) ; } return false ; } case Instruction :: SExt : return Match ( I -> getOperand ( <NUM_LIT> ) ) ; } return false ; } ; while ( Match ( Acc


<s> bool hasMessageSecurityAssist4 ( ) const { return HasMessageSecurityAssist4


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool Is64Bit


<s> SDValue Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL ,


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> static bool is64bitCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode ==


<s> bool <ISA_LIT>CallFrameOptimization :: isProfitable ( MachineFunction & MF , ContextVector & CallSeqVector ) { bool CannotReserveFrame = MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; if ( CannotReserveFrame ) return true ; if ( ! MF . getFunction ( ) -> optForSize ( ) ) return false ; unsigned StackAlign = TFL -> getStackAlignment ( ) ; int64_t Advantage = <NUM_LIT> ; for ( auto CC : CallSeqVector ) { if ( CC . NoStackParams ) continue ; if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . ExpectedDist %


<s> static void aarch64_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( pcum -> pcs_variant == ARM_PCS_AAPCS64 || pcum -> pcs_variant == ARM_PCS_SIMD || pcum -> pcs_variant == ARM_PCS_SVE ) { aarch64_layout_arg ( pcum_v , arg ) ; gcc_assert ( ( pcum -> aapcs_reg != NULL_RTX ) != ( pcum -> aapcs_stack_words != <NUM_LIT> ) ) ; pcum -> aapcs_arg_processed = false


<s> assert ( ( VT . getSizeInBits ( ) == <NUM_LIT> || VT . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && VT != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ; return


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF (

) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ;


<s> assert ( ( Kind == k_Immediate ) && <STR_LIT> ) ; return Imm .


) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> SDValue DemandedRHS = DAG . GetDemandedBits ( RHS , DemandedMask ) ; if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue ( N


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64Bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameInfo ( * this

, is64Bit ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> if ( dep_type != <NUM_LIT> ) return <NUM_LIT> ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < <NUM_LIT> || recog_memoized ( insn ) < <NUM_LIT> ) return cost ; insn_type = get_attr_type ( insn ) ; dep_insn_type = get_attr_type ( dep_insn ) ; switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : if ( insn_type == TYPE_LEA ) { rtx addr = PATTERN ( insn ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == SET ) ; addr = SET_SRC ( addr ) ; if ( modified_in_p ( addr , dep_insn ) ) cost += <NUM_LIT> ; } else if ( ix86_agi_dependent ( dep_insn , insn ) ) cost += <NUM_LIT> ; if ( ix86_flags_dependent ( insn , dep_insn , insn_type ) ) cost = <NUM_LIT> ; if ( insn_type == TYPE_FMOV && get_attr_memory ( insn ) == MEMORY_STORE && ! ix86_agi_dependent ( dep_insn , insn ) ) cost += <NUM_LIT> ; break ; case PROCESSOR_PENTIUMPRO : if ( get_attr_fp_int_src ( dep_insn ) ) cost += <NUM_LIT> ; if ( insn_type == TYPE_FMOV && ( set = single_set ( dep_insn ) ) != NULL_RTX && ( set2 = single_set ( insn ) ) != NULL_RTX && rtx_equal_p ( SET_DEST ( set ) , SET_SRC ( set2 ) ) && MEM_P ( SET_DEST ( set2 ) ) ) cost += <NUM_LIT> ; memory = get_attr_memory ( insn ) ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && !

ix86_agi_dependent ( dep_insn , insn ) ) {


<s> std :: vector < Closure > Closures ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back (


<s> Error ( L , <STR_LIT> ) ; return false ; } SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( FPReg == - <NUM_LIT> ) { Error ( FPRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( SPReg == - <NUM_LIT> ) { Error ( SPRegLoc , <STR_LIT>


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState


<s> return CustomExpandInstNaCl<ISA_LIT> ( Inst , Out ,


<s> const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || (


<s> assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ; Chains . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getTargetLoweringInfo ( ) .


<s> return ( __m128i ) __builtin_ia32_vpcomtrued ( ( __v4si ) __A , (


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering ::

getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ;


<s> static DecodeStatus DecodeVecShiftL32Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftLImm ( Inst , Imm ,


<s> MachineFunction * MF = Filler -> getParent ( ) -> getParent ( ) ; for ( BB2BrMap :: const_iterator I = BrMap . begin ( ) ; I != BrMap . end ( ) ; ++ I ) { if ( I -> second ) { MIBundleBuilder ( I -> second ) . append ( MF -> CloneMachineInstr ( & * Filler ) ) ; ++ UsefulSlots ; } else { I -> first -> insert ( I -> first -> end ( ) , MF ->


<s> return __builtin_ia32_vcvtudq2ph512_mask_round ( ( __v16si ) __A , _mm256_setzero_ph ( ) , ( __mmask16


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA57

( ) ) && usingDefaultRegAlloc ( ) ) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ;


<s> return <NUM_LIT> - MI . getOperand ( Op )


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setReorder ( ) ; Parser . Lex ( )


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * ) const { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; bool isPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , dl , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset )


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList (


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>LETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>BETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbLETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbBETarget (


<s> MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; Symbol -> setSection ( * getCurrentSection ( ) ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start


<s> if ( width_source == SVE_SCALABLE ) return default_estimated_poly_value ( val ) ; HOST_WIDE_INT over_128 = width_source - <NUM_LIT> ; return val . coeffs [ <NUM_LIT> ] + val . coeffs [ <NUM_LIT> ]


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , DL ( computeDataLayout ( * getSubtargetImpl ( ) ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps =


<s> unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> switch ( vmode ) { case E_V8DFmode : case E_V16SFmode : case E_V4DFmode : case E_V8SFmode : case E_V2DFmode : case E_V4SFmode : case E_V8HImode : case E_V8SImode : case E_V32HImode : case E_V64QImode : case E_V16SImode : case E_V8DImode : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) mask |= ( d -> perm [ i ] >= nelt ) << i ; break ; case E_V2DImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << ( i * <NUM_LIT> ) ; vmode = V8HImode ; goto do_subreg ; case E_V4SImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << ( i * <NUM_LIT> ) ; vmode = V8HImode ; goto do_subreg ; case E_V16QImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) { use_pblendvb : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = ( d -> perm [ i ] < nelt ? const0_rtx : constm1_rtx ) ; finish_pblendvb : vperm = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) emit_insn ( gen_sse4_1_pblendvb ( target , op0 , op1 , vperm ) ) ; else emit_insn ( gen_avx2_pblendvb ( target , op0 , op1 , vperm ) ) ; if ( target != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8HImode ; do_subreg : target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , op0 ) ; op1 = gen_lowpart ( vmode , op1


<s> if ( ! selectAddr ( Node , Ptr , Base , Scale , Index , Disp , Segment ) ) return nullptr ; enum AtomicOpc Op ; switch ( Node -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val , Subtarget ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . SimpleTy ) { default : return nullptr ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ]


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { MachineLocation Location ; assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; } return Location


<s> const MachineOperand & Scale = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Disp = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) ; if ( Segment . getReg ( ) != <NUM_LIT> || ! Disp . isImm ( ) || Disp . getImm ( ) != <NUM_LIT> || Scale . getImm ( ) > <NUM_LIT> ) return false ; return true


<s> if ( VT . isVector ( ) ) EltVT = VT . getVectorElementType ( ) ; std :: vector < Constant * > CV ; if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back


<s> if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; if ( ! REG_P ( base_reg ) ) return false ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( ! SYMBOL_REF_P ( base ) || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; else { rtx const_vector = get_pool_constant ( base ) ; if ( SYMBOL_REF_P ( const_vector ) && CONSTANT_POOL_ADDRESS_P ( const_vector ) ) const_vector = get_pool_constant (


<s> - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( unsigned idx = <NUM_LIT> ; idx < array_lengthof ( SplatCsts ) ; ++ idx ) { int i = SplatCsts [ idx ] ; unsigned TypeShiftAmt = i & ( SplatBitSize - <NUM_LIT> ) ; if ( SextVal == ( i << ( int ) TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( unsigned ) i >> TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( unsigned ) i >> TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << TypeShiftAmt ) | ( ( unsigned ) i >> ( SplatBitSize - TypeShiftAmt ) ) ) ) { SDValue Res = BuildSplatI ( i , SplatSize ,


<s> bool isBarriernXS ( ) const { return Kind == k_Barrier && getBarriernXSModifier (


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getBuildVector ( <STR_LIT> , SDLoc ( N ) , { BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) } ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT>


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) :

AsmPrinter ( O , TM , Ctx , Streamer , T ) {


<s> unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod


<s> EVT PtrVT = getPointerTy ( ) ; SDValue Func , Chain ; Func = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getEntryNode ( ) , DescAddr ) ; SDValue Glue ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * A64RI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = A64RI -> getTLSDescCallPreservedMask ( ) ; std :: vector < SDValue


<s> SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && GRRegClassContains ( SrcReg ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; return <STR_LIT> ; } if ( GRRegClassContains ( DestReg ) &&


<s> static void registerAsmPrinter ( AsmPrinterCtorFn F


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; unsigned Val = RHS -> getZExtValue ( ) & ( BitSize - <NUM_LIT> ) ; unsigned ShVal = <STR_LIT> ( ShType ,


<s> } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode ,


<s> tmp1 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( eight ) ) ; tmp2 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( sixteen ) ) ; tmp3 = ( vec_uchar16 ) vec_sl ( ( vec_uint4 ) ( cnt ) , ( vec_uint4 ) ( twentyfour ) ) ; cnt = vec_add ( cnt , vec_and ( tmp1 , vec_cmpeq ( cnt , eight ) ) ) ; cnt = vec_add ( cnt , vec_and ( tmp2 , vec_cmpeq ( cnt , sixteen ) ) ) ; cnt = vec_add ( cnt , vec_and ( tmp3 , vec_cmpeq ( cnt , twentyfour


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant (


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_FPImmediate , S , E ) ; Op -> FPImm . Val = Val ; return


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegFixed


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym


<s> if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt )


<s> if ( MI . getOpcode ( ) == <STR_LIT> && findCMPToFoldIntoCBZ ( &

MI , & getRegisterInfo ( ) ) ) return <NUM_LIT> ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = <NUM_LIT> ; if ( Bytes . size (


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitTPRel32Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI ,


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ; if ( Narrow ) NV = NarrowVector ( NV , *


<s> LLVM_DEBUG ( { BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ;


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI


<s> const GlobalValue * GV = GA -> getGlobal ( ) ; if ( Subtarget -> isTargetELF ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTLSModel ( GV , getTargetMachine ( ) . getRelocationModel ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg ,

getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> BBProb = BB -> getBasicBlock ( ) -> getNOPInsertionPercentage ( ) ; if ( BBProb == multicompiler :: NOPInsertionUnknown ) BBProb = FnProb ; } if ( BBProb <= <NUM_LIT> ) continue ; for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { MachineBasicBlock :: iterator J = std :: next ( I ) ; if ( I -> isPseudo ( ) ) { I = J ; continue ; } unsigned int NumNOPs = MaxNOPsPerInstruction ; if ( NOPsInserted < EarlyNOPThreshold ) NumNOPs = RNG -> Random ( EarlyNOPMaxCount ) ; for ( unsigned int i = <NUM_LIT> ; i < NumNOPs ; i ++ ) { int Roll = RNG -> Random ( <NUM_LIT> ) ; if ( Roll >= BBProb ) continue ; int NOPCode = RNG -> Random ( MAX_NOPS ) ; MachineInstr * NewMI = NULL ; unsigned reg = nopRegs [ NOPCode


<s> break ; case FDSig : IAH . Out ( MI + <STR_LIT> ) ; if ( LE ) { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } else { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } break ; case DSig : if ( LE ) { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } else { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } break ; case DDSig : if ( LE ) { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } else { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; IAH . Out ( MI + <STR_LIT> ) ; } break ; case DFSig : if ( LE ) { IAH . Out ( MI + <STR_LIT> ) ; IAH . Out (


<s> if ( ( TARGET_THUMB || ! frame_pointer_needed ) && REGNO ( addr ) == SP_REGNUM ) return <NUM_LIT> ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && REGNO ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == REGNO ( addr ) && GET_CODE ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM && GET_CODE ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { value = INTVAL ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; } } if ( value == <NUM_LIT> ) { debug_rtx ( addr ) ; warning ( <NUM_LIT> , <STR_LIT> ) ; value = <NUM_LIT>