<s> return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( LastOpc != UncondBrOpc ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_CondUncond


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned LaneSize = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( NumElts != <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + l ] , Mask [ i ] + l


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc dl = MBB . findDebugLoc ( MI ) ; MachineBasicBlock * BB = & MBB ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * syscallMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ( BB -> getIterator ( ) ) ; MF . insert ( It , syscallMBB ) ; MF . insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( syscallMBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB =


<s> int Sign = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand


<s> static inline bool isImmLH ( uint64_t Val


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeUnscaled ( SDValue N , unsigned Size , SDValue & Base , SDValue & OffImm ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Log2_32 ( Size ) ) ) return false ; if ( RHSC >= - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex (


<s> unsigned <ISA_LIT>InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return <NUM_LIT> ; bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second


<s> if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , AP . OutContext ) , AP . OutContext ) ; Expr = <ISA_LIT>MCExpr :: create ( Kind , Expr , AP .


<s> unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; Type * ResultTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / Factor ) ; unsigned NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; unsigned NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; unsigned NumOfSources = Factor


<s> const unsigned Count = Chunk . second ; uint64_t Encoding = <NUM_LIT> ; if ( ( Count != <NUM_LIT> && Count != <NUM_LIT> ) || ! canUseOrr ( ChunkVal , Encoding ) ) continue ; const bool CountThree = Count == <NUM_LIT> ; Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> , ShiftAmt ) } ) ; if ( CountThree ) return true ; for ( ShiftAmt += <NUM_LIT> ; ShiftAmt <


<s> unsigned fc ; if ( scalar ) { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRwithZRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , predicate_decoder ( Inst , fc ,


<s> auto * ZII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; assert ( MBBI -> isReturn ( ) && <STR_LIT> ) ; uint64_t StackSize = MFFrame . getStackSize


<s> ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx ; } } return


<s> Kd ( Kind ) , Supported ( HasFeature ) , DepOpIdx ( Index ) , OpSet1 ( First ) , OpSet2 (


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT . isScalableVector ( ) ) return performSVEAndCombine ( N , DCI ) ; if ( ! ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ) return SDValue ( ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N ->

getOperand ( <NUM_LIT> ) . getNode ( ) ) ;


<s> <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement )


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N )


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream &


<s> int min ; fcomi_cost = ix86_fp_comparison_fcomi_cost ( code ) ; sahf_cost = ix86_fp_comparison_sahf_cost ( code ) ; min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost ( code


<s> rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr

) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) {


<s> tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype


<s> unsigned OrigAlignment = St -> getAlignment ( ) ; unsigned EltOffset = NumVecElts == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Alignment = std :: min ( OrigAlignment , EltOffset ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , SplatVal , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; unsigned Offset = EltOffset ; while ( -- NumVecElts ) { SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , Alignment ) ; Offset += EltOffset


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( ) ; unsigned SlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = <NUM_LIT> ; unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i - <NUM_LIT> ] . getRegClass ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( RegClass != & <STR_LIT> && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RegClass ) ; } } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return


<s> if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > (


<s> EHSecName += FnSecName ; } const MCSectionELF * EHSection = NULL ; if ( const MCSymbol * Group = FnSection . getGroup ( ) ) { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags | ELF :: SHF_GROUP , Kind , FnSection . getEntrySize ( ) ,


<s> MIB . add ( Count ) ; if ( ! IsDo ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; LoLoop . ToRemove . insert ( Start ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; return &


<s> if ( LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> ) return false ; if ( ! Load . hasOneUse ( ) ) return false ; if ( LoadNode -> getBasePtr ( ) != StoreNode -> getBasePtr ( ) || LoadNode -> getOffset ( ) != StoreNode -> getOffset ( ) ) return false ; SDValue Chain = StoreNode -> getChain ( ) ; bool ChainCheck = false ; if ( Chain == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; InputChain = LoadNode -> getChain ( ) ; } else if ( Chain . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> >


<s> static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( RHS ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; if ( ImmFns


<s> for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA -> getReachingLocalUses ( LoLoop . Dec , <STR_LIT> , Uses ) ; if ( Uses . size ( ) > <NUM_LIT> || ! Uses . count ( LoLoop . End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoLoop . Revert = true ; } LoLoop . CheckLegality ( BBUtils . get (


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; auto LoadVReg = buildLoad ( LLT :: scalar ( <NUM_LIT> ) , Addr , Size


<s> if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address


<s> if ( argc < <NUM_LIT> ) return NULL ; if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; kc = kstat_open ( ) ; if ( kc != NULL ) { ksp = kstat_lookup ( kc , CONST_CAST2 ( char * , const char * , <STR_LIT> ) , - <NUM_LIT> , NULL ) ; if ( ksp != NULL && kstat_read ( kc , ksp , NULL ) != - <NUM_LIT> && ksp -> ks_type == KSTAT_TYPE_NAMED ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , <STR_LIT> ) ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_STRING ) buf = KSTAT_NAMED_STR_PTR ( brand ) ; } kstat_close ( kc ) ; for ( i = <NUM_LIT> ; cpu_names [ i ] . name != NULL ; i ++ ) if ( strcmp ( buf , cpu_names [ i ] . name ) == <NUM_LIT> ) cpu = cpu_names [ i ] . cpu ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) return NULL ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( startswith ( buf , <STR_LIT> ) ) { for ( i = <NUM_LIT> ; cpu_names [ i ] . name ; i ++ ) if ( strstr ( buf , cpu_names [ i ] . name ) != NULL ) { cpu = cpu_names [ i ] . cpu ; break ; } break ; } fclose ( f


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _mm_clflush ( void const * __A ) { __builtin_ia32_clflush (


<s> case VECTOR_ALTIVEC : ret = <STR_LIT> ; break ; case VECTOR_VSX : ret = <STR_LIT> ; break ; case VECTOR_P8_VECTOR : ret = <STR_LIT> ; break ; default : ret = <STR_LIT>


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( Ref -> getKind ( ) == MCSymbolRefExpr :: VK_SECREL ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2 ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_1 ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create


<s> if ( MF -> getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { EmitNop ( Ctx , * OutStreamer , <NUM_LIT> , getSubtargetInfo ( ) ) ; return ; } MCSymbol * fentry = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; const MCSymbolRefExpr * Op = MCSymbolRefExpr :: create ( fentry , MCSymbolRefExpr :: VK_PLT , Ctx ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr


<s> rtx addend = NULL_RTX ; rtx reg_addend = NULL_RTX ; rtx const_addend = NULL_RTX ; rtx result = NULL_RTX ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) { if ( base_term_p && MEM_P ( orig_x ) ) return orig_x ; rtx x2 = XVECEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , x2 ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOTPCREL || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) && ( MEM_P ( orig_x ) || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) ) { x = XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_MODE ( orig_x ) != GET_MODE ( x ) && MEM_P ( orig_x ) ) { x = lowpart_subreg ( GET_MODE ( orig_x ) , x , GET_MODE ( x ) ) ; if ( x == NULL_RTX ) return orig_x ; } return


<s> std :: map < unsigned , Chain * > ActiveChains ; std :: vector < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I !=


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT>


<s> initGlobalBaseReg ( MF ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF . end ( ) ; MFI


<s> unsigned CommOpIdx1 = <NUM_LIT> ; unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { Register Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg


<s> if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( Op . type == TYPE_IMM3 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( Op . type == TYPE_IMM5 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( Op . type == TYPE_XMM128 || Op . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; else { if ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P


<s> emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT>


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! TokE . getString ( ) . equals_lower ( <STR_LIT> ) || Parser . getLexer ( ) . peekTok ( ) . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; int Val = MCE -> getValue ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , SS , getLoc ( ) , getContext (


<s> bool hasSHA2 ( ) const { return HasSHA2


<s> imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg (


<s> return ( __m128 ) __builtin_ia32_mulss ( ( __v4sf ) __A ,


<s> new GOTPLTEntry ( <NUM_LIT> , m_SectionData ) ; new GOTPLTEntry ( <NUM_LIT> , m_SectionData


<s> if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ) ; return d


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FrameIdx ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; }


<s> default : break ; case Match_Success : ProcessInstruction ( Inst , Operands ) ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( )


<s> static int mep_address_cost ( rtx addr ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED


<s> <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT>


<s> SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult =


<s> __builtin_ia32_pmovsdb128mem_mask ( ( unsigned int * ) __P , ( __v4si ) __A


<s> rtx addr = XEXP ( mem , <NUM_LIT> ) ; rtx element_offset ; rtx new_addr ; bool valid_addr_p ; gcc_assert ( GET_RTX_CLASS ( GET_CODE ( addr ) ) != RTX_AUTOINC ) ; if ( CONST_INT_P ( element ) ) element_offset = GEN_INT ( INTVAL ( element ) * scalar_size ) ; else { int byte_shift = exact_log2 ( scalar_size ) ; gcc_assert ( byte_shift >= <NUM_LIT> ) ; if ( byte_shift == <NUM_LIT> ) element_offset = element ; else { if ( TARGET_POWERPC64 ) emit_insn ( gen_ashldi3 ( base_tmp , element , GEN_INT ( byte_shift ) ) ) ; else emit_insn ( gen_ashlsi3 ( base_tmp , element , GEN_INT ( byte_shift ) ) ) ; element_offset = base_tmp ; } } if ( element_offset == const0_rtx ) new_addr = addr ; else if ( REG_P ( addr ) || SUBREG_P ( addr ) ) new_addr = gen_rtx_PLUS ( Pmode , addr , element_offset ) ; else if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) ; rtx op1 = XEXP ( addr , <NUM_LIT> ) ; rtx insn ; gcc_assert ( REG_P ( op0 ) || SUBREG_P ( op0 ) ) ; if ( CONST_INT_P ( op1 ) && CONST_INT_P ( element_offset ) ) { HOST_WIDE_INT offset = INTVAL ( op1 ) + INTVAL ( element_offset ) ; rtx offset_rtx = GEN_INT ( offset ) ; if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && ( scalar_size < <NUM_LIT> || ( offset & <NUM_LIT> ) == <NUM_LIT> ) ) new_addr = gen_rtx_PLUS ( Pmode , op0 , offset_rtx ) ; else { emit_move_insn ( base_tmp , offset_rtx ) ; new_addr = gen_rtx_PLUS ( Pmode , op0 , base_tmp ) ; } } else { bool op1_reg_p = ( REG_P ( op1 ) || SUBREG_P ( op1 ) ) ; bool ele_reg_p = ( REG_P ( element_offset ) || SUBREG_P ( element_offset ) ) ; if ( op1_reg_p && ( ele_reg_p || reg_or_subregno ( op1 ) != FIRST_GPR_REGNO ) ) { insn = gen_add3_insn ( base_tmp , op1 , element_offset ) ; gcc_assert ( insn != NULL_RTX ) ; emit_insn ( insn ) ; } else if ( ele_reg_p && reg_or_subregno ( element_offset ) != FIRST_GPR_REGNO ) { insn = gen_add3_insn ( base_tmp , element_offset , op1 ) ; gcc_assert ( insn != NULL_RTX ) ; emit_insn ( insn ) ; } else { emit_move_insn ( base_tmp , op1 ) ; emit_insn ( gen_add2_insn ( base_tmp , element_offset ) ) ; } new_addr = gen_rtx_PLUS ( Pmode , op0 , base_tmp ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } if ( GET_CODE ( new_addr ) == PLUS ) { rtx op1 = XEXP ( new_addr , <NUM_LIT>


<s> } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { emit_insn ( gen_load_toc_v4_pic_si ( ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_insn ( gen_load_toc_v4_PIC_1 ( symF ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest


<s> if ( mode != MAX_MACHINE_MODE && MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ; return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ? <NUM_LIT>


<s> assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } unsigned RetOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; AddOptionalDefs ( MIB ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ; return true


<s> if ( alignment == <NUM_LIT> || ( sizeof ( void * ) == <NUM_LIT> && alignment == <NUM_LIT> ) ) alignment = sizeof ( void * ) ; if ( posix_memalign ( & ptr , alignment , size ) == <NUM_LIT> )


<s> for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> mayStore ( ) )


<s> return __builtin_aarch64_floatunsv2siv2sf ( (


<s> RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( The<ISA_LIT>V9Target ) ; RegisterAsmInfo < <ISA_LIT>ELFMCAsmInfo > A ( The<ISA_LIT>Target


<s> const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1


<s> NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , NumElts ) ; Index = ExtendToType ( N -> getIndex ( ) , NewIndexVT , DAG ) ; if ( IndexVT . getScalarType ( ) == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; assert ( MaskVT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , NumElts ) ; Mask = ExtendToType ( N -> getMask ( ) , ExtMaskVT , DAG , true ) ; MVT NewVT = <STR_LIT> ( VT . getScalarType ( ) , NumElts ) ; Src = ExtendToType ( Src , NewVT , DAG ) ; } } MVT BitMaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; Mask = DAG . getNode ( <STR_LIT> , dl , BitMaskVT , Mask ) ; SDVTList VTs = DAG . getVTList ( BitMaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index } ; NewScatter = DAG . getMaskedScatter ( VTs , N -> getMemoryVT ( ) , dl , Ops , N -> getMemOperand


<s> bool HasRA = MFI -> adjustsStack ( ) || IsPIC ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = HasRA ? - <NUM_LIT> : - <NUM_LIT> ; int RAOffset = - <NUM_LIT> ; int BPOffset = FPOffset - <NUM_LIT> ; int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) ; } else if ( isInt < <NUM_LIT> > ( StackSize ) ) { if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> } else stmt_cost = ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op , true ) ; break ; case MULT_EXPR : case WIDEN_MULT_EXPR : case MULT_HIGHPART_EXPR : stmt_cost = ix86_multiplication_cost ( ix86_cost , mode ) ; break ; case FMA_EXPR : stmt_cost = ix86_vec_cost ( mode , mode == SFmode ? ix86_cost -> fmass : ix86_cost -> fmasd , true ) ; break ; case NEGATE_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( X87_FLOAT_MODE_P ( mode ) ) stmt_cost = ix86_cost -> fchs ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; else stmt_cost = ix86_cost -> add ; break ; case TRUNC_DIV_EXPR : case CEIL_DIV_EXPR : case FLOOR_DIV_EXPR : case ROUND_DIV_EXPR : case TRUNC_MOD_EXPR : case CEIL_MOD_EXPR : case FLOOR_MOD_EXPR : case RDIV_EXPR : case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } if ( kind == vec_construct && stmt_info && STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost *= TYPE_VECTOR_SUBPARTS ( vectype ) ; } if ( stmt_cost == - <NUM_LIT> ) stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype ,


<s> if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg


<s> static bool mips_matching_cpu_name_p ( const char * canonical , const char * given ) { if ( mips_strict_matching_cpu_name_p ( canonical , given ) ) return true ; if ( TOLOWER ( * given ) == 'r' ) given ++ ; if ( ! ISDIGIT ( * given ) ) return false ; if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'v' && TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' ) canonical += <NUM_LIT> ; else if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' && TOLOWER ( canonical [ <NUM_LIT> ] ) == 'm'


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) && shouldUseHorizontalOp ( true , DAG , Subtarget ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Op = SDValue ( DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT>

) , Op , DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , Mask ) ; IsUnary = IsFakeUnary = N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; IsUnary = IsFakeUnary = N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePALIGNRMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : { IsUnary = true ; SDValue MaskNode = N -> getOperand ( <NUM_LIT> ) ; while ( MaskNode -> getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode -> getOperand ( <NUM_LIT> ) ; if ( MaskNode -> getOpcode ( ) == <STR_LIT> ) { EVT VT = MaskNode . getValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( ! VT . isInteger ( ) ) return false ; int NumBytesPerElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; for ( int i = <NUM_LIT> , e = MaskNode -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue Op = MaskNode -> getOperand ( i ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { RawMask . push_back ( ( uint64_t


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> >

( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> SDLoc DL ( Mask ) ; EVT InVT = Mask . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , InVT ) ; auto Op1 = convertToScalableVector ( DAG , ContainerVT , Mask ) ; auto Op2 = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; auto Pg = getPredicateForFixedLengthVector ( DAG ,


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = Subtarget . is<ISA_LIT>64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( get<ISA_LIT>RegisterNumbering ( SrcReg ) * <NUM_LIT>

) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> ; } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr . getOperand ( <NUM_LIT> )


<s> SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , getPointerTy ( ) , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode (

<STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ;


<s> if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; int RegNo = op -> getReg ( )


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder

) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> bool useMachineOutliner ( ) const override { return


<s> Register Tmp2 = MRI . createVirtualRegister ( RC ) ; Register Tmp3 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp1 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addExternalSymbol ( Symbol . data ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_LO32 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp1 , getKillRegState ( true ) ) . addImm ( M0 ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp3 ) . addReg ( <STR_LIT> ) . addReg ( Tmp2 , getKillRegState ( true ) ) . addExternalSymbol ( Symbol . data ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI32 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Result ) . addReg ( Tmp3 , getKillRegState ( true ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } } else { Register Tmp1 = MRI . createVirtualRegister ( RC ) ; Register Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp1 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT>

) . addExternalSymbol ( Symbol . data ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO32 ) ;


<s> const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Next = I -> getNextNode (


<s> if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) return ! reg_overlap_mentioned_p ( value , early_op ) ; return


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>32Target ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( The<ISA_LIT>64Target ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; ( void )


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false ,


<s> selectVSplatUimm3 ( SDValue N , SDValue & Imm


<s> switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch (


<s> void ExpandPseudo :: expandLoadACC ( MachineBasicBlock & MBB , Iter I , unsigned RegSize ) { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Lo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; const MCInstrDesc & Desc = TII . get


<s> if ( T != <NUM_LIT> ) V = V | T ; T = getListValue ( regList . List3From , regList . List3To ) ; if ( T != <NUM_LIT> ) V = V | T ; T = getListValue ( regList . List4From , regList .


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && SelectMsub ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue (


<s> return ( __m512d ) _mm512_insertf32x4 ( _mm512_setzero_ps ( )


<s> MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps -

<NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return <NUM_LIT> ; } unsigned RotAmt = CountLeadingZeros_32 ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned NewOpc = Opcode ; if ( AddrMode == <STR_LIT> ) { unsigned OffsetReg = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getReg ( ) ; if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else { assert ( AddrMode == <STR_LIT> ) ; int InstrOffs = <STR_LIT> ( MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm (


<s> break ; } case <STR_LIT> : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned e = ( isTwoAddr ? <STR_LIT> + <NUM_LIT> : <STR_LIT> ) ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; if ( NumOps > e && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( e ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; for ( ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } default : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT>


<s> if ( WriteBack ) { if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> MachineInstr * SetRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( is64Bit ? & <STR_LIT> : & <STR_LIT> ) ; MachineInstr * Next = I -> getNextNode ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode ::

COPY ) , * TLSBaseAddrReg ) . addReg ( is64Bit ? <STR_LIT> : <STR_LIT> ) ;


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry ( )


<s> case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } if ( kind == vec_construct && stmt_info && STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype ,


<s> static bool getLaneCopyOpcode ( unsigned & CopyOpc , unsigned & ExtractSubReg , const unsigned EltSize ) { switch ( EltSize ) { case <NUM_LIT> : CopyOpc = <STR_LIT> ; ExtractSubReg = <STR_LIT> ; break ; case <NUM_LIT> : CopyOpc =


<s> if ( ! isa < ConstantSDNode > ( Lane ) ) return SDValue ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Vec . getValueType ( ) ; if ( ST -> hasMVEIntegerOps ( ) && VT . getScalarSizeInBits ( ) == <NUM_LIT> ) return LowerEXTRACT_VECTOR_ELT_i1 ( Op , DAG , ST ) ; if ( Op . getValueType ( ) == <STR_LIT> && Vec . getScalarValueSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; } return Op


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . i [ ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v


<s> O << <STR_LIT> << emitCurrentABIString ( ) << '\n' ; if ( Subtarget -> isABI_EABI ( ) ) O << <STR_LIT> << ( Subtarget -> isGP32bit ( ) ? <STR_LIT> : <STR_LIT>


<s> bool <ISA_LIT>DCInstruction :: translateImplicit ( unsigned RegNo ) { assert ( RegNo == <STR_LIT> ) ; Value * Def = getLastDef ( ) ; assert ( Def && <STR_LIT> ) ; getParent ( ) . updateEFLAGS ( Def ) ; return


<s> int Offset = Addr . Offset ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { int Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand ( MMO ) ; } else { MIB . addReg ( Addr . Base . Reg ) ; if (


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) return getAddrNonPIC


<s> static DecodeStatus decodeU12ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> >


<s> void OptimizeLEAPass :: findLEAs ( const MachineBasicBlock & MBB , MemOpMap & LEAs ) { unsigned Pos = <NUM_LIT> ; for ( auto & MI : MBB ) { InstrPos [ & MI ] = Pos += <NUM_LIT> ; if ( isLEA ( MI ) ) LEAs [ getMemOpKey ( MI , <NUM_LIT> )

] . push_back ( const_cast < MachineInstr * > ( & MI ) ) ;


<s> unsigned InsertReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & InsMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: INSERT_SUBREG ) , InsertReg ) . addUse ( ImpDefReg ) . addUse ( SrcReg ) . addImm ( <STR_LIT> ) ; constrainSelectedInstRegOperands ( ImpDefMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( InsMI , TII , TRI , RBI ) ; InsertRegs . push_back ( InsertReg ) ; } } unsigned CopyTo = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FirstCopy = MIB . buildInstr ( TargetOpcode :: COPY , { CopyTo } , { } ) . addReg ( InsertRegs [ <NUM_LIT> ] , <NUM_LIT> , ExtractSubReg ) ; constrainSelectedInstRegOperands ( * FirstCopy , TII , TRI , RBI ) ; unsigned LaneIdx = <NUM_LIT> ; for ( unsigned InsReg : InsertRegs ) { unsigned CopyTo = I . getOperand ( LaneIdx ) . getReg ( ) ; MachineInstr & CopyInst = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( CopyOpc ) , CopyTo ) . addUse ( InsReg ) . addImm ( LaneIdx ) ; constrainSelectedInstRegOperands ( CopyInst , TII , TRI , RBI ) ; ++ LaneIdx ; } const TargetRegisterClass * RC = MRI . getRegClassOrNull ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! RC )


<s> if ( MI -> isCall ( ) || MI -> mayStore ( ) ) return Exit ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( ! RegInfo . isPhysicalRegister ( Reg ) ) continue ; if ( RegInfo . regsOverlap ( Reg , RegInfo . getStackRegister ( )


<s> if ( mode == CCFPmode && ( ! flag_finite_math_only || code == UNLT || code == UNLE || code == UNGT || code == UNGE || code

== UNEQ || code == LTGT ) ) return reverse_condition_maybe_unordered ( code ) ;


<s> DEBUG ( BB -> dump ( ) ) ; if ( ! Fast ) PreprocessForRMW ( ) ; PreprocessForFPConvert ( ) ; DOUT << <STR_LIT> ; Indent = <NUM_LIT> ; SelectRoot ( * CurDAG ) ; DOUT << <STR_LIT>


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> << align


<s> return ( uint32x4_t ) __builtin_neon_vcgtuv4si ( ( int32x4_t ) __a ,


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize ) { case <NUM_LIT> : break ; case <NUM_LIT> : { MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; break ; } case <NUM_LIT> : EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitCallAsanReport ( Ctx , Out , AccessSize , IsWrite ) ; EmitLabel ( Out


<s> if ( Op == TargetOpcode :: G_INTRINSIC && isFPIntrinsic ( getIntrinsicID ( MI ) ) ) return true ; if ( isPreISelGenericFloatingPointOpcode ( Op ) ) return true ; if ( Op != TargetOpcode :: COPY && ! MI . isPHI ( ) && ! isPreISelGenericOptimizationHint ( Op ) ) return false ; auto * RB = getRegBank ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( RB == & <STR_LIT> ) return true ; if ( RB == & <STR_LIT> ) return false ; if ( ! MI . isPHI ( ) || Depth > MaxFPRSearchDepth ) return false ; return any_of ( MI . explicit_uses ( ) , [ & ] ( const MachineOperand & Op ) { return Op . isReg ( ) && onlyDefinesFP ( * MRI . getVRegDef ( Op . getReg ( ) ) , MRI ,


<s> return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode :: G_UADDO : return tryToSimplifyUADDO ( MI , B , Helper , Observer ) ; case TargetOpcode :: G_MEMCPY_INLINE : return Helper . tryEmitMemcpyInline ( MI ) ; case TargetOpcode :: G_MEMCPY : case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMSET


<s> MVT VecVT = Vec . getSimpleValueType ( ) ; if ( CIdx && CIdx -> getAPIntValue ( ) . ult ( VecVT . getVectorNumElements ( ) ) && ! DemandedElts [ CIdx -> getZExtValue ( ) ] ) return Vec ; break ; } } SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; if ( getTargetShuffleInputs ( Op , ShuffleOps , ShuffleMask , DAG , Depth ) ) { int NumOps = ShuffleOps . size ( ) ; if ( ShuffleMask . size ( ) == ( unsigned ) NumElts && llvm :: all_of ( ShuffleOps , [ VT ] ( SDValue V ) { return VT . getSizeInBits ( ) == V . getValueSizeInBits ( ) ; } ) ) { APInt IdentityOp = APInt ::


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return ( int )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectCMP_SWAP ( SDNode * N ) { unsigned Opcode ; EVT MemTy = cast < MemSDNode > ( N ) -> getMemoryVT ( ) ; if ( Subtarget -> hasLSE ( ) ) return false ; if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MVT RegTy = MemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( RegTy , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode >


<s> machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx val = CONST_VECTOR_ELT ( op , BYTES_BIG_ENDIAN ? nunits - <NUM_LIT> : <NUM_LIT> ) ; unsigned step = nunits / <NUM_LIT> ; unsigned copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , val ) ) ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return

gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , val ) ) ;


<s> MachineInstr * Copy = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , is64Bit

? <STR_LIT> : <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ;


<s> unsigned <ISA_LIT>FastISel :: getLibcallReg ( const Twine & Name ) { Type * GVTy = Type :: getInt32PtrTy ( * Context , <NUM_LIT> ) ; EVT LCREVT = TLI . getValueType ( DL , GVTy ) ; if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , nullptr , Name ) ; assert ( GV -> getType ( ) == GVTy && <STR_LIT> ) ; return <ISA_LIT>MaterializeGV ( GV , LCREVT .


<s> if ( ! Cand . isValid ( ) ) return ; if ( TryCand . Reason != NodeOrder && TryCand .


<s> SizeTy = IntegerType :: get ( M -> getContext ( ) , TD -> getIndexSizeInBits ( <NUM_LIT> ) ) ; CapPtrTy = PointerType :: get ( IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) , <NUM_LIT> ) ; return


<s> ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context


<s> unsigned int i ; unsigned int count = ( high - low ) + <NUM_LIT> ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( count -


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler (


<s> const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( )


<s> unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI ->


<s> unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) && Subtarget -> hasFP64 ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; Register ResultReg = createResultReg ( TLI


<s> AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> Register NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY


<s> void <ISA_LIT>FrameLowering :: replaceAdjDynAllocPseudo ( MachineFunction & MF ) const { const <ISA_LIT>InstrInfo & LII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned MaxCallFrameSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; while ( MBBI != MBB -> end ( ) ) { MachineInstr * MI = MBBI ++ ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , MI , DL , LII . get ( <STR_LIT> ) , Dst ) . addReg ( Src ) . addImm ( MaxCallFrameSize ) ; MI -> eraseFromParent


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Kind ==


<s> static SDValue combineSetCCEFLAGS ( SDValue EFLAGS , <STR_LIT> & CC , SelectionDAG & DAG ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS ,


<s> __rv . __o = __builtin_neon_vld4v4si ( ( const __builtin_neon_si * ) __a ) ; return __rv .


<s> static rtx gen_tls_get_addr ( void )


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { assert ( ( ByValSizeInBytes > OffsetInBytes ) && ( ByValSizeInBytes < OffsetInBytes + RegSizeInBytes ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min ( Alignment , LoadSizeInBytes ) ; } unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ; return ; } } unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , PtrTy , StackPtr , DAG . getIntPtrConstant ( ByVal . Address , DL ) ) ; Chain = DAG . getMemcpy ( Chain , DL , Dst , Src , DAG . getConstant ( MemCpySize , DL , PtrTy ) , Alignment

, false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return s -> rtl ; s = ( struct stack_local_entry * ) ggc_alloc ( sizeof ( struct stack_local_entry ) ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ; s -> next = ix86_stack_locals ; ix86_stack_locals =


<s> Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Trunc_bits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( Shl_imm >= VT . getSizeInBits ( ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false ; } uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; assert ( Srl_imm > <NUM_LIT> && Srl_imm < VT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Width = VT . getSizeInBits ( ) - Trunc_bits


<s> if ( CurrentArgIndex == Args [ i ] . OrigArgIndex ) { Out . back ( ) ++ ; } else { Out . push_back ( <NUM_LIT> ) ; CurrentArgIndex ++


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize


<s> bool BreakNext = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg != <STR_LIT> ) continue ; if ( ! MO . isDef


<s> for ( unsigned OpIdx = <NUM_LIT> ; OpIdx < MI . getNumOperands ( ) ; ++ OpIdx ) { MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) continue ; Register OpReg = MO . getReg ( ) ; const RegisterBank * RB = MRI . getRegBankOrNull ( OpReg ) ; if ( RB != DstRB ) { auto * OpDef = MRI . getVRegDef ( OpReg ) ; const LLT & Ty = MRI . getType ( OpReg ) ; MIB . setInsertPt ( * OpDef -> getParent ( ) , std :: next ( OpDef -> getIterator ( ) ) ) ; auto Copy = MIB . buildCopy ( Ty , OpReg ) ; MRI . setRegBank ( Copy . getReg ( <NUM_LIT> ) , * DstRB ) ; MO . setReg ( Copy . getReg (


<s> for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) return None ; Size += TII -> getInstSizeInBytes ( MI ) ; } return


<s> emit_insn ( gen_sse2_lshrv1ti3 ( tmp2 , op1 , GEN_INT ( <NUM_LIT> - bits ) ) ) ; emit_insn ( gen_iorv1ti3 ( tmp3 , tmp1 , tmp2 ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp3 ) ; return ; } rtx op1_v4si = force_reg ( V4SImode , gen_lowpart ( V4SImode , op1 ) ) ; rtx lobits ; rtx hibits ; switch ( bits >> <NUM_LIT> ) { case <NUM_LIT> : lobits = op1_v4si ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : lobits = gen_reg_rtx ( V4SImode ) ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( lobits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : lobits = gen_reg_rtx ( V4SImode ) ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( lobits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; default : lobits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( lobits , op1_v4si , GEN_INT ( <NUM_LIT> )


<s> auto MSN = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; SDValue Mask = MSN -> getMask ( ) ; SDValue Data = MSN -> getValue ( ) ; SDValue Idxs = MSN -> getIndex ( ) ; EVT VT = Data . getValueType ( ) ; if ( ! TLI . isTypeLegal ( VT ) || VT . isScalableVector ( ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; unsigned NumEls = VT . getVectorNumElements ( ) ; EVT SveVT = ( NumEls == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT NeonVT = ( NumEls == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Undef = DAG . getUNDEF ( SveVT ) ; if ( VT . isFloatingPoint ( ) ) Data = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Data ) ; Data = DAG . getNode ( <STR_LIT> , DL , NeonVT , Data ) ; Mask = DAG . getNode ( <STR_LIT> , DL , NeonVT , Mask ) ; Idxs = DAG . getNode ( <STR_LIT> , DL


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> Barrier . Data = Str . data ( ) ; Op -> Barrier . Length = Str . size ( ) ; Op -> StartLoc =


__v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; if ( ! DCI . isAfterLegalizeVectorOps ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; auto OpSize = N -> getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; unsigned Size = DAG . getDataLayout ( ) . getLargestLegalIntTypeSizeInBits ( ) ; if ( OpSize < Size ) { switch ( CC ) { default : break ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , false , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , true , DL ,


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src


<s> const char * arm_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = arm_get_strip_length ( * name


<s> if ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT ,


<s> int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue CCReg = N -> getOperand ( <NUM_LIT> ) ; if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Chain , DAG . getTargetConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getTargetConstant ( CCMaskVal , SDLoc ( N ) , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CCReg ) ; return SDValue (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { assert ( <NUM_LIT> &&


<s> static std :: string <ISA_LIT>_ez_int2hex ( int64_t val ) { std :: stringstream stream ; stream << std :: hex <<


<s> MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt ) ; return true


<s> AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> for ( unsigned i = <NUM_LIT> , e = VecRed . getNumOperands ( ) ; i < e ; i ++ ) Ops . push_back ( VecRed -> getOperand ( i ) ) ; SDValue Red = DCI . DAG . getNode ( OpcodeA , dl , DCI . DAG . getVTList ( { <STR_LIT> , <STR_LIT> } ) , Ops ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Red , SDValue ( Red . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; return SDValue (


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val


<s> static inline bool save_global_or_fp_reg_p ( unsigned int

regno , int leaf_function ATTRIBUTE_UNUSED ) {


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return


<s> Triple T ( TT ) ; if ( T . getArch ( ) == Triple :: arm64_be || T . getArch ( ) == Triple :: aarch64_be ) IsLittleEndian = false ; AssemblerDialect = AsmWriterVariant == Default ? <NUM_LIT> : AsmWriterVariant ; PointerSize = <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives =


<s> if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ) { if ( Fast ) * Fast


<s> if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL


<s> } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; O << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { bool Writeback = true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) Writeback = false ; } O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , BaseReg ) ; if ( Writeback ) O << <STR_LIT> ; O << <STR_LIT> ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MCRegisterClass & MRC = MRI . getRegClass ( <STR_LIT> ) ; bool isStore = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned Reg = MI -> getOperand ( isStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; if ( MRC . contains ( Reg


<s> return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) - MF . getFunction ( ) . isPagerando ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return __builtin_aarch64_ursra_nv8hi_uuus ( __a ,


<s> selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R6 ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetCRC ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetVirt ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> ,


<s> if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ; return <NUM_LIT>


<s> assert ( ( isa < LoadInst > ( VecInst ) || isa < ShuffleVectorInst > ( VecInst ) ) && <STR_LIT> ) ; Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; } assert ( VecBaseTy -> getPrimitiveSizeInBits ( ) . isByteSized


<s> static machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode


<s> ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt


<s> assert ( Amt < <NUM_LIT> && <STR_LIT> ) ; return ( Val << Amt ) | ( Val >> ( ( <NUM_LIT> -


<s> else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_GOTSYM_OFF ) { assemble_name ( fp , <STR_LIT> ) ; if ( GOT_PCREL ) fputs ( <STR_LIT> , fp ) ; fputs ( <STR_LIT> , fp ) ; output_addr_const ( fp , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputc ( ')' , fp ) ; return TRUE ; } else if ( GET_CODE ( x ) == UNSPEC && XINT (

x , <NUM_LIT> ) == UNSPEC_SYMBOL_OFFSET ) {


<s> inline vector signed int vec_adds ( vector signed int a1 ,


<s> Triple TT ( TM . getTargetTriple ( ) ) ; if ( TT . isOSBinFormatMachO ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL )