<s> CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_SaveList ; return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList :


<s> if ( ! Done && MatchAddress ( Addr , AM , false ) ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType == <STR_LIT> ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG


<s> if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_adddi3 ( dest , src1 , src2


<s> __builtin_ia32_pmovusdb512mem_mask ( ( __v16qi * ) __P , ( __v16si )


<s> static __inline__ float __frsp ( float a ) { float d


<s> static struct machine_function * rs6000_init_machine_status


<s> if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT>


<s> for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( llvm :: any_of ( ArgLocs , [ ] ( CCValAssign & A ) { assert ( ( A . getLocInfo ( ) != CCValAssign :: Indirect || A . getValVT ( ) . isScalableVector ( ) ) && <STR_LIT> ) ; return A . getLocInfo ( ) == CCValAssign :: Indirect ; } ) ) return false ; if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) return false ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; return


<s> const char * tmps ; SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_used_regs [ i ] ,


<s> MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) || MI -> isTransient ( ) ) continue ; Modified |= ReduceMI ( MII


<s> static unsigned getLeaOP ( LLT Ty , const <ISA_LIT>Subtarget & STI ) { if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; else if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) return STI


<s> EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( DestVT != <STR_LIT> ) return false ; unsigned Opc = <STR_LIT> ; unsigned ShiftImm ; Value * Src2Value = I -> getOperand ( <NUM_LIT> ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Src2Value ) ) { ShiftImm = CI -> getZExtValue ( ) ; if ( ShiftImm == <NUM_LIT> || ShiftImm >= <NUM_LIT> ) return false ; Opc = <STR_LIT> ; } Value * Src1Value = I -> getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Src1Value ) ; if ( Reg1 == <NUM_LIT> ) return false ; unsigned Reg2 = <NUM_LIT> ; if ( Opc == <STR_LIT> ) { Reg2 = getRegForValue ( Src2Value ) ; if ( Reg2 == <NUM_LIT> ) return false ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Reg1 ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <STR_LIT> ( ShiftTy , ShiftImm ) ) ; else if ( Opc


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> )


<s> if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; unsigned BaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; if ( MI -> modifiesRegister ( BaseReg , TRI ) ) return false ; if ( TII -> isLdStPairSuppressed ( MI ) ) return false ; return true


<s> static DecodeStatus decodePC32DBLBranchOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler


<s> if ( compare_section_name ( section , <STR_LIT> ) || compare_section_name ( section , <STR_LIT> ) || compare_section_name ( section , <STR_LIT> ) || compare_section_name ( section , <STR_LIT> ) || compare_section_name ( section , <STR_LIT> ) || compare_section_name ( section , <STR_LIT> ) || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; if ( size > <NUM_LIT> && size <= g_switch_value && ( rs6000_sdata != SDATA_DATA || TREE_PUBLIC ( decl ) ) ) return true ; } return


<s> return <STR_LIT> ( Op . getMemSegReg ( ) , Op . getMemDisp ( ) , Op . getMemBaseReg ( ) , Op . getMemIndexReg ( ) , Op . getMemScale ( ) , SMLoc ( ) , SMLoc ( ) ) ; } int64_t OrigDisplacement = static_cast < const MCConstantExpr * > ( Op . getMemDisp ( ) ) -> getValue ( ) ; CheckDisplacementBounds ( OrigDisplacement ) ; Displacement +=


<s> MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( OutContext . getOrCreateSymbol ( MO . getSymbolName ( ) ) ) ; if ( ! S -> hasRepresentedCsectSet ( ) ) { MCSectionXCOFF * Sec = OutContext . getXCOFFSection ( S -> getName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , XCOFF :: C_EXT , SectionKind :: getMetadata ( ) ) ; S -> setRepresentedCsect ( Sec ) ; } ExtSymSDNodeSymbols . insert ( S ) ; } } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> __rv . __o = __builtin_neon_vld3v8hi ( ( const __builtin_neon_hi * )


<s> if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & <NUM_LIT> ) == <NUM_LIT>


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N ,

SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ;


<s> else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . first ) ) Kind = k_SPRRegisterList ; <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , SMLoc > > :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> first ) ; array_pod_sort ( Op -> Registers . begin ( ) , Op -> Registers . end ( ) ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return Op


<s> void <ISA_LIT>ELFStreamer :: emitFnEnd ( ) { assert ( FnStart && <STR_LIT> ) ; if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX && ! IsAndroid ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; uint64_t Intval = Opcodes [ <NUM_LIT> ] | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> ; EmitIntValue ( Intval , Opcodes . size (


<s> BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) , <STR_LIT> , <STR_LIT> ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) , <STR_LIT> , <STR_LIT> ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , <STR_LIT> , <NUM_LIT> ) .


<s> case PLUS : if ( XEXP ( addr , <NUM_LIT> ) != virtual_stack_vars_rtx && XEXP ( addr , <NUM_LIT> ) != arg_pointer_rtx && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT val = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ; return val + <NUM_LIT> >= <NUM_LIT> - ( TARGET_POWERPC64 ? <NUM_LIT> : <NUM_LIT> ) ; } break ; case LO_SUM : return ! legitimate_constant_pool_address_p ( addr , QImode , false ) ; case PRE_MODIFY : return TARGET_UPDATE ; case AND : return true


<s> return is<ISA_LIT>64 ( ) ? <NUM_LIT> :


<s> if ( ! <STR_LIT> ( N . getNode ( ) ) || ! IsProfitableToFold ( N , P , P ) || ! IsLegalToFold ( N , P , P , OptLevel ) ) return false ; return selectAddr ( N . getNode ( ) , N . getOperand ( <NUM_LIT>

) , Base , Scale , Index , Disp , Segment ) ;


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Z : case InlineAsm :: Constraint_Zy : const TargetRegisterInfo * TRI = <ISA_LIT>SubTarget -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op .

getValueType ( ) , Op , RC ) , <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) { if ( getRelocationModel ( ) == Reloc :: Default ) setRelocationModel ( Reloc ::


<s> Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , Start ,

End , Size , Identifier , Info . OpDecl ) ;


<s> if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_NUNITS ( x ) . is_constant ( & nelts ) ) return - <NUM_LIT> ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return - <NUM_LIT> ; int firstval = aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , <NUM_LIT> ) ) ; if ( firstval <= <NUM_LIT> ) return - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < nelts ; i ++ ) if ( aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , i )


<s> if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex (


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) && getLexer ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L ,


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val


<s> if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else { assert ( <STR_LIT> ) ; } MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize


<s> bool IsOptimizingSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool HasFastHOps = Subtarget . hasFastHorizontalOps ( ) ; return ! IsSingleSource || IsOptimizingSize


<s> if ( ! isUnary ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; return isVMerge ( N , UnitSize


<s> TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; TargetLibraryInfo * TLI = & getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; <ISA_LIT>LowerAMXCast LAC ( F ) ; C |= LAC .


<s> } else if ( Domain == <STR_LIT> ) { if ( TID . mayStore ( ) || TID . mayLoad ( ) ) return false ; } else { return false ; } return MI -> readsRegister ( Reg ,


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val <


<s> unsigned char perm2 [ <NUM_LIT> ] ; rtx temp ; bool ok ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case E_V2SImode : case E_V2SFmode : perm2 [ <NUM_LIT> ] = elt ; perm2 [ <NUM_LIT> ] = elt + <NUM_LIT> ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 ,


<s> bool <ISA_LIT>ExpandPseudo :: expandSetTagLoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddressReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction * MF = MBB . getParent ( ) ; bool ZeroData = MI . getOpcode ( ) == <STR_LIT> ; const unsigned OpCode1 = ZeroData ? <STR_LIT> : <STR_LIT> ; const unsigned OpCode2 = ZeroData ? <STR_LIT> : <STR_LIT> ; unsigned Size = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Size > <NUM_LIT> && Size % <NUM_LIT> == <NUM_LIT> ) ; if ( Size % ( <NUM_LIT> * <NUM_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( OpCode1 ) , AddressReg ) . addReg ( AddressReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) ; Size -= <NUM_LIT> ; } MachineBasicBlock :: iterator I = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SizeReg ) . addImm ( Size ) ; expandMOVImm ( MBB , I , <NUM_LIT> ) ; auto LoopBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopBB ) ; MF -> insert ( ++ LoopBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoopBB , DL , TII -> get ( OpCode2 ) ) . addDef ( AddressReg ) . addReg ( AddressReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) . setMIFlags ( MI . getFlags ( ) ) ; BuildMI ( LoopBB , DL , TII -> get ( <STR_LIT> ) ) . addDef ( SizeReg ) . addReg ( SizeReg ) . addImm ( <NUM_LIT> * <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( SizeReg ) . addMBB ( LoopBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent (


<s> static SDValue addIPMSequence ( const SDLoc & DL , SDValue Glue , SelectionDAG & DAG ) { SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; SDValue ROTL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SRL , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return ROTL


<s> if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo (


<s> const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; if ( DstSize != <NUM_LIT> && DstSize != <NUM_LIT> ) return false ; return all_of ( MRI . use_instructions ( DstReg ) , [ ] ( const MachineInstr & Use ) { return Use . mayStore (


<s> RegisterTarget < Triple :: x86 , true > X ( The<ISA_LIT>_32Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: x86_64 , true > Y ( The<ISA_LIT>_64Target , <STR_LIT> ,


<s> vabdl_u16 ( uint16x4_t a , uint16x4_t b ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> assert ( Prefix == <STR_LIT> ) ; RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) + Reg )


<s> if ( GPRSaveSize != <NUM_LIT> ) { GPRIdx = MFI -> CreateStackObject ( GPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( ) ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( ) ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize ( FPRSaveSize


<s> static unsigned getMinCallArgumentsSize ( bool is<ISA_LIT>64 , bool isDarwinABI ) { if ( isDarwinABI || is<ISA_LIT>64 ) return <NUM_LIT> * ( is<ISA_LIT>64 ? <NUM_LIT> :


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> return __builtin_aarch64_rsqrtsv2df ( __a ,


<s> MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } int MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; int InsertExtractCost = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost ( Instruction :: InsertElement , SrcVTy , i ) ; else for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost (

Instruction :: ExtractElement , SrcVTy , i ) ;


<s> int aarch64_partial_ptrue_length ( rtx_vector_builder & builder , unsigned int elt_size ) { if ( builder . nelts_per_pattern ( ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned int nelts = builder . encoded_nelts ( ) ; unsigned int i = <NUM_LIT> ; for ( ; i < nelts ; i += elt_size ) if ( INTVAL ( builder . elt ( i ) ) == <NUM_LIT> ) break ; unsigned int vl = i / elt_size ; if ( i == nelts ) return - <NUM_LIT> ; if ( builder . nelts_per_pattern ( ) != <NUM_LIT> ) return <NUM_LIT> ; if ( i > builder . npatterns ( ) && maybe_ne ( nelts , builder . full_nelts ( ) ) ) return <NUM_LIT> ; for ( ; i < nelts ; i += elt_size ) if ( INTVAL ( builder . elt (


<s> case <STR_LIT> : TCC = <STR_LIT> ; if ( LHS . getOpcode ( ) == <STR_LIT> ) std :: swap ( LHS , RHS ) ; break ; } TargetCC = DAG . getConstant ( TCC , <STR_LIT> ) ; if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget (


<s> } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode ::


<s> CPUDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasAddiLoadFusion =


<s> Inst . addOperand ( MCOperand :: createReg ( getReg (


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! isReservedReg ( MF ,


<s> return llvm :: createAsmStreamer ( Ctx , S , OS , isVerboseAsm , useLoc , useCFI , useDwarfDirectory , InstPrint , CE


<s> bool <ISA_LIT>BaseTargetMachine :: addSimpleCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , ObjectCodeEmitter


<s> if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; OpNo = U . getOperandNo ( ) ; V = U . getUser ( ) ; } else if ( isAMXIntrinsic ( V ) ) { return getShape ( cast < IntrinsicInst > ( V ) , OpNo ) ; } else if ( isa < PHINode > ( V ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; V = U . getUser ( ) ; } else { break ; } } return std :: make_pair ( nullptr ,


<s> SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } return L


<s> CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } EmitToStreamer ( OutStreamer , MCInstBuilder ( CallOpcode ) . addOperand ( CallTargetMCOp ) ) ; } auto & Ctx = OutStreamer . getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer . emitLabel ( MILabel ) ; SM . recordStatepoint ( *


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator NMBBI = llvm :: next ( MBBI ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned NewLdOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineInstr * NewMI = AddDefaultPred ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NewLdOpc ) , DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ) ; NewMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; Modified = true ; break ; } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ,


<s> return ( __m64 ) __builtin_arm_wpackdss ( ( long long ) __m1 , ( long long


<s> static SDValue combineSelectAndUse ( SDNode * N , SDValue Slct , SDValue OtherOp , TargetLowering :: DAGCombinerInfo & DCI , bool AllOnes ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ; if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG ) ) return SDValue ( ) ; SDValue TrueVal = OtherOp ; SDValue FalseVal = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , OtherOp , NonConstantVal ) ; if ( SwapSelectOps ) std :: swap ( TrueVal , FalseVal ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CCOp , TrueVal


<s> unsigned arm_cde_end_args ( tree fndecl ) { return DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1q_p_v16qi ? <NUM_LIT> :


<s> return isSImm < <NUM_LIT> , <NUM_LIT> >


<s> static unsigned getLinkageSize ( bool LP64 , bool isMacho ) { if ( isMacho ) return <NUM_LIT> * ( LP64 ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . EatToEndOfStatement ( ) ; return Error ( L , <STR_LIT> ) ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) ) ; Parser . Lex (


<s> Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT>


<s> UI != UE ; ) { MachineOperand & StoreMO = * UI ++ ; MachineInstr & StoreMI = * StoreMO . getParent ( ) ; if ( StoreMI . getParent ( ) == MI . getParent ( ) && isPotentialBlockedMemCpyPair ( MI . getOpcode ( ) , StoreMI . getOpcode ( ) ) && isRelevantAddressingMode ( & MI ) && isRelevantAddressingMode ( & StoreMI ) ) { assert ( MI . hasOneMemOperand ( ) && <STR_LIT> ) ; assert ( StoreMI . hasOneMemOperand ( )


<s> Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> ,


<s> return ( __m128 ) __builtin_ia32_expandsf128_maskz ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) , (


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; unsigned IFlags = Op . getImm ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i )


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . RemoveOperand


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ,


<s> BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) ; ++ NumInstsInserted ; return Reg


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg2 ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc


<s> aarch64_process_components ( components ,


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) continue ; if ( Val . isPowerOf2 ( ) ) { ++ Steps ; continue ; } APInt Floor = APInt ( BitWidth , <NUM_LIT> ) << Val . logBase2 ( ) ; APInt Ceil = Val . isNegative ( ) ? APInt ( BitWidth , <NUM_LIT> ) : APInt ( BitWidth , <NUM_LIT> ) << C . ceilLogBase2 ( ) ; if ( ( Val - Floor ) . ule ( Ceil - Val ) ) { WorkStack . push_back ( Floor ) ; WorkStack . push_back ( Val - Floor ) ; ++ Steps ; continue ; } WorkStack . push_back ( Ceil ) ; WorkStack . push_back ( Ceil - Val ) ; ++ Steps ; if ( Steps > <NUM_LIT> && ( Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ) return false ; if ( Steps > <NUM_LIT> && Subtarget . isABI_O32 ( ) ) return false ; } unsigned RegisterSize = DAG . getTargetLoweringInfo ( ) . getRegisterType ( * DAG . getContext ( ) , VT ) . getSizeInBits ( ) ; Steps *= ( VT . getSizeInBits ( ) != RegisterSize ) * <NUM_LIT> ; if ( Steps > <NUM_LIT>


<s> else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != <STR_LIT> || ! Copy -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain


<s> return ( __m128 ) __builtin_ia32_movhlps ( ( __v4sf ) __A ,


<s> const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<=


<s> if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && ST -> isVolatile ( ) ) { SDNode * N = Op . getNode ( ) ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , { ST -> getChain ( ) , Lo

, Hi , ST -> getBasePtr ( ) } , MemVT , ST -> getMemOperand ( ) ) ;


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg


<s> ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; SmallVector < unsigned , <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case


<s> for ( auto I = From ; I != To ; ++ I ) if ( I -> modifiesRegister ( Reg , TRI ) ) return true ; return false


<s> vmvn_s16 ( int16x4_t a ) { int16x4_t result


<s> static bool rs6000_scalar_mode_supported_p ( scalar_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_epi32 ( int const * base , __m128i index , const int scale ) { __v4si src = __extension__ ( __v4si ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4si mask = __extension__ ( __v4si ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> ,


<s> TmpInst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( N ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - N ) ) ; Inst = TmpInst ; break ; } case <STR_LIT> : { MCInst TmpInst ; int64_t N = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; TmpInst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - N ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( N ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst = TmpInst ; break ; } case <STR_LIT> :


<s> if ( Alignment >= DataSize && ( DataSize == <NUM_LIT> || DataSize == <NUM_LIT> ) ) return DataSize == <NUM_LIT> ? ST -> hasSSE1 ( ) : ST ->


<s> MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataSection ( ) ) ; unsigned PtrSize = TM . getDataLayout ( ) -> getPointerSize ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] .


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize (


<s> struct ix86_frame & frame = cfun -> machine -> frame ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM )

return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ;


<s> if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addImm ( NumBytes ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } else if ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } assert ( ( DestReg != <STR_LIT> || BaseReg == <STR_LIT> ) && <STR_LIT> ) ; if ( ( DestReg == <STR_LIT> ) && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; break ; } bool HasCCOut = true ; int ImmIsT2SO = <STR_LIT> ( ThisVal ) ; bool ToSP = DestReg == <STR_LIT> ; unsigned t2SUB = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2ADD = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2SUBi12 = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2ADDi12 = ToSP ? <STR_LIT> : <STR_LIT> ; Opc = isSub ? t2SUB


<s> static DecodeStatus DecodeUImmWithOffset ( MCInst & Inst , unsigned Value , uint64_t Address , const void *


<s> SDValue <ISA_LIT>TargetLowering :: lowerToVVP ( SDValue Op , SelectionDAG & DAG ) const { auto OCOpt = getVVPOpcode ( Op -> getOpcode ( ) ) ; if ( ! OCOpt . hasValue ( ) ) return SDValue ( ) ; unsigned VVPOC = OCOpt . getValue ( ) ; EVT OpVecVT = Op . getValueType ( ) ; EVT LegalVecVT = getTypeToTransformTo ( * DAG . getContext ( ) , OpVecVT ) ; SDLoc DL ( Op ) ; SDValue AVL = DAG . getConstant ( OpVecVT . getVectorNumElements ( ) , DL , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ; SDValue ConstTrue = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , bool little , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>Default ) , IsLittle ( little ) , IsSoftFloat ( false ) , IsSingleFloat ( false ) , IsFPXX ( false ) , NoABICalls ( false ) , IsFP64bit ( false ) , UseOddSPReg ( true ) , IsNaN2008bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasCn<ISA_LIT> ( false ) , Has<ISA_LIT>3_32 ( false ) , Has<ISA_LIT>3_32r2 ( false ) , Has<ISA_LIT>4_32 ( false ) , Has<ISA_LIT>4_32r2 ( false ) , Has<ISA_LIT>5_32r2 ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , HasDSPR3 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , HasMSA ( false ) , UseTCCInDIV ( false ) , HasSym32 ( false ) , HasEVA ( false ) , DisableMadd4 ( false ) , HasMT ( false ) , StackAlignOverride ( StackAlignOverride ) , TM ( TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) { if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error (


<s> static const <ISA_LIT>MCExpr * CreateGOT ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_AARCH64_GOT ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return <STR_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context


<s> for ( unsigned i = <NUM_LIT> ; i != Multiple - <NUM_LIT> ; ++ i ) { if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; if ( OpVal . getNode ( ) == <NUM_LIT> ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( OpVal . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; while ( ValSizeInBytes > ByteSize ) { ValSizeInBytes >>= <NUM_LIT> ; if ( ( ( Value >> ( ValSizeInBytes * <NUM_LIT> ) ) & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) != ( Value & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) ) return SDValue ( ) ; } int ShAmt = ( <NUM_LIT> - ByteSize ) * <NUM_LIT> ; int MaskVal = ( ( int ) Value << ShAmt


<s> unsigned getDarwinVers ( ) const { if ( isTargetDarwin ( ) ) return TargetTriple . getDarwinMajorNumber ( ) ; return <NUM_LIT>


<s> MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; const DebugLoc & DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; const MachineOperand & PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case


<s> bool x86_extended_reg_mentioned_p ( rtx insn ) { return for_each_rtx ( & PATTERN ( insn ) , extended_reg_mentioned_1 ,


<s> error ( <STR_LIT> , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } if ( fcode == RS6000_BUILTIN_CPU_IS ) { const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask = NULL_RTX ; int hwcap_offset ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_supports_info ) ; i ++ ) if ( strcmp ( hwcap , cpu_supports_info [ i ] . hwcap ) == <NUM_LIT> ) { mask = GEN_INT ( cpu_supports_info [ i ] . mask ) ; hwcap_offset = TCB_HWCAP_OFFSET ( cpu_supports_info [


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT> ) && Subtarget . has<ISA_LIT>32r2Or64 ( ) ) return false ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; return


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser

( parser ) , MII ( mii ) , InstInfo ( nullptr ) {


<s> if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) ) return make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return

make_unique < TargetLoweringObjectFileCOFF > ( ) ;


<s> DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; InstrPos [ DefMI ] = InstrPos [ & MI ] - <NUM_LIT> ; assert ( ( ( InstrPos [ DefMI ] == <NUM_LIT> && MachineBasicBlock :: iterator ( DefMI ) == MBB -> begin ( ) ) || InstrPos [ DefMI ] > InstrPos [ & * std :: prev ( MachineBasicBlock :: iterator ( DefMI ) ) ] ) && <STR_LIT> ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( AddrDispShift ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( )


<s> ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , <NUM_LIT> ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) ,


<s> Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) ==


<s> SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } else { MVT TruncVT = <STR_LIT> ( MaskVT . getSizeInBits ( ) ) ; return DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , TruncVT , Mask ) ) ; } } else { MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) .


<s> if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; SrcReg1 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg1 , <NUM_LIT> ) ; SrcReg2 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; updateValueMap ( I , ResultReg ) ; return


<s> vst4_f16 ( float16_t * __a , float16x4x4_t val ) { __builtin_aarch64_simd_xi __o ; float16x8x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv8hf ( __o , ( float16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hf ( __o , ( float16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hf ( __o , ( float16x8_t ) temp . val [ <NUM_LIT>


<s> if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits


<s> int mmix_reversible_cc_mode ( enum machine_mode


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg =


<s> rtx hi ; rtx lo ; rtx addr ; const char * load_string ; int r ; if ( GET_CODE ( mem ) == FLOAT_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND ) { mem = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; } if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_VECTOR ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : load_string = <STR_LIT> ; break ; case E_HImode : load_string = <STR_LIT> ; break ; case E_SImode : case


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target


<s> RMValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RMValue , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; SDValue FPSCR = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , Ops ) ; Chain = FPSCR . getValue ( <NUM_LIT> ) ; FPSCR = FPSCR . getValue ( <NUM_LIT> ) ; const unsigned RMMask = ~ ( <STR_LIT> :: rmMask << <STR_LIT> ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , DAG . getConstant ( RMMask , DL , <STR_LIT> ) ) ; FPSCR = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPSCR , RMValue ) ; SDValue Ops2 [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , FPSCR } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> if ( getParser ( ) . parseExpression ( Value ) ) return false ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return false


<s> MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst


<s> LEASLInst . addOperand ( RD ) ; LEASLInst . addOperand ( Imm ) ; OutStreamer . emitInstruction ( LEASLInst


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> vmull_high_p64 ( poly64x2_t a , poly64x2_t b ) { return __builtin_aarch64_crypto_pmullv2di_ppp ( a


<s> if ( ! isa < ScalableVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned , CostKind ) ; assert ( ( isa < ScalableVectorType > ( Ty ) && isa < ScalableVectorType > ( CondTy ) ) && <STR_LIT> ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; InstructionCost LegalizationCost = <NUM_LIT> ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( Ty -> getContext ( ) ) ; unsigned CmpOpcode = Ty -> isFPOrFPVectorTy ( ) ? Instruction :: FCmp : Instruction :: ICmp ; LegalizationCost = getCmpSelInstrCost ( CmpOpcode , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) + getCmpSelInstrCost ( Instruction :: Select , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; LegalizationCost *= LT .


<s> UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; AllowsUnalignedMem =


<s> Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M


<s> if ( from == ARG_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - crtl -> outgoing_args_size ; if ( from == FRAME_POINTER_REGNUM ) return ( cfun -> machine -> frame . hard_fp_offset - cfun -> machine -> frame . saved_varargs_size ) ; } if ( to ==


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorLoad ( Op , DAG ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; MachineMemOperand * MMO = LD -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLD ) ; SDValue Ops [ ] = { Result , SDValue ( NewLD . getNode ( ) , <NUM_LIT>


<s> return RBI . getRegBank ( Reg , MRI , TRI ) -> getID


<s> tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p


<s> unsigned Binary = <NUM_LIT> ; if ( SPRRegs || DPRRegs ) { unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg ) ; unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands


<s> int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( class != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - <NUM_LIT> ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - <NUM_LIT> ; } else regno = - <NUM_LIT> ; if ( class == GENERAL_REGS || class == BASE_REGS || ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || FP_REGNO_P ( regno ) ) && ( class == FLOAT_REGS || class == NON_SPECIAL_REGS ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || ALTIVEC_REGNO_P ( regno ) ) && class == ALTIVEC_REGS ) return NO_REGS ; if ( ( class == CR_REGS || class == CR0_REGS ) && regno >= <NUM_LIT> && CR_REGNO_P ( regno ) ) return NO_REGS ; return


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF


<s> static int bytesize ( const_tree type


<s> gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; if ( num_regs == <NUM_LIT> && ! arm_arch6 ) { if ( first_reg == <NUM_LIT> ) first_reg -- ; num_regs ++ ; } if ( num_regs > <NUM_LIT> ) { arm_emit_vfp_multi_reg_pop ( first_reg , <NUM_LIT> , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + <NUM_LIT> , num_regs - <NUM_LIT> , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( VOIDmode , base_reg , plus_constant ( Pmode , base_reg , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> )


<s> } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BrInstr = & * I ; continue ; } if ( analyzeCompare ( * I , SrcReg , CmpValue ) ) { if ( CmpInstr ) return nullptr ; CmpInstr = & * I ; continue ; } CmpBrOnly = false ; break ; } if ( ! TBB || ! FBB || ! CmpInstr ) return nullptr ; switch ( CC ) { case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( TBB , FBB ) ; Modified = true ; break ; case <STR_LIT> : if ( CmpValue == INT_MAX ) return nullptr ; CC = <STR_LIT> ; CmpValue += <NUM_LIT> ; Modified = true ; break ; case <STR_LIT> : if ( CmpValue == INT_MIN ) return nullptr ; CC = <STR_LIT> ; CmpValue -= <NUM_LIT> ; Modified = true ; break ; default : Modified = false ; break ; } return std :: make_unique < TargetMBBInfo > ( TargetMBBInfo { TBB , FBB , BrInstr , CmpInstr , CC , SrcReg , CmpValue ,


<s> static VariantKind getAddressFrag ( VariantKind Kind ) { return static_cast < VariantKind > (


<s> return ( __m128bh ) __builtin_ia32_cvtne2ps2bf16_v8hi (


<s> const __GCC_FV * g = mtrxg , * i = mtrxi ; __GCC_FV * f = mtrxf ; int j ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) sh_media_FTRVADD_S ( mtrxh , & g [ j ] , & i [ j ] , & f [ j ] ) ; sh_media_FTRVADD_S ( mtrxh , & g [ <NUM_LIT> ] , & i [ <NUM_LIT> ] , & f [ <NUM_LIT> ] ) ; sh_media_FTRVADD_S ( mtrxh , & g [ <NUM_LIT> ] , & i [ <NUM_LIT> ] , & f [ <NUM_LIT> ] ) ; sh_media_FTRVADD_S ( mtrxh , & g [ <NUM_LIT> ] , & i [ <NUM_LIT> ] , & f [ <NUM_LIT>


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , llvm :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; return DAG


<s> Reserved . set ( <STR_LIT> ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> Value * EFLAGSDef = computeEFLAGSForDef ( LastEFLAGSChangingDef , getRegNoCallback ( RegNo ) ) ; setRegValWithName ( RegNo , EFLAGSDef


<s> return __builtin_ia32_ucomisdgt ( ( __v2df ) __A , ( __v2df )


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 &&


<s> static SDValue LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { EVT VTs [ ] = { LHS . getValueType ( ) , <STR_LIT> } ; SDValue Ops [ <NUM_LIT> ] = { LHS


<s> mode = <STR_LIT> ; break ; case <NUM_LIT> : mode = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx = int_rtx ; return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , offset_rtx


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetCRC


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = mode_for_size ( width , MODE_INT , <NUM_LIT> ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left )


<s> getBDLAddr12Len4Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) ,


<s> static const <ISA_LIT>MCExpr * CreateABS_G0_NC ( const MCExpr * Expr ,


<s> if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue


<s> F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo . createVirtualRegister


<s> return __builtin_mve_vmulq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a ,


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> if ( ! TheTriple . isOSBinFormatCOFF ( ) ) return Printer . getSymbol ( GV ) ; assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & ( <STR_LIT> | <STR_LIT> ) ) ; if ( ! IsIndirect ) return Printer . getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ; else if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ; Printer . TM . getNameWithPrefix ( Name , GV , Printer

. getObjFileLowering ( ) . getMangler ( ) ) ;


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex ,


<s> else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> ) ; VT = <STR_LIT> ; } unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , DestAM ) ; assert ( RV && <STR_LIT>


<s> MachineBasicBlock :: iterator StoreI ; if ( findMatchingStore ( MBBI , LdStLimit , StoreI ) ) { ++ NumLoadsFromStoresPromoted ; MBBI = promoteLoadFromStore ( MBBI


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction &


<s> if ( IsToVec ) { DecodeFPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rn , Address


<s> DebugLoc :: getUnknownLoc ( ) ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize - TFI . getOffsetOfLocalArea ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) { assert ( MF . getRegInfo ( ) .

isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ;


<s> static bool ix86_macro_fusion_pair_p ( rtx_insn * condgen , rtx_insn * condjmp ) { rtx src , dest ; enum rtx_code ccode ; rtx compare_set = NULL_RTX , test_if , cond ; rtx alu_set = NULL_RTX , addr = NULL_RTX ; if ( ! any_condjump_p ( condjmp ) ) return false ; if ( get_attr_type ( condgen ) != TYPE_TEST && get_attr_type ( condgen ) != TYPE_ICMP && get_attr_type ( condgen ) != TYPE_INCDEC && get_attr_type ( condgen ) != TYPE_ALU ) return false ; compare_set = single_set ( condgen ) ; if ( compare_set == NULL_RTX && ! TARGET_FUSE_ALU_AND_BRANCH ) return false ; if ( compare_set == NULL_RTX ) { int i ; rtx pat = PATTERN ( condgen ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set_src = SET_SRC ( XVECEXP ( pat , <NUM_LIT> , i ) ) ; if ( GET_CODE ( set_src ) == COMPARE ) compare_set = XVECEXP ( pat , <NUM_LIT> , i ) ; else alu_set = XVECEXP ( pat , <NUM_LIT> , i ) ; } } if ( compare_set == NULL_RTX ) return false ; src = SET_SRC ( compare_set ) ; if ( GET_CODE ( src ) != COMPARE ) return false ; if ( ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) ) return false ; if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; if ( addr ) { ix86_address parts ; int ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( rip_relative_addr_p ( & parts ) ) return false ; } test_if = SET_SRC ( pc_set ( condjmp ) ) ; cond = XEXP ( test_if , <NUM_LIT> ) ; ccode = GET_CODE ( cond ) ; if ( ! TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS && ( ccode == GE || ccode == GT || ccode == LE || ccode == LT ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_TEST || get_attr_type ( condgen ) == TYPE_ICMP ) return true ; if ( ! TARGET_FUSE_ALU_AND_BRANCH || ! alu_set ) return false ; dest = SET_DEST ( alu_set ) ; if ( MEM_P ( dest ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_INCDEC && ( ccode == GEU || ccode ==

GTU || ccode == LEU || ccode == LTU ) ) return false ;


<s> bool hasFineGrainedTraps ( ) const { return HasFineGrainedTraps


<s> NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( ArgRegsSaveSize ) { MBBI = MBB . getLastNonDebugInstr


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> hasExtractInsert ( ) ) return SDValue ( ) ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) , And1 = N -> getOperand ( <NUM_LIT> ) ; uint64_t SMPos0 , SMSize0 , SMPos1 , SMSize1 ; ConstantSDNode * CN ; if ( And0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And0 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( ~ CN -> getSExtValue ( ) , SMPos0 , SMSize0 ) ) return SDValue ( ) ; if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) )

|| ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ;


<s> unsigned <ISA_LIT>FastISel :: emitSub ( MVT RetVT , const Value * LHS , const Value * RHS , bool

SetFlags , bool WantResult , bool IsZExt ) {


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { emitSPAdjustment ( MF , MBB , MBBI , NumBytes , None ) ; } emitEpilogueInsns ( MF , MBB , MBBI , NumBytes ,


<s> MCInst I ; MCInstLowering . lowerInstruction ( * MI , I


<s> SDValue <ISA_LIT>TargetLowering :: LowerELFTLSDescCallSeq ( SDValue SymAddr , const SDLoc & DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , {


<s> if ( Subtarget -> isTargetEnvMacho ( ) ) OutStreamer . SwitchSection

( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2


<s> static SDValue extract128BitVector ( SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , SDLoc dl ) { assert ( ( Vec . getValueType ( ) . is256BitVector ( ) || Vec . getValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; return extractSubVector ( Vec , IdxVal , DAG , dl ,


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; int NumElements = VT . getVectorNumElements ( ) ; SDLoc dl ( Op ) ; assert ( VT . getSizeInBits ( ) != <NUM_LIT> && <STR_LIT> ) ; bool V1IsUndef = V1 . getOpcode ( ) == <STR_LIT> ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; MVT NewVT = <STR_LIT> ( NewEltVT , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , NewVT , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , WidenedMask ) ) ; } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) , OSABI ( _OSABI ) { HasReliableSymbolDifference =


<s> if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty


<s> OS << <STR_LIT> << Opcode << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } if ( isPostIncrementForm ( MI , AddOffset


<s> getAddrMode5OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm8 ; bool isAdd ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind (


<s> MachineInstr * PrevVCMP = nullptr ; MachineOperand * PrevVCMPResultKiller = nullptr ; for ( MachineInstr & Instr : MBB . instrs ( ) ) { if ( PrevVCMP ) { if ( MachineOperand * MO = Instr . findRegisterUseOperand ( PrevVCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , true ) ) { PrevVCMPResultKiller = MO ; } } if ( getVPTInstrPredicate ( Instr ) != <STR_LIT> ) continue ; if ( ! IsVCMP ( Instr . getOpcode ( ) ) ) { if ( IsWritingToVCCR ( Instr ) ) PrevVCMP = nullptr ; continue ; } if ( ! PrevVCMP || ! IsVPNOTEquivalent ( Instr , * PrevVCMP ) ) { PrevVCMP = & Instr ; continue ; } Register PrevVCMPResultReg = PrevVCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( Instr . getOperand ( <NUM_LIT> ) ) . addReg ( PrevVCMPResultReg ) ; addUnpredicatedMveVpredNOp ( MIBuilder ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump (


<s> void neon_lane_bounds ( rtx operand , HOST_WIDE_INT low

, HOST_WIDE_INT high , const_tree exp ) {


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpeq ( a , b


<s> WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } return


<s> case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_EXTRACT_VECTOR_ELT : case TargetOpcode :: G_INSERT_VECTOR_ELT : return true ; default : break ; } return hasFPConstraints ( MI , MRI , TRI


<s> args_so_far = pack_cumulative_args ( & args_so_far_v ) ; regno = GP_ARG_FIRST ; for ( cur_arg = fnargs ; cur_arg != <NUM_LIT> ; cur_arg = next_arg ) { tree passed_type = DECL_ARG_TYPE ( cur_arg ) ; machine_mode passed_mode = TYPE_MODE ( passed_type ) ; rtx entry_parm ; if ( TREE_ADDRESSABLE ( passed_type ) ) { passed_type = build_pointer_type ( passed_type ) ; passed_mode = Pmode ; } entry_parm = iq2000_function_arg ( args_so_far , passed_mode , passed_type , true ) ; iq2000_function_arg_advance ( args_so_far , passed_mode , passed_type , true ) ; next_arg = DECL_CHAIN ( cur_arg ) ; if ( entry_parm && store_args_on_stack ) { if ( next_arg == <NUM_LIT> && DECL_NAME ( cur_arg ) && ( strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> || strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> ) ) { last_arg_is_vararg_marker = <NUM_LIT> ; break ; } else { int words ; gcc_assert ( GET_CODE ( entry_parm ) == REG ) ; if ( GET_MODE ( entry_parm ) == BLKmode ) words = ( int_size_in_bytes ( passed_type ) + <NUM_LIT> ) / <NUM_LIT> ; else words = ( GET_MODE_SIZE ( GET_MODE ( entry_parm ) ) + <NUM_LIT> ) / <NUM_LIT> ; regno = REGNO ( entry_parm ) + words - <NUM_LIT> ; } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( stdarg_p ( fntype ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( tsize > <NUM_LIT> ) { rtx tsize_rtx = GEN_INT ( tsize ) ; rtx adjustment_rtx , dwarf_pattern ; rtx_insn * insn ; if ( tsize >


<s> bool CustomExpandInst ( const MCInst & Inst


) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) ||


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> assert ( VA . getValVT ( ) . getSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( VA . getLocVT ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg


<s> void <ISA_LIT>InstructionSelector :: renderFPImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode ::

G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;


<s> return ( GET_CODE ( XEXP ( x , <NUM_LIT>


<s> } } else { switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , false ) ; } } assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue (


<s> return ( ( qword ) ( vec_re ( ( vec_float4 )


<s> Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; auto * IndexVTy = FixedVectorType :: get ( IntegerType :: get (

SrcVTy -> getContext ( ) , IndexSize ) , VF ) ;


<s> for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun

-> machine -> fpr_is_wrapped_separately [ i - <NUM_LIT> ] = true ;


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> ,


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getZExtValue ( ) == <NUM_LIT> && V . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( V . getOperand ( <NUM_LIT> ) ) , N -> getValueType ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = <ISA_LIT>InstrFMA3Info :: getFMA3Group ( MI . getOpcode ( ) ) ; if ( FMA3Group ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , * FMA3Group ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1


<s> for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty }


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; assert ( ! ArchFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName =


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( )


<s> tree decl = aarch64_sls_shared_thunks [ regnum ] ; if ( ! decl ) continue ; const char * name = indirect_symbol_names [ regnum ] ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; ASM_OUTPUT_ALIGN ( out_file , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( out_file , name , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( out_file , name ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; asm_fprintf ( out_file


<s> if ( ! INT14_OK_STRICT && ( strict || ! ( reload_in_progress || reload_completed ) ) && mode != QImode && mode != HImode ) return false ; return base14_operand ( index , mode ) ; } if ( ! TARGET_DISABLE_INDEXING && ( TARGET_NO_SPACE_REGS ? REG_P ( index ) : ( base == XEXP ( x , <NUM_LIT> ) && REG_P ( index ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( base ) ) || REG_POINTER ( base ) ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( index ) ) || ! REG_POINTER ( index ) ) ) ) && MODE_OK_FOR_UNSCALED_INDEXING_P ( mode ) && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( index ) : REG_OK_FOR_INDEX_P ( index ) ) && borx_reg_operand ( base , Pmode ) && borx_reg_operand ( index , Pmode ) ) return true ; if ( ! TARGET_DISABLE_INDEXING && GET_CODE ( index ) == MULT && MODE_OK_FOR_SCALED_INDEXING_P ( mode ) && REG_P ( XEXP ( index , <NUM_LIT> ) ) && GET_MODE ( XEXP ( index , <NUM_LIT> ) ) == Pmode && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) : REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) ) && GET_CODE ( XEXP ( index , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( index , <NUM_LIT> ) ) == ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) && borx_reg_operand ( base , Pmode ) ) return true ; return false ; } if ( GET_CODE ( x ) == LO_SUM ) { rtx y = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( y ) == SUBREG ) y = SUBREG_REG ( y ) ; if ( REG_P ( y ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( y ) : REG_OK_FOR_BASE_P ( y ) ) ) { if ( mode == Pmode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC ) return true ; if ( ! INT14_OK_STRICT && ( strict || ! ( reload_in_progress || reload_completed ) ) && mode !=


<s> Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( index )


<s> return __aarch64_vdup_lane_p16 ( __a ,


<s> <ISA_LIT>JITInfo ( <ISA_LIT>TargetMachine & tm , bool tmIs64Bit ) : TM ( tm ) { useGOT = <NUM_LIT>