<s> case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops ,


<s> return getLabelOpValue ( Inst , OpNo , Fixups , SubtargetInfo

, static_cast < MCFixupKind > ( <STR_LIT> ) ) ;


<s> if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> + ID . getIdentifier (


<s> i = mips_build_integer ( codes , value ) ; codes [ i ] . code = ASHIFT ; codes [ i ]


<s> if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . hasAVX2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) ) { auto BW = Subtarget . hasBWI ( ) ; EVT VecVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CmpVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : VecVT ; SDValue Cmp ; if ( IsOrXorXorCCZero ) { SDValue A = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue D = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp1 = DAG . getSetCC ( DL , CmpVT , A , B , <STR_LIT> ) ; SDValue Cmp2 = DAG . getSetCC ( DL , CmpVT , C , D , <STR_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , Cmp1 , Cmp2 ) ; } else { SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } if ( OpSize == <NUM_LIT> && BW ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; if ( OpSize == <NUM_LIT> ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; SDValue MovMsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cmp ) ; SDValue FFFFs = DAG . getConstant ( OpSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getSetCC ( DL , VT


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT>


<s> for ( end = loop -> end -> next ; end != <NUM_LIT> ; end = end -> next ) if ( end -> label != loop -> end -> label || ! simplejump_p ( end -> fallthrough ) || fallthrough != next_real_insn ( JUMP_LABEL_AS_INSN ( end -> fallthrough ) ) ) return false ; return true


<s> if ( DestVT == <STR_LIT> ) DestVT = Op0 . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID , <STR_LIT> ) , Op0 , Op1


<s> return __builtin_arm_stc ( __coproc ,


<s> } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ; IsSelfLoop = false


<s> if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; }


<s> SDValue getAddrGPRel ( NodeTy * N , SDLoc DL , EVT Ty , SelectionDAG & DAG ) const { assert ( Ty == <STR_LIT> ) ; SDValue GPRel = getTargetNode ( N , Ty , DAG


<s> static struct machine_function * mmix_init_machine_status ( void


<s> assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / <NUM_LIT> > <NUM_LIT> ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseIdx << <STR_LIT> ) ; DEBUG ( UseMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected =


<s> void <ISA_LIT>InstPrinter :: printBarrierOption ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; bool Valid ; StringRef Name ; if ( Opcode == <STR_LIT> ) Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; else Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid )


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ; for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask .


<s> if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; return Inst -> getType ( ) ->

getPrimitiveSizeInBits ( ) <= <NUM_LIT> ;


<s> MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget . hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ; Highs = DAG . getNode ( <STR_LIT> , dl , VT , Highs , Fixup ) ; } SDValue Ops [ ] = { Lows , Highs } ; return DAG . getMergeValues ( Ops


<s> SmallVector < MachineInstr * , <NUM_LIT> > PotentialBlockers ; unsigned BlockCount = <NUM_LIT> ; const unsigned InspectionLimit = <ISA_LIT>AvoidSFBInspectionLimit ; for ( auto PBInst = std :: next ( MachineBasicBlock :: reverse_iterator ( LoadInst ) ) , E = LoadInst -> getParent ( ) -> rend ( ) ; PBInst != E ; ++ PBInst ) { if ( PBInst -> isMetaInstruction ( ) ) continue ; BlockCount ++ ; if ( BlockCount >= InspectionLimit ) break ; MachineInstr & MI = * PBInst ; if ( MI . getDesc ( ) . isCall ( ) ) return PotentialBlockers ; PotentialBlockers . push_back ( & MI ) ; } if ( BlockCount <


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> )

) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI -> getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI -> setObjectSize ( RPI . FrameIdx , <NUM_LIT> ) ; } else Offset -= RPI . isPaired ( )


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal


<s> getRegClassForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) != <NUM_LIT> ) return std :: vector < unsigned > ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r'


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = RoundUpToAlignment ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else VaArgOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; APInt LHSKnownZero


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { EVT BCVT = <STR_LIT> , HalfVT = <STR_LIT> ; switch ( ResVT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; } if ( BCVT != <STR_LIT> ) { SDValue BC = DAG . getBitcast ( BCVT , Op0 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , HalfVT , BC ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Trunc , DAG . getUNDEF ( HalfVT ) ) ; } } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } } if ( Op1 . getOpcode ( ) ==


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int StackSize = ( int ) MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT>


<s> if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> :


<s> } else if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else return false ; unsigned Scale = <NUM_LIT> ; int64_t Dummy1 , Dummy2 ; if ( ! getMemOpInfo ( LdSt . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { BaseOp = & LdSt . getOperand (


<s> shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4


<s> emit_move_insn ( scratch , val ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; emit_insn ( gen_isync


<s> if ( GET_CODE ( dst ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( src ) == MEM ) return <NUM_LIT> ; if ( register_operand ( src , VOIDmode ) ) return


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1


<s> int32_t Imm = SignExtend32 < Bits > ( Value ) * ScaleBy ; Inst . addOperand ( MCOperand :: createImm ( Imm + Offset ) ) ; return MCDisassembler :: Success


<s> bool sh_treg_combine :: is_normal_ccreg ( const_rtx x )


<s> Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX (


<s> return Ext -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> * Ext -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; } ; if ( ! match ( Ext1 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! match ( Ext2 , m_ZExtOrSExt ( m_Value ( ) ) ) || ! areExtDoubled ( cast < Instruction > ( Ext1 ) ) || ! areExtDoubled (

cast < Instruction > ( Ext2 ) ) ) return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Op . dump ( ) ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerWRITE_REGISTER ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG


<s> if ( ( offset & ( va_granularity - <NUM_LIT> ) ) != <NUM_LIT> ) return - <NUM_LIT> ; GetVersionEx ( & version_info ) ; char local_object_name [ sizeof ( OBJECT_NAME_FMT ) + sizeof ( DWORD ) * <NUM_LIT> ] ; if ( version_info . dwMajorVersion > <NUM_LIT> ) { snprintf ( local_object_name , sizeof ( local_object_name ) , OBJECT_NAME_FMT <STR_LIT> , GetCurrentProcessId ( ) ) ; object_name = local_object_name ; } mmap_handle = CreateFileMappingA ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , <NUM_LIT> , <NUM_LIT> , object_name ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , <STR_LIT> ) ; return - <NUM_LIT> ; } for ( r = <NUM_LIT> ; r < <NUM_LIT> ; r ++ ) { mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , <NUM_LIT> , offset , size , addr ) ; if ( mmap_addr == addr ) break ; if ( r != <NUM_LIT> ) Sleep ( <NUM_LIT> ) ; } if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , <STR_LIT> ) ; CloseHandle ( mmap_handle ) ; return -


<s> return ( ( vec_double2 ) ( si_shlqbybi ( ( qword ) ( a


<s> static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> bool <ISA_LIT>TargetMachine :: getEnableTailMergeDefault


<s> if ( Ty . isScalar ( ) ) { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) { Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; } } Val = MIRBuilder . buildBitcast ( VTy , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( VTy , Val ) ; Register HSum = CTPOP . getReg ( <NUM_LIT> ) ; unsigned Opc ; SmallVector < LLT > HAddTys ; if ( Ty . isScalar ( ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: scalar ( <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder UADD ; for ( LLT HTy : HAddTys ) { UADD = MIRBuilder . buildIntrinsic ( Opc , { HTy } , false ) . addUse ( HSum ) ; HSum = UADD . getReg ( <NUM_LIT> ) ; } if ( Ty . isScalar ( ) && Size == <NUM_LIT> ) MIRBuilder . buildZExt


<s> void aarch64_asm_output_alias ( FILE * stream , const tree decl , const tree target ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; const char * value =


<s> return ( __m64 ) __builtin_arm_waddsubhx ( ( __v4hi ) a ,


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm


<s> unsigned <ISA_LIT>TTIImpl :: getPrefetchDistance ( ) const { return <NUM_LIT>


<s> MCContext & OutContext = OutStreamer -> getContext ( ) ; MCSymbol * EPMarkerSym = OutContext . createTempSymbol ( <STR_LIT> , true ) ; const MachineFrameInfo & MFFrame = MF -> getFrameInfo ( ) ; bool IsUsingAlloca = MFFrame . hasVarSizedObjects ( ) ; uint8_t Flags = <NUM_LIT> ; if ( IsUsingAlloca ) Flags |= <NUM_LIT> ; uint32_t DSASize = MFFrame . getStackSize ( ) ; uint32_t DSAAndFlags = DSASize & <NUM_LIT> ; DSAAndFlags |=


<s> OPCODE ( POPCNT ) ; OPCODE ( UMUL_LOHI ) ; OPCODE ( SDIVREM ) ; OPCODE ( UDIVREM ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS )


<s> rtx gen_cmp_fp ( enum rtx_code code , rtx operand0


<s> return ( __m512 ) __builtin_ia32_loadaps512_mask ( ( const __v16sf * ) __P ,


<s> void setVarArgsFPRSize ( unsigned Size ) { VarArgsFPRSize =


<s> unsigned DstReg = LEA . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & AddrDisp = LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) ; return SrcReg == DstReg && LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && AddrDisp . isImm ( ) && ( AddrDisp . getImm ( ) == <NUM_LIT> || AddrDisp . getImm


<s> assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -=


<s> if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand (


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! x86_64_immediate_operand ( src ,

GET_MODE ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ;


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value


<s> if ( MO . isReg ( ) ) return II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Reloc = ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> case IES_PLUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; }


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF


<s> if ( Op . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG ,


<s> static SDValue lowerVectorShuffleAsInsertPS ( const SDLoc & DL , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask ,


<s> return ( __m256i ) __builtin_ia32_broadcasti32x2_256_mask ( ( __v4si ) __A ,


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> perm . length ( ) ; if ( BYTES_BIG_ENDIAN ) return


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool UseSet = MAI -> hasSetDirective ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JTSets ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; bool isNew = JTSets . insert ( MBB ) ; if ( UseSet && isNew


<s> const char * Repl = StringSwitch < const char * > ( Op . getToken ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( Repl ) { MCInst Inst ; Inst . setOpcode (


<s> raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Subtarget -> is32Bit ( ) && Subtarget -> isTargetWindowsMSVC ( ) && ( Subtarget -> getCPU ( ) . empty ( ) || Subtarget -> getCPU ( ) == <STR_LIT> ) ) { OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT>

) . addReg ( <STR_LIT> ) , * Subtarget ) ;


<s> unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getBitcast ( ShVT , SrcOp ) ; MVT ScalarShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) ; assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getConstant ( NumBits / <NUM_LIT> , dl , ScalarShiftTy ) ; return DAG . getBitcast ( VT , DAG . getNode ( Opc , dl , ShVT , SrcOp ,


<s> bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : <NUM_LIT> ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( isDestroy && blockEndIsUnreachable ( MBB , I ) ) return I ; if ( ! reserveCallFrame ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I


<s> return MO . isReg ( ) && MO . getReg ( )

&& Class -> contains ( MO . getReg ( ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( Opc , dl , N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) , N ->

getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == <NUM_LIT> ) &&


<s> const struct insn_operand_data * insn_op ; int idx ; if ( arg == error_mark_node ) return NULL_RTX ; arg_count ++ ; idx = arg_count - ! nonvoid ; insn_op = & insn_data [ icode ] . operand [ idx ] ; op [ arg_count ] = expand_normal ( arg ) ; if ( ( code >= SPARC_BUILTIN_FIRST_FPCMPSHL && code <= SPARC_BUILTIN_LAST_FPCMPSHL && arg_count == <NUM_LIT> ) || ( code >= SPARC_BUILTIN_FIRST_DICTUNPACK && code <= SPARC_BUILTIN_LAST_DICTUNPACK && arg_count == <NUM_LIT> ) ) { if ( ! check_constant_argument ( icode , idx , op [ arg_count ] ) ) return const0_rtx ; } if ( code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR ) { if ( ! address_operand ( op [ arg_count ] , SImode ) ) { op [ arg_count ] = convert_memory_address ( Pmode , op [ arg_count ] ) ; op [ arg_count ] = copy_addr_to_reg ( op [ arg_count ] ) ; } op [ arg_count ] = gen_rtx_MEM ( SImode , op [ arg_count ] ) ; } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ; } switch ( arg_count ) { case <NUM_LIT>


<s> cum -> ints = <NUM_LIT> ; for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : <NUM_LIT> ; param != ( tree ) <NUM_LIT> ; param


<s> void <ISA_LIT>InstPrinter :: printAM2PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O <<


<s> if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_WRITE ) smclass = <NUM_LIT> ; else smclass = <NUM_LIT> ; fprintf ( asm_out_file , <STR_LIT> , ( flags & SECTION_CODE ) ? <STR_LIT> : <STR_LIT> , name , suffix [ smclass


<s> } if ( CM == CodeModel :: Default ) { Triple T ( TT ) ; if ( ! T . isOSDarwin ( ) && ( T . getArch ( ) == Triple :: ppc64 || T . getArch ( ) ==

Triple :: ppc64le ) ) CM = CodeModel :: Medium ;


<s> case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; else return CSR_64_AllRegs_SaveList ; } else


<s> case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } if ( OpcodeTablePtr ) { DenseMap < unsigned * , std :: pair < unsigned , unsigned > > :: const_iterator I = OpcodeTablePtr -> find ( ( unsigned * ) Opc ) ; if ( I != OpcodeTablePtr -> end ( ) ) return true ; } return TargetInstrInfoImpl :: canFoldMemoryOperand (


<s> if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand ( <NUM_LIT> ) ; SDValue U1 = U -> getOperand ( <NUM_LIT> ) ; if ( U0 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U0 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } if ( U1 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U1 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } } break ; } case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI ,


<s> if ( ! isTypeLegal ( I -> getType ( ) , DestVT ) || DestVT . isVector ( ) ) return false ; assert ( ( DestVT == <STR_LIT> || DestVT == <STR_LIT> ) && <STR_LIT> ) ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = EmitIntExt ( SrcVT . getSimpleVT ( ) , SrcReg , <STR_LIT> , ! Signed ) ; if ( SrcReg == <NUM_LIT> ) return false ; } MRI . constrainRegClass ( SrcReg , SrcVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; UpdateValueMap ( I , ResultReg )


<s> unsigned Idx = ( i < <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Idx += Locs [ i ] . first * <NUM_LIT> + Locs [ i ] . second ; Mask2 [ i ] = Idx ; } return DAG . getVectorShuffle ( VT , dl , V1 , V1 , & Mask2 [ <NUM_LIT> ] ) ; } if ( NumLo == <NUM_LIT> || NumHi == <NUM_LIT> ) { if ( NumHi == <NUM_LIT> ) { CommuteVectorShuffleMask ( PermMask , <NUM_LIT> ) ; std :: swap ( V1 , V2 ) ; } unsigned HiIndex ; for ( HiIndex = <NUM_LIT> ; HiIndex < <NUM_LIT> ; ++ HiIndex ) { int Val = PermMask [ HiIndex ] ; if ( Val < <NUM_LIT> ) continue ; if ( Val >= <NUM_LIT> ) break ; } Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ^ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; if ( HiIndex >= <NUM_LIT> ) { Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } int LoMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int * MaskPtr


<s> unsigned <ISA_LIT>AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opcode = Inst . getOpcode (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHMachineFrame (


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qidi ( ( int64x1_t


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF


<s> SDValue Addr = N -> getOperand ( AddrOpIdx ) ; SmallVector < BaseUpdateUser , <NUM_LIT> > BaseUpdates ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) || User -> getNumOperands ( ) != <NUM_LIT> ) continue ; SDValue Inc = User -> getOperand ( UI . getOperandNo ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned ConstInc = getPointerConstIncrement ( User -> getOpcode ( ) , Addr , Inc , DCI . DAG ) ; if ( ConstInc || User -> getOpcode ( ) == <STR_LIT> ) BaseUpdates . push_back ( { User , Inc , ConstInc } ) ; } SDValue Base ; SDValue CInc ; if ( findPointerConstIncrement ( Addr . getNode ( ) , & Base , & CInc ) ) { unsigned Offset = getPointerConstIncrement ( Addr -> getOpcode ( ) , Base , CInc , DCI . DAG ) ; for ( SDNode :: use_iterator UI = Base -> use_begin ( ) , UE =


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup < MVT > ( NEONShuffleTbl , array_lengthof ( NEONShuffleTbl ) , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx


<s> void addAM2OffsetImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE ->


<s> unsigned Binary = <NUM_LIT> ; RegM = II -> getRegisterInfo ( ) . getEncodingValue ( RegM ) ; Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return Binary


<s> virtual const TargetFrameLowering * getFrameLowering


<s> SDValue NextPtr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , DL ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , DL , NextPtr , VAListPtr , MachinePointerInfo ( SV ) ) ; return DAG . getLoad ( VT , DL , InChain , VAList , MachinePointerInfo ( ) , std :: min ( PtrVT . getFixedSizeInBits ( ) , VT . getFixedSizeInBits (


<s> if ( AlwaysBasePointer ) return true ; return needsStackRealignment (


<s> d . one_vector_p = ( which != <NUM_LIT> ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence ( ) ; ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return


<s> MVT VT = Ext -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; MVT WideVT = Ext -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT SelVT = Sel . getSimpleValueType ( ) ; unsigned SelElts = SelVT . getVectorNumElements ( ) ; unsigned CastedElts = WideVT . getVectorNumElements ( ) ; unsigned ExtIdx = cast < ConstantSDNode > ( Ext -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( SelElts % CastedElts == <NUM_LIT> ) { ExtIdx *= ( SelElts / CastedElts ) ; } else if ( CastedElts % SelElts == <NUM_LIT> ) { unsigned IndexDivisor = CastedElts / SelElts ; if ( ExtIdx % IndexDivisor != <NUM_LIT> ) return SDValue ( ) ; ExtIdx /= IndexDivisor ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NarrowingFactor = WideVT . getSizeInBits (


<s> static DecodeStatus DecodeVRRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst ,


<s> unsigned common = dv -> getCommonDomains ( available ) ; if ( dv -> isCollapsed ( ) ) { if ( common ) available = common ; } else if ( common ) used . push_back ( rx ) ; else Kill ( rx ) ; } } if ( isPowerOf2_32 ( available ) ) { unsigned domain = CountTrailingZeros_32 ( available ) ; TII -> SetSSEDomain ( mi , domain ) ; visitHardInstr ( mi , domain ) ; return ; } SmallVector < DomainValue * , <NUM_LIT> > doms ; for ( SmallVector < int , <NUM_LIT> > :: iterator i = used . begin ( ) , e = used . end ( ) ; i != e ; ++ i ) { int rx = * i ; DomainValue * dv = LiveRegs [ rx ] ; if ( ! dv -> getCommonDomains ( available ) ) { Kill ( * i ) ; continue ; } bool inserted = false ; for ( SmallVector < DomainValue * , <NUM_LIT> > :: iterator i = doms . begin ( ) , e = doms . end ( ) ; i != e && ! inserted ; ++ i ) { if ( dv == * i ) inserted = true ; else if ( dv -> Dist < ( * i ) -> Dist ) { inserted = true ; doms . insert ( i , dv ) ; } } if ( ! inserted ) doms . push_back ( dv ) ; } DomainValue * dv = <NUM_LIT> ; while ( ! doms . empty ( ) ) { if ( ! dv ) { dv = doms . pop_back_val ( ) ; continue ; } DomainValue * latest = doms . pop_back_val ( ) ; if ( Merge ( dv , latest ) ) continue ; for ( SmallVector < int , <NUM_LIT> > :: iterator i = used . begin ( ) , e = used . end ( ) ; i != e ; ++ i ) if ( LiveRegs [ * i ] == latest ) Kill ( * i ) ; } if ( ! dv ) dv = Alloc ( ) ; dv -> Dist = Distance ; dv -> AvailableDomains = available ; dv -> Instrs . push_back ( mi ) ; for ( unsigned i = <NUM_LIT> , e = mi -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & mo = mi -> getOperand ( i ) ; if ( ! mo . isReg ( ) ) continue ; int rx = RegIndex ( mo . getReg ( ) ) ; if ( rx < <NUM_LIT> ) continue ; if ( ! LiveRegs || ! LiveRegs [ rx ] || ( mo .

isDef ( ) && LiveRegs [ rx ] != dv ) ) {


<s> if ( ! MFI . isCalleeSavedInfoValid ( ) ) return false ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( auto & CS : CSI ) { if ( <STR_LIT> . contains ( CS . getReg ( ) ) || <STR_LIT> . contains ( CS . getReg ( ) ) ) { assert ( ( Max == std :: numeric_limits < int > :: min ( ) || Max + <NUM_LIT> == CS . getFrameIdx ( ) ) && <STR_LIT> ) ; Min = std :: min ( Min , CS . getFrameIdx ( ) ) ; Max = std :: max ( Max , CS .


<s> uint64_t OriginalValue = CE -> getValue ( ) ; uint64_t InvertedValue = OriginalValue ^ ( ( ( uint64_t ) <NUM_LIT>


<s> return ( int32x4_t ) __builtin_aarch64_ashlv4si ( __a ,


<s> const MCOperand & MO3 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT>


<s> MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent ( ) ; return NextI


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return ( ( regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_POINTER_REGISTER ) || regno == FRAME_POINTER_REGNUM || regno


<s> MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ; TransferImpOps ( MI , MIB , MIB ) ; MI . eraseFromParent ( )


<s> AFI -> setStackSizeSVE ( alignTo ( SVEStackSize , <NUM_LIT> ) ) ; AFI -> setMinMaxSVECSFrameIndex ( MinCSFrameIndex , MaxCSFrameIndex ) ; if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; int UnwindHelpFI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlockEnd ( MBB ) ; RS -> backward ( std :: prev ( MBBI ) ) ; unsigned DstReg = RS -> FindUnusedReg ( &


<s> static const char * getName ( ) { return DEBUG_TYPE


<s> FunctionPass * llvm :: createCleanupLocalDynamicTLSPass ( ) { return new LDTLSCleanup (


<s> assert ( ( ! TT . isOSAIX ( ) || ! RM . hasValue ( ) || * RM == Reloc :: PIC_ ) && <STR_LIT> ) ; if ( RM . hasValue ( ) ) return * RM ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . isOSAIX


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL

== CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ;


<s> if ( ! Op . getImm ( ) -> evaluateAsAbsolute ( Res ) || Res > <NUM_LIT> ) { Error ( Op . getStartLoc ( ) , <STR_LIT> ) ; return false


<s> const int single_width = mode == DImode ? <NUM_LIT> : <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { ( mode == DImode ? split_di : split_ti ) ( operands , <NUM_LIT> , low , high ) ; count = INTVAL ( operands [ <NUM_LIT> ] ) & ( single_width * <NUM_LIT> - <NUM_LIT> ) ; if ( count >= single_width ) { emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; if ( count > single_width ) emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - single_width ) ) ) ; } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ( mode == DImode ? split_di : split_ti ) ( operands , <NUM_LIT> , low , high ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { ix86_expand_clear ( scratch ) ; emit_insn ( ( mode == DImode ? gen_x86_shift_adj_1 : gen_x86_64_shift_adj ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , scratch ) ) ; } else emit_insn ( gen_x86_shift_adj_2 ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ,


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC

) || <STR_LIT> . hasSubClassEq ( & RC ) ) return getRegBank ( <STR_LIT> ) ;


<s> vld1q_u16 ( const uint16_t * __a ) { return ( uint16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi


<s> if ( TARGET_SOFT_FLOAT && ( TARGET_LDRD || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return true ; switch ( code ) { case ARM_POST_INC : case ARM_PRE_DEC : if ( VECTOR_MODE_P ( mode ) ) { if ( code != ARM_PRE_DEC ) return true ; else return false ; } return true ; case


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT


<s> assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM ==


<s> if ( TT . isOSBinFormatMachO ( ) ) return llvm :: make_unique < <ISA_LIT>_MachoTargetObjectFile > ( ) ; return llvm :: make_unique <


<s> if ( ! NeedsStackRealignment && MFI -> getMaxAlignment ( ) > getStackAlignment ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI -> getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI -> getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = RoundUpToAlignment ( NumBytes , MFI -> getMaxAlignment ( ) ) ; } MFI -> setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; unsigned regFP = RegInfo . getDwarfRegNum


<s> void <ISA_LIT>ConstantPoolMBB :: addSelectionDAGCSEId ( FoldingSetNodeID &


<s> NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I


optimize_call_stack ) set_callers_may_not_allocate_frame ( fn ) ;


<s> if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return SH_DYNAMIC_SHIFT_COST ; int value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST )

cost = <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ;


<s> return isMemDisp12 ( BDMem , GR64Reg


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , MI , DL , LII . get ( <STR_LIT> ) , Dst ) . addReg ( Src )


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , OS ( dyn_cast < <ISA_LIT>AsmStreamer > ( & Streamer ) -> getOStream ( ) ) , MCInstLowering ( * this ) { GlobalHeap . push_back ( <NUM_LIT> ) ; Subtarget = & TM . getSubtarget <


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT>


<s> const struct cpu_table * cpu ; unsigned int i ; int fpu ; if ( sparc_debug_string != NULL ) { const char * q ; char * p ; p = ASTRDUP ( sparc_debug_string ) ; while ( ( q = strtok ( p , <STR_LIT> ) ) != NULL ) { bool invert ; int mask ; p = NULL ; if ( * q == '!' ) { invert = true ; q ++ ; } else invert = false ; if ( ! strcmp ( q , <STR_LIT> ) ) mask = MASK_DEBUG_ALL ; else if ( ! strcmp ( q , <STR_LIT> ) ) mask = MASK_DEBUG_OPTIONS ; else error ( <STR_LIT> , q ) ; if ( invert ) sparc_debug &= ~ mask ; else sparc_debug |= mask ; } } if ( TARGET_DEBUG_OPTIONS ) { dump_target_flags ( <STR_LIT> , target_flags ) ; dump_target_flags ( <STR_LIT> , target_flags_explicit ) ; } SUBTARGET_OVERRIDE_OPTIONS ; if ( ! TARGET_64BIT != DEFAULT_ARCH32_P ) error ( <STR_LIT> , DEFAULT_ARCH32_P ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_ARCH64 && ! TARGET_LONG_DOUBLE_128 ) { error ( <STR_LIT> ) ; target_flags |= MASK_LONG_DOUBLE_128 ; } sparc_cmodel = SPARC_DEFAULT_CMODEL ; if ( TARGET_ARCH32 ) sparc_cmodel = CM_32 ; if ( sparc_cmodel_string != NULL ) { if ( TARGET_ARCH64 ) { for ( cmodel = & cmodels [ <NUM_LIT> ] ; cmodel -> name ; cmodel ++ ) if ( strcmp ( sparc_cmodel_string , cmodel -> name ) == <NUM_LIT> ) break ; if ( cmodel -> name == NULL ) error ( <STR_LIT> , sparc_cmodel_string ) ; else sparc_cmodel = cmodel -> value ; } else error ( <STR_LIT> ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! call_used_regs [ i ] ) { error ( <STR_LIT> ) ; call_used_regs [ i ] = <NUM_LIT> ; } fpu = target_flags & MASK_FPU ; if ( ! global_options_set . x_sparc_cpu_and_features ) { for ( def = & cpu_default [ <NUM_LIT> ] ; def -> cpu != - <NUM_LIT> ; ++ def ) if ( def -> cpu == TARGET_CPU_DEFAULT ) break ; gcc_assert ( def -> cpu != - <NUM_LIT> ) ; sparc_cpu_and_features = def -> processor ; } if ( ! global_options_set . x_sparc_cpu ) sparc_cpu = sparc_cpu_and_features ; cpu = & cpu_table [ ( int ) sparc_cpu_and_features ] ; if ( TARGET_DEBUG_OPTIONS ) { fprintf ( stderr , <STR_LIT> , cpu -> name ) ; fprintf ( stderr , <STR_LIT> , cpu_table [ ( int ) sparc_cpu ] . name ) ; dump_target_flags ( <STR_LIT> , cpu -> disable ) ; dump_target_flags ( <STR_LIT> , cpu -> enable ) ; } target_flags &= ~ cpu -> disable ; target_flags |= ( cpu -> enable & ~ ( MASK_FMAF | MASK_VIS3 ) & ~ MASK_CBCOND & ~ ( MASK_VIS4 | MASK_SUBXC ) & ~ ( MASK_LEON | MASK_LEON3 ) ) ; if ( target_flags_explicit & MASK_FPU ) target_flags = ( target_flags & ~


<s> } RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128ToCall ( Op , DAG , LC


<s> continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr ::


<s> int Push = is64 ? <STR_LIT> : <STR_LIT> ; int Pop = is64 ? <STR_LIT> : <STR_LIT> ; int AX = is64 ? <STR_LIT> : <STR_LIT> ; if ( ( FromEFLAGS || ToEFLAGS ) && ( is32 || is64 ) && Subtarget . isTargetNaCl ( ) ) { BuildMI ( MBB , MI , DL , get ( Push ) ) . addReg ( AX ) ; if ( FromEFLAGS ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( Mov ) , Reg ) . addReg ( AX ) ; } if ( ToEFLAGS ) { BuildMI ( MBB , MI , DL , get ( Mov ) , AX ) . addReg ( Reg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; } BuildMI ( MBB , MI , DL , get ( Pop ) , AX ) ; return ; } if ( SrcReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } } if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains (


<s> if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN


<s> StringRef getPassName ( ) const override { return


<s> int64_t Imm = MI -> getOperand ( Op ) . getImm ( ) ; assert ( ( Imm & <NUM_LIT> ) == Imm ) ; printSSEAVXCC ( Imm , O


<s> case TLS_MODEL_LOCAL_DYNAMIC : insns = csky_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , addend ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp ,


<s> CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue S2F = DAG . getBitcast ( <STR_LIT> , Sub ) ; SDValue Shuffle = getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , S2F , <NUM_LIT> , DAG ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Shuffle )


<s> bool isMemDisp12 ( RegisterKind RegKind , bool HasIndex ) const { return isMem ( RegKind , HasIndex ) && inRange ( Mem . Disp ,


<s> if ( regno >= LOC_REG ( <NUM_LIT> ) && regno < LOC_REG ( <NUM_LIT> - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( <NUM_LIT> ) + <NUM_LIT> ) current_frame_info . n_local_regs = regno - LOC_REG ( <NUM_LIT> ) + <NUM_LIT> ; else if ( crtl -> is_leaf && regno >= GR_REG ( <NUM_LIT> ) && regno <= GR_REG ( <NUM_LIT> ) ) current_frame_info . gr_used_mask |= <NUM_LIT> << regno ; return regno


<s> case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false


<s> unsigned getCalleeSavedXMMFrameInfo ( int & origin )


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; } AsmTransCBE = x86_asm_table ; AssemblerDialect =


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128Call ( Op , DAG ,


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address ,


<s> Imm = Vs & <NUM_LIT> ; u = Imm | ( Imm << <NUM_LIT> ) ; if ( Vs == u ) return ( ( ( Vs == V

) ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | Imm ;


<s> bool FixupBWInstPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! FixupBWInsts || skipFunction ( MF . getFunction ( ) ) ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; OptForSize = MF . getFunction ( ) . optForSize ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; LiveRegs . init ( TII -> getRegisterInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> RegN = get<ISA_LIT>RegisterNumbering ( RegN ) ; Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegN >> <NUM_LIT> ) &


<s> for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , AA ) ) return true ; return false


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , DemandedElts , Mask , Inputs , DAG , Depth ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs , Mask ) ; return


<s> default : break ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) encoding = name [ <NUM_LIT> ] ; else encoding = <NUM_LIT> ; if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) mep_unique_section ( decl , <NUM_LIT> ) ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) { if ( encoding == 'f' ) return vftext_section ; else return vtext_section ; } else if ( encoding == 'f' ) return ftext_section ; else return text_section ; } if ( TREE_CODE ( decl ) == VAR_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) switch ( name [ <NUM_LIT> ] ) { case 'b' : return based_section ; case 't' : if ( readonly ) return srodata_section


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags &


<s> continue ; } unsigned Domain = MCID . TSFlags & <STR_LIT> ; if ( Domain == <STR_LIT> ) { if ( ++ Skip == <NUM_LIT> ) pushStack ( nullptr ) ; } else { Skip = <NUM_LIT> ; unsigned MulOpc , AddSubOpc ; bool NegAcc , HasLane ; if ( ! TII -> isFpMLxInstruction ( MCID . getOpcode ( ) , MulOpc , AddSubOpc , NegAcc , HasLane ) || ! FindMLxHazard ( MI ) ) pushStack ( MI ) ; else { ExpandFPMLxInstruction ( MBB , MI , MulOpc , AddSubOpc , NegAcc , HasLane ) ; Changed = true ; } } } return Changed


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ]


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * PtrOp = II . getOperand ( <NUM_LIT> ) ; Value * VecPtr = Builder . CreateBitCast ( PtrOp , VecOp -> getType ( ) -> getPointerTo ( ) ) ; if ( isAllActivePredicate ( Pred ) ) { Builder . CreateStore ( VecOp , VecPtr ) ; return IC . eraseInstFromFunction (


<s> if ( Shuffle . getOpcode ( ) != <STR_LIT> ) { CurOp = PreOp . getOperand ( <NUM_LIT> ) ; Shuffle = PreOp . getOperand ( <NUM_LIT> ) ; if ( Shuffle . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } if ( CurOp . getOpcode ( ) != Op && ( CurStep != ( NumExpectedSteps - <NUM_LIT> ) ) ) return SDValue ( ) ; if ( Shuffle . getOperand ( <NUM_LIT> ) != CurOp ) return SDValue ( ) ; int NumMaskElts = <NUM_LIT> << CurStep ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( Shuffle ) -> getMask ( ) ; for ( int i = <NUM_LIT> ; i < NumVecElts ; ++ i ) if ( ( i < NumMaskElts && Mask [ i ] != ( NumMaskElts + i ) ) || ( i >= NumMaskElts && ! ( Mask [ i ] < <NUM_LIT> ) ) ) return SDValue ( ) ; PreOp = CurOp ; } unsigned Opcode ; switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDLoc DL (


<s> static bool isOpcWithIntImmediate ( SDNode * N , unsigned Opc , unsigned & Imm ) { return N -> getOpcode ( ) == Opc && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode


<s> static DecodeStatus DecodeSVCROp ( MCInst & Inst , unsigned Imm , uint64_t Address , const void * Decoder ) { if ( <STR_LIT> ( Imm ) ) { Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success ; } return Fail


<s> for ( const auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) &&


<s> rtx new_base = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( new_base , GEN_INT ( offset


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder


<s> if ( name . startswith ( <STR_LIT> ) ) return true ; if ( name . startswith ( <STR_LIT> ) ) return true ; if ( name . startswith ( <STR_LIT> ) ) return true ; return false


<s> int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; MVT ShiftVT ; SDValue V = V1 ; unsigned Opcode ; int ShiftAmt = matchVectorShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( ShiftAmt < <NUM_LIT>


<s> assert ( User && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case Instruction :: FMul : { if ( User -> getOpcode ( ) != Instruction :: FSub && User -> getOpcode ( ) != Instruction :: FAdd ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * Ty = User -> getOperand ( <NUM_LIT> ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( <STR_LIT> , getValueType ( DL , Ty ) ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } case Instruction :: Load : { LoadInst * LI = cast < LoadInst > ( I ) ; if ( ! LI -> isUnordered


<s> static DecodeStatus DecodeGPR64x8ClassRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Register


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? <STR_LIT>


<s> static void __attribute__ ( ( format ( printf , <NUM_LIT> , <NUM_LIT> ) ) ) bif_diag ( int diagpos , const char * fmt , ... ) { va_list


<s> unsigned RR = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src , false ) ; if ( RR != <NUM_LIT> ) { ResultReg = RR ; return true


<s> __inline__ static unsigned long long sh_media_MCMPGT_W ( unsigned long long mm , unsigned long long


<s> return ( int16x4_t ) __builtin_neon_vld1v4hi ( ( const


<s> return ( __m128i ) __builtin_ia32_pmovuswb256_mask ( ( __v16hi ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , (


<s> switch ( FirstKind ) { case <STR_LIT> :: Test : case <STR_LIT> :: And : return true ; case <STR_LIT> :: Cmp : case <STR_LIT> :: AddSub : return SecondKind == <STR_LIT> :: AB || SecondKind == <STR_LIT> :: ELG ; case <STR_LIT> ::


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token , Ctx ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> Tok . IsSuffix = IsSuffix ; Op -> StartLoc


<s> bool A57ChainingConstraint :: addIntraChainConstraint ( PBQPRAGraph & G , unsigned Rd , unsigned Ra ) { if ( Rd == Ra ) return false ; LiveIntervals & LIs = G . getMetadata ( ) . LIS ; if ( Register :: isPhysicalRegister ( Rd ) || Register :: isPhysicalRegister ( Ra ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: isPhysicalRegister ( Rd ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: isPhysicalRegister ( Ra ) << '\n' ) ; return false ; } PBQPRAGraph :: NodeId node1 = G . getMetadata ( ) . getNodeIdForVReg ( Rd ) ; PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( Ra ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRdAllowed = & G . getNodeMetadata ( node1 ) . getAllowedRegs ( ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRaAllowed = & G . getNodeMetadata ( node2 ) . getAllowedRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; if ( edge == G . invalidEdgeId ( ) ) { const LiveInterval & ld = LIs . getInterval ( Rd ) ; const LiveInterval & la = LIs . getInterval ( Ra ) ; bool livesOverlap = ld . overlaps ( la ) ; PBQPRAGraph :: RawMatrix costs ( vRdAllowed -> size ( ) + <NUM_LIT> , vRaAllowed -> size ( ) + <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; for ( unsigned j = <NUM_LIT> , je = vRaAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRaAllowed ) [ j ] ; if ( livesOverlap && TRI -> regsOverlap ( pRd , pRa ) ) costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) ; else costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = haveSameParity ( pRd , pRa ) ? <NUM_LIT> : <NUM_LIT> ; } } G . addEdge ( node1 , node2 , std :: move ( costs ) ) ; return true ; } if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 )


<s> InstructionCost <ISA_LIT>TTIImpl :: getExtendedAddReductionCost ( bool IsMLA , bool IsUnsigned , Type * ResTy , VectorType * ValTy , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; EVT ResVT = TLI -> getValueType ( DL , ResTy ) ; if ( ST -> hasMVEIntegerOps ( ) && ValVT .

isSimple ( ) && ResVT . isSimple ( ) ) {


<s> if ( CondReg == <NUM_LIT> ) return false ; unsigned CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get

( CmpOpc ) ) . addReg ( CondReg ) . addReg ( CondReg ) ) ;


<s> int RetFI = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; RetPtr = DAG . getFrameIndex ( RetFI , PtrVT ) ; Entry . Node = RetPtr ; Entry . Ty = PointerType :: getUnqual ( RetTy ) ; if ( ! Subtarget -> is64Bit ( ) ) Entry . IsSRet = true ; Entry . IsReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty (


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) > <NUM_LIT> ) return TypeSplitVector ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) return TypePromoteInteger ; if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT )


<s> static unsigned DemoteRegTo32 ( unsigned RegIn ) { if ( RegIn == <NUM_LIT> ) return <NUM_LIT> ; unsigned RegOut = get<ISA_LIT>SubSuperRegister ( RegIn , <STR_LIT> , false ) ; assert ( RegOut != <NUM_LIT> ) ; return


<s> const LOHArgs & getArgs ( ) const { return Args


<s> if ( SrcOp1Idx > <NUM_LIT> ) { assert ( ( SrcOp1Idx == <NUM_LIT> || SrcOp1Idx == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & WriteMaskOp = MI -> getOperand ( SrcOp1Idx - <NUM_LIT> ) ; if ( WriteMaskOp . isReg ( ) ) { CS << <STR_LIT> << GetRegisterName ( WriteMaskOp . getReg ( ) ) << <STR_LIT> ; if ( SrcOp1Idx == <NUM_LIT> ) { CS << <STR_LIT> ; } } } CS << <STR_LIT> ; for ( int i = <NUM_LIT> , e = ShuffleMask . size ( ) ; i != e ; ++ i ) { if ( i != <NUM_LIT> ) CS << <STR_LIT> ; if ( ShuffleMask [ i ] == SM_SentinelZero ) { CS << <STR_LIT> ; continue ; } bool isSrc1 = ShuffleMask [ i ] < ( int ) e ; CS << ( isSrc1 ? Src1Name : Src2Name ) << '[' ; bool IsFirst = true ; while ( i != e && ShuffleMask [ i ] != SM_SentinelZero && ( ShuffleMask [ i ] < ( int ) e ) == isSrc1 ) { if ( ! IsFirst ) CS << ',' ; else IsFirst = false ; if ( ShuffleMask [ i ] == SM_SentinelUndef ) CS << <STR_LIT> ; else CS << ShuffleMask [ i ] % ( int ) e ; ++ i ; } CS << ']' ; -- i


<s> static int csky_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int dw ATTRIBUTE_UNUSED ) { if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT ) return <NUM_LIT> ; else if ( recog_memoized ( insn ) >= <NUM_LIT> && recog_memoized ( dep ) >= <NUM_LIT> ) { enum attr_type insn_type = get_attr_type ( insn ) ; if ( CSKY_TARGET_ARCH ( CK803 ) ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ; rtx base = XEXP (


<s> HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & <NUM_LIT> ; if ( ( value != <NUM_LIT> ) && ( ( value & ( value - <NUM_LIT> ) )


<s> else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> ) { if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == '{' && Constraint [ Constraint . size ( ) - <NUM_LIT> ] == '}' ) { if ( Constraint . size ( ) > <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'v' && Constraint [ <NUM_LIT> ] == 's' ) { int VSNum = atoi ( Constraint . data ( ) + <NUM_LIT> ) ; assert ( VSNum >= <NUM_LIT> && VSNum <= <NUM_LIT> && <STR_LIT> ) ; if ( VSNum < <NUM_LIT> ) return std :: make_pair ( <STR_LIT> + VSNum , & <STR_LIT> ) ; return std :: make_pair ( <STR_LIT> + VSNum - <NUM_LIT> , & <STR_LIT> ) ; } if ( Constraint . size ( ) > <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'f' ) { int RegNum = atoi ( Constraint . data ( ) + <NUM_LIT> ) ; if ( RegNum > <NUM_LIT> || RegNum < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return Subtarget . hasSPE ( ) ? std :: make_pair ( <STR_LIT> + RegNum , & <STR_LIT> ) : std :: make_pair ( <STR_LIT> + RegNum , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return Subtarget . hasSPE ( ) ? std :: make_pair ( <STR_LIT> + RegNum , & <STR_LIT> ) : std :: make_pair ( <STR_LIT> + RegNum , & <STR_LIT> ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , <STR_LIT> ,


<s> inline SDValue getImm ( const SDNode * Node , unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , Node


<s> for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; CPUsers . push_back ( CPUser ( I , CPEMI , MaxOffs , NegOk , IsSoImm ) ) ; CPEntry * CPE = findConstPoolEntry ( CPI , CPEMI ) ; assert ( CPE && <STR_LIT> ) ; CPE -> RefCount ++ ; break ; } } if ( isThumb && ! MBB . empty ( ) && MBB . begin ( ) -> getOpcode ( ) == <STR_LIT> &&

( ( Offset % <NUM_LIT> ) != <NUM_LIT> || HasInlineAsm ) ) MBBSize += <NUM_LIT> ;


<s> break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return Subtarget -> hasSVE ( ) ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ! Subtarget -> useSVEForFixedLengthVectors ( ) ) return false ; if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_user_abort ( void * const TM_buff ) { texasru_t texasru = * _TEXASRU_PTR (


<s> return _mm_set_epi16 ( * ( short * ) __P , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short

) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> ) ;


<s> return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute (

Attribute :: SanitizeHWAddress ) , false ) . getBytes ( ) ;


<s> O << <STR_LIT> << CurrentFnName << '\n' ; if ( TAI -> hasDotTypeDotSizeDirective ( ) && ! Subtarget -> isLinux ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT>


<s> MBB -> addSuccessor ( NewBB ) ; MachineFunction :: iterator It = ( MF . end ( ) ) -> getIterator ( ) ; MF . insert ( It , NewBB ) ; NewBB -> insert ( NewBB -> instr_begin ( ) , shadowCMP ) ; MachineInstr * MICFDETECTION = NULL ; if ( I -> getOpcode ( ) == <STR_LIT> ) MICFDETECTION = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( wrongDirectionErrorBB ) ; else if ( I -> getOpcode ( ) == <STR_LIT> ) MICFDETECTION = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( wrongDirectionErrorBB ) ; else I -> dump ( ) ; assert ( MICFDETECTION != NULL ) ; NewBB -> push_back ( MICFDETECTION ) ; MachineInstr * MInop = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; NewBB -> push_back ( MInop ) ; MachineInstr * MIjump = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB

( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc ,


<s> bool cy = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool cz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t simm32 = SignExtend64 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; DecodeStatus status ; if ( cz ) { status = DecodeI64RegisterClass ( MI , sz , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; } if ( cy ) { status = DecodeI64RegisterClass ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( sy ) ) ) ; } MI . addOperand ( MCOperand :: createImm ( simm32 ) ) ; return MCDisassembler


<s> if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG


<s> while ( MF . size ( ) > <NUM_LIT> ) MF . erase ( std :: next ( MF . begin ( ) ) ) ; MachineBasicBlock * CaptureSpec = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MachineBasicBlock * CallTarget = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MCSymbol * TargetSym = MF . getContext ( ) . createTempSymbol ( ) ; MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ; const unsigned CallOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const unsigned RetOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; Entry -> addLiveIn ( Reg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( CallOpc ) ) . addSym ( TargetSym ) ; Entry -> addSuccessor ( CaptureSpec ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) ,


<s> printOperand ( MI , opNum , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI -> getOperand


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! ML ) break ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) ,


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> SmallVector < SDValue , <NUM_LIT> > WideInputs ( Inputs . begin ( ) , Inputs . end ( ) ) ; SmallVector < unsigned , <NUM_LIT> > Offsets ( NumInputs , <NUM_LIT> ) ; unsigned WideSizeInBits = RootSizeInBits ; for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) { SDValue & Src = WideInputs [ i ] ; unsigned & Offset = Offsets [ i ] ; Src = peekThroughBitcasts ( Src ) ; EVT BaseVT = Src . getValueType ( ) ; while ( Src . getOpcode ( ) == <STR_LIT> ) { Offset += Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; } WideSizeInBits = std :: max ( WideSizeInBits , ( unsigned ) Src . getValueSizeInBits ( ) ) ; assert ( ( Offset % BaseVT . getVectorNumElements ( ) ) == <NUM_LIT> && <STR_LIT> ) ; Offset /= BaseVT . getVectorNumElements ( ) ; Offset *= NumMaskElts ; } if ( llvm :: all_of ( Offsets , [ ] ( unsigned Offset ) { return Offset == <NUM_LIT> ; } ) ) return SDValue ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts ] ; } WideMask . append ( ( Scale - <NUM_LIT> ) * NumMaskElts , SM_SentinelUndef ) ; resolveTargetShuffleInputsAndMask ( WideInputs , WideMask ) ; assert ( ! WideInputs . empty ( ) && <STR_LIT> ) ; if ( WideInputs . size ( ) > <NUM_LIT> ) return SDValue ( ) ; Depth += count_if ( Offsets , [ ] ( unsigned Offset ) { return Offset > <NUM_LIT> ; } ) ; SDValue WideRoot = WideInputs . front ( ) . getValueSizeInBits ( ) > WideInputs . back ( ) . getValueSizeInBits ( ) ? WideInputs . front ( ) : WideInputs . back ( ) ; if ( SDValue WideShuffle = combine<ISA_LIT>ShuffleChain ( WideInputs , WideRoot , WideMask , Depth , HasVariableMask ,

AllowVariableCrossLaneMask , AllowVariablePerLaneMask , DAG , Subtarget ) ) {


<s> static DecodeStatus DecodeVM512RegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Address , const void * Decoder ) {


( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ;


<s> int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , <NUM_LIT> ) , false ) ) return true ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX )


<s> SDLoc dl ( Op ) ; StoreSDNode * ST = cast < StoreSDNode > ( Op ) ; SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; MachineMemOperand * MMO = ST -> getMemOperand ( ) ; Value = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) )


<s> assert ( DefMI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; RegMO = & DefMI . getOperand ( <NUM_LIT> ) ; ImmMO = & DefMI . getOperand


<s> static SDValue LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Size -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned <ISA_LIT>Reg =


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill )

) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> return ( __m512i ) __builtin_ia32_pabsw512_mask ( ( __v32hi ) __A , ( __v32hi ) _mm512_setzero_hi ( ) , (