<s> EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) || isUInt < <NUM_LIT> > ( Imm64 ) || ! isRunOfOnes64 ( Imm64 , MB , ME ) || ! N0 . hasOneUse ( ) ) return false ; unsigned SH = <NUM_LIT> - ME ; SDLoc Dl ( N )


<s> if ( TID . isCall ( ) || TID . isTerminator ( ) || TID . hasUnmodeledSideEffects ( ) ) return false ; if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO .


<s> return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , FK_Data_4 ) . Case ( <STR_LIT> , FK_SecRel_4 ) . Case ( <STR_LIT>

, FK_SecRel_2 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> SDValue Eight = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue NewMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , VT , X , Eight ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Srl , NewMask ) ; SDValue ShlCount = DAG . getConstant ( ScaleLog , DL , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , And , ShlCount ) ; InsertDAGNode ( DAG , N , Eight ) ; InsertDAGNode ( DAG , N , Srl ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , And ) ; InsertDAGNode ( DAG , N , ShlCount ) ; InsertDAGNode ( DAG , N , Shl ) ; DAG . ReplaceAllUsesWith ( N , Shl ) ; AM . IndexReg = And


<s> NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true


<s> static SDValue addIPMSequence ( const SDLoc & DL , SDValue CCReg , SelectionDAG & DAG ) { SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCReg ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant ( <NUM_LIT> - <STR_LIT> , DL , <STR_LIT> ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return


<s> Size = <NUM_LIT> ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) { Size = Bytes . size ( ) ; return MCDisassembler :: Fail ; } uint64_t Inst = <NUM_LIT> ; for ( uint64_t I = <NUM_LIT> ; I < Size ; ++ I ) Inst =


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: ChangeSection ( Section


<s> bool isVecListFourQ ( ) const { if ( ! isDoubleSpacedVectorList ( ) ) return false ; return VectorList . Count ==


<s> assert ( MCID . hasOptionalDef ( ) && <STR_LIT> ) ; assert ( MCID . NumOperands == Inst . getNumOperands ( ) && <STR_LIT> ) ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } for ( unsigned I = <NUM_LIT> ; I < MCID . NumOperands ; ++ I ) if ( MCID . OpInfo [ I ] . RegClass == <STR_LIT> ) { if ( ( Inst . getOperand ( I ) . getReg ( ) == <STR_LIT> ) && ! hasV8Ops


<s> unsigned i ; if ( ! ptr ) return ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { if ( ! ptr [ i ] ) break ; free ( ptr [ i ] )


<s> inline bool CC_<ISA_LIT>_32_VectorCallIndirect ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; ArgFlags . setInReg ( )


<s> if ( MemVT == EVT ( ) ) return false ; if ( N . getOpcode ( ) != <STR_LIT> ) return false ; SDValue VScale = N . getOperand ( <NUM_LIT> ) ; if ( VScale . getOpcode ( ) != <STR_LIT> ) return false ; TypeSize TS = MemVT . getSizeInBits ( ) ; int64_t MemWidthBytes = static_cast < int64_t > ( TS . getKnownMinSize ( ) ) / <NUM_LIT> ; int64_t MulImm = cast < ConstantSDNode > ( VScale . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ( MulImm % MemWidthBytes ) !=


<s> <STR_LIT> getRestoreGPRRegs ( ) const { return RestoreGPRRegs


<s> Value * <ISA_LIT>IREmitter :: visitATOMUMIN64_DAG ( const SDNode * N


<s> if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_SSE2 ) ix86_split_stlf_stall_load ( ) ; if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS ) ix86_pad_returns ( ) ; if ( TARGET_FOUR_JUMP_LIMIT ) ix86_avoid_jump_mispredicts


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> bool mayNeedRelaxation ( const MCInst


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation :: Type pType ) const { return ApplyFunctions [ pType ] .


<s> const AsmToken & Tok = Parser . getTok ( ) ; bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT>


<s> if ( ! isa < Constant > ( RHS ) || ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLT ; break ; case CmpInst :: ICMP_SGT : case CmpInst :: ICMP_SLE : if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != APInt ( BW , - <NUM_LIT> , true ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLE ; break ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( LHS ) ; if ( BW == <NUM_LIT> && ! Is64Bit ) SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , SrcIsKill , <STR_LIT> ) ; if ( ( BW < <NUM_LIT> ) && ! IsBitTest ) SrcReg = emitIntExt ( VT , SrcReg , <STR_LIT> , true ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) )

. addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ;


<s> Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT>


<s> StoreSDNode * SD = cast < StoreSDNode > ( Op ) ; EVT MemVT = SD -> getMemoryVT ( ) ; if ( ! Subtarget . systemSupportsUnalignedAccess ( ) && ( SD -> getAlignment ( ) < MemVT . getSizeInBits ( ) / <NUM_LIT> ) && ( ( MemVT == <STR_LIT> ) || ( MemVT == <STR_LIT> ) ) ) return lowerUnalignedIntStore ( SD , DAG , Subtarget . isLittle ( ) ) ; return lowerFP_TO_SINT_STORE ( SD ,


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { --


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ ,

__artificial__ ) ) _readgsbase_u64 ( void ) {


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getNOT ( dl , Y , VT ) ) ; } } if ( VT . is128BitVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDLoc DL ( Op ) ; if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Add , <STR_LIT> ) ; return DAG . getSelect ( DL , VT , Cmp , DAG . getAllOnesConstant ( DL , VT ) , Add ) ; } if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> ,


<s> bool isBGQ ( ) const { return TargetTriple . getVendor (


<s> if ( shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: EpilogTail ) ) { auto * EpilogTailHelper = getOrCreateFrameHelper ( M , MMI , Regs , FrameHelperType :: EpilogTail ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( EpilogTailHelper ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) . copyImplicitOps ( MI ) . copyImplicitOps ( * Return ) ; NextMBBI = std :: next ( Return ) ; Return -> removeFromParent ( ) ; } else if ( shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: Epilog ) ) { auto * EpilogHelper = getOrCreateFrameHelper ( M ,

MMI , Regs , FrameHelperType :: Epilog ) ;


<s> if ( V . getSimpleValueType ( ) . isVector ( ) ) return <STR_LIT> ( V . getNode ( ) ) ; auto * C = dyn_cast < ConstantFPSDNode > ( V ) ; return C && C -> getConstantFPValue ( ) -> isAllOnesValue ( ) ; } ; if ( N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstantFP ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && isAllOnesConstantFP ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ; return SDValue ( )


<s> if ( indirect_return_via_cx ) output_indirect_thunk_function ( indirect_thunk_prefix_none , CX_REG , true ) ; if ( indirect_thunk_needed ) output_indirect_thunk_function ( indirect_thunk_prefix_none , INVALID_REGNUM , false ) ; for ( regno = FIRST_REX_INT_REG ; regno <= LAST_REX_INT_REG ; regno ++ ) { if ( TEST_HARD_REG_BIT ( indirect_thunks_used , regno ) ) output_indirect_thunk_function ( indirect_thunk_prefix_none , regno , false ) ; } for ( regno = FIRST_INT_REG ; regno <= LAST_INT_REG ; regno ++ ) { char name [ <NUM_LIT> ] ; tree decl ; if ( TEST_HARD_REG_BIT ( indirect_thunks_used , regno ) ) output_indirect_thunk_function ( indirect_thunk_prefix_none , regno , false ) ; if ( ! ( pic_labels_used & ( <NUM_LIT> << regno ) ) ) continue ; get_pc_thunk_name ( name , regno ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl ,


<s> if ( ! REG_P ( reg ) || insn == NULL ) return result ; for ( result . insn = insn ; result . insn != NULL ; result . insn = prev_nonnote_insn_bb ( result . insn ) ) { if ( BARRIER_P ( result . insn


<s> if ( vl >= <NUM_LIT> && vl <= <NUM_LIT> ) return aarch64_svpattern ( AARCH64_SV_VL1 + ( vl - <NUM_LIT> ) ) ; if ( vl >= <NUM_LIT> && vl <= <NUM_LIT> && pow2p_hwi ( vl ) ) return aarch64_svpattern ( AARCH64_SV_VL16 + ( exact_log2 ( vl ) - <NUM_LIT> ) ) ; int


<s> return <STR_LIT> ( RegNo , Start , End , true , SMLoc ( ) , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) { if ( ! Size ) { Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT>


<s> void setHighSavedGPR ( unsigned Reg ) { HighSavedGPR =


<s> return DecodeMem ( Inst , insn , Address

, Decoder , true , DecodeFPRegsRegisterClass ) ;


<s> static void fatal ( const char * msg ) { fprintf ( stderr , <STR_LIT> , msg ) ; abort ( )


<s> unsigned Intr = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Intr ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < ThumbTargetMachine > Y ( TheThumbTarget ) ; RegisterAsmInfoFn A ( The<ISA_LIT>Target , createMCAsmInfo ) ; RegisterAsmInfoFn B ( TheThumbTarget , createMCAsmInfo ) ; TargetRegistry :: RegisterCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCodeEmitter ( TheThumbTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterAsmBackend ( TheThumbTarget , create<ISA_LIT>AsmBackend


<s> break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : if ( Subtarget -> isTargetDarwin ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; } else { O << TAI -> getWeakRefDirective ( ) << CurrentFnName << <STR_LIT> ; } break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( AFI -> isThumbFunction ( ) ) { EmitAlignment ( MF . getAlignment ( ) , F , AFI -> getAlign ( ) ) ; O << <STR_LIT> ; O << <STR_LIT> ; if ( Subtarget -> isTargetDarwin ( ) ) O << <STR_LIT> << CurrentFnName ; O << <STR_LIT> ; InCPMode = false ; } else { EmitAlignment ( MF . getAlignment ( ) , F ) ; } O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; if ( Subtarget -> isTargetDarwin ( ) ) { MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; } for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ;


<s> static Optional < Instruction * > instCombineSVEST1 ( InstCombiner & IC , IntrinsicInst & II , const DataLayout & DL ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Value * VecOp = II . getOperand ( <NUM_LIT> ) ; Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * PtrOp = II . getOperand ( <NUM_LIT> ) ; Value * VecPtr = Builder . CreateBitCast ( PtrOp , VecOp -> getType ( ) -> getPointerTo ( ) ) ; if ( isAllActivePredicate ( Pred ) ) { StoreInst * Store = Builder . CreateStore ( VecOp , VecPtr ) ; Store -> copyMetadata ( II ) ; return IC . eraseInstFromFunction (


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr


<s> if ( current_frame_info . r [ reg_save_pr ] != <NUM_LIT> && ( grsave_prev == <NUM_LIT> || current_frame_info . r [ reg_save_pr ] == grsave_prev + <NUM_LIT> ) ) { mask |= <NUM_LIT> ; if ( grsave_prev == <NUM_LIT> ) grsave = current_frame_info . r [ reg_save_pr ] ; } if ( mask && TARGET_GNU_AS ) fprintf ( file , <STR_LIT> , mask , ia64_dbx_register_number ( grsave ) ) ; else fputs ( <STR_LIT> , file ) ; if ( current_frame_info . spill_cfa_off != - <NUM_LIT> ) fprintf ( file , <STR_LIT> , ( long )


<s> AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU )


<s> int8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo


<s> return __builtin_mve_vcvtnq_m_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeFP ( const ConstantFP * CFP , EVT VT ) { const APFloat Val = CFP -> getValueAPF ( ) ; bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { unsigned Opc = is64bit ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addFPImm ( CFP ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( cast <


<s> return ( __m128 ) __builtin_ia32_vcvtph2ps_mask ( ( __v8hi ) __A , ( __v4sf )


<s> rtx sh_optimize_sett_clrt :: const_setcc_value ( rtx pat ) const { if ( GET_CODE ( pat ) == SET && REG_P ( XEXP ( pat , <NUM_LIT> ) ) && REGNO ( XEXP ( pat , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && CONST_INT_P ( XEXP ( pat , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( pat , <NUM_LIT> ) ) == <NUM_LIT> || INTVAL ( XEXP ( pat , <NUM_LIT> ) ) == STORE_FLAG_VALUE ) ) return XEXP ( pat , <NUM_LIT> ) ; else return


<s> bool result = isHomogeneousAggregate ( Ty , Base , Members ) ; DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ) ; return result


<s> else if ( Subtarget -> hasV6Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TEOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV4TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasNEON ( ) && emitFPU ) { if ( Subtarget -> hasVFP4 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasV8FP ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget ->


<s> SDLoc DL ( Load ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL , <STR_LIT> ) , Load -> getChain ( ) } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , DL , VT , <STR_LIT> , Ops ) ; ReplaceUses ( SDValue ( Load , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) ) ; ReplaceNode ( N ,


<s> if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { loongarch_emit_move ( dest , value ) ; return


<s> RegisterTarget < Triple :: shuxi32 > X ( getThe<ISA_LIT>32Target ( )


<s> return ( MO1 . isImm ( ) && MO2 . isImm ( ) ) || ( MO1 . isCPI ( ) && MO2 . isCPI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isJTI ( ) && MO2 . isJTI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isSymbol ( ) && MO2 . isSymbol ( ) && MO1 . getSymbolName ( ) == MO2 . getSymbolName ( ) ) || ( MO1 . isGlobal ( ) && MO2 . isGlobal ( ) && MO1 . getGlobal ( ) == MO2 . getGlobal ( ) ) || ( MO1 . isBlockAddress ( ) && MO2 . isBlockAddress ( ) && MO1 . getBlockAddress ( ) == MO2 . getBlockAddress ( ) )

|| ( MO1 . isMCSymbol ( ) && MO2 . isMCSymbol ( ) && MO1 . getMCSymbol ( ) == MO2 . getMCSymbol ( ) ) ;


<s> memcpy ( have_regs_of_mode , m_old_have_regs_of_mode ,


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineSoImmOpValue ( unsigned SoImm ) { unsigned Binary = ( <STR_LIT> ( SoImm ) >> <NUM_LIT>


<s> MCA . getOrCreateSymbolData ( * GP_Disp ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( )


<s> static DecodeStatus decodeU3ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address ,


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const Function * F = MF -> getFunction ( ) ; static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CalleeSavedRegsIntr [ ] =


<s> Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl ,


<s> if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val != <NUM_LIT> ) return false ; } bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > (


<s> if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) -> setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! IsPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( )


<s> if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= InsertVPTBlocks ( MBB ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> const MachineOperand & MO1 = MI . getOperand ( <NUM_LIT> ) ; assert ( MO1 . isImm ( ) && <STR_LIT> ( MO1 . getImm ( ) ) && <STR_LIT> ) ; unsigned V1 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( &


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> EvaluateAsAbsolute ( TargetAddress ) ) { O << '#' << * Expr ; } else { O << <STR_LIT> ; O . write_hex ( static_cast < uint32_t > ( TargetAddress


<s> I != E ; ++ I ) { if ( Offset < I -> Offset ) { MemOps . insert ( I , MemOpQueueEntry ( Offset , Position , MBBI ) ) ; NumMemOps ++ ; Advance = true ; break ; } else if ( Offset == I -> Offset ) { break ; } } } } } } if ( Advance ) { ++ Position ; ++ MBBI ; } else TryMerge = true ; if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( & <STR_LIT> ) ; RS -> forward ( prior ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( prior ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( prior ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = -


<s> return ( __m512i ) __builtin_ia32_psradi512_mask ( ( __v16si ) __A , __B , (


<s> unsigned <ISA_LIT>CodeEmitter :: getShiftOp ( unsigned Imm ) const { switch ( <STR_LIT> ( Imm ) ) { default : llvm_unreachable (


<s> EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( SDValue ReplacedZeroSplat = replaceZeroVectorStore ( DAG , * S ) ) return ReplacedZeroSplat ; if ( ! Subtarget -> isMisaligned128StoreSlow ( ) ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL (


<s> DebugLoc dl = Node -> getDebugLoc ( ) ; EVT VT = cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , VT , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Zero , Zero , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node )

-> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: Fast : return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : return ( Return ? RetCC_<ISA_LIT>_APCS :


<s> MulCandidate ( Instruction * I , ValueList & lhs , ValueList &


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; result = ( poly8x8_t ) __builtin_aarch64_tbx4v8qi ( ( int8x8_t ) __r , __o , ( int8x8_t ) __idx ) ; return


<s> node = cgraph_node :: get ( fn ) ; gcc_assert ( node != NULL ) ; node_v = node -> function_version ( ) ; gcc_assert ( node_v != NULL ) ; if ( node_v -> dispatcher_resolver != NULL ) return node_v -> dispatcher_resolver ; first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ; default_version_info = first_v ; while ( default_version_info != NULL ) { if ( is_function_default_version ( default_version_info -> this_node -> decl ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node = NULL ; struct cgraph_function_version_info * dispatcher_version_info = NULL ; dispatch_decl = make_dispatcher_decl ( default_node -> decl ) ; dispatcher_node = cgraph_node :: get_create ( dispatch_decl ) ; gcc_assert ( dispatcher_node != NULL ) ; dispatcher_node -> dispatcher_function = <NUM_LIT> ; dispatcher_version_info = dispatcher_node -> insert_new_function_version ( ) ; dispatcher_version_info -> next = default_version_info ; dispatcher_node -> definition = <NUM_LIT> ; it_v = default_version_info ; while ( it_v != NULL ) { it_v -> dispatcher_resolver =


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BSelPass ( * PassRegistry ::


<s> static bool isLiteralsPair ( const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpcode = SecondMI .


<s> if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ; std :: swap ( Operands [ i ] , Operands [ <NUM_LIT> ] ) ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( Operands [ j ] . getOpcode ( ) != <STR_LIT> || Operands [ j ] . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) ; } return SDValue


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty ,


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr >


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> || Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType (


<s> void getAnalysisUsage ( AnalysisUsage &


<s> unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get

( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttribute ( Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack (


<s> } unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : return lowerThreadPointer ( SDLoc ( Op ) , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrsAVX2 ) ; i != e ; ++ i ) if ( ReplaceableInstrsAVX2 [ i

] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrsAVX2 [ i ] ;


<s> SDValue rbit = DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> uint32_t RemainingSize = Flags . getByValSize ( ) ; unsigned ByValAlign = Flags . getByValAlign ( ) ; for ( ; RemainingSize >= <NUM_LIT> && LocMemOffset < <NUM_LIT> * <NUM_LIT> ; Offset += <NUM_LIT> , RemainingSize -= <NUM_LIT> , LocMemOffset += <NUM_LIT> ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; SDValue LoadVal = DAG . getLoad ( <STR_LIT> , dl , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned DstReg = O32IntRegs [ LocMemOffset / <NUM_LIT> ] ; RegsToPass . push_back ( std :: make_pair ( DstReg , LoadVal ) ) ; } if ( RemainingSize == <NUM_LIT> ) return ; if ( LocMemOffset < <NUM_LIT> * <NUM_LIT> ) { assert ( RemainingSize <= <NUM_LIT> && RemainingSize >= <NUM_LIT> && <STR_LIT> ) ; unsigned LoadSize = ( RemainingSize == <NUM_LIT> ? <NUM_LIT> : RemainingSize ) ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; if ( ! isLittle ) LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant (

<NUM_LIT> - LoadSize * <NUM_LIT> , <STR_LIT> ) ) ;


<s> switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT>


<s> EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned LaneSize = NumElts / NumLanes ; unsigned Shift = ( LaneSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask


<s> auto Rdx = DAG . getNode ( Op , DL , VecOp . getSimpleValueType ( ) , VecOp ) ; return DAG . getNode ( <STR_LIT> , DL , ScalarOp . getValueType ( ) , Rdx

, DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } rtx tmp = gen_reg_rtx_and_attrs ( source ) ; rs6000_emit_le_vsx_permute ( tmp , source


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT>


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT>


<s> assert ( ! MI . getFlag ( MachineInstr :: FrameSetup ) || checkFrameSetup ( MBB , MI ) ) ; assert ( ! MI . getFlag ( MachineInstr :: FrameDestroy )


<s> bool Changed = false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC || skipModule ( M ) ) return false ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; auto Iter = ScalarMASSFuncs . find ( Func . getName ( ) ) ; if ( Iter == ScalarMASSFuncs . end ( ) ) continue ; SmallVector < User * , <NUM_LIT> > TheUsers ; for ( auto * User : Func . users ( ) ) TheUsers . push_back ( User ) ; for ( auto * User : TheUsers ) if ( auto * CI = dyn_cast_or_null < CallInst > ( User ) ) { if ( isCandidateSafeToLower ( * CI ) ) Changed |= createScalarMASSCall ( Iter -> second , * CI


<s> EltNum = VT . getVectorNumElements ( ) ; } std :: vector < Constant * > CV ; if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ,

DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ) ) ;


<s> if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) ) { unsigned BaseNum ; BaseNum = MatchRegisterName ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) ; if ( BaseNum != <NUM_LIT> ) { getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: RParen ) ) { getLexer ( ) . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > Off ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; SMLoc E = getLexer ( ) . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( BaseNum , Off -> getImm ( ) , S , E ) ) ; return false ; } } } } else


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer


<s> return ( __m64 ) __builtin_ia32_punpcklwd ( ( __v4hi ) __m1 , (


<s> ClobbersEFLAGS = true ; break ; } } if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig -> getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I


<s> if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? <NUM_LIT> : <NUM_LIT> ; if ( GET_MODE_SIZE ( from ) < mov_size || GET_MODE_SIZE ( to ) < mov_size )


<s> return ( __m128i ) __builtin_ia32_pmovsdb128_mask ( ( __v4si ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 )


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; unsigned V0 = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ]


<s> initSubtargetFeatures ( CPU , FS ) ; return * this


<s> if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable


<s> if ( PR_REGNO_P ( regno ) && ( mode ) == BImode ) return <NUM_LIT> ; if ( ( PR_REGNO_P ( regno ) || GR_REGNO_P ( regno ) ) && mode == CCImode ) return <NUM_LIT> ; if ( FR_REGNO_P ( regno ) && mode == XFmode )


<s> assert ( ! isNoopShuffleMask ( Mask ) && <STR_LIT> ) ; int NumElts = Mask . size ( ) ; int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumLaneElts = NumElts / NumLanes ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi )


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return


<s> bool has<ISA_LIT>4 ( ) const { return STI . getFeatureBits ( ) [


<s> LowerBRCOND ( SDValue Op , SelectionDAG &


<s> labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; } reg = load_tls_operand (


<s> vec_uint4 ahi_inf ; vec_uint4 anan ; vec_uint4 iszero ; vec_uint4 result ; union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) a , ( vec_uint4 ) b ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 )


<s> static SDValue LowerREADCYCLECOUNTER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Results ; SDLoc DL ( Op ) ; getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues (


<s> static const <ISA_LIT>MCExpr * CreateTLSDescLo12 ( const MCExpr * Expr , MCContext


<s> vst1q_s16 ( int16_t * a , int16x8_t b ) { __builtin_aarch64_st1v8hi ( ( __builtin_aarch64_simd_hi * ) a ,


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr >


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget -> isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget -> isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> ,


<s> int OverlapDelta = LdDisp1 - LdDisp2 ; LdDisp2 += OverlapDelta ; StDisp2 += OverlapDelta ; Size2 -= OverlapDelta ; } Size1 = std :: abs ( std :: abs ( LdDisp2 ) - std :: abs ( LdDisp1 ) ) ; buildCopies ( Size1 , LoadInst , LdDisp1 , StoreInst , StDisp1 , LMMOffset , SMMOffset ) ; buildCopies ( Size2 , LoadInst , LdDisp2 , StoreInst , StDisp2 , LMMOffset + Size1 , SMMOffset + Size1 ) ; LdDisp1 = LdDisp2 + Size2 ; StDisp1 = StDisp2 + Size2 ; LMMOffset += Size1 + Size2 ; SMMOffset += Size1 + Size2 ; } unsigned Size3 = ( LdDispImm + getRegSizeInBytes ( LoadInst ) ) - LdDisp1 ; buildCopies ( Size3 , LoadInst , LdDisp1 , StoreInst , StDisp1 , LMMOffset ,


<s> switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned HOST_WIDE_INT const2 = UINTVAL ( si2 ) & mask_32bit ; emit_move_insn ( dest , GEN_INT ( const1 | const2 ) ) ; return ; } if ( CONST_INT_P ( si1 ) ) emit_move_insn ( dest , GEN_INT ( ( UINTVAL ( si1 ) & mask_32bit ) << <NUM_LIT> ) ) ; else { rtx si1_di = gen_rtx_REG ( DImode , regno_or_subregno ( si1 ) ) ; rtx shift_rtx = gen_rtx_ASHIFT ( DImode , si1_di , GEN_INT ( <NUM_LIT> ) ) ; rtx mask_rtx = GEN_INT ( mask_32bit << <NUM_LIT> ) ; rtx and_rtx = gen_rtx_AND ( DImode , shift_rtx , mask_rtx ) ; gcc_assert ( ! reg_overlap_mentioned_p ( dest , si1 ) ) ; emit_insn ( gen_rtx_SET ( dest , and_rtx ) ) ; } gcc_assert ( ! reg_overlap_mentioned_p ( dest , tmp ) ) ; if ( CONST_INT_P ( si2 ) ) emit_move_insn ( tmp , GEN_INT


<s> uint64_t Base = Imm >> <NUM_LIT> ; uint64_t Disp = Imm & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT> ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0


<s> if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF


<s> if ( aarch64_advsimd_struct_mode_p ( mode ) ) return VEC_ADVSIMD | VEC_STRUCT ; if ( aarch64_sve_pred_mode_p ( mode ) ) return VEC_SVE_PRED ; scalar_mode inner = GET_MODE_INNER ( mode ) ; if ( VECTOR_MODE_P ( mode ) && ( inner == QImode || inner == HImode || inner == HFmode || inner == SImode || inner == SFmode || inner == DImode || inner == DFmode ) ) { if ( TARGET_SVE ) { if ( known_eq ( GET_MODE_BITSIZE ( mode ) ,

BITS_PER_SVE_VECTOR ) ) return VEC_SVE_DATA ;


<s> break ; } while ( num_args > <NUM_LIT> && h . mode [ num_args ] == VOIDmode ) num_args -- ; ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ] ] [ h . uns_p [ <NUM_LIT> ] ] ; if ( ! ret_type && h . uns_p [ <NUM_LIT> ] ) ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ] ] [ <NUM_LIT> ] ; if ( ! ret_type ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , name , GET_MODE_NAME ( h . mode [ <NUM_LIT> ] ) ) ; for ( i = <NUM_LIT> ; i < ( int ) ARRAY_SIZE ( arg_type ) ; i ++ ) arg_type [ i ] = NULL_TREE ; for ( i = <NUM_LIT> ; i < num_args ; i ++ ) { int m = ( int ) h . mode [ i + <NUM_LIT> ] ; int uns_p = h . uns_p [ i + <NUM_LIT> ] ; arg_type [ i ] = builtin_mode_to_type [ m ] [ uns_p ] ; if ( ! arg_type [ i ] && uns_p ) arg_type [ i ] = builtin_mode_to_type [ m ] [ <NUM_LIT> ] ; if ( ! arg_type [ i ] ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , name , i , GET_MODE_NAME ( m ) ) ; } builtin_hash_struct * * found = builtin_hash_table -> find_slot ( & h , INSERT ) ; if ( * found == NULL ) { h2 = ggc_alloc < builtin_hash_struct > ( ) ; * h2 = h ; * found = h2 ; h2 -> type = build_function_type_list ( ret_type , arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] , NULL_TREE ) ; } return ( * found


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const { return getSubExpr ( ) -> EvaluateAsRelocatable ( Res


<s> if ( ! IsTailCall ) return IsIndirect ? getBLRCallOpcode ( CallerF ) : ( unsigned ) <STR_LIT> ; if ( ! IsIndirect ) return <STR_LIT> ; if ( CallerF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) )


<s> if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <= HA_MAX_NUM_FLDS ) { if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false


<s> static void DecodeUNPCKHPMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts


<s> if ( ReverseVEXT ) std :: swap ( V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; unsigned WhichResult ; if ( isVTRNMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVUZPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [


<s> case <STR_LIT> : { if ( Op . getResNo ( ) == <NUM_LIT> && ! Op -> hasAnyUseOfValue ( <NUM_LIT> ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnesValue ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt , SDLoc ( Op ) , <STR_LIT> ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits ,

OriginalDemandedElts , Known , TLO , Depth ) ;


<s> PointerSize = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT>


<s> src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; if ( total_bytes < <NUM_LIT> ) { dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode , false ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , NE , NULL , SImode , <NUM_LIT> , byte_mode_loop ) ; return true ; } else if ( total_bytes % <NUM_LIT> == <NUM_LIT> ) { dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m = srcmem ; dstmem_m = dstmem ; nds32_emit_mem_move_block ( start_regno , <NUM_LIT> , & dst_itr_m , &

dstmem_m , & src_itr_m , & srcmem_m , true ) ;


<s> memset ( & empty , <NUM_LIT> , sizeof ( empty ) ) ; return mips_multi_members . safe_push (


<s> SDValue <ISA_LIT>TargetLowering :: LowerNaClTargetArch ( SDValue Op , SelectionDAG & DAG ) const { return DAG . getConstant ( PnaclTargetArchitecture<ISA_LIT>_32 , Op . getValueType ( ) . getSimpleVT


<s> Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE )


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - <NUM_LIT> , [ this ] ( const Function & F ) { const auto & ST = this -> TM

-> getSubtarget < <ISA_LIT>Subtarget > ( F ) ;


<s> void mmix_asm_output_labelref ( FILE * stream , const char * name ) { int is_extern = <NUM_LIT> ; for ( ; ( * name == '@' || * name == '*' ) ; name ++ ) if ( * name == '@' ) is_extern = <NUM_LIT> ; asm_fprintf ( stream , <STR_LIT> , is_extern && TARGET_TOPLEVEL_SYMBOLS ? <STR_LIT>


<s> if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( arm_current_function_pac_enabled_p ( ) ) save_reg_mask |= <NUM_LIT> << IP_REGNUM ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= <NUM_LIT> << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % <NUM_LIT> ) != <NUM_LIT> ) { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( ( save_reg_mask & ( <NUM_LIT> << reg ) ) == <NUM_LIT> ) break ; if ( reg <= <NUM_LIT> ) save_reg_mask |= ( <NUM_LIT> << reg ) ; else { cfun -> machine -> sibcall_blocked = <NUM_LIT> ; save_reg_mask |= ( <NUM_LIT> << <NUM_LIT> ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == <NUM_LIT> ) { reg = thumb_find_work_register ( <NUM_LIT> << <NUM_LIT> ) ; if ( ! call_used_or_fixed_reg_p ( reg ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; } return


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue ( ) ; return ( Value != <NUM_LIT> ) && ( ( Value &


<s> bool enableIndirectBrExpand ( ) const override { return useRetpolineIndirectBranches (


<s> if ( ISD == <STR_LIT> && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { int Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * F = BB -> getParent ( ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; F -> DeleteMachineInstr (


<s> return ( poly8x8_t ) __builtin_aarch64_ld1v8qi ( ( const __builtin_aarch64_simd_qi *


<s> if ( isValidPCRelNode < ConstantPoolSDNode > ( N ) || isValidPCRelNode < GlobalAddressSDNode > ( N ) || isValidPCRelNode < JumpTableSDNode > ( N ) || isValidPCRelNode < BlockAddressSDNode > ( N ) ) return true ; return false


<s> bool isTargetDriverKit ( ) const { return TargetTriple . isDriverKit


<s> return gen_got_load_tls_ld ( Pmode , dest ,


<s> return isUndefOrZero ( Val ) || ( Val


<s> OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand (

<NUM_LIT> ) . getMBB ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) ) ;


<s> for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) setOperationAction ( Op , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> return ( CC == CallingConv :: Fast && GuaranteeTailCalls ) || CC == CallingConv :: Tail || CC ==


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Table , Index ) ; if ( Subtarget -> isThumb2 ( ) || ( Subtarget -> hasV8MBaselineOps ( ) && Subtarget -> isThumb ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Table


<s> case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( )


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> switch ( K ) { case TargetTransformInfo :: RGK_Scalar : return TypeSize :: getFixed ( <NUM_LIT> ) ; case TargetTransformInfo ::


<s> static MCDisassembler * createThumbDisassembler ( const Target & T ) { return new


<s> } switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> const MachineOperand & Op = MI . getOperand ( I ) ; const MCOperandInfo & MCOI = MCID . OpInfo [ I ] ; if ( MCOI . OperandType == MCOI :: OPERAND_MEMORY && ( ( MCOI . RegClass != - <NUM_LIT> && ! Op . isReg ( ) && ! Op . isFI ( ) ) || ( MCOI . RegClass == - <NUM_LIT> && ! Op . isImm ( ) ) ) ) { ErrInfo = <STR_LIT> ; return


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . in<ISA_LIT>16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ?


<s> void emitARM64WinCFIClearUnwoundToCall ( ) override { OS <<


<s> static bool Check ( DecodeStatus & Out , DecodeStatus In ) { switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out =


<s> MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , CS ) ; } if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF ::


<s> continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG ->


<s> bool aarch64_is_long_call_p ( rtx sym ) { return aarch64_decl_is_long_call_p ( SYMBOL_REF_DECL ( sym )


<s> SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG .

getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> SDLoc dl ( N ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , dl , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT>


<s> unsigned <ISA_LIT>BSel :: GetAlignmentAdjustment ( MachineBasicBlock & MBB , unsigned Offset ) { const Align Alignment = MBB . getAlignment ( ) ; if ( Alignment == Align ( <NUM_LIT>


<s> SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT> ) { MCI . setOpcode ( <STR_LIT> ) ; } else { unsigned NopSize = EmitNop ( * OutStreamer , MinSize , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; assert ( NopSize == MinSize && <STR_LIT> ) ; ( void ) NopSize ; } } OutStreamer -> EmitInstruction ( MCI , getSubtargetInfo


<s> return ( __mmask16 ) __builtin_ia32_ptestnmb128 ( ( __v16qi ) __A ,


<s> break ; case INSN : { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return <NUM_LIT> ; if ( rtx_equal_p ( x , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( y && rtx_equal_p ( y , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( reg_overlap_mentioned_p ( SET_DEST ( pat ) , y ) ) return <NUM_LIT> ; } } } return <NUM_LIT>


<s> if ( fi < <NUM_LIT> || fi >= ( int ) GPRCS2Frames . size ( ) ) return false ; return GPRCS2Frames [


<s> if ( ! ShouldUseImm && Pred && IsEqualityPred ( * Pred ) ) { const ConstantFP * LHSImm = getConstantFPVRegVal ( LHS , MRI ) ; if ( LHSImm && ( LHSImm -> isZero ( ) && ! LHSImm -> isNegative ( ) ) ) { ShouldUseImm = true ; std :: swap ( LHS , RHS ) ; } } unsigned CmpOpcTbl [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned CmpOpc = CmpOpcTbl [ ShouldUseImm ] [ OpSize == <NUM_LIT>


<s> assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) .


<s> inline static CondCodes getOppositeCondition ( CondCodes CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return NE ; case NE : return EQ ; case HS : return LO ; case LO : return HS ; case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC :


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( DAG . getSubtarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return


<s> ITCounter = CountITSize ( slice ( bits7_0 , <NUM_LIT> , <NUM_LIT> ) ) ; ITState = bits7_0


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , unsigned ExtraT , MachineBasicBlock &

FMBB , unsigned NumF , unsigned ExtraF , const BranchProbability & Probability ) const {


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs

, const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const {


<s> bool <ISA_LIT>InstrInfo :: hasDisplacementPairInsn ( unsigned Opcode ) const { const MCInstrDesc & MCID = get ( Opcode ) ; if ( MCID . TSFlags & <STR_LIT> ) return <STR_LIT>


<s> unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_MICROMIPS ; MCA . setELFHeaderEFlags ( Flags


<s> gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_arm_store_exclusiveqi ; break ; case E_HImode : gen = gen_arm_store_exclusivehi ; break ; case E_SImode : gen = gen_arm_store_exclusivesi ; break ; case E_DImode : gen =


<s> rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; rtx_insn * insn = emit_move_insn ( lr , reg


<s> static inline AddrOpc getAM3Op ( unsigned AM3Opc ) { return ( ( AM3Opc >> <NUM_LIT> ) &


<s> return ( __m128d ) __builtin_ia32_rcp14pd128_mask ( ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) , (


<s> if ( VT . getVectorElementType ( ) != V0 . getValueType ( ) . getVectorElementType ( ) || VT . getVectorElementType ( ) != V1 . getValueType ( ) . getVectorElementType ( ) ) return SDValue ( ) ; bool SplitV0 = V0 . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ; if ( ! isConcatMask ( Mask , VT , SplitV0 ) ) return SDValue ( ) ; EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / <NUM_LIT> ) ; if ( SplitV0 ) { V0 = DAG . getNode ( <STR_LIT> , DL , CastVT , V0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( V1 . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { V1 = DAG . getNode ( <STR_LIT> , DL , CastVT , V1 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL ,


<s> MCAsmParserExtension :: Initialize ( parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; assert ( ( ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr


<s> if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; intoffset /= BITS_PER_UNIT ; do { regno = parms -> regbase + this_slotno ; reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( parms -> ret , <NUM_LIT> , parms -> stack + parms -> nregs ) =

gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ;


<s> if ( GET_MODE_CLASS ( mode ) != MODE_CC ) mode = SELECT_CC_MODE ( comp_code , XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ; return aarch64_get_condition_code_1 ( mode , comp_code )


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( <STR_LIT> ) ; return TargetLowering :: getSDagStackGuard


<s> unsigned N , Opcode ; static std :: map < unsigned , std :: pair < unsigned , unsigned >> IntrinsicMap = { { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } , { <STR_LIT> , { <NUM_LIT> , <STR_LIT> } } } ; std :: tie ( N , Opcode ) = IntrinsicMap [ Intrinsic ] ; assert ( VT . getVectorElementCount ( ) . Min % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / N ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N ,


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno


<s> MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex


<s> bool isWydeH ( ) const { return isLabelImm16 ( )


<s> StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> )


<s> if ( ! TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT ( decl ) ) DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; else DECL_VISIBILITY ( decl ) = VISIBILITY_DEFAULT ; DECL_VISIBILITY_SPECIFIED ( decl


<s> SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi


<s> case CallingConv :: Swift : case CallingConv :: SwiftTail : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : case CallingConv :: Tail : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ; case CallingConv ::


<s> return ( int32x4_t ) __builtin_aarch64_shaddv4si


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address ,

Decoder ) ) ) return MCDisassembler :: Fail ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> )


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_punpcklqdq128 ( ( __v2di


<s> return ( vector signed int ) __builtin_altivec_vsum2sws ( ( vector signed int


<s> return ( __m256d ) __builtin_ia32_scalefpd256_mask ( ( __v4df ) __A , ( __v4df ) __B , ( __v4df ) _mm256_setzero_pd ( ) ,


<s> tree arg ; call_expr_arg_iterator iter ; unsigned attr = rs6000_builtin_info [ fcode ] . attr ; enum insn_code icode = d -> icode ; const struct insn_operand_data * insn_op ; bool uses_spr = ( attr & RS6000_BTC_SPR ) ; rtx cr = NULL_RTX ; if ( uses_spr ) icode = rs6000_htm_spr_icode ( nonvoid ) ; insn_op = & insn_data [ icode ] . operand [ <NUM_LIT> ] ; if ( nonvoid ) { machine_mode tmode = ( uses_spr ) ? insn_op -> mode : E_SImode ; if ( ! target || GET_MODE ( target ) != tmode || ( uses_spr && ! ( * insn_op -> predicate ) ( target , tmode ) ) ) target = gen_reg_rtx ( tmode ) ; if ( uses_spr ) op [ nopnds ++ ] = target ; } FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS ) return const0_rtx ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; op [ nopnds ] = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = ( nonvoid ) ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case HTM_BUILTIN_TENDALL : case HTM_BUILTIN_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; case HTM_BUILTIN_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds +=


<s> Res -> Mem . DefaultBaseReg = DefaultBaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> Mem . FrontendSize = FrontendSize ; Res -> Mem . MaybeDirectBranchDest = MaybeDirectBranchDest ; Res -> UseUpRegs = UseUpRegs ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = false ; return


<s> return ( __m256i ) __builtin_ia32_broadcasti32x2_256_mask ( ( __v4si ) __A , ( __v8si ) _mm256_setzero_si256 ( )


<s> t = build2 ( MODIFY_EXPR , type , gpr , build_int_cst ( type , n_gpr * <NUM_LIT> ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( TARGET_SSE && cfun -> va_list_fpr_size ) { type = TREE_TYPE ( fpr ) ; t = build2 ( MODIFY_EXPR , type , fpr , build_int_cst ( type , n_fpr * <NUM_LIT> + <NUM_LIT> * X86_64_REGPARM_MAX ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } type = TREE_TYPE ( ovf ) ; if ( cfun -> machine -> split_stack_varargs_pointer == NULL_RTX ) ovf_rtx = crtl -> args . internal_arg_pointer ; else ovf_rtx = cfun -> machine -> split_stack_varargs_pointer ; t = make_tree ( type , ovf_rtx ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * UNITS_PER_WORD ) ; if ( chkp_function_instrumented_p ( current_function_decl ) ) chkp_expand_bounds_reset_for_mem ( ovf , t ) ; t = build2 ( MODIFY_EXPR , type , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( ix86_varargs_gpr_size || ix86_varargs_fpr_size ) { type = TREE_TYPE ( sav ) ; t = make_tree ( type , frame_pointer_rtx ) ; if ( ! ix86_varargs_gpr_size ) t = fold_build_pointer_plus_hwi ( t , - <NUM_LIT> * X86_64_REGPARM_MAX ) ; if ( chkp_function_instrumented_p ( current_function_decl ) ) chkp_expand_bounds_reset_for_mem ( sav , t


<s> addPass ( createBreakFalseDeps ( ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( )


<s> machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat )


<s> case MODE_V4DF : return <STR_LIT> ; case MODE_V8SF : return <STR_LIT> ; default : break ; } case <NUM_LIT> : if ( TARGET_AVX512VL || get_attr_mode ( insn ) == MODE_XI || get_attr_mode ( insn ) == MODE_V8DF || get_attr_mode ( insn ) == MODE_V16SF ) return <STR_LIT> ; if ( TARGET_AVX ) return <STR_LIT> ; else return


<s> static bool crx_fixed_condition_code_regs ( unsigned int * p1 , unsigned


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return true ; SMLoc S = getLoc ( ) ; StringRef Kind ; int Reg = - <NUM_LIT> ; OperandMatchResultTy Res = tryParseVectorRegister ( Reg , Kind , RegKind :: NeonVector ) ; if ( Res != MatchOperand_Success ) return true ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: NeonVector ) ; if ( ! KindRes ) return true ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; return tryParseVectorIndex ( Operands )


<s> return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX : case Triple :: Darwin : return Major <


<s> void InsertMul ( Instruction * I , ValueList & LHS , ValueList & RHS ) { Muls . push_back ( make_unique < MulCandidate > ( I ,