<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInline ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; assert ( STI . is64Bit ( ) && <STR_LIT> ) ; assert ( STI . isTargetWindowsCoreCLR ( ) && <STR_LIT> ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = MBB . getBasicBlock ( ) ; MachineBasicBlock * RoundMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * LoopMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * ContinueMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = std :: next ( MBB . getIterator ( ) ) ; MF . insert ( MBBIter , RoundMBB ) ; MF . insert ( MBBIter , LoopMBB ) ; MF . insert ( MBBIter , ContinueMBB ) ; MachineBasicBlock :: iterator BeforeMBBI = std :: prev ( MBBI ) ; ContinueMBB -> splice ( ContinueMBB -> begin ( ) , & MBB , MBBI , MBB . end ( ) ) ; ContinueMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; const int64_t ThreadEnvironmentStackLimit = <NUM_LIT> ; const int64_t PageSize = <NUM_LIT> ; const int64_t PageMask = ~ ( PageSize - <NUM_LIT> ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetRegisterClass * RegClass = & <STR_LIT> ; const unsigned SizeReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , ZeroReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , CopyReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , TestReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , FinalReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , RoundedReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , LimitReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , JoinReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) , ProbeReg = InProlog ? ( unsigned ) <STR_LIT> : MRI . createVirtualRegister ( RegClass ) ; int64_t RCXShadowSlot = <NUM_LIT> ; int64_t RDXShadowSlot = <NUM_LIT> ; if ( InProlog ) { <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const int64_t CalleeSaveSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; const bool HasFP = hasFP ( MF ) ; RCXShadowSlot = <NUM_LIT> + CalleeSaveSize + ( HasFP ? <NUM_LIT> : <NUM_LIT> ) ; RDXShadowSlot = RCXShadowSlot + <NUM_LIT> ; addRegOffset ( BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) , <STR_LIT> , false , RCXShadowSlot ) . addReg ( <STR_LIT> ) ; addRegOffset ( BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) ,

<STR_LIT> , false , RDXShadowSlot ) . addReg ( <STR_LIT> ) ;


<s> bool MVEGatherScatterLowering :: isLegalTypeAndAlignment ( unsigned NumElements , unsigned ElemSize , unsigned Alignment ) { if ( ( ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize ==

<NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ElemSize == <NUM_LIT> ) ) && ElemSize / <NUM_LIT> <= Alignment ) return true ;


<s> else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , <NUM_LIT> ) ; rtx addrop1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) , addrop0 ) ; if ( ! REG_P ( addrop1 ) ) addrop1 = force_reg ( GET_MODE ( addrop1 ) , addrop1 ) ; canon = gen_rtx_PLUS ( GET_MODE ( addr ) ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAdrpLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; unsigned Modifier = <ISA_LIT>MCExpr :: VK_AARCH64_None ; if ( const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) Modifier = Expr -> getKind ( ) ; unsigned FixupKind = <NUM_LIT> ; switch ( Modifier ) { case <ISA_LIT>MCExpr :: VK_AARCH64_None : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_GOT : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL


<s> wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow


<s> void <ISA_LIT>16InstrInfo :: makeFrame ( unsigned SP , int64_t FrameSize , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! NeverUseSaveRestore ) { if ( isUInt < <NUM_LIT> > ( FrameSize ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; else { int Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Base ) ; if ( isInt < <NUM_LIT> > ( - Remainder ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm (


<s> * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != <NUM_LIT> || Alignment <= <NUM_LIT> || Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; } return


<s> tree gimple_folder :: load_store_cookie ( tree type ) { return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN (


<s> return ( vector unsigned char ) __builtin_altivec_vaddubs ( ( vector signed char ) a1 , ( vector signed


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI ) ; return createELFObjectWriter ( MOTW ,


<s> unsigned FrameReg ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) || ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) ) FrameReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isGPFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) ) Offset = spOffset ; else Offset = spOffset + ( int64_t ) stackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; <ISA_LIT>AnalyzeImmediate AnalyzeImm ; unsigned Size = Subtarget . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Offset , Size , true ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; <ISA_LIT>FI -> setEmitNOAT ( ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , TII . get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg

( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;


<s> warning ( <NUM_LIT> , <STR_LIT> , feature ) ; warned_once =


<s> if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) == <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>ConstantPoolSymbol * <ISA_LIT>ConstantPoolSymbol :: Create ( LLVMContext & C , StringRef s , unsigned ID , unsigned char


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoMacro ( ) { OS <<


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols .


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( U ) Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT>


<s> std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ; bool W16AvailableInBlock = LRU . available ( <STR_LIT> ) ; bool W17AvailableInBlock = LRU . available ( <STR_LIT> ) ; bool NZCVAvailableInBlock = LRU . available ( <STR_LIT> ) ; if ( W16AvailableInBlock && W17AvailableInBlock && NZCVAvailableInBlock ) Flags |= MachineOutlinerMBBFlags :: UnsafeRegsDead ; LRU . addLiveOuts ( MBB ) ; if ( W16AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( W17AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( NZCVAvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( any_of ( MBB , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) )

Flags |= MachineOutlinerMBBFlags :: HasCalls ;


<s> if ( VT . isVector ( ) ) return std :: max ( ( ( unsigned ) VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) , <NUM_LIT> ) ; return <ISA_LIT>TargetLowering :: getNumRegisters (


<s> int arm_debugger_arg_offset ( int value , rtx addr ) { rtx insn ; if ( value != <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( addr ) != REG ) return <NUM_LIT> ; if ( REGNO ( addr ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( ( TARGET_THUMB || ! frame_pointer_needed ) && REGNO ( addr ) == SP_REGNUM ) return <NUM_LIT> ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && REGNO ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == REGNO ( addr ) && GET_CODE ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM && GET_CODE ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { value = INTVAL ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; } } if ( value == <NUM_LIT> ) { debug_rtx ( addr )


<s> bool <ISA_LIT>TargetLowering :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { assert ( SrcAS != DestAS


<s> unsigned STReg = getSTReg ( RegNo ) ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; std :: swap ( RegMap [ RegNo ] , RegMap [ RegOnTop ] ) ; assert ( RegMap [ RegOnTop ] < StackTop ) ; std :: swap ( Stack [ RegMap [ RegOnTop ] ] , Stack [ StackTop - <NUM_LIT> ] ) ; BuildMI ( * MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( STReg ) ; ++ NumFXCH


<s> for ( unsigned I = <NUM_LIT> , E = VT . getVectorNumElements ( ) ; I != E ; ++ I ) { SDValue Lane = Op . getOperand ( I ) ; if ( Lane . getOpcode ( ) == <STR_LIT> ) { APInt LowBits ( EltTy . getSizeInBits ( ) , cast < ConstantSDNode > ( Lane ) -> getZExtValue ( ) ) ; Lane = DAG . getConstant ( LowBits . getZExtValue ( ) , dl , <STR_LIT> ) ; } Ops . push_back


<s> getUsefulBits ( Op , Mask , Depth + <NUM_LIT> ) ; Mask = Mask . lshr ( ShiftAmt ) ; } else if ( <STR_LIT> ( ShiftTypeAndValue ) == <STR_LIT> ) { uint64_t ShiftAmt = <STR_LIT> ( ShiftTypeAndValue ) ; Mask = Mask . lshr ( ShiftAmt ) ; getUsefulBits ( Op , Mask , Depth + <NUM_LIT> ) ; Mask = Mask . shl ( ShiftAmt ) ; } else


<s> _cvtmask32_u32 ( __mmask32 __A ) { return ( unsigned int ) __builtin_ia32_kmovd (


<s> inline static unsigned HI22 ( int64_t imm ) { return ( unsigned ) ( ( imm >> <NUM_LIT> ) &

( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ;


<s> if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; else if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; else if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; else if ( ! Options . getABIName ( ) . empty ( ) ) llvm_unreachable ( <STR_LIT> ) ; if ( TT . getArch ( ) == Triple :: mips64 || TT . getArch ( ) ==

Triple :: mips64el ) return <ISA_LIT>ABIInfo :: N64 ( ) ;


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; auto MBBI = MBB . getFirstTerminator ( ) ; bool CanRestoreDirectly = STI . hasV5TOps ( ) && ! ArgRegsSaveSize ; if ( CanRestoreDirectly ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) != <STR_LIT> ) CanRestoreDirectly = ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ; else { auto MBBI_prev = MBBI ; MBBI_prev -- ; assert ( MBBI_prev -> getOpcode ( ) == <STR_LIT> ) ; assert ( MBB . succ_size ( ) == <NUM_LIT> ) ; if ( ( * MBB . succ_begin ( ) ) -> begin ( ) -> getOpcode ( ) == <STR_LIT> ) MBBI = MBBI_prev ; else CanRestoreDirectly = false ; } } if ( CanRestoreDirectly ) { if ( ! DoIt || MBBI -> getOpcode ( ) == <STR_LIT> ) return true ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto MO : MBBI -> operands ( ) ) if ( MO . isReg ( ) && ( MO . isImplicit ( ) || MO . isDef ( ) ) ) MIB . add ( MO ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MBB . erase ( MBBI ) ; return true ; } LivePhysRegs UsedRegs ( STI . getRegisterInfo ( ) ) ; UsedRegs . addLiveOuts ( MBB ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) UsedRegs . addReg ( CSRegs [ i ] ) ; DebugLoc dl = DebugLoc ( ) ; if ( MBBI != MBB . end ( ) ) { dl = MBBI -> getDebugLoc ( ) ; auto InstUpToMBBI = MBB . end ( ) ; while ( InstUpToMBBI != MBBI ) UsedRegs . stepBackward ( * -- InstUpToMBBI ) ; } unsigned PopReg = <NUM_LIT> ; unsigned TemporaryReg =


<s> MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , Copy0MBB ) ; F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) ,


<s> if ( ! isRegInClass ( MO , QPRs ) || ! MO . isUse ( ) || MO . getReg ( ) != DefReg ) continue ; if ( auto * OpDef = RDA . getMIOperand ( & MI , MO ) ) { if ( KnownFalseZeros . count ( OpDef ) ) { KnownFalseZeros . insert ( & MI ) ; break ; } } } if ( ! KnownFalseZeros . count ( & MI ) ) UnknownFalseLanes . insert ( & MI ) ; } auto HasKnownUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Knowns ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Knowns . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( UnknownFalseLanes ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasKnownUsers ( MI , MO , KnownFalseZeros ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; return false ; } } KnownFalseZeros . insert ( MI


<s> if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( )


<s> CurrBase = Base ; CurrOpc = Opcode ; CurrPred = Pred ; MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { bool Overlap = false ; if ( isLoadSingle ( Opcode ) ) { Overlap = ( Base == Reg ) ; if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates (


<s> EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getStore ( ChainIn , DL , Value , Address , MachinePointerInfo ( ) , Align


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false


<s> } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { TmpInst0 . setOpcode ( <STR_LIT> ) ; HasLinkReg = true ; } else if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TmpInst0 . setOpcode ( <STR_LIT> ) ; else { TmpInst0 . setOpcode ( <STR_LIT> ) ; } MCOperand MCOp ; if ( HasLinkReg


<s> return __builtin_mve_vcaddq_rot90_fv8hf ( __a ,


<s> O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ; O << <STR_LIT> << <STR_LIT> ( MO2 . getImm ( )


<s> DebugLoc dl = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ,


<s> return AsmPrinter . MMI -> getObjFileInfo < MachineModuleInfoMachO


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ; if ( SetFlags )


<s> bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12


<s> if ( CC == CallingConv :: GHC ) return nullptr ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( )


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( mm ) , <STR_LIT> ( s ) ,


<s> break ; case 'L' : print_reloc ( file , x , <NUM_LIT> , RKIND_LO ) ; break ; case 'P' : if ( ! flag_pic || SYMBOL_REF_LOCAL_P ( x ) ) output_addr_const ( file , x ) ; else output_addr_reloc ( file , x , <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : switch ( GET_CODE ( operand ) ) { case REG : if ( REGNO ( operand ) > <NUM_LIT> ) internal_error ( <STR_LIT> , REGNO ( operand ) ) ; fprintf ( file , <STR_LIT> , reg_names


<s> auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { auto ToDelete = I ; ++ I ; MBB . erase (


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FrameIdx ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ,

DestReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( MI -> getOperand ( Op + <NUM_LIT> ) . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } printLeaMemReference ( MI , Op ,


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage


<s> static bool vax_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( CONST_INT_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( CONST_INT_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; return


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx (


<s> if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( )


<s> SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Constant * C = ConstantInt :: get ( * DAG . getContext ( ) , APInt :: getAllOnesValue ( ExtVT . getScalarType ( ) . getSizeInBits ( ) ) ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; SDValue Ld = DAG . getLoad ( ExtVT . getScalarType ( ) , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; SDValue Brcst = DAG . getNode ( <STR_LIT> , dl , ExtVT , In


<s> if ( DestVT == <STR_LIT> ) DestVT = Op0 . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID , dl , <STR_LIT> )


<s> unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg


<s> return ( __m512i ) __builtin_ia32_cvtpd2qq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ,


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>_32Target , create<ISA_LIT>_32Disassembler ) ; TargetRegistry :: RegisterMCDisassembler (


<s> if ( isFP64 ( ) ) return MatchOperand_NoMatch ; setFpFormat ( FP_FORMAT_D


<s> switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI . killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . addOperand ( Src ) ; isKill = true ; isUndef =


<s> Target & llvm :: getThe<ISA_LIT>64elTarget (


<s> op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( ! strict && reload_in_progress && ( REG_P ( op0 ) || GET_CODE

( op0 ) == PLUS ) && REG_P ( op1 ) ) return true ;


<s> TotCost += getScalarizationOverhead ( Dst , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( Dst , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ; } return VF + getScalarizationOverhead ( Src , false , true ) ; } } else { assert ( ! Dst -> isVectorTy ( ) ) ; if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) { if ( SrcScalarBits >= <NUM_LIT> || ( I != nullptr && isa < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) return <NUM_LIT> ; return SrcScalarBits > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType


<s> if ( AddrDispShift != <NUM_LIT> ) { if ( MI . isNonListDebugValue ( ) ) { Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; } else { SmallVector < uint64_t , <NUM_LIT> > Ops ; DIExpression :: appendOffset ( Ops , AddrDispShift ) ; for ( MachineOperand & Op : MI . getDebugOperandsForReg ( OldReg ) ) { unsigned OpIdx = MI . getDebugOperandIndex ( & Op ) ; Expr = DIExpression :: appendOpsToArg ( Expr , Ops , OpIdx ) ; } } } MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable ( ) ; unsigned Opcode = MI . isNonListDebugValue ( ) ? TargetOpcode :: DBG_VALUE : TargetOpcode :: DBG_VALUE_LIST ; if ( IsIndirect ) assert ( MI . getDebugOffset ( ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < MachineOperand ,


<s> int monsize ; char * buffer ; register int o ; lowpc = ( char * ) ROUNDDOWN ( ( unsigned long ) lowpc , HISTFRACTION * sizeof ( HISTCOUNTER ) ) ; s_lowpc = lowpc ; highpc = ( char * ) ROUNDUP ( ( unsigned long ) highpc , HISTFRACTION * sizeof ( HISTCOUNTER ) ) ; s_highpc = highpc ; s_textsize = highpc - lowpc ; monsize = ( s_textsize / HISTFRACTION ) + sizeof ( struct phdr ) ; buffer = sbrk ( monsize ) ; if ( buffer == ( char * ) - <NUM_LIT> ) { write ( <NUM_LIT> , MSG , sizeof ( MSG ) ) ; return ; } froms = ( unsigned short * ) sbrk ( s_textsize / HASHFRACTION ) ; if ( froms == ( unsigned short * ) - <NUM_LIT> ) { write ( <NUM_LIT> , MSG , sizeof ( MSG ) ) ; froms = <NUM_LIT> ; return ; } tolimit = s_textsize * ARCDENSITY / <NUM_LIT> ; if ( tolimit < MINARCS ) { tolimit = MINARCS ; } else if ( tolimit > <NUM_LIT> ) { tolimit = <NUM_LIT> ; } tos = ( struct tostruct * ) sbrk ( tolimit * sizeof ( struct tostruct ) ) ; if ( tos == ( struct tostruct * ) - <NUM_LIT>


<s> unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) .


<s> inline const mode_suffix_info & function_instance :: mode_suffix ( ) const { return mode_suffixes [


<s> SMLoc DummyLoc ; if ( ParseRegister ( Reg , DummyLoc , DummyLoc ) || parseEOL (


<s> bool <ISA_LIT>InstPrinter :: printGetPCX ( const MCInst * MI , unsigned opNum , const MCSubtargetInfo & STI , raw_ostream & O ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , Flavour , Flavour


<s> MinSize = <NUM_LIT> ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass (


<s> if ( TARGET_HARD_FLOAT && TARGET_VFP ) { count = <NUM_LIT> ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += <NUM_LIT> ) { if ( ( ! regs_ever_live [ regno ] || call_used_regs [ regno ] ) && ( ! regs_ever_live [ regno + <NUM_LIT> ] || call_used_regs [ regno + <NUM_LIT> ] ) ) { if ( count > <NUM_LIT> ) { if ( count == <NUM_LIT> && ! arm_arch6 ) count ++ ; saved += count * <NUM_LIT> + <NUM_LIT> ; } count = <NUM_LIT> ; } else count ++ ; } if ( count > <NUM_LIT> ) { if ( count == <NUM_LIT> && ! arm_arch6 ) count ++ ; saved += count * <NUM_LIT> + <NUM_LIT> ; } } return saved


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> addLiveIn (


<s> unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc =


<s> static void initTIs ( Module & M , std :: tuple < ThunkInserterT ... > & ThunkInserters ) { ( void ) std :: initializer_list < int > { ( std :: get < ThunkInserterT > ( ThunkInserters ) . init ( M ) , <NUM_LIT>


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses


<s> static DecodeStatus DecodeVecShiftLImm ( MCInst & Inst , unsigned Imm , unsigned


<s> if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , ( define_p ) ? <STR_LIT> : <STR_LIT> ,


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin ,


<s> unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( <STR_LIT> == Addr ) && <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; EmitBICMask ( STI , Out , Addr , Pred ,


<s> if ( Base . getOpcode ( ) == <STR_LIT> && Base . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Base . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && Base . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { uint64_t ShiftAmount = Base . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t LoadBytes = Mem -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ShiftAmount == Log2_32 ( LoadBytes ) ) return false ; } return true


<s> const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; }


<s> unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( )


<s> bool S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool J2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Imm21 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm21 |= <NUM_LIT> <<


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ~ __X


<s> gcc_assert ( ok ) ; if ( parts . base && SUBREG_P ( parts . base ) ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && SUBREG_P ( parts . index ) ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ; if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ; if ( TARGET_CPU_P ( K6 ) && ( ( ! parts . disp && parts . base && parts . index && parts . scale != <NUM_LIT> ) || ( parts . disp && ! parts . base && parts . index && parts . scale != <NUM_LIT> ) || ( ! parts . disp && parts . base && parts . index && parts . scale == <NUM_LIT> ) ) ) cost += <NUM_LIT> ; return


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , false ) , RegSpillOffsets ( <NUM_LIT> ) { RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets [ SpillOffsetTable [ I ] .

Reg ] = SpillOffsetTable [ I ] . Offset ;


<s> if ( ! TARGET_LSE ) return false ; switch ( code ) { case SET : case AND : case IOR


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregxiv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregxiv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregxiv2di_pss


<s> } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false


<s> machine_mode tmode0 , tmode1 , modev2 , modev3 , modeimm ; tmode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; tmode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modev2 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modev3 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; modeimm = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( modev2 ) ) op0 = safe_vector_operand ( op0 , modev2 ) ; if ( VECTOR_MODE_P ( modev3 ) ) op1 = safe_vector_operand ( op1 , modev3 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , modev2 ) ) op0 = copy_to_mode_reg ( modev2 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , modev3 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , modev3 ) ) op1 = copy_to_mode_reg ( modev3 , op1 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op2 ,


<s> Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( ZeroReg ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> )

, Tmp2Reg ) . addReg ( TmpDestReg ) . addReg ( MaskReg ) ;


<s> MachineInstr * BrMI = MBBInfo -> BrInstr ; <STR_LIT> CC = MBBInfo -> BranchCode ; MachineInstrBuilder MIB = BuildMI ( * MBB , BrMI , MBB -> findDebugLoc ( BrMI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MBBInfo -> TBB ) . addImm ( CC ) ; BrMI -> eraseFromParent ( ) ; MBBInfo -> BrInstr = MIB


<s> OperandMatchResultTy parseGR32 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> ,


<s> return ( vector signed int ) __builtin_altivec_vsum4shs ( ( vector signed short ) a1 , (


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> return selectMVIAddr ( <STR_LIT> , Addr , Base , Disp


<s> bool IsLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ShuffleKind == <NUM_LIT> ) { if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> )

, i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ;


<s> <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo >


<s> unsigned align = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: CreateImm


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv8hi ( (


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return


<s> if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align <


<s> auto * ZeroVec = findMIFromReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , G_BUILD_VECTOR , MIB ) ; if ( ! ZeroVec ) return false ; int64_t Zero = <NUM_LIT> ; if ( ! mi_match ( ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Zero ) ) || Zero ) return false ; for ( unsigned i = <NUM_LIT> , e = ZeroVec -> getNumOperands ( ) - <NUM_LIT> ; i < e ; ++ i ) { if ( ZeroVec -> getOperand ( i ) . getReg ( ) != ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; } LLT VecTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT EltTy = VecTy . getElementType ( ) ; if ( VecTy . getSizeInBits ( ) != <NUM_LIT> || EltTy . getSizeInBits ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg , MIB ) ; if ( ! Widen ) return false ; ScalarReg = Widen -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { ScalarReg } ) ; if ( IsFP ) Dup . addImm ( <NUM_LIT>


<s> case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx (


<s> gcc_unreachable ( ) ; } } else { switch ( n ) { case <NUM_LIT> : return SFmode ; case <NUM_LIT> : return DFmode ; case <NUM_LIT> : if ( TARGET_FLOAT128_TYPE ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; default : return opt_scalar_float_mode (


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM ,


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N


<s> auto LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( Src ) -> getElementCount ( ) == ElementCount :: getScalable

( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ;


<s> if ( ! isGPRMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue (


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands


<s> cycles = MAX ( cycles , CEIL ( ops -> stores , issue_info -> stores_per_cycle ) ) ; cycles = MAX ( cycles , CEIL ( ops -> loads + ops -> stores , issue_info ->


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready


<s> void <ISA_LIT>SEInstrInfo :: expandEhReturn ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { <ISA_LIT>ABIInfo ABI = Subtarget . getABI ( ) ; unsigned ADDU = ABI . GetPtrAdduOp ( ) ; unsigned SP = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned RA = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned T9 = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) .


<s> return ( __m128i ) __builtin_ia32_cvttps2qq128_mask ( ( __v4sf ) __A , (


<s> switch ( info -> abi ) { default : abi_string = <STR_LIT> ; break ; case ABI_NONE : abi_string = <STR_LIT> ; break ; case ABI_AIX : abi_string = <STR_LIT> ; break ; case ABI_ELFv2 : abi_string = <STR_LIT> ; break ; case ABI_DARWIN : abi_string = <STR_LIT> ; break ; case ABI_V4 : abi_string = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , abi_string ) ; if ( TARGET_ALTIVEC_ABI ) fprintf ( stderr , <STR_LIT> ) ; if ( TARGET_SPE_ABI ) fprintf ( stderr , <STR_LIT> ) ; if ( info -> first_gp_reg_save != <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , info -> first_gp_reg_save ) ; if ( info -> first_fp_reg_save != <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , info -> first_fp_reg_save ) ; if ( info -> first_altivec_reg_save <= LAST_ALTIVEC_REGNO ) fprintf ( stderr , <STR_LIT> , info -> first_altivec_reg_save ) ; if ( info -> lr_save_p ) fprintf ( stderr , <STR_LIT> , info -> lr_save_p ) ; if ( info -> cr_save_p ) fprintf ( stderr , <STR_LIT> , info -> cr_save_p ) ; if ( info -> vrsave_mask ) fprintf ( stderr , <STR_LIT> , info -> vrsave_mask ) ; if ( info -> push_p ) fprintf ( stderr , <STR_LIT> , info -> push_p ) ; if ( info -> calls_p ) fprintf ( stderr , <STR_LIT> , info -> calls_p ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_save_offset ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_save_offset ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_save_offset ) ; if ( info -> spe_gp_size ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_save_offset ) ; if ( info -> vrsave_size ) fprintf ( stderr , <STR_LIT> , info -> vrsave_save_offset ) ; if ( info -> lr_save_p ) fprintf ( stderr , <STR_LIT> , info -> lr_save_offset ) ; if ( info -> cr_save_p ) fprintf ( stderr , <STR_LIT> , info -> cr_save_offset ) ; if ( info -> varargs_save_offset ) fprintf ( stderr , <STR_LIT> , info -> varargs_save_offset ) ; if ( info -> total_size ) fprintf ( stderr , <STR_LIT>


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Start , End ; unsigned Size ; if ( ParseIntelMemoryOperandSize ( Size ) ) return true ; bool PtrInOperand = bool ( Size ) ; Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , Operands ) ; unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return Error ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) return Error ( Start , <STR_LIT> <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , Start , End ) ) ; return false ; } if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return Error ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return true ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg


<s> if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = IsN64 ? <STR_LIT> : <STR_LIT> ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) { Mask = <ISA_LIT>RegisterInfo :: get<ISA_LIT>16RetHelperMask ( ) ; } } } Ops . push_back ( CLI . DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std

:: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ;


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC


<s> if ( RetTy -> isFloatTy ( ) ) { result = sf<ISA_LIT>16Helper [ stubNum ] ; } else if ( RetTy -> isDoubleTy ( ) ) { result = df<ISA_LIT>16Helper [ stubNum ] ; } else if ( StructType * SRetTy = dyn_cast < StructType > ( RetTy ) ) { if ( SRetTy -> getNumElements ( ) == <NUM_LIT> ) { if ( ( SRetTy -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) && ( SRetTy -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) ) { result = sc<ISA_LIT>16Helper [ stubNum ] ; } else if ( ( SRetTy -> getElementType ( <NUM_LIT> ) -> isDoubleTy ( ) ) && ( SRetTy -> getElementType ( <NUM_LIT> ) -> isDoubleTy ( ) ) ) { result = dc<ISA_LIT>16Helper [ stubNum ] ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( stubNum == <NUM_LIT> ) { needHelper = false ; return <STR_LIT> ; } result = v<ISA_LIT>16Helper


<s> uint64_t Idx = Elt . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Idx % <NUM_LIT> ) == <NUM_LIT> && findEltLoadSrc ( Elt . getOperand ( <NUM_LIT> ) , Ld , ByteOffset ) ) { ByteOffset += Idx / <NUM_LIT> ; return true ; } } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) { SDValue Src = Elt . getOperand ( <NUM_LIT> ) ; unsigned SrcSizeInBits = Src . getScalarValueSizeInBits ( ) ; unsigned DstSizeInBits = Elt .


<s> bool selectBDXAddr12Only ( SDValue Addr , SDValue & Base , SDValue


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands (


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count %


<s> SDLoc DL ( N ) ; if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return getOnesVector ( VT , Subtarget , DAG , DL ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getZeroVector ( VT , Subtarget


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = getSETCC ( CCode , Op0 . getOperand ( <NUM_LIT> ) , dl , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1 ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } if ( ! isNullConstant ( Op1 ) ) { SDValue Xor = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ; return DAG . getSetCC ( dl , VT , Xor , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , CC ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , IsFP ,


<s> DOUT << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J ] << <STR_LIT>


<s> else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) { * count = <NUM_LIT> ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { * count = <NUM_LIT> ; new_mode = ( mode == DCmode ? DFmode : SFmode ) ; } else return false ; if ( ! use_vfp_abi ( pcs_variant , ARM_NUM_REGS ( new_mode ) > <NUM_LIT> ) ) return false ; * base_mode = new_mode ; return true


<s> return __builtin_mve_vmulq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> void <ISA_LIT>MCInstLower :: lowerLongBranchADDiu ( const MachineInstr * MI , MCInst & OutMI , int Opcode , MCSymbolRefExpr :: VariantKind Kind ) const { OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand (


<s> bool <ISA_LIT>InstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; assert ( CCMask > <NUM_LIT> && CCMask < <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = MI ->


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetSoftFloat


<s> if ( ! MFI . isCalleeSavedInfoValid ( ) ) return false ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( auto & CS : CSI ) { if ( <STR_LIT> . contains ( CS . getReg ( ) ) || <STR_LIT> . contains ( CS . getReg ( ) ) ) { assert ( ( Max == std :: numeric_limits < int > :: min ( ) || Max + <NUM_LIT> == CS . getFrameIdx ( ) ) && <STR_LIT> ) ; Min = std :: min ( Min , CS . getFrameIdx ( ) ) ; Max = std :: max ( Max , CS . getFrameIdx ( ) ) ; } } return Min != std :: numeric_limits < int > ::


__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; SDValue CCReg = emitCLC ( DAG , DL , Chain , Src1 ,


<s> SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; MI -> eraseFromParent ( ) ; return


<s> RegM = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegM , isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegM ; else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) ; Binary |= ( RegM & <NUM_LIT> ) << <STR_LIT> ; } return


<s> Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isScalableVector ( ) && isTypeLegal ( Op .


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: COPY ) , Out ) . addReg ( DReg , <NUM_LIT> , Lane ) ; return Out


<s> return ( ( vec_int4 ) ( si_rotmi ( ( qword ) (


<s> if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; return


<s> void <ISA_LIT>LowOverheadLoops :: RevertDo ( MachineInstr * MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_vbroadcastsi256 (


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , * CurDAG


<s> bool IsLive = MBB . isLiveIn ( GPR64 ) || MBB . isLiveIn ( GPR32 ) ; if ( ! IsLive || ! IsImplicit ) { MIB . addReg ( GPR64 , getImplRegState ( IsImplicit ) | getKillRegState ( ! IsLive ) ) ; if ( ! IsLive ) MBB


<s> addPass ( create<ISA_LIT>RetpolineThunksPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( ! TT . isOSDarwin ( ) && ! TT . isOSWindows ( )

) addPass ( createCFIInstrInserter ( ) ) ;


<s> if ( isEssentiallyExtractHighSubvector ( LHS ) ) { RHS = tryExtendDUPToExtractHigh ( RHS , DAG ) ; if ( ! RHS . getNode ( ) ) return SDValue ( ) ; } else if ( isEssentiallyExtractHighSubvector ( RHS ) ) { LHS = tryExtendDUPToExtractHigh ( LHS , DAG ) ; if ( ! LHS . getNode ( ) ) return SDValue ( ) ; } if ( IID == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> )

, N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ;


<s> return getSubtargetImpl ( ) -> getDataLayout


<s> } ; static const unsigned LoopIterations = <NUM_LIT> ; DenseMap < MachineInstr * , DepthInfo > DepthMap ; DepthInfo LoopDepth [ LoopIterations ] = { { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; enum { PhyRegType = <NUM_LIT> , VirRegType = <NUM_LIT> , RegTypeNum = <NUM_LIT> } ; DenseMap < unsigned , MachineInstr * > RegDefMaps [ RegTypeNum ] ; DenseMap < MachineOperand * , MachineInstr * > OperandToDefMap ; DepthMap [ nullptr ] = { <NUM_LIT> , <NUM_LIT> } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > CmovInstructions ; for ( auto & Group : CmovInstGroups ) CmovInstructions . insert ( Group . begin ( ) , Group . end ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < LoopIterations ; ++ I ) { DepthInfo & MaxDepth = LoopDepth [ I ] ; for ( auto * MBB : Blocks ) { RegDefMaps [ PhyRegType ] . clear ( ) ; for ( MachineInstr & MI : * MBB ) { if ( MI . isDebugInstr ( ) ) continue ; unsigned MIDepth = <NUM_LIT> ; unsigned MIDepthOpt = <NUM_LIT> ; bool IsCMOV = CmovInstructions . count ( & MI ) ; for ( auto & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; auto & RDM = RegDefMaps [ TargetRegisterInfo :: isVirtualRegister ( Reg ) ] ; if ( MachineInstr * DefMI = RDM . lookup ( Reg ) ) { OperandToDefMap [ & MO ] = DefMI ; DepthInfo Info = DepthMap . lookup ( DefMI ) ; MIDepth = std :: max ( MIDepth , Info . Depth ) ; if ( ! IsCMOV ) MIDepthOpt = std :: max ( MIDepthOpt , Info . OptDepth ) ; } } if ( IsCMOV ) MIDepthOpt = getDepthOfOptCmov ( DepthMap [ OperandToDefMap . lookup ( & MI . getOperand ( <NUM_LIT> ) ) ] . OptDepth , DepthMap [ OperandToDefMap . lookup ( & MI . getOperand ( <NUM_LIT> ) ) ] . OptDepth ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; RegDefMaps [ TargetRegisterInfo :: isVirtualRegister ( Reg ) ] [ Reg ] = & MI ; } unsigned Latency = TSchedModel . computeInstrLatency ( & MI ) ; DepthMap [ & MI ] = { MIDepth += Latency , MIDepthOpt += Latency


<s> psadbh ( uint8x8_t s , uint8x8_t t ) { return __builtin_loongson_psadbh ( s , t


<s> static inline bool hasLEAOffset ( const


<s> case UNSPEC_TLSIE : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TLSLE : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_ICT : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; break ; default : return false ; } return


<s> return ( __m128i ) __builtin_ia32_pbroadcastw128_gpr_mask ( __A , ( __v8hi ) _mm_setzero_si128 ( )


, float const * __addr , int __scale ) {


<s> const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) ->


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> return A . hasByValAttr ( ) || A . hasInRegAttr ( ) || A . hasSwiftErrorAttr ( ) ; } ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( Info . Callee . isGlobal ( ) ) { const GlobalValue * GV = Info . Callee . getGlobal ( ) ; const Triple & TT = MF . getTarget ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CalleeCC == CallerF . getCallingConv ( ) ; assert ( ( ! Info . IsVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; if ( ! doCallerAndCalleePassArgsTheSameWay ( Info , MF , InArgs ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , arg . type , words , arg . named ) ; } else nregs = function_arg_advance_32 ( cum , mode , arg . type , bytes , words ) ; if ( !


<s> MVT NewVT = MaskVT ; switch ( VT . getSimpleVT ( ) ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; } if ( NewWidth == <NUM_LIT> ) { if ( VT . isInteger ( ) ) NewVT = <STR_LIT> ; else NewVT = <STR_LIT> ; } int Scale = NumElems / NewWidth ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) { int EltIdx = SVOp -> getMaskElt ( i + j ) ; if ( EltIdx < <NUM_LIT> ) continue ; if ( StartIdx == - <NUM_LIT> ) StartIdx = EltIdx - ( EltIdx % Scale ) ; if ( EltIdx != StartIdx + j ) return SDValue ( ) ; } if ( StartIdx == - <NUM_LIT> ) MaskVec . push_back ( - <NUM_LIT> ) ; else MaskVec . push_back ( StartIdx / Scale ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , NewVT , V2 ) ; return DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , &


<s> static DecodeStatus DecodeMSRSystemRegister ( MCInst & Inst , unsigned Imm , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return ( MO . getImm ( )


<s> bool LowOverheadLoop :: AddVCTP ( MachineInstr * MI ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( VCTPs . empty ( ) ) { VCTPs . push_back ( MI ) ; return true ; } MachineInstr * Prev = VCTPs . back ( ) ; if ( ! Prev -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( MI -> getOperand ( <NUM_LIT> ) ) || ! RDA . hasSameReachingDef ( Prev , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false


<s> } if ( ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) && ! MF . getRegInfo ( ) . isLiveIn ( Reg ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs [ Reg ] = true ; } for ( unsigned ArgReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( ! MF . getRegInfo ( ) . isLiveIn ( ArgReg ) ) CopyRegs [ ArgReg ] = true ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! LoRegsToSave . none ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( LoRegsToSave [ Reg ] ) { bool isKill = ! MRI . isLiveIn ( Reg ) ; if ( isKill && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end (


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * N = Use -> getOperand ( i ) . getNode ( ) ; if ( N == Def ) { if ( Use == ImmedUse || Use == Root ) continue ; assert ( N


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT , DAG . getRegister ( is64Bit ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Base , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; unsigned char OperandFlags = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec


<s> return ( __m128i ) __builtin_ia32_pmovusqw512_mask ( ( __v8di ) __A ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitWarningForSpecialLVIInstruction ( Inst . getLoc ( ) ) ; return true ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { emitWarningForSpecialLVIInstruction ( Inst . getLoc ( ) ) ; return true ; } const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; if ( MCID . mayLoad ( ) && Inst . getOpcode ( ) != <STR_LIT> ) { MCInst FenceInst ; FenceInst . setOpcode ( <STR_LIT> ) ; FenceInst . setLoc ( Inst . getLoc ( ) ) ; Out . emitInstruction ( FenceInst , getSTI ( ) ) ; return true ; } return false


<s> static void Passv64i1ArgInRegs ( const SDLoc & Dl , SelectionDAG & DAG , SDValue Chain , SDValue & Arg , SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > & RegsToPass , CCValAssign & VA , CCValAssign & NextVA , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( Subtarget . hasBWI ( ) || Subtarget . hasBMI ( ) ) && <STR_LIT> ) ; assert ( Subtarget . is32Bit ( ) && <STR_LIT> ) ; assert ( Arg . getValueType ( ) == <STR_LIT> &&


<s> assert ( State . PrefixPass == false ) ; MCInst PrefixInst ; PrefixInst . setOpcode ( Opc ) ; State . PrefixPass = true ; Out . EmitInstruction ( PrefixInst ) ; assert ( State . PrefixSaved == <NUM_LIT> ) ; assert ( State . PrefixPass == false


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue ) ; assert ( FPImmEncoding != - <NUM_LIT> && <STR_LIT> ) ; NewInstBuilder . addImm (


<s> if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ; else { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getPtrSizedFrameRegister ( MF ) ; assert ( ( FrameReg == <STR_LIT> || FrameReg == <STR_LIT> ) && <STR_LIT> ) ; } } if ( Reg ) return Reg ; report_fatal_error (


<s> static inline unsigned getAddrMode ( uint64_t TSFlags ) { return ( TSFlags


<s> switch ( Info -> getDecorationStyle ( ) ) { case None : break ; case StdCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; break ; case FastCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; if ( Name [ <NUM_LIT> ] == '_' ) { Name [ <NUM_LIT> ] = '@' ; } else { Name = '@' + Name ; } break ; default : llvm_unreachable (


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return


<s> OPCODE ( XC ) ; OPCODE ( CLC ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE (


<s> Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return getTargetMachine ( ) . getOptLevel ( )


<s> <ISA_LIT>CallingConventionRegisters * getSpecialRegisters ( ) const


<s> return ( __m256d ) __builtin_ia32_pd256_pd ( ( __v2df )


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( CPU . empty ( ) ) CPU = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT ,


<s> } if ( ! issetmem ) srcmem = change_address ( srcmem , mode , * srcptr ) ; destmem = change_address ( destmem , mode , * destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; for ( n = <NUM_LIT> ; prolog_size < desired_align - align ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , mode_value ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; prolog_size += GET_MODE_SIZE ( mode ) ; } destmem = offset_address ( destmem , * count , <NUM_LIT> ) ; destmem = offset_address ( destmem , GEN_INT ( - size - prolog_size ) , <NUM_LIT> ) ; if ( issetmem ) emit_move_insn ( destmem , mode_value ) ; else { srcmem = offset_address ( srcmem , * count , <NUM_LIT> ) ; srcmem = offset_address ( srcmem , GEN_INT ( - size - prolog_size ) , <NUM_LIT> ) ; emit_move_insn ( destmem , srcmem ) ; } for ( n = <NUM_LIT> ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { destmem = offset_address ( destmem , modesize , <NUM_LIT> ) ; if ( issetmem ) emit_move_insn ( destmem , mode_value ) ; else { srcmem = offset_address ( srcmem , modesize , <NUM_LIT> ) ; emit_move_insn ( destmem , srcmem ) ; } } if ( desired_align > <NUM_LIT> && desired_align > align ) { rtx saveddest = * destptr ; gcc_assert ( desired_align <= size ) ; * destptr = expand_simple_binop ( GET_MODE ( * destptr ) , PLUS , * destptr , GEN_INT ( prolog_size ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; if ( REG_P ( * destptr ) && REG_P ( saveddest ) && REG_POINTER ( saveddest ) ) REG_POINTER ( * destptr ) = <NUM_LIT> ; * destptr = expand_simple_binop ( GET_MODE ( * destptr ) , AND , * destptr , GEN_INT ( - desired_align ) , * destptr , <NUM_LIT> , OPTAB_DIRECT ) ; saveddest = expand_simple_binop ( GET_MODE ( * destptr ) , MINUS , saveddest , * destptr , saveddest , <NUM_LIT> , OPTAB_DIRECT ) ; if ( ! issetmem ) * srcptr = expand_simple_binop ( GET_MODE ( * srcptr ) , MINUS , * srcptr , saveddest , * srcptr , <NUM_LIT>


<s> static void makeDMB ( IRBuilder < > & Builder , <STR_LIT> Domain ) { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) ->


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> return ( __m128 ) __builtin_ia32_getexpps128_mask ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8


<s> static MCStreamer * createELFStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , false , ( T

. getArch ( ) == Triple :: thumb || T . getArch ( ) == Triple :: thumbeb ) ) ;


<s> int mmix_print_operand_punct_valid_p ( int code ATTRIBUTE_UNUSED


<s> Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I -> getBlock ( )


<s> unsigned LoIdx = <NUM_LIT> , HiIdx = <NUM_LIT> ; if ( ! isLittle ) std :: swap ( LoIdx , HiIdx ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Word0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( LoIdx , <STR_LIT> ) ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT8 ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT16 ) ; } for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth == <NUM_LIT> )


<s> Align getStackAlignment ( ) const { return stackAlignment


<s> InitialStates . insert ( { BB , PredState } ) ; FinalStates . insert ( { BB , PredState } ) ; for ( BasicBlock * SuccBB : successors ( BB ) ) Worklist . push_back ( SuccBB ) ; } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! isStateStoreNeeded ( Personality , CS ) ) continue ; int State = getStateForCallSite ( BlockColors , FuncInfo , CS ) ; if ( State != PrevState ) insertStateNumberStore ( & I , State ) ; PrevState = State ; } auto EndState = FinalStates . find ( BB ) ; if ( EndState != FinalStates . end ( ) ) if ( EndState -> second != PrevState ) insertStateNumberStore ( BB -> getTerminator ( ) , EndState -> second ) ; } SmallVector < CallSite , <NUM_LIT> > SetJmp3CallSites ; for ( BasicBlock * BB : RPOT ) { for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! CS ) continue ; if ( CS . getCalledValue ( ) -> stripPointerCastsSafe ( ) != SetJmp3 . getCallee ( ) -> stripPointerCastsSafe ( ) ) continue ; SetJmp3CallSites . push_back ( CS ) ; } } for ( CallSite CS : SetJmp3CallSites ) { auto & BBColors = BlockColors [ CS -> getParent ( ) ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; bool InCleanup = isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ; IRBuilder < > Builder ( CS . getInstruction ( ) ) ; Value * State ; if ( InCleanup ) { Value * StateField = Builder . CreateStructGEP ( RegNode -> getAllocatedType ( ) , RegNode , StateFieldIndex ) ; State = Builder . CreateLoad ( Builder . getInt32Ty ( ) , StateField ) ; } else { State = Builder . getInt32 ( getStateForCallSite ( BlockColors , FuncInfo , CS ) ) ; } rewriteSetJmpCallSite ( Builder , F ,


<s> const MCSymbol * Sym = getSymbol ( * Mang , GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang ,


<s> if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget -> hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT


<s> bool <ISA_LIT>FastISel :: SelectRet ( const Instruction * I ) { const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT !=


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case <STR_LIT> : case


<s> bool useMachineOutliner ( ) const override { return


<s> else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr


<s> It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It


<s> int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , <NUM_LIT>


<s> int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace (


<s> unsigned Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( Ctx . getAsmInfo ( ) -> isLittleEndian ( ) ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } unsigned tlsOpNo = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( op == <NUM_LIT> && <STR_LIT> ) ; ( void ) op ; } ++ MCNumEmitted


<s> if ( Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMADD ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName )


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( arg . mode ) ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TREE_CODE ( arg . type ) == VECTOR_TYPE && int_size_in_bytes ( arg . type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( OPT_Wpsabi ,


<s> tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ <NUM_LIT> ] + <NUM_LIT> ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = <NUM_LIT> ; i < nelt ; next ++ , i ++ ) { if ( next == <NUM_LIT> * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == <NUM_LIT> ) && ( d -> vmode != V2DImode ) ) return false ; else next = <NUM_LIT> ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location


<s> void setRAIndex ( int Index ) { ReturnAddrIndex =


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg


<s> unsigned <ISA_LIT>FastISel :: materialize32BitInt ( int64_t Imm , const TargetRegisterClass * RC ) { unsigned ResultReg = createResultReg ( RC ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = <STR_LIT> ; emitInst ( Opc , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } else if ( isUInt < <NUM_LIT> > ( Imm ) ) { emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) .


<s> return ( __m512 ) __builtin_ia32_broadcastf32x2_512_mask ( ( __v4sf ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , raw_ostream & O ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( O , MAI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( O , MAI


<s> SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ; if ( Result . getNode


<s> SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , Glue ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; Glue = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , Glue ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; Glue = EnvVal .


<s> switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; case AsmToken :: Identifier : { OperandMatchResultTy GotShift = ParseShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; uint32_t NumLanes = <NUM_LIT> ; OperandMatchResultTy GotReg = ParseRegister ( Operands , NumLanes ) ; assert ( GotReg != MatchOperand_ParseFail && <STR_LIT> ) ; if ( GotReg == MatchOperand_Success ) { if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) return ParseNEONLane ( Operands , NumLanes ) ; else return MatchOperand_Success ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : case AsmToken :: Dollar : case AsmToken :: Colon : { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; const MCExpr * ImmVal = nullptr ; if ( ParseImmediate ( ImmVal ) !=


<s> if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT>


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Y , <STR_LIT> ) ; if ( SetCCResultType == VT && DAG . ComputeNumSignBits ( Cmp ) == VT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Sub ) ; return DAG . getSelect ( DL , VT , Cmp , Sub , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && ( ! VT . isVector ( ) || VT == <STR_LIT> ) ) { unsigned BitWidth = VT . getScalarSizeInBits ( ) ; APInt MinVal = APInt :: getSignedMinValue ( BitWidth ) ; APInt MaxVal = APInt :: getSignedMaxValue ( BitWidth ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Result = DAG . getNode ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , SetCCResultType ) , X , Y ) ; SDValue SumDiff = Result . getValue (