<s> const int NumBytes = VT . getSizeInBits ( ) / <NUM_LIT> ; const int NumEltBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; assert ( ( Subtarget . hasSSSE3 ( ) && VT . is128BitVector ( ) ) || ( Subtarget . hasAVX2 ( ) && VT . is256BitVector ( ) ) || ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) ) ) ; SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ( NumBytes ) ; SDValue ZeroMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue V ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / NumEltBytes ] ; if ( M < <NUM_LIT> ) { PSHUFBMask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } if ( Zeroable [ i / NumEltBytes ] ) { PSHUFBMask [ i ] = ZeroMask ; continue ; } SDValue SrcV = ( M >= Size ? V2 : V1 ) ; if ( V && V != SrcV ) return SDValue ( ) ; V = SrcV ; M %=


<s> if ( d -> testing_p ) return true ; dfirst = * d ; dsecond = * d ; dthird = * d ; dfirst . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; dfirst . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) + <NUM_LIT> ; dfirst . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; dfirst . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) + <NUM_LIT> ; dsecond . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; dsecond . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) + <NUM_LIT> ; dsecond . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; dsecond . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] & ~ <NUM_LIT> ) + <NUM_LIT> ; dthird . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] % <NUM_LIT> ) ; dthird . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] % <NUM_LIT> ) + <NUM_LIT> ; dthird . perm [ <NUM_LIT> ] = ( d -> perm [ <NUM_LIT> ] %


<s> MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } int UnscaledOffset = getLdStOffsetOp ( MI ) . getImm ( ) * getMemScale ( MI ) ; Update = findMatchingUpdateInsnForward ( MBBI , UnscaledOffset , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } return


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { assert ( InProlog && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; return &


<s> SDLoc DL ( N ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode (


<s> int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= <NUM_LIT> ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ( TT [ <NUM_LIT> ] == 'i' || TT [ <NUM_LIT> ] == 'I' ) && ( TT [ <NUM_LIT> ] == 'a' || TT [ <NUM_LIT> ] == 'A' ) ) { for ( unsigned int i = <NUM_LIT> ; i < ( TT . size ( ) - <NUM_LIT> ) ; i ++ ) if ( TT [ i ] == '6' && TT [ i + <NUM_LIT> ] == '4' ) seen<ISA_LIT> = true ; } if ( seen<ISA_LIT> ) return <NUM_LIT> ; } if ( ! TT . empty ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) {


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable (


<s> SDValue <ISA_LIT>TargetLowering :: lowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; bool RealignOpt = ! MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; uint64_t AlignVal = ( RealignOpt ? cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) : <NUM_LIT> ) ; uint64_t StackAlign = TFI -> getStackAlignment ( ) ; uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; Register SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF )


<s> Inst . addOperand ( MCOperand :: CreateReg (


<s> if ( ! Subtarget -> isThumb ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> (


<s> void <ISA_LIT>PassConfig :: addMachineSSAOptimization ( ) { addPass ( create<ISA_LIT>OptimizePICCallPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; TargetPassConfig :: addMachineSSAOptimization (


<s> static DecodeStatus DecodeRegExtendOperand ( llvm :: MCInst & Inst , unsigned ShiftAmount , uint64_t Address ,


<s> EVT VT = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; } return Chain


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) , LHS , RHS ) . getValue ( <NUM_LIT> ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , LHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; } return std :: make_pair (


<s> void <ISA_LIT>ELFStreamer :: EmitPersonality ( const MCSymbol * Per ) { Personality = Per


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { int ix ; tree ele ; vec < tree > * fndecls ; tree clones [ CLONE_MAX ] ; if ( TARGET_DEBUG_TARGET ) fputs ( <STR_LIT> , stderr ) ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; gcc_assert ( fndecls -> length ( ) >= <NUM_LIT> ) ; memset ( ( void * ) clones , '\0' , sizeof ( clones ) ) ; clones [ CLONE_DEFAULT ] = ( * fndecls ) [ <NUM_LIT> ] ; for ( ix = <NUM_LIT> ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { int priority = rs6000_clone_priority ( ele ) ; if ( ! clones [ priority ] ) clones [ priority ] = ele ; } for ( ix = CLONE_MAX - <NUM_LIT> ; ix >= <NUM_LIT> ; ix -- ) if ( clones [ ix ] ) { if ( TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , ix ,


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ,

MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const {


<s> static bool ix86_expand_vec_perm_const_1 ( struct expand_vec_perm_d * d ) { if ( expand_vec_perm_1 ( d ) ) return true ; if ( expand_vec_perm_pshuflw_pshufhw ( d ) ) return true ; if ( expand_vec_perm_palignr ( d , false ) ) return true ; if ( expand_vec_perm_interleave2 ( d ) ) return true ; if ( expand_vec_perm_broadcast ( d ) ) return true ; if ( expand_vec_perm_vpermq_perm_1 ( d )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) :

LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , is64bit ) {


<s> OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE (


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE


_mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> bool <ISA_LIT>TTIImpl :: hasCompatibleFunctionAttributes ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee )


<s> return ( __m128h ) __builtin_ia32_vfmaddcsh_round ( ( __v8hf ) __A , ( __v8hf )


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCCCARRY ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get


<s> default : gcc_unreachable ( ) ; } rtx dest = lowpart_subreg ( sse_mode , op0 , GET_MODE ( op0 ) ) ; op1 = lowpart_subreg ( sse_mode , op1 , GET_MODE ( op1 ) ) ; op2 = lowpart_subreg ( sse_mode , op2 , GET_MODE ( op2 ) ) ; op1 = gen_rtx_VEC_CONCAT ( double_sse_mode , op1 , op2 ) ; op2 = gen_rtx_VEC_SELECT ( sse_mode , op1 , mask ) ; rtx insn = gen_rtx_SET ( dest , op2 ) ; emit_insn ( insn ) ; if ( high_p ) { if ( sse_mode == V4SFmode ) { mask = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; op2 = gen_rtx_VEC_CONCAT ( V8SFmode , dest , dest ) ; op1 = gen_rtx_VEC_SELECT ( V4SFmode , op2 , mask ) ; } else { int sz = GET_MODE_SIZE ( mode ) ; if ( sz == <NUM_LIT> ) mask = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , GEN_INT (


<s> case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & RetOps [ <NUM_LIT> ] , RetOps . size


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> bool IsVSFRC = isVSFRCRegister ( SrcReg ) ; if ( IsVSFRC && ( Opc == <STR_LIT> ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( FPR128DecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DAG


<s> MCAsmParserExtension :: Initialize ( _Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> Value * <ISA_LIT>IREmitter :: visitVBROADCAST ( const SDNode


<s> if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( Reg , true ) + <NUM_LIT> ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION


<s> if ( ForCodeSize || V . hasOneUse ( ) ) return true ; if ( Subtarget -> hasLSLFast ( ) && V . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( V ) ) return true ; if ( Subtarget -> hasLSLFast ( ) && V . getOpcode ( ) == <STR_LIT> ) { const SDValue LHS = V . getOperand ( <NUM_LIT> ) ; const SDValue RHS = V . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( LHS ) ) return true ; if ( RHS . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( RHS ) ) return true ; } return false


<s> return ( __m128i ) __builtin_ia32_vpshldv_v2di_mask ( ( __v2di ) __A , ( __v2di )


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? <NUM_LIT> : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary =


<s> initializeAnnotationsInference ( * unwrap


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue


<s> assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > (


<s> return ( uint64x1_t ) ( __a <= ( float64x1_t


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , dl , Src . getValueType ( ) , BitNo ) ; SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , BitNo ) ; <STR_LIT> Cond = CC == <STR_LIT> ?


<s> MemOpKey ( const MachineOperand * Base , const MachineOperand * Scale , const MachineOperand * Index , const MachineOperand * Segment , const MachineOperand * Disp ) : Disp ( Disp ) { Operands [ <NUM_LIT> ] = Base


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O


<s> break ; case CortexA55 : break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR82 : case CortexX1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth =


<s> static __inline unsigned long long sh_media_MMULLO_WL ( unsigned long long


<s> case D11 : case D10 : case D9 : case D8 : case D7 : case D6 : case D5 : case D4 : case D3 : case D2 : case D1 : case D0 : case D31 : case D30 : case D29 : case D28 : case D27 : case D26 : case D25 : case D24 : case D23 : case D22 : case D21 : case D20 : case D19 : case D18 : case D17 : case


<s> if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return S


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind


<s> factor = CEIL ( GET_MODE_SIZE ( mode ) , GET_MODE_SIZE ( SImode ) ) ; * total = factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case MULT : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case PLUS : { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; machine_mode op1_mode = GET_MODE ( op1 ) ; if ( op1_mode == VOIDmode && CONST_INT_P ( op1 ) && outer_code == MEM ) op1_mode = Pmode ; if ( outer_code == MEM && ( ( REG_P ( op0 ) && reg_or_ubyte_operand ( op1 , op1_mode ) ) || ctable_addr_operand ( op0 , VOIDmode ) || ctable_addr_operand ( op1 , VOIDmode ) || ( ctable_base_operand ( op0 , VOIDmode ) && REG_P ( op1 ) ) || ( ctable_base_operand ( op1 , VOIDmode ) && REG_P ( op0 ) ) ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } } case SIGN_EXTEND : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ASHIFTRT : { rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( const_1_operand ( op1 , VOIDmode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false


<s> Value * Res = getReg ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) { Res = Builder . CreateOr ( Builder . CreateShl ( Builder . CreateZExt ( SFVals [ Flags [ i ] ] , Res -> getType


<s> for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : MemoryFoldTable2 ) addTableEntry ( Entry , TB_INDEX_2 | TB_FOLDED_LOAD ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : MemoryFoldTable3 ) addTableEntry ( Entry , TB_INDEX_3 | TB_FOLDED_LOAD ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : MemoryFoldTable4 ) addTableEntry ( Entry , TB_INDEX_4 | TB_FOLDED_LOAD ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : BroadcastFoldTable2 ) addTableEntry ( Entry , TB_INDEX_2 |


<s> StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( )


<s> static SDValue PerformLOADCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT .

getScalarType ( ) , NumElems / <NUM_LIT> ) ;


<s> return InlineAsm :: Constraint_Um ; case 'n' : return InlineAsm :: Constraint_Un ; case 'q' : return InlineAsm :: Constraint_Uq ; case 's' : return InlineAsm :: Constraint_Us ; case 't' : return InlineAsm :: Constraint_Ut ; case 'v' : return InlineAsm ::


, MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ;


<s> case ELF :: R_MIPS_GPREL16 : case ELF :: R_MIPS_PC16 : case ELF :: R_MIPS_SUB : return false ; case ELF :: R_MIPS_REL32 : case ELF :: R_MIPS_LITERAL : case ELF :: R_MIPS_CALL16 : case ELF :: R_MIPS_SHIFT5 : case ELF :: R_MIPS_SHIFT6 : case ELF :: R_MIPS_GOT_DISP : case ELF :: R_MIPS_GOT_PAGE : case ELF :: R_MIPS_GOT_OFST : case ELF :: R_MIPS_GOT_HI16 : case ELF :: R_MIPS_GOT_LO16 : case ELF :: R_MIPS_INSERT_A : case ELF :: R_MIPS_INSERT_B : case ELF :: R_MIPS_DELETE : case ELF :: R_MIPS_HIGHER : case ELF :: R_MIPS_HIGHEST : case ELF :: R_MIPS_CALL_HI16 : case ELF :: R_MIPS_CALL_LO16 : case ELF :: R_MIPS_SCN_DISP : case ELF :: R_MIPS_REL16 : case ELF :: R_MIPS_ADD_IMMEDIATE : case ELF :: R_MIPS_PJUMP : case ELF :: R_MIPS_RELGOT : case ELF :: R_MIPS_JALR : case ELF :: R_MIPS_TLS_DTPMOD32 : case ELF :: R_MIPS_TLS_DTPREL32 : case ELF :: R_MIPS_TLS_DTPMOD64 : case ELF :: R_MIPS_TLS_DTPREL64 : case ELF :: R_MIPS_TLS_GD : case ELF :: R_MIPS_TLS_LDM : case ELF :: R_MIPS_TLS_DTPREL_HI16 : case ELF :: R_MIPS_TLS_DTPREL_LO16 : case ELF :: R_MIPS_TLS_GOTTPREL : case ELF :: R_MIPS_TLS_TPREL32 : case ELF :: R_MIPS_TLS_TPREL64 : case ELF :: R_MIPS_TLS_TPREL_HI16 : case ELF :: R_MIPS_TLS_TPREL_LO16 : case ELF :: R_MIPS_GLOB_DAT : case ELF :: R_MIPS_PC21_S2 : case ELF :: R_MIPS_PC26_S2 : case ELF :: R_MIPS_PC18_S3 : case ELF :: R_MIPS_PC19_S2 : case ELF :: R_MIPS_PCHI16 : case ELF :: R_MIPS_PCLO16 : case ELF :: R_MIPS_COPY : case ELF :: R_MIPS_JUMP_SLOT : case ELF :: R_MIPS_NUM : case ELF :: R_MIPS_PC32 : case ELF :: R_MIPS_EH : case ELF :: R_MICROMIPS_26_S1 : case ELF :: R_MICROMIPS_GPREL16 : case ELF :: R_MICROMIPS_LITERAL : case ELF :: R_MICROMIPS_PC7_S1 : case ELF :: R_MICROMIPS_PC10_S1 : case ELF :: R_MICROMIPS_PC16_S1 : case ELF :: R_MICROMIPS_CALL16 : case ELF :: R_MICROMIPS_GOT_DISP : case ELF :: R_MICROMIPS_GOT_PAGE : case ELF :: R_MICROMIPS_GOT_OFST : case ELF :: R_MICROMIPS_GOT_HI16 : case ELF :: R_MICROMIPS_GOT_LO16 : case ELF :: R_MICROMIPS_SUB : case ELF :: R_MICROMIPS_HIGHER : case ELF :: R_MICROMIPS_HIGHEST : case ELF :: R_MICROMIPS_CALL_HI16 : case ELF :: R_MICROMIPS_CALL_LO16 : case ELF :: R_MICROMIPS_SCN_DISP : case ELF ::


<s> void addMemoryIndexedSImm9Operands ( MCInst & Inst


<s> case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: FAdd : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: SDiv : return SelectDiv ( I , true ) ; case Instruction :: UDiv : return SelectDiv ( I , false ) ; case Instruction :: SRem : return SelectRem ( I , true ) ; case Instruction :: URem : return SelectRem ( I , false ) ; case Instruction :: Call : if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) return SelectIntrinsicCall ( * II ) ; return SelectCall ( I ) ; case Instruction :: Select : return SelectSelect ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction ::


<s> } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) : ( ( Offset < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc (


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext (


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode


<s> SDValue <ISA_LIT>TargetLowering :: lowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Cond = createFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue True = DAG . getConstant


<s> static inline void desc_mem_stack_f ( unw_word t , unw_word size , struct unw_state_record * sr ) { set_reg ( sr -> curr . reg + UNW_REG_PSP , UNW_WHERE_NONE , sr -> region_start + MIN ( (

int ) t , sr -> region_len - <NUM_LIT> ) , <NUM_LIT> * size ) ;


<s> asm_output_aligned_bss ( FILE , DECL , NAME , SIZE , ALIGN ) { \ typedef ( * pfunc ) ( ) ; \ extern pfunc __ctors [ ] ; \ extern pfunc __ctors_end [ ] ; \ pfunc * p ; \ for ( p = __ctors_end ; p > __ctors ; ) \ { \ ( *


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> else if ( IDVal == <STR_LIT> ) return ParseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveSyntax


<s> fprintf ( asm_out_file , <STR_LIT> , * ( const char * const

* ) directive , XCOFF_CSECT_DEFAULT_ALIGNMENT_STR ) ;


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return FramePtr ; return <STR_LIT>


<s> uint64_t getPC16DBLBPPEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup

> & Fixups , const MCSubtargetInfo & STI ) const {


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> bool isMem ( ) const override { if ( Kind != k_Memory ) return false ; if ( Memory . BaseRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains

( Memory . OffsetRegNum ) ) return false ;


<s> inline vector signed char vec_sro ( vector signed char


<s> if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next

) && NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION ) insn = next ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT


<s> static inline bool is32ExtendedReg ( unsigned RegNo ) { return ( ( RegNo > <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo > <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo


<s> static void sparc_output_deferred_case_vectors ( void ) { rtx t ; int align ; if ( sparc_addr_list == NULL_RTX && sparc_addr_diff_list == NULL_RTX ) return ; switch_to_section ( current_function_section ( ) ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; for ( t = sparc_addr_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_vec ( XEXP ( t , <NUM_LIT> ) ) ; for ( t = sparc_addr_diff_list ; t ; t = XEXP ( t , <NUM_LIT> )

) sparc_output_addr_diff_vec ( XEXP ( t , <NUM_LIT> ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> bool isMemoryRegisterOffset16 ( ) const { return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal == <NUM_LIT>


<s> emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_USE_SAHF ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode


<s> else { if ( U -> getOperand ( U -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = UseChain ; } } } else if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != <STR_LIT> || ! Copy -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else { return false ; } bool HasRet = false ; for ( const SDNode * U : Copy -> uses ( ) ) { if ( U -> getOpcode ( ) != <STR_LIT> && U -> getOpcode ( ) != <STR_LIT> ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1Rm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , IsGPR ( RegClass ) ? getT1Rd ( insn ) : getT1tRd ( insn ) ) ) ) ; ++ OpIdx ; assert ( OpIdx < NumOps && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isData ( ) && IsGlobalInSmallSection (

GV , TM , Kind ) ) return SmallDataSection ;


<s> vld4_dup_u32 ( const uint32_t * __a ) { uint32x2x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t


<s> return __builtin_mve_vqrdmlahq_n_sv4si ( __a ,


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { TargetRegistry :: RegisterMCAsmInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) ,


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI )


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct

gcc_options * opts , struct gcc_options * ) {


<s> return ( uint32x2_t ) __builtin_neon_vqshl_u_nv2si ( ( int32x2_t ) __a ,


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( VT . is128BitVector ( ) && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; auto OnlyUsedAsSelectCond = [ ] ( SDValue Cond ) { for ( SDNode :: use_iterator UI = Cond -> use_begin ( ) , UE = Cond -> use_end ( ) ; UI != UE ; ++ UI ) if ( ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) || UI . getOperandNo ( ) != <NUM_LIT> ) return false ; return true ; } ; if ( OnlyUsedAsSelectCond ( Cond ) ) { APInt DemandedMask ( APInt :: getSignMask ( BitWidth ) ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; if ( ! TLI . SimplifyDemandedBits ( Cond , DemandedMask , Known , TLO , <NUM_LIT> , true ) ) return SDValue ( ) ; for ( SDNode * U : Cond -> uses ( ) ) { if ( U -> getOpcode ( ) == <STR_LIT> )


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>MCAsmStreamer :: EmitRawTextImpl ( StringRef String ) { if ( ! String . empty ( ) && String . back ( ) == '\n' ) String = String . substr ( <NUM_LIT> , String . size ( ) - <NUM_LIT> ) ; OS <<


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF .


<s> B = N1 . getOperand ( <NUM_LIT> ) ; C = N1 . getOperand ( <NUM_LIT> ) ; } else if ( isLogicOp ( N0 . getOpcode ( ) ) && N0 . hasOneUse ( ) ) { Opc2 = N0 . getOpcode ( ) ; A = N1 ; B = N0 . getOperand ( <NUM_LIT> ) ; C = N0 . getOperand ( <NUM_LIT> ) ; } else return false ; uint64_t Imm ; switch ( Opc1 ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : switch ( Opc2 ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; } break ; case <STR_LIT> : switch ( Opc2 ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; } break ; case <STR_LIT>


<s> if ( fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrMode7Operand ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePostIdxReg ( Inst , Rm , Address , Decoder )


<s> return __builtin_ia32_pcmpistric128 ( ( __v16qi ) __X , (


<s> return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; int64_t Val = CE -> getValue ( ) ; if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = Val ; LaneKind = IndexedLane ; return


<s> case Triple :: MinGW32 : case Triple :: Cygwin : case Triple :: Win32 : if ( TheTriple . getEnvironment ( ) == Triple :: MachO ) return new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; else return new <ISA_LIT>MCAsmInfoCOFF ( TheTriple ) ; default : return new <ISA_LIT>ELFMCAsmInfo (


<s> void paired_expand_vector_move ( rtx operands [ ] ) { rtx op0 = operands [ <NUM_LIT> ] , op1 = operands [ <NUM_LIT> ] ; emit_move_insn ( op0 , op1


<s> MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext


<s> bool isReg ( RegisterKind RegKind ) const { return Kind == KindReg && Reg .


<s> temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v8qi ( ( __builtin_aarch64_simd_qi * ) __a


<s> VariantKind getKind ( ) const { return Kind


<s> return ( vector signed short ) __builtin_altivec_vmhaddshs ( ( vector signed short ) a1 , ( vector

signed short ) a2 , ( vector signed short ) a3 ) ;


<s> if ( Subtarget -> is64Bit ( ) ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; unsigned CopyOpc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> return ( poly16x4_t ) __builtin_neon_vreinterpretv4hiv4hi (


<s> MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . add ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; MIB . add ( MO ) ; } updateOperandRegConstraints ( MF , * NewMI , TII


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor + j ; if ( Mask [ IdxJ * Factor + IdxI ] >= <NUM_LIT> ) { StartMask = Mask [ IdxJ * Factor + IdxI ] - IdxJ ; break ; } } Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( StartMask , LaneLen , <NUM_LIT> ) ) ) ; } } if ( StoreCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( SubVecTy -> getElementType ( ) , BaseAddr , LaneLen * Factor ) ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , PtrTy ) ) ; Builder . CreateCall ( StNFunc , Ops ) ; } return true


<s> case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'U' && Constraint [ <NUM_LIT> ] == 'p' && ( Constraint [ <NUM_LIT> ] == 'l' || Constraint [ <NUM_LIT> ] == 'a' ) ) { return C_RegisterClass


<s> if ( ! IN_RANGE ( index , <NUM_LIT> , <NUM_LIT> ) ) return NULL ; struct loongarch_address_info info ; if ( ( loongarch_classify_address ( & info , x , mode , false ) && ! ( info . type == ADDRESS_REG_REG ) ) || ! loongarch_legitimate_address_p ( mode , x , false ) ) return NULL ; const char * const insn [ ]


<s> static bool isVectorShift ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , bool & isLeft , SDValue & ShVal , unsigned & ShAmt ) { if ( SVOp -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( isVectorShiftLeft ( SVOp , DAG , isLeft , ShVal , ShAmt ) || isVectorShiftRight ( SVOp

, DAG , isLeft , ShVal , ShAmt ) ) return true ;


<s> MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch (


<s> case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand ( )


<s> N -> getMask ( M ) ; return :: isUNPCKHMask ( M , N -> getValueType ( <NUM_LIT> ) , HasAVX2


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg (


<s> SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg )


<s> Size = StringSwitch < unsigned > ( getTok ( ) . getString ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( Size ) { const AsmToken & Tok = Lex ( ) ; if ( ! ( Tok . getString ( ) . equals ( <STR_LIT> ) || Tok . getString ( ) . equals ( <STR_LIT> ) )

) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> } else if ( from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM ) { offset = <NUM_LIT> ; } else if ( from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM ) { offset = ( cfun -> machine -> local_size + cfun -> machine -> out_args_size ) ; } else if ( from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM ) { offset = ( - <NUM_LIT> ) * ( cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun ->

machine -> callee_saved_gpr_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size + cfun -> machine -> eh_return_data_regs_size ) ;


<s> FunctionPass * createSVEAddressingModesPass (


<s> if ( I == MemOp2RegOpTable . end ( ) ) return <NUM_LIT> ; bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; if ( UnfoldLoad && ! FoldedLoad ) return <NUM_LIT> ; if ( UnfoldStore && ! FoldedStore ) return <NUM_LIT> ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & <NUM_LIT> ; return I -> second . first


<s> else if ( Features & <STR_LIT> || Features & <STR_LIT> || Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_3 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features & <STR_LIT> || Features & <STR_LIT> || Features & <STR_LIT> ) EFlags |=


<s> bool NeedPlus = false ; if ( HasBaseReg ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! HasBaseReg ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ECX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RegNo - <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> for ( MachineBasicBlock :: reverse_iterator I ( slot ) ; I != MBB . rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: iterator FI ( llvm :: next ( I ) . base ( ) ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> getDesc ( ) . isPseudo ( ) ) break ; if ( delayHasHazard ( FI , sawLoad , sawStore , RegDefs , RegUses ) ) { insertDefsUses ( FI , RegDefs , RegUses )


<s> if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ; } else


<s> Streamer . visitUsedExpr ( * getSubExpr ( )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> static tree ix86_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string (


<s> for ( ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( MI . isCall ( ) || MI . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI . isDebugInstr ( ) ) MI2LocMap [ & MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; unsigned Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; auto FindBases = [ & ] ( Base2InstMap & Base2Ops , BaseVec & Bases ) { MapIt BI = Base2Ops . find ( Base ) ; if ( BI == Base2Ops . end ( ) ) { Base2Ops [ Base ] . push_back ( & MI ) ; Bases . push_back ( Base ) ; return ; } for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } ; if ( isLd ) FindBases ( Base2LdsMap , LdBases ) ; else FindBases ( Base2StsMap , StBases ) ; if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear ( )


<s> Entry . Node = RetPtr ; Entry . Ty = PointerType :: getUnqual ( RetTy ) ; if ( ! Subtarget -> is64Bit ( ) ) Entry . isSRet = true ; Entry . isReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv

:: C , RetTyABI , Callee , std :: move ( Args ) , <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT NeonMovVT ; unsigned Imm = <NUM_LIT> ; unsigned OpCmode = <NUM_LIT> ; if ( isNeonModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VT . is128BitVector ( ) , Neon_Mov_Imm , NeonMovVT , Imm , OpCmode ) ) { SDValue ImmVal = DAG . getTargetConstant ( Imm , <STR_LIT> ) ; SDValue OpCmodeVal = DAG . getConstant ( OpCmode , <STR_LIT> ) ; if ( ImmVal . getNode ( ) && OpCmodeVal . getNode ( ) ) { SDValue NeonMov = DAG . getNode ( <STR_LIT> , DL , NeonMovVT , ImmVal , OpCmodeVal ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NeonMov ) ; } } uint64_t NegatedImm = ( ~ SplatBits ) . getZExtValue ( ) ; if ( isNeonModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VT . is128BitVector ( ) , Neon_Mvn_Imm , NeonMovVT , Imm , OpCmode ) ) { SDValue ImmVal = DAG . getTargetConstant ( Imm , <STR_LIT> ) ; SDValue OpCmodeVal = DAG . getConstant ( OpCmode , <STR_LIT> ) ; if ( ImmVal . getNode ( ) && OpCmodeVal . getNode ( ) ) { SDValue NeonMov = DAG . getNode ( <STR_LIT> , DL , NeonMovVT , ImmVal , OpCmodeVal ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NeonMov ) ; } } if ( ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && SplatBitSize == <NUM_LIT> ) || ( VT == <STR_LIT> && SplatBitSize == <NUM_LIT> ) ) { APFloat RealVal ( SplatBitSize == <NUM_LIT> ? APFloat :: IEEEsingle : APFloat :: IEEEdouble , SplatBits ) ; uint32_t ImmVal ; if ( A64Imms :: isFPImm ( RealVal


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: x86 , true > X ( getThe<ISA_LIT>_32Target ( ) , <STR_LIT> , <STR_LIT> ,


<s> bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB ) ; } if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc


<s> bool isMachineVerifierClean ( ) const override { return


<s> error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , expected ) ; return false ; } return true


<s> if ( isEntryPredicatedOnVCTP ( Block , false ) || hasImplicitlyValidVPT ( Block , RDA ) ) continue ; SmallVectorImpl < MachineInstr * > & Insts = Block . getInsts ( ) ; for ( auto * MI : Insts ) { if ( isVCTP ( MI ) && getVPTInstrPredicate ( * MI ) != <STR_LIT> ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> || isVectorPredicate ( MI ) ) continue ; if ( ! isPredicatedOnVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return


<s> return ( __m512 ) __builtin_ia32_loadaps512_mask ( ( const __v16sf * ) __P , ( __v16sf ) __W


<s> bool isVmovf = TyOp -> isToken ( ) && ( TyOp -> getToken ( ) == <STR_LIT> || TyOp -> getToken ( ) == <STR_LIT> ) ; <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; bool isFconst = Mnemonic -> isToken ( ) && ( Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> ) ; if ( ! ( isVmovf || isFconst ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; if ( Tok . is ( AsmToken :: Real ) && isVmovf ) { APFloat RealVal ( APFloat :: IEEEsingle , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( IntVal , getContext ( ) ) , S , Parser . getTok ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) && isFconst ) { int64_t Val = Tok . getIntVal ( ) ; Parser . Lex (


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . getImplicitDefs ( ) && ! TID . hasOptionalDef ( ) ) return false ; bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found =


<s> assert ( Imm12 < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ; bool isSub = Opc ==


<s> if ( align < <NUM_LIT> || TYPE_USER_ALIGN ( type ) ) return align ; type = strip_array_types ( type ) ; if ( TYPE_ATOMIC ( type ) ) return align ; mode = TYPE_MODE


<s> bool useNEONForSinglePrecisionFP ( ) const { return hasNEON ( ) &&


<s> const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = <STR_LIT> <= Reg && Reg <= <STR_LIT> ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled =


<s> EVT RootVT = Root . getValueType ( ) ; unsigned RootSizeInBits = RootVT . getSizeInBits ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( SDValue & NewInput : WideInputs ) { assert ( ( WideSizeInBits % NewInput . getValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( WideSizeInBits > NewInput . getValueSizeInBits ( ) ) NewInput = widenSubVector ( NewInput , false , Subtarget , DAG , SDLoc ( NewInput ) , WideSizeInBits ) ; assert ( WideSizeInBits == NewInput . getValueSizeInBits ( ) && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts ] ; } WideMask . append ( ( Scale - <NUM_LIT> ) * NumMaskElts , SM_SentinelUndef ) ; resolveTargetShuffleInputsAndMask ( WideInputs , WideMask ) ; assert ( ! WideInputs . empty ( ) && <STR_LIT> ) ; if ( WideInputs . size ( ) > <NUM_LIT> )


<s> int <ISA_LIT>FrameLowering :: getSEHFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const auto * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; int ObjectOffset = MF . getFrameInfo ( ) . getObjectOffset


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( Subtarget . hasMVEIntegerOps ( ) && shouldGenerateInlineTPLoop ( Subtarget , DAG , ConstantSize , Alignment , true ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dst , Src , DAG . getZExtOrTrunc ( Size , dl , <STR_LIT> ) ) ; if ( Alignment < Align ( <NUM_LIT> ) ) return SDValue ( ) ; if ( ! ConstantSize ) return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMCPY ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget . getMaxInlineSizeThreshold ( ) ) return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMCPY ) ; unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MaxLoadsInLDM = Subtarget . isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && Subtarget . hasMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return


<s> if ( Res != MatchOperand_Success ) return Res ; if ( ParseSuffix && Kind . empty ( ) ) return MatchOperand_NoMatch ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEDataVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , S , getContext ( ) ) ) ; return MatchOperand_Success ; } getParser ( ) . Lex (


<s> if ( IdxVal >= NumElems / <NUM_LIT> ) IdxVal -= NumElems / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert


<s> bool <ISA_LIT>AsmParser :: parseComma ( ) { if ( check ( getTok ( ) . isNot ( AsmToken :: Comma ) , getLoc (


<s> Cost = vectorCostAdjustment ( Cost , Opcode , Src , nullptr ) ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || * Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ! ST -> hasP8Vector ( ) && IsAltivecType ) && * Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return


<s> if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode


<s> bool function_checker :: argument_exists_p ( unsigned int argno ) { gcc_assert ( argno < ( unsigned int )


<s> bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( getThe<ISA_LIT>V9Target (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg )


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const ThumbCalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const DarwinCalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( STI . isThumb1Only


<s> case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; } if ( Is64Bit


<s> return make_unique < <ISA_LIT>DCInstruction >


<s> return ConstantPools -> addEntry ( Streamer ,


<s> unsigned Reg = F128RegDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin ( ) + IdxVal , ElemsPerChunk ) ) ; SDValue VecIdx = DAG . getIntPtrConstant ( IdxVal


<s> scalar_mode elem_mode = GET_MODE_INNER ( mode ) ; elem = force_reg ( elem_mode , elem ) ; insn_code icode = optab_handler ( vec_shl_insert_optab , mode ) ; gcc_assert ( icode != CODE_FOR_nothing ) ; emit_insn ( GEN_FCN ( icode ) ( target , target ,


<s> switch ( NumInsts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg


<s> return ( __m128i ) __builtin_ia32_vpmacssdqh ( ( __v4si ) __A , ( __v4si ) __B , (


<s> FunctionPass * llvm :: create<ISA_LIT>DiscriminateMemOpsPass (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( Triple ( TT ) . isOSBinFormatMachO ( ) ? <STR_LIT> : ( LittleEndian ? <STR_LIT> : <STR_LIT> ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( )


<s> <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , CCInfo ) ; Function :: const_arg_iterator FuncArg = DAG . getMachineFunction ( ) . getFunction ( ) -> arg_begin ( ) ; bool UseSoftFloat = getTargetMachine ( ) . Options . UseSoftFloat ; <ISA_LIT>CCInfo . analyzeFormalArguments ( Ins , UseSoftFloat , FuncArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , <ISA_LIT>CCInfo . hasByValArg ( ) ) ; unsigned CurArgIdx = <NUM_LIT> ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; std :: advance ( FuncArg , Ins [ i ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ i ] . OrigArgIndex ; EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { EVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = Subtarget -> in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC =


<s> unsigned RegOut = get<ISA_LIT>SubSuperRegister ( RegIn , <STR_LIT> , false ) ; assert ( RegOut !=


<s> for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , VLD -> getDebugLoc ( ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt


<s> machine_mode omode ; copyto [ o ] = <NUM_LIT> ; omode = ( machine_mode ) insn_data [ code ] . operand [ o ] . mode ; if ( ao == 'r' ) op [ o ] = target ? target : gen_reg_rtx ( omode ) ; else if ( ao == 't' ) op [ o ] = gen_reg_rtx ( omode ) ; else op [ o ] = args [ ( int ) hex_value ( ao ) ] ; if ( ! ( * insn_data [ code ] . operand [ o ] . predicate ) ( op [ o ] , GET_MODE ( op [ o ] ) ) ) { if ( c == '+' || c == '=' ) { copyto [ o ] = op [ o ] ; op [ o ] = gen_reg_rtx ( omode ) ; } else op [ o ] = copy_to_mode_reg ( omode , op [ o ] ) ; } if ( ao == 'r' ) retval = op [ o ] ; } pat = GEN_FCN ( code ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; emit_insn ( pat ) ; for ( o = <NUM_LIT> ; s16builtins [ i ] . arg_ops [ o ] ; o ++ ) if ( copyto [ o ] ) { emit_move_insn ( copyto [ o ] , op [ o ] ) ; if ( op [ o ] == retval ) retval = copyto [


<s> static __inline void _mm_sfence ( void ) { __builtin_ia32_sfence (


<s> unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) { if ( ! Bits [ i ] . hasValue ( ) || Bits [ i ] . getValue ( ) != VRI . V ) continue ; if ( RLAmt [ i ] != VRI . RLAmt ) continue ; Mask |= ( <NUM_LIT> << i ) ; } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { TruncateToInt32 ( VRI . V , dl ) , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = TruncateToInt32 ( VRI . V ,


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const


<s> DenseMap < MachineBasicBlock * , VisitedBBInfo > :: iterator it = VisitedBBs . find ( MBB ) ; if ( it != VisitedBBs . end ( ) ) { VisitedBBInfo BBInfo = it -> second ; Cycles += BBInfo . Cycles ; return BBInfo . HasReturn ; } unsigned int CyclesToEnd = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MBBI != MBB -> end ( ) ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isReturn ( ) && ! MI -> isCall ( ) ) { VisitedBBs [ MBB ] = VisitedBBInfo ( true , CyclesToEnd ) ; Cycles += CyclesToEnd ; return true ; } CyclesToEnd += TII -> getInstrLatency ( TM -> getInstrItineraryData ( ) , MI ) ; } VisitedBBs [ MBB ] = VisitedBBInfo ( false , CyclesToEnd ) ; Cycles += CyclesToEnd


<s> unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDiu = isN64 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isN64 ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDiu ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = isN64 ? <STR_LIT> : <STR_LIT> ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget


<s> int LaneStart = l * LaneSize ; for ( int i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + LaneStart ] , LaneStart , LaneStart + LaneSize ) ) return false ; if ( NumElts == <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + LaneStart ] , Mask [ i ] + LaneSize ) ) return false ; } } return


<s> break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_XMM128 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM256 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_MOFFS8


<s> uint64_t <ISA_LIT>GOT :: getGPRelOffset ( const Input & pInput , const Fragment & pEntry ) const { return addr ( ) + pEntry . getOffset ( ) - getGPAddr ( pInput


<s> if ( ! ResVT . isSimple ( ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( InNVT . getVectorNumElements ( ) ) ) ; Lo = DAG . getNode ( N -> getOpcode ( ) , DL , LoVT , Lo ) ; Hi = DAG . getNode ( N -> getOpcode ( ) , DL , HiVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Lo ,


<s> return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; }


<s> CASE_AARCH64_ATOMIC_ ( LDADDA ) : CASE_AARCH64_ATOMIC_ ( LDADDAL ) : CASE_AARCH64_ATOMIC_ ( LDCLRA ) : CASE_AARCH64_ATOMIC_ ( LDCLRAL ) : CASE_AARCH64_ATOMIC_ ( LDEORA ) : CASE_AARCH64_ATOMIC_ ( LDEORAL ) : CASE_AARCH64_ATOMIC_ ( LDSETA ) : CASE_AARCH64_ATOMIC_ ( LDSETAL ) : CASE_AARCH64_ATOMIC_ ( LDSMAXA ) : CASE_AARCH64_ATOMIC_ ( LDSMAXAL ) : CASE_AARCH64_ATOMIC_ ( LDSMINA ) : CASE_AARCH64_ATOMIC_ ( LDSMINAL ) : CASE_AARCH64_ATOMIC_ ( LDUMAXA ) : CASE_AARCH64_ATOMIC_ ( LDUMAXAL ) : CASE_AARCH64_ATOMIC_ ( LDUMINA ) : CASE_AARCH64_ATOMIC_ ( LDUMINAL ) : CASE_AARCH64_ATOMIC_ ( SWPA ) : CASE_AARCH64_ATOMIC_ (


<s> } aa , bb ; aa . v = ( vector unsigned int ) ( a ) ; bb . v = ( vector unsigned


<s> unsigned MaskTZ = countTrailingZeros ( Mask ) ; unsigned AMShiftAmt = MaskTZ ; if ( AMShiftAmt <= <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; if ( countTrailingOnes ( Mask >> MaskTZ ) + MaskTZ + MaskLZ != <NUM_LIT> ) return true ; MaskLZ -= ( <NUM_LIT> - X . getSimpleValueType ( ) . getSizeInBits ( ) ) + ShiftAmt ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSRLAmt


<s> void <ISA_LIT>TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE ,


<s> Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType (


<s> if ( kind == vec_to_scalar && where == vect_body && sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( kind == vec_to_scalar && where == vect_epilogue && aarch64_is_reduction ( stmt_info ) ) switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_QImode : return simd_costs -> reduc_i8_cost ; case E_HImode : return simd_costs -> reduc_i16_cost ; case E_SImode : return simd_costs -> reduc_i32_cost ; case