<s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ; if ( MBB . succ_size (


<s> const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int imm2 = MI . getOperand ( imm2_pos ) . getImm ( ) ; int imm3 = MI . getOperand ( imm3_pos ) . getImm ( ) ; if ( imm2 + imm3 <= <NUM_LIT> ) { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> - imm2 - imm3 ) ; newMI . addImm ( imm3 ) ; } else { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> ) ; } MI . eraseFromParent ( ) ; return


<s> if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CheckReg ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( TargetFlags & <STR_LIT> ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( ( TargetFlags & <STR_LIT> ) && ( DestReg == <STR_LIT> ) ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) CheckReg = Inst . getOperand ( <NUM_LIT> ) .


<s> const MCTargetOptions & getTargetOptions ( ) const


<s> bool <ISA_LIT>FrameLowering :: shouldEnableVectorUnit ( MachineFunction & MF ) const { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget


<s> Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , {

AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VecVT , Res , Lo , DAG . getIntPtrConstant ( LoVT . getVectorMinNumElements ( ) , DL ) ) ; } IntVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; GatherOpc = <STR_LIT> ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultScalableVLOps ( VecVT , DL , DAG , Subtarget ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; SDValue VLMinus1 = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && IntVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatVL ; if ( ! IsRV32E64 ) SplatVL = DAG . getSplatVector ( IntVT , DL , VLMinus1 ) ; else SplatVL = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , VLMinus1 , DAG . getRegister ( <STR_LIT> , XLenVT ) ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , IntVT , Mask , VL ) ; SDValue Indices = DAG . getNode ( <STR_LIT> , DL ,


<s> void <ISA_LIT>InstrInfo :: movImm32 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Lo12


<s> void function_builder :: apply_predication ( const function_instance & instance , tree return_type , vec < tree > & argument_types ) const { if ( instance . base -> has_merge_operand_p ( ) ) if ( instance . pred == PRED_TYPE_tu || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , return_type ) ; vector_type_index mask_type_index = function_types [ instance . type . index ] . type_indexes [ RVV_BASE_mask ] ; tree mask_type = builtin_types [ mask_type_index ] . vector ; if ( instance . pred == PRED_TYPE_m || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , mask_type ) ; if ( instance . base -> apply_vl_p ( ) ) argument_types


<s> MVT InterVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; auto InterVec = DAG . getNode ( <STR_LIT> , DL , InterVT , Lo , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , InterVec ) ; } } return DAG . getNode ( <STR_LIT> , DL , VT , Lo ,


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode


<s> rtx riscv_unspec_address ( rtx address , enum riscv_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) { initAsmInfo ( ) ; setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true


<s> if ( Subtarget . hasStdExtV ( ) ) preAssignMask ( Outs , FirstMaskArgument , CCInfo ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode *


<s> if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic != InstrInfo . MaskAgnostic ) return false ; return getSEWLMULRatio ( ) == getSEWLMULRatio (


<s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; CurInfo = getInfoForVSETVLI ( MI ) ; PrevVSETVLIMI = & MI ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( <STR_LIT> ( TSFlags ) ) { unsigned Offset = <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) Offset = <NUM_LIT> ; MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - Offset ) ; if ( VLOp . isReg ( ) ) { VLOp . setReg ( <STR_LIT> ) ; VLOp . setIsKill ( false ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> ,


<s> switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || ( Subtarget . is64Bit ( ) && MemVT == <STR_LIT> ) ) && ( LD -> getExtensionType ( ) == <STR_LIT> || LD -> getExtensionType ( ) == <STR_LIT> ) ) return true ; } return TargetLowering :: isZExtFree ( Val , VT2


<s> static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler :: Success


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( STI , OSABI , TT . isArch64Bit ( )


<s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else if ( LMUL == <NUM_LIT> ) { Opcode = <STR_LIT> ; SubRegIdx = <STR_LIT> ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , AddrInc ) . addReg ( Base ) . addReg ( VL ) ; Base = AddrInc ; } } MBBI -> eraseFromParent ( ) ; return


<s> if ( type == error_mark_node ) return NULL_TREE ; return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES


<s> rtx set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set )


<s> if ( hasAVLReg ( ) ) OS << <STR_LIT> << ( unsigned ) AVLReg ; if ( hasAVLImm ( ) ) OS << <STR_LIT> << ( unsigned ) AVLImm ; OS << <STR_LIT> << <STR_LIT> << ( unsigned ) VLMul << <STR_LIT> << <STR_LIT> << ( unsigned ) SEW << <STR_LIT> << <STR_LIT> << ( bool ) TailAgnostic << <STR_LIT> << <STR_LIT> << ( bool ) MaskAgnostic << <STR_LIT> << <STR_LIT> << ( bool ) MaskRegOp << <STR_LIT> << <STR_LIT>

<< ( bool ) StoreOp << <STR_LIT> << <STR_LIT> << ( bool ) ScalarMovOp << <STR_LIT> << <STR_LIT> << ( bool ) SEWLMULRatioOnly << <STR_LIT> ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } if ( LIS ) { SlotIndex Idx = LIS -> ReplaceMachineInstrInMaps ( MI , *


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O <<


<s> init_derived_machine_modes ( ) ; reinit_regs ( ) ; init_optabs (


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { XLenVT =


<s> static SDValue unpackFromMemLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) . getKnownMinSize ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : if ( ValVT . isScalableVector ( ) ) { return DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack (


<s> static bool CC_<ISA_LIT>Assign2XLen ( unsigned XLen , CCState & State , CCValAssign VA1 , <STR_LIT> ArgFlags1 , unsigned ValNo2 , MVT ValVT2 , MVT LocVT2 , <STR_LIT> ArgFlags2 ) { unsigned XLenInBytes = XLen / <NUM_LIT> ; if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , Reg , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; } else { unsigned StackAlign = std :: max ( XLenInBytes , ArgFlags1 . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , Align ( StackAlign ) ) , VA1 . getLocVT (


<s> MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup , NopBytes , FixedValue ) ; return


<s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ; return Buf . str ( )


<s> const <ISA_LIT>Subtarget & STI = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode == <STR_LIT> ) || Opcode


<s> return expandAuipccInstPair ( MBB , MBBI , NextMBBI , <STR_LIT>


<s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind ; if ( IsCap ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ; Identifier . consume_back ( <STR_LIT> ) ; } else { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64


<s> rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr ) ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( GET_MODE_INNER ( mode


<s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( C && C -> isAllOnesValue ( )


<s> else set = nullptr ; } uint8_t sew = get_sew ( insn -> rtl ( ) ) ; enum vlmul_type vlmul = get_vlmul ( insn -> rtl ( ) ) ; uint8_t ratio = get_attr_ratio ( insn -> rtl ( ) ) ; if ( ratio == INVALID_ATTRIBUTE ) ratio = calculate_ratio ( sew , vlmul ) ; bool ta = tail_agnostic_p ( insn -> rtl ( ) ) ; bool ma = mask_agnostic_p ( insn -> rtl ( ) ) ; int merge_op_idx = get_attr_merge_op_idx ( insn


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL ,


<s> for ( unsigned int i = <NUM_LIT> ; all_ops [ i ] . index != NUM_VECTOR_TYPES ; i ++ ) if ( type_idx == all_ops [ i ] . index

) return all_ops [ i ] . required_extensions ;


<s> if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget .

hasStdExtZfhmin ( ) ) return <NUM_LIT> ;


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm


<s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> )


<s> if ( hasAVLImm ( ) != Other . hasAVLImm ( ) ) return false ; if ( hasAVLImm ( ) ) return getAVLImm ( ) == Other . getAVLImm ( ) ; return getAVLReg ( ) == Other .


<s> insn_info * insn2 = extract_single_source ( set2 ) ; if ( ! insn1 || ! insn2 ) return false ; return source_equal_p ( insn1 , insn2


<s> Lower . lower ( MI , LoweredMI ) ; EmitToStreamer ( * OutStreamer


<s> while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) { assert ( hasFP ( MF )


<s> Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case


<s> if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ; unsigned Max = std :: max ( RVVVectorBitsMin ,


<s> int getMoveF64FrameIndex ( MachineFunction & MF ) { if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , Align (


<s> } } if ( Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( isVectorConfigInstr ( * DefMI ) ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameVLMAX ( Require ) && ( DefInfo . hasAVLImm ( ) || DefInfo . getAVLReg ( ) == <STR_LIT> ) ) { MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( DefInfo . hasAVLImm ( ) ) VLOp . ChangeToImmediate ( DefInfo . getAVLImm ( ) ) ; else VLOp . ChangeToRegister ( DefInfo . getAVLReg ( ) , false ) ; CurInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; continue ; } } } } } CurInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; continue ; } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> )

|| MI . modifiesRegister ( <STR_LIT> ) ) CurInfo = <STR_LIT> ( ) ;


<s> if ( optimize_bb_for_speed_p ( bb ) ) continue ; m = analyze (


<s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'r' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'w' ; if ( FenceArg == <NUM_LIT>


<s> return Kind == KindTy :: Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg .


<s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand (


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode


<s> unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; Size = AF . getAlignment ( ) - MinNopLen ; return true


<s> bool isRV64 ( ) const { return <ISA_LIT>ArchVersion == RV64


<s> static SDValue performBITREVERSECombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Subtarget . hasStdExtZbkb ( ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( getSEWOpNum ( MI ) ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ; else InstrInfo . setAVLImm ( Imm ) ; } else { InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; } } else


<s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; EVT VT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; ReplaceNode ( Node


<s> function_expander :: function_expander ( const function_instance & instance , tree fndecl_in , tree exp_in , rtx target_in ) : function_call_info ( EXPR_LOCATION ( exp_in ) , instance , fndecl_in ) , exp ( exp_in ) ,

target ( target_in ) , opno ( <NUM_LIT> ) {


<s> void <ISA_LIT>ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx


<s> for ( const set_info * set : sets ) if ( set -> bb ( ) -> index ( ) == bb -> index ( ) ) return true ; return false


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BSelPass ( * PassRegistry :: getPassRegistry


<s> DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout , & AF , Fixup ,


<s> <ISA_LIT>LegalizerInfo :: <ISA_LIT>LegalizerInfo ( const <ISA_LIT>Subtarget & ST ) { getLegacyLegalizerInfo ( ) . computeTables


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore


<s> static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_SINGLE ; break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_DOUBLE ; break ; case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_RVE ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } MCA . setELFHeaderEFlags (


<s> OS << getRegisterName ( MI -> getOperand ( opNum + <NUM_LIT> ) . getReg (


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> static void register_builtin_types ( ) { tree int8_type_node = get_typenode_from_name ( INT8_TYPE ) ; tree uint8_type_node = get_typenode_from_name ( UINT8_TYPE ) ; tree int16_type_node = get_typenode_from_name ( INT16_TYPE ) ; tree int32_type_node = get_typenode_from_name (


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( PhysReg


<s> unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ; if ( Op0 . getValueType ( ) != NarrowVT ) Op0 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op0 , Mask , VL ) ; ExtOpc = IsVWMULSU ? <STR_LIT> : ExtOpc ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WMulOpc = <STR_LIT> ; if ( ! IsVWMULSU ) WMulOpc = IsSignExt


<s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > (


<s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ; return Buf . str ( )


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) ||


<s> default : return ; case VK_<ISA_LIT>_TPREL_HI20 : case VK_<ISA_LIT>_TPREL_LO12 : break ; } fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm


<s> struct riscv_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ; return riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg .


<s> bool enableCheriRVCInstrs ( ) const { return


<s> if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ; return


<s> void <ISA_LIT>InstPrinter :: printUimm32contig1endOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O <<


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT>


<s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) !=


<s> if ( NumElts <= LargestEltVT . getSizeInBits ( ) ) { assert ( isPowerOf2_32 ( NumElts ) && <STR_LIT> ) ; WideEltVT = <STR_LIT> ( NumElts ) ; WidenVecLen = <NUM_LIT> ; ExtractElementIdx = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ExtractBitIdx = Idx ; } else { WideEltVT = LargestEltVT ; WidenVecLen = NumElts / WideEltVT . getSizeInBits ( ) ; ExtractElementIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( Log2_64 ( WideEltVT . getSizeInBits ( ) ) , DL , XLenVT ) ) ; ExtractBitIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( WideEltVT . getSizeInBits ( ) - <NUM_LIT> , DL , XLenVT ) ) ; } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; } MVT ContainerVT = VecVT


<s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ; return MCDisassembler ::


<s> high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) , FALSE ) ; } return plus_constant ( Pmode ,


<s> if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success


<s> bool isUnknown ( ) const { return State == Unknown


<s> if ( to == HARD_FRAME_POINTER_REGNUM ) dest = cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( to == STACK_POINTER_REGNUM ) dest = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ; else gcc_unreachable ( )


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; } auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT>


<s> const char * mangle_builtin_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL )

type = TREE_TYPE ( TYPE_NAME ( type ) ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( getVType ( ) )


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { * base = XEXP (


<s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; if ( Res ) ++ <ISA_LIT>NumInstrsCompressed


<s> rtx insn , dwarf , adjust_frame_rtx ; riscv_legitimize_poly_move ( Pmode , adjust_size , tmp , gen_int_mode ( offset , Pmode ) ) ; if ( epilogue ) insn = gen_add3_insn ( target , target , adjust_size ) ; else insn = gen_sub3_insn ( target , target , adjust_size ) ; insn = emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; adjust_frame_rtx = gen_rtx_SET ( target , plus_constant ( Pmode , target , epilogue ? offset : - offset ) ) ; dwarf = alloc_reg_note ( REG_FRAME_RELATED_EXPR , copy_rtx ( adjust_frame_rtx ) , NULL_RTX ) ; REG_NOTES ( insn )


<s> const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; AsmToken Tok = getLexer ( ) . getTok ( ) ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex


<s> set_info * set = safe_dyn_cast < set_info * > ( def ) ; set_avl_info ( avl_info ( vl , set ) ) ; set_insn ( insn ) ; return true ; } return false


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo ,

uint64_t Address , const void * Decoder ) {


<s> BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * LoopHeadMBB ) ; computeAndAddLiveIns ( LiveRegs , * LoopTailMBB


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType (


<s> assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned Opcode ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ; assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register DstReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ; MBBI -> eraseFromParent


<s> if ( ! DCI . isBeforeLegalize ( ) ) break ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || RHS -> getOpcode ( ) == <STR_LIT> || ( RHS -> getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) break ; if ( ! isVariableShift ( Src ) && ! ( Subtarget . hasStdExtM ( ) && isVariableSDivUDivURem ( Src ) ) ) break ; SDLoc DL ( N ) ; return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ) ; } case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> ) break ; return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT>


<s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( )


<s> assert ( Store && Store -> getValue ( ) . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Store -> getMemoryVT ( ) , * Store -> getMemOperand ( ) ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue StoredVal = Store -> getValue ( ) ; MVT VT = StoredVal . getSimpleValueType ( ) ; unsigned EltSizeBits = VT . getScalarSizeInBits ( ) ; assert ( ( EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> ) && <STR_LIT> ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; StoredVal = DAG . getBitcast ( NewVT , StoredVal ) ; return DAG . getStore ( Store -> getChain ( ) , DL , StoredVal , Store -> getBasePtr ( ) , Store -> getPointerInfo ( ) , Store -> getOriginalAlign ( ) ,

Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> bool <ISA_LIT>Subtarget :: useRVVForFixedLengthVectors ( )


<s> void add_policy_operand ( enum tail_policy vta , enum mask_policy vma ) { rtx tail_policy_rtx = gen_int_mode (


<s> if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { vl_regno = regno ; break ; } } if ( vl_regno > GP_REG_LAST ) sorry ( <STR_LIT> , <STR_LIT> ) ; bool emitted_vlmax_vsetvl = false ; rtx vl = gen_rtx_REG ( Pmode , vl_regno ) ; for ( unsigned regno = V_REG_FIRST ; regno <= V_REG_LAST ; ++ regno ) { if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { rtx target = regno_reg_rtx [ regno ] ; machine_mode mode = GET_MODE ( target ) ; poly_uint16 nunits = GET_MODE_NUNITS (


<s> Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( IsScalableVector ) { if ( NF == <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Opc ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; int I = <NUM_LIT> , End = NF , Incr = <NUM_LIT> ; unsigned SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned DstEncoding = TRI -> getEncodingValue ( DstReg ) ; if ( forwardCopyWillClobberTuple ( DstEncoding , SrcEncoding , NF * LMul ) ) { I = NF - <NUM_LIT>


<s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( saved_size ) ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } return


<s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ; return combineSelectAndUseCommutative ( N , DAG , false


<s> } if ( immediate_operand ( scalar_op , Pmode ) ) { ops [ <NUM_LIT> ] = gen_rtx_SIGN_EXTEND ( scalar_mode , force_reg ( Pmode , scalar_op ) ) ; ops [ <NUM_LIT> ] = force_vector_length_operand ( ops [ <NUM_LIT> ] ) ; return false ; } if ( CONST_INT_P ( scalar_op ) ) scalar_op = force_reg ( scalar_mode , scalar_op ) ; rtx vl_x2 = get_vl_x2_rtx ( avl , mode , demote_mode ) ; rtx demote_scalar_op1 , demote_scalar_op2 ; if ( unspec == UNSPEC_VSLIDE1UP ) { demote_scalar_op1 = gen_highpart ( Pmode , scalar_op ) ; demote_scalar_op2 = gen_lowpart ( Pmode , scalar_op ) ; } else { demote_scalar_op1 = gen_lowpart ( Pmode , scalar_op ) ; demote_scalar_op2 = gen_highpart ( Pmode , scalar_op ) ; } rtx temp = gen_reg_rtx ( demote_mode ) ; rtx ta = gen_int_mode ( get_prefer_tail_policy ( ) , Pmode ) ; rtx ma = gen_int_mode ( get_prefer_mask_policy ( ) , Pmode ) ; rtx merge = RVV_VUNDEF ( demote_mode ) ; if ( register_operand ( ops [ <NUM_LIT> ] , mode ) && rtx_equal_p ( ops [ <NUM_LIT> ] , CONSTM1_RTX ( GET_MODE ( ops [ <NUM_LIT> ] ) ) ) ) { merge = gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) ; ta = ops


<s> if ( type == error_mark_node ) return NULL_TREE


<s> void setVarArgsFirstFPR ( unsigned FPR ) { VarArgsFirstFPR = FPR


<s> JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; return getAddr ( N ,


<s> static bool matchRegisterNameHelper ( bool IsRV32E , unsigned & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <NUM_LIT> ; return RegNo


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; return


<s> static MCStreamer * create<ISA_LIT>MCObjectStreamer ( const Triple & TT , MCContext & Ctx , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter *


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI ,


<s> info -> num_gprs = <NUM_LIT> ; info -> num_fprs = <NUM_LIT> ; if ( ! SCALAR_FLOAT_TYPE_P ( fields [ <NUM_LIT> ] . type ) ) std :: swap ( fregno , gregno ) ; return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , gregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; } } num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( ! named && num_bytes != <NUM_LIT> && alignment > BITS_PER_WORD ) info -> gpr_offset += info -> gpr_offset & <NUM_LIT> ; info -> num_fprs = <NUM_LIT> ; info -> num_gprs = MIN ( num_words , MAX_ARGS_IN_REGISTERS - info -> gpr_offset ) ; info -> stack_p = ( num_words - info -> num_gprs ) != <NUM_LIT> ; if ( info -> num_gprs || return_p ) return gen_rtx_REG ( mode , gpr_base + info


<s> ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc , SplatZero , <STR_LIT> ) ; } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , SplatOne , Mask , VL ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , MaskContainerVT , Trunc , SplatZero , DAG . getCondCode ( <STR_LIT> ) ,


<s> return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) && ( find_access ( insn -> defs ( ) , VL_REGNUM ) || find_access ( insn -> defs ( ) , VTYPE_REGNUM ) ) ) { set_unknown ( ) ; return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) ) return ; vl_vtype_info :: operator = ( get_vl_vtype_info ( insn ) ) ; m_insn = insn ; m_state = VALID ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_demands [ DEMAND_AVL ] = true ; m_demands [ DEMAND_RATIO ] = true ; return ; } if ( has_vl_op ( insn -> rtl ( ) ) ) m_demands [ DEMAND_AVL ] = true ; if ( get_attr_ratio ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_RATIO ] = true ; else { m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ DEMAND_LMUL ] = true ; } if ( get_attr_ta ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_TAIL_POLICY ] = true ; if ( get_attr_ma ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_MASK_POLICY ] = true ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) return ; if ( scalar_move_insn_p ( insn -> rtl ( )


<s> return function_instance ( <STR_LIT> , bases :: read_vl , shapes :: read_vl , none_ops

[ <NUM_LIT> ] , PRED_TYPE_none , & p_none_void_ops ) ;


<s> int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( IsVarArg ) { auto ArgRegs = IsRV32 ? RV32IntRegs : RV64IntRegs ; unsigned NumRegs = llvm :: <STR_LIT> ; unsigned Idx = CCInfo . getFirstUnallocated ( ArrayRef < MCPhysReg > ( ArgRegs , <NUM_LIT> ) ) ; unsigned RegSize = IsRV32 ? <NUM_LIT> : <NUM_LIT> ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = alignTo ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } } if ( ! OutChains . empty ( ) ) { OutChains . push_back (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI ,


<s> Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return


<s> rtx set2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set1 )


<s> basic_block cfg_bb ; rtx_insn * rinsn ; FOR_ALL_BB_FN ( cfg_bb , fn ) FOR_BB_INSNS ( cfg_bb , rinsn ) if ( NONDEBUG_INSN_P ( rinsn ) && has_vtype_op ( rinsn ) ) return true ; return false


<s> int elmul_log2 ; if ( sew == eew ) elmul_log2 = lmul_log2 ; else if ( sew > eew ) elmul_log2 = lmul_log2 - std :: log2 ( sew / eew ) ; else elmul_log2 = lmul_log2 + std :: log2 ( eew / sew ) ; if ( float_p ) return floattype (


<s> case VK_<ISA_LIT>_None : closeParen = false ; break ; case VK_<ISA_LIT>_LO12 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI20 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PCREL_LO12 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PCREL_HI20 : OS <<


<s> case EXCESS_PRECISION_TYPE_STANDARD : return ( ( TARGET_ZFH || TARGET_ZHINX ) ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand

:: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ;


<s> Register Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL ,

Node -> getValueType ( <NUM_LIT> ) , Operands ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Src . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc , SplatZero , <STR_LIT> ) ; } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT MaskContainerVT = ContainerVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , SplatOne ,


<s> return llvm :: all_of ( Values , [ ] ( SDValue V ) { return V -> isUndef ( )


<s> MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - Offset ) ; if ( VLOp . isReg ( ) ) { VLOp . setReg ( <STR_LIT> ) ; VLOp . setIsKill ( false ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI =


<s> vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avin = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avout = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_kill = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; bitmap_vector_ones ( vector_transp , last_basic_block_for_fn ( cfun ) ) ; bitmap_vector_clear ( vector_antic , last_basic_block_for_fn ( cfun )


<s> static MCSymbolRefExpr :: VariantKind getModifierVariantKind ( <STR_LIT> Modifier ) { switch ( Modifier ) { case <STR_LIT> : return MCSymbolRefExpr :: VK_NTPOFF ; } llvm_unreachable ( <STR_LIT>


<s> Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP ( MaxVal , DL , VT ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT ,


<s> const riscv_subset_t * end ( ) const


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return


<s> if ( ! N0 -> hasOneUse ( ) || N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * N0C = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; auto * N1C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! N0C || ! N1C ) return SDValue ( ) ; int64_t C0 = N0C -> getSExtValue ( ) ; int64_t C1 = N1C -> getSExtValue ( ) ; int64_t CA , CB ; if ( C0 == - <NUM_LIT> || C0 == <NUM_LIT> || C0 == <NUM_LIT> || isInt < <NUM_LIT> > ( C1 ) ) return SDValue ( ) ; if ( ( C1 / C0 ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 ) && isInt < <NUM_LIT> > ( C1 % C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 ) ) ) { CA = C1 / C0 ; CB = C1 % C0 ; } else if ( ( C1 / C0 + <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 + <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 - C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 + <NUM_LIT> ) ) ) { CA = C1 / C0 + <NUM_LIT> ; CB = C1 % C0 - C0 ; } else if ( ( C1 / C0 - <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 - <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 + C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 - <NUM_LIT> ) ) ) { CA = C1 / C0 - <NUM_LIT> ; CB = C1 % C0 + C0 ; } else return SDValue ( ) ; SDLoc DL ( N )


<s> bool <ISA_LIT>RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( MBB ) ; return


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; SDValue Srl = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { uint64_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t VC2 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; return VC1 == maskLeadingOnes < uint64_t > ( VC2 ) ; } uint32_t VC1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Srl . getConstantOperandVal (


<s> unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == XLenVT && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize +=


<s> if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCapModeOnly_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32CapModeOnly_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size =


<s> case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand


<s> unsigned getMaxInterleaveFactor ( ) const { return hasVInstructions ( ) ?


<s> const char * getPassName ( ) const override


<s> x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT


<s> I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return


<s> case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType (


<s> if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else return false


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; return getAddr ( N , DAG


<s> if ( ! isLoweredToCall ( Call -> getCalledFunction ( ) ) ) { continue ; } } return false ; } if ( auto * Branch = dyn_cast < BranchInst > ( & I ) ) { if ( Branch -> isUnconditional ( ) || L -> isLoopLatch ( BB ) ) { InstrCount -- ; continue ; } else if ( auto * Cond = dyn_cast < IntrinsicInst > ( Branch -> getCondition ( ) ) ) { if ( Cond -> getIntrinsicID ( ) == <STR_LIT> ) { HasInnerHardwareLoop = true ; Next = Branch -> getSuccessor ( <NUM_LIT> ) ; InstrCount = <NUM_LIT> ; continue ; } } } if ( I . isTerminator ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! TLI -> isOperationLegalOrCustom ( ISD , VT ) ) return false ; if ( I . getOpcode ( ) == Instruction


<s> if ( ! demand_p ( DEMAND_AVL ) ) return true ; if ( demand_p ( DEMAND_NONZERO_AVL ) && other . has_non_zero_avl ( ) ) return true ; return get_avl_info ( ) ==


<s> static void insertSext ( const <ISA_LIT>InstrInfo * TII , DebugLoc DL , MachineBasicBlock * MBB , unsigned ValReg , unsigned ShamtReg ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ValReg )

. addReg ( ValReg ) . addReg ( ShamtReg ) ;


<s> static unsigned calculate_sew ( vlmul_type vlmul


<s> if ( hasSameVTYPE ( Require ) ) return true ; if ( Require . MaskRegOp && hasSameVLMAX ( Require ) && TailAgnostic == Require . TailAgnostic && MaskAgnostic == Require .


<s> bool hasSameSEW ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ; assert ( ! isUnknown ( ) && ! Other . isUnknown


<s> static MCSymbolRefExpr :: VariantKind getVariantKind ( unsigned Flags ) { switch ( Flags & <STR_LIT>


<s> Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMOLo = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineMemOperand * MMOHi = MF . getMachineMemOperand ( MPI . getWithOffset ( <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI

) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOLo ) ;


<s> <STR_LIT> ( ) ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d =


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ; unsigned Opc = <NUM_LIT>


<s> unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT )


<s> CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT>


<s> switch ( code ) { case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_addr_const ( file , riscv_strip_unspec_address (


<s> static bool different_ratio_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return info1 . get_ratio ( ) !=


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; for ( int I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) if ( MFI . getStackID ( I ) == TargetStackID :: ScalableVector ) return true ; return


<s> if ( ! DF ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT> : return & F ; } } return nullptr


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Val . getOperand ( <NUM_LIT> ) . getOpcode


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { return


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; return getAddr ( N


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT>


<s> static rtx riscv_force_binary ( machine_mode mode , enum rtx_code code , rtx x , rtx y ) { return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x


<s> HOST_WIDE_INT shifted_val ; shifted_val = ( value << shift ) | ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << shift ) - <NUM_LIT> ) ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( ! TARGET_64BIT && ( value > INT32_MAX || value < INT32_MIN ) ) { unsigned HOST_WIDE_INT loval = sext_hwi ( value , <NUM_LIT> ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( value - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; struct riscv_integer_op hicode


<s> unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [


<s> unsigned SubRegClassID = getRegClassIDForVecVT ( SubVecVT ) ; unsigned SubRegIdx = <STR_LIT> ; for ( const unsigned RCID : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( VecRegClassID > RCID && SubRegClassID <= RCID ) { VecVT = VecVT . getHalfNumVectorElementsVT ( ) ; bool IsHi = InsertExtractIdx >= VecVT . getVectorElementCount ( )


<s> auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII ->


<s> SDValue <ISA_LIT>TargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( Op


<s> LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; if ( ! IsMasked ) doAtomicBinOpExpansion ( TII , MI , DL , & MBB ,


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef (


<s> if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ; unsigned VL = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return ( LT . first - <NUM_LIT> ) +


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT>


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) / <NUM_LIT> ; const MCExpr * Expr = MO . getExpr ( ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr ::


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI )


<s> assert ( Kind == KindTy :: VTypeImm && <STR_LIT> ) ; Twine vtypei ( getSEW ( Vtypei . Sew ) ) ; vtypei . concat ( Twine


<s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm .


<s> assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorLMULMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorLMULMax )


<s> poly_int64 riscv_v_adjust_bytesize ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { poly_uint16 mode_size = GET_MODE_SIZE ( mode ) ; if ( maybe_eq ( mode_size , ( uint16_t ) - <NUM_LIT> ) ) mode_size = riscv_vector_chunks * scale ; if ( known_gt ( mode_size , BYTES_PER_RISCV_VECTOR ) ) mode_size = BYTES_PER_RISCV_VECTOR ; return mode_size ; } return


<s> MF -> insert ( ++ LoopMBB -> getIterator ( ) , DoneMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; if ( ! IsMasked ) doAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width , PtrIsCap ) ; else doMaskedAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs


<s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand ::


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) <


<s> MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; if ( TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto II = MBB


<s> SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL ,


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; return <NUM_LIT>


<s> if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ; cfun -> machine -> naked_p


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCSubtargetInfo


<s> assert ( IsAbsolute && <STR_LIT> ) ; ( void ) IsAbsolute ; Data . clear ( ) ; Fixups . clear ( ) ; raw_svector_ostream OS ( Data ) ; assert ( Layout . getAssembler ( ) . getContext ( ) . getAsmInfo ( ) -> getMinInstAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value == <NUM_LIT> ) { WasRelaxed = OldSize != Data . size ( ) ; return true ; } auto AddFixups = [ & Fixups , & AddrDelta ] ( unsigned Offset , std :: pair < unsigned , unsigned > Fixup ) { const MCBinaryExpr & MBE = cast < MCBinaryExpr > ( AddrDelta ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getLHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getRHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; } ; if ( isUIntN ( <NUM_LIT> , Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc1 ) ; <STR_LIT> :: write < uint8_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc2 ) ; <STR_LIT> :: write < uint16_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc4 ) ; <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> ,


<s> OperandMatchResultTy parsePairGR128 ( OperandVector & Operands


<s> return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc


<s> Register <ISA_LIT>FrameLowering :: getSPReg ( ) const { if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) return <STR_LIT> ; else return


<s> } BuildMI ( MBB , II , DL , get ( Opc ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( VL ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; movImm ( MBB , II , DL , N , NumOfVReg , Flag ) ; if ( ! STI . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) ,


<s> RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { if ( MI . getNumOperands ( ) == <NUM_LIT> ) { auto & MOCount = MI . getOperand ( <NUM_LIT> ) ; if ( MOCount . isReg ( ) ) FixupKind = <STR_LIT> ; else FixupKind = <STR_LIT> ; } else { FixupKind = <STR_LIT>