<s> } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } } if ( NotAlways ) continue ; Instruction * TI = ( * I ) -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { if ( ! BI -> isConditional ( ) ) continue ; CountedExitBranch = BI ; } else continue ; CountedExitBlock = * I ; ExitCount = EC ; break ; } if ( ! CountedExitBlock ) return MadeChange ; BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader || mightUseCTR ( TT , Preheader ) ) Preheader = InsertPreheaderForLoop ( L , this ) ; if ( ! Preheader ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ) ; MadeChange = true ; SCEVExpander SCEVE ( * SE , <STR_LIT> ) ; LLVMContext & C = SE -> getContext ( ) ; Type * CountType = TT . isArch64Bit ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; if ( ! ExitCount -> getType ( ) -> isPointerTy ( ) && ExitCount -> getType ( ) != CountType ) ExitCount = SE -> getZeroExtendExpr ( ExitCount , CountType ) ; ExitCount = SE -> getAddExpr ( ExitCount , SE -> getConstant ( CountType , <NUM_LIT> ) ) ; Value * ECValue = SCEVE . expandCodeFor ( ExitCount , CountType , Preheader -> getTerminator ( ) ) ; IRBuilder < > CountBuilder ( Preheader -> getTerminator ( ) ) ; Module * M = Preheader -> getParent ( )


<s> VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , Alignment , AddressSpace ) ; unsigned NumElem = SrcVTy -> getVectorNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedLoad ( SrcVTy ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedStore ( SrcVTy ) ) || ! isPowerOf2_32 ( NumElem ) ) { int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost


<s> i = __builtin_spe_mfspefscr ( ) ; i &= ~ __SPEFSCR_FRMC ; i |= rnd ; __builtin_spe_mtspefscr ( i


<s> RegisterTarget < Triple :: ppc64 , true > Y ( getThe<ISA_LIT>64Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { OperandFlags = isPIC ? <STR_LIT> : <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) { if ( isPIC && ! is64Bit ) { Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG .

getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ;


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; UpdateValueMap ( I , SrcReg ) ; return


<s> static MCFixupKind getImmFixupKind ( uint64_t TSFlags ) { unsigned Size = <STR_LIT> ( TSFlags ) ; bool isPCRel = <STR_LIT> ( TSFlags ) ; switch ( Size ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : return isPCRel ? MCFixupKind ( <STR_LIT> )


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWindowsUnwindTables ( WinEH :: FrameInfo * Frame ) { EHStreamer . EmitUnwindInfo ( * this ,


<s> void setLRIsSpilledForFarJump ( bool s ) { LRSpilledForFarJump =


<s> void <ISA_LIT>TargetStreamer :: emitPersonalityIndex ( unsigned Index ) { llvm_unreachable ( <STR_LIT>


<s> const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue ( unsigned SYSm ) { return <STR_LIT> ( ( <NUM_LIT> << <NUM_LIT> ) |


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI

, const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) {


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter (


<s> __arm_ldc ( const unsigned int __coproc , const unsigned int __CRd , const void * __p ) { return __builtin_arm_ldc ( __coproc ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAddSubImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; unsigned FixupKind = <NUM_LIT> ; switch ( cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr ::


<s> Value * <ISA_LIT>IREmitter :: visitLCMPXCHG8_DAG (


<s> x ^= x >> <NUM_LIT> ; x ^= x >> <NUM_LIT> ; x &= <NUM_LIT> ; return ( <NUM_LIT> >>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectVLD ( SDNode * N , bool isUpdating , unsigned NumVecs , const uint16_t * Opcodes ) { assert ( NumVecs >= <NUM_LIT> && NumVecs <= <NUM_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned OpcodeIndex ; bool is64BitVector = VT . is64BitVector ( ) ; switch ( VT . getScalarType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OpcodeIndex = is64BitVector ? <NUM_LIT> : <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = is64BitVector ? <NUM_LIT> : <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = is64BitVector ? <NUM_LIT> : <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = is64BitVector ? <NUM_LIT> : <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDLoc dl ( N ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue


<s> switch ( getMnemonicFromOpcode ( MI . getOpcode ( ) ) ) { case FlagArithMnemonic :: ADC : case FlagArithMnemonic :: ADCX : case FlagArithMnemonic :: RCL : case FlagArithMnemonic :: RCR : case FlagArithMnemonic :: SBB : case FlagArithMnemonic :: SETB : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; case FlagArithMnemonic :: ADOX : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; } unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void )


<s> } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << '#' << * Op


<s> if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG

. getTargetConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ; return true


<s> assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0 ) ) == std :: end ( MemoryFoldTable0 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable1 ) , std :: end ( MemoryFoldTable1 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable1 ) , std :: end ( MemoryFoldTable1 ) ) == std :: end ( MemoryFoldTable1 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable2 ) , std :: end ( MemoryFoldTable2 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable2 ) , std :: end ( MemoryFoldTable2 ) ) == std :: end ( MemoryFoldTable2 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable3 ) , std :: end ( MemoryFoldTable3 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable3 ) , std :: end ( MemoryFoldTable3 ) ) == std :: end ( MemoryFoldTable3 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable4 ) , std :: end ( MemoryFoldTable4 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable4 ) , std ::

end ( MemoryFoldTable4 ) ) == std :: end ( MemoryFoldTable4 ) && <STR_LIT> ) ;


<s> rtx rr ; if ( TARGET_SHMEDIA ) { int rr_regno = sh_media_register_for_return ( ) ; if ( rr_regno < <NUM_LIT> ) rr_regno = pr_reg ; rr = gen_rtx_REG ( DImode , rr_regno ) ; } else rr = gen_rtx_REG ( SImode , pr_reg ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } if ( TARGET_SH5 ) { int offset ; save_schedule schedule ; save_entry * entry ; entry = sh5_schedule_saves ( & live_regs_mask , & schedule , <NUM_LIT> ) ; offset = entry [ <NUM_LIT> ] .


<s> unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Lo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 ,


<s> static SDValue PerformSHLCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; EVT VT = N0 . getValueType ( ) ; if ( N1C && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> || ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { APInt Mask = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT>


<s> static MCSymbol * GetLazyPtr ( MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName (


<s> } } if ( ! SrcReg ) SrcReg = getRegForValue ( Op0 ) ; if ( ! SrcReg ) return false ; auto * SI = cast < StoreInst > ( I ) ; if ( SI -> isAtomic ( ) ) { AtomicOrdering Ord = SI -> getOrdering ( ) ; if ( isReleaseOrStronger ( Ord ) ) { unsigned AddrReg = getRegForValue ( PtrV ) ; return emitStoreRelease ( VT , SrcReg , AddrReg , createMachineMemOperandFor ( I ) ) ; } } Address Addr ; if ( ! computeAddress ( PtrV , Addr , Op0 -> getType ( ) ) ) return false ; if ( ! emitStore ( VT , SrcReg , Addr , createMachineMemOperandFor ( I ) ) ) return false ; return


<s> simple : tmp = ix86_expand_compare ( code , op0 , op1 ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; return ; case DImode : if ( TARGET_64BIT ) goto simple ; case TImode : { rtx lo [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ; rtx_code_label * label2 ; enum rtx_code code1 , code2 , code3 ; machine_mode submode ; if ( CONSTANT_P ( op0 ) && ! CONSTANT_P ( op1 ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } split_double_mode ( mode , & op0 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; split_double_mode ( mode , & op1 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; submode = mode == DImode ? SImode : DImode ; if ( ( code == EQ || code == NE ) && ( ! optimize_insn_for_size_p ( ) || hi [ <NUM_LIT> ] == const0_rtx || lo [ <NUM_LIT> ] == const0_rtx ) ) { rtx xor0 , xor1 ; xor1 = hi [ <NUM_LIT> ] ; if ( hi [ <NUM_LIT> ] != const0_rtx ) xor1 = expand_binop ( submode , xor_optab , xor1 , hi [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; xor0 = lo [ <NUM_LIT> ] ; if ( lo [ <NUM_LIT> ] != const0_rtx ) xor0 = expand_binop ( submode , xor_optab , xor0 , lo [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp = expand_binop ( submode , ior_optab , xor1 , xor0 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } if ( CONST_INT_P ( hi [ <NUM_LIT> ] ) ) switch ( code ) { case LT : case LTU : case GE : case GEU : if ( lo [ <NUM_LIT> ] == const0_rtx ) { ix86_expand_branch ( code , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; return ; } break ; case LE : case LEU : case GT : case GTU : if ( lo [ <NUM_LIT> ] == constm1_rtx ) { ix86_expand_branch ( code , hi [ <NUM_LIT> ] , hi [ <NUM_LIT>


<s> const HOST_WIDE_INT dep_flags ; const char * const name ; } flags [ ] = { { OPTION_MASK_P9_VECTOR , OTHER_P9_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_P8_VECTOR , OTHER_P8_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_VSX , OTHER_VSX_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_ALTIVEC , OTHER_ALTIVEC_MASKS , <STR_LIT> } , } ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( flags ) ; i ++ ) { HOST_WIDE_INT no_flag = flags [ i ] . no_flag ; if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) { HOST_WIDE_INT dep_flags = flags [ i ] . dep_flags ; HOST_WIDE_INT set_flags = ( rs6000_isa_flags_explicit & rs6000_isa_flags & dep_flags ) ; if ( set_flags ) { for ( j = <NUM_LIT> ; j < ARRAY_SIZE ( rs6000_opt_masks ) ; j ++ ) if ( ( set_flags & rs6000_opt_masks [ j ] . mask ) != <NUM_LIT> ) { set_flags &= ~ rs6000_opt_masks [ j ] . mask ; error ( <STR_LIT> , flags [ i ] . name , rs6000_opt_masks [ j ] . name ) ; } gcc_assert ( ! set_flags ) ; } rs6000_isa_flags &=


<s> if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( (

( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getDarwinTLSCallPreservedMask ( ) const { return CSR_64_TLS_Darwin_RegMask


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; if ( SubIdx == <STR_LIT> &&


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op ,


<s> if ( User * P2I = testI2P ( I2P ) ) { auto Src = getValueSource ( P2I -> getOperand ( <NUM_LIT> ) ) ; AllocOperands AO = getRangeForAllocation ( Src ) ; if ( AO != AllocOperands ( ) ) Casts . push_back ( pair <

AllocOperands , Instruction * > ( AO , & I2P ) ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) .


<s> static DecodeStatus DecodeShiftRightImm8 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm ,


<s> case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget -> hasMSA ( ) && type -> isVectorTy ( ) && cast < VectorType > ( type ) -> getBitWidth ( ) == <NUM_LIT> ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case


<s> if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , <NUM_LIT> ) ; for ( i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> ,


<s> bool isNotSingleFloat ( ) const { return ! IsSingleFloat


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv8qi ( ( int8x8_t )


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false


<s> unsigned low_part_offset = subreg_lowpart_offset ( SImode ,


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ;


<s> return __builtin_mve_vcmpneq_m_n_fv4sf ( __a ,


<s> unsigned NumSrcBits = In . getScalarValueSizeInBits ( ) ; assert ( NumSrcBits > NumDstBits && <STR_LIT> ) ; auto MatchMinMax = [ ] ( SDValue V , unsigned Opcode , const APInt & Limit ) -> SDValue { APInt C ; if ( V . getOpcode ( ) == Opcode && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) . getNode ( ) , C ) && C == Limit ) return V . getOperand ( <NUM_LIT> ) ; return SDValue ( ) ; } ; APInt SignedMax , SignedMin ; if ( MatchPackUS ) { SignedMax = APInt :: getAllOnesValue ( NumDstBits ) . zext ( NumSrcBits ) ; SignedMin = APInt ( NumSrcBits , <NUM_LIT> ) ; } else { SignedMax = APInt :: getSignedMaxValue ( NumDstBits ) . sext ( NumSrcBits ) ; SignedMin = APInt :: getSignedMinValue ( NumDstBits ) . sext ( NumSrcBits


<s> switch ( SrcSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_SITOFP : return <STR_LIT> ; case TargetOpcode :: G_UITOFP : return <STR_LIT> ; case TargetOpcode :: G_FPTOSI : return <STR_LIT> ; case TargetOpcode :: G_FPTOUI : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_SITOFP : return <STR_LIT> ; case TargetOpcode :: G_UITOFP : return <STR_LIT> ; case TargetOpcode :: G_FPTOSI : return <STR_LIT> ; case TargetOpcode :: G_FPTOUI : return <STR_LIT> ; default : return GenericOpc ; } default : return GenericOpc ; } case <NUM_LIT> : switch ( SrcSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_SITOFP : return <STR_LIT> ; case TargetOpcode :: G_UITOFP : return <STR_LIT> ; case TargetOpcode :: G_FPTOSI : return <STR_LIT> ; case TargetOpcode :: G_FPTOUI : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_SITOFP : return <STR_LIT> ; case TargetOpcode :: G_UITOFP : return <STR_LIT> ; case TargetOpcode :: G_FPTOSI : return <STR_LIT> ; case TargetOpcode :: G_FPTOUI : return <STR_LIT> ; default : return GenericOpc ; } default : return GenericOpc ; } default : return GenericOpc ; } ; return GenericOpc


<s> case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; } } MachineRelocation R ; if ( MO . isGlobal ( ) ) { R = MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > ( MO . getGlobal ( ) ) , <NUM_LIT> , isa < Function > ( MO . getGlobal ( ) ) ) ; } else if ( MO . isSymbol ( ) ) { R = MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , <NUM_LIT> ) ; } else if ( MO . isCPI ( ) ) { R = MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } else { assert ( MO . isJTI ( ) ) ; R = MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && Reloc != <STR_LIT> ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; R . setConstantVal ( - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ) ; } MCE . addRelocation ( R ) ; } else if ( MO . isMBB ( ) ) { unsigned Reloc = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Reloc = <STR_LIT> ; else Reloc = <STR_LIT> ; MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getMBB ( ) ) ) ; } else { errs ( ) << <STR_LIT> << MO << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } return rv


) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> return ( __m128d ) __builtin_ia32_cmpunordpd ( ( __v2df ) __A ,


<s> rtx op1 = operands [ <NUM_LIT> ] ; rtx insn ; bool need_ccmpeq = false ; if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { op0 = force_reg ( mode , op0 ) ; op1 = force_reg ( mode , op1 ) ; } else { if ( code != EQ || mode == DImode ) { op0 = force_reg ( mode , op0 ) ; if ( op1 != const0_rtx || code == GTU || code == GEU ) op1 = force_reg ( mode , op1 ) ; } } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpId = <NUM_LIT> ; break ; case <STR_LIT> : OpId = <NUM_LIT> ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + <NUM_LIT> ; return true


<s> else { Expr = MO . getExpr ( ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } } Fixups . push_back ( MCFixup :: create ( Offset , Expr , ( MCFixupKind ) Kind ) ) ; if ( AllowTLS && OpNum + <NUM_LIT> < MI . getNumOperands ( ) ) { const MCOperand & MOTLS = MI . getOperand


<s> if ( Asm . isThumbFunc ( Sym ) ) Value |= <NUM_LIT> ; } } if ( IsResolved && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { assert ( Sym && <STR_LIT> ) ; if ( Sym -> isExternal ( ) || Value >= <NUM_LIT> ) IsResolved = false ; } if ( A && ( ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) ) IsResolved = false ; ( void ) adjustFixupValue ( Fixup , Value , false , & Asm . getContext ( )


<s> static const SDValue * getNormalLoadInput ( const SDValue & Op ) { const SDValue * InputLoad = & Op ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) != <STR_LIT> ) return nullptr ; LoadSDNode * LD = cast < LoadSDNode


<s> int TailCallReturnAddrDelta = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) ; assert ( ! ( TailCallReturnAddrDelta < <NUM_LIT> ) && <STR_LIT> ) ; } FrameReg = TRI -> getStackRegister ( ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea


<s> const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > (


<s> if ( MII == MBB . end ( ) || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ShadowBytes += TII -> getInstSizeInBytes ( * MII ) ; if ( MII -> isCall ( ) ) break ; ++ MII ; } while ( ShadowBytes < NumNOPBytes ) ShadowBytes += EmitNop ( OutContext , * OutStreamer

, NumNOPBytes - ShadowBytes , getSubtargetInfo ( ) ) ;


<s> int <ISA_LIT>ConstantPoolJT :: getExistingMachineCPValue ( MachineConstantPool * CP , Align Alignment


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false


<s> SMLoc getEndLoc ( ) const { return EndLoc


<s> inline static bool isScale ( const MachineOperand & MO ) { return MO . isImm ( ) && ( MO . getImm ( ) == <NUM_LIT> || MO . getImm ( ) == <NUM_LIT> || MO . getImm ( ) == <NUM_LIT> ||


<s> const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; const Value * Val = S -> getValueOperand ( ) ; const Value * Ptr = S ->


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple TheTriple ( TT ) ; RM = TheTriple . isOSDarwin ( ) ? Reloc ::


<s> SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB -> addSuccessor ( SinkMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; MachineInstrBuilder MIB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator FalseInsertionPoint = FalseMBB -> begin ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , unsigned > FalseBBRegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) { auto & MI = * MIIt ++ ; if ( ! MI . mayLoad ( ) ) { Register FalseReg = MI . getOperand ( <STR_LIT> ( MI ) == CC ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; while ( true ) { auto FRIt = FalseBBRegRewriteTable . find ( FalseReg ) ; if ( FRIt == FalseBBRegRewriteTable . end ( ) ) break ; FalseReg = FRIt -> second ; } FalseBBRegRewriteTable [ MI . getOperand ( <NUM_LIT> ) . getReg ( ) ] = FalseReg ; continue ; } assert ( <STR_LIT> ( MI ) == OppCC && <STR_LIT> <STR_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register TmpReg = MRI -> createVirtualRegister ( RC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( * MBB -> getParent ( ) , MI , TmpReg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; auto * NewCMOV = NewMIs . pop_back_val ( ) ; assert ( <STR_LIT> ( * NewCMOV ) == OppCC && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewCMOV -> dump ( ) ) ; MBB -> insert ( MachineBasicBlock :: iterator ( MI ) , NewCMOV ) ; if ( & * MIItBegin == & MI ) MIItBegin = MachineBasicBlock :: iterator ( NewCMOV ) ; for ( auto * NewMI : NewMIs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ) ; FalseMBB -> insert ( FalseInsertionPoint , NewMI ) ; for ( auto & MOp : NewMI -> uses ( ) ) { if ( ! MOp . isReg ( ) ) continue ; auto It = FalseBBRegRewriteTable . find ( MOp . getReg ( ) ) ; if ( It == FalseBBRegRewriteTable . end (


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode


<s> if ( pic_offset_table_rtx && regno == REAL_PIC_OFFSET_TABLE_REGNUM && ( regs_ever_live [ REAL_PIC_OFFSET_TABLE_REGNUM ] || current_function_profile || current_function_calls_eh_return || current_function_uses_const_pool ) ) { if ( ix86_select_alt_pic_regnum ( ) != INVALID_REGNUM ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( current_function_calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = <NUM_LIT> ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM )


<s> void \ fini_section ( void ) \ { \ if ( in_section != in_fini ) \ { \ in_section = in_fini ; \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP )


<s> const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , <NUM_LIT> , false , false , false , MachinePointerInfo ( DstSV ) ,


<s> MachineOperand & Reg0 = MI -> getOperand ( <NUM_LIT> ) , & Reg2 = MI -> getOperand ( <NUM_LIT> ) , & Reg4 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Imm1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & JTI3 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! Reg0 . isReg ( ) ) return false ; if ( ! Reg2 . isReg ( ) ) return false ; if ( ! Reg4 . isReg ( ) ) return false ; if ( ! Imm1 . isImm ( ) ) return false ; if ( ! JTI3 . isJTI ( ) ) return false ; MI -> dump ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = STI . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned VReg1 = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned LoadOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LoadOpc ) , VReg ) ; MIB . addReg ( Reg0 . getReg ( ) ) . addImm ( Imm1 . getImm ( ) ) . addReg ( Reg2 . getReg ( ) ) . addJumpTableIndex ( JTI3 . getIndex ( ) ) . addReg ( Reg4 . getReg ( ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MIB = BuildMI ( MBB , MI , DL , TII . get ( CmpOpc ) , VReg1 ) . addReg ( VReg ) ; MIB . addReg ( Reg0 . getReg ( ) ) . addImm ( Imm1 . getImm ( ) ) . addReg ( Reg2 . getReg ( ) ) . addJumpTableIndex ( JTI3 . getIndex ( ) + <NUM_LIT> ) . addReg ( Reg4 . getReg ( ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; unsigned JmpOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( JmpOpc ) ) . addReg ( VReg1 , RegState :: Kill ) ; MI -> eraseFromParent (


<s> <STR_LIT> Flags = cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> + i ) ) -> getArgFlags ( ) ; bool AlwaysUseMutable = ( CC == CallingConv :: Fast ) && PerformTailCallOpt ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; int FI = MFI -> CreateFixedObject ( VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; if ( Flags . isByVal ( ) ) return


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA


<s> SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueOp = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; unsigned CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VTs , & Ops [ <NUM_LIT> ] , Ops .


<s> return ScoreboardHazardRecognizer :: getHazardType ( SU , Stalls


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return


<s> static int getStackOffset ( const MachineFunction & MF , int ObjectOffset ) { const auto & MFI = MF . getFrameInfo


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { SDLoc dl ( Node ) ; if ( Node -> isMachineOpcode ( ) ) { Node -> setNodeId ( - <NUM_LIT> ) ; return ; } switch ( Node -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return ; } } SelectCode (


<s> static DecodeStatus DecodePowerTwoOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val < MinLog || Val > MaxLog ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> << Val ) ) ; return


<s> } else if ( <STR_LIT> . contains ( SrcReg ) ) { Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) )


<s> bool isMSRSystemRegister ( ) const { if ( ! isSysReg ( ) ) return false ; return SysReg . MSRReg


<s> bool <ISA_LIT>DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != <STR_LIT> ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( int j = <NUM_LIT> ; j < Shift ; ++ j ) if ( ! Zeroable [ j + ( Left ? <NUM_LIT> : ( Size - Shift ) ) ] ) return false ; return true ; } ; auto MatchShift = [ & ] ( int Shift , bool Left ) { unsigned Pos = Left ? Shift : <NUM_LIT> ; unsigned Low = Left ? <NUM_LIT>


<s> MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result )


<s> if ( ! RM . hasValue ( ) ) return Reloc


<s> emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn )


<s> return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> ) , Subtarget -> has64BitPointers ( ) ? <NUM_LIT>

: <NUM_LIT> , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; Opc = LHS . getValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { if ( ! hasHardQuad && LHS . getValueType ( ) == <STR_LIT> ) { if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ; CompareFlag = TLI . LowerF128Compare ( LHS , RHS , <ISA_LIT>CC , dl , DAG ) ; Opc = <STR_LIT> ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl ,


<s> AddOptionalDefs ( MIB ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; return NewDestReg ; } } } if ( IsIndirect ) { MachineInstrBuilder MIB ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; else MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; DestReg = NewDestReg ; AddOptionalDefs ( MIB


<s> MinFPR = Reg ; } } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { } else if ( RC == <STR_LIT> ) { HasVRSAVESaveArea = true ; } else if ( RC == <STR_LIT> ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - getRegisterNumbering ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S