<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { bool LocalChange = false ; for ( MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return __builtin_aarch64_qtbx4v16qi ( r , __o , (


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { OutStreamer . SwitchSection ( OutContext . getObjectFileInfo (


<s> static void tLDRpci_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; const MachineConstantPool * MCP = MI . getParent ( ) -> getParent ( ) -> getConstantPool ( ) ; MachineConstantPoolEntry mcpe = MCP -> getConstants ( ) [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ; const Constant * cv = mcpe . Val . ConstVal ; SExpr *


<s> return ( __m128i ) __builtin_ia32_vpmacsww ( ( __v8hi ) __A , ( __v8hi )


, ( __D << <NUM_LIT> ) | __C , _MM_FROUND_CUR_DIRECTION ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ( RegNo & <NUM_LIT> ) ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = IntPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( i == NULL || i == PREV_INSN ( BB_HEAD ( bb ) ) ) continue ; if ( any_condjump_p ( i ) && onlyjump_p ( i ) ) { try_optimize_cbranch (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI


<s> const TargetMachine & TM = MF . getTarget ( ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ( Subtarget . isABI_FPXX ( ) && ! Subtarget . hasMTHC1 ( ) ) || ( FP64 && ! Subtarget . useOddSPReg ( ) ) ) { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( TM . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & TRI = * static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getRegisterInfo ( ) ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; const TargetRegisterClass * RC2 = FP64 ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( LoReg , HiReg ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill (


<s> if ( EltSize == <NUM_LIT> ) { unsigned MfvsrdIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrdIndex ) return <NUM_LIT> ; } else if ( EltSize == <NUM_LIT> ) { unsigned MfvsrwzIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrwzIndex ) return <NUM_LIT> ; } return vectorCostAdjustment ( <NUM_LIT> , Opcode , Val , nullptr ) ; } else if ( ST -> hasDirectMove ( ) ) return <NUM_LIT> ; } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> ) LHSPenalty += <NUM_LIT> ; if ( ISD == <STR_LIT> || ISD == <STR_LIT> ) return LHSPenalty + Cost ; return


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI . CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI . CreateFixedObject ( RegSizeInBytes , VaArgOffset , true


<s> if ( SrcVT == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) { return Op ; } return SDValue ( ) ; } assert ( SrcVT . getSimpleVT ( ) <= <STR_LIT> && SrcVT . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size


<s> emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_move_insn ( mem


<s> if ( MI -> getOperand ( OpNum ) . getReg ( ) ) { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << 's'


<s> case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr_REV ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rm ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , mr ) \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : LLVM_EXPAND_ADC_SBB_INSTR ( ADC ) return FlagArithMnemonic :: ADC ; LLVM_EXPAND_ADC_SBB_INSTR ( SBB ) return FlagArithMnemonic :: SBB ; LLVM_EXPAND_INSTR_SIZES ( RCL , rCL ) LLVM_EXPAND_INSTR_SIZES ( RCL , r1 ) LLVM_EXPAND_INSTR_SIZES ( RCL , ri ) return FlagArithMnemonic


<s> SDValue Tmp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Tmp1 . getValueType ( ) ; SDValue AbsVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp0 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> ,


<s> static void demoteInst ( MCInst & Inst , const MCInstrInfo & InstInfo ) { unsigned NewOpc = demoteOpcode ( Inst . getOpcode ( ) ) ; Inst . setOpcode ( NewOpc ) ; const MCOperandInfo * OpInfo = InstInfo . get ( Inst . getOpcode


<s> unsigned getSsatBitPosValue ( const MachineInstr & MI ,


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , ELFRefKind , DarwinRefKind , Addend ) ) { return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; for ( unsigned i = <NUM_LIT> ; i != AllowedModifiers . size ( )


<s> int64_t StackOffsetVal ; if ( Parser . parseExpression ( StackOffset ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! StackOffset -> evaluateAsAbsolute ( StackOffsetVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( StackOffsetVal < <NUM_LIT> ) { Warning ( Loc , <STR_LIT> ) ; IsCpRestoreSet = false ; } else { IsCpRestoreSet =


<s> break ; case 'w' : break ; default : return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } else { if ( Suffix ) return Error ( Loc , <STR_LIT> ) ; } auto parseOne = [ & ] ( ) -> bool { const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * Value = dyn_cast_or_null < MCConstantExpr > ( Expr ) ; if ( ! Value ) { return Error ( Loc , <STR_LIT> ) ; } switch ( Width ) { case <NUM_LIT>


<s> sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( ( code != EQ && code != NE && ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && sh_compare_op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ; if ( ( TARGET_SH4 || TARGET_SH2A ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ( mode == SFmode ? emit_sf_insn : emit_df_insn ) ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) , gen_rtx_USE ( VOIDmode , get_fpscr_rtx ( ) ) ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee (

code , SImode , sh_compare_op0 , sh_compare_op1 ) ) ) ;


return default_estimated_poly_value ( val ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _fxrstor ( void * __P ) { return __builtin_ia32_fxrstor (


<s> if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( )


<s> static DecodeStatus DecodeCOP0RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> void addSImm10s8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) / <NUM_LIT>


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & , const MCTargetOptions & Options ) { IsLittleEndian =


<s> SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { Offset *= <NUM_LIT> ; } if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize *


<s> } ; if ( IsUnitSplat ( OpMultiplier ) ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } else if ( IsUnitDup ( OpMultiplier ) ) { auto * DupInst = cast < IntrinsicInst > ( OpMultiplier ) ; auto * DupPg = DupInst -> getOperand ( <NUM_LIT> ) ; if ( OpPredicate == DupPg ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } } return instCombineSVEVectorBinOp ( IC ,


<s> SmallPtrSetImpl < Instruction * > & getAdds ( ) { return


<s> unsigned Opcode = U . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; } break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; } break ; } if ( ! NewOpc ) continue ; unsigned UserOffset = getUserOffset ( U ) ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; if ( ! U . KnownAlignment ) MaxOffs -= <NUM_LIT> ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , MaxOffs , false , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * U . MI ) ; U . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = U . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ]


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectSIToFP ( const Instruction * I ) { return <ISA_LIT>SelectIntToFP ( I ,


<s> unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OpReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; warnIfNoMacro ( IDLoc ) ; if ( SrcReg != <STR_LIT> && OpReg != <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , OpReg , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc


<s> printFCCOperand ( const MCInst * MI , int opNum ,


<s> unsigned CC ; if ( ! ITBlock . empty ( ) ) { CC = ITBlock . back ( ) ; ITBlock . pop_back ( ) ; } else CC = <STR_LIT> ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { I -> setImm ( CC ) ; ++


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val <


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; auto PredTy = VT . getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) , true ) ; SDValue Mask = getPTrue ( DAG , DL ,


<s> if ( <ISA_LIT>EarlyIfConv && get<ISA_LIT>Subtarget ( )


<s> static inline uint64_t decodeAdvSIMDModImmType4 ( uint8_t Imm ) { uint64_t EncVal = Imm ; return ( EncVal << <NUM_LIT> ) | ( EncVal


<s> } nregs = ( ( GET_MODE_BITSIZE ( mode ) + BITS_PER_WORD - <NUM_LIT> ) / BITS_PER_WORD ) ; if ( nregs > MMIX_MAX_REGS_FOR_VALUE ) internal_error ( <STR_LIT> , nregs , MMIX_MAX_REGS_FOR_VALUE ) ; for ( i = <NUM_LIT> ; i < nregs - <NUM_LIT> ; i ++ ) vec [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , first_val_regnum + i ) , GEN_INT ( ( i + <NUM_LIT> ) * BITS_PER_UNIT ) ) ; vec [ nregs - <NUM_LIT> ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , first_val_regnum + nregs - <NUM_LIT> ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( nregs , vec


<s> FunctionPass * llvm :: create<ISA_LIT>VSXSwapRemovalPass


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; unsigned Opc = <NUM_LIT> ; bool Offset = true ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq (


<s> unsigned NumElts = SizeInBits / EltSizeInBits ; unsigned SrcEltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits ; APInt UndefBits ( SizeInBits , <NUM_LIT> ) ; APInt MaskBits ( SizeInBits , <NUM_LIT> ) ; auto SplitBitData = [ & ] ( ) { if ( UndefBits . getBoolValue ( ) && ! AllowUndefs ) return false ; UndefElts = SmallBitVector ( NumElts , false ) ; EltBits . resize ( NumElts , APInt ( EltSizeInBits , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { APInt UndefEltBits = UndefBits . lshr ( i * EltSizeInBits ) ; UndefEltBits = UndefEltBits . zextOrTrunc ( EltSizeInBits ) ; if ( UndefEltBits . isAllOnesValue ( ) ) { UndefElts [ i ] = true ; continue ; } APInt Bits = MaskBits . lshr ( i * EltSizeInBits ) ; Bits = Bits . zextOrTrunc ( EltSizeInBits ) ; EltBits [ i ] = Bits . getZExtValue ( ) ; } return true ; } ; auto ExtractConstantBits = [ SizeInBits ] ( const Constant * Cst , APInt & Mask , APInt & Undefs ) { if ( ! Cst ) return false ; unsigned CstSizeInBits = Cst -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( isa < UndefValue > ( Cst ) ) { Mask = APInt :: getNullValue ( SizeInBits ) ; Undefs = APInt :: getLowBitsSet ( SizeInBits , CstSizeInBits ) ; return true ; } if ( auto * CInt = dyn_cast < ConstantInt > ( Cst ) ) { Mask = CInt -> getValue ( ) . zextOrTrunc ( SizeInBits ) ; Undefs = APInt :: getNullValue ( SizeInBits ) ; return true ; } if ( auto * CFP = dyn_cast < ConstantFP > ( Cst ) ) { Mask = CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . zextOrTrunc ( SizeInBits ) ; Undefs = APInt :: getNullValue ( SizeInBits ) ; return true ; } return false ; } ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { const SDValue & Src = Op . getOperand ( i ) ; if ( Src . isUndef ( ) ) { APInt Undefs = APInt :: getLowBitsSet ( SizeInBits , SrcEltSizeInBits ) ; UndefBits |= Undefs . shl ( i * SrcEltSizeInBits ) ; continue ; } auto * Cst = cast < ConstantSDNode > ( Src ) ; APInt Bits = Cst -> getAPIntValue (


<s> assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO


<s> bool has<ISA_LIT>64r2 ( ) const { return <ISA_LIT>ArchVersion >=


<s> if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term

, <NUM_LIT> ) ) ) term = XEXP ( term , <NUM_LIT> ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = <STR_LIT> <= Reg && Reg <= <STR_LIT> ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled =


<s> else switch_to_section ( data_section ) ; if ( TARGET_LITTLE_ENDIAN ) fputs


<s> int iq2000_reg_mode_ok_for_base_p ( rtx reg , machine_mode mode ATTRIBUTE_UNUSED ,


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx


<s> return ( TlsSetValue ( key , ( void * ) ptr ) != <NUM_LIT> ) ?


<s> for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; return EltsFromConsecutiveLoads ( VT , Elts ,


<s> static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [


<s> switch ( Opcode ) { case <STR_LIT> : if ( VT == <STR_LIT> ) { ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnesValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } } break ; case <STR_LIT>


<s> static bool isSequentialOrUndefInRange ( ArrayRef < int > Mask , int Pos , int Size , int Low ) { for ( int i = Pos , e = Pos + Size ; i != e ; ++ i , ++ Low ) if ( ! isUndefOrEqual ( Mask [ i ] , Low ) ) return false ; return true


<s> if ( extra_pop > <NUM_LIT> ) { unsigned long extra_mask = ( <NUM_LIT> << extra_pop ) - <NUM_LIT> ; live_regs_mask |= extra_mask << ARM_NUM_INTS ( size ) ; } if ( high_regs_pushed ) { unsigned long mask = live_regs_mask & <NUM_LIT> ; int next_hi_reg ; if ( size <= <NUM_LIT> ) mask |= <NUM_LIT> << <NUM_LIT> ; if ( size <= <NUM_LIT> ) mask |= <NUM_LIT> << <NUM_LIT> ; if ( mask == <NUM_LIT> ) internal_error ( <STR_LIT> ) ; for ( next_hi_reg = <NUM_LIT> ; next_hi_reg < <NUM_LIT> ; next_hi_reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << next_hi_reg ) ) break ; while ( high_regs_pushed ) { for ( regno = <NUM_LIT> ; regno <= LAST_LO_REGNUM ; regno ++ ) { if ( mask & ( <NUM_LIT> << regno ) ) high_regs_pushed -- ; if ( high_regs_pushed == <NUM_LIT> ) break ; } mask &= ( <NUM_LIT> << regno ) - <NUM_LIT> ; thumb_pop ( asm_out_file , mask ) ; for ( regno = <NUM_LIT> ; regno <= LAST_LO_REGNUM ; regno ++ ) { if ( mask & ( <NUM_LIT> << regno ) ) { asm_fprintf ( asm_out_file , <STR_LIT> , next_hi_reg , regno ) ; for ( next_hi_reg ++ ; next_hi_reg < <NUM_LIT> ; next_hi_reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << next_hi_reg ) ) break ; } } } live_regs_mask &= ~ <NUM_LIT> ; } had_to_push_lr = ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ; live_regs_mask &= <NUM_LIT> ; if ( crtl -> args . pretend_args_size == <NUM_LIT> || TARGET_BACKTRACE ) { if ( had_to_push_lr ) live_regs_mask |= <NUM_LIT> << PC_REGNUM ; if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( ! had_to_push_lr ) thumb_exit ( asm_out_file , LR_REGNUM ) ; } else { if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( had_to_push_lr ) { if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } thumb_pop ( asm_out_file , <NUM_LIT> << LAST_ARG_REGNUM ) ; if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; asm_fprintf ( asm_out_file , <STR_LIT> , LAST_ARG_REGNUM , IP_REGNUM ) ; regno = LR_REGNUM ; } else regno = LAST_ARG_REGNUM ; } else regno =


<s> int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { const uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( T , TT .


<s> uint64_t got_base = m_GOT . addr ( ) ; assert ( got_base && <STR_LIT> ) ; <ISA_LIT>PLT :: iterator it = m_pSectionData -> begin ( ) ; <ISA_LIT>PLT :: iterator ie = m_pSectionData -> end ( ) ; assert ( it != ie && <STR_LIT> ) ; uint32_t GOTEntrySize = <STR_LIT> ; uint32_t GOTEntryAddress = got_base + GOTEntrySize * <NUM_LIT> ; uint32_t PLTEntryAddress = plt_base + <ISA_LIT>PLT0 :: EntrySize ; ++ it ; uint32_t PLT1EntrySize = <ISA_LIT>PLT1 :: EntrySize ; <ISA_LIT>PLT1 * plt1 = NULL ; uint32_t * Out = NULL ; while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; Out = static_cast < uint32_t * > ( malloc ( <ISA_LIT>PLT1 :: EntrySize ) ) ; memcpy ( Out , aarch64_plt1 , <ISA_LIT>PLT1 :: EntrySize ) ; <ISA_LIT>Relocator :: DWord imm = helper_get_page_address ( GOTEntryAddress ) - helper_get_page_address ( PLTEntryAddress ) ; Out [ <NUM_LIT> ] = helper_reencode_adr_imm ( Out [ <NUM_LIT> ] , imm >>


<s> bool <ISA_LIT>_MC :: is64BitMemOperand ( const MCInst & MI , unsigned


<s> if ( Val . countTrailingOnes ( ) >= Width ) return true ; APInt Mask = Val | CurDAG -> computeKnownBits ( N -> getOperand (


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , instr , Insn , Address , this , STI ) ; if ( Result !=


<s> if ( Ty -> isVectorTy ( ) && IsComplex ) return NumVectorInstToHideOverhead ; return BaseT :: getAddressComputationCost (


<s> MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GO , GOKind , TM ) ) ; Align GOAlign = getGVAlignment ( GO , GO -> getParent ( ) -> getDataLayout ( ) ) ; if ( GOAlign > Csect -> getAlignment ( ) ) Csect -> setAlignment ( GOAlign ) ; } ; for ( const auto & G : M . globals ( ) ) setCsectAlignment ( & G ) ; for ( const auto & F : M ) setCsectAlignment ( &


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; AddDefaultPred (


<s> static void finish_bundle_state_table


<s> static bool aarch64_optab_supported_p ( int op , machine_mode mode1 , machine_mode


<s> if ( StackSize || MFFrame -> hasVarSizedObjects ( ) || MFFrame -> hasCalls ( ) ) StackSize += <STR_LIT> ; return StackSize


<s> case MCSymbolRefExpr :: VK_GOT : assert ( Type == RT32_32 ) ; return IsPCRel ? ELF :: R_386_GOTPC : ELF :: R_386_GOT32 ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr :: VK_PLT


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm


<s> bool inPicMode ( ) { return IsPicEnabled


<s> if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT>


<s> ATReg = Opts -> getATRegIndex ( ) ; Reorder = Opts -> isReorder


<s> switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 &&


) _mm512_setzero_qi ( ) , ( __mmask64 ) - <NUM_LIT> ) ;


<s> assert ( ( Opcode == Instruction :: SExt || Opcode == Instruction :: ZExt ) && <STR_LIT> ) ; auto * Src = VecTy -> getElementType ( ) ; assert ( isa < IntegerType > ( Dst ) && isa < IntegerType > ( Src ) && <STR_LIT> ) ; auto Cost = getVectorInstrCost ( Instruction :: ExtractElement , VecTy , Index ) ; auto VecLT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; auto DstVT = TLI -> getValueType ( DL , Dst ) ; auto SrcVT = TLI -> getValueType ( DL , Src ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; if ( ! VecLT . second . isVector ( ) || ! TLI -> isTypeLegal ( DstVT ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; if ( DstVT . getFixedSizeInBits ( ) < SrcVT . getFixedSizeInBits ( ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SExt : return Cost


<s> MachineInstr * Inst = MRI -> getVRegDef ( SrcReg ) ; if ( BB1 && Inst -> getOpcode ( ) == <STR_LIT> && Inst -> getParent ( ) == BB2 ) { NextReg = getIncomingRegForBlock ( Inst , BB1 ) ; BB1 = nullptr


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget <


<s> return ( __m64 ) __builtin_arm_wmulwsmr ( ( __v2si ) a ,


<s> __a = ( __vector signed short ) vec_splats ( __m1 ) ; __b = ( __vector signed short ) vec_splats ( __m2 ) ; __c = vec_vmsumshm ( __a , __b , __zero ) ; return ( __m64 ) ( ( __vector long long )


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; StatepointOpers SOpers ( & MI ) ; if ( unsigned PatchBytes = SOpers . getNumPatchBytes ( ) ) { emit<ISA_LIT>Nops ( * OutStreamer , PatchBytes , Subtarget ) ; } else { const MachineOperand & CallTarget = SOpers . getCallTarget ( ) ; MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable (


<s> MCSymbolData & SD = Asm . getSymbolData ( R . Sym -> AliasedSymbol ( ) ) ; return ( ( R . Reloc . Type == ELF :: R_MIPS_GOT16 ) && ! SD . isExternal ( ) ) || ( R .


<s> static bool r10k_simplified_address_p ( rtx x ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x , <NUM_LIT> ) ; return x == virtual_incoming_args_rtx || CONSTANT_P


<s> return VT1 == <STR_LIT> && VT2 == <STR_LIT> && Subtarget ->


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetGlobalValueSymbol ( const GlobalValue * GV ) const { SmallString < <NUM_LIT> > NameStr ; Mang -> getNameWithPrefix ( NameStr , GV , false ) ; MCSymbol * Symb = OutContext . GetOrCreateSymbol (


<s> ArgIsFixed . clear ( ) ; for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) ArgIsFixed .


<s> if ( ! LogicalShift && <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( - <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == N0 . getOpcode ( ) ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NewShiftVal = ShiftVal + ShiftVal2 ; if ( NewShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = EltBits . size ( ) ; i != e ; ++ i ) { APInt & Elt = EltBits [ i ] ; if ( UndefElts [ i ] ) Elt = <NUM_LIT> ; else if ( <STR_LIT> == Opcode ) Elt <<= ShiftVal ; else if ( <STR_LIT> == Opcode ) Elt . ashrInPlace ( ShiftVal ) ; else Elt . lshrInPlace ( ShiftVal ) ; } UndefElts = <NUM_LIT> ; return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) , DAG , SDLoc ( N ) ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue

( NumBitsPerElt ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> unsigned TopReg = Stack [ StackTop - <NUM_LIT> ] ; Stack [ OldSlot ] = TopReg ; RegMap [ TopReg ] = OldSlot ; RegMap [ FPRegNo ] = ~ <NUM_LIT> ; Stack [ -- StackTop ] = ~


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) && Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( )


<s> static DecodeStatus DecodeDoubleRegLoad ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; MachineInstrBuilder ( * MBB . getParent ( ) , std :: prev ( MBBI ) ) . addReg ( SrcReg , RegState :: Implicit ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; MachineInstrBuilder ( * MBB . getParent ( ) , std :: prev ( MBBI ) ) . addReg ( SrcReg , ( getKillRegState ( KillSrc ) | RegState :: Implicit ) ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc , false ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { unsigned SrcRegHi = RI . getMatchingSuperReg ( RI . getSubReg ( SrcReg , <STR_LIT> ) , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegLo = RI . getMatchingSuperReg ( RI . getSubReg ( SrcReg , <STR_LIT> ) , <STR_LIT> , &


<s> if ( ! isTargetShuffle ( N . getOpcode ( ) ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( ! getTargetShuffleMask ( N . getNode ( ) , VT , true , Ops , Mask , IsUnary ) ) return false ; int Size = Mask . size ( ) ; SDValue V1 = Ops [ <NUM_LIT> ] ; SDValue V2 = IsUnary ? V1 : Ops [ <NUM_LIT> ] ; KnownUndef = KnownZero = APInt :: getZero ( Size ) ; V1 = peekThroughBitcasts ( V1 ) ; V2 = peekThroughBitcasts ( V2 ) ; assert ( ( VT . getSizeInBits ( ) % Size ) == <NUM_LIT> && <STR_LIT> ) ; unsigned EltSizeInBits = VT . getSizeInBits ( ) / Size ; APInt UndefSrcElts [ <NUM_LIT> ] ; SmallVector < APInt , <NUM_LIT> > SrcEltBits [ <NUM_LIT> ] ; bool IsSrcConstant [ <NUM_LIT> ] = { getTargetConstantBitsFromNode ( V1 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) , getTargetConstantBitsFromNode ( V2 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { assert ( isUndefOrZero ( M ) && <STR_LIT> ) ; if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ; if ( SM_SentinelZero == M ) KnownZero . setBit ( i ) ; continue ; } unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( )


<s> MCSymbol * <ISA_LIT>ELFStreamer :: emitCFILabel ( ) { MCSymbol * Label = getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MCELFStreamer :: emitLabel ( Label ) ; return


<s> if ( GET_CODE ( op ) != SYMBOL_REF )


<s> LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs


<s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL


<s> unsigned A15SDOptimizer :: getDPRLaneFromSPR ( unsigned SReg ) { unsigned DReg = TRI -> getMatchingSuperReg ( SReg , <STR_LIT> , & <STR_LIT> ) ; if ( DReg != <STR_LIT> ) return <STR_LIT> ; return


<s> uint64_t currEltVal = ( imm >> ( i * size ) ) & mask ; if ( currEltVal != lowestEltVal ) { allMatched = false ; break ; } } if ( allMatched ) { eltVal = lowestEltVal ; break ; } size *= <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> ; i < size ; ++ i ) { eltVal = ror ( eltVal , size ) ; uint32_t clz = countLeadingZeros ( eltVal ) - ( <NUM_LIT> - size ) ; uint32_t cto = CountTrailingOnes_64 ( eltVal ) ; if ( clz + cto == size ) { unsigned immr = size - ( i + <NUM_LIT> ) ; uint64_t nimms = ~ ( size - <NUM_LIT> ) << <NUM_LIT> ; nimms |= ( cto - <NUM_LIT> ) ; unsigned N = ( ( nimms >> <NUM_LIT> ) & <NUM_LIT> ) ^ <NUM_LIT> ; encoding = ( N << <NUM_LIT> ) | ( immr << <NUM_LIT> ) | ( nimms & <NUM_LIT> ) ; return true ; } } return


<s> bool getAddImmPrefix ( ) { return AddImmPrefix


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed =


<s> SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT>


<s> * p = '_' ; dollar_inside ++ ; p = strchr ( p + <NUM_LIT> , '$' ) ; } if ( TREE_PUBLIC ( n -> decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( n -> decl ) ) { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file , <STR_LIT> , buffer , name ) ; fprintf ( data -> file , <STR_LIT> , buffer , name ) ; } if ( data -> function_descriptor ) { fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } fputs ( <STR_LIT> , data -> file ) ; assemble_name ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } else if ( DECL_WEAK ( n -> decl ) && ! data -> function_descriptor ) ASM_WEAKEN_DECL ( data -> file , n -> decl , name , NULL ) ; } else { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = getLoc


<s> Value * <ISA_LIT>IREmitter :: visitFOR (


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter (


<s> UndefSrcElts . setBit ( i ) ; continue ; } auto * Cst = cast < ConstantFPSDNode > ( Src ) ; APInt RawBits = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; SrcEltBits [ i ] = RawBits . zextOrTrunc ( SrcEltSizeInBits ) ; } return CastBitData ( UndefSrcElts , SrcEltBits ) ; } if ( auto * Cst = getTargetConstantFromNode ( Op ) ) { Type * CstTy = Cst -> getType ( ) ; if ( ! CstTy -> isVectorTy ( ) || ( SizeInBits != CstTy -> getPrimitiveSizeInBits ( ) ) ) return false ; unsigned SrcEltSizeInBits = CstTy -> getScalarSizeInBits ( ) ; unsigned NumSrcElts = CstTy -> getVectorNumElements ( ) ; APInt UndefSrcElts ( NumSrcElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > SrcEltBits ( NumSrcElts , APInt ( SrcEltSizeInBits , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumSrcElts ; ++ i ) if ( ! CollectConstantBits ( Cst -> getAggregateElement ( i ) , SrcEltBits [ i ] , UndefSrcElts , i ) ) return false ; return CastBitData ( UndefSrcElts , SrcEltBits ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && EltSizeInBits <= VT . getScalarSizeInBits ( ) ) { if ( auto * Broadcast = getTargetConstantFromNode ( Op . getOperand ( <NUM_LIT> ) ) ) { unsigned SrcEltSizeInBits = Broadcast -> getType ( ) -> getScalarSizeInBits ( ) ; unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits ; APInt UndefSrcElts ( NumSrcElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > SrcEltBits ( <NUM_LIT> , APInt ( SrcEltSizeInBits , <NUM_LIT> ) ) ; if ( CollectConstantBits ( Broadcast , SrcEltBits [ <NUM_LIT> ] , UndefSrcElts , <NUM_LIT> ) ) { if ( UndefSrcElts [ <NUM_LIT> ] ) UndefSrcElts . setBits ( <NUM_LIT> , NumSrcElts ) ; SrcEltBits . append ( NumSrcElts - <NUM_LIT> , SrcEltBits [ <NUM_LIT> ] ) ; return CastBitData ( UndefSrcElts , SrcEltBits ) ; } } } if ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { unsigned SrcEltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits ; APInt UndefSrcElts ( NumSrcElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > SrcEltBits ; auto * CN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SrcEltBits . push_back ( CN -> getAPIntValue ( ) . zextOrTrunc ( SrcEltSizeInBits ) ) ; SrcEltBits . append ( NumSrcElts - <NUM_LIT> , APInt ( SrcEltSizeInBits , <NUM_LIT> ) ) ; return CastBitData ( UndefSrcElts


<s> return ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg ==


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( VRegs


<s> unsigned <ISA_LIT>16InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int


<s> if ( HideSandboxBase ) { MCContext & Context = Out . getContext ( ) ; MCSymbol * RetTarget = Context . createTempSymbol ( <STR_LIT> , true ) ; PushReturnAddress ( STI , Context , Out , RetTarget ) ; MCInst JMPInst ; JMPInst . setOpcode ( <STR_LIT> ) ; JMPInst . addOperand ( Op ) ; Out . EmitInstruction ( JMPInst , STI ) ; Out . EmitCodeAlignment ( kNaCl<ISA_LIT>InstructionBundleSize ) ; Out . EmitLabel ( RetTarget ) ; } else { Out . EmitBundleLock ( true ) ; MCInst CALLInst


<s> break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : case <STR_LIT> : { Mask . push_back ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { Mask . push_back ( i ) ; } break ; } case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERM2X128Mask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> BroadcastIdx -= BeginIdx ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } if ( V . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast ( DL , VT , V . getOperand ( <NUM_LIT> ) , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; SDValue BC = peekThroughBitcasts ( V ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( MayFoldLoad ( BC ) && ! cast < LoadSDNode > ( BC ) -> isVolatile ( ) ) { if ( ! Subtarget . is64Bit ( ) && VT . getScalarType ( ) == <STR_LIT> ) BroadcastVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; LoadSDNode * Ld = cast < LoadSDNode > ( BC ) ; SDValue BaseAddr = Ld -> getOperand ( <NUM_LIT> ) ; EVT SVT = BroadcastVT . getScalarType ( ) ; unsigned Offset = BroadcastIdx * SVT . getStoreSize ( ) ; SDValue NewAddr = DAG . getMemBasePlusOffset ( BaseAddr , Offset , DL ) ; V = DAG . getLoad ( SVT , DL , Ld -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Ld -> getMemOperand ( ) , Offset , SVT . getStoreSize ( ) ) ) ; } else if (


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) )


<s> case PROCESSOR_K6 : return <NUM_LIT> ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_PENTIUM4 : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case


<s> assert ( Kind == CondCode && <STR_LIT>


<s> getBDXAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; uint64_t Index = getMachineOpValue ( MI , MI . getOperand (


<s> if ( Cond . getOpcode ( ) != <STR_LIT> ) return Op ; return createCMovFP ( DAG , Cond , Op . getOperand ( <NUM_LIT> ) , Op

. getOperand ( <NUM_LIT> ) , SDLoc ( Op ) ) ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , JT -> getDebugLoc ( ) , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex (


<s> SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , InArgs , Handler ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) . Options

. GuaranteedTailCallOpt ) ? alignTo ( Handler . StackSize , <NUM_LIT> ) : <NUM_LIT> ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( <STR_LIT> ( Value ) != - <NUM_LIT> || <STR_LIT> ( - Value ) != -


<s> static bool aarch64_vfp_is_call_candidate ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , int * nregs ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; return aarch64_vfp_is_call_or_return_candidate ( mode , type , & pcum -> aapcs_vfp_rmode , nregs , NULL ,


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS )


<s> string source = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * load = ctx -> load ( <NUM_LIT> , source ) ; SExpr * stor = ctx -> store ( ctx -> address ( target ) , load ) ; alfbb . addStatement ( label , TII -> getName ( MI .


<s> name = XSTR ( XVECEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; tlsname = XALLOCAVEC ( char , strlen ( name ) + <NUM_LIT> ) ; strcpy ( tlsname , <STR_LIT> ) ; strcat ( tlsname , name + <NUM_LIT> ) ; rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx (


<s> Inst . addOperand ( MCOperand :: CreateImm ( CE ->


<s> bool HasAnyUndefs ; BVN -> isConstantSplat ( IntBits , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , true ) ; BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs


<s> return ( uint32x4_t ) __builtin_neon_vabauv4si ( ( int32x4_t ) __a , (


<s> if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) O << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs ; O <<


<s> unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; EVT FromVT = Op . getNode ( ) ? Op . getValueType ( ) : VT ; unsigned FromBytesPerElement = FromVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( FromBytesPerElement < BytesPerElement ) return false ; unsigned Byte = ( ( Elem * FromBytesPerElement ) % <STR_LIT> + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else if ( Op . getOpcode ( ) == <STR_LIT> && Op . hasOneUse ( ) ) { SmallVector < int , <STR_LIT> > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < <NUM_LIT> ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / <STR_LIT> ) ; Byte = unsigned ( NewByte ) % <STR_LIT> ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ; } else


<s> if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getValueType ( ) . getSimpleVT ( ) ; if ( VecVT . is256BitVector ( ) ) { DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; if ( IdxVal >= NumElems / <NUM_LIT> ) IdxVal -= NumElems / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op .


<s> Symbol . setIsRegistered ( true ) ; Symbols . push_back ( &


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT .


<s> } } if ( ! FoundSource ) { SourceVecs . push_back ( SourceVec ) ; MinElts . push_back ( EltNo ) ; MaxElts . push_back ( EltNo ) ; } } if ( SourceVecs . size ( ) > <NUM_LIT> ) return SDValue ( ) ; SDValue ShuffleSrcs [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; int VEXTOffsets [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; int OffsetMultipliers [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < SourceVecs . size ( ) ; ++ i ) { unsigned NumSrcElts = SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) ; SDValue CurSource = SourceVecs [ i ] ; if ( SourceVecs [ i ] . getValueType ( ) . getVectorElementType ( ) != VT . getVectorElementType ( ) ) { EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , SourceVecs [ i ] . getValueSizeInBits ( ) / VT . getVectorElementType ( ) . getSizeInBits ( ) ) ; CurSource = DAG . getNode ( <STR_LIT> , dl , CastVT , SourceVecs [ i ] ) ; OffsetMultipliers [ i ] = CastVT . getVectorNumElements ( ) / NumSrcElts ; NumSrcElts *= OffsetMultipliers [ i ] ; MaxElts [ i ] *= OffsetMultipliers [ i ] ; MinElts [ i ] *= OffsetMultipliers [ i ] ; } if ( CurSource . getValueType ( ) == VT ) { ShuffleSrcs [ i ] = CurSource ; VEXTOffsets [ i ] = <NUM_LIT> ; continue ; } else if ( NumSrcElts < NumElts ) { ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , CurSource , DAG . getUNDEF ( CurSource . getValueType ( ) ) ) ; continue ; } assert ( NumSrcElts == <NUM_LIT> * NumElts && <STR_LIT> ) ; if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , CurSource , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ITCondMask ) ; Op -> ITMask . Mask = Mask ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT>


<s> rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) { add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } dest = gen_rtx_MEM ( word_mode , tmpreg ) ; insn = emit_move_insn ( dest , src ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta )


<s> static bool isFuncletReturnInstr ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case


<s> bool isThumb1OnlyFunction ( ) const { return isThumb && !


<s> return ; } sve_switcher sve ; for ( unsigned int type_i = <NUM_LIT> ; type_i < NUM_VECTOR_TYPES ; ++ type_i ) { vector_type_index type = vector_type_index ( type_i ) ; register_vector_type ( type ) ; if ( type != VECTOR_TYPE_svbool_t ) for ( unsigned int count = <NUM_LIT> ; count <= MAX_TUPLE_SIZE ; ++ count ) register_tuple_type ( count , type ) ; } register_svpattern ( ) ; register_svprfop ( ) ; function_table = new hash_table < registered_function_hasher > ( <NUM_LIT> ) ; function_builder


<s> CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { MVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; Register ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; updateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; Register ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; updateValueMap ( I , ResultReg


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFEXP2_D_1 ( MachineInstr * MI , MachineBasicBlock * BB ) const { return


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , CallConv , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , OrigArg . Reg , Offset ) ; } ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget (

) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ;


<s> case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> const MCExpr * <ISA_LIT>AsmParser :: evaluateRelocExpr ( const MCExpr * Expr , StringRef RelocStr ) { <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind = StringSwitch < <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind > ( RelocStr ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GOT_CALL ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_CALL_HI16 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_CALL_LO16 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_DTP_HI ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_DTP_LO ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GOT ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GOT_HI16 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GOT_LO16 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GOTTPREL ) .

Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_GPREL ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_ABS_HI ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_ABS_LO ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_TLSGD ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_TLSLDM ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_TP_HI ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: CEK_TP_LO ) . Default ( <ISA_LIT>MCExpr :: CEK_None ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( CPUType , CPUSubtype )


<s> static DecodeStatus DecodeVSRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , VSRegs


<s> TS . setUsesMicro<ISA_LIT> ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ; else TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym


<s> return ( __m128 ) __builtin_ia32_minss ( ( __v4sf ) __A ,


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( ) , false , true , true , <NUM_LIT> ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG

. getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> static inline bool isVPTOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SDValue V = LowerI64IntToFP16 ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return SDValue ( ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getStoreSize ( ) ; Align Alignment ( Size ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , Alignment ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( VT , SrcVT , dl , Chain , StackSlot


<s> CVal = C -> getSExtValue ( ) ; break ; } return ; } case 'K' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'L' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'M' : { if ( ! isUInt < <NUM_LIT> > ( CVal ) ) return ; if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ ( uint32_t ) CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } case 'N' : { if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) ==


<s> return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister (


<s> void setISALevelAndRevisionFromPredicates ( const PredicateLibrary & P ) { if ( P . has<ISA_LIT>64 ( ) ) { ISALevel = <NUM_LIT> ; if ( P . has<ISA_LIT>64r6 ( ) ) ISARevision = <NUM_LIT> ; else if ( P . has<ISA_LIT>64r2 ( ) ) ISARevision = <NUM_LIT> ; else ISARevision = <NUM_LIT> ; } else if ( P . has<ISA_LIT>32 (


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return nullptr


<s> int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; EVT ResTy = Op . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ResTy ) ) return SDValue ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) { EVT SatVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( SatVT . getScalarSizeInBits ( ) != IntBits ) return SDValue ( ) ; } SDLoc DL ( N ) ; bool IsSigned = ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; unsigned IntrinsicOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getConstant ( IntrinsicOpcode , DL , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C


<s> std :: string FullFS = FS ; if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS =


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO


<s> for ( auto I = ++ MachineBasicBlock :: iterator ( Block . getPredicateThen ( ) ) , E = ++ MachineBasicBlock :: iterator ( Divergent -> MI ) ; I != E ; ++ I ) RemovePredicate ( & * I ) ; unsigned Size = <NUM_LIT> ; auto E = MachineBasicBlock :: reverse_iterator ( Divergent -> MI ) ; auto I = MachineBasicBlock :: reverse_iterator ( Insts . back ( ) . MI ) ; MachineInstr * InsertAt = nullptr ; while ( I != E ) { InsertAt = & * I ; ++ Size ; ++ I ; } MachineInstrBuilder MIB = BuildMI ( * InsertAt -> getParent ( ) , InsertAt , InsertAt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Block . getPredicateThen ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( Block . getPredicateThen ( ) ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else if ( Block . isVPT ( ) ) { bool RemovedVCTP = false ; for ( PredicatedMI & Elt : Block . getInsts ( ) ) { MachineInstr * MI = Elt . MI ; if ( isVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; LoLoop . ToRemove . insert ( MI ) ; RemovedVCTP = true ; continue ; } } if ( RemovedVCTP ) LoLoop . BlockMasksToRecompute . insert ( Block . getPredicateThen ( ) ) ; } } else if ( Block . IsOnlyPredicatedOn ( LoLoop . VCTP ) && Block . isVPST ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Block . getPredicateThen


<s> static DecodeStatus DecodeRestrictedIPredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( ( Val & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return MCDisassembler ::


<s> if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back (


<s> if ( offsettable_address_p ( true , GET_MODE ( op ) , XEXP ( op , <NUM_LIT> ) ) ) return true ; worst_case = ( ( TARGET_POWERPC64 && GET_MODE_CLASS ( reg_mode ) == MODE_INT ) || GET_MODE_SIZE (


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x16_t ) __builtin_aarch64_qtbx3v16qi ( ( int8x16_t ) r , __o , (


<s> } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ,

ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ;


<s> if ( RegWidth == <NUM_LIT> && ( Value & ~ <NUM_LIT> ) ) return false ; uint64_t MOVZEquivalent = RegWidth == <NUM_LIT> ? ~


<s> else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveObjectArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescSeq ( DirectiveID . getLoc ( ) ) ; else return true ; } else if ( IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveSEHAllocStack ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHAllocStack ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegs ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegs ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegs ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveLR ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHPrologEnd ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHPrologEnd ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHCustom ( DirectiveID . getLoc ( ) ) ; else return true ; } else return


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P (


<s> __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2di ( ( __builtin_aarch64_simd_di * ) __a , __o


<s> uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( triple . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) )


<s> <STR_LIT> getModifier ( ) const { return


<s> static DecodeStatus DecodeVM512RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo % <NUM_LIT> || RegNo

> <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , V1 ,

DAG . getConstant ( TargetMask , dl , <STR_LIT> ) ) ;


<s> static SDValue getUnpackl ( SelectionDAG & DAG , const SDLoc & dl , EVT VT , SDValue V1 , SDValue V2 ) { SmallVector < int , <NUM_LIT> > Mask ; createUnpackShuffleMask ( VT , Mask ,


<s> static void InsertLDR_STR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int Offset , bool isDef , const DebugLoc & DL , unsigned NewOpc , unsigned Reg , bool RegDeadKill , bool RegUndef , unsigned BaseReg , bool BaseKill , bool BaseUndef , bool OffKill , bool OffUndef , <STR_LIT> Pred , unsigned PredReg , const TargetInstrInfo * TII , bool isT2 ) { if ( isDef


<s> bool Changed = false ; for ( auto * F : Functions ) { DominatorTree * DT = & getAnalysis < DominatorTreeWrapperPass > ( * F ) . getDomTree ( ) ; BasicBlock * Root = DT -> getRoot ( ) ; ReversePostOrderTraversal < BasicBlock * > RPOT ( Root ) ; for ( auto * BB : RPOT ) for ( Instruction & I : make_early_inc_range ( * BB ) ) Changed |= optimizeIntrinsic ( & I ) ; } return Changed


<s> if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; EVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , ExtVT . getScalarType ( ) ) ; const Constant * C = ( dyn_cast < ConstantSDNode > ( Cst )


<s> if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; Fixups [ Fixups . size ( ) - <NUM_LIT> ] . setOffset ( <NUM_LIT> ) ; writeData ( Binary , <NUM_LIT> ,


<s> MCOperand hi = create<ISA_LIT>MCOperand ( HiKind , GOTSym , OutContext ) ; MCOperand lo = create<ISA_LIT>MCOperand ( LoKind , GOTSym , OutContext ) ; EmitSETHI ( OutStreamer , hi , RD , STI ) ; EmitOR ( OutStreamer , RD , lo , RD , STI


<s> if ( GET_CODE ( x ) == SET ) return ia64_spec_check_src_p (


<s> BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset -=


<s> return ( __m256i ) __builtin_ia32_prorq256_mask ( ( __v4di ) __A , __B , (


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO (

) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> static bool InRange ( int64_t Value , unsigned short Shift , int LBound , int HBound ) { int64_t Value2 = Value >> Shift ; if ( ( Value2 << Shift ) == Value && ( Value2 >= LBound ) && ( Value2 < HBound ) ) return true ; return false


<s> if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( E ) ) { switch ( A64E -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_DTPREL_G2 : case <ISA_LIT>MCExpr :: VK_DTPREL_G1 : case <ISA_LIT>MCExpr :: VK_DTPREL_G0 : case <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 : case <ISA_LIT>MCExpr :: VK_TPREL_G2 : case <ISA_LIT>MCExpr :: VK_TPREL_G1 : case <ISA_LIT>MCExpr ::


<s> return adjustPqBits ( Inst , Value , <NUM_LIT>


<s> return ( float32x2_t ) __builtin_neon_vld1_lanev2sf ( ( const __builtin_neon_sf *


<s> const MCSectionMachO & RefSec = cast < MCSectionMachO > ( Symbol . getSection ( ) ) ; return RefSec . getType ( ) != MachO ::


<s> void mips_output_aligned_bss ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align ) { extern tree last_assemble_variable_decl ; if ( mips_in_small_data_p ( decl ) ) named_section ( <NUM_LIT>


<s> unsigned PairedPhys = <NUM_LIT> ; if ( VRM && VRM -> hasPhys ( Hint . second ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Hint . second ) , Odd , this ) ; if ( PairedPhys && MRI . isReserved ( PairedPhys ) ) PairedPhys = <NUM_LIT> ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = <NUM_LIT> , E = Order . size ( ) ; I !=


<s> if ( ResTy != MatchOperand_Success || ! Op ) return MatchOperand_ParseFail ; Operands . push_back ( std :: move ( Op ) ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: LParen ) ) break ; break ; } } return MatchOperand_Success


<s> static SDValue splitStores ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { StoreSDNode * S = cast < StoreSDNode > ( N ) ; if ( S -> isVolatile ( ) || S -> isIndexed ( ) ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( SDValue ReplacedZeroSplat = replaceZeroVectorStore ( DAG , * S ) ) return ReplacedZeroSplat ; if ( ! Subtarget -> isMisaligned128StoreSlow ( ) ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) ,

S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> const AsmToken & Tok = Parser . getTok ( ) ; std :: string LowerID = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = getLexer ( ) . is ( AsmToken :: Hash


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addFrameIndex ( FI ) . addImm ( Offset )

. addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( ! COffs || COffs -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , getAL ( CurDAG , SDLoc ( N ) ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ) ; return


<s> static __inline unsigned long long sh_media_MSUB_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_subv4hi3 ( ( v4hi ) mm , (


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op )


<s> return ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort (


<s> bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) ==


, <NUM_LIT> , ( __mmask32 ) - <NUM_LIT> ) ;


<s> vmls_s8 ( int8x8_t a , int8x8_t b , int8x8_t c ) { int8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> warnIfNoMacro ( IDLoc ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned Opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned RtReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & BaseOp = Inst . getOperand ( <NUM_LIT> ) ; if ( BaseOp . isImm ( ) ) { int64_t ImmValue = BaseOp . getImm ( ) ; if ( ImmValue == <NUM_LIT> ) { TOut . emitRR ( Opcode , RtReg , BaseReg , IDLoc , STI ) ; return false ; } } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( expandLoadAddress ( ATReg , BaseReg , BaseOp , ! isGP64bit ( ) , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( Opcode , RtReg , ATReg , IDLoc , STI ) ; return


<s> else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass (

createFalkorMarkStridedAccessesPass ( ) ) ;


<s> else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; bool RAXImplicitDead = false ; for ( MachineOperand & Op : llvm :: drop_begin ( MI . operands ( ) ) ) { if ( Op . isReg ( ) && Op . isImplicit ( ) && Op . isDead ( ) && TRI -> regsOverlap ( Op . getReg ( ) , <STR_LIT> ) ) { Op . setIsDead ( false ) ; Op . setIsDef ( true ) ; RAXImplicitDead = true ; } OriginalCall -> addOperand ( Op ) ; } auto * Marker = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) -> moveCallSiteInfo ( & MI , Marker ) ; const uint32_t * RegMask = TRI -> getCallPreservedMask ( * MBB . getParent ( ) , CallingConv :: C ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , <NUM_LIT> ) . addRegMask

( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit | ( RAXImplicitDead ? ( RegState :: Dead | RegState :: Define ) : RegState :: Define ) ) . getInstr ( ) ;


<s> if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8s4OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst


<s> ia64_dconst_0_375_rtx = const_double_from_real_value ( rv , DFmode ) ; } return ia64_dconst_0_375_rtx


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( isdigit ( Constraint [ <NUM_LIT> ] ) ) { std :: string Suffix ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; unsigned Index = atoi ( Suffix . c_str ( ) ) ; if ( Index < <NUM_LIT> && Map [ Index ] ) return std :: make_pair ( Map [


<s> return ( int32x4_t ) __builtin_neon_vmla_lanev4si ( __a ,


<s> case Type :: FloatTyID : case Type :: DoubleTyID : return true ; case Type :: FP128TyID : return Subtarget . hasP9Vector