<s> SDValue <ISA_LIT>TargetLowering :: LowerINIT_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Trmp = Op . getOperand ( <NUM_LIT> ) ; SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP

( PATTERN ( last_real_insn ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> return ( ( type == <NUM_LIT> || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type )

) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + sh_hard_regno_nregs ( BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ;


<s> if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS


<s> CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; AssemblerDialect = <NUM_LIT> ; SupportsDebugInformation = true ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT (

<NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ;


<s> static rtx loongarch_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! IMM12_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = loongarch_force_temporary ( temp , high )


<s> rtx cvt ; rtvec cvt_vec ; rtx cvt_unspec ; rtvec move_vec ; rtx move_unspec ; if ( GET_CODE ( tmp ) == SCRATCH ) tmp = gen_reg_rtx ( V2DImode ) ; if ( MEM_P ( dest ) ) dest = rs6000_address_for_fpconvert ( dest ) ; cvt = gen_rtx_fmt_e ( code , GET_MODE ( dest ) , src ) ; cvt_vec = gen_rtvec ( <NUM_LIT> , cvt ) ; cvt_unspec = gen_rtx_UNSPEC ( V2DImode , cvt_vec , UNSPEC_IEEE128_CONVERT ) ; emit_insn ( gen_rtx_SET ( tmp , cvt_unspec ) ) ; move_vec = gen_rtvec ( <NUM_LIT> , tmp ) ; move_unspec = gen_rtx_UNSPEC ( GET_MODE ( dest ) , move_vec , UNSPEC_IEEE128_MOVE ) ; emit_insn ( gen_rtx_SET ( dest , move_unspec


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( )


<s> inline vector unsigned short vec_mfvscr (


<s> if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) ==


<s> static SDValue BuildIntrinsicOp ( unsigned IID , SDValue Op0 , SDValue Op1 , SDValue Op2 , SelectionDAG & DAG ,


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = & * std :: next ( MBBI ) ; return llvm :: is_contained ( MBB -> successors (


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; if ( AssemblerOptions . size ( ) == <NUM_LIT> ) return reportParseError ( Loc , <STR_LIT> ) ; AssemblerOptions . pop_back ( ) ; setAvailableFeatures ( AssemblerOptions . back ( ) ->


<s> unsigned Size = AI -> getPointerOperand ( ) -> getType (

) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) ;


<s> bool useExperimentalZeroingPseudos ( ) const { return UseExperimentalZeroingPseudos


<s> static inline bool isZeroOrAllOnes ( SDValue N ,


<s> if ( ! MCID . isPredicable ( ) ) return false ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function (


<s> if ( td == NULL_TREE ) return false ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return


<s> void <ISA_LIT>LowOverheadLoops :: IterationCountDCE ( LowOverheadLoop & LoLoop ) { if ( ! LoLoop . IsTailPredicationLegal ( ) ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstr * Def = RDA -> getMIOperand ( LoLoop . Start , isDo (

LoLoop . Start ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> if ( IID == <NUM_LIT> ) return false ; uint8_t index = <NUM_LIT> ; Name . consumeInteger ( <NUM_LIT> , index ) ; if ( index >= Prefetches . size ( ) ) Prefetches . resize ( index + <NUM_LIT> ) ; Prefetches [ index ] = { IID , D } ; max_index = std :: max ( max_index , static_cast < int16_t > ( index ) ) ; } } assert ( max_index + <NUM_LIT> >= <NUM_LIT> && <STR_LIT> ) ; assert ( static_cast < size_t > ( max_index + <NUM_LIT> ) == Prefetches . size ( ) && <STR_LIT> <STR_LIT> ) ; return ! Prefetches . empty (


<s> static DecodeStatus DecodeSPE4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> Register DefRegister = FaultingMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; FaultMaps :: FaultKind FK = static_cast < FaultMaps :: FaultKind > ( FaultingMI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MCSymbol * HandlerLabel = FaultingMI . getOperand ( <NUM_LIT> ) . getMBB ( ) -> getSymbol ( ) ; unsigned Opcode = FaultingMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned OperandsBeginIdx = <NUM_LIT> ; assert ( FK < FaultMaps :: FaultKindMax && <STR_LIT> ) ; FM . recordFaultingOp ( FK , HandlerLabel ) ; MCInst MI


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>CC ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG , ST -> isThumb ( ) , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( LHS , RHS ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT>


<s> case GTU : case ORDERED : case UNORDERED : case UNEQ : case LTGT : mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask


<s> AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage (


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_ROUND_MASK )


<s> EVT CmpVT = Op0 . getValueType ( ) ; if ( CmpVT . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ; assert ( ( CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> ) && <STR_LIT> ) ; if ( CmpVT == <STR_LIT> && ! Subtarget . isAtom ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { ConstantSDNode * COp0 = dyn_cast < ConstantSDNode > ( Op0 ) ; ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op0 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits


<s> if ( LoadBase . isReg ( ) ) return LoadBase . getReg ( ) == StoreBase . getReg ( ) ; return LoadBase . getIndex ( ) ==


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> const auto * CmpRHSC = dyn_cast < ConstantFP > ( CmpRHS ) ; if ( CmpRHSC && CmpRHSC -> isNullValue ( ) ) CmpRHS = CmpLHS ; } unsigned CC ; bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>SSEConditionCode ( Predicate ) ; if ( CC > <NUM_LIT> ) return false ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * FR32 = & <STR_LIT> ; const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , FR32 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned AndReg = fastEmitInst_rr ( Opc [ <NUM_LIT> ] , RC , CmpReg , false , LHSReg


<s> case <STR_LIT> : addLeaRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) . addReg ( leaInReg2 ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) . addImm ( <STR_LIT> ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; if ( LV ) { LV -> getVarInfo ( leaInReg ) . Kills


<s> assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes ( * I ) ; } return


<s> ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Filler ) ) return false ; MBB . splice ( llvm :: next ( Slot ) , & MBB , llvm :: next ( Filler


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ) ;


<s> unsigned SubRegCopy = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) ) .

addDef ( SubRegCopy ) . addUse ( CopyReg , <NUM_LIT> , <STR_LIT> ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI )


<s> for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ]


<s> if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode ,


<s> ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT == <STR_LIT> ) { unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , Result32 , true , <STR_LIT> ) ; } else if ( DstVT != <STR_LIT> ) { ResultReg = fastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ; if ( ResultReg ==


<s> static int aarch64_reassociation_width ( unsigned opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params -> vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) )


<s> vld1_p64 ( const poly64_t * __a ) { return ( poly64x1_t ) __builtin_neon_vld1di ( (


<s> Register O1 = ValDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool CanNegateL ; bool MustBeFirstL ; if ( ! canEmitConjunction ( O0 , CanNegateL , MustBeFirstL , IsOR , MRI , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; bool MustBeFirstR ; if ( ! canEmitConjunction ( O1 , CanNegateR , MustBeFirstR , IsOR , MRI , Depth + <NUM_LIT> ) ) return false ; if ( MustBeFirstL && MustBeFirstR ) return false ; if ( IsOR ) { if ( ! CanNegateL && ! CanNegateR ) return false ; CanNegate = WillNegate && CanNegateL && CanNegateR ; MustBeFirst = ! CanNegate ; } else { assert ( Opcode == TargetOpcode :: G_AND && <STR_LIT>


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getSIMDShift16OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT>


<s> int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> removeOperand ( CCUse ) ; if ( Type == <STR_LIT> ) Branch -> removeOperand ( <NUM_LIT> ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> removeOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . add ( Compare . getOperand ( I ) ) ; MIB . add ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . add ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) { MIB . add (


<s> int ix86_frame_pointer_required ( void ) { if ( cfun -> machine

-> accesses_prev_frame ) return <NUM_LIT> ;


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return createMachOStreamer ( Ctx , TAB , OS ,

Emitter , RelaxAll , DWARFMustBeAtTheEnd , true ) ;


<s> const <ISA_LIT>TargetMachine & getTargetMachine ( ) const { return static_cast < const <ISA_LIT>TargetMachine & > (


_mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt . getValueType ( ) ; if ( getTypeAction ( * DAG . getContext ( ) , EltVT ) == TargetLowering :: TypePromoteFloat ) { SDLoc dl ( Op ) ; EVT IEltVT = <STR_LIT> ( EltVT . getScalarSizeInBits ( ) ) ; assert ( getTypeAction ( * DAG . getContext ( ) , IEltVT ) != TargetLowering :: TypePromoteFloat ) ; SDValue VecIn = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = VecIn . getValueType ( ) ; EVT IVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , IEltVT , VecVT . getVectorNumElements ( ) ) ; SDValue IElt = DAG . getNode ( <STR_LIT> , dl , IEltVT , Elt ) ; SDValue IVecIn = DAG . getNode ( <STR_LIT> , dl , IVecVT , VecIn ) ; SDValue IVecOut = DAG . getNode ( <STR_LIT> , dl , IVecVT , IVecIn , IElt , Lane ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> unsigned EltSize = Ty . getVectorElementType ( ) . getSizeInBits ( ) ; BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Subtarget . hasDSP ( ) ) return SDValue ( ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle (

) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ;


<s> fprintf ( asm_out_file , <STR_LIT> , ( * targetm

. strip_name_encoding ) ( frame_table_label ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState (


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; unsigned FirstOpc = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpc = SecondMI . getOpcode ( ) ; if ( ST . hasArithmeticBccFusion ( ) && isArithmeticBccPair ( FirstOpc , SecondOpc , FirstMI ) ) return true ; if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstOpc , SecondOpc , FirstMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstOpc , SecondOpc ) ) return true ; if ( ST . hasFuseCryptoEOR ( ) && isCryptoEORPair ( FirstOpc , SecondOpc ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstOpc , SecondOpc , FirstMI , SecondMI ) )


<s> if ( NewC . Op0 . getValueType ( ) != <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . ICmpType == <STR_LIT> ) return ; if ( NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> ) { if ( CmpVal == uint64_t ( - <NUM_LIT> ) ) return ; CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<=


<s> AU . addRequired < MachineDominatorTree >


<s> void <ISA_LIT>AsmPrinter :: EmitXRayTable ( ) { if ( Sleds . empty ( ) ) return ; if ( Subtarget -> isTargetELF ( ) ) { auto * Section = OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_GROUP | ELF :: SHF_MERGE , <NUM_LIT> , CurrentFnSym -> getName ( ) ) ; auto PrevSection = OutStreamer -> getCurrentSectionOnly ( ) ; OutStreamer -> SwitchSection ( Section ) ; for ( const auto & Sled : Sleds ) { OutStreamer -> EmitSymbolValue ( Sled . Sled , <NUM_LIT> ) ; OutStreamer -> EmitSymbolValue ( CurrentFnSym , <NUM_LIT> ) ; auto Kind = static_cast < uint8_t > (


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> return <ISA_LIT>ABIInfo ( <STR_LIT> )


<s> unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , DL , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , DL , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB


<s> bool hasFuseArithmeticLogic ( ) const { return HasFuseArithmeticLogic


<s> if ( TARGET_ELF && tls_referenced_p ( x ) ) return false ; return ( ( GET_CODE ( x ) != CONST_DOUBLE && GET_CODE ( x ) != CONST_VECTOR ) || GET_MODE ( x ) == VOIDmode || ( TARGET_POWERPC64 && mode == DImode ) || easy_fp_constant ( x , mode ) || easy_vector_constant


<s> return ( __m256i ) __builtin_ia32_vcvttph2w256_mask ( __A , ( __v16hi ) _mm256_setzero_si256 ( ) , ( __mmask16 )


<s> if ( getStreamer ( ) . getCurrentSection ( ) . first -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return false


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEabiAttr ( SMLoc L ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Tag = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; L = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Value = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex


<s> for ( auto & I : PreHeader . instrs ( ) ) if (

I . getOpcode ( ) == LOOPi ) return & I ;


<s> void \ fini_section ( ) \ { \ if ( ( ! TARGET_ELF ) && in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ in_section =


<s> if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( SrcReg ) MIB . addReg ( SrcReg


<s> const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( )


<s> return ( __m128 ) __builtin_ia32_vfmaddss3_maskz ( ( __v4sf ) __W , - ( __v4sf ) __A , - (


<s> if ( hasNOP ( ) ) { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> return N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || isExtendedBUILD_VECTOR ( N , DAG ,


<s> case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCEIL : return true ; } return false


<s> return selectBDAddr ( <STR_LIT> , Addr , Base


<s> if ( Shift >= DstBits ) return <NUM_LIT> ; unsigned ImmR = RegSize - Shift ; unsigned ImmS = std :: min < unsigned > ( SrcBits - <NUM_LIT> , DstBits - <NUM_LIT> - Shift ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZext ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> )

. addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ;


<s> PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT>

) && Subtarget . hasFPIdx ( ) ) return false ;


<s> if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT>


<s> static MachineBasicBlock * emitMonitor ( MachineInstr & MI , MachineBasicBlock * BB , const <ISA_LIT>Subtarget & Subtarget , unsigned Opc ) { DebugLoc dl = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned MemOpc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) .

addReg ( MI . getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ;


<s> psrlh_u ( uint16x4_t s , uint8_t amount ) { return __builtin_loongson_psrlh_u ( s


<s> for ( auto & Terminator : Terminators ) if ( mustRelaxBranch ( Terminator , Terminator . Address ) ) return true ; return


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT )


<s> const ArrayRef < MCPhysReg > ByValArgRegs = CC . intArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . numIntArgRegs ( ) - ByVal . FirstIdx ) * CC . regSize ( ) ) ; else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , DL , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy ) , StorePtr , MachinePointerInfo ( FuncArg , Offset ) ) ; OutChains . push_back (


<s> SDValue callFunction ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , const char * fnName , SDValue Dst , SDValue Src , SDValue Size ) { auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node = Op


<s> int NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( int i = <NUM_LIT> , j = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( ! isUndefOrEqual ( BitI1 , j ) ) return false ; } return


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { return TargetLowering :: getRegForInlineAsmConstraint ( TRI ,


<s> void <ISA_LIT>ELFStreamer :: emitFnStart ( ) { assert ( FnStart == <NUM_LIT> ) ; FnStart = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( FnStart


<s> MCELFStreamer :: emitInstruction ( Inst


<s> MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; MBB -> addSuccessor ( NextMBB ) ; } MBB = NextMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextDestReg ) . addReg ( ThisDestReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextSrcReg ) . addReg ( ThisSrcReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextCountReg ) . addReg ( ThisCountReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NextCountReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor (


<s> uint64_t Offset = cast < ConstantInt > ( cast < ConstantAsMetadata > ( cast < MDTuple > ( CallToInline . getOperand ( <NUM_LIT> ) . getMetadata ( ) ) -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) -> getZExtValue ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; assert ( ! ( STI . is64Bit ( ) && STI . isTargetWindowsCoreCLR ( ) ) && <STR_LIT> ) ; const uint64_t StackProbeSize = TLI . getStackProbeSize ( MF ) ; uint64_t ProbeChunk = StackProbeSize


<s> MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE ,


<s> } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) return false ; } MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI ->


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> case <STR_LIT> : return true ; case <STR_LIT> : switch ( Def -> getOperand ( <NUM_LIT> ) . getType ( ) ) { default : return false ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return true ; } case


<s> MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( ) - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildMaskLowPtrBits ( PtrTy , ListTmp , Log2 ( Alignment ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrSize , PtrAlign ) ) ; MI . eraseFromParent ( ) ; return


<s> bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & *


<s> unsigned MandarinInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex


<s> return ( __m256h ) __builtin_ia32_vfcmaddcph256_mask3 ( ( __v16hf ) __A , ( __v16hf ) __B , (


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( unsigned InnerVT = ( unsigned ) <STR_LIT> ; InnerVT <= ( unsigned ) <STR_LIT> ; ++ InnerVT ) setTruncStoreAction ( VT . getSimpleVT ( ) , ( <STR_LIT> ) InnerVT , Expand ) ; } setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT


<s> static void aarch64_add_constant ( int regnum , int scratchreg , HOST_WIDE_INT delta ) { HOST_WIDE_INT mdelta = delta ; rtx this_rtx = gen_rtx_REG ( Pmode , regnum ) ; rtx scratch_rtx = gen_rtx_REG ( Pmode , scratchreg ) ; if ( mdelta < <NUM_LIT> ) mdelta = - mdelta ; if ( mdelta >= <NUM_LIT> * <NUM_LIT> ) { ( void ) aarch64_build_constant ( scratchreg , delta , true ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , scratch_rtx ) ) ; } else if ( mdelta >


<s> if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> && I -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ) return true ; } return false ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm


<s> vf1 = ( __vector float ) vec_ctf ( vm1 , <NUM_LIT> ) ; return ( ( __m128 ) ( __vector unsigned long long ) { ( ( __vector unsigned long long ) vf1 ) [ <NUM_LIT> ] , ( ( __vector

unsigned long long ) __A ) [ <NUM_LIT> ] } ) ;


<s> if ( FirstInstrToMove != SecondInstrToMove ) MBB -> splice ( FirstTerminator , MBB , SecondInstrToMove ) ; MBB -> splice ( FirstTerminator , MBB , CRI . MI ) ; unsigned Opc = CRI . MI -> getOpcode ( ) ; bool InvertOrigBranch , InvertNewBranch , TargetIsFallThrough ; computeBranchTargetAndInversion ( Opc , Branch -> getOpcode ( ) , UsingDef1 , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough ) ; MachineInstr * SplitCond = UsingDef1 ? CRI . CopyDefs . second : CRI . CopyDefs . first ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( InvertNewBranch ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( TargetIsFallThrough ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Branch -> dump ( ) ) ; BlockSplitInfo BSI { Branch , SplitBefore , SplitCond , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough , MBPI , CRI . MI , UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second } ; bool Changed = splitMBB ( BSI ) ; if ( Changed ) { bool Input1CRlogical = CRI . TrueDefs . first && isCRLogical ( * CRI . TrueDefs . first ) ; bool Input2CRlogical = CRI . TrueDefs . second && isCRLogical ( * CRI . TrueDefs . second ) ; if ( Input1CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo


<s> return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType , CPUSubtype ) , OS


<s> if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = TLI . getPointerTy ( DL ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( DL ) ) ; Register ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg


<s> unsigned Register = FPR16DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> const AsmToken & Tok = getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok . getString ( ) ; <STR_LIT> CC = parseCondCodeString ( Cond ) ; if ( CC == <STR_LIT> )


<s> InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder ,


<s> Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % <NUM_LIT> ) == <NUM_LIT> ) && FP_REGNO_P ( last_regno ) ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return <NUM_LIT> ; if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return


<s> for ( auto & useDef : regInfo . reg_operands ( virtReg ) ) { ( void ) useDef ; ++ useDefCount


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void <ISA_LIT>InstPrinter :: printCallOperand ( const MCInst * MI , int OpNum ,


<s> assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM == Reloc ::


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl (


<s> tls [ <NUM_LIT> ] = <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == UNSPEC ) { char off = which == RS6000_PLTSEQ_PLT_PCREL34 ? '8' : '4' ; if ( XINT ( operands [ <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSGD ) sprintf ( tls , <STR_LIT> , off , rel64 ) ; else if ( XINT ( operands [ <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) sprintf ( tls , <STR_LIT> , off , rel64 ) ; } gcc_assert ( DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4 ) ; static char str [ <NUM_LIT> ] ; char off = WORDS_BIG_ENDIAN ? '2' : '4' ; const char * addend = ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; switch ( which ) { case RS6000_PLTSEQ_TOCSAVE : sprintf ( str , <STR_LIT> <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , tls , rel64 ) ; break ; case RS6000_PLTSEQ_PLT16_HA : if ( DEFAULT_ABI == ABI_V4 && ! flag_pic ) sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 ) ; else sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 , addend ) ; break ; case


<s> for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , VecTys [ i ] , Expand ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; } setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( Subtarget . hasDSPR2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( ! Subtarget . abiUsesSoftFloat ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasCn<ISA_LIT> ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; else if ( Subtarget . isGP64bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . isGP64bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( NoDPLoadStore ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget . has<ISA_LIT>32r6 ( )


<s> if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> virtual bool doInitialization ( Module & M ) override { if ( ! TOC . empty ( ) )


<s> static __inline void _MM_SET_EXCEPTION_STATE ( unsigned int __mask ) { _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_EXCEPT_MASK ) |


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; } } assert ( StringRef ( Modifier ) == <STR_LIT> && <STR_LIT> ) ; printOperand ( MI , OpNo


<s> } } if ( ldm_p ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ldm_regs ) ) ; int regno , slot ; for ( regno = sreg , slot = <NUM_LIT> ; regno <= ereg ; regno ++ , slot ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , slot * <NUM_LIT> ) ; rtx set = gen_rtx_SET ( reg , gen_frame_mem ( SImode , addr ) ) ; XVECEXP ( par , <NUM_LIT> , slot ) = set ; } insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; for ( regno = sreg ; regno <= ereg ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } } } expand_csky_stack_adjust ( adjust ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx ,


<s> void <ISA_LIT>InstPrinter :: printImmHex ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> static __inline unsigned long long sh_media_MMULFXRP_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MMULFXRP_W ( ( v4hi ) mm , (


<s> const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ?


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) ,


<s> dbgs ( ) << <STR_LIT> ; EC -> dump ( ) ; dbgs ( ) << <STR_LIT> << VectorWidth << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ceil -> dump ( ) ; ) ; bool Zero = SE -> getMinusSCEV ( SE -> getBackedgeTakenCount ( L ) , SE -> getUDivExpr ( SE -> getAddExpr ( SE -> getMulExpr ( Ceil , VW ) , SE -> getNegativeSCEV ( VW ) ) , VW ) ) -> isZero ( ) ; if ( ! Zero ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } auto * IV = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * IVExpr = SE -> getSCEV ( IV ) ; auto * AddExpr = dyn_cast < SCEVAddRecExpr > ( IVExpr ) ; if ( ! AddExpr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; IVExpr -> dump ( ) ) ; return false ; } if ( AddExpr -> getLoop ( ) != L ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Base = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Base || ! Base -> isZero ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Step = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Step ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddExpr -> getOperand ( <NUM_LIT> ) -> dump ( ) ) ; return false ; } auto StepValue = Step -> getValue ( ) -> getSExtValue ( ) ; if ( VectorWidth == StepValue ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StepValue << <STR_LIT> << VectorWidth <<


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } assert ( L -> empty ( ) && <STR_LIT> ) ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef Cpu , StringRef FeatureString , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CodeModel , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , computeDataLayout ( ) , TT , Cpu , FeatureString , Options , getEffectiveRelocModel ( RM ) , CodeModel , OptLevel ) , Subtarget ( TT , Cpu , FeatureString , * this , Options , CodeModel , OptLevel ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) { initAsmInfo ( )


<s> unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( Reg0 ) << <STR_LIT> << getRegisterName (


<s> bool <ISA_LIT>InstructionSelector :: selectBrJT ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_BRJT && <STR_LIT> ) ; Register JTAddr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned JTI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; Register Index = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TargetReg = MRI . createVirtualRegister


<s> if ( ! rtx_equal_p ( func_addr , func ) ) emit_move_insn ( func_addr , func ) ; abi_reg = func_addr ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( is_pltseq_longcall ) { rtvec v = gen_rtvec ( <NUM_LIT> , abi_reg , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( <NUM_LIT> , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , abi_reg ) ; } else { func = force_reg ( Pmode , func ) ; func_addr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( func_addr , gen_rtx_MEM ( Pmode , func ) ) ; rtx ctr_reg = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( ctr_reg , func_addr ) ; func_addr = ctr_reg ; rtx func_toc_offset = GEN_INT ( GET_MODE_SIZE ( Pmode ) ) ; rtx func_toc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func , func_toc_offset ) ) ; toc_load = gen_rtx_USE ( VOIDmode , func_toc_mem ) ; if ( ! ( GET_CODE ( func_desc ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( func_desc ) ) && TARGET_POINTERS_TO_NESTED_FUNCTIONS && ! chain_already_loaded ( get_current_sequence ( ) -> next -> last ) ) { rtx sc_reg = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; rtx func_sc_offset = GEN_INT ( <NUM_LIT> * GET_MODE_SIZE ( Pmode ) ) ; rtx func_sc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func , func_sc_offset ) ) ; emit_move_insn ( sc_reg , func_sc_mem ) ; abi_reg = sc_reg ; } } } else { abi_reg = toc_reg ; func_addr = func ; } call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; n_call = <NUM_LIT> ; if ( toc_load ) call [ n_call ++ ] =


<s> Value * <ISA_LIT>IREmitter :: visitVSRLDQ ( const


<s> } case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegShiftedReg . SrcReg << <STR_LIT> ( <STR_LIT> ( RegShiftedReg . ShiftImm ) ) << <STR_LIT> << RegShiftedReg . ShiftReg << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftImm ) << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegShiftedImm . SrcReg << <STR_LIT> ( <STR_LIT> ( RegShiftedImm . ShiftImm ) ) << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftImm ) << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ; } case k_VectorList : OS << <STR_LIT> << VectorList . Count << <STR_LIT> << VectorList . RegNum << <STR_LIT> ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case


<s> case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg2 = ExtReg ; } } if ( ! UseImm ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) , DestReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) , DestReg ) . addReg ( SrcReg1 )


<s> bool is<ISA_LIT>32 ( ) const { return <ISA_LIT>ArchVersion


<s> Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> , Loc , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printMatrixTile ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & RegOp = MI -> getOperand ( OpNum ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; O << getRegisterName ( RegOp . getReg (


<s> bool isHiImm16 ( ) { if ( ! isImm ( ) ) return false ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return Value != <NUM_LIT> && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( )


<s> static unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , CC ) ) ; } return SDValue ( ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG ) ) return V ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT>


<s> break ; case CCValAssign :: AExt : ExtType = <STR_LIT> ; break ; } ArgValue = DAG . getExtLoad ( ExtType , DL , VA . getLocVT ( ) , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , MemVT ) ; InVals . push_back ( ArgValue ) ; } } <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( isVarArg ) { if ( ! Subtarget -> isTargetDarwin ( ) || IsWin64 ) { saveVarArgRegisters ( CCInfo , DAG , DL , Chain ) ; } unsigned StackOffset = CCInfo . getNextStackOffset ( ) ; StackOffset = ( ( StackOffset + <NUM_LIT> ) & ~ <NUM_LIT> ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; if ( MFI . hasMustTailInVarArgFunc ( ) ) { SmallVector < MVT , <NUM_LIT> > RegParmTypes ; RegParmTypes . push_back ( <STR_LIT> ) ; RegParmTypes . push_back ( <STR_LIT> ) ; SmallVectorImpl < ForwardedRegister > & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; CCInfo . analyzeMustTailForwardedRegisters ( Forwards , RegParmTypes , CC_<ISA_LIT>_AAPCS ) ; if ( ! CCInfo . isAllocated ( <STR_LIT> ) ) { unsigned X8VReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; Forwards . push_back ( ForwardedRegister ( X8VReg , <STR_LIT> , <STR_LIT> ) ) ; } } } if ( IsWin64 ) { for ( unsigned I = <NUM_LIT> , E = Ins . size ( ) ; I != E ; ++ I ) { if ( Ins [ I ] . Flags . isInReg ( ) ) { assert ( ! FuncInfo -> getSRetReturnReg ( ) ) ; MVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrTy ) ) ; FuncInfo -> setSRetReturnReg ( Reg ) ; SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ I ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ; } } } unsigned StackArgSize = CCInfo . getNextStackOffset ( ) ; bool TailCallOpt = MF . getTarget ( ) . Options . GuaranteedTailCallOpt ; if ( DoesCalleeRestoreStack ( CallConv , TailCallOpt ) ) { StackArgSize = alignTo ( StackArgSize , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore ( StackArgSize ) ; } FuncInfo -> setBytesInStackArgArea ( StackArgSize ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) Subtarget -> getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; return


<s> vec_perm_builder builder ( nelts , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i


<s> ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node ,


<s> Instruction * Inst = dyn_cast < Instruction > ( Op ) ; assert ( Inst && <STR_LIT> ) ; Imcomings . push_back ( Inst ) ; } Value * StorePtr = updatePhiIncomings ( BB , Imcomings


<s> return ( uint16x4_t ) __builtin_neon_vcgtzv4hf (


<s> __arm_stc ( const unsigned int __coproc , const unsigned int __CRd ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo


<s> static void AnalyzeVarArgs ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Ins ) { State . AnalyzeFormalArguments ( Ins ,


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O <<


<s> return TargetTriple . getOS ( ) == Triple ::


<s> MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc )


<s> static <ISA_LIT>ABIInfo CheriPureCap ( ) { return <ISA_LIT>ABIInfo ( ABI :: N64 ,


<s> std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock * Pred : SuccBB -> predecessors ( ) ) if ( ! examinePred ( * Pred , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo & MFI = Fn -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( & MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU , * IM


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , false ) )

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; ( void ) TRI ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( It , mainMBB ) ; MF -> insert ( It , restoreMBB ) ; MF -> insert ( It , sinkMBB ) ; restoreMBB -> setHasAddressTaken ( ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned LabelReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned LabelReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT>

) ) . addMBB ( mainMBB ) . addImm ( <STR_LIT> ) ;


<s> rtx target = operands [ <NUM_LIT> ] ; enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx op0 = operands [ <NUM_LIT> ] ; rtx op1 = operands [ <NUM_LIT> ] ; loongarch_extend_comparands ( code , & op0 , & op1 ) ; op0 = force_reg ( word_mode , op0 ) ; gcc_assert ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) ; if ( code == EQ || code == NE ) { rtx zie = loongarch_zero_if_equal ( op0 , op1 ) ; loongarch_emit_binary ( code , target ,


<s> ( void ) adjustFixupValue ( Fixup , Target . getConstant ( ) ) ; return false


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT>


<s> MCAsmParserExtension :: Initialize ( parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits (


<s> static bool isCSRestore ( MachineInstr * MI , const unsigned * CSRegs ) { return ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( )

&& isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) ;


<s> size_t len = strlen ( TREE_STRING_POINTER ( args ) ) ; char * str_to_check = ( char * ) alloca ( len + <NUM_LIT> ) ; strcpy ( str_to_check , TREE_STRING_POINTER ( args ) ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> , pragma_or_attr ) ; return false ; } unsigned int num_commas = num_occurences_in_str ( ',' , str_to_check ) ; char * token = strtok ( str_to_check , <STR_LIT> ) ; unsigned int num_attrs = <NUM_LIT> ; while ( token ) { num_attrs


<s> if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } } if ( RHSC && RHSC -> getSExtValue ( ) == - <NUM_LIT> && CC == <STR_LIT> && LHS . getOpcode ( )

!= <STR_LIT> && ProduceNonFlagSettingCondBr ) {


<s> switch ( GET_CODE ( x ) ) { case MEM : case CONST : x = XEXP ( x , <NUM_LIT> ) ; break ; case UNSPEC : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; x = XEXP ( x ,


<s> ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; bool HasImmForm = instrHasImmForm ( MI . getOpcode ( ) , IsVFReg , III , PostRA ) ; if ( HasImmForm && transformToImmFormFedByAdd ( MI , III , ForwardingOperand , * DefMI , KillFwdDefMI ) ) return true ; if ( HasImmForm && transformToImmFormFedByLI ( MI , III , ForwardingOperand , * DefMI ) ) return true ; if ( ! HasImmForm && simplifyToLI ( MI , * DefMI

, ForwardingOperand , KilledDef ) ) return true ;


<s> if ( ( NumElts % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast (


<s> continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; NewLoc . Block = & MF . front ( ) ; NewLoc . InsertionPt = & * NewLoc . Block -> begin ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewLoc . InsertionPt ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } if ( IsLiveIn || UnsafeCount > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } assert ( UnsafeCount == <NUM_LIT> && ! IsLiveIn && <STR_LIT> <STR_LIT> ) ; SmallPtrSetIterator < MachineInstr * > It = llvm :: find_if ( AllDefs , IsUnsafe ) ; assert ( It != AllDefs . end ( ) && <STR_LIT> ) ; MachineInstr * DefMI = * It ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> << * DefMI ) ; MachineBasicBlock :: iterator DefIt = DefMI ; ++ DefIt ; if ( DefIt != DefMI -> getParent ( ) -> end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefMI << <STR_LIT> << * DefIt ) ; NewLoc . Block = DefIt -> getParent ( ) ; NewLoc . InsertionPt = & * DefIt ; } FixupLocsForFn . emplace_back ( NewLoc )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CodeModel :: Medium , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) { initAsmInfo (


<s> break ; default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstStore ( Opc , SrcReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; unsigned Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return true ; } return


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT>


<s> Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; MVT DestVT = Op . getSimpleValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT>


<s> return ( unsigned long long ) __builtin_mulv2si3 ( ( v2si ) mm , (


<s> int len = strlen ( lines [ i ] ) ; if ( * real_pos <= len ) break ; ( * real_line ) ++ ; * real_pos -= len - <NUM_LIT> ; } ( * real_pos


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue (


<s> void <ISA_LIT>GNULDBackend :: initTargetSymbols ( IRBuilder & pBuilder , Module & pModule ) { if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null


<s> if ( ! STI -> has<ISA_LIT>32r6 ( ) || STI -> inMicro<ISA_LIT>Mode ( ) ) return false ; return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasForbiddenSlot ( I ) ; } , [ this ] ( auto & IInSlot , auto


<s> rtx tag ; if ( cfun -> machine -> doloop_tags == <NUM_LIT> || cfun -> machine -> doloop_tag_from_end == is_end ) { cfun -> machine -> doloop_tags ++ ; cfun -> machine -> doloop_tag_from_end = is_end ; } tag = GEN_INT ( cfun -> machine -> doloop_tags - <NUM_LIT> ) ; if ( is_end ) emit_jump_insn ( gen_doloop_end_internal ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , tag ) ) ; else emit_insn ( gen_doloop_begin_internal ( operands [ <NUM_LIT> ] ,


<s> return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue


<s> } } bool RV ; unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV && <STR_LIT> ) ; ( void ) RV ; unsigned Size = VT .


<s> unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { auto ToDelete = I ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved


<s> SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , CondBranches ,


<s> void addGPR64AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getGPR64Reg ( ) )


<s> return emit_insn ( gen_rtx_SET ( x , y )


<s> if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { auto * First = dyn_cast < User > ( Pair . first ) ; auto * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; auto * I = cast < Instruction > ( U . getUser


<s> SMLoc getOffsetOfLoc ( ) const override { return


<s> if ( RegNo > sizeof ( GPRDecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> machine_mode result_mode = GET_MODE ( dest ) ; if ( result_mode != compare_mode ) return false ; if ( code == UNGE || code == UNGT || code == UNLE || code == UNLT ) { code = reverse_condition_maybe_unordered ( code ) ; std :: swap ( true_cond , false_cond ) ; } bool max_p ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return false ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ; else return false ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN ,


<s> if ( ! InsMI ) return false ; if ( ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return false ; int64_t Index = <NUM_LIT> ; if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Index ) )


<s> decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES ( decl ) ; attrs_type_log = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; for ( i = <NUM_LIT> , d = bdesc_tm ; i < ARRAY_SIZE ( bdesc_tm ) ; i ++ , d ++ ) { if ( ( d -> mask & ix86_isa_flags ) != <NUM_LIT> || (


<s> bool <ISA_LIT>RegisterInfo :: isAnyArgRegReserved ( const MachineFunction & MF ) const { return llvm :: any_of ( * <STR_LIT> . MC , [ this , & MF ] ( MCPhysReg r ) { return isReservedReg ( MF , r ) ; } )


<s> return __builtin_mve_vsubq_n_uv4si ( __a ,


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( FalseVal ) ; if ( ! C ) return false ; if ( AllOnes ) return C -> isAllOnesValue ( ) ; return C -> isNullValue


<s> static __inline qword si_selb ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_sel ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b


<s> MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer -> EmitLabel ( Stub ) ; OutStreamer -> EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * Anon = MCSymbolRefExpr :: create ( AnonSymbol , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: create ( LazyPtr , OutContext ) ; const MCExpr * Sub = MCBinaryExpr :: createSub ( LazyPtrExpr , Anon , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer -> EmitLabel ( AnonSymbol ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: createHa ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: createLo ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer -> SwitchSection ( LSPSection ) ; OutStreamer -> EmitLabel ( LazyPtr ) ; OutStreamer -> EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; MCSymbol * DyldStubBindingHelper = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) { OutStreamer -> EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } else { OutStreamer -> EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT>


<s> bool ix86_force_load_from_GOT_p ( rtx x ) { return ( ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) && ! TARGET_PECOFF && ! TARGET_MACHO && ! flag_plt && ! flag_pic && ix86_cmodel != CM_LARGE && GET_CODE

( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ;


<s> int _U_Qfeq ( long double a , long double b ) { return ( _U_Qfcmp ( a , b


<s> for ( size_t i = <NUM_LIT> , e = CCAssignments . size ( ) ; i != e ; ++ i ) CCAssignments [ i ] = <NUM_LIT> ; for ( size_t i = <NUM_LIT> , e = SFAssignments . size ( ) ;

i != e ; ++ i ) SFAssignments [ i ] = <NUM_LIT> ;


<s> for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( !


<s> return <NUM_LIT> * getPointerTy ( DL ) . getSizeInBits ( )


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && legitimate_address_p (


<s> if ( DAG . getSubtarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return


<s> unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( Op0Reg ) . addReg ( Op0Reg ) ; unsigned ResultReg = createResultReg (


<s> if ( isFence ( Dest -> getValue ( ) ) ) { ElimNodes . insert ( * Dest ) ; ElimEdges . insert ( E ) ; for ( const Edge & DE : Dest -> edges ( ) ) ElimEdges . insert ( DE ) ; } } } int MitigatedGadgets = <NUM_LIT> , RemainingGadgets = <NUM_LIT> ; NodeSet ReachableNodes { G } ; for ( const Node & RootN : G . nodes ( ) ) { if ( llvm :: none_of ( RootN . edges ( ) , MachineGadgetGraph :: isGadgetEdge ) ) continue ; ReachableNodes . clear ( ) ; std :: function < void ( const Node * , bool ) > FindReachableNodes = [ & ] ( const Node * N , bool FirstNode ) { if ( ! FirstNode ) ReachableNodes . insert ( * N ) ; for ( const Edge & E : N -> edges ( ) ) { const Node * Dest = E . getDest ( ) ; if ( MachineGadgetGraph :: isCFGEdge ( E ) && ! ElimEdges . contains ( E ) && ! ReachableNodes . contains ( * Dest ) ) FindReachableNodes ( Dest , false ) ; } } ; FindReachableNodes ( & RootN , true ) ; for ( const Edge & E : RootN . edges ( ) ) { if ( MachineGadgetGraph :: isGadgetEdge ( E ) ) { if ( ReachableNodes . contains ( * E . getDest ( ) ) ) { ++ RemainingGadgets ; } else { ++ MitigatedGadgets


<s> GlobalBaseReg = <NUM_LIT> ; SelectionDAGISel :: runOnFunction ( Fn ) ; InsertVRSaveCode ( Fn ) ; return true


<s> <ISA_LIT>PLT1 * <ISA_LIT>PLT :: create ( ) { <ISA_LIT>PLT1 * plt1_entry = new ( std :: nothrow ) <ISA_LIT>PLT1 (


<s> static SDValue foldXorTruncShiftIntoCmp ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N1 ) || ! cast < ConstantSDNode > ( N1 ) -> isOne ( ) ) return SDValue ( ) ; SDValue Shift = N0 . getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> || ! Shift . hasOneUse ( ) ) return SDValue ( ) ; EVT ShiftTy = Shift . getValueType ( ) ; if ( ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> && ShiftTy != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) || Shift . getConstantOperandVal ( <NUM_LIT> ) != ShiftTy . getSizeInBits ( ) - <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue ShiftOp = Shift . getOperand ( <NUM_LIT> ) ; EVT ShiftOpTy = ShiftOp . getValueType ( ) ; SDValue Cond = DAG . getSetCC ( DL , <STR_LIT> , ShiftOp , DAG . getConstant ( - <NUM_LIT> , DL ,


<s> } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( MI , OpNo , O


<s> Value * <ISA_LIT>IREmitter :: visitFMIN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) && canRealignStack ( MF ) ) ) { if ( isFrameOffsetLegal ( MI , FPOffset ) ) return false ; } if ( ! MFI -> hasVarSizedObjects ( ) && isFrameOffsetLegal ( MI , Offset ) ) return false ; return


<s> printThumbAddrModeImm5SOperand ( MI , Op , O ,


<s> if ( scaleShuffleElements ( SVN0 -> getMask ( ) , <NUM_LIT> , ShuffleMask0 ) && scaleShuffleElements ( SVN1 -> getMask ( ) , <NUM_LIT> , ShuffleMask1 ) ) { SDValue Op00 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op01 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op10 = SVN1 -> getOperand ( <NUM_LIT> ) ; SDValue Op11 = SVN1 -> getOperand ( <NUM_LIT> ) ; if ( ( Op00 == Op11 ) && ( Op01 == Op10 ) ) { std :: swap ( Op10 , Op11 ) ; ShuffleVectorSDNode :: commuteMask ( ShuffleMask1 ) ; } if ( ( Op00 == Op10 ) && ( Op01 == Op11 ) ) { SmallVector < int , <NUM_LIT> > ShuffleMask ; ShuffleMask . append ( ShuffleMask0 . begin ( ) , ShuffleMask0 . end ( ) ) ; ShuffleMask . append ( ShuffleMask1 . begin ( ) , ShuffleMask1 . end ( ) ) ; SDLoc DL ( N ) ; SDValue Res = DAG . getNode ( Opcode , DL , VT , Op00 , Op01 ) ; Res = DAG . getBitcast ( <STR_LIT>


<s> bool allocateSeparateGVMemory ( ) const override { return true ; return


<s> for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { APInt Val = SplatValue . extractBits ( ScalarSize , ScalarSize * i ) ; Constant * Const ; if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type

:: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ;