<s> <STR_LIT> ET = getShiftExtendType ( ) ; return ( ET == <STR_LIT> || ET == <STR_LIT> ) && ( getShiftExtendAmount ( ) == Log2_32 ( Width / <NUM_LIT> ) || getShiftExtendAmount


<s> else if ( STI . isTargetWindows ( ) ) return <STR_LIT> ; else return STI . isThumb ( )


<s> for ( unsigned I = <NUM_LIT> , E = Operands . size ( ) ; I != E


<s> MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNode ( <STR_LIT> , dl , VT


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; if ( ! Memory . OffsetRegNum ) { <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; } else { Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> :


<s> SDLoc dl ( N ) ; LHS = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; LHS = DAG . getBitcast ( <STR_LIT> , LHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , LHS , RHS ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && RHS . hasOneUse ( ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N ) ; RHS = DAG . getVectorShuffle ( <STR_LIT> , dl , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; RHS = DAG . getBitcast (


<s> if ( -- CPE -> RefCount == <NUM_LIT> ) { removeDeadCPEMI ( CPEMI ) ; CPE -> CPEMI = nullptr ; -- NumCPEs ; return true


<s> MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent ( )


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction &


<s> if ( BaseReg . getReg ( ) ) { printOperand ( MI , Op , O , Modifier , AsmVariant ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <NUM_LIT> , O , Modifier , AsmVariant ) ; NeedPlus = true ; } assert ( DispSpec . isImm ( ) && <STR_LIT> ) ; int64_t DispVal = DispSpec . getImm (


<s> assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; } MI . getOperand ( i ) . ChangeToRegister ( ScratchReg , false , false , true ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) MI .


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mul_ss ( __m128 __A , __m128 __B ) { __m128 a , b , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = a * b ; return ( vec_sel ( __A , c , mask ) ) ; __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] * __B [ <NUM_LIT> ] ; return ( __A )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant (

C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ;


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) != ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return false ; if ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) != ( Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return false ; return


<s> MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) BaseReg = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; else BaseReg = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( BaseReg ) . addImm ( BPOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; MIB . addRegMask ( TRI -> getNoPreservedMask ( ) ) ; BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB , <NUM_LIT> ) ; thisMBB -> addSuccessor ( sinkMBB , <NUM_LIT> ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) , LabelReg ) ; if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else


<s> if ( VT != <STR_LIT> && ( ! HasInt256 || VT != <STR_LIT> ) ) return false ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; } return


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ArgsPreserved , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getParamCC ( CallConv , false ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( ! VA . needsCustom ( ) && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset ,


<s> bool <ISA_LIT>TargetLowering :: isNarrowingProfitable ( MVT VT1 , MVT VT2 ) const { return ! ( VT1 == <STR_LIT> &&


<s> unsigned VF = VecTy -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; unsigned NumOfSources = Factor ; InstructionCost ShuffleCost = getShuffleCost ( TTI :: SK_PermuteTwoSrc , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfShufflesPerStore = NumOfSources - <NUM_LIT> ; unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore


<s> char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRange , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( OriginalError == Match_MnemonicFail ) return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; if ( OriginalError == Match_Unsupported ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; assert ( OriginalError == Match_InvalidOperand && <STR_LIT> ) ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( Operand . getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand . getLocRange ( ) ; return Error ( Operand . getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end

( Match ) , Match_Unsupported ) == <NUM_LIT> ) {


<s> Inst . addOperand ( MCOperand :: createImm ( unsigned


<s> } <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } emitSelect ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , CondCode , MIB ) ; I . eraseFromParent ( ) ; return true


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: addFullAddress ( const MachineInstrBuilder & MIB , <ISA_LIT>AddressMode & AM ) { AM . IndexReg = constrainOperandRegClass ( MIB -> getDesc ( ) , AM . IndexReg , MIB -> getNumOperands (


<s> return ( __m256i ) __builtin_ia32_loaddquqi256_mask ( ( const char * ) __P , ( __v32qi ) __W , ( __mmask32 )


<s> Value * Row = nullptr , * Col = nullptr ; Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = cast < IntrinsicInst > ( U . getUser ( ) ) ; std :: tie ( Row , Col ) = getShape


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V16HImode ; goto do_subreg ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V16HImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = ( d -> perm [ i / <NUM_LIT> ] < <NUM_LIT> ? const0_rtx : constm1_rtx ) ; vmode = V32QImode ; nelt = <NUM_LIT> ; target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , op0 ) ; op1 = gen_lowpart ( vmode , op1 ) ; goto finish_pblendvb ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ) << i ; break ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V4DImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << ( i * <NUM_LIT> ) ; vmode = V8SImode ; goto do_subreg ; default : gcc_unreachable ( ) ; } switch ( vmode ) { case V8DFmode : case V8DImode : mmode = QImode ; break ; case V16SFmode


<s> r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + <NUM_LIT> ) ; emit_move_insn ( r11 , GEN_INT ( offset ) ) ; emit_insn ( gen_adddi3 ( r11 , r11 , pointer ) ) ; base_address = gen_rtx_MEM ( Pmode , r11 )


<s> static void mips_emit_move_or_split ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type ) ; else mips_emit_move ( dest , src


<s> static bool r10k_needs_protection_p_call ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) { const_rtx mem = *


<s> if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> BinOp ; SDValue Src = DAG . matchBinOpReduction ( Extract , BinOp , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ; if ( ! Src ) return SDValue ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getScalarType ( ) ; if ( SrcSVT != ExtractVT || ( SrcVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { unsigned NumElts = SrcVT . getVectorNumElements ( ) ; unsigned NumSubElts = NumElts / <NUM_LIT> ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcSVT , NumSubElts ) ; unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ; } MinPos = DAG . getBitcast ( <STR_LIT> , MinPos ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MinPos ) ; MinPos = DAG . getBitcast ( SrcVT , MinPos ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; return DAG . getNode ( <STR_LIT> , DL , ExtractVT , MinPos , DAG

. getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> static int rs6000_loop_align_max_skip ( rtx_insn * label


<s> static rtx gen_safe_HIGH64 ( rtx dest , HOST_WIDE_INT


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new NaCl<ISA_LIT>_64AsmBackend ( T ,


<s> return parseRegister ( Operands , RegGR , <STR_LIT> , <ISA_LIT>Operand


<s> if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin (


<s> } } SDValue Ops [ <NUM_LIT> ] = { getUNDEF64 ( SDLoc ( N ) ) , convertTo ( SDLoc ( N ) , <STR_LIT> , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue ( N , <NUM_LIT>


<s> MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang


<s> assert ( canMakeTailCallConditional ( BranchCond , TailCall ) ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; assert ( BranchCond . size ( ) == <NUM_LIT> ) ; if ( CC != BranchCond [ <NUM_LIT> ] . getImm (


<s> return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> static SDValue emitMemMemImm ( SelectionDAG & DAG , const SDLoc & DL , unsigned Op , SDValue Chain , SDValue Dst , SDValue Src , uint64_t Size ) { return DAG . getNode ( Op , DL , getMemMemVTs ( Op , DAG ) , Chain , Dst , Src , DAG .

getConstant ( Size - <NUM_LIT> , DL , Src . getValueType ( ) ) ) ;


<s> bool Thumb2SizeReduce :: ReduceMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; bool LiveCPSR = MBB . isLiveIn ( <STR_LIT> ) ; MachineInstr * BundleMI = nullptr ; CPSRDef = nullptr ; HighLatencyCPSR = false ; for ( auto * Pred : MBB . predecessors ( ) ) { const MBBInfo & PInfo = BlockInfo [ Pred -> getNumber ( ) ] ; if ( ! PInfo . Visited ) { continue ; } if ( PInfo . HighLatencyCPSR ) { HighLatencyCPSR = true ; break ; } } bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = std :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } if ( MI -> isDebugInstr ( ) ) continue ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; bool NextInSameBundle = NextMII != E && NextMII -> isBundledWithPred ( ) ; if ( ReduceMI ( MBB , MI , LiveCPSR , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = std :: prev ( NextMII ) ; MI = & * I ; if ( NextInSameBundle && ! NextMII -> isBundledWithPred ( ) ) NextMII -> bundleWithPred ( ) ; } if ( BundleMI && ! NextInSameBundle && MI -> isInsideBundle ( ) ) { if ( BundleMI -> killsRegister ( <STR_LIT> ) ) LiveCPSR = false ; MachineOperand * MO = BundleMI -> findRegisterDefOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isDead ( ) ) LiveCPSR = true ; MO = BundleMI -> findRegisterUseOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isKill ( ) ) LiveCPSR = true ; } bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> isCall ( ) ) { CPSRDef = nullptr ; HighLatencyCPSR = false ; IsSelfLoop = false ; } else if ( DefCPSR ) { CPSRDef = MI ; HighLatencyCPSR = isHighLatencyCPSR ( CPSRDef ) ; IsSelfLoop = false ; } } MBBInfo & Info = BlockInfo [ MBB . getNumber ( ) ] ; Info . HighLatencyCPSR = HighLatencyCPSR ; Info . Visited = true ; return


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters ) Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> for ( auto & C : Candidates ) { if ( C -> size ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } C -> PopulateLoads ( ) ; ValueList & LHS = static_cast < BinOpChain * > ( C . get ( ) ) -> LHS ; ValueList & RHS = static_cast < BinOpChain * > (


<s> half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , <NUM_LIT> ) ; hi_half [ num ] = adjust_address (


<s> return isRepeatedShuffleMask ( <NUM_LIT> , VT , Mask ,


<s> case <STR_LIT> : case <STR_LIT> : { Register Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> slowTwoMemOps ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; Push -> cloneMergedMemRefs ( MF , { & * DefMov , & * Store } ) ; DefMov -> eraseFromParent ( ) ; } else { PushOpcode = Is64Bit ? <STR_LIT>


<s> Register MoveReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; return


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: G_SADDO : return std :: make_pair ( emitADDS ( Dst , LHS , RHS , MIRBuilder ) , <STR_LIT> ) ; case TargetOpcode :: G_UADDO : return std :: make_pair ( emitADDS ( Dst , LHS ,


<s> unsigned getMinVectorRegisterBitWidth ( ) const { return <NUM_LIT>


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( ImmVal >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL ,


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress || reload_in_progress ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false


<s> if ( ! Subtarget -> hasV6T2Ops ( ) ) return NULL ; unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> &&


<s> TagStoreInstr & FirstTagStore = TagStores [ <NUM_LIT> ] ; TagStoreInstr & LastTagStore = TagStores [ TagStores . size ( ) - <NUM_LIT> ] ; Size = LastTagStore . Offset - FirstTagStore . Offset + LastTagStore . Size ; DL = TagStores [ <NUM_LIT> ] . MI -> getDebugLoc ( ) ; Register Reg ; FrameRegOffset = TFI -> resolveFrameOffsetReference ( * MF , FirstTagStore . Offset , false , false , Reg , false , true ) ; FrameReg = Reg ; FrameRegUpdate = None ; mergeMemRefs ( TagStores , CombinedMemRefs ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( const auto & Instr : TagStores ) { dbgs ( ) << <STR_LIT> << * Instr . MI ; } ) ; const int kSetTagLoopThreshold = <NUM_LIT> ; if ( Size < kSetTagLoopThreshold ) { if ( TagStores . size ( ) < <NUM_LIT> ) return ; emitUnrolled ( InsertI ) ; } else { MachineInstr * UpdateInstr = nullptr ; int64_t TotalOffset ; if ( IsLast ) { if ( InsertI != MBB -> end ( ) && canMergeRegUpdate ( InsertI , FrameReg , FrameRegOffset . getBytes ( ) + Size , & TotalOffset ) ) { UpdateInstr = & * InsertI ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * UpdateInstr ) ; } } if ( ! UpdateInstr && TagStores . size ( ) < <NUM_LIT> ) return ; if ( UpdateInstr ) { FrameRegUpdate = TotalOffset ; FrameRegUpdateFlags = UpdateInstr -> getFlags ( ) ; } emitLoop ( InsertI


<s> InstructionCost <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { assert ( TLI -> InstructionOpcodeToISD (


<s> if ( std :: find ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) , NextBB ) == MBB -> succ_end ( ) ) return false ; MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT>


<s> static SDValue lowerV16I32Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue ShufPS = lowerShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ; return DAG . getBitcast ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR64 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand (


<s> Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices


<s> sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_2 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_3 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , IOR , t_2 , t_3 , t_2 , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_2 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case E_V8QImode : sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT )


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val , ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode ( ) ) { case <STR_LIT> : return Mask ; case <STR_LIT>


<s> SpecialCallingConvType getSpecialCallingConv (


<s> unsigned char * OldByte = ( unsigned char * ) Old ; * OldByte ++ = <NUM_LIT> ; unsigned * OldWord = ( unsigned * ) OldByte ; unsigned NewAddr = ( intptr_t ) New ; unsigned OldAddr = ( intptr_t ) OldWord ; * OldWord = NewAddr -


<s> bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg =


<s> unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; poly_uint64 vector_bits = ( vec_flags & ( VEC_PARTIAL | VEC_SVE_PRED ) ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; return vector_element_size ( vector_bits , GET_MODE_NUNITS (


<s> void printxmmwordmem ( const MCInst * MI ,


<s> } else { auto C_P2HalfMemSize = MIRBuilder . buildConstant ( s32 , P2HalfMemSize ) ; auto Addr = MIRBuilder . buildPtrAdd ( PtrTy , BaseAddr , C_P2HalfMemSize ) ; auto Load_P2Half = MIRBuilder . buildLoad ( s32 , BaseAddr , * P2HalfMemOp ) ; auto Load_Rem = MIRBuilder . buildLoad ( s32 , Addr , * RemMemOp ) ; if ( Size == <NUM_LIT> ) MIRBuilder . buildMerge ( Val , { Load_P2Half , Load_Rem } ) ; else { auto Merge = MIRBuilder . buildMerge ( s64 , { Load_P2Half , Load_Rem } ) ; MIRBuilder . buildTrunc ( Val , Merge ) ; } } } MI . eraseFromParent ( ) ; break ; } case G_UITOFP : { Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; if ( SrcTy != s32 ) return false ; if ( DstTy != s32 && DstTy != s64 ) return false ; auto C_HiMask = MIRBuilder . buildConstant ( s32 , UINT32_C ( <NUM_LIT> ) ) ; auto Bitcast = MIRBuilder . buildMerge ( s64 , { Src , C_HiMask . getReg ( <NUM_LIT> ) } ) ; MachineInstrBuilder TwoP52FP = MIRBuilder . buildFConstant ( s64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; if ( DstTy == s64 ) MIRBuilder . buildFSub (


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo


<s> static SDValue PerformADDVecReduce ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMVEIntegerOps ( ) || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; auto MakeVecReduce = [ & ] ( unsigned Opcode , unsigned OpcodeA , SDValue NA , SDValue NB ) { if ( NB -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VecRed = NB -> getOperand ( <NUM_LIT> ) ; if ( VecRed -> getOpcode ( ) != Opcode || VecRed . getResNo ( ) != <NUM_LIT> || NB -> getOperand ( <NUM_LIT> ) != SDValue ( VecRed . getNode ( ) , <NUM_LIT> ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Lo = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NA

, DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> const MCExpr * Length ; bool HasLength = ( MemKind == BDLMem ) ? true : false ; bool HasVectorIndex = ( MemKind == BDVMem ) ? true : false ; if ( parseAddress ( HaveReg1 , Reg1 , HaveReg2 , Reg2 , Disp , Length , HasLength , HasVectorIndex ) ) return MatchOperand_ParseFail ; const unsigned * Regs ; switch ( RegKind ) { case GR32Reg : Regs = <STR_LIT> ; break ; case GR64Reg : Regs = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( MemKind ) { case BDMem : if ( HaveReg1 ) { if ( parseAddressRegister ( Reg1 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg1 . Num ] ; } if ( HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDXMem : if ( HaveReg1 ) { if ( parseAddressRegister ( Reg1 ) ) return MatchOperand_ParseFail ; if ( HaveReg2 ) Index = Regs [ Reg1 . Num ] ; else Base = Regs [ Reg1 . Num ] ; } if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; case BDLMem : if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( HaveReg1 && HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDRMem : if ( ! HaveReg1 || Reg1 . Group != RegGR ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LengthReg = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; case BDVMem : if ( ! HaveReg1 || Reg1 . Group != RegV ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc


<s> tree aarch64_general_builtin_decl ( unsigned code , bool ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ]


<s> if ( std :: error_code EC = SymAddr . getError ( ) ) report_fatal_error ( EC . message ( ) ) ; uint64_t SymSize = SymI -> getSize ( ) ; int64_t Addend = * ELFRelocationRef ( Rel ) . getAddend ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( SymName ) ; if ( ! Sym -> isVariable ( ) ) Sym -> setVariableValue ( MCConstantExpr :: create ( * SymAddr , Ctx ) ) ; const MCExpr * Expr = nullptr ; bool hasAddend = false ; switch ( RelType ) { case R_<ISA_LIT>_64_NONE : case R_<ISA_LIT>_64_COPY : break ; case R_<ISA_LIT>_64_64 : case R_<ISA_LIT>_64_16 : case R_<ISA_LIT>_64_8 : case R_<ISA_LIT>_64_32 : case R_<ISA_LIT>_64_32S : case R_<ISA_LIT>_64_PC32 : case R_<ISA_LIT>_64_PC16 : case R_<ISA_LIT>_64_PC8 : case R_<ISA_LIT>_64_PC64 : hasAddend = true ; Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOT32


<s> unsigned <ISA_LIT>InstrInfo :: getInstBundleLength ( const MachineInstr & MI ) const { unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end


<s> static void EmitREST ( const llvm :: MCSubtargetInfo & STI , const MCInst & Inst , unsigned Reg32 , bool IsMem , MCStreamer & Out ) { unsigned Reg64 = get<ISA_LIT>SubSuperRegister_ ( Reg32 , <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; if ( ! IsMem ) { EmitMoveRegReg ( STI , false , Reg32 , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Out ) ; } else { unsigned IndexOpPosition ; MCInst SandboxedInst = Inst ; if ( SandboxMemoryRef ( & SandboxedInst , & IndexOpPosition


<s> if ( code == SMAX || code == SMIN ) c = GE ; else c = GEU ; if ( code == SMAX || code == UMAX ) target = emit_conditional_move ( dest , c , op0 , op1 , mode , op0 , op1 , mode , <NUM_LIT> ) ; else target = emit_conditional_move ( dest , c , op0 , op1 , mode , op1 , op0 , mode , <NUM_LIT> ) ; gcc_assert ( target


<s> SDValue <ISA_LIT>TargetLowering :: GetF64FormalArgument ( CCValAssign & VA , CCValAssign & NextVA , SDValue & Root , SelectionDAG & DAG , DebugLoc dl ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = <STR_LIT> ; else RC = <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA .


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; if ( hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ,


<s> bool <ISA_LIT>PostLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { const auto * LI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( )


<s> unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } } return DestReg


<s> assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; for ( MachineInstr & MI : make_range ( VCMP -> getIterator ( ) , MI -> getIterator ( ) ) ) { MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; } VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; } finalizeBundle ( Block , MachineBasicBlock :: instr_iterator ( MIBuilder . getInstr ( ) ) , MBIter ) ; Modified = true ; } for ( MachineInstr * DeadMI : DeadInstructions ) { if ( DeadMI -> isInsideBundle ( ) ) DeadMI -> eraseFromBundle ( ) ; else DeadMI -> eraseFromParent ( ) ; } return


<s> if ( ! getBranchInfo ( * I ) . hasMBBTarget ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> bool isBrTarget ( ) { return isBrImm ( ) || isToken (


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( getThe<ISA_LIT>64elTarget ( ) ) ; PassRegistry * PR = PassRegistry :: getPassRegistry (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) { switch ( UserOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FPVector ( SDValue Op , SelectionDAG & DAG , const SDLoc & dl ) const { unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool SignedConv = Opc == <STR_LIT> ; bool FourEltRes = Op . getValueType ( ) == <STR_LIT> ; SDValue Wide = widenVec ( DAG , Op . getOperand ( <NUM_LIT> ) , dl ) ; EVT WideVT = Wide . getValueType ( ) ; unsigned WideNumElts = WideVT . getVectorNumElements ( ) ; MVT IntermediateVT = FourEltRes ? <STR_LIT> : <STR_LIT> ; SmallVector < int , <NUM_LIT> > ShuffV ; for ( unsigned i = <NUM_LIT> ; i < WideNumElts ; ++ i ) ShuffV . push_back ( i + WideNumElts ) ; int Stride = FourEltRes ? WideNumElts / <NUM_LIT> : WideNumElts / <NUM_LIT> ; int SaveElts = FourEltRes ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . isLittleEndian ( ) ) for ( int i = <NUM_LIT> ; i < SaveElts ; i ++ ) ShuffV [ i * Stride ] = i ; else for ( int i = <NUM_LIT> ; i <= SaveElts ; i ++ ) ShuffV [ i * Stride - <NUM_LIT> ] = i - <NUM_LIT> ; SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; SDValue Arrange = DAG . getVectorShuffle ( WideVT , dl , Wide , ShuffleSrc2 , ShuffV ) ; SDValue Extend ; if ( SignedConv ) { Arrange = DAG . getBitcast ( IntermediateVT , Arrange ) ; EVT ExtVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Subtarget . hasP9Altivec ( ) ) ExtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WideVT . getVectorElementType ( ) , IntermediateVT . getVectorNumElements ( ) ) ; Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT , Arrange , DAG . getValueType ( ExtVT ) ) ; } else Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT ,


<s> return TokError ( Str ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; assert ( PRCTX_Op2 && <STR_LIT> ) ; createSysAlias ( PRCTX -> Encoding << <NUM_LIT> | PRCTX_Op2 , Operands , S ) ; } Lex ( ) ; bool ExpectRegister = ( Op . lower ( ) . find ( <STR_LIT> ) == StringRef :: npos ) ; bool HasRegister = false ; if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) || parseRegister ( Operands )


<s> void or1k_expand_compare ( rtx * operands ) { rtx sr_f = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; if ( ! TARGET_SFIMM ) XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) = force_reg ( SImode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; PUT_MODE ( operands [ <NUM_LIT>


<s> Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getElementType ( ) , BaseAddr , VecTy -> getNumElements ( ) * Factor ) ; CallInst * VldN = createLoadIntrinsic ( BaseAddr ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ;


<s> return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b )


<s> vrev64_p16 ( poly16x4_t a ) { return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> , <NUM_LIT> ,


<s> if ( TARGET_INTERWORK ) arm_cpp_interwork = <NUM_LIT> ; if ( arm_arch5t ) target_flags &= ~ MASK_INTERWORK ; if ( TARGET_IWMMXT && ! ARM_DOUBLEWORD_ALIGN ) error ( <STR_LIT> ) ; if ( TARGET_IWMMXT_ABI && ! TARGET_IWMMXT ) error ( <STR_LIT> ) ; if ( TARGET_INTERWORK && ! TARGET_BPABI && ! bitmap_bit_p ( arm_active_target . isa , isa_bit_thumb ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; target_flags &= ~ MASK_INTERWORK ; } if ( TARGET_SOFT_FLOAT ) arm_fpu_attr = FPU_NONE ; else arm_fpu_attr = FPU_VFP ; if ( TARGET_AAPCS_BASED ) { if ( TARGET_CALLER_INTERWORKING ) error ( <STR_LIT> ) ; else if ( TARGET_CALLEE_INTERWORKING ) error ( <STR_LIT> ) ; } if ( ! arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE ) sorry ( <STR_LIT> ) ; if ( use_cmse && ! arm_arch_cmse ) error ( <STR_LIT> ) ; if ( use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM ) error ( <STR_LIT> ) ; if ( TARGET_AAPCS_BASED ) { if ( arm_abi == ARM_ABI_IWMMXT ) arm_pcs_default =


<s> return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr :: VK_PLT : assert ( Type == RT32_32 ) ; return ELF :: R_386_PLT32 ; case MCSymbolRefExpr :: VK_INDNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF


<s> assert ( isCRBitMask ( ) && <STR_LIT>


<s> return getSTI ( ) . getFeatureBits (


<s> bool rs6000_function_pcrel_p ( struct function * fn ) { if ( DEFAULT_ABI != ABI_ELFv2


<s> bool <ISA_LIT>AsmParser :: parseSetPushDirective ( ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( AssemblerOptions . back ( ) . get ( ) ) ) ; getTargetStreamer ( ) .


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo


<s> if ( LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) B = LHS . getOperand ( <NUM_LIT> ) ; cast < ShuffleVectorSDNode > ( LHS . getNode ( ) ) -> getMask ( LMask ) ; } else { if ( LHS . getOpcode ( ) != <STR_LIT> ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( N ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( RMask ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) { unsigned Idx = RMask [ i ] ; if ( Idx < N ) RMask [ i ] += N ; else if ( Idx < <NUM_LIT> * N ) RMask [ i ] -= N ; } for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) { unsigned LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx >= <NUM_LIT> * N || RIdx >= <NUM_LIT> * N || ( ! A . getNode ( ) && ( LIdx < N || RIdx < N ) ) || ( ! B . getNode ( ) && ( LIdx >= N || RIdx >= N ) ) ) continue ; if ( ! ( LIdx == <NUM_LIT> * i && RIdx == <NUM_LIT> * i + <NUM_LIT> ) && ! ( isCommutative && LIdx == <NUM_LIT> * i + <NUM_LIT> && RIdx == <NUM_LIT> * i ) ) return false ; } LHS = A . getNode ( ) ? A : B ; RHS = B . getNode ( ) ?


<s> static int ia64_reloc_rw_mask ( void ) { return flag_pic ? <NUM_LIT>


<s> return ( __m128 ) __builtin_ia32_movlhps ( ( __v4sf ) __A ,


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( MachineRegisterInfo :: reg_iterator ri = MRI . reg_begin ( <STR_LIT> ) , re = MRI . reg_end ( ) ; ri != re ; ++ ri


<s> static std :: pair < unsigned , const TargetRegisterClass * > parseRegisterNumber ( StringRef Constraint , const TargetRegisterClass * RC , const unsigned * Map , unsigned Size ) { assert ( * ( Constraint . end ( ) - <NUM_LIT> ) == '}'


<s> res . as_short [ <NUM_LIT> ] = m1 . as_short [ <NUM_LIT> ] ; res . as_short [ <NUM_LIT> ] = m2 . as_short [ <NUM_LIT> ] ; return ( __m64 ) res . as_m64


<s> void <ISA_LIT>MCInstLower :: lowerLongBranchLUi ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( LowerOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind ; unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; switch ( TargetFlags ) { case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: MEK_HIGHEST ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: MEK_HIGHER ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: MEK_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: MEK_LO ; break ; default : report_fatal_error ( <STR_LIT> ) ; } if ( MI -> getNumOperands ( ) == <NUM_LIT> ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) -> getSymbol ( ) , * Ctx ) ; const <ISA_LIT>MCExpr * <ISA_LIT>Expr = <ISA_LIT>MCExpr :: create ( Kind ,


<s> } bool PreferAVX512 = ( ( Subtarget . hasAVX512 ( ) && InSVT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && InSVT == <STR_LIT> ) ) && ( InVT . getSizeInBits ( ) > <NUM_LIT> ) && ( Subtarget . hasVLX ( ) || InVT . getSizeInBits ( ) > <NUM_LIT> ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! PreferAVX512 && VT . getSizeInBits ( ) >= <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; assert ( Mid && <STR_LIT> ) ; SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; assert ( V && <STR_LIT> ) ; return V ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( InVT ) && InVT . isVector ( ) && SVT != <STR_LIT> && Subtarget . hasAVX512 ( ) && ( InSVT != <STR_LIT> || Subtarget . hasBWI ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) ) { unsigned TruncOpc = <NUM_LIT> ; SDValue SatVal ; if ( auto SSatVal = detectSSatPattern ( In , VT ) ) { SatVal = SSatVal ; TruncOpc =


<s> unsigned <ISA_LIT>VectorTargetTransformInfo :: getShuffleCost ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { if ( Kind != Reverse ) return VectorTargetTransformImpl :: getShuffleCost ( Kind , Tp , Index ,


<s> if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( type == vector_pair_type_node ) return <STR_LIT> ; if ( type == vector_quad_type_node


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this )

, FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> StringRef getPassName ( ) const override { return


<s> return __aarch64_vdupq_lane_f32 ( __a ,


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmPrinter ( ) { TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>AsmPrinterPass ) ; TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>AsmPrinterPass ) ; TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>64LETarget ( ) , create<ISA_LIT>AsmPrinterPass


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool needsFrameMoves = MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { assert ( ! HasFP && <STR_LIT> ) ; AFI -> setLocalStackSize ( NumBytes ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; if ( NumBytes && ! canUseRedZone ( MF ) ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( FrameLabel , - NumBytes ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } else if ( NumBytes ) { ++ NumRedZoneFunctions ; } return ; } int FPOffset = <NUM_LIT> ; if ( HasFP ) { assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> && ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; FPOffset = - ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( FPOffset >= <NUM_LIT> && <STR_LIT> ) ; } while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT>


<s> const Triple & T = ST . getTargetTriple ( ) ; std :: string Ret = <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) || ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! ST . is<ISA_LIT>64 ( ) && ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) && ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits


<s> } if ( Features [ <STR_LIT> ] ) { assert ( Features [ <STR_LIT> ] ) ; return <NUM_LIT> ; } if ( Features [ <STR_LIT> ] ) { assert ( Features [ <STR_LIT> ] ) ; return <NUM_LIT> ; } assert ( ! Features [ <STR_LIT> ] ) ; return None


<s> c = vec_adds ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> , true


<s> return :: getBranchTargetOpValue ( MI , OpIdx


<s> Update = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> (


<s> unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; } return


<s> <STR_LIT> getExtendForAtomicOps ( ) const override { return <STR_LIT>


<s> for ( SDNode :: use_iterator UI = N -> use_begin ( ) , E = N -> use_end ( ) ; UI != E ; ++ UI ) { if ( MemSDNode * Memop = dyn_cast < MemSDNode > ( * UI ) ) { if ( Memop -> getMemoryVT ( ) == <STR_LIT> ) { Base = N . getOperand


<s> if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return true


<s> return ( <NUM_LIT> | ( feature_deps :: IDENT ( ) . enable & mask

? AARCH64_FL_ ## IDENT : <NUM_LIT> ) ) ;


<s> NegatibleCost N2Cost = NegatibleCost :: Expensive ; SDValue NegN2 = getNegatedExpression ( N2 , DAG , LegalOps , OptForSize , N2Cost , Depth + <NUM_LIT> ) ; if ( ! NegN2 ) return SDValue ( ) ; if ( Flags . hasNoSignedZeros ( ) || Options . NoSignedZerosFPMath ) { NegatibleCost N0Cost = NegatibleCost :: Expensive ; SDValue NegN0 = getNegatedExpression ( N0 , DAG , LegalOps , OptForSize , N0Cost , Depth + <NUM_LIT> ) ; NegatibleCost N1Cost = NegatibleCost :: Expensive ; SDValue NegN1 = getNegatedExpression ( N1 , DAG , LegalOps , OptForSize , N1Cost , Depth + <NUM_LIT> ) ; if ( NegN0 && N0Cost <= N1Cost ) { Cost = std :: min ( N0Cost , N2Cost ) ; return DAG . getNode ( Opc , Loc , VT , NegN0 , N1 , NegN2 , Flags ) ; } else if ( NegN1 ) { Cost = std :: min ( N1Cost , N2Cost ) ; return DAG . getNode ( Opc , Loc , VT , N0 , NegN1


<s> if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugValue ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; std :: sort ( Candidates . begin ( ) , Candidates . end ( ) , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerVectorShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> JTI -> addJumpTableBaseAddr ( JTIndex , JTBase ) ; DOUT << <STR_LIT> << JTIndex << <STR_LIT> << ( void * ) JTBase << '\n' ; const std :: vector < MachineBasicBlock * > & MBBs = ( * MJTEs ) [ JTIndex ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = MBBs . size ( ) ; i != e ; ++ i ) { if ( IsPIC ) emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> , JTBase ) ; else emitMachineBasicBlock ( MBBs [ i ]


<s> const MCExpr * <ISA_LIT>ELFTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_DTPOFF ,


<s> if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget )


<s> static DecodeStatus DecodeIntRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = IntRegDecoderTable [ RegNo


<s> static inline const MachineInstrBuilder & addDirectMem ( const MachineInstrBuilder & MIB ,


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } SDValue Ops [ ] = {


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T ) { HasScatteredSymbols = true


<s> void <ISA_LIT>InstrFMA3Info :: initRMGroup ( const uint16_t * RegOpcodes , const uint16_t * MemOpcodes , unsigned Attr ) { <ISA_LIT>InstrFMA3Group * G = new <ISA_LIT>InstrFMA3Group ( RegOpcodes , MemOpcodes , Attr ) ; assert ( ( ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] ) && <STR_LIT> ) ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ MemOpcodes [ <NUM_LIT>


<s> if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) -


<s> inline vector unsigned int vec_vadduws ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vadduws ( ( vector signed int ) a1 , (


<s> const uint64_t Win64MaxSEHOffset = <NUM_LIT> ; uint64_t SEHFrameOffset = std :: min ( SPAdjust


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Rm = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ; return getRelocType32 ( Modifier , getType32


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget

( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue ( ) ; return ( ( Value & ~ <NUM_LIT>


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg (


<s> inline void vec_stl ( vector unsigned char a1 , int a2 ,


<s> targetm . sched . first_cycle_multipass_init = core2i7_first_cycle_multipass_init ; targetm . sched . first_cycle_multipass_begin = core2i7_first_cycle_multipass_begin ; targetm . sched . first_cycle_multipass_issue = core2i7_first_cycle_multipass_issue ; targetm . sched . first_cycle_multipass_backtrack = core2i7_first_cycle_multipass_backtrack ; targetm . sched . first_cycle_multipass_end


<s> return <STR_LIT> ; case CmpInst :: ICMP_EQ : case CmpInst :: FCMP_OEQ : return <STR_LIT> ; case CmpInst :: ICMP_SGT : case CmpInst :: FCMP_OGT : return <STR_LIT> ; case CmpInst :: ICMP_SGE : case CmpInst :: FCMP_OGE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : case CmpInst :: FCMP_UGT : return <STR_LIT> ; case CmpInst :: FCMP_OLT : return <STR_LIT> ; case CmpInst :: ICMP_ULE : case CmpInst ::


<s> rtx body = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx and_base = XEXP (


<s> if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> ,


<s> TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter (


<s> case E_DFmode : case E_XFmode : case E_QImode : case E_HImode : case E_SImode : simple : tmp = ix86_expand_compare ( code , op0 , op1 ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; return ; case E_DImode : if ( TARGET_64BIT ) goto simple ; case E_TImode : if ( ( code == EQ || code == NE ) && ! optimize_insn_for_size_p ( ) ) goto simple ; { rtx lo [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ; rtx_code_label * label2 ; enum rtx_code code1 , code2 , code3 ; machine_mode submode ; if ( CONSTANT_P ( op0 ) && ! CONSTANT_P ( op1 ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } split_double_mode ( mode , & op0 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; split_double_mode ( mode , & op1 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; submode = mode == DImode ? SImode : DImode ; if ( CONST_INT_P ( hi [ <NUM_LIT> ] ) ) switch ( code ) { case LT : case LTU : case GE : case GEU : if ( lo [ <NUM_LIT> ] == const0_rtx ) { ix86_expand_branch ( code , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; return ; } break ; case LE : case LEU : case GT : case GTU : if ( lo [ <NUM_LIT> ] == constm1_rtx ) { ix86_expand_branch ( code , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; return ; } break ; default : break ; } switch ( code ) { case LE : case LEU : case GT : case GTU : std :: swap ( lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ; std :: swap ( hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ; code = swap_condition ( code )


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; return lower<ISA_LIT>FPLogicOp ( N ,


<s> EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , DL , ValTy , N -> getOperand ( <NUM_LIT> ) , Add . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return


<s> if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> ) return CS ; } } return


<s> assert ( lsb <= msb && <STR_LIT> ) ; for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ; return ~


<s> HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS =


<s> else Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler ::


<s> if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( getPointerWidth ( ) , Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; if ( ! getLexer ( ) . is ( AsmToken :: LBrac ) ) return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ; Parser . Lex ( ) ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( SM . getSym ( )


<s> EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI . CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; return DAG . getFrameIndex ( FI ,


<s> static void mips_maybe_swap_ready ( rtx_insn * * ready , int pos1 , int pos2 , int limit ) { if ( pos1 < pos2 && INSN_PRIORITY ( ready [ pos1 ] ) + limit >= INSN_PRIORITY ( ready [ pos2 ] ) ) { rtx_insn * temp


<s> if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue


<s> _Unwind_Reason_Code __gnu_Unwind_Resume ( _Unwind_Control_Block * ucbp , phase2_vrs * entry_vrs ) { _Unwind_Reason_Code pr_result ; entry_vrs -> core . r [ R_PC ] = UCB_SAVED_CALLSITE_ADDR ( ucbp ) ; if ( UCB_FORCED_STOP_FN (


<s> return ( int32x4_t ) __builtin_aarch64_ssri_nv4si ( __a ,


<s> gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ; return XVECLEN ( parallel_rtx


<s> return ( __m128i ) vec_max ( ( __v4si )


<s> if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return combineAddOrSubToADCOrSBB ( N


<s> if ( align & <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) :

DecodeVSTInstruction ( Inst , Insn , Address , Decoder ) ;


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Subtarget . hasMSA ( ) || ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; if ( Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) && SplatBitSize <= <NUM_LIT> ) { if ( SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> ) return SDValue ( ) ; if ( ResTy . isInteger ( ) && ! HasAnyUndefs ) return Op ; EVT ViaVecTy ; switch ( SplatBitSize ) { default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue (


<s> if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; LLVM_FALLTHROUGH ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB


<s> regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs

[ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return <NUM_LIT> ;


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( <STR_LIT> . hasSubClassEq ( RC ) ) return


<s> return __builtin_loongson_psraw_s ( s , amount


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler ::


<s> static inline unsigned getAccessSize (


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += RegInfo ->


<s> const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const Function & CF = OF . Candidates . front ( ) . getMF ( ) -> getFunction ( ) ; bool ShouldSignReturnAddr = false ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { StringRef Scope = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) ShouldSignReturnAddr = true ; else if ( Scope . equals ( <STR_LIT> ) && ! IsLeafFunction ) ShouldSignReturnAddr = true ; } bool ShouldSignReturnAddrWithAKey = true ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { const StringRef Key = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT>


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return Error ( L , <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: Create ( Sym , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setManipulatesSP ( true ) ; return DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc

( Op ) , <STR_LIT> , Op . getValueType ( ) ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> if ( parseRegister ( Operands ) == MatchOperand_Success || parseImmediate ( Operands ) == MatchOperand_Success ) return false ; Error ( getLoc ( ) , <STR_LIT> ) ; return true


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText (

<STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ;


<s> for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v64s8 , v32s16 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_MUL , v32s16 } , LegacyLegalizeActions :: Legal ) ; if ( ! Subtarget . hasVLX ( ) ) return ; const LLT v8s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto Ty : { v8s16 , v16s16 } ) LegacyInfo . setAction

( { G_MUL , Ty } , LegacyLegalizeActions :: Legal ) ;


<s> case Expression : return true ; case Immediate : case ContextImmediate : return isInt < <NUM_LIT> > ( getImmS16Context (


<s> static MachineBasicBlock * EmitXBegin ( MachineInstr * MI , MachineBasicBlock * MBB , const TargetInstrInfo * TII ) { DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = MBB ; ++ I ; MachineBasicBlock * thisMBB = MBB ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I ,


<s> static void translateRegister ( MCInst & mcInst , Reg reg ) { uint8_t llvmRegnums [ ] = { ALL_REGS <NUM_LIT> } ; uint8_t llvmRegnum = llvmRegnums [ reg ] ; mcInst . addOperand ( MCOperand :: createReg


<s> if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; if ( SrcElVT . isFloatingPoint ( ) ) if ( ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) ) return SDValue ( ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> ) { uint64_t MaxIndex = <NUM_LIT> ; uint64_t SrcElSize = SrcElVT . getStoreSize ( ) . getKnownMinSize ( ) ; ConstantSDNode * OffsetConst = dyn_cast < ConstantSDNode > ( Offset . getNode ( ) ) ; if ( nullptr == OffsetConst || OffsetConst -> getZExtValue ( ) > MaxIndex * SrcElSize || OffsetConst -> getZExtValue ( ) % SrcElSize ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Offset . getValueType (


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR ) ; initialize<ISA_LIT>ExpandISELPass ( PR ) ; initialize<ISA_LIT>PreEmitPeepholePass ( PR ) ; initialize<ISA_LIT>TLSDynamicCallPass (


<s> if ( OpI . getOpcode ( ) != <STR_LIT> || OpI . getOperand ( <NUM_LIT> ) != Op0 || ! isa < ConstantSDNode > ( OpI . getOperand ( <NUM_LIT> ) ) || OpI . getConstantOperandVal ( <NUM_LIT> ) != I * N ) return SDValue ( ) ; } SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op0 , DAG . getConstant ( N , DL


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && ! cast < LoadSDNode > ( N0 ) -> isVolatile ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue (


<s> } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( <NUM_LIT> )


<s> bool need_address_override ; uint64_t AdSize = TSFlags & <STR_LIT> ; if ( ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) ) { need_address_override = true ; } else if ( MemoryOperand < <NUM_LIT> ) { need_address_override = false ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is16BitMemOperand ( MI , MemoryOperand , STI ) ) ; need_address_override = is32BitMemOperand ( MI , MemoryOperand ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; need_address_override = is16BitMemOperand ( MI , MemoryOperand , STI ) ; } else { assert ( STI . hasFeature ( <STR_LIT> ) ) ; assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; need_address_override = ! is16BitMemOperand ( MI , MemoryOperand , STI ) ; } if ( need_address_override ) emitByte ( <NUM_LIT> , CurByte , OS ) ; uint64_t Encoding = TSFlags & <STR_LIT> ; if ( Encoding == <NUM_LIT> ) Rex = emitOpcodePrefix ( TSFlags , CurByte , MemoryOperand , MI , Desc , STI , OS ) ; else emitVEXOpcodePrefix ( TSFlags , CurByte , MemoryOperand , MI , Desc , OS ) ; uint64_t Form = TSFlags & <STR_LIT> ; switch ( Form ) { default : break ; case <STR_LIT> :


<s> case E_SImode : gen_neg = gen_negsi2 ; break ; case E_DImode : gen_neg = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } e1 = gen_reg_rtx ( inmode ) ; e2 = gen_reg_rtx ( inmode ) ; res = gen_reg_rtx ( outmode ) ; half = const_double_from_real_value ( dconsthalf , inmode ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , op1 ) , UNSPEC_FXAM ) ) ) ; emit_insn ( gen_abs ( e1 , op1 ) ) ; half = force_reg ( inmode , half ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( inmode , e1 , half ) ) ) ; if ( inmode != XFmode ) { tmp1 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( tmp1 , gen_rtx_FLOAT_EXTEND ( XFmode , e2 ) ) ) ; } else tmp1 = e2 ; switch ( outmode ) { case E_SFmode : case E_DFmode : { rtx tmp0 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_frndintxf2_floor ( tmp0 , tmp1 ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( <NUM_LIT> , tmp0 ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; case E_XFmode : emit_insn ( gen_frndintxf2_floor ( res , tmp1 ) ) ; break ; case E_HImode : emit_insn ( gen_lfloorxfhi2 ( res , tmp1 ) ) ; break ; case E_SImode : emit_insn ( gen_lfloorxfsi2 ( res , tmp1 ) ) ; break ; case E_DImode : emit_insn ( gen_lfloorxfdi2 ( res , tmp1 ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_neg ( res , res ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = <NUM_LIT> ; emit_move_insn ( op0 , res


<s> bool <ISA_LIT>DAGToDAGISel :: selectADDRzri ( SDValue Addr , SDValue & Base , SDValue & Index , SDValue & Offset ) { return


<s> RegDefsUses RegDU ( TM ) ; MemDefsUses MemDU ( MBB . getParent ( ) -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Filler ) ) { MBB . splice ( llvm :: next ( Slot ) , & MBB , llvm :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , llvm :: next ( llvm :: next ( Slot ) ) ) ; ++ UsefulSlots ; return true ; } return


<s> O << <STR_LIT> << * RawSym << '\n' ; O << <STR_LIT> ; O << <STR_LIT> << * AnonSymbol << '\n' ; O << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; OutStreamer . SwitchSection ( LSPSection ) ; O << * LazyPtr << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; } O << '\n' ; return ; } const MCSection * StubSection = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> )