<s> Offset -= <NUM_LIT> ; } if ( hasFP ( MF ) ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; } if ( TRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; SavedRegs . set ( TRI ->


<s> switch ( ArithOp . getOpcode ( ) ) { case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( Opcode ==


<s> Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr =


<s> bool <ISA_LIT>AsmParser :: parseSet<ISA_LIT>16Directive ( ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo <


<s> if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ; return S


<s> static __inline vec_double2 spu_mul ( vec_double2 a , vec_double2 b ) { return ( ( vec_double2 ) ( si_dfm ( ( qword ) (


<s> assert ( isPowerOf2_32 ( NumSplits ) && <STR_LIT> ) ; unsigned Stages = Log2_32 ( NumSplits ) ; for ( unsigned s = Stages ; s > <NUM_LIT> ; -- s ) { unsigned NumConcatElts = Ops [ <NUM_LIT> ] -> getType ( ) -> getVectorNumElements ( ) * <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> << ( s - <NUM_LIT> ) ; ++ i ) { SmallVector < uint32_t , <NUM_LIT> > ConcatMask ( NumConcatElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Ops [ i ] = Builder . CreateShuffleVector ( Ops [ i * <NUM_LIT> ] , Ops [ i * <NUM_LIT> + <NUM_LIT> ] , ConcatMask ) ; } } NumElts = OpTy -> getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { Ops [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , ArrayRef < int > { <NUM_LIT> , <NUM_LIT> } ) ; } else if ( NumElts >= <NUM_LIT> ) { SmallVector < uint32_t , <NUM_LIT> > ConcatMask ( NumElts ) ; unsigned SubElts = Ops [ <NUM_LIT> ] -> getType ( ) -> getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != SubElts ; ++ i ) ConcatMask [ i ] = i ; for ( unsigned i = SubElts ; i != NumElts ; ++ i ) ConcatMask [ i ] = ( i % SubElts ) + SubElts ; Value * Zero = Constant :: getNullValue ( Ops [ <NUM_LIT> ] -> getType ( ) ) ; Ops [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Ops [ <NUM_LIT> ] , Zero , ConcatMask ) ; } Add -> replaceUsesOfWith ( Op , Ops [ <NUM_LIT> ] ) ; Add -> setHasNoSignedWrap ( false ) ; Add -> setHasNoUnsignedWrap ( false ) ; return false


<s> if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( VR ) ) MRI . constrainRegClass ( VR , RC ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( VR ) ; InsInstrs . push_back (


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case


<s> Value * <ISA_LIT>IREmitter :: visitVPERM2X128 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp ( )


<s> } unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; } else


<s> void <ISA_LIT>InstPrinter :: printNeonUImm64MaskOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MOUImm8 = MI -> getOperand ( OpNum ) ; assert ( MOUImm8 . isImm ( ) && <STR_LIT> ) ; uint32_t UImm8 = MOUImm8 . getImm ( ) ; uint64_t Mask = <NUM_LIT> ; for ( unsigned ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( UImm8 >> ByteNum ) & <NUM_LIT> ) Mask |= ( uint64_t ) <NUM_LIT> << ( <NUM_LIT> * ByteNum ) ; } O <<


<s> const MCFixupKind FK = Fixup . getKind ( ) ; const unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , FK ) ; const unsigned Type = getRelocType ( Target , FK , IsPCRel ) ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } uint32_t other_half = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : other_half = ( FixedValue >>


<s> EVT VT = <STR_LIT> ; assert ( Op . getOpcode ( ) == unsigned ( BinOp ) && <STR_LIT> ) ; Opnds . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == unsigned ( BinOp ) ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; auto * Idx = dyn_cast < ConstantSDNode > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Idx ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( SrcOpMap . begin ( ) != SrcOpMap . end ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR32Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands , ( int


<s> if ( Offset % Scale != <NUM_LIT> ) return false ; Offset /= Scale


<s> const uint16_t * intArgRegs ( ) const { return IntArgRegs


<s> unsigned Op = Subtarget . useCheriExactEquals ( ) ? ( is64 ? <STR_LIT> : <STR_LIT> ) : ( is64 ? <STR_LIT> : <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( Op ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return BB


<s> SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( *

I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; return


<s> void <ISA_LIT>InstPrinter :: printPSBHintOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned psbhintop = MI -> getOperand ( OpNum )


<s> if ( TREE_CODE ( decl ) == VAR_DECL && ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl )

) || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) ) {


) : default_hidden_stack_protect_fail ( ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler ( STI , T


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL


<s> if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame (


<s> __builtin_neon_vst1_lanev8qi ( ( __builtin_neon_qi * ) __a , ( int8x8_t )


<s> <ISA_LIT>BETargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt

:: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> void <ISA_LIT>AsmPrinter :: NaClAlignIndirectJumpTargets ( MachineFunction & MF ) { if ( MachineJumpTableInfo * JtInfo = MF . getJumpTableInfo ( ) ) { const std :: vector < MachineJumpTableEntry > & JT = JtInfo -> getJumpTables ( ) ; for ( unsigned I = <NUM_LIT> ; I < JT . size ( )


<s> DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; return SDValue ( Res , <NUM_LIT> ) ; } unsigned isDev = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! isDev ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; unsigned Op1 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op2 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op3 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue


<s> Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * AE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { ELFRefKind = AE -> getKind ( ) ; Expr = AE -> getSubExpr ( ) ; } const MCSymbolRefExpr * SE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; if ( SE ) { DarwinRefKind = SE -> getKind ( ) ; return true ; } const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; SE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; if ( ! SE ) return false ; DarwinRefKind = SE -> getKind ( ) ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; if ( ! AddendExpr ) return false ; Addend = AddendExpr -> getValue ( ) ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub ) Addend = - Addend ; return ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID || DarwinRefKind ==


<s> uint32x4x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregoiv4si (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetMsa ( ) { OS << <STR_LIT>


<s> return ( DL . getTypeSizeInBits ( VecTy ) +


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . getObjectOffset ( FrameRegIdx )


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> } else { assert ( MO . isSymbol ( ) && StringRef ( MO . getSymbolName ( ) ) == <STR_LIT> && <STR_LIT> ) ; Model = TLSModel :: GeneralDynamic ; } switch ( Model ) { case TLSModel :: InitialExec : RefFlags |= <ISA_LIT>MCExpr :: VK_GOTTPREL ; break ; case TLSModel :: LocalExec : RefFlags |= <ISA_LIT>MCExpr :: VK_TPREL ; break ; case TLSModel :: LocalDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_DTPREL ; break ; case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; <ISA_LIT>MCExpr :: VariantKind RefKind ; RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( RefFlags ) ; Expr = <ISA_LIT>MCExpr :: Create (


<s> ArrayRef < int > PermMask = SVOp -> getMask ( ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { unsigned SrcElt = PermMask [ i ] < <NUM_LIT> ? <NUM_LIT> : PermMask [ i ] ; for ( unsigned j = <NUM_LIT> ; j != BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ; } SDValue VPermMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ResultMask [ <NUM_LIT> ] , ResultMask . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 ,


<s> } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT>


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) ) return MachineJumpTableInfo


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r


<s> VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned LaneLen = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , LaneLen ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; auto Mask = SVI -> getShuffleMask ( ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { if ( Mask [ i ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Mask [ i ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { if ( Mask [ j * Factor + i ] >= <NUM_LIT> ) { StartMask = Mask [ j * Factor


<s> std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; bool is64BitVector = VT . is64BitVector ( ) ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) SrcReg = V0 ; else { SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = is64BitVector ? SDValue ( createDPairNode ( V0 , V1 ) , <NUM_LIT> ) : SDValue ( createQPairNode ( V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = is64BitVector ? SDValue ( createDTripleNode ( V0 , V1 , V2 ) , <NUM_LIT> ) : SDValue ( createQTripleNode ( V0 , V1 , V2 ) , <NUM_LIT> ) ; else { SDValue V3 = N -> getOperand


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOffsetOfOperator ( SMLoc Start ) { SMLoc OffsetOfLoc = Start ; Parser . Lex ( ) ; Start = Parser . getTok ( ) . getLoc ( ) ; assert ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) &&


<s> int is_called_in_ARM_mode ( tree func ) { gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; if ( TARGET_CALLEE_INTERWORKING && TREE_PUBLIC ( func ) ) return TRUE ; return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) != NULL_TREE ; return


<s> const AsmToken Tok2 = Parser . getTok ( ) ; SMLoc E ; const MCExpr * EVal ; if ( ! Tok2 . is ( AsmToken :: Integer ) || getParser ( ) . parseExpression ( EVal , E ) ) { getLexer ( ) . UnLex ( Tok1 ) ; return MatchOperand_NoMatch ; } const AsmToken Tok3 = Parser . getTok ( ) ; if ( ! Tok3 . is ( AsmToken :: RParen ) ) { getLexer ( ) . UnLex ( Tok2 ) ; getLexer ( ) . UnLex ( Tok1 ) ; return MatchOperand_NoMatch ; } Parser . Lex ( ) ; const AsmToken & Tok4 = Parser . getTok ( ) ; StringRef Suffix = Tok4 . getString ( ) ; if ( Suffix != <STR_LIT> && Suffix != <STR_LIT> ) { getLexer ( ) . UnLex


<s> static bool important_for_bundling_p ( rtx_insn * insn ) { return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) != ITANIUM_CLASS_IGNORE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn


<s> if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; auto AC = getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( * L -> getHeader ( ) -> getParent ( ) ) ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * TTI , EphValues ) ; if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { MadeChange |= convertToCTRLoop ( * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } if ( MadeChange ) return MadeChange ; int Limit = CTRLoopLimit ; if ( Limit >= <NUM_LIT> ) { if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TM -> is<ISA_LIT>64 ( )


<s> NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; computeBlockSize ( OrigBB ) ; computeBlockSize ( NewBB ) ; adjustBBOffsetsAfter ( OrigBB


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI


<s>
if
(
Subtarget
.
isTargetMachO
(
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
ExtraCSSpill
=
true
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
int
Reg
=
SavedRegs
.
find_first
(
)
;
Reg
!=
<NUM_LIT>
;
Reg
=
SavedRegs
.
find_next
(
Reg
)
)
dbgs
(
)
<<
' '
<<
PrintReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
bool
CanEliminateFrame
=
NumRegsSpilled
==
<NUM_LIT>
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
MFI
->
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
NumRegsSpilled
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
&&
!
ExtraCSSpill
)
{
if
(
UnspilledCSGPR
!=
<STR_LIT>
)
{
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
PrintReg
(
UnspilledCSGPR
,
RegInfo
)


<s> for ( int M : SVN -> getMask ( ) ) Mask . push_back ( M ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> if ( ResVT . is256BitVector ( ) ) return Concat128BitVectors ( V1 , V2 , ResVT , NumElems , DAG , dl ) ; if ( Op . getNumOperands ( ) == <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getScalarType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue V3 = Op . getOperand ( <NUM_LIT> ) ; SDValue V4 = Op . getOperand ( <NUM_LIT> ) ; return Concat256BitVectors ( Concat128BitVectors ( V1 , V2 , HalfVT , NumElems / <NUM_LIT> , DAG , dl ) , Concat128BitVectors ( V3 , V4 , HalfVT , NumElems /

<NUM_LIT> , DAG , dl ) , ResVT , NumElems , DAG , dl ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return &


<s> if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> , <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; if ( ! Flags . hasNoSignedZeros ( ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; Cost = ( NegA || NegB || NegC ) ? NegatibleCost :: Cheaper : NegatibleCost :: Neutral ; for ( int i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case <STR_LIT> : if ( SDValue NegOp0 = getNegatedExpression ( Op . getOperand ( <NUM_LIT> ) , DAG , LegalOperations , ForCodeSize , Cost , Depth + <NUM_LIT> ) ) return DAG . getNode ( Opc , SDLoc ( Op ) , VT , NegOp0 ) ; break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass


<s> rtx pat = PATTERN ( insn ) ; if ( get_attr_type ( insn ) == TYPE_FLOAD && GET_CODE ( pat ) == SET && ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) == SFmode || GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) == DFmode ) && MEM_P ( XEXP ( pat , <NUM_LIT> ) ) ) { rtx addr = XEXP ( XEXP ( pat , <NUM_LIT> ) , <NUM_LIT>


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCapFloat64Store ( MachineInstr & MI , MachineBasicBlock * BB )


<s> return __builtin_loongson_psrah_s ( s ,


<s> if ( isSpecialLLVMGlobalArrayForStaticInit ( GV ) ) return ; MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; SectionKind GVKind ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( GV -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( GV , TM ) : getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) , TM ) ) ; GVSym -> setContainingCsect ( Csect ) ; if ( GV -> isDeclaration ( ) ) return ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> emitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym


<s> uint64_t Index = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMergeValues ( { Pred , Load . getValue ( <NUM_LIT> ) } ,


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned CmpOpc ; if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiXOpc ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm


<s> break ; case ORDERED : case UNORDERED : case UNGT : case UNLT : case UNEQ : case UNGE : case UNLE : case LTGT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_ARCH64 ) { if ( MEM_P ( x ) ) { tree expr = MEM_EXPR ( x ) ; if ( expr ) mark_addressable ( expr ) ; slot0 = x ; } else { slot0 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot0 , x ) ; } if ( MEM_P ( y ) ) { tree expr = MEM_EXPR ( y ) ; if ( expr ) mark_addressable ( expr ) ; slot1 = y ; } else { slot1 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot1 , y ) ; } libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , DImode , XEXP ( slot0 , <NUM_LIT> ) , Pmode , XEXP ( slot1 , <NUM_LIT> ) , Pmode ) ; mode = DImode ; } else { libfunc = gen_rtx_SYMBOL_REF ( Pmode ,


<s> if ( BB -> size ( ) > <NUM_LIT> ) if ( auto * TI = dyn_cast < TerminatorInst > ( & * std :: prev ( BB -> end ( ) , <NUM_LIT> ) ) ) Builder . SetInsertPoint ( TI ) ; materializeEFLAGS (


<s> return TargetTriple . getOS ( ) == Triple ::


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC :


<s> return ( ( ( unsigned long ) addr ) >> <NUM_LIT> ) &


<s> if ( RegNum == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegNum = getReg ( regKindToRegClass ( <STR_LIT> ) , RegNum ) ; RegOp = <STR_LIT> ( RegNum , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else return MatchOperand_ParseFail ; RegOp -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( RegOp ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * expr = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! expr || ! validateMSAIndex ( ( int ) expr -> getValue ( ) , Kind ) ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; bool insve = Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> ; if ( insve && Operands . size ( ) > <NUM_LIT> ) { if ( expr -> getValue ( ) != <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , VIdx ) ) ; } else Operands . push_back ( <STR_LIT> ( expr , VIdx , E ) ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange (

Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ;


<s> unsigned EltSize = VT . getScalarSizeInBits ( ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) { unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opc ) ; } if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) ==


<s> return LowerSTATEPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , TM , getSubtargetInfo ( ) , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIAllocStack ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT>


<s> bool arm_ge_bits_access ( void ) { if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES


<s> if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains (


<s> if ( unsigned Reg = State . AllocateReg ( RegList ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) , LocVT ,


<s> } } if ( ! SN -> isTruncatingStore ( ) && ! SN -> isVolatile ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> )

, Ops , MemVT , SN -> getMemOperand ( ) ) ;


<s> return ( __m128 ) __builtin_ia32_cvtsi642ss ( ( __v4sf )


<s> static unsigned sizeConstant ( unsigned Size ) { return Size


<s> inline static bool isAnyMOVWMovAlias ( uint64_t Value , int RegWidth ) { if ( isAnyMOVZMovAlias ( Value , RegWidth


<s> void <ISA_LIT>CodeEmitter :: addPCLabel ( unsigned LabelID ) { DEBUG ( errs ( ) << <STR_LIT> << LabelID << <STR_LIT> << ( void * ) MCE


<s> MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc


<s> for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , TII ) ) return true ; return false


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) )


<s> return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand


<s> if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm (


<s> if ( ! Enable<ISA_LIT>LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * ,


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Op0 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( ! Op1 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode (

<STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> void <ISA_LIT>BaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( )


<s> CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset


<s> if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand

:: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ;


<s> return ( __m256i ) __builtin_ia32_broadcasti64x2_256_mask ( ( __v2di ) __A , ( __v4di ) _mm256_undefined_si256 ( )


<s> if ( ISD == <STR_LIT> && Index == ( ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return Cost ; } else if ( ST -> hasQPX ( ) && Val -> getScalarType ( ) -> isFloatingPointTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue


<s> unsigned CC = <STR_LIT> ; if ( instrInITBlock ( ) ) CC = ITStates . back ( ) ; return


<s> ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ; return Changed


<s> return ( int32x4_t ) __builtin_neon_vdup_nv4si ( ( __builtin_neon_si )


<s> Opc = <STR_LIT> ; break ; } N0 = SDValue ( CurDAG -> getTargetNode ( Opc , dl , N0VT , <STR_LIT> , N0 ) , <NUM_LIT> ) ; return CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , N0 , SRIdx , N0 . getValue


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MCInstrDesc & ADDrr = TII -> get ( getADDrrFromLEA ( Opcode ) ) ; const MachineOperand & Src = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MFI , I , MI . getDebugLoc ( ) , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( Opcode , MI . getOperand ( <NUM_LIT> ) ) ) ; const MachineOperand & SrcR = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MFI , I , MI . getDebugLoc ( ) , ADDri , DstR ) . add ( SrcR ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; LLVM_DEBUG ( NewMI -> dump ( )


<s> bool isImm0_31 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( )


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightArithmetic ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightLogical ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ; return SDValue


<s> if ( Subtarget . isLittleEndian ( ) ) for ( int i = <NUM_LIT> ; i < SaveElts ; i ++ ) ShuffV [ i * Stride ] = i ; else for ( int i = <NUM_LIT> ; i <= SaveElts ; i ++ ) ShuffV [ i * Stride - <NUM_LIT> ] = i - <NUM_LIT> ; SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; SDValue Arrange = DAG . getVectorShuffle ( WideVT , dl , Wide , ShuffleSrc2 , ShuffV ) ; SDValue Extend ; if ( SignedConv ) { Arrange = DAG . getBitcast ( IntermediateVT , Arrange ) ; EVT ExtVT = Src . getValueType ( ) ; if ( Subtarget . hasP9Altivec ( ) ) ExtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WideVT . getVectorElementType ( ) , IntermediateVT . getVectorNumElements ( ) ) ; Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT , Arrange , DAG . getValueType (


<s> return & InstrInfo . getRegisterInfo


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> if ( isParsingIntelSyntax ( ) ) return ParseIntelOperand (


<s> if ( CC == CallingConv :: Cold ) { return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; } return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_<ISA_LIT>64_Altivec_RegMask : CSR_<ISA_LIT>64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget .

hasSPE ( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ; return


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static const char * const Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeList A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addFnAttribute ( C , <STR_LIT> ) ; A = A . addFnAttribute ( C , Attribute :: ReadNone ) ; A = A . addFnAttribute ( C , Attribute :: NoInline ) ; FunctionCallee F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( ! TM . isPositionIndependent ( ) ) { if ( needsFPHelperFromSig ( * F_ ) )


<s> CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; } return


<s> SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : { IsZExt = true ; unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { addPass ( create<ISA_LIT>CopyPhysRegsPass ( get<ISA_LIT>TargetMachine ( )


<s> if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) ==


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( ! cum ) return false ; if ( TARGET_SHCOMPACT ) { cum -> byref = shcompact_byref ( cum , mode ,


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> -> contains ( Reg ) ) break ; MFI -> setObjectOffset ( CSI [ i ] . getFrameIdx ( ) , StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += MFI -> getObjectAlignment ( CSI [ i ] . getFrameIdx ( ) ) ; } if ( hasFP ( MF ) || MFI -> adjustsStack ( ) ) { MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setFPStackOffset ( StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; <ISA_LIT>FI -> setRAStackOffset ( StackOffset ) ; StackOffset += RegSize ; if ( MFI -> adjustsStack ( ) ) TopCPUSavedRegOff += RegSize ; } StackOffset = ( ( StackOffset + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size (


<s> uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr


<s> if ( check ( getLexer ( ) . is ( AsmToken :: Percent ) , L , <STR_LIT> ) || getParser ( ) . parseExpression ( Val , End ) || check ( isa < <ISA_LIT>MCExpr > ( Val ) , L , <STR_LIT> ) ) return nullptr ; return <STR_LIT> ( Val , Start , End ) ; } case AsmToken :: LCurly : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; return ParseRoundingModeOp ( Start ) ; } default : { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) , EndLoc ; const MCExpr * Expr = nullptr ; unsigned Reg = <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( Parser . parseExpression ( Expr


<s> static bool f64RetAssign ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , CCState & State ) { static const uint16_t HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t LoRegList [ ] = { <STR_LIT> ,


<s> HOST_WIDE_INT offset , required_offset ; rtx addr , base ; if ( ! MEM_P ( dest ) || ! REG_P ( src ) || GET_MODE ( dest ) != word_mode ) return false ; regno = REGNO ( src ) ; if ( ! IN_RANGE ( regno , GP_ARG_FIRST , GP_ARG_LAST ) || reg_values [ regno ] ) return false ; argno = regno


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; VecMem . clear ( ) ; VecMem . push_back ( Ld0 ) ; VecMem . push_back ( Ld1 ) ; return


<s> bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; } InstrDistance += TII -> getInstrLatency ( TM -> getSubtargetImpl ( ) -> getInstrItineraryData ( ) , CurInst ) ; Found = getPreviousInstr ( CurInst , MFI


<s> APInt ShiftVal = cast < ConstantSDNode > ( N1 ) -> getAPIntValue ( ) ; if ( ShiftVal . zextOrTrunc ( <NUM_LIT> ) . uge ( NumBitsPerElt ) ) { if ( LogicalShift ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( Opcode == <STR_LIT> && ( ShiftVal + <NUM_LIT> ) == NumBitsPerElt && N0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( LogicalShift && ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned ShiftImm = ShiftVal . getZExtValue ( ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt <<= ShiftImm ; else if ( <STR_LIT> == Opcode ) Elt . ashrInPlace ( ShiftImm ) ; else Elt . lshrInPlace ( ShiftImm ) ; } return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) , DAG ,


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Token , Loc , EndLoc ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length =


<s> if ( ! valid_psw_flag ( op , <STR_LIT> ) ) return NULL_RTX ; return rx_expand_void_builtin_1_arg ( op , gen_clrpsw , false ) ; case RX_BUILTIN_SETPSW : if ( ! valid_psw_flag ( op , <STR_LIT> ) ) return NULL_RTX ; return rx_expand_void_builtin_1_arg ( op , gen_setpsw , false ) ; case RX_BUILTIN_INT : return rx_expand_void_builtin_1_arg ( op , gen_int , false ) ; case RX_BUILTIN_MACHI : return rx_expand_builtin_mac ( exp , gen_machi ) ; case RX_BUILTIN_MACLO : return rx_expand_builtin_mac ( exp , gen_maclo ) ; case RX_BUILTIN_MULHI : return rx_expand_builtin_mac ( exp , gen_mulhi ) ; case RX_BUILTIN_MULLO : return rx_expand_builtin_mac ( exp , gen_mullo ) ; case RX_BUILTIN_MVFACHI : return rx_expand_int_builtin_0_arg ( target , gen_mvfachi ) ; case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : emit_insn ( gen_rmpa ( ) ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target


<s> int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; return ! AA -> isNoAlias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 . getValue ( ) , Overlapb , Op2 .


<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; SMLoc NewFPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int NewFPReg = tryParseRegister ( ) ; if ( NewFPReg == - <NUM_LIT> ) return Error ( NewFPRegLoc , <STR_LIT> ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Comma ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc NewSPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int NewSPReg = tryParseRegister ( ) ; if ( NewSPReg == - <NUM_LIT> ) return Error ( NewSPRegLoc , <STR_LIT> ) ; if ( NewSPReg != <STR_LIT> && NewSPReg != FPReg ) return Error ( NewSPRegLoc , <STR_LIT> ) ; FPReg = NewFPReg ; int64_t Offset = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } getParser ( ) . getStreamer ( ) . EmitSetFP ( static_cast < unsigned > ( NewFPReg )

, static_cast < unsigned > ( NewSPReg ) , Offset ) ;


<s> bool nds32_valid_CVp5_p ( rtx op ) { HOST_WIDE_INT ival = const_vector_to_hwint ( op ) ; return ( ival < ( ( <NUM_LIT> << <NUM_LIT> ) + <NUM_LIT> ) ) && (


<s> EntryBuilder . buildCopy ( { DstReg } , { Register ( <STR_LIT> ) } ) ; MFReturnAddr = DstReg ; I . eraseFromParent ( ) ; return true ; } MFI . setFrameAddressIsTaken ( true ) ; Register FrameAddr ( <STR_LIT> ) ; while ( Depth -- ) { Register NextFrame = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto Ldr = MIRBuilder . buildInstr ( <STR_LIT> , { NextFrame } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Ldr , TII , TRI , RBI ) ; FrameAddr = NextFrame ; } if ( IntrinID == <STR_LIT> ) MIRBuilder . buildCopy ( { DstReg } , { FrameAddr } ) ; else { MFI . setReturnAddressIsTaken ( true ) ; MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; } I . eraseFromParent ( ) ; return true ; } case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { Register ( <STR_LIT> ) } ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MF -> getFrameInfo ( ) . setFrameAddressIsTaken ( true ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; I . eraseFromParent ( ) ; return


<s> water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , NewBB ,


<s> if ( M == i ) continue ; if ( M == i + Size ) { BlendMask |= <NUM_LIT> << i ; continue ; } if ( Zeroable [ i ] ) { if ( V1IsZeroOrUndef ) { ForceV1Zero = true ; Mask [ i ] = i ; continue ; } if ( V2IsZeroOrUndef ) { ForceV2Zero = true ; BlendMask |= <NUM_LIT> << i ; Mask [ i ] = i + Size ; continue ; } } return false ; } return


<s> LPAC :: AluCode AluCode = LPAC :: isdTo<ISA_LIT>AluCode ( AluOperator ) ; if ( AluCode != LPAC :: UNKNOWN ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; AluOp = CurDAG -> getTargetConstant ( AluCode , SDLoc ( Addr ) , <STR_LIT> ) ; return true


<s> assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; int Offset = <NUM_LIT> ; if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { bool Negative = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned Imm12 = getImm12 ( insn ) ; Offset = Negative ? - <NUM_LIT> - Imm12 : <NUM_LIT> * Imm12 ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Imm8 = getImm8 ( insn ) ; Offset = - <NUM_LIT> - Imm8 ; } else Offset = decodeImm12 ( insn


<s> uint32_t Reg = RI -> getRegClass ( <STR_LIT> ) . getRegister ( RI -> getEncodingValue ( getReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> return N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> )


<s> struct ix86_address parts ; rtx base , index , disp ; HOST_WIDE_INT scale ; addr_space_t seg ; if ( ix86_decompose_address ( addr , & parts ) <= <NUM_LIT> ) return false ; base = parts . base ; index = parts . index ; disp = parts . disp ; scale = parts . scale ; seg = parts . seg ; if ( base ) { rtx reg = ix86_validate_address_register ( base ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_BASE_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_BASE_NONSTRICT_P ( reg ) ) ) return false ; } if ( index ) { rtx reg = ix86_validate_address_register ( index ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_INDEX_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P ( reg ) ) ) return false ; } if ( base && index && GET_MODE ( base ) != GET_MODE ( index ) ) return false ; if ( seg != ADDR_SPACE_GENERIC && ( ( base && GET_MODE ( base ) != word_mode ) || ( index && GET_MODE ( index ) != word_mode ) ) ) return false ; if ( scale != <NUM_LIT> ) { if ( ! index ) return false ; if ( scale != <NUM_LIT> && scale != <NUM_LIT> && scale != <NUM_LIT> ) return false ; } if ( disp ) { if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) != UNSPEC_MACHOPIC_OFFSET ) switch ( XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : gcc_assert ( flag_pic ) ; if ( ! TARGET_64BIT ) goto is_legitimate_pic ; return false ; case UNSPEC_GOTPCREL : case UNSPEC_PCREL : gcc_assert ( flag_pic ) ; goto is_legitimate_pic ; case UNSPEC_GOTTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF


<s> Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; SupportsDebugInformation =


<s> MCFragment * <ISA_LIT>MCExpr :: findAssociatedFragment (


<s> const TargetMachine & TM = Fn . getTarget ( ) ; TL = TM . getTargetLowering ( ) ; AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI )


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout ,


<s> if ( HasPackedStackAttr && BackChain && ! SoftFloat ) report_fatal_error ( <STR_LIT> ) ; bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv ::


<s> return StringSwitch < <STR_LIT> > ( CC ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT>

) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> static SDValue LowerSVEIntrinsicIndex ( SDNode * N , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Op2 . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) ScalarTy = <STR_LIT> ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL ,


<s> if ( OldCollisions . size ( ) <= <NUM_LIT> ) continue ; bool Fixed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; for ( unsigned ScratchReg : <STR_LIT> ) { if ( ! LR . available ( ScratchReg ) || MRI . isReserved ( ScratchReg ) ) continue ; LoadInfo NewLdI ( LdI ) ; NewLdI . BaseReg = ScratchReg ; unsigned NewTag = * getTag ( TRI , MI , NewLdI ) ; if ( TagMap . count ( NewTag ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( ScratchReg , TRI ) << '\n' ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg ( ScratchReg ) ; if ( LdI . IsPrePost ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( ScratchReg , TRI ) << '\n' ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ScratchReg ) ; BuildMI ( * MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , DL , TII -> get ( <STR_LIT> ) , LdI . BaseReg ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } for ( int I = <NUM_LIT> , E = OldCollisions . size ( ) ; I != E ; ++ I ) if ( OldCollisions [ I ] == & MI ) { std :: swap ( OldCollisions [ I ] , OldCollisions [ E - <NUM_LIT> ] ) ; OldCollisions . pop_back ( ) ; break ; } TagMap [ NewTag ] . push_back ( & MI ) ; ++ NumCollisionsAvoided ; Fixed = true ; Modified = true ; break ; } if ( ! Fixed )


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( getTargetMachine ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> ,


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( ! Op . isImm ( ) ) return printOperand ( MI , OpNo , STI , O ) ; if ( PrintBranchImmAsAddress ) O << formatHex ( Op . getImm ( ) ) ; else O << formatImm ( Op


<s> void <ISA_LIT>ParallelDSP :: InsertParallelMACs ( Reduction & R ) { auto CreateSMLAD = [ & ] ( LoadInst * WideLd0 , LoadInst * WideLd1 , Value * Acc , bool Exchange , Instruction * InsertAfter ) { Value * Args [ ] = { WideLd0 , WideLd1 , Acc } ; Function * SMLAD = nullptr ; if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; Instruction * Call = Builder . CreateCall ( SMLAD , Args ) ; NumSMLAD ++ ; return Call ; } ; Instruction * InsertAfter = R . getRoot ( ) ; Value * Acc = R . getAccumulator ( ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; MulCandList & MulCands = R


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL

( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return true ;


<s> return ( uint8x8_t ) ( __a == <NUM_LIT>


<s> if ( flags & FLAG_READ_FPCR ) return true ; return flags &


<s> const MCSymbolData & SD = Streamer . getOrCreateSymbolData ( Symbol ) ; if ( MCELF :: GetType ( SD ) & ( ELF :: STT_FUNC << ELF_STT_Shift ) ) Streamer


<s> if ( ! TARGET_EXPLICIT_RELOCS && cfun -> machine -> global_pointer > <NUM_LIT> && cfun -> machine ->


<s> if ( ninsns == <NUM_LIT> ) return ; if ( * hilo_delay < <NUM_LIT> && reg_set_p ( lo_reg , pattern ) ) nops = <NUM_LIT> - * hilo_delay ; else if ( * delayed_reg != <NUM_LIT> && reg_referenced_p ( * delayed_reg , pattern ) ) nops = <NUM_LIT> ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < <NUM_LIT> ) nops = <NUM_LIT> ; else nops = <NUM_LIT> ; * hilo_delay += nops ; while ( nops -- > <NUM_LIT> ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay +=


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget -> useLVIControlFlowIntegrity ( ) || ! Subtarget -> is64Bit ( ) ) return false ; const Function & F = MF . getFunction ( ) ; if ( ! F . hasOptNone ( ) && skipFunction ( F ) ) return false ; ++ NumFunctionsConsidered ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; bool Modified = false ; for ( auto & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned ClobberReg = TRI -> findDeadCallerSavedReg ( MBB , MBBI ) ; if ( ClobberReg != <STR_LIT>


<s> UnsignedFree = true ; ImmIdx = <NUM_LIT> ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == <NUM_LIT> ) return TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= <NUM_LIT> && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue (


<s> bool useLongCalls ( ) const { return


<s> if ( ! mips_get_unaligned_mem ( src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } if ( dest1 ) { if ( unsigned_p ) emit_insn ( gen_zero_extendsidi2


<s> } case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; return Offset > <NUM_LIT> || Offset < <NUM_LIT> || Offset & <NUM_LIT> ; } case <STR_LIT> : int64_t Offset = ( Value & ~ <NUM_LIT> ) ; return Offset == <NUM_LIT> ; } llvm_unreachable (


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return ( Endian == <STR_LIT> ? InfosLE :

InfosBE ) [ Kind - FirstTargetFixupKind ] ;


<s> if ( ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && ! HOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && HOp . getOperand ( <NUM_LIT> ) != HOp . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; auto updateHOp = [ ] ( SDValue HorizOp , SelectionDAG & DAG ) { SDValue X ; if ( HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) ) { assert ( ! HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; X = HorizOp . getOperand ( <NUM_LIT> ) ; } else if ( HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) ) { assert ( ! HorizOp . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; X = HorizOp . getOperand ( <NUM_LIT> ) ; } else { return HorizOp ; } return DAG . getNode ( HorizOp . getOpcode ( ) , SDLoc ( HorizOp ) , HorizOp . getValueType ( ) , X , X ) ; } ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( HOp . getScalarValueSizeInBits ( ) == <NUM_LIT> && HOp . getValueType ( ) == VT ) { assert ( ( HOp . getValueType ( ) == <STR_LIT> || HOp . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; return updateHOp ( HOp , DAG ) ; } return SDValue ( )


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return false ; if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return true ; assert ( false && <STR_LIT> ) ; return false


<s> diag ( pos , <STR_LIT> ) ; exit ( <NUM_LIT> )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset +=


<s> static inline bool isPTrueOpcode ( unsigned Opc ) { switch ( Opc )


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = <NUM_LIT> ; SelectionDAGISel :: runOnMachineFunction ( MF


<s> if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) return true ; AM = SavedAM ; break ; unsupported_gep : break ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg


<s> static inline __ev64_opaque__ __internal_ev_mwhgumian ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT


<s> unsigned int nunits ; static char buf [ sizeof ( <STR_LIT> ) ] ; if ( GET_MODE_NUNITS ( mode ) . is_constant ( & nunits ) ) snprintf ( buf , sizeof ( buf


<s> return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , false , ( T . getArch ( ) == Triple :: thumb ||

T . getArch ( ) == Triple :: thumbeb ) ) ;


<s> static const struct { const uint64_t Kind ; const FeatureBitset ArchCheck ; const FeatureBitset Features ; } Extensions [ ] = { { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> } } , { ( <STR_LIT> | <STR_LIT> ) , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV6KBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_2aBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_1MMainlineBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_1MMainlineBit } , { <STR_LIT> } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , } ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT>


<s> return __builtin_ia32_vcvtsd2sh_mask_round ( __B , __A , _mm_setzero_ph ( ) , ( __mmask8 ) -


<s> DstPtr = MIRBuilder . buildMaskLowPtrBits ( PtrTy , ListTmp , Log2 ( Alignment ) ) ; } else DstPtr = List ; LLT ValTy = MRI . getType ( Dst ) ; uint64_t ValSize = ValTy . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValTy , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getThumbBLXTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return encodeThumbBLOffset ( MO . getImm ( )


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , Register SourceRegister , bool IsKill , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * ) const { DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * TD -> getPointerSize (


<s> bool isDecl = GV -> isDeclaration ( ) ; if ( GV -> hasHiddenVisibility ( ) && ! isDecl && ! GV -> hasCommonLinkage ( ) ) return false ; return GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage (


<s> else if ( flag_pic ) x = sparc_legitimize_pic_address ( x , NULL_RTX ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x


<s> if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext


<s> SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue rd = DAG . getNode ( <STR_LIT> , DL , Tys , Chain ) ; if ( Subtarget -> is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } Chain = HI . getValue ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT>


<s> Op0 = DAG . getNode ( Extend , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx


<s> const TargetFrameLowering * getFrameLowering ( ) const


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsS32 ( ) ) return makeArrayRef ( S32IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> if ( ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) || ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & <STR_LIT> && MO . isDead


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ; return MI . getOperand ( Idx


<s> const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; assert ( DstRB . getID ( ) == SrcRB . getID ( ) && <STR_LIT> ) ; assert ( DstTy . getSizeInBits ( ) > SrcTy . getSizeInBits ( ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( canTurnIntoCOPY ( SrcRC , DstRC ) ) return selectTurnIntoCOPY ( I , MRI , SrcReg , SrcRC , DstReg , DstRC ) ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC ,


<s> if ( ! SrcBytes || ! Alignment || * Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && * Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; if ( TLI -> allowsMisalignedMemoryAccesses ( LT . second , <NUM_LIT> ) ) return Cost ; assert ( Alignment ) ; Cost += LT . first * ( ( SrcBytes / Alignment -> value ( ) ) - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = cast < FixedVectorType > ( Src ) -> getNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost ( Instruction :: ExtractElement , Src , i ) ; return Cost


<s> return isMem ( RegKind , HasIndex ) && inRange ( Mem . Disp ,


<s> return gen_rtx_UNSPEC ( Pmode , gen_rtvec (


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART (