<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( syscallMBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = syscallMBB ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent (


<s> return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError

( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) ;


<s> static DecodeStatus decodeBranch ( MCInst & MI , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { if ( ! tryAddingSymbolicOperand ( Insn + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( Insn ) ) ; return MCDisassembler :: Success


<s> static bool arm_is_segment_info_known ( rtx orig , bool * is_readonly ) { * is_readonly = false ; if ( LABEL_REF_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_P ( orig ) ) { if ( CONSTANT_POOL_ADDRESS_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_LOCAL_P ( orig ) && ! SYMBOL_REF_EXTERNAL_P ( orig ) && SYMBOL_REF_DECL ( orig ) && ( ! DECL_P ( SYMBOL_REF_DECL ( orig ) ) || ! DECL_COMMON ( SYMBOL_REF_DECL ( orig ) ) ) ) { tree decl = SYMBOL_REF_DECL ( orig ) ; tree init = ( TREE_CODE ( decl ) == VAR_DECL ) ? DECL_INITIAL ( decl ) : ( TREE_CODE ( decl ) == CONSTRUCTOR ) ? decl : <NUM_LIT> ; int reloc = <NUM_LIT> ; bool named_section ,


<s> for ( unsigned int pi = <NUM_LIT> ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) for ( unsigned


<s> unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . setDesc ( TII . getMemoryInstr ( MI . getOpcode ( )


<s> bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Clone =


<s> SDValue <ISA_LIT>TargetLowering :: LowerParabixOperation ( SDValue Op , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ; Op . dump ( ) ) ; static bool FirstTimeThrough = true ; if ( FirstTimeThrough ) { resetOperations ( ) ; FirstTimeThrough = false ; } MVT VT = Op . getSimpleValueType ( ) ; CastAndOpKind kind = std :: make_pair ( ( <STR_LIT> ) Op . getOpcode ( ) , VT ) ; if ( CAOops . find ( kind ) != CAOops . end ( ) ) return lowerWithCastAndOp ( Op , DAG ) ; if ( OpKindActions . find ( ( OpKind ) kind ) != OpKindActions . end ( ) ) return lowerWithOpAction ( Op , DAG ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return PXLowerADD ( Op , DAG ) ; case <STR_LIT> : return PXLowerSUB ( Op , DAG ) ; case <STR_LIT> : return PXLowerMUL ( Op ,


<s> EVT ScalarVT = EVT :: getIntegerVT ( Ctx , <STR_LIT> / NumElts ) ; EVT MemVT = EVT :: getVectorVT ( Ctx , ScalarVT , NumElts , true ) ; return MemVT


<s> if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue PSHUFB = lowerVectorShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable


<s> <STR_LIT> AK = <STR_LIT> ( ArchName ) ; if ( AK == <STR_LIT> :: <ISA_LIT>V7S ) CPUString = <STR_LIT> ; else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState


<s> if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig >


<s> if ( ! TARGET_FPRS || ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_SINGLE_FLOAT && mode == SFmode ) return true ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( is_complex_IBM_long_double ( mode


<s> gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb


<s> std :: string <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } return <ISA_LIT>ArchFeature


<s> MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; unsigned NumIterations = <NUM_LIT> ; while ( foldMachineFunction ( MF , MLI , MDT ) ) { modified = true ; NumIterations ++ ; assert ( NumIterations < <NUM_LIT> && <STR_LIT> ) ; } if ( modified


<s> SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result .


<s> static bool isMOVHLPS_v_undef_Mask ( ArrayRef < int > Mask , EVT VT ) { unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) !=


<s> if ( ! isa < Instruction > ( V ) ) return true ; if ( generateSignBits ( V ) ) return false ; return ! isa < OverflowingBinaryOperator > ( V


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) { return BaseT :: getCmpSelInstrCost ( Opcode , ValTy


<s> while ( TREE_CODE ( target ) == ARRAY_TYPE ) target = TREE_TYPE ( target ) ; as = TYPE_ADDR_SPACE ( target ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) ) return true ; return pru_nongeneric_pointer_addrspace ( target )


<s> SZFrameObjVec SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectSize = MFI . getObjectSize ( Obj ) ; } for ( auto & MBB : MF ) for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) { if ( TII -> hasDisplacementPairInsn ( MI . getOpcode ( ) ) ) SortingObjects [ Index ] . DPairCount ++ ; else if ( ! ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ) SortingObjects [ Index ] . D12Count ++ ; } } } auto CmpD12 = [ ] ( const SZFrameSortingObj & A , const SZFrameSortingObj & B ) { if ( ! A . IsValid || ! B . IsValid ) return A . IsValid ; if ( ! A . ObjectSize || ! B . ObjectSize ) return A . ObjectSize > <NUM_LIT> ; uint64_t ADensityCmp = A . D12Count * B . ObjectSize ; uint64_t BDensityCmp = B . D12Count * A . ObjectSize ; if ( ADensityCmp != BDensityCmp ) return ADensityCmp < BDensityCmp ; return A . DPairCount * B . ObjectSize < B . DPairCount * A . ObjectSize ; } ; std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , CmpD12 ) ; unsigned Idx = <NUM_LIT>


<s> } else Align = TD -> getPreferredTypeAlignmentShift ( CTy ) ; printVisibility ( name , GVar -> getVisibility ( ) ) ; OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( GVar , Mang , TM ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) O << <STR_LIT> << name << '\n' ; O << TAI -> getCOMMDirective ( ) << name << ',' << Size ; if ( TAI -> getCOMMDirectiveTakesAlignment ( ) ) O << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 (


<s> return ( __m512i ) __builtin_ia32_vpconflictdi_512_mask ( ( __v8di ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 )


<s> const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op0Reg = emitAnd_ri ( <STR_LIT> , Op0Reg , Mask ) ; Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Mask ) ; } Register ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op1Reg ) ; if ( NeedTrunc ) ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg ,


<s> void <ISA_LIT>DeadRegisterDefinitions :: processMachineBasicBlock ( MachineBasicBlock & MBB ) { const MachineFunction & MF = * MBB . getParent ( ) ; for ( MachineInstr & MI : MBB ) { if ( usesFrameIndex ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( atomicBarrierDroppedOnZero ( MI . getOpcode ( ) ) || atomicReadDroppedOnZero ( MI . getOpcode ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; for ( int I = <NUM_LIT> , E = Desc . getNumDefs ( )


<s> static rtx get_tls_get_addr ( void ) { if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ; return tls_get_addr_libfunc


<s> assert ( ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . has<ISA_LIT>64r6 ( ) ) ; SDValue Cond = createFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( )


<s> case E_QImode : return V16QImode ; case E_HImode : return V8HImode ; case E_SImode : return V4SImode ; case E_DImode : return V2DImode ; case E_SFmode : return V4SFmode ; case


<s> regno = REGNO ( x ) ; if ( strict_p ) return ( CSKY_GENERAL_REGNO_P ( regno ) || CSKY_GENERAL_REGNO_P ( reg_renumber [ regno


<s> assert ( NumElts == ( int ) Zeroable . getBitWidth ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > TargetMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask


<s> static MCOperand createPCXRelExprOp ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * GOTLabel , MCSymbol * StartLabel , MCSymbol * CurLabel , MCContext & OutContext ) { const MCSymbolRefExpr * GOT = MCSymbolRefExpr :: Create ( GOTLabel , OutContext ) ; const MCSymbolRefExpr * Start = MCSymbolRefExpr :: Create ( StartLabel , OutContext ) ; const MCSymbolRefExpr * Cur = MCSymbolRefExpr :: Create ( CurLabel , OutContext ) ; const MCBinaryExpr * Sub = MCBinaryExpr :: CreateSub ( Cur , Start , OutContext ) ; const MCBinaryExpr * Add = MCBinaryExpr :: CreateAdd ( GOT , Sub , OutContext ) ; const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: Create ( Kind ,


<s> unsigned Reg = SavedRegs [ I ] ; if ( Reg == <NUM_LIT> ) continue ; int CURegNum = getCompactUnwindRegNum ( Reg , Is64Bit ) ; if ( CURegNum == - <NUM_LIT> ) return ~ <NUM_LIT> ; RegEnc |= ( CURegNum & <NUM_LIT> ) << ( Idx ++ * <NUM_LIT> ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT> ) ; return


<s> return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DCI ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case


<s> return ; } for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) if ( Succ != MBB ) findReturns (


<s> SubregIdx = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( EltSize == <NUM_LIT> ) { Opc = <STR_LIT> ; SubregIdx = <STR_LIT> ; } else if ( EltSize == <NUM_LIT> ) { Opc = <STR_LIT> ; SubregIdx = <STR_LIT> ; } else if ( EltSize == <NUM_LIT> ) { Opc = <STR_LIT> ; SubregIdx = <STR_LIT> ; } else if ( EltSize == <NUM_LIT> ) { Opc = <STR_LIT> ; SubregIdx = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } } return std :: make_pair ( Opc


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , TII ,


<s> MachineBasicBlock :: const_iterator I = MI ; ++ I ; MachineBasicBlock :: const_instr_iterator II = std :: prev ( I . getInstrIterator ( ) ) ; assert ( II -> isInsideBundle ( ) && <STR_LIT> ) ; int Idx = - <NUM_LIT> ; while ( II -> isInsideBundle ( ) ) { Idx = II -> findRegisterDefOperandIdx ( Reg , false , true , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; -- II ; ++ Dist ; } assert ( Idx != - <NUM_LIT> && <STR_LIT> ) ; DefIdx = Idx ; return II


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT

, FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> ) :


<s> assert ( Bundle . isFixed ( ) && <STR_LIT> ) ; for ( unsigned i = Bundle . FixCount ; i > <NUM_LIT> ; -- i ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( i - <NUM_LIT> ) << <STR_LIT> << unsigned ( Bundle .

FixStack [ i - <NUM_LIT> ] ) << '\n' ) ;


<s> static DecodeStatus DecodeT2Imm7S4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( INT32_MIN ) ) ; else { int imm = Val & <NUM_LIT> ; if ( ! ( Val & <NUM_LIT> ) ) imm *= -


<s> SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NegOne = DAG . getConstant ( APInt :: getAllOnesValue ( ExtVT . getScalarSizeInBits ( ) ) , dl , ExtVT ) ; SDValue Zero = DAG . getConstant ( APInt :: getNullValue ( ExtVT . getScalarSizeInBits ( ) ) ,


<s> BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor (


<s> StringRef label = LabelToEmit ; if ( ! label . empty ( ) ) { if ( addFen


<s> SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry , dl , DAG ) ; return CallResult . first ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > && AB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , std :: move ( OW ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return


<s> auto Pg = getPredicateForFixedLengthVector ( DAG , DL , InVT ) ; if ( <STR_LIT> ( Mask . getNode ( ) ) ) return Pg ; auto Op1 = convertToScalableVector ( DAG , ContainerVT , Mask ) ; auto Op2 = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; return DAG . getNode ( <STR_LIT> , DL , Pg . getValueType ( ) , { Pg , Op1 , Op2 ,


<s> emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return <NUM_LIT> ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y =


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned


<s> return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; unsigned Imm = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Imm , <NUM_LIT> * Rot ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> (


<s> tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return NUM_TYPE_SUFFIXES ; for ( unsigned int size_i = <NUM_LIT> ; size_i < MAX_TUPLE_SIZE ; ++ size_i ) for ( unsigned int suffix_i = <NUM_LIT> ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) { vector_type_index type_i = type_suffixes [ suffix_i ] . vector_type ; tree type = acle_vector_types [ size_i ] [ type_i ] ; if ( type && matches_type_p ( type , actual ) ) { if ( size_i + <NUM_LIT> == num_vectors ) return type_suffix_index ( suffix_i ) ; if ( num_vectors == <NUM_LIT> ) error_at ( location , <STR_LIT> <STR_LIT> , actual


<s> if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand

( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > MorphToMemRegImm ( unsigned BaseReg , std :: unique_ptr < <ISA_LIT>Operand > Op , unsigned AluOp ) { const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = MEMORY_REG_IMM ; Op -> Mem . BaseReg


<s> auto * ConstMask = dyn_cast < ConstantDataVector > ( Mask ) ; if ( ! ConstMask ) return false ; unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( Vec -> getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ; Constant * BoolMask = getNegativeIsTrueBoolVec ( ConstMask ) ; IC . Builder . CreateMaskedStore ( Vec , PtrCast , Align ( <NUM_LIT> ) ,


<s> SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && prior ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) , & MF . getTarget ( ) ) ; while ( ++ Start != llvm :: next ( I


<s> AlignmentIsInBytes = false ; HasSingleParameterDotFile = true ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true


<s> Value * <ISA_LIT>IREmitter :: visitLFENCE (


<s> if ( ! multiple_operation_profitable_p ( false , count , <NUM_LIT> ) ) { rtx seq ; start_sequence ( ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != <NUM_LIT> ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != <NUM_LIT> ?


<s> for ( CountMap :: const_iterator Chunk = Counts . begin ( ) , End = Counts . end ( ) ; Chunk != End ; ++ Chunk ) { const uint64_t ChunkVal = Chunk -> first ; const unsigned Count = Chunk -> second ; uint64_t Encoding = <NUM_LIT> ; if ( ( Count != <NUM_LIT> && Count != <NUM_LIT> ) || ! canUseOrr ( ChunkVal , Encoding ) ) continue ; const bool CountThree = Count == <NUM_LIT> ; Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> , ShiftAmt ) } ) ; if ( CountThree ) return true ; for ( ShiftAmt += <NUM_LIT> ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> , ShiftAmt ) } ) ; return true ; } return


<s> int i ; for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , <NUM_LIT> , i ) , str_mem ) ) return true ; } return false


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex


<s> bool <ISA_LIT>MCSymbolRefExpr :: EvaluateAsRelocatableImpl ( MCValue & Res ,


<s> unsigned Mask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned NumTZ = countTrailingZeros ( Mask ) ; assert ( NumTZ <= <NUM_LIT> &&


<s> p -> next = export_head ; p -> name = name ; p -> is_data = is_data


<s> return new pass_remove_partial_avx_dependency ( ctxt


<s> return ( __m256 ) __builtin_ia32_roundps256 ( ( __v8sf )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32LETarget ( ) , create<ISA_LIT>LEDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( )


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; MachineMemOperand * MMO = LD -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLD ) ; SDValue Ops [ ] = { Result , SDValue ( NewLD . getNode ( ) , <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE (


<s> if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses (


<s> for ( MachineOperand & Def : MI . defs ( ) ) if ( Def . isReg ( ) ) LoadDepRegs . set ( Def . getReg ( ) ) ; } for ( MachineInstr & MI : MBB ) { assert ( ! ( HardenLoadAddr . count ( & MI ) && HardenPostLoad . count ( & MI ) ) && <STR_LIT> ) ; if ( HardenLoadAddr . erase ( & MI ) ) { const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemRefBeginIdx = <STR_LIT> ( Desc . TSFlags ) ; assert ( MemRefBeginIdx >= <NUM_LIT> && <STR_LIT> ) ; MemRefBeginIdx += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = MI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; MachineOperand & IndexMO = MI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; hardenLoadAddr ( MI , BaseMO , IndexMO , AddrRegToHardenedReg ) ; continue ; } if ( HardenPostLoad . erase ( & MI ) ) { assert ( ! MI . isCall ( ) && <STR_LIT> ) ; if ( isDataInvariantLoad ( MI ) ) { MachineInstr * SunkMI = sinkPostLoadHardenedInst ( MI , HardenPostLoad ) ; if ( SunkMI != & MI ) { if ( ! SunkMI ) continue ; HardenPostLoad . insert ( SunkMI ) ; continue ; } } AddrRegToHardenedReg [ MI . getOperand ( <NUM_LIT> ) . getReg ( ) ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; hardenPostLoad ( MI ) ; continue ; } if ( ! MI . isCall ( ) ) continue ; if ( ! HardenInterprocedurally ) continue ; auto InsertPt = MI . getIterator ( ) ; DebugLoc Loc = MI .


<s> DebugLoc DL = AtomicNode -> getDebugLoc ( ) ; return DAG . getAtomic ( <STR_LIT> , DL , AtomicNode -> getMemoryVT ( ) , FenceOp . getOperand ( <NUM_LIT> ) , AtomicNode -> getOperand ( <NUM_LIT> ) , AtomicNode -> getOperand (

<NUM_LIT> ) , AtomicNode -> getMemOperand ( ) , Release , FenceScope ) ;


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT>


<s> O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ; O << <STR_LIT> << getFunctionNumber


<s> bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes == <NUM_LIT> ) return SDValue ( ) ; if ( CByte ) { uint64_t ByteVal = CByte -> getZExtValue ( ) ; if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && countPopulation ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; if ( CByte && CByte -> getZExtValue ( ) == <NUM_LIT> ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , Dst , Dst , Bytes ) ; Chain = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; SDValue DstPlus1 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , DstPlus1 , Dst ,


<s> MVT MaskVT = VT . changeTypeToInteger ( ) ; SDValue MaskNode ; MVT ShuffleVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { V1 = widenSubVector ( V1 , false , Subtarget , DAG , DL , <NUM_LIT> ) ; V2 = widenSubVector ( V2 , false , Subtarget , DAG , DL , <NUM_LIT> ) ; ShuffleVT = V1 . getSimpleValueType ( ) ; int NumElts = VT . getVectorNumElements ( ) ; unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > AdjustedMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : AdjustedMask ) if ( NumElts <= M ) M += ( Scale - <NUM_LIT> ) * NumElts ; MaskNode = getConstVector ( AdjustedMask , MaskVT , DAG , DL , true ) ; MaskNode = widenSubVector ( MaskNode , false , Subtarget , DAG , DL , <NUM_LIT> ) ; } else { MaskNode = getConstVector ( Mask , MaskVT , DAG , DL , true ) ; } SDValue


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode (


<s> std :: swap ( Idx1L , Idx1H ) ; } if ( Idx0L != <NUM_LIT> * i || Idx1L != <NUM_LIT> * i + <NUM_LIT> || Idx0H != <NUM_LIT> * i + <NUM_LIT> || Idx1H != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; if ( ! Mul ) { Mul = Op0L -> getOperand ( <NUM_LIT> ) ; if ( Mul -> getOpcode ( ) != <STR_LIT> || Mul . getValueType ( ) . getVectorNumElements ( ) != <NUM_LIT> * e ) return SDValue ( ) ; } if ( Mul != Op0L -> getOperand ( <NUM_LIT> ) || Mul != Op1L -> getOperand ( <NUM_LIT> ) || Mul != Op0H -> getOperand ( <NUM_LIT> ) || Mul != Op1H -> getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } ShrinkMode Mode ; if ( ! canReduceVMulWidth ( Mul . getNode ( ) , DAG , Mode ) || Mode == ShrinkMode :: MULU16 ) return SDValue ( ) ; auto PMADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { EVT InVT = Ops [ <NUM_LIT> ] . getValueType ( ) ; assert ( InVT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( InVT == Ops [ <NUM_LIT> ] . getValueType ( ) && <STR_LIT> ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) / <NUM_LIT> ) ; EVT TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand ( OpNum ) . getImm (


<s> bool Emitter < CodeEmitter > :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( )


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction &


<s> ShuffleMask . push_back ( <NUM_LIT> ) ; unsigned ZMask = Imm & <NUM_LIT> ; unsigned CountD = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned CountS = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned InVal = <NUM_LIT> + CountS ; ShuffleMask [ CountD ] = InVal ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ]


<s> unsigned getLength ( ) const { return CurType .


<s> return ( __m128i ) __builtin_ia32_vpconflictdi_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( )


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & SelectionDAGISel :: ID , <NUM_LIT> , false , false ) ; Registry . registerPass ( * PI , true


<s> return ( __m128i ) __builtin_ia32_pmovswb128_mask ( ( __v8hi )


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } uint64_t NegatedImm = ( ~ SplatBits ) . getZExtValue ( ) ; Val = isNEONModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMVNModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value = V ; else if ( V != Value ) usesOnlyOneValue = false ; } if ( ! Value . getNode ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( usesOnlyOneValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , & Ops [ <NUM_LIT> ] , NumElts ) ; Val = LowerBUILD_VECTOR ( Val , DAG


<s> machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi (


<s> for ( std :: list < bb_entry > :: const_iterator i = trace . bb_entries . begin ( ) ; i != trace . bb_entries . end ( ) ; ++ i ) { if ( i -> setcc . empty ( ) && i -> cstore . empty ( ) ) continue ; if ( i -> cstore . empty ( ) ) log_return ( false , <STR_LIT> ) ; if ( ! can_extend_ccreg_usage ( * i , trace ) ) return false ; if ( ! can_remove_cstore ( * i , trace ) && modified_in_p ( m_ccreg , i -> cstore . insn ) ) log_return ( false , <STR_LIT> ) ; } if ( cstore_count != <NUM_LIT> && inv_cstore_count != <NUM_LIT> ) { rtx_insn * i = make_inv_ccreg_insn ( ) ; if ( recog_memoized ( i ) < <NUM_LIT> ) { log_msg ( <STR_LIT> ) ; log_rtx ( PATTERN ( i ) ) ; log_return ( false , <STR_LIT> ) ; } } if ( dominating_cstore == cstore_normal && ! try_invert_branch_condition ( trace ) ) return false ; for ( std :: list < bb_entry > :: const_iterator i = trace . bb_entries . begin ( ) ; i != trace . bb_entries . end ( ) ; ++ i ) { if ( i -> cstore . empty ( )


<s> if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; return ; } if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isGlobal ( ) || MI -> getOperand ( opNum + <NUM_LIT> ) . isCPI ( ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT>


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace ) ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = Src -> getVectorNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost ( Instruction :: ExtractElement , Src , i ) ; return Cost


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = ArgLocs . size ( ) * <NUM_LIT> ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; return Chain


<s> SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } else { if ( Subtarget -> useMovt ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; }


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [

i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ;


<s> } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitEHSjLjLongJmp ( MachineInstr * MI , MachineBasicBlock * MBB ) const { DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP

) . addImm ( SPOffset ) . addReg ( BufReg ) ;


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumElts , DAG . getConstant ( VT . getScalarSizeInBits ( ) - <NUM_LIT> , SDLoc ( N ) , VT . getScalarType ( ) ) ) ; SDValue Val = DAG . getBuildVector ( VT , SDLoc ( N ) , Ops ) ; auto Shift = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CmpLHS , Val ) ; auto Or = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shift , N -> getOperand ( <NUM_LIT> ) ) ; return Or ; } } if ( N0 . getOpcode ( ) != <STR_LIT> || CCVT . getVectorElementCount ( ) != ElementCount :: getFixed ( <NUM_LIT> ) || CCVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return SDValue ( ) ; SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N )


<s> if ( regno >= FIRST_PSEUDO_REGISTER ) return INVALID_REGNUM ; if ( ! TEST_HARD_REG_BIT ( reg_class_contents [ CR_REGS


<s> if ( Subtarget -> hasFp256 ( ) ) { SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; } if ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) return SDValue ( ) ; assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , -


<s> p = <NUM_LIT> - __builtin_popcountl ( __M ) ; while ( m != <NUM_LIT> ) { c = __builtin_clzl ( m ) ; t = __X << ( p - c ) ; m ^= ( mask >>


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { using namespace <ISA_LIT> ; switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>ATTInstPrinter :: printLeaMemReference ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & BaseReg = MI -> getOperand ( Op ) ; const MCOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; O << * DispSpec . getExpr ( ) ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op , O ) ; if ( IndexReg . getReg (


<s> Value * StackPtr = ArgI ++ ; Value * StackSize = ArgI ++ ; Value * ArgC = ArgI ++ ; Value * ArgV = ArgI ++ ; Value * RSP = Builder -> CreatePtrToInt ( StackPtr , I64Ty ) ; RSP = Builder -> CreateAdd ( RSP , Builder -> CreateZExtOrBitCast ( StackSize , I64Ty ) ) ; RSP = Builder -> CreateSub ( RSP , Builder -> getInt64 ( <NUM_LIT> ) ) ; Builder -> CreateStore ( Builder -> getInt ( APInt :: getAllOnesValue ( <NUM_LIT> ) ) , Builder -> CreateIntToPtr ( RSP , I64Ty -> getPointerTo ( ) ) ) ; Idx [ <NUM_LIT> ] = Builder -> getInt32 ( RegOffsetsInSet [ RegLargestSupers [ <STR_LIT> ] ] ) ; Builder -> CreateStore ( RSP , Builder -> CreateInBoundsGEP ( Regset , Idx ) ) ; Idx [ <NUM_LIT> ] = Builder -> getInt32 ( RegOffsetsInSet [ RegLargestSupers [ <STR_LIT> ] ] ) ; Builder -> CreateStore ( Builder -> CreateZExt ( ArgC , Builder -> getInt64Ty ( ) ) , Builder -> CreateInBoundsGEP ( Regset , Idx ) ) ; Idx [ <NUM_LIT> ] = Builder -> getInt32 ( RegOffsetsInSet [ <STR_LIT> ] ) ; Builder -> CreateStore ( Builder -> CreatePtrToInt ( ArgV , Builder -> getInt64Ty ( ) ) , Builder -> CreateInBoundsGEP ( Regset , Idx ) ) ; Builder -> CreateRetVoid (


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return


<s> std :: make_unsigned_t < T > Val = MCE -> getValue ( ) ; uint64_t encoding = <STR_LIT> ( Val , sizeof ( T ) * <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( encoding )


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opc = Orig -> getOpcode ( ) ; if ( Opc == <STR_LIT> && ! isSafeToClobberEFLAGS ( MBB , I ) ) { DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else


<s> auto Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , { } ) ; if ( DestReg == DescribedReg ) return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcReg , false ) , Expr ) ; if ( unsigned SubRegIdx = TRI -> getSubRegIndex ( DestReg , DescribedReg ) ) { unsigned SrcSubReg = TRI -> getSubReg ( SrcReg


<s> return Kind == KindImm && inRange ( Imm ,


<s> Value * <ISA_LIT>IREmitter :: visitMOVLHPS ( const


<s> rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + <NUM_LIT> ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || ( aarch64_simd_decl_p ( cfun -> decl ) && FP_REGNUM_P ( regno ) ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; RTX_FRAME_RELATED_P ( insn )


<s> static DecodeStatus decodeBDVAddr12Operand ( MCInst & Inst , uint64_t Field , const unsigned * Regs ) { uint64_t Index = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ]


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true )


<s> if ( mode == V16SFmode || mode == V8DFmode ) emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP14 ) ) ) ; else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT (


<s> gen_zero_extend = gen_zero_extendqisi2 ; break ; case DImode : gen_divmod4_1 = signed_p ? gen_divmoddi4_1 : gen_udivmoddi4_1 ; gen_test_ccno_1 = gen_testdi_ccno_1 ; gen_zero_extend = gen_zero_extendqidi2 ; break ; default : gcc_unreachable ( ) ; } end_label = gen_label_rtx ( ) ; qimode_label = gen_label_rtx ( ) ; scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; scratch = expand_simple_binop ( mode , IOR , scratch , operands [ <NUM_LIT> ] , scratch , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_test_ccno_1 ( scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp0 = gen_rtx_EQ ( VOIDmode , tmp0 , const0_rtx ) ; tmp0 = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp0 , gen_rtx_LABEL_REF ( VOIDmode , qimode_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp0 ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = qimode_label ; div = gen_divmod4_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( div ) ; emit_jump_insn ( gen_jump ( end_label ) ) ; emit_barrier ( ) ; emit_label ( qimode_label ) ; tmp0 = simplify_gen_subreg ( HImode , scratch , mode , <NUM_LIT> ) ; tmp1 = simplify_gen_subreg ( HImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; tmp2 = simplify_gen_subreg ( QImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; emit_insn ( gen_udivmodhiqi3 ( tmp0 , tmp1 , tmp2 ) ) ; if ( signed_p ) { div = gen_rtx_DIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_MOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { div = gen_rtx_UDIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_UMOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } tmp1 = gen_rtx_ZERO_EXTRACT ( mode , tmp0 , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; if ( REG_P ( operands [ <NUM_LIT> ] ) ) insn = emit_move_insn ( operands [ <NUM_LIT> ] , tmp1 ) ; else { scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , tmp1 ) ; insn = emit_move_insn ( operands [ <NUM_LIT> ] , scratch ) ; } set_unique_reg_note ( insn ,


<s> Instr ( unsigned Opcode , unsigned Def , unsigned LHS , unsigned RHS ) : Opcode ( Opcode ) , Def ( Def ) , LHS ( LHS ) ,


<s> inline bool Pred_t2_so_imm ( SDNode * inN )


<s> if ( ! isMem ( ) ) return false ; if ( Mem . Mode != ImmediateOffset )


<s> MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const bool ArePtrs64bit = ABI . ArePtrs64bit ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; if ( Size == <NUM_LIT> ) { if ( isMicro<ISA_LIT> ) { LL = <STR_LIT> ; SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor (


<s> const unsigned AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return VectorSelectTbl [ Idx


<s> addr = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; } emit_move_insn ( temp , addr ) ; if ( offset ) temp = gen_rtx_PLUS ( Pmode , temp , offset ) ; x = gen_rtx_MEM ( DImode , temp ) ; } return x


<s> assert ( ( VT . is512BitVector ( ) || VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op . getNode ( ) ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems < <NUM_LIT> || ( NumElems == <NUM_LIT> && Subtarget . canExtendTo512DQ ( ) ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget .

hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ;


<s> case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) ; else if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI ,


<s> SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType


<s> } else if ( Advance ) { ++ Position ; ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else { TryMerge = true ; } if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( isThumb1 ? & <STR_LIT> : & <STR_LIT> ) ; RS -> forward ( std :: prev ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( std :: prev ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( std :: prev ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear ( ) ; NumMemOps =


<s> void <ISA_LIT>GNULDBackend :: emitRelocation ( llvm :: ELF :: Elf64_Rela & pRel , Relocation :: Type pType , uint32_t pSymIdx , uint64_t pOffset , int64_t pAddend ) const { uint64_t r_info = mcld :: bswap32 ( pType ) ; r_info <<= <NUM_LIT> ; r_info |= pSymIdx ; pRel . r_info


<s> assert ( isSimilarDispOp ( Op1 , Op2 ) && <STR_LIT> ) ; if ( Op1 . isJTI ( ) ) return <NUM_LIT> ; return Op1 . isImm ( ) ? Op1 . getImm ( ) - Op2 . getImm ( ) : Op1 .


<s> bool SelectAddrIdx ( SDValue N , SDValue & Base


<s> return ( int32x4_t ) __builtin_neon_vdup_nv4si ( ( __builtin_neon_si )


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } if ( Subtarget -> useMovt ( ) )


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) , DL ( getSubtargetImpl ( ) -> isTargetNaCl ( ) ? <STR_LIT> <STR_LIT> : ( getSubtargetImpl ( ) -> isTarget64BitILP32 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this


<s> return ! nds32_naked_function_p ( decl


<s> if ( Src -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = Src -> getVectorNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT>


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; unsigned opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue DivRem = DAG . getNode ( opc , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG .


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt

( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ;


<s> else append_name ( instance . mode_suffix ( ) . string ) ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ! overloaded_p || instance . shape -> explicit_type_suffix_p ( i ) ) append_name ( instance . type_suffix ( i ) . string ) ; append_name ( pred_suffixes [ instance . pred ] ) ; return finish_name (


<s> static enum arm_cond_code get_arm_condition_code ( rtx comparison ) { enum arm_cond_code code = maybe_get_arm_condition_code (


<s> __attribute__ ( ( __always_inline__ ) )


<s> return __builtin_mve_vldrwq_uv4si ( ( __builtin_neon_si *


<s> int size = int_size_in_bytes ( type ) ; if ( size <= <NUM_LIT> ) ++ cum -> words ; else if ( size <= <NUM_LIT> ) cum -> words += <NUM_LIT> ; else ++ cum -> words ; } else { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE (


<s> else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( ZeroReg ) MIB . addReg (


<s> static __inline qword si_dfms ( qword a , qword b , qword c ) { union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , cc , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] - cc . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] - cc . d [ <NUM_LIT> ] ; return ( ( qword ) ( dd


<s> inline bool wrapped_symbol_hasher :: equal ( const value_type * x , const


<s> } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> >= ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeUImm6 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } } uint64_t TSFlags = getInstDesc ( Inst . getOpcode


<s> if ( ! optimize || optimize_size ) return <NUM_LIT> ; do next = next_nonnote_insn ( next ) ; while ( next && LABEL_P ( next ) ) ; if ( ! next || ! INSN_P ( next ) || recog_memoized (

next ) == CODE_FOR_consttable_2 ) return <NUM_LIT> ;


<s> return ( __m64 ) __builtin_ia32_paddd ( ( __v2si ) __m1 , (


<s> off = build3 ( COMPONENT_REF , TREE_TYPE ( f_foff ) , unshare_expr ( valist ) , f_foff , NULL_TREE ) ; rsize = UNITS_PER_HWFPVALUE ; osize = MAX ( GET_MODE_SIZE ( TYPE_MODE ( type ) ) , UNITS_PER_WORD ) ; } else { top = build3 ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , unshare_expr ( valist ) , f_gtop , NULL_TREE ) ; off = build3 ( COMPONENT_REF , TREE_TYPE ( f_goff ) , unshare_expr ( valist ) , f_goff , NULL_TREE ) ; rsize = ( size + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD ; if ( rsize > UNITS_PER_WORD ) { t = build2 ( BIT_AND_EXPR , TREE_TYPE ( off ) , unshare_expr ( off ) , build_int_cst ( TREE_TYPE ( off ) , - rsize ) ) ; gimplify_assign ( unshare_expr ( off ) , t , pre_p ) ; } osize = rsize ; } t = build2 ( NE_EXPR , boolean_type_node , unshare_expr ( off ) , build_int_cst ( TREE_TYPE ( off ) , <NUM_LIT> ) ) ; addr = build3 ( COND_EXPR , ptr_type_node , t , NULL_TREE , NULL_TREE ) ; t = fold_convert ( TREE_TYPE ( off ) , build_int_cst ( NULL_TREE , rsize ) ) ; t = build2 ( POSTDECREMENT_EXPR , TREE_TYPE ( off ) , off , t ) ; t = fold_convert ( sizetype , t ) ; t = fold_build1 ( NEGATE_EXPR , sizetype , t ) ; t = fold_build_pointer_plus ( top , t ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) t = fold_build_pointer_plus_hwi ( t , rsize - size ) ; COND_EXPR_THEN ( addr ) = t ; if ( osize > UNITS_PER_WORD ) { t = fold_build_pointer_plus_hwi ( unshare_expr ( ovfl ) , osize - <NUM_LIT> ) ; u = build_int_cst ( TREE_TYPE ( t ) , - osize ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t


<s> bool isCortexR5 ( ) const { return <ISA_LIT>ProcFamily ==


<s> rtx hi = gen_highpart ( DImode , x ) ; rtx tmp = gen_reg_rtx ( V2DImode ) ; emit_insn ( gen_vec_concatv2di ( tmp , lo ,


<s> void <ISA_LIT>AsmPrinter :: printSavedRegsBitmask ( raw_ostream & O ) { unsigned CPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned i = <NUM_LIT> , e = CSI . size ( ) ; for ( ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register


<s> MachineBasicBlock & NewMBB = * MF . CreateMachineBasicBlock ( ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( & MBB ) ) , & NewMBB ) ; if ( Br ) { assert ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & Succ && <STR_LIT> ) ; Br -> getOperand ( <NUM_LIT> ) . setMBB ( & NewMBB ) ; if ( ! UncondBr ) { MachineBasicBlock & OldLayoutSucc = * std :: next ( MachineFunction :: iterator ( & NewMBB ) ) ; assert ( MBB . isSuccessor ( & OldLayoutSucc ) && <STR_LIT> <STR_LIT> ) ; auto BrBuilder = BuildMI ( & MBB , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( & OldLayoutSucc ) ; UncondBr = & * BrBuilder ; } if ( ! NewMBB . isLayoutSuccessor ( & Succ ) ) { SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII . insertBranch ( NewMBB , & Succ , nullptr , Cond , Br -> getDebugLoc ( ) ) ; } } else { assert ( ! UncondBr && <STR_LIT> ) ; assert ( NewMBB . isLayoutSuccessor ( & Succ ) &&


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt ::


<s> return ( __m128i ) __builtin_ia32_loaddquqi128_mask ( ( const char * ) __P , ( __v16qi ) __W ,


<s> if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg0 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfp_dscli_dd || icode == CODE_FOR_dfp_dscli_td || icode == CODE_FOR_dfp_dscri_dd || icode == CODE_FOR_dfp_dscri_td ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_crypto_vshasigmaw || icode == CODE_FOR_crypto_vshasigmad ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || wi :: geu_p ( wi :: to_wide ( arg1 ) , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || wi :: geu_p ( wi :: to_wide ( arg2 ) , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg


<s> unsigned CurrentSubReg = * SubRegIt ; unsigned EncVal = MCRegInfo -> getEncodingValue ( CurrentSubReg ) ; Value |= <NUM_LIT> << EncVal ; if ( GPR32RegClass -> contains ( CurrentSubReg ) || GPR64RegClass -> contains ( CurrentSubReg ) ) ri_gprmask |= Value ; else if ( FGR32RegClass -> contains ( CurrentSubReg ) || FGR64RegClass -> contains ( CurrentSubReg ) || AFGR64RegClass -> contains ( CurrentSubReg ) ||

MSA128BRegClass -> contains ( CurrentSubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ;


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; }


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( )


<s> if ( d -> vmode != V4HImode || d -> one_operand_p ) return false ; if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { perm2 [ i ] = d -> perm [ i ] & <NUM_LIT> ; rmask [ i ] = ( d -> perm [ i ] & <NUM_LIT> ? const0_rtx : constm1_rtx ) ; } mask = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( <NUM_LIT> , rmask ) ) ; mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0


<s> BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent ( ) ; return BB


<s> return __builtin_mve_vqrdmulhq_n_sv4si ( __a ,


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT FromVT , EVT ToVT ) const { if ( ! FromVT . isInteger ( ) || ! ToVT . isInteger (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , DL ( computeDataLayout ( TargetTriple ) ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( )


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( )


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> vaddlv_u16 ( uint16x4_t a ) { uint32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand (


<s> SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return St


<s> MCObjectWriter * createObjectWriter ( raw_ostream &


<s> final_emit_insn_group_barriers ( dump ) ; bundling ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; if ( sched_verbose && dump ) fprintf ( dump , <STR_LIT> , INSN_UID ( NEXT_INSN ( current_sched_info -> prev_head ) ) , INSN_UID ( PREV_INSN ( current_sched_info


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI


<s> void <ISA_LIT>AsmPrinter :: printAddrMode4Operand ( const MachineInstr * MI , int Op , const char * Modifier ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM


<s> if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( ImmVal ) ) ; return Success


<s> if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && ! isDispSafeForFrameIndex ( Val ) ) return true ; } AM . Disp


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( )


<s> unsigned & OpIdx = NumOpsAdded ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx = <NUM_LIT> ; unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> void <ISA_LIT>InstrInfo :: getNoopForMachoTarget ( MCInst


<s> return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains


<s> if ( TargetTriple . getOS ( ) == llvm :: Triple :: FreeBSD ) return <STR_LIT> ; else return <STR_LIT> ; } return is<ISA_LIT>64 ( ) ?


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB ,


<s> BranchOffset = SignExtend32 < <NUM_LIT> > ( BranchOffset << <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm (


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > (


<s> if ( useSVEForFixedLengthVectorVT ( Op . getValueType ( ) ) ) return LowerFixedLengthInsertVectorElt ( Op , DAG ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT

== <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ;


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const mcld :: Target & pTarget , const std :: string & pTriple ) { return new DWARFLineInfo


<s> int64_t getFrameAdjustment ( const MachineInstr & I ) const { assert ( isFrameInstr ( I ) ) ; if ( isFrameSetup ( I ) ) return I . getOperand ( <NUM_LIT> ) . getImm ( ) ; return I . getOperand ( <NUM_LIT> ) . getImm