<s> static inline unsigned isImmPCRel ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - GPRCS1Size ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - GPRCS2Size ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - DPRCSSize ) ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes ) ; if ( HasFP ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; } AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( needsStackRealignment ( MF ) ) { unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ; if ( ! AFI -> isThumbFunction ( ) ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ,


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( ! AsmPrinter . OutStreamer . hasRawTextSupport ( ) ) Opcode = getShortenedInstr ( Opcode ) ; OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands


<s> int in_toc_section ( void ) \ { \ return in_section


<s> } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { return Error ( L , <STR_LIT> ) ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleHardFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleMT ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleCRC ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleNoCRC ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option ==


<s> } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> void <ISA_LIT>Subtarget :: SetJITMode


SplitTy , OrigArg . Flags , OrigArg . IsFixed ) ;


<s> Type * ArgTy = Type :: getInt32Ty ( Ctx ) ; StructType * RetTy = StructType :: get ( Ctx , { ArgTy , ArgTy } , true ) ; auto RetVal = MRI . createGenericVirtualRegister ( getLLTForType ( * RetTy , MIRBuilder . getMF ( ) . getDataLayout ( ) ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall , { RetVal , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; MIRBuilder . buildUnmerge ( { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , OriginalResult } , RetVal ) ; break ; } case G_FCMP : { assert ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && <STR_LIT> ) ; auto OpSize = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; auto OriginalResult = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Predicate = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto Libcalls = getFCmpLibcalls ( Predicate , OpSize ) ; if ( Libcalls . empty ( ) ) { assert ( ( Predicate == CmpInst :: FCMP_TRUE || Predicate == CmpInst :: FCMP_FALSE ) && <STR_LIT> ) ; MIRBuilder . buildConstant ( OriginalResult , Predicate == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } auto & Ctx = MIRBuilder . getMF ( ) . getFunction ( ) -> getContext ( ) ; assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < unsigned , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI

. createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ;


<s> return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn


<s> return __builtin_aarch64_floatdihf ( __a )


<s> static bool isLowerSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT> CC , const SDValue K ) { return ( isGTorGE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == RHS && K == TrueVal ) || (


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type (


<s> tree idp ; rtx rtlname , newrtl ; rtx symref ; rtlname = XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; if ( i386_pe_dllexport_name_p ( oldname ) ) { error ( <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ) ; return ; } else if ( i386_pe_dllimport_name_p ( oldname ) ) { gcc_assert ( DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && DECL_DLLIMPORT_P ( decl ) ) ; return ; } newname = alloca ( strlen ( DLL_IMPORT_PREFIX ) + strlen ( oldname ) + <NUM_LIT>


<s> int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> &&


<s> if ( ! mmix_shiftable_wyde_value ( value ) ) { char s [ <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ] ; sprintf ( s , HOST_WIDEST_INT_PRINT_HEX , value ) ; internal_error ( <STR_LIT> , s ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT>


<s> SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O


<s> const Value * LHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * RHS = CI -> getOperand ( <NUM_LIT> ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * RHSC = dyn_cast < ConstantFP > ( RHS ) ; if ( RHSC && RHSC -> isNullValue ( ) ) RHS = LHS ; } static const uint16_t SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get

( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ;


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ in_section = in_sdata ; \ fprintf ( asm_out_file , <STR_LIT>


<s> if ( MO . isCPI ( ) ) return true ; if ( MO . isGlobal ( ) ) return isGVStub ( MO . getGlobal ( ) , TM ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex ( ) ; return MFI . isFixedObjectIndex ( Idx ) && MFI . isImmutableObjectIndex ( Idx ) ; } } return


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getSubtarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align )


<s> __rint64x ( double __a ) { return __builtin_aarch64_frint64xdf (


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList


<s> switch ( i & <NUM_LIT> ) { case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT>


<s> enum x86_64_reg_class alt_classes [ MAX_CLASSES ] ; zero_width_bitfields = <NUM_LIT> ; if ( classify_argument ( mode , type , alt_classes , bit_offset , zero_width_bitfields ) != n ) zero_width_bitfields = <NUM_LIT> ; else for ( int i = <NUM_LIT> ; i < n ; i ++ ) if ( classes [ i ] != alt_classes [ i ] ) { zero_width_bitfields = <NUM_LIT> ; break ; } if ( zero_width_bitfields == <NUM_LIT>


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT>

, <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> const TargetRegisterClass * RC = is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned PtrReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Shift1Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm (


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind )


<s> static void printMemReference ( <ISA_LIT>AsmPrinter & P , const MachineInstr * MI , unsigned Op , raw_ostream & O , const char * Modifier = nullptr ) { assert ( isMem ( MI , Op ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( Op + <STR_LIT> ) ; if ( Segment . getReg (


<s> } const char * RegName = getRegisterName ( RegNo ) ; if ( ! Subtarget . isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O <<


<s> const AsmToken & Tok = Parser . getTok ( ) ; std :: string LowerID = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = parseOptionalToken ( AsmToken :: Hash ) ; if ( ! Hash && getLexer ( ) . isNot ( AsmToken :: Integer ) ) { if ( ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateShiftExtend ( ShOp , <NUM_LIT> , false , S , E , getContext ( ) ) ) ; return MatchOperand_Success


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getGPR64Reg ( )


<s> SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , NumExtracts ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind (


<s> unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . getOpcode ( ) == TargetInstrInfo :: INLINEASM ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetInstrInfo :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC )


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) ->


<s> if ( target_parts ) targ_options = TREE_TARGET_OPTION ( target_parts ) ; else targ_options = TREE_TARGET_OPTION ( target_option_current_node ) ; gcc_assert ( targ_options ) ; arm_print_asm_arch_directives ( stream , targ_options ) ; fprintf ( stream , <STR_LIT> ) ; if ( TARGET_THUMB ) { if ( is_called_in_ARM_mode ( decl ) || ( TARGET_THUMB1 && ! TARGET_THUMB1_ONLY && cfun -> is_thunk ) ) fprintf ( stream , <STR_LIT> ) ; else if ( TARGET_THUMB1 ) fprintf ( stream , <STR_LIT> ) ; else fprintf ( stream , <STR_LIT> ) ; } else fprintf ( stream ,


<s> TargetLowering :: ArgListTy Args = getDivRemArgList ( N , DAG . getContext ( ) ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; CallLoweringInfo CLI ( DAG ) ; CLI . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) . setDebugLoc ( SDLoc ( N ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDNode * ResNode = CallResult . first . getNode ( ) ; assert ( ResNode -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; return ResNode -> getOperand ( <NUM_LIT>


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE ->


<s> bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG

. getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; if ( InMicro<ISA_LIT>Mode && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler = CurrI ; return true ; } return


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfoELF ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true )


<s> static bool mmix_print_operand_punct_valid_p ( unsigned char


<s> bool <ISA_LIT>ELFObjectWriter :: needsRelocateWithSymbol ( unsigned Type ) const { switch ( Type ) { default : return true ; case ELF


<s> if ( Name == <STR_LIT> ) return getATReg ( ) ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; if ( is<ISA_LIT>64 ( ) && <NUM_LIT> <= CC && CC <= <NUM_LIT> ) CC += <NUM_LIT> ; if ( CC == - <NUM_LIT> && is<ISA_LIT>64 ( ) ) CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> case 'f' : case 'v' : return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] == 'r' ) return RegName + <NUM_LIT> ; } return RegName


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi (


<s> return ( ( qword ) ( vec_cmpeq ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateToken ( StringRef Str , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand


<s> static int getEquivalentCallShort ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> assert ( ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetAndroid ( ) ) && <STR_LIT> ) ; unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl (


<s> EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CPN = dyn_cast < ConstantPointerNull > ( C ) ) { ( void ) CPN ; assert ( CPN -> getType ( ) -> getPointerAddressSpace ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return materializeInt ( ConstantInt :: get ( Type :: getInt64Ty ( * Context ) , <NUM_LIT> ) ,


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = vecWidth / ElVT . getSizeInBits


<s> bool isXRaySupported ( ) const override { return true


<s> return __arm_vqrshrntq_n_u32 ( __a ,


<s> static bool ia64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( reg_classes_intersect_p ( rclass , BR_REGS ) ) return from == to ; if ( SCALAR_FLOAT_MODE_P ( from ) != SCALAR_FLOAT_MODE_P ( to ) ) return ! reg_classes_intersect_p ( rclass , FR_REGS ) ; return true


<s> BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT> ; continue ; } } uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -=


<s> return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == <NUM_LIT> || ImmVal == <NUM_LIT> ) return TTI :: TCC_Free ; } ImmIdx = <NUM_LIT> ; break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt


<s> if ( MO . isImm ( ) ) { uint64_t Imm = MO . getImm ( ) ; Imm -= Offset ; Imm &= ( <NUM_LIT> << Bits ) - <NUM_LIT> ; Imm += Offset ; O << formatImm ( Imm ) ; return ; } printOperand ( MI , opNum ,


<s> static bool isMul ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> return Opc == <STR_LIT> || isT2i32Load ( Opc


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fallMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , fallMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MachineRegisterInfo & MRI = MF


<s> ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( checkDenormalAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , DenormalMode :: getPreserveSign ( ) ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( checkDenormalAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , DenormalMode :: getPositiveZero ( ) ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else { if ( ! STI . hasVFP2Base ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3Base ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . NoTrappingFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( STI . isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( MMI ) { if ( const Module * SourceModule =


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( STI . isTargetNaCl (


<s> struct ix86_address addr ; if ( ! TARGET_TLS_DIRECT_SEG_REFS ) return orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( ix86_decompose_address ( x , & addr ) == <NUM_LIT> || addr . seg != DEFAULT_TLS_SEG_REG || addr . disp == NULL_RTX || GET_CODE ( addr . disp ) != CONST ) return orig_x ; unspec = XEXP ( addr . disp , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) == PLUS && CONST_INT_P ( XEXP ( unspec , <NUM_LIT> ) ) ) unspec =


<s> return __builtin_mve_vabdq_uv4si ( __a ,


<s> bool hasDivideIn<ISA_LIT>Mode ( ) const { return


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ; } } } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e

; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ;


<s> if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) mips_prepare_builtin_arg ( & ops [ opno ++


<s> bool ThumbRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) { return false


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; } if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ,


<s> for ( first_reg = <NUM_LIT> + <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg


<s> if ( SDValue Folded = foldCSELofCTTZ ( N , DAG ) ) return Folded ; return performCONDCombine ( N , DCI , DAG ,


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( getThe<ISA_LIT>elTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( getThe<ISA_LIT>64elTarget ( ) ) ; PassRegistry * PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>DelaySlotFillerPass ( *


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ,


<s> HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX =


<s> static __inline vec_double2 spu_msub ( vec_double2 a , vec_double2 b , vec_double2 c ) { return ( ( vec_double2 ) ( si_dfms ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) (


<s> setRequiredFeatureString ( IC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( IC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * DC = <STR_LIT> ( Op ) ; if ( ! DC ) return TokError ( <STR_LIT> ) ; else if ( ! DC -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( DC -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( DC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( DC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * AT = <STR_LIT> ( Op ) ; if ( ! AT ) return TokError ( <STR_LIT> ) ; else if ( ! AT -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( AT -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( AT -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ?


<s> MachineInstr * replaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII ->

get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ;


<s> rtx_vector_builder v ( mode , nelts , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < nelts ; i ++ ) { rtx x = builder . elt ( i + nelts_reqd - n_trailing_constants ) ; if ( ! valid_for_const_vector_p ( elem_mode , x ) ) x = const0_rtx ; v . quick_push ( x ) ; } rtx const_vec = v . build ( ) ; emit_move_insn ( target , const_vec


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) { if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) PM -> add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID


<s> Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ; } AM =


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi


<s> enum { COFF = ( <NUM_LIT> << MCObjectFileInfo :: IsCOFF ) , ELF = ( <NUM_LIT> << MCObjectFileInfo :: IsELF ) , MACHO = ( <NUM_LIT> << MCObjectFileInfo :: IsMachO ) , OMF = ( <NUM_LIT> << MCObjectFileInfo :: IsOMF ) , WASM = ( <NUM_LIT> << MCObjectFileInfo :: IsWasm ) , } ; static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) ,


<s> assert ( ( Succ -> empty ( ) || ! Succ -> begin ( ) -> isPHI ( ) ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( llvm :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP


<s> PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = false ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS =


<s> if ( ! has_0f_opcode || has_vex_w ) return <NUM_LIT> + <NUM_LIT> ; if ( ! TARGET_64BIT ) return <NUM_LIT> + <NUM_LIT> ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return <NUM_LIT> + <NUM_LIT> ; } else { if ( MEM_P ( recog_data . operand [ i ] ) && x86_extended_reg_mentioned_p ( recog_data . operand [ i


<s> static bool AreSequentialAccesses ( MemInst * MemOp0 , MemInst * MemOp1 , const DataLayout & DL , ScalarEvolution & SE ) { if ( isConsecutiveAccess ( MemOp0 , MemOp1 , DL , SE ) ) return true ; return


<s> asm_fprintf ( asm_out_file , <STR_LIT> , to_print . c_str ( ) ) ; aarch64_last_printed_arch_string = to_print ; } const struct processor * this_tune = aarch64_get_tune_cpu ( targ_options -> x_explicit_tune_core ) ; if ( flag_debug_asm && aarch64_last_printed_tune_string != this_tune -> name ) { asm_fprintf ( asm_out_file , <STR_LIT> ASM_COMMENT_START <STR_LIT> , this_tune -> name ) ; aarch64_last_printed_tune_string = this_tune -> name ; } ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( stream , name


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses


<s> unsigned <STR_LIT> ( Type * Ty ) const { return


<s> if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget .


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT> && <STR_LIT> ) ; const MachineConstantPoolEntry & CPE = MCP -> getConstants ( ) [ CPI ] ; assert ( ! CPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; Offset = - cast < ConstantInt > ( CPE . Val . ConstVal ) -> getSExtValue ( ) ; break ; } } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) { if ( DstReg == FramePtr && FramePtr != <STR_LIT> ) ATS .

emitSetFP ( FramePtr , <STR_LIT> , - Offset ) ;


<s> static bool finishStackBlock ( SmallVectorImpl < CCValAssign > & PendingMembers , MVT LocVT , <STR_LIT> & ArgFlags , CCState & State , Align SlotAlign ) { unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; const Align StackAlign = State . getMachineFunction ( ) . getDataLayout ( ) . getStackAlignment ( ) ; const Align OrigAlign = ArgFlags . getNonZeroOrigAlign ( ) ; const Align Alignment = std :: min ( OrigAlign , StackAlign


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMt ( ) ; Parser . Lex


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> printOperand ( MI , opNum , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( ! MO . isImm ( ) || MO . getImm ( ) != <NUM_LIT> ) { printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; } O <<


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * LoopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * DoneMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; ++ MFI ; MF -> insert ( MFI , LoopMBB ) ; MF -> insert ( MFI , DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> begin ( ) , MBB , MI , MBB -> end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; unsigned ValReg = MRI . createVirtualRegister ( ValueRC ) ; unsigned UpdReg = ( Opcode ? MRI . createVirtualRegister ( ValueRC ) : Rs2Reg ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , ValReg ) . addReg ( Val0Reg ) . addMBB ( MBB ) . addReg ( DestReg ) . addMBB ( LoopMBB ) ; if ( CondCode ) { BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ValReg ) . addReg ( Rs2Reg ) ; BuildMI ( LoopMBB , DL , TII . get ( Opcode ) , UpdReg ) . addReg ( ValReg ) . addReg ( Rs2Reg ) . addImm ( CondCode ) ; } else if ( Opcode ) { BuildMI ( LoopMBB , DL , TII . get ( Opcode ) , UpdReg ) . addReg ( ValReg ) . addReg ( Rs2Reg ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned TmpReg =


<s> return ( uint8x8_t ) __builtin_neon_vqadduv8qi ( ( int8x8_t )


<s> if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; gcc_assert ( NONDEBUG_INSN_P ( def_insn ) ) ; unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link ->


<s> if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; return DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool IsFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char


<s> rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < <NUM_LIT> ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode ,


<s> uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM256 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_REL8 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset


<s> ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( DAG . getEntryNode ( ) , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; return CallResult . first ; } SDValue Offset ; if ( GV -> isDeclaration ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; }


<s> return isLegalMaskedLoadStore ( DataType ,


<s> vld3q_s16 ( const int16_t * __a ) { int16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi (


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return true


<s> if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_DEC ) ) ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( ind , <NUM_LIT> ) ) ) ind = XEXP ( ind , <NUM_LIT> ) ; int factor = MIN ( GET_MODE_SIZE ( GET_MODE ( op ) ) , <NUM_LIT> ) ; if ( GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && IN_RANGE ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) , - <NUM_LIT> * factor , <NUM_LIT> * factor ) && ( INTVAL (

XEXP ( ind , <NUM_LIT> ) ) & ( factor - <NUM_LIT> ) ) == <NUM_LIT> ) return TRUE ;


<s> if ( TARGET_64BIT ) for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) if (

TEST_HARD_REG_BIT ( regs_live , i ) && ! call_used_regs [ i ] ) return ;


<s> bool targetHandlesStackFrameRounding ( ) const override { return true


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef Cpu , StringRef FeatureString , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CodeModel , CodeGenOpt :: Level OptLevel , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( ) , TT , Cpu , FeatureString , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CodeModel ) , OptLevel ) , Subtarget ( TT , Cpu , FeatureString , * this , Options , getCodeModel ( ) , OptLevel ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) { initAsmInfo (


<s> void setSRetReturnReg ( unsigned Reg ) { SRetReturnReg =


<s> if ( using_mfcr_multiple && count > <NUM_LIT> ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( r , <NUM_LIT> ) = reg ; RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } else for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) ,


<s> } if ( ! GV -> isThreadLocal ( ) ) return false ; if ( ! TM ) return true ; TLSModel :: Model Model = TM -> getTLSModel ( GV ) ; return Model == TLSModel :: GeneralDynamic || Model == TLSModel


<s> __builtin_altivec_dstt ( ( void * ) a1


<s> bool hasMacroFusion ( ) const { return


<s> buildCFAOffs ( InsMBB , InsPt , DL , SPOffsetFromCFA , ZII ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( InsMBB , InsPt , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( Size - <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } ; bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; MachineBasicBlock * DoneMBB = nullptr ; MachineBasicBlock * LoopMBB = nullptr ; if ( NumFullBlocks < <NUM_LIT> ) { for ( unsigned int i = <NUM_LIT> ; i < NumFullBlocks ; i ++ ) allocateAndProbe ( * MBB , MBBI , ProbeSize , true ) ; } else { uint64_t LoopAlloc = ProbeSize * NumFullBlocks ; SPOffsetFromCFA -= LoopAlloc ; BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; buildDefCFAReg ( * MBB , MBBI , DL , <STR_LIT> , ZII ) ; emitIncrement ( * MBB , MBBI , DL , <STR_LIT> , - int64_t ( LoopAlloc ) , ZII ) ; buildCFAOffs ( * MBB , MBBI , DL , - int64_t ( <STR_LIT> + LoopAlloc ) , ZII ) ; DoneMBB = <STR_LIT> ( MBBI , MBB ) ; LoopMBB = <STR_LIT> ( MBB ) ; MBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MBB = LoopMBB ; allocateAndProbe ( * MBB , MBB -> end ( ) , ProbeSize , false ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( MBB ) ; MBB = DoneMBB ; MBBI = DoneMBB -> begin ( ) ; buildDefCFAReg ( * MBB , MBBI , DL , <STR_LIT> , ZII ) ; } if ( Residual ) allocateAndProbe ( * MBB , MBBI , Residual , true ) ; if ( StoreBackchain ) BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( getBackchainOffset ( MF ) ) . addReg ( <NUM_LIT> ) ; StackAllocMI -> eraseFromParent ( ) ; if ( DoneMBB !=


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) .


<s> const AsmToken & Tok = getTok ( ) ; SMLoc S = getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned PStateImm = - <NUM_LIT> ; const auto * SVCR = <STR_LIT> ( Tok . getString


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> switch ( code ) { case OPT_mabi_ : if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_32 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_O64 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi


<s> Op -> ISBOpt . Val = Opt ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


PM . add ( createThumb2ITBlockPass ( ) ) ;


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ; MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; return static_cast < <ISA_LIT>TargetStreamer & >


<s> SVEIntrinsicOpts ( ) : ModulePass ( ID ) { initializeSVEIntrinsicOptsPass ( * PassRegistry :: getPassRegistry (


<s> return & InstrInfo . getRegisterInfo


<s> gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; base = ( REGNO ( operands [ <NUM_LIT> ] ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; i ++ ) { p += sprintf ( & pattern [ p ] , <STR_LIT> , base + i ) ; } strcpy ( & pattern [ p ] , <STR_LIT> ) ; output_asm_insn ( pattern , operands


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> output_quoted_string ( stream , name ) ; putc ( '\n' , stream ) ; } else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ; fprintf ( stream , <STR_LIT> ,


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV ,


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == <NUM_LIT> ) { return true ; } return


<s> bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF |


<s> return ( __m128 ) __builtin_ia32_cmpltps ( ( __v4sf ) __A , ( __v4sf )


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { const GlobalValue * GV = & Alias ; if ( ! GV -> hasDLLExportStorageClass ( ) ) continue ; while ( const GlobalAlias * A = dyn_cast < GlobalAlias > ( GV ) ) GV = A -> getAliasedGlobal ( ) ; if ( isa < Function > ( GV ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else if ( isa < GlobalVariable > ( GV ) ) DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals )

GenerateExportDirective ( Symbol , true ) ;


<s> static bool isIndirectBranchOpcode ( int Opc ) { using namespace llvm :: <ISA_LIT> ; ( Opc == NAME ## ari || Opc == NAME ## ari_nt || Opc == NAME ## ari_t ) assert ( ! BRKIND ( BCFW ) && ! BRKIND ( BCFD ) && ! BRKIND ( BCFS ) && <STR_LIT> ) ; return BRKIND (


<s> static void init_enabled_abi_types ( ) { enabled_abi_types [ DEFAULT_ABI_BASE ] [ DEFAULT_ABI_EXT ] = <NUM_LIT> ; int abi_base , abi_ext ; for ( unsigned int i = <NUM_LIT> ; i < MULTILIB_LIST_LEN ; i ++ ) { abi_base = tm_multilib_list [ i << <NUM_LIT> ] ; abi_ext = tm_multilib_list [ ( i


<s> MachineBasicBlock * TBB = <NUM_LIT> , * FBB = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; SmallVector < MachineOperand , <NUM_LIT> > CondPrior ; MachineFunction :: iterator BBi = BB ; MachineFunction :: iterator OldPrior = prior ( BBi ) ; bool B = TII -> AnalyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != MF -> begin ( ) && ! TII -> AnalyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor


<s> struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( link -> ref


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { unsigned NumElems = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT>


<s> if ( Val - <NUM_LIT> == <NUM_LIT> * i ) { Odd = true ; continue ; } Odd = false ; Even = false ; break ; } if ( Even || Odd ) { SDValue LHS = DAG . getNode ( <STR_LIT> , dl , VT , SDValue ( Vector , <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , dl , VT , SDValue ( Vector , <NUM_LIT> ) , DAG . getConstant ( NumElts , dl , <STR_LIT> ) ) ; if ( Even && ! Odd ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; if ( Odd && ! Even ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; } } if ( usesOnlyOneValue ) { if ( ! isConstant ) { if ( Value . getOpcode ( ) != <STR_LIT> || Value . getValueType ( ) != VT ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; } SDValue Lane = Value . getOperand ( <NUM_LIT> ) ; Value = Value . getOperand ( <NUM_LIT> ) ; if ( Value . getValueSizeInBits ( ) == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; Value = WidenVector ( Value , DAG ) ; } unsigned Opcode = getDUPLANEOp ( VT . getVectorElementType ( ) ) ; return DAG . getNode ( Opcode , dl , VT , Value , Lane ) ; } if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; EVT EltTy = VT . getVectorElementType ( ) ; assert ( ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; MVT NewType = <STR_LIT> ( EltTy . getSizeInBits ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , NewType , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , NewType , NumElts ) ; SDValue Val = DAG . getBuildVector ( VecVT , dl , Ops ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Val . dump ( ) ; ) ; Val = LowerBUILD_VECTOR ( Val , DAG ) ; if ( Val . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } } bool PreferDUPAndInsert = ! isConstant && NumDifferentLanes >= <NUM_LIT> && NumDifferentLanes < ( ( NumElts - NumUndefLanes )

/ <NUM_LIT> ) && NumDifferentLanes >= NumConstantLanes ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Align MemAlign = getKnownAlignment ( II . getArgOperand ( <NUM_LIT> ) , IC . getDataLayout ( ) , & II , & IC . getAssumptionCache ( ) , & IC . getDominatorTree ( ) ) ; unsigned AlignArg = II . getNumArgOperands ( ) - <NUM_LIT> ; Value * AlignArgOp = II . getArgOperand ( AlignArg ) ; MaybeAlign Align = cast < ConstantInt > ( AlignArgOp ) -> getMaybeAlignValue ( ) ; if ( Align && * Align < MemAlign ) { return IC . replaceOperand ( II , AlignArg , ConstantInt :: get ( Type :: getInt32Ty ( II . getContext ( ) ) , MemAlign . value ( ) , false ) ) ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } Constant * XorMask ; if ( match ( Arg , m_Xor ( PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) , PatternMatch :: m_Constant ( XorMask ) ) ) && II . getType ( ) == ArgArg -> getType ( ) ) { if ( auto * CI = dyn_cast < ConstantInt > ( XorMask ) ) { if ( CI -> getValue ( ) . trunc ( <NUM_LIT> ) . isAllOnesValue ( ) ) { auto TrueVector = IC . Builder . CreateVectorSplat ( cast < FixedVectorType > ( II . getType ( ) ) -> getNumElements ( ) , IC . Builder . getTrue ( ) ) ; return BinaryOperator :: Create ( Instruction :: Xor , ArgArg , TrueVector ) ; } } } KnownBits ScalarKnown ( <NUM_LIT> ) ; if ( IC . SimplifyDemandedBits ( & II , <NUM_LIT> , APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) , ScalarKnown , <NUM_LIT> ) ) { return & II ; } break ; } case <STR_LIT> : { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } if ( ! II . getMetadata ( LLVMContext


<s> NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NewIsUnscaled = true ; break ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . addOperand ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( )


, reload_fenv , restore_fnenv ) , update_call ) ;


<s> return ( vector signed short ) __builtin_altivec_vpkpx ( ( vector signed int ) a1 , ( vector signed int )


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { StringRef WinEHParentName = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( WinEHParentName != F . getName ( ) && ! WinEHParentName . empty ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; if ( WinEHParentName . empty ( ) ) { bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; } F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH : addSEHStateStores ( F , FuncInfo ) ; break ; } PersonalityFn = nullptr ; Personality = EHPersonality ::


<s> * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; * ( ( intptr_t * ) RelocPos ) |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { * ( ( intptr_t * ) RelocPos ) |= ( intptr_t ) ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; ResultPtr = ( ResultPtr & <NUM_LIT> ) >> <NUM_LIT> ; assert ( ResultPtr >= - <NUM_LIT> && ResultPtr <= <NUM_LIT> ) ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr & <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr


<s> unsigned LL = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned SC = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AlignedAddr = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned OldVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal0 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned SllRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT>


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; JTI = ( ( <ISA_LIT>BaseTargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF )


<s> opts -> x_rs6000_isa_flags = ptr -> x_rs6000_isa_flags ; opts -> x_rs6000_isa_flags_explicit = ptr -> x_rs6000_isa_flags_explicit ; ( void ) rs6000_option_override_internal (


<s> int SpReg = <NUM_LIT> ; rs . enterBasicBlock ( MBB ) ; rs . forward ( II ) ; BitVector Candidates = RI . getAllocatableSet ( * II -> getParent ( ) -> getParent ( ) , & <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } int DefReg = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { DefReg = MO . getReg ( ) ; break ; } } BitVector Available = rs . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; unsigned FirstRegSaved = <NUM_LIT> , SecondRegSaved = <NUM_LIT> ; unsigned FirstRegSavedTo = <NUM_LIT> , SecondRegSavedTo = <NUM_LIT> ; Reg = Available . find_first ( ) ; if ( Reg == - <NUM_LIT> ) { Reg = Candidates . find_first ( ) ; Candidates . reset ( Reg ) ; if ( DefReg != Reg ) { FirstRegSaved = Reg ; FirstRegSavedTo = <STR_LIT> ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } } else Available . reset ( Reg ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Imm ) . addImm ( - <NUM_LIT> ) ; NewImm = <NUM_LIT> ; if ( FrameReg == <STR_LIT> ) { SpReg = Available . find_first ( ) ; if ( SpReg == -


<s> if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT ) ) return SDValue ( ) ; break ; } SmallVector < SDValue , <NUM_LIT> > LHSElts , RHSElts ; for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; if ( RHS . getValueSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { if ( ! IsShift ) return SDValue ( ) ; RHS = DAG . getZExtOrTrunc ( RHS , DL , VT . getScalarType ( ) ) ; } LHSElts . push_back ( LHS )


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg


<s> static MCSymbol * GetAnonSym ( MCSymbol * Sym , MCContext &


<s> } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t )


<s> do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> case <STR_LIT> : { unsigned OpOffset = <STR_LIT> ( Desc . TSFlags ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { default : if ( ( Desc . TSFlags & <STR_LIT> ) == <STR_LIT> ) break ; return false ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; } return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> + OpOffset , <NUM_LIT> + OpOffset ) ; } case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( needsStackRealignment ( MF ) ) return true ; if ( MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ; } return false


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty (


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int RegNo = - <NUM_LIT> ; RegNo = tryParseRegister ( Mnemonic ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return


<s> DebugLoc dl = N . getDebugLoc ( ) ; if ( SelectAddressRegReg ( N , Disp , Base , DAG ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm