<s> SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast < GlobalAddressSDNode > ( Op ) ; auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstantPool (

CPV , PtrVT , <NUM_LIT> ) ) , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size ,


<s> if ( VT . isFloatingPoint ( ) && ! IsFixedLength ) { if ( PassThru ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; PassThru = getSVESafeBitCast ( PassThruVT , PassThru , DAG ) ; } InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( IndexVT , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , true , DAG ) ; if ( ExtTy == <STR_LIT> ) Opcode = getSignExtendedGatherOpcode ( Opcode ) ; if ( IsFixedLength ) { if ( Index . getSimpleValueType ( ) . isFixedLengthVector ( ) ) Index = convertToScalableVector ( DAG , IndexVT , Index ) ; if ( BasePtr . getSimpleValueType ( ) . isFixedLengthVector ( ) ) BasePtr = convertToScalableVector ( DAG , IndexVT , BasePtr ) ; Mask = convertFixedMaskToScalableVector ( Mask , DAG ) ; } SDValue Ops [ ] = { Chain , Mask , BasePtr , Index , InputVT } ; SDValue Result = DAG . getNode ( Opcode , DL , VTs , Ops ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( IsFixedLength ) { Result = convertFromScalableVector ( DAG , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Result ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Result ) ; Result = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( parseRegister ( Reg ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( Reg . StartLoc , Reg . EndLoc ) ) ; return false ; } SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; Register Reg1 , Reg2 ; bool HaveReg1 , HaveReg2 ; const MCExpr * Expr ; const MCExpr * Length ; if ( parseAddress ( HaveReg1 , Reg1 , HaveReg2 , Reg2 , Expr , Length , true , true ) ) return true ; if ( HaveReg1 && Reg1 . Group != RegGR && Reg1 . Group != RegV && parseAddressRegister ( Reg1 ) ) return true ; if ( HaveReg2 && parseAddressRegister (


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_PLT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCHI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCLO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFHI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFLO


<s> enum machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode


<s> if ( isThumb1Only ( ) ) return <NUM_LIT> ; if ( isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> return ( ( qword ) ( vec_xor ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar ( b


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst


<s> if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [


<s> static DecodeStatus DecodeThumbBCCTargetOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Val <<


<s> return __builtin_aarch64_ld1v4sf ( ( const __builtin_aarch64_simd_sf


<s> static MCOperand createPCXCallOP ( MCSymbol * Label


<s> quotient = __divdi3 ( a , b ) ; * remainder = a - b *


<s> if ( Size >= <NUM_LIT> && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == <NUM_LIT> || DstAlign >= <NUM_LIT> ) && ( SrcAlign == <NUM_LIT> || SrcAlign >= <NUM_LIT> ) ) ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> hasAVX2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasAVX ( ) ) return <STR_LIT> ; } if ( Subtarget -> hasSSE2


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { auto & MBB = * MI . getParent ( ) ; auto DL = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: LOAD_STACK_GUARD : { assert ( Subtarget . isTargetLinux ( ) && <STR_LIT> ) ; const int64_t Offset = Subtarget . is<ISA_LIT>64 ( ) ? - <NUM_LIT> : - <NUM_LIT> ; const unsigned Reg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Offset ) . addReg ( Reg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && isAnImmediateOperand ( MI . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasVSX ( )


<s> if ( MO . isImm ( ) ) O << ( unsigned short


<s> case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } const bool IsWrite = MII . get ( Inst . getOpcode ( ) ) . mayStore ( ) ; for ( unsigned Ix = <NUM_LIT> ; Ix < Operands . size ( ) ; ++ Ix ) { assert ( Operands [ Ix ] ) ; MCParsedAsmOperand & Op = * Operands [ Ix ] ; if ( Op . isMem (


<s> return helper_sign_extend ( ( ( ( pTarget >> <NUM_LIT> ) ) & <NUM_LIT> ) |


<s> unsigned <ISA_LIT>InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned & NewImm ) const { llvm_unreachable ( <STR_LIT>


<s> if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_GOT_DISP : case SYMBOL_TLSGD


<s> MCFragment * <ISA_LIT>MCExpr :: findAssociatedFragment


<s> static unsigned getRegisterWidth ( const MCOperandInfo & Info ) { if ( Info . RegClass == <STR_LIT> || Info . RegClass == <STR_LIT> ) return <NUM_LIT> ; if ( Info . RegClass == <STR_LIT> ||


<s> static std :: string computeDataLayout ( const <ISA_LIT>Subtarget & ST ) { std :: string Ret = <STR_LIT> ; if ( ST . isLittle ( ) )


<s> SmallVector < int , <NUM_LIT> > ScaledMask ; int Scale = NumSrcElts / Mask . size ( ) ; scaleShuffleMask < int > ( Scale , Mask , ScaledMask ) ; Mask = std :: move ( ScaledMask ) ; } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { int ExtractIdx = ( int ) N -> getConstantOperandVal ( <NUM_LIT> ) ; int Scale = Mask . size ( ) / NumSrcElts ; int Lo = Scale * ExtractIdx ; int Hi = Scale * ( ExtractIdx + <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = ( int ) Mask . size ( ) ; i != e ; ++ i ) if ( i < Lo || Hi <= i ) Mask [ i ] = SM_SentinelUndef ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { assert ( VT . getSizeInBits ( ) >= SrcSVT .


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI


<s> MF = & Func ; TM = & Func . getTarget ( ) ; const <ISA_LIT>Subtarget & ST = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM -> getInstrInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return


<s> Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( )


<s> if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> -> begin


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return false


<s> unsigned <ISA_LIT>ConstantIslands :: GetOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( isThumb && MI -> getOpcode ( ) == <STR_LIT> && ( Offset % <NUM_LIT> != <NUM_LIT> || HasInlineAsm ) ) Offset += <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin


<s> case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; default : break ; } if ( ! Opc ) return false ; MachineIRBuilder MIB ( I ) ; auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) . addImm ( * LaneIdx ) ; constrainSelectedInstRegOperands ( * Dup , TII , TRI ,


<s> int32_t ImmValue = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmValue , Loc ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; VTs . push_back ( N -> getValueType ( <NUM_LIT> ) ) ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , VTs , Ops ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New ,


<s> auto * CNode = dyn_cast < ConstantPoolSDNode > ( Ptr ) ; if ( ! CNode || CNode -> isMachineConstantPoolEntry ( ) || CNode -> getOffset ( ) != <NUM_LIT> ) return nullptr ; return CNode -> getConstVal


<s> RxSBGOperands RxSBG [ ] = { RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) , RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) } ; unsigned Count [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) while ( expandRxSBG ( RxSBG [ I ] ) ) Count [ I ] += <NUM_LIT> ; if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return <NUM_LIT> ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { convertTo ( SDLoc ( N ) , <STR_LIT> , Op0 ) , convertTo ( SDLoc ( N ) , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue


<s> if ( ! DoMerge ) return false ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { int Offset = AddSub == <STR_LIT> ? - Bytes : Bytes ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { int Offset = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } } else { int Offset = AddSub == <STR_LIT> ? - Bytes : Bytes ; BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState


<s> assert ( ( ! UndefLower || ! isUndefUpperHalf ( Mask ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfNumElts = NumElts / <NUM_LIT> ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , HalfNumElts ) ; if ( ! UndefLower && isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfNumElts , HalfNumElts ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( UndefLower && isSequentialOrUndefInRange ( Mask , HalfNumElts , HalfNumElts , <NUM_LIT> ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; } int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( HalfNumElts ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) ) return SDValue ( ) ; assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; unsigned NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; unsigned NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; assert ( NumLowerHalves + NumUpperHalves <= <NUM_LIT> && <STR_LIT> ) ; unsigned EltWidth = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! UndefLower ) { if ( NumUpperHalves == <NUM_LIT> ) return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) ) { if ( EltWidth == <NUM_LIT> && NumLowerHalves && HalfVT . is128BitVector ( ) && !

is128BitUnpackShuffleMask ( HalfMask ) ) return SDValue ( ) ;


<s> ITBlocks [ IT ] . insert ( & MI ) ; Predicates [ & MI ] = IT ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > DeadITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Killed ; RDA -> collectLocalKilledOperands ( Def , Killed ) ; for ( auto * MI : Killed ) { if ( ! Predicates . count ( MI ) ) continue ; MachineInstr * IT = Predicates [ MI ] ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( MI ) ; ModifiedITs . insert ( IT ) ; if ( CurrentBlock . empty ( ) ) { DeadITs . insert ( IT ) ; ModifiedITs . erase ( IT ) ; } } if ( ModifiedITs . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * MI : Killed ) dbgs ( ) << <STR_LIT> << * MI ; for ( auto * MI : DeadITs ) dbgs ( ) << <STR_LIT> <<


<s> r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( dst , r


<s> MachineInstr * ChkStkStub = nullptr ; for ( MachineInstr & MI : PrologMBB ) { if ( MI . isCall ( ) && MI . getOperand ( <NUM_LIT> ) . isSymbol ( ) && ChkStkStubSymbol == MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ) { ChkStkStub = &


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG


<s> } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { return false ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> )


<s> bool IsMasked = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; IsMasked = true ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? <STR_LIT> : <STR_LIT> ; return true


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr (

MI , OS ) ) printInstruction ( MI , OS ) ;


<s> if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ; auto SelectOpcode = VT . isVector ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( SelectOpcode , DL , VT , IsOp0Nan , Op1 ,


<s> bool inverted ; switch ( code ) { case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case NE : code = reverse_condition_maybe_unordered ( code ) ; if ( ! can_invert ) { rtx tmp = gen_reg_rtx ( cmp_result_mode ) ; if ( arm_expand_vector_compare ( tmp , code , op0 , op1 , true ) ) gcc_unreachable ( ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( cmp_result_mode , tmp ) ) ) ; return false ; } inverted = true ; break ; default : inverted = false ; break ; } switch ( code ) { case LE : case LT : if ( op1 != CONST0_RTX ( cmp_mode ) ) { code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; } case EQ : case GE : case GT : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , op1 ) ) ; return inverted ; case GEU : case GTU : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; return inverted ; case LEU : case LTU : emit_insn ( gen_neon_vc ( swap_condition ( code ) , cmp_mode , target , force_reg ( cmp_mode , op1 ) , op0 ) ) ; return inverted ; case LTGT : case ORDERED : { rtx gt_res = gen_reg_rtx (


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { assert ( Encoding == DW_EH_PE_absptr && <STR_LIT>


<s> return __builtin_shuffle ( a , ( uint32x2_t ) { <NUM_LIT> ,


<s> if ( Opc == <STR_LIT> ) ShiftAmt = ElementType . getSizeInBits ( ) - <NUM_LIT> ; else return DAG . getConstant ( <NUM_LIT> , VT ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; if ( VT == SrcOp . getSimpleValueType ( ) && <STR_LIT> ( SrcOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Elts ; unsigned NumElts = SrcOp -> getNumOperands ( ) ; ConstantSDNode * ND ; switch ( Opc ) { default : llvm_unreachable ( <NUM_LIT> ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt


<s> int ix86_atom_sched_reorder ( FILE * dump , int sched_verbose , rtx_insn * * ready , int * pn_ready , int clock_var ) { int issue_rate = - <NUM_LIT> ; int n_ready = * pn_ready ; int i ; rtx_insn * insn ; int index = - <NUM_LIT> ; issue_rate = ix86_issue_rate ( ) ; if ( ! TARGET_CPU_P ( BONNELL ) && ! TARGET_CPU_P ( SILVERMONT ) && ! TARGET_CPU_P ( INTEL ) ) return issue_rate ; if ( n_ready <= <NUM_LIT> ) return issue_rate ; if ( ! reload_completed ) return issue_rate ; if ( ( index = do_reorder_for_imul ( ready , n_ready ) ) >= <NUM_LIT> ) { if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , INSN_UID ( ready [ index ] ) ) ; insn = ready [ index ]


<s> StringRef getPassName ( ) const override { return AARCH64_TYPE_PROMO_NAME


<s> unsigned <ISA_LIT>RegisterInfo :: getPtrSizedStackRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register StackReg = getStackRegister ( ) ; if ( Subtarget . isTarget64BitILP32 ( ) ) StackReg =

get<ISA_LIT>SubSuperRegister ( StackReg , <NUM_LIT> ) ;


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op ,


<s> <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer


<s> if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) != Pred2 [ <NUM_LIT> ] . getReg ( ) ) return false ; <STR_LIT> P1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> P2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( P1 == P2 ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; return false


<s> MF -> push_back ( BB ) ; const Align MaxAlign = MCP -> getConstantPoolAlign ( ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : Align ( <NUM_LIT> ) ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( Log2 ( MaxAlign ) + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; Align Alignment = CPs [ i ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ; unsigned LogAlign = Log2 ( Alignment ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] / Size == Input && Mask [ i ] % Size != i ) return false ; return true


<s> if ( Subtarget -> isTargetELF ( ) ) { auto & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ;


<s> int SlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , FPDiff - SlotSize ) ; EVT VT = Is64Bit ?


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty ( ) && <STR_LIT> ) ; Chain = CallInfo


<s> if ( GET_CODE ( body ) != PARALLEL ) return <NUM_LIT> ; rtx set = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( set ) == SET && MEM_P ( SET_DEST (


<s> if ( STI . getCPU ( ) == <STR_LIT> ) return <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; else if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) && STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; else if ( STI . hasFeature (


<s> unsigned HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( LoReg , HiReg ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . storeRegToStack ( MBB , I , HiReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI , <NUM_LIT> ) ; return true ; } return


<s> std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; std :: string LocalName = <STR_LIT> + Name ; Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; std :: string


<s> inline void getAddressOperands ( <ISA_LIT>ISelAddressMode & AM , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp ,


<s> void PreAnalyzeCallResult ( const SmallVectorImpl < <STR_LIT> > & Ins , CCAssignFn Fn , const Type * RetTy , const char * Func ) { OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear


<s> return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_SUB ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_DISP ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_GD


<s> bool hasInvariantFunctionDescriptors ( ) const { return HasInvariantFunctionDescriptors


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT>

) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ;


<s> if ( F . hasExternalLinkage ( ) && F . getName ( )

== <STR_LIT> ) emitSpecialCodeForMain ( ) ;


<s> void Note ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Note ( L , Msg ,


<s> return ( ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ( ! call_used_regs [ reg ] || ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC ) )

) || ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != <NUM_LIT> ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) ) ) ) ;


<s> return ( __m512d ) __builtin_ia32_cvtqq2pd512_mask ( ( __v8di ) __A , (


<s> if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , TargetFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , TargetFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , TargetFlags ) ; } else { Result = getAddr ( GN , DAG , TargetFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode

( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . add ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent (


<s> static const unsigned RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State


<s> if ( isDarwinABI || is<ISA_LIT>64 ) return <NUM_LIT> * ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT>


<s> EVT VT = Value . getValueType ( ) ; if ( ( VT == <STR_LIT> ) || SD -> isTruncatingStore ( ) ) { SDValue SWL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateStoreLR ( <STR_LIT> , DAG , SD , SWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } assert ( VT == <STR_LIT> ) ; SDValue SDL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain


<s> Amount = alignTo ( Amount , getStackAlign ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t MulAmt = C -> getZExtValue ( ) ; if ( isPowerOf2_64 ( MulAmt ) || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> ) return SDValue ( ) ; uint64_t MulAmt1 = <NUM_LIT> ; uint64_t MulAmt2 = <NUM_LIT> ; if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { DebugLoc DL = N -> getDebugLoc ( ) ; if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode

( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ;


<s> unsigned int i ; state = data ; if ( REG_P ( x ) ) for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS ( REGNO ( x ) , GET_MODE


<s> MachineInstr & MI = * I ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> )


<s> if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; if ( InMicro<ISA_LIT>Mode && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode


<s> void <ISA_LIT>InstPrinter :: printNamedOpOrImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid


<s> lowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , Size ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Val = Load ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getConstant ( <NUM_LIT> - MemVT . getSizeInBits ( ) , dl , <STR_LIT> ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant


<s> const unsigned SafeReg64 = <STR_LIT> ; if ( HideSandboxBase ) { if ( ( Reg32 != SafeReg32 ) && ( Reg32 != SafeReg64 ) ) { MCInst MOVInst ; MOVInst . setOpcode ( <STR_LIT> ) ; MOVInst . addOperand ( MCOperand :: CreateReg ( SafeReg32 ) ) ; MOVInst . addOperand ( MCOperand :: CreateReg ( Reg32 ) ) ; Out . EmitInstruction ( MOVInst ) ; Reg32 = SafeReg32 ; } } const unsigned Reg64 = get<ISA_LIT>SubSuperRegister_ ( Reg32 , <STR_LIT> ) ; MCSymbol * RetTarget = NULL ; if ( IsCall && HideSandboxBase ) { MCContext & Context = Out . getContext ( ) ; RetTarget = CreateTempLabel ( Context , <STR_LIT> ) ; const MCExpr * RetTargetExpr = MCSymbolRefExpr :: Create ( RetTarget , Context ) ; MCInst PUSHInst ; PUSHInst . setOpcode ( <STR_LIT> ) ; PUSHInst . addOperand ( MCOperand :: CreateExpr ( RetTargetExpr


<s> void arm_asm_declare_function_name ( FILE * file , const char * name , tree decl ) { size_t cmse_name_len ; char * cmse_name = <NUM_LIT> ; char cmse_prefix [ ] = <STR_LIT> ; if ( use_cmse && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) { cmse_name_len = sizeof ( cmse_prefix ) + strlen ( name ) ; cmse_name = XALLOCAVEC ( char , cmse_name_len ) ; snprintf ( cmse_name , cmse_name_len , <STR_LIT> , cmse_prefix , name


<s> case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MTCR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addImm ( Imm1 ) . addImm


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count == <NUM_LIT> ) { return true


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ;


<s> void emitTCEntry ( const MCSymbol & S , MCSymbolRefExpr :: VariantKind Kind ) override { const MCAsmInfo * MAI = Streamer . getContext


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { <ISA_LIT>ISelAddressMode AM ; if ( MatchAddress ( N , AM )


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static bool isConjunctionDisjunctionTree ( const SDValue Val , unsigned Depth ) { if ( ! Val . hasOneUse ( ) ) return false ; if ( Val -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Depth > <NUM_LIT> ) return


<s> if ( II && ( ( II -> getIntrinsicID ( ) == <STR_LIT> ) || II -> getIntrinsicID ( ) == <STR_LIT> ) ) return false ; if ( PtrValue -> getType ( ) -> getPointerElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { const SCEV * LSCEV = SE -> getSCEVAtScope ( const_cast < Value * > ( PtrValue ) , L ) ; const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LARSCEV || LARSCEV -> getLoop ( ) != L ) return false ; if ( const SCEVConstant * StepConst = dyn_cast < SCEVConstant > ( LARSCEV -> getStepRecurrence ( * SE ) ) ) { const APInt & ConstInt = StepConst -> getValue ( ) -> getValue ( ) ; if ( ConstInt . isSignedIntN ( <NUM_LIT> ) && ConstInt . srem ( <NUM_LIT> ) != <NUM_LIT> ) return false ; } } return true ; } ; auto isDSFormCandidate = [ ] ( const Instruction * I , const Value * PtrValue ) { assert ( ( PtrValue && I ) && <STR_LIT> ) ; if ( isa < IntrinsicInst > ( I ) ) return false ; Type * PointerElementType = PtrValue -> getType ( ) -> getPointerElementType ( ) ; return ( PointerElementType -> isIntegerTy ( <NUM_LIT> ) ) || ( PointerElementType -> isFloatTy ( ) ) || ( PointerElementType -> isDoubleTy ( ) ) || ( PointerElementType -> isIntegerTy ( <NUM_LIT> ) && llvm :: any_of ( I -> users ( ) , [ ] ( const User * U ) { return isa < SExtInst > ( U ) ; } ) ) ; } ; auto isDQFormCandidate = [ & ] ( const Instruction * I , const Value * PtrValue ) { assert ( ( PtrValue && I ) && <STR_LIT> ) ; auto * II = dyn_cast < IntrinsicInst > ( I ) ; if ( II ) return II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ; return ST && ST -> hasP9Vector ( ) && ( PtrValue -> getType ( ) -> getPointerElementType ( ) -> isVectorTy ( ) ) ; } ; SmallVector < Bucket , <NUM_LIT> > UpdateFormBuckets = collectCandidates ( L , isUpdateFormCandidate , MaxVarsUpdateForm ) ; if ( ! UpdateFormBuckets . empty ( ) ) MadeChange |= updateFormPrep (


<s> } else if ( type == long_long_unsigned_type_node || type == long_long_integer_type_node ) error ( <STR_LIT> ) ; else if ( type == double_type_node ) error ( <STR_LIT> ) ; else if ( type == long_double_type_node ) error ( <STR_LIT> ) ; else if ( type == boolean_type_node ) error ( <STR_LIT> ) ; else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) error ( <STR_LIT> ) ; switch ( altivec_type ) { case 'v' : unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case SFmode : result = V4SF_type_node ; break ; case V4SImode : case V8HImode : case V16QImode : case V4SFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case SImode : case V4SImode : result = bool_V4SI_type_node ; break ; case HImode : case V8HImode : result = bool_V8HI_type_node ; break ; case QImode : case V16QImode : result = bool_V16QI_type_node ; default : break


<s> bool useMachineCombiner ( ) const override { return true


<s> if ( SubregToRegMI ) Imm &= <NUM_LIT> ; OpcodePair Opcode ; if ( auto R = SplitAndOpc ( Imm , RegSize , Imm0 , Imm1 ) ) Opcode = R . getValue ( ) ; else return false ; MachineFunction * MF = MI . getMF ( ) ; const TargetRegisterClass * FirstInstrDstRC = TII -> getRegClass ( TII -> get ( Opcode . first ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * FirstInstrOperandRC = TII -> getRegClass ( TII -> get ( Opcode . first ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * SecondInstrDstRC = ( Opcode . first == Opcode . second ) ? FirstInstrDstRC : TII -> getRegClass ( TII -> get ( Opcode . second ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * SecondInstrOperandRC = ( Opcode . first == Opcode . second ) ? FirstInstrOperandRC : TII -> getRegClass ( TII -> get ( Opcode . second ) , <NUM_LIT> , TRI , * MF ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewTmpReg = MRI ->

createVirtualRegister ( FirstInstrDstRC ) ;


<s> set_optab_libfunc ( sub_optab , mode , NULL ) ; set_optab_libfunc ( eq_optab , mode , NULL ) ; set_optab_libfunc ( ne_optab , mode , NULL ) ; set_optab_libfunc ( lt_optab , mode , NULL ) ; set_optab_libfunc ( le_optab , mode , NULL ) ; set_optab_libfunc ( ge_optab , mode , NULL ) ; set_optab_libfunc ( gt_optab , mode , NULL ) ; set_optab_libfunc ( unord_optab , mode , NULL


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned InsertPSMask ; if ( ! matchVectorShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( InsertPSMask , DL


<s> unsigned ExtractNum = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , OpLHS , OpLHS , DAG .

getConstant ( ExtractNum , <STR_LIT> ) ) ;


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer -> EmitLabel


<s> static bool isUnpackWdShuffleMask ( ArrayRef < int > Mask , MVT VT ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; SmallVector < int ,


<s> bool isMemVX32X ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg (


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg (


<s> if ( cast < StoreInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand >


<s> Type * PointerElementType ; if ( LoadInst * LMemI = dyn_cast < LoadInst > ( & J ) ) { PtrValue = LMemI -> getPointerOperand ( ) ; PointerElementType = LMemI -> getType ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( & J ) ) { PtrValue = SMemI -> getPointerOperand ( ) ; PointerElementType = SMemI -> getValueOperand ( ) -> getType ( ) ; } else if ( IntrinsicInst * IMemI = dyn_cast < IntrinsicInst > ( & J ) ) { PointerElementType = Type :: getInt8Ty ( J


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand (


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else


<s> assert ( ( Ext != <STR_LIT> || NumLoads == <NUM_LIT> ) && <STR_LIT> ) ; unsigned loadRegZize = RegSz ; if ( Ext == <STR_LIT> && RegSz >= <NUM_LIT> ) loadRegZize = <NUM_LIT> ; EVT LoadUnitVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclrLoadTy , loadRegZize / SclrLoadTy . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , loadRegZize / MemVT . getScalarSizeInBits ( ) ) ; assert ( WideVecVT . getSizeInBits ( ) == LoadUnitVecVT . getSizeInBits ( ) && <STR_LIT> ) ; assert ( TLI . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( SclrLoadTy . getSizeInBits ( ) / <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Res = DAG . getUNDEF ( LoadUnitVecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; Chains . push_back ( ScalarLoad . getValue ( <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; else Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , Res , ScalarLoad , DAG . getIntPtrConstant ( i , dl ) ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chains ) ; SDValue SlicedVec = DAG . getBitcast ( WideVecVT , Res ) ; unsigned SizeRatio = RegSz / MemSz ; if ( Ext == <STR_LIT> ) { if ( Subtarget . hasSSE41 ( ) ) { SDValue Sext = DAG . getNode ( <STR_LIT> , dl , RegVT , SlicedVec ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> )


<s> EmitFrames ( nullptr ) ; MCWinCOFFStreamer :: FinishImpl (


<s> sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes +


<s> __attribute__ ( ( __always_inline__ ) )


<s> ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; return ret


<s> unsigned OpNum = <NUM_LIT> ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc != <STR_LIT> ) { OpNum = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } MI . getOperand ( OpNum ) . setMBB (


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; SpillsVRS = true ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineBasicBlock * MBB = MBBI . getNode ( ) -> getBlock ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { unsigned Reg ; const Value * Entry ; if ( ! isCallViaRegister ( * I , Reg , Entry ) ) continue ; Changed =


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT>


<s> if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT>


<s> if ( isShiftedMask_32 ( Val ) ) { MB = CountLeadingZeros_32 ( Val ) ; ME = CountLeadingZeros_32 ( ( Val - <NUM_LIT> ) ^ Val ) ; return true ; } else { Val = ~


<s> unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = ABI . GetStackPtr ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( MFI -> hasVarSizedObjects ( ) && ! MFI -> isFixedObjectIndex ( FrameIndex ) ) FrameReg = ABI . GetBasePtr ( ) ; else if ( MFI -> isFixedObjectIndex ( FrameIndex ) ) FrameReg = getFrameRegister ( MF ) ; else FrameReg = ABI . GetStackPtr ( ) ; } else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg =


<s> if ( GET_CODE ( PATTERN ( in_insn ) ) == UNSPEC_VOLATILE ) return false ; return ! store_data_bypass_p ( out_insn


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm )


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC ; if ( Subtarget . isABI_N64 ( ) ) RC = ( const TargetRegisterClass * ) & <STR_LIT> ; else RC = ( const TargetRegisterClass * ) & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; if ( Subtarget . isABI_N64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget . isABI_N32 ( ) ) { const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg


<s> TerminatorInfo <ISA_LIT>LongBranch :: describeTerminator ( MachineInstr & MI ) { TerminatorInfo Terminator ; Terminator . Size = TII -> getInstSizeInBytes ( MI ) ; if ( MI . isConditionalBranch ( ) || MI . isUnconditionalBranch ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT>


<s> size_t <ISA_LIT>TargetELFStreamer :: calculateContentSize ( ) const { size_t Result = <NUM_LIT> ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; switch ( item . Type ) { case AttributeItem :: HiddenAttribute : break ; case AttributeItem :: NumericAttribute : Result += getULEB128Size ( item . Tag ) ; Result += getULEB128Size ( item . IntValue ) ; break ; case AttributeItem :: TextAttribute : Result += getULEB128Size ( item . Tag ) ; Result += item . StringValue . size ( ) + <NUM_LIT> ; break ; case AttributeItem :: NumericAndTextAttributes : Result += getULEB128Size ( item . Tag ) ; Result += getULEB128Size ( item . IntValue ) ; Result += item . StringValue . size ( )


<s> ParallelMAC ( Instruction * I , ValueList & V ) : Mul ( I )


<s> fprintf ( defines_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i < num_ovld_stanzas ; i ++ ) if ( strcmp ( ovld_stanzas [ i ] . extern_name , <STR_LIT> ) ) { if ( ovld_stanzas [ i ] . ifdef ) fprintf ( defines_file , <STR_LIT> , ovld_stanzas [ i ] . ifdef ) ; fprintf ( defines_file , <STR_LIT> , ovld_stanzas [ i ] . extern_name , ovld_stanzas [ i ] . intern_name ) ; if ( ovld_stanzas [ i ] . ifdef ) fprintf ( defines_file , <STR_LIT> ) ; } fprintf ( defines_file ,


<s> Mode = TargetSubtarget :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; return OptLevel >= CodeGenOpt


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT>

, Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


<s> if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . UnrollAndJam


<s> if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) && ! useConstPool ( ) ) UseMovt = true ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) )

|| ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( Subtarget . isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = Subtarget . is64Bit ( ) ? Subtarget . getRegisterInfo ( ) -> getDarwinTLSCallPreservedMask ( ) : Subtarget . getRegisterInfo ( ) -> getCallPreservedMask ( * F , CallingConv :: C ) ; if ( Subtarget . is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( !


<s> static void addImplySP ( MCInst & Inst , int64_t


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) { return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getBitcast ( <STR_LIT> , N1 ) ) ) ; } if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask


<s> if ( speed ) goto performance_cost ; else goto size_cost ; performance_cost : switch ( code ) { case SET : return false ; case USE : * total = <NUM_LIT> ; break ; case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; default : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } return true ; size_cost : switch ( code ) { case SET : return false ; case USE : * total = <NUM_LIT> ; break ; case CONST_INT : if ( outer_code ==


<s> default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT>


<s> static SDValue combineAndnp ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT . isVector ( ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF ) { tpsym = operands [ <NUM_LIT> ] ; n = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] ) , t == 'b' ? UNS_TPREL : UNS_GPREL ) ; n = gen_rtx_CONST ( mode , n ) ; } else if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { tpsym = XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; tpoffs = XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; n = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , tpsym ) , t == 'b' ? UNS_TPREL : UNS_GPREL ) ; n = gen_rtx_PLUS ( mode , n , tpoffs ) ; n = gen_rtx_CONST ( mode , n ) ; } else if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == UNSPEC ) return false ; else { error ( <STR_LIT> ) ; return false ; } n = gen_rtx_PLUS ( mode , ( t == 'b' ? mep_tp_rtx ( ) : mep_gp_rtx ( ) ) , n ) ; n = emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , n ) ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( n ) ; return true ; } } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { t = mep_section_tag ( operands [ i ] ) ; if ( GET_CODE ( operands [ i ] ) == MEM && ( t == 'b' || t == 't' ) ) { rtx sym , n , r ; int u ; sym = XEXP ( operands [ i ] , <NUM_LIT> ) ; if ( GET_CODE ( sym ) == CONST && GET_CODE ( XEXP ( sym , <NUM_LIT> ) ) == UNSPEC ) sym = XVECEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( t == 'b' )


<s> static SDValue combineFMADDSUB ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NegVal = isFNEG ( DAG , N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! NegVal ) return SDValue ( ) ; unsigned NewOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits


<s> ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; data -> ifetch_block_len


<s> LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! SelectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD , <NUM_LIT>


<s> uint64_t Imm = cast < const ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; uint64_t MSB = cast < const ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; APInt OpUsefulBits ( UsefulBits ) ; OpUsefulBits = <NUM_LIT> ; APInt ResultUsefulBits ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; ResultUsefulBits . flipAllBits ( ) ; APInt Mask ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; getUsefulBits ( Op , ResultUsefulBits ,


<s> return ( uint8x8_t ) __builtin_neon_vmvnv8qi ( ( int8x8_t


<s> case Instruction :: BitCast : { return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; } case Instruction :: IntToPtr : { if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: PtrToInt : { if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( const StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB )

&& isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) {


<s> assert ( Scale < <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Base , Offset ; unsigned Opc ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Base , Offset , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ; ReplaceUses ( SDValue ( N , ChainIdx ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; assert ( MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) && <STR_LIT> ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI .


<s> static bool readsLocalId ( const IntrinsicInst * II ) { switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT>


<s> return __builtin_neon_vfmsl_highv4sf ( __r ,


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm ,


<s> default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file


<s> op = gen_rtx_SET ( dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( code == NOT ) emit_insn ( op ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob ) ) ) ; } if ( dst != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ]


<s> return ( long long ) __builtin_ia32_vcvttsd2si64 ( (


<s> SDValue Odd0 = DAG . getVectorShuffle ( VT , dl , Op0 , Op0 , Mask ) ; SDValue Odd1 = DAG . getVectorShuffle ( VT , dl , Op1 , Op1 , Mask ) ; MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget . hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } SDValue In = Move . getOperand ( <NUM_LIT> ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; uint64_t TSFlags = getInstrInfo ( ) -> get ( In . getMachineOpcode ( ) ) . TSFlags ; if ( ( TSFlags & <STR_LIT> ) != <STR_LIT> && ( TSFlags & <STR_LIT> )

!= <STR_LIT> && ( TSFlags & <STR_LIT> ) != <STR_LIT> ) continue ;


<s> static bool loongarch_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p (


<s> MachineInstr * MI = MBBI ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; int Opcode = MI -> getOpcode ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isAM4 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool DoMerge = false ; <STR_LIT> Mode = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( isAM4 ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; } assert ( ! <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { assert ( ! <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Offset = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( isAM4 ) { if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; Mode = <STR_LIT> ; } else if ( isAM4 && Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; Mode = <STR_LIT> ; } } else { if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( isAM4 ) { if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge =


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> .


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { if ( STI . hasE2 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( DestReg < <STR_LIT> ) ; assert ( DestReg < <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( SrcReg , RegState :: Define ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , Flag ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; unsigned PtrSize = PtrVT . getSizeInBits ( ) ; IntegerType * PtrTy = Type :: getIntNTy ( * DAG . getContext ( ) , PtrSize ) ; SDValue TlsGetAddr = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = PtrTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , PtrTy , TlsGetAddr , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT>


<s> } unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForceAllBaseRegAlloc ) return true ; break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) && canRealignStack ( MF ) ) ) { if ( isFrameOffsetLegal ( MI , FPOffset )


<s> const BlockAddress * BA = BASDN -> getBlockAddress ( ) ; if ( Subtarget . is64BitELFABI ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , SDLoc ( BASDN ) , GA ) ; } if ( Subtarget . is32BitELFABI ( ) && isPositionIndependent ( ) ) return getTOCEntry ( DAG , SDLoc ( BASDN ) , DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ) ; unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> ,


<s> bool hasVFP2Base ( ) const { return HasVFPv2D16SP


<s> case <STR_LIT> : Type = ELF :: R_AARCH64_JUMP26 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_CALL26 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSDESC_ADR_PAGE ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_8 : return ELF :: R_AARCH64_ABS64 ; case FK_Data_4 : return ELF :: R_AARCH64_ABS32 ; case FK_Data_2 : return ELF :: R_AARCH64_ABS16 ; case <STR_LIT> : Type = ELF :: R_AARCH64_ADD_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LD64_GOT_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LDST8_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LDST16_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LDST32_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LDST64_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_LDST128_ABS_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G0 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G0_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G1 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G1_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G2 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G2_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_UABS_G3 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_SABS_G0 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_SABS_G1 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_MOVW_SABS_G2 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G2 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G1 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G0 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_ADD_DTPREL_LO12 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 ; break ; case <STR_LIT> : Type = ELF :: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC ; break ; case


<s> if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant


<s> case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) break ; SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , <STR_LIT> , TopPart , SDValue ( ) ) . getValue ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue MulRHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , MulLHS , MulRHS ) ; SDValue ResultHigh = SDValue ( Mul , <NUM_LIT> ) ; ReplaceUses ( SDValue ( N ,


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm ,


<s> switch ( TM . getTLSModel ( GV ) ) { case TLSModel :: GeneralDynamic : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalDynamic : Modifier = <STR_LIT> ; break ; case TLSModel :: InitialExec : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalExec : Modifier = <STR_LIT> ; break ; } } else if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { Modifier = <STR_LIT> ; } } break ; case MachineOperand :: MO_BlockAddress : Name = GetBlockAddressSymbol ( MO . getBlockAddress ( )


<s> const InstrItineraryData * getInstrItineraryData ( ) const override


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false , <NUM_LIT>