<s> case LibFunc_fmaxf : case LibFunc_fmaxl : Opcode = <STR_LIT> ; break ; } } if ( Opcode ) { EVT EVTy = TLI -> getValueType ( DL , CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( EVTy == <STR_LIT> ) return true ; if ( TLI -> isOperationLegalOrCustom ( Opcode , EVTy ) ) continue ; else if ( EVTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , EVTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst > ( J ) ; if ( CI -> getSrcTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || CI -> getDestTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , CI -> getSrcTy ( ) -> getScalarType ( ) ) || isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , CI -> getDestTy ( ) -> getScalarType ( ) ) ) return true ; } else if ( isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: UDiv || J -> getOpcode ( ) == Instruction :: SDiv || J -> getOpcode ( ) == Instruction :: URem || J -> getOpcode ( ) == Instruction :: SRem ) ) { return true ; } else if ( ! TM . is<ISA_LIT>64 ( ) && isLargeIntegerTy ( false , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: Shl || J -> getOpcode ( ) == Instruction :: AShr || J -> getOpcode ( ) == Instruction :: LShr ) ) { return true ; } else if ( isa < IndirectBrInst > ( J ) || isa < InvokeInst > ( J ) ) { return true ; } else if ( SwitchInst * SI = dyn_cast < SwitchInst > ( J ) ) { if ( SI -> getNumCases ( ) + <NUM_LIT> >= ( unsigned ) TLI -> getMinimumJumpTableEntries ( ) ) return true ; } if ( J -> getOpcode ( ) == Instruction :: FRem ) return true ; if ( ST -> useSoftFloat ( ) ) { switch ( J -> getOpcode ( ) ) { case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction ::


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant *


<s> const SmallVectorImpl < unsigned > & getRegList ( ) const { assert ( ( Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR ) && <STR_LIT> ) ; return Registers


<s> return __builtin_mve_vcvtbq_m_f32_f16v4sf ( __inactive ,


<s> if ( SizeInBits == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; } if ( RegBankID == <STR_LIT> ) { switch ( SizeInBits ) { default : return nullptr ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT>


<s> else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) , OpFlag ) ; DebugLoc DL = JT -> getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if (


<s> void RegDefsUses :: addLiveOut ( const MachineBasicBlock & MBB , const MachineBasicBlock & SuccBB ) { for ( MachineBasicBlock :: const_succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( * SI != & SuccBB ) for ( const auto & LI : ( * SI )

-> liveins ( ) ) Uses . set ( LI . PhysReg ) ;


<s> assert ( Operand . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Operand . getExpr ( ) ; const MCSymbolRefExpr * SymExpr = static_cast < const MCSymbolRefExpr * > ( Expr ) ; assert ( SymExpr -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT && <STR_LIT> ) ; MCSymbol * LabelSym = getContext ( ) . getOrCreateSymbol ( SymExpr -> getSymbol ( ) . getName ( ) ) ; emitLabel ( LabelSym , Inst . getLoc (


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> size_t THMToTHMStub :: alignment ( ) const { return


<s> if ( ! emitCmp ( ResultReg , CI ) ) return false ; updateValueMap ( I ,


<s> static MCDisassembler * create<ISA_LIT>_64Disassembler ( const Target & T , const MCSubtargetInfo &


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } else if ( AreSequentialLoads ( Ld3 , Ld2 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul1 -> Exchange = true ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul0 -> Exchange = true ; R . AddMulPair ( PMul1 , PMul0 ) ; return true ; } return false ; } ; MulCandList & Muls = R . getMuls ( ) ; const unsigned Elems = Muls . size ( ) ; SmallPtrSet < const Instruction * , <NUM_LIT> > Paired ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { MulCandidate * PMul0 = static_cast < MulCandidate * > ( Muls [ i ] . get ( ) ) ; if ( Paired . count ( PMul0 -> Root ) ) continue ; for ( unsigned j = <NUM_LIT> ; j < Elems ; ++ j ) { if ( i == j ) continue ; MulCandidate * PMul1 = static_cast < MulCandidate * > ( Muls [ j ] . get ( ) ) ; if ( Paired . count ( PMul1 -> Root ) ) continue ; const Instruction * Mul0 = PMul0 -> Root ; const Instruction * Mul1 = PMul1 -> Root ; if ( Mul0 == Mul1 ) continue ; assert ( PMul0 != PMul1 && <STR_LIT> ) ; if ( CanPair ( R , PMul0 , PMul1 ) ) { Paired . insert ( Mul0 )


<s> long long Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT>


<s> LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ShouldUseMOV16PIC ) { AddPICADD_MOVi16_PICID ( MI , MBB , MBBI , ! isThumb2 , PredReg , Pred , DstReg , DstIsDead , LO16 , HI16 ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred )


<s> Src1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( Src1 ) -- NumNewCopies ; if ( Src1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) ++ NumRemovableCopies ; } unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool AllUsesAreCopies = true ; for ( MachineRegisterInfo :: use_instr_nodbg_iterator Use = MRI -> use_instr_nodbg_begin ( Dst ) , E = MRI -> use_instr_nodbg_end ( ) ; Use != E ; ++ Use ) { unsigned SubReg ; if ( getSrcFromCopy ( & * Use , MRI , SubReg ) || isTransformable ( & * Use ) ) ++ NumRemovableCopies ; else if ( Use -> getOpcode ( ) == <STR_LIT> || Use -> getOpcode ( ) == <STR_LIT> ) ; else AllUsesAreCopies = false ; } if ( AllUsesAreCopies ) -- NumNewCopies ; if ( NumNewCopies <= NumRemovableCopies ) return true ; return TransformAll


<s> F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg

( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) Changed |= adjustCallSequence ( MF , * BB , I ) ; return


<s> } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Symbol -> setUsedInReloc ( ) ; } RelSymbol = Asm . getAtom ( * Symbol ) ; if ( Symbol -> isInSection ( ) ) { const MCSectionMachO & Section = static_cast < const MCSectionMachO & > ( * Fragment -> getParent ( ) ) ; if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) RelSymbol = nullptr ; } if ( RelSymbol ) { if ( RelSymbol != Symbol ) Value += Layout . getSymbolOffset ( * Symbol ) - Layout . getSymbolOffset ( * RelSymbol ) ; } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) { Index = Symbol -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Value += Writer -> getSymbolAddress ( * Symbol , Layout ) ; if ( IsPCRel ) Value -= FixupAddress + ( <NUM_LIT> << Log2Size ) ; } else if ( Symbol -> isVariable ( ) ) { const MCExpr * Value = Symbol -> getVariableValue ( ) ; int64_t Res ; bool isAbs = Value -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ; if ( isAbs ) { FixedValue = Res ; return ; } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } MCSymbolRefExpr :: VariantKind Modifier = Target . getSymA ( ) -> getKind ( ) ; if ( IsPCRel ) { if ( IsRIPRel ) { if ( Modifier == MCSymbolRefExpr :: VK_GOTPCREL ) { if ( unsigned ( Fixup . getKind ( ) ) == <STR_LIT> ) Type = MachO :: <ISA_LIT>_64_RELOC_GOT_LOAD ; else Type = MachO :: <ISA_LIT>_64_RELOC_GOT ; } else if ( Modifier == MCSymbolRefExpr :: VK_TLVP ) { Type = MachO :: <ISA_LIT>_64_RELOC_TLV ; } else if ( Modifier != MCSymbolRefExpr :: VK_None ) { report_fatal_error ( <STR_LIT> , false ) ; } else { Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED ; switch ( - ( Target . getConstant ( ) + ( <NUM_LIT> << Log2Size ) ) ) { case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_1 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_2 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_4 ; break ; } } } else


<s> } insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> return create ( VK_<ISA_LIT>_HI , Expr


<s> static bool arm_legitimate_constant_p_1 ( machine_mode , rtx x ) { if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant ( x , false ) ) return false ; return flag_pic || ! label_mentioned_p (


<s> vmull_high_p64 ( poly64x2_t a , poly64x2_t b ) { return __builtin_aarch64_crypto_pmullv2di_ppp ( a ,


<s> Align Alignment = Subtarget . is<ISA_LIT>64 ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align (


<s> CondRegArray <ISA_LIT>FlagsCopyLoweringPass :: collectCondsInRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator TestPos ) { CondRegArray CondRegs = { } ; for ( MachineInstr & MI : llvm :: reverse ( llvm :: make_range ( MBB . begin ( ) , TestPos ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( Cond != <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && TRI -> isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) CondRegs [ Cond ] = MI

. getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> state -> insns_left = state -> issue_rate ; advance_state ( curr_state


<s> if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> if ( ! isImm ( ) ) return DiagnosticPredicateTy :: NoMatch ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return DiagnosticPredicateTy :: NoMatch ; uint64_t Value = CE -> getValue ( ) ; if ( Value % Angle == Remainder && Value <= <NUM_LIT> ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy


<s> unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; align *= ( <NUM_LIT> << size ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( regs == <NUM_LIT> ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMSRMask ( unsigned MMask , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_MSRMask ) ; Op -> MMask . Val = MMask ; Op -> StartLoc = S ; Op -> EndLoc =


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; Reloc :: Model RM = Subtarget -> getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! Subtarget -> has<ISA_LIT>64 ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . EmitRawText ( StringRef (


<s> return slots - ( ia64_rse_slot_num ( bspstore ) + slots


<s> string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I * <NUM_LIT> * <NUM_LIT> ) ; SExpr * Reg_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> ,

ctx -> load ( <NUM_LIT> , SP ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ;


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value


<s> SDValue <ISA_LIT>TargetLowering :: LowerDarwinGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MVT PtrMemVT = getPointerMemTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( PtrMemVT , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , Align ( PtrMemVT . getSizeInBits ( ) / <NUM_LIT> ) , MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; FuncTLVGet = DAG . getZExtOrTrunc ( FuncTLVGet , DL , PtrVT ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getTLSCallPreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; unsigned Opcode = <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( FuncTLVGet ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; Ops . push_back ( DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; Ops . push_back ( DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; Ops . push_back ( DAG . getRegisterMask


<s> static inline bool isTOCSaveRestoreRequired ( const <ISA_LIT>Subtarget & Subtarget ) { return Subtarget . isAIXABI ( ) || ( Subtarget . is64BitELFABI ( ) && ! Subtarget . isUsingPCRelativeCalls (


<s> unsigned getCheriHWRegsReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_CheriHWRegs ) && <STR_LIT> ) ; unsigned ClassID =


<s> if ( Flags . empty ( ) ) return <NUM_LIT> ; return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT>


<s> static bool isMOVSLDUPMask ( ArrayRef < int > Mask , EVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits (

) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ;


<s> rtx high_part = gen_highpart ( mode , src ) ; rtx low_part = gen_lowpart ( mode , src ) ; emit_move_insn_1 ( word0 , high_part ) ; emit_move_insn_1 ( word1 ,


<s> if ( is128BitLaneCrossingShuffleMask ( MaskEltVT , Mask ) ) { if ( Subtarget . hasAVX2 ( ) && MaskVT . is256BitVector ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( Mask ) ; return true ; } if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask


<s> void <ISA_LIT>AsmPrinter :: printUnsignedImm ( const MachineInstr * MI , int opNum ) { const MachineOperand & MO = MI -> getOperand


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || df_regs_ever_live_p


<s> if ( ! isPowerOf2_32 ( NumElems ) ) return nullptr ; const Value * Op = BO ; unsigned Stages = Log2_32 ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != Stages ; ++ i ) { const auto * BO = dyn_cast < BinaryOperator > ( Op ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return nullptr ; if ( i != <NUM_LIT> && ! BO -> hasNUses ( <NUM_LIT> ) ) return nullptr ; Value * LHS = BO -> getOperand ( <NUM_LIT> ) ; Value * RHS = BO -> getOperand ( <NUM_LIT> ) ; auto * Shuffle = dyn_cast < ShuffleVectorInst > ( LHS ) ; if ( Shuffle ) { Op = RHS ; } else { Shuffle = dyn_cast < ShuffleVectorInst > ( RHS ) ; Op = LHS ; } if ( ! Shuffle || Shuffle -> getOperand ( <NUM_LIT> ) != Op ) return nullptr ; unsigned MaskEnd = <NUM_LIT> << i ; for ( unsigned Index = <NUM_LIT> ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskValue ( Index ) != ( int ) ( MaskEnd + Index ) ) return nullptr ; } return const_cast < Value * > ( Op


<s> Ret . DefsSingleUse &= MRI -> hasOneNonDBGUse ( Def2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Ret . DefsSingleUse &= MRI -> hasOneNonDBGUse ( Ret . CopyDefs . second -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( Def2 && <STR_LIT> ) ; Ret . TrueDefs = std :: make_pair ( Def1 , Def2 ) ; } else { Ret . TrueDefs = std :: make_pair ( Def1 , nullptr ) ; Ret . CopyDefs . second = nullptr ; } } Ret . ContainedInBlock = <NUM_LIT> ; for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { unsigned Opc = UseMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsISEL = <NUM_LIT> ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsBR = <NUM_LIT> ; Ret . FeedsLogical = isCRLogical ( UseMI ) ; if ( UseMI . getParent ( ) != MIParam . getParent ( ) ) Ret . ContainedInBlock = <NUM_LIT> ; } Ret . SingleUse = MRI -> hasOneNonDBGUse ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! Ret . IsNullary ) { Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . first -> getParent ( ) ) ; if ( Ret . IsBinary ) Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . second -> getParent ( ) ) ; } LLVM_DEBUG ( Ret . dump


<s> return ( __m128h ) __builtin_ia32_vfmaddsh3_mask ( ( __v8hf ) __W , ( __v8hf ) __A , (


<s> Parser . Lex ( ) ; return false ; } else if ( getLexer ( ) . is ( AsmToken :: Equal ) ) { getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg .


<s> u = fold_convert ( TREE_TYPE ( t ) , build_int_cst ( NULL_TREE , rsize - size ) ) ; t = build ( PLUS_EXPR , TREE_TYPE ( t ) , t , u ) ; } COND_EXPR_THEN ( addr ) = t ; if ( osize > UNITS_PER_WORD ) { u = fold_convert ( TREE_TYPE ( ovfl ) , build_int_cst ( NULL_TREE , osize - <NUM_LIT> ) ) ; t = build ( PLUS_EXPR , TREE_TYPE ( ovfl ) , ovfl , u ) ; u = fold_convert ( TREE_TYPE ( ovfl ) , build_int_cst ( NULL_TREE , - osize ) ) ; t = build ( BIT_AND_EXPR , TREE_TYPE ( ovfl ) , t , u ) ; align = build ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; } else align = NULL ; u = fold_convert ( TREE_TYPE ( ovfl ) , build_int_cst ( NULL_TREE , osize ) ) ; t = build ( POSTINCREMENT_EXPR , TREE_TYPE ( ovfl ) , ovfl , u ) ; if ( BYTES_BIG_ENDIAN && osize > size ) { u = fold_convert ( TREE_TYPE ( t ) , build_int_cst ( NULL_TREE , osize - size ) ) ; t = build ( PLUS_EXPR , TREE_TYPE ( t ) , t , u ) ; } if ( align ) t = build ( COMPOUND_EXPR , TREE_TYPE ( t ) , align , t ) ; COND_EXPR_ELSE ( addr ) = t ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return addr


<s> return ! In64BitMode && ( isTargetCygMing ( ) || isTargetKnownWindowsMSVC (


<s> if ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) != <NUM_LIT> ) return false ; switch ( MI . getOpcode ( ) ) { default : return true ; case TargetOpcode :: COPY : case TargetOpcode ::


<s> } if ( Subtarget -> isTargetWindows ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ; res = DAG . getLoad ( getPointerTy ( ) , dl , Chain , res , MachinePointerInfo


<s> return Index < <ISA_LIT>Relocs . size ( ) && ! <ISA_LIT>Relocs [ Index ] . HasMatchingHi && ! isPrecededByMatchingHi ( Asm ,


<s> } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( <NUM_LIT> ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ; else emit_insn ( gen_sse2_cvttpd2dq ( x , value


<s> return DAG . getTarget ( ) . shouldAssumeDSOLocal ( * Mod , GV ) && ! dyn_cast_or_null < GlobalIFunc > ( GV ) ; } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( StringRef FuncName , bool IsDeclaration , const XCOFF :: StorageClass & SC ) { auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( FuncName ) ) ) ; if ( IsDeclaration && ! S -> hasContainingCsect ( ) ) { MCSectionXCOFF * Sec = Context . getXCOFFSection ( S -> getName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; S -> setContainingCsect ( Sec ) ; } MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) ; return getAIXFuncEntryPointSymbolSDNode ( F -> getName ( ) , F


<s> SDValue getGlobalAddr<ISA_LIT> ( NodeTy * N , EVT Ty , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; SDValue Gl = getTargetNode ( N , Ty , DAG , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> ParseExpression ( const MCExpr * & EVal ) { if ( getParser ( ) . parseExpression


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return RegBits


<s> x = gen_rtx_VEC_MERGE ( mode , x , CONST0_RTX ( mode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V8HImode : case V16QImode : vsimode = V4SImode ; goto widen ; case V4HImode : case V8QImode : if ( ! mmx_ok ) return false ; vsimode = V2SImode ; goto widen ; widen : var = convert_modes ( SImode , GET_MODE_INNER (


<s> void <ISA_LIT>TargetStreamer :: emitRRRX ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , unsigned Reg2 , MCOperand Op3 , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MCInst TmpInst ; TmpInst . setOpcode ( Opcode


<s> vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) mep_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mivc2 : for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) fixed_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) call_used_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) call_used_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } if ( flag_pic == <NUM_LIT> ) warning ( OPT_fpic , <STR_LIT> ) ; if ( flag_pic == <NUM_LIT> ) warning ( OPT_fPIC , <STR_LIT> ) ; if ( TARGET_S && TARGET_M ) error (


<s> if ( mode == SImode ) fn = gen_load_locked_si ; else if ( mode ==


<s> SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseOperand ( ) { if ( isParsingIntelSyntax ( )


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG .

getConstant ( SType , DL , <STR_LIT> ) ) ;


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering


<s> Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( ThunkReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; insertSpeculationBarrier ( & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) , * Entry , Entry


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget <


<s> if ( fcode == ARM_BUILTIN_SAT_IMM_CHECK ) { rtx min_sat = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; rtx max_sat = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; gcc_assert ( CONST_INT_P ( min_sat ) ) ; gcc_assert ( CONST_INT_P ( max_sat ) ) ; rtx sat_imm = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( sat_imm )


<s> int TruncatedVectorStart = SwappedOps ? Size : <NUM_LIT> ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Split , TruncatedVectorStart , Delta ) ) return false ; if ( isAnyInRange ( Mask . slice ( Split , Size - Split )

, TruncatedVectorStart , TruncatedVectorStart + Size ) ) return false ;


<s> unsigned rs1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeIntRegsRegisterClass ( MI , rs1


<s> auto * CPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( E . Val . MachineCPVal ) ; auto * CPC = dyn_cast < <ISA_LIT>ConstantPoolConstant > ( CPV ) ; if ( ! CPC


<s> initializeEvexToVexInstPassPass ( * PassRegistry :: getPassRegistry ( )


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rda , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rda , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ; } if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo , Address , Decoder ) ) )


<s> return <NUM_LIT> - MI . getOperand (


<s> Value * <ISA_LIT>IREmitter :: visitSAHF ( const SDNode


<s> CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming ->


<s> } vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; l = gen_reg_rtx ( V16QImode ) ; op = gen_lowpart ( V16QImode , d -> op0 ) ; emit_insn ( gen_ssse3_pshufbv16qi3 ( l , op , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; h = gen_reg_rtx ( V16QImode ) ; op = gen_lowpart ( V16QImode , d -> op1 ) ; emit_insn ( gen_ssse3_pshufbv16qi3 ( h , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != V16QImode ) op = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_iorv16qi3 ( op , l , h ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target ,


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass


<s> for ( unsigned I = <NUM_LIT> ; I != array_lengthof ( HardFloatLibCalls ) ; ++ I ) { assert ( ( I == <NUM_LIT> || HardFloatLibCalls [ I - <NUM_LIT> ] < HardFloatLibCalls [ I ] ) && <STR_LIT> ) ; if ( HardFloatLibCalls [ I ] . Libcall != RTLIB :: UNKNOWN_LIBCALL ) setLibcallName ( HardFloatLibCalls [ I ] . Libcall


<s> if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > <NUM_LIT> ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM ) save


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { MaskLow . push_back ( i ) ; MaskLow . push_back ( i + <NUM_LIT> ) ; } createUnpackShuffleMask ( VT , MaskLowTemp1 , true , false ) ; createUnpackShuffleMask ( VT , MaskHighTemp1 , false , false ) ; scaleShuffleMask ( <NUM_LIT> , MaskHighTemp1 , MaskHighWord ) ; scaleShuffleMask ( <NUM_LIT> , MaskLowTemp1 , MaskLowWord


<s> SmallVector < int , <NUM_LIT> > Mask ( S0 -> getMask ( ) . begin ( ) , S0 -> getMask ( ) . end ( ) ) ; Mask . append ( S1 -> getMask ( ) . begin ( ) , S1 -> getMask ( ) . end ( ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } } if ( all_of ( N -> ops ( ) , [ ] ( SDValue Op ) { return Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; } ) ) { SmallVector < SDValue , <NUM_LIT> > Extracts ; for ( unsigned Op = <NUM_LIT> ; Op < N -> getNumOperands ( ) ; Op ++ ) { SDValue O = N -> getOperand ( Op ) ; for ( unsigned i = <NUM_LIT> ; i < O . getValueType ( ) . getVectorNumElements ( ) ; i ++ ) { SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , O , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Extracts . push_back ( Ext ) ; } } return DAG . getBuildVector ( VT , DL , Extracts ) ; } if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( TypeSize :: Fixed ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; int NumIns = N


<s> if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) continue ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , <NUM_LIT> ) && known_eq ( offset , <NUM_LIT> ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components , cfun -> machine -> frame . spare_pred_reg ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine


<s> unsigned I2 = ! ( J2 ^ S ) ; unsigned imm10 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm11 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned tmp = ( S << <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) | ( imm10 << <NUM_LIT> ) | imm11 ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand


<s> Scale = <NUM_LIT> ; } break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; } break ; } if ( ! NewOpc ) continue ; unsigned UserOffset = getUserOffset ( U ) ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; if ( ! U . KnownAlignment ) MaxOffs -= <NUM_LIT> ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , MaxOffs , false , true


<s> else if ( msize <= <NUM_LIT> ) base_off += msize ; if ( base_off >= <NUM_LIT> ) { base_off = <NUM_LIT> - <NUM_LIT> ; base_off -= ( ( ( base_off % msize ) - ( off_val_1 % msize ) ) + msize ) % msize ; } if ( base_off <= - <NUM_LIT> ) { base_off = - <NUM_LIT> + <NUM_LIT> ; base_off += ( ( ( base_off % msize ) - ( off_val_1 % msize ) ) + msize ) % msize ; } new_off_1 = off_val_1 - base_off ; new_off_3 = off_val_3 - base_off ; if ( new_off_1 > stp_off_upper_limit || new_off_1 < stp_off_lower_limit || new_off_3 > stp_off_upper_limit || new_off_3 < stp_off_lower_limit ) return false ; replace_equiv_address_nv ( mem_1 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 ) , true ) ; replace_equiv_address_nv ( mem_2 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 + msize ) , true ) ; replace_equiv_address_nv ( mem_3 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 ) , true ) ; replace_equiv_address_nv ( mem_4 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 + msize ) , true ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) || ! aarch64_mem_pair_operand ( mem_3 , mode ) ) return false ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; } emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , plus_constant ( DImode , base , base_off ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] ,


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm ,


<s> if ( Size <= RCSize && <NUM_LIT> <= Align ) { int PtrOffset = SrcIdx * <NUM_LIT> ; unsigned NewImm = ( DstIdx << <NUM_LIT> ) | ZMask ; unsigned NewOpCode = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewMI = FuseInst ( MF , NewOpCode , OpNum , MOs , InsertPt , MI , * this , PtrOffset ) ; NewMI -> getOperand ( NewMI -> getNumOperands ( ) - <NUM_LIT> ) . setImm ( NewImm ) ; return NewMI ; } } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned RCSize = getRegClass ( MI . getDesc ( ) , OpNum , & RI , MF ) -> getSize ( ) ; if ( Size <= RCSize && <NUM_LIT> <= Align ) { unsigned NewOpCode = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewMI = FuseInst ( MF , NewOpCode , OpNum , MOs , InsertPt , MI , * this , <NUM_LIT> ) ; return NewMI ; } } break ; } ; return nullptr


<s> return create<ISA_LIT>MachObjectWriter ( OS , is64 , ( is64 ? MachO :: CPU_TYPE_POWERPC64 : MachO :: CPU_TYPE_POWERPC ) ,


<s> return MIB . addImm ( <NUM_LIT> ) . addReg (


<s> table = lookupAVX512 ( MI . getOpcode ( ) , dom ) ; if ( dom == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } assert ( table && <STR_LIT> ) ; MI . setDesc ( get ( table [ Domain - <NUM_LIT> ]


<s> return emitCapFloatStore < <STR_LIT> , <STR_LIT> > ( Subtarget , MI , <STR_LIT> , BB


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) ==


<s> Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext )


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser (

Options , _STI , MII ) , STI ( _STI ) , Parser ( _Parser ) {


<s> bool isS16ImmX16 ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm ( ) )

&& ( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; }


<s> SDValue Src = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) { APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT>


<s> return ( int16x4x2_t ) { vtrn1_s16 ( a , b ) , vtrn2_s16 (


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key += <STR_LIT> ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ; } return I .


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 )


<s> if ( skipFunction ( F ) ) return false ; if ( F . isDeclaration ( ) ) return false ; Func = & F ; ConsideredSExtType = Type :: getInt64Ty ( Func -> getContext ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << Func -> getName ( ) << '\n' ) ; Instructions SExtInsts ; analyzeSExtension ( SExtInsts ) ; return propagateSignExtension ( SExtInsts


<s> Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst


<s> return ( __m512i ) __builtin_ia32_vcvttph2uw512_mask_round ( __B , ( __v32hi ) _mm512_setzero_si512 ( ) ,


<s> static bool mips_small_register_classes_for_mode_p ( machine_mode


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT>


<s> MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( AddrTmp , false , false , true ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( i == <STR_LIT> ) MIB . addDisp ( MO , LabelOffset ) ; else if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOs


<s> int <ISA_LIT>AsmParser :: matchMSA128CtrlRegisterName ( StringRef Name ) { int CC ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; return CC


<s> void setLocalStackSize ( unsigned Size


<s> BroadcastIdx = i ; break ; } } if ( BroadcastIdx < <NUM_LIT> ) return SDValue ( ) ; assert ( BroadcastIdx < ( int ) Mask . size ( ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; SDValue V = V1 ; for ( ; ; ) { switch ( V . getOpcode ( ) ) { case <STR_LIT> : { int OperandSize = Mask . size ( ) / V . getNumOperands ( ) ; V = V . getOperand ( BroadcastIdx / OperandSize ) ; BroadcastIdx %= OperandSize ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int BeginIdx = ( int ) ConstantIdx -> getZExtValue ( ) ; int EndIdx = BeginIdx + ( int ) VInner . getSimpleValueType ( ) . getVectorNumElements ( ) ; if ( BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx ) { BroadcastIdx -= BeginIdx ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } if ( V . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast ( DL , VT , V . getOperand ( <NUM_LIT> ) , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; SDValue BC = V ; while ( BC . getOpcode ( ) == <STR_LIT> ) BC = BC . getOperand ( <NUM_LIT> ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) { V = V . getOperand ( BroadcastIdx


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( TT ) , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle

, * this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) {


<s> return ( __m128i ) __builtin_ia32_cvtps2udq128_mask ( ( __v4sf ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT>


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |=

~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = <STR_LIT>


<s> bool requiresVirtualBaseRegisters ( const MachineFunction & MF ) const


<s> addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy )

addPass ( createCFGSimplificationPass ( ) ) ;


<s> if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDNode * In64 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In , SubReg32 ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( In64 , <NUM_LIT> ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , Shift32 ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; return Out


<s> bool <ISA_LIT>Subtarget :: mipsSEUsesSoftFloat


<s> const LegalizerInfo * <ISA_LIT>Subtarget ::


<s> const TargetRegisterClass * RC = & <STR_LIT> ; EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC ->

getSize ( ) , RC -> getAlignment ( ) , false ) ;


<s> if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name


<s> assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( PFI -> usesPICBase ( ) ) { HasGPSaveArea = true ; int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] .


<s> case MULT : if ( index ) return <NUM_LIT> ; index = XEXP ( op , <NUM_LIT> ) ; scale_rtx = XEXP ( op , <NUM_LIT> ) ; break ; case UNSPEC : if ( XINT ( op , <NUM_LIT> ) == UNSPEC_TP && TARGET_TLS_DIRECT_SEG_REFS && seg == SEG_DEFAULT ) seg = TARGET_64BIT ? SEG_FS : SEG_GS ; else return <NUM_LIT> ; break ; case REG : case SUBREG : if ( ! base ) base = op ; else if ( ! index ) index = op ; else return <NUM_LIT> ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : if ( disp ) return <NUM_LIT> ; disp = op ; break ; default : return <NUM_LIT> ; } } } else if ( GET_CODE ( addr ) == MULT ) { index = XEXP ( addr , <NUM_LIT> ) ; scale_rtx = XEXP ( addr , <NUM_LIT> ) ; } else if ( GET_CODE ( addr ) == ASHIFT ) { rtx tmp ; index = XEXP ( addr , <NUM_LIT> ) ; tmp = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( tmp ) != CONST_INT ) return <NUM_LIT> ; scale = INTVAL ( tmp ) ; if ( ( unsigned HOST_WIDE_INT ) scale > <NUM_LIT> ) return <NUM_LIT> ; scale = <NUM_LIT> << scale ; retval = - <NUM_LIT> ; } else disp = addr ; if ( scale_rtx ) { if ( GET_CODE ( scale_rtx ) != CONST_INT ) return <NUM_LIT> ; scale = INTVAL ( scale_rtx ) ; } base_reg = base && GET_CODE ( base ) == SUBREG ? SUBREG_REG ( base ) : base ; index_reg = index && GET_CODE ( index ) == SUBREG ? SUBREG_REG ( index ) : index ; if ( base_reg && index_reg && scale == <NUM_LIT> && ( index_reg == arg_pointer_rtx || index_reg == frame_pointer_rtx || ( REG_P ( index_reg ) && REGNO ( index_reg ) == STACK_POINTER_REGNUM ) ) ) { rtx tmp ; tmp = base , base = index , index = tmp ; tmp = base_reg , base_reg = index_reg , index_reg = tmp ; } if ( ( base_reg == hard_frame_pointer_rtx || base_reg == frame_pointer_rtx || base_reg == arg_pointer_rtx ) && ! disp )


<s> static SDValue PerformSExtCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT OpVT = Op . getValueType ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( ( VT == <STR_LIT> && OpVT == <STR_LIT> ) || ( VT == <STR_LIT> && OpVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) return DAG .


<s> TSM . init ( & Func . getSubtarget ( ) ) ; TII = ST . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I


<s> Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; std :: string Str = Tok . getIdentifier ( ) ; Parser . Lex ( ) ; const MCExpr * IdVal ; SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { while ( <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & nextTok = Parser . getTok ( ) ; if ( nextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( )


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) .


<s> bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR ) AddDefaultT1CC ( MIB ) ; else AddDefaultCC ( MIB


<s> static const char * sparc_mangle_type ( const_tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return <STR_LIT> ; return


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> if ( parseOperand ( Operands , Name ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } Parser . Lex ( ) ; return false


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > (


<s> return ( __m128 ) __builtin_ia32_loadss_mask ( __P , ( __v4sf ) _mm_setzero_ps ( )


<s> return isImm ( <NUM_LIT> , <NUM_LIT> )


<s> if ( Mask [ i ] < <NUM_LIT> ) continue ; assert ( Mask [ i ] < Size * <NUM_LIT> && <STR_LIT> ) ; if ( BlendMask [ Mask [ i ] % Size ] < <NUM_LIT> ) BlendMask [ Mask [ i ] % Size ] = Mask [ i ] ; else if ( BlendMask [ Mask [ i ] % Size ] != Mask [ i ] ) return SDValue ( ) ; PermuteMask [ i ] = Mask [ i ] % Size ; } unsigned EltSize = VT . getScalarSizeInBits


<s> Frame . Begin = getContext ( ) . createTempSymbol ( ) ; MCELFStreamer :: EmitLabel ( Frame .


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) ) { assert ( ST -> hasNEON ( ) ) ; SDValue X = N -> getOperand ( <NUM_LIT> ) ; SDValue NX = DAG . getNode ( <STR_LIT> , dl , VT , getZeroVector ( VT , DAG , dl ) , X ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , dl , VT , X , NX ) ; EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; SDValue Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Bits ) ; } if ( ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) && ( N -> getOpcode ( ) == <STR_LIT> ) ) { unsigned NumBits = ElemTy . getSizeInBits ( ) ; SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT


<s> rtx x ; bool ok ; if ( vselect_insn == NULL_RTX ) init_vselect_insn ( ) ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , <NUM_LIT> ) ; PUT_MODE ( x , v2mode ) ; XEXP ( x ,


<s> MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Static ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> if ( ! type ) return true ; return ! sh_attr_renesas_p (


<s> if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ; } } if ( isSplatVector ( N1 . getNode ( ) ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( N1C && ( <NUM_LIT> == N1C -> getZExtValue ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; } } return SDValue ( )


<s> if ( NumBytes >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HI22 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LO10 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDrr ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ,

<STR_LIT> ) . addImm ( HIX22 ( NumBytes ) ) ;


<s> return __builtin_mve_vrev32q_m_sv16qi ( __arm_vuninitializedq_s8 ( ) ,


<s> void getAnalysisUsage ( AnalysisUsage


<s> Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable ; else InstTable = ReverseSTiTable ; } int Opcode = Lookup ( InstTable , MI . getOpcode ( ) ) ; assert ( Opcode != - <NUM_LIT> && <STR_LIT> ) ; unsigned NotTOS = ( TOS == Op0 ) ? Op1 : Op0 ; MBB -> remove ( & * I ++ ) ; I = BuildMI ( * MBB , I , dl , TII -> get ( Opcode ) ) . addReg ( getSTReg ( NotTOS ) ) ; if ( ! MI . mayRaiseFPException ( ) ) I -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; if ( KillsOp0 && KillsOp1 && Op0


<s> Value * RVal = RI -> getReturnValue ( ) ; if ( ! RVal ) continue ; Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( )


<s> unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LivePhysRegs LiveRegs ( TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB ) ; MBB . addSuccessor (


<s> static DecodeStatus DecodesFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const


<s> unsigned <ISA_LIT>MCCodeEmitter :: getLWydeOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { return getLabelOpValue ( Inst , OpNo , Fixups , SubtargetInfo , static_cast < MCFixupKind > (


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool Verbose , raw_ostream & Out ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , *


<s> bool <STR_LIT> ( SDNode * N , bool isUnary ) { if ( ! isUnary ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> +

<NUM_LIT> ) || ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ;


<s> unsigned PushOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc ,

false , & is<ISA_LIT>Area2Register , MachineInstr :: FrameSetup ) ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoDsp ( ) ; return


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; RTLIB :: Libcall LC ; switch ( SVT


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>elTarget , create<ISA_LIT>elDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64Target ,


<s> if ( ! MO . isReg ( ) ) return true ; OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return false ; } return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo ,


<s> DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand ::


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno )


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs


<s> int UnscaledLdOffset = TII -> hasUnscaledLdStOffset ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize <= ( UnscaledStOffset +


<s> for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true


<s> SDValue Value = StoreNode -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result


<s> uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; uint64_t Form = TSFlags & <STR_LIT> ; if ( Form == <STR_LIT> ) return <STR_LIT> ; if ( ( Form == <STR_LIT> || Form == <STR_LIT> ) && MI . getDesc ( ) . isBranch ( ) ) return <STR_LIT> ; if ( Form == <STR_LIT> && MI . getOpcode ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateMCValue (


<s> return ( __mmask64 ) __builtin_ia32_ucmpb512_mask ( ( __v64qi ) __A , ( __v64qi )


<s> } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg ) ; return true ; } } return false ; } case <STR_LIT> : case <STR_LIT> : { const auto * MTI = cast < MemTransferInst > ( II ) ; if ( MTI -> isVolatile ( ) )


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant ( <NUM_LIT> , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , xFGETSIGN


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT ) , Subtype


<s> bool <ISA_LIT>InstructionSelector :: selectMergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg0 ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned DefReg = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( DefReg , RegBank ) ; if ( ! emitInsertSubreg ( DefReg , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I , MRI , MF ) ) return false ; for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; ++ Idx ) { unsigned Tmp = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst ) ) return


<s> bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList :


<s> return ( ( qword ) ( vec_sra ( vec_mulo ( ( vec_short8 ) ( a ) , ( vec_short8 ) ( b ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> ,


<s> CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef (


<s> int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; ++ MBBI ; for ( ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; if ( isMatchingUpdateInsn ( I , MI , BaseReg , UnscaledOffset ) )


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitExtend ( <STR_LIT> Opc , EVT DstVT , unsigned Src , EVT SrcVT , unsigned & ResultReg ) { unsigned RR = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src , false ) ; if ( RR == <NUM_LIT> )


<s> enum machine_mode mode ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , <NUM_LIT> , valtype ) ; return gen_rtx_REG ( mode


<s> case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT>


<s> unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case IA64_BUILTIN_BSP : if ( ! target || ! register_operand ( target , DImode ) ) target = gen_reg_rtx ( DImode ) ; emit_insn ( gen_bsp_value ( target ) ) ; target = convert_memory_address ( ptr_mode , target ) ; return target ; case IA64_BUILTIN_FLUSHRS : emit_insn ( gen_flushrs ( ) ) ; return const0_rtx ; case IA64_BUILTIN_INFQ : case IA64_BUILTIN_HUGE_VALQ : { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = CONST_DOUBLE_FROM_REAL_VALUE ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ : case


<s> setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( MF ) ; if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) ,


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI .


<s> int BranchOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( BranchOffset > <NUM_LIT> ) BranchOffset = - <NUM_LIT> * ( <NUM_LIT> - BranchOffset ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> return ( unsigned long long ) __builtin_lshrv2si3 ( (


<s> SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; do { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; } while ( End . getPointer ( ) < EndPtr ) ; Identifier = LineBuf ; assert ( ( End . getPointer ( ) == EndPtr || Info . isKind ( InlineAsmIdentifierInfo :: IK_Invalid ) ) && <STR_LIT> ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Invalid ) ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ; } else if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_EnumVal


<s> auto ReturnReg = GetReturnAddress ( ) ; assert ( ReturnReg == <STR_LIT> && <STR_LIT> ) ; auto StackReg = GetStackPtr ( ) ; assert ( StackReg == <STR_LIT> && <STR_LIT> ) ; assert ( GetFramePtr ( ) == <STR_LIT> && <STR_LIT> ) ; if ( MRI . getRARegister ( ) != ReturnReg ) { const_cast < MCRegisterInfo & > ( MRI ) . RAReg = ReturnReg ; } assert ( MRI . getRARegister ( ) == ReturnReg && <STR_LIT> ) ; assert ( MRI . getProgramCounter ( ) == <NUM_LIT> && <STR_LIT> ) ; auto & InitialState = MAI . getInitialFrameState ( ) ; unsigned C11Dwarf = MRI . getDwarfRegNum ( StackReg , true ) ; for ( const MCCFIInstruction & Inst : InitialState ) { if ( Inst . getOperation ( ) == MCCFIInstruction :: OpDefCfaRegister ) { if ( Inst . getRegister ( ) != C11Dwarf ) { const_cast < MCCFIInstruction & > ( Inst ) . setRegister ( C11Dwarf ) ; } } else if ( Inst . getOperation ( ) == MCCFIInstruction :: OpDefCfa ) { if ( Inst . getRegister ( ) != C11Dwarf


<s> virtual const char * getPassName ( )


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo )


<s> static SDValue emitStrictFPComparison ( SDValue LHS , SDValue RHS , const SDLoc & dl , SelectionDAG & DAG , SDValue Chain , bool IsSignaling ) { EVT VT = LHS . getValueType ( ) ; assert ( VT != <STR_LIT> ) ; const bool FullFP16 = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasFullFP16 ( ) ; if ( VT == <STR_LIT> && ! FullFP16 ) { LHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , LHS } ) ; RHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { LHS . getValue ( <NUM_LIT> ) , RHS } ) ; Chain = RHS . getValue (


<s> bool <ISA_LIT>LowerHomogeneousPrologEpilog :: runOnModule ( Module & M ) { if ( skipModule ( M ) ) return


<s> switch ( sparc_cpu ) { case PROCESSOR_NIAGARA : case PROCESSOR_NIAGARA2 : case PROCESSOR_NIAGARA3 : default : return <NUM_LIT> ; case PROCESSOR_NIAGARA4 : case PROCESSOR_NIAGARA7 : case PROCESSOR_V9 : return <NUM_LIT> ; case PROCESSOR_SUPERSPARC : return <NUM_LIT>


<s> MILOHDirective ( MCLOHType Kind , const LOHArgs & Args ) : Kind ( Kind ) , Args ( Args . begin ( ) , Args . end ( ) ) { assert ( isValidMCLOHType ( Kind ) && <STR_LIT>


<s> unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; } return RegNo | ( Align << <NUM_LIT>


<s> rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = <NUM_LIT> ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { rtx reg = gen_rtx_REG ( reg_mode , <NUM_LIT> ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( reg_mode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set (


<s> FOR_BB_INSNS_REVERSE ( bb , insn ) { if ( ! NONDEBUG_INSN_P (


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset ,


<s> auto * LIWP = getAnalysisIfAvailable < LoopInfoWrapperPass > ( ) ; auto * LI = LIWP ? & LIWP -> getLoopInfo ( ) : nullptr ; DomTreeUpdater DTU ( DT , DomTreeUpdater :: UpdateStrategy :: Lazy ) ; <ISA_LIT>LowerAMXIntrinsics LAT ( F , DTU ,


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> c = ( __v2df ) vec_cmpge ( a , b ) ; return ( __m128d ) _mm_setr_pd ( c [


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg ( Memory .


<s> bool isUImm8Shift2 ( ) { return isUImm < <NUM_LIT> , <NUM_LIT> >


<s> fprintf ( dump_file , <STR_LIT> ) ; dump_insn_slim ( dump_file , insn ) ; } rtx src = SET_SRC ( pc_set ( insn ) ) ; bool inverted = GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != PC ; gcc_assert ( GET_CODE ( XEXP ( src , <NUM_LIT> + ! inverted ) ) == PC ) ; rtx cond = copy_rtx ( XEXP ( src , <NUM_LIT> ) ) ; gcc_assert ( COMPARISON_P ( cond ) && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == CC_REGNUM && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) ; enum rtx_code inv_cond_code = reversed_comparison_code ( cond , insn ) ; gcc_assert ( inv_cond_code != UNKNOWN ) ; rtx inv_cond = gen_rtx_fmt_ee ( inv_cond_code , GET_MODE ( cond ) , copy_rtx ( XEXP ( cond , <NUM_LIT> ) ) , copy_rtx ( XEXP ( cond , <NUM_LIT> ) ) ) ; if ( inverted ) std :: swap ( cond , inv_cond ) ; insert_insn_on_edge ( gen_speculation_tracker ( cond ) , BRANCH_EDGE ( bb ) ) ; insert_insn_on_edge ( gen_speculation_tracker ( inv_cond ) , FALLTHRU_EDGE ( bb ) ) ; needs_tracking = true ; } else if ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) { if ( needs_tracking && ! need_second_pass ) { rtx_insn * seq = aarch64_speculation_clobber_sp ( ) ; emit_insn_before ( seq , insn ) ; } else { fixups_pending ++ ; need_second_pass = true ; } } else if ( find_reg_note ( insn , REG_NON_LOCAL_GOTO , NULL_RTX ) ) { rtx_insn * seq = aarch64_speculation_clobber_sp ( ) ; emit_insn_before ( seq , insn ) ; needs_tracking = true ; } } else { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; dump_insn_slim ( dump_file , insn ) ; } } } FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * end = BB_END ( bb ) ; rtx_insn * call_insn = NULL ; if ( bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) { rtx_insn * label = NULL ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) ) label = insn ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) label = insn ; if ( INSN_P ( insn ) ) break ; } gcc_assert ( label ) ; emit_insn_after ( aarch64_speculation_establish_tracker ( ) , label ) ; } for ( insn = BB_HEAD ( bb ) ; ; insn = NEXT_INSN ( insn ) ) { if ( NONDEBUG_INSN_P ( insn ) && recog_memoized ( insn ) >= <NUM_LIT> &&

( get_attr_speculation_barrier ( insn ) == SPECULATION_BARRIER_TRUE ) ) {


<s> <ISA_LIT>MCInstLower ( MCContext & ctx , AsmPrinter & printer ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerSymbolOperandDarwin ( const MachineOperand & MO , MCSymbol


<s> static unsigned int aarch64_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment = aarch64_function_arg_alignment (


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>MFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } if ( IsVarArg


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b ) ; return __ev_addusiaaw ( t )


<s> const MCOperand & MO = MI . getOperand ( Idx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( ) -