<s> } case <STR_LIT> : case <STR_LIT> : { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { static const auto ValidSatTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned Instrs = LT . second . getScalarSizeInBits ( ) == RetTy -> getScalarSizeInBits ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( any_of ( ValidSatTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first * Instrs ; break ; } case <STR_LIT> : { static const auto ValidAbsTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidAbsTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case <STR_LIT> : { InstructionCost Cost = <NUM_LIT> ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) .

getTypeForEVT ( RetTy -> getContext ( ) ) ;


<s> const TargetMachine & TM = AP . TM ; Mangler * Mang = AP . Mang ; const DataLayout & DL = AP . getDataLayout ( ) ; MCContext & Ctx = AP . OutContext ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MachO .


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . isPagerando ( ) ) { return getPOT ( JT , DAG ) ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) { return getAddrLarge ( JT , DAG ) ; } else if ( getTargetMachine ( ) . getCodeModel (


<s> w = ( __vector signed short ) vec_splats ( __w ) ; return ( __m64 ) ( ( __vector long long ) w ) [ <NUM_LIT> ] ; __m64_union __res ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT> ] =


<s> if ( mode1 == mode2 ) return NULL ; if ( ! TARGET_FLOAT128_CVT ) { if ( ( mode1 == KFmode && mode2 == IFmode ) || ( mode1 == IFmode && mode2 == KFmode ) ) return N_ ( <STR_LIT> <STR_LIT> ) ; if ( TARGET_IEEEQUAD && ( ( mode1 == IFmode && mode2 == TFmode ) || ( mode1 == TFmode && mode2 == IFmode )


<s> bool <ISA_LIT>AddressTypePromotion :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( F . isDeclaration ( ) ) return false ; Func = &


<s> } if ( matchADDRrr ( Addr , LHS , RHS ) ) { if ( dyn_cast < FrameIndexSDNode > ( RHS ) ) std :: swap ( LHS , RHS ) ; if ( matchADDRri ( RHS , Index , Offset ) ) { Base = LHS ; return true ; } if ( matchADDRri ( LHS , Base , Offset ) ) { Index = RHS ; return true ; } Base = LHS ; Index = RHS ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << '$' << ( int64_t ) Op . getImm ( ) << markup ( <STR_LIT> ) ; if ( CommentStream && ( Op . getImm ( ) > <NUM_LIT> || Op . getImm ( ) < - <NUM_LIT> ) ) * CommentStream << format ( <STR_LIT> PRIX64 <STR_LIT> , ( uint64_t ) Op . getImm ( ) ) ; }


<s> const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = <STR_LIT> ; Info . flags = MachineMemOperand :: MONone ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 )


<s> unsigned copyRegToRegClass ( const TargetRegisterClass * ToRC , unsigned SrcReg , unsigned Flag = <NUM_LIT> , unsigned SubReg = <NUM_LIT> ) { Register TmpReg = createResultReg ( ToRC


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( )


<s> EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> )


<s> SmallString < <NUM_LIT> > EHSecName ( Prefix ) ; if ( FnSecName != <STR_LIT> ) { EHSecName += FnSecName ; } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection ) ; emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> static void seh_emit_save ( FILE * f , struct seh_frame_state * seh , rtx reg , HOST_WIDE_INT cfa_offset ) { const unsigned int regno = REGNO ( reg ) ; HOST_WIDE_INT offset ; seh -> reg_offset [ regno ] = cfa_offset ; gcc_assert ( seh -> sp_offset >= cfa_offset ) ; offset = seh -> sp_offset -


<s> if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return read_only_private_data_section


<s> assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; if ( ! Subtarget . hasSSE2 ( ) || ! Op -> hasOneUse ( ) ) return SDValue ( ) ; APInt Mask = APInt :: getAllOnes ( Op . getScalarValueSizeInBits ( ) ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; Mask = APInt :: getLowBitsSet ( Src . getScalarValueSizeInBits ( ) , Op . getScalarValueSizeInBits ( ) ) ; Op = Src ; break ; } case <STR_LIT> : { if ( auto * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Mask = Cst -> getAPIntValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } break ; } } SmallVector < SDValue , <NUM_LIT> > VecIns ; if ( Op . getOpcode ( ) == <STR_LIT> && matchScalarReduction ( Op , <STR_LIT> , VecIns ) ) { EVT VT = VecIns [ <NUM_LIT> ] . getValueType ( ) ; assert ( llvm :: all_of ( VecIns , [ VT ] ( SDValue V ) { return VT == V . getValueType ( ) ; } ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getSizeInBits ( ) ) ) return SDValue ( ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [ Slot ] ; SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ) ; } <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , VecIns . back ( ) , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V ; } } if ( Op . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> BinOp ; if ( SDValue Match = DAG . matchBinOpReduction ( Op . getNode ( ) , BinOp , { <STR_LIT> } ) ) { <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , Match , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return


<s> const LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT SrcTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( ! DstTy . isVector ( ) && ! SrcTy . isVector ( ) && <STR_LIT> ) ; if ( I . getNumOperands ( ) != <NUM_LIT> ) return false ; if ( DstTy . getSizeInBits ( ) != <NUM_LIT> || SrcTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; auto * DstRC = & <STR_LIT> ; Register SubToRegDef = MRI . createVirtualRegister ( DstRC ) ; MachineInstr & SubRegMI = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; Register SubToRegDef2 = MRI . createVirtualRegister ( DstRC ) ; MachineInstr & SubRegMI2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MachineInstr & BFM = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( SubToRegDef ) . addUse ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( SubRegMI , TII


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . isX32 ( ) ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI


<s> if ( XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return <NUM_LIT> ; default : return <NUM_LIT>


<s> OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH


<s> if ( GET_MODE_BITSIZE ( mode ) < BITS_PER_WORD ) return mode_for_size ( BITS_PER_WORD , GET_MODE_CLASS ( mode ) , <NUM_LIT> ) . require ( ) ; return mode


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { unsigned SType =


<s> if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ;


<s> __builtin_altivec_stvxl ( ( vector signed int ) a1 , a2 ,


<s> unsigned retval = <NUM_LIT> ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = arm_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval


<s> SDLoc DL ( Op ) ; unsigned Opcode ; if ( is32Bit ( VT ) ) { Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Opcode = <STR_LIT> ; } else if ( DAG . ComputeNumSignBits ( Op1 ) > <NUM_LIT> ) { Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ; SDValue Ops [ <NUM_LIT>


<s> NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; std :: unique_ptr < DominatorTree > DeleteDT ; DominatorTree * DT = nullptr ; if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ; if ( DT == nullptr && ( NumInterestingAllocas > <NUM_LIT> || ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) ) { DeleteDT = std :: make_unique < DominatorTree > ( * F ) ; DT = DeleteDT . get ( ) ; } std :: unique_ptr < PostDominatorTree > DeletePDT ; PostDominatorTree * PDT = nullptr ; if ( auto * P = getAnalysisIfAvailable < PostDominatorTreeWrapperPass > ( ) ) PDT = & P -> getPostDomTree ( ) ; if ( PDT == nullptr && ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) { DeletePDT = std :: make_unique < PostDominatorTree > ( * F ) ; PDT = DeletePDT . get ( ) ; } SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = insertBaseTaggedPointer ( Allocas , DT ) ; for ( auto & I : Allocas ) { const AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( Info . Tag < <NUM_LIT> ) continue ; IRBuilder < > IRB ( Info . AI -> getNextNode ( ) ) ; Function * TagP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> , { Info . AI -> getType ( ) } ) ; Instruction * TagPCall = IRB . CreateCall ( TagP , { Constant :: getNullValue ( Info . AI -> getType ( ) ) , Base , ConstantInt :: get ( IRB . getInt64Ty ( ) , Info . Tag ) } ) ; if ( Info . AI -> hasName ( ) ) TagPCall -> setName ( Info . AI -> getName ( ) + <STR_LIT> ) ; Info . AI -> replaceAllUsesWith ( TagPCall ) ; TagPCall -> setOperand ( <NUM_LIT> , Info . AI ) ; if ( UnrecognizedLifetimes . empty ( ) && Info . LifetimeStart . size ( ) == <NUM_LIT> && Info . LifetimeEnd . size ( ) == <NUM_LIT> ) { IntrinsicInst * Start = Info . LifetimeStart [ <NUM_LIT> ] ; IntrinsicInst * End = Info . LifetimeEnd [ <NUM_LIT> ] ; uint64_t Size = dyn_cast < ConstantInt > ( Start -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Size = alignTo ( Size , kTagGranuleSize ) ; tagAlloca ( AI , Start -> getNextNode ( ) , Start -> getArgOperand ( <NUM_LIT> ) , Size ) ; if ( PDT != nullptr && postDominates ( PDT , End , Start ) ) { untagAlloca ( AI , End , Size ) ; } else { SmallVector < Instruction * , <NUM_LIT> >


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) .

isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ;


<s> if ( MinSPF == SPF_SMIN && PatternMatch :: match ( MinRHS , PatternMatch :: m_ConstantInt ( MinC ) ) && MinC -> getValue ( ) == ( ( - Imm ) - <NUM_LIT> ) ) return true ; } return false ; } ; if ( isSSatMin ( Inst -> getOperand ( <NUM_LIT> ) ) || ( Inst -> hasNUses ( <NUM_LIT> ) && ( isSSatMin ( * Inst -> user_begin ( ) ) || isSSatMin ( * ( ++ Inst -> user_begin ( ) ) ) ) ) ) return true ; } return false


<s> softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( RHS . getNode ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS


<s> static void moxie_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ; output_operand_lossage ( <STR_LIT>


<s> emitSel16 ( unsigned Opc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock (


<s> static rtx zero_all_vector_registers ( HARD_REG_SET need_zeroed_hardregs ) { if ( ! TARGET_AVX ) return NULL ; for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ; return gen_avx_vzeroall ( )


<s> return ; } emitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCFragment * InstructionFragment = getCurrentFragment ( ) ; SMLoc InstLoc = Inst . getLoc ( ) ; if ( LastLabel && ! LastLabel -> isUnset ( ) && LastLabelLoc . isValid ( ) && InstLoc . isValid ( ) ) { const SourceMgr * SourceManager = getContext ( ) .


<s> int Val = N -> getMaskElt ( i ) ; if ( Val >= <NUM_LIT> ) Mask |= Val ; if ( i != <NUM_LIT> ) Mask <<= <NUM_LIT> ; } return


<s> if ( MBB -> pred_size ( ) == <NUM_LIT> && Loop != nullptr && Loop -> getHeader ( ) == MBB ) { for ( auto I = MBB -> pred_begin ( ) ; I != MBB -> pred_end ( ) ; ++ I ) if ( Loop -> contains ( * I ) ) PredMBB = ( * I == MBB ? nullptr : * I ) ; } assert ( ( PredMBB == nullptr || ! Loop ||

Loop -> contains ( PredMBB ) ) && <STR_LIT> ) ;


<s> static SDValue LowerLabelRef ( SDValue HiPart , SDValue LoPart , bool isPIC , SelectionDAG & DAG ) { EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDLoc DL (


<s> else if ( LOC_REGNO_P ( regno ) ) return <NUM_LIT> + current_frame_info . n_input_regs + regno - LOC_REG ( <NUM_LIT> ) ; else if ( OUT_REGNO_P ( regno ) ) return ( <NUM_LIT> + current_frame_info . n_input_regs + current_frame_info . n_local_regs + regno - OUT_REG ( <NUM_LIT> ) ) ; else return regno


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ in_section = in_fini ; \ fprintf ( asm_out_file , <STR_LIT>


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt (


<s> return BB . succ_size ( ) == <NUM_LIT> ; } ; if ( ! isEligibleBB ( MBB ) ) return false ; unsigned NumPredBBs = MBB . pred_size ( ) ; if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock * TmpMBB = * MBB . pred_begin ( ) ; if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; } else return false ; MachineInstr * BI = & * MBB . getFirstInstrTerminator ( ) ; MachineInstr * CMPI = MRI -> getVRegDef ( BI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( int I = <NUM_LIT> ; I <= <NUM_LIT> ; I ++ ) if ( CMPI -> getOperand ( I ) . isReg ( ) ) { MachineInstr * Inst = MRI -> getVRegDef ( CMPI -> getOperand ( I ) . getReg ( ) ) ; if ( Inst -> getParent ( ) == & MBB && Inst -> getOpcode ( ) != <STR_LIT> ) return false ; } PredMBB = Pred1MBB ; MBBtoMoveCmp =


<s> if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Index == <NUM_LIT>


<s> static inline bool isVCTP ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } if ( ! EnableCombineMGatherIntrinsics ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; Register Reg = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( DstOpcode ) , <NUM_LIT> , MRI -> getTargetRegisterInfo ( ) , * MBB -> getParent ( ) ) ) ; MachineInstrBuilder Bld = BuildMI ( * MBB , MI , DL , TII -> get ( DstOpcode ) , Reg ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) Bld . add ( MO ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( Reg ) ; return


<s> vpmin_s8 ( int8x8_t a , int8x8_t b ) { return __builtin_aarch64_sminpv8qi ( a , b


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> static void removeUseSoftFloat ( Function & F ) { AttrBuilder B ; DEBUG ( errs ( ) << <STR_LIT> ) ; B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; F . removeAttributes ( AttributeList :: FunctionIndex , B ) ; if ( F . hasFnAttribute


<s> auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , { O0 , O1 } ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType ( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ; N = User ; ConstTrue = TrueRes ; ConstFalse = FalseRes ; } while ( N -> hasOneUse


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; IsTailCallReturn |= RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF .


<s> MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( MF -> getFunction ( ) , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; const MCSymbol * BaseSym = <ISA_LIT>FI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; for ( auto * JTBB : JTBBs ) { const MCExpr * Value = MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; if ( Size != <NUM_LIT> ) Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( <NUM_LIT>


<s> Register SspFirstShrReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( ShrRIOpc ) , SspFirstShrReg ) . addReg ( SspSubReg ) . addImm ( Offset ) ; unsigned IncsspOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowMBB , DL , TII -> get ( IncsspOpc ) ) . addReg ( SspFirstShrReg ) ; Register SspSecondShrReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( ShrRIOpc ) , SspSecondShrReg ) . addReg ( SspFirstShrReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( <STR_LIT> ) ; fixShadowMBB -> addSuccessor ( sinkMBB ) ; fixShadowMBB -> addSuccessor ( fixShadowLoopPrepareMBB ) ; unsigned ShlR1Opc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register SspAfterShlReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowLoopPrepareMBB , DL , TII -> get ( ShlR1Opc ) , SspAfterShlReg ) . addReg ( SspSecondShrReg ) ; Register Value128InReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned MovRIOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowLoopPrepareMBB , DL , TII -> get ( MovRIOpc ) , Value128InReg ) . addImm ( <NUM_LIT> ) ; fixShadowLoopPrepareMBB -> addSuccessor ( fixShadowLoopMBB ) ; Register DecReg = MRI . createVirtualRegister ( PtrRC ) ; Register CounterReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( <STR_LIT> ) , CounterReg ) . addReg ( SspAfterShlReg ) . addMBB ( fixShadowLoopPrepareMBB ) . addReg ( DecReg ) . addMBB ( fixShadowLoopMBB ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( IncsspOpc ) ) . addReg ( Value128InReg ) ; unsigned DecROpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( DecROpc ) , DecReg ) . addReg ( CounterReg ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( fixShadowLoopMBB ) . addImm ( <STR_LIT> ) ; fixShadowLoopMBB -> addSuccessor ( sinkMBB ) ; fixShadowLoopMBB -> addSuccessor ( fixShadowLoopMBB


<s> MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = llvm :: find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPELogAlign ( * U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i

) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) {


<s> for ( unsigned i = <NUM_LIT> , j = l ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ; int BitI1 = Mask [ l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( ! isUndefOrEqual ( BitI1 , j


<s> return ( __m128 ) __builtin_ia32_cmpunordps ( ( __v4sf ) __A ,


<s> if ( Model == TLSModel :: LocalDynamic ) Model = TLSModel :: GeneralDynamic ; } SDValue TPOff ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue TPWithOff_lo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , ThreadBase , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue TPWithOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPWithOff_lo , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return TPWithOff ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue SymAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ; return gen_avx_vzeroall (


<s> void <ISA_LIT>ConstantIslands :: scanFunctionJumpTables ( ) { for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & I : MBB ) if ( I . isBranch ( ) && ( I . getOpcode ( ) == <STR_LIT> || I . getOpcode ( ) == <STR_LIT> )


<s> if ( ! ( ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) || ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC0 = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> CC1 = cast < CondCodeSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ! Subtarget . hasAVX ( ) && ! ( cheap<ISA_LIT>FSETCC_SSE ( CC0 ) && cheap<ISA_LIT>FSETCC_SSE ( CC1 ) ) ) return SDValue ( ) ; unsigned NumElts = <NUM_LIT> / N00Type . getSizeInBits ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , N00Type , NumElts ) ; EVT BoolVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue ZeroIndex = DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Vec00 = DAG . getNode ( <STR_LIT> , DL , VecVT , N00 ) ; SDValue Vec01 = DAG . getNode ( <STR_LIT> , DL , VecVT , N01 ) ; SDValue Vec10 = DAG . getNode ( <STR_LIT> , DL , VecVT , N10 ) ; SDValue Vec11 = DAG . getNode ( <STR_LIT> , DL , VecVT , N11 ) ; SDValue Setcc0 = DAG . getSetCC ( DL , BoolVecVT , Vec00 , Vec01 , CC0 ) ; SDValue Setcc1 = DAG . getSetCC ( DL , BoolVecVT , Vec10 , Vec11 , CC1 ) ; SDValue Logic = DAG . getNode ( N -> getOpcode ( ) , DL , BoolVecVT , Setcc0 , Setcc1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Logic


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> break ; } printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , STI , O ) ; O << <STR_LIT>


<s> mips16_lay_out_constants ( true ) ; if ( mips_cfg_in_reorg ( ) ) { mips_df_reorg ( ) ; free_bb_for_insn (


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops


<s> MachineIRBuilder & MIRBuilder = Helper . MIRBuilder ; MachineRegisterInfo & MRI = * MIRBuilder . getMRI ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto BitReverse = MIRBuilder . buildBitReverse ( Ty , MI . getOperand ( <NUM_LIT> ) ) ; MIRBuilder . buildCTLZ ( MI . getOperand ( <NUM_LIT> )


<s> bool nosave_low_regs ; attrs = DECL_ATTRIBUTES ( current_function_decl ) ; interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ( ) ; trapa_handler = lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ; interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler ; nosave_low_regs = lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ; CLEAR_HARD_REG_SET ( * live_regs_mask ) ; if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && interrupt_handler && df_regs_ever_live_p ( FPSCR_REG ) ) target_flags &= ~ MASK_FPU_SINGLE ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && TARGET_FPU_SINGLE ) for ( int count = <NUM_LIT> , reg = FIRST_FP_REG ; reg <= LAST_FP_REG ; reg += <NUM_LIT> ) if ( df_regs_ever_live_p ( reg ) && df_regs_ever_live_p ( reg + <NUM_LIT> ) && ( ! call_used_regs [ reg ] || interrupt_handler ) && ++ count > <NUM_LIT> ) { target_flags &= ~ MASK_FPU_SINGLE ; break ; } rtx pr_initial = has_hard_reg_initial_val ( Pmode , PR_REG ) ; bool pr_live = ( pr_initial ? ( ! REG_P ( pr_initial ) || REGNO ( pr_initial ) != ( PR_REG ) ) : df_regs_ever_live_p ( PR_REG ) ) ; pr_live |= df_regs_ever_live_p ( RETURN_ADDRESS_POINTER_REGNUM ) ; bool has_call = pr_live ; int count ; for ( count = <NUM_LIT> , reg = FIRST_PSEUDO_REGISTER ; reg -- != <NUM_LIT> ; ) { if ( reg == PR_REG ? pr_live : interrupt_handler ? ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && ( ! fixed_regs [ reg ] || reg == MACH_REG || reg == MACL_REG || reg == PIC_OFFSET_TABLE_REGNUM ) && has_call ) ) && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM && reg != RETURN_ADDRESS_POINTER_REGNUM && reg != T_REG && reg != GBR_REG && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG && ( reg != FPSCR_REG || TARGET_FPU_ANY ) ) : ( ( false ) || ( df_regs_ever_live_p ( reg ) && ( ( ! call_used_regs [ reg ] && ! ( reg != PIC_OFFSET_TABLE_REGNUM && fixed_regs [ reg ] && call_used_or_fixed_reg_p ( reg ) ) ) || ( trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY ) ) ) || ( crtl -> calls_eh_return && ( reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ) ) || ( ( reg == MACL_REG || reg == MACH_REG ) && df_regs_ever_live_p ( reg ) && sh_cfun_attr_renesas_p ( ) ) ) ) { SET_HARD_REG_BIT ( * live_regs_mask , reg ) ; count += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ) ) ; if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && GET_MODE_CLASS ( REGISTER_NATURAL_MODE ( reg ) ) == MODE_FLOAT ) { if ( FP_REGISTER_P ( reg ) ) { if ( ! TARGET_FPU_SINGLE && ! df_regs_ever_live_p ( reg ^ <NUM_LIT> ) ) { SET_HARD_REG_BIT ( * live_regs_mask , ( reg ^ <NUM_LIT> ) ) ; count += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ^ <NUM_LIT> ) ) ; } } else if ( XD_REGISTER_P ( reg ) ) { target_flags &= ~ MASK_FPU_SINGLE ; } } } if ( nosave_low_regs && reg == R8_REG


<s> return __builtin_mve_vmovnbq_m_uv4si ( __a ,


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { return ( Opc == <STR_LIT> ) ? ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) *


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr ; return


<s> SDValue Undef = DAG . getUNDEF ( SveVT ) ; if ( VT . isFloatingPoint ( ) ) Src0 = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Src0 ) ; Src0 = DAG . getNode ( <STR_LIT> , DL , NeonVT , Src0 ) ; Mask = DAG . getNode ( <STR_LIT> , DL , NeonVT , Mask ) ; Idxs = DAG . getNode ( <STR_LIT> , DL , NeonVT , Idxs ) ; Src0 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Src0 ) ; Mask = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Mask ) ; Idxs = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Idxs ) ; EVT PredVT = SveVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Pg = getPTrue ( DAG , DL , PredVT , ( NumEls == <NUM_LIT> ) ? VL2 : VL4 ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask , Pg ) ; EVT MemVT = MGN -> getMemoryVT ( ) . changeTypeToInteger ( ) ; <STR_LIT> Ext = MGN ->


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm ; if ( Datasize ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) ; imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; } else { if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR32RegisterClass ( Inst , Rd


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & _MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) , MII ( _MII ) { Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> if ( CSI . empty ( ) ) return ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; for ( const auto & Info : CSI ) { if ( SVE != ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID :: ScalableVector ) ) continue ; unsigned Reg = Info . getReg ( ) ; if ( SVE && ! static_cast < const <ISA_LIT>RegisterInfo & > ( TRI ) . regNeedsCFI ( Reg , Reg ) ) continue ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , TRI . getDwarfRegNum (


<s> } else if ( isUInt < <NUM_LIT> > ( Imm ) ) { emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( Lo ) { Register TmpReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TmpReg )


<s> if ( MSA_SUPPORTED_MODE_P ( imode ) ) { switch ( imode ) { case E_V4SImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_w ; else unpack = gen_msa_ilvr_w ; cmpFunc = gen_msa_clt_s_w ; break ; case E_V8HImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_h ; else unpack = gen_msa_ilvr_h ; cmpFunc = gen_msa_clt_s_h ; break ; case E_V16QImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_b ; else unpack = gen_msa_ilvr_b ; cmpFunc = gen_msa_clt_s_b ; break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ <NUM_LIT> ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx


<s> rtx nds32_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { if ( count != <NUM_LIT>


<s> if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( )


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT>


<s> static unsigned int aarch64_autovectorize_vector_sizes ( void ) { return ( <NUM_LIT> | <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createNumericReg ( unsigned Index , const MCRegisterInfo

* RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue (


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_COP2 ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister (


<s> for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) ) { if ( searchBackward ( MBB , I ) ) continue ; if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I


<s> RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode ,


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext &


<s> bool <ISA_LIT>InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const { if ( DestRC != SrcRC ) { return false ; } DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if (


<s> return new <ISA_LIT>16InstrInfo ( STI


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS , RHS , Ops ) ; return DAG . getNode ( <STR_LIT> ,


<s> if ( builder . encoded_nelts ( ) == <NUM_LIT> ) return aarch64_emit_set_immediate ( target , builder ) ; unsigned int elt_size = aarch64_widest_sve_pred_elt_size ( builder ) ; if ( int vl = aarch64_partial_ptrue_length ( builder , elt_size ) ) { machine_mode mode = aarch64_sve_pred_mode ( elt_size ) . require ( ) ; if ( aarch64_svpattern_for_vl ( mode , vl ) != AARCH64_NUM_SVPATTERNS ) return aarch64_emit_set_immediate


<s> SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code64 ) ; } } else


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef CPU , bool Is64Bit ) : <ISA_LIT>AsmBackend ( T , CPU ) , MRI ( MRI ) , Is64Bit ( Is64Bit ) { memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; OffsetSize = Is64Bit ? <NUM_LIT> :


<s> bool branchTargetEnforcement ( ) const


<s> return isMem ( ) && isConstantMemOff ( ) && isInt < Bits


<s> static SDValue PerformORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DAG , Subtarget ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VorrVT ; SDValue Val = isVMOVModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VorrVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VorrVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vorr = DAG . getNode ( <STR_LIT> , dl , VorrVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) )


<s> type = build_qualified_type ( TREE_TYPE ( type ) , <NUM_LIT> ) ; type = build_pointer_type ( type ) ; arg = fold_convert ( type , arg ) ; } if ( fcode == RS6000_OVLD_VEC_LXVL && POINTER_TYPE_P ( type ) && TYPE_READONLY ( TREE_TYPE ( type ) ) ) { type = build_qualified_type ( TREE_TYPE ( type ) , <NUM_LIT> ) ; type = build_pointer_type ( type ) ; arg = fold_convert ( type , arg ) ; } args [ n ] = arg ; types [ n ] = type ; } if ( n != expected_args && ! ( fcode == RS6000_OVLD_VEC_PROMOTE || fcode == RS6000_OVLD_VEC_SPLATS || fcode == RS6000_OVLD_VEC_EXTRACT || fcode == RS6000_OVLD_VEC_INSERT || fcode == RS6000_OVLD_VEC_STEP ) ) return NULL ; tree returned_expr = NULL ; resolution res = unresolved ; if ( fcode == RS6000_OVLD_VEC_MUL ) returned_expr = resolve_vec_mul ( & res , args , types , loc ) ; else if ( fcode == RS6000_OVLD_VEC_CMPNE ) returned_expr = resolve_vec_cmpne ( & res , args , types , loc ) ; else if ( fcode == RS6000_OVLD_VEC_ADDE || fcode == RS6000_OVLD_VEC_SUBE ) returned_expr = resolve_vec_adde_sube ( & res , fcode , args , types , loc ) ; else if ( fcode == RS6000_OVLD_VEC_ADDEC || fcode == RS6000_OVLD_VEC_SUBEC ) returned_expr = resolve_vec_addec_subec ( & res , fcode , args , types , loc ) ; else if ( fcode == RS6000_OVLD_VEC_SPLATS || fcode == RS6000_OVLD_VEC_PROMOTE ) returned_expr = resolve_vec_splats ( & res , fcode , arglist , nargs ) ; else if ( fcode == RS6000_OVLD_VEC_EXTRACT ) returned_expr = resolve_vec_extract ( & res , arglist , nargs , loc ) ; else if ( fcode == RS6000_OVLD_VEC_INSERT ) returned_expr = resolve_vec_insert ( & res , arglist , nargs , loc ) ; else if ( fcode == RS6000_OVLD_VEC_STEP ) returned_expr = resolve_vec_step ( & res , arglist , nargs ) ; if ( res == resolved ) return returned_expr ; unsigned int adj_fcode = fcode - RS6000_OVLD_NONE ; if ( res == resolved_bad ) { const char * name = rs6000_overload_info [ adj_fcode ] . ovld_name ; error ( <STR_LIT> , name ) ; return error_mark_node ; } bool unsupported_builtin = false ; rs6000_gen_builtins instance_code ; bool supported = false ; ovlddata * instance = rs6000_overload_info [ adj_fcode ] . first_instance ; gcc_assert ( instance != NULL ) ; gcc_assert ( nargs > <NUM_LIT> || ! instance -> next ) ; switch ( fcode


<s> return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) ==


<s> bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) )


<s> for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int


<s> return ( __m256i ) __builtin_ia32_punpckhwd256 ( ( __v16hi ) __A ,


<s> Inst . addOperand ( MCOperand :: createReg ( ACCRegs [ getACCReg (


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> static SDValue getV4<ISA_LIT>ShuffleImm8ForMask ( ArrayRef < int > Mask , SDLoc DL , SelectionDAG & DAG ) { return DAG . getConstant ( getV4<ISA_LIT>ShuffleImm ( Mask


<s> if ( OpIdx + <NUM_LIT> >= NumOps ) return false ; assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && ( OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; if ( getIBit ( insn ) == <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; unsigned Imm12 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Offset = <STR_LIT> ( AddrOpcode , Imm12 , <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; getImmShiftSE ( ShOp , ShImm ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( AddrOpcode , ShImm , ShOp ) ) ) ; } OpIdx += <NUM_LIT> ; return true


<s> if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return val > - <NUM_LIT> && val < <NUM_LIT> ; else return val > - <NUM_LIT> && val < <NUM_LIT> ; } return TARGET_LDRD && arm_address_register_rtx_p ( index , strict_p ) ; } if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ! ( arm_arch4 && ( mode == HImode || mode == HFmode || ( mode == QImode && outer == SIGN_EXTEND ) ) ) ) { if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && power_of_two_operand ( xiop1 , SImode ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && power_of_two_operand ( xiop0 , SImode ) ) ) ; } else if ( code == LSHIFTRT || code == ASHIFTRT || code == ASHIFT || code == ROTATERT ) { rtx op = XEXP ( index , <NUM_LIT> ) ; return ( arm_address_register_rtx_p ( XEXP ( index , <NUM_LIT> ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ; } } if ( arm_arch4


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && GET_CODE ( elt ) == CONST_DOUBLE && real_equal ( CONST_DOUBLE_REAL_VALUE ( elt )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; } CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler =


<s> break ; case <STR_LIT> : ExtVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getOnesVector ( ExtVT , DAG , DL ) ; else V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; SDValue Shuffle = DAG . getVectorShuffle ( ExtVT , DL , V1 , V2 , Mask ) ; int NumElems = VT . getVectorNumElements ( ) ; if ( ( Subtarget . hasBWI ( ) && ( NumElems >= <NUM_LIT> ) ) || ( Subtarget . hasDQI ( ) && ( NumElems < <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Shuffle ) ; return DAG . getNode ( <STR_LIT> , DL


<s> static void checkIs32 ( MCContext & Ctx , SMLoc Loc , <ISA_LIT>_64RelType Type ) { if ( Type != RT64_32 ) Ctx .


<s> static <ISA_LIT>Operand * CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg ,


<s> return plus_constant ( Pmode , frame , -


<s> return ( <ISA_LIT>ArchVersion >= <ISA_LIT>32r3 && <ISA_LIT>ArchVersion <

<ISA_LIT>32Max ) || has<ISA_LIT>64r2 ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE


<s> return decodeUImmOperand < <NUM_LIT> > (


<s> return ( __m128i ) __builtin_ia32_vpcomeqd ( ( __v4si ) __A ,


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( LegalizerHelper & Helper , MachineInstr & MI ) const { MachineIRBuilder & MIRBuilder = Helper . MIRBuilder ; switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( createMemLibcall ( MIRBuilder , * MIRBuilder . getMRI ( ) , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent (


<s> return ( ( vec_int4 ) ( si_mpyh ( ( qword ) ( a


<s> do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( ArgRegsSaveSize ) { MBBI = MBB .


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym -> print ( O , P . MAI ) ; else { O << '(' ; GVSym -> print ( O , P . MAI ) ; O << ')' ; } P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; P . MF -> getPICBaseSymbol ( ) -> print ( O , P . MAI ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ; P . MF -> getPICBaseSymbol ( ) ->


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME )


<s> APInt Offset ( <NUM_LIT> , <NUM_LIT> ) ; const Value * BaseGV = PAI . getPointer ( ) -> stripAndAccumulateConstantOffsets ( getDataLayout ( ) , Offset , true ) ; auto * BaseGVB = dyn_cast < GlobalValue > ( BaseGV ) ; if ( ! BaseGVB ) { BaseGVB = PAI . getGV ( ) ; std :: string Buf ; raw_string_ostream OS ( Buf ) ; OS << <STR_LIT> << * BaseGVB << <STR_LIT> ; BaseGV -> getContext ( ) . emitError ( OS . str ( )


<s> if ( INSN_P ( insn ) ) return PATTERN ( insn ) ; return


<s> unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT>


<s> unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( )


<s> const MCExpr * ExtraImmOp = <NUM_LIT> ; if ( ( PatchedName . startswith ( <STR_LIT> ) || PatchedName . startswith ( <STR_LIT> ) ) && ( PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) ) ) { bool IsVCMP = PatchedName . startswith ( <STR_LIT> ) ; unsigned SSECCIdx = IsVCMP ? <NUM_LIT> : <NUM_LIT> ; unsigned SSEComparisonCode = StringSwitch < unsigned > ( PatchedName . slice ( SSECCIdx , PatchedName . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( SSEComparisonCode != ~ <NUM_LIT> ) { ExtraImmOp = MCConstantExpr :: Create ( SSEComparisonCode , getParser ( ) . getContext ( ) ) ; if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else { assert ( PatchedName . endswith ( <STR_LIT> ) && <STR_LIT> ) ; PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } } } if ( PatchedName . startswith ( <STR_LIT> )


<s> MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) { SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; } if (


<s> Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; case <STR_LIT> : lowerABS ( N , Results , DAG ) ; return ; case <STR_LIT> : LowerLOAD ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = LowerTruncate ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerVectorExtend ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerFP_TO_INT_SAT ( SDValue ( N , <NUM_LIT> ) ,


<s> LocInfo = CCValAssign :: Indirect ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; unsigned Reg ; const <ISA_LIT>Subtarget & Subtarget = State . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetELF ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else if ( Subtarget . isTargetXPLINK64 ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Offset = Reg && ! Subtarget . isTargetXPLINK64 ( ) ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg (


<s> case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint


<s> if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( MulAmt , N , DAG , VT , DL ) ; if ( ! NewMul ) { assert ( MulAmt != <NUM_LIT> && MulAmt != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; int64_t SignMulAmt = C -> getSExtValue ( ) ; if ( ( SignMulAmt != INT64_MIN ) && ( SignMulAmt != INT64_MAX ) && ( SignMulAmt != - INT64_MAX ) ) { int NumSign = SignMulAmt > <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; bool IsPowerOf2_64PlusOne = isPowerOf2_64 ( NumSign * SignMulAmt - <NUM_LIT> ) ; bool IsPowerOf2_64MinusOne = isPowerOf2_64 ( NumSign * SignMulAmt + <NUM_LIT> ) ; if ( IsPowerOf2_64PlusOne ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( NumSign * SignMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( IsPowerOf2_64MinusOne ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( NumSign * SignMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) ) ; } if ( ( IsPowerOf2_64PlusOne || IsPowerOf2_64MinusOne ) && NumSign == - <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL ,


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc


<s>
if
(
reversed
^
far
)
code
=
reverse_condition
(
code
)
;
gcc_assert
(
mode
==
DImode
)
;
switch
(
code
)
{
case
NE
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
EQ
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
GE
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
LT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
LE
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
GT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
<NUM_LIT>
)
)
>=
profile_probability
::
even
(
)
)
^
far
)
<STR_LIT>
:
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
*
p
=
p
<
string
+
<NUM_LIT>
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
<NUM_LIT>
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
<NUM_LIT>
&&
delta
<
<NUM_LIT>
)
veryfar
=
<NUM_LIT>
;
}
strcpy
(
p
,
<STR_LIT>
)
;
if
(
annul
||
!
final_sequence
)
p
[
<NUM_LIT>
]
=
'6'
;
p
+=
<NUM_LIT>
;
if
(
veryfar
)
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
else
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T


<s> vtstq_p16 ( poly16x8_t a , poly16x8_t b ) { return ( uint16x8_t ) ( ( ( ( uint16x8_t ) a ) & ( ( uint16x8_t ) b ) ) !=


<s> unsigned getVSRpEvenReg ( ) const { assert ( isVSRpEvenRegNumber ( ) && <STR_LIT> ) ; return ( unsigned ) Imm . Val >>


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , TTI :: TargetCostKind CostKind , const Instruction * I ) { int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , CostKind , I ) ; return vectorCostAdjustment ( Cost , Opcode , ValTy , nullptr


<s> long int <ISA_LIT>ELFWriterInfo :: computeRelocation ( unsigned SymOffset , unsigned RelOffset , unsigned RelTy ) const { llvm_unreachable ( <STR_LIT>


<s> AU . addRequired < MachineLoopInfo > (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getDefRegState ( true ) | getDeadRegState ( RegDeadKill ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) | getUndefRegState ( BaseUndef ) ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else


<s> } MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ElemTy == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . isABI_N64 ( ) )

return MachineJumpTableInfo :: EK_GPRel64BlockAddress ;


<s> V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getBuildVector ( <STR_LIT> , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DAG . getBuildVector ( <STR_LIT> , DL , V2Mask ) ) ; SDValue


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << Binary << std :: dec << <STR_LIT> ; MCE . emitWordLE (


<s> if ( sibcall_p ) insn = gen_sibcall_gp ( addr ) ; else if ( ! retval ) insn = gen_call_gp ( addr , b0 ) ; else insn = gen_call_value_gp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) ,


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI ,


<s> if ( hasFP ( MF ) ) { MRI -> setPhysRegUsed ( <STR_LIT> ) ; MRI -> setPhysRegUsed ( <STR_LIT> ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) MRI -> setPhysRegUsed ( RegInfo -> getBaseRegister ( ) ) ; unsigned NumGPRSpilled = <NUM_LIT> ; unsigned NumFPRSpilled = <NUM_LIT> ; bool ExtraCSSpill = false ; bool CanEliminateFrame = true ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; i += <NUM_LIT> ) { assert ( CSRegs [ i + <NUM_LIT> ] && <STR_LIT> ) ; const unsigned OddReg = CSRegs [ i ] ; const unsigned EvenReg = CSRegs [ i + <NUM_LIT> ] ; assert ( ( <STR_LIT> . contains ( OddReg ) && <STR_LIT> . contains ( EvenReg ) ) ^ ( <STR_LIT> . contains ( OddReg ) && <STR_LIT> . contains ( EvenReg ) ) && <STR_LIT> ) ; const bool OddRegUsed = MRI -> isPhysRegUsed ( OddReg ) ; const bool EvenRegUsed = MRI -> isPhysRegUsed ( EvenReg ) ; if ( ! OddRegUsed && ! EvenRegUsed ) { if ( <STR_LIT> . contains ( OddReg ) ) { UnspilledCSGPRs . push_back ( OddReg ) ; UnspilledCSGPRs . push_back ( EvenReg ) ; }


<s> SDValue NewDUP ; if ( IsDUPLANE ) NewDUP = DAG . getNode ( N . getOpcode ( ) , dl , NewDUPVT , N . getOperand ( <NUM_LIT> ) , N . getOperand ( <NUM_LIT> ) ) ; else NewDUP = DAG . getNode ( <STR_LIT> , dl , NewDUPVT , N . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , NarrowTy , NewDUP , DAG . getConstant


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> ,


<s> inline static bool isGlobalStubReference ( unsigned char TargetFlag ) { switch ( TargetFlag ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( ) ,


<s> SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op . getOperand ( <NUM_LIT> ) ) ; SDValue And0 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op0

, DAG . getConstant ( Mask - <NUM_LIT> , IntValTy ) ) ;


<s> return __builtin_mve_vmovntq_m_sv4si ( __a ,


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; int NumElts = VT . getVectorNumElements ( ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerVectorShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( VT . isInteger ( ) && ! Subtarget . hasAVX2 ( ) ) { int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getBitcast ( FpVT , V1 ) ; V2 = DAG . getBitcast ( FpVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I16VectorShuffle ( Op , V1 , V2 ,


<s> if ( ! Index ) return SDValue ( ) ; unsigned DstNumElt = DstVT . getVectorNumElements ( ) ; const APInt & APIntIndex = Index -> getAPIntValue ( ) ; APInt NewIndex ( APIntIndex . getBitWidth ( ) , DstNumElt ) ; NewIndex *= APIntIndex ; if ( NewIndex . getBitWidth ( ) > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue ExtractSrc = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , DstVT . getScalarType ( ) , ExtractSrc . getValueType ( ) . getVectorNumElements ( ) * DstNumElt ) ; SDValue BitCast = DAG . getNode ( <STR_LIT> ,


<s> insn_info = DF_INSN_INFO_GET ( load_insn ) ; use = DF_INSN_INFO_USES ( insn_info ) ; def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; rtx_insn * tocrel_insn = DF_REF_INSN ( def_link -> ref ) ; gcc_assert ( tocrel_insn ) ; rtx base , offset ; rtx tocrel_expr = SET_SRC ( PATTERN ( tocrel_insn ) ) ; const_rtx tocrel_base ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) gcc_unreachable ( ) ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; rtx const_vector = get_pool_constant ( base ) ; if ( SYMBOL_REF_P ( const_vector ) ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; rtx new_mem ; enum machine_mode mode = GET_MODE ( const_vector ) ; if ( mode == V1TImode ) return ; else if ( mode == V16QImode ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V8HImode ) || ( mode == V8HFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode ,


<s> auto & Inst = RF . getInst ( ) ; auto & STI = * RF . getSubtargetInfo ( ) ; bool Is16BitMode = STI . getFeatureBits ( ) [


<s> std :: string FullFS = FS ; if ( In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead = <NUM_LIT> ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer256Bit )


<s> } if ( cfun -> va_list_fpr_size ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( fpr ) , fpr , build_int_cst ( NULL_TREE , n_fpr ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( call_ABI_of_interest ( cfun -> decl ) ) rs6000_passes_float = true ; } t = make_tree ( TREE_TYPE ( ovf ) , virtual_incoming_args_rtx ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * MIN_UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size && n_gpr < GP_ARG_NUM_REG && n_fpr < FP_ARG_V4_MAX_REG ) return ; t = make_tree ( TREE_TYPE ( sav ) , virtual_stack_vars_rtx ) ; if ( cfun -> machine -> varargs_save_offset ) t = fold_build_pointer_plus_hwi ( t , cfun -> machine -> varargs_save_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( sav ) , sav , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode


<s> EVT VT = Op . getValueType ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || ( hasHardQuad && TLI . isTypeLegal ( VT ) ) ) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ; assert ( VT == <STR_LIT> ||


<s> getShiftRight32Imm ( const MCInst & MI , unsigned Op ,

SmallVectorImpl < MCFixup > & Fixups ) const {


<s> llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Result = Result & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HI : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHERA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHESTA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; } Res = MCValue :: get ( Result ) ; } else { MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case VK_<ISA_LIT>_HI : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case


<s> return getTargetMachine ( ) . getRelocationModel ( ) ==


<s> static void InsertReturnAddressAuth ( MachineFunction & MF , MachineBasicBlock & MBB ) { if ( ! ShouldSignReturnAddress ( MF ) ) return ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator (


<s> Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , <NUM_LIT> ) ; return DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget -> hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> ,


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Register ReservedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> void ix86_expand_convert_uns_sixf_sse ( rtx , rtx ) { gcc_unreachable ( )


<s> virtual const <ISA_LIT>ELFWriterInfo * getELFWriterInfo


<s> SDValue SelectOp1 = Select -> getOperand ( <NUM_LIT> ) ; SDValue SelectOp2 = Select -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) std :: swap ( SelectOp1 , SelectOp2 ) ; if ( ! ( SelectOp2 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SelectOp2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) && SelectOp2 . getOperand ( <NUM_LIT> ) == SelectOp1 ) ) return false ; if ( SetCC . getOperand ( <NUM_LIT> ) != SelectOp1 ) return false ; APInt SplatVal ; if ( ( CC == <STR_LIT> ) && ! ( ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isOneValue ( ) ) || ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ) return false ; if ( ( CC == <STR_LIT> ) && ! ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) || <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ; if ( SelectOp1 . getOpcode ( ) != <STR_LIT> ) return false ; Op0 = SelectOp1 . getOperand ( <NUM_LIT> ) ; Op1 = SelectOp1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return false ; return true


<s> int OffsetRegNum ; bool OffsetRegShifted ; enum ShiftType ShiftType ; const MCExpr * ShiftAmount = <NUM_LIT> ; const MCExpr * Offset = <NUM_LIT> ; if ( ParseMemoryOffsetReg ( Negative , OffsetRegShifted , ShiftType , ShiftAmount , Offset , OffsetIsReg , OffsetRegNum , E ) ) return true ; const AsmToken & RBracTok = Parser . getTok ( ) ; if ( RBracTok . isNot ( AsmToken :: RBrac ) ) { Error ( RBracTok . getLoc ( ) , <STR_LIT> ) ; return true ; } E = RBracTok . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; <ISA_LIT>Operand * WBOp = <NUM_LIT> ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { WBOp = <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ; Writeback = true ; Parser . Lex ( ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , OffsetIsReg , Offset , OffsetRegNum , OffsetRegShifted , ShiftType , ShiftAmount , Preindexed , Postindexed , Negative , Writeback , S , E ) ) ; if ( WBOp ) Operands . push_back ( WBOp ) ; return false ; } else if ( Tok . is ( AsmToken :: RBrac ) ) { E = Tok . getLoc ( ) ; Parser . Lex ( ) ; int OffsetRegNum = <NUM_LIT> ; bool OffsetRegShifted = false ; enum ShiftType ShiftType = Lsl ; const MCExpr * ShiftAmount = <NUM_LIT> ; const MCExpr * Offset = <NUM_LIT> ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . isNot ( AsmToken :: EndOfStatement ) ) { Postindexed = true ; Writeback =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case <STR_LIT> : case <STR_LIT>


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand


<s> case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> << size ) ) ; return