<s> if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg


<s> case G_VASTART : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_ADD : case G_SUB : case G_MUL : case G_SDIV : case G_SREM : case G_UDIV : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; if ( Op0Size == <NUM_LIT> ) OperandsMapping = getMSAMapping ( MF ) ; break ; case G_STORE : case G_LOAD : if ( Op0Size == <NUM_LIT> ) { OperandsMapping = getOperandsMapping ( { getMSAMapping ( MF ) , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } if ( ! Op0Ty . isPointer ( ) ) InstTy = TI . determineInstType ( & MI ) ; if ( InstTy == InstType :: FloatingPoint || ( Op0Size == <NUM_LIT> && InstTy == InstType :: Ambiguous ) ) OperandsMapping = getOperandsMapping ( { getFprbMapping ( Op0Size ) , & <STR_LIT> [ <STR_LIT> ] } ) ; else OperandsMapping = getOperandsMapping ( { getGprbOrCustomMapping ( Op0Size , MappingID ) , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_PHI : if ( ! Op0Ty . isPointer ( ) ) InstTy = TI . determineInstType ( & MI ) ; if ( InstTy == InstType :: Integer && Op0Size == <NUM_LIT> ) { OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] } ) ; return getInstructionMapping ( CustomMappingID , <NUM_LIT> , OperandsMapping , <NUM_LIT> ) ; } return getInstrMappingImpl ( MI ) ; case G_SELECT : { if ( ! Op0Ty . isPointer ( ) ) InstTy = TI . determineInstType ( & MI ) ; if ( InstTy == InstType :: FloatingPoint || ( Op0Size == <NUM_LIT> && InstTy == InstType :: Ambiguous ) ) { const RegisterBankInfo :: ValueMapping * Bank = getFprbMapping ( Op0Size ) ; OperandsMapping = getOperandsMapping ( { Bank , & <STR_LIT> [ <STR_LIT> ] , Bank , Bank } ) ; break ; } else { const RegisterBankInfo :: ValueMapping * Bank = getGprbOrCustomMapping ( Op0Size , MappingID ) ; OperandsMapping = getOperandsMapping ( { Bank , & <STR_LIT> [ <STR_LIT> ] , Bank , Bank } ) ; } break ; } case G_IMPLICIT_DEF : if ( ! Op0Ty . isPointer ( ) ) InstTy = TI . determineInstType ( & MI ) ; if ( InstTy == InstType :: FloatingPoint ) OperandsMapping = getFprbMapping ( Op0Size ) ; else OperandsMapping = getGprbOrCustomMapping ( Op0Size , MappingID ) ; break ; case G_UNMERGE_VALUES : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; MappingID = CustomMappingID ; break ; case G_MERGE_VALUES : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; MappingID = CustomMappingID ; break ; case G_FADD : case G_FSUB


<s> return __aarch64_vget_lane_any ( __a ,


<s> enum machine_mode mode ; tree type = TREE_TYPE ( field ) ; if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; mode = TYPE_MODE ( TREE_CODE ( type ) == ARRAY_TYPE ? get_inner_array_type ( type ) : type ) ; if ( mode == DFmode || mode == DCmode || GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return MIN ( <NUM_LIT> , computed ) ; return


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function


<s> void <ISA_LIT>AsmPrinter :: EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> RV , bool LE ) { using namespace <ISA_LIT>16HardFloatInfo ; unsigned MovOpc = <STR_LIT> ; switch ( RV ) { case FRet : EmitInstrRegReg ( STI , MovOpc , <STR_LIT> , <STR_LIT> ) ; break ; case DRet : EmitMovFPIntPair ( STI , MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case CFRet


<s> distance = increase_distance ( prev , next , distance ) ; if ( insn_uses_reg_mem ( regno , next ) ) { * found = true ; return distance ; } if ( insn_defines_reg ( regno , INVALID_REGNUM , next ) ) { * redefined = true ; return - <NUM_LIT> ; } prev = next ; } if ( next == BB_END ( bb ) ) break ; next = NEXT_INSN ( next


<s> assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned ATReg = <STR_LIT> ; unsigned FinalDstReg = <STR_LIT> ; unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool Is32Bit = isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ; unsigned FinalOpcode = Inst . getOpcode ( ) ; if ( DstReg == SrcReg ) { ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; FinalDstReg = DstReg ; DstReg = ATReg ; } if ( ! loadImmediate ( ImmValue , DstReg , <STR_LIT> , Is32Bit , false , Inst . getLoc ( ) , Out , STI ) ) { switch ( FinalOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode =


<s> const char * res ; if ( ( res = aarch64_general_mangle_builtin_type ( type ) ) || ( res = <STR_LIT> ( type ) ) ) return res ; } return NULL


<s> SDValue M = DAG . getNode ( <STR_LIT> , dl , VT , R , CM1 ) ; M = getTargetVShiftNode ( <STR_LIT> , dl , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , M ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , M , R ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , VSelM , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , VSelM ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , R , CM2 ) ; M = getTargetVShiftNode ( <STR_LIT> , dl , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , M ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , M , R ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , VSelM , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , VSelM ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , DAG . getNode ( <STR_LIT> , dl , VT , R , R ) , R ) ; return R ; } if ( VT . is256BitVector ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; SDValue V1 = Extract128BitVector ( R , <NUM_LIT> , DAG , dl ) ; SDValue V2 = Extract128BitVector ( R , NumElems


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> bool is<ISA_LIT>SOImmNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> return __builtin_mve_vrev64q_m_uv16qi ( __inactive ,


<s> MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) .


<s> bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI


<s> bool <ISA_LIT>FrameLowering :: shouldCombineCSRLocalStackBump ( MachineFunction & MF , unsigned StackBumpBytes ) const { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI . hasVarSizedObjects


<s> static SDValue lowerV16F32VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , const SmallBitVector & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( )


<s> Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV

) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ;


<s> ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> neg_b = vec_splat ( ( vec_uint4 ) ( si_from_int ( - b ) ) , <NUM_LIT> ) ; mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> else return false ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return true


<s> SMLoc ExprEnd ; if ( getParser ( ) . parseExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , MemStart , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . parseParenExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT>


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF


<s> else if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCRetInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType


<s> return ( vector signed char ) __builtin_altivec_vsubsbs ( ( vector signed char


<s> bool Fast ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Ld -> getAlignment ( ) >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , * Ld -> getMemOperand ( ) , & Fast ) && ! Fast ) ) ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; unsigned HalfOffset = <NUM_LIT> ; SDValue Ptr1 = Ld -> getBasePtr ( ) ; SDValue Ptr2 = DAG . getMemBasePlusOffset ( Ptr1 , HalfOffset , dl ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr1 , Ld -> getPointerInfo ( ) , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr2 , Ld -> getPointerInfo ( ) . getWithOffset ( HalfOffset ) , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , RegVT , Load1 , Load2 ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ; } if ( Ext == <STR_LIT> && ! Subtarget . hasAVX512 ( ) && RegVT . isVector ( ) && RegVT . getScalarType ( ) == <STR_LIT> && DCI . isBeforeLegalize ( ) ) { unsigned NumElts = RegVT . getVectorNumElements ( ) ; EVT IntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; if ( TLI . isTypeLegal ( IntVT


<s>
unsigned
OriginalError
=
MatchInstruction
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
switch
(
OriginalError
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
Match_Success
:
if
(
!
MatchingInlineAsm
&&
validateInstruction
(
Inst
,
Operands
)
)
return
true
;
if
(
!
MatchingInlineAsm
)
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
emitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_InvalidImmUnsignedi4
:
{
SMLoc
ErrorLoc
=
(
(
<ISA_LIT>Operand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
return
Error
(
ErrorLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
}
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
MissingFeatures
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
case
Match_MnemonicFail
:
case
Match_Unsupported
:
break
;
}
if
(
Op
.
getToken
(
)
.
empty
(
)
)
{
Error
(
IDLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
return
true
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
const
char
*
MemSize
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
FeatureBitset
ErrorInfoMissingFeatures
;
unsigned
Match
[
<NUM_LIT>
]
;
bool
HasVectorReg
=
false
;
<ISA_LIT>Operand
*
MemOp
=
nullptr
;
for
(
const
auto
&
Op
:
Operands
)
{
<ISA_LIT>Operand
*
<ISA_LIT>Op
=
static_cast
<
<ISA_LIT>Operand
*
>
(
Op
.
get
(
)
)
;
if
(
<ISA_LIT>Op
->
isVectorReg
(
)
)
HasVectorReg
=
true
;
else
if
(
<ISA_LIT>Op
->
isMem
(
)
)
{
MemOp
=
<ISA_LIT>Op
;
assert
(
MemOp
->
Mem
.
Size
==
<NUM_LIT>
&&
<STR_LIT>
)
;
break
;
}
}
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
if
(
MemOp
&&
HasVectorReg
)
MemOp
->
Mem
.
Size
=
MemSize
[
I
]
;
Match
[
I
]
=
Match_MnemonicFail
;
if
(
MemOp
||
!
HasVectorReg
)
{
Match
[
I
]
=
MatchInstruction
(
Operands
,
Inst
,
ErrorInfoIgnore
,
MissingFeatures
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
if
(
Match
[
I
]
==
Match_MissingFeature
)
ErrorInfoMissingFeatures
=
MissingFeatures
;
}
}
Op
.
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
std
::
count
(
std
::
begin
(
Match
)
,
std
::
end
(
Match
)
,
Match_Success
)
;
if
(
NumSuccessfulMatches


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TargetOptions Options = Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options ; return ( Options . UnsafeFPMath || Options . AllowFPOpFusion == FPOpFusion


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT>


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee )


<s> void \ init_section ( ) \ { \ if ( ( ! TARGET_ELF ) && in_section != in_init ) \

{ \ fprintf ( asm_out_file , <STR_LIT> , INIT_SECTION_ASM_OP ) ; \ in_section = in_init ; \ } \ }


<s> Function * MCR = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { Function * DMB = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Domain = Subtarget -> isMClass (


<s> static inline unsigned getT1Imm3 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>TDCPass ( )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI ,

const MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTPLT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTTPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_DTPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_TPOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PLT || XINT ( x , <NUM_LIT> ) == UNSPEC_PCREL || XINT ( x , <NUM_LIT> ) == UNSPEC_SYMOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PCREL_SYMOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTFUNCDESC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFFFUNCDESC ) ) return false ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E'


<s> bool <ISA_LIT>TTIImpl :: canMacroFuseCmp ( ) { return ST -> hasMacroFusion ( ) || ST ->


<s> return VectorList . Count == <NUM_LIT> &&


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab .


<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; MakeLibCallOptions CallOptions


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNum ; SMLoc RegEndLoc , LayoutLoc ; StringRef Layout ; if ( ! IdentifyRegister ( RegNum , RegEndLoc , Layout , LayoutLoc ) || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNum ) || Layout . size ( ) != <NUM_LIT> ) { return MatchOperand_NoMatch ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: RBrac ) ) { SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateWrappedReg ( RegNum , S , E ) ) ; return MatchOperand_Success ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex


<s> bool <ISA_LIT>AsmParser :: parseSetNoReorderDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken ::


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; EltIdx = ( EltIdx < <NUM_LIT> ) ? <NUM_LIT> : EltIdx - <NUM_LIT> ; pshufbMask . push_back ( DAG . getConstant ( EltIdx , <STR_LIT> ) ) ; } V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , V2 ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) ; SDValue NewV = V1 ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int Elt0 = MaskVals [ i * <NUM_LIT> ] ; int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ; if ( ( Elt0 & <NUM_LIT> ) != <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant ( <NUM_LIT> , TLI .

getShiftAmountTy ( InsElt0 . getValueType ( ) ) ) ) ;


<s> RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT>


<s> end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; cmp = gen_rtx_fmt_ee ( ( enum rtx_code ) code , cmp_mode , op0 , op1 ) ; target = gen_rtx_REG ( CCmode , CC_REGNUM ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , CCmode ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , cmp ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op0 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op1 ) ; start_sequence ( ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) { end_sequence ( ) ; return


<s> if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode


<s> } ; unsigned Opc = OpcTable [ IsZext ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true ; } return FastEmitInst_rii ( Opc , RC , Op0 ,


<s> if ( TARGET_LINUX_ABI ) init_sync_libfuncs


<s> void <ISA_LIT>LowOverheadLoops :: RevertWhile ( MachineInstr * MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * DestBB = getWhileLoopStartTargetBB ( * MI ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RevertWhileLoopStartLR ( MI , TII


<s> return ( uint16x8_t ) __builtin_neon_vmulluv8qi ( ( int8x8_t ) __a , (


<s> const MCExpr * getMemOff ( ) const { assert ( ( Kind == k_Memory ) && <STR_LIT> ) ; return Mem


<s> bool isToken ( ) const override { return Kind


<s> DEBUG_FUNCTION void rs6000_debug_print_mode ( ssize_t m ) { ssize_t rc ; fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( m ) ) ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) fprintf ( stderr , <STR_LIT> , reload_reg_map [ rc ] . name , rs6000_debug_addr_mask ( reg_addr [ m ] . addr_mask [ rc ] , true ) ) ; if ( rs6000_vector_unit [ m ] != VECTOR_NONE || rs6000_vector_mem [ m ] != VECTOR_NONE || ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) || ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) || reg_addr [ m ] . scalar_in_vmx_p ) { fprintf ( stderr , <STR_LIT> , rs6000_debug_vector_unit ( rs6000_vector_unit [ m ] ) , rs6000_debug_vector_unit ( rs6000_vector_mem [ m ] ) , ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) ? 's' : '*' , ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ? 'l' : '*' , ( reg_addr [ m ] . scalar_in_vmx_p ) ? 'y' : 'n' ) ; } fputs ( <STR_LIT> , stderr


<s> static bool matchFConstantToConstant ( MachineInstr & MI , MachineRegisterInfo & MRI ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) ; Register DstReg = MI . getOperand ( <NUM_LIT>


<s> return createMacroFusionDAGMutation (


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { for ( unsigned c = <NUM_LIT> ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO .


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI .

hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ,


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string =

opts -> x_aarch64_override_tune_string ;


<s> bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( )


<s> unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm ( <NUM_LIT> ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI ->


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && Subtarget . hasSSE2 ( ) ) { SDLoc dl ( N ) ; MVT IntVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Op0 = DAG . getBitcast ( IntVT , N -> getOperand (


<s> t = get_attr_type ( insn ) ; return is_fmac_op ( t ) || ( fmul_ok


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ,


<s> return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return NULL_RTX


<s> if ( ( ! State -> isFirstByValRegValid ( ) ) && ( <STR_LIT> <= reg ) && ( reg <= <STR_LIT> ) ) { State -> setFirstByValReg ( reg ) ; if ( State -> getCallOrPrologue ( ) ==


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( int i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i


<s> for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; i ++ ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i


<s> emitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> unsigned Align = GVar -> getAlignment ( ) ; unsigned RequiredPadding = <NUM_LIT> - ( Size % <NUM_LIT> ) ; bool PaddingPossible = RequiredPadding == <NUM_LIT> || ( CDAInit && CDAInit -> isString ( ) ) ; if ( ! PaddingPossible || Align > <NUM_LIT> || Size > ConstpoolPromotionMaxSize ) return SDValue ( ) ; unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , F ) && ! ( Size <= <NUM_LIT> && allUsersAreInFunctions ( GVar ) ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar ,


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; } return false


<s> static char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> ,


<s> if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N


<s> unsigned ResultReg = createResultReg ( RC ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = <STR_LIT> ; emitInst ( Opc , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } else if ( isUInt < <NUM_LIT> > ( Imm ) ) { emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TmpReg ) . addImm ( Hi ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return <NUM_LIT> ; if ( ! vsx_const -> all_words_same ) return <NUM_LIT> ; if ( vsx_const -> all_bytes_same ) return <NUM_LIT> ; if ( vsx_const -> all_half_words_same ) { short sign_h_word = vsx_const -> half_words [ <NUM_LIT> ] ; if ( EASY_VECTOR_15 ( sign_h_word )


<s> if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; ix86_adjust_counter ( count , i )


<s> case <STR_LIT> : Changed |= shortenOn001 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : { Changed |= shortenOn001AddCC ( MI , <STR_LIT> , CCLive ) ; break ; } case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; } unsigned UsedLow = <NUM_LIT> ; unsigned UsedHigh = <NUM_LIT> ; for ( auto MOI = MI . operands_begin ( ) , MOE = MI . operands_end ( ) ; MOI != MOE ; ++ MOI ) { MachineOperand & MO = * MOI ; if ( MO . isReg ( ) ) { if ( unsigned Reg = MO . getReg ( ) ) { assert ( Reg < <STR_LIT> && <STR_LIT> ) ; if ( MO . isDef ( ) ) { LiveLow &= ~ LowGPRs [ Reg ] ; LiveHigh &= ~ HighGPRs [ Reg ] ; } else if ( ! MO . isUndef (


<s> } if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + MaskCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; unsigned NumOfSources = Factor ; InstructionCost ShuffleCost = getShuffleCost ( TTI :: SK_PermuteTwoSrc , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfShufflesPerStore = NumOfSources - <NUM_LIT> ; unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore


<s> return addr_cost -> register_offset ; } } switch ( info . type ) { case ADDRESS_LO_SUM : case ADDRESS_SYMBOLIC : case ADDRESS_REG_IMM : cost += addr_cost -> imm_offset ; break ; case ADDRESS_REG_WB : if ( c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY ) cost += addr_cost -> pre_modify ; else if ( c == POST_INC || c == POST_DEC || c == POST_MODIFY ) cost += addr_cost -> post_modify ; else gcc_unreachable ( ) ; break ; case ADDRESS_REG_REG : cost += addr_cost -> register_offset ; break ; case ADDRESS_REG_SXTW : cost += addr_cost -> register_sextend ; break ; case ADDRESS_REG_UXTW : cost += addr_cost -> register_zextend ; break ; default : gcc_unreachable ( ) ; } if ( info . shift > <NUM_LIT>


<s> static SDValue LowerToTLSGeneralDynamicModel32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; unsigned RCSize = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; RCSize = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; RCSize = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; RCSize = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; RCSize = <NUM_LIT> ; break ; } if ( Size < RCSize


<s> bool <ISA_LIT>TargetLowering :: lowerInterleavedLoad ( LoadInst * LI , ArrayRef < ShuffleVectorInst * > Shuffles , ArrayRef < unsigned > Indices , unsigned Factor ) const { assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; unsigned VecSize = DL . getTypeAllocSizeInBits ( VecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( VecSize != <NUM_LIT> && VecSize != <NUM_LIT> ) ) return false ; Type * EltTy = VecTy -> getVectorElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr (


<s> const char * rs6000_overloaded_builtin_name ( enum rs6000_builtins fncode ) { return rs6000_builtin_info [ ( int ) fncode ]


<s> bool isSelectSupported ( SelectSupportKind Kind ) const override { return ( Kind != ScalarCondVectorVal


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) )


<s> auto * CPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( CP -> getConstants ( ) [ index ] . Val . MachineCPVal ) ; auto * Constant = cast < <ISA_LIT>ConstantPoolConstant > ( CPV ) ; Constant -> GVars . insert ( GVars . begin ( ) , GVars . end ( ) ) ; } return index


<s> unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BaseRegister = FP ? <STR_LIT> : <STR_LIT> ; MI . getOperand ( i ) . ChangeToRegister ( BaseRegister , false ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( Offset <= <NUM_LIT> && Offset >= - <NUM_LIT> ) { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( BaseRegister ) . addImm ( Offset ) ; } else { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Offset ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> )

, <STR_LIT> ) . addReg ( BaseRegister ) . addReg ( <STR_LIT> ) ;


<s> hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DCI , Subtarget ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VorrVT ; SDValue Val = isVMOVModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VorrVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VorrVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vorr = DAG . getNode ( <STR_LIT> , dl , VorrVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result


<s> if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) return <STR_LIT> ; else { if ( GET_MODE ( operands [ <NUM_LIT> ] ) == XFmode ) return


<s> if ( Reg != <STR_LIT> ) BusyRegs . push_back (


<s> const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI ->

getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ;


<s> static bool isPreISelGenericFloatingPointOpcode ( unsigned Opc ) { switch ( Opc ) { case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : return true


<s> Out . EmitBundleLock ( true ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock ( )


<s> if ( Kind == k_RegisterIndex && RegIdx . Index == <NUM_LIT> && RegIdx . Kind & RegKind_GPR


<s> unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand (


<s> if ( Is32BitImm ) { if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { ImmValue = SignExtend64 < <NUM_LIT> > ( ImmValue ) ; } else { Error ( IDLoc , <STR_LIT> ) ; return true ; } } bool UseSrcReg = false ; if ( SrcReg != <STR_LIT> ) UseSrcReg = true ; unsigned TmpReg = DstReg ; if ( UseSrcReg && ( DstReg == SrcReg ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { if ( ! UseSrcReg ) SrcReg = <STR_LIT> ; emitRRI ( <STR_LIT> , DstReg , SrcReg , ImmValue , IDLoc , Instructions ) ; } else if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { unsigned TmpReg = DstReg ; if ( SrcReg == DstReg ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } emitRRI ( <STR_LIT> , TmpReg , <STR_LIT> , ImmValue , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; } else if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; if ( ! Is32BitImm && ! isInt < <NUM_LIT> > ( ImmValue ) ) { emitRRI ( <STR_LIT> , TmpReg , <STR_LIT> , Bits31To16 , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; } else emitRI ( <STR_LIT> , TmpReg , Bits31To16 , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits15To0 , TmpReg , IDLoc , Instructions ) ; if ( UseSrcReg ) createAddu ( DstReg , TmpReg , SrcReg , ! Is32BitImm , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits47To32 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; emitRI ( <STR_LIT> , TmpReg , Bits47To32 , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits31To16 , TmpReg , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits15To0 , TmpReg , IDLoc , Instructions ) ; if ( UseSrcReg ) createAddu ( DstReg , TmpReg , SrcReg , ! Is32BitImm , Instructions ) ; } else { warnIfNoMacro ( IDLoc ) ; uint16_t Bits63To48 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits47To32 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT>


<s> unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#' << Val ; if ( Shift != <NUM_LIT> ) printShifter ( MI , OpNum + <NUM_LIT> , STI , O ) ; if ( CommentStream ) * CommentStream << '=' << ( Val << Shift ) << '\n' ; }


<s> HOST_WIDE_INT high = value >> <NUM_LIT> ; if ( high == <NUM_LIT> || high == - <NUM_LIT> ) return <NUM_LIT> ; high >>= <NUM_LIT> ; if ( low == <NUM_LIT> ) return num_insns_constant_wide ( high ) + <NUM_LIT> ; else if ( high == <NUM_LIT> ) return num_insns_constant_wide ( low ) + <NUM_LIT> ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + <NUM_LIT> ) ; } else return


<s> rtx pmv = XEXP ( src , <NUM_LIT> ) ; rtx src_reg = XEXP ( pmv , <NUM_LIT> ) ; rtx src_mod = XEXP ( pmv , <NUM_LIT> ) ; rtx set = gen_rtx_SET ( src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , <NUM_LIT> ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) && ! xstormy16_below100_operand ( dest , mode ) && ! REG_P ( src ) && GET_CODE (

src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ;


<s> unsigned <ISA_LIT>ABIInfo :: GetZeroReg ( ) const { return AreGprs64bit ( ) ? <STR_LIT> :


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; SDValue ResValue = Outs [ i ]


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - <NUM_LIT> ) ; SrcML = MachineLocation ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - <NUM_LIT> ) ; SrcML = MachineLocation ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML


<s> gimple * gimple_folder :: fold_to_pfalse ( ) { return gimple_build_assign ( lhs , build_zero_cst ( TREE_TYPE ( lhs ) )


<s> bool mergeStoresAfterLegalization ( EVT MemVT ) const override { return ! MemVT . isVector ( )


<s> } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 (


<s> vst1_p16 ( poly16_t * a , poly16x4_t b


<s> unsigned CopyOpcodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; CopyOpcodes [ i ] != - <NUM_LIT> ; i ++ ) if ( Opcode


<s> unsigned postOffset ( unsigned LogAlign = <NUM_LIT> ) const { unsigned PO = Offset + Size ; return


<s> for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS << '\x7' ; return true


<s> while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) && get_attr_length ( insn )


<s> void addImmOperands ( MCInst & Inst , unsigned


<s> auto & MF = * FirstMI . getParent ( ) -> getParent ( ) ; auto AnySubOrSuperRegCalleePreserved = [ & MF , TRI ] ( MCPhysReg PR ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ & MF , TRI ] ( MCPhysReg SubOrSuper ) { return TRI -> isCalleeSavedPhysReg ( SubOrSuper , MF ) ; } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) :


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst .

addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> bool broadcast_perm = true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { nd . perm [ i ] = d -> perm [ i ] & mask ; if ( nd . perm [ i ] != i ) identity_perm = false ; if ( nd . perm [ i ] ) broadcast_perm = false ; } if ( identity_perm ) { if ( ! d -> testing_p ) emit_move_insn ( d -> target , d -> op0 ) ; return true ; } else if ( broadcast_perm && TARGET_AVX2 ) { rtx ( * gen ) ( rtx , rtx ) = NULL ; switch ( d -> vmode ) { case E_V64QImode : if ( TARGET_AVX512BW ) gen = gen_avx512bw_vec_dupv64qi_1 ; break ; case E_V32QImode : gen = gen_avx2_pbroadcastv32qi_1 ; break ; case E_V32HImode : if ( TARGET_AVX512BW ) gen = gen_avx512bw_vec_dupv32hi_1 ; break ; case E_V16HImode : gen = gen_avx2_pbroadcastv16hi_1 ; break ; case E_V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16si_1 ; break ; case E_V8SImode : gen = gen_avx2_pbroadcastv8si_1 ; break ; case E_V16QImode : gen = gen_avx2_pbroadcastv16qi ; break ; case E_V8HImode : gen = gen_avx2_pbroadcastv8hi ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16sf_1 ; break ; case E_V8SFmode : gen = gen_avx2_vec_dupv8sf_1 ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8df_1 ; break ; case E_V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i ] = d -> perm [ i ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT>


<s> const TargetRegisterInfo * TRI = MI -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI -> getFlags ( ) & MachineInstr :: FrameDestroy ) return <NUM_LIT> ; if ( MI -> register_sgx_type != <NUM_LIT> ) return MI -> register_sgx_type ; if ( MI -> mayLoad ( ) && MI -> sgx_type == <NUM_LIT> ) { MI -> dump ( ) ; errs ( ) << ( void * ) MI << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } if ( MI -> isCall ( ) ) { if ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> uses ( ) . begin ( ) -> getReg ( ) == ( MI -> uses ( ) . begin ( ) + <NUM_LIT> ) -> getReg ( ) ) return <NUM_LIT> ; } if ( MI -> mayLoad ( ) && MI -> sgx_type == <NUM_LIT> ) return <NUM_LIT> ; for ( auto OP = MI -> uses ( ) . begin ( ) ; OP != MI -> uses ( ) . end ( ) ; OP ++ ) { if ( OP -> isReg ( ) && OP -> getReg ( ) != <STR_LIT> && OP -> getReg ( ) != <STR_LIT> && OP -> getReg ( ) != <STR_LIT> && MI -> readsRegister ( OP -> getReg ( ) , TRI ) ) { if ( private_set . find ( OP -> getReg ( ) ) != private_set . end ( ) ) { return <NUM_LIT> ; } } } return


<s> DIExpression * Expr = const_cast < DIExpression * > ( MI . getDebugExpression ( ) ) ; if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable ( ) ; if ( IsIndirect ) assert ( MI . getOperand ( <NUM_LIT> ) . getImm


<s> SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , <STR_LIT> , dl , DAG . getEntryNode ( ) , FudgePtr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild ,


<s> const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode

( ) , MachinePointerInfo :: getGOT ( ) ) ;


<s> Opcode = <STR_LIT> ; if ( TrueVal32 > FalseVal32 ) { Swap = true ; } } } else if ( ( TrueVal == FalseVal + <NUM_LIT> ) || ( TrueVal + <NUM_LIT> == FalseVal ) ) { Opcode = <STR_LIT> ; if ( TrueVal > FalseVal ) { Swap = true ; } } if ( Swap ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } if ( Opcode != <STR_LIT> ) { FVal = TVal ; } } SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; EVT VT = TVal . getValueType ( ) ; return DAG . getNode ( Opcode , dl , VT , TVal , FVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; EVT VT = TVal . getValueType ( ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; SDValue CS1 = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , CC1Val , Cmp ) ; if ( CC2 != <STR_LIT> ) { SDValue CC2Val = DAG . getConstant ( CC2 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TVal , CS1 , CC2Val ,


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , IsV9 ( false ) , V8DeprecatedInsts ( false ) , IsVIS ( false ) ,

Is64Bit ( is64Bit ) , HasHardQuad ( false ) , UsePopc ( false ) {


<s> if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; llvm :: sort ( Candidates , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti || Candidate -> CanMergeToLSDouble ) { MachineInstr * Merged = MergeOpsUpdate ( * Candidate ) ; if ( Merged ) { Changed = true ; unsigned Opcode = Merged -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MergeBaseUpdateLSDouble ( * Merged ) ; else MergeBaseUpdateLSMultiple ( Merged ) ; } else { for ( MachineInstr * MI : Candidate -> Instrs ) { if ( MergeBaseUpdateLoadStore ( MI ) ) Changed = true ; } } } else { assert ( Candidate -> Instrs . size ( ) == <NUM_LIT> ) ; if ( MergeBaseUpdateLoadStore ( Candidate -> Instrs . front ( ) ) ) Changed = true ; } } Candidates . clear ( ) ; for ( MachineInstr * MI : MergeBaseCandidates ) MergeBaseUpdateLSDouble ( * MI ) ; MergeBaseCandidates . clear (


<s> return ( __m512i ) __builtin_ia32_psrawi512_mask ( ( __v32hi ) __A , __imm , (


<s> O << RegName ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print


<s> if ( Val > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler :: Success


<s> int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , RegTok . getLoc ( ) , RegTok . getEndLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok


<s> } else if ( auto * I = dyn_cast < Instruction > ( V ) ) { if ( I -> getOpcode ( ) == Instruction :: Mul ) return I ; } return nullptr ; } ; auto InsertMul = [ this ] ( Instruction * I ) { Value * LHS = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) ; Value * RHS = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) ; Muls . push_back ( std :: make_unique < MulCandidate > ( I , LHS , RHS ) ) ; } ; for ( auto * Add : Adds ) { if ( Add == Acc ) continue ; if ( auto * Mul = GetMulOperand ( Add -> getOperand ( <NUM_LIT> ) ) ) InsertMul ( Mul ) ; if ( auto * Mul = GetMulOperand ( Add -> getOperand ( <NUM_LIT>


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( ( UseSExt ) ? CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) . addImm ( <NUM_LIT>


<s> DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , SVI -> getType ( ) ) ; SubVecs [ SVI ] . push_back ( SubVec ) ; } } for ( ShuffleVectorInst * SVI : Shuffles ) { auto & SubVec = SubVecs


<ISA_LIT>WinCOFFObjectWriter > ( Is64Bit ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr *


<s> Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Opcode , Op0 , Op1 ,

Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> if ( flags & SECTION_TLS ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( <STR_LIT> , asm_out_file ) ; fputc ( '\n' , asm_out_file


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool InsertAcc ( Value * V ) { if ( Acc ) return false ; Acc = V ; return


<s> case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT>


<s> ArrayRef < MCPhysReg > <ISA_LIT>BaseRegisterInfo :: getIntraCallClobberedRegs ( const MachineFunction * MF ) const { static const MCPhysReg IntraCallClobberedRegs [ ] = {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return


<s> unsigned <ISA_LIT>InstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { assert ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) && <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MBBI != FirstMBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; const TargetInstrInfo * TII = TM .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; } uint64_t TSFlags = getInstDesc ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( TSFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && ! hasEightFccRegisters ( ) ) return Match_NoFCCRegisterForCurrentISA ; return Match_Success


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNum , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( false ) ; if ( Op != nullptr ) RegNum = Op


<s> if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error (


<s> if ( Func . getName ( ) != <STR_LIT> && Func . getName ( ) != <STR_LIT> ) return false ; if ( Constant * Exp = dyn_cast < Constant > ( CI -> getArgOperand ( <NUM_LIT> ) ) ) if ( ConstantFP * CFP = dyn_cast_or_null < ConstantFP > ( Exp -> getSplatValue ( ) ) ) { if ( ! CI -> hasNoInfs ( ) || ! CI -> hasApproxFunc ( ) ) return false ; if ( ! CFP -> isExactlyValue ( <NUM_LIT> ) && ! CFP -> isExactlyValue ( <NUM_LIT> ) ) return false ; if ( CFP -> isExactlyValue ( <NUM_LIT> ) && ! CI -> hasNoSignedZeros ( ) ) return false ; CI -> setCalledFunction ( <STR_LIT> ( & M , <STR_LIT> , CI -> getType ( ) ) ) ; return


<s> unsigned ImmOp = Inst . getNumOperands ( ) - <NUM_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( ImmOp ) . isImm ( ) && ( ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Inst

. getNumOperands ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL )

, Subtarget ( TT , CPU , FS ) , DL ( ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple (


<s> FunctionPass * llvm :: create<ISA_LIT>BoolRetToIntPass (


<s> void <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry )


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ,


<s> Name = ( Name [ <NUM_LIT> ] == 'r' ) ? Name . drop_front ( <NUM_LIT> ) : Name . drop_front ( ) ; switch ( Name . size ( ) ) { default : return - <NUM_LIT> ; case <NUM_LIT> : switch ( Name [ <NUM_LIT> ] ) { default : return - <NUM_LIT> ; case '0' : return <NUM_LIT> ; case '1' : return <NUM_LIT> ; case '2' : return <NUM_LIT> ; case '3' : return <NUM_LIT> ; case '4' : return <NUM_LIT> ; case '5' : return <NUM_LIT> ; case '6' : return <NUM_LIT> ; case '7' : return


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O <<


<s> void <ISA_LIT>TargetMachine :: resetSubtarget ( MachineFunction * MF ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( MF -> getFunction


<s> inline int vec_all_gt ( vector float a1 ,


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry CostTblNoPairwise [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT>


<s> bool is<ISA_LIT>6xx ( ) const { return Is<ISA_LIT>6xx


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode ( )


<s> if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps -

<NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = MBB . end ( ) ; for ( MachineInstr & MI : MBB ) { bool IsCall = MI . isCall ( ) ; bool IsReturn = MI . isReturn ( ) ; bool IsControlFlow = IsCall || IsReturn ; if ( Is<ISA_LIT>INTR && IsReturn ) continue ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { CurState = EXITS_CLEAN ; continue ; } if ( ! IsControlFlow && CurState == EXITS_DIRTY ) continue ; if ( hasYmmOrZmmReg ( MI ) ) { CurState = EXITS_DIRTY ; continue ; } if ( ! IsControlFlow ) continue ; if ( IsCall && ! callHasRegMask ( MI ) ) continue ; if ( CurState


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue


<s> void addVectorIndexHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( )


<s> break ; case LABEL_REF : x = XEXP ( x , <NUM_LIT> ) ; case CODE_LABEL : ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , CODE_LABEL_NUMBER ( x ) ) ; assemble_name ( asm_out_file , buf ) ; break ; case CONST_INT : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case CONST : output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) { if ( CONST_DOUBLE_HIGH ( x ) || CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) fprintf ( file , <STR_LIT> , ( unsigned long ) CONST_DOUBLE_HIGH ( x ) , ( unsigned long ) CONST_DOUBLE_LOW ( x ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , CONST_DOUBLE_LOW ( x ) ) ; } else output_operand_lossage ( <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else { gcc_assert ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } break ; case MINUS : if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '-' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']' , file ) ; break ; case UNSPEC : gcc_assert ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) ; output_pic_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , code ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTPCREL : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_NTPOFF : if ( TARGET_64BIT ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_DTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTNTPOFF : if ( TARGET_64BIT ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI , OpNum ,


<s> if ( tryOptCompareBranchFedByICmp ( I , ICmp , MIB ) ) return true ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; auto PredOp = ICmp . getOperand ( <NUM_LIT> ) ; emitIntegerCompare ( ICmp . getOperand ( <NUM_LIT> ) , ICmp . getOperand ( <NUM_LIT> ) , PredOp , MIB ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( static_cast < CmpInst :: Predicate > ( PredOp . getPredicate ( ) ) ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , isO32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , Subtarget -> mipsSEUsesSoftFloat ( ) , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = isN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ]


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter & Printer ) { MCContext & Ctx = Printer . OutContext ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO16 ; else if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_HA16 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_None ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr

:: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > NonPredicated ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; NonPredicated . insert ( MI ) ; continue ; } } Predicated . insert ( MI ) ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutMIs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutUsers ; SmallVector < MachineBasicBlock * , <NUM_LIT> >


<s> assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr :: VK_PLT : assert ( Type == RT32_32 ) ; return ELF :: R_386_PLT32 ; case MCSymbolRefExpr :: VK_INDNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE ; case MCSymbolRefExpr :: VK_GOTNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GOTIE


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT SrcVT = ExtVal . getOperand ( <NUM_LIT> ) . getValueType


<s> State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset = State . AllocateStack ( SizeInBytes , SizeInBytes ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> if ( Subtarget . hasPAuth ( ) ) MI . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: InternalRead ) ; MI . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createNegateRAState ( nullptr ) ) ; BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; if ( Subtarget . hasPAuth ( ) && MBBAUT != MBB . end ( ) && MBBAUT -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBAUT , DL , TII -> get ( ShouldSignReturnAddrWithAKey ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBAUT ) ; MBB . erase (


<s> if ( __count >= <NUM_LIT> ) { if ( __count >= <NUM_LIT> ) { const __v16qu zero = { <NUM_LIT> } ; return ( __m128i ) zero ; } else { const __v16qu __shift = vec_splats ( ( unsigned char ) ( ( __count - <NUM_LIT> ) * <NUM_LIT> ) ) ; return ( __m128i ) vec_sro ( ( __v16qu ) __A , __shift ) ; return ( __m128i ) vec_slo ( ( __v16qu ) __A , __shift ) ; } } else { const __v16qu __shiftA = vec_splats ( ( unsigned char ) ( ( <NUM_LIT> - __count ) * <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerSTACKMAP ( const MachineInstr & MI ) { SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; SM . recordStackMap ( MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT>


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string jumpLabel = <STR_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) jumpLabel = MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) -> getName ( ) ; SExpr * call = ctx -> call ( ctx -> labelRef ( jumpLabel ) ) ; alfbb . addStatement ( label , TII -> getName ( MI . getOpcode


<s> return ( __m128i ) __builtin_ia32_vpcomneqw ( ( __v8hi )