<s> unsigned Srl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = CountTrailingOnes_32 ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return nullptr ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB <


<s> void addComplexRotationEvenOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast <


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc )


<s> void <ISA_LIT>InstPrinter :: printShiftOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O , <STR_LIT> Shift ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( Shift == <STR_LIT> && MO . isImm ( ) && MO . getImm ( ) == <NUM_LIT>


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags ) { char * ext ; const struct processor * cpu ; char * str = ( char * ) alloca ( strlen ( to_parse ) + <NUM_LIT> ) ; size_t len ; strcpy ( str , to_parse ) ; ext = strchr ( str , '+' ) ; if ( ext != NULL ) len = ext - str ; else len = strlen ( str ) ; if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , str , len ) == <NUM_LIT> ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags =


<s> int rx = RegIndex ( mo . getReg ( ) ) ; if ( rx < <NUM_LIT> ) continue ; Force ( rx , domain ) ; } for ( unsigned i = <NUM_LIT> , e = mi -> getDesc ( ) . getNumDefs ( ) ; i != e ; ++ i ) { MachineOperand & mo = mi -> getOperand ( i ) ; if ( ! mo . isReg ( ) ) continue ; int rx = RegIndex ( mo . getReg ( ) ) ; if ( rx <


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo


return new <ISA_LIT>TargetELFStreamer ( S ) ;


<s> void <ISA_LIT>InstPrinter :: printSIMDType10Operand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned RawVal = MI -> getOperand ( OpNo


<s> LEASLInst . addOperand ( RD ) ; MCOperand CZero = MCOperand :: createImm ( <NUM_LIT> ) ; LEASLInst . addOperand ( CZero ) ; LEASLInst . addOperand ( CZero ) ; LEASLInst . addOperand (


<s> bool hasV7Ops ( ) const { return getSTI ( ) . getFeatureBits ( )


<s> StackSize = State . getNextStackOffset ( ) ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( ! Info . IsFixed ) NumXMMRegs = State . getFirstUnallocated ( XMMArgRegs ) ; return Res


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine (

T , TT , CPU , FS , Options , RM , CM , OL , false ) , DL ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isCtlzFast (


<s> static DecodeStatus DecodeFCCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned DestinationRegister , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * ) const { DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned getImmShiftOpValue ( const MCInst & MI , unsigned Idx , SmallVectorImpl < MCFixup >

& Fixups , const MCSubtargetInfo & STI ) const {


<s> __asm__ volatile ( <STR_LIT> : [ val ] <STR_LIT> ( __rdtime . value ) , [ tid ] <STR_LIT> ( __rdtime . timeid ) : ) ; return


<s> for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { std :: vector < CPEntry > & CPEs =


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = <NUM_LIT>


<s> } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) ( MMO ) ; return false


, <NUM_LIT> , ( __mmask64 ) - <NUM_LIT> ) ;


<s> SDValue Ptr = MaskLoad -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) == <STR_LIT> ) Ptr = Ptr -> getOperand


<s> RegDU . setUnallocatableRegs ( * MBB . getParent ( ) ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( * TM . getDataLayout ( ) , MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) ,

RegDU , * IM , Slot , Filler ) ) return false ;


<s> sh_cpu = PROCESSOR_SH1 ; assembler_dialect = <NUM_LIT> ; if ( TARGET_SH2 ) sh_cpu = PROCESSOR_SH2 ; if ( TARGET_SH2E ) sh_cpu = PROCESSOR_SH2E ; if ( TARGET_SH2A ) sh_cpu = PROCESSOR_SH2A ; if ( TARGET_SH3 ) sh_cpu = PROCESSOR_SH3 ; if ( TARGET_SH3E ) sh_cpu = PROCESSOR_SH3E ; if ( TARGET_SH4 ) { assembler_dialect = <NUM_LIT> ; sh_cpu = PROCESSOR_SH4 ; } if ( TARGET_SH4A ) { assembler_dialect = <NUM_LIT> ; sh_cpu = PROCESSOR_SH4A ; } if ( ! TARGET_SH3 && TARGET_USERMODE ) TARGET_USERMODE = false ; if ( ! strcmp ( sh_div_str , <STR_LIT> ) ) sh_div_strategy = SH_DIV_CALL_DIV1 ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && TARGET_FPU_ANY ) sh_div_strategy = SH_DIV_CALL_FP ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && TARGET_DYNSHIFT ) sh_div_strategy = SH_DIV_CALL_TABLE ; else { if ( TARGET_HARD_SH4 ) sh_div_strategy = SH_DIV_CALL_TABLE ; else if ( TARGET_SH2A ) sh_div_strategy = SH_DIV_INTRINSIC ; else sh_div_strategy = SH_DIV_CALL_DIV1 ; } if ( sh_divsi3_libfunc [ <NUM_LIT> ] ) ; else if ( TARGET_DIVIDE_CALL_FP ) sh_divsi3_libfunc = <STR_LIT> ; else if ( TARGET_DIVIDE_CALL_TABLE ) sh_divsi3_libfunc = <STR_LIT> ; else sh_divsi3_libfunc = <STR_LIT> ; if ( sh_branch_cost == - <NUM_LIT> ) { sh_branch_cost = <NUM_LIT> ; } if ( ! global_options_set . x_TARGET_ZDCBRANCH && TARGET_HARD_SH4 ) TARGET_ZDCBRANCH = <NUM_LIT> ; if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( flag_pic && ! TARGET_PREFERGOT ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && global_options_set . x_flag_schedule_insns ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! global_options_set . x_flag_schedule_insns ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && ! TARGET_ACCUMULATE_OUTGOING_ARGS ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; TARGET_ACCUMULATE_OUTGOING_ARGS = <NUM_LIT> ; } if ( flag_unsafe_math_optimizations )


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectShiftA_32 ( const MachineOperand & Root ) const { auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None || * MaybeImmed > <NUM_LIT> ) return None ; uint64_t Enc = ( <NUM_LIT> - * MaybeImmed ) &


<s> DebugLoc dl = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only (


<s> else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= <NUM_LIT> ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ; * offset = addr .


<s> BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin (


<s> return selectVSplatCommon ( N , Imm , false


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : break ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBIT_CONVERT ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ITBlock . instrInITBlock ( ) ) Result = MCDisassembler :: SoftFail ; Check ( Result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; ITBlock . setITState ( Firstcond , Mask ) ; } return Result ; } if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Insn32 = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; Result = decodeInstruction ( DecoderTableThumb32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb232 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableVFP32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return Result ; } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate (


<s> if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; UseOneConstNR = false ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( )


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG )


<s> static __inline unsigned long long sh_media_MSHLLD_W ( unsigned long


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( StartLoc , <STR_LIT> ) ; Lex ( ) ; OperandMatchResultTy ResTy ; if ( Kind == MCK_AnyReg ) ResTy = parseAnyReg ( Operands ) ; else if ( Kind == MCK_VR128 ) ResTy = parseVR128 ( Operands ) ; else if ( Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20 ) ResTy = parseBDXAddr64 ( Operands ) ; else if ( Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20 ) ResTy = parseBDAddr64 ( Operands ) ; else if ( Kind == MCK_BDVAddr64Disp12 ) ResTy = parseBDVAddr64 ( Operands ) ; else if ( Kind == MCK_PCRel32 ) ResTy = parsePCRel32 ( Operands ) ; else if ( Kind == MCK_PCRel16 ) ResTy = parsePCRel16 ( Operands ) ; else { const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( Expr ) ) return Error ( StartLoc , <STR_LIT> ) ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; ResTy = MatchOperand_Success ; } if ( ResTy != MatchOperand_Success ) return true ; } MCInst Inst = MCInstBuilder ( Entry -> Opcode ) ; for ( size_t i = <NUM_LIT> ; i < Operands . size ( ) ; i ++ ) { MCParsedAsmOperand & Operand = * Operands [


<s> uint64_t UpperboundTC = SE -> getSignedRange ( TC ) . getUpper ( ) . getZExtValue ( ) ; if ( UpperboundTC > MaxMinusVW && ! ForceTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; dbgs ( ) << UpperboundTC << <STR_LIT> << MaxMinusVW << <STR_LIT> ; ) ; return false ; } auto * One = SE -> getOne ( TripCount -> getType ( ) ) ; auto * ElementCount = SE -> getAddExpr ( BTC , One ) ; auto * ECPlusVWMinus1 = SE -> getAddExpr ( ElementCount , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ) ; ConstantRange RangeCeil = SE -> getSignedRange ( Ceil ) ; ConstantRange RangeTC = SE -> getSignedRange ( TC ) ; if ( ! RangeTC . isSingleElement ( ) ) { auto ZeroRange = ConstantRange ( APInt ( TripCount -> getType ( ) -> getScalarSizeInBits ( ) , <NUM_LIT> ) ) ; RangeTC = RangeTC . unionWith ( ZeroRange ) ; } if ( ! RangeTC . contains ( RangeCeil ) && ! ForceTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * IV = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * IVExpr = SE -> getSCEV ( IV ) ; auto * AddExpr = dyn_cast < SCEVAddRecExpr > ( IVExpr ) ; if ( ! AddExpr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; IVExpr -> dump ( ) ) ; return false ; } if ( AddExpr -> getLoop ( ) != L ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Step = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Step ) { LLVM_DEBUG ( dbgs ( ) <<


<s> static SDValue PerformSubCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 .


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { CPU = <STR_LIT> ; } else if ( CPU == <STR_LIT> ) { CPU = <STR_LIT> ; return * this ; } else if ( CPU != <STR_LIT> && CPU != <STR_LIT> ) { CPU = <STR_LIT> ; } } else { errs ( ) << <STR_LIT> << TargetTriple . getArch ( ) << <STR_LIT> << CPU << <STR_LIT> ; exit ( <NUM_LIT> ) ; } if ( CPU == <STR_LIT> ) <ISA_LIT>ArchVersion = <ISA_LIT>32I ; else if ( CPU == <STR_LIT> ) <ISA_LIT>ArchVersion =


<s> NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case <STR_LIT> : NumBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: BUNDLE : NumBytes = getInstBundleLength


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc


<s> unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> -


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_None ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr ::


<s> auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateImm , getContext ( ) ) ) ; Parser . Lex ( ) ; return


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> &&

OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> MCStreamer * S ; if ( ! Triple ( TT ) . isOSNaCl ( ) ) S = createELFStreamer ( Context , MAB ,

OS , Emitter , RelaxAll , NoExecStack ) ;


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) { LoRegsToSave [ Reg ] = true ; } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToSave [ Reg ] = true ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) && ! MF . getRegInfo ( ) . isLiveIn ( Reg ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs [ Reg ] = true ; } for ( unsigned ArgReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( ! MF . getRegInfo ( ) . isLiveIn ( ArgReg ) ) CopyRegs [ ArgReg ] = true ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! LoRegsToSave . none ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( LoRegsToSave [ Reg ] ) { bool isKill = ! MRI . isLiveIn ( Reg ) ; if ( isKill && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> )

) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> CC = ( CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( EFLAGS . getOpcode ( ) , SDLoc ( EFLAGS ) , VT , DAG . getBitcast ( OpVT , BC . getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( OpVT , BC . getOperand ( <NUM_LIT> ) ) ) ; } unsigned EltBits = BCVT . getScalarSizeInBits ( ) ; if ( DAG . ComputeNumSignBits ( BC ) == EltBits ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; APInt SignMask = APInt :: getSignMask ( EltBits ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( SDValue Res = TLI . SimplifyMultipleUseDemandedBits ( BC , SignMask , DAG ) ) { SDLoc DL ( EFLAGS ) ; if ( EltBits == <NUM_LIT> ) { MVT MovmskVT = BCVT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; Res = DAG . getBitcast ( MovmskVT , Res ) ; Res = getPMOVMSKB ( DL , Res , DAG , Subtarget ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { Res = getPMOVMSKB ( DL , Res , DAG , Subtarget ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } } } if ( <STR_LIT> ( Op0 . getNode ( ) ) ) return DAG . getNode ( EFLAGS . getOpcode ( ) , SDLoc ( EFLAGS ) , VT , Op1 , Op1 ) ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) return DAG . getNode ( EFLAGS . getOpcode

( ) , SDLoc ( EFLAGS ) , VT , Op0 , Op0 ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { if ( Immed == std :: numeric_limits < int64_t > :: min ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Immed << <STR_LIT> ) ; return false ; } Immed = std :: abs ( Immed ) ; bool IsLegal = ( ( Immed >> <NUM_LIT> ) == <NUM_LIT> || ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Immed << <STR_LIT> << (

IsLegal ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ;


<s> CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt (


<s> else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && dest_vmx_p ) return <STR_LIT> ; else if ( dest_fp_p ) return <STR_LIT> ; } else if ( src_regno >= <NUM_LIT> && MEM_P ( dest ) ) { if ( src_gpr_p ) { if ( TARGET_QUAD_MEMORY && quad_load_store_p ( dest , src ) ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && src_vmx_p && altivec_indexed_or_indirect_operand ( src , mode ) ) return <STR_LIT> ; else if ( TARGET_VSX && src_vsx_p ) { if ( mode_supports_vsx_dform_quad ( mode ) && quad_address_p ( XEXP ( dest , <NUM_LIT> ) , mode , true ) ) return <STR_LIT> ; else if ( TARGET_P9_VECTOR ) return <STR_LIT> ; else if ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && src_vmx_p ) return <STR_LIT> ; else if ( src_fp_p ) return <STR_LIT> ; } else if ( dest_regno >= <NUM_LIT> && ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_WIDE_INT || GET_CODE ( src ) == CONST_DOUBLE || GET_CODE ( src ) == CONST_VECTOR ) ) { if ( dest_gpr_p


<s> case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ->


<s> void <ISA_LIT>InstPrinter :: printBDRAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { unsigned Base = MI -> getOperand ( OpNum ) . getReg ( ) ; uint64_t Disp = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; unsigned Length = MI -> getOperand ( OpNum + <NUM_LIT> ) .


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( )


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoAllLanes ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> void printImpl ( raw_ostream & OS , const


<s> errs ( ) . write_hex ( Word ) << <STR_LIT> ) ; MCE . emitWordBE ( Word


<s> MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugValue ( ) ) ++ I ; if ( I != E ) { unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = llvm :: getITInstrPredicate ( I , NPredReg ) ; if ( NCC == CC || NCC == OCC ) return true ; } return


<s> if ( Use -> isMachineOpcode ( ) ) { const TargetInstrDesc & TID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( TID . mayStore ( ) ) return true ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; } return false


<s> src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx ( dest_vecmode ) ; set = gen_rtx_SET ( vec , src ) ; set_insn = emit_insn_before ( set , insn ) ; df_insn_rescan ( set_insn ) ; if ( cfun -> can_throw_non_call_exceptions ) { rtx note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) { control_flow_insns . safe_push ( set_insn ) ; add_reg_note ( set_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } } src = gen_rtx_SUBREG ( dest_mode , vec , <NUM_LIT> ) ; set = gen_rtx_SET ( dest , src ) ; PATTERN ( insn ) = set ; INSN_CODE ( insn ) = - <NUM_LIT> ; recog_memoized ( insn ) ; df_insn_rescan ( insn ) ; bitmap_set_bit ( convert_bbs , bb -> index ) ; } } if ( v4sf_const0 ) { calculate_dominance_info ( CDI_DOMINATORS ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; bb = nearest_common_dominator_for_set ( CDI_DOMINATORS , convert_bbs


<s> TYPE_PRECISION ( fpreg_type ) = <NUM_LIT> ; layout_type ( fpreg_type ) ; ( * lang_hooks . types . register_builtin_type ) ( fpreg_type , <STR_LIT> ) ; float80_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( float80_type ) = <NUM_LIT> ; layout_type ( float80_type ) ; ( * lang_hooks . types . register_builtin_type ) ( float80_type , <STR_LIT> ) ; if ( ! TARGET_HPUX ) { tree ftype ; tree float128_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( float128_type ) = <NUM_LIT> ; layout_type ( float128_type ) ; ( * lang_hooks . types . register_builtin_type ) ( float128_type , <STR_LIT> ) ; ftype = build_function_type_list ( float128_type , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_INFQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_INFQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_HUGE_VALQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_HUGE_VALQ ] = decl ; ftype = build_function_type_list ( float128_type , float128_type , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_FABSQ ] = decl ; ftype = build_function_type_list ( float128_type , float128_type , float128_type , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_COPYSIGNQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_COPYSIGNQ ] = decl ; } else ( * lang_hooks . types . register_builtin_type ) ( long_double_type_node , <STR_LIT> ) ; vms_patch_builtins ( ) ; add_builtin_function ( ( name ) , ( type ) , ( code ) , BUILT_IN_MD , \ NULL , NULL_TREE ) decl = def_builtin ( <STR_LIT> , build_function_type_list ( ptr_type_node , NULL_TREE ) , IA64_BUILTIN_BSP ) ; ia64_builtins [ IA64_BUILTIN_BSP ] = decl ; decl = def_builtin ( <STR_LIT> , build_function_type_list ( void_type_node , NULL_TREE ) , IA64_BUILTIN_FLUSHRS ) ; ia64_builtins [ IA64_BUILTIN_FLUSHRS ] = decl ; if (


<s> return ( __m512 ) __builtin_ia32_cvtudq2ps512_mask ( ( __v16si ) __A , ( __v16sf ) _mm512_setzero_ps ( ) , (


<s> if ( Subtarget -> isGP64bit ( ) ) return lowerFCOPYSIGN64 (

Op , DAG , Subtarget -> hasExtractInsert ( ) ) ;


<s> else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode


<s> if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( TwoRepStos ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; Count = Size ; EVT CVT = Count . getValueType ( ) ; SDValue Left = DAG . getNode ( <STR_LIT> , dl , CVT , Count , DAG . getConstant ( ( AVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , CVT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , ( CVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , Left , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( <STR_LIT> ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; } else if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft


<s> TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm ( ( int64_t ) <STR_LIT> ) ) ; TSTInst . addOperand ( MCOperand ::


<s> if ( usePackedStack ( MF ) && ! ( IsVarArg && ! SoftFloat ) ) { if ( <STR_LIT> . contains ( Reg ) ) Offset += BackChain ? <NUM_LIT> : <NUM_LIT> ; else Offset = <NUM_LIT> ; } return


<s> <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = <ISA_LIT>_condCodeToString ( CC ) ; O <<


<s> const <ISA_LIT>FrameLowering * getFrameLowering


<s> bool Filled = false ; if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always || ! TII -> getEquivalentCompactForm ( I ) ) { if ( searchBackward ( MBB , * I ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; Filled = true ; } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; } } else if ( searchForward ( MBB , I ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } ++


<s> return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_maskz_loadu_epi64 ( __mmask8 __U , void const * __P ) { return ( __m128i ) __builtin_ia32_loaddqudi128_mask ( ( const long long * ) __P , ( __v2di )


<s> Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) ,

false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTbl ,


<s> return RegIdx . RegInfo -> getRegClass ( <STR_LIT> )


<s> case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : case 'R' : case 'H' : report_fatal_error ( <STR_LIT> ) ; return true ; } } printOperand ( MI , OpNum , O ) ; return false


<s> bool <ISA_LIT>TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasAVX512 ( ) && ! LoadVT . isVector ( ) && BitcastVT . isVector ( ) && BitcastVT . getVectorElementType ( ) == <STR_LIT> ) return false ; if ( ! Subtarget . hasDQI ( ) && BitcastVT == <STR_LIT> && LoadVT == <STR_LIT> ) return false ; return TargetLowering :: isLoadBitCastBeneficial (


<s> const MCExpr * IdVal ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; Op = <ISA_LIT>Operand :: CreateImm ( IdVal ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op ) ; case AsmToken :: LCurly : return ParseRegisterList ( Op ) ; case AsmToken ::


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> rtx mmix_dynamic_chain_address ( rtx frame ) { return plus_constant ( frame , -


<s> const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) ==


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap


<s> auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx


<s> const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP = true ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } FrameReg =


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetSoftFloat (


<s> unsigned OpNum = Inst . getNumOperands ( ) ; unsigned Opcode = Inst . getOpcode ( ) ; unsigned NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( OpNum - <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> &&

Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> VTs . push_back ( <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ; } return DAG . getNode ( Opc , dl , TrueVal . getValueType ( ) ,

TrueVal , FalseVal , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , CompareFlag ) ;


<s> auto * RHSN1 = dyn_cast < ConstantSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! LHSN1 || LHSN1 != RHSN1 || ! RHSN1 -> isNullValue ( ) ) return SDValue ( ) ; SDValue Op1 = LHS -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = RHS -> getOperand ( <NUM_LIT> ) ; EVT OpVT1 = Op1 . getValueType ( ) ; EVT OpVT2 = Op2 . getValueType ( ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || OpVT1 != OpVT2 || Op2 . getOpcode ( ) != <STR_LIT> || OpVT1 . getVectorElementType ( ) != VT ) return SDValue ( ) ; SDValue Val1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Op2 .


<s> uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElemsPerChunk = vecWidth / VecVT . getScalarSizeInBits ( ) ; return Index


<s> if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != <NUM_LIT> ||

ix86_preferred_stack_boundary >= <NUM_LIT> ) return align ;


<s> NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> return ( __m128d ) __builtin_ia32_vfmaddsd3_round ( ( __v2df ) __W , -


<s> static __inline__ double __fnmsub ( double x , double y , double z ) { double r


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned >


<s> case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr (


<s> } } const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT (


<s> SDValue Extract = LHS -> getOperand ( <NUM_LIT> ) ; if ( Extract -> getOpcode ( ) != <STR_LIT> || Extract -> getValueType ( <NUM_LIT> ) != N -> getValueType ( <NUM_LIT> ) || Extract -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue InnerSetCC = Extract -> getOperand ( <NUM_LIT> ) ; if ( InnerSetCC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue InnerPred = InnerSetCC . getOperand ( <NUM_LIT> ) ; if ( Pred . getOpcode ( ) == <STR_LIT> && InnerPred . getOpcode ( ) == <STR_LIT> && Pred . getConstantOperandVal ( <NUM_LIT> ) == InnerPred . getConstantOperandVal ( <NUM_LIT> ) && Pred -> getConstantOperandVal ( <NUM_LIT> ) >= <STR_LIT> && Pred -> getConstantOperandVal ( <NUM_LIT> )


<s> union { __ev64_opaque__ v ; uint16_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [


<s> if ( Imm . isPosZero ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } StringRef FPType ; bool IsLegal = false ; SmallString < <NUM_LIT> > ImmStrVal ; Imm . toString ( ImmStrVal ) ; if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } if ( IsLegal ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FPType << <STR_LIT> <<


<s> bool aarch64_legitimate_pic_operand_p ( rtx x ) { poly_int64 offset ; x = strip_offset_and_salt ( x , &


<s> Target & getThe<ISA_LIT>leTarget ( ) { static Target


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> CallContext ( ) : Call ( nullptr ) , SPCopy ( nullptr ) , ExpectedDist ( <NUM_LIT> ) , MovVector ( <NUM_LIT> , nullptr ) , NoStackParams ( false )


<s> bool output_addr_const_extra ( FILE * file , rtx x ) { rtx op ; if ( GET_CODE ( x ) != UNSPEC ) return false ; op = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOTTPOFF : output_addr_const ( file , op ) ; fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , op ) ; fputs ( <STR_LIT>


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = <NUM_LIT> , num_regs = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( )


<s> if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( ! SC -> EndGroup ) return <NUM_LIT> ; else return <NUM_LIT> ; } return <NUM_LIT>


<s> case GT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LTU : return <STR_LIT> ; case LEU : return <STR_LIT> ; case GTU : return <STR_LIT> ; case GEU : return <STR_LIT> ; default : gcc_unreachable (


<s> return ( ( vec_int4 ) ( si_ori ( ( qword ) ( a )


<s> if ( mode == VOIDmode ) mode = TImode ; gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode ,


<s> SmallVector < StringRef , <NUM_LIT> > AsmPieces ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) ) { return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && ( matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) ) { AsmPieces . clear ( ) ; const std :: string & ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) { AsmPieces . clear ( ) ; const std :: string & ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { InlineAsm :: ConstraintInfoVector Constraints = IA


<s> unsigned Op0 = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg (


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; Vec = Extract128BitVector ( Vec , DAG . getConstant ( Upper ? NumElems / <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , Upper ? DAG . getConstant ( IdxVal - NumElems / <NUM_LIT> , <STR_LIT> ) : Idx ) ; } assert ( Vec . getValueSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget -> hasSSE41orAVX ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( )


<s> insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) =


<s> __inline__ static void sh_media_FVCOPY_S ( const void * fvg


<s> if ( ! Root . isReg ( ) ) return None ; MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * ShiftInst = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! ShiftInst ) return None ; <STR_LIT> ShType = getShiftTypeForInst ( * ShiftInst ) ; if ( ShType == <STR_LIT> ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * ShiftInst , MRI ) ) return None ; MachineOperand & ShiftRHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; auto Immed = getImmedFromMO ( ShiftRHS ) ; if ( ! Immed ) return None ; MachineOperand & ShiftLHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; Register ShiftReg = ShiftLHS . getReg ( ) ; unsigned NumBits = MRI . getType ( ShiftReg ) . getSizeInBits (


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAreaOffset ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> )


<s> SmallPtrSet < Value * , <NUM_LIT> > Defs ; SmallVector < Value * , <NUM_LIT> > WorkList ; WorkList . push_back ( V ) ; Defs . insert ( V ) ; while ( ! WorkList . empty ( ) ) { Value * Curr = WorkList . back ( ) ; WorkList . pop_back


<s> __o = __builtin_aarch64_set_qregoiv4si ( __o , ( int32x4_t ) val . val [


<s> if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; if ( Inst . getOpcode ( ) != <STR_LIT> ) DecodeZPRRegisterClass ( Inst , Zdn , Addr


<s> void printf64mem ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> for ( Target * T : { & The<ISA_LIT>32Target , & The<ISA_LIT>64Target , & The<ISA_LIT>64LETarget } ) { RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: registerMCAdjustCodeGenOpts ( * T , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T


<s> bool <ISA_LIT>TargetLowering :: isAccessedAsGotIndirect ( SDValue GA ) const { if ( Subtarget . is32BitELFABI ( ) ) return true ; if ( Subtarget . isAIXABI ( ) ) return true ; CodeModel :: Model CModel = getTargetMachine ( ) . getCodeModel ( ) ; if ( CModel == CodeModel :: Small || CModel ==


<s> if ( NumV2Inputs == <NUM_LIT> ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V1 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; APInt SplatBits


<s> APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( ! Hash ) return MatchOperand_NoMatch ; TokError ( <STR_LIT>


<s> TargetIRAnalysis <ISA_LIT>BaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl (


<s> <STR_LIT> Cond = StringSwitch < <STR_LIT> > ( Constraint ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case (

<STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr & I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF ->

getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> ) |


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>TargetMachine & TM ,


<s> const TargetMachine & TM = mf . getTarget ( ) ; MRI = & mf . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM .


<s> OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID ,


<s> if ( Subtarget -> hasLSE ( ) ) return


<s> else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { Align Alignment = DL . getPrefTypeAlign ( GV -> getType ( ) ) ; if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Alignment ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( IsPositionIndependent ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( IsPositionIndependent ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; return NewDestReg ; } } } if ( IsIndirect ) { MachineInstrBuilder MIB ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; else MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; DestReg = NewDestReg ; AddOptionalDefs ( MIB ) ; } return


<s> F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget -> hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i !=


<s> if ( Chunk == <NUM_LIT> || Chunk == std :: numeric_limits <


<s> return ( __m128i ) __builtin_ia32_vpshld ( ( __v4si ) __A , ( __v4si )


<s> assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> ,


<s> bool vax_maybe_split_dimode_move ( rtx * operands ) { return ( TARGET_QMATH && ( ! MEM_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC || ! illegal_addsub_di_memory_operand ( operands [ <NUM_LIT> ] , DImode ) ) && ( ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) INTVAL ( operands [ <NUM_LIT> ]

) >= <NUM_LIT> ) || GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) ) ;


<s> const bool HideSandboxBase = ( FlagHideSandboxBase && Is64Bit && ! FlagUseZeroBasedSandbox ) ; if ( HideSandboxBase ) { MCContext & Context = Out . getContext ( ) ; MCSymbol * RetTarget = CreateTempLabel ( Context , <STR_LIT> ) ; PushReturnAddress ( STI , Context , Out , RetTarget ) ; MCInst JMPInst ; JMPInst . setOpcode ( <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI . getDesc ( ) . TSFlags ) ; if ( FMA3Group ) return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , FMA3Group -> isIntrinsic ( ) ) ; if ( <STR_LIT> ( Desc . TSFlags ) ) { unsigned CommutableOpIdx1 = Desc . getNumDefs ( ) + <NUM_LIT> ; unsigned CommutableOpIdx2 = Desc . getNumDefs ( ) + <NUM_LIT> ; if ( ( MI . getDesc ( ) . getOperandConstraint ( Desc . getNumDefs ( ) , MCOI :: TIED_TO ) != - <NUM_LIT> ) ) { if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } else { -- CommutableOpIdx1 ; } } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return


<s> if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , DL , Ptr . getValueType ( ) ) ) ; } int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return new <ISA_LIT>_64MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( TT . isOSLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return new <ISA_LIT>WindowsTargetObjectFile ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return new TargetLoweringObjectFileCOFF (


<s> case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; } EVT VT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpImm ) , ResultReg ) . addReg ( Op0Reg ) . addImm ( CI -> getZExtValue ( ) & <NUM_LIT> ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CReg ) . addReg ( Op1Reg ) ; if ( CReg != <STR_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: KILL ) , <STR_LIT> ) . addReg ( CReg , RegState :: Kill ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpReg ) , ResultReg ) . addReg ( Op0Reg ) ; UpdateValueMap ( I , ResultReg ) ; return true


<s> State = IES_ERROR ; break ; case IES_PLUS : case IES_MINUS : case IES_DIVIDE : case IES_MULTIPLY : case IES_LPAREN : State = IES_INTEGER ; if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { assert ( ! IndexReg && <STR_LIT> ) ; IndexReg = TmpReg ; Scale = TmpInt


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Align TargetAlign = TFI -> getStackAlign ( ) ; Align MaxAlign = MFI . getMaxAlign ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { if ( LP64 ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , FramePointer ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , FramePointer ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , FramePointer ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , FramePointer ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign . value ( ) - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( )


<s> if ( NextVA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> - id ) ) ) ; else { assert ( NextVA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue


<s> MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } const MCExpr * Sym =


<s> void dimode_scalar_chain :: make_vector_copies ( unsigned regno ) { rtx reg = regno_reg_rtx [ regno ] ; rtx vreg = gen_reg_rtx ( DImode ) ; df_ref ref ; for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { start_sequence ( ) ; if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( vreg , tmp ) ; } else if ( TARGET_SSE4_1 ) { emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse4_1_pinsrd ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; } else { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; rtx_insn * insn = DF_REF_INSN ( ref ) ; emit_conversion_insns ( seq , insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , REGNO ( vreg ) , INSN_UID ( insn ) ) ; } for ( ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( bitmap_bit_p ( insns


<s> EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { if ( Op -> isImm ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addImm ( Op -> getImm ( ) ) ) ; else if ( Op -> isReg ( ) ) { if ( Op -> getReg ( ) != UsedRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) .


<s> return ( __m64 ) __builtin_ia32_cvtps2pi ( ( __v4sf


<s> XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( layout . locals_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout .


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? <STR_LIT> : <STR_LIT> ; return true


<s> getAddrMode6OneLane32AddressOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & Reg = MI . getOperand ( Op ) ; const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; } return RegNo | ( Align


<s> return new <ISA_LIT>FastTileConfig (


<s> NewSuccessor -> splice ( NewSuccessor -> end ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( BIL . back ( ) ) ) , MBB -> end ( ) ) ; NewSuccessor -> transferSuccessorsAndUpdatePHIs ( MBB ) ; for ( auto & LI : MBB -> liveins ( ) ) NewSuccessor -> addLiveIn ( LI ) ; LivePhysRegs LPR ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( MachineInstr & MI : * MBB ) LPR . stepForward ( MI , Clobbers ) ; for ( auto & LI : LPR ) NewSuccessor -> addLiveIn ( LI ) ; } else { MBB -> removeSuccessor ( Successor ) ; } MBB -> addSuccessor ( IsTrueBlockRequired ? TrueBlock : Successor ) ; MBB -> addSuccessor ( IsFalseBlockRequired ? FalseBlock


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( )


<s> Imm = CE -> getValue ( ) ; return true ; } return


<s> bool isCoprocOption ( ) const { return Kind ==


<s> MCELFStreamer * llvm :: create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB

, raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) {


<s> case MCK_1 : ImmVal = <NUM_LIT> ; break ; case MCK_2 : ImmVal = <NUM_LIT> ; break ; case MCK_3 : ImmVal = <NUM_LIT> ; break ; case MCK_4 : ImmVal = <NUM_LIT> ; break ; case MCK_5 : ImmVal = <NUM_LIT> ; break ; case MCK_6 : ImmVal = <NUM_LIT> ; break ; case MCK_7 : ImmVal = <NUM_LIT> ; break ; default : return Match_InvalidOperand ; } <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( Op . isU3Imm ( ) && Op . getImm ( ) == ImmVal


<s> SDValue getAddrGlobal ( NodeTy * N , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDLoc DL ( N )


<s> Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } default : return false


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __llwpcb ( void * pcbAddress ) { __builtin_ia32_llwpcb ( pcbAddress


<s> if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned Bits = VT . getScalarSizeInBits ( ) ; uint64_t BitMask = Bits == <NUM_LIT> ? - <NUM_LIT> : ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) for ( int j = <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( i ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( j ) ) ; if ( ! BVN0 || ! BVN1 ) continue ; bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ; ++ k ) { ConstantSDNode * CN0 = dyn_cast < ConstantSDNode > ( BVN0 -> getOperand ( k ) ) ; ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( BVN1 -> getOperand ( k ) ) ; if ( ! CN0 || ! CN1 || CN0 -> getZExtValue ( ) != ( BitMask & ~ CN1 -> getZExtValue ( ) ) ) { FoundMatch =


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model >


<s> crtl -> stack_realign_finalized = true ; return ; } } if ( crtl -> drap_reg ) { basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; if ( ! REGNO_REG_SET_P ( DF_LR_IN ( bb ) , REGNO ( crtl -> drap_reg ) ) ) { crtl -> drap_reg = NULL_RTX ; crtl -> need_drap = false ; } } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks (


<s> for ( auto * PredMI : Predicates ) if ( isVCTP ( PredMI ) ) return true ; return false


<s> <ISA_LIT>AsmInstrumentation * llvm :: Create<ISA_LIT>AsmInstrumentation ( const MCTargetOptions & MCOptions , const MCContext & Ctx , const MCSubtargetInfo * & STI ) { Triple T ( STI -> getTargetTriple ( ) ) ; const bool hasCompilerRTSupport = T . isOSLinux ( ) ; if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ; if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return

new <ISA_LIT>AddressSanitizer64 ( STI ) ;


<s> return ( ( ix86_fp_comparison_cost ( code ) == ix86_fp_comparison_fcomi_cost ( code ) ) || ( ix86_fp_comparison_cost ( swapped_code ) == ix86_fp_comparison_fcomi_cost (


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> bool IndexIs256 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( IndexIs128 || IndexIs256 ) { unsigned IndexOffset = insn . sibIndex - ( insn . addressSize == <NUM_LIT> ? SIB_INDEX_RAX : SIB_INDEX_EAX ) ; SIBIndex IndexBase = IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0 ; insn . sibIndex = ( SIBIndex ) ( IndexBase + ( insn . sibIndex == SIB_INDEX_NONE ? <NUM_LIT> : IndexOffset ) ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM } } else { indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } scaleAmount = MCOperand :: CreateImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) { pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; } else baseReg = MCOperand :: CreateReg ( <NUM_LIT>


<s> for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( LEGACY_SSE_REGNO_P ( regno ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ; return gen_avx_vzeroall (


<s> if ( VT . isFloatingPoint ( ) ) { assert ( VT != <STR_LIT> ) ; if ( VT == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; VT = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; } unsigned Opcode = <STR_LIT> ; if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> &&

isNullConstant ( RHS ) && ! isUnsignedIntSetCC ( CC ) ) {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = * PassRegistry


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ; return CostKind == TTI :: TCK_RecipThroughput


<s> bool SelectAddrMode2Base ( SDValue N , SDValue & Base , SDValue & Offset , SDValue


<s> void printImpl ( raw_ostream & OS , const MCAsmInfo * MAI


<s> if ( ! Subtarget . is64BitELFABI ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv (


<s> SDValue <ISA_LIT>TargetLowering :: lowerOr ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op .


<s> break ; } case <STR_LIT> : { LLT Ty = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S64 ) || Ty == LLT :: fixed_vector ( <NUM_LIT> , P0 ) ) Opc = <STR_LIT> ; else if ( Ty == S64 || Ty == P0 ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; selectVectorLoadIntrinsic ( Opc , <NUM_LIT> , I ) ; break ; } case <STR_LIT> : { Register Src1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Src1 ) ; unsigned Opc ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S64 ) || Ty == LLT :: fixed_vector ( <NUM_LIT> , P0 ) ) Opc = <STR_LIT> ; else if ( Ty == S64 || Ty == P0 ) Opc = <STR_LIT> ; else llvm_unreachable (


<s> const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT>


<s> case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return <NUM_LIT>


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) &&

! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) {


<s> AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; V1 = Base