<s> if ( lFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( ( attrMask & ATTR_XD ) && ( attrMask & ATTR_REXW ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithREXw ; const struct InstructionSpecifier * specWithREXw ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithREXw , insn , attrMask & ( ~ ATTR_XD ) ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specWithREXw = specifierForUID ( instructionIDWithREXw ) ; if ( is64BitEquivalent ( spec -> name , specWithREXw -> name ) ) { insn -> instructionID = instructionIDWithREXw ; insn -> spec = specWithREXw ; } else { insn -> instructionID = instructionID ; insn -> spec = spec ; } return <NUM_LIT> ; } if ( insn -> prefixPresent [ <NUM_LIT> ] && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const struct InstructionSpecifier * specWithOpsize ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec


<s> unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI


<s> if ( Base . isReg ( ) && Base . getReg ( ) == <STR_LIT> ) { assert ( Index . isReg ( ) && Index . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } if ( Index . isReg ( ) && Index . getReg ( ) == <STR_LIT> ) return true ; return isMemOperand ( MI , Op


<s> rtx end_label = gen_label_rtx ( ) ; value = force_reg ( QImode , value ) ; if ( need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( size , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , end_label ) ; if ( ! need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_label ( byte_mode_label ) ; nds32_emit_post_inc_load_store ( value , itr , QImode ,


<s> case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst ,


<s> } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = is64bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; return ResultReg


<s> case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL_V2I64 ( Op , DAG


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return


<s> if ( GET_MODE ( x ) == SImode ) { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , <NUM_LIT> ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , <NUM_LIT> ) == const2_rtx ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , <NUM_LIT> ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) && INTVAL ( XEXP ( op1 , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; } if ( treg_set_expr ( op1 , SImode ) ) return <NUM_LIT> ; if ( treg_set_expr ( op0 , SImode ) )


<s> void <ISA_LIT>NaClRewritePass :: AlignAllJumpTargets ( MachineFunction & MF ) { MachineJumpTableInfo * jt_info = MF . getJumpTableInfo ( ) ; if ( jt_info ) { const std :: vector < MachineJumpTableEntry > & JT = jt_info -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> ; i < JT . size ( ) ; ++ i ) { std :: vector < MachineBasicBlock * > MBBs = JT [ i ] . MBBs ; for ( unsigned j = <NUM_LIT> ; j < MBBs . size ( ) ; ++ j ) { MBBs [ j ] -> setAlignment ( <NUM_LIT> ) ; } } } for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { MachineBasicBlock & MBB


<s> void <ISA_LIT>InstrInfo :: expandZExtPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned Size ) const { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size , MI . getOperand ( <NUM_LIT>


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; RegNo = parseRegisterName ( & MatchRegisterName ) ; if ( RegNo == <STR_LIT> ) RegNo = parseRegisterName ( & MatchRegisterAltName ) ; if ( RegNo != <STR_LIT> ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch


<s> exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Incr2 ) . addReg ( Incr ) . addReg ( ShiftAmt ) ; BB = loopMBB ; unsigned LL = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( <STR_LIT> ) . addReg ( AndRes ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , BinOpRes ) .


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_named_user_abort ( void * const TM_buff , unsigned char * code ) { texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; * code = _TEXASRU_FAILURE_CODE ( texasru


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .

Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> inline unsigned char getAM5Offset ( unsigned


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N ,


<s> OperandMatchResultTy parseFP128 ( SmallVectorImpl < MCParsedAsmOperand * >


<s> if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN ->


<s> SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , Base , Offset , InputVT } ; return DAG . getNode ( Opcode , DL , VTs


<s> static bool CantUseSP ( const MachineFrameInfo * MFI ) { return MFI -> hasVarSizedObjects ( ) || MFI ->


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG (


<s> if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable =


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O <<


<s> bool Is64BitMode = TM . getSubtargetImpl ( ) -> is64Bit ( ) ; unsigned Size = GetInstSizeWithDesc ( * MI , & Desc , IsPIC , Is64BitMode ) ; if ( Desc . getOpcode ( ) == <STR_LIT> ) { Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; } return Size


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } bb = <NUM_LIT> ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } timevar_pop ( TV_MACH_DEP ) ; return <NUM_LIT>


<s> ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; } Register ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( HasAVX ) MIB . addReg ( ImplicitDefReg ) ; MIB . addReg ( OpReg )


<s> } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresDifferentSrcAndDst : return Error ( IDLoc , <STR_LIT> ) ; case Match_Immz : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm1_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm3_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; uint64_t Imm = getConstantImm ( ) - Offset ; Imm &= ( <NUM_LIT> << Bits ) -


<s> Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ) ; return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasSwap ( false ) , HasBitCount ( false ) , HasFPIdx ( false ) , In<ISA_LIT>16Mode ( false ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , IsAndroid ( false ) , RM ( _RM ) { std :: string CPUName =


<s> return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } break ; case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; case TargetOpcode :: G_OR : return <STR_LIT> ; default : return GenericOpc


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> else t2 = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , base ) ; t2 = gen_const_mem ( Pmode , t2 ) ; emit_insn ( gen_rtx_SET ( t1 , t2 ) ) ; base = t1 ; } break ; case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : t1 = gen_reg_rtx ( Pmode ) ; base = gen_sym_unspec ( base , UNSPEC_TLSGD ) ; emit_insn ( gen_rtx_SET ( t1 , gen_rtx_HIGH ( Pmode , base ) ) ) ; emit_insn ( gen_rtx_SET ( t1 , gen_rtx_LO_SUM ( Pmode , t1 , base ) ) ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; emit_insn ( gen_add3_insn ( t1 , t1 , pic_offset_table_rtx ) ) ; base = gen_reg_rtx ( Pmode ) ; or1k_tls_call ( base , t1 ) ; break ; case TLS_MODEL_INITIAL_EXEC : t1 = gen_reg_rtx ( Pmode ) ; t2 = gen_reg_rtx ( Pmode ) ; base = gen_sym_unspec ( base , UNSPEC_GOTTPOFF ) ; emit_insn ( gen_rtx_SET ( t1 , gen_rtx_HIGH ( Pmode , base ) ) ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; emit_insn ( gen_add3_insn ( t1 , t1 , pic_offset_table_rtx ) ) ; t1 = gen_rtx_LO_SUM ( Pmode , t1 , base ) ; emit_move_insn ( t2 , gen_const_mem ( Pmode , t1 ) ) ; t1 = gen_rtx_REG ( Pmode , TLS_REGNUM ) ; emit_insn ( gen_add3_insn ( t2 , t2 , t1 ) ) ; base = t2 ; break ; case TLS_MODEL_LOCAL_EXEC : x = gen_sym_unspec ( x , UNSPEC_TPOFF ) ; t1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( t1 , gen_rtx_HIGH ( Pmode , x ) ) ) ; t2 = gen_rtx_REG ( Pmode , TLS_REGNUM ) ; emit_insn ( gen_add3_insn ( t1 , t1 , t2 ) ) ; return gen_rtx_LO_SUM ( Pmode , t1 , x ) ; default : gcc_unreachable ( ) ; } break ; case LO_SUM : case UNSPEC : return x ; } gcc_checking_assert ( register_operand ( base , Pmode ) ) ; if ( addend == const0_rtx ) return base ; if ( satisfies_constraint_I ( addend ) || virtual_frame_reg_operand ( base , VOIDmode ) ) return gen_rtx_PLUS ( Pmode , base , addend ) ; else { rtx hi , lo ; bool ok = ( or1k_legitimize_address_displacement ( & hi , & lo , INTVAL ( addend ) , SImode ) ) ; gcc_assert ( ok ) ; t2 = can_create_pseudo_p ( ) ?


<s> if ( VecTy -> getNumElements ( ) < <NUM_LIT> ) return false ; if ( ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Alignment < ElSize / <NUM_LIT> ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == <NUM_LIT> ) return true ; return VecSize % <NUM_LIT>


<s> if ( ! MO . isImm ( ) ) { return printOperand ( MI , OpNo , STI , O ) ; } if ( PrintBranchImmAsAddress ) { uint64_t Target = Address + MO . getImm ( ) ; Target &=


<s> static void ReplaceLongIntrinsic ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Opc = <NUM_LIT> ; if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else return ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue LongMul = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> )

, N -> getOperand ( <NUM_LIT> ) , Lo , Hi ) ;


<s> offsets -> saved_regs_mask = arm_compute_save_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * <NUM_LIT> ; saved = core_saved ; if ( TARGET_REALLY_IWMMXT ) { for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) saved += <NUM_LIT> ; } func_type = arm_current_func_type ( ) ; if ( ! IS_VOLATILE ( func_type ) && TARGET_HARD_FLOAT ) saved += arm_get_vfp_saved_size ( ) ; } else { offsets -> saved_regs_mask = thumb1_compute_save_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * <NUM_LIT> ; saved = core_saved ; if ( TARGET_BACKTRACE ) saved += <NUM_LIT> ; } offsets -> saved_regs = offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + saved ; offsets -> soft_frame = offsets -> saved_regs + CALLER_INTERWORKING_SLOT_SIZE ; if ( crtl -> is_leaf && frame_size == <NUM_LIT> && ! cfun -> calls_alloca ) { offsets -> outgoing_args = offsets -> soft_frame ; offsets -> locals_base = offsets -> soft_frame ; return offsets ; } if ( ARM_DOUBLEWORD_ALIGN && ( offsets -> soft_frame & <NUM_LIT> ) ) { offsets -> soft_frame += <NUM_LIT> ; if ( frame_size + crtl ->


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type *


<s> warning ( OPT_Wattributes , <STR_LIT> , name ) ; return NULL_TREE ; } if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } fndecl = * node ; if ( ! TREE_PUBLIC ( fndecl ) ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs


<s> case 'r' : if ( REG_P ( x ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] ) ; else if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) fprintf ( file , <STR_LIT> ) ; else output_operand_lossage ( <STR_LIT> ) ; break ; case 'H' : if ( REG_P ( x ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) + <NUM_LIT> ] ) ; else output_operand_lossage ( <STR_LIT> ) ; break ; case 'd' : if ( REG_P ( x ) ) { if ( GET_MODE ( x ) == DFmode || GET_MODE ( x ) == DImode ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] , reg_names [ REGNO ( operand ) + <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) ] ) ; } else output_operand_lossage ( <STR_LIT> ) ; break ; case 'h' : print_reloc ( file , x , <NUM_LIT> , RKIND_HI ) ; break ; case 'L' : print_reloc ( file , x , <NUM_LIT> , RKIND_LO ) ; break ; case 'P' : if ( ! flag_pic || SYMBOL_REF_LOCAL_P ( x ) ) output_addr_const ( file , x ) ; else output_addr_reloc ( file , x , <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : switch ( GET_CODE ( operand ) ) { case REG


<s> rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; notx = gen_rtx_NOT ( V16QImode , sel


<s> unsigned <ISA_LIT>64TargetMachine :: getJITMatchQuality ( ) { if ( sizeof ( void * ) == <NUM_LIT> )


<s> return __builtin_aarch64_sminpv4si ( a , b


<s> gcc_assert ( avail != <NUM_LIT> ) ; if ( TARGET_MIPS16 && ! ( avail & BUILTIN_AVAIL_MIPS16 ) ) { error ( <STR_LIT> , DECL_NAME ( fndecl ) ) ; return ignore ? const0_rtx : CONST0_RTX ( mode ) ; } switch ( d -> builtin_type ) { case MIPS_BUILTIN_DIRECT : return mips_expand_builtin_direct ( d -> icode , target , exp , true ) ; case MIPS_BUILTIN_DIRECT_NO_TARGET : return mips_expand_builtin_direct ( d -> icode , target , exp , false ) ; case MIPS_BUILTIN_MOVT : case MIPS_BUILTIN_MOVF : return mips_expand_builtin_movtf ( d -> builtin_type , d -> icode , d -> cond , target , exp ) ; case MIPS_BUILTIN_CMP_ANY : case


<s> Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE


<s> SmallVector < Instruction * , <NUM_LIT> > DecomposedVectors ; SmallVector < Value * , <NUM_LIT> > TransposedVectors ; VectorType * ShuffleTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( isa < LoadInst > ( Inst ) ) { decompose ( Inst , Factor , ShuffleTy , DecomposedVectors ) ; transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getVectorElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getVectorNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , VectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; Value * WideVec = concatenateVectors ( Builder , TransposedVectors


<s> initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = <NUM_LIT> ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts ->


<s> if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false


<s> if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= <NUM_LIT> ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = <NUM_LIT> ; i


<s> MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT>


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock &

FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , BranchProbability Probability ) const {


<s> std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , LC , VT , In , CallOptions , dl , Chain ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first ,


<s> SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , SplatVT , DAG . getZExtOrTrunc ( InIdx , DL , IntEltVT ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue Seq = DAG . getNode ( <STR_LIT> , DL , SplatVT , Zero , One ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , PredVT , SplatIdx , Seq , DAG . getCondCode ( <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , SplatVT , Cmp ,


<s> if ( GET_CODE ( x ) != GET_CODE ( y ) ) return false ; rtx x_op0 = XEXP ( x , <NUM_LIT> ) ; rtx x_op1 = XEXP ( x , <NUM_LIT> ) ; rtx y_op0 = XEXP ( y , <NUM_LIT> ) ; rtx y_op1 = XEXP ( y , <NUM_LIT> ) ; if ( ! REG_P ( x_op0 ) || ! REG_P ( y_op0


<s> static DecodeStatus DecodeVSRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( )


<s> static __inline vec_int4 spu_rl ( vec_int4 a , int b ) { return ( ( vec_int4 ) ( si_roti ( ( qword ) ( a ) , b )


<s> static int loongarch_zero_extend_cost ( rtx


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) ,

JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E -> getSymbol ( ) ; CalleeFn = M -> getFunction (


<s> if ( const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , <STR_LIT> ) ; return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; Imm = N


<s> case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < <NUM_LIT> ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR


<s> static bool is64bitCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode


<s> MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) . getSizeInBits ( ) ) ; MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType


<s> MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF )


<s> return Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getMetadata (


<s> if ( I -> isDebugValue ( ) ) continue ; if ( Triple ( TM . getTargetTriple ( ) ) . isOSNaCl ( ) ) { int Dummy ; Iter FI ( llvm :: next ( I ) . base ( ) ) ; if ( terminateSearch ( * I ) || ( IsDangerousLoad ( * FI , & Dummy ) || IsDangerousStore ( * FI , & Dummy ) || FI -> modifiesRegister ( <STR_LIT> , TM . getRegisterInfo ( ) ) ) ) break ; } else { if ( terminateSearch ( * I


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; return ; } const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm (


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'y' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; if ( ! isPowerOf2_64 ( MO . getImm ( ) ) ) return true ; O << Log2_64 ( MO . getImm


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( )


<s> return std :: string ( <STR_LIT> ) + ( IsWrite ?

<STR_LIT> : <STR_LIT> ) + utostr ( AccessSize ) ;


<s> struct unw_table_entry * _Unwind_FindTableEntry ( void * pc , unsigned long * segment_base , unsigned long * gp ) { struct unw_ia64_callback_data data


<s> Val = ( Op1 . second == Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_NE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second != Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_LT : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second < Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_LE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> <STR_LIT> ) ; Val = ( Op1 . second <= Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_GT : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second > Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_GE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> <STR_LIT> ) ; Val = ( Op1 . second >= Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; } } } assert ( OperandStack . size ( ) == <NUM_LIT> && <STR_LIT> ) ; return OperandStack . pop_back_val ( ) . second


<s> for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) { SDValue SubVec = Op . getOperand ( i ) ; if ( SubVec . isUndef ( ) ) continue ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) ++ NumZero ; else { assert ( i < sizeof ( NonZeros ) * CHAR_BIT ) ; NonZeros |= ( uint64_t ) <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero <= <NUM_LIT> ) { SDValue Vec = NumZero ? getZeroVector ( ResVT , Subtarget , DAG , dl ) : DAG . getUNDEF ( ResVT ) ; if ( ! NumNonZero ) return Vec ; unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo


<s> Inst . addOperand ( MCOperand :: createReg ( getLO32DSPReg ( ) )


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Shifter ) ; Op -> Shift . ShiftTy = ShTy ; Op -> StartLoc = S ; Op -> EndLoc


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) ) + getMachineOpValue ( MI , MI . getOperand


<s> if ( ! Mst -> isTruncatingStore ( ) ) return SDValue ( ) ; EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> ,


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) -


<s> return MatchOperand_NoMatch ; } SMLoc S = Tok . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , S ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> void setBaseReg ( SDValue Reg ) { BaseType = RegBase ; Base_Reg =


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple


<s> EVT ScalarVT = Value . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Stores [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Ex = DAG . getNode ( <STR_LIT> , dl , ScalarVT , Value , DAG . getConstant ( Idx , dl , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Store ; if ( ScalarVT != ScalarMemVT ) Store = DAG . getTruncStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , MinAlign ( Alignment , Idx * Stride ) , SN -> getAAInfo ( ) ) ; else Store = DAG . getStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , MinAlign ( Alignment , Idx * Stride ) , SN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && SN -> isIndexed ( ) ) { assert ( SN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Store = DAG . getIndexedStore ( Store , dl , BasePtr , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ; Stores [ Idx ] = Store ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Stores ) ; if ( SN -> isIndexed ( ) ) { SDValue RetOps [ ] = { TF , Stores [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ; } return TF ; } assert ( SN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( Value . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ,


<s> static int feature_compare ( const void * v1 , const void * v2 ) { typedef struct _function_version_info { tree version_decl ; tree predicate_chain


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : <NUM_LIT> ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR :

<NUM_LIT> ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : <NUM_LIT> ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : <NUM_LIT> ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : <NUM_LIT> ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : <NUM_LIT> ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : <NUM_LIT> ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : <NUM_LIT> ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitRRX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> SDLoc DL ( BV ) ; SDValue InVec0 , InVec1 ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue InVec2 , InVec3 ; unsigned <ISA_LIT>Opcode ; bool CanFold = true ; if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , Half , InVec0 , InVec1 ) && isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , Half , NumElts , InVec2 , InVec3 ) && ( ( InVec0 . isUndef ( ) || InVec2 . isUndef ( ) ) || InVec0 == InVec2 ) && ( ( InVec1 . isUndef ( ) || InVec3 . isUndef ( ) ) || InVec1 == InVec3 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , Half , InVec0 , InVec1 ) && isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , Half , NumElts , InVec2 , InVec3 ) && ( ( InVec0 . isUndef ( ) || InVec2 . isUndef ( ) ) || InVec0 == InVec2 ) && ( ( InVec1 . isUndef ( ) || InVec3 . isUndef ( ) ) || InVec1 == InVec3 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else CanFold = false ; if ( CanFold ) { if ( NumUndefsLO + <NUM_LIT> == Half || NumUndefsHI + <NUM_LIT> == Half ) return SDValue ( ) ; SDValue V0 = InVec0 . isUndef ( ) ? InVec2 : InVec0 ; SDValue V1 = InVec1 . isUndef ( ) ? InVec3 : InVec1 ; assert ( ( ! V0 . isUndef ( ) || ! V1 . isUndef ( ) ) && <STR_LIT> ) ; bool isUndefLO = NumUndefsLO == Half ; bool isUndefHI = NumUndefsHI == Half ; return ExpandHorizontalBinOp ( V0 , V1 , DL , DAG , <ISA_LIT>Opcode , false , isUndefLO , isUndefHI ) ; } } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { unsigned <ISA_LIT>Opcode ; if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , NumElts , InVec0 , InVec1 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , NumElts , InVec0 , InVec1 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , NumElts , InVec0 , InVec1 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else if ( isHorizontalBinOpPart ( BV , <STR_LIT> , DAG , <NUM_LIT> , NumElts , InVec0 , InVec1 ) ) <ISA_LIT>Opcode = <STR_LIT> ; else return SDValue (


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Y , <STR_LIT> ) ; if ( SetCCResultType == VT && DAG . ComputeNumSignBits ( Cmp ) == VT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Sub ) ; return DAG . getSelect ( DL , VT , Cmp , Sub , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } return SDValue ( )


<s> return ( uint16_t ) __builtin_neon_vget_laneuv4hi ( ( int16x4_t )


<s> static DecodeStatus DecodeShiftRight8Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void


<s> return ( __m128 ) __builtin_ia32_cmpnltps ( ( __v4sf ) __A , (


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } if ( NegAcc ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } if ( NegRes ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode =


<s> unsigned nunits = GET_MODE_NUNITS ( data_mode ) ; unsigned elem_size = vector_size / nunits ; if ( ( TARGET_AVX512F && vector_size == <NUM_LIT> ) || ( TARGET_AVX512VL && ( vector_size == <NUM_LIT> || vector_size == <NUM_LIT> ) ) ) { if ( elem_size == <NUM_LIT> || elem_size == <NUM_LIT> || ( TARGET_AVX512BW && ( elem_size == <NUM_LIT> || elem_size == <NUM_LIT> ) ) ) return smallest_int_mode_for_size ( nunits ) ; } scalar_int_mode elem_mode = smallest_int_mode_for_size ( elem_size * BITS_PER_UNIT ) ; gcc_assert ( elem_size * nunits == vector_size ) ; return mode_for_vector ( elem_mode ,


<s> printThumbAddrModeRI5Operand ( MI , Op ,


<s> __o = __builtin_aarch64_ld2v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI

. getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) {


<s> Streamer . SwitchSection ( AttributeSection ) ; } else { AttributeSection = Streamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize ,


<s> } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned BeginIdx = IsQRegs ? <STR_LIT> : <STR_LIT> ; int Spacing = <NUM_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( SubRegs - <NUM_LIT> ) ; Spacing =


<s> if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> )


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame


<s> bool <ISA_LIT>TargetLowering :: generateFMAsInMachineCombiner ( EVT VT , CodeGenOpt :: Level OptLevel )


<s> void <ISA_LIT>InstPrinter :: printAddrModeMemSrc ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op1 = MI -> getOperand ( OpNum ) ; const MCOperand & Op2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Op1 .


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>4 ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>4


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF


<s> unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( isRegInSet ( RegDefs , Reg ) || isRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( isRegInSet ( RegDefs , Reg ) ) return true ; } } return


<s> HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST =


<s> case 'p' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCPmode , code = EQ ; break ; case 's' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCSmode , code = EQ ; break ; case 'z' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; } if ( code == UNKNOWN ) { error ( <STR_LIT> , constraints [ i ] ) ; continue ; } if ( invert ) code = reverse_condition ( code ) ; rtx dest = outputs [ i ] ; if ( ! saw_asm_flag ) { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_REG ( CCmode , FLAGS_REG ) ; saw_asm_flag = true ; } else { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_SCRATCH ( SImode ) ; } rtx x = gen_rtx_REG ( mode , FLAGS_REG ) ; x = gen_rtx_fmt_ee ( code , QImode , x , const0_rtx ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! SCALAR_INT_MODE_P ( dest_mode ) ) { error ( <STR_LIT> ) ; continue ; } if ( dest_mode == DImode && ! TARGET_64BIT ) dest_mode = SImode ; if ( dest_mode != QImode ) { rtx destqi = gen_reg_rtx ( QImode ) ; emit_insn ( gen_rtx_SET ( destqi , x ) ) ; if ( TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p ( cfun ) ) { x = force_reg ( dest_mode , const0_rtx ) ; emit_insn ( gen_movstrictqi ( gen_lowpart ( QImode , x ) , destqi ) ) ; } else x = gen_rtx_ZERO_EXTEND ( dest_mode , destqi ) ; } if ( dest_mode != GET_MODE ( dest ) ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( tmp , x ) ) ; emit_insn ( gen_zero_extendsidi2 ( dest , tmp ) ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; } rtx_insn * seq =


<s> if ( tree attr = lookup_attribute ( <STR_LIT> , attrs ) ) { tree mangled_name = TREE_VALUE ( TREE_VALUE ( attr ) ) ; return IDENTIFIER_POINTER ( mangled_name ) ; } return NULL


<s> SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , NewPtr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , Ld -> isVolatile ( ) , Ld


<s> return isIntImmediate ( N . getNode (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( )


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( TARGET_ILP32 ) { rtx t = gen_rtx_REG ( ptr_mode , <NUM_LIT> ) ; REG_POINTER ( t ) = <NUM_LIT> ; emit_move_insn ( t , gen_rtx_MEM ( ptr_mode , this_rtx ) ) ; if ( satisfies_constraint_I ( vcall_offset_rtx ) ) { emit_insn ( gen_ptr_extend_plus_imm ( tmp , t , vcall_offset_rtx ) ) ; vcall_offset = <NUM_LIT> ; } else emit_insn ( gen_ptr_extend ( tmp , t ) ) ; } else emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( vcall_offset ) { if ( ! satisfies_constraint_J ( vcall_offset_rtx ) ) { rtx tmp2 = gen_rtx_REG ( Pmode , next_scratch_gr_reg ( ) ) ; emit_move_insn ( tmp2 , vcall_offset_rtx ) ; vcall_offset_rtx = tmp2 ; } emit_insn ( gen_adddi3 ( tmp , tmp , vcall_offset_rtx ) ) ; } if ( TARGET_ILP32 ) emit_insn ( gen_zero_extendsidi2 ( tmp , gen_rtx_MEM ( ptr_mode , tmp ) ) ) ; else emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; ia64_expand_call ( NULL_RTX , funexp , NULL_RTX , <NUM_LIT> ) ; insn = get_last_insn ( ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; try_split ( PATTERN ( insn ) , insn , <NUM_LIT> ) ; emit_barrier ( ) ; emit_all_insn_group_barriers ( NULL ) ; insn = get_insns (


<s> __arm_cdp2 ( const unsigned int __coproc , const unsigned int __opc1 , const unsigned int __CRd , const unsigned int __CRn , const unsigned int __CRm ,


<s> if ( RxSBG . Rotate != <NUM_LIT> ) ShiftedIn = ( ( ShiftedIn << RxSBG . Rotate ) | ( ShiftedIn >> ( <NUM_LIT> - RxSBG . Rotate ) ) ) ; return ( ShiftedIn & RxSBG . Mask )


<s> if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices


<s> if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && ( ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ImmMask != <NUM_LIT> && ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false


<s> void addUImm4Operands ( MCInst & Inst , unsigned


<s> void <ISA_LIT>WinCOFFStreamer :: emitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: emitWinEHHandlerData ( Loc


<s> static const Permute * matchDoublePermute ( const SmallVectorImpl < int > & Bytes , SmallVectorImpl < int > & Transform ) { for ( auto & P : PermuteForms ) if ( matchDoublePermute ( Bytes , P , Transform ) ) return & P ; return


<s> bool isNotTargetNaCl ( ) const { return ! TargetTriple .


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( const GlobalValue * GV , Reloc :: Model RelocM ) const { if ( ! shouldAssumeDSOLocal ( RelocM , TargetTriple , * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetDarwin ( ) && RelocM == Reloc :: PIC_ && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return


<s> EmitTargetCodeForMemcmp ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src1 , SDValue Src2 , SDValue Size , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; Chain = emitCLC ( DAG , DL , Chain ,


<s> if ( pass_as_float ) { tree next_fp_tmp = create_tmp_var ( TREE_TYPE ( f_next_fp ) ) ; tree cmp ; bool is_double = size == <NUM_LIT> && TREE_CODE ( eff_type ) == REAL_TYPE ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_fp ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , valist , pre_p ) ; tmp = next_fp_limit ; if ( size > <NUM_LIT> && ! is_double ) tmp = fold_build_pointer_plus_hwi ( unshare_expr ( tmp ) , <NUM_LIT> - size ) ; tmp = build2 ( GE_EXPR , boolean_type_node , unshare_expr ( next_fp_tmp ) , unshare_expr ( tmp ) ) ; cmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; if ( ! is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_ALIGN ( eff_type ) > BITS_PER_WORD || ( is_double || size == <NUM_LIT> ) ) { tmp = fold_convert ( sizetype , next_fp_tmp ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , tmp , size_int ( UNITS_PER_WORD ) ) ; tmp = fold_build_pointer_plus ( unshare_expr ( next_fp_tmp ) , tmp ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , tmp , pre_p ) ; } if ( is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_MODE ( eff_type ) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN ) { tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ; tmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr


<s> if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr ->


<s> } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB , AddrReg


<s> if ( ( Count & <NUM_LIT> ) != <NUM_LIT> ) { for ( uint64_t i = <NUM_LIT> , e = ( Count & <NUM_LIT> ) ; i != e ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; } Count /=


<s> HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false


<s> Value * P = II . getOperand ( <NUM_LIT> ) ; Value * A = II . getOperand ( <NUM_LIT> ) ; auto FMul = II . getOperand ( <NUM_LIT> ) ; Value * B , * C ; if ( ! match ( FMul , m_Intrinsic < <STR_LIT> > ( m_Specific ( P ) , m_Value ( B ) , m_Value ( C ) ) ) ) return None ; if ( ! FMul -> hasOneUse ( )


<s> return __builtin_mve_veorq_sv16qi ( __a ,


<s> while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneUse ( CondDefReg ) ) { for ( auto UI = MRI . use_instr_begin ( CondDefReg ) , UE = MRI . use_instr_end ( ) ; UI != UE ; ++ UI ) { if ( CondDef == & * UI ) continue ; if ( UI -> getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { CondCode = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ! emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate (


<s> return ( __m128i ) __builtin_ia32_pslldi128 ( (


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) ; } return


<s> if ( dispatch_window_list -> next ) return dispatch_window_list -> next -> violation ; return dispatch_window_list -> violation


<s> return Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT>


<s> if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements


<s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( nullptr == InFlag ) { Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValueLo = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValueHi = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; } else { ArgValueLo = DAG . getCopyFromReg ( Root , Dl , VA . getLocReg ( )


<s> if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 (


<s> case FK_Data_4 : switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; default : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32 ; } case FK_SecRel_2 : return COFF :: IMAGE_REL_<ISA_LIT>_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH20T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH24T ; case <STR_LIT> : case <STR_LIT>


<s> if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; } return


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( CantUnwindLoc .


<s> bool useAA ( ) const override { return


<s> else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo ,


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : deinterleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; break ; } for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , VectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( Factor == <NUM_LIT> ) interleave8bitStride4 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; if ( Factor == <NUM_LIT> ) interleave8bitStride3 ( DecomposedVectors , TransposedVectors , NumSubVecElems ) ; break ; default : return false ; } Value * WideVec = concatenateVectors ( Builder , TransposedVectors ) ; StoreInst * SI = cast < StoreInst > ( Inst ) ; Builder . CreateAlignedStore ( WideVec , SI -> getPointerOperand ( ) , SI -> getAlign (


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; Register IntReg = RegInfo . createVirtualRegister ( & RC ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( MFC1 )

, IntReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok (


<s> for ( i = <NUM_LIT> ; i < d -> nelt ; ++ i ) if ( ( d -> perm [ i ] ^ ( i * <NUM_LIT> ) ) & ( <NUM_LIT> * d -> nelt / <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_SIZE ( GET_MODE_INNER ( d -> vmode ) ) ; m128 = GEN_INT ( - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / <NUM_LIT> - <NUM_LIT> ) ; unsigned which = d -> perm [ i ] >= nelt ; unsigned xorv = ( i >= nelt / <NUM_LIT> && i < <NUM_LIT> * nelt / <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ ( i * eltsz + j ) ^ xorv ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ ( i * eltsz + j ) ^ xorv ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0


<s> return MCInstBuilder ( Opcode ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI -> getOperand

( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSSE3 ( ) ) { int Idx = CostTableLookup ( SSSE3AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSSE3AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSEAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; int Idx = CostTableLookup ( SSEAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSEAltShuffleTbl [ Idx ] . Cost ; return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp


<s> void EmitByte ( unsigned char C , unsigned & CurByte ,


<s> return ( int16x4_t ) __builtin_neon_vabsv4hi (


<s> if ( Value & ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ) return static_cast < int64_t > ( Value ) - ( <NUM_LIT> << BitWidth ) ; else return


<s> mem = gen_frame_mem ( GET_MODE ( reg ) , addr ) ; return gen_rtx_SET ( store ? mem : reg , store ? reg


<s> if ( DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . isPseudo ( ) ) return false ; unsigned UseIdx ; for ( UseIdx = <NUM_LIT> ; UseIdx < UseMI . getNumOperands ( ) ; ++ UseIdx ) if ( UseMI . getOperand ( UseIdx ) . isReg ( ) && UseMI . getOperand ( UseIdx ) . getReg ( ) == Reg ) break ; assert ( UseIdx < UseMI . getNumOperands ( ) && <STR_LIT> ) ; assert ( UseIdx < UseMCID . getNumOperands ( ) && <STR_LIT> ) ; const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; MCRegister ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass ==


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size

== <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> hasExtractInsert ( ) ) return SDValue ( ) ; SDValue ShiftRight = N -> getOperand ( <NUM_LIT> ) , Mask = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftRightOpc = ShiftRight . getOpcode ( ) ; if ( ShiftRightOpc != <STR_LIT> && ShiftRightOpc != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * CN ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy .

getSizeInBits ( ) ) return SDValue ( ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; MachineOperand & OffsetMO = MI -> getOperand ( <NUM_LIT> ) ; <ISA_LIT>CallingConventionRegisters * Regs = STI . getSpecialRegisters ( ) ; uint64_t Offset = ( MFFrame . getMaxCallFrameSize ( ) + Regs -> getCallFrameSize ( ) +

Regs -> getStackPointerBias ( ) + OffsetMO . getImm ( ) ) ;


<s> return __builtin_ia32_vcvtps2phx128_mask ( ( __v4sf ) __A , _mm_setzero_ph ( ) , ( __mmask8


<s> HOST_WIDE_INT off ; rtx base ; gcc_assert ( MEM_P ( dest ) ) ; if ( GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == REG ) { base = XEXP ( dest , <NUM_LIT> ) ; off = <NUM_LIT> ; } else { gcc_assert ( GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ; base = XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ; off = INTVAL ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) ; } if ( base == hard_frame_pointer_rtx ) { saveop = <STR_LIT> ; off = - off ; } else { gcc_assert ( base == stack_pointer_rtx ) ; saveop = <STR_LIT> ; } src_regno = REGNO ( src ) ; switch ( src_regno ) { case BR_REG ( <NUM_LIT> ) : gcc_assert ( ! current_frame_info . r [ reg_save_b0 ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case PR_REG ( <NUM_LIT> ) : gcc_assert ( ! current_frame_info . r [ reg_save_pr ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_LC_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_lc ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_PFS_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_pfs ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_UNAT_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_unat ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case GR_REG ( <NUM_LIT> ) : case GR_REG ( <NUM_LIT> ) : case GR_REG ( <NUM_LIT> ) : case GR_REG (


<s> case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ <NUM_LIT> ] ) { case 'b' : RC = & <STR_LIT> ; break ; case 'h' : RC = & <STR_LIT> ; break ; case 's' : RC = & <STR_LIT> ; break ; case 'd' : RC = & <STR_LIT> ; break ; case 'q' : RC = & <STR_LIT> ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( )


<s> if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad , TM . getPointerSize ( ) , Alignment ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI


<s> Info . opc = <STR_LIT> ; const EVT VT = TLI . getMemValueType ( DL , CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; ElementCount EC = VT . getVectorElementCount ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumVecs ; ++ I ) assert ( VT == TLI . getMemValueType ( DL , CI . getArgOperand ( I ) -> getType ( ) ) && <STR_LIT> ) ; Info . memVT = EVT :: getVectorVT ( CI . getType ( ) -> getContext ( ) ,

VT . getScalarType ( ) , EC * NumVecs ) ;


<s> if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < <NUM_LIT> ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! ( * targetm . binds_local_p ) ( function )


<s> if ( UsesWinAAPCS ) return invalidateWindowsRegisterPairing ( Reg1 , Reg2 , NeedsWinCFI , IsFirst ) ; if ( NeedsFrameRecord ) return Reg2 ==


<s> void emitFnStartLocNotes ( ) const { for ( const SMLoc & Loc : FnStartLocs ) Parser . Note


<s> bool <ISA_LIT>InstructionSelector :: selectVaStartAAPCS ( MachineInstr & I , MachineFunction & MF , MachineRegisterInfo & MRI )


<s> bool hasLZCNTFalseDeps ( ) const { return HasLZCNTFalseDeps


<s> while ( n_ready -- ) { rtx_insn * insn ; int insn_size ; if ( ready_try [ n_ready ] ) continue ; insn = get_ready_element ( n_ready ) ; insn_size = min_insn_size


<s> addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass


<s> unsigned MaskEnd ; for ( unsigned r = <NUM_LIT> ; r < <NUM_LIT> ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = SelectInt64CountDirect ( RImm ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = <NUM_LIT> ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - <NUM_LIT> ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( <NUM_LIT>


<s> tree t ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; t = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ; return ( t


<s> bool <ISA_LIT>InstrInfo :: optimizeCompareInstr ( MachineInstr * Compare , unsigned SrcReg , unsigned SrcReg2 , int Mask , int Value , const MachineRegisterInfo * MRI ) const { assert ( ! SrcReg2 && <STR_LIT> ) ; bool IsLogical = ( Compare -> getDesc ( ) . TSFlags & <STR_LIT>


<s> enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx target = operands [ <NUM_LIT> ] ; rtx op0 = operands [ <NUM_LIT> ] ; rtx op1 = operands [ <NUM_LIT> ] ; rtx result = target ; if ( ! REG_P ( op0 ) || REGNO ( op0 ) != T_REG || ! CONST_INT_P ( op1 ) ) return false ; if ( ! REG_P ( result ) ) result = gen_reg_rtx ( SImode ) ; HOST_WIDE_INT val = INTVAL ( op1 ) ; if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movt ( result ,


<s> switch ( mode ) { case DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 ,


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( CC ) { default : break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } if ( NegateFCC ( LHS , RHS , CC ) ) std :: swap ( TrueV , FalseV ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) ,


<s> } } if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) || getLexer ( ) . is ( AsmToken :: Plus ) ) { if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; } Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT>


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> && ! ST -> hasAVX2


<s> <ISA_LIT>QPXLoadSplat ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>QPXLoadSplatPass ( * PassRegistry ::


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , SDValue Size , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; Chain = emitCLC ( DAG , DL , Chain


<s> bool <ISA_LIT>TargetLowering :: preferShiftsToClearExtremeBits ( SDValue Y ) const { EVT VT = Y . getValueType


<s> return ( ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET ==

<STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> ) && getShiftExtendAmount ( ) <= <NUM_LIT> ;


<s> if ( size == POINTER_SIZE / BITS_PER_UNIT && ! ( TARGET_NO_PIC || TARGET_AUTO_PIC ) && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) { static const char * const directive [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; fputs ( directive [ ( aligned_p != <NUM_LIT> ) ] [ POINTER_SIZE == <NUM_LIT> ] , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue rd = DAG . getNode ( <STR_LIT> , DL , Tys , Chain ) ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } Chain = HI . getValue ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT> ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << ( * SExt ) << '\n' ) ; bool insert = false ; for ( const User * U : SExt -> users ( ) ) { const Instruction * Inst = dyn_cast < GetElementPtrInst > ( U ) ; if ( Inst && Inst -> getNumOperands ( ) > <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Inst << '\n' ) ; insert = true ; break ; } } Instruction * Inst = SExt ; Value * Last ; do { int OpdIdx = <NUM_LIT> ; const BinaryOperator * BinOp = dyn_cast < BinaryOperator > ( Inst ) ; if ( BinOp && isa < ConstantInt > ( BinOp -> getOperand ( <NUM_LIT> ) ) ) OpdIdx = <NUM_LIT> ; Last = Inst -> getOperand ( OpdIdx ) ; Inst = dyn_cast < Instruction > ( Last ) ; } while ( Inst && canGetThrough ( Inst ) && shouldGetThrough ( Inst ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Last << '\n' ) ; DenseMap < Value * , Instruction * > :: iterator AlreadySeen = SeenChains . find ( Last ) ; if ( insert || AlreadySeen != SeenChains


<s> void mmix_asm_output_source_filename ( FILE * stream , const char * name ) { fprintf ( stream , <STR_LIT> ) ; OUTPUT_QUOTED_STRING ( stream


<s> __b = ( __vector signed short ) vec_splats ( __m2 ) ; __c = __a * __b ; return ( __m64 ) ( ( __vector long long ) __c


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm . Val =