<s> assert ( ! BytesAdded && <STR_LIT> ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) )


<s> return ( uint16x8_t ) __builtin_neon_vtstv8hi (


<s> if ( SDValue MAdd = combineLoopMAddPattern ( N , DAG , Subtarget ) ) return MAdd ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return

DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ;


<s> Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , VT ) , SDValue ( Carry , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , VT ) ) ; } SDNode * AddCarry = CurDAG -> getMachineNode ( ADDuOp , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry


<s> static DecodeStatus DecodeThumbCmpBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::

CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> void setMinMaxSVECSFrameIndex ( int Min , int Max ) { MinSVECSFrameIndex = Min ; MaxSVECSFrameIndex =


<s> int val = ( unsigned int ) MI -> getOperand ( OpNo ) . getImm ( ) ; if ( val >= <NUM_LIT> ) val = val - <NUM_LIT> ; O <<


<s> static bool isUncondBranchOpcode ( int Opc ) { using namespace llvm :: <ISA_LIT> ; assert ( ! BRKIND ( BRCFW ) && ! BRKIND ( BRCFD ) && ! BRKIND ( BRCFS ) && <STR_LIT> <STR_LIT> ) ; return BRKIND (


_mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> return loongarch_split_move_p ( dest , src


<s> B . setInstrAndDebugLoc ( MI ) ; auto Lane = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , MatchInfo . second ) ; B . buildInstr ( MatchInfo . first , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Lane } ) ; MI . eraseFromParent


<s> emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_e ( code


<s> if ( Rd == Ra ) return false ; LiveIntervals & LIs = G . getMetadata ( ) . LIS ; if ( Register :: isPhysicalRegister ( Rd ) || Register :: isPhysicalRegister ( Ra ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: isPhysicalRegister ( Rd ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: isPhysicalRegister ( Ra ) << '\n' ) ; return false ; } PBQPRAGraph :: NodeId node1 = G . getMetadata ( ) . getNodeIdForVReg ( Rd ) ; PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( Ra ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRdAllowed = & G . getNodeMetadata ( node1 ) . getAllowedRegs ( ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRaAllowed = & G . getNodeMetadata ( node2 ) . getAllowedRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; if ( edge == G . invalidEdgeId ( ) ) { const LiveInterval & ld = LIs . getInterval ( Rd ) ; const LiveInterval & la = LIs . getInterval ( Ra ) ; bool livesOverlap = ld . overlaps ( la ) ; PBQPRAGraph :: RawMatrix costs ( vRdAllowed -> size ( ) + <NUM_LIT> , vRaAllowed -> size ( ) + <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; for ( unsigned j = <NUM_LIT> , je = vRaAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRaAllowed ) [ j ] ; if ( livesOverlap && TRI -> regsOverlap ( pRd , pRa ) ) costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) ; else costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = haveSameParity ( pRd , pRa ) ? <NUM_LIT> : <NUM_LIT> ; } } G . addEdge ( node1 , node2 , std :: move ( costs ) ) ; return true ; } if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRaAllowed ) ; } PBQPRAGraph :: RawMatrix costs ( G . getEdgeCosts ( edge ) ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; PBQP :: PBQPNum sameParityMax = std :: numeric_limits < PBQP :: PBQPNum


<s> return ( poly8x8_t ) __builtin_neon_vld1_dupv8qi ( ( const __builtin_neon_qi * ) __a


<s> unsigned getReg ( ) const override { assert ( Kind == k_Register && <STR_LIT> ) ; return Reg . RegNum


<s> return m16_check_op ( op , ( - <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> <<


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) ,

CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_APCS ) {


<s> int MaxSubElts = <NUM_LIT> / EltSizeInBits ; for ( int NumSubElts = MinSubElts ; NumSubElts <= MaxSubElts ; NumSubElts *= <NUM_LIT> ) { int RotateAmt = matchShuffleAsBitRotate ( Mask , NumSubElts ) ; if ( RotateAmt < <NUM_LIT> ) continue ; int NumElts = Mask . size ( ) ; MVT RotateSVT = <STR_LIT> ( EltSizeInBits * NumSubElts ) ; RotateVT = <STR_LIT> ( RotateSVT , NumElts /


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF )

|| MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ;


<s> for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneCrossing [ <NUM_LIT> ] && LaneCrossing [ <NUM_LIT> ] ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneUsed [ <NUM_LIT> ] && LaneUsed [ <NUM_LIT> ] ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int & M = InLaneMask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( ( M % Size ) / LaneSize ) != ( i / LaneSize ) ) M = ( M % LaneSize ) + ( ( i / LaneSize ) * LaneSize ) + Size ; } assert ( ! is128BitLaneCrossingShuffleMask ( VT , InLaneMask ) && <STR_LIT> ) ; if ( ! AllLanes && ! is128BitLaneRepeatedShuffleMask ( VT , InLaneMask ) ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast ( PVT


<s> LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs ) ; State . AllocateReg ( IntRegs


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsHigh = <STR_LIT> ( Reg ) ; MI . setDesc ( get ( IsHigh


<s> return ( __m256 ) __builtin_ia32_vfnmaddps256 ( ( __v8sf ) __A , (


<s> Opc = <STR_LIT> ; } unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align ==


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X


<s> static int SizeForSuffix ( StringRef T ) { return StringSwitch < int > ( T ) . EndsWith ( <STR_LIT> , <NUM_LIT> ) . EndsWith ( <STR_LIT> , <NUM_LIT>


<s> do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE (


<s> static bool isLdOffsetInRangeOfSt ( MachineInstr & LoadInst , MachineInstr & StoreInst , const <ISA_LIT>InstrInfo * TII ) { assert ( isMatchingStore ( LoadInst , StoreInst ) && <STR_LIT> ) ; int LoadSize = TII -> getMemScale ( LoadInst ) ; int StoreSize = TII -> getMemScale ( StoreInst ) ; int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize <= ( UnscaledStOffset +


<s> if ( ! aarch64_classify_address ( & addr , op , mode , false , ADDR_QUERY_ANY ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return offset_6bit_signed_scaled_p ( mode , addr . const_offset ) ; return addr . type


<s> NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && Operands . size ( ) == <NUM_LIT> && ( Name == <STR_LIT> || Name == <STR_LIT> ) ) { std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; } return false


<s> return Opc == TargetOpcode :: G_SEXT || Opc ==


<s> Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasVAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasVPCLMULQDQ = false ; HasGFNI = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasVBMI2 = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false


) _mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MIRBuilder . buildCopy ( SPReg , Register ( <STR_LIT> ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT> ) / <NUM_LIT> ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg


<s> const char * abi ; if ( TARGET_FPU ) abi = <STR_LIT> ; else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi )


<s> bool aarch64_mov_operand_p ( rtx x , enum aarch64_symbol_context context , machine_mode mode ) { if ( GET_CODE ( x ) == HIGH && aarch64_valid_symref ( XEXP ( x , <NUM_LIT> ) ,

GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ) return true ;


<s> SDLoc DL ( N ) ; SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , Chain , Tgt ,


<s> Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; } else { ++ Result ; } if ( ! Shift ) return Result ; if ( ( unsigned ) ( Imm & <NUM_LIT> ) == Remainder ) { ++ Result ; return Result ; } if ( Imm ) ++ Result ; if ( ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ++ Result ; if ( Remainder & <NUM_LIT> )


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI .


<s> MCStreamer * <ISA_LIT>TargetMachine :: createMCStreamerToAsm ( MCContext & Context , std :: unique_ptr < formatted_raw_ostream > FOut , MCInstPrinter * InstPrinter , MCCodeEmitter * MCE , MCAsmBackend * MAB ) { MCStreamer * S = new <ISA_LIT>MCAsmStreamer ( Context , std :: move ( FOut ) , Options . MCOptions . AsmVerbose , InstPrinter


<s> return ( __m128d ) __builtin_ia32_expandloaddf128_maskz ( ( __v2df * ) __P , ( __v2df

) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> const <ISA_LIT>InstrRelaxTableEntry * llvm :: lookupRelaxTable ( unsigned ShortOp ) { return lookupRelaxTableImpl ( InstrRelaxTable ,


<s> if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR ) { warning ( <STR_LIT> ) ; target_flags &= ~ MASK_INLINE_DIV_THR ; } if ( ia64_fixed_range_string ) fix_range ( ia64_fixed_range_string ) ; ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload ; flag_schedule_insns_after_reload =


<s> static inline void setDirectAddressInInstr ( MachineInstr * MI , unsigned Operand , unsigned Reg ) { MI -> getOperand ( Operand ) . setReg ( Reg ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . setReg


<s> return __builtin_aarch64_frint64zdf ( __a )


<s> return ( __m512i ) __builtin_ia32_vpdpbusd_v16si_mask ( ( __v16si ) __A , ( __v16si )


<s> static DecodeStatus DecodeBranchTarget26MM ( MCInst & Inst , unsigned Offset ,

uint64_t Address , const void * Decoder ) {


<s> inline vector unsigned int vec_vavguw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vavguw ( ( vector signed int ) a1 , ( vector signed


<s> VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } return false


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ,


<s> rtl_opt_pass * make_pass_mips_machine_reorg2 ( gcc


<s> if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) ==

CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ;


<s> } if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , Parser . getTok ( ) . getLoc ( ) , * this ) ) ; return


<s> static SDValue LowerSIGN_EXTEND_AVX512 ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; MVT VTElt = VT . getVectorElementType ( ) ; MVT InVTElt = InVT . getVectorElementType ( ) ; SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget -> hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NegOne = DAG . getConstant ( APInt :: getAllOnesValue ( ExtVT . getScalarSizeInBits ( ) )


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectFPExt ( Instruction * I ) { if ( Subtarget -> hasSSE2 ( ) && I -> getType ( ) -> isDoubleTy ( ) ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> )


<s> void DecodeMOVLHPSMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts /

<NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ;


<s> return ( __m128d ) __builtin_ia32_rndscalepd_128_mask ( ( __v2df ) __A , __imm , ( __v2df ) _mm_setzero_pd ( ) , (


<s> static inline unsigned getLsb ( uint32_t


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL


<s> bool IsPredicatedOn ( MachineInstr * MI ) const { return VPST -> Predicates .


<s> const DataLayout * DL = TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> <<


<s> if ( suffix == 'w' ) return XFmode ; return VOIDmode


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue Glue = emitCmp ( DAG , DL , C ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( TrueOp ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( FalseOp ) ; if ( TrueC && FalseC ) { int64_t TrueVal = TrueC -> getSExtValue ( ) ; int64_t FalseVal = FalseC -> getSExtValue ( ) ; if ( ( TrueVal == - <NUM_LIT> && FalseVal == <NUM_LIT> ) || ( TrueVal == <NUM_LIT> && FalseVal == - <NUM_LIT> ) ) { if ( TrueVal == <NUM_LIT> ) C . CCMask ^=


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE &&


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) )


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterAsmParser < <ISA_LIT>_32ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterAsmParser < <ISA_LIT>_64ATTAsmParser > Y (


<s> static DecodeStatus DecodeBranchTargetMM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > (


<s> void WinEHStatePass :: linkExceptionRegistration ( IRBuilder < > & Builder , Function * Handler ) { Handler -> addFnAttr ( <STR_LIT> ) ; Type * LinkTy = getEHLinkRegistrationType ( ) ; Value * HandlerI8 = Builder . CreateBitCast ( Handler , Builder . getInt8PtrTy ( ) ) ; Builder . CreateStore ( HandlerI8 , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ; Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo (


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == <NUM_LIT> ) return true ; return false


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v'


<s> assert ( SlotSize == <NUM_LIT> || SlotSize == <NUM_LIT> ) ; unsigned RegA = ( SlotSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty


<s> static bool aarch64_vect_struct_mode_p ( machine_mode mode )


<s> if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand MMO ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , MFI . getObjectOffset ( FI ) + Offset , MFI . getObjectSize ( FI


<s> unsigned Index ; if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else return true ; switch ( Mode ) { default : return true ; case 'x' : Reg = <STR_LIT> + Index


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , const Instruction * I ) { int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ; return vectorCostAdjustment ( Cost , Opcode , ValTy , nullptr


<s> for ( auto Ty : { v16s16 , v8s32 } ) setAction ( { G_MUL , Ty } , Legal ) ; for ( const auto & Ty : { v64s8 , v32s16 , v16s32 , v8s64 } ) { setAction ( { G_CONCAT_VECTORS , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_CONCAT_VECTORS , <NUM_LIT> , Ty


<s> tree zero = build_zero_cst ( element_type ) ; unsigned int element_bytes = type_suffix ( <NUM_LIT> ) . element_bytes ; unsigned int count = constant_lower_bound ( TYPE_VECTOR_SUBPARTS ( vectype ) ) ; gcc_assert ( vl * element_bytes <= count ) ; tree_vector_builder builder ( vectype , count , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < count * <NUM_LIT> ; ++ i ) { bool bit = ( i & ( element_bytes - <NUM_LIT> ) ) == <NUM_LIT> && i < vl * element_bytes ; builder . quick_push ( bit ? minus_one : zero ) ; } return gimple_build_assign ( lhs , builder .


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; return true ; } return false


<s> void EmitBasicBlockEnd ( const MachineBasicBlock & MBB )


<s> MachineInstr * <ISA_LIT>LowOverheadLoops :: ExpandLoopStart ( LowOverheadLoop & LoLoop ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; IterationCountDCE ( LoLoop ) ; MachineInstr * InsertPt = LoLoop . InsertPt ; MachineInstr * Start = LoLoop . Start ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; bool IsDo = Start -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = LoLoop . getStartOpcode ( ) ; MachineOperand & Count = LoLoop . getCount ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , InsertPt -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count ) ; if ( ! IsDo ) MIB . add ( Start -> getOperand ( <NUM_LIT>


<s> return scalar_types [ type_suffix ( i ) . vector_type


<s> static inline bool isAdvSIMDModImmType7 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm &


<s> long int <ISA_LIT>ELFWriterInfo :: getDefaultAddendForRelTy ( unsigned RelTy , long int Modifier


<s> bool hasTransactionalExecution ( ) const { return HasTransactionalExecution


<s> vld1_s32 ( const int32_t * a ) { return __builtin_aarch64_ld1v2si ( ( const __builtin_aarch64_simd_si *


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> EVT MemVT = MSC -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; if ( MemVT . getScalarSizeInBits ( ) <= IndexVT . getScalarSizeInBits ( ) ) { IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; } else { MemVT = getContainerForFixedLengthVector ( DAG , MemVT ) ; IndexVT = MemVT . changeTypeToInteger ( ) ; } InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index


<s> rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode


<s> uint64_t UnsignedVal = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; int64_t SignedVal = cast < ConstantSDNode > ( Node ) -> getSExtValue ( ) ; EVT DestType = Node -> getValueType ( <NUM_LIT> ) ; <STR_LIT> Extension ; EVT MemType ; assert ( ( DestType == <STR_LIT> || DestType == <STR_LIT> ) && <STR_LIT> ) ; if ( DestType == <STR_LIT> ) { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } else if ( UnsignedVal <= UINT32_MAX ) { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } else if ( SignedVal >= INT32_MIN && SignedVal <= INT32_MAX ) { Extension = <STR_LIT> ; MemType = <STR_LIT>


<s> void <ISA_LIT>AsmBackend :: RelaxInstruction ( const MCInstFragment * IF , MCInst & Res ) const { unsigned RelaxedOp = getRelaxedOpcode ( IF -> getInst ( ) . getOpcode ( ) ) ; if ( RelaxedOp == IF -> getInst ( ) . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; IF -> getInst ( ) . dump_pretty (


<s> bool isVecListTwoMQ ( ) const { return isSingleSpacedVectorList ( ) && VectorList . Count == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ; return


<s> Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( ( char * ) ( Op + <NUM_LIT> ) , Str . data ( ) , Str . size ( ) ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT>

, DL , <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ConstantIslandPass ( <ISA_LIT>TargetMachine & tm


<s> void DecodePUNPCKLMask ( EVT VT , SmallVectorImpl < unsigned > & ShuffleMask ) { DecodeUNPCKLPMask ( VT , ShuffleMask


<s> static bool isCMP ( SDValue Op ) { return Op . getOpcode ( ) == <STR_LIT> && ! Op . getNode (


<s> static bool classof ( const MCExpr * E ) { return E -> getKind (


<s> case DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable (


<s> if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned SoImm = MI . getOperand ( Op ) . getImm ( ) ; int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned )


<s> static reg_class_t mmix_preferred_output_reload_class ( rtx


<s> call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) length += <NUM_LIT> ; else if ( TARGET_64BIT && ! local_call ) length += sibcall ? <NUM_LIT> : <NUM_LIT> ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += <NUM_LIT> ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && ( TARGET_LONG_PIC_PCREL_CALL || local_call ) ) ) { length += <NUM_LIT> ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && (

! local_call || flag_pic ) ) length += <NUM_LIT> ;


<s> if ( MBBI != MBB . begin ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { MachineInstr * PrevMI = prior ( MBBI ) ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { printOperand ( MI , opNum , STI , O ) ; if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) return ; if ( MO . isImm ( ) && MO . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT>


<s> did_load = <NUM_LIT> ; } if ( ! delta ) ; else if ( simple_add ) emit_move_insn ( this_rtx , this_value ) ; else { emit_move_insn ( scratch1 , GEN_INT ( delta ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch1 ) ) ; } if ( vcall_offset ) { rtx offset_addr ; if ( ! did_load ) emit_load_ptr ( scratch0 , this_rtx ) ; offset_addr = plus_constant ( Pmode , scratch0 , vcall_offset ) ; if ( strict_memory_address_p ( ptr_mode , offset_addr ) ) ; else if ( scratch0 != scratch1 ) { emit_move_insn ( scratch1 , GEN_INT ( vcall_offset ) ) ; offset_addr = gen_rtx_PLUS ( Pmode , scratch0 , scratch1 ) ; } else if ( CONST_OK_FOR_ADD ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch0 , GEN_INT ( vcall_offset ) ) ) ; offset_addr = scratch0 ; } else gcc_unreachable ( ) ; emit_load_ptr ( scratch0 , offset_addr ) ; if ( Pmode != ptr_mode ) scratch0 = gen_rtx_TRUNCATE ( ptr_mode , scratch0 ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch0 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( TARGET_SH1 && ! flag_weak ) sibcall = gen_sibcalli_thunk ( funexp , const0_rtx ) ; else if ( TARGET_SH2 && flag_pic ) { if ( TARGET_FDPIC ) { sibcall = gen_sibcall_pcrel_fdpic ( funexp , const0_rtx ) ; XEXP ( XVECEXP ( sibcall , <NUM_LIT> , <NUM_LIT> )


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo &


<s> void <ISA_LIT>TargetELFStreamer :: emitObjectArch ( unsigned Value


<s> for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs


<s> static MCDisassembler * create<ISA_LIT>64Disassembler ( const Target &


<s> static SDValue combineKSHIFT ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG


<s> MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC =


<s> if ( Subtarget . is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget . hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget . is64Bit ( ) && ! Subtarget . isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> if ( isImm ( ) ) { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> TRI = STI -> getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI


<s> VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align . value ( ) - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align . value ( ) , DL , VAList . getValueType ( ) ) ) ; } auto & TD = DAG . getDataLayout ( ) ; unsigned ArgSizeInBytes = TD . getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( alignTo ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL , VAList . getValueType ( ) ) ) ; Chain = DAG . getStore ( VAListLoad . getValue ( <NUM_LIT> ) , DL , Tmp3 , VAListPtr , MachinePointerInfo ( SV ) ) ; if ( ! Subtarget . isLittle ( ) && ArgSizeInBytes < ArgSlotSizeInBytes ) { unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes ; VAList = DAG . getNode ( <STR_LIT> , DL , VAListPtr . getValueType ( ) , VAList , DAG . getIntPtrConstant ( Adjustment , DL ) ) ; } return DAG . getLoad ( VT , DL , Chain , VAList


<s> MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . addMBB ( getWhileLoopStartTargetBB ( * MI ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg


<s> case 'q' : break ; case 'H' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { return true ; } else { PrintMemReference ( MI , OpNo , O , <STR_LIT> ) ; } return false ; case 'P' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O , <STR_LIT> ) ; } else { PrintMemReference ( MI , OpNo , O , <STR_LIT> ) ; } return false


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) Bits = CountTrailingZeros_32 ( Size ) ; return


<s> if ( MI . memoperands_empty ( ) ) return ; ( * MI . memoperands_begin ( )


<s> V = rotr32 ( ~ <NUM_LIT> , getSOImmValRotate ( V ) ) & V ; assert ( V == ( rotr32 ( <NUM_LIT> , getSOImmValRotate ( V )


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrRegImm ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> return hash_combine ( DenseMapInfo < int > :: getHashValue ( V . FI ) , DenseMapInfo < int > :: getHashValue ( V .


<s> <STR_LIT> <ISA_LIT>HazardRecognizer970 :: GetInstrType ( unsigned Opcode , bool & isFirst , bool & isSingle , bool & isCracked , bool & isLoad , bool & isStore ) { const MCInstrDesc & MCID = TM . getInstrInfo ( ) -> get ( Opcode ) ; isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags & <STR_LIT> ; return ( <STR_LIT> ) ( TSFlags


<s> void <ISA_LIT>AsmPrinter :: printMemBOption ( const MachineInstr * MI , int OpNum , raw_ostream &


<s> else if ( Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ ( <NUM_LIT> << ( <NUM_LIT> - CC ) ) : - <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ <NUM_LIT> << ( <NUM_LIT> - CC ) : - <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ ( ~ <NUM_LIT> << ( <NUM_LIT> - CC ) ) : <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ <NUM_LIT> << ( <NUM_LIT> - CC ) : - <NUM_LIT> ; else if ( Cond == <STR_LIT> || Cond == <STR_LIT> ) C . CCMask = CC < <NUM_LIT> ? ~ ( ~ <NUM_LIT> << ( <NUM_LIT> - CC ) ) : <NUM_LIT> ; else llvm_unreachable ( <STR_LIT> )


<s> return decodeBDRAddr12Operand ( Inst , Field , <STR_LIT>


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> char * aarch64_output_sve_scalar_inc_dec ( rtx offset ) { poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( offset_value . coeffs [ <NUM_LIT> ] == offset_value . coeffs [ <NUM_LIT> ] ) ; if ( offset_value . coeffs [ <NUM_LIT> ] > <NUM_LIT> ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , <STR_LIT>

, AARCH64_SV_ALL , offset_value . coeffs [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> <ISA_LIT>AddressMode ( ) : BaseType ( RegBase ) , Scale ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , Disp ( <NUM_LIT> )

, GV ( <NUM_LIT> ) , GVOpFlags ( <NUM_LIT> ) {


<s> if ( stack_realign_fp ) return ( ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) || ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ) ; else return to == STACK_POINTER_REGNUM ?


<s> ConstantInt * ValConst = dyn_cast_or_null < ConstantInt > ( NodeVal -> getValue ( ) ) ; if ( ValConst && NodeName -> getString ( ) == LiteralName ) { return ValConst -> getZExtValue ( ) ; } } report_fatal_error ( <STR_LIT> + LiteralName + <STR_LIT>


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { unsigned Val = ( MO . getImm ( ) & <NUM_LIT> ) ; assert ( Val == MO . getImm ( ) && <STR_LIT> ) ; unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#'


<s> static SDValue LowerWRITE_REGISTER ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue WriteValue = Op -> getOperand ( <NUM_LIT> ) ; assert ( WriteValue . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , WriteValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ops [ ] = { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Lo , Hi } ; return DAG . getNode ( <STR_LIT> , DL


<s> if ( FrameIdx < <NUM_LIT> ) return ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI -> getObjectAlignment ( FrameIdx ) ; if ( Align >= <NUM_LIT> ) return ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo


<s> return ( __m128 ) __builtin_ia32_unpcklps ( ( __v4sf )


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasAVX512 ( ) )


<s> if ( Subtarget . hasNEON ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair


<s> int group_count = <NUM_LIT> ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn )


<s> if ( ! ( CC == <STR_LIT> || CC == <STR_LIT> ) ) return SDValue ( ) ; if ( EFLAGS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpcode = EFLAGS . getOpcode ( ) ; if ( CmpOpcode != <STR_LIT> && CmpOpcode != <STR_LIT> ) return SDValue ( ) ; auto * CmpConstant = dyn_cast < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ; if ( ! CmpConstant ) return SDValue ( ) ; const APInt & CmpVal = CmpConstant -> getAPIntValue ( ) ; SDValue CmpOp = EFLAGS . getOperand ( <NUM_LIT> ) ; unsigned CmpBits = CmpOp . getValueSizeInBits ( ) ; assert ( CmpBits == CmpVal . getBitWidth ( ) && <STR_LIT> ) ; if ( CmpOp . getOpcode ( ) == <STR_LIT> ) CmpOp = CmpOp . getOperand ( <NUM_LIT> ) ; if ( CmpOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = CmpOp . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; assert ( ( VecVT . is128BitVector ( ) || VecVT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ; unsigned NumEltBits = VecVT . getScalarSizeInBits ( ) ; bool IsAnyOf = CmpOpcode == <STR_LIT> && CmpVal . isNullValue ( ) ; bool IsAllOf = CmpOpcode == <STR_LIT> && NumElts <= CmpBits && CmpVal . isMask ( NumElts ) ; if ( ! IsAnyOf && ! IsAllOf ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue BC = peekThroughBitcasts ( Vec ) ; MVT BCVT = BC . getSimpleValueType ( ) ; unsigned BCNumElts = BCVT . getVectorNumElements ( ) ; unsigned BCNumEltBits = BCVT . getScalarSizeInBits ( ) ; if ( ( BCNumEltBits == <NUM_LIT> || BCNumEltBits == <NUM_LIT> ) && BCNumEltBits > NumEltBits && DAG . ComputeNumSignBits ( BC ) > ( BCNumEltBits - NumEltBits ) ) { SDLoc DL ( EFLAGS ) ; unsigned CmpMask = IsAnyOf ? <NUM_LIT> : ( ( <NUM_LIT> << BCNumElts ) - <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BC ) , DAG . getConstant ( CmpMask , DL , <STR_LIT> ) ) ; } } if ( IsAllOf && Subtarget . hasSSE41 ( ) ) { SDValue BC = peekThroughBitcasts (


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Ws1 = RegInfo . createVirtualRegister ( RC ) ; unsigned Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI -> eraseFromParent


<s> static bool isRIPRelative ( const MCInst & MI , const MCInstrInfo & MCII ) { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned CurOp = <STR_LIT> ( Desc ) ; int MemoryOperand = <STR_LIT> ( TSFlags ) ; if ( MemoryOperand < <NUM_LIT> ) return false ; unsigned BaseRegNum = MemoryOperand + CurOp +


<s> <ISA_LIT>PostRASchedStrategy ( const MachineSchedContext * C ) : PostGenericScheduler ( C


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return

C -> getAPIntValue ( ) . ule ( <NUM_LIT> ) ;


<s> unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize


<s> BranchSize = BrOffset ; MaxAlign = std :: max ( MaxAlign , Src -> getAlignment ( ) ) ; int DestBlock = Dest -> getNumber ( ) ; BranchSize += BlockSizes [ DestBlock ] . first ; for ( unsigned i = DestBlock + <NUM_LIT> , e = Src -> getNumber ( ) ; i < e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i ) -> getAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( DestBlock >= FirstImpreciseBlock ) ; } else { unsigned StartBlock = Src -> getNumber ( ) ; BranchSize = BlockSizes [ StartBlock ] . first - BrOffset ; MaxAlign = std :: max ( MaxAlign , Dest -> getAlignment ( ) ) ; for ( unsigned i = StartBlock + <NUM_LIT> , e = Dest -> getNumber ( ) ; i != e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i )


<s> return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short


<s> rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; xops [ <NUM_LIT> ] = gen_rtx_REG ( BImode , PR_REG ( <NUM_LIT> ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [


<s> if ( SawStore ) return true ; SawLoad = true ; } if ( MI -> mayStore ( ) ) { if ( SawStore ) return true ; SawStore = true ; if ( SawLoad ) return true ; } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( isRegInSet ( RegDefs , Reg ) || isRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( )


<s> UpperBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UpperBits ) ; SDValue LowerBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VTs , UpperBits , LowerBits ) . getValue ( <NUM_LIT> ) ; } else { SDValue UpperBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VTs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , UpperBits ) . getValue ( <NUM_LIT> ) ; } break ; } assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; if ( IsSigned ) { SDValue UpperBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; SDValue LowerBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VTs


<s> static bool ix86_allocate_stack_slots_for_args ( void ) { return ! ix86_function_naked ( current_function_decl )


<s> MVT VecIntVT = V . getSimpleValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle , APInt

( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( Cond . getOpcode ( ) != <STR_LIT> ) return Op ; return createCMovFP ( DAG , Cond , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , SDLoc


<s> return __builtin_mve_vsubq_m_n_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a


<s> static inline uint8_t encodeAdvSIMDModImmType3 (


<s> if ( * name != '*' && * user_label_prefix && * stripped != FASTCALL_PREFIX

) stripped = ACONCAT ( ( user_label_prefix , stripped , NULL ) ) ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue

> & Results , SelectionDAG & DAG ) const {


<s> assert ( TTI -> getPrefetchDistance ( ) && <STR_LIT> ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return lowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT> ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; if ( ! ResultReg


<s> if ( x > <NUM_LIT> ) return __clz_tab [ x >> <NUM_LIT> ] + <NUM_LIT> ; return __clz_tab [ x ] -


<s> MCStreamer & OS = getStreamer ( ) ; MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHT_REL ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( Name ) ; const MCSymbolRefExpr * ExprRef = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Context ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( <NUM_LIT> ) ; OS . PushSection ( ) ; OS . SwitchSection ( Sec ) ; OS . EmitValueImpl ( ExprRef , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet =


<s> unsigned Width = ShrunkMask . getActiveBits ( ) ; if ( Width == <NUM_LIT> ) return false ; Width = PowerOf2Ceil ( std :: max ( Width , <NUM_LIT> ) ) ; Width = std :: min ( Width , Size ) ; APInt ZeroExtendMask = APInt :: getLowBitsSet ( Size , Width ) ; if ( ZeroExtendMask == Mask ) return true ; if ( ! ZeroExtendMask . isSubsetOf ( Mask | ~ Demanded ) ) return false ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( ZeroExtendMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op


<s> if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ; MI . addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } if ( ! NoFloat && ( Control & <NUM_LIT> ) != <NUM_LIT> ) { if ( Subtarget . hasVector ( ) ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { unsigned Reg = <STR_LIT> [ I ] ; MI . addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } }


<s> return createMachOStreamer ( Ctx , TAB , OS , Emitter , RelaxAll , DWARFMustBeAtTheEnd , true


<s> const int64_t C0 = C0Node -> getSExtValue ( ) ; APInt CA = C0Node -> getAPIntValue ( ) * C1Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C0 ) || isLegalAddImmediate ( CA . getSExtValue ( ) ) ) return true ; if ( ConstantMaterializationCost ( ( unsigned ) CA . getZExtValue ( ) , Subtarget ) > <NUM_LIT> ) return false ; return true


<s> if ( DecodeMovePRegPair ( Inst , RegPair , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; unsigned RegRs ; if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> has<ISA_LIT>32r6 ( ) ) RegRs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; else RegRs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPRMM16MovePRegisterClass ( Inst , RegRs , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; unsigned RegRt = fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> int register_ok_for_ldd ( rtx reg ) { if ( ! REG_P ( reg ) ) return <NUM_LIT> ; if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER ) return ( REGNO ( reg ) % <NUM_LIT> == <NUM_LIT> ) ; return


<s> static __inline qword si_rotma ( qword a , qword b ) { vec_uint4 neg_b ; vec_uint4 mask ; neg_b = ( vec_uint4 ) vec_sub ( vec_splat_s32 ( <NUM_LIT> ) , ( vec_int4 ) ( b ) ) ; mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_sra ( ( vec_int4 ) ( a ) , ( vec_uint4 ) vec_or


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { SDValue CCVal = Op -> getOperand ( <NUM_LIT> ) ; SDValue TVal = Op -> getOperand ( <NUM_LIT> ) ; SDValue FVal = Op -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( Ty . isScalableVector ( ) ) { SDValue TruncCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCVal ) ; MVT PredVT = <STR_LIT> ( <STR_LIT> , Ty . getVectorElementCount ( ) ) ; SDValue SplatPred = DAG . getNode ( <STR_LIT> , DL , PredVT , TruncCC ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , SplatPred , TVal , FVal ) ; } if ( <STR_LIT> ( CCVal ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( CCVal -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , CCVal . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( OFCC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand


<s> SDValue BaseShAmt ; MVT EltVT = VT . getVectorElementType ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Amt ) ) { BaseShAmt = BV -> getSplatValue ( ) ; if ( BaseShAmt && BaseShAmt . isUndef ( ) ) BaseShAmt = SDValue ( ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = dyn_cast < ShuffleVectorSDNode > ( Amt ) ; if ( SVN && SVN -> isSplat ( ) ) { unsigned SplatIdx = ( unsigned ) SVN -> getSplatIndex ( ) ; SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { assert ( ( SplatIdx < InVec . getSimpleValueType ( ) . getVectorNumElements ( ) ) && <STR_LIT> ) ; BaseShAmt = InVec . getOperand ( SplatIdx ) ; } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( ! BaseShAmt ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , InVec , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; } } if ( BaseShAmt . getNode ( ) )


<s> bool isGPR32Asm ( ) const { return Kind == k_Register && Reg . Kind ==


<s> CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ return HasSVE ? <STR_LIT> ## n : <STR_LIT> ## n CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> )


<s> auto * S = new <ISA_LIT>WinCOFFStreamer ( Context , std :: move ( MAB ) , std :: move ( Emitter ) , OS ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return S


<s> __vector signed short a , b ; __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short


<s> static __inline void * si_to_ptr ( qword q ) { union { qword q ; void * p ; }


<s> bool inMicro<ISA_LIT>Mode ( ) const { return getSTI ( ) . getFeatureBits ( ) [


<s> unsigned addressReg ( <STR_LIT> VT )


<s> uint64_t SizeEncoding = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; return SizeEncoding -


<s> int loongarch_regno_mode_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno ==


<s> HOST_WIDE_INT offsets [ <NUM_LIT> ] , offset , align [ <NUM_LIT> ] ; rtx base = NULL_RTX ; rtx cur_base , cur_offset ; int i , gap ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) { if ( ! mem_ok_for_ldrd_strd ( operands [ nops + i ] , & cur_base , & cur_offset , & align [ i ] ) ) return false ; if ( i == <NUM_LIT> ) base = cur_base ; else if ( REGNO ( base ) != REGNO ( cur_base ) ) return false ; offsets [ i ] = INTVAL ( cur_offset ) ; if ( GET_CODE ( operands [ i ] ) == SUBREG ) return false ; } if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) return false ; gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; if ( gap != GET_MODE_SIZE ( SImode ) ) return false ; if ( ! align_ok_ldrd_strd ( align [ <NUM_LIT> ]


<s> static bool isVShiftRImm ( SDValue Op , EVT VT , bool isNarrow , bool isIntrinsic , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= - <NUM_LIT> ) { Cnt = -


<s> if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) || ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) ) FrameReg = <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isGPFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) ) Offset = spOffset ; else Offset = spOffset + ( int64_t ) stackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( <STR_LIT> ) ; } MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) .


<s> void rs6000_emit_xxspltidp_v2df ( rtx dst , long value ) { if ( ( ( value & <NUM_LIT> ) == <NUM_LIT> ) && ( ( value & <NUM_LIT> ) !=


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer . SwitchSection ( getObjFileLowering (


<s> else if ( STI -> hasV8MMainlineOps ( ) ) CMSERestoreFPRegsV8 (


<s> Arg = TruncInput . getOperand ( <NUM_LIT> ) ; continue ; } } break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode )


<s> for ( const SMLoc & Loc : CantUnwindLocs ) Parser . Note ( Loc


<s> bool m16_based_address_p ( rtx x , machine_mode mode , insn_operand_predicate_fn offset_predicate ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && M16_REG_P ( REGNO ( addr . reg ) ) &&

offset_predicate ( addr . offset , mode ) ) ;


<s> } MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && CountThree ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; if ( CountThree ) { transferImpOps ( MI , MIB , MIB1 ) ; MI . eraseFromParent ( ) ; return true ; } for ( ShiftAmt += <NUM_LIT> ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } MachineInstrBuilder MIB2 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define

| getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ;


<s> return ( __m512i ) __builtin_ia32_pmovsxbw512_mask ( ( __v32qi ) __A , ( __v32hi ) _mm512_setzero_hi ( ) , ( __mmask32 ) -


<s> if ( TARGET_SHCOMPACT && ( ( current_function_args_info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) || current_function_has_nonlocal_label ) ) return gen_frame_mem ( SImode , return_address_pointer_rtx ) ; val = get_hard_reg_initial_val ( Pmode , TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; if ( TARGET_SH1 ) return gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> ,


<s> bool isT2SOImmNeg ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> emit_library_call_value ( gen_tls_get_addr ( ) , dest , LCT_CONST , Pmode


<s> if ( ! isScalarLoadToVector ( SrcOp . getNode ( ) , & LD ) ) LD = dyn_cast < LoadSDNode > ( SrcOp ) ; if ( ! LD ) { MVT ExtVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( ExtVT != <STR_LIT> || Subtarget -> is64Bit ( ) ) && SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == ExtVT ) { OpVT = ( OpVT == <STR_LIT>


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; unsigned OpIdx = <NUM_LIT> ; Binary |= encodeNEONRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRn ( MI


<s> if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( DAG . ComputeMaxSignificantBits ( Op0 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( DAG . ComputeMaxSignificantBits ( Op1 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op0 . getOperand ( <NUM_LIT> ) ) && Op0 . hasOneUse ( ) && ( <ISA_LIT>CC ==


<s> assert ( ! VT . isVector ( ) && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , N0 ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> resetUnwindDirectiveParserState ( ) ; getTargetStreamer ( ) . emitFnEnd ( ) ; return false


<s> unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned NewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned OldVal = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned BinOpRes = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal0 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned SllRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrLSB2 )

. addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FP8Reg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ; break ; case


<s> if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return Op ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT>

) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ;


<s> if ( TARGET_X32 ) d_add_builtin_version ( <STR_LIT> ) ; } else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_80387 ) d_add_builtin_version ( <STR_LIT> ) ; else d_add_builtin_version ( <STR_LIT>


<s> static void aarch64_parse_tune_string ( const char * tune_string , struct


<s> OS << formatHex ( ( Op . getImm ( ) << <NUM_LIT> ) | <NUM_LIT> ) ; } else { assert ( Op . isExpr ( ) &&


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , * CurDAG


<s> if ( NumNonZero > <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue V ( <NUM_LIT> , <NUM_LIT> ) ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero


<s> const MCSymbolData & SD = Asm . getSymbolData ( * Reloc . Symbol ) ; if ( MCELF :: GetBinding ( SD ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_GOT16


<s> HOST_WIDE_INT iq2000_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == <NUM_LIT> ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { HOST_WIDE_INT frame_size = ( ! cfun -> machine -> initialized ) ? compute_frame_size ( get_frame_size ( ) ) : cfun -> machine -> total_size ; offset = offset -


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm8s4Operand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1


<s> auto AddrI = BuildMI ( * Pred , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , TargetReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } TargetAddrSSA . AddAvailableValue ( Pred , TargetReg ) ; } unsigned TargetReg = TargetAddrSSA . GetValueInMiddleOfBlock ( & MBB ) ; MBB . setHasAddressTaken ( ) ; auto InsertPt = MBB . SkipPHIsLabelsAndDebug ( MBB . begin ( ) ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addMBB ( & MBB ) ; ++ NumInstsInserted ; ( void ) CheckI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CheckI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { Register AddrReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto AddrI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , AddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addReg ( AddrReg , RegState :: Kill ) ; ++ NumInstsInserted ; ( void ) CheckI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CheckI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ; Register UpdatedStateReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto CMovI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( CMovOp ) , UpdatedStateReg ) . addReg ( PS -> InitialReg ) . addReg ( PS -> PoisonReg ) . addImm ( <STR_LIT> ) ; CMovI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( true ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CMovI -> dump ( ) ; dbgs ( )


<s> if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = <NUM_LIT> ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ; cfun -> machine -> next_fcc += count ; return gen_rtx_REG ( mode , regno


<s> Defs &= ~ ( <NUM_LIT> << DReg ) ; } if ( Kills && I != MBB -> begin ( ) ) { MachineBasicBlock :: iterator I2 = std :: prev ( I ) ; while ( StackTop ) { unsigned KReg = getStackEntry ( <NUM_LIT> ) ; if ( ! ( Kills & ( <NUM_LIT> << KReg ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; popStackAfter ( I2 ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; } } while ( Kills ) { unsigned KReg = countTrailingZeros ( Kills ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; freeStackSlotBefore ( I , KReg ) ; Kills &= ~ ( <NUM_LIT>


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAligned } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAligned } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCCodeEmitter :: getFixupKindInfo (


<s> void <ISA_LIT>ConstantIslands :: doInitialPlacement ( std :: vector < MachineInstr * > & CPEMIs ) { MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : <NUM_LIT> ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } DEBUG ( BB ->


<s> MVT OpVT = Op . getSimpleValueType ( ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; MVT WideOpVT = OpVT ; if ( ( ! Subtarget . hasDQI ( ) && NumElems == <NUM_LIT> ) || NumElems < <NUM_LIT> ) WideOpVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; if ( IdxVal == <NUM_LIT> && <STR_LIT> ( Vec . getNode ( ) ) ) { Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , SubVec , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } MVT SubVecVT = SubVec . getSimpleValueType ( ) ; unsigned SubVecNumElems = SubVecVT . getVectorNumElements ( ) ; assert ( IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Undef = DAG . getUNDEF ( WideOpVT ) ; if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getTargetConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , SubVec , ZeroIdx ) ; Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; if ( Vec . isUndef ( ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; if ( llvm :: all_of ( Vec -> ops ( ) . slice ( IdxVal + SubVecNumElems ) , [ ] ( SDValue V ) { return V . isUndef ( )


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Base = i +


<s> for ( ; I < ByVal . NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { assert ( ( ByValSizeInBytes > OffsetInBytes ) && ( ByValSizeInBytes < OffsetInBytes + RegSizeInBytes ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal .


<s> return ( uint16x4_t ) __builtin_aarch64_addpv4hi ( ( int16x4_t )


<s> if ( HasAccum ) { SDValue AccLo = N -> getOperand ( OpIdx ++ ) ; SDValue AccHi = N -> getOperand ( OpIdx ++ ) ; if ( IsBigEndian ) std :: swap ( AccLo , AccHi ) ; Ops . push_back ( SDValue ( createGPRPairNode ( <STR_LIT> , AccLo , AccHi ) , <NUM_LIT> ) ) ; } for ( size_t I = <NUM_LIT> ; I < NumExtraOps ; I ++ ) Ops . push_back ( N -> getOperand ( OpIdx ++ ) ) ; SDValue Imm = N -> getOperand ( OpIdx ) ; uint32_t ImmVal = cast < ConstantSDNode > ( Imm ) -> getZExtValue ( ) ; Ops . push_back ( getI32Imm ( ImmVal , Loc ) ) ; if ( HasAccum ) { SDValue Pred = getAL ( CurDAG , Loc ) ; SDValue PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Ops . push_back ( Pred ) ; Ops . push_back ( PredReg ) ; } SDNode * InstrNode = CurDAG -> getMachineNode ( Opcode , Loc , <STR_LIT> , Ops ) ; SDValue ResultPair = SDValue ( InstrNode , <NUM_LIT> ) ; uint16_t SubRegs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; if ( IsBigEndian ) std :: swap ( SubRegs [ <NUM_LIT> ] , SubRegs [ <NUM_LIT> ] ) ; for ( size_t ResIdx = <NUM_LIT> ; ResIdx < <NUM_LIT> ; ResIdx ++ ) { if ( SDValue ( N , ResIdx ) . use_empty ( ) ) continue ; SDValue SubReg = CurDAG -> getTargetExtractSubreg ( SubRegs [ ResIdx ] , Loc , <STR_LIT> , ResultPair ) ; ReplaceUses ( SDValue ( N ,


<s> static const char * const CPUDirectives [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; if ( Subtarget . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport


<s> unsigned <ISA_LIT>16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return <NUM_LIT>


<s> } if ( ( val & <NUM_LIT> ) == <NUM_LIT> || ( val & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; i = <NUM_LIT> ; while ( ( ( val >>= <NUM_LIT> ) & <NUM_LIT>


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; bool IsSignaling = Op . getOpcode ( ) == <STR_LIT> ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS , Chain , IsSignaling ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC =


<s> static SDValue lowerV16F32VectorShuffle ( SDLoc DL , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask


<s> LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( Load ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return false ; switch ( Load -> getExtensionType ( )


<s> ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregciv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t