<s> expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI ) ; break ; case <STR_LIT> : expandDPLoadStore ( MBB , MI , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : expandDPLoadStore ( MBB , MI , <STR_LIT> , <STR_LIT> ) ; break ; case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ITBlock . instrInITBlock ( ) && ! ITBlock . instrLastInITBlock ( ) ) S = SoftFail ; break ; default : break ; } unsigned CC ; CC = ITBlock . getITCC ( ) ; if ( CC == <NUM_LIT> ) CC = <STR_LIT> ; if ( ITBlock . instrInITBlock ( ) ) ITBlock . advanceITState ( ) ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator I = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( I == MI . end ( ) ) break ; if ( OpInfo [ i ] . isPredicate ( ) ) { I = MI . insert ( I , MCOperand :: CreateImm ( CC ) ) ; ++ I ; if ( CC == <STR_LIT> ) MI . insert ( I , MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else MI . insert ( I , MCOperand :: CreateReg ( <STR_LIT> ) ) ; return S ; } } I = MI . insert ( I , MCOperand


<s> unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned RegSize = STI . isGP32bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned StackAlign = getStackAlignment ( ) ; unsigned LocalVarAreaOffset = <ISA_LIT>FI -> needGPSaveRestore ( ) ? ( MFI -> getObjectOffset ( <ISA_LIT>FI -> getGPFI ( ) ) + RegSize ) : <ISA_LIT>FI -> getMaxCallFrameSize ( ) ; uint64_t StackSize = RoundUpToAlignment ( LocalVarAreaOffset , StackAlign ) + RoundUpToAlignment ( MFI -> getStackSize ( ) , StackAlign ) ; MFI -> setStackSize ( StackSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else expandLargeImm ( SP , - StackSize , STI . isABI_N64 ( ) , TII , MBB , MBBI , dl ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation ::


<s> if ( RPI . IsGPR ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } ; if ( ReverseCSRRestoreSeq ) for ( const RegPairInfo & RPI :


<s> virtual bool isSelectSupported ( SelectSupportKind Kind )


<s> SDValue LHS = ShiftOperand . getOperand ( <NUM_LIT> ) ; SDValue RHS = ShiftOperand . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = LHS . getOpcode ( ) ; if ( ( ExtOpc != <STR_LIT> && ExtOpc != <STR_LIT> ) || RHS . getOpcode ( ) != ExtOpc ) return SDValue ( ) ; LHS = LHS . getOperand ( <NUM_LIT> ) ; RHS = RHS . getOperand ( <NUM_LIT> ) ; EVT MulVT = LHS . getValueType ( ) ; if ( MulVT . getVectorElementType ( ) != <STR_LIT> || RHS . getValueType ( ) != MulVT ) return SDValue ( ) ; unsigned Opc = ExtOpc == <STR_LIT>


<s> return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed :


<s> if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand (


<s> return ( <NUM_LIT> && ( ! TARGET_SHCOMPACT || current_function_args_info . stack_regs == <NUM_LIT> ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC (

decl ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ;


<s> In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , DAG . getBitcast ( <STR_LIT> , OpLo ) , DAG . getBitcast ( <STR_LIT> , OpHi ) , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getBitcast ( <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask1 ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask2 ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( <STR_LIT> , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OpLo = DAG . getBitcast ( <STR_LIT> ,


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( )


<s> static <ISA_LIT>Operand * MorphToMEMri ( unsigned Base , <ISA_LIT>Operand * Op ) { const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = k_MemoryImm ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg


<s> else return DAG . getConstant ( <NUM_LIT> , VT ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( Opc , dl , VT , SrcOp , DAG . getConstant ( ShiftAmt , <STR_LIT>


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG


<s> decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , <NUM_LIT> ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , <NUM_LIT> ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , <NUM_LIT> ) ) ) ) { if ( ( TREE_CODE ( decl_op1 ) == VAR_DECL || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( TREE_CODE ( decl_op0 ) == VAR_DECL || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return

( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = LHS . getValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc =


<s> unsigned <ISA_LIT>CodeEmitter :: getMSAMemEncoding ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT>


<s> break ; case <NUM_LIT> : * ptree = ms_va_list_type_node ; * pname = <STR_LIT> ; return <NUM_LIT> ; case <NUM_LIT> : * ptree = sysv_va_list_type_node


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ? <STR_LIT> :


<s> assert ( isMem ( MI , Op ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CallerCC != CalleeCC ) return false ; if ( CalleeCC != CallingConv :: Fast && CalleeCC != CallingConv :: C ) return false ; if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags


<s> } if ( save_fp_p ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_gp_p ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_lp_p ) { reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = * MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , VReg , Offset ) ; } )


<s> void setAttributeItems ( unsigned Attribute , unsigned IntValue , StringRef StringValue , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeItem ::


<s> SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT> ; } } if ( Glue . getNode ( ) ) AsmNodeOperands . push_back ( Glue ) ; if ( ! Changed ) return nullptr ; SDValue New = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) , AsmNodeOperands ) ; New -> setNodeId ( -


<s> if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get (


<s> unsigned <ISA_LIT>BaseInstrInfo :: getPredicationCost ( const MachineInstr & MI ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) ||

MI . isImplicitDef ( ) ) return <NUM_LIT> ;


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MMULFXRP_W ( ( v4hi ) mm , ( v4hi )


<s> return __builtin_mve_vsubq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a


<s> case ORDERED : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_ABS ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case EQ : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , gen_rtx_ABS ( compare_mode , op0 ) ) ) ) ; op0 = temp ; break ; case UNGE : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; false_cond = true_cond ; true_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case GT : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; true_cond = false_cond ; false_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; return


<s> info -> world_save_p = <NUM_LIT> ; break ; } } if ( WORLD_SAVE_P ( info ) ) { info -> vrsave_size = <NUM_LIT> ; info -> lr_save_p = <NUM_LIT> ; if ( info -> vrsave_mask == <NUM_LIT> ) info -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info ->

first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ;


<s> const <ISA_LIT>TargetMachine * getTM ( ) const { return


<s> SDLoc dl ( Op ) ; SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Cmp -> getOperand ( <NUM_LIT> ) ) ; SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b


<s> selectVSplatUimm6 ( SDValue N , SDValue & Imm ) const { return selectVSplatCommon ( N , Imm , false


<s> _mm_cvtt_roundsd_u64 ( __m128d __A , const int __R ) { return ( unsigned long long ) __builtin_ia32_vcvttsd2usi64 (


<s> auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty


<s> static bool modifiesConditionCode ( MachineInstr * From , MachineInstr * To , const bool CheckOnlyCCWrites , const TargetRegisterInfo * TRI ) { MachineBasicBlock :: iterator I = To , E = From , B = To -> getParent ( ) -> begin ( ) ; if ( I == B ) return true ; if ( To -> getParent ( ) != From -> getParent ( ) ) return true ; for ( -- I ; I != E ; -- I ) { const MachineInstr & Instr =


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C )

) return <ISA_LIT>MaterializeGV ( GV , VT ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << ( int32_t ) Op . getImm ( ) ; } else


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return


<s> void <ISA_LIT>InstPrinter :: printU12ImmOperand ( const MCInst * MI , int


<s> if ( ! isSingleSpacedVectorList ( ) ) return false ; return VectorList . Count == <NUM_LIT>


<s> errs ( ) << <STR_LIT> << this << '\n' ; errs ( ) << <STR_LIT> ; if ( Base . getNode ( ) != <NUM_LIT> ) Base . getNode ( ) -> dump ( ) ; else errs ( ) << <STR_LIT> ; if ( hasIndexField ( ) ) { errs ( ) << <STR_LIT> ; if ( Index . getNode ( ) != <NUM_LIT> ) Index . getNode ( ) -> dump ( ) ; else errs ( ) << <STR_LIT> ; } errs ( ) << <STR_LIT> << Disp ; if ( IncludesDynAlloc ) errs ( ) <<


<s> Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; } unsigned StackID = TargetStackID :: Default ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } assert ( Opc


<s> if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; return


<s> unsigned <ISA_LIT>FastISel :: emitAnd_ri ( MVT RetVT , unsigned LHSReg ,


<s> case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerBUILD_<ISA_LIT>CTOR ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op ,


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = & * std :: next ( MBBI ) ; for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) ,


<s> bool <ISA_LIT>TargetLowering :: shouldLocalize ( const MachineInstr & MI , const TargetTransformInfo * TTI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: G_GLOBAL_VALUE ) { const GlobalValue & GV = * MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( )


<s> for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { unsigned Val = <NUM_LIT> ; SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) != <STR_LIT> ) Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; Mask |=


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Fd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Lane == <NUM_LIT> ) BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Ws , <NUM_LIT> , <STR_LIT> ) ; else { unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT>


<s> return ( MI -> getOpcode ( ) == Opcode && ! MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && MI -> getOperand ( <NUM_LIT> ) .


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return getSubtargetImpl ( ) -> getSelectionDAGInfo (


<s> if ( GET_CODE ( op ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( op ) , 'M'


<s> auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode ,


<s> bool <ISA_LIT>ConstantIslands :: fixupImmediateBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; unsigned TargetOperand = branchTargetOperand (


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Rdm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rdm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else if ( Inst . getOpcode ( ) ==


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine


<s> return ( __m128 ) __builtin_ia32_addss_mask_round ( ( __v4sf ) __A , ( __v4sf ) __B , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 )


<s> ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , JITInfo ( ) { initAsmInfo ( )


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , bool JIT , bool Is64Bit ) { if ( CM )


<s> return ( SYMBOL_REF_P ( base ) && CONSTANT_POOL_ADDRESS_P ( base ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (

get_pool_constant ( base ) , Pmode ) ) ;


<s> if ( SYMBOL_REF_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) ) return <NUM_LIT> ; return


<s> Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ; } AM =


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return


<s> if ( ( RotateAmt % <NUM_LIT> ) == <NUM_LIT> ) return SDValue ( ) ; unsigned ShlAmt = RotateAmt ; unsigned SrlAmt = RotateVT . getScalarSizeInBits ( ) - RotateAmt ; V1 = DAG . getBitcast ( RotateVT , V1 ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , RotateVT , V1 , DAG . getTargetConstant ( ShlAmt , DL , <STR_LIT> ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , RotateVT , V1 , DAG . getTargetConstant ( SrlAmt , DL , <STR_LIT> ) ) ; SDValue Rot = DAG . getNode ( <STR_LIT> , DL , RotateVT , SHL , SRL ) ; return DAG . getBitcast ( VT


<s> Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( Ref -> getKind ( ) == MCSymbolRefExpr :: VK_SECREL ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool IsSubWord = ( BitSize < <NUM_LIT> ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI . getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register BitShift = ( IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ) ; Register NegBitShift = ( IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register NewVal = MRI . createVirtualRegister ( RC ) ; Register RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; Register RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; Register RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg


<s> if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , Align ( <NUM_LIT> ) ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) ) { AFI -> markGlobalAsPromotedToConstantPool ( GVar ) ; AFI -> setPromotedConstpoolIncrease ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> ) ; } ++ NumConstpoolPromoted ; return DAG . getNode ( <STR_LIT> , dl


<s> DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , Op2 ) ) ; return true ; } ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : { if ( EltVT . getSizeInBits ( ) != <NUM_LIT> && EltVT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( VT . isInteger ( ) != Op . getSimpleValueType ( ) . isInteger ( ) ) return false ; return BitcastAndCombineShuffle ( Opcode , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> :


<s> void addRegOperands ( MCInst & Inst ,


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs = <NUM_LIT> ; } return


<s> if ( TT . isOSBinFormatMachO ( ) ) { emitNonLazyStubs ( MMI , * OutStreamer ) ; emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } else if ( TT . isOSBinFormatCOFF ( ) ) { if ( MMI -> usesMSVCFloatingPoint ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; return ; } emitStackMaps ( SM ) ; } else if ( TT . isOSBinFormatELF ( ) ) { emitStackMaps (


<s> unsigned getMaxSVEVectorSizeInBits ( )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode6 ( SDNode * Parent , SDValue N , SDValue & Addr , SDValue & Align ) { Addr = N ; unsigned Alignment = <NUM_LIT> ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( Parent ) ) { unsigned LSNAlign = LSN


<s> } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize ,


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize (


<s> IdxVal -= ( IdxVal / ElemsPerChunk ) * ElemsPerChunk ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; MVT VVT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; MVT VVT = Op . getOperand ( <NUM_LIT> ) .


<s> CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( F , Info . Callee . isReg ( ) , true ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; MIB . addImm ( <NUM_LIT> ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; int FPDiff = <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; if ( ! IsSibCall ) { unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; FPDiff = NumReusableBytes - NumBytes ; assert ( FPDiff % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } const auto & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , true , FPDiff ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; if ( Info . IsVarArg && Info . IsMustTailCall ) { for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use .


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: EmitWinEHHandlerData ( Loc ) ; EHStreamer . EmitUnwindInfo ( * this , getCurrentWinFrameInfo


<s> static SDValue performDivRemCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; unsigned LO = ( Ty == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned HI = ( Ty == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue DivRem = DAG . getNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO


<s> int regno = REGNO ( operands [ <NUM_LIT> ] ) ; regno = ( ( regno - FIRST_VFP_REGNUM ) >> <NUM_LIT> ) ; if ( lane > <NUM_LIT> && lane >= GET_MODE_NUNITS ( mode ) / <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_int_mode ( regno + <NUM_LIT> , constmode


<s> Error ( FnStartLoc , <STR_LIT> ) ; return true ; } FnStartLoc = L ; getTargetStreamer ( ) . emitFnStart ( ) ; return false


<s> temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [


<s> const MachineOperand & MO = Br . getOperand ( I ) ; if ( MO . isMBB ( ) ) return MO . getMBB ( ) ; } llvm_unreachable ( <STR_LIT>


<s> static char * detect_caches_freebsd ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = <NUM_LIT> ; sysctlbyname ( <STR_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; l1_sizekb = <NUM_LIT>


_mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> void addCPURegsAsmOperands ( MCInst & Inst ,


<s> RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: registerMCAdjustCodeGenOpts ( * T , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T ,


<s> unsigned NewOpc = mergedOpcode ( MemInstr -> getOpcode ( ) , AluOffset . isImm ( ) ) ; assert ( AluOpcode != LPAC :: UNKNOWN && <STR_LIT> ) ; assert ( NewOpc != <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder InstrBuilder = BuildMI ( * BB , MemInstr , MemInstr -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; InstrBuilder . addReg ( Dest . getReg ( ) , getDefRegState ( true ) ) ; InstrBuilder . addReg ( Base . getReg ( ) , getKillRegState ( true ) ) ; if ( AluOffset . isReg ( ) ) InstrBuilder . addReg ( AluOffset . getReg ( ) ) ; else if ( AluOffset . isImm ( ) ) InstrBuilder . addImm (


<s> if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) return Error ( IDLoc , <STR_LIT> ) ; break ; case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> || Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> ) return Error ( IDLoc , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . erase ( std :: next ( Inst . begin ( ) ) ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . insert ( std :: next ( Inst . begin ( ) ) , MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . insert ( Inst . end ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( )


<s> vrsqrtss_f32 ( float32_t a , float32_t b ) { float32_t result


<s> MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UserOffset = getUserOffset ( U ) ; int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( )


<s> virtual void EmitValueImpl ( const MCExpr * Value , unsigned Size


<s> Value * <ISA_LIT>IREmitter :: visitPMULUDQ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( ! Worthy ) continue ; Value * TDCFunc = <STR_LIT> ( & M , <STR_LIT> , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I ->


<s> OperandMatchResultTy parseFP128 ( OperandVector &


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > <NUM_LIT> && ninsns <= <NUM_LIT> && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) ) return <NUM_LIT> ; else return


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI


<s> bbs = get_loop_body ( loop ) ; for ( i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn )

) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) {


<s> static unsigned Copy<ISA_LIT>64ByValRegs ( MachineFunction & MF , SDValue Chain , DebugLoc dl , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , const CCValAssign & VA , const <STR_LIT> & Flags , MachineFrameInfo * MFI , bool IsRegLoc , SmallVectorImpl < SDValue > & InVals , <ISA_LIT>FunctionInfo * <ISA_LIT>FI , EVT PtrTy , const Argument * FuncArg ) { const uint16_t * Reg = <ISA_LIT>64IntRegs + <NUM_LIT> ; int FOOffset ; if ( IsRegLoc ) { Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , & <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( FuncArg , I * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OutChains . push_back ( Store )


<s> assert ( Kind == KindAccessReg && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! OffsetIsInRange ( Offset , EndInsertOffset , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { BaseInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; } EndInsertOffset += CPUsers [ CPUIndex ] . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT>


<s> const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getCPUDirective ( ) ; switch ( Directive )


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return Subtarget -> isTargetDarwin ( ) ? LowerGlobalAddressDarwin ( Op , DAG ) : LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op


<s> BundleMI = MI ; continue ; } if ( MI -> isDebugValue ( ) ) continue ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; bool NextInSameBundle = NextMII != E && NextMII -> isBundledWithPred ( ) ; if ( ReduceMI ( MBB , MI , LiveCPSR , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = std :: prev ( NextMII ) ; MI = & * I ; if ( NextInSameBundle && ! NextMII -> isBundledWithPred ( ) ) NextMII -> bundleWithPred ( ) ; } if ( BundleMI && ! NextInSameBundle && MI -> isInsideBundle ( ) ) { if ( BundleMI -> killsRegister ( <STR_LIT> ) ) LiveCPSR = false ; MachineOperand * MO = BundleMI -> findRegisterDefOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isDead ( ) ) LiveCPSR = true ; MO = BundleMI -> findRegisterUseOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isKill ( ) ) LiveCPSR = true ; } bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> isCall ( ) ) { CPSRDef = nullptr


enum machine_mode mode ATTRIBUTE_UNUSED ) {


<s> static SDValue LowerVACOPY ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand


<s> TargetLowering :: CallLoweringInfo CLI ( * CurDAG ) ; CLI . setChain ( CurDAG -> getRoot ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * CurDAG -> getContext ( ) ) , CurDAG -> getExternalSymbol ( <STR_LIT> , TLI -> getPointerTy ( DL ) ) , std :: move ( Args ) , <NUM_LIT> ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; std :: pair < SDValue , SDValue >


<s> while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT>


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32

: \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK2 : \ case TYPE_VK4 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ case TYPE_VK32 : \ case TYPE_VK64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> } if ( pcs_variant != ARM_PCS_AAPCS_LOCAL ) return false ; return ( TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT && ( TARGET_VFP_DOUBLE ||


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfoImpl ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target


<s> RegisterTarget < Triple :: arm , true > X ( getThe<ISA_LIT>LETarget ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget ( ) , <STR_LIT> ,


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA

. getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> ( ( struct u4 * ) ptr ) -> data = data ; return data


<s> int64_t Res ; if ( SD . getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } if ( ! Symbol -> getVariableValue ( ) -> EvaluateAsRelocatable ( Target , & Layout , & Fixup ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; return RecordRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; } if ( Symbol -> isInSection ( ) ) { if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) Base = nullptr ; } if ( Base ) { Index = Base -> getIndex ( ) ; IsExtern = <NUM_LIT> ; if ( Base != & SD ) Value += Layout . getSymbolOffset ( & SD ) - Layout . getSymbolOffset ( Base ) ; } else if ( Symbol -> isInSection ( ) ) { if ( ! Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) && Log2Size != <NUM_LIT> ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; const MCSectionData & SymSD = Asm . getSectionData ( SD . getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; IsExtern = <NUM_LIT> ; Value += Writer -> getSymbolAddress ( & SD , Layout ) ; if ( IsPCRel ) Value -= Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) + ( <NUM_LIT> << Log2Size ) ; } else { if ( SD . getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD . getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; } } if ( ( Type == MachO :: ARM64_RELOC_BRANCH26 || Type == MachO :: ARM64_RELOC_PAGE21 || Type == MachO :: ARM64_RELOC_PAGEOFF12 ) && Value ) { assert ( ( Value & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsExtern << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ) ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; Type = MachO :: ARM64_RELOC_ADDEND ; Index = Value ; IsPCRel = <NUM_LIT> ; Log2Size = <NUM_LIT> ; IsExtern = <NUM_LIT> ; Value = <NUM_LIT> ; } FixedValue = Value ; MachO :: any_relocation_info MRE ; MRE . r_word0


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } else { const MCExpr * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , Inst . getLoc ( ) ) ; Inst . setOpcode ( <STR_LIT> )


<s> static SDValue genConstMult ( SDValue X , APInt C , const SDLoc & DL , EVT VT , EVT ShiftTy , SelectionDAG & DAG ) { if ( C == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( C == <NUM_LIT> ) return X ; if ( C . isPowerOf2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( C . logBase2 ( ) , DL , ShiftTy ) ) ; unsigned BitWidth = C . getBitWidth ( ) ; APInt Floor = APInt ( BitWidth , <NUM_LIT> ) << C . logBase2 ( ) ; APInt Ceil = C . isNegative ( ) ? APInt ( BitWidth , <NUM_LIT> ) : APInt ( BitWidth , <NUM_LIT> ) << C . ceilLogBase2 ( ) ; if ( ( C - Floor ) . ule ( Ceil - C ) ) { SDValue Op0 = genConstMult ( X , Floor , DL ,


<s> word_type i ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ; -- i ) a >>= <NUM_LIT> ; return a


<s> void <ISA_LIT>DAGToDAGISel :: emitFunctionEntryCode ( ) { const Function & F = MF -> getFunction ( ) ; if ( F . hasExternalLinkage ( ) && F . getName ( ) == <STR_LIT>


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > C (


<s> if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) { SDValue S = V . getOperand (


<s> Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Length


<s> if ( Sym ) { if ( Asm . isThumbFunc ( Sym ) ) Value |= <NUM_LIT> ; } } if ( IsResolved && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { assert ( Sym && <STR_LIT> ) ; if ( Sym -> isExternal ( ) || Value >= <NUM_LIT> ) IsResolved = false ; } if ( Sym && Sym -> isELF ( ) ) { unsigned Type = dyn_cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) { if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) IsResolved =


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ? CSR_iOS_ThisReturn_RegMask :


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S , OS )


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : if ( ! TryParseRegisterWithWriteBack ( Operands ) ) return false ; if ( ! TryParseShiftRegister ( Operands ) ) return false ; case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return ParseMemory ( Operands ) ; case AsmToken :: LCurly : return ParseRegisterList ( Operands ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return


<s> case E_V8HImode : gen = gen_avx2_pbroadcastv8hi ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16sf_1 ; break ; case E_V8SFmode : gen = gen_avx2_vec_dupv8sf_1 ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8df_1 ; break ; case E_V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i ] = d -> perm [ i ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0


<s> if ( ! isImm ( ) ) return false ; if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> gen_speculation_check_bi , gen_speculation_check_qi , gen_speculation_check_hi , gen_speculation_check_si , gen_speculation_check_di , gen_speculation_check_sf , gen_speculation_check_df , gen_speculation_check_xf , gen_speculation_check_ti , gen_speculation_check_di , gen_speculation_check_di , gen_speculation_check_di , } ; gen_func_t * gen_check ; if ( ts & BEGIN_DATA ) { if ( simple_check_p ) { gcc_assert ( mflag_sched_spec_ldc ) ; if ( clearing_check_p ) gen_check = gen_ld_c_clr ; else gen_check = gen_ld_c_nc ; } else { if ( clearing_check_p ) gen_check = gen_chk_a_clr ; else gen_check = gen_chk_a_nc ; } } else if ( ts & BEGIN_CONTROL ) { if ( simple_check_p ) { gcc_assert ( ! ia64_needs_block_p ( ts ) ) ; if ( clearing_check_p ) gen_check = gen_ld_c_clr ; else gen_check = gen_ld_c_nc ; } else { gen_check = gen_chk_s ; } } else gcc_unreachable ( ) ; gcc_assert ( mode_no >= <NUM_LIT> ) ; return gen_check [ mode_no


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT>


<s> MVT EVT = MaskVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) if ( i == Idx ) MaskVec . push_back ( DAG . getConstant ( NumElems , EVT ) ) ; else MaskVec . push_back ( DAG .


<s> switch ( GET_MODE_NUNITS ( mode ) ) { case <NUM_LIT> : return V16BImode ; case <NUM_LIT> : return V8BImode ; case <NUM_LIT> : return


<s> if ( ! ConstExpr ) return false ; uint64_t Value = ConstExpr -> getValue ( ) ; return Value < LPCC


<s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState

:: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> Op -> VCC . Val = CC ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) return GOT_None ; const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const MCSymbol & S = Ref -> getSymbol ( ) ; if ( S . getName ( ) != <STR_LIT> ) return GOT_None ; if ( RHS && RHS -> getKind ( )

== MCExpr :: SymbolRef ) return GOT_SymDiff ;


<s> static <ISA_LIT>Operand * CreateCoprocNum ( unsigned CopVal , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_CoprocNum ) ; Op -> Cop .


<s> int TiedOp = MCID . getOperandConstraint ( NextOpIndex , MCOI :: TIED_TO ) ; assert ( TiedOp >= <NUM_LIT> && <STR_LIT> ) ; RegNum = Inst . getOperand ( TiedOp ) . getReg ( ) ; } Inst . addOperand ( MCOperand ::


<s> static void ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl


<s> EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; for ( auto & Reg : Regs ) { Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , Subtarget , DAG ) ; Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , Subtarget , DAG ) ; } for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ; if ( Regs . size ( ) > <NUM_LIT> ) { Regs . resize ( Regs . size ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> static inline bool is_float128_p ( tree t ) { return ( t == float128_type_node || ( t && t == float128t_type_node ) || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t


<s> SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } else { MVT TruncVT = <STR_LIT> ( MaskVT


<s> unsigned getPointerSize ( ) const { StringRef Name = TheTarget . getName ( ) ; if ( Name == <STR_LIT> ) return <NUM_LIT> ; assert ( Name == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> return Subtarget . isABI_N64 ( ) ? & <STR_LIT> : &


<s> default : gcc_unreachable ( ) ; } } if ( y == const0_rtx && REG_P ( x ) && ( code == EQ || code == NE ) && ( GET_MODE ( x ) == HImode || GET_MODE ( x ) == QImode ) ) return CC_NZmode ; if ( ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == DImode ) && y == const0_rtx && ( code == EQ || code == NE || code == LT || code == GE ) && ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == AND || GET_CODE ( x ) == NEG || ( GET_CODE ( x ) == ZERO_EXTRACT && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ) ) return CC_NZmode ; if ( ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == DImode ) && ( REG_P ( y ) || GET_CODE ( y ) == SUBREG ) && ( GET_CODE ( x ) == ASHIFT || GET_CODE ( x ) == ASHIFTRT || GET_CODE ( x ) == LSHIFTRT || GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) ) return CC_SWPmode ; if ( ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == DImode ) && ( REG_P ( y ) || GET_CODE ( y ) == SUBREG ) && ( code == EQ || code == NE ) && GET_CODE ( x ) == NEG ) return CC_Zmode ; if ( ( GET_MODE ( x ) == QImode || GET_MODE ( x ) == HImode ) && y == const0_rtx ) return ( ( code == GT || code == GE || code == LE || code == LT ) ? CC_SESWPmode : CC_ZESWPmode ) ; if ( ( GET_MODE ( x ) == DImode || GET_MODE ( x ) == TImode ) && code == NE && GET_CODE ( x ) == PLUS && GET_CODE ( y ) == ZERO_EXTEND ) return CC_Cmode ; return CCmode


, char __b2 , char __b3 , char __b4 , char __b5 , char __b6 , char __b7 ) {


<s> static Relocator :: Address helper_GOT_ORG ( <ISA_LIT>_64Relocator & pParent ) { return pParent . getTarget ( ) . getGOT ( ) . addr


<s> case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return <NUM_LIT> ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return <NUM_LIT> ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return <NUM_LIT> ; case CPU_POWER8 : return <NUM_LIT> ; case CPU_POWER9 : return <NUM_LIT> ; default : return


<s> return __builtin_mve_vrev32q_m_sv8hi ( __inactive ,


<s> unsigned Imm ; switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 || MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 && <STR_LIT> ( Imm ) < <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MIB -> setDesc ( TII . get ( MinusOne ? <STR_LIT>


DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x =

copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ;


<s> assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > (


<s> bool enableMachineScheduler ( ) const


<s> V1 = Extract128BitVector ( V1 , EltNo , DAG , dl ) ; if ( EltNo >= NumElems / <NUM_LIT> ) EltNo -= NumElems / <NUM_LIT> ; } EVT EltVT = SrcVT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) V1 = PromoteSplati8i16 ( V1 , DAG , EltNo ) ; if ( Is256BitVec ) { V1 = DAG . getNode ( <STR_LIT> ,


<s> mem = recog_data . operand [ <NUM_LIT> ] ; if ( get_attr_speculable1 ( insn ) == SPECULABLE1_YES ) { if ( ! reload_completed ) { if ( ! REG_P ( reg ) || AR_REGNO_P ( REGNO ( reg ) ) ) return - <NUM_LIT> ; if ( ! MEM_P ( mem ) ) return - <NUM_LIT> ; { rtx mem_reg = XEXP ( mem , <NUM_LIT> ) ; if ( ! REG_P ( mem_reg ) ) return - <NUM_LIT> ; } mode_rtx = mem ; } else if ( get_attr_speculable2 ( insn ) == SPECULABLE2_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else return - <NUM_LIT> ; } else if ( get_attr_data_speculative ( insn ) == DATA_SPECULATIVE_YES || get_attr_control_speculative ( insn ) == CONTROL_SPECULATIVE_YES || get_attr_check_load ( insn ) == CHECK_LOAD_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else { enum attr_itanium_class attr_class = get_attr_itanium_class ( insn ) ; if ( attr_class == ITANIUM_CLASS_CHK_A || attr_class == ITANIUM_CLASS_CHK_S_I || attr_class == ITANIUM_CLASS_CHK_S_F ) mode_rtx = reg ; else return - <NUM_LIT> ; } mode_no = ia64_mode_to_int ( GET_MODE (


<s> add_libcall ( libcall_htab , convert_optab_libfunc ( sfloat_optab , SFmode , DImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfloat_optab , DFmode , DImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufloat_optab , SFmode , SImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufloat_optab , DFmode , SImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufloat_optab , SFmode , DImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufloat_optab , DFmode , DImode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sext_optab , SFmode , HFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( trunc_optab , HFmode , SFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , SImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , SImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , DImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , DImode , DFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( sfix_optab , DImode , SFmode ) ) ; add_libcall ( libcall_htab , convert_optab_libfunc ( ufix_optab , DImode , SFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( add_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( sdiv_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc ( smul_optab , DFmode ) ) ; add_libcall ( libcall_htab , optab_libfunc (


<s> BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( CPEBB -> begin ( ) ) ) ; AdjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB ) &&


<s> static uint32_t swapHalfWords ( uint32_t Value , bool IsLittleEndian ) { if ( IsLittleEndian ) { uint32_t Swapped = ( Value &


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst


<s> else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return


<s> setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action


<s> MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: parseVariantKind ( Modifier ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_REFLONG ; return <ISA_LIT>MCExpr :: create ( Kind ,


<s> static AsmPrinter * create<ISA_LIT>AsmPrinterPass ( TargetMachine & tm , MCStreamer & Streamer ) { const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isDarwin ( ) ) return new <ISA_LIT>DarwinAsmPrinter ( tm , Streamer ) ; return new <ISA_LIT>LinuxAsmPrinter ( tm


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( Op , DAG , <STR_LIT> , <STR_LIT> ) ; return getAddrGlobal ( Op , DAG ,


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue Vec = Op0 . getOperand ( <NUM_LIT> ) ; for ( auto * U : Vec -> uses ( ) ) { if ( U != Op0 . getNode ( ) && U -> hasOneUse ( ) && U -> getOpcode ( ) == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) == Vec && U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue OtherRound = SDValue ( * U -> use_begin ( ) , <NUM_LIT> ) ; if ( OtherRound . getOpcode ( ) == N -> getOpcode ( ) && OtherRound . getOperand ( OpNo ) == SDValue ( U , <NUM_LIT> ) && OtherRound . getValueType ( ) == <STR_LIT> ) { SDValue VRound


<s> unsigned add = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; return <NUM_LIT> ; } -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( BytesRemoved ) * BytesRemoved


<s> StringRef getPassName ( ) const override { return


<s> if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this ->

Options . FloatABIType = FloatABI :: Hard ;


<s> if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; else if ( Value > <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ?


<s> MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg (


<s> offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; extra = <NUM_LIT> ; switch ( mode ) { case E_V4HImode : case E_V2SImode : case E_V1DImode : case E_V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case E_DFmode : case E_DDmode : case E_DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case E_TFmode : case E_IFmode : case E_KFmode : case E_TDmode : case E_TImode : case E_PTImode


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = Subtarget . getFrameLowering ( ) -> getFramePointerSaveOffset ( ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex (


<s> return Changed ; } for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) { bool Filled = false ; if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always || ! TII -> getEquivalentCompactForm ( I ) ) { if ( searchBackward ( MBB , * I ) ) { Filled = true ; } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; } } else if ( searchForward ( MBB , I ) ) { Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } continue ; } } if ( ( InMicro<ISA_LIT>Mode || ( STI . has<ISA_LIT>32r6 ( ) && <ISA_LIT>CompactBranchPolicy != CB_Never ) ) && TII -> getEquivalentCompactForm ( I ) ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc ( ) ) ; continue ; } BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , std :: next ( I , <NUM_LIT>


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I )


<s> if ( ! arm_get_set_operands ( producer , consumer , & value , & addr ) ) return <NUM_LIT> ; return reg_overlap_mentioned_p ( value , addr )


<s> SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( ) ; bool is64bit = Subtarget . is<ISA_LIT>64 ( ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( Model == TLSModel :: LocalExec ) { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTEntryHi , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister (


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT ExtractVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned Mull2VectorIdx = VT . getVectorNumElements ( ) / <NUM_LIT> ; SDValue VMullIdx = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue VMull2Idx = DAG . getConstant ( Mull2VectorIdx , DL , <STR_LIT> ) ; SDValue VMullV0 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V0 , VMullIdx ) ; SDValue VMullV1 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V1 , VMullIdx ) ; SDValue VMull2V0 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V0


<s> if ( isRegInFprb ( ValueReg , MRI ) ) { if ( Ty . isScalar ( ) ) { assert ( ( ( TySize == <NUM_LIT> && MemSizeInBytes == <NUM_LIT> ) || ( TySize == <NUM_LIT> && MemSizeInBytes == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( MemSizeInBytes == <NUM_LIT> ) return isStore ? <STR_LIT> : <STR_LIT> ; if ( STI . isFP64bit ( ) ) return isStore ? <STR_LIT> : <STR_LIT> ; return isStore ? <STR_LIT> : <STR_LIT> ; } if ( Ty . isVector ( ) ) { assert ( STI . hasMSA ( ) && <STR_LIT> ) ; assert ( ( TySize == <NUM_LIT> && MemSizeInBytes == <NUM_LIT> ) && <STR_LIT> ) ; switch ( Ty . getElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } } return


<s> if ( ID == <STR_LIT> || ID == <STR_LIT> ) VecTy = dyn_cast < FixedVectorType > ( I -> getType ( ) -> getContainedType ( <NUM_LIT> ) ) ; else VecTy = dyn_cast < FixedVectorType > ( I -> getType ( ) ) ; } else if ( ID == <STR_LIT> ) { VecTy = dyn_cast < FixedVectorType > ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; } else { VecTy = dyn_cast < FixedVectorType > ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; } assert ( VecTy && <STR_LIT> ) ; return VecTy


<s> case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; default : Inst . addOperand ( MCOperand :: CreateReg


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : <NUM_LIT> ) ; if ( ! no_rtl ) { if ( gp_saved > <NUM_LIT> ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > <NUM_LIT> ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE


<s> bool <ISA_LIT>PassConfig :: addPostFastRegAllocRewrite ( ) { addPass ( create<ISA_LIT>FastTileConfigPass ( ) ) ; return true


<s> comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; } last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } for ( i = first ; i <= last ; ++ i


<s> if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_long_type_node ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( type == vector_pair_type_node ) return


<s> for ( df_ref ref = DF_INSN_DEFS ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( ref ) ) ) { df_link * use ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( NONDEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) && ( DF_REF_REG_MEM_P ( use -> ref ) || ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( use -> ref ) ) ) ) break ; if ( use ) convert_reg ( insn , DF_REF_REG ( ref ) , * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) ; else if ( MAY_HAVE_DEBUG_BIND_INSNS ) { auto_vec < rtx_insn * , <NUM_LIT> > to_reset_debug_insns ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( DEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) ) { rtx_insn * debug_insn = DF_REF_INSN ( use -> ref ) ; df_link * def ; for ( def = DF_REF_CHAIN ( use -> ref ) ; def ; def = def -> next ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( def -> ref ) ) ) break ; if ( def ) to_reset_debug_insns . safe_push ( debug_insn ) ; else { * DF_REF_REAL_LOC ( use -> ref ) = * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ; df_insn_rescan ( debug_insn ) ; } } while ( ! to_reset_debug_insns . is_empty ( ) ) { rtx_insn * debug_insn = to_reset_debug_insns . pop ( ) ; INSN_VAR_LOCATION_LOC ( debug_insn ) = gen_rtx_UNKNOWN_VAR_LOC ( ) ; df_insn_rescan_debug_internal ( debug_insn ) ; } } } for ( df_ref ref = DF_INSN_USES ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) if ( rtx

* vreg = defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) {


<s> if ( ix86_force_drap || ( ( cfun -> machine -> outgoing_args_on_stack || crtl -> sp_is_clobbered_by_asm ) && ! ACCUMULATE_OUTGOING_ARGS ) ) crtl -> need_drap = true ; if ( stack_realign_drap ) { unsigned int regno = find_drap_reg ( ) ; rtx drap_vreg ; rtx arg_ptr ; rtx_insn * seq , * insn ; arg_ptr = gen_rtx_REG ( Pmode , regno ) ; crtl -> drap_reg = arg_ptr ; start_sequence ( ) ; drap_vreg = copy_to_reg ( arg_ptr ) ; seq = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_before ( seq , NEXT_INSN ( entry_of_function ( )


<s> unsigned CC = DAG . getMachineFunction ( ) . getFunction ( ) -> getCallingConv ( ) ; bool isVarArg = DAG . getMachineFunction ( ) . getFunction ( ) -> isVarArg ( ) ; CCState CCInfo ( CC , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeReturn ( Op . getNode ( ) , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = Op . getOperand ( realRVLocIdx *


<s> case G_CONSTANT : { int Imm = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) . getLimitedValue ( ) ; unsigned LUiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LUi , * ORi ; LUi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( LUiReg ) . addImm ( Imm >> <NUM_LIT> ) ; ORi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( LUiReg ) . addImm ( Imm & <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * LUi , TII , TRI , RBI ) ) return false ; if ( ! constrainSelectedInstRegOperands ( * ORi , TII , TRI , RBI ) ) return false ; I . eraseFromParent ( ) ; return true ; } case G_GLOBAL_VALUE : { if ( MF . getTarget ( ) . isPositionIndependent ( ) ) return false ; const llvm :: GlobalValue * GVal = I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; unsigned LUiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LUi , * ADDiu ; LUi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef (


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> || LHS . getValueType ( ) != VT ) return SDValue ( ) ; auto * LHSN1 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSN1 = dyn_cast < ConstantSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! LHSN1 || LHSN1 != RHSN1 || ! RHSN1 -> isZero ( ) ) return SDValue ( ) ; SDValue Op1 = LHS -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = RHS -> getOperand ( <NUM_LIT> ) ; EVT OpVT1 = Op1 . getValueType ( ) ; EVT OpVT2 = Op2 . getValueType ( ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || OpVT1 != OpVT2 || Op2 . getOpcode ( ) != <STR_LIT> || OpVT1 . getVectorElementType ( ) != VT ) return SDValue ( ) ; SDValue Val1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Op2 . getOperand ( <NUM_LIT> ) ; EVT ValVT = Val1 -> getValueType ( <NUM_LIT>


<s> static void report_neither_nor ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT


<s> case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_X : if ( ! SelectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2