<s> SDValue StoredVal = Store -> getValue ( ) ; assert ( ( StoredVal . getValueType ( ) . is256BitVector ( ) || StoredVal . getValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; if ( ! Store -> isSimple ( ) ) return SDValue ( ) ; SDLoc DL ( Store ) ; SDValue Value0 , Value1 ; std :: tie ( Value0 , Value1 ) = splitVector ( StoredVal , DAG , DL ) ; unsigned HalfOffset = Value0 . getValueType ( ) . getStoreSize


<s> switch ( code ) { case CONST_INT : if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) < <NUM_LIT> ) * total = <NUM_LIT> ; else if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) < <NUM_LIT> ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case SYMBOL_REF : * total = optimize_size ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : * total = ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ) ; return


<s> return ; case ADDRESS_CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file , x ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , loongarch_strip_unspec_address ( x ) ) ; return ; } if ( CONST_INT_P ( x ) ) output_addr_const ( file , x ) ; else gcc_unreachable (


<s> static void dumpBytes ( const SmallVectorImpl < int > & Bytes , std :: string Msg ) { dbgs ( ) << Msg . c_str


<s> int regs [ <NUM_LIT> ] ; int base_reg ; HOST_WIDE_INT offset ; char buf [ <NUM_LIT> ] ; int i ; switch ( load_multiple_sequence ( operands , nops , regs , & base_reg , & offset ) ) { case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT>


<s> static Constant * SegmentOffset ( IRBuilder < > &

IRB , int Offset , unsigned AddressSpace ) {


<s> } scalar_float_mode mode ; if ( ! CONST_DOUBLE_P ( value ) || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = <NUM_LIT> ; long res [ <NUM_LIT> ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode ==


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI


<s> return <NUM_LIT> ; } assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ; if ( ! FalseBlock


<s> if ( isa < PHINode > ( I -> getArgOperand ( <NUM_LIT> ) ) ) return processPhiNode ( I ) ; SmallVector < Instruction * , <NUM_LIT> > CandidatesForRemoval ; Value * Cursor = I -> getOperand ( <NUM_LIT> ) , * EarliestReplacement = nullptr ; const auto * IVTy = cast < VectorType > ( I -> getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > ( Cursor


<s> static inline bool isBranchRetTrap ( MachineInstr * MI ) { return ( MI -> isBranch ( ) || MI -> isReturn ( ) || MI -> getOpcode (


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Warning ( L ,


<s> case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K

) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ;


<s> if ( Size == <NUM_LIT> ) { const TargetLowering * TLI = MF -> getSubtarget ( ) . getTargetLowering ( ) ; const MCExpr * Base = TLI -> getPICJumpTableRelocBaseExpr ( MF , JTI , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; } else { const MCSymbol * BaseSym = AFI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create


<s> if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) &&

! AM . IncludesDynAlloc ) return false ;


<s> InstructionCost ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; InstructionCost BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } InstructionCost MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; InstructionCost InsertExtractCost = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost ( Instruction :: InsertElement , SrcVTy , i ) ; else for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost (

Instruction :: ExtractElement , SrcVTy , i ) ;


<s> return __builtin_ia32_minsh_mask_round ( __A , __B , _mm_setzero_ph ( ) , (


<s> __inline__ static void sh_media_FMTRXCOPY_S ( const void * mtrxg , void * mtrxf ) { const __GCC_MTRX * g = mtrxg ; __GCC_MTRX * f = mtrxf ; * f =


<s> for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) OriginalArgWasF128 . push_back ( originalTypeIsF128 ( CLI . RetTy , CLI . Callee .


<s> static DecodeStatus DecodeSImm8OptLsl ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { signed Val = ( int8_t ) Imm ; unsigned Shift = ( Imm & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> case CallingConv :: Fast : case CallingConv :: PreserveMost : if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; return IsVarArg ? CC_<ISA_LIT>_DarwinPCS_VarArg


<s> const MCPhysReg * <STR_LIT> ( const MachineFunction


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitINSERT_FD ( MachineInstr * MI , MachineBasicBlock * BB ) const { assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister (


<s> unsigned char OpFlag = Subtarget . classifyLocalReference ( nullptr ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlign ( ) , CP -> getOffset ( ) , OpFlag ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( getGlobalWrapperKind ( ) , DL , PtrVT , Result ) ; if (


<s> void <ISA_LIT>InstrInfo :: insertSelect ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DstReg , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo


<s> if ( d -> name == <NUM_LIT> ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , ( long unsigned ) i ) ; continue ; } if ( gimple_func ) { gcc_assert ( icode == CODE_FOR_nothing ) ; op [ nopnds ++ ] = void_type_node ; icode = d [ <NUM_LIT> ] . icode ; } else { if ( ! ( d -> code == MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL || d -> code == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) && ( attr & RS6000_BTC_QUAD ) == <NUM_LIT> ) attr_args -- ; gcc_assert ( attr_args == insn_data [ icode ] . n_operands - <NUM_LIT> ) ; } if ( d -> code == MMA_BUILTIN_DISASSEMBLE_ACC || d -> code == VSX_BUILTIN_DISASSEMBLE_PAIR ) { op [ nopnds ++ ] = build_pointer_type ( void_type_node ) ; if ( d -> code == MMA_BUILTIN_DISASSEMBLE_ACC ) op [ nopnds ++ ] = build_pointer_type ( vector_quad_type_node ) ; else op [ nopnds ++ ] = build_pointer_type ( vector_pair_type_node ) ; } else { unsigned j = <NUM_LIT> ; if ( attr & RS6000_BTC_QUAD && d -> code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL && d -> code != VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) j = <NUM_LIT> ; for ( ; j < ( unsigned ) insn_data [ icode ] . n_operands ; j ++ ) { machine_mode mode = insn_data [ icode ] . operand [ j ] . mode ; if ( gimple_func && mode == XOmode ) op [ nopnds ++ ] = build_pointer_type ( vector_quad_type_node ) ; else if ( gimple_func && mode == OOmode && d -> code == VSX_BUILTIN_ASSEMBLE_PAIR ) op [ nopnds ++ ] = build_pointer_type ( vector_pair_type_node ) ; else op [ nopnds ++ ] = builtin_mode_to_type [ mode ] [ <NUM_LIT> ] ; } } switch ( nopnds ) { case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT>


<s> e = XVECEXP ( p , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( e ) == SET && MEM_P ( SET_DEST ( e ) ) && REG_P ( SET_SRC ( e ) ) ) ; reg = REGNO ( SET_SRC ( e ) ) ; gcc_assert ( reg >= lastreg ) ; if ( i != <NUM_LIT> ) fprintf ( out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( out_file , <STR_LIT> , reg ) ; if ( flag_checking ) { e = XEXP ( SET_DEST ( e ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) gcc_assert ( REG_P ( XEXP ( e , <NUM_LIT> ) ) && REGNO ( XEXP ( e , <NUM_LIT> ) ) == SP_REGNUM && CONST_INT_P ( XEXP ( e , <NUM_LIT> ) ) && offset == INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) ; else gcc_assert ( i == <NUM_LIT> && REG_P ( e ) && REGNO ( e ) == SP_REGNUM ) ; offset += reg_size ; } } fprintf ( out_file , <STR_LIT> ) ; if ( padfirst ) fprintf ( out_file ,


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; return


<s> if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress ) && ORIGINAL_REGNO ( x ) ==

REGNO ( pic_offset_table_rtx ) ) return true ;


<s> Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: SjLj ; AbsoluteEHSectionOffsets =


<s> static Instruction :: BinaryOps intrinsicIDToBinOpCode ( unsigned Intrinsic ) { switch ( Intrinsic ) { case <STR_LIT> : return Instruction :: BinaryOps :: FMul ; case <STR_LIT> : return Instruction :: BinaryOps :: FAdd ; case <STR_LIT> : return Instruction :: BinaryOps :: FSub ; default : return Instruction :: BinaryOpsEnd


<s> return ( uint32x2_t ) __builtin_neon_vld1v2si ( ( const __builtin_neon_si


<s> if ( OptLevel != CodeGenOpt :: None ) PM . add ( create<ISA_LIT>GlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> if ( ! HasLazyResolverStubs || TM . getRelocationModel ( ) == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration ( ) && ! GV ->


<s> } else { MCInst FMov ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg


<s> case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> :


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return getSubtargetImpl ( ) ->


<s> void <ISA_LIT>ExpandPseudo :: ExpandVTBL ( MachineBasicBlock :: iterator & MBBI , unsigned Opc , bool IsExt , unsigned NumRegs ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) ; unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg (


<s> int64_t Offset = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } getTargetStreamer ( ) . emitSetFP ( static_cast < unsigned > ( NewFPReg ) , static_cast < unsigned > ( NewSPReg ) , Offset ) ; return false


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target , mcld


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned Scratch1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Scratch2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Scratch1 ) .

addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( Reg1 != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI ) ; if ( ! CommutedMI ) return false ; } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 = <NUM_LIT> ; unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc


<s> InEpilogCFI = false ; MCSymbol * Label = S . EmitCFILabel ( ) ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ; CurFrame -> EpilogMap [ CurrentEpilog ] . push_back (


<s> assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( )

< <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;


<s> uint64_t TrueWeight = <NUM_LIT> , FalseWeight = <NUM_LIT> ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( <NUM_LIT> ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } SmallVector < BasicBlock * , <NUM_LIT> > ExitBlocks ; L -> getExitBlocks ( ExitBlocks ) ; for ( auto & BB : ExitBlocks ) { for ( auto & PHI : BB -> phis ( ) ) { for ( int Idx = <NUM_LIT> , EndIdx = PHI . getNumIncomingValues ( ) ; Idx < EndIdx ; Idx ++ ) { const BasicBlock * IncomingBB = PHI . getIncomingBlock ( Idx ) ; const Value * IncomingValue = PHI . getIncomingValue ( Idx ) ; if ( L -> contains ( IncomingBB ) && memAddrUsesCTR ( IncomingValue , TM , Visited ) ) return false ; } } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . is<ISA_LIT>64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , <NUM_LIT> ) ; return true


<s> bool <ISA_LIT>InstructionSelector :: isWorthFoldingIntoExtendedReg ( MachineInstr & MI , const MachineRegisterInfo & MRI ) const { Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . hasOneNonDBGUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasOptSize ( ) ) return true ; if ( ! STI . hasLSLFast ( )


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler

& Mang , const TargetMachine & TM ) const {


<s> static DecodeStatus DecodeVSSRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> if ( mode != SFmode && GET_MODE_CLASS ( mode ) != MODE_INT ) return true ; if ( ! SUBREG_P ( src ) || ! sf_subreg_operand ( src , mode )


<s> return isLegalMaskedLoadStore ( DataType , Alignment


<s> bool Changed = false ; unsigned NumOps = N -> getNumOperands ( ) ; SDLoc dl ( N ) ; SDValue Glue = N -> getGluedNode ( ) ? N -> getOperand ( NumOps - <NUM_LIT> ) : SDValue ( nullptr , <NUM_LIT> ) ; SmallVector < bool , <NUM_LIT> > OpChanged ; for ( unsigned i = <NUM_LIT> , e = N -> getGluedNode ( ) ? NumOps - <NUM_LIT> : NumOps ; i < e ; ++ i ) { SDValue op = N -> getOperand ( i ) ; AsmNodeOperands . push_back ( op ) ; if ( i < InlineAsm :: Op_FirstOperand ) continue ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( i ) ) ) { Flag = C -> getZExtValue ( ) ; Kind = InlineAsm :: getKind ( Flag ) ; } else continue ; if ( Kind == InlineAsm :: Kind_Imm ) { SDValue op = N -> getOperand ( ++ i ) ; AsmNodeOperands . push_back ( op ) ; continue ; } unsigned NumRegs = InlineAsm :: getNumOperandRegisters ( Flag ) ; if ( NumRegs ) OpChanged . push_back ( false ) ; unsigned DefIdx = <NUM_LIT> ; bool IsTiedToChangedOp = false ; if ( Changed && InlineAsm :: isUseOperandTiedToDef ( Flag , DefIdx ) ) IsTiedToChangedOp = OpChanged [ DefIdx ] ; if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ; SDValue V0 = N -> getOperand ( i + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg (


<s> return __ev_mwsmiaa ( t , ( ( __ev64_s32__ ) {


<s> int imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { if ( imm == <NUM_LIT> ) imm = INT32_MIN ; else imm *= - <NUM_LIT> ; } if ( imm != INT32_MIN ) imm


<s> FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getNode ( <STR_LIT> , SDLoc ( V2 ) , <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx


<s> void <ISA_LIT>RegisterSema :: onRegisterGet ( unsigned RegNo ) { if ( RegNo !=


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( Op . getValueType ( ) ) ) return LowerFixedLengthInsertVectorElt ( Op , DAG ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT . getScalarType ( ) == <STR_LIT> ) { EVT VectorVT = getPromotedVTForPredicate ( VT ) ; SDLoc DL ( Op ) ; SDValue ExtendedVector = DAG . getAnyExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , VectorVT ) ; SDValue ExtendedValue = DAG . getAnyExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , VectorVT . getScalarType ( ) . getSizeInBits

( ) < <NUM_LIT> ? <STR_LIT> : VectorVT . getScalarType ( ) ) ;


<s> static DecodeStatus DecodeStoreInt ( MCInst & Inst , unsigned insn ,

uint64_t Address , const void * Decoder ) {


<s> const struct d_target_info_spec handlers [ ] = { { <STR_LIT> , arm_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers )


<s> if ( I == Last ) return false ; RelLsIter Hi = I ++ ; return ( I -> Reloc . Type == ELF :: R_MIPS_LO16 ) && ( Hi -> Sym == I -> Sym


<s> Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I


<s> static void ready_reorder ( rtx_insn * * ready , int nready ) { if ( nready == <NUM_LIT> ) swap_reorder ( ready , nready ) ; else if ( nready > <NUM_LIT> ) qsort ( ready , nready , sizeof ( rtx_insn * )


<s> for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : { uint64_t FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV8 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresFlagSetting : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_1 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_3 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_7 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_31 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_32 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_63 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_ImmRange0_239 : return Error ( ErrorLoc , <STR_LIT> )


<s> } } } else { CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>_SVR4 ) ; } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>_SVR4_ByVal ) ; unsigned NumBytes = CCByValInfo . getNextStackOffset ( ) ; int SPDiff = CalculateTailCallSPDiff ( DAG , isTailCall , NumBytes ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) ) ; SDValue CallSeqStart = Chain ; SDValue LROp , FPOp ; Chain = EmitTailCallLoadFPAndRetAddr ( DAG , SPDiff , Chain , LROp , FPOp , false , dl ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < TailCallArgumentInfo , <NUM_LIT> > TailCallArguments ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; bool seenFloatArg = false ; for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg


<s> rtx tmp = crx_expand_compare ( code , VOIDmode ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF


<s> return ( __m512d ) __builtin_ia32_rcp28pd_mask ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( ) , (


<s> auto ceil = [ ] ( unsigned A , unsigned B ) { return ( A + B - <NUM_LIT> ) / B ; } ; unsigned NumElts = cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) ; assert ( Factor > <NUM_LIT> && NumElts % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned VF = NumElts / Factor ; unsigned NumEltsPerVecReg = ( <NUM_LIT> / getScalarSizeInBits ( VecTy ) ) ; unsigned NumVectorMemOps = getNumVectorRegs ( VecTy ) ; unsigned NumPermutes = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) { BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector


<s> bool isHigh = ! MRI . isLowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! MRI . isLowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >=


<s> SDNode * In128 = DAG . getMachineNode ( Extend , DL , <STR_LIT> , Op0 ) ; SDValue Result = DAG . getNode ( Opcode , DL , <STR_LIT> , SDValue ( In128 , <NUM_LIT> ) , Op1 ) ; bool Is32Bit = is32Bit ( VT ) ; SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT>


<s> bool ComplexPatternFuncMutatesDAG ( ) const override


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( IN_NAMED_SECTION ( decl ) ) return get_named_section ( decl , NULL , reloc ) ; } if ( decl_readonly_section ( decl , reloc ) ) { if ( TREE_PUBLIC ( decl ) ) return read_only_data_section ; else return read_only_private_data_section ; } else { if ( TREE_CODE ( decl ) == VAR_DECL && DECL_THREAD_LOCAL_P ( decl ) ) { if ( TREE_PUBLIC ( decl ) ) return tls_data_section ; else if ( bss_initializer_p ( decl ) ) { DECL_COMMON ( decl )


<s> if ( ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks ( ) == <NUM_LIT> ) return TTI :: AMK_PreIndexed ; return TTI


<s> for ( auto & MO : MI -> operands ( ) ) { const MCOperand MCOp =


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( RestoreMBB ) ; MI . getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB ) ; auto RestoreMBBI = RestoreMBB -> begin ( ) ; BuildMI ( * RestoreMBB , RestoreMBBI , DL , TII . get ( <STR_LIT> ) ) ; BuildMI ( * RestoreMBB , RestoreMBBI , DL , TII .

get ( <STR_LIT> ) ) . addMBB ( TargetMBB ) ;


<s> MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT>


<s> rtx tmp ; gcc_assert ( reload_completed ) ; if ( GET_MODE_SIZE ( GET_MODE ( dest ) ) < <NUM_LIT> ) dest = gen_rtx_REG ( SImode , REGNO ( dest ) ) ; tmp = gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ; if ( reload_completed && ( ! TARGET_USE_MOV0


<s> SDValue SizeNode = DAG . getIntPtrConstant ( Flags . getByValSize ( ) , dl ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , true ,

false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> rtx new_addr = NULL ; gcc_assert ( CONST_INT_P ( element_offset ) ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) ; rtx op1 = XEXP ( addr , <NUM_LIT> ) ; if ( CONST_INT_P ( op1 ) ) { HOST_WIDE_INT offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) + INTVAL ( element_offset ) ; if ( offset == <NUM_LIT> ) new_addr = op0 ; else { rtx plus = gen_rtx_PLUS ( Pmode , op0 , GEN_INT ( offset ) ) ; new_addr = gen_rtx_CONST ( Pmode


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiti ( ( __builtin_neon_ti )


<s> static unsigned selectSelectOpc ( MachineInstr & I , MachineRegisterInfo & MRI , const RegisterBankInfo & RBI ) { const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; bool IsFP = ( RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) -> getID ( ) != <STR_LIT> ) ; LLT Ty = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) return IsFP ? <STR_LIT> : <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) || Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) return


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> static bool isWorthFoldingADDlow ( SDValue N ) { for ( auto Use : N -> uses ( ) ) { if ( Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> ) return false ; if ( cast < MemSDNode > ( Use ) ->

getOrdering ( ) > Monotonic ) return false ;


<s> } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT>


<s> rtx tmp = crx_expand_compare ( code , GET_MODE ( dest ) ) ; emit_move_insn ( dest ,


<s> break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MCOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ++ ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp + <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> SDValue <ISA_LIT>TargetLowering :: lowerLog10 ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case


<s> int arith_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == CONST_INT && SMALL_INT ( op ) ) return <NUM_LIT> ; return register_operand ( op ,


<s> rtx symbol ; int flags ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl ,


<s> rtx_insn * insn ; sparc_leaf_function_p = optimize > <NUM_LIT> && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > <NUM_LIT> ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed


<s> tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size = cfun -> va_list_gpr_size ; int vr_save_area_size = cfun -> va_list_fpr_size ; int vr_offset ; cum = & crtl -> args . info ; if ( cfun -> va_list_gpr_size ) gr_save_area_size = MIN ( ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD , cfun -> va_list_gpr_size ) ; if ( cfun -> va_list_fpr_size ) vr_save_area_size = MIN ( ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG , cfun -> va_list_fpr_size ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( cum -> aapcs_nvrn == <NUM_LIT> ) ; vr_save_area_size = <NUM_LIT> ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist ,


<s> ASSERT_EQ ( UNSPEC , GET_CODE ( src ) ) ; ASSERT_EQ ( BLKmode , GET_MODE ( src ) ) ; ASSERT_EQ ( UNSPEC_MEMORY_BLOCKAGE , XINT ( src , <NUM_LIT> ) ) ; rtx v0 = XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) ; rtx scratch_a = XEXP ( dst , <NUM_LIT> ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_a ) ) ; rtx scratch_b = XEXP ( v0 , <NUM_LIT> ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_b ) ) ; ASSERT_EQ ( scratch_a , scratch_b ) ; ASSERT_TRUE ( rtx_equal_p ( dst , v0 ) ) ; ASSERT_NE ( - <NUM_LIT> , recog_memoized ( insn ) ) ; insn = NEXT_INSN ( insn ) ; ASSERT_EQ ( INSN , GET_CODE ( insn ) ) ; set = single_set ( insn ) ; ASSERT_NE ( NULL , set ) ; src = SET_SRC ( set ) ; ASSERT_EQ ( UNSPEC_VOLATILE , GET_CODE ( src ) ) ; ASSERT_EQ ( UNSPECV_RDTSCP , XINT ( src


<s> if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) &&

TT . isThumb ( ) ) OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ;


<s> MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( auto I = std :: next ( MBB . rbegin ( ) ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) { ConditionDef = & * I ; break ; } if ( I -> readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn

( <STR_LIT> ) ) SingleUseCondition = false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> if ( TT . isOSBinFormatMachO ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI ) ; return createELFObjectWriter ( MOTW , OS , true


<s> if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL


<s> static DecodeStatus DecodeDTripleRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT>


<s> MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MI -> getOperand ( i ) , MCOp , AP , isDarwin


<s> SDValue Src1Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src1 ) ; SDValue Src1Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Src1Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src1Hi ) ; SDValue Src2 = Op . getOperand ( <NUM_LIT> ) ; SDValue Src2Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src2 ) ; SDValue Src2Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src2 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Src2Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src2Hi ) ; bool hasChain = false ; unsigned hiOpc = Op . getOpcode ( ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; } SDValue


<s> bool OptimizePICCall :: isCallViaRegister ( MachineInstr & MI , unsigned & Reg , ValueType & Val ) const { if ( ! MI . isCall ( ) ) return false ; MachineOperand * MO = getCallTargetRegOpnd ( MI ) ; if ( ! MO ) return false ; Reg = MO -> getReg ( ) ; Val = ( Value * ) nullptr ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = MRI . getVRegDef ( Reg ) ; assert ( DefMI ) ; if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI -> hasOneMemOperand ( ) ) ; Val = ( * DefMI -> memoperands_begin ( ) ) -> getValue ( ) ; if ( ! Val ) Val = ( * DefMI -> memoperands_begin ( ) ) -> getPseudoValue ( ) ; return


<s> Metadata * FineIBT = MMI . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( FineIBT ) { Changed |= applyFineIBT ( MF ) ; FixICalls ( MF ) ; FixDCalls ( MF ) ; } else { Changed |= applyCoarseIBT ( MF ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB .


<s> unsigned Opc ; if ( SetNZCV ) Opc = isSub ? <STR_LIT> : <STR_LIT> ; else Opc = isSub ? <STR_LIT> : <STR_LIT> ; const unsigned MaxEncoding = <NUM_LIT> ; const unsigned ShiftSize = <NUM_LIT> ; const unsigned MaxEncodableValue = MaxEncoding << ShiftSize ; while ( ( ( unsigned ) Offset ) >= ( <NUM_LIT> << ShiftSize ) ) { unsigned ThisVal ; if ( ( ( unsigned ) Offset ) > MaxEncodableValue ) { ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) .

addImm ( Offset ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlag ( Flag ) ;


<s> if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos ,


<s> return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ,


<s> if ( scalar ) { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRwithZRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , predicate_decoder ( Inst , fc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: LCurly ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; const MCExpr * Expr ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) >


<s> const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> needsStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB )


<s> static rtx mips_unspec_address_offset ( rtx base , rtx offset , enum mips_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode


<s> if ( isLegalAVL ( AVL ) ) return AVL ; return getNode ( <STR_LIT> , AVL . getValueType ( )


<s> void addRegQBRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> >


<s> unsigned int encoded_nelts = d -> perm . encoding ( ) . encoded_nelts ( ) ; for ( unsigned int i = <NUM_LIT> ; i < encoded_nelts ; ++ i ) if ( ! d -> perm [ i ] . is_constant ( ) ) return false ; if ( d -> testing_p ) return true ; if ( vmode != V8QImode && vmode != V16QImode ) return false ; unsigned int nelt = d -> perm . length ( ) . to_constant ( ) ; for ( unsigned int i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( BYTES_BIG_ENDIAN ? d -> perm [ i ] . to_constant ( ) ^ ( nelt - <NUM_LIT> ) : d -> perm [ i ] . to_constant ( ) ) ; sel = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; sel = force_reg (


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue <ISA_LIT>CC ; SDValue Flag = EmitCmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) Opc = IsN64 ?


<s> enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn )

) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ;


<s>
const
char
*
for_string
=
<STR_LIT>
;
const
char
*
for_decimal
=
<STR_LIT>
;
const
char
*
to_close
=
;
count_string
=
<NUM_LIT>
;
for
(
i
=
<NUM_LIT>
;
i
<
n
;
i
++
)
{
c
=
*
p
++
;
if
(
c
>=
' '
&&
c
<
<NUM_LIT>
)
{
if
(
for_string
)
fputs
(
for_string
,
file
)
;
putc
(
c
,
file
)
;
if
(
c
==
'"'
)
{
putc
(
c
,
file
)
;
++
count_string
;
}
for_string
=
;
for_decimal
=
<STR_LIT>
;
to_close
=
<STR_LIT>
;
++
count_string
;
if
(
count_string
>=
<NUM_LIT>
)
{
fputs
(
to_close
,
file
)
;
for_string
=
<STR_LIT>
;
for_decimal
=
<STR_LIT>
;
to_close
=
;
count_string
=
<NUM_LIT>
;
}
}
else
{
if
(
for_decimal
)
fputs
(
for_decimal
,
file
)
;
fprintf
(
file
,
<STR_LIT>
,
c
)
;
for_string
=
<STR_LIT>
;
for_decimal
=
<STR_LIT>
;
to_close
=
<STR_LIT>
;
count_string
=


<s> return ABI . IsN64 ( ) ? <STR_LIT> :


<s> unsigned getPointerSize ( ) const { return <NUM_LIT>


<s> EVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) ,


<s> Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , Flag ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ; SDValue Ops1 [ <NUM_LIT> ] = { Chain . getValue (


<s> SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT>


<s> if ( isSlotPreAllocated ( MFI , ST . FI ) ) continue ; Register RetagReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( RetagReg ) ) continue ; int Score = <NUM_LIT> ; SmallVector < Register , <NUM_LIT> > WorkList ; WorkList . push_back ( RetagReg ) ; while ( ! WorkList . empty ( ) ) { Register UseReg = WorkList . pop_back_val ( ) ; for ( auto & UseI : MRI -> use_instructions ( UseReg ) ) { unsigned Opcode = UseI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) continue ; if ( UseI . isCopy ( ) ) { Register DstReg = UseI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( DstReg ) ) WorkList . push_back ( DstReg ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ST . FI << <STR_LIT> << ST . Tag << <STR_LIT> << Register :: virtReg2Index ( UseReg ) << <STR_LIT> << UseI << <STR_LIT> ) ; Score ++ ; } } int TotalScore = RetagScore [ ST ] += Score ; if ( TotalScore > MaxScore || ( TotalScore == MaxScore && ST . FI > MaxScoreST . FI ) ) { MaxScore = TotalScore ; MaxScoreST = ST ; } } if ( MaxScoreST . FI < <NUM_LIT> ) return None ; if ( MaxScoreST . Tag == <NUM_LIT> ) return MaxScoreST . FI ; SlotWithTag SwapST { - <NUM_LIT> , - <NUM_LIT> } ; for ( auto * I : ReTags ) { SlotWithTag ST { * I } ; if ( ST .


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue TgtBA = DAG . getBlockAddress ( BA , PtrVT , true ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> static unsigned HOST_WIDE_INT sparc_asan_shadow_offset (


<s> return <NUM_LIT> ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : return <NUM_LIT> ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return <NUM_LIT> ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case


<s> llvm :: copy ( Mask , RMask . begin ( ) ) ; } else { C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( A != C ) { std :: swap ( C , D ) ; ShuffleVectorSDNode :: commuteMask ( RMask ) ; } if ( ! ( A == C && B == D ) ) return false ; unsigned Num128BitChunks = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumEltsPer128BitChunk = NumElts / Num128BitChunks ; assert ( ( NumEltsPer128BitChunk % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != NumElts ; j += NumEltsPer128BitChunk ) { for ( unsigned i = <NUM_LIT> ; i != NumEltsPer128BitChunk ; ++ i ) { int LIdx = LMask [ i + j ] , RIdx = RMask [ i + j ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; unsigned NumEltsPer64BitChunk = NumEltsPer128BitChunk


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftExtFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> } for ( ; RegMaskStartIdx < MI . getNumOperands ( ) ; ++ RegMaskStartIdx ) OriginalCall -> addOperand ( MI . getOperand ( RegMaskStartIdx ) ) ; auto * Marker = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) -> moveCallSiteInfo ( & MI


<s> union { _Float16 _Complex a ; float b ; } u = { . a = __A } ; return ( __m512h ) _mm512_set1_ps ( u .


<s> } x ; x . s [ <NUM_LIT> ] = s ; return ( x . q


<s> unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo ,


<s> assert ( ( SubMode == ia || SubMode ==


<s> SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M


<s> } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == <NUM_LIT> && ( gregno & <NUM_LIT> ) == <NUM_LIT> ) gregno += <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + <NUM_LIT> ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 , r2 )


<s> __attribute__ ( ( __always_inline__ ) ) vreinterpret_f64_s8 (


<s> return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> , DL ) , Align (

Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> ) , false , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> case ELF :: R_<ISA_LIT>_GOT16 : return true ; case ELF :: R_<ISA_LIT>_HI16 : case ELF :: R_<ISA_LIT>_LO16 : case ELF :: R_<ISA_LIT>_32 : return true ; case ELF :: R_<ISA_LIT>_GPREL16 : return false


<s> if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode ->


<s> Subtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI )

Changed |= runOnMachineBasicBlock ( * FI ) ;


<s> <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ; if ( ! Hash && getLexer ( ) . isNot ( AsmToken ::


<s> case E_HImode : gen = gen_aarch64_load_exclusivehi ; break ; case E_SImode : gen = gen_aarch64_load_exclusivesi ; break ; case E_DImode : gen = gen_aarch64_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem


<s> MachineInstr * MI = & * MBBI ; unsigned FirstOpnd , NumRegs ; if ( ! isNEONMultiRegOp ( MI -> getOpcode ( ) , FirstOpnd , NumRegs ) ) continue ; MachineBasicBlock :: iterator NextI = next ( MBBI ) ; for ( unsigned R = <NUM_LIT> ; R < NumRegs ; ++ R ) { MachineOperand & MO = MI -> getOperand ( FirstOpnd + R ) ; assert ( MO . isReg ( ) && MO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned VirtReg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( VirtReg ) && <STR_LIT> ) ; static const unsigned NEONDRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; MO . setReg ( NEONDRegs [ R ] ) ; if ( MO . isUse ( ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MO . getReg ( ) ) . addReg ( VirtReg ) ) ; if ( MO . isKill ( ) ) { MachineInstr * CopyMI = prior ( MBBI ) ; CopyMI -> findRegisterUseOperand ( VirtReg ) -> setIsKill ( ) ; } MO . setIsKill ( )


<s> static bool ix86_warn_func_return ( tree decl ) { return ! ix86_function_naked ( decl


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_<ISA_LIT>_AAVPCS_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere

( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ;


<s> if ( Val . ValTy != Query . Types [ <NUM_LIT> ] ) continue ; if ( Val . PtrTy != Query . Types [ <NUM_LIT> ] ) continue ; if ( Val . MemSize != Query . MMODescrs [ <NUM_LIT> ] . SizeInBits ) continue ; if ( Val . MustBeNaturallyAligned && Query . MMODescrs [ <NUM_LIT> ] . SizeInBits % Query . MMODescrs [ <NUM_LIT> ] . AlignInBits != <NUM_LIT> ) continue ; return true ; } return false


<s> static rtx gen_safe_SET64 ( rtx dest , HOST_WIDE_INT val ) { return gen_rtx_SET ( dest , GEN_INT


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectStoreLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return St


<s> if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . ParseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc ,


<s> static inline unsigned getImm3 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> unsigned int i , mask = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == <NUM_LIT> ) return mask ; for ( i = cfun -> args_info . vregno - <NUM_LIT> ; i >= ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> void printtbytemem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo , O


<s> } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize )

<= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ;


<s> bool Valid ; StringRef Name ( SysReg . Data , SysReg . Length ) ; uint32_t Bits = <STR_LIT> ( ) .


<s> __inline__ static void sh_media_STLO_Q ( void * p , int


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Subtarget -> isTargetILP32 ( ) ) break ; Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand (


<s> if ( pred ) rws_sum [ regno ] . write_count ++ ; else rws_sum [ regno ] . write_count = <NUM_LIT> ; rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and


<s> return CreateReg ( Index , RegKind_MSACtrl , RegInfo ,


<s> bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( RegInfo -> requiresRegisterScavenging ( MF ) ) if ( needsFP ( MF ) || spillsCR ( MF ) ) { const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = is<ISA_LIT>64 ?


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( ! isBrAnalysisUnpredicatedTerminator ( I , * this ) ) break ; if ( ! I -> getDesc ( ) . isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) .


<s> if ( slot == NULL ) return false ; entry = ( struct mips_lo_sum_offset * ) * slot ; if ( option == INSERT ) { if ( entry == NULL ) { entry = XNEW ( struct mips_lo_sum_offset ) ; entry -> base = base ; entry -> offset = INTVAL ( offset ) ; * slot = entry ; } else { if ( INTVAL ( offset ) > entry -> offset ) entry -> offset


<s> Bytes = - Bytes ; Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; } emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , Bytes , Opc , TII , Flag , NeedsWinCFI , HasWinCFI ) ; SrcReg = DestReg ; } assert ( ! ( SetNZCV && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr ) ; SrcReg = DestReg


<s> bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'e' && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 's' ) { if ( NoCPU )


<s> bool <ISA_LIT>TargetLowering :: IsTailCallConvention ( CallingConv :: ID CallCC


<s> return __builtin_mve_vmlasq_n_uv16qi ( __a ,


<s> compute_frame_size ( get_frame_size ( ) ) ; if ( ( from ) == FRAME_POINTER_REGNUM ) ( offset ) = <NUM_LIT> ; else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) ) ( offset ) = <NUM_LIT> ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - ( POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != <NUM_LIT> ) ) ; } return


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IdLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } default : break ; } llvm_unreachable ( <STR_LIT>


<s> return ParseMemOperand ( Op ) ; case AsmToken :: Register : return ParseRegister ( Op ) ; case AsmToken :: Dollar : { getLexer ( ) . Lex ( ) ; MCValue Val ; if ( getParser ( ) . ParseRelocatableExpression ( Val ) ) return true ; Op = <STR_LIT> ( Val ) ; return


<s> } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parse<ISA_LIT>AsmOperand ( <ISA_LIT>Operand * & Op , bool isCall ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal ; Op = nullptr ; switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( )


<s> EVT ResVT = ( Opcode == <STR_LIT> ) ? <STR_LIT> : SrcVT . getVectorElementType ( ) ; EVT RdxVT = SrcVT ; if ( SrcVT . isFixedLengthVector ( ) || Opcode == <STR_LIT> ) RdxVT = getPackedSVEVectorVT ( ResVT ) ; SDValue Pg = getPredicateForVector ( DAG , DL , SrcVT ) ; SDValue Rdx = DAG . getNode ( Opcode , DL , RdxVT , Pg , VecOp ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , ResVT , Rdx , DAG

. getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> static bool DisassembleN2RegFrm ( MCInst & MI , unsigned Opc , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded


<s> if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) { Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; return false ; } FeatureBitset ToggleFeatures = EnableFeature ? ( ~ STI . getFeatureBits ( ) & Extension . Features ) : ( STI . getFeatureBits ( ) & Extension . Features ) ; uint64_t Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; return false ; } Error ( ExtLoc , <STR_LIT> +


<s> df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use ,


<s> MCFixupKind Kind ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return


<s> bool <ISA_LIT>LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * >


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return


<s> unsigned int num_of_st = <NUM_LIT> ; for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( STACK_REGNO_P ( regno ) || MMX_REGNO_P ( regno ) ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { num_of_st ++ ; break ; } if ( num_of_st == <NUM_LIT> ) return false ; bool return_with_x87 = false ; return_with_x87 = ( crtl -> return_rtx && ( STACK_REG_P ( crtl -> return_rtx ) ) ) ; bool complex_return = false ; complex_return = ( crtl -> return_rtx && COMPLEX_MODE_P ( GET_MODE ( crtl -> return_rtx ) ) ) ; if ( return_with_x87 ) if ( complex_return ) num_of_st = <NUM_LIT> ; else num_of_st = <NUM_LIT> ; else num_of_st = <NUM_LIT> ; rtx st_reg = gen_rtx_REG ( XFmode , FIRST_STACK_REG ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg , st_reg )


<s> static unsigned GetFunctionSizeInBytes ( const MachineFunction & MF , const <ISA_LIT>BaseInstrInfo & TII ) { unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . GetInstSizeInBytes (


<s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . FeatureBits = FeatureBits ; Op -> StartLoc


<s> bool hasZeroCycleZeroingFP ( ) const { return


<s> SDNode * LD = N -> getOperand ( LoadIdx ) . getNode ( ) ; if ( LD -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( LoadSDN -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ; SDValue NewResults [


<s> static DecodeStatus DecodeGPRnopcRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT>


<s> Register VReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; while ( DefMI -> isCopy ( ) ) { Register CopyVReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( CopyVReg ) ) return false ; if ( ! MRI -> hasOneDef ( CopyVReg ) ) return false ; DefMI = MRI -> getVRegDef ( CopyVReg ) ; } switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { if ( IsTestAndBranch ) return false ; if ( DefMI -> getParent ( ) != MBB ) return false ; if ( ! MRI -> hasOneNonDBGUse ( VReg ) ) return false ; bool Is32Bit = ( DefMI -> getOpcode ( ) == <STR_LIT> ) ; uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; Register NewReg = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MO . setIsKill ( false ) ; if ( ! Is32Bit && Imm < <NUM_LIT> ) NewMI -> getOperand ( <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return <NUM_LIT>


<s> } const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRR ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset ) { if ( N . getOpcode ( ) != <STR_LIT> ) { ConstantSDNode * NC = dyn_cast < ConstantSDNode >


<s> if ( Subtarget . isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding (


<s> return __builtin_mve_vrshrq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> else if ( FP_REGNUM_P ( regno ) ) return AARCH64_DWARF_V0 + regno - V0_REGNUM ; else if ( PR_REGNUM_P ( regno ) ) return AARCH64_DWARF_P0 + regno - P0_REGNUM ; else if ( regno == VG_REGNUM ) return


<s> unsigned encoding ; const MCOperand op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( op1 . isReg ( ) && <STR_LIT> ) ; encoding = ( get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) << <NUM_LIT> ) ; MCOperand op2 = MI . getOperand (


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && isGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isData ( ) && isGlobalInSmallSection ( GV , TM ,


<s> assert ( mInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; MachineOperand & destOper = mInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; int numArgs = mInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & mInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; int valArgIndx = lastAddrIndx + <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( t1 ) ; MIB . addReg ( t2 ) ; unsigned t3 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( cmovOpc ) , t3 ) ; MIB . addReg ( t2 ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MIB . addReg ( t3 ) ; assert ( mInstr -> hasOneMemOperand ( ) && <STR_LIT> ) ; ( * MIB ) . setMemRefs ( mInstr -> memoperands_begin ( ) , mInstr -> memoperands_end ( ) ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , destOper . getReg ( ) ) ; MIB . addReg ( <STR_LIT> ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB (


<s> void addUImm4Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> <ISA_LIT>CallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; return TFI -> hasFP ( MF ) ? Regs ->

getFramePointerRegister ( ) : Regs -> getStackPointerRegister ( ) ;


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU ,


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> return Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith

( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ;


( __v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc ==


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O


<s> LandingPadInst * LP = nullptr ; for ( BasicBlock & BB : F ) { LP = BB . getLandingPadInst ( ) ; if ( LP ) break ; } if ( ! LP ) return false ; PersonalityFn = dyn_cast < Function > ( LP -> getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isMSVCEHPersonality ( Personality ) ) return false ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMIPtr = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; assert ( MMIPtr && <STR_LIT> )


<s> if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; unsigned NumOriginalElts = OriginalVT . getVectorNumElements ( ) ; InVec = peekThroughOneUseBitcasts ( InVec ) ; EVT CurrentVT = InVec . getValueType ( ) ; if ( ! CurrentVT . isVector ( ) ) return SDValue ( ) ; unsigned NumCurrentElts = CurrentVT . getVectorNumElements ( ) ; if ( ( NumOriginalElts % NumCurrentElts ) != <NUM_LIT> ) return SDValue ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , true , ShuffleOps , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned Scale = NumOriginalElts / NumCurrentElts ; if ( Scale > <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ScaledMask ; scaleShuffleMask < int > ( Scale , ShuffleMask , ScaledMask ) ; ShuffleMask = std :: move ( ScaledMask ) ; } assert ( ShuffleMask . size ( ) == NumOriginalElts && <STR_LIT> ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumOriginalElts ) ? SM_SentinelUndef : ShuffleMask [ Elt ] ; if ( Idx == SM_SentinelZero ) return EltVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , EltVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , EltVT ) ; if ( Idx == SM_SentinelUndef ) return DAG . getUNDEF ( EltVT ) ; if ( llvm :: any_of ( ShuffleMask , [ ] ( int M ) { return M == SM_SentinelZero ; } ) ) return SDValue ( ) ; assert ( <NUM_LIT> <= Idx && Idx < ( int ) ( <NUM_LIT> * NumOriginalElts ) && <STR_LIT> ) ; SDValue LdNode = ( Idx < ( int ) NumOriginalElts ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; unsigned AllowedUses = ( ShuffleOps . size ( ) > <NUM_LIT> && ShuffleOps [ <NUM_LIT> ] == ShuffleOps [ <NUM_LIT> ] ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue