<s> } assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace (


<s> MCAsmBackend * llvm :: createThumbLEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { return create<ISA_LIT>AsmBackend ( T , MRI ,


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI ) { MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser (


<s> if ( Bytes <= <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT>

) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> const MCExpr * Value ; if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma )


<s> break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; auto V = ( MO . getImm ( ) <= <NUM_LIT> ) ? <NUM_LIT> : MO . getImm ( ) ; return V - <NUM_LIT>


<s> return Kind == Memory && ( ! Mem . Size || Mem . Size


<s> if ( ! IsEffectivelyImm13 ) { MCInst TmpInst ; const MCExpr * Expr = adjustPICRelocation ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , ValExpr ) ; TmpInst . setLoc ( IDLoc ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCRegOp ) ; TmpInst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; Instructions . push_back ( TmpInst ) ; PrevReg = MCRegOp ; } if ( ! IsImm || IsEffectivelyImm13 || ( ImmValue & <NUM_LIT> ) ) { MCInst TmpInst ; const MCExpr * Expr ; if ( IsEffectivelyImm13 ) Expr = ValExpr ; else Expr = adjustPICRelocation ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , ValExpr ) ; TmpInst . setLoc


<s> OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; emitNops ( NoopsInSledCount ) ; OutStreamer -> emitLabel ( Target


<s> Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi ,


<s> return ( __m512 ) __builtin_ia32_expandloadsf512_maskz ( ( const __v16sf * ) __P , ( __v16sf ) _mm512_setzero_ps ( ) , (


<s> unsigned Value = CE -> getValue ( ) ; if ( Value >= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | <NUM_LIT> ; else Value |= <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> if ( REG_P ( op ) ) regnum = REGNO ( op ) ; else if ( GET_CODE ( op ) == PLUS && REG_P ( XEXP ( op , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( op ,

<NUM_LIT> ) ) ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ;


<s> Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI . setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI . setObjectSExt ( FI , true ) ; } if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI . setObjectOffset ( FI , Offset ) ; } SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; FIN . getNode ( ) -> sgx_type = sgx_type ? <NUM_LIT> : <NUM_LIT> ; SDValue Val = DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG .

getMachineFunction ( ) , FI ) , <NUM_LIT> , MMOFlags ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op ) ) . first ; } return Op


<s> if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = <NUM_LIT> ; cost += inline_memory_move_cost ( mode , class1 , <NUM_LIT> ) ; cost += inline_memory_move_cost ( mode , class2 , <NUM_LIT> ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += <NUM_LIT> ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += <NUM_LIT> ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return MAX ( <NUM_LIT> , MMX_CLASS_P ( class1 ) || MMX_CLASS_P ( class2 ) ? ix86_cost -> mmxsse_to_integer : ix86_cost -> ssemmx_to_integer ) ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P (


<s> static DecodeStatus DecodeShiftRight8Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> SmallSet < unsigned , <NUM_LIT> > KilledRegs ; DenseMap < unsigned , unsigned > Killer ; for ( unsigned i = <NUM_LIT> , e = memOps . size ( ) ; i != e ; ++ i ) { if ( i == memOpsBegin ) { i = memOpsEnd ; if ( i == e ) break ; } if ( memOps [ i ] . Position < insertPos && memOps [ i ] . isKill ) { unsigned Reg = memOps [ i ] . Reg ; KilledRegs . insert ( Reg ) ; Killer [ Reg ] = i ; } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; SmallVector < unsigned , <NUM_LIT> > ImpDefs ; SmallVector < MachineOperand * , <NUM_LIT> > UsesOfImpDefs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( MIOperands MO ( memOps [ i ] . MBBI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) || ! MO -> isImplicit ( ) || MO -> isDead ( ) ) continue ; unsigned DefReg = MO -> getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; findUsesOfImpDef ( UsesOfImpDefs , memOps , DefReg , memOps [ i ] . Position , insertPos ) ; } } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs , ImpDefs ) ) return ; Merges . push_back ( std :: prev ( Loc ) ) ; for ( SmallVectorImpl < MachineOperand * > :: iterator I = UsesOfImpDefs . begin ( ) , E = UsesOfImpDefs . end ( ) ; I != E ; ++ I ) ( * I ) -> setIsUndef ( ) ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { if ( Regs [ i - memOpsBegin ] .


<s> SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ; } MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg


<s> return __builtin_aarch64_uqshrn_nv8hi_uus ( __a ,


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> Mask . resize ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != ( int ) NumElts ; ++ i ) { Mask [ i ] = i ; if ( UndefElts [ i ] || ( ! IsBLENDV && EltBits [ i ] . isZero ( ) ) || ( IsBLENDV && EltBits

[ i ] . isNonNegative ( ) ) ) Mask [ i ] += NumElts ;


<s> MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) .


<s> label_ref_list_t ref , newref ; for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , <NUM_LIT> ) != XINT ( pool_vector [ i ] . value , <NUM_LIT> ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = <NUM_LIT> ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - <NUM_LIT> ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = ( label_ref_list_t ) pool_alloc ( label_ref_list_pool ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend =


<s> if ( ! isShiftedImm ( ) && ( ! isImm ( ) || ! isa < MCConstantExpr > ( getImm ( ) ) ) ) return DiagnosticPredicateTy :: NoMatch ; bool IsByte = std :: is_same < int8_t , std :: make_signed_t < T


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; } else { ++ Result ; } if ( ! Shift ) return


<s> break ; default : { if ( InCPMode && AFI -> isThumbFunction ( ) ) InCPMode = false ; } } printInstruction (


<s> static DecodeStatus DecodeFPR128_loRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t

Addr , const MCDisassembler * Decoder ) {


<s> void <ISA_LIT>InstPrinter :: printMemRiOperand ( const MCInst * MI , int OpNo , raw_ostream & OS , const char * Modifier ) { const MCOperand & RegOp = MI


<s> if ( ! isSingleSpacedVectorIndexed ( )


<s> if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr


<s> LPR . addLiveOuts ( MBB ) ; for ( MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; std :: bitset < <NUM_LIT> > Defs ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; MachineInstr & MI = * I ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) - <STR_LIT> ; if ( Reg >= <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) { Defs . set ( Reg


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl


<s> assert ( static_cast < size_t > ( cpu_arch ) < ( sizeof ( generic_cpu_name_table ) / sizeof ( generic_cpu_name_table [ <NUM_LIT> ] ) ) ) ; return generic_cpu_name_table [ cpu_arch


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return ! isDirectCall && ( GV -> hasLocalLinkage ( ) || GV


<s> if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) && ! ( TARGET_SHCOMPACT && ( ( crtl -> args . info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) || crtl -> saves_all_registers ) ) ) x = hard_reg ; else x = gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } else x = NULL_RTX ; return x


<s> Inst . addOperand ( MCOperand :: CreateReg ( getFCCReg (


<s> if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += <NUM_LIT> * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor


<s> void addImm0_508s4NegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr


<s> void mmix_asm_output_def ( FILE * stream , const char * name , const char * value ) { assemble_name ( stream , name ) ; fprintf ( stream ,


<s> unsigned NumOperands = MI . getNumOperands ( ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) )

|| ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ;


<s> case <NUM_LIT> : case <NUM_LIT> : { EABase eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> : insn -> displacementSize = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <NUM_LIT> : insn -> eaDisplacement = ( mod == <NUM_LIT> ? EA_DISP_8 : EA_DISP_32 ) ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = EA_BASE_sib ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm + evexrm ) ; break ; } break ; } } return <NUM_LIT>


<s> return BuildVec -> getSplatValue ( ) ; } return SDValue (


<s> return ( __m128i ) __builtin_ia32_pmovusdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_undefined_si128 ( ) ,


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { assert ( Encoding == DW_EH_PE_absptr && <STR_LIT> ) ; Triple T ( MMI -> getModule ( ) -> getTargetTriple ( ) ) ; if ( T . isOSNaCl ( ) ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV


<s> if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) { SmallVector < SDValue


<s> bool HasFP = false ; uint32_t CompactUnwindEncoding = <NUM_LIT> ; unsigned SubtractInstrIdx = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned InstrOffset = <NUM_LIT> ; unsigned StackAdjust = <NUM_LIT> ; unsigned StackSize = <NUM_LIT> ; unsigned PrevStackSize = <NUM_LIT> ; unsigned NumDefCFAOffsets = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Instrs . size ( ) ; i != e ; ++ i ) { const MCCFIInstruction & Inst = Instrs [ i ] ; switch ( Inst . getOperation ( ) ) { default : return <NUM_LIT> ; case MCCFIInstruction :: OpDefCfaRegister : { HasFP = true ; assert ( MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) == ( Is64Bit ? <STR_LIT> : <STR_LIT> ) && <STR_LIT> ) ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; StackAdjust = <NUM_LIT> ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { PrevStackSize = StackSize ; StackSize = std :: abs ( Inst . getOffset ( ) ) / StackDivide ; ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU ::


<s> Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Type * Ty = Input -> getType ( ) ; if ( ! ( Ty -> getVectorNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { Ptr , Builder . getInt32


<s> int half_elts = GET_MODE_NUNITS ( GET_MODE ( XEXP ( sel , <NUM_LIT> ) ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) ; lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn


<s> if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE ->


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg


) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ;


<s> if ( ! STI . hasE2 ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasHighRegisters ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved )


<s> GlobalAddressSDNode * GlobalAddr = cast < GlobalAddressSDNode > ( Op . getNode ( ) ) ; SDValue TargetAddr = DAG . getTargetGlobalAddress ( GlobalAddr -> getGlobal ( ) , Op ,


<s> static DecodeStatus DecodeQQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg


<s> static DecodeStatus DecodeFPR128LoRegisterClass ( llvm :: MCInst & Inst , unsigned

RegNo , uint64_t Address , const void * Decoder ) {


<s> unsigned getT2AddrModeImm8OffsetOpValue ( const MachineInstr & MI , unsigned


<s> void <ISA_LIT>MCCodeEmitter :: emitSegmentOverridePrefix ( unsigned SegOperand , const MCInst & MI ,


<s> bool <ISA_LIT>AsmParser :: requestsDoubleOperand ( StringRef Mnemonic ) { bool IsDouble = StringSwitch < bool > ( Mnemonic . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Default ( false ) ; return


<s> case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFNEGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTRUNCATECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performFMinNumFMaxNumCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI


<s> switch ( CM ) { default : break ; case CodeModel :: Default : CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; break ; case CodeModel :: JITDefault : CM = CodeModel


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetMsa ( ) ; return


<s> SDValue BitcastVector = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue BitcastLoad = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue InsVecElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BitcastVector , BitcastLoad , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( <STR_LIT> , InsVecElt ) ; } } if ( Subtarget . isISA3_1 ( ) ) { if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; } if ( ! C ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue Mtvsrz = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned InsertAtElement = C -> getZExtValue ( ) ; unsigned InsertAtByte = InsertAtElement * BytesInEachElement ; if ( Subtarget . isLittleEndian ( )


<s> return ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved <


<s> Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getRegister (


<s> } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT != <STR_LIT>


<s> if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } return false


<s> if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetInsertSubreg ( <STR_LIT> , DL , VT , getUNDEF ( DL , <STR_LIT> ) , N ) ; if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , DL , VT , N ) ; assert ( N . getValueType ( ) ==


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; auto * Idx = dyn_cast < ConstantSDNode > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Idx ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( ! SrcOpMap . empty ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt EltCount = APInt :: getZero ( NumElts


<s> std :: unique_ptr < DCFunction > <ISA_LIT>DCTranslator :: createDCFunction ( DCModule & DCM , const MCFunction


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT ResVT = Op . getValueType ( ) ; assert ( ResVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue V1 = Op . getOperand (


<s> if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( can_create_pseudo_p ( ) ) ) ) { base = loongarch_force_temporary ( dest , base ) ; loongarch_emit_move ( dest , loongarch_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; loongarch_emit_move ( dest , src


<s> bool <ISA_LIT>ElimCompare :: convertToLoadAndTrap ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned LATOpcode = TII -> getLoadAndTrap ( MI . getOpcode ( ) ) ; if ( ! LATOpcode ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( LATOpcode ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return


<s> } bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } assert ( WidenedMask . size ( ) == <NUM_LIT> ) ; bool IsInsert = true ; int V2Index = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i ] < <NUM_LIT> ) continue ; if ( WidenedMask [ i ] < <NUM_LIT> ) { if ( WidenedMask [ i ] != i ) { IsInsert = false ; break ; } } else { if ( V2Index >= <NUM_LIT> || WidenedMask [ i ] != <NUM_LIT> ) { IsInsert = false ; break ; } V2Index = i ; } } if ( IsInsert && V2Index >= <NUM_LIT> ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue Subvec = DAG . getNode ( <STR_LIT> , DL , SubVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return insert128BitVector ( V1 , Subvec , V2Index * <NUM_LIT> , DAG , DL ) ; } SDValue Ops [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; unsigned PermMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i ]


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup >

& Fixups , const MCSubtargetInfo & STI ) const {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveNext ( SMLoc L ) { getTargetStreamer ( ) . EmitARM64WinCFISaveNext ( ) ; return


<s> return false ; } if ( needsLowering ) { uint64_t UnscaledOffset = Addr . getOffset ( ) * ScaleFactor ; unsigned ResultReg = FastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . getReg ( ) , false , UnscaledOffset , <STR_LIT> ) ; if ( ResultReg == <NUM_LIT> ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffset ( <NUM_LIT> ) ; } return true


<s> } EVT IdiomVT = Op . getValueType ( ) ; if ( isPackedVectorType ( IdiomVT ) && ! supportsPackedMode ( Op . getOpcode ( ) , IdiomVT ) ) return splitVectorOp ( Op


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTblNoPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTblNoPairWise [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( IsPairwise ) { if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTblPairWise , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTblPairWise , ISD , MTy


<s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; X -> initMCCodeGenInfo ( RM , CM


<s> return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case


<s> case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , false , false , true ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetInstrInfo :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT>


<s> else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) { if ( ! TT . isOSFuchsia ( ) ) report_fatal_error ( <STR_LIT> ) ; else if ( CM != CodeModel :: Kernel ) report_fatal_error


<s> static unsigned copyPhysRegOpcode_AVX512 ( unsigned & DestReg , unsigned & SrcReg ) { if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <STR_LIT> ) ; return <STR_LIT> ; } if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && MaskRegClassContains ( SrcReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <STR_LIT>


<s> void addMemTBHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( Revert ) { if ( Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( Start ) ; else Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( Dec , true ) ; RevertLoopEnd ( End , FlagsAlreadySet ) ; } else { Start = ExpandLoopStart ( ML , Start , InsertPt ) ; RemoveDeadBranch ( Start ) ; End = ExpandLoopEnd ( ML , Dec


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SecondReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ThirdReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( has<ISA_LIT>1 ( ) && ! has<ISA_LIT>2 ( ) ) { unsigned ATReg = getATReg ( IDLoc


<s> else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v8_1a : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7em : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7s : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6t2 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6k : <ISA_LIT>ArchFeature =


<s> ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( MEM_P ( x ) && MEM_VOLATILE_P ( x ) ) return <NUM_LIT> ; return xstormy16_below100_operand ( x ,


<s> vec_const_128bit_type vsx_const ; if ( TARGET_POWER10 && vec_const_128bit_to_bytes ( vec , mode , & vsx_const ) ) { unsigned imm = constant_generates_lxvkq ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } imm = constant_generates_xxspltiw ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } imm = constant_generates_xxspltidp ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } } if ( TARGET_P9_VECTOR && xxspltib_constant_p ( vec , mode , & num_insns , & xxspltib_value ) ) { if ( num_insns == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( xxspltib_value & <NUM_LIT> ) ; return <STR_LIT> ; } return <STR_LIT> ; } } if ( TARGET_ALTIVEC ) { rtx splat_vec


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> if ( FlagUseZeroBasedSandbox ) { Inst -> getOperand ( IndexOpPosition ) . setReg ( DemoteRegTo32_ ( IndexReg ) ) ; }


<s> SDLoc dl ( Op ) ; if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ; nextOffset +=


<s> bool isPostIdxImm8 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val ==


<s> SDValue Dot = N -> getOperand ( <NUM_LIT> ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; auto isZeroDot = [ ] ( SDValue Dot ) { return ( Dot . getOpcode ( ) == <STR_LIT> || Dot . getOpcode ( ) == <STR_LIT> ) && isZerosVector ( Dot . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; if ( ! isZeroDot ( Dot ) ) std :: swap ( Dot , A ) ; if ( ! isZeroDot ( Dot ) ) return SDValue


<s> return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SetVector < Instruction * > Predicates ; DenseMap < Instruction * , Instruction * > NewPredicates ; for ( auto * I : MaskedInsts ) { <STR_LIT> ID = I -> getIntrinsicID ( ) ; unsigned PredOp = ID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * Predicate = dyn_cast < Instruction > ( I -> getArgOperand ( PredOp ) ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; VectorType * VecTy = getVectorType ( I ) ; Value * NumElements = ComputeElements ( TripCount , VecTy ) ; if ( ! NumElements ) continue ; if ( ! isTailPredicate ( Predicate , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; Predicates . insert ( Predicate ) ; InsertVCTPIntrinsic ( Predicate , NewPredicates , VecTy ,


<s> static MCSymbol * getPICLabel ( StringRef Prefix , unsigned FunctionNumber , unsigned LabelId ,


<s> addPass ( createAtomicExpandPass ( ) )


<s> int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type ) mode = type_natural_mode ( arg . type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , arg . type , words , arg . named ) ; } else nregs = function_arg_advance_32 ( cum , mode , arg . type , bytes , words ) ; if ( !


<s> static __inline __m64 _mm_setzero_si64 ( void ) { return __builtin_ia32_mmx_zero (


<s> return Ty1 -> isIntegerTy ( <NUM_LIT> ) && Ty2 -> isIntegerTy ( <NUM_LIT>


<s> if ( ! Subtarget -> isThumb ( ) ) return <STR_LIT> ( AbsImm ) != - <NUM_LIT> ; if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> (


<s> return ( __m128i ) __builtin_ia32_pabsq128_mask ( ( __v2di ) __A , ( __v2di )

_mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; bool isTailCall = isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) ; if ( isTailCall ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , false , false , false , false , <NUM_LIT> , getLibcallCallingConv ( Call ) , isTailCall , false , true , Callee , Args , DAG , Op -> getDebugLoc ( ) ) ; std :: pair < SDValue , SDValue > CallInfo


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } if ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && RelaxedOp == <STR_LIT> ) { Res . setOpcode (


<s> OS << <STR_LIT> << Opcode << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } if ( isPostIncrementForm ( MI , AddOffset ) ) { OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } return


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo


<s> return ( int8x8_t ) __builtin_neon_vcreatev8qi ( (


<s> NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Neg = MIB . buildInstr ( NegOpc , { RC } , { Src2Reg } ) ; constrainSelectedInstRegOperands ( * Neg , TII , TRI , RBI ) ; auto SShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Neg } ) ; constrainSelectedInstRegOperands ( * SShl , TII


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return


<s> return ( __m128i ) __builtin_ia32_paddusb128 ( ( __v16qi ) __A ,


<s> assert ( <STR_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Scale = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Index = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Disp = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Segment = MI -> getOperand ( <NUM_LIT> ) ; unsigned ArgSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ArgMode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Align = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( MI -> hasOneMemOperand ( ) && <STR_LIT> ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; const TargetInstrInfo * TII = MBB -> getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * AddrRegClass = getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * OffsetRegClass = getRegClassFor ( <STR_LIT> ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned TotalNumIntRegs = <NUM_LIT> ; unsigned TotalNumXMMRegs = <NUM_LIT> ; bool UseGPOffset = ( ArgMode == <NUM_LIT> ) ; bool UseFPOffset = ( ArgMode == <NUM_LIT> ) ; unsigned MaxOffset = TotalNumIntRegs * <NUM_LIT> + ( UseFPOffset ? TotalNumXMMRegs * <NUM_LIT> : <NUM_LIT> ) ; unsigned ArgSizeA8 = ( ArgSize + <NUM_LIT> ) & ~ <NUM_LIT> ; bool NeedsAlign = ( Align > <NUM_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * overflowMBB ; MachineBasicBlock * offsetMBB ; MachineBasicBlock * endMBB ; unsigned OffsetDestReg = <NUM_LIT> ; unsigned OverflowDestReg = <NUM_LIT> ; unsigned OffsetReg = <NUM_LIT> ; if ( ! UseGPOffset && ! UseFPOffset ) { OffsetDestReg = <NUM_LIT> ; OverflowDestReg = DestReg ; offsetMBB = nullptr ; overflowMBB = thisMBB ; endMBB = thisMBB ; } else { OffsetDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; OverflowDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction * MF = MBB ->


<s> uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( ConstantSDNode * Op2 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Value = - Op2 -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || isInt < <NUM_LIT> > ( Value ) ) { SDValue Ops [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( int32_t ( Value ) , VT ) } ; Node = CurDAG -> MorphNodeTo ( Node , <STR_LIT> , Node -> getVTList ( ) , Ops , array_lengthof ( Ops ) ) ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } } if ( ! ResNode ) ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == NULL || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump ( CurDAG ) ; errs ( ) << <STR_LIT>


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT>

) , DPRCSFrames ( <NUM_LIT> ) , SpilledCSRegs ( MF . getTarget ( ) . getRegisterInfo ( ) -> getNumRegs ( ) ) , JumpTableUId ( <NUM_LIT> ) , ConstPoolEntryUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) {


<s> rtx saved_rp ; rtx ins ; HOST_WIDE_INT insns [ <NUM_LIT> ] ; int i , len ; if ( count != <NUM_LIT> ) return NULL_RTX ; rp = get_hard_reg_initial_val ( Pmode , <NUM_LIT> ) ; if ( TARGET_64BIT || TARGET_NO_SPACE_REGS ) return rp ; saved_rp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( saved_rp , rp ) ; ins = copy_to_reg ( gen_rtx_AND ( Pmode , rp , MASK_RETURN_ADDR ) ) ; label = gen_label_rtx ( ) ; if ( TARGET_PA_20 ) { insns [ <NUM_LIT> ] =


<s> if ( ! MFI . isMaxCallFrameSizeComputed ( ) ) MFI .


<s> offset += size ; if ( ACCUMULATE_OUTGOING_ARGS && ( ! current_function_is_leaf || current_function_calls_alloca ) ) { offset += current_function_outgoing_args_size ; frame -> outgoing_arguments_size = current_function_outgoing_args_size ; } else frame -> outgoing_arguments_size = <NUM_LIT> ; if ( ! current_function_is_leaf || current_function_calls_alloca ) frame -> padding2 = ( ( offset + preferred_alignment - <NUM_LIT> ) & - preferred_alignment ) - offset ; else frame -> padding2 = <NUM_LIT> ; offset += frame -> padding2 ; frame -> stack_pointer_offset = offset ; frame -> to_allocate = ( size + frame -> padding1 + frame -> padding2 + frame -> outgoing_arguments_size + frame -> va_arg_size ) ; if ( ( ! frame -> to_allocate && frame -> nregs <= <NUM_LIT> ) || ( TARGET_64BIT && frame -> to_allocate >= ( HOST_WIDE_INT ) <NUM_LIT> ) ) frame -> save_regs_using_mov = false ; if ( TARGET_RED_ZONE && current_function_sp_is_unchanging && current_function_is_leaf ) { frame -> red_zone_size = frame -> to_allocate ; if ( frame -> save_regs_using_mov ) frame -> red_zone_size += frame -> nregs * UNITS_PER_WORD ; if ( frame -> red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE ) frame -> red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE ; } else frame -> red_zone_size = <NUM_LIT> ; frame -> to_allocate -= frame -> red_zone_size ; frame -> stack_pointer_offset -= frame -> red_zone_size ; fprintf ( stderr , <STR_LIT> , frame -> nregs ) ; fprintf ( stderr , <STR_LIT> , size ) ; fprintf ( stderr , <STR_LIT> , stack_alignment_needed ) ; fprintf ( stderr , <STR_LIT> , frame -> padding1 ) ; fprintf ( stderr , <STR_LIT> , frame -> va_arg_size ) ; fprintf ( stderr , <STR_LIT> , frame -> padding2 ) ; fprintf ( stderr , <STR_LIT> , frame -> to_allocate ) ; fprintf ( stderr , <STR_LIT> , frame -> red_zone_size ) ; fprintf ( stderr , <STR_LIT> ,


<s> void \ sdata2_section ( void ) \ { \ if ( in_section != in_sdata2 ) \ { \ in_section = in_sdata2 ; \ fprintf ( asm_out_file

, <STR_LIT> , SDATA2_SECTION_ASM_OP ) ; \ } \ }


<s> static int sh_contains_memref_p_1 ( rtx * loc


<s> static bool needsFP ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( )


ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) {


<s> return true ; case R8 : case R9 : case R10 : case R11 : case R12 : return ! isIOS ; default : return


<s> void <ISA_LIT>ELFStreamer :: emitHandlerData ( ) { FlushUnwindOpcodes ( false )


<s> <ISA_LIT>elTargetMachine ( const Module & M , const std :: string &


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm


<s> if ( ! MI . mayLoadOrStore ( ) ) return false ; unsigned XFormOpcode = RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) ; assert ( ( XFormOpcode != <STR_LIT> ) && <STR_LIT> ) ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! instrHasImmForm ( XFormOpcode , IsVFReg , III , PostRA ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setReg ( RegMO -> getReg ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setIsKill ( RegMO -> isKill ( ) ) ; MI . getOperand ( III . ImmOpNo )


<s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT>


<s> return Create ( VK_AARCH64_DTPREL_G0_NC ,


<s> return ( uint32x4_t ) __builtin_aarch64_lbtruncuv4sfv4si


<s> static __inline qword si_selb ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_sel ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b


<s> if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <NUM_LIT> , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( Opc , DL , DAG . getVTList ( <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm (


<s> std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( STI


<s> USItype hi , lo ; hi = a / ( ( ( UDItype ) <NUM_LIT> ) <<


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags

. getByValAlign ( ) , false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Code == <NUM_LIT> ) O << <STR_LIT> ; else if ( Code == <NUM_LIT> ) O


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else


<s> static <ISA_LIT>Operand * CreateProcIFlags ( <STR_LIT> IFlags , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( ProcIFlags ) ; Op -> IFlags . Val = IFlags ; Op -> StartLoc


<s> else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; return orig ; } if ( reg == <NUM_LIT>


<s> for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; unsigned Qn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Qn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Qm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Qd


<s> AsmToken :: TokenKind kind = getLexer ( ) . getKind ( ) ; switch ( kind ) { default : return true ; case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . parseExpression ( EVal )


<s> return create<ISA_LIT>MachObjectWriter ( OS , false , MachO :: CPU_TYPE_<ISA_LIT>


<s> OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode


<s> if ( auto * ConstAVL = dyn_cast < ConstantSDNode > ( AVL ) ) { LegalAVL = CDAG . getConstant ( ( ConstAVL -> getZExtValue ( ) + <NUM_LIT> ) / <NUM_LIT> , <STR_LIT> ) ; } else { auto ConstOne = CDAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; auto PlusOne = CDAG . getNode ( <STR_LIT> , <STR_LIT> , { AVL , ConstOne } ) ; LegalAVL = CDAG . getNode ( <STR_LIT> , <STR_LIT> , { PlusOne , ConstOne } ) ; } } SDValue AnnotatedLegalAVL = CDAG .


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ]


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned opc [ <NUM_LIT> ] ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned Reg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( IsIntegerCC ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { if ( TRI -> getRegSizeInBits ( Reg , MRI ) == <NUM_LIT> ) { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } else { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } }


<s> const TargetFrameLowering * TFI = MF . getTarget (


<s> Chain = ( depth || AlwaysFlush ) ? getFLUSHW ( Op , DAG ) : DAG . getEntryNode ( ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? ( stackBias + <NUM_LIT> ) : <NUM_LIT> ; while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegFixed


<s> return Reg == <STR_LIT> ? Reg : get<ISA_LIT>SubSuperRegister ( Reg


<s> rtx or1k_dynamic_chain_addr ( rtx frame ) { return plus_constant ( Pmode , frame ,


<s> return getTargetMachine ( ) . isPositionIndependent


<s> unsigned RegNum = isVector ? matchVectorRegName ( Name ) : MatchRegisterName ( Name ) ; RegKind Kind = isVector ? RegKind :: NeonVector : RegKind :: Scalar ; if ( RegNum == <NUM_LIT> ) RegNum = matchReqRegisterNameAlias ( Name ,


<s> uint8_t OpFlagHi = IsPIC ? <STR_LIT> : <STR_LIT> ; uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; if ( IsPIC ) Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , getGlobalReg ( DAG , <STR_LIT> ) ) ; return Result


<s> SchedModel . init ( * ST . getSchedModel ( ) , & ST , TII ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF -> getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : * MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; unsigned Offset ; if ( TII -> getLdStBaseRegImmOfs ( & MI ,


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; Register StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl ,


<s> unsigned <ISA_LIT>ABIInfo :: GetStackPtr ( ) const { return <STR_LIT>


<s> x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , <NUM_LIT> , <NUM_LIT> ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( SImode , sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg )


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( errs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB ,


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; DebugLoc DL ; determineFrameLayout ( MF


<s> static int getCompactUnwindRegNum ( const uint16_t * CURegs , unsigned Reg ) { for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return -


<s> for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , UnpackedVT , Regs [ i ] ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum / <NUM_LIT> ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , PackedVT , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ; } if ( OutVT == <STR_LIT> ) { Regs [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , PackedVT , Regs [ <NUM_LIT> ] , Regs [ <NUM_LIT> ] ) ; Regs [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , OutVT , Regs [ <NUM_LIT> ] , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return Regs [ <NUM_LIT> ] ; } else if ( RegNum > <NUM_LIT> ) { Regs . resize ( RegNum ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> gcc_assert ( ! TEST_HARD_REG_BIT ( rws_insn , regno )


<s> static bool isUnalignedLoadStore ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> raw_svector_ostream VecOS ( Code ) ; Emitter . encodeInstruction ( Relaxed , VecOS , Fixups , * RF . getSubtargetInfo ( ) ) ; const unsigned OldSize = RF . getContents ( ) . size ( ) ; const unsigned NewSize = Code . size ( ) ; assert ( NewSize >= OldSize && <STR_LIT> ) ; unsigned Delta = NewSize - OldSize ; if ( Delta > RemainingSize ) return false


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm & <NUM_LIT> ) ==


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X ( getThe<ISA_LIT>Target

( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> } uint64_t AlignMask = ( uint64_t ( <NUM_LIT> ) << Block . LogAlignment ) - <NUM_LIT> ; Position . Address = ( Position . Address + AlignMask ) & ~ AlignMask ; Block . Address =


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; DebugLoc DL


<s> static void report_not_enum ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual , tree enumtype ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno


<s> bool isFeatureMFTB ( ) const { return FeatureMFTB


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum )


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , St


<s> enum insn_code icode = d -> icode ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat


<s> return ( __m256i ) __builtin_ia32_pternlogq256_maskz ( ( __v4di ) __A , ( __v4di ) __B , (


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( Base || Index || Length ) Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return false


<s> bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; MachineInstr :: MIFlag Flag = isSub ? MachineInstr :: FrameSetup : MachineInstr :: FrameDestroy ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; unsigned Rax = ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; if ( isSub && ! isEAXLiveIn ( MBB ) ) Reg = Rax ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; unsigned MovRIOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned AddSubRROpc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; if ( Reg ) { BuildMI ( MBB , MBBI , DL , TII . get ( MovRIOpc ) , Reg ) . addImm ( Offset ) . setMIFlag ( Flag ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AddSubRROpc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } else if ( Offset > <NUM_LIT>


<s> assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS (


<s> if ( FiOpc != <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; MIBundleBuilder Bundle ( BB , I ) ; unsigned MalkrzOpc = TII . getMalkrzFromFiMalkrz ( Opc ) ; unsigned MalkrzNumOperands = TII . get ( MalkrzOpc ) . getNumOperands ( ) ; MachineInstrBuilder Malkrz = BuildMI ( F , DL , TII . get ( MalkrzOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < MalkrzNumOperands ; i ++ ) { Malkrz . add ( MI . getOperand ( i ) ) ; } Bundle . prepend ( Malkrz ) ; unsigned FiNumOperands = TII . get ( FiOpc ) . getNumOperands ( ) ; MachineInstrBuilder Fi = BuildMI ( F , DL , TII . get ( FiOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < FiNumOperands ; i ++ ) { Fi . add ( MI . getOperand ( i + MalkrzNumOperands ) ) ; } Bundle . prepend ( Fi )


<s> void <ISA_LIT>InstPrinter :: printCondCode ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm


<s> return parseAddress ( Operands , BDRMem


<s> else if ( fpr_size ) offset = - ( int ) ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD - ( int ) ( GP_ARG_NUM_REG * reg_size ) ; if ( gpr_size + fpr_size ) { rtx reg_save_area = assign_stack_local ( BLKmode , gpr_size + fpr_size , <NUM_LIT> ) ; gcc_assert ( MEM_P ( reg_save_area ) ) ; reg_save_area = XEXP ( reg_save_area , <NUM_LIT> ) ; if ( GET_CODE ( reg_save_area ) == PLUS ) { gcc_assert ( XEXP ( reg_save_area , <NUM_LIT> ) == virtual_stack_vars_rtx ) ; gcc_assert ( CONST_INT_P ( XEXP ( reg_save_area , <NUM_LIT> ) ) ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset = offset ; save_area = plus_constant ( Pmode , virtual_stack_vars_rtx , offset ) ; } } else { first_reg_offset = next_cum . words ; save_area = crtl -> args . internal_arg_pointer ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && targetm . calls . must_pass_in_stack ( arg ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( arg . type ) , arg . type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area ,


<s> int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FirstShift = <STR_LIT> ; unsigned SecondShift = <STR_LIT> ; if ( has<ISA_LIT>32r2 ( ) ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) { uint64_t MaxShift = <NUM_LIT> ; uint64_t ShiftValue = ImmValue ; if ( ImmValue != <NUM_LIT> ) ShiftValue = MaxShift - ImmValue ; TOut . emitRRI ( <STR_LIT> , DReg , SReg , ShiftValue , Inst . getLoc ( ) , STI ) ; return false ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , ImmValue , Inst . getLoc ( ) , STI ) ; return false ; } return true ; } if ( has<ISA_LIT>32 ( ) ) { if ( ImmValue == <NUM_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , <NUM_LIT> , Inst . getLoc ( ) , STI ) ; return false ; } switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; case <STR_LIT>


<s> } uint64_t SEHStackAllocAmt = NumBytes ; if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , true ) ; -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( Terminator == MBB . end ( ) || ! isTailCallOpcode ( Terminator -> getOpcode ( ) ) ) { int Offset = - <NUM_LIT> * <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; assert ( Offset >= <NUM_LIT>


<s> if ( MI -> hasOrderedMemoryRef ( ) ) return false ; if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; MachineBasicBlock :: iterator StoreI


<s> unsigned <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT>


<s> switch ( OldOpcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> return ( __mmask64 ) __builtin_ia32_kxordi ( ( __mmask64 ) __A , (


<s> <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) { if ( getRelocationModel ( ) ==


<s> static unsigned computeBasePointerSaveOffset ( const <ISA_LIT>Subtarget & STI ) { if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64 ( ) ? -


<s> SEOp = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Dest = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask2 = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftAmnt = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BinOpRes = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB . getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB . getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( I ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loopMBB , BranchProbability :: getOne ( ) ) ; loopMBB -> addSuccessor ( sinkMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> normalizeSuccProbs ( ) ; BuildMI ( loopMBB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( IsNand ) { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( <STR_LIT> ) . addReg ( BinOpRes ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else if ( ! IsSwap ) { BuildMI ( loopMBB , DL , TII -> get ( Opcode ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) ,

BinOpRes ) . addReg ( Incr ) . addReg ( Mask ) ;


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp )


<s> unsigned XFormOpcode = RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) ; assert ( ( XFormOpcode != <STR_LIT> ) && <STR_LIT> ) ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! instrHasImmForm ( XFormOpcode , IsVFReg , III , PostRA ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI


<s> I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand (


<s> if ( TARGET_LONG_DOUBLE_128 ) { if ( ! TARGET_IEEEQUAD ) init_float128_ibm ( TFmode ) ; else init_float128_ieee (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , false , <NUM_LIT> ) ; initAsmInfo (


<s> int64_t branch_offset = dest - pSource ; if ( ( branch_offset > <ISA_LIT>GNULDBackend :: MAX_FWD_BRANCH_OFFSET ) || ( branch_offset < <ISA_LIT>GNULDBackend :: MAX_BWD_BRANCH_OFFSET ) ) { return true


<s> if ( arm_rtx_shift_left_p ( x ) ) return x ; else for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( shift_rtx_codes ) ; i ++ ) if ( GET_CODE ( x ) == shift_rtx_codes [ i ] ) return x ; } if ( GET_CODE ( x ) == code ) return


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && IsComplex ) return


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) { if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( ! isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( offsetToAlignment ( Offset . getImm ( ) , Align ( <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ; Inst . clear (


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E =


<s> return removeBranchImpl ( MBB , BytesRemoved , false


<s> static bool isOpcWithIntImmediate ( const SDNode * N , unsigned Opc , uint64_t


<s> unsigned regSize ( ) const { return IsO32 ?


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode (


<s> int bs0 , bs1 , p , len ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; for ( bs0 = <NUM_LIT> ; bs0 < HOST_BITS_PER_WIDE_INT ; bs0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs0 ) )


<s> cycles = MAX ( cycles , CEIL ( ops -> loads + ops -> stores , issue_info -> loads_stores_per_cycle ) ) ; cycles = MAX ( cycles , CEIL ( ops -> general_ops

, issue_info -> general_ops_per_cycle ) ) ;


<s> bool IsOptimizingSize = DAG . getMachineFunction ( ) .


<s> for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; NonPredicated . insert ( MI ) ; break ; } } if ( ! NonPredicated . contains ( MI ) ) Predicated . insert ( MI ) ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutMIs ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; assert ( ML . getNumBlocks ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ExitBlocks . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * ExitBB = ExitBlocks . front ( ) ; for ( const MachineBasicBlock :: RegisterMaskPair & RegMask : ExitBB -> liveins ( ) ) { if ( RegMask . PhysReg == <STR_LIT> ) return false ; if ( QPRs -> contains ( RegMask . PhysReg ) ) if ( auto * MI = RDA . getLocalLiveOutMIDef ( Header , RegMask . PhysReg ) ) LiveOutMIs . insert ( MI ) ; } for ( auto * MI : LiveOutMIs ) { if ( NonPredicated . count ( MI ) && FalseLanesUnknown . contains ( MI ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> std :: unique_ptr < <ISA_LIT>Operand > Op ( new ( Mem ) <ISA_LIT>Operand ( Token ) ) ; Op -> Tok . Data = ( const char * ) ( Op . get ( ) + <NUM_LIT> ) ; Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( ( void * ) Op -> Tok . Data , Str . data ( ) , Str . size ( ) ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; Op -> Is<ISA_LIT>64 =


<s> if ( Subtarget . hasAVX512 ( ) ) { if ( IsStrict ) return DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , N0 } ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; } SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( ( double ) ( <NUM_LIT> << <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWordMask ) ; if ( IsStrict ) { SDValue fHI = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , HI } ) ; fHI = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { fHI . getValue ( <NUM_LIT> ) , fHI , TWOHW } ) ; SDValue fLO = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , LO } ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI . getValue ( <NUM_LIT> ) , fLO . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Chain , fHI , fLO } ) ; } SDValue fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI ) ; fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI , TWOHW ) ; SDValue fLO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true