<s> const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL } ) for ( auto Ty : { s8 , s16 , s32 , s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64


<s> CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && ! IsCCallConvention ( CalleeCC ) ) return false ; return


<s> return DAG -> getNode ( <STR_LIT> , dl , VT ,


<s> if ( <STR_LIT> ( N . getNode ( ) ) && IsLegalToFold ( N , P , P , OptLevel ) ) return SelectAddrRRI20 ( N . getOperand ( <NUM_LIT> ) , Base


<s> int label = ++ current_machopic_label_num ; gcc_assert ( ! TARGET_64BIT ) ; symb = targetm . strip_name_encoding ( symb ) ; length = strlen ( stub ) ; binder_name = XALLOCAVEC ( char , length + <NUM_LIT> ) ; GEN_BINDER_NAME_FOR_STUB ( binder_name , stub , length ) ; length = strlen ( symb ) ; symbol_name = XALLOCAVEC ( char , length + <NUM_LIT> ) ; GEN_SYMBOL_NAME_FOR_SYMBOL ( symbol_name , symb , length ) ; sprintf ( lazy_ptr_name , <STR_LIT> , label ) ; if ( MACHOPIC_ATT_STUB ) switch_to_section ( darwin_sections [ machopic_picsymbol_stub3_section ] ) ; else if ( MACHOPIC_PURE ) switch_to_section ( darwin_sections [ machopic_picsymbol_stub2_section ] ) ; else switch_to_section ( darwin_sections [ machopic_symbol_stub_section ] ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; if ( MACHOPIC_ATT_STUB ) { fprintf ( file , <STR_LIT> ) ; } else if ( MACHOPIC_PURE ) { rtx tmp = gen_rtx_REG ( SImode , <NUM_LIT> ) ; output_set_got ( tmp , NULL_RTX ) ; fprintf ( file , <STR_LIT> , label , lazy_ptr_name , label ) ; fprintf ( file , <STR_LIT> ) ; } else fprintf ( file , <STR_LIT> , lazy_ptr_name ) ; if ( MACHOPIC_ATT_STUB ) return ; fprintf ( file , <STR_LIT> , binder_name ) ; if ( MACHOPIC_PURE ) { fprintf ( file , <STR_LIT> , lazy_ptr_name , binder_name ) ; fprintf ( file , <STR_LIT>


<s> Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val , DAG . getValueType ( ValVT ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; case CCValAssign :: ZExtUpper : case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val , DAG . getValueType ( ValVT ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , ValVT ,


<s> static bool isVTBLMask ( ArrayRef < int > M , EVT VT ) { return VT == <STR_LIT> && M . size ( ) ==


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerSin ( SDValue Op ,


<s> if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( RegSaveFrameIndex ) , MachineMemOperand :: MOStore , Offset , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( <STR_LIT> ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } F -> DeleteMachineInstr ( MI


<s> return ( __m512i ) __builtin_ia32_pmovzxwq512_mask ( ( __v8hi ) __A , ( __v8di )


<s> const MCExpr * getConstantPoolImm ( ) const { assert ( isConstantPoolImm ( ) && <STR_LIT> ) ; return Imm . Val


<s> return __builtin_aarch64_ashr_simddi ( __a ,


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += <NUM_LIT> ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get (


<s> } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) { Inst . setOpcode ( <STR_LIT> ) ; } else { if ( ! isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset . getImm ( ) ) ) ; } } Instructions . push_back ( Inst ) ; if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Instructions . push_back ( NopInst )


<s> if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , LD -> getDebugLoc ( ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal

( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;


<s> void addUImmOperands ( MCInst & Inst , unsigned N ) const { if ( isImm ( ) && ! isConstantImm ( ) ) { addExpr ( Inst , getImm ( ) ) ; return ; } addConstantUImmOperands < Bits , <NUM_LIT> , <NUM_LIT> > ( Inst , N


<s> if ( MI . getNumOperands ( ) < <NUM_LIT> ) return false ; unsigned ShOpVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ShImm = <STR_LIT>


<s> auto isVMOVNOriginalMask = [ & ] ( ArrayRef < int > M , bool rev ) { unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ; } return true ; } ; if ( Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( SDValue U = PerformVQDMULHCombine ( Trunc . getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ) { DAG . ReplaceAllUsesWith ( Trunc . getOperand ( <NUM_LIT> ) , U ) ; return SDValue ( ) ; } } if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc -> getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNOriginalMask ( Shuffle -> getMask ( ) , false ) || isVMOVNOriginalMask ( Shuffle -> getMask ( ) , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = i * NumElements * ToEltVT


<s> if ( MI -> getOperand ( i ) . isImplicit ( ) ) continue ; if ( ( int ) i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; printOperand ( MI , i ) ; } O <<


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable (


<s> InstructionCost <ISA_LIT>TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty ,


<s> unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , <NUM_LIT> ) ) return <NUM_LIT> ; } if ( saved_int_regs & <NUM_LIT> ) return <NUM_LIT> ; } if ( TARGET_INTERWORK && saved_int_regs != <NUM_LIT> && ! IS_INTERRUPT ( func_type ) ) return <NUM_LIT> ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != <NUM_LIT> && saved_int_regs != ( <NUM_LIT> << LR_REGNUM ) ) return <NUM_LIT> ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return <NUM_LIT> ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return <NUM_LIT> ; if ( saved_int_regs && ! ( saved_int_regs & ( <NUM_LIT> << LR_REGNUM ) ) ) return <NUM_LIT> ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return <NUM_LIT> ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return <NUM_LIT> ; return


<s> if ( ! Subtarget . hasSSE2 ( ) && VT . is128BitVector ( ) ) { Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } else


<s> static SDValue PerformADDECombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && SelectMadd ( N , & DAG ) ) return SDValue ( N ,


<s> MachineBasicBlock * newBB = NULL ; for ( auto & Reg : functionCallArgs ) { MachineBasicBlock * lastCheck = NULL ; newBB = insertVoting ( MF , MI


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoDsp ( ) ; return false


<s> if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) store_string = <STR_LIT> ; else if ( mode == DFmode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_DFORM_SCALAR ) { if ( mode == SFmode ) store_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case QImode : store_string = <STR_LIT> ; break ; case HImode : store_string = <STR_LIT> ; break ; case SImode : case SFmode : store_string = <STR_LIT> ; break ; case DImode : case DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else fatal_insn ( <STR_LIT> , reg ) ; if ( ! MEM_P ( mem ) ) fatal_insn ( <STR_LIT> , mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; fusion_split_address ( addr , & hi , & lo ) ; emit_fusion_addis ( tmp_reg , hi , <STR_LIT> , GET_MODE_NAME ( mode ) ) ; emit_fusion_load_store ( reg , tmp_reg , lo , store_string ) ; return <STR_LIT>


<s> if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + <NUM_LIT> ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = <NUM_LIT> ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , <NUM_LIT> ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - <NUM_LIT> ) cum -> intoffset =


<s> const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = CountTrailingZeros_32 ( v ) ; uint32_t msb = ( <NUM_LIT> - CountLeadingZeros_32


<s> inline vector signed char vec_sld ( vector signed char a1 , vector signed char a2 ,


<s> return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD |


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue (


<s> return ( __m256 ) __builtin_ia32_broadcastf32x4_256_mask ( ( __v4sf ) __A , ( __v8sf ) _mm256_undefined_pd ( ) , (


<s> if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT ) ; if ( CompareOpc ==


<s> return ( __m128 ) __builtin_ia32_cvtpd2ps ( (


<s> int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable , true ) ; return DAG . getFrameIndex ( FI , PtrVT ) ; } if ( Flags . isCopyElisionCandidate ( ) ) { EVT ArgVT = Ins [ i ] . ArgVT ; SDValue PartAddr ; if ( Ins [ i ] . PartOffset == <NUM_LIT> ) { int FI = MFI . CreateFixedObject ( ArgVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , false ) ; PartAddr = DAG . getFrameIndex ( FI , PtrVT ) ; return DAG . getLoad ( ValVT , dl , Chain , PartAddr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { int64_t PartBegin = VA . getLocMemOffset ( ) ; int64_t PartEnd = PartBegin + ValVT . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI . getObjectIndexBegin ( ) ; for ( ; MFI . isFixedObjectIndex ( FI ) ; ++ FI ) { int64_t ObjBegin = MFI . getObjectOffset ( FI ) ; int64_t ObjEnd = ObjBegin + MFI . getObjectSize ( FI ) ; if ( ObjBegin <= PartBegin && PartEnd <= ObjEnd ) break ; } if ( MFI . isFixedObjectIndex ( FI ) ) { SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getFrameIndex ( FI , PtrVT ) , DAG . getIntPtrConstant ( Ins [ i ] .


<s> unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back


<s> TargetStackID :: Value <ISA_LIT>FrameLowering :: getStackIDForScalableVectors ( ) const { return TargetStackID :: ScalableVector


<s> inline SDValue getI64Imm ( uint64_t Imm , const


<s> if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM ) ; } else O << <STR_LIT> ( Mode ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Mode == <STR_LIT> ) O << <STR_LIT> ; } else { printOperand ( MI , Op ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> if ( MI . definesRegister ( DefReg ) ) LastLivePos = std :: min ( LastLivePos , MIPosition ) ; MachineOperand * UseOp = MI . findRegisterUseOperand ( DefReg ) ; if ( ! UseOp ) continue ; if ( UseOp -> isKill ( ) ) LastLivePos = std :: min ( LastLivePos , MIPosition ) ; Uses [ MIPosition ] = UseOp ; } for ( std :: map < unsigned , MachineOperand * > :: iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > (

C -> getZExtValue ( ) ) ) weight = CW_Constant ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineInstr * <ISA_LIT>InstrInfo :: getForwardingDefMI ( MachineInstr & MI , unsigned & OpNoForForwarding , bool & SeenIntermediateUse ) const { OpNoForForwarding = ~ <NUM_LIT> ; MachineInstr * DefMI = nullptr ; MachineRegisterInfo * MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MRI -> isSSA ( ) ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; Register Reg = MI . getOperand ( i ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( Register :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else


<s> return DAG . getConstant ( APInt ( Op -> getValueType ( <NUM_LIT> ) . getScalarType ( ) . getSizeInBits ( ) , Op -> getConstantOperandVal ( ImmOp ) , IsSigned

) , SDLoc ( Op ) , Op -> getValueType ( <NUM_LIT> ) ) ;


<s> O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : { Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin ( ) ) ; TmpInst . setOpcode ( <STR_LIT> ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isGlobal ( ) ) ; MCSymbol * & TOCEntry = TOC [ Mang -> getSymbol ( MO . getGlobal ( ) ) ] ; if ( TOCEntry == <NUM_LIT> ) TOCEntry = GetTempSymbol ( <STR_LIT> , TOCLabelID ++ ) ; const MCExpr * Exp = MCSymbolRefExpr :: Create ( TOCEntry , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateExpr


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ^ is_swapped ] ; high = nelt / <NUM_LIT> ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; return ! Subtarget ->


<s> emit_insn ( gen_store_df_high ( mips_subword ( dest , <NUM_LIT> ) , src ) ) ; } else { rtx low_dest ; low_dest = mips_subword ( dest , <NUM_LIT> ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { emit_move_insn ( mips_subword ( dest , <NUM_LIT> ) , mips_subword ( src


<s> bool isMemoryUnscaled ( ) const { if ( ! isMem ( ) ) return false ; if ( Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) )


<s> initialize<ISA_LIT>CTRLoopsVerifyPass ( * PassRegistry ::


<s> Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Op0 , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts = <NUM_LIT> ; SVT = <STR_LIT> ; } Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getBuildVector ( NewVT , dl , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) && Subtarget . hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return Op ; if ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) return Op ; if ( SrcVT . isVector ( ) && DstVT . isVector (


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatMaskR ( SDValue N , SDValue &


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg

( SrcReg , getKillRegState ( isKill ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitPTEST ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg


<s> return ( __m512i ) __builtin_ia32_expandloadqi512_mask ( ( const __v64qi * ) __C ,


<s> const char * pass_name = current_pass -> name ; if ( pass_name && ( ( strcmp ( pass_name , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp ( pass_name , <STR_LIT> ) == <NUM_LIT> ) ) ) return ! satisfies_constraint_Da ( mem ) || MEM_VOLATILE_P ( mem ) ; return


<s> mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 ,


<s> __builtin_aarch64_st1v2df ( ( __builtin_aarch64_simd_df * ) a ,


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU ,


<s> FunctionPass * llvm :: create<ISA_LIT>BranchSelectionPass ( ) { return new <ISA_LIT>BSel (


<s> static void rs6000_xcoff_asm_output_anchor ( rtx symbol ) { char buffer [ <NUM_LIT> ] ; sprintf ( buffer , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , SYMBOL_REF_BLOCK_OFFSET ( symbol ) ) ; fprintf ( asm_out_file , <STR_LIT> , SET_ASM_OP ) ; RS6000_OUTPUT_BASENAME ( asm_out_file , XSTR ( symbol , <NUM_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> ) ; RS6000_OUTPUT_BASENAME ( asm_out_file , buffer


<s> return infer_vector_or_tuple_type ( argno , vectors_per_tuple


<s> unsigned LS = findLastSet ( RImm ) ; if ( LS != r - <NUM_LIT> ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( <NUM_LIT> ) << ( LS + <NUM_LIT> ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ; } } if ( ! RMin ) return getInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; SDValue Val = SDValue ( getInt64Direct ( CurDAG , dl ,


<s> case <STR_LIT> : Streamer . EmitRawText ( StringRef ( <STR_LIT> ) + String . lower ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Streamer . EmitRawText ( StringRef ( <STR_LIT> ) + String


<s> __attribute__ ( ( __always_inline__ ) ) vreinterpret_f64_s32 (


<s> DebugLoc dl = SVOp -> getDebugLoc ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; MVT NewVT ; unsigned Scale ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Scale ; ++ j ) { int EltIdx = SVOp -> getMaskElt ( i + j ) ; if ( EltIdx < <NUM_LIT> ) continue ; if ( StartIdx < <NUM_LIT> ) StartIdx = ( EltIdx / Scale ) ; if ( EltIdx != ( int ) ( StartIdx * Scale + j ) ) return SDValue ( ) ; } MaskVec . push_back ( StartIdx


<s> LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Alignment >= Align ( <NUM_LIT> ) && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false


<s> void printf64mem ( const MachineInstr * MI , unsigned OpNo ) { printMemReference ( MI ,


<s> if ( needsStackRealignment ( MF ) ) return true ; return MFI -> getLocalFrameSize ( ) >= <NUM_LIT> ; } return


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; if ( AssemblerOptions . size ( ) == <NUM_LIT> ) return reportParseError ( Loc , <STR_LIT>


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs ) ; for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; bool BumpSP = RPII == RegPairs . rbegin ( ) ; if ( RPI . IsGPR ) { if ( BumpSP ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; } else { if ( BumpSP ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; } DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg2 ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; const int Offset = BumpSP ? - RPI . Offset : RPI . Offset ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( BumpSP ) MIB . addReg ( <STR_LIT> , RegState :: Define ) ; if ( RPI . isPaired ( ) ) { MBB . addLiveIn ( Reg1 ) ; MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . setMIFlag (


<s> if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( N ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Base ,

CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < <NUM_LIT> && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset & <NUM_LIT> ; low_off = offset < <NUM_LIT> ? - low_off : low_off ; insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( dest , GEN_INT ( offset - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( emit_move_imm )


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , const Instruction * I ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getCastInstrCost ( Opcode , Dst , Src ) ; return vectorCostAdjustment ( Cost , Opcode


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( ! isBaseRegConflictPossible ( DAG , ClobberSet ) ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; if ( ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize || ConstantSize -> getZExtValue ( ) > Subtarget . getMaxInlineSizeThreshold ( ) ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg =


<s> switch ( type ) { case ONEBYTE : decision = & ONEBYTE_SYM ; break ; case TWOBYTE : decision = & TWOBYTE_SYM ; break ; case THREEBYTE_38 : decision = & THREEBYTE38_SYM ; break ; case THREEBYTE_3A : decision = & THREEBYTE3A_SYM


<s> emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> EVT EltVT = VT . getVectorElementType ( ) ; SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML -> getPointerInfo ( ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , VT , ML -> getSrc0 ( ) , Load ,


<s> return ( __m128i ) __builtin_ia32_cvttpd2udq256_mask ( ( __v4df ) __A , ( __v4si )


<s> static rtx get_vector_offset ( rtx mem , rtx element , rtx base_tmp , unsigned scalar_size ) { if ( CONST_INT_P ( element ) ) return GEN_INT ( INTVAL ( element ) * scalar_size ) ; gcc_assert ( satisfies_constraint_Q ( mem ) ) ; rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( GET_MODE ( mem ) ) - <NUM_LIT> ) ; rtx and_op = gen_rtx_AND ( Pmode , element , num_ele_m1 ) ; emit_insn ( gen_rtx_SET ( base_tmp , and_op ) ) ; int shift = exact_log2 ( scalar_size ) ; gcc_assert ( shift >= <NUM_LIT> ) ; if ( shift > <NUM_LIT> ) { rtx shift_op = gen_rtx_ASHIFT ( Pmode , base_tmp


<s> SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; return DAG . getZExtOrTrunc ( V , DL , VT ) ; } if ( SExtVT == <STR_LIT> ) { assert ( <NUM_LIT> == DAG . ComputeNumSignBits ( V ) && <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getUNDEF ( <STR_LIT> ) ) ; } else assert ( SExtVT . getScalarType ( ) != <STR_LIT> && <STR_LIT> ) ; if ( FPCastVT != <STR_LIT> ) V = DAG . getBitcast ( FPCastVT


<s> else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + <NUM_LIT> ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1


<s> rtx p = PATTERN ( i ) ; return GET_CODE ( p ) == SET && GET_CODE ( XEXP ( p


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig


<s> assemble_name ( stream , name ) ; fputs ( <STR_LIT> ,


<s> if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDValue Index = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDNode * Extract = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , VT , N , Index ) ; return SDValue ( Extract , <NUM_LIT> ) ; } assert ( N . getValueType ( ) == VT


<s> static __inline float sh_media_FGETSCR (


<s> if ( mode == P2HImode || mode == P2QImode )

return GET_MODE_SIZE ( mode ) / <NUM_LIT> ;


<s> unsigned <ISA_LIT>OptimizePICCall :: getCount ( ValueType Entry


<s> gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( ! cum -> gp_reg_found && cum -> arg_number < <NUM_LIT> && ( type == <NUM_LIT> || SCALAR_FLOAT_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_N32 : case ABI_64 : gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( named && ( type == <NUM_LIT> || FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || mode == V2SFmode ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; if ( info -> fpr_p && GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_UNIT_SIZE ( mode ) <


<s> void * RelocPos = ( char * ) Function + MR -> getMachineCodeOffset ( ) ; intptr_t ResultPtr = resolveRelocDestAddr ( MR ) ; switch ( ( <STR_LIT> ) MR -> getRelocationType ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; if ( ResultPtr >= <NUM_LIT> ) * ( ( intptr_t * ) RelocPos ) |= <NUM_LIT> << <STR_LIT> ; else { * ( ( intptr_t * ) RelocPos ) &= ~ ( <NUM_LIT> << <STR_LIT> ) ; ResultPtr = - ResultPtr ; } if ( MR -> getRelocationType ( ) == <STR_LIT> ) ResultPtr = ResultPtr >> <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; * ( ( intptr_t * ) RelocPos ) |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; break ; } case <STR_LIT> : case


<NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ;


<s> } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: op_iterator O = ChainNext -> op_begin ( ) , OE = ChainNext -> op_end ( ) ; O != OE ; ++ O ) if ( ! Visited . count ( O -> getNode ( ) ) ) Queue . push_back ( O -> getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ; Queue . clear ( ) ; for ( SmallSet < SDNode * , <NUM_LIT> > :: iterator I = LoadRoots . begin ( ) , IE = LoadRoots . end ( ) ; I != IE ; ++ I ) { Queue . push_back ( * I ) ; while ( ! Queue . empty ( ) ) { SDNode * LoadRoot = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( LoadRoot )


<s> uint64_t getPC16DBLEncoding ( const MCInst & MI , unsigned OpNum ,

SmallVectorImpl < MCFixup > & Fixups ) const {


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( ! <STR_LIT> ( N . getNode ( ) ) || ! IsProfitableToFold ( N , P , P ) || ! IsLegalToFold ( N , P , P , OptLevel ) ) return false ; return SelectAddr ( P , N . getOperand ( <NUM_LIT> ) , Base , Scale , Index


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) { SubReg = <STR_LIT> ; return MI -> getOperand ( <NUM_LIT>


<s> static bool mips_far_type_p ( const_tree type ) { return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES (


<s> assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ;


<s> if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) { ExtraReg = CSRegs [ i ] ; break ; } } if ( ExtraReg != <NUM_LIT> ) { MF . getRegInfo ( ) . setPhysRegUsed ( ExtraReg ) ; } else { assert ( RS && <STR_LIT> ) ; const TargetRegisterClass * RC =


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT>


<s> bool isMemOffs8 ( ) const { return Kind == Memory && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem . Size


<s> if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; SDValue SBB = materializeSBB ( Y . getNode ( ) , NewEFLAGS , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; SDValue NewCmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , DAG . getConstant ( <NUM_LIT> , DL , Z . getValueType ( ) ) ) ; SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> )


<s> MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ; return get<ISA_LIT>VectorSplatScalar ( * OpMI


<s> int NumEltsPerLane = NumElts / NumLanes ; int NumInnerEltsPerLane = NumInnerElts / NumLanes ; DemandedLHS = APInt :: getZero ( NumInnerElts ) ; DemandedRHS = APInt :: getZero ( NumInnerElts ) ; for ( int Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( int Elt = <NUM_LIT> ; Elt != NumInnerEltsPerLane ; ++ Elt ) { int OuterIdx = ( Lane * NumEltsPerLane ) + Elt ; int InnerIdx = ( Lane * NumInnerEltsPerLane ) + Elt ; if ( DemandedElts [ OuterIdx ] ) DemandedLHS . setBit ( InnerIdx ) ; if ( DemandedElts [ OuterIdx + NumInnerEltsPerLane ]


<s> Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && tryFoldLoad ( Node , N1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , N1 . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( N1 . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; CurDAG -> setNodeMemRefs ( CNode , { cast < LoadSDNode > ( N1 ) -> getMemOperand ( ) } ) ; return CNode ; } SDValue Ops [ ] = { N0 , N1 , Imm } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( ROpc ,


<s> if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 . getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 . getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 . getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; Register Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1


<s> Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( <STR_LIT> ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo (


<s> return false ; case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_FP : translateFPRegister ( mcInst , insn . modRM &


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty (


<s> MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr ,


<s> static void loongarch_for_each_saved_reg ( HOST_WIDE_INT sp_offset , loongarch_save_restore_fn fn ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { loongarch_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine

-> frame . fmask , regno - FP_REG_FIRST ) ) {


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned DNum = CSI [ i ] . getReg ( ) - <STR_LIT> ; if ( DNum >= <NUM_LIT> ) continue ; int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectAlignment ( FI , DNum % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( DNum == <NUM_LIT> ) MFI . setObjectAlignment ( FI , MFI . getMaxAlignment ( ) ) ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ; Opc = isThumb ? <STR_LIT>


<s> for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ; Setup = FindLoopIterations ( Preheader -> getSinglePredecessor ( ) ) ; if ( ! Setup ) return false ; } IntrinsicInst * Decrement = nullptr ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( IsDecrement ( I ) ) { Decrement = cast < IntrinsicInst > ( & I ) ; break ; } } } if ( ! Decrement ) return false ; ClonedVCTPInExitBlock = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * L << * Setup << <STR_LIT> << * Decrement << <STR_LIT> ) ; if ( TryConvert ( Setup -> getArgOperand (


<s> JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ) ; assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ; const GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue >


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto InsertPt = MI . getIterator ( ) ; DebugLoc Loc = MI . getDebugLoc ( ) ; if ( FenceCallAndRet ) { if ( MI . isReturn ( ) ) return ; BuildMI ( MBB , std :: next ( InsertPt ) , Loc , TII -> get ( <STR_LIT> ) ) ; ++ NumInstsInserted ; ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { unsigned ActualRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ActualRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState

:: Kill ) . addReg ( ActualRetAddrReg , RegState :: Kill ) ;


<s> isFirst = isSingle = isCracked = isLoad = isStore = false ; return <STR_LIT> ; } Opcode = ~ Opcode ; const MCInstrDesc & MCID = TII . get ( Opcode ) ; isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags & <STR_LIT> ; return ( <STR_LIT> ) ( TSFlags &


<s> Value * <ISA_LIT>IREmitter :: visitATOMSWAP64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> SDValue EltIdx = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = InputVector . getValueType ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( InputVector ) ; if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( VT == <STR_LIT> && InputVector . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( EltIdx ) && isa < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = N -> getConstantOperandVal ( <NUM_LIT> ) ; auto * InputC = cast < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ; const APInt & InputValue = InputC -> getAPIntValue ( ) ; uint64_t Res = InputValue [ ExtractedElt ] ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address ,

Decoder ) ) ) return MCDisassembler :: Fail ;


<s> printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> )

. getImm ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> int sh_expand_t_scc ( enum rtx_code code , rtx target ) { rtx result = target ; HOST_WIDE_INT val ; if ( GET_CODE ( sh_compare_op0 ) != REG || REGNO ( sh_compare_op0 ) != T_REG || GET_CODE ( sh_compare_op1 ) != CONST_INT ) return <NUM_LIT> ; if ( GET_CODE ( result ) != REG ) result = gen_reg_rtx ( SImode ) ; val = INTVAL ( sh_compare_op1 ) ; if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movt ( result ) ) ; else if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , result ) ) ; emit_insn ( gen_subc ( result , result , result ) ) ; emit_insn ( gen_addsi3 ( result , result , const1_rtx ) ) ; } else if ( code == EQ || code == NE ) emit_insn ( gen_move_insn ( result , GEN_INT ( code == NE ) ) ) ; else return <NUM_LIT> ; if ( result != target ) emit_move_insn


<s> if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vextv16qi ; break ; case E_V8QImode : gen = gen_neon_vextv8qi ; break ; case E_V4HImode : gen = gen_neon_vextv4hi ; break ; case E_V8HImode : gen = gen_neon_vextv8hi ; break ; case E_V2SImode : gen = gen_neon_vextv2si ; break ; case E_V4SImode : gen = gen_neon_vextv4si ; break ; case E_V4HFmode : gen = gen_neon_vextv4hf ; break ; case E_V8HFmode : gen = gen_neon_vextv8hf ; break ; case E_V2SFmode : gen = gen_neon_vextv2sf ; break ; case E_V4SFmode : gen = gen_neon_vextv4sf ; break ; case E_V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d


<s> addPass ( create<ISA_LIT>OptimizePICCallPass ( get<ISA_LIT>TargetMachine


<s> return ( unsigned long long ) __builtin_ia32_vcvtsd2usi64 ( ( __v2df


<s> if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , <NUM_LIT> , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT


<s> case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT> : emitVFPLoadStoreInstruction ( MI ) ; break ; case


<s> PM . add ( createBasicTargetTransformInfoPass ( getTargetLowering ( ) ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this )


<s> switch ( mode ) { case E_V1TImode : subparts = <NUM_LIT> ; break ; case E_V2DFmode : case E_V2DImode : subparts = <NUM_LIT> ; break ; case E_V4SFmode : case E_V4SImode : subparts = <NUM_LIT> ; break ; case E_V8HImode : subparts = <NUM_LIT> ; break ; case E_V16QImode : subparts = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = <NUM_LIT> ; i < subparts / <NUM_LIT> ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / <NUM_LIT> ) ; for ( i = subparts / <NUM_LIT> ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / <NUM_LIT> ) ; return


<s> Value * FI8 = Builder . CreateBitCast ( F , Type :: getInt8PtrTy ( F ->


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . getObjectOffset ( FrameRegIdx ) ; llvm_unreachable ( <STR_LIT>


<s> assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk =


<s> extern __inline __m256d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_i32gather_pd ( double const * base , __m128i index , const int scale ) { __v4df zero = _mm256_setzero_pd (


<s> case E_DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_arm_load_exclusiveqi ; break ; case E_HImode : gen = gen_arm_load_exclusivehi ; break ; case E_SImode : gen = gen_arm_load_exclusivesi ; break ; case E_DImode : gen = gen_arm_load_exclusivedi ; break ; default : gcc_unreachable (


<s> UP . Partial = UP . Runtime = true ; } TargetTransformInfo :: getUnrollingPreferences ( F ,


<s> auto E = OpcodeToGroup . end ( ) ; for ( auto I = OpcodeToGroup . begin ( ) ; I != E ; I ++ ) { const <ISA_LIT>InstrFMA3Group * G = I -> second ; if ( DeletedGroups . find ( G ) == DeletedGroups . end ( ) ) { DeletedGroups . insert ( G


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineFunction :: iterator It = BB ; ++ It ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned oldval = dest ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * TRC , * TRCsp ; if ( Size == <NUM_LIT> ) { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } else { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; MRI . constrainRegClass ( scratch , TRCsp ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; MRI . constrainRegClass ( incr , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( incr ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , scratch ) . addReg ( oldval ) . addReg ( incr ) . addImm ( Cond ) ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addMBB ( loopMBB ) ; BB -> addSuccessor (


<s> TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , NIsKill , TotalOffs ) ; if ( ! N ) return false ; NIsKill = true ; TotalOffs = <NUM_LIT> ; } uint64_t ElementSize = DL . getTypeAllocSize ( Ty ) ; std :: pair < unsigned , bool > Pair = getRegForGEPIndex ( Idx ) ; unsigned IdxN = Pair . first ; bool IdxNIsKill = Pair . second ; if ( ! IdxN ) return false ; if ( ElementSize != <NUM_LIT> ) { unsigned C = fastEmit_i ( VT , VT , <STR_LIT> , ElementSize ) ; if ( ! C ) return false ; IdxN = emitMul_rr ( VT , IdxN , IdxNIsKill , C , true ) ; if ( ! IdxN ) return false ; IdxNIsKill = true


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) )


<s> unsigned <ISA_LIT>MachOTargetObjectFile :: getTTypeEncoding ( ) const { return DW_EH_PE_indirect | DW_EH_PE_pcrel


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout )


<s> if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; machine_mode mmsk = mode_for_int_vector ( mode ) . require ( ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > <NUM_LIT> ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( !


<s> return ( __m256i ) __builtin_ia32_broadcasti64x2_256_mask ( ( __v2di ) __A ,


<s> int converted_insns = <NUM_LIT> ; bitmap_obstack_initialize ( NULL ) ; candidates = BITMAP_ALLOC ( NULL ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_md_add_problem ( ) ; df_analyze ( ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( scalar_to_vector_candidate_p ( insn ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ; bitmap_set_bit ( candidates , INSN_UID ( insn ) ) ; } } remove_non_convertible_regs ( candidates ) ; if ( bitmap_empty_p ( candidates ) ) if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; while ( ! bitmap_empty_p ( candidates ) ) { unsigned uid = bitmap_first_set_bit ( candidates ) ; scalar_chain chain ; chain . build ( candidates , uid ) ; if ( chain . compute_convert_gain ( ) > <NUM_LIT> ) converted_insns += chain .


<s> bool isMemNoOffsetT2NoSp ( bool alignOK = false , unsigned Alignment = <NUM_LIT> ) const { if ( ! isGPRMem ( ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory .


<s> static DecodeStatus DecodePredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> && Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Val != <STR_LIT> && ! <ISA_LIT>Insts [ Inst . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , MCDisassembler :: SoftFail ) ; Inst . addOperand ( MCOperand :: createImm ( Val )


<s> set_conv_libfunc ( sext_optab , mode_iter , BFmode , NULL ) ; set_conv_libfunc ( sext_optab , BFmode , mode_iter , NULL


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; bool Success = true ; if ( VReg ) { const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , VReg , Offset ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFn , AssignFn ) ; Success = handleAssignments ( MIRBuilder , SplitArgs , Handler


<s> unsigned LOOPi = ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( )


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case (

<STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD_SUB ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; EVT T = Node -> getValueType ( <NUM_LIT> ) ; SDValue negOp = DAG . getNode ( <STR_LIT> , dl , T , DAG . getConstant ( <NUM_LIT> , T ) , Node -> getOperand ( <NUM_LIT> ) ) ; return DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , negOp ,

cast < AtomicSDNode > ( Node ) -> getSrcValue ( ) , cast < AtomicSDNode > ( Node ) -> getAlignment ( ) ) ;


<s> if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ; else Const = ConstantFP :: get ( Type :: getDoubleTy ( C


<s> static void mips_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx addr , end_addr , high , low , opcode , mem ; rtx trampoline [ <NUM_LIT> ] ; unsigned int i , j ; HOST_WIDE_INT end_addr_offset , static_chain_offset , target_function_offset ; end_addr_offset = mips_trampoline_code_size ( ) ; static_chain_offset = end_addr_offset ; target_function_offset = static_chain_offset + GET_MODE_SIZE ( ptr_mode ) ; addr = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; end_addr = mips_force_binary ( Pmode , PLUS , addr , GEN_INT ( end_addr_offset ) ) ; i = <NUM_LIT> ; if ( TARGET_USE_PIC_FN_ADDR_REG ) { trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( AT_REGNUM , target_function_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( STATIC_CHAIN_REGNUM , static_chain_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_JR ( AT_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_MOVE ( PIC_FUNCTION_ADDR_REGNUM , AT_REGNUM ) ) ; } else if ( ptr_mode == DImode ) { trampoline [ i ++ ] = OP ( MIPS_MOVE ( AT_REGNUM , RETURN_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP (


<s> static bool resolveBuildVector ( BuildVectorSDNode * BVN , APInt & CnstBits , APInt & UndefBits ) { EVT VT = BVN -> getValueType ( <NUM_LIT> ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { unsigned NumSplats = VT . getSizeInBits ( ) / SplatBitSize ; for ( unsigned i = <NUM_LIT> ; i < NumSplats ; ++ i ) { CnstBits <<=


<s> bool <ISA_LIT>InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute (


<s> } auto GetFunnelShift = [ & DAG , & DL , VT , Opc ] ( SDValue Op0 , SDValue Op1 , SDValue Amt ) { if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Amt ) ) ; } ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1Op1 . getOperand ( <NUM_LIT> ) ) && ShAmt1Op1 . getConstantOperandAPInt ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1Op1 ; ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; } if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( ( SumC -> getAPIntValue ( ) == Bits || ( SumC -> getAPIntValue ( ) == <NUM_LIT> && ShMsk1 ) ) && ShAmt1Op1 == ShAmt0 ) return GetFunnelShift ( Op0 , Op1 , ShAmt0 ) ; } } else if ( auto * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { auto * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ( ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) ) == Bits ) return GetFunnelShift ( Op0 , Op1 , ShAmt0 ) ; } else if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ) { unsigned InnerShift = ( <STR_LIT> == Opc ? <STR_LIT> : <STR_LIT> ) ; SDValue ShAmt1Op0 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op0 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op0 = ShAmt1Op0 . getOperand ( <NUM_LIT> ) ; if ( MaskC -> getSExtValue ( ) == ( Bits - <NUM_LIT> ) && ( ShAmt1Op0 == ShAmt0 || ShAmt1Op0 == ShMsk0 ) ) { if ( Op1 . getOpcode ( ) == InnerShift && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT>

) ) && Op1 . getConstantOperandAPInt ( <NUM_LIT> ) == <NUM_LIT> ) {


<s> if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( TLI . getTypeAction ( * DAG . getContext ( ) , StoreVT ) == TargetLowering :: TypeWidenVector && <STR_LIT> ) ; EVT WideVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , StoreVT ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT , <NUM_LIT>


<s> return ( __m512i ) __builtin_ia32_punpcklwd512_mask ( ( __v32hi ) __A , ( __v32hi ) __B , (


<s> OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW )


<s> auto IsMoveLR = [ ] ( MachineInstr * MI , unsigned Reg ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; MachineBasicBlock * MBB = Start -> getParent ( ) ; unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * PredLRDef = SearchForDef ( Start , MBB -> rend ( ) , <STR_LIT> ) ; if ( PredLRDef && ! IsMoveLR ( PredLRDef , CountReg ) ) PredLRDef = nullptr ; MachineInstr * SuccLRDef = SearchForDef ( Start , MBB -> end ( ) , <STR_LIT> ) ; if ( SuccLRDef && ! IsMoveLR ( SuccLRDef , CountReg ) ) SuccLRDef = nullptr ; if ( SuccLRDef ) { MachineBasicBlock :: iterator End ( SuccLRDef ) ; if ( ! SearchForDef ( Start , End , CountReg ) ) { return SuccLRDef ; } else SuccLRDef = nullptr ; } if ( PredLRDef


<s> Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONDataInsn = insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return


<s> SDLoc dl ( Op ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> ,


<s> if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] =


<s> I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! Subtarget . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool RestrictR15 = FlagRestrictR15 ; assert ( FlagUseZeroBasedSandbox || RestrictR15 ) ; if ( Subtarget . isTargetNaCl64 ( ) ) { if ( RestrictR15 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; const bool RestrictR11 = FlagHideSandboxBase && ! FlagUseZeroBasedSandbox ; if ( RestrictR11 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } return Reserved


<s> const TargetRegisterClass * TRC , * TRCsp ; if ( Size == <NUM_LIT> ) { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } else { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; MRI . constrainRegClass ( scratch , TRCsp ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; MRI . constrainRegClass ( incr , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( incr ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , scratch ) . addReg ( oldval ) . addReg ( incr ) . addImm ( Cond ) ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch


<s> if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add

( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ;


<s> if ( Kind != k_Register || Reg . Kind

!= RegKind :: SVEDataVector ) return DiagnosticPredicateTy :: NoMatch ;


<s> rtx addr = XEXP ( op , <NUM_LIT> ) ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < <NUM_LIT> )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , Address , STI , O ) && ! print<ISA_LIT>AliasInstr ( MI , STI , O ) ) printInstruction


<s> if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < <NUM_LIT> ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! ( * targetm . binds_local_p ) ( function ) ) return false ; return


<s> void EmitARM64WinCFISaveRegX ( unsigned Reg , int Offset )


<s> assert ( SrcVT . getVectorNumElements ( ) == ShuffleMask . size ( ) && <STR_LIT> ) ; assert ( Subtarget . getTargetLowering ( ) -> isShuffleMaskLegal ( ShuffleMask , SrcVT ) && <STR_LIT> ) ; if ( SrcVT . getScalarSizeInBits ( ) == <NUM_LIT> ||

! Subtarget . hasAVX2 ( ) ) return false ;


<s> pat = vec_sel ( ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , vec_sr ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) ) ; return ( ( qword ) ( vec_perm ( vec_perm ( a , b , pattern ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS &&


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None


<s> MIB . addFrameIndex ( AM . Base . FrameIndex ) ; } MIB . addImm ( AM . Scale ) . addReg ( AM . IndexReg ) ; if ( AM . GV ) MIB . addGlobalAddress ( AM . GV , AM . Disp ,


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; Out . EmitBundleLock (


<s> const <ISA_LIT>TargetMachine & getTargetMachine ( ) { return static_cast < const <ISA_LIT>TargetMachine & > (


<s> getTargetStreamer ( ) . emitARM64WinCFIContext ( ) ; return


<s> void addKind ( <STR_LIT> Value ) { AlignBranchKind |=


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Pg = N -> getOperand ( <NUM_LIT> ) ; if ( ( Pg . getOpcode ( ) == <STR_LIT> ) && ( Pg . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) ) return DAG . getNode ( PredOpc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT>

) , Pg , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; <ISA_LIT>GOTEntry * got = NULL ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += <STR_LIT> ; } return


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) != - <NUM_LIT> ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB