<s> } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * <NUM_LIT> ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg ,


<s> __vector signed short w ; w = ( __vector signed short ) vec_splats ( __w ) ; return ( __m64 ) ( ( __vector long long ) w ) [ <NUM_LIT> ] ; __m64_union __res ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT>


<s> uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer ,


<s> machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ; if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee )

) XEXP ( mem , <NUM_LIT> ) = force_reg ( mode , callee ) ;


<s> rtx op1 = XEXP ( comparison , <NUM_LIT> ) ; rtx_insn * seq , * last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 ) ; seq = get_insns ( ) ; end_sequence ( )


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask .


<s> if ( V0 . getNode ( ) == <NUM_LIT> ) { V0 = Elt . getOperand ( <NUM_LIT> ) ; V0NumElts = V0 . getValueType ( ) . getVectorNumElements ( ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V0 ) { Mask [ i ] = ( cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; continue ; } else if ( V1 . getNode ( ) == <NUM_LIT> ) { V1 = Elt . getOperand ( <NUM_LIT> ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V1 ) { unsigned Lane = cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Mask [ i ] = ( Lane + V0NumElts ) ; continue ; } else { return false


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorList ( unsigned RegNum , unsigned Count , unsigned NumElements , char ElementKind , bool IsSVE , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorList , Ctx ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . NumElements = NumElements ; Op -> VectorList . ElementKind = ElementKind


<s> args . reserve ( nargs ) ; for ( unsigned int i = <NUM_LIT> ; i < nargs ; ++ i ) args . quick_push ( expand_normal ( CALL_EXPR_ARG ( call_expr , i ) ) ) ; return base -> expand (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; unsigned Flags = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) | getDefRegState ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; MIB . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , Flags ) ; } if ( NewOpc == <STR_LIT> ) MIB . addReg ( SrcReg , RegState


<s> unsigned sy = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <ISA_LIT>ValToCondCode ( cf , isIntegerBCKind ( MI ) ) ) ) ; DecodeStatus status ; if ( cy ) { status = DecodeI64RegisterClass ( MI , sy , Address , Decoder


<s> uint64_t SrlImm = <NUM_LIT> ; if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , SrlImm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , SrlImm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; } else if ( isOpcWithIntImmediate ( Op0 , <STR_LIT> , SrlImm ) ) { Opd0 = Op0 -> getOperand (


<s> if ( tmp == nullptr ) op1 = validize_mem ( force_const_mem ( mode , op1 ) ) ; else op1 = tmp ; } } if ( can_create_pseudo_p ( ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && VECTOR_MODE_P ( mode ) && ( MEM_P ( op1 ) && SYMBOL_REF_P ( XEXP ( op1 , <NUM_LIT> ) ) && CONSTANT_POOL_ADDRESS_P ( XEXP ( op1 , <NUM_LIT> ) ) ) ) { rtx first = ix86_broadcast_from_constant ( mode , op1 ) ; if ( first != nullptr ) { op1 = gen_reg_rtx ( mode ) ; if ( FLOAT_MODE_P ( mode ) || ( ! TARGET_64BIT && GET_MODE_INNER ( mode ) == DImode ) ) first = force_const_mem ( GET_MODE_INNER ( mode ) , first ) ; bool ok = ix86_expand_vector_init_duplicate ( false , mode , op1 , first ) ; gcc_assert ( ok ) ; emit_move_insn ( op0 , op1 ) ; return ; } } if ( can_create_pseudo_p ( ) && SSE_REG_MODE_P ( mode ) && ( ( MEM_P ( op0 ) && ( MEM_ALIGN ( op0 ) < align ) ) || ( MEM_P ( op1 ) && ( MEM_ALIGN ( op1 ) < align ) ) ) ) { rtx tmp [ <NUM_LIT> ] ; if ( ! register_operand ( op0 , mode ) && ! register_operand ( op1 , mode ) ) { rtx scratch = ix86_gen_scratch_sse_rtx ( mode ) ; emit_move_insn ( scratch , op1 ) ; op1 = scratch ; } tmp [ <NUM_LIT> ] = op0 ; tmp [ <NUM_LIT> ] = op1 ; ix86_expand_vector_move_misalign ( mode , tmp ) ; return ; } if ( mode == V1TImode && SUBREG_P ( op1 ) && GET_MODE ( SUBREG_REG ( op1 ) ) == TImode && TARGET_64BIT &&

TARGET_SSE && can_create_pseudo_p ( ) ) {


<s> return ( int32x4_t ) __builtin_neon_vsublsv4hi


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ,


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( )


<s> static Optional < MCPhysReg > tryToFindRegisterToRename ( const MachineFunction & MF , Register Reg , LiveRegUnits & DefinedInBB , LiveRegUnits & UsedInBetween , SmallPtrSetImpl < const TargetRegisterClass * > & RequiredClasses , const TargetRegisterInfo * TRI ) { const MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; auto AnySubOrSuperRegCalleePreserved = [ & MF , TRI ] ( MCPhysReg PR ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ & MF , TRI ] ( MCPhysReg SubOrSuper ) { return TRI -> isCalleeSavedPhysReg ( SubOrSuper , MF ) ; } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI ] ( const TargetRegisterClass * C ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ C , TRI ] ( MCPhysReg SubOrSuper ) { return C == TRI -> getMinimalPhysRegClass ( SubOrSuper ) ; } ) ; } ) ; } ; auto * RegClass = TRI -> getMinimalPhysRegClass ( Reg ) ; for ( const MCPhysReg & PR : *


<s> MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( V2 . isUndef ( ) || isZerosVector ( V2 . getNode ( ) ) ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getBuildVector ( IndexVT , DL , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; } else


<s> d . vmode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; int ei = INTVAL ( e ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : d . one_vector_p = false ; if ( ! rtx_equal_p ( op0 , op1 ) ) break ; case <NUM_LIT> : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - <NUM_LIT> ; d . op0 = op1 ; d . one_vector_p = true ; break ; case <NUM_LIT> : d . op1 = op0 ; d . one_vector_p =


<s> return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister ( RegIdx


<s> SDValue Swap = DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode >


<s> assert ( ( ( Val && ! VRegs . empty ( ) ) || ( ! Val && VRegs . empty ( ) ) ) && <STR_LIT> ) ; if ( VRegs . size ( ) > <NUM_LIT> ) return false ; MIRBuilder . buildInstr


<s> __builtin_sh_media_STLO_Q ( p , k ) ; __builtin_sh_media_STLO_Q ( p + <NUM_LIT> , k ) ; __builtin_sh_media_STHI_Q ( p


<s> else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) { if ( ! isScalarVecReg ( CopySrcReg ) ) SwapVector [ VecIdx ] . MentionsPhysVR = <NUM_LIT> ; return CopySrcReg ; } return lookThruCopyLike ( CopySrcReg , VecIdx


<s> const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; unsigned Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFNEGorFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op


<s> static int stackSlotSize ( ) { return <NUM_LIT>


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> && ( Subtarget . hasAVX2 ( ) || MayFoldLoad ( Op0 . getOperand ( <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && ( Subtarget . hasAVX2 ( ) || ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && MayFoldLoad ( Op0 . getOperand ( <NUM_LIT> ) ) ) ) && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT . getScalarType ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } if ( llvm :: all_of ( Ops , [ Op0 ] ( SDValue Op ) { return Op . getOpcode ( ) == Op0 . getOpcode ( ) ; } ) ) { unsigned NumOps = Ops . size ( ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : if ( NumOps == <NUM_LIT> && VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SmallVector < SDValue , <NUM_LIT> > LHS , RHS ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { LHS . push_back ( Ops [ i ] . getOperand ( <NUM_LIT> ) ) ; RHS . push_back ( Ops [ i ] . getOperand (


<s> use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv8si_0 ; break ; case E_V8SFmode : use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv8sf_0 ; break ; case E_V4DFmode : use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv4df_0 ; break ; case E_V4DImode : use_vector_set = TARGET_AVX && TARGET_64BIT ; gen_vec_set_0 = gen_vec_setv4di_0 ; break ; case E_V16SImode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16si_0 ; break ; case E_V16SFmode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16sf_0 ; break ; case E_V8DFmode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8df_0 ; break ; case E_V8DImode : use_vector_set = TARGET_AVX512F && TARGET_64BIT && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8di_0 ; break ; case E_V8HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8hf_0 ; break ; case E_V16HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16hf_0 ; break ; case E_V32HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv32hf_0 ; break ; case E_V32HImode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv32hi_0 ; default : break ; } if ( use_vector_set ) { if ( gen_vec_set_0 && one_var == <NUM_LIT> ) { var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; emit_insn ( gen_vec_set_0 ( target , CONST0_RTX ( mode ) , var ) ) ; return true ; } emit_insn ( gen_rtx_SET ( target , CONST0_RTX ( mode ) ) ) ; var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } switch ( mode ) { case E_V2SFmode : case E_V2SImode : if ( ! mmx_ok ) return false ; case E_V2DFmode : case E_V2DImode : if ( one_var != <NUM_LIT> ) return false ; var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_CONCAT ( mode , var , CONST0_RTX ( GET_MODE_INNER ( mode ) ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; return true


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( N -> getNumOperands ( ) != <NUM_LIT> && N -> getNumOperands ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; if ( cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) >= e ) return false ; } return


<s> DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( SrcReg ) ; Register DstReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode ) , DstReg ) . addReg ( SrcReg ) . setMIFlags ( MI .


<s> if ( BW > <NUM_LIT> ) return false ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } int TestBit = - <NUM_LIT> ; bool IsCmpNE ; if ( ( Predicate == CmpInst :: ICMP_EQ ) || ( Predicate == CmpInst :: ICMP_NE ) ) { if ( const auto * C = dyn_cast < Constant > ( LHS ) ) if ( C -> isNullValue ( ) ) std :: swap ( LHS , RHS ) ; if ( ! isa < Constant > ( RHS ) ) return false ; if ( ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; if ( const auto * AI = dyn_cast < BinaryOperator > ( LHS ) ) if ( AI -> getOpcode ( ) == Instruction :: And && isValueAvailable ( AI ) ) { const Value * AndLHS = AI -> getOperand ( <NUM_LIT> ) ; const Value * AndRHS = AI -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( AndLHS , AndRHS ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndRHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) { TestBit = C -> getValue ( ) . logBase2 ( ) ; LHS = AndLHS ; } } if ( VT == <STR_LIT> ) TestBit = <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_NE ; } else if ( Predicate == CmpInst :: ICMP_SLT ) { if ( ! isa < Constant > ( RHS ) ) return false ; if ( ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = true ; } else if ( Predicate == CmpInst :: ICMP_SGT ) { if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != - <NUM_LIT> ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = false


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; emitFrameDirective ( ) ; bool EmitCPLoad = ( MF -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && <ISA_LIT>MFI -> globalBaseRegSet ( ) && <ISA_LIT>MFI -> globalBaseRegFixed ( ) ; if ( <ISA_LIT>NoCpload ) EmitCPLoad = false ; if ( OutStreamer -> hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> >


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AlignedAddr = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned OldVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal0 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB


<s> DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( Amount ) ) { if ( Amount < <NUM_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( - Amount ) ; else if ( Amount > <NUM_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Amount ) ; } else assert ( false


<s> for ( int i = <NUM_LIT> , e = ( int ) VT . getVectorNumElements ( ) ; i != e ; ++ i ) if ( Mask [ i ] == i ) ++ CorrectPosV1 ; else if ( Mask [ i ] == i + <NUM_LIT> ) ++ CorrectPosV2 ; if ( CorrectPosV1 == <NUM_LIT> || CorrectPosV2 == <NUM_LIT> ) return


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment (


<s> static SDValue concat256BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) { SDValue V = insert256BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT>


<s> if ( Offset > <NUM_LIT> ) Offset -= OffsetStride ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit , false ) ; if ( Paired !=


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { return false


<s> const InlineAsmIdentifierInfo & Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( ! PtrInOperand ) Size = SM . getElementSize ( ) << <NUM_LIT> ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return Error ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( ) , ErrMsg ) ) return Error ( Start , ErrMsg ) ; if ( isParsingMSInlineAsm ( ) ) return CreateMemForMSInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) , Operands ) ; if ( Parser . isParsingMasm ( ) && is64BitMode (


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat


<s> return __builtin_aarch64_sqrshlqi ( __a ,


<s> hasConsumedDollar = false ; Parser . Lex ( ) ; return MatchOperand_Success ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; if ( Kind == <STR_LIT> ) { if ( RegNum != <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = <NUM_LIT> ; } int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( Kind ) ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; hasConsumedDollar = false ; Parser . Lex ( ) ; if ( ( RegKind == <STR_LIT> ) && ( getLexer ( ) . is ( AsmToken :: LParen ) ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( parseRegs ( Operands , RegKind ) != MatchOperand_Success ) return MatchOperand_NoMatch ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return MatchOperand_NoMatch ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return


<s> vld2q_u16 ( const uint16_t * __a ) { uint16x8x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t


<s> Value * <ISA_LIT>IREmitter :: visitMOVDDUP (


<s> if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . parseAbsoluteExpression ( Value ) ) return nullptr ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr


<s> static void write_autogenerated_header ( FILE * file ) { fprintf ( file ,


<s> STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg1 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_unpackv1ti || icode == CODE_FOR_unpackkf || icode == CODE_FOR_unpacktf || icode == CODE_FOR_unpackif || icode == CODE_FOR_unpacktd ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg1 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat


<s> unsigned Hi4 = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; unsigned Lo12 = Value & <NUM_LIT> ; Value = ( Hi4 << <NUM_LIT>


<s> MVT MaskTy = Mask . getSimpleValueType ( ) ; SDLoc dl ( N ) ; SDNodeTreeBuilder b ( & DAG , dl ) ; if ( DCI . isBeforeLegalize ( ) ) { if ( MaskTy == <STR_LIT> && VT == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return b . IFH1 ( Mask , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( MaskTy == <STR_LIT> && VT == <STR_LIT> && ( Subtarget -> hasAVX2 ( ) || Subtarget -> hasAVX ( ) ) ) { Mask = DAG . getNode ( <STR_LIT> , dl , VT , Mask ) ; DCI . AddToWorklist ( Mask . getNode ( )


<s> operands [ <NUM_LIT> ] = GEN_INT ( right ) ; gen_shifty_hi_op ( LSHIFTRT , operands ) ; } if ( first > <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( first ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; total_shift -= first ; mask <<= first ; } if ( first >= <NUM_LIT> ) emit_insn ( mask <= <NUM_LIT> ? gen_zero_extendqisi2 ( dest , gen_lowpart ( QImode , dest ) ) : gen_zero_extendhisi2 ( dest , gen_lowpart ( HImode , dest ) ) ) ; if ( total_shift > <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( total_shift ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; } break ; } case <NUM_LIT> : shift_gen_fun = gen_shifty_op ; case <NUM_LIT> : if ( mask & ( ( HOST_WIDE_INT ) <NUM_LIT> << ( <NUM_LIT> - total_shift ) ) ) mask |= ( HOST_WIDE_INT ) ~ <NUM_LIT> << ( <NUM_LIT> - total_shift ) ; case <NUM_LIT> : if ( currently_expanding_to_rtl || reload_in_progress || reload_completed ) { rtx operands [ <NUM_LIT> ] ; gcc_assert ( kind <= <NUM_LIT> ) ; if ( right ) { emit_insn ( gen_lshrsi3 ( dest , source , GEN_INT ( right ) ) ) ; source = dest ; } emit_insn ( gen_andsi3 ( dest , source , GEN_INT ( mask ) ) ) ; if ( total_shift ) { operands [ <NUM_LIT> ] = dest ; operands [ <NUM_LIT> ] = dest ; operands [ <NUM_LIT> ] = GEN_INT ( total_shift ) ; shift_gen_fun ( ASHIFT , operands ) ; } break ; } else { int neg = <NUM_LIT> ; if ( kind != <NUM_LIT> && total_shift < <NUM_LIT> ) { neg = - ext_shift_amounts [ total_shift ] [ <NUM_LIT> ] ; if ( neg > <NUM_LIT> ) neg -= ext_shift_amounts [ total_shift ] [ <NUM_LIT>


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt ::

None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ;


<s> } if ( GET_CODE ( x ) == PLUS ) { rtx arg1 = XEXP ( x , <NUM_LIT> ) ; rtx arg2 = XEXP ( x , <NUM_LIT> ) ; rtx index = NULL_RTX ; if ( REG_P ( arg1 ) && RTX_OK_FOR_BASE ( arg1 , strict ) ) index = arg2 ; else if ( REG_P ( arg2 ) && RTX_OK_FOR_BASE ( arg2 , strict ) ) index = arg1 ; else return false ; switch ( GET_CODE ( index ) ) { case CONST_INT : { HOST_WIDE_INT val = INTVAL ( index ) ; int factor ; if ( val < <NUM_LIT> ) return false ; switch ( GET_MODE_SIZE ( mode ) )


<s> static bool BitsProperlyConcatenate ( const APInt & A , const APInt & B ) { unsigned LastActiveBitInA = A . countTrailingZeros


<s> return __builtin_mve_vmulq_sv16qi ( __a ,


<s> if ( In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride )


<s> unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> shmask = vec_cmple ( lshift , shmax ) ; result = vec_sl ( ( __v8hu ) __A , lshift ) ; result = vec_sel ( ( __v8hu ) shmask , result , shmask ) ; return ( __m128i ) result


<s> F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthBitcastToSVE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto SrcOp = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerDstVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT ContainerSrcVT = getContainerForFixedLengthVector ( DAG , SrcOp . getValueType ( ) ) ; SrcOp = convertToScalableVector ( DAG , ContainerSrcVT


<s> int32_t tmp = ( int32_t ) MO1 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp & <NUM_LIT> ; return Value


<s> inline vector unsigned short vec_vmrghh ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned short ) __builtin_altivec_vmrghh ( ( vector signed short ) a1 , ( vector signed short


<s> return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: ICmp : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse


<s> void ExpandPseudo :: expandStoreACC ( MachineBasicBlock & MBB , Iter I , unsigned MFHiOpc , unsigned MFLoOpc , unsigned RegSize ) { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I ->

getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> if ( code == MULT && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && exact_log2 ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) > <NUM_LIT> ) return XEXP ( op , <NUM_LIT> ) ; else if ( code == ROTATE && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return XEXP ( op , <NUM_LIT> ) ; else if ( code == ROTATERT || code == ASHIFT || code == LSHIFTRT || code == ASHIFTRT ) { if ( ! CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) * shift_reg = XEXP ( op , <NUM_LIT> ) ; return XEXP ( op , <NUM_LIT> ) ; } return


<s> } uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == <NUM_LIT> || ( AM . Scale > <NUM_LIT> && ( uint64_t )


<s> vmovl_high_u32 ( uint32x4_t a ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> void <ISA_LIT>LinuxAsmPrinter :: emitGNUAttributes ( Module & M ) { Metadata * MD = M . getModuleFlag ( <STR_LIT> ) ; MDString * FloatABI = dyn_cast_or_null < MDString > ( MD ) ; if ( ! FloatABI ) return ; StringRef flt = FloatABI -> getString ( ) ; if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP | Val_GNU_Power_ABI_LDBL_IBM128 ) ; else if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP | Val_GNU_Power_ABI_LDBL_IEEE128 ) ; else if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP


<s> void <ISA_LIT>TargetLowering :: Set<ISA_LIT>16LibcallName ( RTLIB :: Libcall l , const char * Name ) { setLibcallName ( l


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; SDValue BrCode = DAG . getConstant ( getFPBranchCodeFromCond ( CC )


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) )


<s> return __builtin_mve_vqrshlq_sv4si ( __a ,


<s> if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) && ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetWindows ( ) ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT>


<s> const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned <ISA_LIT>16SPAliasReg = <ISA_LIT>FI -> get<ISA_LIT>16SPAliasReg ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> )

, <ISA_LIT>16SPAliasReg ) . addReg ( <STR_LIT> ) ;


<s> return InsertSubVector ( Result , Vec , IdxVal ,


<s> const MCOperand & MOImm = MI -> getOperand ( OpNum ) ; int32_t Imm = unpackSignedImm ( <NUM_LIT> , MOImm


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( VT . getSizeInBits ( ) / <NUM_LIT> > LS -> getAlignment ( ) ) { assert ( <STR_LIT> ) ; if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder


<s> if ( ISA_HAS_MSA ) sizes -> safe_push


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) == <STR_LIT> ; Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType


<s> if ( TM . getCodeModel ( ) != CodeModel :: Small ) return <NUM_LIT> ; <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( GV , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == nullptr ) return AM . Base . Reg ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static && TLI . getPointerTy ( DL ) == <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addGlobalAddress ( GV ) ; } else { unsigned Opc = TLI . getPointerTy ( DL ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> )


<s> static SDValue lowerVectorShuffleAsElementInsertion ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT ExtVT = VT ; MVT EltVT = VT . getVectorElementType ( ) ; int V2Index = find_if ( Mask , [ & Mask ] ( int M ) { return M >= ( int ) Mask . size ( ) ; } ) - Mask . begin ( ) ; bool IsV1Zeroable = true ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( i != V2Index && ! Zeroable [ i ] ) { IsV1Zeroable = false ; break ; } SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue (


<s> return DisableFramePointerElim ( MF ) || MFI


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; Register SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++


<s> static bool mayTailCallThisCC ( CallingConv :: ID CC ) { switch ( CC ) { case CallingConv :: C : case CallingConv :: Win64 : case CallingConv :: <ISA_LIT>_64_SysV : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: Swift : return true


<s> else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE


<s> bool useAA ( ) const override { return isCortexA53 ( )


<s> return ( int16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi * )


<s> if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( <STR_LIT> ( Load -> getBasePtr ( ) . getOpcode ( ) ) ) return false ; if ( <STR_LIT> ( Store -> getBasePtr ( ) .


<s> Set<ISA_LIT>16LibcallName ( RTLIB :: SINTTOFP_I32_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: SINTTOFP_I32_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: UINTTOFP_I32_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: UINTTOFP_I32_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OEQ_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OEQ_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: UNE_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: UNE_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OGE_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OGE_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OLT_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OLT_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OLE_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OLE_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OGT_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: OGT_F64 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB :: UO_F32 , <STR_LIT> ) ; Set<ISA_LIT>16LibcallName ( RTLIB ::


<s> SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * Hi64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegEven ) ; SDNode * Lo64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegOdd ) ; unsigned alignment = StNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue OutChains [


<s> FunctionPass * llvm :: createMLxExpansionPass ( ) { return new MLxExpansion


<s> MF = & Func ; TM = & Func . getTarget ( ) ; const <ISA_LIT>Subtarget & ST = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return


<s> void add<ISA_LIT>SOImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> return parseAddress ( Operands , <STR_LIT> ,


<s> if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg (


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getTarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; unsigned TotalSkipped =


<s> unsigned VReg = <NUM_LIT> ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , i , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; const TargetInstrDesc & Desc = MI . getDesc ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( Desc . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , TmpReg , FrameReg , Offset , false , TII , * this , dl ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , TmpReg , FrameReg , Offset , TII , * this , dl ) ; } MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister (


<s> int SlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , FPDiff - SlotSize , false ) ; EVT VT = Is64Bit ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , VT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack (

NewReturnAddrFI ) , false , false , <NUM_LIT> ) ;


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp , rtx pushed ) { rtx second , bypass ; rtx label = NULL_RTX ; rtx condition ; int bypass_probability = - <NUM_LIT> , second_probability = - <NUM_LIT> , probability = - <NUM_LIT> ; rtx i ; if ( target2 != pc_rtx ) { rtx tmp = target2 ; code = reverse_condition_maybe_unordered ( code ) ; target2 = target1 ; target1 = tmp ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp , & second , & bypass ) ; if ( pushed ) ix86_free_from_memory ( GET_MODE ( pushed ) ) ; if ( split_branch_probability >= <NUM_LIT> ) { probability = split_branch_probability ; if ( bypass ) bypass_probability = <NUM_LIT> ; if ( second ) second_probability = <NUM_LIT> ; } if ( bypass != NULL_RTX ) { label = gen_label_rtx ( ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , bypass , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; if ( bypass_probability >= <NUM_LIT> ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB

, GEN_INT ( bypass_probability ) , REG_NOTES ( i ) ) ;


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getHighBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt LowMask = APInt :: getLowBitsSet ( LowWidth , <NUM_LIT> ) ; unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LowMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , HighMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ; unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits


<s> } ; auto ExpandLoopEnd = [ this ] ( MachineLoop * ML , MachineInstr * Dec , MachineInstr * End ) { MachineBasicBlock * MBB = End -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; End -> eraseFromParent ( ) ; Dec -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( Revert ) { if ( Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( Start ) ; else Start -> eraseFromParent ( ) ; RevertLoopDec ( Dec ) ; RevertLoopEnd ( End ) ; } else { Start = ExpandLoopStart ( ML , Start ) ; RemoveDeadBranch (


<s> RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Val = getv64i1Argument ( VA , RVLocs [ ++ I ] , Chain , DAG , dl , Subtarget , & InFlag ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && ( VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) ) { if ( VA . getValVT ( ) . isVector ( ) && ( ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) ) ) { Val = lowerRegToMasks ( Val , VA . getValVT ( ) , VA . getLocVT (


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , Val . getValueType ( ) ) ; Val = convertToScalableVector ( DAG , ContainerVT , Val ) ; switch ( ContainerVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , Val ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , Val


<s> static const EVT VTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [


<s> else if ( ( VT == <STR_LIT> && Subtarget -> hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasAVX ( ) ) ) RecipOp = <STR_LIT> ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) ,


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return


<s> BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( j ) ) ; if ( ! BVN0 || ! BVN1 ) continue ; bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ; ++ k ) { ConstantSDNode * CN0 = dyn_cast < ConstantSDNode > ( BVN0 -> getOperand ( k ) ) ; ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( BVN1 -> getOperand ( k ) ) ; if ( ! CN0 || ! CN1 || CN0 -> getZExtValue ( ) != ( BitMask & ~ CN1 -> getZExtValue ( ) ) ) { FoundMatch = false ; break ; } } if ( FoundMatch ) return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( BVN0 , <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> - i ) , N1 -> getOperand ( <NUM_LIT> - j ) ) ; } return SDValue (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo


<s> bool getFPImmIsExact ( ) const { assert ( Kind == k_FPImm && <STR_LIT> ) ; return FPImm .


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR ) ; initializeEvexToVexInstPassPass ( PR ) ; initializeFixupLEAPassPass (


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ in_section = in_sdata ; \

fprintf ( asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP ) ; \ } \ }


<s> gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true


<s> return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm ::


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> bool fixCallImmediates ( ) const { return FixCallImmediates


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isSimple ( ) || Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Op . getValueType ( ) . is64BitVector ( ) && ! Op . getValueType ( ) . is128BitVector ( ) ) return SDValue ( ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> && ( FloatBits != <NUM_LIT> || ! Subtarget -> hasFullFP16 ( ) ) ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> )


<s> return ( vector unsigned int ) __builtin_altivec_vmaxuw ( ( vector signed int )


<s> switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SrcReg ) ; return ResultReg ; } case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; break ; } } if ( VT == <STR_LIT> && Opc


<s> } else { const TargetRegisterClass * TRC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; VR = MRI -> createVirtualRegister ( TRC ) ; Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB ) . addReg ( <NUM_LIT> ) ; else BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB , Subtarget . classifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( Op ) ) ; addFrameReference ( MIB , FI ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ; } return


<s> case <STR_LIT> : Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare . getOpcode ( ) , Type , & Compare ) ; if ( ! FusedOpcode ) return false ; Register SrcReg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( ( Type == <STR_LIT> || Type == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> removeOperand ( CCUse ) ; if ( Type == <STR_LIT> ) Branch -> removeOperand ( <NUM_LIT> ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> removeOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode ==


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; O << '#' ; if ( Op . getImm ( ) < <NUM_LIT> ) O << '-' << ( - Op . getImm


<s> if ( Subtarget -> isThumb1Only ( ) ) EmitAlignment ( <NUM_LIT> ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel ( JTI ) ; OutStreamer -> EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; OutStreamer -> EmitDataRegion ( OffsetWidth == <NUM_LIT> ? MCDR_DataRegionJT8 : MCDR_DataRegionJT16 ) ; for ( auto MBB : JTBBs ) { const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; MCSymbol * TBInstPC = GetCPISymbol ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; const MCExpr * Expr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( TBInstPC , OutContext ) , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; Expr = MCBinaryExpr :: createSub ( MBBSymbolExpr , Expr , OutContext ) ; Expr = MCBinaryExpr :: createDiv ( Expr , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( Expr , OffsetWidth


<s> SDValue Value = Op -> getOperand ( <NUM_LIT> ) ; EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDValue Result = DAG . getNode ( Opc , DL , ResTy ,


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_Success ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok (


<s> static bool IsVPNOTEquivalent ( MachineInstr & Cond , MachineInstr & Prev ) { assert ( IsVCMP ( Cond . getOpcode ( ) ) && IsVCMP ( Prev . getOpcode ( ) ) ) ; if ( Cond . getOpcode ( ) != Prev . getOpcode ( ) ) return false ; MachineOperand & CondOP1 = Cond . getOperand ( <NUM_LIT> ) , & CondOP2 = Cond


<s> switch ( MI -> getOperand ( Op ) . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG .


<s> unsigned int regno ; switch ( mode ) { case E_HFmode : case E_HCmode : case E_SFmode : case E_SCmode : case E_DFmode : case E_DCmode : case E_TFmode : case E_SDmode : case E_DDmode : case E_TDmode : regno = FIRST_SSE_REG ; break ; case E_XFmode : case E_XCmode : regno =


<s> return aarch64_classify_vector_mode ( mode )


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true


<s> for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : make_range ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canDefBePartOfLOH ( MI ) ) { const MachineOperand & Def = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Def . isReg ( ) && Def . isDef ( ) && <STR_LIT> ) ; assert ( Op . isReg ( ) && Op . isUse ( ) && <STR_LIT> ) ; int DefIdx = mapRegToGPRIndex ( Def . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( Op


<s> GetInstSeqLs ( Imm & ~ <NUM_LIT> , RemSize , SeqLs ) ; AddInstr ( SeqLs , Inst ( ORi , Imm &


<s> MCOperand hi = create<ISA_LIT>MCOperand ( HiKind , GOTSym , OutContext ) ; MCOperand lo = create<ISA_LIT>MCOperand ( LoKind , GOTSym , OutContext ) ; emitLEAzzi ( OutStreamer , lo , RD , STI ) ; MCOperand M032 = MCOperand :: createImm ( M0 ( <NUM_LIT> ) ) ; emitANDrm ( OutStreamer , RD , M032 , RD


<s> static tree aarch64_stack_protect_guard


<s> assert ( VT . is256BitVector ( ) && VT . isInteger ( ) && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const


<s> unsigned mergedOpcode ( unsigned OldOpcode , bool ImmediateOffset ) { switch ( OldOpcode ) { case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> MachineInstr * FixupBWInstPass :: tryReplaceLoad ( unsigned New32BitOpcode , MachineInstr * MI ) const { unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI -> getNumOperands


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT = <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( ( VT == <STR_LIT> ) || VT . is64BitVector ( ) ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT>


<s> SDValue TWOHW = DAG . getConstantFP ( ( double ) ( <NUM_LIT> << <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWordMask ) ; if ( IsStrict ) { SDValue fHI = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , HI } ) ; fHI = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { fHI . getValue ( <NUM_LIT> ) , fHI , TWOHW } ) ; SDValue fLO = DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , LO } ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , fHI . getValue ( <NUM_LIT> ) , fLO . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { Chain , fHI , fLO } ) ; } SDValue fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI ) ; fHI = DAG . getNode ( <STR_LIT> , DL


<s> Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && Operands . size ( ) == <NUM_LIT> && ( Name == <STR_LIT> || Name == <STR_LIT> ) ) { std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; } if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) { if ( Operands . size ( ) != <NUM_LIT> ) return false ; <ISA_LIT>Operand & EHOp = ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ; if ( EHOp . isU1Imm ( ) && EHOp . getImm ( ) == <NUM_LIT> ) Operands . pop_back ( ) ; } return


<s> unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , EltTy ) ) ; SDValue SGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT> , dl , VT , & Sz [ <NUM_LIT> ] , NumElts ) ) ; SmallVector < SDValue , <NUM_LIT> > Amt ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - Lg2 , EltTy ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , dl , VT , SGN , DAG . getNode ( <STR_LIT> , dl , VT , & Amt [ <NUM_LIT> ] , NumElts ) ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SmallVector < SDValue , <NUM_LIT> > Lg2Amt ( NumElts , DAG . getConstant ( Lg2 , EltTy ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , dl , VT , ADD , DAG . getNode ( <STR_LIT> , dl , VT , & Lg2Amt [ <NUM_LIT> ] , NumElts ) ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG . getConstant ( <NUM_LIT> , EltTy ) ) ; SDValue Zero = DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , NumElts ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Zero ,


<s> bool haveFeatures ( FeatureBitset ActiveFeatures ) const { return ( FeaturesRequired & ActiveFeatures


<s> bool useIndirectThunkBranches ( ) const


<s> switch ( TLInfo . getTargetMachine ( ) . getCodeModel


<s> bool allowsUnalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = <NUM_LIT> , bool * Fast = nullptr ) const override { if ( RequireStrictAlign )


<s> unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPR64spRegisterClass ( Inst , Rn


<s> Value * <ISA_LIT>IREmitter :: visitVBSL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; const <ISA_LIT>RegisterInfo * <ISA_LIT>RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned StackAlignment = <ISA_LIT>RI -> getStackAlignment ( ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) if ( RI . getRegClass (

RegNum ) -> getAlignment ( ) > StackAlignment ) {


<s> if ( Domain == <STR_LIT> ) { if ( ++ Skip == <NUM_LIT> ) pushStack ( <NUM_LIT> ) ; } else { Skip = <NUM_LIT> ; unsigned MulOpc , AddSubOpc ; bool NegAcc , HasLane ; if ( ! TII -> isFpMLxInstruction ( MCID . getOpcode ( ) , MulOpc , AddSubOpc , NegAcc , HasLane ) || ! FindMLxHazard ( MI ) ) pushStack ( MI ) ; else { ExpandFPMLxInstruction ( MBB , MI , MulOpc , AddSubOpc , NegAcc , HasLane ) ; E = MBB . rend ( ) ; Changed = true ; continue ; } } ++ MII


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( get ( <STR_LIT> ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs =


<s> Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; COMMDirectiveTakesAlignment = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: SjLj ; AbsoluteEHSectionOffsets = false


<s> static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: CreateReg ( FirstReg + getVectorListStart


<s> uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } } if ( RHSC && RHSC -> getSExtValue ( ) == - <NUM_LIT> && CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> && ProduceNonFlagSettingCondBr ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC ,


<s> static __inline qword si_ilh ( signed short imm ) { return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm ) ) ,


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: aarch64 , true > X ( The<ISA_LIT>Target ,


<s> unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ) ; } assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> ,


<s> if ( Op0Reg == <NUM_LIT> ) return false ; if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( DL . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , CurDbgLoc , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT , Subtarget ) ; if ( CompareOpc == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( Op1 ) ; if ( Op1Reg == <NUM_LIT> )


<s> CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( isVCTP ( MI ) ) VCTP = MI ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) return false ; bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate


<s> bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= <NUM_LIT> && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; return <STR_LIT>


<s> unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo


<s> return ( __m128i ) __builtin_ia32_pmovusdw256_mask ( ( __v8si ) __A , (

__v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4 ; else if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4_ByVal ; else if ( Flag ==


<s> } if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : { MachineModuleInfoCOFF & MMICOFF = MF . getMMI ( ) . getObjFileInfo < MachineModuleInfoCOFF > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMICOFF .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Callee , Sym ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Callee ) ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Sym ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT> ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( OutStreamer , TLSDescCall ) ; MCInst BLR ; BLR . setOpcode ( <STR_LIT> ) ; BLR . addOperand ( Callee ) ; EmitToStreamer ( OutStreamer , BLR ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI ) ; case TargetOpcode ::


<s> static SDValue GENLowerMUL ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT>


<s> const MCExpr * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( MCConstantExpr :: create ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) , getContext ( ) ) , Inst . getLoc ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } else { const MCExpr * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , Inst . getLoc ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } Out . emitInstruction ( Inst , getSTI (


<s> case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_ZNVER4 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_SKYLAKE : case PROCESSOR_SKYLAKE_AVX512 : case PROCESSOR_CASCADELAKE : case PROCESSOR_CANNONLAKE : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return <NUM_LIT> ; case PROCESSOR_ICELAKE_CLIENT : case PROCESSOR_ICELAKE_SERVER : case PROCESSOR_TIGERLAKE : case PROCESSOR_COOPERLAKE : case PROCESSOR_ROCKETLAKE : return <NUM_LIT> ; case PROCESSOR_SAPPHIRERAPIDS : return


<s> for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromNode ( * FlagUI ) ; switch ( CC ) { case <STR_LIT> : case


<s> static void initReachingDef ( const MachineFunction & MF , InstrToInstrs * ColorOpToReachedUses , BlockToInstrPerColor & Gen , BlockToRegSet & Kill , BlockToSetOfInstrsPerColor & ReachableUses , const MapRegToId & RegToId , const MachineInstr * DummyOp , bool ADRPMode ) { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; unsigned NbReg = RegToId . size ( ) ; for ( const MachineBasicBlock & MBB : MF ) { auto & BBGen = Gen [ & MBB ] ; BBGen = make_unique < const MachineInstr * [ ] > ( NbReg ) ; std :: fill ( BBGen . get ( ) , BBGen . get ( ) + NbReg , nullptr ) ; BitVector & BBKillSet = Kill [ & MBB ] ; BBKillSet . resize ( NbReg ) ; for ( const MachineInstr & MI : MBB ) { bool IsADRP = MI . getOpcode ( ) == <STR_LIT> ; if ( IsADRP || ! ADRPMode ) for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ( ! ADRPMode && ! MO . isUse ( ) ) || ( ADRPMode && ( ! IsADRP || ! MO . isDef ( ) ) ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; CurReg = ItCurRegId -> second ; if ( ! BBGen [ CurReg ] && ! BBKillSet . test ( CurReg ) ) getSet ( ReachableUses , MBB , CurReg , NbReg ) . insert ( & MI ) ; if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( &


<s> AsmPrinter :: printPICJumpTableSetLabel ( uid ,


<s> int <ISA_LIT>AsmParser :: matchCPURegisterName ( StringRef Name ) { int CC ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) .

Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return Is64Bit ? <STR_LIT>


<s> return ( __m64 ) __builtin_arm_wcmpgtuh ( ( __v4hi ) __m1 , ( __v4hi )


<s> Instruction * Inst = CS . getInstruction ( ) ; SmallVector < OperandBundleDef , <NUM_LIT> > OpBundles ; CS . getOperandBundlesAsDefs ( OpBundles ) ; SmallVector < Value * , <NUM_LIT> > OptionalArgs ; if ( Personality == EHPersonality :: MSVC_CXX ) { OptionalArgs . push_back ( CxxLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; OptionalArgs . push_back ( emitEHLSDA ( Builder , & F ) ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( CS . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallSite NewCS ; if ( CS . isCall ( ) ) { auto * CI = cast < CallInst > ( Inst ) ; CallInst * NewCI = Builder . CreateCall ( SetJmp3 , Args , OpBundles ) ; NewCI -> setTailCallKind ( CI -> getTailCallKind ( ) ) ; NewCS = NewCI ; } else { auto * II = cast < InvokeInst > ( Inst


<s> if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst .

addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;