<s> rtx x , cond ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; aarch64_emit_load_exclusive ( mode , rval , mem , operands [ <NUM_LIT> ] ) ; cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , operands [ <NUM_LIT> ] ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond ,


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFunnelShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerEXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT_SAT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP16_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerStore ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFaddFsub ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerISNAN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerLRINT_LLRINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget ,


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; FrameReg = ( RegInfo -> needsStackRealignment ( MF ) ) ? RegInfo -> getStackRegister ( ) : RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> enableVPU ( ) ) { for ( MVT VecVT : AllVectorVTs ) addRegisterClass (


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return force_reg ( SImode , x ) ; return x


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable


<s> bool isCPURegsAsm ( ) const { return Kind == k_Register && Reg . Kind


<s> int reg_increment ; int offset_adj ; int regs_per_val ; gcc_assert ( ( mode == SImode ) || consecutive ) ; gcc_assert ( ! return_pc || load ) ; reg_increment = GET_MODE_SIZE ( mode ) ; regs_per_val = reg_increment / <NUM_LIT> ; offset_adj = return_pc ? <NUM_LIT> : <NUM_LIT> ; if ( count <= <NUM_LIT> || GET_CODE ( XVECEXP ( op , <NUM_LIT> , offset_adj ) ) != SET || ( load && ! REG_P ( SET_DEST ( XVECEXP ( op , <NUM_LIT> , offset_adj ) ) ) ) ) return false ; elt = XVECEXP ( op , <NUM_LIT> , offset_adj ) ; if ( GET_CODE ( SET_SRC ( elt ) ) == PLUS ) { i ++ ; base = <NUM_LIT> ; update = true ; if ( ! REG_P ( SET_DEST ( elt ) ) || ! REG_P ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) || ( REGNO ( SET_DEST ( elt ) ) != REGNO ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) ) || ! CONST_INT_P ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) || INTVAL ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) != ( ( count - <NUM_LIT> - offset_adj ) * reg_increment ) ) return false ; } i = i + offset_adj ; base = base + offset_adj ; if ( ( count <= i ) && ( mode == SImode ) ) return false ; elt = XVECEXP ( op , <NUM_LIT> , i - <NUM_LIT> ) ; if ( GET_CODE ( elt ) != SET ) return


<s> d = vec_and ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b ) ) ; return ( ( qword ) ( vec_nor


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp .


<s> NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isCortexA8 ( ) ) { if ( NumRegs < <NUM_LIT> ) return <NUM_LIT> ; UOps = ( NumRegs / <NUM_LIT> ) ; if ( NumRegs % <NUM_LIT> ) ++ UOps ; return UOps ; } else if ( Subtarget . isCortexA9 ( ) ) { UOps = ( NumRegs


<s> machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode


<s> if ( ISD == <STR_LIT> ) return <NUM_LIT> * CostFactor ; unsigned EltSize = Val -> getScalarSizeInBits ( ) ; if ( EltSize == <NUM_LIT> ) { unsigned MfvsrdIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrdIndex ) return <NUM_LIT> ; } else if ( EltSize == <NUM_LIT> ) { unsigned MfvsrwzIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrwzIndex ) return <NUM_LIT> ; } return CostFactor ; } else if ( ST -> hasDirectMove ( ) ) return <NUM_LIT> ; } unsigned LHSPenalty =


<s> hasLowDefLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass (


<s> EVT T = Node -> getValueType ( <NUM_LIT> ) ; SDValue negOp = DAG . getNode ( <STR_LIT> , dl , T , DAG . getConstant ( <NUM_LIT> , T ) , Node -> getOperand ( <NUM_LIT> ) ) ; return DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , negOp , cast < AtomicSDNode > ( Node ) -> getSrcValue ( )

, cast < AtomicSDNode > ( Node ) -> getAlignment ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ; if ( End . getPointer ( ) == EndPtr ) break ; } Identifier = LineBuf ; if ( ! Result ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ) ; } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Identifier ) ; MCSymbolRefExpr :: VariantKind Variant


<s> const <ISA_LIT>Subtarget & ST = Func . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = ST . getInstrInfo


<s> AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = <NUM_LIT> ; Op -> Reg . EqualityTy =


<s> return ! ElimEdges . contains ( E ) && ! CutEdges . contains ( E ) && MachineGadgetGraph :: isGadgetEdge ( E ) ; } ; do { const MachineGadgetGraph :: Edge * CheapestSoFar = nullptr ; MachineGadgetGraph :: NodeSet GadgetSources { * Graph } , GadgetSinks { * Graph } ; for ( const auto & N : Graph -> nodes ( ) ) { if ( ElimNodes . contains ( N ) ) continue ; for ( const auto & E : N . edges ( ) ) { if ( IsGadgetEdge ( E ) ) { GadgetSources . insert ( N ) ; GadgetSinks . insert ( * E . getDest ( ) ) ; } } } for ( const auto & N : Graph -> nodes ( ) ) { if ( ElimNodes . contains ( N ) ) continue ; for ( const auto & E : N . edges ( ) ) { if ( IsCFGEdge ( E ) ) { if ( GadgetSources . contains ( N ) || GadgetSinks . contains ( * E . getDest ( ) ) ) { if ( ! CheapestSoFar || E . getValue ( ) < CheapestSoFar -> getValue ( ) ) CheapestSoFar = & E ; } } } } assert ( CheapestSoFar && <STR_LIT> ) ; CutEdges . insert ( * CheapestSoFar ) ; ElimEdges . insert ( * CheapestSoFar ) ; } while ( elimMitigatedEdgesAndNodes ( * Graph , ElimEdges , ElimNodes ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CutEdges . count (


<s> static bool UsesVectorABI ( StringRef CPU , StringRef FS ) { bool VectorABI = true ; if ( CPU . empty ( ) || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) VectorABI = false ; SmallVector < StringRef , <NUM_LIT> > Features ; FS . split ( Features , <STR_LIT> , - <NUM_LIT> ,


<s> const Function & F = MF . getFunction ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JumpTableTargets ; if ( auto * JTI = MF . getJumpTableInfo ( ) ) for ( auto & JTE : JTI -> getJumpTables ( ) ) for ( auto * MBB : JTE . MBBs ) JumpTableTargets . insert ( MBB ) ; bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { bool CouldCall = false , CouldJump


<s> if ( verbose ) fprintf ( stderr , <STR_LIT> , string ) ; putenv ( CONST_CAST ( char


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < EVT > & OutTys , const SmallVectorImpl < <STR_LIT> > & ArgsFlags , SelectionDAG & DAG ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext (


<s> MachineOperand * MO = getCallTargetRegOpnd ( MI ) ; if ( ! MO ) return false ; Reg = MO -> getReg ( ) ; Val = <NUM_LIT> ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = MRI . getVRegDef ( Reg ) ; assert ( DefMI ) ; if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI -> hasOneMemOperand ( ) ) ; Val = ( * DefMI -> memoperands_begin ( ) ) ->


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue


<s> } } else { UnknownAttrsMap :: const_iterator attr_it = m_UnknownAttrs . find ( pTag ) ; if ( attr_it == m_UnknownAttrs . end ( ) ) { return NULL ; } else { return & attr_it


<s> OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( TC , getSubtargetInfo ( )


<s> if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , false ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx


<s> if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS && ! MSA_SUPPORTED_MODE_P ( mode


<s> assert ( ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> && ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ) ; int FPOffset = - ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( FPOffset >=


<s> InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx


<s> TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . optForSize ( ) ; MinimizeSize = MF . getFunction ( ) . optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT .

end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ;


<s> const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg ,


<s> start_sequence ( ) ; emit_insn ( gen_ls2_alu1_turn_enabled_insn ( ) ) ; mips_ls2 . alu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_alu2_turn_enabled_insn ( ) ) ; mips_ls2 . alu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu1_turn_enabled_insn ( ) ) ; mips_ls2 . falu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu2_turn_enabled_insn ( ) ) ; mips_ls2 . falu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; mips_ls2 . alu1_core_unit_code = get_cpu_unit_code ( <STR_LIT> ) ; mips_ls2 . alu2_core_unit_code = get_cpu_unit_code ( <STR_LIT>


<s> bool useMulOps ( ) const { return UseMulOps


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; } return


<s> if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN ) return more ; return more -


<s> TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( <STR_LIT> , <STR_LIT> , <NUM_LIT> , SectionKind :: getReadOnlyWithRel


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , <STR_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV ,


<s> virtual MVT getShiftAmountTy ( EVT LHSTy )


<s> ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned <ISA_LIT>OpcV = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Op . getOpcode ( ) ) ) { SDValue BaseShAmt ; MVT EltVT = VT . getVectorElementType ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Amt ) ) { BaseShAmt = BV -> getSplatValue ( ) ; if ( BaseShAmt && BaseShAmt . getOpcode ( ) == <STR_LIT> ) BaseShAmt = SDValue ( ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = dyn_cast < ShuffleVectorSDNode > ( Amt ) ; if ( SVN && SVN -> isSplat ( ) ) { unsigned SplatIdx = ( unsigned ) SVN -> getSplatIndex ( ) ; SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { assert ( ( SplatIdx < InVec . getSimpleValueType ( ) . getVectorNumElements ( ) ) && <STR_LIT> ) ; BaseShAmt = InVec . getOperand ( SplatIdx ) ; } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( ! BaseShAmt ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , InVec , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; } } if ( BaseShAmt . getNode ( ) ) { assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT ,


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR4 ( ( v8qi ) mm ,


<s> if ( skipFunction ( F ) ) return false ; if ( ! EnableAddressTypePromotion || F . isDeclaration ( ) ) return false ; Func = & F ; ConsideredSExtType = Type :: getInt64Ty ( Func -> getContext ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT>


<s> if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) SplitArgs . back ( ) . Flags . setZExt ( ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { SplitArgs . clear ( ) ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; } if ( SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; return true


<s> const <ISA_LIT>InstrInfo & TII = * MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL ; unsigned MoveReg = <STR_LIT> ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , MoveReg ) , CSI [ CSIIndex ] . getFrameIdx ( ) ) ) ; unsigned RestoreOp = <STR_LIT> ; if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get (

RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR3Spilled && ! CR4Spilled ) ) ) ;


<s> static void arm_asm_emit_except_personality ( rtx personality ) { fputs ( <STR_LIT> , asm_out_file


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT>


<s> bool isDstIdx ( ) const { return ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( getMemSegReg ( ) == <NUM_LIT> || getMemSegReg ( ) == <STR_LIT> ) && ( getMemBaseReg ( ) == <STR_LIT> || getMemBaseReg ( ) == <STR_LIT>

|| getMemBaseReg ( ) == <STR_LIT> ) && isa < MCConstantExpr > ( getMemDisp ( ) ) && cast < MCConstantExpr > ( getMemDisp ( ) ) -> getValue ( ) == <NUM_LIT> ;


<s> AU . addRequired < TargetLibraryInfo > ( ) ; FunctionPass :: getAnalysisUsage (


<s> EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL


<s> OperandMatchResultTy parseAR32 ( OperandVector & Operands ) { return parseRegister ( Operands


<s> if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMVEPairVectorIndexOperand < <NUM_LIT> > ( Inst , index , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMVEPairVectorIndexOperand < <NUM_LIT> > ( Inst , index , Address , Decoder )


<s> bool Is32Bit = is32Bit ( VT ) ; Even = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ; Odd = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL


<s> case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> if ( RegVT == <STR_LIT> ) RC = Subtarget -> in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = Has<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = AddLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg


<s> LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ; SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , SDTys , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , VLDDup . getValue ( <NUM_LIT> ) ) ; return VLDDup ; } return SDValue (


<s> unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { AtomicSDNode * AN = cast < AtomicSDNode > ( N . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; return N


<s> unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF )


<s> emit_insn ( gen_load_locked_si ( reg ,


<s> xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) && ! s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , <NUM_LIT> ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x )


<s> for ( i = <NUM_LIT> ; i < nunits / <NUM_LIT> ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ; return


<s> MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; } AddOptionalDefs ( MIB ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { unsigned NewDestReg = createResultReg ( TLI .


<s> std :: vector < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs ) ) ; } std :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef _CPU ) : MCAsmBackend ( ) , CPU (


<s> unsigned getCallOpcode ( const <ISA_LIT>Subtarget & STI , bool isDirect ) { if ( isDirect ) return STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . isThumb ( ) ) return <STR_LIT> ; if ( STI . hasV5TOps ( ) ) return <STR_LIT> ; if ( STI . hasV4TOps (


<s> const auto * DefaultSuperclass = TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & <STR_LIT> ) { InflateGP8RC ++ ; return & <STR_LIT> ; } if ( RC == & <STR_LIT> && EnableGPRToVecSpills ) InflateGPRC ++ ; } for ( const auto * I = RC -> getSuperClasses ( ) ; * I ; ++ I ) { if ( getRegSizeInBits ( * * I ) != getRegSizeInBits ( * RC ) ) continue ; switch ( ( * I ) -> getID ( ) ) { case <STR_LIT> : return Subtarget . hasP8Vector ( ) ? * I :


<s> if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != <STR_LIT> && VT


<s> if ( Op0 == Op1 ) return true ; unsigned Opcode0 = Op0 . getOpcode ( ) ; if ( ( Opcode0 == <STR_LIT> || Opcode0 == <STR_LIT> || Opcode0 == <STR_LIT> ) && Op0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; unsigned Opcode1 = Op1 . getOpcode ( ) ; if ( ( Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> ) && Op1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src . getNode ( ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode


<s> bool hasD16 ( ) const { return STI . getFeatureBits ( ) [


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op . getOperand ( <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> static <ISA_LIT>Operand * CreateShiftedRegister ( <STR_LIT> ShTy , unsigned SrcReg , unsigned ShiftReg , unsigned ShiftImm , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftedRegister ) ; Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc =


<s> NumPEReloadVSR += <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , VSRContainingGPRs [ Dst ] . second ) . addReg ( Dst ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , VSRContainingGPRs [ Dst ] . first ) . addReg ( TRI -> getSubReg ( Dst , <STR_LIT> ) , getKillRegState ( true ) ) ; } else if ( VSRContainingGPRs [ Dst ] . second == <NUM_LIT> ) { assert ( Subtarget . hasP8Vector ( ) ) ; ++ NumPEReloadVSR ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , VSRContainingGPRs [ Dst ] . first ) . addReg ( TRI -> getSubReg ( Dst , <STR_LIT> ) , getKillRegState ( true ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Restored . set ( Dst ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . loadRegFromStackSlotNoUpd ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { assert ( Subtarget . is32BitELFABI ( ) && <STR_LIT> ) ; bool is31 = needsFP (


<s> bool <ISA_LIT>InstrInfo :: optimizeCompareInstr ( MachineInstr & CmpInstr , Register SrcReg , Register SrcReg2 , int CmpMask , int CmpValue , const MachineRegisterInfo * MRI ) const { assert ( CmpInstr . getParent ( ) ) ; assert ( MRI ) ; int DeadNZCVIdx = CmpInstr . findRegisterDefOperandIdx ( <STR_LIT> , true ) ; if ( DeadNZCVIdx != - <NUM_LIT> ) { if ( CmpInstr . definesRegister ( <STR_LIT> ) || CmpInstr . definesRegister ( <STR_LIT> ) ) { CmpInstr . eraseFromParent ( ) ; return true ; } unsigned Opc = CmpInstr . getOpcode ( ) ; unsigned NewOpc = convertToNonFlagSettingOpc ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr . setDesc ( MCID ) ; CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( create<ISA_LIT>FixupSetCC ( ) ) ; addPass ( create<ISA_LIT>OptimizeLEAs ( ) ) ; addPass ( create<ISA_LIT>CallFrameOptimization ( )


<s> uint64_t SubMembers = <NUM_LIT> ; if ( ! isHomogeneousAggregate ( AT -> getElementType ( ) , Base , SubMembers ) ) return false ; Members += SubMembers * AT -> getNumElements ( ) ; } else if ( Ty -> isFloatTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_FLOAT ) return false ; Members = <NUM_LIT> ; Base = HA_FLOAT ; } else if ( Ty -> isDoubleTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_DOUBLE ) return false ; Members = <NUM_LIT> ; Base = HA_DOUBLE ; } else if ( auto * VT = dyn_cast < VectorType > ( Ty ) ) { Members =


<s> } else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'C' : loongarch_print_int_branch_condition ( file , code , letter ) ; break ; case 'N' : loongarch_print_int_branch_condition ( file , reverse_condition ( code ) , letter ) ; break ; case 'F' : loongarch_print_float_branch_condition ( file , code , letter ) ; break ; case 'W' : loongarch_print_float_branch_condition ( file , reverse_condition ( code ) , letter ) ; break ; case 'T' : case 't' : { int truth = ( code == NE ) == ( letter == 'T' ) ; fputc ( <STR_LIT> [ truth * <NUM_LIT> + FCC_REG_P ( REGNO ( XEXP ( op , <NUM_LIT> ) ) ) ] , file ) ; } break ; case 'Y' : if ( code == CONST_INT && UINTVAL ( op ) < ARRAY_SIZE ( loongarch_fp_conditions ) ) fputs ( loongarch_fp_conditions [ UINTVAL ( op ) ] , file ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'Z' : loongarch_print_operand ( file , op , <NUM_LIT> ) ; fputc ( ',' , file ) ; break ; case 'A' : if ( loongarch_memmodel_needs_rel_acq_fence ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'G' : if ( loongarch_memmodel_needs_release_fence ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'i' : if ( code != REG ) fputs ( <STR_LIT> ,


<s> __inline__ static unsigned long long sh_media_MSAD_UBQ ( unsigned long long mm , unsigned long long mn , unsigned long long mw ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return res


<s> } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; llvm :: sort ( ScratchRegs , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ; for ( const auto & Reg


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ? ( MCFixupKind ) <STR_LIT>


<s> const MCOperand & Op2 = MI -> getOperand ( opNum + <NUM_LIT> ) ; bool PrintedFirstOperand = false ; if ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) { printOperand ( MI , opNum , STI , O ) ; PrintedFirstOperand = true ; } const bool SkipSecondOperand = PrintedFirstOperand && ( ( Op2 . isReg ( ) && Op2 . getReg ( ) == <STR_LIT> ) || ( Op2 . isImm ( ) && Op2 . getImm ( ) == <NUM_LIT> ) ) ; if ( ! SkipSecondOperand ) { if ( PrintedFirstOperand ) O <<


<s> if ( ! SuccBB ) return false ; RegDefsUses RegDU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn


<s> const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : { MachineModuleInfoCOFF & MMICOFF = MF . getMMI ( ) . getObjFileInfo < MachineModuleInfoCOFF > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMICOFF . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , true ) ; } break ; } case <STR_LIT>


<s> if ( Op . getOpcode ( ) == <STR_LIT> && cast <

LoadSDNode > ( Op ) -> isUnindexed ( ) ) return true ;


<s> MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ; StoreBB -> clearLiveIns ( ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; LoadCmpBB -> clearLiveIns ( ) ; computeLiveIns ( LiveRegs , MRI


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isEnvironmentMachO ( ) && TheTriple . getArch ( ) == Triple :: x86_64 ) return create<ISA_LIT>_64MachORelocationInfo ( Ctx ) ; else if ( TheTriple . isOSBinFormatELF ( ) ) return create<ISA_LIT>_64ELFRelocationInfo ( Ctx ) ; return llvm :: createMCRelocationInfo ( TT


<s> srcreg = gen_rtx_REG ( word_mode , reg ) ; delta = GEN_INT ( mod ) ; insn = emit_insn ( gen_post_store ( basereg , srcreg , delta ) ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) =


<s> if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX ?


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR32Regs ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> void emitARM64WinCFISaveFReg ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT>


<s> int MemRefBegin = <STR_LIT> ( Desc . TSFlags , MemOp -> getOpcode ( ) ) ; if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; BaseReg = MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) ; if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm


<s> const MCExpr * AssemblerConstantPools :: addEntry ( MCStreamer


<s> if ( basic_align < <NUM_LIT> ) return


<s> assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ; if ( ! FalseBlock ) return <NUM_LIT>


<s> bool isCSR = ! isFixed && ObjectOffset >= - ( ( int ) AFI -> getCalleeSavedStackSize ( ) ) ; const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; if ( SVEStackSize ) llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) ) { if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( isCSR && RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) UseFP = true ; } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bits = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bits ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return FP ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ext64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> int regno , maxregno = IP_REGNUM ; tree result_type ; rtx result_rtl ; to_clear_mask [ <NUM_LIT> ] = ( <NUM_LIT> << ( NUM_ARG_REGS ) ) - <NUM_LIT> ; to_clear_mask [ <NUM_LIT> ] |= ( <NUM_LIT> << IP_REGNUM ) ; if ( TARGET_HARD_FLOAT && ! TARGET_THUMB1 ) { uint64_t float_mask = ( <NUM_LIT> << ( D7_VFP_REGNUM + <NUM_LIT> ) ) - <NUM_LIT> ; maxregno = LAST_VFP_REGNUM ; float_mask &= ~ ( ( <NUM_LIT> << FIRST_VFP_REGNUM ) - <NUM_LIT> ) ; to_clear_mask [ <NUM_LIT> ] |= float_mask ; float_mask = ( <NUM_LIT> << ( maxregno - <NUM_LIT> ) ) - <NUM_LIT> ; to_clear_mask [ <NUM_LIT> ] = float_mask ; emit_use ( gen_rtx_REG ( SImode , IP_REGNUM ) ) ; to_clear_mask [ <NUM_LIT> ] &= ~ ( <NUM_LIT> << IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; to_clear_mask [ <NUM_LIT> ] &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; } for ( regno = NUM_ARG_REGS ; regno < LAST_VFP_REGNUM ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( call_used_regs [ regno ] ) to_clear_mask [ regno / <NUM_LIT> ] |= ( <NUM_LIT> << ( regno % <NUM_LIT> ) ) ; } result_type = TREE_TYPE ( DECL_RESULT


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> __rv . __o = __builtin_neon_vld4v8bf ( ( const __builtin_neon_bf * ) __ptr ) ; return __rv .


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ; return false


<s> bool e8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : case


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( )


<s> dest = gen_rtx_ZERO_EXTRACT ( SImode , scratch_reg , rtx16 , rtx16 ) ; if ( mask ) emit_insn ( gen_rtx_SET ( dest , gen_int_mode ( mask , SImode ) ) ) ; emit_insn ( gen_andsi3 ( cleared_reg , cleared_reg , scratch_reg ) ) ; } if ( saved_clearing ) emit_move_insn ( clearing_reg , saved_clearing_reg ) ; if ( clearing_regno <= maxregno && bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) { emit_move_insn ( clearing_reg , const0_rtx ) ; emit_use ( clearing_reg ) ; bitmap_clear_bit ( to_clear_bitmap , clearing_regno ) ; } for ( regno = minregno ; regno <= maxregno ; regno ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap , regno ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && bitmap_bit_p ( to_clear_bitmap , regno + <NUM_LIT> ) ) { emit_move_insn ( gen_rtx_REG ( DFmode , regno ) , CONST1_RTX ( DFmode ) ) ; emit_use ( gen_rtx_REG ( DFmode , regno ) ) ; regno ++ ; } else { emit_move_insn ( gen_rtx_REG ( SFmode , regno ) , CONST1_RTX ( SFmode ) ) ; emit_use ( gen_rtx_REG ( SFmode , regno ) ) ; } } else { emit_move_insn ( gen_rtx_REG ( SImode , regno ) , clearing_reg ) ; emit_use ( gen_rtx_REG ( SImode ,


<s> materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID ,

BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ;


<s> ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT>


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void \ rdata_section ( ) \ { \ if ( in_section != in_rdata ) \ { \ if ( mips_abi != ABI_32 && mips_abi != ABI_O64 ) \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP_64 ) ; \ else \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP_32 ) ; \ in_section


<s> return true ; } unsigned LaneSize = <NUM_LIT> ; SmallVector < int , <NUM_LIT> > MaskVal ( LaneSize , - <NUM_LIT> ) ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( Mask [ i + l ] < <NUM_LIT>


<s> if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; return std :: make_pair ( FIST ,


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSFreeBSD ( ) ) return make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) ) return make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile


<s> static bool iq2000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( REGNO_REG_CLASS ( regno ) == GR_REGS ? ( regno & <NUM_LIT> ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) <= <NUM_LIT> : (

regno & <NUM_LIT> ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_vprotdi ( ( __v4si )


<s> bool isVSRegNumber ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm (


<s> ComplexRendererFns selectArithShiftedRegister ( MachineOperand & Root ) const { return selectShiftedRegister (


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( create<ISA_LIT>PreLegalizerCombiner (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFCOPYSIGN ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; assert ( Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( Ty == <STR_LIT> || Has<ISA_LIT>64 ) return LowerFCOPYSIGNLargeIntReg ( Op , DAG ) ; return LowerFCOPYSIGNSmallIntReg ( Op , DAG , Subtarget -> isLittle


<s> MCSymbolRefExpr :: VariantKind <ISA_LIT>AsmParser :: getVariantKind ( StringRef Symbol ) { MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 ) . Case

( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 ) . Default ( MCSymbolRefExpr :: VK_None ) ;


<s> emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } } else if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg ) ; return true ; } } return false ; } case <STR_LIT> : case <STR_LIT> : { const auto * MTI = cast < MemTransferInst > ( II ) ; if ( MTI -> isVolatile ( ) ) return false ; if ( ! MTI -> getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; const char * IntrMemName = isa < MemCpyInst > ( II ) ? <STR_LIT> : <STR_LIT> ; return lowerCallTo ( II , IntrMemName , II -> getNumArgOperands ( ) - <NUM_LIT> ) ; } case <STR_LIT> :


<s> const TableEntry * I = std :: lower_bound ( Table , Table


<s> return addr ( ) + ( <ISA_LIT>GOTPLT0Num + num ) * GOTPLTEntry


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; if ( Idx -> getOpcode ( ) == <STR_LIT> ) { SDValue AllOnes = Vec -> getOperand ( <NUM_LIT> ) ; SDValue Pred = Vec -> getOperand ( <NUM_LIT> ) ; if ( getIntrinsicID ( Idx . getNode ( ) ) == <STR_LIT> && Idx -> getOperand ( <NUM_LIT> ) . getNode ( ) == Vec . getNode ( ) && Vec -> getOpcode ( ) == <STR_LIT> && AllOnes -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( AllOnes -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( AllOnes -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue InvPred = DAG . getNode ( <STR_LIT> , DL , Pred . getValueType ( ) , Pred ) ; return DAG . getNode ( <STR_LIT> , DL , VT , AllOnes ,


<s> if ( current_function_decl ) { mode = TARGET_THUMB ? <STR_LIT> : <STR_LIT> ; add_attribute ( mode , attributes ) ; return ; } if ( lookup_attribute ( <STR_LIT> , * attributes ) != NULL ) return ; mode = thumb_flipper ? <STR_LIT> : <STR_LIT> ; add_attribute ( mode , attributes ) ; thumb_flipper = ! thumb_flipper


<s> } for ( ; i < insn_data [ icode ] . n_operands && arglist != <NUM_LIT> ; i ++ ) ops [ i ] = mips_prepare_builtin_arg ( icode , i , & arglist ) ; switch ( i ) { case <NUM_LIT> : emit_insn ( GEN_FCN ( icode ) ( ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ; break ; case <NUM_LIT>


<s> return ( __m128 ) __builtin_ia32_cmpnless ( ( __v4sf ) __A , ( __v4sf )


<s> if ( Bytes . size ( ) < <NUM_LIT> ) return Fail ; Size = <NUM_LIT> ; uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | (


<s> static DecodeStatus DecodeBankedReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! R


<s> MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Subtarget . getStackAlignment ( ) . value ( ) ) . add


<s> if ( CS ) if ( CS -> arg_empty ( ) || ! CS -> paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) || CS -> paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) || Subtarget -> isTargetMCU ( ) ) return <NUM_LIT> ; return


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>LETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>BETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn A ( TheThumbLETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( TheThumbBETarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbLETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbBETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbLETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbBETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbLETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbBETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>LETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>BETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbLETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbBETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbLETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbBETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>LETarget , create<ISA_LIT>LEMCCodeEmitter


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSize == Offset ) return ; if ( LeftoverBytes ) { assert ( ( ByValSize > Offset ) && ( ByValSize < Offset + RegSize ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = RegSize / <NUM_LIT> , TotalSizeLoaded = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt


<s> } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } unsigned LaneTmp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp2 ) . addReg ( <STR_LIT> ) . addReg ( LaneReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( WdTmp2 ) . addReg ( WdTmp2 ) . addReg ( LaneTmp2 ) ; MI -> eraseFromParent ( ) ; return BB


<s> MVT ExtVT = <STR_LIT> ( <STR_LIT> ( EltBits * Scale ) , NumElements / Scale ) ; InputV = ShuffleOffset ( InputV ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) InputV = extractSubVector ( InputV , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( int ) VT . getSizeInBits ( ) / Scale ) ) ; InputV = DAG . getNode ( <STR_LIT> , DL , ExtVT , InputV ) ; return DAG . getBitcast ( VT , InputV ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( AnyExt && EltBits == <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { Offset , - <NUM_LIT> , SafeOffset ( Offset + <NUM_LIT> ) ? Offset + <NUM_LIT> : - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { Offset / <NUM_LIT> , - <NUM_LIT> , SafeOffset ( Offset + <NUM_LIT> ) ? ( Offset + <NUM_LIT> ) / <NUM_LIT> : - <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ; int PSHUFWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; unsigned OddEvenOp = ( Offset & <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( OddEvenOp , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFWMask , DL , DAG ) ) ) ; } if ( ( Scale * EltBits ) == <NUM_LIT> && EltBits < <NUM_LIT> && Subtarget . hasSSE4A ( ) ) { assert ( NumElements == ( int ) Mask . size ( ) && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; int LoIdx = Offset * EltBits ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , InputV , DAG . getConstant ( EltBits , DL , <STR_LIT> ) , DAG . getConstant ( LoIdx , DL , <STR_LIT> ) ) ) ; if ( isUndefInRange ( Mask , NumElements / <NUM_LIT> , NumElements / <NUM_LIT> ) || ! SafeOffset ( Offset + <NUM_LIT> ) ) return DAG . getBitcast ( VT , Lo ) ; int HiIdx = ( Offset + <NUM_LIT> ) * EltBits ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , InputV , DAG . getConstant ( EltBits , DL , <STR_LIT> ) ,

DAG . getConstant ( HiIdx , DL , <STR_LIT> ) ) ) ;


<s> case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( { MachineBasicBlock :: iterator PrevI = PrevMI ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( )


<s> return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) (

si_from_int ( <NUM_LIT> - count ) ) , <NUM_LIT> ) ) ) ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crcc_w_d_w ( long int _1 , int _2 ) { return ( int ) __builtin_loongarch_crcc_w_d_w ( ( long int ) _1 , ( int


<s> if ( ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || ! isImmSExti16i8Value ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) )


<s> unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end (


<s> rtx TWO52 ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & TWO52r , fmt -> p - <NUM_LIT> , mode ) ; TWO52 = const_double_from_real_value ( TWO52r , mode ) ; TWO52 = force_reg ( mode , TWO52


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; DebugLoc DL ; bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { DL = MBBI -> getDebugLoc ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } int NumBytes = MFI -> getStackSize ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; uint64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; ArgumentPopSize = StackAdjust . getImm ( ) ; } else { ArgumentPopSize = AFI -> getArgumentStackToRestore ( ) ; } NumBytes += ArgumentPopSize ; unsigned NumRestores = <NUM_LIT> ; MachineBasicBlock :: iterator LastPopI = MBB . getFirstTerminator ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( LastPopI != MBB . begin ( ) ) { do { ++ NumRestores ; -- LastPopI ; } while ( LastPopI != MBB . begin ( ) && isCSRestore ( LastPopI , CSRegs ) ) ; if ( ! isCSRestore ( LastPopI , CSRegs ) ) { ++ LastPopI ; -- NumRestores ; } } NumBytes -= NumRestores * <NUM_LIT> ; assert ( NumBytes >=


<s> m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null


<s> MachineBasicBlock :: iterator NextI = I ; ++ NextI ; if ( NextI == MergeMI ) ++ NextI ; unsigned Opc = I -> getOpcode ( ) ; bool IsScaled = ! TII -> isUnscaledLdSt ( Opc ) ; int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; return


<s> int tmpwidth ; int retval = simd_valid_immediate ( op , mode , <NUM_LIT> , & tmpconst , & tmpwidth ) ; if ( retval == - <NUM_LIT> ) return <NUM_LIT> ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return


<s> static DecodeStatus DecodeSimm18Lsl3 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) * <NUM_LIT> ) ) ; return MCDisassembler ::


<s> Optional < unsigned > VScaleMax = VScaleRangeAttr . getVScaleRangeMax ( ) ; MinSVEVectorSize = VScaleRangeAttr . getVScaleRangeMin ( ) * <NUM_LIT> ; MaxSVEVectorSize = VScaleMax ? VScaleMax . getValue ( ) * <NUM_LIT> : <NUM_LIT> ; } else { MinSVEVectorSize = SVEVectorBitsMinOpt ; MaxSVEVectorSize = SVEVectorBitsMaxOpt ; } assert ( MinSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( MaxSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( ( MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( MaxSVEVectorSize == <NUM_LIT> ) MinSVEVectorSize = ( MinSVEVectorSize / <NUM_LIT> ) * <NUM_LIT> ; else { MinSVEVectorSize = ( std :: min ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; MaxSVEVectorSize = ( std :: max ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; } Key += <STR_LIT> ; Key += std :: to_string ( MinSVEVectorSize ) ; Key += <STR_LIT> ; Key += std :: to_string ( MaxSVEVectorSize ) ; Key += CPU ; Key += TuneCPU


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; }


<s> case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N ,


<s> uint64_t NumBits1 = VT1 . getFixedSizeInBits ( ) ; uint64_t NumBits2 = VT2 . getFixedSizeInBits ( ) ; return NumBits1 >


<s> SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N00 . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N00 ) , VT , N00 ) ; } unsigned FPOpcode ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0 ) ; if ( N0 . hasOneUse ( ) && LogicOp0 . getOpcode ( ) == <STR_LIT> && LogicOp0 . hasOneUse ( ) && LogicOp0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp0 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp1 = DAG . getBitcast ( VT , LogicOp1 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp0 . getOperand ( <NUM_LIT> ) , CastedOp1 ) ; } if ( N0 . hasOneUse ( ) && LogicOp1 . getOpcode ( ) == <STR_LIT> && LogicOp1 . hasOneUse ( ) && LogicOp1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp0 = DAG . getBitcast ( VT , LogicOp0 ) ; return DAG . getNode ( FPOpcode , DL0 , VT ,

LogicOp1 . getOperand ( <NUM_LIT> ) , CastedOp0 ) ;


<s> return new <ISA_LIT>PassConfig ( this , PM )


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM .


<s> static DecodeStatus DecodeGPRnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler ::


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg

) return CSR_<ISA_LIT>_AllRegs_RegMask ;


<s> __builtin_mve_vstrhq_uv8hi ( ( __builtin_neon_hi * )


<s> MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = VT . changeVectorElementType ( SVT ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } } if ( Opcode == InOpcode ) return DAG . getNode ( Opcode , SDLoc ( N ) ,


<s> break ; default : gcc_unreachable ( ) ; } if ( to == FRAME_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) offset


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { return


<s> N1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; MVT ShufVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , ShufVT , N1 ) ; N1 = getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; return DAG . getBitcast ( VT , N1 ) ; } } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N1 = DAG . getNode ( <STR_LIT> , dl


<s> unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint , isVector ? <STR_LIT> : <STR_LIT> ) ; return false


<s> SDValue Chain = DAG . getStore ( St -> getChain ( ) , dl , Val , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) , St -> getAAInfo ( ) ) ; return Chain ; } return SDValue (


<s> TypeSize = OrigTy -> getPrimitiveSizeInBits ( ) ; if ( TypeSize > <NUM_LIT> || TypeSize < <NUM_LIT> ) return false ; if ( ! isSupportedValue ( V ) || ! shouldPromote ( V ) || ! isLegalToPromote ( V ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> << TypeSize << <STR_LIT> ) ; SetVector < Value * > WorkList ; SmallPtrSet < Value * , <NUM_LIT> > Sources ; SmallPtrSet < Instruction * , <NUM_LIT> > Sinks ; WorkList . insert ( V ) ; SmallPtrSet < Value * , <NUM_LIT> > CurrentVisited ; CurrentVisited . clear ( ) ; auto AddLegalInst = [ & ] ( Value * V ) { if ( CurrentVisited . count ( V ) ) return true ; if ( isa < GetElementPtrInst > ( V ) ) return true ; if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; else if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I -> operands ( ) ) { if ( ! AddLegalInst ( U ) ) return false ; } } if ( isSource ( V ) || shouldPromote ( V ) ) { for ( Use & U : V -> uses ( ) ) { if ( ! AddLegalInst ( U . getUser ( ) ) ) return false ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * I : CurrentVisited ) I -> dump ( ) ; ) ; unsigned ToPromote = <NUM_LIT> ; for ( auto * V : CurrentVisited ) { if ( Sources . count ( V ) ) continue ; if ( Sinks . count ( cast < Instruction > ( V ) ) ) continue ; ++ ToPromote ; } if ( ToPromote < <NUM_LIT> ) return false


<s> std :: vector < MachineBasicBlock * > :: iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , NewBB , CompareMBBNumbers ) ; WaterList . insert ( IP


<s> unsigned getAddrModeImm12OpValue ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & MO = MI . getOperand ( Op ) ; const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; uint32_t Binary ; Binary = Imm12 &


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = <NUM_LIT> * HOST_BITS_PER_WIDE_INT - <NUM_LIT> ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT>


<s> gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg


<s> if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false


<s> static SDValue LowerZERO_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT . is512BitVector ( ) || SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_AVX512 ( Op , Subtarget , DAG ) ; if ( Subtarget . hasFp256 ( ) ) if ( SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ) return Res ; assert ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) !=


<s> switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getMGatherNode ( Opc , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getScatterNode ( Opc , Op , DAG , Src , Base , Index , Scale , Chain ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( Opc ) return DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; Opc = Unsigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG

. getConstant ( SSECC , dl , <STR_LIT> ) ) ;


<s> if ( Val & ( UINT64_C ( <NUM_LIT> ) << <NUM_LIT> ) ) return countLeadingOnes ( Val ) ; return countLeadingZeros ( Val )


<s> if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Src = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) ) return SDValue ( ) ; if ( SDValue Not = IsNOT ( Src , DAG ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( V ) , VT , DAG . getBitcast ( SrcVT , Not ) ) ; } return SDValue ( ) ; } ; if ( SDValue Not = GetNot ( N0 ) ) { X = Not ; Y = N1 ; } else if ( SDValue Not = GetNot ( N1 ) ) { X =


<s> if ( m_pRelocator == NULL ) m_pRelocator = new <ISA_LIT>64Relocator ( * this , config ( ) ) ; return


<s> static SDValue combineVectorSignBitsTruncation ( SDNode * N , SDLoc & DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX512 ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( NumSignBits != InSVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT !=


<s> unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: pair < unsigned , unsigned > Opcodes = getMFHiLoOpc ( Src ) ; if ( ! Opcodes . first ) return false ; return expandCopyACC ( MBB , I , Opcodes . first , Opcodes


<s> if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc ,


<s> __v8sf mask = _mm256_cmp_ps ( src , src , _CMP_EQ_OQ ) ; return ( __m256 ) __builtin_ia32_gathersiv8sf ( src , base , ( __v8si ) index ,


<s> return Kind == k_VectorList && VectorList . Count == NumRegs && ! VectorList . ElementKind && ! VectorList


<s> static void computeKnownBitsBinOp ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth , unsigned OpNo ) { APInt Src0DemE = getDemandedSrcElements ( Op , DemandedElts , OpNo ) ; APInt Src1DemE = getDemandedSrcElements ( Op , DemandedElts


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg