<s> case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) Known = Known . trunc ( <NUM_LIT> ) ; unsigned ShAmt = C -> getZExtValue ( ) ; computeGREV ( Known . Zero , ShAmt ) ; computeGREV ( Known . One , ShAmt ) ; if ( Opc == <STR_LIT> ) Known = Known . sext ( BitWidth


<s> add_input_operand ( mode , RVV_VUNDEF ( mode )


<s> return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment

, isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT>


<s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( )


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT>


<s> if ( known_eq ( UINTVAL ( offset1 ) + size , UINTVAL ( offset2 ) ) ) { * reversed = false ; return true ; } if ( known_eq ( UINTVAL ( offset2 ) + size , UINTVAL ( offset1 ) ) ) { * reversed = true ; return true ; } return


<s> switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) ; } else { BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) .


<s> SDNode * Result = nullptr ; SDValue SrcReg = CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ; for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG ->

getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } return Result


<s> if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( )


<s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default : Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res ,


<s> static inline bool hasVecPolicyOp ( uint64_t TSFlags ) { return TSFlags & HasVecPolicyOpMask


<s> const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 . getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT>


<s> uint64_t getAlignmentMask ( uint64_t Length , bool IsRV64 ) { if ( IsRV64


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter


<s> for ( auto Instr : Res ) { bool Compressed ; switch ( Instr . Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Compressed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm ) ; break ; case <STR_LIT>


<s> break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( offset ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ Count


<s> if ( ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) .

addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ;


<s> MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , IsStrided , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsStrided , false , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , {


<s> if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) return State . AllocateReg ( <STR_LIT> ) ; return State . AllocateReg ( ArgVRs ) ; } if ( RC == & <STR_LIT> ) return State . AllocateReg ( ArgVRM2s ) ; if ( RC == & <STR_LIT> ) return State .


<s> SDValue Index = MSN -> getIndex ( ) ; SDValue Mask = MSN -> getMask ( ) ; SDValue Val = MSN -> getValue ( ) ; MVT VT = Val . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( MSN -> getBasePtr ( ) . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! MSN -> isTruncatingStore ( ) && <STR_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; SDValue VL ; if ( VT . isFixedLengthVector ( ) ) { MVT ContainerVT ; if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MSN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back (


<s> Align <ISA_LIT>ELFTargetObjectFile :: getAlignmentForPreciseBounds ( uint64_t Size , const TargetMachine & TM ) const { if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI ( ) ) return Align ( ) ; const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; return <STR_LIT> ( Size , RTM


<s> if ( ! isa < FixedVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; if ( Ty -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; InstructionCost BaseCost = <NUM_LIT> ; unsigned VL = cast < FixedVectorType > (


<s> bool <ISA_LIT>RemoveRedundancyVSETVL :: runOnMachineFunction ( MachineFunction & MF ) { collectRedundancyVSETVLIInMF ( MF


<s> case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT>


<s> collectRedundancyVSETVLIInMF ( MF ) ; return removeRedundancy (


<s> const auto * RVFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) ) return true ; RegScavenger


<s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( )


<s> assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) <= <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Expr , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr ; return


<s> assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMin <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ; if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std

:: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> . contains ( SrcReg ) ) ) { Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else llvm_unreachable (


<s> Register SrcReg = <STR_LIT> ; Register Result = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Num = <NUM_LIT> ; if ( ! IsRV64 && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq ; <STR_LIT> ( Val , IsRV64 , Seq ) ; assert ( Seq . size ( ) > <NUM_LIT> ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT>


<s> std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT> ( ABIName ) ; if ( TargetABI != <STR_LIT> && ModuleTargetABI -> getString


<s> collectRedundancyVSETVLIInMF ( MachineFunction & MF ) { for ( auto & MBB : MF )


<s> static const uint64_t GREVMasks [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Stage = <NUM_LIT> ; Stage != <NUM_LIT> ; ++ Stage ) { unsigned Shift = <NUM_LIT> << Stage ; if ( ShAmt & Shift ) { uint64_t Mask = GREVMasks [ Stage ] ; uint64_t Res = ( ( x & Mask ) << Shift ) | ( ( x >> Shift ) & Mask ) ; if ( IsGORC ) Res |= x


<s> <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> ,


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( Flag ) ; return ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . setMIFlag ( Flag ) ; return ; } unsigned Opc ; bool IsScalableVector = true ; unsigned NF = <NUM_LIT> ; unsigned LMul = <NUM_LIT> ; unsigned SubRegIdx = <STR_LIT> ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT>


<s> if ( Subtarget . hasStdExtD ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F64_Interrupt_SaveList : CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F32_Interrupt_SaveList : CSR_XLEN_F32_Interrupt_SaveList ; return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_Interrupt_SaveList : CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64_L64PC128_SaveList


<s> void riscv_expand_conditional_branch ( rtx label , rtx_code code , rtx op0 , rtx op1 ) { if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) riscv_emit_float_compare ( & code , & op0 , & op1 ) ; else riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; emit_jump_insn ( gen_condjump ( condition ,


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) &&

! Subtarget . hasStdExtZfhmin ( ) ) return <NUM_LIT> ;


<s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC )

, RegInfo -> getSpillAlign ( * RC ) , false ) ;


<s> e . add_output_operand ( dest , mode ) ; if ( mask ) e . add_input_operand ( mask , GET_MODE ( mask ) ) ; else e . add_all_one_mask_operand ( mask_mode ) ; e . add_vundef_operand ( mode ) ; e . add_input_operand ( src , GET_MODE ( src ) ) ; if ( len ) e . add_input_operand ( len


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; switch (


<s> Ret = RE -> evaluateAsConstant ( Imm ) ; VK = RE -> getKind ( ) ; } else if ( auto CE = dyn_cast < MCConstantExpr > ( Val ) ) { Ret = true ; VK = <ISA_LIT>MCExpr


<s> bool hasSameVLMAX ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ; assert ( ! isUnknown ( ) && ! Other . isUnknown ( ) &&


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr ::

VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;


<s> if ( Reg == <STR_LIT> ) return <NUM_LIT> ; if ( Reg . isVirtual ( ) ) { auto * Def = MRI . getUniqueVRegDef ( Reg ) ; switch ( Def -> getOpcode ( ) ) { default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ; return arg . stack_p ? arg


<s> return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( )

? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ;


<s> return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtZfh ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtF ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtD ( ) ) return false ; break ; } unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ; if ( LMul > Subtarget . getMaxLMULForFixedLengthVectors (


<s> slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset


<s> LoopIfBodyMBB -> addSuccessor ( LoopTailMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: UMax : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; case AtomicRMWInst :: UMin : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } insertMaskedMerge ( TII , DL , LoopIfBodyMBB , Scratch1Reg ,

DestReg , IncrReg , MaskReg , Scratch1Reg ) ;


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , Ty ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Cond


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isUInt < <NUM_LIT>


<s> unsigned StackID = MFI . getStackID ( I ) ; if ( StackID != TargetStackID :: ScalableVector ) continue ; if ( MFI . isDeadObjectIndex ( I ) ) continue ; ObjectsToAllocate . push_back ( I ) ; } int64_t Offset = <NUM_LIT> ; Align RVVStackAlign ( <NUM_LIT> ) ; for ( int FI : ObjectsToAllocate ) { int64_t ObjectSize = MFI . getObjectSize ( FI ) ; auto ObjectAlign = std :: max ( Align ( <NUM_LIT> ) , MFI . getObjectAlign ( FI ) ) ; if ( ObjectSize < <NUM_LIT> ) ObjectSize = <NUM_LIT> ; Offset = alignTo ( Offset + ObjectSize , ObjectAlign ) ; MFI . setObjectOffset ( FI , - Offset ) ; RVVStackAlign = std :: max ( RVVStackAlign , ObjectAlign ) ; } uint64_t StackSize = Offset ; if ( auto AlignmentPadding = offsetToAlignment ( StackSize ,


<s> } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> )


<s> case AtomicOrdering :: Acquire : return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ; case AtomicOrdering :: Release : return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ; case AtomicOrdering :: AcquireRelease : return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ?


<s> llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair (


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; unsigned PI , PO , PR , PW , SI , SO , SR , SW ; switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) { case NotAtomic : case Unordered : case Monotonic : case Acquire : case Release : case AcquireRelease : case SequentiallyConsistent : PI = <NUM_LIT> << <NUM_LIT> ; PO = <NUM_LIT> << <NUM_LIT> ; PR = <NUM_LIT> << <NUM_LIT> ; PW = <NUM_LIT> << <NUM_LIT> ; } switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) { case SingleThread


<s> auto * SVal = dyn_cast < MCSymbolRefExpr > ( Val ) ; if ( ! SVal || SVal -> getKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; return <STR_LIT> ( Str )


<s> unsigned <ISA_LIT>TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return new <ISA_LIT>GatherScatterLowering (


<s> O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( MaskedoffAgnostic )


<s> auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( Caller . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet ||


<s> if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType ( )


<s> SDValue <ISA_LIT>TargetLowering :: lowerToScalableOp ( SDValue Op , SelectionDAG & DAG , unsigned NewOpc , bool HasMask ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isVector ( ) ) { Ops . push_back ( V ) ; continue ; } assert ( useRVVForFixedLengthVectorVT ( V . getSimpleValueType ( ) ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; if ( HasMask ) Ops . push_back


<s> initialize<ISA_LIT>CleanupVSETVLIPass ( * PassRegistry ::


<s> MCStreamer * create<ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && MOW , std :: unique_ptr < MCCodeEmitter > && MCE , bool RelaxAll ) { return create<ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( MOW ) , std :: move (


<s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( Register & ) RegNo , Name ) ) return Error ( StartLoc , <STR_LIT> ) ; getParser ( ) . Lex ( ) ; return


<s> unsigned Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> std :: unique_ptr < <ISA_LIT>Operand > OptionalImmOp ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { int64_t ImmVal ; SMLoc ImmStart = getLoc ( ) ; if ( getParser ( ) . parseIntToken ( ImmVal , <STR_LIT> ) ) return MatchOperand_ParseFail ; SMLoc ImmEnd = getLoc ( ) ; OptionalImmOp = <ISA_LIT>Operand :: createImm ( MCConstantExpr :: create ( ImmVal , getContext ( ) ) , ImmStart , ImmEnd , isRV64 ( ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , OptionalImmOp ? <STR_LIT> : <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT>


<s> OutMI . setOpcode ( RVV -> BaseInstr ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; const MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( TRI && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { int OpNo = ( int ) MI -> getOperandNo ( & MO ) ; assert ( OpNo >= <NUM_LIT> && <STR_LIT> ) ; if ( OpNo == RVV -> getVLIndex ( ) || OpNo == RVV -> getSEWIndex ( ) || OpNo == RVV -> getMergeOpIndex ( ) ) continue ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { Reg = TRI -> getSubReg ( Reg ,


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm (


<s> bool formsPairWith ( const <ISA_LIT>BitmanipPat & Other )


<s> Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps -


<s> if ( Pmode == DImode ) return gen_got_load_tls_gddi ( dest , sym ) ; else return gen_got_load_tls_gdsi ( dest , sym


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr ::


<s> if ( ! ( getSTI ( ) . getFeatureBits ( ) [


<s> AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIPU ( SDValue Dest ,


<s> SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , XLenMinus1 ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL


<s> static SDValue splatPartsI64WithVL ( const SDLoc & DL , MVT VT , SDValue Lo , SDValue Hi , SDValue VL , SelectionDAG & DAG ) { if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi )


<s> return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset


<s> return ( tune_param -> memory_cost + memory_move_secondary_cost ( mode , rclass , in


<s> struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info .


<s> Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister

, RegState :: Kill ) . setMIFlag ( Flag ) ;


<s> assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT ,


<s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_CALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) )


<s> unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ; return static_cast < <ISA_LIT>VLMUL > (


<s> unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT>


<s> if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; return


<s> rtx_insn * insn ; regstat_init_n_sets_and_refs ( ) ; FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < <NUM_LIT> ) continue ; m -> get_or_insert ( regno


<s> case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const auto & OpIdx : enumerate ( Op -> ops ( ) ) ) { SDValue V = OpIdx . value ( ) ; assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isFixedLengthVector ( ) ) { Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == <STR_LIT> || Section == <STR_LIT> ) return true ; return false ; } if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ; return isInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty


<s> if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI ,


<s> static void riscv_file_start ( void ) { default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> :


<s> unsigned num_int = <NUM_LIT> , num_float = <NUM_LIT> ; int n = riscv_flatten_aggregate_argument ( type , fields ) ; for ( int i = <NUM_LIT> ; i < n ; i ++ ) { num_float += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ; num_int += INTEGRAL_TYPE_P ( fields [ i ] . type


<s> if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic != InstrInfo . MaskAgnostic )


<s> bool hasStdExtZbf ( ) const { return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return ! isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT>


<s> SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Val , Mask , VL ; if ( const auto * VPStore = dyn_cast < VPStoreSDNode > ( Op ) ) { Val = VPStore -> getValue ( ) ; Mask = VPStore -> getMask ( ) ; VL = VPStore -> getVectorLength ( ) ; } else { const auto * MStore = cast < MaskedStoreSDNode > ( Op ) ; Val = MStore -> getValue ( ) ; Mask = MStore -> getMask ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT .


<s> for ( unsigned int pred_idx = <NUM_LIT> ; group . preds [ pred_idx ] != NUM_PRED_TYPES ; ++ pred_idx ) for ( unsigned


<s> if ( ! StartVal ) return std :: make_pair ( nullptr , nullptr ) ; APInt StrideVal ( StartVal -> getValue ( ) . getBitWidth ( ) , <NUM_LIT> ) ; ConstantInt * Prev = StartVal ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { auto * C = dyn_cast_or_null < ConstantInt > ( StartC -> getAggregateElement ( i ) ) ; if ( ! C ) return std :: make_pair ( nullptr , nullptr ) ; APInt LocalStride = C -> getValue ( ) - Prev -> getValue ( ) ; if ( i == <NUM_LIT> ) StrideVal = LocalStride ; else if ( StrideVal != LocalStride ) return std :: make_pair ( nullptr , nullptr ) ; Prev = C ; } Value * Stride = ConstantInt :: get ( StartVal -> getType ( ) , StrideVal ) ; return std :: make_pair ( StartVal , Stride


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType


<s> } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . addReg ( Base ) . addReg ( VL ) ; } MBBI -> eraseFromParent ( ) ; return true


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( DataTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( DataTy , Align ( Alignment ) ) ) )


<s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ; StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ; I = std :: find_if ( B , E , isdigit ) ; Prefix = StringRef ( B , I - B ) ; if ( I == E ) return std


<s> bool hasStdExtZvlsseg ( ) const { return


<s> switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering ::


<s> Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr ,


<s> FunctionPass * llvm :: create<ISA_LIT>PulpHWLoopsPass (


<s> SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) ,


<s> std :: tie ( LMul , Fractional ) = <ISA_LIT>VType :: decodeVLMUL ( VLMul ) ; LMul = Fractional ? ( <NUM_LIT> / LMul ) : ( LMul * <NUM_LIT> ) ; assert ( SEW >= <NUM_LIT> && <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( unsigned VTypeI , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ; Op -> VType . Val = VTypeI ; Op -> StartLoc


<s> uint64_t getRVVPadding ( ) const { return RVVPadding


<s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression (


<s> unsigned <ISA_LIT>TargetLowering :: getSubregIndexByMVT ( MVT VT , unsigned Index ) { <STR_LIT> LMUL = getLMUL ( VT ) ; if ( LMUL == <STR_LIT> :: LMUL_F8 || LMUL == <STR_LIT> :: LMUL_F4 || LMUL == <STR_LIT> :: LMUL_F2 || LMUL == <STR_LIT> :: LMUL_1 ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; return <STR_LIT>


<s> unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) return MatchOperand_NoMatch ; } getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E ) ) ; } return MatchOperand_Success


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = TM . getTargetCPU (


<s> return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == <STR_LIT> ) { if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; } BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( <NUM_LIT> ) . addImm


<s> bool pass_vsetvl :: can_refine_vsetvl_p ( const basic_block cfg_bb , const vector_insn_info & info ) const { if ( ! m_vector_manager -> all_same_ratio_p ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; if ( ! m_vector_manager -> all_same_avl_p ( cfg_bb , m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; size_t expr_id = bitmap_first_set_bit ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> same_vlmax_p ( info ) ) return false ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> compatible_avl_p ( info ) ) return false ; edge e ; edge_iterator ei ; bool all_valid_p = true ; FOR_EACH_EDGE ( e , ei , cfg_bb ->


<s> uint64_t FrameSize = MFI . getStackSize ( ) ; for ( int ID = MFI . getObjectIndexBegin ( ) , EID = MFI . getObjectIndexEnd ( ) ; ID < EID ; ID ++ ) { if ( MFI . getStackID ( ID ) == TargetStackID :: <ISA_LIT>Vector && ! MFI . isDeadObjectIndex ( ID ) ) { FrameSize = alignTo ( FrameSize , TRI -> getSpillAlignment ( <STR_LIT> ) ) ; FrameSize += TRI -> getSpillSize (


<s> FOR_BB_INSNS ( bb , insn ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( m -> get_or_insert ( regno ) > <NUM_LIT> ) { if ( extend ) { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( XEXP ( mem , <NUM_LIT> ) ) ) ; XEXP ( XEXP ( pat , i ) , <NUM_LIT> ) = replace_equiv_address ( XEXP ( mem , <NUM_LIT> ) , addr ) ; } else { addr = targetm . legitimize_address ( addr , addr , GET_MODE ( mem ) ) ; XEXP ( pat , i ) = replace_equiv_address


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCContext & Ctx = Asm . getContext ( ) ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt ,


<s> assert ( ABI != <STR_LIT> && <STR_LIT> ) ; TargetABI = ABI


<s> bool isRV32E ( ) const { return IsRV32E


<s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGFFMask ( SDNode * Node ) { SDLoc DL ( Node ) ; unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs ,


<s> if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT>


<s> YamlIO . mapOptional ( <STR_LIT> , MFI


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionCapMode (


<s> case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return


<s> assert ( EEW == InstrInfo . SEW && <STR_LIT> ) ; if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( ! InstrInfo . StoreOp && ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic != InstrInfo . MaskAgnostic


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; } MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } if ( ! isNullConstant ( Idx ) ) { SDValue VL = DAG . getConstant ( <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( )


<s> return isSimpleMove ( MI , FrameIndex ,


<s> if ( FRM == <STR_LIT> ) return SDValue ( ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc ; if ( SatVT == DstVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstVT == <STR_LIT> && SatVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ; SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , DL , DstVT ) ; return DAG . getSelectCC ( DL , Src , Src , ZeroInt , FpToInt , <STR_LIT> ::


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res .


<s> static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst


<s> const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT


<s> int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : case CCValAssign :: BCvt : ExtType = <STR_LIT> ; break ; } Val = DAG . getExtLoad ( ExtType , DL , LocVT , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) ,


<s> static bool avl_unavailable_p ( const vector_insn_info & info1 , const


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > &


<s> dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; if ( epilogue_cfa_sp_offset && REGNO ( reg ) == HARD_FRAME_POINTER_REGNUM ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( epilogue_cfa_sp_offset ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx ,


<s> break ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT>


<s> return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > (

RVVVectorLMULMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { assert ( LastInst . getDesc ( ) .

isConditionalBranch ( ) && <STR_LIT> ) ;


<s> } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst .


<s> if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) switch ( width ) { case <NUM_LIT> : if ( TARGET_ZFHMIN ) return <STR_LIT> ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) switch ( width ) { case <NUM_LIT> : if ( TARGET_ZFH ) return <STR_LIT> ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( dest_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT>


<s> if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) )


<s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc :: Model RM , CodeModel ::


<s> } if ( BINARY_P ( expr ) ) { op1_val = eval_value ( XEXP ( expr , <NUM_LIT> ) , regno_to_rtx ) ; op2_val = eval_value ( XEXP ( expr , <NUM_LIT> ) , regno_to_rtx ) ; } switch ( GET_CODE ( expr ) ) { case CONST_POLY_INT : return rtx_to_poly_int64 ( expr ) ; case CONST_INT : return INTVAL ( expr ) ; case MULT : if ( op1_val . is_constant ( ) ) return op1_val . to_constant ( ) * op2_val ; else if ( op2_val . is_constant ( ) ) return op1_val * op2_val . to_constant


<s> return true ; } if ( selectImpl ( I , *


<s> bool <ISA_LIT>InsertVSETVLI :: needVSETVLI ( const VSETVLIInfo & Require , const VSETVLIInfo & CurInfo ) { if ( CurInfo . isCompatible ( Require , false ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI (


<s> const FeatureBitset & FeatureBits = static_cast < const MCDisassembler * > ( Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool IsRV32E = FeatureBits [ <STR_LIT> ] ; if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) )


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; SmallVector < MachineOperand , <NUM_LIT> > ThisCond ; ThisCond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( )


<s> <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( MaskedOff ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , NF + <NUM_LIT> ) , SDValue ( Load ,


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister

, RegState :: Kill ) . addReg ( VL , RegState :: Kill ) ;


<s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type


<s> SDValue <ISA_LIT>TargetLowering :: lowerMaskedGather ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; const auto * MemSD = cast < MemSDNode > ( Op . getNode ( ) ) ; EVT MemVT = MemSD -> getMemoryVT ( ) ; MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; <STR_LIT> LoadExtType ; SDValue Index , Mask , PassThru , VL ; if ( auto * VPGN = dyn_cast < VPGatherSDNode > ( Op . getNode ( ) ) ) { Index = VPGN -> getIndex ( ) ; Mask = VPGN -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPGN -> getVectorLength ( ) ; LoadExtType = <STR_LIT> ; } else { auto * MGN = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; Index = MGN -> getIndex ( ) ; Mask = MGN -> getMask ( ) ; PassThru = MGN -> getPassThru ( ) ; LoadExtType = MGN -> getExtensionType ( ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( LoadExtType == <STR_LIT> && <STR_LIT> ) ; ( void ) LoadExtType ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; if ( XLenVT == <STR_LIT> && IndexVT . getVectorElementType ( ) . bitsGT ( XLenVT ) ) { IndexVT = IndexVT . changeVectorElementType ( XLenVT ) ; SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , Mask . getValueType ( ) , VL ) ; Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ; } unsigned IntID = IsUnmasked ? <STR_LIT> :


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = TT . isArch64Bit ( ) ?


<s> static SDValue getTargetNode ( JumpTableSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetJumpTable ( N -> getIndex


<s> static int64_t getBaseAdjustForCompression ( int64_t Offset , unsigned Opcode ) { return Offset & ~ compressedLDSTOffsetMask (


<s> InstructionCost <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * VTy , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( ! isa < FixedVectorType > ( VTy ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( VTy -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( ! ST -> useRVVForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( VTy -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; int ISD = TLI ->


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( STI , OSABI


<s> } StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: getVariantKindForName ( Identifier ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { return MatchOperand_ParseFail


<s> SDValue NewWOp = DAG . getNode ( N -> getOpcode ( ) , DL , <STR_LIT> , NewOp0 , NewOp1 ) ; SDValue NewRes = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewWOp , DAG


<s> if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; return MoveF64FrameIndex


<s> default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |=


<s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT (


<s> inline static <STR_LIT> getVLMUL ( unsigned VType ) { unsigned VLMUL = VType & <NUM_LIT>


<s> unsigned BitWidth = IsWInstruction ? <NUM_LIT> : VT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( BitWidth ) && <STR_LIT> ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; if ( BitWidth < <NUM_LIT> || ShAmt1 != ( BitWidth / <NUM_LIT> ) || ShAmt2 != ( BitWidth - <NUM_LIT> ) ) return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt = ShAmt1 ^ ShAmt2 ; if ( CombinedShAmt == <NUM_LIT> ) return Src ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( CombinedShAmt , DL , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ; if ( ! IsWInstruction ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG .


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - XLenInBytes ; SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant (


<s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> OS << getRegisterName ( MI -> getOperand ( opNum + <NUM_LIT> ) .


<s> MVT VecVT = VectorVal . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL


<s> static bool isCompressedReg ( Register Reg ) { return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg


<s> bool hasStdExtZhinx ( ) const { return HasStdExtZhinx


<s> MachineInstr * PrevVSETVLI = nullptr ; for ( auto MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) { PrevVSETVLI = nullptr


<s> uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write ( Bits ) ; ++ MCNumEmitted


<s> return ! Subtarget . useRVVForFixedLengthVectors ( ) || ( VT . isFixedLengthVector ( ) && VT . getVectorElementType (


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return riscv_classify_symbol ( x


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG &


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { if ( ! hasFP ( MF ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI .


<s> return static_cast < int8_t > ( MergeOpIndex


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>InsertVSETVLIPass


<s> bool hasVInstructionsI64 ( ) const { return HasStdExtV


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind =


<s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { MaskedOff , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( NF + <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( )


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG ,


<s> unsigned MaskOpIdx = I -> MaskOpIdx ; if ( ! isa < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) || cast < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) -> getReg ( ) != <STR_LIT> ) return false ; const auto * Glued = N -> getGluedNode ( ) ; if ( ! Glued || Glued -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) || cast < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; SDValue MaskSetter = Glued -> getOperand ( <NUM_LIT> ) ; const auto IsVMSet = [ ] ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; } ; if ( ! MaskSetter -> isMachineOpcode ( ) || ! IsVMSet ( MaskSetter . getMachineOpcode ( ) ) ) return false ; Optional < unsigned > TailPolicyOpIdx ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MaskedMCID = TII -> get ( N -> getMachineOpcode ( ) ) ; bool IsTA = true ; if ( <STR_LIT> ( MaskedMCID . TSFlags ) ) { TailPolicyOpIdx = N -> getNumOperands ( ) - <NUM_LIT> ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( ! ( N -> getConstantOperandVal ( * TailPolicyOpIdx ) & <STR_LIT> ) ) { if ( I -> UnmaskedTUPseudo == I -> MaskedPseudo && ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; if ( ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) IsTA = false ; } } if ( IsTA ) { uint64_t TSFlags = TII -> get ( I -> UnmaskedPseudo ) . TSFlags ; assert ( ! <STR_LIT> ( TSFlags ) && <STR_LIT> ( TSFlags ) && ! <STR_LIT> (


<s> return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , true ,


<s> rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { rinsn = insn -> rtl ( ) ; gcc_assert ( vsetvl_insn_p ( rinsn ) && <STR_LIT> ) ; } else { gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl (


<s> bool <ISA_LIT>TargetLowering :: isLegalElementTypeForRVV ( Type * ScalarTy ) const { if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return Subtarget . hasVInstructionsI64 ( ) ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasVInstructionsF16 ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasVInstructionsF32 ( ) ; if ( ScalarTy -> isDoubleTy ( ) ) return Subtarget


<s> errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI =


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: riscv , false > A ( The<ISA_LIT>Target ,


<s> bool hasStdExtZbp ( ) const { return HasStdExtZbp


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'f' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler


<s> static bool hasFixedResult ( const VSETVLIInfo & Info , const <ISA_LIT>Subtarget & ST ) { if ( ! Info . hasAVLImm ( ) ) return <STR_LIT> == Info . getAVLReg ( ) ; unsigned AVL = Info


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - StackSize + RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameDestroy ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg ,

StackSize , MachineInstr :: FrameDestroy ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode ::


<s> Inst . addOperand ( MCOperand :: createImm (


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable (


<s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N )


<s> static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> )


<s> int <ISA_LIT>TTIImpl :: getIntImmCost ( <STR_LIT> IID , unsigned Idx , const APInt & Imm ,


<s> inline bool registered_function_hasher :: equal ( value_type value , const compare_type & key ) { return value -> instance == key


<s> if ( ST -> hasVInstructions ( ) && MaxVectorSizeInBits != <NUM_LIT> ) return MaxVectorSizeInBits / <STR_LIT> ; return BaseT :: getMaxVScale


<s> if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set


<s> static rtx riscv_emit_binary ( enum rtx_code code , rtx dest ,


<s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; return true


<s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) VL = CurDAG -> getTargetConstant

( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) , VT ) ) return true ; return