<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Scalar . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) Scalar = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scalar ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar ) ; } case <STR_LIT> : { const auto & MF = DAG . getMachineFunction ( ) ; const auto * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned Reg = RegInfo -> getLocalAddressRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , Op . getSimpleValueType ( ) ) ; } case <STR_LIT> : { SDValue FnOp = Op .


<s> const CallLowering * getCallLowering ( ) const override { return CL . get ( )


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , const TargetOptions & Options ) { std :: string dataLayout = <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; return dataLayout


<s> return ( uint16x4_t ) __builtin_neon_vrshluv4hi ( ( int16x4_t


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertOpc , InsSubRegIdx ; std :: tie ( InsertOpc , InsSubRegIdx ) = getInsertVecEltOpInfo ( FPRBank , ScalarTy . getSizeInBits ( ) ) ; if ( ! Dst ) Dst = MRI . createVirtualRegister ( DstRC ) ; auto InsElt = MIRBuilder . buildInstr ( InsertOpc , { * Dst } , { WidenedOp1 -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) . addImm ( <NUM_LIT> ) . addUse ( WidenedOp2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * InsElt , TII , TRI , RBI


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken


<s> break ; case <STR_LIT> : Type = <STR_LIT> ; break ; default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare . getOpcode ( ) , Type , & Compare ) ; if ( ! FusedOpcode ) return false ; Register SrcReg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( ( Type == <STR_LIT> || Type == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . add ( Compare . getOperand ( I ) ) ; MIB . add ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . add ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) { MIB . add ( Target ) ; MIB . addRegMask ( RegMask ) ; } MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MBBI -> clearRegisterKills ( SrcReg , TRI ) ; if ( SrcReg2 ) MBBI -> clearRegisterKills ( SrcReg2 , TRI ) ; } FusedComparisons += <NUM_LIT> ; return


<s> MachineMemOperand * MO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addConstantPoolIndex ( CPI ) . addMemOperand ( MO ) ; GlobalBaseReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) ; CFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , const Triple & TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT , true ) , Subtype ( st ) { HasDataInCodeSupport =


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPLoad ( SMLoc Loc ) { if ( AssemblerOptions . back ( ) -> isReorder ( ) ) Warning ( Loc , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Reg ; OperandMatchResultTy ResTy = parseAnyRegister ( Reg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT>


<s> if ( delayHasHazard ( * I , RegDU , IM ) ) continue ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( I -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( I -> getOperand ( AddrIdx ) . getReg ( )

) ) || I -> modifiesRegister ( <STR_LIT> , TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ) continue ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )

. addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> virtual bool gate ( function * fun ATTRIBUTE_UNUSED ) { return pru_current_abi


, <NUM_LIT> , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ; return MIB . addReg ( Reg , State ,


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , CondBranches


<s> return isIntS34Immediate ( Op . getNode


<s> if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , true ) ; O << * NLPSym ; return ; } case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage (


<s>
if
(
Reg
==
BasePointerReg
)
SavedRegs
.
set
(
Reg
)
;
bool
RegUsed
=
SavedRegs
.
test
(
Reg
)
;
unsigned
PairedReg
=
<STR_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
producePairRegisters
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
if
(
MF
.
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
&&
!
Subtarget
.
isTargetWindows
(
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
}
unsigned
CSStackSize
=
<NUM_LIT>
;
unsigned
SVECSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
{
auto
RegSize
=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
SVECSStackSize
+=
RegSize
;
else
CSStackSize
+=
RegSize
;
}
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
uint64_t
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(


<s> } break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case REG : if ( ! IS_PSEUDO_P ( operands [ <NUM_LIT> ] ) ) { int r = REGNO ( operands [ <NUM_LIT> ] ) ; sh = gen_rtx_REG ( nmode , r ) ; sl = gen_rtx_REG ( nmode , r + HARD_REGNO_NREGS ( r , nmode ) ) ; } else { sh = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ; sl = gen_rtx_SUBREG ( nmode , operands [ <NUM_LIT> ] , GET_MODE_SIZE ( nmode ) ) ; } break ; case CONST_DOUBLE : if ( operands [ <NUM_LIT> ] == const0_rtx ) sh = sl = const0_rtx ; else split_double ( operands [ <NUM_LIT> ] , & sh , & sl ) ; break ; case CONST_INT : if ( operands [ <NUM_LIT> ] == const0_rtx ) sh = sl = const0_rtx ; else { int vl , vh ; switch ( nmode ) { default : gcc_unreachable ( ) ; } sl = GEN_INT ( vl ) ; sh = GEN_INT ( vh ) ; } break ; case SUBREG : sl = gen_rtx_SUBREG ( nmode , SUBREG_REG ( operands [ <NUM_LIT> ] ) , SUBREG_BYTE ( operands [ <NUM_LIT> ] ) + GET_MODE_SIZE ( nmode ) ) ; sh = gen_rtx_SUBREG ( nmode , SUBREG_REG ( operands [ <NUM_LIT> ] ) , SUBREG_BYTE


<s> EVT VT = Op . getValueType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthVECTOR_SHUFFLEToSVE ( Op , DAG ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; assert ( V1 . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ShuffleMask . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 . getOperand ( <NUM_LIT> ) ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( Lane ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( Lane ) ) ; unsigned Opcode = getDUPLANEOp ( V1 . getValueType ( ) . getVectorElementType ( ) ) ; return constructDup ( V1 , Lane , dl , VT , Opcode , DAG ) ; } for ( unsigned LaneSize : { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) { unsigned Lane = <NUM_LIT> ; if ( isWideDUPMask ( ShuffleMask , VT , LaneSize , Lane ) ) { unsigned Opcode = LaneSize == <NUM_LIT> ? <STR_LIT> : LaneSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MVT NewEltTy = <STR_LIT> ( LaneSize ) ; unsigned NewEltCount = VT . getSizeInBits ( ) / LaneSize ; MVT NewVecTy = <STR_LIT> ( NewEltTy , NewEltCount ) ; V1 = DAG . getBitcast ( NewVecTy , V1 ) ; V1 = constructDup ( V1 , Lane , dl , NewVecTy , Opcode , DAG ) ; return DAG . getBitcast ( VT , V1 ) ; } } if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( ( ( VT . getVectorNumElements ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( VT . getVectorNumElements (

) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) && ShuffleVectorInst :: isReverseMask ( ShuffleMask ) ) {


<s> vmlsq_n_s32 ( int32x4_t a , int32x4_t b , int32_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize =


<s> bool <ISA_LIT>TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee


<s> APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG ) ; TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Op1 , DemandedMask ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ; } return SDValue (


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned NewImm ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL


<s> Value * <ISA_LIT>IREmitter :: visitATOMUMAX64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return S ; } if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( <NUM_LIT> + ( Imm & <NUM_LIT>


<s> if ( code >= ARM_BUILTIN_MAX ) return error_mark_node ; return arm_builtin_decls [


<s> assert ( isLegal ( MI , TII ) && <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) ) . add ( { MI -> getOperand ( <NUM_LIT> ) , MI -> getOperand ( SrcOpIdx ) } ) ; return


<s> gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == <NUM_LIT> ) ; rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , <NUM_LIT> ) ) ; rtx hi = GEN_INT ( CONST_WIDE_INT_ELT ( imm , <NUM_LIT> )


<s> getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; forbidModuleDirective (


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering . getPointerTy ( ) == <STR_LIT> ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII .


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getBFTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI .


<s> DItype __fixtfdi ( TFtype a ) { if ( a < <NUM_LIT> ) return - __fixunstfdi ( - a ) ; return __fixunstfdi (


<s> bool isPICStyleStubAny ( ) const { return PICStyle == PICStyles :: StubDynamicNoPIC || PICStyle == PICStyles ::


<s> MCRelocationInfo * create<ISA_LIT>ElfRelocation ( const Triple & TheTriple ,


<s> static HOST_WIDE_INT mips_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return


<s> assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( SDValue Rotate = lowerShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 ,


<s> static bool hasPartialRegUpdate ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code64 ) ; } }


<s> ZeroOperandPosition = I -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - <NUM_LIT> ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I


<s> unsigned Bit = ( Value >> i ) & <NUM_LIT> ; if ( ( Value & ~ ( ~ <NUM_LIT> << i ) ) == <NUM_LIT> ) { Imm |= ( <NUM_LIT> << i ) ; break ; } if ( Bit != PrevBit ) Imm |= ( <NUM_LIT> << i ) ; PrevBit = Bit ; } return Imm


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero

, DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinUnwindCode ( unsigned UnwindCode , int Reg , int Offset ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; MCSymbol * Label = S . emitCFILabel ( ) ; auto Inst = WinEH :: Instruction ( UnwindCode , Label ,


<s> } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned NewImm ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , & NewImm ) ; BuildMI ( MBB , II , DL , TII . get ( ADDu ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg =


<s> const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( hasConsumedDollar ) { hasConsumedDollar = false ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer (


<s> if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return


<s> BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( RetrySwapVal ) . addReg ( NegBitShift


<s> bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveInst (


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue Sub = Op0 . getOperand ( <NUM_LIT> ) ; if ( Sub . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = Sub . getOperand ( <NUM_LIT> ) ; SDValue SubOp1 = Sub . getOperand ( <NUM_LIT> ) ; if ( ( SubOp0 . getOpcode ( ) == <STR_LIT> ) && ( SubOp1 . getOpcode ( ) == <STR_LIT> ) ) { return DCI . DAG . getNode ( <STR_LIT> , dl , VT , SubOp0 . getOperand ( <NUM_LIT> ) , SubOp1 . getOperand ( <NUM_LIT> ) , DCI . DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } } if ( Op0 . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; int EltToExtract = DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ConstNode = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstNode || ConstNode -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; EltToExtract = EltToExtract ? <NUM_LIT> : <NUM_LIT> ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bitcast = DCI . DAG . getBitcast ( <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bitcast , DCI . DAG . getTargetConstant ( EltToExtract , dl , <STR_LIT> ) ) ; } return SDValue


<s> return __builtin_mve_vqrshrntq_n_sv4si ( __a ,


<s> break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case ABSU_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } combined_fn cfn ; if ( ( kind == vector_stmt || kind == scalar_stmt ) && stmt_info && stmt_info -> stmt && ( cfn = gimple_call_combined_fn ( stmt_info -> stmt ) ) != CFN_LAST ) switch ( cfn ) { case CFN_FMA : stmt_cost = ix86_vec_cost ( mode , mode == SFmode ? ix86_cost -> fmass : ix86_cost -> fmasd ) ; break ; default : break ; } if ( ( kind == vec_construct || kind == vec_to_scalar ) && stmt_info && ( STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type || STMT_VINFO_TYPE ( stmt_info ) == store_vec_info_type ) && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost *= ( TYPE_VECTOR_SUBPARTS ( vectype ) + <NUM_LIT> ) ; } if ( stmt_cost == - <NUM_LIT> ) stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= <NUM_LIT> ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info ->


<s> uint32_t getAddrModeISOpValue ( const MachineInstr & MI


<s> SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & RetOps [ <NUM_LIT> ] , RetOps


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT>


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success


const_tree type , bool named ATTRIBUTE_UNUSED ) {


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ; else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg


<s> if ( ! isDoubleSpacedVectorAllLanes (


<s> tree v2sf_ftype_long_pcfloat = build_function_type_list ( V2SF_type_node , long_integer_type_node , pcfloat_type_node , NULL_TREE ) ; tree void_ftype_v2sf_long_pcfloat = build_function_type_list ( void_type_node , V2SF_type_node , long_integer_type_node , pcfloat_type_node , NULL_TREE ) ; def_builtin ( <STR_LIT> , v2sf_ftype_long_pcfloat , PAIRED_BUILTIN_LX ) ; def_builtin ( <STR_LIT> , void_ftype_v2sf_long_pcfloat , PAIRED_BUILTIN_STX ) ; d = bdesc_paired_preds ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; ++ i , d ++ ) { tree type ; HOST_WIDE_INT mask = d -> mask ; if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } gcc_assert ( d -> icode != CODE_FOR_nothing ) ; if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , ( int ) i , get_insn_name ( d -> icode ) , ( int ) d -> icode , GET_MODE_NAME ( insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ) ) ; switch ( insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ) { case


<s> static bool isLDSTPIIMM ( InsnType insn ) { return ( ( ( insn ) & <NUM_LIT> )


<s> if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > <NUM_LIT> ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode


<s> class LLVM_LIBRARY_VISIBILITY <ISA_LIT>MCInstLower { MCContext & Ctx ; Mangler * Mang ; const MachineFunction & MF ; const TargetMachine & TM ; const MCAsmInfo & MAI ; <ISA_LIT>AsmPrinter & AsmPrinter ; public : <ISA_LIT>MCInstLower ( Mangler * mang , const MachineFunction & MF


<s> auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT> ) / <NUM_LIT> ; Align Alignment = commonAlignment ( TFL -> getStackAlign ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand


<s> static bool isConstantOrUndef ( int Op , int


<s> CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize )


<s> bool hasVDSPV2_HALF ( ) const { return HasVDSPV2 && UseHardFloat


<s> offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == <NUM_LIT> ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > <NUM_LIT> ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign


<s> std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ; CMovI . getOperand ( CMovI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . setImm ( Inverted ? <STR_LIT> : <STR_LIT> ) ; FlagUse . setIsKill ( true


<s> static void aarch64_emit_mult ( rtx dst , rtx ptrue , rtx src1 , rtx src2 ) { if ( ptrue ) emit_insn ( gen_aarch64_pred ( UNSPEC_COND_FMUL , GET_MODE ( dst ) , dst , ptrue , src1 , src2 , gen_int_mode ( SVE_RELAXED_GP , SImode ) ) ) ; else emit_set_insn ( dst , gen_rtx_MULT ( GET_MODE ( dst )


<s> SDValue CsetOp = CmpOp -> getOperand ( IsAdd ? <NUM_LIT> : <NUM_LIT> ) ; auto CC = getCSETCondCode ( CsetOp ) ; if ( CC != ( IsAdd ? <STR_LIT> : <STR_LIT> ) ) return SDValue ( ) ; return DAG . getNode ( Op -> getOpcode ( ) , SDLoc ( Op ) , Op -> getVTList ( ) , Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand (

<NUM_LIT> ) , CsetOp . getOperand ( <NUM_LIT> ) ) ;


<s> Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( PredStateReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y


<s> return getLoadStoreRegOpcode ( DestReg , RC , isStackAligned


<s> static DecodeStatus DecodeLoadF32 ( MCInst & Inst , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMem ( Inst , insn , Address ,

Decoder , true , DecodeF32RegisterClass ) ;


<s> bool hasMulDivAdd ( ) const { return


<s> bool isShrImm32 ( ) const { return isShrFixedWidth ( <NUM_LIT>


<s> unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ?


<s> static SDValue foldTruncStoreOfExt ( SelectionDAG & DAG , SDNode * N ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( auto Store = dyn_cast < StoreSDNode > ( N ) ) { if ( ! Store -> isTruncatingStore ( ) || Store -> isIndexed ( ) ) return SDValue ( ) ; SDValue Ext = Store -> getValue ( ) ; auto ExtOpCode = Ext . getOpcode ( ) ; if ( ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> ) return SDValue ( ) ; SDValue Orig = Ext -> getOperand ( <NUM_LIT>


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) && MF .

getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) ;


<s> return regno ; } if ( crtl -> is_leaf ) { for ( regno = GR_REG ( <NUM_LIT> ) ; regno <= GR_REG ( <NUM_LIT> ) ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_or_fixed_reg_p ( regno ) && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & <NUM_LIT> ) == <NUM_LIT> && ! is_emitted ( regno ) ) { current_frame_info . gr_used_mask |=


<s> EVT SVT = VT . getVectorElementType ( ) ; EVT InVT = In . getValueType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && InVT == <STR_LIT> && VT == <STR_LIT> ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , <STR_LIT> , USatVal , DL , DAG , Subtarget ) ; assert ( Mid && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mid ) ; } } bool PreferAVX512 = ( ( Subtarget . hasAVX512 ( ) && InSVT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && InSVT == <STR_LIT> ) ) && ( InVT . getSizeInBits ( ) > <NUM_LIT> ) && ( Subtarget . hasVLX ( ) || InVT . getSizeInBits ( ) > <NUM_LIT> ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! PreferAVX512 && VT . getSizeInBits ( ) >= <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT>


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveFRegP ( unsigned Reg , int


<s> void <ISA_LIT>InstrInfo :: insertOutlinerEpilogue ( MachineBasicBlock & MBB , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . FrameConstructionID == MachineOutlinerTailCall )


<s> assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry ; if ( Subtarget -> has<ISA_LIT>32II ( ) ) Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; else { SDNode * StatusWord = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDValue Constant1 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , VT ) ; Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( StatusWord


<s> unsigned Shift = ( NumLaneElts == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt %= NumLaneElts ; unsigned ShAmt = i << Shift ; if ( ShAmt >= <NUM_LIT> ) ShAmt -= <NUM_LIT> ; Mask |= Elt <<


<s> return decodeSImmOperand < <NUM_LIT> > ( Inst


<s> enum resolver_ident arm_describe_resolver ( tree fndecl ) { if ( DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1qv16qi && DECL_MD_FUNCTION_CODE ( fndecl ) < ARM_BUILTIN_MVE_BASE ) return arm_cde_resolver ; return


<s> auto IsFreeTruncation = [ & ] ( Value * Op ) { if ( auto * Cast = dyn_cast < CastInst > ( Op ) ) { if ( Cast -> getParent ( ) == Mul -> getParent ( ) && ( Cast -> getOpcode ( ) == Instruction :: SExt || Cast -> getOpcode ( ) == Instruction :: ZExt ) && Cast -> getOperand ( <NUM_LIT> )

-> getType ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return true ;


<s> static tree pa_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT ) abi = <STR_LIT> ; else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return


<s> OutStreamer . EmitLabel ( StubLabel ) ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue


<s> if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } return S


<s> void <ISA_LIT>MCAsmStreamer :: EmitBundleUnlock


<s> bool WasOriginalRetVectorFloat ( unsigned ValNo )


<s> bool inMicro<ISA_LIT>32r6Mode ( ) const { return InMicro<ISA_LIT>Mode && has<ISA_LIT>32r6 ( )


<s> <STR_LIT> Flags ; Flags . setOrigAlign ( DL . getABITypeAlign ( ArgTy ) ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = constrainOperandRegClass ( TII . get ( CallOpc ) , CalleeReg , isThumb2 ? <NUM_LIT> : <NUM_LIT> ) ; MIB . addReg ( CalleeReg ) ; } else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < Register , <NUM_LIT> >


<s> static void iq2000_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < <NUM_LIT> ) iq2000_save_gp_regs = <NUM_LIT> ; if ( iq2000_save_fp_regs < <NUM_LIT> ) iq2000_save_fp_regs = <NUM_LIT> ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM ( BLKmode , ptr


<s> return ; } const auto & Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ASanAccessInfo AccessInfo ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; uint64_t ShadowBase ; int MappingScale ; bool OrShadowOffset ; getAddressSanitizerParams ( Triple ( TM . getTargetTriple ( ) ) , <NUM_LIT> , AccessInfo . CompileKernel , & ShadowBase , & MappingScale , & OrShadowOffset ) ; StringRef Name = AccessInfo . IsWrite ? <STR_LIT> :


<s> set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , base == reg ? NULL_RTX


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN


<s> static __inline qword si_rotqby ( qword a , qword count ) { vec_uchar16 left , right ; left = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT>


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < <NUM_LIT> ) return regno ; if ( IS_FPA_REGNUM ( regno ) ) return ( TARGET_AAPCS_BASED ? <NUM_LIT> : <NUM_LIT> ) + regno - FIRST_FPA_REGNUM ; if ( IS_VFP_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return <NUM_LIT>


<s> unsigned NumEls = Op . getValueType ( ) . getVectorNumElements ( ) ; MVT ElemVT = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( SDValue ScalarV = getSplatValue ( Op . getNode ( ) ) ) { MVT LegalResVT = <STR_LIT> ( ElemVT , <NUM_LIT> ) ; auto AVL = DAG . getConstant ( NumEls , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , LegalResVT , Op . getOperand ( <NUM_LIT> ) , AVL ) ; } return SDValue (


<s> const SymbolListType & getGlobalGOTSyms ( ) const { return


<s> return ( __m128i ) __builtin_ia32_vpcomfalsed ( ( __v4si ) __A , (


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>16InstrInfo ( const <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>16InstrInfo


<s> if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree


<s> if ( ! isUIntN ( <NUM_LIT> , Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : if ( ! isIntN ( <NUM_LIT> , Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : if ( ! isIntN ( <NUM_LIT> , Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( )


<s> SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( isSigned ) { SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , BottomHalf , ShiftAmt ) ; TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , Tmp1 , <STR_LIT> ) ; } else { TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , DAG . getConstant ( <NUM_LIT> , VT ) , <STR_LIT> ) ; } DAG . DeleteNode ( MulResult . getNode ( ) ) ; SDValue Ops [ <NUM_LIT> ] = { BottomHalf


<s> rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode ,


<s> } } else { for ( unsigned i = BG . StartIdx ; i < Bits . size ( ) ; ++ i ) { if ( ! Bits [ i ] . hasValue ( ) ) continue ; if ( Bits [ i ] . getValueBitIndex ( ) >= <NUM_LIT> ) return false ; } for ( unsigned i = <NUM_LIT> ; i <= BG . EndIdx ; ++ i ) { if ( ! Bits [ i ] . hasValue ( ) ) continue ; if ( Bits [ i ] . getValueBitIndex ( ) >= <NUM_LIT> ) return false ; } } return true ; } ; for ( auto & BG : BitGroups ) { if ( BG . StartIdx < <NUM_LIT> && BG . EndIdx < <NUM_LIT> ) { if ( IsAllLow32 ( BG ) ) { if ( BG . RLAmt >= <NUM_LIT> ) { BG . RLAmt -= <NUM_LIT> ; BG . Repl32CR = true ; } BG . Repl32 = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BG . V . getNode ( ) << <STR_LIT> << BG . RLAmt << <STR_LIT> << BG . StartIdx << <STR_LIT> << BG . EndIdx << <STR_LIT> ) ; } } } for ( auto I = BitGroups . begin ( ) ; I != BitGroups . end ( ) ; ) { auto IP = ( I == BitGroups . begin ( ) ) ? std :: prev ( BitGroups . end ( ) )


<s> unsigned <STR_LIT> ( SDNode * N , unsigned EltSize ) { assert ( isSplatShuffleMask ( N , EltSize )


<s> <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; SDValue BrCode = DAG . getConstant ( getFPBranchCodeFromCond ( CC ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType (


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , int OpNum


<s> if ( ( hasQPX ( ) || isBGQ ( ) ) && ! isQPXStackUnaligned ( ) ) return <NUM_LIT> ; return


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( )


<s> return llvm :: all_of ( Mask , [ CmpVal ] (


<s> return isShlFixedWidth ( <NUM_LIT> )


<s> return __builtin_loongson_pinsrh_0_u ( s ,


<s> CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 =


<s> ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregoiv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregoiv2di_pss ( __o , <NUM_LIT> ) ; return


<s> if ( isIntS16Immediate ( CN , Imm ) && ( ! Align || isAligned ( * Align , Imm ) ) ) { Disp = DAG . getTargetConstant ( Imm , DL , CNType ) ; Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CNType ) ; break ; } if ( ( CNType == <STR_LIT> || isInt < <NUM_LIT> > ( CNImm ) ) && ( ! Align || isAligned ( * Align , CNImm ) ) ) { int32_t Addr = ( int32_t ) CNImm ; Disp = DAG . getTargetConstant ( ( int16_t ) Addr , DL , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( int16_t ) Addr ) >> <NUM_LIT> , DL , <STR_LIT> ) ; uint32_t LIS = CNType == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( LIS , DL , CNType , Base ) , <NUM_LIT> ) ; break ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else Base = N ; break ; } case <STR_LIT> : break ; default : { FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ; Base = FI ? N : N


<s> SDValue RetAddr ; if ( depth == <NUM_LIT> ) RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; else { SDValue Chain = getFLUSHW ( Op , DAG ) ; RetAddr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , VT ) ; for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetAddr , DAG . getIntPtrConstant ( ( i == depth -


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } return new <ISA_LIT>BasicMCBuilder ( Opcode , Format , <ISA_LIT>Insts


<s> HOST_WIDE_INT size = <NUM_LIT> ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE (


<s> case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED : case ORDERED : case UNEQ : case UNGE : case UNLT : case UNGT : case UNLE : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : return <NUM_LIT> ; case IOR : if ( TARGET_THUMB2 ) return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; return <NUM_LIT> ; case AND


<s> } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap


<s> default : break ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT>


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize


<s> RestoreReg ( Out , RegCtx . addressReg ( <STR_LIT> ) ) ; RestoreReg ( Out , RegCtx . shadowReg ( <STR_LIT> ) ) ; EmitAdjustRSP ( Ctx , Out , <NUM_LIT> ) ; unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( Ctx . getRegisterInfo ( ) && FrameReg != <STR_LIT> ) { RestoreReg ( Out , <STR_LIT>


<s> if ( callee_opts == caller_opts ) return true ; struct arm_build_target caller_target ; struct arm_build_target callee_target ; caller_target . isa = sbitmap_alloc ( isa_num_bits ) ; callee_target . isa = sbitmap_alloc ( isa_num_bits ) ; arm_configure_build_target ( & caller_target , caller_opts , false ) ; arm_configure_build_target ( & callee_target , callee_opts , false ) ; if ( ! bitmap_subset_p ( callee_target . isa , caller_target .


<s> if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG


<s> bool <ISA_LIT>LegalizerInfo :: legalizeCustom ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_VAARG : return legalizeVaArg ( MI , MRI , MIRBuilder ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; } llvm_unreachable (


<s> Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ; if ( I != E


<s> case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Subtarget . hasSPE ( ) && VA . getLocVT ( ) == <STR_LIT> ) { bool isLittleEndian = Subtarget . isLittleEndian ( ) ; SDValue SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ( <NUM_LIT> ) ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( <NUM_LIT> ) , DarwinDirective ( <STR_LIT> ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , Is<ISA_LIT>64 ( is64Bit ) , HasAltivec ( false ) , HasQPX ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS


<s> DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS ) , ExtType ) ; SDValue UMin = DAG . getNode ( <STR_LIT> , SDLoc ( SubusLHS ) , ExtType , SubusRHS , SaturationConst ) ; SDValue NewSubusLHS = DAG . getZExtOrTrunc ( SubusLHS , SDLoc ( SubusLHS ) , ShrinkedType ) ; SDValue NewSubusRHS = DAG . getZExtOrTrunc ( UMin , SDLoc ( SubusRHS ) , ShrinkedType ) ; SDValue Psubus = DAG . getNode ( <STR_LIT> , SDLoc

( N ) , ShrinkedType , NewSubusLHS , NewSubusRHS ) ;


<s> RegisterAsmLexer < <ISA_LIT>AsmLexer > X


<s> if ( Subtarget -> has<ISA_LIT>32 ( ) && SelectMsub ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( )


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qiv4hi ( (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>BLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; } return MO . getImm ( )


<s> static const struct processor * aarch64_get_tune_cpu ( enum aarch64_processor cpu ) { if ( cpu != aarch64_none ) return & all_cores [ cpu ] ; return & all_cores [ TARGET_CPU_DEFAULT & <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM


<s> if ( I . getOpcode ( ) == TargetOpcode :: G_GEP ) { if ( auto COff = getConstantVRegVal ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { int64_t Imm = * COff ; if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; return ; } } } else if ( I . getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) { AM . Base . FrameIndex = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; AM . BaseType = <STR_LIT> ; return ; } AM . Base . Reg = I . getOperand ( <NUM_LIT> )


<s> ops [ memnum ] = adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ; output_move_double ( ops , false , & count ) ; return


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( ! get<ISA_LIT>Subtarget ( ) . has<ISA_LIT>64 ( ) ) PM -> add ( create<ISA_LIT>EmitGPRestorePass (


<s> if ( Res . getConstant ( ) != <NUM_LIT> ) return ABI . IsN32 ( ) || ABI . IsN64 ( ) ; return true


<s> } SmallVector < MachineLoop * , <NUM_LIT> > Loops ( MLI -> begin ( ) , MLI -> end ( ) ) ; for ( int i = <NUM_LIT> ; i < ( int ) Loops . size ( ) ; ++ i ) for ( MachineLoop * Child : Loops [ i ] -> getSubLoops ( ) ) Loops . push_back ( Child ) ; for ( MachineLoop * CurrLoop : Loops ) { if ( ! CurrLoop -> getSubLoops ( ) . empty ( ) ) continue ; CmovGroups CmovInstGroups ; if ( ! collectCmovCandidates ( CurrLoop -> getBlocks ( ) , CmovInstGroups ) ) continue ; if ( ! checkForProfitableCmovCandidates ( CurrLoop -> getBlocks ( ) , CmovInstGroups ) ) continue ; Changed = true ; for ( auto & Group : CmovInstGroups ) convertCmovInstsToBranches ( Group ) ; } return Changed


<s> case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable (


<s> if ( VReg == <NUM_LIT> ) return <NUM_LIT> ; MVT VMVT = TLI . getValueType ( DL , V -> getType ( ) , true ) . getSimpleVT ( ) ; if ( ( VMVT == <STR_LIT> ) ||


<s> unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } assert ( NumNonZero == <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getVectorNumElements ( ) >= <NUM_LIT> ) return Op ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getUNDEF ( ResVT ) , Op

. getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> break ; case <STR_LIT> : Scale = <NUM_LIT> ; break ; } if ( ( V & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; V /= Scale ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> )


<s> bool isCRBitNumber ( ) const { return ( Kind == Expression && isUInt < <NUM_LIT> > ( getExprCRVal ( ) ) ) || ( Kind == Immediate && isUInt < <NUM_LIT> > ( getImm


<s> bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) , GlobalRef ) ; } if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalRef , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalRef


<s> bool <ISA_LIT>ConstantIslands :: findAvailableWater ( CPUser & U , unsigned UserOffset , water_iterator & WaterIter , bool CloserWater ) { if ( WaterList . empty ( ) ) return false ; unsigned BestGrowth = ~ <NUM_LIT> ; MachineBasicBlock * UserBB = U . MI -> getParent ( ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( getCPELogAlign ( U . CPEMI


<s> OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc

, getLoc ( ) , getContext ( ) , EqTy ) ) ;


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; }


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass ( create<ISA_LIT>Os16 ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloat ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( createPartiallyInlineLibCallsPass (


<s> void \ fini_section ( void ) \ { \ if ( in_section != in_fini ) \ { \ in_section

= in_fini ; \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ } \ }


<s> unsigned VF = SrcVTy -> getVectorNumElements ( ) ; auto getIndexSizeInBits = [ ] ( Value * Ptr , const DataLayout & DL ) { unsigned IndexSize = DL . getPointerSizeInBits ( ) ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( IndxTy -> isVectorTy ( ) ) IndxTy = IndxTy -> getVectorElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor > <NUM_LIT> ) { Type * SplitSrcTy = VectorType :: get ( SrcVTy -> getScalarType ( ) , VF / SplitFactor ) ; return SplitFactor * getGSVectorCost ( Opcode , SplitSrcTy , Ptr , Alignment , AddressSpace ) ; } const int GSOverhead = <NUM_LIT> ; return GSOverhead + VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment ,


<s> default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare . getOpcode ( ) , Type , & Compare ) ; if ( ! FusedOpcode ) return false ; unsigned SrcReg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . add ( Compare . getOperand ( I ) ) ; MIB . add ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . add ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) MIB . addRegMask ( RegMask ) ; MBBI = Compare


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags


<s> if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && ! isDispSafeForFrameIndex ( Val ) ) return true ; } AM . Disp


<s> MVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ElemTy == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ]


<s> bool existed ; const char * func_name = XSTR ( func , <NUM_LIT> ) ; rtx * slot = & mips16_local_aliases -> get_or_insert ( func_name , & existed ) ; gcc_assert ( slot != NULL ) ; if ( ! existed ) { rtx local


<s> int xstormy16_splittable_below100_operand ( rtx x , enum machine_mode mode ) { if ( GET_CODE ( x ) == MEM && MEM_VOLATILE_P ( x ) ) return <NUM_LIT> ; return xstormy16_below100_operand ( x , mode


<s> return ( uint16x4_t ) __builtin_neon_vreinterpretv4hidi


<s> int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; } MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; assert ( TII -> get ( Opcode ) . getNumOperands ( ) == <NUM_LIT> && TII -> get

( NewOpc ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt >= <NUM_LIT> ) { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } else OffReg = OffReg . getOperand ( <NUM_LIT> ) ; } else { ShOpcVal = <STR_LIT> ; } } ShImm = CurDAG -> getTargetConstant (


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res


<s> return ( __m256i ) __builtin_ia32_pmaxsw256_mask ( ( __v16hi ) __A , ( __v16hi )


<s> rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2


<s> if ( ! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return <NUM_LIT> ; else { const int mov_insn_sz = mov_insn_size ( mode , consider_sh2a ) ; const int mode_sz = GET_MODE_SIZE ( mode ) ; int r = <NUM_LIT> * mov_insn_sz * disp_scale ; if ( mode_sz > mov_insn_sz ) r -= mode_sz -


<s> switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) / <NUM_LIT> ; else if ( INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS


<s> bool BigStack = ( RS && estimateStackSize ( MF ) >= TII . estimateRSStackLimit ( MF ) ) || MFI -> hasVarSizedObjects ( ) || ( MFI -> adjustsStack ( ) && ! hasReservedCallFrame ( MF ) ) ; if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed


<s> if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias , * Mang ) ; OS . flush


<s> unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , TRI . getRegSizeInBits ( RC ) / <NUM_LIT> , false ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg


<s> ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition ( CC ) ) ; return


<s> if ( IsMicro<ISA_LIT> ) { Result = readInstruction16 ( Bytes , Address , Size , Insn , IsBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R616 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( has<ISA_LIT>32r6 ( ) && isFP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r6FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } if ( hasCOP3 ( )


<s> rtx pat ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode2


<s> DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT>


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , true ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ?

std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) :


__artificial__ ) ) _mm_setcsr ( unsigned int __I ) {


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; } bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue


<s> cmpOpcode = <STR_LIT> ; break ; } default : { I -> dump ( ) ; errs ( ) << <STR_LIT> ; check = false ; } } if ( check ) { assert ( loadOpcode != <NUM_LIT> ) ; assert ( cmpOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ; MIload -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { MIload -> addOperand ( MF , I -> getOperand ( opcount ) ) ; } MIload -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < MIload -> getNumOperands ( ) ; opcount ++ ) { if ( MIload -> getOperand ( opcount ) . isReg ( ) ) { MIload -> getOperand ( opcount ) . setReg ( getSlaveReg1 ( I

-> getOperand ( opcount ) . getReg ( ) ) ) ;


<s> MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent ( ) ; return


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ; return


<s> if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return


<s> EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; updateValueMap ( I , SrcReg ) ; return true


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( x ) && reg_set_p ( x , prev ) ) return true ; return false


<s> case <STR_LIT> : \ return <STR_LIT> ; case <STR_LIT> : \ case <STR_LIT> : \


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : <NUM_LIT> ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos ,

DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ;


<s> if ( bitmap_bit_p ( edge_components , <NUM_LIT> ) && bitmap_bit_p ( DF_LIVE_IN ( e -> dest ) , <NUM_LIT> ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , e -> dest -> index ) ; bitmap_clear_bit ( components , <NUM_LIT>


<s> if ( Data != std :: end ( IntrinsicsWithoutChain ) && Data ->


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI , getSubtargetInfo ( ) ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget )


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) { Reset ( )


<s> bool <ISA_LIT>MCCodeEmitter :: is<ISA_LIT>32r6 ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( )


<s> if ( PerformTailCallOpt && I -> getOpcode ( ) == <STR_LIT> ) { if ( int CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; CalleeAmt *= - <NUM_LIT> ; unsigned StackReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else


<s> static bool isCombineInstrCandidate64 ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> mem = XEXP ( set , opnum ) ; while ( GET_CODE ( mem ) == SUBREG ) mem = SUBREG_REG ( mem ) ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; return ( volatile_ok || ! MEM_VOLATILE_P (