<s> else { opcode = <NUM_LIT> ; size = <NUM_LIT> ; } mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , HImode ) ) ; mem = adjust_address ( m_tramp , ptr_mode , offset + <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = <NUM_LIT> ; break ; case CX_REG : opcode = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } else opcode = <NUM_LIT> ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + <NUM_LIT> ) ; emit_move_insn ( mem , chain_value


<s> return __builtin_ia32_vtestnzcps ( ( __v4sf ) __M , (


<s> fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; } if ( TARGET_ARCH32 && fixed_regs [ <NUM_LIT> ] ) fixed_regs [ <NUM_LIT> ] = <NUM_LIT> ; else if ( TARGET_ARCH64 && fixed_regs [ <NUM_LIT> ] == <NUM_LIT> ) fixed_regs [ <NUM_LIT> ] = <NUM_LIT> ; if ( ! TARGET_V9 ) { int regno ; for ( regno = SPARC_FIRST_V9_FP_REG ; regno <= SPARC_LAST_V9_FP_REG ; regno ++ ) fixed_regs [ regno ] = <NUM_LIT> ; for ( regno = SPARC_FIRST_V9_FCC_REG + <NUM_LIT> ; regno <= SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = <NUM_LIT> ; } if ( ! TARGET_FPU ) { int


<s> unsigned NumDefs = I . getNumOperands ( ) - <NUM_LIT> ; unsigned SrcReg = I . getOperand ( NumDefs ) . getReg ( ) ; unsigned DefSize = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) .


<s> void PreAnalyzeFormalArgumentsForF128_ ( const SmallVectorImpl < <STR_LIT> > &


<s> rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return <NUM_LIT> ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) { if ( REG_P ( early_op ) ) early_op


<s> static __inline void si_hgti ( qword a , signed int b ) { union { vector signed int


<s> vmode = aarch64_simd_container_mode ( mode , <NUM_LIT> ) ; rtx op_v = aarch64_simd_gen_const_vector_dup ( vmode , INTVAL


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . v =


<s> static DecodeStatus decodeU16ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t


<s> bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb232 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return checkDecodedInstruction ( MI , Size , Address , CS , Insn32 , Result ) ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableVFP32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( Result , MI ) ; return Result ; } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONDataInsn = Insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } uint32_t NEONCryptoInsn = Insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } uint32_t NEONv8Insn = Insn32 ; NEONv8Insn &= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8NEON32 , MI , NEONv8Insn , Address , this


<s> SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> static bool ok_for_max_constant ( HOST_WIDE_INT val ) { if ( rx_max_constant_size == <NUM_LIT> || rx_max_constant_size == <NUM_LIT> )


<s> for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ]


<s> if ( IDVal == <STR_LIT> ) parseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirective<ISA_LIT> ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnwindRaw (


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate (


<s> } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; bool IsPCRel = MCE . earlyResolveAddresses ( ) ? true : false ; if ( ( ! Is64BitMode || DispForReloc || BaseReg != <NUM_LIT> ) && IndexReg . getReg ( ) == <NUM_LIT> && ( ( BaseReg == <NUM_LIT> && MCE . earlyResolveAddresses ( ) ) || BaseReg == <STR_LIT> || ( BaseReg != <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: ESP ) ) ) { if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; } else { unsigned BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; } else if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , IsPCRel ) ; } } } else { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } else if ( isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp8 = true ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg ==


<s> SDValue Extend = InsertVectorElt . getOperand ( <NUM_LIT> ) ; unsigned ExtendOpcode = Extend . getOpcode ( ) ; bool IsSExt = ExtendOpcode == <STR_LIT> || ExtendOpcode == <STR_LIT> || ExtendOpcode == <STR_LIT> ; if ( ! IsSExt && ExtendOpcode != <STR_LIT> && ExtendOpcode != <STR_LIT> && ExtendOpcode != <STR_LIT> ) return SDValue ( ) ; EVT TargetType = VectorShuffle . getValueType ( ) ; EVT PreExtendType = calculatePreExtendType ( Extend , DAG ) ; if ( ( TargetType != <STR_LIT> && TargetType != <STR_LIT> && TargetType != <STR_LIT> ) || ( PreExtendType == <STR_LIT> ) ) return SDValue ( ) ; EVT PreExtendVT = TargetType . changeVectorElementType ( PreExtendType ) ; if ( PreExtendVT . getVectorElementCount ( ) != TargetType . getVectorElementCount ( ) ) return SDValue ( ) ; if ( TargetType . getScalarSizeInBits ( ) != PreExtendVT . getScalarSizeInBits


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & getInstrInfo ( ) -> getRegisterInfo


<s> return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint )


<s> if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) x = XEXP ( x , <NUM_LIT> ) ; if ( MEM_P ( x )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg = <STR_LIT> ; return MFI . getObjectOffset


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups ,

STI ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ;


<s> BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; RC = updatedRC ( RC ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return


<s> bool has<ISA_LIT> ( ) const { return ! ( STI . getFeatureBits ( )


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; Register VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; Register VR1 = RegInfo . createVirtualRegister ( RC


<s> assert ( StOpc != <NUM_LIT> && <STR_LIT> ) ; if ( StSize >= <NUM_LIT> ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . addReg ( Data ) ) ; } else if ( IsThumb1 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ; MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( AddrIn ) . addImm ( StSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) ) ; } else { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) .


<s> getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { { s32 , s32 } } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s32 } , { s32 , p0 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_GEP , G_INTTOPTR } ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalFor ( { { s32 , p0 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( { G_GLOBAL_VALUE , G_JUMP_TABLE } ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_DYN_STACKALLOC ) . lowerFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_VASTART ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FABS , G_FSQRT } ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalFor ( { { s32 , s32 } , { s32 , s64 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_FCEIL , G_FFLOOR } ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 } , { s64 , s32 } ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_FPTOUI ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . lowerForCartesianProduct ( { s32 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s64 , s32 } , { s32 } ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_UITOFP ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . customForCartesianProduct ( { s64 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SEXT_INREG ) . lower ( ) ; computeTables ( ) ; verify ( * ST . getInstrInfo


<s> unsigned Offset = GetInitialOffset ( Fn ) ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; if ( MBB -> getNumber ( ) > <NUM_LIT> ) { auto & BS = BlockSizes [ MBB -> getNumber ( ) - <NUM_LIT> ] ; BS . first -=


<s> inline vector unsigned int vec_vmuleuh ( vector unsigned short a1


<s> if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return <STR_LIT> ; if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) { if ( TYPE_MODE ( type ) == BFmode ) return <STR_LIT> ; else return <STR_LIT> ; } if ( TYPE_NAME ( type ) != NULL ) { const char * res ; if ( ( res = aarch64_general_mangle_builtin_type ( type ) ) || ( res


<s> if ( CapAlign > <NUM_LIT> && Op . size ( ) >= CapAlign . value ( ) && ! IsNonZeroMemset ) { LLVM_DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << Op . size ( ) << <STR_LIT> << ( Op . isFixedDstAlign ( ) ? Op . getDstAlign ( ) . value ( ) : <NUM_LIT> ) << <STR_LIT> << ( Op . isMemset ( ) ? <NUM_LIT> : Op . getSrcAlign ( ) . value ( ) ) << <STR_LIT> << CapAlign . value ( ) << <STR_LIT> ) ; if ( Op . isAligned ( CapAlign ) ) { return CapType ; } else if ( ! Op .


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( *


<s> return ( __m128i ) __builtin_ia32_pminuw128 ( ( __v8hi )


<s> static DecodeStatus DecodeRestrictedUPredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( ( Val & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return MCDisassembler ::


<s> std :: vector < llvm :: Value * > AsmArgs ; llvm :: FunctionType * AsmFTy = llvm :: FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes ,


<s> SMLoc ExprEnd ; getLexer ( ) . UnLex ( AsmToken ( AsmToken :: LParen , <STR_LIT> ) ) ; if ( getParser ( ) . parseExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( BaseReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( IndexReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregciv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t


<s> if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( create<ISA_LIT>PostRewritePass (


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineSIGN_EXTEND ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineMERGE ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI


<s> const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( Op ) ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! restrict_addressing_modes_for_nacl && Sh ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt


<s> return CreateReg ( Index , RegKind_FCC , RegInfo


<s> LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { return


<s> static bool TryRemove ( MachineInstr * MI , ReachingDefAnalysis & RDA , InstSet & ToRemove , InstSet & Ignore ) { auto WontCorruptITs = [ ] ( InstSet & Killed , ReachingDefAnalysis & RDA ) { SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > BasicBlocks ; for ( auto * Dead : Killed ) BasicBlocks . insert ( Dead -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & IT : * MBB ) { if ( IT . getOpcode ( ) != <STR_LIT> ) continue ; RDA . getReachingLocalUses ( & IT , MCRegister :: from ( <STR_LIT> ) , ITBlocks [ & IT ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > RemoveITs ; for ( auto * Dead : Killed ) { if ( MachineOperand * MO = Dead -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA . getMIOperand ( Dead , * MO ) ; RemoveITs . insert ( IT ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( Dead ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ! ModifiedITs . empty ( ) ) return false ; Killed . insert ( RemoveITs . begin ( ) , RemoveITs . end ( ) ) ; return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; if ( ! RDA . isSafeToRemove ( MI , Uses , Ignore ) ) return false ; if ( WontCorruptITs ( Uses , RDA ) ) { ToRemove . insert ( Uses . begin ( ) , Uses . end ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ; for ( auto * Use : Uses ) dbgs ( ) << <STR_LIT> << * Use ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Killed ; RDA . collectKilledOperands ( MI , Killed ) ; if ( WontCorruptITs ( Killed , RDA ) ) { ToRemove . insert ( Killed . begin ( ) , Killed . end ( ) ) ; LLVM_DEBUG ( for ( auto * Dead : Killed ) dbgs ( ) << <STR_LIT> << * Dead ) ; } return true ; } return false


<s> __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val


<s> int intregs , intoffset ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> )


<s> if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> ,


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) ,


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; if ( ! A -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; return ; } uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; return ; } Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT>


<s> InOp = InOp . getOperand ( <NUM_LIT> ) ; InVT = InOp . getSimpleValueType ( ) ; InNumElts = InVT . getVectorNumElements ( ) ; } } if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> ( InOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < InNumElts ; ++ i ) Ops . push_back ( InOp . getOperand ( i ) ) ; SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , EltVT ) : DAG . getUNDEF ( EltVT ) ; for ( unsigned i = <NUM_LIT> ; i < WidenNumElts - InNumElts ; ++ i ) Ops . push_back ( FillVal ) ; return DAG . getNode ( <STR_LIT> , dl


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList


<s> return __arm_vcmpneq_m_n_f32 ( __a ,


<s> if ( TARGET_ARM_P ( flags ) && write_symbols != NO_DEBUG && ! TARGET_APCS_FRAME && ( TARGET_DEFAULT & MASK_APCS_FRAME ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; if ( TARGET_THUMB_P ( flags ) && TARGET_IWMMXT ) error ( <STR_LIT> ) ; if ( TARGET_HARD_TP && TARGET_THUMB1_P ( flags ) ) error ( <STR_LIT> ) ; if ( TARGET_THUMB_P ( flags ) && TARGET_VXWORKS_RTP && flag_pic ) { error ( <STR_LIT>


<s> void <ISA_LIT>InstrInfo :: movImm16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi6 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo10 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi6 )


<s> return ( __mmask16 ) __builtin_ia32_cmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , arg . type ) ; else if ( res > <NUM_LIT> ) { nregs ++ ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location ,


<s> break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl


<s> OpFlag = <STR_LIT> ; } else if ( Subtarget . isPICStyleStubNoDynamic ( ) ) { OpFlag = <STR_LIT> ; } auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget . is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG

. getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ;


<s> unsigned CorrectPosV2 = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = ( int ) VT . getVectorNumElements ( ) ; i != e ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) { ++ CorrectPosV1 ; ++ CorrectPosV2 ; continue ; } if ( Mask [ i ] == i ) ++ CorrectPosV1 ; else if ( Mask [ i ] == i + <NUM_LIT> ) ++ CorrectPosV2 ; } if ( CorrectPosV1 == <NUM_LIT> || CorrectPosV2


<s> ELF<ISA_LIT>AsmBackend ( const Target & T ,


<s> Target & llvm :: getTheARM64Target ( ) { static Target


<s> if ( ! isMem ( ) || ! Memory . OffsetRegNum || Memory . isNegative

|| Memory . Alignment != <NUM_LIT> || Memory . BaseRegNum == <STR_LIT> ) return false ;


<s> MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer ,


<s> unsigned align = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> << align ) ) ; return


<s> perm1 += <NUM_LIT> ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == <NUM_LIT> ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , <NUM_LIT> ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( <NUM_LIT> , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } return true


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_ZC ; return TargetLowering :: getInlineAsmMemConstraint (


<s> int aarch64_simd_attr_length_move ( rtx_insn * insn ) { machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) && REG_P ( recog_data . operand [ <NUM_LIT> ] ) ) { mode = GET_MODE ( recog_data . operand [ <NUM_LIT> ] ) ; switch ( mode ) { case OImode : return <NUM_LIT> ; case CImode : return <NUM_LIT> ; case XImode : return


<s> Relocator :: DWord thumbBit = ( ( ! pReloc . symInfo ( ) -> isUndef ( ) || pReloc . symInfo ( ) -> isDyn ( ) ) && ( pReloc . symInfo ( ) -> type ( ) ==

ResolveInfo :: Function ) && ( ( pReloc . symValue ( ) & <NUM_LIT> ) != <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign :: ZExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign :: AExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ; case CCValAssign :: Full : return


<s> char __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __iocsrrd_b ( unsigned int _1 ) { return ( unsigned char ) __builtin_loongarch_iocsrrd_b ( ( unsigned


<s> if ( ! MemOp0 -> isSimple ( ) || ! MemOp1 -> isSimple ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( isConsecutiveAccess ( MemOp0 , MemOp1 ,


<s> BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { Register ActualRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ActualRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addReg ( ActualRetAddrReg , RegState :: Kill ) ; } int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ; Register UpdatedStateReg = MRI -> createVirtualRegister (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = encodeNeonVMOVImmediate ( CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( Value )


<s> const AsmToken & Tok = Parser . getTok ( ) ; <STR_LIT> ExtOp = StringSwitch < <STR_LIT> > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ExtOp == <STR_LIT> ) return true ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateExtend ( ExtOp , <NUM_LIT> , S , E , getContext ( ) ) ) ; return false ; } bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ; if ( ! Hash && getLexer ( ) . isNot ( AsmToken :: Integer ) ) { SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateExtend ( ExtOp , <NUM_LIT> , S , E , getContext ( ) ) ) ; return false ; } if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateExtend ( ExtOp , MCE -> getValue ( ) , S , E , getContext (


<s> const <ISA_LIT>Subtarget & Subtarget = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasCmpxchg16b ( ) ) return false ; unsigned CmpXchgNbWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned OpWidth = MemType ->


<s> int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return


<s> gcc_assert ( DECL_P ( * node ) ) ; if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true


<s> rtx code = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; size = nds32_byte_to_size ( byte ) ; switch ( nds32_mem_format ( operands [ <NUM_LIT> ] ) ) { case ADDRESS_REG : operands [ <NUM_LIT> ] = code ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case ADDRESS_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern ,


<s> bool isPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; bool isCodeLarge = ( TM . getCodeModel ( ) == CodeModel :: Large ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { if ( ( isPIC ) && ( isCodeLarge ) ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { const MachineOperand & firstMO = MI -> getOperand ( opNum - <NUM_LIT> ) ; if ( firstMO . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ; } else if ( ( isPIC ) && ( MI -> getOpcode ( ) == <STR_LIT> ) && ( ! MO . isReg ( ) ) &&


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue Neg16 = BuildSplatI ( - <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue RHSSwap = BuildIntrinsicOp ( <STR_LIT> , RHS , Neg16 , DAG , dl ) ; LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; RHSSwap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHSSwap ) ; SDValue LoProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; SDValue HiProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHSSwap , Zero , DAG , dl , <STR_LIT> ) ; HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; return BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , Zero


<s> auto Prepare = [ & ] ( ) { AllocaAddr = CreateAllocaInst ( Builder , Bitcast -> getParent ( ) ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst


<s> if ( <ISA_LIT>ScalarSSEf64 ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> } else if ( MO . isImm ( ) && ! TID . OpInfo [ i ] . isPredicate ( ) ) { if ( MO . getImm ( ) > Limit || ( MO . getImm ( ) & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; } } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = TID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && TID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( TID . getOpcode ( ) == <STR_LIT> || TID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && TID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( Scale > <NUM_LIT> && ! isPred && MO . isImm ( ) ) MIB . addImm ( MO . getImm ( ) / Scale ) ; else { if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } } if ( ! TID . isPredicable ( ) && NewTID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; DOUT << <STR_LIT> << * MI << <STR_LIT> << * MIB ; MBB . erase (


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation :: Type pType ) const { return <NUM_LIT>


<s> Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) ) ) MIB . add ( MO ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( Rt , <NUM_LIT> , <STR_LIT> ) ; Rt =


<s> } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! Register :: isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) && Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement )


<s> static bool isSequentialOrUndefInRange ( ArrayRef < int > Mask , unsigned Pos , unsigned Size , int Low , int Step = <NUM_LIT> ) { for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i , Low += Step ) if ( ! isUndefOrEqual ( Mask [


<s> In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( ExtendInVecOpc , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( ExtendInVecOpc , dl , HalfVT , In ) ; if ( auto * Shuf = dyn_cast < ShuffleVectorSDNode > ( In ) ) if ( hasIdenticalHalvesShuffleMask ( Shuf -> getMask ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpLo ) ; SDValue ZeroVec = DAG . getConstant ( <NUM_LIT> , dl , InVT ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Opc == <STR_LIT> ; SDValue OpHi = getUnpackh ( DAG , dl , InVT ,


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelPLT ( ) const { assert ( m_pRelPLT != NULL && <STR_LIT> ) ; return *


<s> bool <ISA_LIT>TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == <NUM_LIT> ) return false ; if ( Subtarget . hasInt256 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; return true


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> if ( Indices [ i ] != - <NUM_LIT> && Indices [ i ] != Idx ) return SDValue ( ) ; Idx += <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ResTy , Op -> getOperand ( <NUM_LIT>


<s> BasicBlock * Latch = L -> getLoopLatch ( ) ; for ( PHINode & Phi : Latch -> phis ( ) ) { const auto * Ty = Phi . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; const bool IsReduction = RecurrenceDescriptor :: AddReductionVar ( & Phi , RecurrenceDescriptor :: RK_IntegerAdd , L , HasFnNoNaNAttr , RecDesc ) ; if ( ! IsReduction ) continue ; Instruction * Acc = dyn_cast < Instruction > ( Phi . getIncomingValueForBlock ( Latch ) ) ; if ( ! Acc ) continue ; Reductions . push_back ( Reduction ( & Phi , Acc ) ) ; } return ! Reductions . empty ( ) ; } ; ReductionList Reductions ; if ( ! FindReductions ( Reductions )


<s> const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . CreateTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: Create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: CreateSub ( Res , PC ,


<s> return ( __m64 ) __builtin_arm_wunpckilw ( ( __v2si )


<s> for ( auto & MBB : * MF ) { if ( ! PrevCanFallthough ) { Changed = true ; MBB . setAlignment ( Alignment ) ; } PrevCanFallthough = MBB . canFallThrough ( ) ; if ( STI -> hasLOB ( ) ) { for ( const auto & MI : reverse ( MBB . terminators ( ) ) ) { if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getMBB ( ) == MBB . getNextNode ( ) ) continue ; if ( isLoopStart ( MI ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { PrevCanFallthough = true


<s> } if ( VT . isInteger ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) { switch ( ISD ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( ! VT . isFloatingPoint ( ) ) return false ; if ( TLI -> useSoftFloat ( ) ) { switch ( I . getOpcode ( ) ) { default : return true ; case Instruction :: Alloca : case Instruction :: Load : case Instruction :: Store : case Instruction :: Select : case Instruction :: PHI : return false ; } } if ( I . getType ( ) -> isDoubleTy ( ) && ! ST


<s> void <ISA_LIT>InstPrinter :: printTraceSyncBOption ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( MO . isImm ( ) ) { O << <STR_LIT> ; O . write_hex ( MO . getImm ( ) ) ; } else { O << * MO . getExpr


<s> Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr


<s> static int getIDWithAttrMask ( uint16_t * instructionID , struct InternalInstruction * insn , uint16_t attrMask ) { bool hasModRMExtension ; InstructionContext instructionClass = contextForAttrs ( attrMask ) ; hasModRMExtension = modRMRequired ( insn -> opcodeType , instructionClass , insn -> opcode ) ; if ( hasModRMExtension ) { if ( readModRM ( insn ) ) return - <NUM_LIT> ; * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , insn -> modRM ) ; } else { * instructionID = decode ( insn -> opcodeType ,

instructionClass , insn -> opcode , <NUM_LIT> ) ;


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = <STR_LIT> ; break ; case 'c' : if ( ! TARGET_AVX ) str = <STR_LIT> ; break ; case 'd' : if ( ! TARGET_AVX2 ) str = <STR_LIT> ; break ; case 'e' : if ( ! TARGET_AVX512F ) str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , <NUM_LIT> ) ; gcc_assert ( ok ) ; pop_cfun (


<s> if ( ResVT . getScalarSizeInBits ( ) == <NUM_LIT> ) { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; } unsigned ConvOpcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( ConvOpcode , dl , ResVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; unsigned ByteSize = Op1VT . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Val , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( ByteSize , dl , false ) , DAG . getValueType ( Op1VT ) } ; Val = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , cast < StoreSDNode > ( N ) -> getMemoryVT ( ) , cast < StoreSDNode > ( N )


<s> return ( __m64 ) __builtin_arm_wsadb ( ( __v8qi ) __A , (


<s> tree function_resolver :: report_no_such_form ( type_suffix_index type ) { error_at ( location , <STR_LIT> , fndecl , get_vector_type ( type ) ) ; return error_mark_node


<s> static bool mmix_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { RTX_CODE code = GET_CODE ( x ) ; if ( code == CONST_INT || code == CONST_DOUBLE ) return <NUM_LIT> ; return CONSTANT_ADDRESS_P ( x


<s> int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs


<s> second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , <NUM_LIT> ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && reg_referenced_p ( XEXP ( cond , <NUM_LIT> ) , PATTERN ( second ) ) && ! reg_referenced_p (

XEXP ( cond , <NUM_LIT> ) , PATTERN ( second ) ) ) {


<s> MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI ,


<s> void <ISA_LIT>BranchRelaxation :: computeBlockSize ( const MachineBasicBlock & MBB ) { unsigned Size = <NUM_LIT> ; for ( const MachineInstr & MI : MBB ) Size += TII ->


<s> static void getLabelAccessInfo ( bool IsPIC , const <ISA_LIT>Subtarget & Subtarget , unsigned & HiOpFlags , unsigned & LoOpFlags , const GlobalValue * GV = nullptr ) { HiOpFlags = <STR_LIT> ; LoOpFlags =


<s> else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalFunctionSymbol ( Name ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back (


<s> return i ; } if ( ( val & <NUM_LIT> ) == <NUM_LIT> || ( val & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; i = <NUM_LIT> ; while ( ( ( val <<= <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) ++ i ; return i


<s> static bool aarch64_vfp_is_call_candidate ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , int * nregs ) { CUMULATIVE_ARGS * pcum = get_cumulative_args


<s> SmallString < <NUM_LIT> > Key ; Key . reserve ( <ISA_LIT> . size ( ) + FS . size ( ) ) ; Key += <ISA_LIT> ; Key += FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , <ISA_LIT> , FS


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) ) ; SDValue Offset = DAG . getNode ( <STR_LIT>


<s> return ( int64x2_t ) __builtin_aarch64_sqshl_nv2di ( __a ,


<s> const TargetRegisterClass * RC2 = FP64 ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . storeRegToStack ( MBB , I , HiReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI , <NUM_LIT> ) ; return true ; } return false


<s> switch ( get_attr_type ( insn ) ) { case TYPE_SDIV : case TYPE_UDIV : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx

+ <NUM_LIT> ) , MachineMemOperand :: MOLoad , Size , Align ) ) ;


<s> return <ISA_LIT>ATTInstPrinter :: getRegisterName


<s> return Create ( VK_<ISA_LIT>_HI , Expr , isDarwin


<s> static rtx gen_frame_store ( rtx reg , rtx frame_reg , int offset ) { return gen_frame_set ( reg , frame_reg , offset


<s> bool <ISA_LIT>InstrInfo :: isAsCheapAsAMove ( const


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) )


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { for ( MCRegAliasIterator AI ( Reg , Subtarget -> getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return false


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return new ELF<ISA_LIT>AsmBackend ( T , TT . getOS (


<s> if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex


<s> static __inline void __cpuidex ( int __cpuid_info [ <NUM_LIT> ] , int __leaf ,


<s> static const <ISA_LIT>MCExpr * CreateHa ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_HA , Expr , Ctx


<s> static DecodeStatus DecodeMveVCTP ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


gen_flush ( SImode , validize_mem ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) ) ) ) ;


<s> int <ISA_LIT>FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return <NUM_LIT> ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset = PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else return <NUM_LIT> ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( <NUM_LIT>


<s> SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; assert ( Src . getValueType ( ) . isFloatingPoint ( ) ) ; if ( Src . getValueType ( ) == <STR_LIT> ) { if ( IsStrict ) { Src = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Chain , Src } , Flags ) ; Chain = Src . getValue ( <NUM_LIT> ) ; } else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; } SDValue Conv ; unsigned Opc = <STR_LIT> ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( MRI && FrameReg != <STR_LIT> ) { SpillReg ( Out , <STR_LIT> ) ; if ( FrameReg == <STR_LIT> ) { Out . EmitCFIAdjustCfaOffset ( <NUM_LIT> ) ; Out . EmitCFIRelOffset ( MRI -> getDwarfRegNum ( <STR_LIT> , true ) , <NUM_LIT> ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( FrameReg ) ) ; Out . EmitCFIRememberState ( ) ; Out . EmitCFIDefCfaRegister ( MRI -> getDwarfRegNum ( <STR_LIT> , true ) ) ; } EmitAdjustRSP ( Ctx , Out , - <NUM_LIT> ) ; SpillReg ( Out , RegCtx .


<s> if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; EmitNops ( * OutStreamer , Num , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; return ; } auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; OutStreamer -> emitBytes (


<s> unsigned get<ISA_LIT>RegNum ( const MCOperand & MO ) const { return Ctx . getRegisterInfo ( ) -> getEncodingValue (


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetDsp


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) .


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDNode * Pair = DAG . getMachineNode ( <STR_LIT> , DL ,


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock :: iterator MBBI = ( * BIL . back ( ) ) ; NewSuccessor = ( MBBI != MBB -> getLastNonDebugInstr ( ) || ! MBB -> canFallThrough ( ) ) ? MF -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; ++ It ; if ( ! NewSuccessor ) { for ( auto & Succ : MBB -> successors ( ) ) { if ( MBB -> isLayoutSuccessor ( Succ ) ) { Successor = Succ ; break ; } } } else Successor = NewSuccessor ; if ( IsFalseBlockRequired ) { FalseBlock = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , FalseBlock ) ; } if ( IsTrueBlockRequired ) { TrueBlock = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBlock ) ; } if (


<s> return false ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : if ( ! STI . isTargetWindows ( ) ) return false ; MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : Register StatReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( RBI . getSizeInBits ( StatReg , MRI , TRI ) == <NUM_LIT> && <STR_LIT> ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RBI . getSizeInBits ( SrcReg , MRI , TRI ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Register PtrReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( PtrReg ) . isPointer ( ) && <STR_LIT> ) ; if ( ! I . hasOneMemOperand ( ) ) return false ; const MachineMemOperand * MemOp = * I . memoperands_begin ( ) ; unsigned NumBytesToStore = MemOp -> getSize ( ) ; unsigned Opc = getStlxrOpcode


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : case CCValAssign :: ZExt : Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; break ; case CCValAssign :: AExtUpper : assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; break ; } if ( RegsUsed . count ( VA . getLocReg ( ) ) ) { SDValue & Bits = std :: find_if ( RetVals . begin ( ) , RetVals . end ( ) , [ = ] ( const std :: pair < unsigned , SDValue > & Elt ) { return Elt . first == VA . getLocReg ( ) ; } ) -> second ; Bits = DAG . getNode ( <STR_LIT> , DL , Bits . getValueType ( ) , Bits , Arg ) ; } else { RetVals . emplace_back ( VA . getLocReg ( ) , Arg ) ; RegsUsed . insert ( VA . getLocReg ( ) ) ; } } SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( auto & RetVal : RetVals ) { Chain = DAG . getCopyToReg ( Chain , DL , RetVal . first , RetVal . second , Flag ) ; Flag = Chain . getValue (


<s> void addAdrpLabelOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) addExpr ( Inst , getImm ( ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc Loc ( N ) ; const uint16_t * OurOpcodes ; switch ( VT . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT DataTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , NumVecs * <NUM_LIT> ) ; EVT ResultTys [ ] = { DataTy , <STR_LIT> } ; auto Data = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , Loc , DataTy ) , <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; for ( unsigned Stage = <NUM_LIT> ; Stage < NumVecs ; ++ Stage ) { SDValue Ops [ ] = { Data , N -> getOperand ( <NUM_LIT> ) , Chain } ; auto LoadInst = CurDAG -> getMachineNode ( OurOpcodes [ Stage ] , Loc , ResultTys , Ops ) ; Data = SDValue ( LoadInst , <NUM_LIT> ) ; Chain = SDValue ( LoadInst , <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < NumVecs ; i ++ ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , Loc , VT , Data ) ) ; ReplaceUses ( SDValue ( N ,


<s> tree cst = TREE_VALUE ( args ) ; if ( TREE_CODE ( cst ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) != <NUM_LIT> && strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) != <NUM_LIT> && strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) != <NUM_LIT> &&

strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) != <NUM_LIT> ) {


<s>
if
(
GET_CODE
(
body
)
==
ASM_INPUT
)
templ
=
XSTR
(
body
,
<NUM_LIT>
)
;
else
if
(
asm_noperands
(
body
)
>=
<NUM_LIT>
)
templ
=
decode_asm_operands
(
body
,
,
,
,
,
)
;
else
return
<NUM_LIT>
;
do
{
int
ppi_adjust
=
<NUM_LIT>
;
do
c
=
*
templ
++
;
while
(
c
==
' '
||
c
==
'\t'
)
;
if
(
(
c
==
'p'
||
c
==
'P'
)
&&
strncasecmp
(
<STR_LIT>
,
templ
,
<NUM_LIT>
)
)
ppi_adjust
=
<NUM_LIT>
;
else
if
(
(
c
==
'r'
||
c
==
'R'
)
&&
!
strncasecmp
(
<STR_LIT>
,
templ
,
<NUM_LIT>
)
)
ppi_adjust
=
<NUM_LIT>
;
while
(
c
&&
c
!=
'\n'
&&
!
IS_ASM_LOGICAL_LINE_SEPARATOR
(
c
,
templ
)
)
{
if
(
c
==
':'
&&
maybe_label
)
{
ppi_adjust
=
<NUM_LIT>
;
break
;
}
else
if
(
c
==
'\''
||
c
==
'"'
)
maybe_label
=
false
;
c
=
*
templ
++
;
}
sum
+=


<s> return ! STI . getFeatureBits ( ) [ <STR_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumByteElts ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , LUTVec ) ; SDValue M0F = DAG . getConstant ( <NUM_LIT> , DL , ByteVecVT ) ; SDValue FourV = DAG . getConstant ( <NUM_LIT> , DL , ByteVecVT ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ; SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , M0F ) ; SDValue HighPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , HighNibbles ) ; SDValue LowPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , LowNibbles ) ; SDValue PopCnt = DAG . getNode ( <STR_LIT> , DL

, ByteVecVT , HighPopCnt , LowPopCnt ) ;


<s> int OptimizeLEAPass :: calcInstrDist ( const MachineInstr & First , const MachineInstr & Last ) { const MachineBasicBlock * MBB = First . getParent


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res


<s> if ( ! Subtarget -> hasAVX ( ) ) return std :: make_pair ( <NUM_LIT> , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasSSE2 ( ) ) return std :: make_pair ( <NUM_LIT> , false ) ; } bool hasUnsigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; bool hasSigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; } } else if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasUnsigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = hasSigned ? <STR_LIT> : <NUM_LIT> ; break ; case <STR_LIT>


<s> __builtin_ia32_pmovusdw128mem_mask ( ( __v8hi * ) __P ,


<s> bool is64Bit ( ) const { return getSTI ( ) . getTargetTriple ( ) . getArch ( ) ==


<s> assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ; bool isAdd = Imm >= <NUM_LIT> ; if ( Imm == INT32_MIN ) Imm = <NUM_LIT> ; Imm = ( ( Imm < <NUM_LIT> ? - Imm : Imm ) / <NUM_LIT> ) | ( int ) isAdd << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm )


<s> return ( float32x4_t ) __builtin_neon_vabdfv4sf (


<s> MachineMemOperand * BaseMemOperand = MF . getMachineMemOperand ( DstPtrInfo , MachineMemOperand :: MOStore , ObjSize , Align ( <NUM_LIT> ) ) ; bool UseSetTagRangeLoop = kSetTagLoopThreshold >= <NUM_LIT> && ( int ) ObjSize >= kSetTagLoopThreshold ; if ( ! UseSetTagRangeLoop ) return EmitUnrolledSetTag ( DAG , dl , Chain , Addr , ObjSize , BaseMemOperand , ZeroData ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Opcode ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Addr ) -> getIndex ( ) ; Addr = DAG . getTargetFrameIndex ( FI , <STR_LIT> ) ; Opcode = ZeroData ? <STR_LIT> : <STR_LIT> ; } else { Opcode = ZeroData ?


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Shifter ) ; Op -> Shift . ShiftTy = ShTy ; Op -> StartLoc = S ; Op -> EndLoc =


<s> InFlag = SDValue ( ) ; StoreTailCallArgumentsToStackSlot ( DAG , Chain , TailCallArguments , MemOpChains2 , dl ) ; if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains2 [ <NUM_LIT> ] , MemOpChains2 . size ( ) ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) ,


<s> SDValue OtherVal = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( - <NUM_LIT> , OtherVal . getValueType ( ) ) , NewCmp ) ; return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( <NUM_LIT> , OtherVal .


<s> EVT LdVT = LoadNode -> getMemoryVT ( ) ; if ( LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> ) return false ; SDValue Undef = StoreNode -> getOffset ( ) ; if ( Undef -> getOpcode ( ) != <STR_LIT> ) return false ; if ( StoredVal . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! StoredVal . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! LoadNode -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( StoredVal -> getOperand ( <NUM_LIT> ) . getNode ( ) != LoadNode ) return false ; if ( StoreNode -> isNonTemporal ( ) ) return false ; SDValue Address = StoreNode ->


<s> unsigned T9Reg = <STR_LIT> ; RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; } else Ops . push_back ( Callee ) ; if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = <STR_LIT> ; EVT Ty = <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass


<s> static unsigned getRn ( InsnType insn ) { return getBits ( insn , <NUM_LIT> ,


<s> assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; EVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize /


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI . eraseFromParent (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImmTLS ( const MCExpr * Imm , const MCExpr * Sym , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindImmTLS , StartLoc , EndLoc ) ; Op -> ImmTLS .


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ; if ( BCSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BCSrc ) ; } if ( SDValue V = combineVectorSignBitsTruncation ( N , DL , DAG


<s> int nelems = GET_MODE_NUNITS ( mode ) ; lane = ( nelems - <NUM_LIT>


<s> const MCInstrDesc * Desc = & II -> get ( Opcode ) ; MI . setDesc ( * Desc ) ; return Desc


<s> ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand (


<s> return getSTI ( ) . getFeatureBits (


<s> if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig . getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . add ( Orig . getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; }


<s> } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { --


<s> if ( ! IsVerboseAsm ) return ; T . toVector ( CommentToEmit ) ; if ( EOL ) CommentToEmit . push_back


<s> else emit_insn ( gen_avx2_gtv4di3 ( tmp0 , tmp1 , input ) ) ; } else { tmp0 = expand_simple_binop ( mode , LSHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; tmp0 = expand_simple_unop ( mode , NEG , tmp0 , NULL , false ) ; } tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , <NUM_LIT> , OPTAB_DIRECT ) ; break ; case E_V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - <NUM_LIT>


<s> if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , call ,


<s> SDLoc dl ( N ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI .

DAG . getNode ( <STR_LIT> , dl , VT , X ) ;


<s> if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; if ( MF -> protectArgs ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { ++ Idx ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT>


<s> SDLoc dl ( V ) ; while ( NumElems > <NUM_LIT> ) { if ( EltNo < NumElems / <NUM_LIT> ) { V = getUnpackl ( DAG , dl , VT , V , V ) ; } else { V = getUnpackh ( DAG , dl , VT , V , V ) ; EltNo -= NumElems / <NUM_LIT> ; } NumElems >>= <NUM_LIT> ; } return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> | Flags ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> | <STR_LIT> | Flags ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , Ty , Hi


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI ,


<s> return ( __m128d ) __builtin_ia32_cvtusi2sd64 ( ( __v2df )


<s> assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back (


<s> long long d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> (


<s> MachineInstr & BLR = * MBBI ; assert ( isBLR ( BLR ) ) ; unsigned BLOpcode ; Register Reg ; bool RegIsKilled ; switch ( BLR . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : BLOpcode = <STR_LIT> ; Reg = BLR . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) ; RegIsKilled = BLR . getOperand ( <NUM_LIT> ) . isKill ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = BLR . getDebugLoc ( ) ; MachineFunction & MF = * MBBI -> getMF ( ) ; MCContext & Context = MBB . getParent ( ) -> getContext ( ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ Reg ] ( auto T ) { return T . Reg == Reg ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( ThunkIt -> Name ) ; MachineInstr * BL = BuildMI ( MBB , MBBI , DL , TII -> get ( BLOpcode ) ) . addSym ( Sym ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != -


<s> if ( m -> fs . fp_valid ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( m -> fs . drap_valid ) { base_reg = crtl -> drap_reg ; base_offset = <NUM_LIT> - cfa_offset ; } else if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( m -> fs


<s> return Create ( VK_<ISA_LIT>_HA16 , Expr , Ctx


<s> auto RequiredType = X -> getType ( ) ; auto * PN = dyn_cast < PHINode > ( X -> getArgOperand ( <NUM_LIT> ) ) ; assert ( PN && <STR_LIT> ) ; if ( ! PN -> hasOneUse ( ) ) return false ; for ( Value * IncValPhi : PN -> incoming_values ( ) ) { auto * Reinterpret = isReinterpretToSVBool ( IncValPhi ) ; if ( ! Reinterpret || RequiredType != Reinterpret -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) return false ; } LLVMContext & Ctx = PN -> getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( PN ) ; PHINode * NPN = Builder . CreatePHI ( RequiredType , PN -> getNumIncomingValues ( ) ) ; Worklist . push_back ( PN ) ; for ( unsigned I = <NUM_LIT> ; I < PN -> getNumIncomingValues ( ) ; I ++ ) { auto * Reinterpret = cast < Instruction > ( PN -> getIncomingValue ( I ) ) ; NPN -> addIncoming ( Reinterpret -> getOperand ( <NUM_LIT> ) , PN -> getIncomingBlock ( I ) ) ; Worklist . push_back ( Reinterpret ) ; } X -> replaceAllUsesWith ( NPN ) ; X -> eraseFromParent ( ) ; for ( auto & I : Worklist ) if ( I -> use_empty ( ) ) I -> eraseFromParent ( ) ; return true


<s> if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) ,


<s> int regs_to_push ; cfun -> machine -> uses_anonymous_args = <NUM_LIT> ; local_cum = * pcum ; csky_function_arg_advance ( local_cum_v , arg ) ; regs_to_push = CSKY_NPARM_REGS - local_cum . reg ; if ( regs_to_push ) * pretend_size = regs_to_push *


<s> SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset = <NUM_LIT> ; } } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false


<s> } ( ) ; static const auto EqZeroOptions = [ this ] ( ) { TTI :: MemCmpExpansionOptions Options ; if ( ST -> hasAVX2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> is64Bit ( ) ) { Options . LoadSizes . push_back (


<s> unsigned Bytes = Arg . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand


<s> MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( Is64Bit ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( InProlog ) { for ( ++ ExpansionMBBI ; ExpansionMBBI != MBBI ; ++ ExpansionMBBI ) ExpansionMBBI -> setFlag ( MachineInstr :: FrameSetup ) ; } return


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> bool isLegalMaskedStore ( Type * DataType ) { return ST -> hasSVE


<s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG .


<s> const GlobalValue * GV = cast < GlobalValue > ( M -> getNamedValue ( ThunkIt -> Name ) ) ; MachineInstr * BL = isThumb ? BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( IndirectCall . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( IndirectCall . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addGlobalAddress ( GV ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( GV ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> RemoveOperand ( FirstOpIdxToRemove ) ; BL -> RemoveOperand ( SecondOpIdxToRemove ) ; BL -> copyImplicitOps ( MF , IndirectCall ) ; MF . moveCallSiteInfo ( & IndirectCall , BL ) ; BL -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true , RegIsKilled ) ) ; MBB . erase ( MBBI ) ; return MBB


<s> bool <STR_LIT> ( SDValue Elt ) { return ( ( isa < ConstantSDNode > ( Elt ) && cast < ConstantSDNode > ( Elt ) -> isNullValue ( ) ) || ( isa < ConstantFPSDNode > ( Elt ) &&

cast < ConstantFPSDNode > ( Elt ) -> getValueAPF ( ) . isPosZero ( ) ) ) ;


<s> return ( __m256i ) __builtin_ia32_cvtps2udq256_mask ( ( __v8sf ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8


<s> __builtin_ia32_pmovsqd128mem_mask ( ( unsigned long long * ) __P , ( __v2di )


<s> if ( VT . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG .


<s> for ( const char * Name = V -> getNameStart ( ) , * E = Name + V -> getNameLen ( ) ; Name != E ; ++ Name ) if ( isprint ( * Name )


<s> std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false