<s> int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding )


<s> ConstantPools -> emitForCurrentSection ( Streamer


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> case SUBREG : fprintf ( stream , <STR_LIT> , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , <NUM_LIT> ) ; rtx index = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , <STR_LIT> , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; if ( base_num == <NUM_LIT> && index_num != <NUM_LIT> ) std :: swap ( base_num , index_num ) ; fprintf ( stream , <STR_LIT> , reg_names [ index_num ] , reg_names [ base_num ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case


<s> else { rtx got , tga , tmp1 , tmp2 ; if ( rs6000_pcrel_p ( ) ) got = const0_rtx ; else if ( TARGET_64BIT ) got = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else { if ( flag_pic == <NUM_LIT> ) got = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; else { rtx gsym = rs6000_got_sym ( ) ; got = gen_reg_rtx ( Pmode ) ; if ( flag_pic == <NUM_LIT> ) rs6000_emit_move ( got , gsym , Pmode ) ; else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr , got ) , UNSPEC_TLSGD ) ; tga = rs6000_tls_get_addr ( ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; global_tlsarg = arg ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , argreg , Pmode ) ; global_tlsarg = NULL_RTX ; rtvec vec = gen_rtvec ( <NUM_LIT> , copy_rtx ( arg ) ) ; rtx uns = gen_rtx_UNSPEC ( Pmode , vec , UNSPEC_TLS_GET_ADDR ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , uns ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , got ) , UNSPEC_TLSLD ) ; tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg )


<s> static void mips_code_end ( void ) { mips_finish_stub ( &


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext &


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: JITDefault ) RM = Reloc :: Static ; else if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> return ( reload_completed && xstormy16_compute_stack_layout (


<s> MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Shifters ( NumElts , DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ) ; SDValue Shifter = DAG . getNode ( <STR_LIT> , DL ,


<s> Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first


<s> return CC == CallingConv :: WebKit_JS ?


<s> for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; if ( FFI -> getMaxAlignment ( ) == MaxAlign ) return false ; FFI -> setMaxAlignment ( MaxAlign ) ; return true


<s> return ( ET == <STR_LIT> || ET == <STR_LIT> ) && ( getShiftExtendAmount ( ) == Log2_32 (

Width / <NUM_LIT> ) || getShiftExtendAmount ( ) == <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( - ( uint32_t ) CE -> getValue


<s> return ( vector unsigned int ) __builtin_altivec_vaddcuw ( ( vector signed int ) a1 ,


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum )


<s> dbgs ( ) << <STR_LIT> << this << '\n' ; dbgs ( ) << <STR_LIT> ; if ( Base_Reg . getNode ( ) ) Base_Reg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Base_FrameIndex << '\n' << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump


<s> Value * <ISA_LIT>IREmitter :: visitVMULLs ( const SDNode *


<s> ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createMacroFusionDAGMutation ( DAG -> TII )


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( Mnemonic . startswith (


<s> ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , ops ) ; return <STR_LIT>


<s> void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP ) ; \ in_section


<s> return new <ISA_LIT>MCCodeEmitter ( InstrInfo ,


<s> while ( MBBI != MBBE ) { -- MBBI ; MachineInstr * MI = MBBI ; if ( resultTests ( MI , SrcReg , SrcSubReg ) ) { if ( ! CCRefs . Use && ! SrcRefs && convertToBRCT ( MI , Compare , CCUsers ) ) { BranchOnCounts += <NUM_LIT> ; return true ; } if ( ( ! CCRefs && convertToLoadAndTest ( MI ) ) || ( ! CCRefs . Def && adjustCCMasksForInstr ( MI , Compare , CCUsers ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) return false ; CCRefs |= getRegReferences ( MI ,


<s> return ( float32x2_t ) __builtin_neon_vset_lanev2sf ( ( __builtin_neon_sf ) __a ,


<s> void printlea32mem ( const MachineInstr * MI ,


<s> static bool ix86_function_naked ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn ) ) ) return true ; return


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , PtrOff ) ; } if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , dl , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; assert ( G && <STR_LIT> ) ; std :: vector < SDValue > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) { Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } const uint32_t * Mask ; assert ( Mask && <STR_LIT> ) ; if ( InFlag . getNode ( )


<s> return false ; } auto * One = SE -> getOne ( TripCount -> getType ( ) ) ; auto * ElementCount = SE -> getAddExpr ( BTC , One ) ; auto * ECPlusVWMinus1 = SE -> getAddExpr ( ElementCount , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ) ; ConstantRange RangeCeil = SE -> getSignedRange ( Ceil ) ; ConstantRange RangeTC = SE -> getSignedRange ( TC ) ; if ( ! RangeTC . isSingleElement ( ) ) { auto ZeroRange = ConstantRange ( APInt ( TripCount -> getType ( ) -> getScalarSizeInBits ( ) , <NUM_LIT> ) ) ; RangeTC = RangeTC . unionWith ( ZeroRange ) ; } if ( ! RangeTC . contains ( RangeCeil ) && ! ForceTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * IV = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * IVExpr = SE -> getSCEV ( IV ) ; auto * AddExpr = dyn_cast < SCEVAddRecExpr > ( IVExpr ) ; if ( ! AddExpr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; IVExpr -> dump ( ) ) ; return false


<s> return ( TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst )


<s> this -> m_insn_fma_head_map = new hash_map < rtx_insn * , fma_node * > ; this -> m_fma_forests . clear ( ) ; this -> m_next_forest_id


<s> static bool IsInSmallSection ( uint64_t Size ) { return Size > <NUM_LIT> && Size


<s> SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Chain , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT>


<s> bool Valid ; uint32_t Bits = <STR_LIT> ( ) . fromString ( getSysReg (


<s> case V8QImode : gen = gen_aarch64_dup_lanev8qi ; break ; case V8HImode : gen = gen_aarch64_dup_lanev8hi ; break ; case V4HImode : gen = gen_aarch64_dup_lanev4hi ; break ; case V4SImode : gen = gen_aarch64_dup_lanev4si ; break ; case V2SImode : gen = gen_aarch64_dup_lanev2si ; break ; case V2DImode : gen = gen_aarch64_dup_lanev2di ; break ; case V4SFmode : gen = gen_aarch64_dup_lanev4sf ; break ; case V2SFmode : gen = gen_aarch64_dup_lanev2sf ; break ; case V2DFmode : gen = gen_aarch64_dup_lanev2df ; break ; default : return false ; } emit_insn ( gen ( out , in0 , lane ) ) ; return true


<s> if ( Subtarget . isDarwinABI ( ) ) return nullptr ; if ( ! TM . is<ISA_LIT>64 ( ) ) return nullptr ; if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) . test ( <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList : CSR_SVR464_Altivec_ViaCopy_SaveList ; else return SaveR2 ? CSR_SVR464_R2_ViaCopy_SaveList


<s> MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) ->


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue


<s> if ( auto * BitCast = dyn_cast < BitCastInst > ( Ptr ) ) { auto * BCTy = cast < VectorType > ( BitCast -> getType ( ) ) ; auto * BCSrcTy = cast < VectorType > ( BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( BCTy -> getNumElements ( ) == BCSrcTy -> getNumElements ( ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> void <ISA_LIT>TargetStreamer :: emitRI ( unsigned Opcode , unsigned Reg0 , int32_t Imm , SMLoc IDLoc , const MCSubtargetInfo


<s> Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg


<s> if ( <STR_LIT> ( Cond . getNode ( ) ) && <STR_LIT> ( LHS . getNode ( ) ) && <STR_LIT> ( RHS . getNode ( ) ) ) return SDValue ( ) ; if ( SDValue BlendOp = lowerVSELECTtoVectorShuffle ( Op , Subtarget , DAG ) ) return BlendOp ; MVT CondVT = Cond . getSimpleValueType ( ) ; unsigned CondEltSize = Cond . getScalarValueSizeInBits ( ) ; if ( CondEltSize == <NUM_LIT> ) return Op ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue Mask = DAG . getSetCC ( dl , MaskVT , Cond , getZeroVector ( CondVT , Subtarget , DAG , dl ) , <STR_LIT> ) ; return DAG . getSelect ( dl , VT , Mask , LHS , RHS ) ; } if ( CondEltSize != EltSize ) { if ( CondEltSize != DAG . ComputeNumSignBits ( Cond ) ) return SDValue ( ) ; MVT NewCondSVT = <STR_LIT> ( EltSize ) ; MVT NewCondVT = <STR_LIT> ( NewCondSVT , NumElts ) ; Cond = DAG . getSExtOrTrunc ( Cond , dl , NewCondVT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cond , LHS , RHS ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : { MVT CastVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Cond = DAG . getBitcast ( CastVT , Cond ) ; LHS = DAG . getBitcast ( CastVT ,


<s> return ( int8x8_t ) __builtin_neon_vshl_nv8qi (


<s> else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , <NUM_LIT> , GET_MODE ( variable ) ,


<s> uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ; uint32_t lsb_mask = ( <NUM_LIT> << lsb ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( ~ ( msb_mask ^


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr )


<s> EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) ) return false ; unsigned VTSize = VT . getSimpleVT (


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I8 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I16 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SREM_I32 ; else if ( VT == <STR_LIT> ) LC =


<s> unsigned <ISA_LIT>FastISel :: emitLSL_rr ( MVT RetVT , unsigned Op0Reg , bool Op0IsKill , unsigned Op1Reg , bool Op1IsKill ) { unsigned Opc = <NUM_LIT> ; bool NeedTrunc = false ; uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op1Reg = emitAND_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op1IsKill = true


, ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( ! N . hasOneUse ( ) ) return false ; ConstantSDNode * MulConst = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! MulConst ) return false ; if ( ! MulConst -> hasOneUse ( ) ) return false ; unsigned MulConstVal = MulConst -> getZExtValue ( ) ; if ( MulConstVal == <NUM_LIT> ) return false ; PowerOfTwo = MaxShift ; while ( ( MulConstVal % ( <NUM_LIT> << PowerOfTwo ) ) != <NUM_LIT> ) { -- PowerOfTwo ; if ( PowerOfTwo == <NUM_LIT> ) return false ; } unsigned NewMulConstVal = MulConstVal / ( <NUM_LIT> << PowerOfTwo ) ; NewMulConst = CurDAG -> getConstant ( NewMulConstVal , SDLoc ( N ) , <STR_LIT> ) ; unsigned OldCost = ConstantMaterializationCost ( MulConstVal , Subtarget ) ; unsigned NewCost = ConstantMaterializationCost ( NewMulConstVal , Subtarget ) ; return NewCost


<s> assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; warnIfNoMacro ( IDLoc ) ; unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; bool IsLargeOffset = ! ( isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) && isInt < <NUM_LIT> > ( OffsetValue ) ) ; if ( IsLargeOffset ) { if ( loadImmediate ( OffsetValue , ATReg , SrcReg , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Out , STI ) ) return true ; } int64_t FirstOffset = IsLargeOffset ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; int64_t SecondOffset = IsLargeOffset ? <NUM_LIT> : OffsetValue ; if ( isLittle ( ) ) std :: swap ( FirstOffset , SecondOffset ) ; if ( IsLargeOffset ) { TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , FirstOffset , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , SecondOffset , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI


<s> return ! call_used_regs [ r ] && df_regs_ever_live_p ( r


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = <NUM_LIT> ; if ( is64BitVector ) { Opc = DOpcodes [ OpcodeIndex ] ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( N -> getOperand ( Vec + <NUM_LIT> ) ) ; } else { if ( Lane < NumElts ) { Opc = QOpcodes0 [ OpcodeIndex ] ; } else { Lane -= NumElts ; Opc = QOpcodes1 [ OpcodeIndex ] ; } for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( CurDAG -> getTargetExtractSubreg ( SubregIdx , dl , RegVT , N -> getOperand ( Vec + <NUM_LIT> ) ) ) ; } Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; if ( ! IsLoad ) return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( )


<s> default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : case


<s> CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; } CmpInst :: Predicate Predicate = CI -> getPredicate ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( Predicate ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> ) return false ; unsigned Arg2 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg2 == <NUM_LIT> ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( Arg1 ) . addReg ( Arg2 ) ) ; if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return


<s> MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( <STR_LIT> ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register BaseReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; unsigned Shifter = <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; return


<s> return ( int ) __builtin_ia32_vcvttsd2si32 ( ( __v2df ) __A ,


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf64 ) return false ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> )


<s> inline SDValue getI8Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm ,


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) || ( TARGET_HAVE_MVE && ( VALID_MVE_MODE ( mode1 ) || VALID_MVE_STRUCT_MODE ( mode1 ) ) && ( VALID_MVE_MODE ( mode2 ) || VALID_MVE_STRUCT_MODE ( mode2 ) ) ) ) return true ; return false


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI


<s> unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Dst , Src ) ) return expandCopyACC ( MBB , I , Dst , Src , <NUM_LIT> ) ; if ( <STR_LIT> . contains ( Dst , Src ) ) return expandCopyACC ( MBB , I , Dst , Src , <NUM_LIT> ) ; return false


<s> } else return true ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == <NUM_LIT> || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == <NUM_LIT> || ( ( ( to ) == IFmode ) + ( ( from ) == IFmode ) ) == <NUM_LIT> || ( ( ( to ) == KFmode ) + ( ( from ) == KFmode ) ) == <NUM_LIT> || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == <NUM_LIT> || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == <NUM_LIT> || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == <NUM_LIT> ) ) return false ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + <NUM_LIT> ) / <NUM_LIT> ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == <NUM_LIT> ||


<s> OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE (


<s> if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerSTORE ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> ,


<s> MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) ; } if ( setLR ) MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegState :: Implicit ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegState :: ImplicitDefine ) ; return true ; } return


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned i ; for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; if ( DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { ShiftAmt += i ; if ( ! isUnary ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt - i ) ) return - <NUM_LIT> ; } else { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt - i ) & <NUM_LIT> ) ) return - <NUM_LIT> ; } } else { ShiftAmt -= i ; if ( ! isUnary ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt

( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> static bool is_prefetch ( rtx_insn * insn ) { return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn )


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; if ( DstSize != <NUM_LIT> && DstSize != <NUM_LIT>


<s> if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue


<s> return create<ISA_LIT>MachObjectWriter ( OS , true , MachO


<s> return ST -> hasMacroFusion ( ) || ST -> hasBranchFusion


<s> strncpy ( string , input_string , string_length ) ; string [ string_length - <NUM_LIT> ] = '\0' ; char * ntoken = string ; while ( ( ntoken = strchr ( string , separator ) ) ) { size_t token_length = ntoken - string ; * ntoken = '\0' ; aarch64_parse_one_override_token ( string , token_length , tune ) ; string = ++


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry ::


<s> else { error_p = false ; rs6000_isa_flags_explicit |= mask ; if ( ! invert ) { if ( mask == OPTION_MASK_VSX ) { mask |= OPTION_MASK_ALTIVEC ; TARGET_AVOID_XFORM = <NUM_LIT> ; } } if ( rs6000_opt_masks [ i ] . invert ) invert = ! invert ; if ( invert ) rs6000_isa_flags &= ~ mask ; else rs6000_isa_flags |= mask ; } break ; } if ( error_p && ! not_valid_p ) { for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_vars ) ; i ++ ) if ( strcmp ( r , rs6000_opt_vars [ i ] . name ) == <NUM_LIT> ) { size_t j = rs6000_opt_vars [ i ] . global_offset ; * ( ( int * ) ( ( char * ) & global_options + j ) ) = ! invert ; error_p = false ; not_valid_p = false ; break ; } } } if ( error_p ) { const char * eprefix , * esuffix ; ret = false ; if ( attr_p ) { eprefix = <STR_LIT> ; esuffix = <STR_LIT> ; } else { eprefix = <STR_LIT> ; esuffix = <STR_LIT> ; } if ( cpu_opt ) error ( <STR_LIT> , cpu_opt , eprefix , q , esuffix ) ; else if ( not_valid_p ) error ( <STR_LIT> , eprefix , q , esuffix ) ; else error ( <STR_LIT> , eprefix , q , esuffix ) ; } } } else if ( TREE_CODE ( args ) == TREE_LIST ) { do { tree value = TREE_VALUE ( args ) ; if ( value ) { bool ret2 = rs6000_inner_target_options ( value , attr_p ) ; if ( ! ret2 ) ret = false ; } args = TREE_CHAIN ( args ) ; } while ( args != NULL_TREE ) ; } else gcc_unreachable


<s> MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; Push -> cloneMergedMemRefs ( MF , { DefMov , & * Store } ) ; DefMov -> eraseFromParent ( ) ; } else { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addReg ( Reg ) . getInstr ( ) ; Push -> cloneMemRefs ( MF , * Store ) ; } break ; } } if ( ! TFL -> hasFP ( MF ) ) TFL -> BuildCFI ( MBB , std :: next ( Push ) , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , SlotSize ) ) ; MBB . erase ( Store ) ; } if ( Context . SPCopy && MRI -> use_empty ( Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) Context . SPCopy -> eraseFromParent ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setHasPushSequences ( true


<s> return true ; } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { Info =


<s> static tree cache ; if ( cache == NULL_TREE ) cache = build_pointer_type ( build_qualified_type

( void_type_node , TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE ) ) ;


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : return <NUM_LIT>


<s> case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None


<s> result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char )

__A , ( __vector unsigned char ) perm_mask ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel , bool verbose ) { const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isFlavorIntel ( ) ) { return new <ISA_LIT>IntelAsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , OptLevel


<s> case <STR_LIT> : FOp = <STR_LIT> ; MOp = <STR_LIT> ; break ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ValOpIdx = <STR_LIT> ; unsigned VSrc = MI . getOperand ( ValOpIdx ) . getReg ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) ; for ( int i = <NUM_LIT> ; i <


<s> if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx +=


<s> return Opc == <STR_LIT> || isT1i32Load ( Opc ) || isT2i32Load


<s> const EDInstInfo * <ISA_LIT>64Disassembler :: getEDInfo


<s> assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addReg ( LoReg ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addReg


<s> return ( uint8x16_t ) __builtin_mve_vcaddq_rot90v16qi ( ( int8x16_t


<s> else { MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , CSI [ CSIIndex ] . getFrameIdx ( ) ) ) ; RestoreOp = <STR_LIT> ; MoveReg = <STR_LIT> ; } if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR3Spilled && !


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT>


<s> void ix86_split_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ <NUM_LIT> ] ; op0 = operands [ <NUM_LIT>


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT>


<s> return ( REG_P ( op0 ) && REG_P ( op1 ) && ( ( INT_REG_OK_FOR_BASE_P ( op0 , strict ) && INT_REG_OK_FOR_INDEX_P ( op1 , strict

) ) || ( INT_REG_OK_FOR_BASE_P ( op1 , strict ) && INT_REG_OK_FOR_INDEX_P ( op0 , strict ) ) ) ) ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property ::


<s> return <ISA_LIT>AsmPrinter :: emitInstruction ( MI ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; MCSymbol * EndOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( EndOfSled , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer -> emitLabel ( EndOfSled ) ; recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_ENTER ) ; break ; } case TargetOpcode :: PATCHABLE_RET : { unsigned RetOpcode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst RetInst ; RetInst . setOpcode ( RetOpcode ) ; for ( const auto & MO : make_range ( std :: next ( MI -> operands_begin ( ) ) , MI -> operands_end ( ) ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) RetInst . addOperand ( MCOp ) ; } bool IsConditional ; if ( RetOpcode == <STR_LIT> ) { IsConditional = true ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { break ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { IsConditional = false ; } else { EmitToStreamer ( * OutStreamer , RetInst ) ; break ; } MCSymbol * FallthroughLabel ; if ( IsConditional ) { FallthroughLabel = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ( static_cast < <STR_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( MCSymbolRefExpr :: create ( FallthroughLabel , OutContext ) ) ) ; RetInst = MCInst ( ) ; RetInst . setOpcode ( <STR_LIT> ) ; } OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , RetInst ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> )


<s> SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , ValTy , Shl . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SMPos0 , DL , <STR_LIT> ) , DAG . getConstant ( SMSize0 , DL , <STR_LIT> ) , And0 . getOperand ( <NUM_LIT> ) ) ; } else { if ( ~ CN -> getSExtValue ( ) == ( ( ( ( int64_t ) <NUM_LIT> << SMSize0 ) - <NUM_LIT> ) << SMPos0 ) && ( ( SMSize0 + SMPos0 <= <NUM_LIT> && Subtarget . has<ISA_LIT>64r2 ( ) ) || ( SMSize0 + SMPos0 <= <NUM_LIT> ) ) ) { bool isConstCase = And1 . getOpcode ( ) != <STR_LIT> ; if ( And1 . getOpcode ( ) == <STR_LIT> ) { if ( ! ( CN1 = dyn_cast < ConstantSDNode > ( And1 -> getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; } else { if ( ! ( CN1 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; } if ( CN -> getSExtValue ( ) & CN1 -> getSExtValue ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ValTy = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; SDValue Const1 ; SDValue SrlX ; if ( ! isConstCase ) { Const1 = DAG . getConstant ( SMPos0 , DL , <STR_LIT> ) ; SrlX = DAG . getNode ( <STR_LIT> , DL , And1 -> getValueType (


<s> bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( ) ; unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; if ( ! <STR_LIT> . contains ( Reg ) && ! isWin64


<s> if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! llvm :: prior (


<s> if ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( )

== <STR_LIT> ) return LowerTruncateToBT ( Op , CC , dl , DAG ) ;


<s> } else { return false ; } } else if ( VRI . Repl32 != BG . Repl32 ) { return false ; } return VRI . RLAmt == EffRLAmt ; } ; for ( auto & BG : BitGroups ) { if ( ! MatchingBG ( BG ) ) continue ; if ( BG . StartIdx <= BG . EndIdx ) { for ( unsigned i = BG . StartIdx ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } else { for ( unsigned i = BG . StartIdx ; i < Bits . size ( ) ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; for ( unsigned i = <NUM_LIT> ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } } bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; bool NeedsRotate = VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( bool ) Res ; if ( Use32BitInsts ) NumAndInsts += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; else NumAndInsts += SelectInt64Count ( Mask ) + <NUM_LIT> ; unsigned NumRLInsts = <NUM_LIT> ; bool FirstBG = true ; for ( auto & BG : BitGroups ) { if ( ! MatchingBG ( BG ) ) continue ; NumRLInsts += SelectRotMask64Count ( BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , ! FirstBG ) ; FirstBG = false ; } DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << ( VRI . Repl32 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << NumAndInsts << <STR_LIT> << NumRLInsts << <STR_LIT> ) ; if ( NumAndInsts > NumRLInsts ) continue ; if ( Use32BitInsts && NumAndInsts == NumRLInsts ) continue ; DEBUG ( dbgs ( ) <<


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - <NUM_LIT> ] = true ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) cfun -> machine -> lr_is_wrapped_separately = true ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) cfun -> machine -> toc_is_wrapped_separately


<s> return ( vector signed int ) __builtin_altivec_vupklsh (


<s> unsigned getSORegRegOpValue ( const MachineInstr & MI ,


<s> BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( Pred ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; BICInst . addOperand ( MCOperand ::


<s> return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSignExtendCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : return CombineVLDDUP ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Has<ISA_LIT>Expressions = true ; if ( TheTriple . isMIPS32 ( ) ) UseIntegratedAssembler = true ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUABI64 ) UseIntegratedAssembler = true ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUABIN32 ) UseIntegratedAssembler = true ; if ( TheTriple . getArch ( ) == Triple :: mips64el && TheTriple . isAndroid


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> return parseMSARegs ( Operands , ( int


<s> reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 ,


<s> } else base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; scratch = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; if ( GET_CODE ( base ) == MINUS || ( GET_CODE ( base ) == PLUS && ! CONST_INT_P ( XEXP ( base , <NUM_LIT> ) ) ) ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( base_plus , outval ) ) { if ( ! reg_overlap_mentioned_p ( scratch , outval ) ) std :: swap ( scratch , base_plus ) ; else { rtx scratch_hi = gen_rtx_REG ( HImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( base_plus , outval ) ) { if ( ! reg_overlap_mentioned_p ( scratch , outval ) ) std :: swap ( scratch , base_plus ) ; else { rtx scratch_hi = gen_rtx_REG ( HImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_insn ( gen_addsi3 ( base_plus , base


<s> } } } } else if ( DefMI -> isCopyLike ( ) ) { Reg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) { DefMI = MRI -> getVRegDef ( Reg ) ; continue ; } } else if ( DefMI -> isInsertSubreg ( ) ) { Reg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ; return


<s> Op = SDValue ( DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address ,


<s> virtual bool gate ( function * fun ATTRIBUTE_UNUSED ) { return pru_current_abi


<s> cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( DisableFramePointerElim ( MF ) && MFI -> adjustsStack ( ) ) return true ; return MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || needsStackRealignment


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false


<s> switch ( Desc -> TSFlags & <STR_LIT> ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable (


<s> int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI =


<s> getMemEncodingMMImm4Lsl1 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> )


<s> printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; O <<


<s> if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Integer : case AsmToken :: Real : case AsmToken :: Hash : { S = getLoc ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; if ( Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Real ) ) Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; else if ( IntVal != <NUM_LIT> || isNegative ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; return false ; } const MCExpr * ImmVal ; if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal


<s> if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( CONST_INT_P ( x ) && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ; return aarch64_simd_valid_immediate ( v_op , NULL


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ( mode == HFmode || ( TARGET_SSE && TARGET_SSE_MATH ) ) && flag_finite_math_only

&& ! flag_trapping_math && flag_unsafe_math_optimizations ) ;


<s> int getFAIndex ( ) const { return FrameAddrIndex


<s> static SDValue Concat256BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned

NumElems , SelectionDAG & DAG , SDLoc dl ) {


<s> MRI = & MF . getRegInfo ( ) ; SchedModel . init ( ST . getSchedModel ( ) , & ST , TII ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; unsigned Offset ; if ( TII -> getMemOpBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( & MI ) ; } PrevBaseReg = BaseReg ; } else PrevBaseReg = <NUM_LIT> ; } } return false


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCAsmInfo ) ; for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b ) ; return __ev_mwumian ( t , ( ( __ev64_s32__ )


<s> void <ISA_LIT>ConstantIslands :: createNewWater ( unsigned CPUserIndex , unsigned UserOffset , MachineBasicBlock * & NewMBB ) { CPUser & U = CPUsers [ CPUserIndex ] ; MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; unsigned CPELogAlign = getCPELogAlign ( CPEMI ) ; MachineBasicBlock * UserMBB = UserMI -> getParent ( ) ; const BasicBlockInfo & UserBBI = BBInfo [ UserMBB -> getNumber ( ) ] ; if ( BBHasFallthrough ( UserMBB ) ) { unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = std :: next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset


<s> if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return


<s> auto * SingleMemOpTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; InstructionCost MemOpCost ; bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps ; if ( UseMaskedMemOp ) MemOpCost = getMaskedMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace , CostKind ) ; else MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; unsigned VF = VecTy -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; InstructionCost MaskCost ; if ( UseMaskedMemOp ) { APInt DemandedLoadStoreElts = APInt :: getZero ( VecTy -> getNumElements ( ) ) ; for ( unsigned Index : Indices ) { assert ( Index < Factor && <STR_LIT> ) ; for ( unsigned Elm = <NUM_LIT> ; Elm < VF ; Elm ++ ) DemandedLoadStoreElts . setBit ( Index + Elm * Factor ) ; } Type * I1Type = Type :: getInt1Ty ( VecTy -> getContext ( ) ) ; MaskCost = getReplicationShuffleCost ( I1Type , Factor , VF , UseMaskForGaps ? DemandedLoadStoreElts : APInt :: getAllOnes ( VecTy -> getNumElements ( ) ) , CostKind ) ; if ( UseMaskForGaps ) { auto * MaskVT = FixedVectorType :: get ( I1Type , VecTy -> getNumElements ( ) ) ; MaskCost += getArithmeticInstrCost ( BinaryOperator :: And , MaskVT , CostKind ) ; } } if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = UseMaskedMemOp || NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + MaskCost

+ NumOfUnfoldedLoads * MemOpCost + NumOfMoves ;


<s> if ( SPDiff ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; int SlotSize = is<ISA_LIT>64 ?


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: f2003f > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT>


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MBB -> pred_empty ( ) || ( isBlockOnlyReachableByFallthrough ( & * MBB ) && ! ( MBB -> isEHFuncletEntry ( ) ) ) ) { MachineInstr * MI_subi = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MBB -> insert ( I


<s> const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = <NUM_LIT> ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = <NUM_LIT> ; return


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) ,


<s> else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV


<s> int invert ; rtx label1 , label2 ; invert = <NUM_LIT> ; reg = gen_int_relational ( test_code , NULL_RTX , cmp0 , cmp1 , & invert ) ; if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != <NUM_LIT> ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0


<s> } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case LPCC :: ICC_EQ : case LPCC :: ICC_NE : case LPCC :: ICC_MI : case LPCC :: ICC_PL : case LPCC :: ICC_F : case LPCC :: ICC_T : break ; case LPCC :: ICC_CS : case LPCC :: ICC_CC : case LPCC :: ICC_VS : case LPCC :: ICC_VC : case LPCC ::


<s> if ( ! out_obj_filename ) fatal_error ( input_location , <STR_LIT> ) ; if ( ! dumppfx ) dumppfx = out_obj_filename ; const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , host_descr_filename ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , out_obj_filename ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false , NULL ) ; obstack_free ( & argv_obstack , NULL ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack ,


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const char * JTEntryDirective = MAI -> getData32bitsDirective ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool UseSet = MAI -> hasSetDirective ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JTSets ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; bool isNew = JTSets . insert ( MBB ) ; if ( UseSet &&


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) .


<s> mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( VOIDmode , reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET (


<s> assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize (


<s> Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> assert ( ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasFPCVT ( ) && <STR_LIT> ) ; SDValue Src = Op . getOperand ( Op -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; bool WordInt = Src . getSimpleValueType ( ) . SimpleTy == <STR_LIT> ; bool Signed = Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ; unsigned MovOpc = ( WordInt && ! Signed ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( MovOpc , dl , <STR_LIT> , Src ) ; return convertIntToFP ( Op , Mov , DAG , Subtarget


<s> MCObjectStreamer :: emitFill ( NumBytes , FillValue


<s> break ; case E_SImode : case E_HImode : case E_QImode : break ; default : gcc_unreachable ( ) ; } if ( mode_signbit_p ( mode , * loc ) ) return false ; val = INTVAL ( * loc ) ; if ( ( val < <NUM_LIT> && val !=


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return Error ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( ) , ErrMsg ) ) return Error ( Start , ErrMsg ) ; if ( isParsingMSInlineAsm ( ) ) return CreateMemForMSInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) , Operands ) ; if ( Parser . isParsingMasm ( ) && is64BitMode


<s> Align getStackAlignment ( ) const { return stackAlignment


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) return Subtarget .

isTargetCygMing ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( ( is<ISA_LIT>64 && VT != <STR_LIT> && VT != <STR_LIT> ) || ( ! is<ISA_LIT>64 && VT != <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; bool is64Bit = is<ISA_LIT>64 && VT == <STR_LIT> ; unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , is64Bit ? <STR_LIT> : <STR_LIT> ) . Case ( <STR_LIT> , (

isDarwinABI || is<ISA_LIT>64 ) ? <NUM_LIT> : <STR_LIT> ) . Case ( <STR_LIT> , ( ! is<ISA_LIT>64 && isDarwinABI ) ? <NUM_LIT> :


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( Registry )


<s> MachineInstr * RV = <ISA_LIT>BaseInstrInfo :: optimizeSelect ( MI , SeenMIs , PreferFalse ) ; if ( ! RV && getSubtarget ( ) . hasV8_1MMainlineOps ( ) && ! PreferNoCSEL ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! DestReg . isVirtual ( ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; SeenMIs . insert ( NewMI ) ; return NewMI ; } return RV


<s> Update = findMatchingUpdateInsnBackward ( MBBI , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } int UnscaledOffset = getLdStOffsetOp ( MI ) . getImm ( ) * TII -> getMemScale ( MI ) ; Update = findMatchingUpdateInsnForward ( MBBI , UnscaledOffset , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } return false


<s> if ( Bytes || ( ! Offset && SrcReg != DestReg ) ) { assert ( ( DestReg != <STR_LIT> || Bytes % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; if ( Bytes < <NUM_LIT> ) { Bytes = - Bytes ; Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; } emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , Bytes , Opc , TII , Flag , NeedsWinCFI , HasWinCFI ) ; SrcReg = DestReg ; } assert ( ! ( SetNZCV && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag ,


<s> float32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD ->

getMemoryVT ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> __v4su result ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; shmask = rshift < shmax ; result = vec_vsrw ( ( __v4su ) __A , rshift ) ; result = vec_sel ( shmask , result


<s> return isUImm < <NUM_LIT> , <NUM_LIT> >


<s> return Input . getValueSizeInBits ( ) < RootSizeInBits ; } ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > WideInputs ( Inputs . begin ( ) , Inputs . end ( ) ) ; SmallVector < unsigned , <NUM_LIT> > Offsets ( NumInputs , <NUM_LIT> ) ; unsigned WideSizeInBits = RootSizeInBits ; for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) { SDValue & Src = WideInputs [ i ] ; unsigned & Offset = Offsets [ i ] ; Src = peekThroughBitcasts ( Src ) ; EVT BaseVT = Src . getValueType ( ) ; while ( Src . getOpcode ( ) == <STR_LIT> ) { Offset += Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; } WideSizeInBits = std :: max ( WideSizeInBits , ( unsigned ) Src . getValueSizeInBits ( ) ) ; assert ( ( Offset % BaseVT . getVectorNumElements ( ) ) == <NUM_LIT> && <STR_LIT> ) ; Offset /= BaseVT . getVectorNumElements ( ) ; Offset *= NumMaskElts ; } if ( llvm :: all_of ( Offsets , [ ] ( unsigned Offset ) { return Offset == <NUM_LIT> ; } ) ) return SDValue ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Imm = <NUM_LIT> ; unsigned CurBit = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { CurBit ^= ( Val >> i ) & <NUM_LIT> ; Imm |= ( CurBit << i ) ; if ( ( Val & ~ ( ~ <NUM_LIT> << i ) ) == <NUM_LIT> ) { Imm |= <NUM_LIT> << i ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return S


<s> static SDValue LowerSINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) { SDLoc dl ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand (


<s> SDValue <ISA_LIT>DAGToDAGISel :: createTuple ( ArrayRef < SDValue > Regs , const unsigned RegClassIDs [ ] , const unsigned SubRegs [ ] ) { if ( Regs . size ( ) == <NUM_LIT> ) return Regs [ <NUM_LIT> ] ; assert ( Regs . size ( ) >= <NUM_LIT> && Regs


<s> bool isExynosM1 ( ) const { return CPUString ==


<s> static inline bool isZeroNode ( SDValue Elt ) { return ( ( isa < ConstantSDNode > ( Elt ) && cast < ConstantSDNode > ( Elt ) -> getZExtValue ( ) == <NUM_LIT> ) ||

( isa < ConstantFPSDNode > ( Elt ) && cast < ConstantFPSDNode > ( Elt ) -> getValueAPF ( ) . isPosZero ( ) ) ) ;


<s> if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> )


<s> const auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; int64_t FPOffset = getFPOffset ( MF , ObjectOffset ) . getFixed ( ) ; int64_t Offset = getStackOffset ( MF , ObjectOffset ) . getFixed ( ) ; bool isCSR = ! isFixed && ObjectOffset >= - ( ( int ) AFI -> getCalleeSavedStackSize ( MFI ) ) ; const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) && ! isSVE ) { PreferFP &= ! SVEStackSize ; if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( isCSR && RegInfo -> hasStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> hasStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) UseFP = true ; } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo


<s> SmallPtrSet < SDNode * , <NUM_LIT> > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > <NUM_LIT> ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( <NUM_LIT> ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode (


<s> const TargetInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState ::


<s> void SwitchMode ( uint64_t mode ) { uint64_t oldMode = STI . getFeatureBits ( ) & ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; unsigned FB = ComputeAvailableFeatures ( STI . ToggleFeature


<s> return ( __m64 ) __builtin_arm_wsrawi ( (


<s> return MRI . getRegClass ( Register ) ->


<s> bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , IsVarArg ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , IsVarArg ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; if ( ! SplitRegs . empty ( ) ) { MIRBuilder . buildMerge ( OrigRet . Reg , SplitRegs ) ; } } CallSeqStart . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps (


<s> static __inline qword si_rothm ( qword a , qword b ) { vec_ushort8 neg_b ; vec_ushort8 mask ; neg_b = ( vec_ushort8 ) vec_sub ( vec_splat_s16 ( <NUM_LIT> ) , (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( x == ret ) fprintf ( stderr , <STR_LIT> ) ; else if ( ! ret ) fprintf ( stderr , <STR_LIT> ) ; else { fprintf ( stderr


<s> bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( ! Callee && ! Symbol ) return false ; if ( IsTailCall ) return false ; CodeModel :: Model CM = TM . getCodeModel ( ) ; if ( CM != CodeModel :: Large && ! Subtarget -> useSmallAddressing ( ) ) return false ; if ( CM == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) return false ; if ( IsVarArg ) return false ; const Function * F = dyn_cast_or_null < Function > ( Callee ) ; if ( FuncInfo . MF -> getFunction ( ) . isPagerando ( ) || ( F && F -> isPagerando ( ) ) ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr

. getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; CmpInst :: Predicate P = ( CmpInst :: Predicate ) Predicate . getPredicate ( ) ; MachineInstr * FoldCmp = tryFoldIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( FoldCmp ) return { FoldCmp , P } ; unsigned CmpOpc = <NUM_LIT> ; Register ZReg ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ( CmpTy . isScalar ( ) || CmpTy . isPointer ( ) ) && <STR_LIT> ) ; if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) || CmpTy . isPointer ( ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT>


<s> ix86_first_cycle_multipass_data_t data = ix86_first_cycle_multipass_data ; gcc_assert ( data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; data -> ifetch_block_len = <NUM_LIT> ; data -> ifetch_block_n_insns


<s> return ( __m512i ) __builtin_ia32_vplzcntd_512_mask ( ( __v16si ) __A , ( __v16si ) _mm512_setzero_si512 ( ) ,


<s> return ( __m128i ) __builtin_ia32_vplzcntd_128_mask ( ( __v4si ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( tramp_code_sz ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , ptr_mode , tramp_code_sz ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; if ( GET_MODE ( fnaddr ) != ptr_mode ) fnaddr = convert_memory_address ( ptr_mode , fnaddr ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , tramp_code_sz + POINTER_BYTES ) ; emit_move_insn ( mem , chain_value ) ; a_tramp = XEXP ( m_tramp , <NUM_LIT> ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , a_tramp , ptr_mode , plus_constant


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo (


<s> return ; } unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ; } DebugLoc DL = DebugLoc


<s> static bool isCalleeSavedCR ( unsigned Reg ) { return <STR_LIT> == Reg || Reg == <STR_LIT> ||


<s> bool hasVDSPV2 ( ) const { return HasVDSPV2


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoOddSPReg ( ) { <ISA_LIT>TargetStreamer :: emitDirectiveSetNoOddSPReg ( )


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodesFPR32RegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR32DecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler ::