<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> static SDValue lowerV2I64Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL ,

<STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ;


<s> Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> StartLoc = S ; Op -> EndLoc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout )


<s> case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , true , <STR_LIT> ) ; case <STR_LIT> : case


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( )


<s> vqshrn_n_u64 ( uint64x2_t __a , const int __b ) { return ( uint32x2_t ) __builtin_neon_vqshrnu_nv2di ( (


<s> uint64_t value = symbol -> fragRef ( ) -> getOutputOffset ( ) ; uint64_t addr = symbol -> fragRef ( ) -> frag ( ) -> getParent ( ) -> getSection ( ) . addr ( ) ; sym_value = addr + value ; } Stub * stub = getStubFactory ( ) -> create ( pRel , sym_value , pBuilder , * getBRIslandFactory ( ) ) ; if ( stub == NULL ) return false ; assert ( stub -> symInfo ( ) != NULL ) ; pRel . setSymInfo ( stub -> symInfo ( ) ) ; LDSection & symtab = getOutputFormat ( )


<s> unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N


<s> return ( __m512i ) __builtin_ia32_movdqa32load512_mask ( ( const __v16si * ) __P ,


<s> OS << <STR_LIT> << Offset << <STR_LIT>


<s> static SDValue PerformBLENDICombine ( SDNode * N , SelectionDAG & DAG ) { SDValue V0 = N -> getOperand ( <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == V0 . getValueType ( ) && VT == V1 . getValueType ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) if ( auto * Mask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( Mask ->

getZExtValue ( ) == <NUM_LIT> && ! isShuffleFoldableLoad ( V0 ) ) {


<s> unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ; Inst . addOperand ( MCOperand :: CreateImm ( Value )


<s> static bool mips_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return mips_const_insns ( x )


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { <STR_LIT> , <STR_LIT>


<s> if ( OutStreamer . hasRawTextSupport ( ) ) return ; const <ISA_LIT>ElfTargetObjectFile & TLOFELF = static_cast < const <ISA_LIT>ElfTargetObjectFile & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFELF . getAttributesSection (


<s> x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_nested_too_deep ( void * const TM_buff ) { texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; return _TEXASRU_NESTING_OVERFLOW (


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , STI . getFramePointerReg ( ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs (


<s> for ( unsigned I = <NUM_LIT> ; I < RequiredGprsUponSplit ; I ++ ) { unsigned Reg = State . AllocateReg ( AvailableRegs [ I ] ) ; assert ( Reg && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo ,


<s> } if ( ( d -> vec_flags == VEC_ADVSIMD || d -> vec_flags == VEC_SVE_DATA || d -> vec_flags == ( VEC_SVE_DATA | VEC_PARTIAL ) || d -> vec_flags == VEC_SVE_PRED ) && known_gt ( nelt , <NUM_LIT> ) ) { if ( aarch64_evpc_rev_local ( d ) ) return true ; else if ( aarch64_evpc_rev_global ( d ) ) return true ; else if ( aarch64_evpc_ext ( d ) ) return true ; else if ( aarch64_evpc_dup ( d ) ) return true ; else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d ) ) return true ; else if ( aarch64_evpc_trn ( d ) ) return true ; else if ( aarch64_evpc_sel ( d


<s> MI = & * Def ; break ; } if ( J == I ) return false ; } } MachineInstr * Sub = nullptr ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineBasicBlock :: reverse_iterator RI = ++ I . getReverse ( ) , RE = CmpInstr . getParent ( ) == MI -> getParent ( ) ? Def . getReverse ( ) : CmpInstr . getParent ( ) -> rend ( ) ; MachineInstr * Movr0Inst = nullptr ; for ( ; RI != RE ; ++ RI ) { MachineInstr & Instr = * RI ; if ( ! IsCmpZero && isRedundantFlagInstr ( CmpInstr , SrcReg , SrcReg2 , CmpMask , CmpValue , Instr ) ) { Sub = & Instr ; break ; } if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) { if ( ! Movr0Inst && Instr . getOpcode ( ) == <STR_LIT> && Instr . registerDefIsDead ( <STR_LIT> , TRI ) ) { Movr0Inst = & Instr ; continue ; } return false ; } } if ( ! IsCmpZero && ! Sub ) return false ; bool IsSwapped = ( SrcReg2 != <NUM_LIT> && Sub && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ; bool IsSafe = false ; SmallVector < std :: pair < MachineInstr * , <STR_LIT> > , <NUM_LIT> > OpsToUpdate ; MachineBasicBlock :: iterator E = CmpInstr . getParent ( ) -> end ( ) ; for ( ++ I ; I != E ; ++ I ) { const MachineInstr & Instr = * I ; bool ModifyEFLAGS = Instr . modifiesRegister ( <STR_LIT> , TRI ) ; bool UseEFLAGS = Instr . readsRegister ( <STR_LIT> , TRI ) ; if ( ! UseEFLAGS && ModifyEFLAGS ) { IsSafe = true ; break ; } if ( ! UseEFLAGS && ! ModifyEFLAGS ) continue ; <STR_LIT> OldCC = <STR_LIT> ; if ( IsCmpZero || IsSwapped ) { if ( Instr . isBranch ( ) ) OldCC = <STR_LIT> ( Instr ) ; else { OldCC = <STR_LIT> ( Instr ) ; if ( OldCC == <STR_LIT> ) OldCC = <STR_LIT> ( Instr ) ; } if ( OldCC == <STR_LIT> ) return false ; } <STR_LIT> ReplacementCC = <STR_LIT> ; if ( IsCmpZero ) { switch ( OldCC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( __mmask8 ) __builtin_ia32_pcmpeqd128_mask ( ( __v4si ) __A ,


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool IsThumb ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5


<s> for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i )


<s> if ( fntype_or_decl && DECL_P ( fntype_or_decl ) ) fn = fntype_or_decl ; fntype = fn ? TREE_TYPE ( fn ) : fntype_or_decl ; if ( ix86_function_type_abi ( fntype ) == MS_ABI ) { if ( TARGET_64BIT ) return function_value_ms_64 ( orig_mode


<s> const MachineBasicBlock * MBB = MBBI -> getParent ( ) ; while ( MBBI == MBB -> begin ( ) ) { if ( MBB == & MBB -> getParent ( ) ->

front ( ) ) return MachineBasicBlock :: const_iterator ( ) ;


<s> const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , <STR_LIT> ) , getTargetNode ( N , Ty , DAG , <STR_LIT> | MO_NC )

, getTargetNode ( N , Ty , DAG , <STR_LIT> | MO_NC ) , getTargetNode ( N , Ty , DAG , <STR_LIT> | MO_NC ) ) ;


<s> if ( aarch64_classify_symbol ( base , offset , SYMBOL_CONTEXT_ADR ) != SYMBOL_FORCE_TO_MEM ) return true ; else return mode != ptr_mode ; } return aarch64_tls_referenced_p ( x


<s> Inst . addOperand ( MCOperand :: CreateImm ( getCoproc


<s> LoadMI = MRI . getUniqueVRegDef ( LoadReg ) ; assert ( LoadMI && <STR_LIT> ) ; } if ( ! ( IsZExt && isZExtLoad ( LoadMI ) ) && ! ( ! IsZExt && isSExtLoad ( LoadMI ) ) ) return false ; if ( RetVT != <STR_LIT> || SrcVT > <STR_LIT> ) { updateValueMap ( I , Reg ) ; return true ; } if ( IsZExt ) { Register Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg = Reg64 ; } else { assert ( ( MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getSubReg


<s> MachineModuleInfoMachO & <ISA_LIT>MCInstLower :: getMachOMMI


<s> assert ( inImplicitITBlock ( ) ) ; assert ( ! isITBlockFull ( ) ) ; assert ( Cond == ITState . Cond || Cond == <STR_LIT> ( ITState . Cond ) ) ; unsigned TZ = countTrailingZeros ( ITState . Mask ) ; unsigned NewMask = <NUM_LIT>


<s> return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_int ( <NUM_LIT> - count ) ) ,


<s> bool <ISA_LIT>FrameLowering :: needsFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet ::

FunctionIndex , Attribute :: Naked ) ) return false ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; } assert ( Opc &&


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return


<s> MachineIRBuilder MIRBuilder ( MI ) ; MIRBuilder . buildInstr ( MatchInfo . Opc , { MatchInfo . Dst } , MatchInfo


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> int <ISA_LIT>A57FPLoadBalancing :: scavengeRegister ( Chain * G , Color C , MachineBasicBlock & MBB ) { RegScavenger RS ; RS . enterBasicBlock ( & MBB ) ; RS . forward ( MachineBasicBlock :: iterator ( G -> getStart ( ) ) ) ; unsigned RegClassID = G -> getStart ( ) -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; BitVector AvailableRegs = RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( MachineBasicBlock :: iterator I = G -> getStart ( ) , E = G -> getEnd ( ) ; I != E ; ++ I ) { RS . forward


<s> case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC64 : ELF :: R_<ISA_LIT>_64_64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC32 : ELF :: R_<ISA_LIT>_64_32 ; case RT64_32S : return ELF :: R_<ISA_LIT>_64_32S ; case RT64_16 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC16 : ELF :: R_<ISA_LIT>_64_16 ; case RT64_8 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC8 : ELF :: R_<ISA_LIT>_64_8 ; } case MCSymbolRefExpr :: VK_GOT : switch ( Type ) { case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC64 : ELF :: R_<ISA_LIT>_64_GOT64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC32 : ELF :: R_<ISA_LIT>_64_GOT32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT64_64 ) ; assert ( ! IsPCRel ) ; return ELF :: R_<ISA_LIT>_64_GOTOFF64 ; case MCSymbolRefExpr :: VK_TPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_TPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_TPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_DTPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_DTPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : llvm_unreachable ( <STR_LIT> ) ; } case MCSymbolRefExpr :: VK_SIZE : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_SIZE64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_SIZE32 ; case RT64_32S : case


<s> if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ; return TargetLowering :: getSafeStackPointerLocation ( IRB )


<s> static const <ISA_LIT>MCExpr * CreateHi ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_ABS_HI ,


<s> return true ; case 'R' : if ( MO . getType ( ) == MachineOperand :: MO_Register ) { OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) + <NUM_LIT> ) ; return false ; } } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : if ( MO . getReg ( ) == <STR_LIT> ) return false ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8s4OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , dl , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V =

combineExtSetcc ( N , DAG , Subtarget ) ) return V ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & Ostream , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { unsigned Value = getBinaryCodeForInstr ( Inst , Fixups ,


<s> case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return VS ; case HI : return LS ; case LS : return HI ; case GE : return LT ; case LT :


<s> enum direction ia64_hpux_function_arg_padding ( machine_mode mode , const_tree type ) { if ( type && AGGREGATE_TYPE_P ( type ) && int_size_in_bytes ( type ) < UNITS_PER_WORD ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type )


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( unsigned


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; if ( AssemblerOptions . size ( ) == <NUM_LIT> ) return reportParseError ( Loc , <STR_LIT> ) ; MCSubtargetInfo & STI = copySTI ( ) ; AssemblerOptions . pop_back ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( AssemblerOptions . back ( )


<s> SDValue In64 ; if ( Subtarget . hasHighWord ( ) ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; } else { In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; if ( Subtarget . hasHighWord ( ) ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; } llvm_unreachable ( <STR_LIT> )


<s> RegisterTarget < Triple :: cpu0el , true > Y ( The<ISA_LIT>elTarget , <STR_LIT> , <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Enable<ISA_LIT>TailCalls


<s> return ( __m128d ) vec_mergel ( ( __v2df ) __A ,


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> , VA . getLocInfo ( ) == CCValAssign :: SExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA .


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case


<s> bool SelectAddrIdx ( SDValue N , SDValue


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ! ( MFI . hasCalls ( ) || ! MRI . reg_nodbg_empty ( <STR_LIT> ) || ! MRI . reg_nodbg_empty ( <STR_LIT> )


<s> return isConstantImm ( ) ? isUInt < Bits > ( getConstantImm ( ) ) :


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( CallerF -> getReturnType ( ) -> is<ISA_LIT>_FP80Ty ( ) && ! RetTy -> is<ISA_LIT>_FP80Ty ( ) ) return false ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( ! CCMatch && CallerCC == CallingConv :: <ISA_LIT>_StdCall ) return false ; if ( isVarArg && ! Outs . empty ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins


<s> void LLVMInitializePowerPCAsmPrinter ( ) { TargetRegistry :: RegisterAsmPrinter ( The<ISA_LIT>32Target ,


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; unsigned IgnoredFrameReg ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum +


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( Subtarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( ! Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; Register TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT>


<s> void <ISA_LIT>CCState :: PreAnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArgs [ Outs [ i ] . OrigArgIndex ] . Ty ,


<s> return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> ) ShiftTy = <STR_LIT> ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { SMLoc L = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; ShiftReg = tryParseRegister ( ) ; if ( ShiftReg == - <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return - <NUM_LIT> ; } } else


<s> int speci , regi ; gcc_assert ( REG_P ( op ) ) ; if ( ! canon_reg_names [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] ) { for ( regi = <NUM_LIT> ; regi < LAST_GP_REGNUM ; regi ++ ) for ( speci = <NUM_LIT> ; speci < <NUM_LIT> ; speci ++ ) { const int sz = ( speci == <NUM_LIT> ) ? <NUM_LIT> : ( ( speci == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( regi + sz ) > ( <NUM_LIT> * <NUM_LIT> ) ) continue ; const char * suffix = <STR_LIT> ; switch ( ( sz << <NUM_LIT> ) | ( regi % <NUM_LIT> ) ) { case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; default : continue ; } sprintf ( & canon_reg_names [ speci ] [ regi ] [ <NUM_LIT> ] , <STR_LIT> , regi / <NUM_LIT> , suffix ) ; } } switch ( GET_MODE_SIZE ( GET_MODE ( op ) ) ) { case <NUM_LIT> : speci = <NUM_LIT>


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return


<s> void addMVEVectorIndexOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops


<s> SDValue X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; if ( HasR2 ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> int mips_dspalu_bypass_p ( rtx out_insn , rtx in_insn ) { int i ; int num_bypass = ARRAY_SIZE ( dspalu_bypass_table ) ; enum insn_code out_icode = ( enum insn_code ) INSN_CODE ( out_insn ) ; enum insn_code in_icode = ( enum insn_code


<s> emit_insn ( gen_sync_icache ( validize_mem ( gen_rtx_MEM ( DImode , trampaddr ) ) , GEN_INT ( mmix_trampoline_size -


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( SrcReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC


<s> if ( frame_pointer_needed ) return to == HARD_FRAME_POINTER_REGNUM ; return true


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16 ( SDValue Addr , SDValue & Base , SDValue & Offset ) { llvm_unreachable ( <STR_LIT>


<s> case IES_RPAREN : case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) { ErrMsg = <STR_LIT> ; return


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> else { rtx loc = gen_rtx_PLUS ( Pmode , tmp , vcall_offset_rtx ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , gen_rtx_USE ( VOIDmode , gen_rtx_REG ( SImode , LR_REGNO ) ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; if ( DEFAULT_ABI == ABI_ELFv2 ) cfun -> machine -> r2_setup_needed = true ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT>


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst ,

Src , Size , Align , RTLIB :: MEMSET ) ;


<s> } else { if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_PE_SHARED ) * f ++ = 's' ; } * f = '\0' ; fprintf ( asm_out_file , <STR_LIT> , name , flagchars ) ; if ( flags & SECTION_LINKONCE ) { bool discard = ( flags & SECTION_CODE ) || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; fprintf ( asm_out_file , <STR_LIT> , ( discard ? <STR_LIT>


<s> static SDValue performDSPShiftCombine ( unsigned Opc , SDNode * N , EVT Ty , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned EltSize = Ty . getScalarSizeInBits ( ) ; BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Subtarget . hasDSP ( ) ) return SDValue ( ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( Opc , DL , Ty , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( SplatValue . getZExtValue ( ) , DL ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , false ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CM , OL ) , isLittle ( false ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , false , * this ) { initAsmInfo (


<s> TgtMBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( )


<s> else { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } if ( mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } else { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + <NUM_LIT> * cum -> words ; } } if ( ( ( TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32 ) && ! TARGET_SOFT_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT && cum -> nargs_prototype <= <NUM_LIT> && type != NULL_TREE && ! cum -> incoming ) || ( ! TARGET_64BIT && ! TARGET_GAS && ! cum -> incoming && cum -> indirect && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { retval = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , fpr_reg_base ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , gpr_reg_base ) , const0_rtx ) ) ) ; } else { if ( TARGET_SOFT_FLOAT || ( ! TARGET_PORTABLE_RUNTIME && ! TARGET_64BIT && ! TARGET_ELF32 && cum -> indirect ) || GET_MODE_CLASS ( mode ) != MODE_FLOAT || ( type

&& AGGREGATE_TYPE_P ( type ) ) ) retval = gen_rtx_REG ( mode , gpr_reg_base ) ;


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget . getFrameLowering ( )


<s> putc ( '\n' , file ) ; } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( TARGET_RELOCATABLE && ! TARGET_SECURE_PLT && ( get_pool_size ( ) != <NUM_LIT> || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name == '.' ) desc_name ++ ; if ( TREE_PUBLIC ( decl ) ) fprintf ( file , <STR_LIT> , desc_name ) ; fprintf ( file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; fprintf ( file , <STR_LIT> , desc_name ) ; fprintf ( file , <STR_LIT> , orig_name ) ; fputs ( <STR_LIT> , file ) ; fputs ( <STR_LIT> , file ) ; fprintf ( file , <STR_LIT> ) ; } ASM_OUTPUT_LABEL ( file ,


<s> rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; emit_move_insn ( reg , mem ) ; return alloc_reg_note ( REG_CFA_RESTORE ,


<s> std :: vector < Constant * > CV ; if ( SrcVT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat


<s> static int get_reg ( enum ia64_frame_regs r ) { reg_emitted (


<s> int RegBytes = TRI -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( RegBytes > <NUM_LIT> ) return false ; const TargetRegisterClass * NOREXRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> } ; if ( RC == NOREXRegClasses [ Log2_32 ( RegBytes ) ] ) return false ; const TargetRegisterClass * GPRRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> ,


get<ISA_LIT>SubSuperRegister ( Reg , VT ) ;


<s> } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags (


<s> int getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm ,


<s> uint64_t getPC32DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> Worklist . push_back ( PreHeader ) ; Visited . insert ( LoopStart -> getParent ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( Visited . count ( MBB ) ) continue ; for ( MachineInstr & MI : * MBB ) { if ( ! IsInvalidTPInstruction ( MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB = BuildMI ( * PreHeader , PreHeader -> getFirstTerminator ( ) , LoopStart -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; LoopStart -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; RevertWhileLoopStartLR ( LoopStart , TII , <STR_LIT> , true ) ; return MIB ; } Visited . insert ( MBB ) ; for ( auto * Pred : MBB -> predecessors ( ) ) Worklist . push_back ( Pred ) ; } return


<s> TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( )


<s> bool isImm1_8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm


<s> break ; case <STR_LIT> : case <NUM_LIT> : break ; } for ( unsigned i = <NUM_LIT> ; i != MI . getNumOperands ( ) ; ++ i ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned SrcReg = MI . getOperand ( i ) . getReg ( ) ; if ( SrcReg >= <STR_LIT> && SrcReg <= <STR_LIT> ) VEX_L = <NUM_LIT> ; } unsigned NumOps = MI . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; bool IsDestMem = false ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : IsDestMem = true ; NumOps = CurOp = <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getNumOperands ( ) > CurOp && MI . getOperand ( CurOp ) . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) { VEX_4V = getVEXRegisterEncoding ( MI , IsDestMem ? CurOp - <NUM_LIT> : CurOp ) ; CurOp ++ ; } if ( IsDestMem ) CurOp = <NUM_LIT> ; if ( ( TSFlags >> <NUM_LIT> ) & <STR_LIT> ) NumOps -- ; for ( ; CurOp != NumOps ; ++ CurOp ) { const MCOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( ! VEX_B && MO . isReg ( ) && ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO . getReg ( ) ) ) VEX_X = <NUM_LIT> ; } break ; default : if ( ! MI . getNumOperands ( ) ) break ; if ( MI . getOperand ( CurOp ) . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; CurOp ++


<s> GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; if ( OpFlags != <STR_LIT> ) assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , TargetFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , TargetFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel (


<s> static DecodeStatus DecodeCPSInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> static std :: string computeDataLayout ( const Triple & TT ) { return <STR_LIT>


<s> std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( )


<s> const AsmToken & Tok = getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned Reg = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( Reg == <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = Reg ; Lex ( ) ; return


<s> auto MI = MBB . begin ( ) ; if ( MI == MBB . end ( ) || EndbrOpcode != MI -> getOpcode ( ) ) { BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) ,


<s> const MCExpr * Expr = getMemOffset ( ) ; addExpr ( Inst , Expr ) ; Inst . addOperand ( MCOperand :: createImm ( getMemOp ( )


<s> tmp = build ( GE_EXPR , boolean_type_node , next_fp_tmp , tmp ) ; cmp = build ( COND_EXPR , void_type_node , tmp , build ( GOTO_EXPR , void_type_node , lab_false ) , NULL ) ; if ( ! is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_ALIGN ( eff_type ) > BITS_PER_WORD || ( is_double || size == <NUM_LIT> ) ) { tmp = fold_convert ( ptr_type_node , size_int ( UNITS_PER_WORD ) ) ; tmp = build ( BIT_AND_EXPR , ptr_type_node , next_fp_tmp , tmp ) ; tmp = build ( PLUS_EXPR , ptr_type_node , next_fp_tmp , tmp ) ; tmp = build ( MODIFY_EXPR , ptr_type_node , next_fp_tmp , tmp ) ; gimplify_and_add ( tmp , pre_p ) ; } if ( is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_MODE ( eff_type ) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN ) { tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build ( COMPLEX_EXPR , type , real , imag ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build ( LABEL_EXPR , void_type_node , lab_false ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , next_stack ) ; tmp = build ( MODIFY_EXPR , void_type_node , addr , tmp ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build2 ( MODIFY_EXPR , ptr_type_node , next_fp_tmp , valist ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build2 ( MODIFY_EXPR , ptr_type_node , valist , next_fp_tmp ) ; gimplify_and_add ( tmp , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_convert ( ptr_type_node , size_int ( rsize ) ) ; tmp = build ( PLUS_EXPR , ptr_type_node , next_o , tmp ) ; tmp = build ( GT_EXPR , boolean_type_node , tmp , next_o_limit ) ; tmp = build ( COND_EXPR , void_type_node , tmp , build ( GOTO_EXPR , void_type_node , lab_false ) , NULL ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , next_o ) ; tmp = build ( MODIFY_EXPR , void_type_node , addr , tmp ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( tmp , pre_p


<s> return ( __m256i ) __builtin_ia32_lddqu256 ( ( char const *


<s> int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) { assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 <= Offset2 ) && <STR_LIT> ) ; const MachineFrameInfo & MFI = FirstLdSt . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; return shouldClusterFI ( MFI , BaseOp1 . getIndex ( ) , Offset1 , FirstOpc , BaseOp2 . getIndex ( ) , Offset2 , SecondOpc ) ; } assert ( Offset1 <= Offset2 && <STR_LIT>


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm )


<s> static bool isCSRestore ( MachineInstr * MI , const MCPhysReg * CSRegs ) { unsigned RtIdx = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) RtIdx = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( ! isCalleeSavedRegister ( MI -> getOperand ( RtIdx ) . getReg ( ) , CSRegs ) || ! isCalleeSavedRegister ( MI -> getOperand ( RtIdx + <NUM_LIT> ) . getReg ( ) , CSRegs ) || MI -> getOperand ( RtIdx + <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; return true


<s> SMLoc S ; bool isParenExpr = false ; <ISA_LIT>AsmParser :: OperandMatchResultTy Res = MatchOperand_NoMatch ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands .


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return lowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget


<s> if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction (


<s> static inline unsigned getCompareZeroCCMask ( unsigned int Flags ) { return ( Flags &

CompareZeroCCMaskMask ) >> CompareZeroCCMaskShift ;


<s> case M16_REGS : case GENERAL_REGS : return <NUM_LIT> ; case ACC_REGS : return <NUM_LIT> ; case FP_REGS


<s> int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= <NUM_LIT> ; rshift /= <NUM_LIT> ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = <NUM_LIT> ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i *


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O ,


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op .


<s> RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( The<ISA_LIT>V9Target


<s> unsigned BrOffset = getOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32


<s> if ( ! is_gimple_assign ( def ) || ( ! gimple_assign_load_p ( def ) && ( gimple_assign_rhs_code ( def ) != BIT_FIELD_REF || ! VECTOR_TYPE_P ( TREE_TYPE ( TREE_OPERAND ( gimple_assign_rhs1 ( def ) , <NUM_LIT> )

) ) ) ) ) stmt_cost += ix86_cost -> sse_to_integer ;


<s> while ( ( cur = val . find_first_of ( <STR_LIT> , prev ) ) != std :: string :: npos ) { word = val . substr ( prev , cur - prev


<s> static bool WindowsRequiresStackProbe ( const MachineFunction & MF , size_t StackSizeInBytes ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = ( MFI . getStackProtectorIndex ( ) > <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; return ( StackSizeInBytes >= StackProbeSize ) && ! F . hasFnAttribute (


<s> void printAbsAddrOperand ( const MachineInstr *


<s> BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; if ( Is64Bit ) { const unsigned RegAX = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg10 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg11 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVrr = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVri = IsLP64 ? <STR_LIT> : <STR_LIT> ; if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( MOVrr ) , RegAX ) . addReg ( Reg10 ) ; BuildMI ( allocMBB , DL , TII . get ( MOVri ) , Reg10 ) . addImm ( StackSize ) ; BuildMI ( allocMBB , DL , TII . get ( MOVri ) , Reg11 ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; } else { BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addImm ( StackSize ) ; } if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { if ( STI . useRetpoline ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF . getMMI ( ) . setUsesMorestackAddr ( true ) ; } else { if ( Is64Bit ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; else BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; } if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) ; else BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) ; allocMBB -> addSuccessor ( & PrologueMBB ) ; checkMBB -> addSuccessor


<s> if ( TARGET_ARCH64 && type != <NUM_LIT> && AGGREGATE_TYPE_P (


<s> SDValue <ISA_LIT>TargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG


<s> if ( ! MEM_P ( x ) || ! SYMBOL_REF_P ( XEXP ( x , <NUM_LIT> ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) continue ; mode = GET_MODE ( x ) ; if ( ! VECTOR_MODE_P ( mode ) ) return ; constant = get_pool_constant ( XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , <NUM_LIT> ) ; if ( constant == NULL_RTX || GET_CODE ( constant ) != CONST_VECTOR ) return ; } first = XVECEXP ( constant , <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < GET_MODE_NUNITS ( mode ) ; ++ i ) { rtx tmp = XVECEXP ( constant , <NUM_LIT> , i ) ; if ( ! rtx_equal_p ( tmp , first ) ) return ; } broadcast_mem = force_const_mem ( GET_MODE_INNER ( mode ) , first ) ; vec_dup = gen_rtx_VEC_DUPLICATE ( mode , broadcast_mem ) ; validate_change ( insn , loc , vec_dup


<s> if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= <NUM_LIT> ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info ->


<s> assert ( Amt < <NUM_LIT> && <STR_LIT> ) ; return ( Val >> Amt ) | ( Val << ( (


<s> return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , FK_Data_4

) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? &


<s> void startExplicitITBlock ( <STR_LIT> Cond , unsigned Mask ) { assert ( ! inITBlock ( ) ) ; ITState . Cond = Cond ; ITState . Mask = Mask ; ITState . CurPosition = <NUM_LIT> ; ITState . IsExplicit = true


<s> explicit <ISA_LIT>ScalarTargetTransformImpl ( const TargetLowering * TL ) : ScalarTargetTransformImpl ( TL


<s> if ( DisableForwardSearch || ! Slot -> isCall ( ) ) return false ; RegDefsUses RegDU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; NoMemInstr NM ; Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , Filler ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot


<s> HasHazard |= SawStore | SawLoad ; SawStore = true ; } else if ( Candidate . mayLoad ( ) ) { HasHazard |= SawStore ; SawLoad = true ; } assert ( ( ! Candidate . isCall ( ) && !

Candidate . isReturn ( ) ) && <STR_LIT> ) ;


<s> if ( getUniqueInsertion ( Op . getNode ( ) , UniqueIdx ) ) { SDValue AccuV = DAG . getUNDEF ( Op . getValueType ( ) ) ; auto ElemV = Op -> getOperand ( UniqueIdx ) ; SDValue IdxV = DAG . getConstant ( UniqueIdx , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , AccuV , ElemV , IdxV ) ; } if ( SDValue ScalarV = getSplatValue ( Op . getNode ( ) ) ) { MVT LegalResVT = <STR_LIT> ( ElemVT , <NUM_LIT> ) ; auto AVL = DAG . getConstant ( NumEls , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , LegalResVT , Op . getOperand ( <NUM_LIT> ) , AVL ) ; } return SDValue (


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val


<s> const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext ( )


<s> assert ( MemOpcodes && <STR_LIT> ) ; return MemOpcodes [ Form231


<s> bool hasVDSPV2_FLOAT ( ) const { return HasVDSPV2


<s> if ( T -> isPointerTy ( ) ) T = T -> getPointerElementType ( ) ; if ( T -> getScalarSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; T -> dump ( ) ) ; return false ; } if ( isa < StoreInst > ( I ) || isa < LoadInst > ( I ) ) { Value * Ptr = isa < LoadInst > ( I ) ? I . getOperand ( <NUM_LIT> ) : I . getOperand ( <NUM_LIT> ) ; int64_t NextStride = getPtrStride ( PSE , Ptr , L ) ; if ( NextStride == <NUM_LIT> ) { continue ; } else if ( NextStride == - <NUM_LIT> || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } else if ( EnableMaskedGatherScatters ) { const SCEV * PtrScev = replaceSymbolicStrideSCEV ( PSE , llvm :: ValueToValueMap ( ) , Ptr ) ; if ( auto AR = dyn_cast < SCEVAddRecExpr > ( PtrScev ) ) { const SCEV * Step = AR -> getStepRecurrence ( * PSE . getSE ( ) ) ; if ( PSE . getSE ( ) -> isLoopInvariant ( Step , L ) ) continue ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT>


<s> switch ( MI . getOpcode ( ) ) { default : break ; case TargetOpcode :: COPY : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> .


<s> void printi16mem ( const MachineInstr * MI , unsigned OpNo ) { O <<


<s> Attribute SFAttr = F . getFnAttribute ( <STR_LIT> ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS ,

* this , Options . StackAlignmentOverride ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr


<s> return ( ( TARGET_FMOVD ? <NUM_LIT> : <NUM_LIT> ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return <NUM_LIT> ; if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) return <NUM_LIT> * ( ( GET_MODE_SIZE ( mode )


<s> FunctionPass * llvm :: create<ISA_LIT>EmitGPRestorePass ( <ISA_LIT>TargetMachine & tm ) { return new Inserter ( tm


<s> return ( __m128d ) __builtin_ia32_cmpnltsd ( ( __v2df ) __A , (


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & CTX ) { return new <ISA_LIT>MCCodeEmitter (


<s> bool <ISA_LIT>InstructionSelector :: selectUnmergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) && <STR_LIT> ) ; unsigned NumDefs = I . getNumOperands ( ) - <NUM_LIT> ; unsigned SrcReg = I . getOperand ( NumDefs ) . getReg ( ) ; unsigned DefSize = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) . addImm ( Idx * DefSize ) ; if ( ! select ( ExtrInst ) ) return false ; } I . eraseFromParent ( )


<s> GlobalBaseReg = <NUM_LIT> ; <ISA_LIT>Lowering = TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ; <ISA_LIT>SubTarget = TM . getSubtargetImpl ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode


<s> emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; OutStreamer -> AddComment (


<s> auto Mapping = getValueMapping ( OpRegBankIdx [ Idx ] , <NUM_LIT> ) ; if ( ! Mapping -> isValid ( ) ) return false ; OpdsMapping [ Idx ]


<s> return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; } O << <STR_LIT> << getRegisterName (


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case


<s> static DecodeStatus DecodetGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void *


<s> bool hasMTHC1 ( ) const { return true


<s> MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Width = VT . getSizeInBits ( ) ; if ( V0 . getValueSizeInBits ( ) > Width ) V0 = extractSubVector ( V0 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; else if ( V0 . getValueSizeInBits ( ) < Width ) V0 = insertSubVector ( DAG . getUNDEF ( VT ) , V0 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; if ( V1 . getValueSizeInBits ( ) > Width ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; else if ( V1 . getValueSizeInBits ( ) < Width ) V1 = insertSubVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; return DAG . getNode ( HOpcode , SDLoc ( BV ) , VT


<s> else MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MAI -> addInitialFrameState ( MCCFIInstruction :: createDefCfa ( nullptr , Reg


<s> void <ISA_LIT>ELFStreamer :: emitFnStart ( ) { assert ( FnStart == nullptr ) ; FnStart = getContext ( )


<s> initialize<ISA_LIT>MemAluCombinerPass ( * PassRegistry :: getPassRegistry (


<s> void <ISA_LIT>InstrInfo :: replaceInstrOperandWithImm ( MachineInstr & MI , unsigned OpNo , int64_t Imm ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; Register InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; if ( MI . implicit_operands ( ) . empty ( ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) { MachineOperand & MO = MI


<s> * hi_op1 = gen_highpart ( SImode , op1 ) ; * lo_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_lowpart_offset


<s> unsigned getSORegRegOpValue ( const MachineInstr & MI ,


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) )


<s> return MI && ( MI -> getOpcode ( ) == <STR_LIT> || ( STI

-> useLVIControlFlowIntegrity ( ) && MI -> isCall ( ) ) ) ;


<s> InlineAsmHelper ( LLVMContext & C_ , BasicBlock * BB_ ) : C ( C_ ) , BB


<s> if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1 -> getConstantOperandVal ( <NUM_LIT> ) ; Flags = SetCC0 -> getOperand ( <NUM_LIT> ) ; return true


<s> virtual const char * getPassName ( )


<s> <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , OL


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU , bool isLittle ) { switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = getMachOSubTypeFromArch ( TheTriple . getArchName ( ) ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TheTriple , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) &&


<s> assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> )


<s> bool <ISA_LIT>SLSHardening :: hardenBLRs ( MachineBasicBlock & MBB ) const { if ( ! ST -> hardenSlsBlr ( ) ) return false ; bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MachineBasicBlock :: iterator NextMBBI ; for ( ; MBBI != E ; MBBI = NextMBBI ) { MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( isBLR ( MI ) ) { ConvertBLRToBL ( MBB , MBBI ) ; Modified = true ; } } return Modified


<s> static SDValue performMulVectorExtendCombine ( SDNode * Mul , SelectionDAG & DAG ) { EVT VT = Mul -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = performBuildVectorExtendCombine ( Mul -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue Op1 = performBuildVectorExtendCombine ( Mul -> getOperand ( <NUM_LIT> ) , DAG ) ; if ( ! Op0 && ! Op1 ) return SDValue ( ) ; SDLoc DL ( Mul ) ; return DAG . getNode ( Mul -> getOpcode ( ) , DL , VT , Op0 ? Op0 : Mul -> getOperand (

<NUM_LIT> ) , Op1 ? Op1 : Mul -> getOperand ( <NUM_LIT> ) ) ;


<s> DEBUG ( errs ( ) << <STR_LIT> ; errs ( ) . write_hex ( Word


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EncodeImms = true ; break ; } for ( const MachineOperand & MO : MI -> operands


<s> rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = <NUM_LIT> ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable (


<s> Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) { const Constant * C = <NUM_LIT> ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; SDValue CP = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits


<s> unsigned RegSize = Ty . getSizeInBits ( ) ; bool Is32Bit = ( RegSize == <NUM_LIT> ) ; const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ) { if ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) { auto TstMI = MIRBuilder . buildInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { Ty } , { LHS } ) ; TstMI . addImm ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) ; constrainSelectedInstRegOperands ( * TstMI , TII , TRI , RBI ) ; return & * TstMI ; } } if ( auto Fns = selectLogicalShiftedRegister ( RHS ) ) return emitInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { Ty } , { LHS }


<s> CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) )


<s> } else if ( <STR_LIT> . contains ( BP ) ) { MinGPR = std :: min < unsigned > ( MinGPR , BP ) ; HasGPSaveArea = true ; } } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSAVESaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSaveArea ) { assert ( LowerBound <= <NUM_LIT> && <STR_LIT> ) ; LowerBound &= ~ ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = VRegs . size ( ) ; i != e ; ++ i ) { int FI = VRegs [ i ] . getFrameIdx


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) ,


<s> } Options . setMacro ( ) ; Parser . Lex ( ) ; return false


<s> if ( Subtarget -> isMClass ( ) && Subtarget -> hasDSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV8MBaselineOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV4TOps ( ) ) return <STR_LIT> ; else return


<s> FOREACH_FUNCTION_ARGS ( m_fntype , type , iter ) { if ( type == void_type_node || i >= m_nargs ) break ; if ( i >= m_base_arg && TREE_CODE ( type ) == ENUMERAL_TYPE && ! require_immediate_enum ( i - m_base_arg , type ) ) return false ; i +=


<s> HOST_WIDE_INT size ; size_directive_output = <NUM_LIT> ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream ,


<s> if ( isa < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) && Predicate_simm13 ( Addr . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB64 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef


<s> return InsertSubVector ( Result , Vec , IdxVal , DAG


<s> explicit <ISA_LIT>PagerandoOptimizer ( ) : MachineFunctionPass ( ID


<s> bool <ISA_LIT>TargetLowering :: shouldConvertPhiType ( Type * From , Type * To ) const { if ( ! Subtarget . is64Bit


<s> EVT InScalarVT = InVT . getVectorElementType ( ) ; if ( InScalarVT . getFixedSizeInBits ( ) <= ScalarVT . getFixedSizeInBits ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto IsConstVectorInRange = [ ] ( SDValue V , unsigned Min , unsigned Max ) { return <STR_LIT> ( V , [ Min , Max ] ( ConstantSDNode * C ) { return ! ( C -> getAPIntValue ( ) . ult ( Min ) || C -> getAPIntValue ( ) . ugt ( Max ) ) ; } ) ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; auto AVGSplitter = [ & ] ( SDValue Op0 , SDValue Op1 ) { unsigned NumElemsPow2 = PowerOf2Ceil ( NumElems ) ; EVT Pow2VT = EVT :: getVectorVT ( * DAG . getContext ( ) , ScalarVT , NumElemsPow2 ) ; if ( NumElemsPow2 != NumElems ) { SmallVector < SDValue , <NUM_LIT> > Ops0 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops1 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Idx = DAG . getIntPtrConstant (


<s> bool sparc_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS


<s> NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) return


<s> unsigned Scale = Log2_32 ( SizeInBytes ) ; int64_t ImmOff = ValAndVReg -> Value . getSExtValue ( ) ; if ( ImmOff % SizeInBytes == <NUM_LIT> && ImmOff >= <NUM_LIT> && ImmOff < ( <NUM_LIT> << Scale ) ) return None ; auto isPreferredADD = [ ] ( int64_t ImmOff ) { if ( ( ImmOff & <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ImmOff & <NUM_LIT> ) != <NUM_LIT> ) return false ; return ( ImmOff & <NUM_LIT> ) != <NUM_LIT> && ( ImmOff & <NUM_LIT> ) != <NUM_LIT> ; } ; if ( isPreferredADD ( ImmOff ) || isPreferredADD ( - ImmOff ) )


<s> if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT>


<s> static SDValue LowerF128_FPEXTEND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPEXT_F64_F128 ) , <NUM_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG ,

TLI . getLibcallName ( RTLIB :: FPEXT_F32_F128 ) , <NUM_LIT> ) ;