<s> int shift ; _Unwind_VRS_Get ( context , _UVRSC_CORE , R_SP , _UVRSD_UINT32 , & reg ) ; op = next_unwind_byte ( uws ) ; shift = <NUM_LIT> ; while ( op & <NUM_LIT> ) { reg += ( ( op & <NUM_LIT> ) << shift ) ; shift += <NUM_LIT> ; op = next_unwind_byte ( uws ) ; } reg += ( ( op & <NUM_LIT> ) << shift ) + <NUM_LIT> ; _Unwind_VRS_Set ( context , _UVRSC_CORE , R_SP , _UVRSD_UINT32 , & reg ) ; continue ; } if ( op == <NUM_LIT> ) { op = next_unwind_byte ( uws ) ; op = ( ( op & <NUM_LIT> ) << <NUM_LIT> ) | ( op & <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_VFP , op , _UVRSD_VFPX ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( ( op & <NUM_LIT> ) == <NUM_LIT> ) { op = <NUM_LIT> | ( ( op & <NUM_LIT> ) + <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_FPA , op , _UVRSD_FPAX ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } op = <NUM_LIT> | ( ( op & <NUM_LIT> ) + <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_VFP , op , _UVRSD_VFPX ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( ( op & <NUM_LIT> ) == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { op = next_unwind_byte ( uws ) ; op = ( ( op & <NUM_LIT> ) << <NUM_LIT> ) | ( op & <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_WMMXD , op , _UVRSD_UINT64 ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( op == <NUM_LIT> ) { op = next_unwind_byte ( uws ) ; if ( op == <NUM_LIT> || ( op & <NUM_LIT> ) != <NUM_LIT> ) return _URC_FAILURE ; if ( _Unwind_VRS_Pop ( context , _UVRSC_WMMXC , op , _UVRSD_UINT32 ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( ( op & <NUM_LIT> ) == <NUM_LIT> ) { op = <NUM_LIT> | ( ( op & <NUM_LIT> ) + <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_WMMXD , op , _UVRSD_UINT64 ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( op == <NUM_LIT> ) { op = next_unwind_byte ( uws ) ; op = ( ( op & <NUM_LIT> ) << <NUM_LIT> ) | ( op & <NUM_LIT> ) ; if ( _Unwind_VRS_Pop ( context , _UVRSC_FPA , op , _UVRSD_FPAX ) != _UVRSR_OK ) return _URC_FAILURE ; continue ; } if ( op ==


<s> Size = LastTagStore . Offset - FirstTagStore . Offset + LastTagStore . Size ; DL = TagStores [ <NUM_LIT> ] . MI -> getDebugLoc ( ) ; Register Reg ; FrameRegOffset = TFI -> resolveFrameOffsetReference ( * MF , FirstTagStore . Offset , false , false , Reg , false , true ) ; FrameReg = Reg ; FrameRegUpdate = None ; mergeMemRefs ( TagStores , CombinedMemRefs ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( const auto & Instr : TagStores ) { dbgs ( ) << <STR_LIT> << * Instr . MI ; } ) ; const int kSetTagLoopThreshold = <NUM_LIT> ; if ( Size < kSetTagLoopThreshold ) { if ( TagStores . size ( ) < <NUM_LIT> ) return ; emitUnrolled ( InsertI


<s> const char * <ISA_LIT>GNUInfo :: dyld ( ) const { return m_Triple . isArch32Bit ( )


<s> void <ISA_LIT>StackTagging :: tagAlloca ( AllocaInst * AI , Instruction * InsertBefore , Value * Ptr , uint64_t Size ) { auto SetTagZeroFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; auto StgpFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; InitializerBuilder IB ( Size , DL , Ptr , SetTagFunc ,


<s> if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes ; NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; } MBBI -> setDesc ( ZII -> get ( NewOpcode ) ) ; MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else if ( StackSize ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , StackSize


<s> if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg ,


<s> return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple ::


<s> } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; Register DstRegX = DstMO . getReg ( ) ; Register DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW


<s> EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; assert ( ( NumElems % <NUM_LIT> ) == <NUM_LIT> && ( SizeInBits %


<s> unsigned Opcode = Src . getOpcode ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; auto IsRepeatedOpOrOneUseConstant = [ ] ( SDValue Op0 , SDValue Op1 ) { if ( Op0 == Op1 ) return true ; SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src .


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_store_ps ( float * __P , __m128 __A ) { assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ; vec_st ( ( __v4sf ) __A , <NUM_LIT> , ( __v4sf *


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target ,


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: mips , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mipsel , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mips64 , true > A ( getThe<ISA_LIT>64Target (


<s> return ( __mmask32 ) __builtin_ia32_kandnsi ( ( __mmask32 ) __A , ( __mmask32 )


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; MCAsmParserExtension :: Initialize (


<s> DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) .


<s> if ( ( P == ICmpInst :: ICMP_ULT ) && ( Stride -> getZExtValue


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> static SDValue LowerADD ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) . is256BitVector ( ) && Op . getValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return Lower256IntArith ( Op


<s> HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false


<s> LLVM_FALLTHROUGH ; } case <STR_LIT> : assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } if ( Subtarget . hasVLX ( ) ) if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return BitBlend ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( at


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { if ( TLI . getNumRegistersForCallingConv ( Ctx , CC , SplitEVTs [ i ] ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned CurVReg = VRegs [ i ] ; ArgInfo CurArgInfo = ArgInfo { CurVReg , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) } ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; if ( MRI . getType ( CurVReg ) . getSizeInBits ( ) == <NUM_LIT> ) { CurVReg = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , CurVReg ) . getReg ( <NUM_LIT> ) ; } else { MVT NewVT = TLI . getRegisterTypeForCallingConv ( Ctx , CC , SplitEVTs [ i ] ) ; if ( EVT ( NewVT ) != SplitEVTs [ i ] ) { unsigned ExtendOp = TargetOpcode :: G_ANYEXT ; if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: SExt ) ) ExtendOp = TargetOpcode :: G_SEXT ; else if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: ZExt ) ) ExtendOp = TargetOpcode :: G_ZEXT ; LLT NewLLT ( NewVT ) ; LLT OldLLT ( <STR_LIT> ( CurArgInfo . Ty ) ) ; CurArgInfo . Ty = EVT ( NewVT ) . getTypeForEVT ( Ctx ) ; if ( NewVT . isVector ( ) ) { if ( OldLLT . isVector ( ) ) { if ( NewLLT . getNumElements ( ) > OldLLT . getNumElements ( ) ) { if ( NewLLT . getNumElements ( ) != OldLLT . getNumElements ( ) * <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildMerge ( { NewLLT } , { CurVReg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } else { CurVReg = MIRBuilder . buildInstr ( ExtendOp , { NewLLT } , { CurVReg } ) . getReg ( <NUM_LIT> ) ; } } else if ( NewLLT . getNumElements ( ) == <NUM_LIT> ) { auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildBuildVector ( { NewLLT } , { CurVReg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Ops . push_back ( Chain ) ; Ops . push_back ( Func ) ; Ops . push_back ( SymAddr ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; Glue = Chain . getValue


<s> bool rs6000_is_valid_mask ( rtx mask , int * b , int * e , machine_mode mode ) { unsigned HOST_WIDE_INT val = INTVAL ( mask ) ; unsigned HOST_WIDE_INT bit ; int nb , ne ; int n = GET_MODE_PRECISION ( mode ) ; if ( mode != DImode && mode != SImode ) return false ; if ( INTVAL ( mask ) >= <NUM_LIT> ) { bit = val & - val ; ne = exact_log2 ( bit ) ; nb = exact_log2 ( val + bit ) ; } else if ( val + <NUM_LIT> == <NUM_LIT> ) { nb = n ; ne = <NUM_LIT> ; } else if ( val & <NUM_LIT> ) { val = ~ val ; bit = val & - val ; nb = exact_log2 ( bit ) ; ne = exact_log2 ( val + bit ) ; } else { bit = val & - val ; ne = exact_log2 ( bit ) ; if ( val + bit == <NUM_LIT> ) nb = n ; else nb = <NUM_LIT> ; } nb -- ; if ( nb < <NUM_LIT> || ne < <NUM_LIT> || nb >= n || ne >= n ) return false ; if ( b ) * b = nb ; if ( e ) * e = ne ; return


<s> bool enableMultipleCopyHints ( ) const override { return


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue Vec = Op0 . getOperand ( <NUM_LIT> ) ; for ( auto * U : Vec -> uses ( ) ) { if ( U != Op0 . getNode ( ) && U -> hasOneUse ( ) && U -> getOpcode ( ) == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) == Vec && U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue OtherExtend = SDValue ( * U -> use_begin ( ) , <NUM_LIT> ) ; if ( OtherExtend . getOpcode ( ) == <STR_LIT> && OtherExtend . getOperand ( <NUM_LIT> ) == SDValue ( U , <NUM_LIT> ) && OtherExtend . getValueType ( ) == <STR_LIT> ) { SDValue VExtend = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Vec ) ; DCI . AddToWorklist ( VExtend . getNode ( ) ) ; SDValue Extract1 = DAG . getNode ( <STR_LIT> , SDLoc ( U ) , <STR_LIT> , VExtend , DAG . getConstant

( <NUM_LIT> , SDLoc ( U ) , <STR_LIT> ) ) ;


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF


<s> MCSymbol * StartLabel = OutContext . createTempSymbol ( ) ; MCSymbol * EndLabel = OutContext . createTempSymbol ( ) ; MCSymbol * SethiLabel = OutContext . createTempSymbol ( ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; OutStreamer -> emitLabel ( StartLabel ) ; MCOperand Callee = createPCXCallOP ( EndLabel , OutContext ) ; EmitCall ( * OutStreamer , Callee , STI ) ; OutStreamer -> emitLabel ( SethiLabel ) ; MCOperand hiImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 , GOTLabel , StartLabel , SethiLabel , OutContext ) ; EmitSETHI ( * OutStreamer , hiImm , MCRegOP , STI ) ; OutStreamer -> emitLabel ( EndLabel ) ; MCOperand loImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC10 , GOTLabel , StartLabel , EndLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , loImm , MCRegOP , STI ) ; EmitADD ( * OutStreamer , MCRegOP , RegO7 , MCRegOP , STI


<s> if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( GV -> getAlignment ( ) < <NUM_LIT> && ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , Flags ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { const Constant * C = CP -> getConstVal ( ) ; ImmOpnd = CurDAG -> getTargetConstantPool ( C , <STR_LIT> , CP -> getAlignment ( ) , <NUM_LIT> , Flags ) ; } } if ( FirstOp == <NUM_LIT> ) ( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; else ( void ) CurDAG -> UpdateNodeOperands ( N , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; if ( Base . getNode ( ) -> use_empty ( ) )

CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_cvtepi64_storeu_epi16 ( void *


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask


<s> } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( CS . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallSite NewCS ; if ( CS . isCall ( ) ) { auto * CI = cast < CallInst > ( Inst ) ; CallInst * NewCI = Builder . CreateCall ( SetJmp3


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> EvaluateAsRelocatable ( Res , Layout


<s> return __a * __aarch64_vget_lane_any (


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; int


<s> } if ( csky_selected_cpu ) { if ( csky_selected_arch && ( csky_selected_cpu -> base_arch != csky_selected_arch -> base_arch ) ) warning ( <NUM_LIT> , <STR_LIT> , csky_selected_cpu -> name , csky_selected_arch -> name ) ; if ( ! csky_selected_arch ) csky_selected_arch = & all_architectures [ csky_selected_cpu -> base_arch ] ; csky_initialize_isa ( all_sbits , csky_selected_arch -> isa_bits ) ; target -> core_name = csky_selected_cpu -> name ; } else if ( csky_selected_arch ) { csky_selected_cpu = csky_selected_arch ; target -> arch_name = csky_selected_arch -> name ; } else { csky_selected_cpu = & all_cores [ TARGET_CPU_DEFAULT ] ; csky_selected_arch = & all_architectures [ csky_selected_cpu -> base_arch ] ; csky_initialize_isa ( all_sbits , csky_selected_arch -> isa_bits ) ; target -> core_name = csky_selected_cpu -> name ; } if ( ! csky_selected_tune ) csky_selected_tune = & all_cores [ csky_selected_cpu -> core ] ; gcc_assert ( csky_selected_tune ) ; gcc_assert ( csky_selected_arch ) ; gcc_assert ( csky_selected_cpu ) ; csky_initialize_isa ( target -> isa , csky_selected_cpu


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = l * NumLaneElts ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO


<s> unsigned tgt = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateImm ( tgt ) ) ; return MCDisassembler ::


<s> rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false


<s> return <NUM_LIT> ; case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return <NUM_LIT> - HasFP ; } case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; bool IsPagerando = MF . getFunction


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; } return TargetRegisterInfo :: getPhysicalRegisterRegClass ( Reg , VT


<s> return ( poly16x4_t ) __builtin_aarch64_ld1v4hi ( ( const


<s> return __builtin_ia32_vcvtps2phx512_mask_round ( ( __v16sf ) __A , _mm256_setzero_ph ( ) , ( __mmask16 ) -


<s> } else gcc_unreachable ( ) ; } } else { if ( mode == TImode ) split_double_mode ( mode , & operand , <NUM_LIT> , & parts [ <NUM_LIT> ] , & parts [ <NUM_LIT> ] ) ; if ( mode == XFmode || mode == TFmode ) { machine_mode upper_mode = mode == XFmode ? SImode : DImode ; if ( REG_P ( operand ) ) { gcc_assert ( reload_completed ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operand ) + <NUM_LIT> ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( upper_mode , REGNO ( operand ) + <NUM_LIT> ) ; } else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , DImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; parts [ <NUM_LIT> ] = adjust_address ( operand , upper_mode , <NUM_LIT> ) ; } else if ( GET_CODE ( operand ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , operand ) ; real_to_target ( l , & r , mode ) ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] , l [ <NUM_LIT> ] , DImode ) ; if ( upper_mode == SImode ) parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; else if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] ,


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> Value * <ISA_LIT>IREmitter :: visitVSHRs ( const


<s> bool isMemDisp12Len8 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange ( Mem . Length , <NUM_LIT>


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand (


<s> SDValue <ISA_LIT>TargetLowering :: LowerToBT ( SDValue And , <STR_LIT> CC , DebugLoc dl , SelectionDAG & DAG ) const { SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Mask = APInt :: getAllOnesValue ( BitWidth ) , Zeros , Ones ; DAG . ComputeMaskedBits ( Op0 , Mask , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( Ty ) , Op . getOperand ( <NUM_LIT> ) , Op

. getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> return <NUM_LIT> ; case NE : return <NUM_LIT> ; case GE : case GEU : return <NUM_LIT> ; case GT : case GTU


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVecShiftR32OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand


<s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI .


<s> switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true


<s> SDValue <ISA_LIT>TargetLowering :: lowerFABS ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 ( Op , DAG , Subtarget


<s> return ( __m64 ) __builtin_ia32_pfrcpit1 ( ( __v2sf )


<s> frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ; entry_iterator it , end = m_GOT


<s> return __builtin_aarch64_frint64xsf (


<s> return - <NUM_LIT> ; } case MCExpr :: Unary : return - <NUM_LIT> ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; int64_t LHSVal = EvaluateCRExpr ( BE -> getLHS ( ) ) ; int64_t RHSVal = EvaluateCRExpr ( BE -> getRHS ( ) ) ; int64_t Res ; if ( LHSVal < <NUM_LIT> || RHSVal < <NUM_LIT> ) return - <NUM_LIT> ; switch ( BE -> getOpcode ( ) ) { default : return - <NUM_LIT> ; case MCBinaryExpr :: Add : Res = LHSVal + RHSVal ; break ; case MCBinaryExpr :: Mul : Res = LHSVal * RHSVal ; break ; } return Res < <NUM_LIT> ? - <NUM_LIT> : Res ; } } llvm_unreachable (


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return <STR_LIT> ; assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ; return


<s> bool <ISA_LIT>16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , <STR_LIT> , true ) ; return


<s> return __builtin_arm_stc2 ( __coproc ,


<s> static bool arm_output_ttype ( rtx x ) { fputs ( <STR_LIT> , asm_out_file )


<s> } for ( map = _r_debug . r_map ; map ; map = map -> l_next ) { if ( ! map -> l_name ) continue ; ret = find_fde_for_dso ( ( Elf64_Addr ) pc , map , pseg_base , pgp ) ; if ( ret


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS8 : switch ( Type ) { case RT32_32 : return IsPCRel ? ELF :: R_386_PC32 : ELF :: R_386_32 ; case RT32_16 : return IsPCRel ? ELF :: R_386_PC16 : ELF :: R_386_16 ; case RT32_8 : return IsPCRel ? ELF :: R_386_PC8 : ELF :: R_386_8 ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_GOT : assert ( Type == RT32_32 ) ; if ( IsPCRel ) return ELF :: R_386_GOTPC ; if ( ! Ctx . getAsmInfo ( ) -> canRelaxRelocations ( ) ) return ELF :: R_386_GOT32 ; return Kind == <STR_LIT> ? ELF :: R_386_GOT32X : ELF :: R_386_GOT32 ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr


<s> unsigned CPIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPoolEntry & MCPE = ( * MCPEs ) [ CPIndex ] ; JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ) ; assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ; const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant >


<s> if ( DCI . isBeforeLegalize ( ) || ! Subtarget -> hasNEON ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( N0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = N0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode (


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; if ( isNegative ) RealVal . changeSign ( ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isPosZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; } Parser . Lex (


<s> MachineBasicBlock * NewBlock = Preheader -> getParent ( ) -> CreateMachineBasicBlock ( Preheader -> getBasicBlock ( ) ) ; Preheader -> getParent ( ) -> insert ( ++ Preheader -> getIterator ( ) , NewBlock ) ; Br -> removeFromParent ( ) ; NewBlock -> insert ( NewBlock -> end ( ) , Br ) ; Preheader -> replaceSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) , NewBlock ) ; NewBlock -> addSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * NewBlock , Br , WLS -> getDebugLoc ( ) , TII -> get ( WLS -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MIB . add ( WLS ->


<s> void <ISA_LIT>CodeEmitter :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> <<


<s> for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set_src = SET_SRC ( XVECEXP ( pat , <NUM_LIT> , i ) ) ; if ( GET_CODE ( set_src ) == COMPARE ) compare_set = XVECEXP ( pat , <NUM_LIT> , i ) ; else alu_set = XVECEXP ( pat , <NUM_LIT> , i ) ; } } if ( compare_set == NULL_RTX ) return false ; src = SET_SRC ( compare_set ) ; if ( GET_CODE ( src ) != COMPARE ) return false ; if ( ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) ) return false ; if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; if ( addr ) { ix86_address parts ; int ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( ix86_rip_relative_addr_p ( & parts ) ) return false ; } handle_stack_protect_test : test_if = SET_SRC ( pc_set ( condjmp )


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Subtarget -> is64Bit ( ) ) { SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , DAG . getConstant ( VarArgsGPOffset , <STR_LIT> ) , FIN , SV , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , DAG . getConstant ( VarArgsFPOffset , <STR_LIT> ) , FIN , SV , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , OVFIN , FIN , SV , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue RSFIN = DAG . getFrameIndex ( RegSaveFrameIndex , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , RSFIN , FIN , SV , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps


<s> assert ( std :: is_sorted ( std :: begin ( NEONLdStTable ) , std :: end ( NEONLdStTable ) ) && <STR_LIT> ) ; TableChecked = true ; } auto I = std :: lower_bound ( std :: begin ( NEONLdStTable ) , std :: end


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT . changeVectorElementTypeToInteger (


<s> BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) ; ++


<s> } unsigned Scale = NumElems / NewWidth ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += Scale ) { unsigned StartIdx = ~ <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < Scale ; ++ j ) { SDValue Elt = PermMask . getOperand ( i + j ) ; if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; unsigned EltIdx = cast < ConstantSDNode > ( Elt ) -> getZExtValue ( ) ; if ( StartIdx == ~ <NUM_LIT> ) StartIdx = EltIdx - ( EltIdx % Scale ) ; if ( EltIdx != StartIdx + j ) return SDValue ( ) ; } if ( StartIdx == ~ <NUM_LIT> ) MaskVec . push_back ( DAG . getUNDEF ( MaskEltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( StartIdx / Scale , MaskEltVT


<s> if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy . getSizeInBits ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , ValTy , Shl . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SMPos0 , DL , <STR_LIT> ) , DAG . getConstant ( SMSize0 , DL , <STR_LIT> ) , And0 . getOperand ( <NUM_LIT> ) ) ; } else { if ( ~ CN -> getSExtValue ( ) == ( ( ( ( int64_t ) <NUM_LIT> << SMSize0 ) - <NUM_LIT> ) << SMPos0 ) && ( ( SMSize0 + SMPos0 <=

<NUM_LIT> && Subtarget . has<ISA_LIT>64r2 ( ) ) || ( SMSize0 + SMPos0 <= <NUM_LIT> ) ) ) {


<s> const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT>


<s> const char * Symbol = getRetpolineSymbol ( Subtarget , AvailableReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , AvailableReg ) . addReg ( CalleeVReg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToES ( Symbol ) ; MI . setDesc ( TII -> get ( Opc ) ) ; MachineInstrBuilder ( * BB -> getParent ( ) , & MI ) . addReg ( AvailableReg ,

RegState :: Implicit | RegState :: Kill ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSegAlloca ( MachineInstr * MI , MachineBasicBlock * BB , bool Is64Bit ) const { const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; assert ( EnableSegmentedStacks ) ; unsigned TlsReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TlsOffset = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineBasicBlock * mallocMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * bumpMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * continueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * AddrRegClass = getRegClassFor ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned mallocPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , bumpSPPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , tmpSPVReg = MRI . createVirtualRegister ( AddrRegClass ) , sizeVReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , physSPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineFunction :: iterator MBBIter = BB ; ++ MBBIter ; MF -> insert ( MBBIter , bumpMBB ) ; MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , tmpSPVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( tmpSPVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( tmpSPVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( tmpSPVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ,


<s> if ( HasBaseReg ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! HasBaseReg ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ; else { O <<


<s> StackOffset <ISA_LIT>FrameLowering :: resolveFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg , bool PreferFP , bool ForSimm ) const { const auto & MFI = MF . getFrameInfo ( ) ; int ObjectOffset = MFI . getObjectOffset ( FI ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , FrameReg , PreferFP ,


<s> FILE * f ; int i ; if ( argc < <NUM_LIT> ) return NULL ; if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; kc = kstat_open ( ) ; if ( kc != NULL ) { ksp = kstat_lookup ( kc , CONST_CAST2 ( char * , const char * , <STR_LIT> ) , - <NUM_LIT> , NULL ) ; if ( ksp != NULL && kstat_read ( kc , ksp , NULL ) != - <NUM_LIT> && ksp -> ks_type == KSTAT_TYPE_NAMED ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , <STR_LIT> ) ) ; if ( brand == NULL ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , <STR_LIT> ) ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_STRING ) buf = KSTAT_NAMED_STR_PTR ( brand ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_CHAR ) buf = brand -> value . c ; } kstat_close ( kc ) ; for ( i = <NUM_LIT> ; cpu_names [ i ] . name != NULL ; i ++ ) if ( strcmp ( buf , cpu_names [ i ] . name ) == <NUM_LIT> ) cpu = cpu_names [ i ] . cpu ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) return NULL ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { for ( i = <NUM_LIT> ; cpu_names [ i ] . name ; i ++ ) if ( strstr ( buf , cpu_names [ i ] . name ) != NULL ) { cpu = cpu_names [ i ] . cpu ; break ; } break ; } fclose ( f )


<s> while ( next ( I ) != MBB . end ( ) ) next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB


<s> SDValue <ISA_LIT>TargetLowering :: lowerLog ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , Op ,


<s> static enum aarch_parse_opt_result aarch_handle_pac_ret_protection ( char * str ATTRIBUTE_UNUSED , char * rest ATTRIBUTE_UNUSED ) { aarch_ra_sign_scope = AARCH_FUNCTION_NON_LEAF ; aarch_ra_sign_key =


<s> SDValue <ISA_LIT>SETargetLowering :: lowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { LoadSDNode & Nd = * cast < LoadSDNode > ( Op ) ; if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerLOAD ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ; if ( ! Subtarget -> isLittle ( ) ) std


<s> UseOp = MI . findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI . getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> .


<s> const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { OperandMatchResultTy ResTy = MatchAnyRegisterNameWithoutDollar ( Operands , DefSymbol . substr ( <NUM_LIT> ) , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; return true ; } else if ( ResTy == MatchOperand_ParseFail ) llvm_unreachable ( <STR_LIT> ) ; return false ; } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) { Parser . Lex ( ) ; const MCConstantExpr * Const = static_cast < const MCConstantExpr * > ( Expr ) ; Operands . push_back ( <STR_LIT> ( Const , S , Parser . getTok ( ) . getLoc ( ) , * this ) ) ; return true ; } } return false


<s> static bool isSignExtended ( SDNode * N , SelectionDAG & DAG ) { return N -> getOpcode ( ) == <STR_LIT> || isExtendedBUILD_VECTOR ( N ,


<s> UP . UpperBound = true ; if ( ! ST -> isMClass ( ) ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP ) ; UP . OptSizeThreshold = <NUM_LIT> ; UP . PartialOptSizeThreshold = <NUM_LIT> ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost


<s> bool <ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool No<ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( <ISA_LIT>16Attr && No<ISA_LIT>16Attr ) && <STR_LIT> ) ; if ( <ISA_LIT>16Attr ) Subtarget = & <ISA_LIT>16Subtarget ; else if ( No<ISA_LIT>16Attr ) Subtarget = & No<ISA_LIT>16Subtarget ; else Subtarget =


<s> static const uint8_t Nops [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) <NUM_LIT> ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count !=


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> bool <ISA_LIT>TargetMachine :: addInstSelector (


<s> return decodeRegisterClass ( Inst , RegNo , RRegs


<s> void <ISA_LIT>ConstantIslands :: JumpTableFunctionScan ( MachineFunction & MF ) { for ( MachineFunction :: iterator MBBI = MF . begin ( ) , E = MF . end ( ) ; MBBI != E ;


<s> Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler


<s> } return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant


<s> bool <ISA_LIT>MCInstLower :: lowerLongBranch ( const MachineInstr * MI , MCInst & OutMI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT>


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MI -> getOperand ( OpNum ) . getImm ( ) *


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand MMO ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , MFI . getObjectOffset ( FI ) + Offset , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI )


<s> MCOperand RegPLT = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , AddrSym , OutContext ) ; emitLEAzii ( * OutStreamer , cim24 , loImm , MCRegOP , STI ) ; MCOperand M032 = MCOperand :: createImm ( M0 ( <NUM_LIT> ) ) ; emitANDrm ( * OutStreamer , MCRegOP , M032 , MCRegOP , STI ) ; emitSIC ( * OutStreamer , RegPLT , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_HI32 , AddrSym , OutContext ) ; emitLEASLrri ( * OutStreamer , MCRegOP , RegPLT


<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ! TARGET_USE_GATHER ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= <NUM_LIT> || scale > <NUM_LIT> || ( scale & ( scale - <NUM_LIT> ) ) != <NUM_LIT> ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI


<s> if ( ! tree_fits_uhwi_p ( arg ) || ( elt = tree_to_uhwi ( arg ) , elt > max ) ) { error ( <STR_LIT> ,


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx =


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64Bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameInfo ( * this , is64Bit ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , MachOWriterInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isDarwin ( ) )

setRelocationModel ( Reloc :: DynamicNoPIC ) ;


<s> SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok . getString ( ) ; <STR_LIT> CC = parseCondCodeString ( Cond ) ; if ( CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , std :: max ( <NUM_LIT> , TotalArgRegsSaveSize ) ) ; AFI -> setVarArgsFrameIndex ( FrameIndex


<s> void printf512mem ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> addr |= Rn << <NUM_LIT> ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm8 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> static void check_enabling ( void ) \ { \ extern long sysconf ( int ) ; \ \ int prot = ( int ) sysconf ( <NUM_LIT> ) ; \ if ( prot != <NUM_LIT> ) \ need_enable_exec_stack


<s> SelectRoot ( * CurDAG ) ; DOUT ( llvm :: dbgs ( )


<s> CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn (


<s> void <ISA_LIT>AsmParser :: cvtLdWriteBackRegAddrMode3 ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


__artificial__ ) ) _mm512_stream_load_si512 ( void * __P ) {


<s> OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; OutStreamer -> EmitThumbFunc


<s> unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addReg ( TempReg ) ; break ; } case CmpInst :: ICMP_UGT : emitInst ( <STR_LIT> , ResultReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; break ; case CmpInst :: ICMP_ULT : emitInst ( <STR_LIT> , ResultReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; break ; case CmpInst :: ICMP_UGE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_ULE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_SGT : emitInst ( <STR_LIT> , ResultReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; break ; case CmpInst :: ICMP_SLT : emitInst ( <STR_LIT> , ResultReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; break ; case CmpInst :: ICMP_SGE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_SLE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: FCMP_OEQ : case CmpInst :: FCMP_UNE : case CmpInst :: FCMP_OLT


<s> break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src

) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrFI ( SDValue Addr , SDValue & Base ) const { llvm_unreachable ( <STR_LIT> ) ; return false


<s> unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; unsigned SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcOddReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestOddReg ) ; Offset += <NUM_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i64scatter_ps ( void * addr , __m512i index , int scale , int hint ) { __builtin_ia32_scatterpfqps ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , ( int


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , CCValAssign :: LocInfo LocInfo , CCState & State ) { Register Reg = State . AllocateReg ( ArgGPRs ) ; if (


<s> bool IsV2Zero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( ! IsV1Zero && ! IsV2Zero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } int MaskLO = WidenedMask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : WidenedMask [ <NUM_LIT> ] ; int MaskHI = WidenedMask [ <NUM_LIT> ] < <NUM_LIT> ?


<s> return ( ( AM5Opc >> <NUM_LIT> ) & <NUM_LIT> ) ? sub :


<s> MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant ( <NUM_LIT> , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , xFGETSIGN , DAG . getConstant


<s> void onIdentifierExpr ( const MCExpr * SymRef , StringRef SymRefName ) { PrevState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_PLUS : case IES_MINUS : State = IES_INTEGER ; Sym = SymRef


<s> while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , DL , NumBytes , true ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaOffset ( nullptr , - CSSize - SlotSize ) ) ; } -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { MBBI =


<s> return static_cast < <ISA_LIT>ELFStreamer &


<s> static SDValue getAtomicLoadArithTargetConstant ( SelectionDAG * CurDAG , SDLoc dl , enum AtomicOpc & Op , MVT NVT , SDValue Val , const <ISA_LIT>Subtarget * Subtarget ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Val ) ) { int64_t CNVal = CN -> getSExtValue ( ) ; if ( ( int32_t ) CNVal != CNVal ) return Val ; if ( CNVal == INT32_MIN ) return CurDAG -> getTargetConstant ( CNVal , dl , NVT ) ; if ( Op == ADD ) { if ( ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) && ! Subtarget -> slowIncDec ( ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal , dl , NVT ) ; } if ( Op == ADD && Val . hasOneUse ( ) ) { if ( Val . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; return Val . getOperand ( <NUM_LIT> ) ; } if ( Val . getOpcode ( ) == <STR_LIT> && NVT == <STR_LIT> && Val . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; Val = Val . getOperand ( <NUM_LIT> ) ; return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , NVT , Val . getOperand ( <NUM_LIT> ) ) ; } } return Val


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target , create<ISA_LIT>ElfRelocation ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>Target


<s> unsigned <ISA_LIT>RegisterInfo :: getPICCallReg ( void ) { return <STR_LIT>


<s> } else if ( isa < StoreInst > ( SingleUser ) ) return getLoadStoreAddrMode ( HasVector , I -> getType ( ) ) ; } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa <


<s> MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR =


<s> case PRE_DEC : case POST_INC : return false ; case PLUS : { rtx base , index ; base = XEXP ( mem , <NUM_LIT> ) ; index = XEXP ( mem , <NUM_LIT> ) ; if ( ! RX_REG_P ( base ) || ! CONST_INT_P


<s> FunctionPass * llvm :: createCheriInvalidatePass ( ) { return new CheriInvalidatePass


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_VECTORS && VECTOR_MODE_P ( mode ) ) return <NUM_LIT> ; return GET_MODE_BITSIZE ( mode )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodePUNPCKLMask ( VT , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeUNPCKLPMask ( VT , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( NumElems , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned OpNum = ( Index == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return getShuffleScalarElt ( V . getOperand ( OpNum ) . getNode ( ) , Index , DAG , Depth + <NUM_LIT> ) ; } case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPSMask ( <NUM_LIT> , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPSMask ( <NUM_LIT> , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPDMask ( <NUM_LIT> , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPDMask ( <NUM_LIT> , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERM2F128Mask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( )


<s> RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets

[ SpillOffsetTable [ I ] . Reg ] = SpillOffsetTable [ I ] . Offset ;


<s> void setArgumentStackToRestore ( unsigned v ) { ArgumentStackToRestore =


<s> rtx op1 = operands [ <NUM_LIT> ] ; return mep_expand_setcc_1 ( code , dest , op0 ,


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( )


<s> Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( ( Addr . Offset & <NUM_LIT> ) != <NUM_LIT> ) ) UseOffset = false ; break ; case <STR_LIT> : Opc = <STR_LIT> ; assert ( UseRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addImm ( Addr .

Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ;


<s> assert ( DOPTable . count ( MI . getOpcode ( ) ) && <STR_LIT> ) ; return DOPTable [ MI . getOpcode (


<s> return ( __m128d ) __builtin_ia32_vfmaddpd ( ( __v2df ) __A , ( __v2df )


<s> bool isU8ImmX8 ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && ( getImm (


<s> if ( MO . isImm ( ) ) return ( MO . getImm ( ) >> shift ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; return


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue


<s> for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( *


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT )


<s> static inline uint32_t helper_reencode_add_imm ( uint32_t pInst , uint32_t pImm ) { return ( pInst & ~ ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) ) | ( ( pImm & get_mask ( <NUM_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , Is<ISA_LIT>64 ( is64Bit ) , TargetTriple ( TT ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU ,


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> return ( int32_t ) __builtin_aarch64_sqrshrn_ndi ( __a ,


<s> FINI_SECTION_FUNCTION void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP ) ; \ in_section =


<s> const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> )


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) SavedRegs .


<s> SmallPtrSet < Instruction * , <NUM_LIT> > AllAdds ; if ( ! RecordMemoryOps ( & BB ) ) continue ; for ( Instruction & I : reverse ( BB ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , & BB , R ) ) continue ; R . InsertMuls


<s> StringRef getPassName ( ) const override { return


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter *


<s> int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E &&


<s> static DecodeStatus DecodeCOP2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto * Arg0 = dyn_cast < CastInst > ( Args [ <NUM_LIT> ] ) ; if ( Opcode == Instruction :: Mul && ( ! Arg0 || Arg0 -> getOpcode ( ) != Extend -> getOpcode ( ) || Arg0 -> getOperand ( <NUM_LIT> ) -> getType ( ) != Extend -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return false ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; auto * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits (


<s> static bool isVEXTMask ( const SmallVectorImpl < int > & M , EVT VT , bool & ReverseVEXT , unsigned & Imm ) { unsigned NumElts = VT . getVectorNumElements ( ) ; ReverseVEXT = false ; Imm = M [ <NUM_LIT> ] ; unsigned ExpectedElt = Imm ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { ExpectedElt += <NUM_LIT> ; if ( ExpectedElt == NumElts * <NUM_LIT>


<s> unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDValue Src = Op . getOperand ( OpNo ) ; SDValue Chain = IsStrict ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SDValue R = lowerFPToIntToFP ( Op , DAG , Subtarget ) ) return R ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) return lowerINT_TO_FP_vXi64 ( Op , DAG , Subtarget ) ; return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT>


<s> unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; if ( ( AI -> getOperation ( ) == AtomicRMWInst :: And ) || ( AI -> getOperation ( ) == AtomicRMWInst :: Sub ) ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < <NUM_LIT> ) ? AtomicExpansionKind :: None


<s> if ( ST -> hasAVX ( ) ) { int Idx = FindInTable ( AVX1CostTable , array_lengthof ( AVX1CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; } return TargetTransformInfo :: getArithmeticInstrCost (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_i32scatter_ps ( float *


<s> Instruction * <ISA_LIT>ParallelDSP :: CreateSMLADCall ( LoadInst * VecLd0 , LoadInst * VecLd1 , Instruction * Acc , Instruction * InsertAfter ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; VecLd0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; VecLd1 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CreateLoadIns ( Builder , Acc , & VecLd0 ) ; CreateLoadIns ( Builder , Acc , & VecLd1 ) ; Value * Args [ ] = { VecLd0 , VecLd1 , Acc } ; Function * SMLAD = <STR_LIT> ( M


<s> Register ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; int64_t Imm = UseSExt ? CI -> getSExtValue ( )


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstrAndDebugLoc ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( { NewTy } , { ValReg } ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MMO ) ; }


<s> if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return ( code == CONST_INT && INTVAL ( index ) < CSKY_LD16_MAX_OFFSET ( SImode )

&& INTVAL ( index ) >= <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> bool Absolute = true ; if ( Inst . getOperand ( AddrOp ) . isExpr ( ) ) { const MCExpr * MCE = Inst . getOperand ( AddrOp ) . getExpr ( ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( MCE ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) Absolute = false ; } if ( Absolute && ( Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return ; MCOperand Saved = Inst . getOperand ( AddrOp ) ; MCOperand Seg = Inst . getOperand ( AddrBase + <NUM_LIT> ) ; Inst = MCInst


<s> unsigned <ISA_LIT>16SPAliasReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> get<ISA_LIT>16SPAliasReg (


<s> static bool isConsecutiveLS ( LSBaseSDNode * LS , LSBaseSDNode * Base , unsigned Bytes , int Dist , SelectionDAG & DAG ) { EVT VT = LS -> getMemoryVT ( ) ; if ( VT . getSizeInBits ( ) / <NUM_LIT> != Bytes ) return false ; SDValue Loc = LS -> getBasePtr ( ) ; SDValue BaseLoc = Base -> getBasePtr ( ) ; if ( Loc . getOpcode ( ) == <STR_LIT> ) { if ( BaseLoc . getOpcode ( ) != <STR_LIT> ) return false ; const MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = cast < FrameIndexSDNode > ( Loc ) -> getIndex ( ) ; int BFI = cast < FrameIndexSDNode > ( BaseLoc ) -> getIndex ( ) ; int FS = MFI -> getObjectSize ( FI ) ; int BFS = MFI -> getObjectSize ( BFI ) ; if ( FS != BFS || FS != ( int ) Bytes ) return false ; return MFI -> getObjectOffset ( FI ) == ( MFI -> getObjectOffset ( BFI ) + Dist * Bytes ) ; } if ( DAG . isBaseWithConstantOffset ( Loc ) && Loc . getOperand ( <NUM_LIT> ) == BaseLoc && cast < ConstantSDNode > ( Loc . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) == Dist * Bytes ) return true ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; const GlobalValue * GV1 = NULL ; const GlobalValue * GV2 = NULL ; int64_t Offset1 = <NUM_LIT> ; int64_t Offset2 = <NUM_LIT> ; bool isGA1 = TLI . isGAPlusOffset ( Loc . getNode ( ) , GV1 , Offset1 ) ; bool isGA2 = TLI . isGAPlusOffset ( BaseLoc . getNode ( ) , GV2 , Offset2 ) ; if ( isGA1 && isGA2 && GV1 == GV2 ) return Offset1 == (


<s> return ( __m128i ) __builtin_ia32_pmovusdb512_mask ( ( __v16si ) __A , ( __v16qi ) _mm_undefined_si128 ( )


<s> static bool areAdjacentMasksSequential ( ArrayRef < int > Mask ) { for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) if ( Mask [ i ] + <NUM_LIT>

!= Mask [ i + <NUM_LIT> ] ) return false ;


<s> if ( LHS == InnerRHS && RHS == InnerLHS ) InnerSwapped = true ; else if ( LHS != InnerLHS || RHS != InnerRHS ) return false ; switch ( CC ) { case <STR_LIT> : if ( ! InnerIsSel ) return false ; if ( InnerCC != <STR_LIT> && InnerCC != <STR_LIT> ) return false ; NeedSwapOps = ( InnerCC == <STR_LIT> ) ? InnerSwapped : ! InnerSwapped ; break ; case <STR_LIT> : if ( ! IsUnCmp && InnerCC != <STR_LIT> ) return false ; IsUnCmp = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( InnerCC == <STR_LIT> || ( InnerCC == <STR_LIT> && ! InnerSwapped ) || ( InnerCC == <STR_LIT> && InnerSwapped ) ) NeedSwapOps = ( TrueResVal == <NUM_LIT> ) ; else return false ; break ; case <STR_LIT> : if ( ! IsUnCmp && InnerCC != <STR_LIT> ) return false ; IsUnCmp = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( InnerCC == <STR_LIT> || ( InnerCC == <STR_LIT> && ! InnerSwapped ) || ( InnerCC == <STR_LIT> && InnerSwapped ) ) NeedSwapOps = ( TrueResVal == - <NUM_LIT> ) ; else return false ; break ; default : return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( ) ) ; return true


<s> PostGenericScheduler :: initialize ( Dag


<s> static SDValue LowerSIGN_EXTEND_Mask ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VTElt = VT . getVectorElementType ( ) ; SDLoc dl ( Op ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ExtVT = VT ; if ( ! Subtarget . hasBWI ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ExtVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits ( ) ; InVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; In = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getUNDEF ( InVT ) , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; WideVT = <STR_LIT> ( ExtVT . getVectorElementType ( ) , NumElts ) ; } SDValue V ; MVT WideEltVT = WideVT . getVectorElementType (


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; TD = getDataLayout ( ) ; resetOperationActions ( )


<s> assert ( std :: prev ( MBBI ) -> isTerminator ( ) && <STR_LIT> ) ; const TargetInstrInfo * TII = ST -> getInstrInfo ( ) ; assert ( ST -> hasDataBarrier ( ) || ST -> hasSB ( ) ) ; bool ProduceSB = ST -> hasSB ( ) && ! AlwaysUseISBDSB ; unsigned BarrierOpc = ProduceSB ? ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( MBBI == MBB . end ( ) || ! isSpeculationBarrierEndBBOpcode ( MBBI -> getOpcode ( )

) ) BuildMI ( MBB , MBBI , DL , TII -> get ( BarrierOpc ) ) ;


<s> static bool pa_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) != GET_MODE_CLASS ( mode2 ) ) return false ; return


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; isPositionIndependentOrROPI = STI -> getTargetLowering ( ) -> isPositionIndependent ( ) || STI -> isROPI ( ) ; AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureLogAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange


<s> const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL ,


<s> return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; default : return


<s> if ( Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI , & RI ) ) return true ; return


<s> return __builtin_aarch64_lfloorudfdi (


<s> EVT VT = Op0 . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumActiveLanes = NumElts ; assert ( ( NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> ) && <STR_LIT> ) ; while ( NumActiveLanes > <NUM_LIT> ) { unsigned RevOpcode = NumActiveLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Rev = DAG . getNode ( RevOpcode , dl , VT , Op0 ) ; Op0 = DAG . getNode ( BaseOpcode , dl , VT , Op0 , Rev ) ; NumActiveLanes /= <NUM_LIT> ; } SDValue Res ; if ( NumActiveLanes == <NUM_LIT> ) { SDValue Ext0 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext3 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant