<s> vshrn_n_u16 ( uint16x8_t __a , const int __b ) { return ( uint8x8_t ) __builtin_neon_vshrn_nv8hi ( (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg (


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT>


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , bool


<s> MachineBasicBlock :: iterator MBI = searchBackwards ( p , I , MFI ) ; if ( MBI != MachineBasicBlock :: iterator ( ) ) { MachineInstr * NewMI = postRAConvertToLEA ( MFI , MBI ) ; if ( NewMI ) { ++ NumLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; MBI -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MFI -> erase ( MBI ) ; MachineBasicBlock :: iterator J = static_cast < MachineBasicBlock


<s> const MCExpr * RHS = BE -> getRHS ( ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) std :: swap ( LHS , RHS ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef || RHS -> getKind ( ) != MCExpr :: Constant ) llvm_unreachable ( <STR_LIT> ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( LHS ) ; ( void ) SRE ; assert ( isInt < <NUM_LIT> > ( cast < MCConstantExpr > ( RHS ) -> getValue ( ) ) && <STR_LIT> ) ; assert ( ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ) && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast


<s> return __builtin_mve_vmulq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> if ( RegisterVT != <STR_LIT> ) return NumRegisters ; } if ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) return <NUM_LIT> ; if ( ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) { if ( VT == <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) return <NUM_LIT> ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC ,


<s> if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDef = ( isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode ,


<s> __builtin_arm_set_fpscr_nzcvqc ( ( __builtin_arm_get_fpscr_nzcvqc ( ) & ~ <NUM_LIT> ) | ( * __carry


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode )


<s> rtx_insn * insns = get_insns ( ) ; compute_bb_for_insn ( ) ; df_analyze ( ) ; shorten_branches ( get_insns


<s> } else { MIB . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) ; } MIB . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; return MIB . getInstr


<s> case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit )


<s> SDValue getExtractVEXTRACTImmediate ( SDNode * N , unsigned VecWidth , const SDLoc & DL ) { assert ( ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) && <STR_LIT> ) ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; unsigned NumElemsPerChunk = VecWidth / VecVT . getScalarSizeInBits ( ) ; return getI8Imm ( Index / NumElemsPerChunk , DL


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode (


<s> OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; } OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>PagerandoOptimizerPass ( ) { return new <ISA_LIT>PagerandoOptimizer (


<s> assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask (


<s> if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; auto * ShiftC = dyn_cast < ConstantSDNode > ( N1 ) ; auto * AndC = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftC || ! AndC ) return SDValue ( ) ; APInt MaskVal = AndC -> getAPIntValue ( ) ; APInt NewMaskVal = MaskVal . lshr ( ShiftC -> getAPIntValue ( ) ) ; unsigned OldMaskSize = MaskVal . getMinSignedBits ( ) ; unsigned NewMaskSize = NewMaskVal . getMinSignedBits ( ) ; if ( ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) || ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) ) { SDLoc DL (


<s> bool <ISA_LIT>GNULDBackend :: finalizeTargetSymbols ( ) { return true


<s> unsigned Size = STI . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return ATReg


<s> return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case


<s> bool <ISA_LIT>CodeGenPrepare :: isNarrowInstSupported ( Instruction * I ) { if ( ! ST -> hasDSP ( ) || ! EnableDSP || ! isSupportedType ( I ) ) return false ; if ( ST -> isThumb ( ) && ! ST -> hasThumb2 ( ) ) return false ; if ( I -> getOpcode ( ) != Instruction :: Add && I -> getOpcode ( ) != Instruction :: Sub


<s> rtx arm_stack_protect_tls_canary_mem ( bool reload ) { rtx tp = gen_reg_rtx ( SImode ) ; if ( reload ) emit_insn ( gen_reload_tp_hard ( tp ) ) ; else emit_insn ( gen_load_tp_hard ( tp ) ) ; rtx reg = gen_reg_rtx


<s> tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST


<s> if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; else if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT> ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [


<s> static void setRequiredFeatureString ( FeatureBitset FBS , std :: string & Str ) { if ( FBS [ <STR_LIT> ]


<s> std :: unique_ptr < MCObjectTargetWriter

> create<ISA_LIT>WinCOFFObjectWriter ( ) {


<s> <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = shouldGuaranteeTCO ( CallConv , DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> && VA . getValVT ( ) . getSizeInBits ( ) != VA . getLocVT ( ) . getSizeInBits ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI . setObjectOffset ( FI


<s> do { insn = PREV_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( mep_use_post_modify_for_set_p ( PATTERN ( insn ) , reg , offset ) ) { mep_make_parallel ( insn , set_insn


<s> auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpVT , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( NegAddend , SDLoc ( CmpRHS ) , CmpVT ) , AN -> getMemOperand ( ) ) ; auto LockOp = lowerAtomicArithWithLOCK ( AtomicSub , DAG , Subtarget ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , DAG . getUNDEF ( CmpVT ) ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , LockOp . getValue ( <NUM_LIT> ) ) ; return LockOp ; } if ( ! Comparison . isNullValue ( ) ) return SDValue ( ) ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else return SDValue ( ) ; SDValue LockOp = lowerAtomicArithWithLOCK ( CmpLHS , DAG , Subtarget ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , DAG . getUNDEF ( CmpVT ) ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , LockOp . getValue ( <NUM_LIT> ) ) ; return


<s> if ( Disp . isExpr ( ) ) { if ( Base . getReg ( ) ) O << <STR_LIT> ; O << * Disp . getExpr ( ) ; } else { assert ( Disp . isImm ( ) && <STR_LIT> ) ; if ( Base . getReg ( ) ) { if ( Disp . getImm ( ) != <NUM_LIT> ) { O << <STR_LIT> ; O << <STR_LIT> ; O . write_hex ( Disp . getImm ( ) & <NUM_LIT> ) ; } } else


<s> DebugLoc DL = Op . getDebugLoc ( ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode >


<s> Value * <ISA_LIT>InstrSema :: translatePop ( unsigned OpSize ) { Value * OldSP = getReg ( <STR_LIT> ) ; Type * OpTy = IntegerType :: get ( * Ctx , OpSize * <NUM_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( * Ctx , OldSP -> getType

( ) -> getIntegerBitWidth ( ) ) , OpSize ) ;


<s> bool isMemDisp20 ( RegisterKind RegKind , bool


<s> } for ( MachineFunction :: iterator MBI = MF . begin ( ) ; MBI != MF . end ( ) ; MBI ++ ) { MachineBasicBlock * MBB = MBI ; MachineBasicBlock :: iterator I = MBI -> end ( ) ; if ( I == MBB -> begin ( ) ) continue ; I -- ; MachineInstr * LastInst = I ; if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * Target = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB2OrderMap [ Target ] == BB2OrderMap [ MBB ] +


<s> OperandMatchResultTy parseADDR64 ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_compresssi256_mask ( ( __v8si ) __A , ( __v8si )


<s> AssemblerDialect = AsmWriterFlavor ; GlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AlignDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; ZeroDirectiveSuffix = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <NUM_LIT> ; Data8bitsDirective =


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ] [ regno


<s> EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( ) , <NUM_LIT> ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , dl , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , dl , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , NewPtr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , NewAlign , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; return ; } llvm_unreachable ( <STR_LIT>


<s> return ( uint8x16_t ) __builtin_mve_vcaddq_rot270v16qi ( ( int8x16_t ) __a , (


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler (


<s> dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; } )


<s> bool FPMover :: runOnMachineFunction ( MachineFunction & F ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) )


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> GetInstSizeInBytes ( * I ) ; } return Offset


<s> builder . quick_push ( build_all_ones_cst ( bool_type ) ) ; for ( unsigned int i = <NUM_LIT> ; i < element_bytes ; ++ i ) builder . quick_push ( build_zero_cst ( bool_type ) ) ; return gimple_build_assign ( lhs , builder . build (


<s> void printf64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; bool SeenZero = false ; if ( canChangeToInt ( LHS , SeenZero , Subtarget ) && canChangeToInt ( RHS , SeenZero , Subtarget ) && ( SeenZero || ( DAG . isKnownNeverNaN ( LHS ) && DAG . isKnownNeverNaN ( RHS ) ) ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = bitcastf32Toi32 ( LHS , DAG ) ; RHS = bitcastf32Toi32 ( RHS , DAG ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , <ISA_LIT>cc , LHS1 , LHS2 , RHS1 , RHS2 , Dest } ; return DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; } return SDValue (


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; SDValue Sign = DAG . getConstant ( APInt :: getSignedMinValue ( <NUM_LIT> ) , DL , VT ) ; N0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Sign ) ; N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 , Sign ) ; Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Result = DAG . getNode ( Opcode , DL , VT , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Result , Sign ) ; } <STR_LIT> CC ; switch ( Opcode ) { case <STR_LIT> : CC = <STR_LIT> :: SETLT ; break ; case <STR_LIT> : CC =


<s> bool <ISA_LIT>TargetLowering :: needsCmpXchgNb ( const Type * MemType ) const { const <ISA_LIT>Subtarget & Subtarget = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget


<s> if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true ; } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this )


<s> if ( strncmp ( <STR_LIT> , str , <NUM_LIT> ) == <NUM_LIT> ) { isa_flags = <NUM_LIT> ; str += <NUM_LIT> ; } parse_res = aarch64_parse_extension ( str , & isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { aarch64_isa_flags = isa_flags ; return true ; } switch (


<s> return ( __m128i ) vec_or ( ( __v2di )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( )


<s> if ( INSN_ADDRESSES_SET_P ( ) ) return INSN_ADDRESSES ( INSN_UID ( lab ) ) > INSN_ADDRESSES ( INSN_UID ( insn ) ) ; while ( insn ) { if ( insn ==


<s> else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( MF ) ) ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( ) << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask ) ; O << <STR_LIT>

<< <ISA_LIT>FI -> getFPUTopSavedRegOff ( ) << '\n' ;


<s> while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( )


<s> machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case E_DFmode : gen_copysign =


<s> bool <ISA_LIT>BaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == <NUM_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + <STR_LIT> + Twine ( stackSize ) +

<STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ;


<s> return std :: string ( <STR_LIT> ) + ( IsWrite ? <STR_LIT> : <STR_LIT> )


<s> unsigned getFGR64Reg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_FGR ) && <STR_LIT> ) ; return RegIdx . RegInfo -> getRegClass ( <STR_LIT> ) .


<s> assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; unsigned Op = <NUM_LIT> ; unsigned VR = <NUM_LIT> ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( UseImmLabel ) { Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { const TargetRegisterClass * TRC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; VR = MRI -> createVirtualRegister ( TRC ) ; Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB ) . addReg ( <NUM_LIT> ) ; else BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB , Subtarget . classifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( Op ) ) ; addFrameReference ( MIB , FI , <NUM_LIT> ) ; if ( UseImmLabel ) MIB


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << * getSymbol (


<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 .


<s> printAMIndexedWB ( MI , OpNum , BitWidth / <NUM_LIT>


<s> if ( ! isNonZeroElementsInOrder ( Zeroable , Mask , V1 . getValueType ( ) , IsLeftZeroSide ) ) return SDValue ( ) ; unsigned VEXPANDMask = ( ~ Zeroable ) . getZExtValue ( ) ; MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ||


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred )


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE (


<s> label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns


<s> static bool isi32Store ( unsigned Opc ) { return Opc == <STR_LIT> || isT1i32Store ( Opc ) || isT2i32Store (


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty


<s> ix86_option_override_internal ( true , & global_options ,


<s> Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; } assert ( Opc


<s> case Match_InvalidUImm ## nbits : \ return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> ) ; case Match_InvalidSImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> , \ <STR_LIT> ) ; case Match_InvalidUImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> , \ <STR_LIT> ) ; CASE_MATCH_INVALID_UIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_SIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_UIMM_LSB0 ( <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm10 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> __builtin_neon_vst1_lanev2si ( ( __builtin_neon_si * ) __a , ( int32x2_t )


<s> OS << '$' << StringRef ( getRegisterName (


<s> if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } else { unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg


<s> initializeAnnotationsInferencePass ( * PassRegistry :: getPassRegistry


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF


<s> AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr =


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { int Offset = <NUM_LIT>


<s> return ( long long ) __builtin_ia32_vcvttsd2si64 ( ( __v2df ) __A


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel (


<s> return Create ( VK_AARCH64_TPREL_G0_NC , Expr


<s> if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Offset ) ) BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset ) ; else { BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ; } unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT> ; } else { OperandBase = OffsetOperandNo ; } unsigned StackReg = MI . getOperand ( FIOperandNum ) . getReg ( ) ; MI . getOperand ( OperandBase ) . ChangeToRegister ( StackReg , false ) ; MI . getOperand ( OperandBase + <NUM_LIT> ) . ChangeToRegister ( SReg , false


<s> SDLoc dl ( Op ) ; auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget


<s> if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= DataSize && <STR_LIT> ) ; assert ( NumBytes <= FullSizeBytes && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes -


<s> bool useFPVFMx16 ( ) const { return useFPVFMx ( ) && hasFullFP16


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) )


<s> static SExpr * t_addrmode_sp_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I


<s> if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue (


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA57 ( ) && ! static_cast < const <ISA_LIT>TargetMachine * > ( TM ) -> isPBQPUsed ( ) ) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ; return true


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , SDLoc dl ) { if ( ! FPDiff ) return Chain ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , ( int64_t ) FPDiff - SlotSize , false ) ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex (


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( Subtarget -> getTargetABI ( ) ) { case <ISA_LIT>Subtarget :: O32 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N32 : return


<s> for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I )


<s> SDValue Res = DAG . getNode ( IntrData -> Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , GenCF . getValue ( <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Res . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; SDValue Results [ ] = { SetCC , Store } ; return DAG . getMergeValues ( Results , dl ) ; } case COMPRESS_TO_MEM : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToCompress = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = DataToCompress . getSimpleValueType ( ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; if ( isAllOnesConstant ( Mask ) ) return DAG . getStore ( Chain , dl , DataToCompress , Addr , MemIntr -> getMemOperand ( ) ) ; SDValue Compressed = getVectorMaskingNode ( DAG . getNode ( IntrData -> Opc0 , dl , VT , DataToCompress ) , Mask , DAG . getUNDEF ( VT ) , Subtarget , DAG ) ; return DAG . getStore ( Chain , dl , Compressed , Addr , MemIntr -> getMemOperand ( ) ) ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToTruncate = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; EVT VT = MemIntr -> getMemoryVT ( ) ; if ( isAllOnesConstant ( Mask ) ) return DAG . getTruncStore ( Chain , dl , DataToTruncate , Addr , VT , MemIntr -> getMemOperand ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; return DAG . getMaskedStore ( Chain , dl , DataToTruncate , Addr , VMask , VT , MemIntr -> getMemOperand ( ) , true ) ; } case EXPAND_FROM_MEM : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType (


<s> Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg ,


<s> void <ISA_LIT>InstrInfo :: movImm16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi6 = ( ( Val + <NUM_LIT>


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) { if ( <ISA_LIT>MFI -> getEmitNOAT ( ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym


<s> SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return GetTLSADDR ( DAG , Chain , GA , &

InFlag , PtrVT , <STR_LIT> , <STR_LIT> ) ;


<s> gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { rtx ( * gen_x86_shift_adj_1 ) ( rtx , rtx , rtx , rtx ) = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1 ; emit_move_insn ( scratch , high [ <NUM_LIT> ] ) ; emit_insn ( gen_ashr3 ( scratch , scratch , GEN_INT ( half_width - <NUM_LIT> ) ) ) ; emit_insn ( gen_x86_shift_adj_1 ( low [ <NUM_LIT> ] , high [ <NUM_LIT>

] , operands [ <NUM_LIT> ] , scratch ) ) ;


<s> int64_t Size ; if ( parseImmExpr ( Size ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFIAllocStack ( Size ) ; return false


<s> SDValue Hi = DAG . getVectorShuffle ( InVT , dl , In , DAG . getUNDEF ( InVT ) , HiMask ) ; Hi = DAG . getNode ( Opc , dl , HalfVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && InVT . is128BitVector ( ) && <STR_LIT> ) ; SDValue Curr = In ; SDValue SignExt = Curr ; if ( InVT != <STR_LIT> ) { MVT DestVT = VT == <STR_LIT> ? <STR_LIT> : VT ; unsigned DestWidth = DestVT . getScalarSizeInBits ( ) ; unsigned Scale = DestWidth / InSVT . getSizeInBits ( ) ; unsigned InNumElts = InVT . getVectorNumElements ( ) ; unsigned DestElts = DestVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( InNumElts , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != DestElts ; ++ i ) Mask [ i * Scale + ( Scale - <NUM_LIT> ) ] = i ; Curr = DAG . getVectorShuffle ( InVT , dl , In , In , Mask ) ; Curr = DAG . getBitcast ( DestVT , Curr ) ; unsigned SignExtShift = DestWidth - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , DestVT , Curr

, DAG . getTargetConstant ( SignExtShift , dl , <STR_LIT> ) ) ;


<s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Reg ) { case <NUM_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT>


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = <NUM_LIT> ; switch ( mode ) { case E_QImode : idx = <NUM_LIT> ; break ; case E_HImode : idx = <NUM_LIT> ; break ; case E_SImode : idx = <NUM_LIT> ; break ; case E_DImode : idx = <NUM_LIT>


<s> int <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands ) { if ( IsFreeOperator ( U ) ) return TTI :: TCC_Free ; return BaseT :: getUserCost (


<s> } else if ( SearchSignedMulLong ( Src1 , & Opc , A , B , true ) ) { Acc = Src0 ; } else { return false ; } if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , Acc , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( N -> getOpcode ( ) == <STR_LIT> && SearchSignedMulLong ( SDValue ( N , <NUM_LIT> ) , & Opc , A , B , false ) ) { if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> int ia64_hard_regno_rename_ok ( int from , int to ) { if ( to == current_frame_info . reg_fp || to == current_frame_info . reg_save_b0 || to == current_frame_info . reg_save_pr || to == current_frame_info . reg_save_ar_pfs || to == current_frame_info . reg_save_ar_unat || to == current_frame_info . reg_save_ar_lc ) return <NUM_LIT> ; if ( from == current_frame_info . reg_fp || from == current_frame_info . reg_save_b0 || from == current_frame_info . reg_save_pr || from == current_frame_info . reg_save_ar_pfs || from == current_frame_info . reg_save_ar_unat || from == current_frame_info . reg_save_ar_lc ) return <NUM_LIT> ; if ( OUT_REGNO_P ( to ) && to >= OUT_REG ( current_frame_info . n_output_regs ) ) return <NUM_LIT> ; if ( PR_REGNO_P ( from ) && PR_REGNO_P ( to ) ) return ( from & <NUM_LIT> ) == ( to & <NUM_LIT> ) ; return


<s> VectorType * VecTy = getVectorType ( cast < IntrinsicInst > ( & I ) ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; } else if ( auto * Int = dyn_cast < IntrinsicInst


<s> void relaxInstruction ( MCInst & Inst ,

const MCSubtargetInfo & STI ) const override {


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C )


<s> MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; getStreamer ( ) . EmitIntValue ( ImmOp64 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; if ( emitPartialAddress ( TOut , IDLoc , Sym ) ) return true ; if ( isABI_N64 ( ) ) TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; else TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; if ( isABI_N32 ( ) || isABI_N64 ( ) ) TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) ) return false ; bool Changed =


<s> return ( can_create_pseudo_p ( ) && ! ( cfun -> curr_properties & PROP_rtl_split_insns


<s> <ISA_LIT>MCAsmInfoELF :: <ISA_LIT>MCAsmInfoELF ( const Triple & TT ) { AssemblerDialect = AD_ATT ; CalleeSaveStackSlotSize = <NUM_LIT> ; CodePointerSize = <NUM_LIT> ; Data64bitsDirective = <STR_LIT> ; ExceptionsType = ExceptionHandling


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , ArchFS


<s> static unsigned char aarch64_class_max_nregs ( reg_class_t regclass , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; unsigned int nregs , vec_flags ; switch ( regclass ) { case TAILCALL_ADDR_REGS : case POINTER_REGS : case GENERAL_REGS : case


<s> if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && ! isDispSafeForFrameIndex ( Val ) )


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l + NumLaneElts / <NUM_LIT> ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ; int BitI1 = Mask [ l +


<s> else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; return -


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym )


<s> bool <ISA_LIT>DAGToDAGISel :: tryFP_TO_INT ( SDNode * N , SDLoc dl ) { if ( ! Subtarget -> hasMVEFloatOps ( ) ) return false ; EVT Type = N -> getValueType ( <NUM_LIT> ) ; if ( ! Type . isVector ( ) ) return false ; unsigned int ScalarBits = Type . getScalarSizeInBits ( ) ; bool IsUnsigned = N -> getOpcode ( ) == <STR_LIT> ; SDNode * Node = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { if ( Node -> getOperand ( <NUM_LIT> ) != Node -> getOperand ( <NUM_LIT> ) ) return false ; SDNodeFlags Flags = Node -> getFlags ( ) ; if ( ScalarBits == <NUM_LIT> && ! Flags . hasNoInfs ( ) && IsUnsigned ) return false ; unsigned Opcode ; switch ( ScalarBits ) { case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> :


<s> } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { int16_t imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ( imm % EncodingAlignment ) == <NUM_LIT> ) ) { KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSKnown . Zero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } Disp = DAG . getTargetConstant ( imm , dl , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { int16_t Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! EncodingAlignment || ( Imm % EncodingAlignment ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , dl


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand


<s> const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO -> getAlign ( ) < MMO -> getSize ( ) ) ) return true ; } return


<s> if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end (


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand


<s> } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } if ( PointerType * Ty = dyn_cast < PointerType > ( Obj -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else


<s> bool <ISA_LIT>RegisterBankInfo :: onlyDefinesFP ( const MachineInstr & MI , const MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , unsigned Depth ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_EXTRACT_VECTOR_ELT : case TargetOpcode ::


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo (


<s> static unsigned getShufflePALIGNRImmediate ( ShuffleVectorSDNode * SVOp ) { return getShuffleAlignrImmediate ( SVOp ,


<s> emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ <NUM_LIT> ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ <NUM_LIT> ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [


<s> Offset -= <STR_LIT> ; int FrameIdx = MFFrame . CreateFixedSpillStackObject ( <NUM_LIT> , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } ZFI -> setRestoreGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; int Offset = getRegSpillOffset ( MF , Reg ) ; if ( StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } } } ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; int CurrOffset = - <STR_LIT> ; if ( usePackedStack ( MF ) ) CurrOffset += StartSPOffset ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; CurrOffset -=


) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) ) ;


<s> void addMemTBBOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Register FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl ,

DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> Vals . push_back ( DAG . getConstant ( Cst , DL , SVT ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Vals ) ; } SDValue V = peekThroughBitcasts ( Op ) ; if ( V != Op && V . getOpcode ( ) == <STR_LIT> ) { MVT InnerVT = V . getSimpleValueType ( ) ; MVT InnerEltVT = InnerVT . getVectorElementType ( ) ; if ( OpEltVT == InnerEltVT ) { assert ( OpVT == InnerVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V . getOperand ( <NUM_LIT> ) ) ; } if ( InnerEltVT . getSizeInBits ( ) < InputBits ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( OpVT , V ) ) ; } if ( V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == InputBits ) { SDValue ExtractedV = V . getOperand ( <NUM_LIT> ) ; SDValue OrigV = ExtractedV . getOperand (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG ,


<s> const SetOfInstructions & getLOHRelated ( ) const { return LOHRelated


<s> int strict_p = reload_completed ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) )


<s> getT2AddrModeImm12OffsetOpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; unsigned Value = <NUM_LIT> ; int32_t tmp = ( int32_t ) MO1 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm .


<s> int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op .

getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> return std :: unique_ptr < MCObjectWriter > ( create<ISA_LIT>ELFObjectWriter ( OS ,


<s> static SDValue lower1BitShuffleAsKSHIFTR ( const SDLoc & DL , ArrayRef < int > Mask , MVT VT , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( ! V2 . isUndef ( ) ) return SDValue ( ) ; int ShiftAmt = - <NUM_LIT> ; int NumElts = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; assert ( ( M == SM_SentinelUndef || ( <NUM_LIT> <= M && M < NumElts ) ) && <STR_LIT> ) ; if ( M < <NUM_LIT> )


<s> if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MF


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_SETJMP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Val = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT>

) , Op . getOperand ( <NUM_LIT> ) , Val ) ;


<s> MCSymbol * getJumpTableEntryPCRelSymbol ( int Idx ) const { return JumpTableEntryInfo [ Idx ]


<s> for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( <NUM_LIT> ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - <NUM_LIT> ; if ( ShiftAmt == <NUM_LIT> || ShiftAmt > <NUM_LIT> ) return false ; break ; } case Instruction


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true


<s> static unsigned int mips16e_find_first_register ( unsigned int mask , const unsigned char * regs , unsigned int size ) { unsigned int i ; for ( i = <NUM_LIT> ; i < size ; i ++ ) if ( BITSET_P ( mask ,


<s> return isMemDisp20 ( BDMem , ADDR64Reg )


<s> virtual raw_ostream & GetCommentOS ( ) { if ( ! IsVerboseAsm ) return


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return * CM ; return CodeModel ::


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> return ( isTargetELF ( ) && ! isTargetNaCl ( ) ) || TM . getRelocationModel ( ) ==


<s> void setTextFragment ( RegionFragment *


<s> assert ( isMem ( BDLMem ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp


<s> EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> ,


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> <ISA_LIT>TargetStreamer :: emitDirectiveModuleOddSPReg ( Enabled , IsO32ABI ) ; ABIFlagsSection . OddSPReg


<s> default : continue ; case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT>


<s> bool VectorABI = UsesVectorABI ( CPU , FS ) ; std :: string Ret = <STR_LIT> ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( Triple ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret +=


) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetDarwin ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode

( ) , FrameAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> Type * Tys [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; Module * M = I -> getParent ( ) -> getParent ( ) -> getParent ( ) ; auto Fn = <STR_LIT> ( M , I -> getIntrinsicID ( ) , Tys ) ; auto CI = CallInst :: Create ( Fn , Ops , I -> getName ( ) , I ) ; I -> replaceAllUsesWith ( CI ) ; I -> eraseFromParent


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg .


<s> forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { bool wasInITBlock = inITBlock ( ) ; while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit ,


) ) _kshiftri_mask32 ( __mmask32 __A , unsigned int __B ) {


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T ) { HasAbsolutizedSet =


<s> return selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } } if ( N . getOpcode ( ) == <STR_LIT> ) { PatternNodeWithChain = N ; if ( IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , Parent , Root , OptLevel ) ) { auto * MI = cast < MemIntrinsicSDNode > ( PatternNodeWithChain ) ; return selectAddr ( MI , MI -> getBasePtr ( ) , Base , Scale , Index , Disp


<s> DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ,


<s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) ,


<s> if ( mode == TFmode && ! ( TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( mode == TImode ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 , mode ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; if ( reload_in_progress && GET_CODE ( rs1 ) == HIGH && XEXP ( rs1 , <NUM_LIT> ) == imm1 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return <NUM_LIT> ; if ( GET_CODE ( rs1 ) == SUBREG ) rs1 = SUBREG_REG ( rs1 ) ; if ( ! REG_P ( rs1 ) ) return <NUM_LIT> ; if ( rs2 ) { if ( GET_CODE ( rs2 ) == SUBREG ) rs2 = SUBREG_REG ( rs2 ) ; if ( ! REG_P ( rs2 ) ) return <NUM_LIT> ; } if ( strict ) { if ( ! REGNO_OK_FOR_BASE_P ( REGNO ( rs1 ) ) || ( rs2 && ! REGNO_OK_FOR_BASE_P ( REGNO ( rs2 ) ) )


<s> output_addr_const ( stream , x ) ; fputs ( <STR_LIT> , stream ) ; break ; case REG : if ( TARGET_REDUCED_REGS && REGNO ( x ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op0 ) && REGNO ( op0 ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op1 ) && REGNO ( op1 ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , reg_names [ REGNO ( op0 ) ] , INTVAL ( op1 ) ) ; } else if ( REG_P ( op0 ) && REG_P ( op1 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( op0 ) ] , reg_names [ REGNO ( op1 ) ] ) ; } else if ( GET_CODE ( op0 ) == MULT && REG_P ( op1 ) ) { int sv ; if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else gcc_unreachable ( ) ; fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( op1 ) ] , reg_names [ REGNO ( XEXP ( op0 , <NUM_LIT> ) ) ] , sv ) ; } else { debug_rtx ( x ) ; gcc_unreachable ( ) ; } break ; case POST_MODIFY : op0 = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; op1 = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op0 ) && REGNO ( op0 ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op1 ) && REGNO (


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name +

<STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MI . getOperand ( OpNum ) .


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( )


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCSymbol * Symbol , <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ; if ( TARGET_K6 && ( ( ! parts . disp && parts . base && parts . index && parts . scale != <NUM_LIT> ) || ( parts . disp && ! parts . base && parts . index && parts . scale != <NUM_LIT> ) || ( ! parts . disp && parts . base && parts . index && parts . scale ==


<s> bool shouldSignWithBKey ( ) const { return


<s> SDValue SignMask2x64 ( SDValue A ) { assert ( A . getSimpleValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( A . getSimpleValueType ( ) != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue V = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> ,

DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A ) ;


<s> Inst . setOpcode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( get<ISA_LIT>SubSuperRegister ( Reg , VT ) ) ) ; Op . addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst


<s> if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New . getNode ( ) ; } if ( ! N -> isMachineOpcode ( ) ) SelectCode ( N ) ; return true ; } } unsigned Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) && RISBG . Start >= <NUM_LIT> && RISBG . End >= RISBG . Start && ( ( RISBG . Start + RISBG . Rotate ) & <NUM_LIT> ) >= <NUM_LIT> && ( ( RISBG . End + RISBG . Rotate ) & <NUM_LIT> ) >= ( ( RISBG . Start + RISBG


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ; MCE . addRelocation ( GetRelocation (


<s> bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true


<s> MaskInst . addOperand ( MCOperand :: createReg ( AddrReg ) ) ; MaskInst . addOperand ( MCOperand :: createReg ( AddrReg ) ) ; MaskInst . addOperand ( MCOperand ::


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( )


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } return MCConstantExpr :: create ( Val , getContext ( ) ) ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { const MCSymbol * Symbol = & MSRE -> getSymbol ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( <ISA_LIT>MCExpr :: isSupportedBinaryExpr ( VK , BE ) ) return <ISA_LIT>MCExpr :: create ( VK , Expr , getContext ( ) ) ; const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res


<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo (


<s> switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ; } return DefCycle


<s> static bool isUndefOrZeroOrInRange ( ArrayRef < int > Mask


<s> if ( TREE_CODE ( cst ) != INTEGER_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( compare_tree_int ( cst , REGPARM_MAX ) > <NUM_LIT> ) { warning ( OPT_Wattributes , <STR_LIT> , name , REGPARM_MAX ) ; * no_add_attrs = true ; } return NULL_TREE ; } if ( TARGET_64BIT ) { if ( ( TREE_CODE ( * node ) != FUNCTION_TYPE && TREE_CODE ( * node ) != METHOD_TYPE ) || ix86_function_type_abi ( * node ) != MS_ABI ) warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } } else if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * node ) ) ) { error ( <STR_LIT> ) ; } } else if ( is_attribute_p ( <STR_LIT> , name ) ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES (


<s> float * f = fvf ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) f [ i ] = g [ i ] + h [ i ] ; f [ <NUM_LIT> ] = g [ <NUM_LIT> ] + h [


<s> unsigned POTReg = getPOTBaseRegister ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) { return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , POTReg , PtrVT ) ; } else { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; SDValue POTAddress = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; POTAddress = DAG . getLoad ( PtrVT , dl , Chain , POTAddress , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; Chain = POTAddress . getValue


<s> if ( isDarwinABI ) return is<ISA_LIT>64 ? - <NUM_LIT> :


<s> assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr :: VK_PLT : assert ( Type == RT32_32 ) ; return ELF :: R_386_PLT32 ; case MCSymbolRefExpr :: VK_INDNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE ; case MCSymbolRefExpr :: VK_GOTNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GOTIE


<s> static SDValue LowerNeonVLDIntrinsic ( SDValue Op , SelectionDAG & DAG , unsigned Opcode ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! VT . is64BitVector ( ) ) return SDValue ( ) ; SDValue Ops [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) } ; return DAG . getNode ( Opcode , dl , Node -> getVTList


<s> Type * Ty = User -> getOperand ( <NUM_LIT> ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( <STR_LIT> , getValueType ( DL , Ty ) ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } case Instruction :: Load : { LoadInst * LI = cast < LoadInst > ( I ) ; if ( ! LI -> isUnordered ( ) ) return true ; if ( User -> getOpcode ( ) != Instruction :: Store


<s> SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( MaskVT . getVectorElementType ( ) != <STR_LIT> ) { if ( PassThru . isUndef ( ) || <STR_LIT> ( PassThru . getNode ( ) ) ) return Op ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , getZeroVector ( VT , Subtarget , DAG , dl ) , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Select = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Select , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ; } assert ( ( ! N -> isExpandingLoad ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isExpandingLoad ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> (


<s> return ( poly128_t ) __builtin_neon_vreinterprettiv16qi (


<s> Context = & funcInfo . Fn -> getContext ( ) ; bool ISASupported = ! Subtarget -> has<ISA_LIT>32r6 ( ) && Subtarget -> has<ISA_LIT>32 ( ) ; TargetSupported = ISASupported && ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) ) ; UnsupportedFPMode = Subtarget -> isFP64bit


<s> if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const MVT BlockType = getOptimalRepmovsType ( Subtarget , Align ) ; const uint64_t BlockBytes = BlockType . getSizeInBits ( ) / <NUM_LIT> ; const uint64_t BlockCount = Size / BlockBytes ; const uint64_t BytesLeft = Size % BlockBytes ; SDValue RepMovs = emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , DAG . getIntPtrConstant ( BlockCount , dl ) , BlockType ) ; if ( BytesLeft == <NUM_LIT> ) return RepMovs ; assert ( BytesLeft && <STR_LIT> ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return emitRepmovsB ( Subtarget , DAG , dl , Chain , Dst , Src , Size ) ; SmallVector < SDValue , <NUM_LIT> >


<s> assert ( isT2SOImmTwoPartVal ( Imm ) && <STR_LIT> ) ; unsigned V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( Imm ) )


<s> SDValue C = N1 . getOperand ( <NUM_LIT> ) ; SDValue B ; if ( N0 . getOperand ( <NUM_LIT> ) == A ) B = N0 . getOperand ( <NUM_LIT> ) ; else if ( N0 . getOperand ( <NUM_LIT> ) == A ) B = N0 . getOperand ( <NUM_LIT> ) ; else return false ; SDLoc dl ( N ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ternlog = CurDAG -> getNode ( <STR_LIT> , dl , NVT , A , B , C , Imm ) ; ReplaceNode ( N , Ternlog .


<s> if ( ! HasStoreVarArgs ) HasStoreVarArgs = true ; FnStoreVarArgs . push_back ( <ISA_LIT>FIHolder (


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex ,

const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override {


<s> assert ( VT == <STR_LIT> && isPowerOf2_32 ( EltSize ) && EltSize <= <NUM_LIT> && <STR_LIT> ) ; if ( N -> getMaskElt ( <NUM_LIT> ) % EltSize != <NUM_LIT> ) return false ; unsigned ElementBase = N -> getMaskElt ( <NUM_LIT> ) ; if ( ElementBase >= <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != EltSize ; ++ i ) if ( N -> getMaskElt ( i ) < <NUM_LIT> || N -> getMaskElt ( i ) != ( int ) ( i + ElementBase ) ) return false ; for ( unsigned i = EltSize , e = <NUM_LIT> ; i != e ; i += EltSize ) { if ( N -> getMaskElt ( i ) < <NUM_LIT> ) continue ; for ( unsigned j = <NUM_LIT> ; j != EltSize ; ++ j ) if ( N -> getMaskElt ( i + j ) != N -> getMaskElt ( j