<s> unsigned LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; bool LHSIsKill = hasTrivialKill ( LHS ) ; if ( NeedExtend ) LHSReg = EmitIntExt ( SrcVT , LHSReg , RetVT , IsZExt ) ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = IsZExt ? C -> getZExtValue ( ) : C -> getSExtValue ( ) ; if ( C -> isNegative ( ) ) ResultReg = emitAddSub_ri ( ! UseAdd , RetVT , LHSReg , LHSIsKill , - Imm , SetFlags , WantResult ) ; else ResultReg = emitAddSub_ri ( UseAdd , RetVT , LHSReg , LHSIsKill , Imm , SetFlags , WantResult ) ; } if ( ResultReg ) return ResultReg ; if ( ExtendType != <STR_LIT> && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) if ( ( SI -> getOpcode ( ) == Instruction :: Shl ) && ( C -> getZExtValue ( ) < <NUM_LIT> ) ) { unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI -> getOperand ( <NUM_LIT> ) ) ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ExtendType , C -> getZExtValue ( ) , SetFlags , WantResult ) ; } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( RHS ) ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ExtendType , <NUM_LIT> , SetFlags , WantResult ) ; } if ( isValueAvailable ( RHS ) ) if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) { if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand (


<s> static SDValue Lower512IntUnary ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getSimpleValueType ( ) . is512BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return LowerVectorIntUnary ( Op


<s> static SDValue LowerVecReduceF ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { if ( ! ST -> hasMVEFloatOps ( ) )


<s> AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return


<s> Value * <ISA_LIT>IREmitter :: visitBSR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; } return DAG . getNode ( NewOp , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> UnwindOpcodeAssembler ( ) : HasPersonality ( <NUM_LIT> ) { OpBegins . push_back (


<s> else if ( warn_psabi_flags & WARN_PSABI_ZERO_WIDTH_BITFIELD ) inform ( input_location , <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url12 ) ; } * count = ag_count ; } else return false ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) { * count = <NUM_LIT> ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { * count = <NUM_LIT> ; new_mode = ( mode == DCmode ? DFmode : SFmode ) ; } else return false ; if ( ! use_vfp_abi ( pcs_variant , ARM_NUM_REGS ( new_mode ) > <NUM_LIT> ) ) return false ; * base_mode = new_mode ; if ( TARGET_GENERAL_REGS_ONLY ) error ( <STR_LIT> , type ) ; return


<s> FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x =


<s> otherops [ <NUM_LIT> ] = base_reg ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; otherops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) | nds32_regno_to_enable4 ( regno + <NUM_LIT> ) ; sprintf ( buff , <STR_LIT> , update_base , enable4 ) ; } else if ( regno == <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno + <NUM_LIT> ) ; sprintf ( buff , <STR_LIT> , update_base , enable4 ) ; } else { sprintf ( buff , <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = MF . getTarget ( ) . getInstrInfo (


<s> unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; if ( isPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; SDLoc DL ( GA ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( JT ) , PtrVT , GA , DAG . getNode ( <STR_LIT> , DL , PtrVT ) ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( )


<s> return CONSTANT_P ( x ) && legitimate_address_p ( Pmode ,


<s> return ( vector unsigned int ) __builtin_altivec_lvewx ( a1 , ( void *


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>V9Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget ( )


<s> static struct unw_table_entry * find_fde_for_dso ( Elf64_Addr pc , rt_link_map * map , unsigned long * pseg_base , unsigned long * pgp ) { rt_segment * seg ; Elf64_Addr seg_base ; struct unw_table_entry * f_base ; size_t lo , hi ; for ( seg = map -> l_segments ; seg ; seg = ( rt_segment * ) seg -> s_next ) { if ( pc >= seg -> s_map_addr && pc < seg -> s_map_addr + seg -> s_mapsz ) break ; } if ( ! seg ) return NULL ; f_base = ( struct unw_table_entry * ) ( map -> l_unwind_table ) ; seg_base = ( Elf64_Addr ) seg -> s_map_addr ; lo = <NUM_LIT> ; hi = map -> l_unwind_sz / sizeof ( struct unw_table_entry ) ; while ( lo < hi ) { size_t mid = ( lo + hi ) / <NUM_LIT> ; struct unw_table_entry * f = f_base + mid ; if ( pc < f -> start_offset + seg_base ) hi = mid ; else if ( pc >= f -> end_offset + seg_base ) lo = mid + <NUM_LIT> ; else { Elf64_Dyn * dyn = map -> l_ld ; * pgp = <NUM_LIT> ; for ( ; dyn -> d_tag != DT_NULL ; dyn ++ ) { if ( dyn -> d_tag == DT_PLTGOT ) { * pgp = dyn -> d_un . d_ptr ; break ; } } * pseg_base = seg_base ; return f


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) PrivateGlobalPrefix = <STR_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; AllowAtInName = true ; UseIntegratedAssembler =


<s> unsigned SizeInBits ; unsigned OpLSHR ; unsigned OpASHR ; unsigned OpSHL ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; auto ShiftEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ DstTy ] ( const ShiftEntry & El ) { return El . SizeInBits == DstTy . getSizeInBits ( ) ; } ) ; if ( ShiftEntryIt == std :: end ( OpTable ) ) return false ; unsigned Opcode = <NUM_LIT> ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : Opcode = ShiftEntryIt -> OpSHL ; break ; case TargetOpcode :: G_ASHR : Opcode = ShiftEntryIt ->


<s> TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true


<s> if ( TT . isOSBinFormatELF ( ) ) { unsigned FeatureFlagsAnd = <NUM_LIT> ; if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_IBT ; if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_SHSTK ; if ( FeatureFlagsAnd ) { if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> ,


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; Result = DAG . getNode ( getGlobalWrapperKind ( ) , dl


<s> bool isTargetWin64 ( ) const { return In64BitMode && isOSWindows (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: Fast : return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : return ( Return ? RetCC_<ISA_LIT>_APCS


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case

TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> return isAbsMem ( ) && Mem . ModeSize


<s> tmpInst . setOpcode ( Opcode ) ; tmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; tmpInst . addOperand ( Op1 ) ; tmpInst . setLoc ( IDLoc ) ; Instructions . push_back (


<s> return ( __m128i ) __builtin_ia32_pmovusqb128_mask ( ( __v2di ) __A , ( __v16qi )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast <


<s> if ( isThumb2 ( ) ) { EncodedValue &= <NUM_LIT> ; EncodedValue |= <NUM_LIT> ; } return EncodedValue


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) ,


<s> assert ( Kind == k_ShiftExtend && <STR_LIT> ) ; return ShiftExtend


<s> } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = <NUM_LIT> ; pcum -> prototype_p = false ; if ( mode != VOIDmode ) { pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else pcum ->


<s> unsigned getNumFixupKinds ( ) const override { return


<s> SDLoc DL ( Op ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , VT , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( Op , V1 , V2 , Subtarget ,


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : { if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_NEG : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Expr , MCFixupKind


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case


<s> break ; case RegPairInfo :: FPR64 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: FPR128 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: ZPR : LdrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: PPR : LdrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired


<s> const MCExpr * Disp = MCConstantExpr :: create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <STR_LIT> , <STR_LIT> ,


<s> TOut . emitR ( <STR_LIT> , DstReg , IDLoc , STI ) ; TOut . emitRRI ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , ATReg , IDLoc , STI ) ; if ( useTraps ( ) ) { TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; } else { MCContext & Context = TOut . getStreamer ( ) . getContext ( ) ; MCSymbol * BrTarget = Context . createTempSymbol ( ) ; MCOperand LabelOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( BrTarget , Context ) ) ; TOut . emitRRX ( <STR_LIT> , DstReg , ATReg , LabelOp , IDLoc , STI ) ; if ( AssemblerOptions . back ( ) -> isReorder ( ) ) TOut . emitNop ( IDLoc , STI ) ; TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; TOut . getStreamer ( ) . EmitLabel ( BrTarget ) ; } TOut . emitR ( <STR_LIT> , DstReg


<s> else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get (


<s> Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; }


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Enc = <STR_LIT> ( - CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> unsigned getT2SOImmOpValue ( const MachineInstr & MI , unsigned


<s> RC = ( const TargetRegisterClass * ) & <STR_LIT> ; return <ISA_LIT>16SPAliasReg = MF . getRegInfo ( ) . createVirtualRegister (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; auto IsFreeTruncation = [ VT ] ( SDValue Op ) { unsigned TruncSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; return <STR_LIT> ( Op . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( SrcOpcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) )


<s> return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return false ; Imm = N ; if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N ) -> getGlobal ( ) ->


<s> Name = StringRef ( std :: string ( <STR_LIT> ) + getLexer ( ) . getTok ( ) . getString ( ) . str ( ) ) ; break ; case AsmToken :: Identifier : Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; break ; } unsigned RegNo = MatchRegisterName (


<s> if ( NumElts % <NUM_LIT> != <NUM_LIT> ) return false ; NewMask . clear ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { int M0 = M [ i ] ; int M1 = M [ i + <NUM_LIT> ] ; if ( M0 == - <NUM_LIT> && M1 == - <NUM_LIT> ) { NewMask . push_back ( - <NUM_LIT> ) ; continue ; } if ( M0 == - <NUM_LIT> && M1 != - <NUM_LIT> && ( M1 % <NUM_LIT> ) == <NUM_LIT> ) { NewMask . push_back ( M1 / <NUM_LIT> ) ; continue ; } if ( M0 != - <NUM_LIT> && ( M0 % <NUM_LIT> ) == <NUM_LIT> && ( ( M0 + <NUM_LIT> ) == M1 || M1 == - <NUM_LIT> ) ) { NewMask . push_back ( M0 / <NUM_LIT> ) ; continue ; } NewMask . clear ( ) ; return false ; } assert ( NewMask . size ( ) == NumElts


<s> if ( I == MBB . end ( ) || I -> getOpcode ( ) != EndbrOpcode ) { BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , TII -> get


<s> default : return SDValue ( ) ; case <STR_LIT> : { if ( ! isSplatVector ( Op . getNode ( ) ) ) return SDValue ( ) ; Ld = Op . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; if ( VT . is256BitVector ( ) ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) ) return SDValue ( ) ; break ; } } bool Is256 = VT . is256BitVector ( ) ; if ( ConstSplatVal && Subtarget -> hasAVX2 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateTraceSyncBarrierOpt ( <STR_LIT> Opt , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_TraceSyncBarrierOpt ) ; Op -> TSBOpt . Val = Opt ; Op -> StartLoc =


<s> static bool rx_small_data_operand ( rtx op ) { if ( rx_small_data_limit == <NUM_LIT> ) return


<s> StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return


<s> Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ; return Res


<s> if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { if ( Name == <STR_LIT> ) return FK_NONE ; } else { if ( Name == <STR_LIT> ) return


<s> Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex


<s> return ( RegIdx . Index == <NUM_LIT> || ( RegIdx . Index >= <NUM_LIT> && RegIdx . Index <=

<NUM_LIT> ) || RegIdx . Index == <NUM_LIT> ) ;


<s> if ( hasDisp && MSrc . isReg ( ) ) MSrc . setIsKill ( false ) ; MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addOperand ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MachineInstr * MIO = BuildMI ( * BB , ( MachineInstr * ) MIM , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) . addOperand ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MIM . addReg ( MIO -> getOperand ( <NUM_LIT> ) . getReg ( )


<s> MachineBasicBlock * CPEBB = CPEMI -> getParent ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( <NUM_LIT> )


<s> MachineInstr & MI = * MBBI ; if ( MI . isCall ( ) || MI . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI . isDebugValue ( ) ) MI2LocMap [ & MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; unsigned Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap . find ( Base ) ; if ( BI != Base2LdsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } else


<s> const char * rs6000_indirect_sibcall_template ( rtx * operands , unsigned


<s> tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION (


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> )


<s> return isImmediate < <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) || LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) )


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } return false ; } ; auto ScanLoop = [ & ] ( Loop * L ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( maybeLoweredToCall ( I ) || IsHardwareLoopIntrinsic ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ) ; return false ; } } } return true ; } ; for ( auto Inner : * L ) if ( ! ScanLoop ( Inner ) ) return false ; if ( ! ScanLoop ( L ) ) return false ; LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CounterInReg = true ; HWLoopInfo . IsNestingLegal = false ; HWLoopInfo . PerformEntryTest = true ; HWLoopInfo . CountType = Type :: getInt32Ty


<s> HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI =


<s> if ( ! ( flags & SECTION_DEBUG ) ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( HAVE_AS_SPARC_NOBITS ) { if ( flags & SECTION_BSS ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT>


<s> uint64_t Min = MinAlign ( SrcAlignInBytes , DestAlignInBytes ) ; KnownBits KB = computeKnownBits ( LengthInBytes , getDataLayout ( ) ) ; Min = MinAlign ( Min , <NUM_LIT> << KB .


<s> return create<ISA_LIT>AsmBackend ( T , STI ,


<s> static bool nds32_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) if ( size < <NUM_LIT> || size > <NUM_LIT> *


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { assert ( <NUM_LIT> &&


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { StringRef Flags = <STR_LIT> , Reg = SpecialReg ; if ( Reg . endswith ( <STR_LIT> ) ) { Flags = <STR_LIT> ; Reg = Reg . drop_back ( <NUM_LIT> ) ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true


<s> assert ( opcode == <STR_LIT> || opcode == <STR_LIT> ) ; SDValue Hi32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; SDValue Lo32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) Lo32 = DAG . getNode ( opcode , dl , <STR_LIT> , Lo32 ) ; else Hi32 = DAG . getNode ( opcode , dl ,


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <NUM_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op ) . isReg ( ) && isScale ( MI -> getOperand ( Op + <NUM_LIT> ) ) && MI -> getOperand ( Op + <NUM_LIT> ) . isReg ( ) && ( MI -> getOperand ( Op + <NUM_LIT> ) . isImm ( ) || MI -> getOperand ( Op + <NUM_LIT> ) . isGlobal

( ) || MI -> getOperand ( Op + <NUM_LIT> ) . isCPI ( ) || MI -> getOperand ( Op + <NUM_LIT> ) . isJTI ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerELEMENT_COUNT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT VecVT = cast < VTSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; assert ( VecVT . isScalableVector ( ) && <STR_LIT> ) ; unsigned NumByteElts = <STR_LIT> / <NUM_LIT> ; EVT ElCntVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , { NumByteElts , true } ) ; SDValue EC = Op ; if ( ( VecVT != ElCntVT ) || ( VT != <STR_LIT> ) ) { SDValue Undef = DAG . getValueType ( ElCntVT ) ; EC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Undef ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ; if ( NumElts


<s> if ( ShiftImm >= RetVT . getSizeInBits ( ) ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar (


<s> return mips_expand_builtin_direct ( d -> icode , target , exp , false ) ; case MIPS_BUILTIN_MOVT : case MIPS_BUILTIN_MOVF : return mips_expand_builtin_movtf ( d -> builtin_type , d -> icode , d -> cond , target , exp ) ; case MIPS_BUILTIN_CMP_ANY : case MIPS_BUILTIN_CMP_ALL : case MIPS_BUILTIN_CMP_UPPER : case MIPS_BUILTIN_CMP_LOWER : case MIPS_BUILTIN_CMP_SINGLE : return mips_expand_builtin_compare ( d -> builtin_type , d -> icode , d -> cond , target , exp ) ; case


<s> static __inline__ float __fabsf ( float x ) { float


<s> if ( M . empty ( ) ) return ; MCSymbol * TOCBaseSym = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSectionXCOFF * TOCBaseSection = OutStreamer -> getContext ( ) . getXCOFFSection ( StringRef ( <STR_LIT> ) , XCOFF :: XMC_TC0 , XCOFF :: XTY_SD , XCOFF :: C_HIDEXT , SectionKind :: getData ( ) ) ; cast < MCSymbolXCOFF > ( TOCBaseSym ) -> setContainingCsect ( TOCBaseSection ) ; OutStreamer -> SwitchSection (


<s> DollarIsPC = true ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; AllowSymbolAtNameStart = true


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLSMultiple ( MachineInstr * MI ) { if ( isThumb1 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; Register Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end


<s> Imm += Offset ; Imm += AdjustOffset ; Inst . addOperand ( MCOperand ::


<s> if ( GET_CODE ( base ) == SYMBOL_REF || GET_CODE ( base ) == LABEL_REF ) { if ( aarch64_classify_symbol ( base , offset ) != SYMBOL_FORCE_TO_MEM ) return true ; else return mode !=


<s> unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz != <NUM_LIT> && EltSz != <NUM_LIT> && EltSz != <NUM_LIT> ) return false ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz )


<s> if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , Register > :: iterator I = LocalValueMap . find ( V ) ; Register LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; auto debugLoc = DbgLoc ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; DbgLoc = debugLoc ; if ( TLI . getPointerTy ( DL ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] =


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) &&

! Subtarget . isOSWindows ( ) ) return false ;


<s> void Thumb1InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & st = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; assert ( <STR_LIT> . contains ( DestReg , SrcReg ) && <STR_LIT> ) ; if ( st . hasV6Ops ( ) || <STR_LIT> . contains ( SrcReg ) || ! <STR_LIT> . contains ( DestReg ) ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) )

. addReg ( DestReg , getDefRegState ( true ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( unsigned ) i >> TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( unsigned ) i >> TypeShiftAmt ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << TypeShiftAmt ) | ( ( unsigned ) i >> ( SplatBitSize - TypeShiftAmt ) ) ) ) { SDValue Res = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; static const unsigned IIDs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> } ; Res = BuildIntrinsicOp ( IIDs [ SplatSize - <NUM_LIT> ] , Res , Res , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Res ) ; } if ( SextVal == ( int ) ( ( ( unsigned ) i << <NUM_LIT> ) | ( i < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) { SDValue T = BuildSplatI ( i , SplatSize , <STR_LIT> , DAG , dl ) ; return BuildVSLDOI ( T , T , <NUM_LIT> , Op . getValueType ( ) , DAG


<s> static bool matchRegisterNameHelper ( const MCSubtargetInfo & STI , MCRegister & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <STR_LIT> ) RegNo


<s> assert ( Scale > <NUM_LIT> && <STR_LIT> ) ; int NumElements = VT . getVectorNumElements ( ) ; int EltBits = VT . getScalarSizeInBits ( ) ; assert ( ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) && <STR_LIT> ) ; assert ( Scale * EltBits <= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> ( EltBits * Scale ) , NumElements / Scale ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ExtVT , InputV ) ) ; } if ( AnyExt && EltBits == <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ; int PSHUFHWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFHWMask , DL , DAG ) ) ) ; } if ( ( Scale * EltBits ) == <NUM_LIT> && EltBits < <NUM_LIT> && Subtarget -> hasSSE4A ( ) ) { assert ( NumElements == ( int ) Mask .


<s> SDValue <ISA_LIT>TargetLowering :: prepareVolatileOrAtomicLoad ( SDValue Chain , const

SDLoc & DL , SelectionDAG & DAG ) const {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; Mask . push_back ( isa < ConstantSDNode > ( CondElt ) ? i + ( isNullConstant ( CondElt ) ? Size : <NUM_LIT> ) : - <NUM_LIT> ) ; } return DAG . getVectorShuffle ( VT , dl , LHS , RHS


<s> for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get (

TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> bool isMemPCRelImm12 ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum != <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue


<s> rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; HOST_WIDE_INT lo = sext_hwi ( vcall_offset , <NUM_LIT> ) ; HOST_WIDE_INT hi = vcall_offset - lo ; rtx tmp ; tmp = gen_rtx_MEM ( Pmode , this_rtx ) ; emit_move_insn ( scratch , tmp ) ; if ( hi != <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED (


<s> unsigned getRegisterBitWidth ( bool Vector ) const { if ( Vector


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack ( MF


<s> if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI =


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= runOnMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; } return Modified


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( Val ) ; if ( ! LT . second . isVector (


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR (


<s> bool <ISA_LIT>ConstantIslands :: decrementCPEReferenceCount ( unsigned CPI , MachineInstr * CPEMI ) { CPEntry * CPE = findConstPoolEntry ( CPI , CPEMI ) ; assert ( CPE && <STR_LIT> ) ; if ( -- CPE -> RefCount == <NUM_LIT> ) { removeDeadCPEMI ( CPEMI ) ; CPE -> CPEMI


<s> static enum mips_split_type mips_insn_split_type ( rtx insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; if ( bb ) { if ( optimize_bb_for_speed_p ( bb )


<s> virtual bool hasRelocationAddend ( )


<s> bool IsTbx ; if ( isTblTbxInstruction ( MI -> getOpcode ( ) , Layout , IsTbx ) ) { O << <STR_LIT> << ( IsTbx ? <STR_LIT> : <STR_LIT> ) << Layout << '\t' << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> ) << <STR_LIT> ; unsigned ListOpNum = IsTbx ? <NUM_LIT> : <NUM_LIT> ; printVectorList ( MI , ListOpNum , STI , O , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( ListOpNum + <NUM_LIT> ) . getReg ( ) , <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } if ( const LdStNInstrDesc * LdStDesc = getLdStNInstrDesc ( Opcode ) ) { O << <STR_LIT> << LdStDesc -> Mnemonic <<


<s> switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } case <STR_LIT> : { StoreSDNode * SD = dyn_cast < StoreSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } } } AliasReg = CurDAG -> getRegister ( <STR_LIT> , TLI .


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT>


<s> EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple


<s> MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg (


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) return llvm :: make_unique < <ISA_LIT>_MachoTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return llvm ::

make_unique < <ISA_LIT>_COFFTargetObjectFile > ( ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ?


<s> struct mips_arg_info info ; if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = SFmode ; else if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , mode ,


<s> return <STR_LIT> ; case <STR_LIT> : return ( isReservedReg ( MF , <STR_LIT> ) || isReservedReg ( MF , <STR_LIT> ) ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return isReservedReg ( MF , <STR_LIT> ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return isReservedReg ( MF , <STR_LIT> ) ? <NUM_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) )


<s> struct machine_function * rs6000_init_machine_status ( void )


<s> ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o


<s> if ( isPreIncrementForm ( MI , AddOffset ) ) { OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT>


<s> bool getReserveFP ( ) const { return ReserveFP


<s> return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_<ISA_LIT>CTOR ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT>


<s> return ( uint8x8_t ) ( __a > <NUM_LIT>


<s> ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || NC -> getZExtValue ( ) != <NUM_LIT> ) return false ; Base = Offset = N ; return true


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef


<s> return ( __m128i ) __builtin_ia32_pmovzxbw128_mask ( ( __v16qi ) __A , ( __v8hi ) __W , (


<s> void <ISA_LIT>AsmParser :: emitInstruction ( MCInst & Inst , OperandVector &


<s> bool IsImmPreLdSt = IsPreLdSt && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! IsImmPreLdSt ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && ! IsPreLdSt ) { Register BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MI . modifiesRegister ( BaseReg , TRI ) ) return false ; } if ( isLdStPairSuppressed ( MI ) ) return false ; const MCAsmInfo * MAI = MI . getMF ( ) -> getTarget ( ) . getMCAsmInfo ( ) ; bool NeedsWinCFI = MAI -> usesWindowsCFI ( ) && MI . getMF ( ) -> getFunction ( ) . needsUnwindTableEntry ( ) ; if ( NeedsWinCFI && ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( T == AM . Segment ) ; AM . Segment = Copy ; EVT VT = N . getValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base_Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return false ; getAddressOperands ( AM , Base , Scale , Index , Disp


<s> if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> ,


<s> default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; } unsigned EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYSCALAR : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; MachineBasicBlock :: iterator InsertPoint = MI -> getNextNode ( ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI ->


<s> static scalar_int_mode aarch64_sve_element_int_mode ( machine_mode mode ) { poly_uint64 vector_bits = ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; unsigned int elt_bits = vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; return int_mode_for_size ( elt_bits , <NUM_LIT> ) .


<s> if ( i <= <NUM_LIT> && TARGET_THUMB2 && code == PLUS ) result = remainder ; else { end = i - <NUM_LIT> ; if ( end < <NUM_LIT> ) end += <NUM_LIT> ; result = remainder & ( ( <NUM_LIT> << end ) | ( ( i < end ) ? ( <NUM_LIT> >> ( <NUM_LIT> - end ) ) : <NUM_LIT> ) ) ; i -= <NUM_LIT> ; } } else { i -= TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ; continue ; } if ( TARGET_THUMB2 ) { b1 = ( remainder & <NUM_LIT> ) >> <NUM_LIT> ; b2 = ( remainder & <NUM_LIT> ) >> <NUM_LIT> ; b3 = ( remainder & <NUM_LIT> ) >> <NUM_LIT> ; b4 = remainder & <NUM_LIT> ; if ( loc > <NUM_LIT> ) { unsigned int tmp = b1 & b2 & b3 & b4 ; unsigned int tmp2 = tmp + ( tmp << <NUM_LIT> ) + ( tmp << <NUM_LIT> ) + ( tmp << <NUM_LIT> ) ; unsigned int matching_bytes = ( tmp == b1 ) + ( tmp == b2 ) + ( tmp == b3 ) + ( tmp == b4 ) ; if ( tmp && ( matching_bytes >= <NUM_LIT> || ( matching_bytes == <NUM_LIT> && const_ok_for_op ( remainder & ~ tmp2 , code ) ) ) ) { result = tmp2 ; i = tmp != b1 ? <NUM_LIT> : tmp != b2 ? <NUM_LIT> : tmp != b3 ? <NUM_LIT> : <NUM_LIT> ; } else if ( b1 == b3 && ( ! b2 || ! b4 || ( remainder & <NUM_LIT> & ~ result ) ) ) { result = remainder & <NUM_LIT> ; i = <NUM_LIT>


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; return BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , Zero , DAG , dl ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue EvenParts = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; EvenParts = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , EvenParts ) ; SDValue OddParts = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; OddParts = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OddParts ) ; int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ;


<s> if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget (


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) { rtx sub = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , <NUM_LIT> ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = <NUM_LIT> ; } return <NUM_LIT>


<s> return :: isUNPCKL_v_undef_Mask ( N -> getMask ( ) , N

-> getValueType ( <NUM_LIT> ) , HasAVX2 ) ;


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return __builtin_aarch64_qtbl4v16qi ( __o , (


<s> _Unwind_Word _Unwind_GetCFA ( _Unwind_Context * context ) { return ( ( phase1_vrs *


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return <NUM_LIT> ; } return BaseT :: getCFInstrCost ( Opcode , CostKind , I


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S ,


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinUnwindCode ( unsigned UnwindCode , int Reg , int Offset ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; auto Inst = WinEH :: Instruction ( UnwindCode , nullptr , Reg , Offset ) ; if ( InEpilogCFI ) CurFrame -> EpilogMap [ CurrentEpilog ]


<s> return ( __m64 ) __builtin_arm_wcmpeqw ( ( __v2si ) __m1 ,


<s> static Target The<ISA_LIT>V9Target ; return


<s> return ( __m128i ) __builtin_ia32_vpcomtrueb ( ( __v16qi ) __A , (


<s> case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC


<s> inline vector unsigned char vec_vaddubm ( vector unsigned char a1 , vector unsigned char a2 ) { return ( vector unsigned char ) __builtin_altivec_vaddubm ( ( vector signed

char ) a1 , ( vector signed char ) a2 ) ;


<s> pattern = PATTERN ( insn ) ; len = XVECLEN ( pattern , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < len ; i ++ ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , <NUM_LIT> ) ) ) ) return XEXP ( part , <NUM_LIT> ) ; } gcc_assert ( GET_CODE ( XVECEXP ( pattern , <NUM_LIT>


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false


<s> MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; SmallVector < MachineOperand , <NUM_LIT> > CondPrior ; MachineFunction :: iterator BBi = BB ; MachineFunction :: iterator OldPrior = std :: prev ( BBi ) ; bool B = TII -> AnalyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != MF -> begin ( ) && ! TII -> AnalyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Opc = <STR_LIT> ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } unsigned amt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Opc == <STR_LIT> && amt == <NUM_LIT> ) Opc = <STR_LIT> ; unsigned imm = <STR_LIT> ( Op , amt , Opc , idx_mode ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; } else { Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; unsigned tmp = <STR_LIT> ( Op , imm , <STR_LIT> , idx_mode ) ; Inst . addOperand ( MCOperand :: createImm ( tmp ) ) ; } if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst ,


<s> if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue


<s> unsigned regno ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && GET_MODE ( reg ) == DFmode ) ) ) ; else return NULL_RTX ; regno = REGNO (


<s> __o = __builtin_aarch64_ld2v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; return ret


<s> for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) addFixup (


<s> return __builtin_aarch64_sminpv4hi ( a


<s> unsigned PredCond = <STR_LIT> ( Pred ) ; unsigned PredHint = <STR_LIT> ( Pred ) ; if ( PredCond == <STR_LIT> ) return <STR_LIT> ( <STR_LIT> , PredHint ) ; if ( PredCond == <STR_LIT> ) return <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( Modifier && <STR_LIT> ) ; unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( StringRef ( Modifier ) == <STR_LIT> ) { switch ( ( <STR_LIT> ) Code ) { case <STR_LIT> : return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O


<s> qword q ; unsigned short s [ <NUM_LIT> ] ; } x


<s> if ( Op . isReg ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_MISC : if ( Op . isImm ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } return Match_InvalidOperand


<s> if ( frame_pointer_needed && regno >= HARD_FRAME_POINTER_REGNUM && regno < HARD_FRAME_POINTER_REGNUM + GET_MODE_SIZE ( Pmode ) ) return true ; if ( regno == RA_REGNUM && df_regs_ever_live_p ( RA_REGNUM ) ) return true ; if ( regno == RA_REGNUM + <NUM_LIT> && df_regs_ever_live_p ( RA_REGNUM + <NUM_LIT> ) ) return true ; return


<s> bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub = true ; } if ( InsertSub


<s> SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok . getString ( ) ; <STR_LIT> CC = parseCondCodeString ( Cond )


<s> UseOneConstNR = false ; unsigned Opcode = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Estimate = DAG . getNode ( Opcode , DL , VT , Op ) ; if ( RefinementSteps == <NUM_LIT> && ! Reciprocal ) Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Op , Estimate ) ; return Estimate ; } if ( VT . getScalarType ( ) == <STR_LIT> && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { assert ( Reciprocal && <STR_LIT> ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; if ( VT == <STR_LIT> ) { SDValue Zero = DAG . getIntPtrConstant (


<s> } else { lo_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , <NUM_LIT> ) ; hi_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , <NUM_LIT>


<s> if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op


<s> ParseExpression ( const MCExpr * & EVal ) { if ( isDarwin ( ) ) return ParseDarwinExpression ( EVal ) ; if ( getParser ( ) . parseExpression ( EVal ) ) return true ; EVal = FixupVariantKind (


<s> if ( INTVAL ( startop ) < <NUM_LIT> && INTVAL ( startop ) > <NUM_LIT> && ( INTVAL ( sizeop ) + INTVAL ( startop ) < <NUM_LIT> ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) > <NUM_LIT> ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) + INTVAL ( shiftop ) < <NUM_LIT> ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) + INTVAL ( shiftop ) >= <NUM_LIT> ) && ( <NUM_LIT> - ( INTVAL ( shiftop ) & <NUM_LIT> ) ) >= INTVAL ( sizeop ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this


<s> } if ( Idx == <NUM_LIT> && InVT . getSizeInBits ( ) <= <NUM_LIT> ) return Op ; if ( Size == <NUM_LIT> && Idx * InVT . getScalarSizeInBits ( ) == <NUM_LIT> && InVT . getSizeInBits ( ) == <NUM_LIT> ) return Op ; if ( useSVEForFixedLengthVectorVT ( InVT ) ) { SDLoc DL ( Op ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , InVT ) ; SDValue NewInVec = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Splice = DAG . getNode ( <STR_LIT> , DL , ContainerVT , NewInVec , NewInVec , DAG . getConstant ( Idx , DL , <STR_LIT> ) ) ; return convertFromScalableVector ( DAG , Op . getValueType ( ) , Splice ) ; } return SDValue ( )


<s> if ( type == <NUM_LIT> && ( align & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst , Insn


<s> if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { addPass ( & LiveVariablesID , false ) ; addPass ( create<ISA_LIT>TLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( create<ISA_LIT>TOCRegDepsPass ( )


<s> assert ( MI . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand MOpSHMI = MI . getOperand ( <NUM_LIT> ) ; MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; if ( SHMI + MEMI != <NUM_LIT> ) return false ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI -> getOpcode ( ) != <STR_LIT> && SrcMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MachineInstr * NewInstr = BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , SrcMI -> getOpcode ( ) == <STR_LIT> ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( SrcMI -> getOperand ( <NUM_LIT> ) ) . add ( MOpSHMI ) ; ( void )


<s> if ( ! satisfies_constraint_Is14 ( index ) ) return false ; } if ( ! cfun -> machine -> strict_aligned_p ) return true ; else if ( NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) return true ; } break ; case <NUM_LIT> : if ( satisfies_constraint_Is17 ( gen_int_mode ( INTVAL ( index ) + <NUM_LIT> , SImode ) ) ) { if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) ) { if ( ! satisfies_constraint_Is14 ( index ) ) return false ; } if ( ! cfun -> machine -> strict_aligned_p ) return true ; else if ( NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) return true ; } break ; default : return false ; } return false ; case MULT : op0 = XEXP ( index , <NUM_LIT> ) ; op1 = XEXP ( index , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int multiplier ; multiplier = INTVAL ( op1 ) ; if ( multiplier != <NUM_LIT> && multiplier != <NUM_LIT> && multiplier != <NUM_LIT> && multiplier != <NUM_LIT> ) return false ; regno = REGNO ( op0 ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return


<s> bool isZero ( ) const { return K == ConstZero ||


<s> <ISA_LIT>_64GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ; assert ( got_entry != NULL


<s> static SDValue genConstMult ( SDValue X , APInt C , const SDLoc & DL , EVT VT , EVT ShiftTy , SelectionDAG & DAG ) { if ( C == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( C == <NUM_LIT> ) return X ; if ( C . isPowerOf2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( C . logBase2 ( ) , DL , ShiftTy ) ) ; unsigned BitWidth = C . getBitWidth ( ) ; APInt Floor = APInt ( BitWidth , <NUM_LIT> ) << C . logBase2 ( ) ; APInt Ceil = C . isNegative ( ) ? APInt ( BitWidth , <NUM_LIT> ) : APInt ( BitWidth , <NUM_LIT> ) << C . ceilLogBase2 ( ) ; if ( ( C - Floor ) . ule ( Ceil - C ) ) { SDValue Op0 = genConstMult ( X , Floor ,


<s> default : break ; case Match_Success : if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } while ( processInstruction ( Inst , Operands ) ) ; forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error (


<s> assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; unsigned OffsetIdx = MI . getNumExplicitOperands (


<s> unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; Binary |= getMachineOpValue ( MI , OpIdx ++ )


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! HasFP || ( hasStackRealignment ( MF ) && FrameIndex >= <NUM_LIT> ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; Register FrameReg = getFrameRegister ( MF ) ; if ( FrameIndex >= <NUM_LIT> ) { if ( hasBasePointer ( MF ) ) FrameReg = getBaseRegister ( ) ; else if ( hasStackRealignment ( MF ) ) FrameReg = <STR_LIT> ; } if ( ( isSPLSOpcode ( MI . getOpcode ( ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) || ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! Reg ) Reg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( Reg && <STR_LIT> ) ; bool HasNegOffset = false ; if ( Offset < <NUM_LIT> ) { HasNegOffset = true ; Offset = - Offset ; } if ( ! isInt < <NUM_LIT> > ( Offset ) ) { BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( static_cast < uint32_t > ( Offset ) >> <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( Offset & <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MI . getParent ( ) , II , DL , HasNegOffset ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg ) . addReg ( Reg ) . addImm ( LPCC :: ICC_T ) ; MI . eraseFromParent ( ) ; return ; } if ( isSPLSOpcode ( MI . getOpcode ( ) ) || isRMOpcode ( MI . getOpcode ( ) ) ) { MI . setDesc ( TII -> get ( getRRMOpcodeVariant ( MI . getOpcode ( ) ) ) ) ; if ( HasNegOffset ) { assert ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setImm (


<s> uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createImm ( Length + <NUM_LIT> )


<s> static bool lowerVectorFCMP ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIB ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCMP ) ; const auto & ST = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; if ( ! DstTy . isVector ( ) || ! ST . hasNEON ( ) ) return false ; const auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned EltSize = MRI . getType ( LHS ) . getScalarSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Splat = get<ISA_LIT>VectorSplat ( * MRI . getVRegDef ( RHS ) , MRI ) ; bool IsZero = Splat && Splat -> isCst ( ) && Splat -> getCst ( ) == <NUM_LIT> ; bool Invert ; <STR_LIT> CC , CC2 ; changeVectorFCMPPredTo<ISA_LIT>CC ( Pred , CC , CC2 , Invert ) ; bool NoNans = ST . getTargetLowering ( ) -> getTargetMachine ( ) . Options . NoNaNsFPMath ; MIB . setInstrAndDebugLoc ( MI ) ; auto Cmp = getVectorFCMP ( CC , LHS , RHS , IsZero , NoNans , MRI ) ; Register CmpRes ; if ( CC2 == <STR_LIT> ) CmpRes = Cmp ( MIB ) ; else { auto Cmp2 = getVectorFCMP ( CC2 , LHS , RHS , IsZero , NoNans , MRI ) ; auto Cmp2Dst = Cmp2 ( MIB


<s> translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_CC : mcInst . addOperand ( MCOperand :: createImm ( insn . immediates [ <NUM_LIT> ] ) ) ; return false ; case ENCODING_FP : translateFPRegister ( mcInst , insn . modRM & <NUM_LIT> ) ; return false ; case ENCODING_VVVV : translateRegister ( mcInst , insn . vvvv ) ; return false ; case ENCODING_DUP : return translateOperand ( mcInst , insn . operands [ operand . type - TYPE_DUP0 ] , insn ,


<s> if ( mode == BLKmode ) words = ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; else words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( ! targetm . calls . pass_by_reference ( & cum , mode , type , named ) && cum < MT_NUM_ARG_REGS && ( cum + words ) > MT_NUM_ARG_REGS ) { int bytes = ( MT_NUM_ARG_REGS - cum )


<s> if ( ! FixupBWInsts || skipFunction ( MF . getFunction ( ) ) ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; OptForSize = MF . getFunction ( ) . hasOptSize ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; LiveRegs . init ( TII ->


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , Micro<ISA_LIT>Enabled ( false ) , STI ( STI ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; Pic = MCA . getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ; uint64_t Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features & <STR_LIT> || Features & <STR_LIT> || Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features & <STR_LIT> )


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned FrameReg = <STR_LIT> ; unsigned stackBias = Subtarget -> getStackPointerBias ( ) ; SDValue FrameAddr ; if ( depth == <NUM_LIT> ) { FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; if ( Subtarget -> is64Bit ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( stackBias , dl ) ) ; return FrameAddr ; } SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? ( stackBias + <NUM_LIT> ) : <NUM_LIT> ; while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; FrameAddr = DAG . getLoad ( VT , dl , Chain , Ptr , MachinePointerInfo ( ) , false ,


<s> TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto BTI = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! BTI ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBTIHint ( BTI -> Encoding , Tok . getString ( ) ,


<s> putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , <STR_LIT> , c ) ; cur_pos += <NUM_LIT> ; } if ( cur_pos > <NUM_LIT> && i + <NUM_LIT> < len ) { cur_pos = <NUM_LIT> ; fprintf ( stream ,


<s> return ( poly64x1_t ) __builtin_neon_vreinterpretdiv4hi ( ( int16x4_t


<s> return IsRegInClass ( Reg , & <STR_LIT>


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; const TargetLowering * TLI = Subtarget -> getTargetLowering ( ) ; if ( TLI -> isConstTrueVal ( N1 . getNode ( ) ) && ( N0 -> getOpcode ( ) == <STR_LIT> || N0 -> getOpcode ( ) == <STR_LIT> ) ) { if ( CanInvertMVEVCMP ( N0 ) ) { SDLoc DL ( N0 ) ; <STR_LIT> CC = <STR_LIT> ( getVCMPCondCode ( N0 ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops


<s> if ( ! NeedCfg ) return false ; for ( auto & IPAndShapes : PosAndShapes ) addTileConfig ( IPAndShapes


<s> assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file ) ; } else assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , <NUM_LIT>


<s> O << <STR_LIT> << CPUDirectives [ Directive ] << '\n' ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind


<s> static unsigned getOffsetONFromFION ( const MachineInstr & MI , unsigned FIOperandNum ) { unsigned OffsetOperandNo = ( FIOperandNum == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNum - <NUM_LIT> ; return OffsetOperandNo


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) MF . getRegInfo ( ) . setPhysRegUsed ( RegInfo


) _MM_SET_ROUNDING_MODE ( unsigned int __mode ) {


<s> InsnType Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder


<s> SmallVector < MachineInstr * , <NUM_LIT> > BranchInstrs ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; <ISA_LIT>InstrInfo :: BranchType R = TII -> AnalyzeBranch ( MBB , TrueBB , FalseBB , Cond , false , BranchInstrs ) ; if ( ( R == <ISA_LIT>InstrInfo :: BT_None ) || ( R == <ISA_LIT>InstrInfo :: BT_NoBranch ) ) return std :: make_pair ( R , nullptr ) ; if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB


<s> bool IsAligned = Alignment == <NUM_LIT> || Alignment == MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , TLI . getPointerTy ( ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: max ( Alignment / <NUM_LIT> , <NUM_LIT> ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ; } if ( RegVT . isVector ( ) && RegVT . isInteger ( ) && Subtarget -> hasSSE2 ( ) && ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) { assert ( MemVT != RegVT && <STR_LIT> ) ; assert ( MemVT . isVector ( ) && <STR_LIT> ) ; unsigned NumElems = RegVT . getVectorNumElements ( ) ; unsigned MemSz = MemVT . getSizeInBits ( ) ; assert ( RegSz > MemSz && <STR_LIT> ) ; if ( Ext == <STR_LIT> && RegSz == <NUM_LIT> && ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( ! isPowerOf2_32 ( RegSz * MemSz *


<s> regno = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; if ( regno > <NUM_LIT> && regno != SP_REGNUM && regno != FP_REGNUM ) return ADDRESS_NOT_16BIT_FORMAT ; switch ( mode_test ) { case E_QImode : if ( val >= <NUM_LIT> && val < <NUM_LIT> && regno < <NUM_LIT> ) return ADDRESS_LO_REG_IMM3U ; break ; case E_HImode : if ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) && regno < <NUM_LIT> ) return ADDRESS_LO_REG_IMM3U ; break ; case E_SImode : case E_SFmode : case E_DFmode : if ( ( regno == <NUM_LIT> ) && ( val >= - <NUM_LIT> && val <= - <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) ) ) return ADDRESS_R8_IMM7U ; if ( ( regno == FP_REGNUM ) && ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) ) ) return ADDRESS_FP_IMM7U ; else if ( ( regno == SP_REGNUM ) && ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) ) ) return ADDRESS_SP_IMM7U ; else if ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val %


<s> return matchVectorAddressRecursively ( N , AM


<s> while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; op0 = XEXP ( cmp , <NUM_LIT> ) ; op1 = XEXP ( cmp , <NUM_LIT> ) ; if ( ! CONST_INT_P ( op1 ) || INTVAL ( op1 ) != <NUM_LIT> ) continue ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered )


<s> dumpProcResourceCounters ( ) ; if ( LastFPdOpCycleIdx != UINT_MAX ) dbgs ( ) << <STR_LIT> << LastFPdOpCycleIdx


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT . isVector ( ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) )


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) O << <STR_LIT> << MO2 . getImm


<s> OperandMatchResultTy parseADDR32 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegGR ,


<s> unsigned ShiftImm = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseMemRegOffsetShift ( ShiftTy , ShiftImm ) ) return MatchOperand_ParseFail ; E = Parser . getTok ( ) . getLoc ( ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePostIdxReg ( Reg , isAdd , ShiftTy , ShiftImm , S ,


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ; return SDValue


) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> return MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) .


<s> nregs = pcum -> aapcs_ncrn ; if ( ( nregs & <NUM_LIT> ) && arm_needs_doubleword_align ( mode , type ) ) nregs ++ ; } else nregs = pcum -> nregs ; if ( nregs < NUM_ARG_REGS ) * pretend_size

= ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } assert ( false && <STR_LIT> ) ; return <NUM_LIT>


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { static const TypeConversionCostTblEntry < <STR_LIT> > NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( encoding )


<s> rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , target , dup ) ) ; if ( recog_memoized ( insn ) < <NUM_LIT> ) { rtx_insn * seq ; start_sequence ( ) ; XEXP ( dup , <NUM_LIT> ) = force_reg ( GET_MODE_INNER ( mode ) , val ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >=