<s> if ( ! LPAC :: isPostOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) || ( Op2 . isExpr ( ) ) ) ) Value |= ( <NUM_LIT> << PBitShift ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Value &= ~ ( <NUM_LIT> <<


<s> assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize (


<s> SDValue Tmp = b . XOR ( A1 , A2 ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( A1 , A2


<s> else { args [ argno ] = convert_to_pmode ( args [ argno ] ) ; vector_type = displacement_vector_type ( ) ; if ( units == UNITS_elements && ! scaled_p ) shift_idx = argno + <NUM_LIT> ; } tree scalar_displacement_type = TREE_TYPE ( vector_type ) ; if ( shift_idx >= <NUM_LIT> ) { machine_mode arg_mode = GET_MODE ( args [ shift_idx ] ) ; if ( arg_mode == VOIDmode ) arg_mode = DImode ; unsigned int elt_bytes = GET_MODE_UNIT_SIZE ( mem_mode ) ; rtx shift = gen_int_mode ( exact_log2 (


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) Binary |= encodeVFPRn ( MI , OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( )

|| MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) ) ; MVT SVT = VT . getVectorElementType ( ) ; MVT InSVT = InVT . getVectorElementType ( ) ; assert ( SVT . getSizeInBits ( ) > InSVT . getSizeInBits ( ) ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) && ! ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) && ! ( VT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int InSize = InSVT . getSizeInBits ( ) * VT . getVectorNumElements ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , dl , std :: max ( InSize , <NUM_LIT> ) ) ; } assert ( ( Op . getOpcode ( ) != <STR_LIT> || InVT == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( ExtOpc , dl , VT , In ) ; assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType ( ) != <STR_LIT> ) { Curr = DAG . getNode ( <STR_LIT> , dl , CurrVT , DAG . getUNDEF ( CurrVT ) , Curr ) ; MVT CurrSVT = <STR_LIT> ( CurrVT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; CurrVT = <STR_LIT> ( CurrSVT , CurrVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Curr = DAG . getBitcast ( CurrVT , Curr ) ; } SDValue SignExt = Curr ; if ( CurrVT != InVT ) { unsigned SignExtShift = CurrVT . getScalarSizeInBits ( ) - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr

, DAG . getConstant ( SignExtShift , dl , <STR_LIT> ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; const unsigned PtrByteSize = Subtarget . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ; CCInfo . AllocateStack ( LinkageSize , PtrByteSize ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_AIX ) ; const unsigned MinParameterSaveAreaSize = <NUM_LIT> * PtrByteSize ; const unsigned NumBytes = LinkageSize + MinParameterSaveAreaSize ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; for ( CCValAssign & VA : ArgLocs ) { SDValue Arg = OutVals [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; if ( VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } if ( ! isTailCall && ! isPatchPoint && ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { const MCRegister TOCBaseReg = Subtarget . getTOCPointerRegister ( ) ; const MCRegister StackPtrReg = Subtarget . getStackPointerRegister (


<s> unsigned PredReg = <NUM_LIT> ; DebugLoc dl = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } MachineInstrBuilder MIBuilder = BuildMI ( Block , MBIter , dl , TII -> get ( <STR_LIT> ) ) ; MachineInstr * LastMI = MI ; MachineBasicBlock :: iterator InsertPos = MIBuilder . getInstr ( ) ; MIBuilder . addImm ( VPTMaskValue :: T ) ; finalizeBundle ( Block , InsertPos . getInstrIterator ( ) ,


<s> if ( REG_P ( x1 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( REGNO ( x1 ) ) ] ) ; if ( REG_P ( x2 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( REGNO ( x2 ) ) ] ) ; return ; } else if ( satisfies_constraint_I ( x2 ) ) { output_addr_const ( stream , x2 ) ; return ; } } } if ( TARGET_BASE_ADDRESSES && mmix_legitimate_constant_p ( Pmode


<s> std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addReg ( CondReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor


<s> void <ISA_LIT>InstrInfo :: setExecutionDomain ( MachineInstr * MI , unsigned Domain ) const { assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> )


<s> if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } } return true


<s> Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT>


<s> bool <STR_LIT> ( SDNode * N ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( <STR_LIT> ( N , N -> getNumOperands ( ) ) ) if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( N ) ) return CFP -> getValueAPF ( ) . isNegZero ( ) ; return


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return hasFP ( MF )


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( )

> DefaultSafeSPDisplacement ) return true ;


<s> static DecodeStatus DecodeBankedReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( ( R << <NUM_LIT> ) | SysM ) )


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle


<s> return Subtarget . hasVLX ( ) || ( Subtarget . hasAVX512 (


<s> assert ( OpVT == <STR_LIT> || ( OpVT == <STR_LIT> ) ) ; EVT floatVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Op . getValueType ( ) == <STR_LIT> && ( ! hasHardQuad || ! TLI . isTypeLegal ( OpVT ) ) ) { const char * libName = TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: SINTTOFP_I32_F128 : RTLIB :: SINTTOFP_I64_F128 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( OpVT


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? d -> nelt : <NUM_LIT> ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * <NUM_LIT> + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen =


<s> if ( ! DCI . isBeforeLegalizeOps ( ) ) { if ( InVT == <STR_LIT> ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , VT ) ; return DAG . getSelect ( DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI ,


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; MVT VT = SVOp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane


<s> void <ISA_LIT>AIXAsmPrinter :: emitPGORefs ( ) { if ( OutContext . hasXCOFFSection ( <STR_LIT> , XCOFF :: CsectProperties ( XCOFF :: XMC_RW , XCOFF :: XTY_SD ) ) ) { MCSection * CntsSection = OutContext . getXCOFFSection ( <STR_LIT> , SectionKind :: getData ( ) , XCOFF :: CsectProperties ( XCOFF :: XMC_RW , XCOFF :: XTY_SD ) , true ) ; OutStreamer -> SwitchSection ( CntsSection ) ; if ( OutContext . hasXCOFFSection ( <STR_LIT> , XCOFF :: CsectProperties ( XCOFF ::

XMC_RW , XCOFF :: XTY_SD ) ) ) OutStreamer -> emitXCOFFRefDirective ( <STR_LIT> ) ;


<s> for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return - <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind


<s> unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = <ISA_LIT>FrameInfo :: getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize (


<s> rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls .

split_complex_arg ) return rs6000_complex_function_value ( mode ) ;


<s> bool has<ISA_LIT>32 ( ) const { return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 ,


<s> if ( ! TREE_PUBLIC ( decl ) || DECL_COMMON ( decl ) || DECL_INITIAL ( decl ) == NULL_TREE || DECL_INITIAL ( decl )

== error_mark_node || ( flag_zero_initialized_in_bss && initializer_zerop ( DECL_INITIAL ( decl ) ) ) ) return ;


<s> HOST_WIDE_INT disp = spill_fill_data . prev_off [ iter ] - cfa_off ; rtx disp_rtx = GEN_INT ( disp ) ; rtx mem ; if ( spill_fill_data . prev_addr [ iter ] ) { if ( satisfies_constraint_N ( disp_rtx ) ) { * spill_fill_data . prev_addr [ iter ] = gen_rtx_POST_MODIFY ( DImode , spill_fill_data . iter_reg [ iter ] , gen_rtx_PLUS ( DImode , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; add_reg_note ( spill_fill_data . prev_insn [ iter ] , REG_INC , spill_fill_data . iter_reg [ iter ] ) ; } else { if ( ! satisfies_constraint_I ( disp_rtx ) ) { rtx tmp = gen_rtx_REG ( DImode , next_scratch_gr_reg ( ) ) ; emit_move_insn ( tmp , disp_rtx ) ; disp_rtx = tmp ; } emit_insn ( gen_adddi3 ( spill_fill_data . iter_reg [ iter ] , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; } } else if ( disp == <NUM_LIT> && spill_fill_data . init_reg [ iter ] == stack_pointer_rtx && frame_pointer_needed ) { mem = gen_rtx_MEM ( GET_MODE ( reg ) , hard_frame_pointer_rtx ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; return mem ; } else { rtx seq ; rtx_insn * insn ; if ( disp == <NUM_LIT> ) seq = gen_movdi ( spill_fill_data . iter_reg [ iter ] , spill_fill_data . init_reg [ iter ] ) ; else { start_sequence ( ) ; if ( ! satisfies_constraint_I ( disp_rtx )


<s> if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT> ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , <NUM_LIT> ) ) ; } else if ( GET_CODE ( addr


<s> ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps


<s> return Printer . GetExternalSymbolSymbol ( MO . getSymbolName


<s> void EmitARM64WinCFISaveFRegP ( unsigned Reg ,


<s> <ISA_LIT>LegalizerInfo :: FCmpLibcallsList <ISA_LIT>LegalizerInfo :: getFCmpLibcalls ( CmpInst :: Predicate Predicate ) const { assert ( CmpInst :: isFPPredicate ( Predicate ) && <STR_LIT> ) ; return FCmp32Libcalls [ Predicate


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizeMathLibCalls


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory

. BaseRegNum ) || Memory . Alignment != <NUM_LIT> ) return false ;


<s> offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; fpr_mode = ( TARGET_SINGLE_FLOAT ? SFmode : DFmode ) ; for ( regno = FP_REG_LAST - MAX_FPRS_PER_FMT + <NUM_LIT> ; regno >= FP_REG_FIRST ; regno -= MAX_FPRS_PER_FMT ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { if ( ! TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT && ( fixed_regs [ regno ] || fixed_regs [ regno + <NUM_LIT> ] ) ) { if ( fixed_regs [ regno ] ) mips_save_restore_reg ( SFmode , regno + <NUM_LIT>


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; unsigned RegSize = MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) ; bool Is32Bit = ( RegSize == <NUM_LIT> ) ; const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI


<s> if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p


<s> rtx tmp2 = gen_reg_rtx ( XFmode ) ; rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , <NUM_LIT> ) , XEXP ( test , <NUM_LIT> ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx (


<s> __inline__ static double sh_media_FMOV_QD ( long


<s> emitRX ( Opcode , DstReg , MCOperand :: createImm ( Imm ) , IDLoc


<s> if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode (


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( const SDValue & Elt : N -> op_values ( ) ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned HalfSize = EltSize /


<s> return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 ,


<s> SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( ) , ResNo ) ) ; } std :: vector < SDValue > VLDDupResults ; for ( unsigned n = <NUM_LIT> ; n < NumVecs ; ++ n ) VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , n ) ) ; VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , NumVecs ) ) ; DCI . CombineTo ( VLD , VLDDupResults ) ; return true


<s> if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; if ( OpStr == <STR_LIT> ) Size = <NUM_LIT> ; return


. types . register_builtin_type ( ix86_float16_type_node , <STR_LIT> ) ;


<s> void aarch64_addti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = gen_lowpart ( DImode , op1 ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode


<s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( Arg . getValueSizeInBits ( ) / <NUM_LIT> , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy (


<s> return ( ( vec_uint4 ) ( si_clz ( ( qword ) ( a ) )


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM . add ( create<ISA_LIT>BranchSelectionPass (


<s> sh_treg_combine :: sh_treg_combine ( gcc :: context * ctx , bool split_insns , const char * name ) : rtl_opt_pass ( default_pass_data , ctx )


<s> assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable1 ) , std :: end ( MemoryFoldTable1 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable1 ) , std :: end ( MemoryFoldTable1 ) ) == std :: end ( MemoryFoldTable1 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable2 ) , std :: end ( MemoryFoldTable2 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable2 ) , std :: end ( MemoryFoldTable2 ) ) == std :: end ( MemoryFoldTable2 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable3 ) , std :: end ( MemoryFoldTable3 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable3 ) , std :: end ( MemoryFoldTable3 ) ) == std :: end ( MemoryFoldTable3 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable4 ) , std :: end ( MemoryFoldTable4 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable4 ) , std :: end ( MemoryFoldTable4 ) ) == std :: end ( MemoryFoldTable4 ) && <STR_LIT> ) ; FoldTablesChecked . store ( true , std :: memory_order_relaxed ) ; } const <ISA_LIT>MemoryFoldTableEntry * Data = std :: lower_bound ( Table . begin ( ) , Table . end ( ) , RegOp ) ; if ( Data != Table . end ( ) && Data -> KeyOp == RegOp && ! ( Data -> Flags & TB_NO_FORWARD ) ) return Data ; return


<s> case <STR_LIT> : return ELF :: R_MIPS_PC21_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PC26_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_GPRel_4 : if ( isN64 ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( Op ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( )


<s> Value * <ISA_LIT>IREmitter :: visitREP_MOVS (


<s> unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst

. addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF


<s> advanceTo ( MachineBasicBlock :: iterator NextBegin ) { MachineBasicBlock :: iterator LastEmittedMI = HazardRec -> getLastEmittedMI ( ) ; MachineBasicBlock :: iterator I = ( ( LastEmittedMI != nullptr && LastEmittedMI -> getParent ( ) == MBB ) ? std :: next ( LastEmittedMI ) : MBB -> begin ( ) ) ; for ( ; I != NextBegin ; ++ I ) { if ( I -> isPosition ( ) || I ->


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseImm ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Tilde


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm (


<s> static bool rx_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return to == FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM


<s> if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return NULL ; } switch ( Opcode ) { default : break ; case <STR_LIT> : { SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , TFI


<s> bool MLxExpansion :: ExpandFPMLxInstructions ( MachineBasicBlock & MBB ) { bool Changed = false ; clearStack ( ) ; IgnoreStall . clear ( ) ; unsigned Skip = <NUM_LIT> ; MachineBasicBlock :: reverse_iterator MII = MBB . rbegin ( ) , E = MBB . rend ( ) ; while ( MII != E ) { MachineInstr * MI = & * MII ; if ( MI -> isPosition ( ) || MI -> isImplicitDef ( ) || MI -> isCopy ( ) ) { ++ MII ; continue ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> isBarrier


<s> AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineDominatorTree >


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) ) return genConstMult ( N -> getOperand ( <NUM_LIT> )

, C -> getZExtValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ;


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_long_type_node ) return <STR_LIT> ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE (


<s> bool isFPVectorizationPotentiallyUnsafe ( ) { return ! ST -> isTargetDarwin (


<s> if ( vr4130_swap_insns_p ( ready [ nready - <NUM_LIT> ] , ready [ nready - <NUM_LIT> ] ) ) mips_promote_ready ( ready , nready - <NUM_LIT> ,


<s> static __inline qword si_shlh ( qword a , qword b ) { vec_ushort8 mask ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( ( vec_ushort8 ) ( b ) , vec_splat_u16 (

<NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>ShortenInst :: shortenFPConv ( MachineInstr & MI , unsigned Opcode ) { if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MachineOperand Dest ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Src ( MI . getOperand (


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( )


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N


<s> __vector signed char b ; b = ( __vector signed char ) vec_splats ( __b ) ; return ( __m64 ) ( ( __vector long long ) b ) [ <NUM_LIT> ] ; __m64_union res ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ]


<s> static void aarch64_parse_arch ( void ) { char * ext ; const struct processor * arch ; char * str = ( char * ) alloca ( strlen ( aarch64_arch_string ) + <NUM_LIT> ) ; size_t len ; strcpy ( str , aarch64_arch_string ) ; ext = strchr ( str , '+' ) ; if ( ext != NULL ) len = ext - str ; else len = strlen ( str ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> , str ) ; return ; } for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , str , len ) == <NUM_LIT> ) { selected_arch = arch ; aarch64_isa_flags = selected_arch -> flags ; if ( ! selected_cpu ) selected_cpu = & all_cores [ selected_arch -> core ] ; if ( ext != NULL ) { aarch64_parse_extension ( ext


<s> unsigned ADDu = <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < ABI . EhDataRegSize ( ) ;


<s> case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_N1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm7_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm11_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed : case Match_UImm16_AltRelaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm16 : case Match_SImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm19_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm20_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm26_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm32 : case Match_SImm32_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm32_Coerced : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm9 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm10 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm10Lsl1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm10Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm10Lsl3 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_MemSImm11


<s> return new <ISA_LIT>ALFWriter ( nullptr , nullptr


<s> unsigned OpNo = Op . getNode ( ) -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue N0 = Op . getOperand ( OpNo ) ; MVT SrcVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; switch ( SrcVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT>


<s> return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT>


<s> if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) ; if ( StrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear (


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( t1 , x )


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , MRI . getDwarfRegNum ( Reg , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> static unsigned getV4<ISA_LIT>ShuffleImm ( ArrayRef < int > Mask ) { assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT>


<s> assert ( ( Kind == k_Memory ) && <STR_LIT> ) ; return Mem .


<s> return ( ( AM3Opc >> <NUM_LIT> ) & <NUM_LIT> ) ?


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : STI ( STI ) , MII ( MII ) , UC ( Parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT>


<s> if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI , JTBB ,


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! FuncInfo -> isLeafProc (


<s> return ( __m256i ) __builtin_ia32_pmovsxbw256 ( ( __v16qi


<s> void addImm1_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> SDValue M0F = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Mask0F ) ; SmallVector < SDValue , <NUM_LIT> > Four ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FourV = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Four ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ; SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , M0F ) ; SDValue HighPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , HighNibbles ) ; SDValue LowPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , LowNibbles ) ; SDValue PopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , HighPopCnt , LowPopCnt ) ; if ( EltVT == <STR_LIT>


<s> MRI = & MF . getRegInfo ( ) ; SchedModel . init ( ST . getSchedModel ( ) , & ST , TII ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB


<s> if ( VT == <STR_LIT> ) { AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } getAddressOperands ( AM , SDLoc ( N ) , VT , Base , Scale ,


<s> } Parser . Lex ( ) ; <STR_LIT> FpABI ; if ( ! parseFpABIValue ( FpABI , <STR_LIT> ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT>


<s> static bool f64AssignAAPCS ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , CCState & State , bool CanFail ) { static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , ShadowRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned


<s> TargetIRAnalysis <ISA_LIT>BaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } )


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( ) ; clearRegisterClasses ( ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) set<ISA_LIT>16HardFloatLibCalls ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> } if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { op0 = gen_lowpart ( V16QImode , op0 ) ; op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_movdqu ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_SSE_SPLIT_REGS ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { if ( TARGET_SSE_PARTIAL_REG_DEPENDENCY ) emit_move_insn ( op0 , CONST0_RTX ( mode ) ) ; else emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; if ( mode != V4SFmode ) op0 = gen_lowpart ( V4SFmode , op0 ) ; m = adjust_address ( op1 , V2SFmode , <NUM_LIT> ) ; emit_insn ( gen_sse_loadlps ( op0 , op0 , m ) ) ; m = adjust_address ( op1 , V2SFmode , <NUM_LIT> ) ; emit_insn ( gen_sse_loadhps ( op0 , op0 , m ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( optimize_size ) { op0 = gen_lowpart ( V4SFmode , op0 ) ; op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_movups ( op0 ,


<s> void <ISA_LIT>InstPrinter :: printHexImm ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; O << format ( <STR_LIT> , Op


<s> if ( isBitwiseNot ( Op0 ) ) return SDValue ( ) ; if ( ! SupportedVectorShiftWithImm ( VT0 . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) return SDValue ( ) ; unsigned EltBitWidth = VT0 . getScalarSizeInBits ( ) ; if ( EltBitWidth != DAG . ComputeNumSignBits ( Op0 ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned ShiftVal = SplatVal . countTrailingOnes ( ) ; SDValue ShAmt = DAG . getConstant ( EltBitWidth - ShiftVal , DL ,


<s> case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [


<s> if ( N -> getMaskElt ( <NUM_LIT> ) % EltSize != <NUM_LIT> ) return false ; unsigned ElementBase = N -> getMaskElt ( <NUM_LIT> ) ; if ( ElementBase >= <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != EltSize ; ++ i ) if ( N -> getMaskElt ( i ) < <NUM_LIT> || N -> getMaskElt ( i

) != ( int ) ( i + ElementBase ) ) return false ;


<s> StringRef getToken ( ) const { assert ( Kind == k_Token && <STR_LIT> ) ; return StringRef ( Tok . Data ,


<s> assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ; if ( HasSecRelSymbolRef ( Bin -> getLHS ( ) ) || HasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind (


<s> LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) const { if ( ! Subtarget -> is<ISA_LIT>1 ( ) ) return Op ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CCReg = AddLiveIn ( MF , <STR_LIT> , <STR_LIT> ) ; SDValue Chain = DAG . getEntryNode ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue CondReg = DAG . getCopyFromReg ( Chain , dl , CCReg , <STR_LIT> ) ; CondReg = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , CondReg ) ; CondReg = DAG . getCopyFromReg ( CondReg , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CondReg


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) -


<s> rtx memt = assign_stack_temp ( TImode , <NUM_LIT> ) ; emit_move_insn ( memt , SUBREG_REG ( in ) ) ; return adjust_address ( memt , mode , <NUM_LIT> ) ; } else if ( force && GET_CODE ( in ) == REG ) { rtx memx = assign_stack_temp ( mode ,


<s> static const MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target


<s> unsigned EltSize = VT . getScalarSizeInBits ( ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT )


_pdep_u32 ( unsigned int __X , unsigned int __Y ) {


<s> MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( T . get<ISA_LIT>CPUForArch ( Arch ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitArch ( ID ) ; return


<s> OperandMatchResultTy parseBDXAddr64 ( OperandVector


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> SDLoc DL ( N ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! TrueC || ! FalseC ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Cond . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt & TrueVal = TrueC -> getAPIntValue ( ) ; const APInt & FalseVal = FalseC -> getAPIntValue (


<s> Op -> Kind = k_MemoryReg ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = offsetReg ; Op -> Mem . Off = nullptr ; return


<s> case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { EVT Ty = Op . getValueType ( ) ; if ( Ty == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; } else if ( Ty . isVector ( ) && Ty . isInteger ( ) && isTypeLegal ( Ty ) ) { return DAG . getNode ( <STR_LIT> , dl , Ty , Op . getOperand ( <NUM_LIT> ) ) ; } else { report_fatal_error ( <STR_LIT> ) ; } } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> )


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumResultVecs + <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; for ( unsigned i = AddrOpIdx + <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemIntrinsicSDNode * MemInt = cast < MemIntrinsicSDNode > ( N ) ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOpc , N -> getDebugLoc ( ) , SDTys , Ops . data ( ) , Ops . size ( ) , MemInt -> getMemoryVT ( ) , MemInt -> getMemOperand ( ) ) ; std :: vector < SDValue > NewResults ; for ( unsigned i = <NUM_LIT> ; i < NumResultVecs ; ++ i ) { NewResults . push_back ( SDValue ( UpdN . getNode ( ) , i ) ) ; } NewResults . push_back ( SDValue ( UpdN . getNode ( ) , NumResultVecs + <NUM_LIT>


<s> Register FramePtr = TRI -> getFrameRegister ( MF ) ; Register MachineFramePtr = Is64BitILP32 ? Register ( get<ISA_LIT>SubSuperRegister ( FramePtr , <NUM_LIT> ) ) : FramePtr ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsWin64CFI = IsWin64Prologue && MF . getFunction ( ) . needsUnwindTableEntry ( ) ; bool IsFunclet = MBBI == MBB . end ( ) ? false : isFuncletReturnInstr ( * MBBI ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t MaxAlign = calculateMaxStackAlign ( MF ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; unsigned TailCallArgReserveSize = - <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; bool HasFP = hasFP ( MF ) ; uint64_t NumBytes = <NUM_LIT> ; bool NeedsDwarfCFI = ( ! MF . getTarget ( ) . getTargetTriple ( ) . isOSDarwin ( ) && ! MF . getTarget ( ) . getTargetTriple ( ) . isOSWindows ( ) ) && MF . needsFrameMoves ( ) ; if ( IsFunclet ) { assert ( HasFP && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; } else if ( HasFP ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize - TailCallArgReserveSize ; if ( TRI -> hasStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; } else { NumBytes = StackSize - CSSize - TailCallArgReserveSize ; } uint64_t SEHStackAllocAmt = NumBytes ; MachineBasicBlock :: iterator AfterPop = MBBI ; if ( HasFP ) { if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { int Offset = <NUM_LIT> + mergeSPUpdates ( MBB , MBBI , true ) ; emitSPUpdate ( MBB , MBBI , DL , Offset , true ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , MachineFramePtr ) . addUse ( MachineFramePtr ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( NeedsDwarfCFI ) { unsigned DwarfStackPtr = TRI -> getDwarfRegNum ( Is64Bit ? <STR_LIT> : <STR_LIT> , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfa ( nullptr , DwarfStackPtr , SlotSize ) ) ; if ( ! MBB . succ_empty ( ) &&


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocRegOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocReg ( Reg , S


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr


) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; MCInstLowering . Lower ( & * I ,


<s> TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; if ( ! EnableEncodeLiterals ) return false ; for ( auto & MBB : MF ) { unsigned Index = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , E = MBB . end ( ) ; MI != E ; ++ MI , ++ Index ) { if ( isStoreLocalValue ( * MI ) ) { obfuscateLiteralOperand ( MF , * MI


<s> IRBuilder < > Builder ( InsertAtEnd ) ; Type * I64Ty = Builder . getInt64Ty ( ) ; Value * SP = Builder . CreatePtrToInt ( StackPtr , I64Ty ) ; SP = Builder . CreateAdd ( SP , Builder . CreateZExtOrBitCast ( StackSize , I64Ty ) ) ; SP = Builder . CreateSub ( SP , Builder . getInt64 ( <NUM_LIT> ) ) ; Builder . CreateStore ( Builder . getInt ( APInt :: getAllOnesValue ( <NUM_LIT> ) ) , Builder . CreateIntToPtr ( SP , I64Ty -> getPointerTo ( ) ) ) ; auto InitRegTo = [ & ] ( unsigned RegNo , Value * Val ) { unsigned RegLargestSuper = getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ RegNo ] ; assert ( RegLargestSuper == RegNo ) ; unsigned RegOffsetInSet = getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet


<s> tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( attr ) ; attr = TREE_VALUE ( TREE_VALUE ( attr ) ) ; return ( TREE_CODE ( attr ) == STRING_CST && strcmp ( TREE_STRING_POINTER ( attr ) ,


<s> NumRLInsts += SelectRotMask64Count ( BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , ! FirstBG ) ; FirstBG = false ; } DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << ( VRI . Repl32 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << NumAndInsts << <STR_LIT> << NumRLInsts << <STR_LIT> ) ; if ( NumAndInsts > NumRLInsts ) continue ; if ( Use32BitInsts && NumAndInsts == NumRLInsts ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ) VRot = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; else VRot = VRI . V ; SDValue TotalVal ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; } else { TotalVal = SDValue ( SelectInt64 ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , TotalVal ) , <NUM_LIT> ) ; } if ( ! Res ) Res


<s> static machine_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode


<s> MachineJumpTableInfo * JTI = MF . getJumpTableInfo ( ) ; if ( JTI != NULL ) { const std :: vector < MachineJumpTableEntry > & JT = JTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> ; i < JT . size ( ) ; ++ i ) { const std :: vector < MachineBasicBlock * > &


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend

& MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack ) {


<s> Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel


<s> OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE (


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex


<s> In<ISA_LIT>16HardFloat = true ; } PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM == Reloc ::


<s> bool Is64bit = ( DestVT == <STR_LIT> ) ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned QuotReg = fastEmitInst_rr ( DivOpc , RC , Src0Reg , Src1Reg ) ; assert ( QuotReg && <STR_LIT> ) ; unsigned ResultReg = fastEmitInst_rrr ( MSubOpc , RC ,


<s> unsigned IncrementIndex = StartIndex == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Phi -> addIncoming ( NewIndex , Phi -> getIncomingBlock ( StartIndex ) ) ; Phi -> addIncoming ( Phi -> getIncomingValue ( IncrementIndex ) , Phi -> getIncomingBlock ( IncrementIndex


<s> if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) && <STR_LIT> ( Imm ) != - <NUM_LIT> ) return true ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasFP64 ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; return false


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || CurSlots == <NUM_LIT> ) { CurGroup . clear ( ) ; CurSlots = CurBranches


<s> SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ) ) ; } if ( VT == <STR_LIT> && Subtarget . is64Bit ( ) && ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { APInt HiMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( N -> getOperand ( <NUM_LIT> ) , HiMask ) || DAG . MaskedValueIsZero ( N -> getOperand ( <NUM_LIT> ) , HiMask ) ) { SDLoc dl ( N ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ) ; } } if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; SmallVector < APInt , <NUM_LIT> > SrcPartials ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps , & SrcPartials ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT>


<s> unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; updateValueMap ( I ,


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } TypeSize Scale = TypeSize :: Fixed ( <NUM_LIT> ) ; unsigned Width ; int64_t MinOffset , MaxOffset ; bool Success = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getMemOpInfo ( NewOpc , Scale , Width , MinOffset , MaxOffset ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; if ( MBBI -> getOperand ( MBBI -> getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || CSStackSizeInc < MinOffset || CSStackSizeInc > MaxOffset ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( CSStackSizeInc ) , TII , InProlog ? MachineInstr :: FrameSetup : MachineInstr :: FrameDestroy ) ; return std :: prev ( MBBI ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % Scale == <NUM_LIT> ) ; MIB . addImm ( CSStackSizeInc /


<s> if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return <NUM_LIT> ; unsigned RHSReg ; if ( ! LHSReg


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue


<s> unsigned j = <NUM_LIT> ; if ( attr & RS6000_BTC_QUAD && d -> code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL && d -> code != VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) j = <NUM_LIT> ; for ( ; j < ( unsigned ) insn_data [ icode ] . n_operands ; j ++ ) { machine_mode mode = insn_data [ icode ] . operand [ j ] . mode ; if ( gimple_func && mode == XOmode ) op [ nopnds ++ ] = build_pointer_type ( vector_quad_type_node ) ; else if ( gimple_func && mode == OOmode && d -> code == VSX_BUILTIN_ASSEMBLE_PAIR ) op [ nopnds ++ ] = build_pointer_type ( vector_pair_type_node ) ; else op [ nopnds ++ ] = builtin_mode_to_type [ mode ] [ <NUM_LIT> ] ; } } switch ( nopnds ) { case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [


<s> if ( Elem >= VT . getVectorNumElements ( ) ) return false ; auto * Load = dyn_cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Load || ! Load -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( Load -> getMemoryVT ( ) . getSizeInBits ( ) != Load -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return false ; SDValue Base , Disp , Index ; if ( ! selectBDVAddr12Only ( Load -> getBasePtr ( ) , ElemV , Base , Disp , Index ) || Index . getValueType ( ) != VT . changeVectorElementTypeToInteger ( ) ) return false ; SDLoc DL ( Load ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL , <STR_LIT> ) , Load -> getChain ( ) } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , DL


<s> return aarch64_classify_vector_mode ( mode )


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasThumb2DSP ) { if ( Flags . empty ( ) ) return <NUM_LIT> | ( int ) hasThumb2DSP ; return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case

( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( DAG . ComputeMinSignedBits ( Op0 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( DAG . ComputeMinSignedBits ( Op1 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op0 . getOperand ( <NUM_LIT> ) ) && Op0 . hasOneUse ( ) && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDVTList VTs = DAG . getVTList ( CmpVT , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; return Add . getValue ( <NUM_LIT> ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . hasOneUse ( ) && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDVTList VTs = DAG . getVTList ( CmpVT , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 . getOperand ( <NUM_LIT> ) ) ; return Add . getValue (


<s> int intregs , intoffset ; machine_mode mode ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode


<s> } else if ( type == long_long_unsigned_type_node || type == long_long_integer_type_node ) error ( <STR_LIT> <STR_LIT> ) ; else if ( type == double_type_node ) error ( <STR_LIT> ) ; } switch ( altivec_type ) { case 'v' : unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case TImode : result = ( unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node ) ; break ; case DImode : result = ( unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node ) ; break ; case SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case SFmode : result = V4SF_type_node ; break ; case DFmode : result = V2DF_type_node ; break ; case V4SImode : case V8HImode : case V16QImode : case V4SFmode : case V2DImode : case V2DFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case DImode : case V2DImode : result = bool_V2DI_type_node ; break ; case SImode : case V4SImode : result = bool_V4SI_type_node ; break ; case HImode : case V8HImode :


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) )


<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getResNo ( ) == <NUM_LIT> && N0 . getValueType


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) || ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) ) OS << <STR_LIT> ; else if ( Kind != MCSymbolRefExpr :: VK_None )


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent (


<s> if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end (


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( )


<s> inline tree function_instance :: displacement_vector_type (


<s> auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType


<s> BB -> addSuccessor ( copy0MBB ) ; } BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( sinkMBB ) ; } copy0MBB -> addSuccessor ( sinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = sinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * sinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( copy0MBB ) . addReg ( Op2Reg ) . addMBB ( thisMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } if ( CascadedCMOV ) { MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( jcc1MBB ) ; BuildMI ( * sinkMBB , std :: next ( MachineBasicBlock :: iterator ( MIB . getInstr ( ) ) ) , DL , TII -> get ( TargetOpcode :: COPY ) , CascadedCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CascadedCMOV -> eraseFromParent ( ) ; } for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) ( MIIt ++ ) -> eraseFromParent ( ) ; return sinkMBB


<s> unsigned EltSize = EltTy . getSizeInBits ( ) ; if ( tryOptConstantBuildVec ( I , DstTy , MRI ) ) return true ; if ( tryOptBuildVecToSubregToReg ( I , MRI ) ) return true ; if ( EltSize < <NUM_LIT> || EltSize > <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; MachineInstr * ScalarToVec = emitScalarToVector ( DstTy . getElementType ( ) . getSizeInBits ( ) , DstRC , I . getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; if ( ! ScalarToVec ) return false ; Register DstVec = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstSize = DstTy . getSizeInBits ( ) ; MachineInstr * PrevMI = nullptr ; for ( unsigned i = <NUM_LIT> , e = DstSize / EltSize + <NUM_LIT> ; i < e ; ++ i ) { PrevMI = & * emitLaneInsert ( None , DstVec , I . getOperand ( i ) . getReg ( ) , i - <NUM_LIT> , RB , MIB ) ; DstVec = PrevMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( DstSize < <NUM_LIT> ) { const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DstVec , MRI , TRI ) , DstSize ) ; if ( ! RC ) return false ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( RC , TRI , SubReg ) ) return false ; if ( SubReg != <STR_LIT> && SubReg != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << DstSize << <STR_LIT> ) ; return false ; } Register Reg = MRI . createVirtualRegister ( RC ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB . buildInstr ( TargetOpcode :: COPY , { DstReg } , { } ) . addReg ( DstVec , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( Reg ) ; RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } else { assert ( PrevMI && <STR_LIT> ) ; PrevMI -> getOperand ( <NUM_LIT> ) . setReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; constrainSelectedInstRegOperands ( * PrevMI , TII , TRI , RBI ) ; } I . eraseFromParent ( ) ; return


<s> getUImm5Lsl2Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { uint64_t Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res >> <NUM_LIT> ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; return


<s> void <ISA_LIT>AsmParser :: createCpRestoreMemOp ( bool IsLoad , int StackOffset , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; if ( IsLoad ) { TOut . emitLoadWithImmOffset ( <STR_LIT> , <STR_LIT> , <STR_LIT> , StackOffset ,


<s> return ( vcall_offset >= - <NUM_LIT> ||


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return I -> getFlag ( MachineInstr :: FrameSetup ) ||

I -> getFlag ( MachineInstr :: FrameDestroy ) ;


<s> return MI . isCall ( ) || ( ! MI . isPseudo ( ) &&


<s> State ( IES_PLUS ) , PrevState ( IES_ERROR ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Imm ( imm ) , Sym ( <NUM_LIT> ) , StopOnLBrac ( stoponlbrac ) , AddImmPrefix ( addimmprefix ) { Info . clear


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , * this , OptLevel , Verbose ) ) ; return false


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> for ( unsigned i = <NUM_LIT> , e = CallSeqStart . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( CallSeqStart . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( CallSeqStart , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Call . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Call . getOperand


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> has<ISA_LIT>64r6 ( ) ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue


<s> AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Define ) ; emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , VARegSaveSize ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; AddDefaultPred ( MIB ) ; MIB . copyImplicitOps ( & * MBBI ) ; MBB . erase ( MBBI


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( RegVT == Ins [ i ] . VT && <STR_LIT> ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ArgOffset = VA . getLocMemOffset ( ) ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint32_t BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; int FI = MFI -> CreateFixedObject ( ArgSize , ArgOffset + BEAlign , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue ArgValue ; <STR_LIT> ExtType = <STR_LIT> ; MVT MemVT = VA . getValVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : break ; case CCValAssign :: BCvt : MemVT = VA . getLocVT ( ) ; break ; case CCValAssign :: SExt : ExtType = <STR_LIT> ; break ; case CCValAssign :: ZExt : ExtType = <STR_LIT> ; break ; case CCValAssign :: AExt : ExtType = <STR_LIT> ; break ; } ArgValue = DAG . getExtLoad ( ExtType , DL , VA . getLocVT ( ) , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , MemVT , false , false , false , <NUM_LIT> , nullptr ) ; InVals . push_back ( ArgValue ) ; } } if ( isVarArg ) { if ( ! Subtarget -> isTargetDarwin ( ) ) { saveVarArgRegisters ( CCInfo , DAG , DL , Chain ) ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned StackOffset = CCInfo . getNextStackOffset ( ) ; StackOffset = ( ( StackOffset + <NUM_LIT> ) & ~ <NUM_LIT> ) ; AFI -> setVarArgsStackIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned StackArgSize = CCInfo . getNextStackOffset ( ) ; bool TailCallOpt = MF . getTarget ( ) . Options . GuaranteedTailCallOpt ; if ( DoesCalleeRestoreStack ( CallConv , TailCallOpt ) ) { StackArgSize = RoundUpToAlignment ( StackArgSize , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> static __inline vec_double2 spu_promote ( double a , int element ) { union { vec_double2 v ; double d [ <NUM_LIT> ] ; }


<s> uint64_t Imm ; if ( ! A64Imms :: isLogicalImmBits ( RegWidth , Bits , Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( Bits )