<s> case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> || ( TARGET_HAVE_MVE && nregs >= <NUM_LIT> ) ) templ = <STR_LIT> ; else templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; ops [ <NUM_LIT> ] = reg ; break ; } case PLUS : if ( GET_CODE ( addr ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; case LABEL_REF : { int i ; int overlap = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * i ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , DImode , <NUM_LIT> * i ) ; if ( reg_overlap_mentioned_p ( ops [ <NUM_LIT> ] , mem ) ) { gcc_assert ( overlap == - <NUM_LIT> ) ; overlap = i ; } else { if ( TARGET_HAVE_MVE && LABEL_REF_P ( addr ) ) sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; else sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } } if ( overlap != - <NUM_LIT> ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * overlap ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , SImode , <NUM_LIT> * overlap ) ; if ( TARGET_HAVE_MVE && LABEL_REF_P ( addr ) ) sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; else sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } return <STR_LIT> ; } default : gcc_unreachable ( ) ; } sprintf ( buff , templ , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; return <STR_LIT>


<s> return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> , <NUM_LIT>


<s> for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestHi . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredHi . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addOperand ( DesiredLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg )

. addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ;


<s> RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; default : return false ; } } else


<s> case k_Immediate : OS << <STR_LIT> ; OS << * Imm . Val ; OS << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> ; OS << Mem . Base ; OS << <STR_LIT> ; OS << * Mem . Off ; OS <<


<s> static <ISA_LIT>Operand * CreateExpr ( const MCExpr * Val , SMLoc S , SMLoc


<s> if ( Mask [ i ] == - <NUM_LIT> ) return false ; if ( Zeroable [ i ] ) continue ; if ( NextElement == - <NUM_LIT> ) { NextElement = Mask [ i ] != <NUM_LIT> ? VectorType . getVectorNumElements ( ) : <NUM_LIT> ; IsZeroSideLeft = NextElement != <NUM_LIT>


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned PC_ID = AFI -> createPICLabelUId ( ) ; MachineInstrBuilder PicADD = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( NotThumb ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( PC_ID ) . addImm ( Pred ) . addReg ( PredReg ) ; ( void ) PicADD ; LO16 = LO16 . addImm (


<s> const TargetInstrDesc & TID = get ( Opc ) ; const TargetOperandInfo & TOI = TID . OpInfo [ Index ] ; const TargetRegisterClass * RC = TOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( TOI . RegClass ) ; unsigned NumDefs = TID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <NUM_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { MVT VT = * RC -> vt_begin ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; Load = DAG . getTargetNode ( getLoadRegOpcode ( RC , isAligned ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; } std :: vector < MVT > VTs ; const TargetRegisterClass * DstRC = <NUM_LIT> ; if ( TID . getNumDefs ( ) > <NUM_LIT> ) { const TargetOperandInfo & DstTOI = TID . OpInfo [ <NUM_LIT> ] ; DstRC = DstTOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( DstTOI . RegClass ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++


<s> std :: tie ( SrcRC , DstRC ) = getRegClassesForCopy ( I , TII , MRI , TRI , RBI ) ; if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RBI . getSizeInBits ( DstReg , MRI , TRI ) << '\n' ) ; return false ; } bool KnownValid = false ; auto CheckCopy = [ & ] ( ) { assert ( ( I . isCopy ( ) || ( ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) && <STR_LIT> ) ; assert ( KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ) ; ( void ) KnownValid ; return true ; } ; if ( I . isCopy ( ) ) { if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; if ( SrcSize > DstSize ) { unsigned SubReg = <NUM_LIT> ; if ( getMinSizeForRegBank ( SrcRegBank ) > DstSize ) { const TargetRegisterClass * SubregRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; getSubRegForClass ( DstRC , TRI , SubReg ) ; MachineIRBuilder MIB ( I


<s> VectorType * ShuffleVecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * ShuffleEltTy = ShuffleVecTy -> getVectorElementType ( ) ; unsigned ShuffleElemSize = DL . getTypeSizeInBits ( ShuffleEltTy ) ; unsigned WideInstSize ; if ( ! Subtarget . hasAVX ( ) || ( Factor != <NUM_LIT> && Factor != <NUM_LIT> ) ) return false ; if ( isa < LoadInst > ( Inst ) ) { WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; if ( cast < LoadInst > ( Inst ) -> getPointerAddressSpace ( ) ) return false ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> && Factor == <NUM_LIT> ) return true ; if ( ShuffleElemSize == <NUM_LIT> && isa < StoreInst > ( Inst ) && Factor == <NUM_LIT> && ( WideInstSize

== <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) <NUM_LIT> ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult

( isSigned ) . setZExtResult ( ! isSigned ) ;


<s> return ( __mmask32 ) __builtin_ia32_ptestmb256 ( ( __v32qi ) __A ,


<s> assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF64Op ( Op , DAG , Op . getOpcode ( ) ) ; if ( Op . getValueType ( ) != <STR_LIT> ) return Op ; SDLoc dl ( Op ) ; SDValue SrcReg128 = Op . getOperand


<s> static bool CC_<ISA_LIT>_Assign_f64 ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) llvm_unreachable


<s> return DecodeMem ( Inst , insn , Address , Decoder ,


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass


<s> return requiresRegisterScavenging ( MF


<s> void <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT>


<s> MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; bool isThumb = AFI -> isThumbFunction ( ) ; <STR_LIT> Pred = isThumb ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Opc == <STR_LIT> ||


<s> if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next (


<s> switch ( VVPOpcode ) { case <STR_LIT> : \


<s> BBInfo . resize ( MF -> getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) computeBlockSize ( & * I ) ; adjustBBOffsetsAfter ( & MF -> front ( ) ) ; for ( MachineBasicBlock & MBB : * MF ) { if ( ! BBHasFallthrough ( & MBB ) ) WaterList . push_back ( & MBB ) ; for ( MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; int Opc = MI . getOpcode ( ) ; if ( MI . isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = false ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = false ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits =


<s> if ( IsSVEPrefetch ) { if ( auto Res = <STR_LIT> ( N ) ) return Optional < unsigned > ( Res -> Encoding ) ; } else if ( auto Res = <STR_LIT> ( N ) ) return Optional < unsigned > ( Res -> Encoding ) ; return Optional < unsigned > ( ) ; } ; auto LookupByEncoding = [ ] ( unsigned E ) { if ( IsSVEPrefetch ) { if ( auto Res = <STR_LIT> ( E ) ) return Optional < StringRef > ( Res -> Name ) ; } else if ( auto Res = <STR_LIT> ( E ) ) return Optional < StringRef > ( Res -> Name ) ; return Optional < StringRef > ( ) ; } ; unsigned MaxVal = IsSVEPrefetch ? <NUM_LIT> : <NUM_LIT> ; if ( parseOptionalToken ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Integer ) ) { const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > MaxVal ) { TokError ( <STR_LIT> + utostr ( MaxVal ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByEncoding ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM . getValueOr ( <STR_LIT> ) , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByName ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> )


<s> MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = <STR_LIT> ( EltTy , <NUM_LIT> * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( <STR_LIT> , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( <NUM_LIT> , DL ,


<s> void ThumbRegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: resolveFrameIndex ( MI , BaseReg , Offset ) ; const <ISA_LIT>BaseInstrInfo & TII = * STI . getInstrInfo ( ) ; int Off


<s> if ( flag_check_pointer_bounds ) warning ( <NUM_LIT> , <STR_LIT>


<s> TII . copyPhysReg ( MBB , I , DL , <STR_LIT> , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , <STR_LIT> , true ) ; return true


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> +

Subtarget . getCPUString ( ) + <STR_LIT> <STR_LIT> ) ;


<s> case k_Memory : delete Mem . Base ; break ; case k_RegList : delete RegList .


<s> EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( Subtarget . isABI_O32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue ,


<s> MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; if ( TT . isOSBinFormatCOFF ( ) ) return new


<s> static SDValue lowerVectorShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector (

) && ! VT . is256BitVector ( ) ) ) && <STR_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; Op = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , VT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT>


<s> const char * pic_name = reg_names [ REGNO ( pic_offset_table_rtx ) ] ; int align ; text_section ( ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_LABEL ( asm_out_file , pic_helper_symbol_name ) ; if ( flag_delayed_branch ) fprintf ( asm_out_file , <STR_LIT> , pic_name , pic_name ) ; else fprintf ( asm_out_file , <STR_LIT> ,


<s> return Op ; } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; SDLoc dl ( Op ) ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , CallOptions , dl , Chain ) ; return IsStrict ? DAG . getMergeValues ( { Result , Chain } , dl )


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { <ISA_LIT>TextSectOffset ++ ; if ( Name == <STR_LIT> ) Name = <STR_LIT> ; Name = StringSwitch < StringRef > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Name ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; Operands . push_back ( <STR_LIT> ( Head , NameLoc ) ) ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> :: COND_INVAL ) return Error ( SuffixLoc , <STR_LIT> ) ; const MCExpr * CC_Expr = MCConstantExpr :: create ( ( int64_t ) CC , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( CC_Expr , Parser . getTok ( ) . getLoc ( ) , SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> )


<s> rtx seq ; if ( PREV_INSN ( insn ) == NULL ) return <NUM_LIT> ; seq = NEXT_INSN ( PREV_INSN (


<s> static bool isMOVLHPSMask ( ArrayRef < int > Mask , EVT VT ) { if ( ! VT . is128BitVector ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual

( Mask [ i + e ] , i + NumElems ) ) return false ;


<s> return MO . isImm ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) || MO

. isGlobal ( ) || MO . isBlockAddress ( ) || MO . isMCSymbol ( ) ;


<s> return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , N -> getOffset (


<s> return ( __m256d ) __builtin_ia32_vfmaddpd256 ( - ( __v4df ) __A , (


<s> MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , EltInVec ,


<s> void emitSIBByte ( unsigned SS , unsigned Index , unsigned Base , unsigned & CurByte , raw_ostream & OS ) const { emitByte ( modRMByte ( SS , Index , Base ) , CurByte ,


<s> const TargetRegisterClass * <ISA_LIT>TargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == <STR_LIT> ) return & <STR_LIT> ; if ( VT == <STR_LIT> ) return & <STR_LIT> ; } return TargetLowering :: getRegClassFor


<s> if ( ElementWidth == <NUM_LIT> && Shift ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; Inst . addOperand ( MCOperand :: createImm ( Shift ) ) ; return Success


<s> static MCRegister convertFPR32ToFPR64 ( MCRegister Reg ) { assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT>


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int NumBytes , <STR_LIT> Pred , unsigned PredReg , bool isThumb , const TargetInstrInfo & TII , const <ISA_LIT>RegisterInfo & MRI , DebugLoc dl ) { if ( isThumb ) emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , <STR_LIT> , NumBytes , TII , MRI , dl ) ; else emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , <STR_LIT> , <STR_LIT> , NumBytes ,


<s> return ( int32x2_t ) __builtin_neon_vget_lowv4si (


<s> bool sh2a_function_vector_p ( tree func ) { tree list ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; list = SH_ATTRIBUTES ( func ) ; while ( list ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return true ; list = TREE_CHAIN (


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv4hi ( (


<s> return new <ISA_LIT>AsmBackend ( STI . getTargetTriple ( )


<s> StatepointOpers SOpers ( & MI ) ; if ( unsigned PatchBytes = SOpers . getNumPatchBytes ( ) ) { EmitNops ( * OutStreamer , PatchBytes , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } else { const MachineOperand & CallTarget = SOpers . getCallTarget ( ) ; MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm (


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { printS16ImmOperand ( MI , OpNo ) ; } else { if ( Subtarget . isDarwin ( ) ) O << <STR_LIT> ; printOp ( MI -> getOperand


<s> if ( isAllOnes ( Mask ) ) return Op ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CP , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT>


<s> return getSubExpr ( ) -> EvaluateAsRelocatable ( Res


_mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; Register OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; OpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , OpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return


<s> return __builtin_mve_vrmulhq_uv16qi ( __a ,


<s> MachineFunction :: const_iterator NextBlock = ++ Water -> getIterator ( ) ; if ( NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = Align ( <NUM_LIT> ) ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber (


<s> CurState = ST_DIRTY ; continue ; } if ( ! isControlFlow ) continue ; BBHasCall = true ; if ( CurState == ST_DIRTY ) { if ( EntryState != ST_UNKNOWN ) { BuildMI ( * MBB , I , dl , TII -> get ( <STR_LIT> ) ) ; ++ NumVZU ; } CurState = ST_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << BBNum << <STR_LIT> << CurState << '\n' ) ; if ( EntryState != ST_UNKNOWN || ( ! BBHasCall && CurState != ST_UNKNOWN ) ) BBSolved [ BBNum ] = true ; if ( CurState != BBState [ BBNum ] ) Changed = true ; BBState [ BBNum ] = CurState ; return


<s> temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4di ( ( __builtin_aarch64_simd_di * ) __a


<s> static SDValue PerformFNEGCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SVT = VT . getScalarType ( ) ; SDValue Arg = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) -> hasNoSignedZeros ( ) && Subtarget -> hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT


<s> return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false


<s> return gen_rtx_REG ( mode , MOXIE_R0


<s> static inline const char * getAMSubModeAltStr ( AMSubMode Mode , bool isLD ) { switch ( Mode ) { default : llvm_unreachable


<s> if ( ! ST -> hasDotProd ( ) || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( Op0 . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned ExtOpcode = Op0 . getOpcode ( ) ; if ( ExtOpcode != <STR_LIT> && ExtOpcode != <STR_LIT> ) return SDValue ( ) ; EVT Op0VT = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Op0VT != <STR_LIT> ) return SDValue


<s> static bool isValidVectorKind ( StringRef Suffix , RegKind


<s> F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ; } return ; } StringRef GuardMode = M . getStackProtectorGuard ( ) ; if ( ( GuardMode == <STR_LIT> || GuardMode . empty ( ) ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations


<s> rtx scale_rtx = NULL_RTX ; int i ; out -> base = out -> index = out -> symbol = out -> label = out -> disp = NULL_RTX ; out -> scale = <NUM_LIT> ; if ( REG_P ( addr ) ) { out -> base = addr ; return true ; } if ( GET_CODE ( addr ) == LABEL_REF ) { out -> label = addr ; return true ; } if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { rtx addends [ <NUM_LIT> ] , op ; addends [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; addends [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addends [ <NUM_LIT> ] ) == LABEL_REF && CONST_INT_P ( addends [ <NUM_LIT> ] ) ) { out -> label = addends [ <NUM_LIT> ] ; out -> disp = addends [ <NUM_LIT> ] ; return true ; } if ( ! REG_P ( addends [ <NUM_LIT> ] ) ) std :: swap ( addends [ <NUM_LIT> ] , addends [ <NUM_LIT> ] ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { op = addends [ i ] ; switch ( GET_CODE ( op ) ) { case REG : if ( ! base ) base = op ; else if ( ! index ) { index = op ; scale = <NUM_LIT> ; } else return false ; break ; case CONST_INT : case UNSPEC : if ( disp ) return false ; disp = op ; break ; case MULT : if ( index ) return false ; index = XEXP ( op , <NUM_LIT>


<s> OptionalArgs . push_back ( emitEHLSDA ( Builder , & F ) ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( Call . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallBase * NewCall ; if ( auto * CI = dyn_cast < CallInst > ( & Call ) ) { CallInst * NewCI = Builder . CreateCall ( SetJmp3 , Args , OpBundles ) ; NewCI -> setTailCallKind ( CI ->


<s> else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand ::


) _mm256_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: tryT2IndexedLoad ( SDNode * N ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; EVT LoadedVT = LD -> getMemoryVT ( ) ; bool isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode =


<s> rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return


<s> vec_uchar16 x ; x = vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ; return ( ( qword ) ( vec_sll ( ( vec_uchar16 )


<s> TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE && ! TARGET_XCOFF ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl ,


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> } else jump = emit_jump_insn_after ( gen_return ( ) , insn ) ; if ( optimize ) emit_barrier_after ( jump ) ; emit_label_after ( bp -> near_label , insn ) ; JUMP_LABEL ( jump ) = bp -> far_label ; ok = invert_jump ( insn , label , <NUM_LIT> ) ; gcc_assert ( ok


<s> static void InsertDAGNode ( SelectionDAG & DAG , SDValue Pos , SDValue N ) { if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId (

) > Pos . getNode ( ) -> getNodeId ( ) ) {


<s> void SLSBLRThunkInserter :: insertThunks ( MachineModuleInfo & MMI


<s> } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression


<s> void MCLDInitialize<ISA_LIT>LDTargetInfo ( ) { mcld :: RegisterTarget < llvm :: Triple :: arm > X


<s> if ( MFI -> hasVarSizedObjects ( ) || spillsCR ( MF ) || hasNonRISpills ( MF ) || ( hasSpills ( MF ) && ! isInt < <NUM_LIT> > ( StackSize ) ) ) { const TargetRegisterClass * GPRC


<s> if ( ! MF . getName ( ) . startswith ( getDerived ( ) . getThunkPrefix ( ) ) ) { if ( InsertedThunks ) return false ; if ( ! getDerived ( ) . mayUseThunk ( MF ) ) return false ; getDerived ( ) . insertThunks ( MMI ) ; InsertedThunks = true ; return true ; } getDerived ( ) . populateThunk ( MF


<s> return __builtin_ia32_rndscaleph512_mask_round ( __A , __B , _mm512_setzero_ph ( ) , ( __mmask32 )


<s> return ( __m128i ) __builtin_ia32_cvtpd2dq256_mask ( ( __v4df ) __A , ( __v4si ) _mm_setzero_si128 ( ) , (


<s> static bool isGRClass ( const TargetRegisterClass & RC ) { return RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT>

) || RC . hasSuperClassEq ( & <STR_LIT> ) ;


<s> bool <STR_LIT> ( SDValue Op , MVT EltVT , const <ISA_LIT>Subtarget & Subtarget , bool AssumeSingleUse ) { assert ( Subtarget . hasAVX (


<s> virtual void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const LLVM_OVERRIDE ; virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const LLVM_OVERRIDE ; virtual MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const LLVM_OVERRIDE { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const LLVM_OVERRIDE { return false ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return


<s> case <ISA_LIT>Subtarget :: O64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N32 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI : return <STR_LIT> ; default : break ; } llvm_unreachable (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getNumOperands ( ) != <NUM_LIT> || N1 . getNumOperands ( ) != <NUM_LIT> || ! N0 . getOperand ( <NUM_LIT> ) . isUndef ( ) || ! N1 . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > Mask ; int NumElts = VT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( int Elt : SVOp -> getMask ( ) ) Mask . push_back ( Elt < NumElts ? Elt : ( Elt - NumElts / <NUM_LIT> ) ) ; SDLoc DL ( N ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , N0

. getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) ) ;


<s> Optional < ParamLoadedValue > <ISA_LIT>BaseInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const { if ( auto DstSrcPair = isCopyInstrImpl (


<s> } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; StackOffset FPOffset = { ObjectOffset , <STR_LIT> } ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ; if ( ! UseFP && ( isFixed || isCSR ) ) ScalableOffset = SVEStackSize ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset ( FPOffset , <STR_LIT> ) + ScalableOffset ; } if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; if ( canUseRedZone ( MF ) ) Offset -= AFI -> getLocalStackSize ( ) ; } return StackOffset ( Offset ,


<s> gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) { tree parm ; for ( parm = DECL_ARGUMENTS ( fun ) ; parm && parm != void_list_node ; parm = TREE_CHAIN ( parm ) ) if ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( parm ) ) ) return true ; } else { function_args_iterator args_iter ; tree arg_type ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) if ( rs6000_parm_needs_stack ( args_so_far , arg_type ) ) return true ; } return false


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvt_roundsh_i32 ( __m128h __A , const int __R ) { return ( int ) __builtin_ia32_vcvtsh2si32_round (


<s> return ( float32x4_t ) __builtin_neon_vminfv4sf


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; buildCallOperands ( Ops , CallConv , dl , isTailCall , isVarArg , isPatchPoint , hasNest , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget , isIndirect ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { <STR_LIT> , <STR_LIT> } ; Chain = DAG . getNode ( CallOpc , dl , ReturnTypes , Ops ) ; Glue = Chain . getValue ( <NUM_LIT>


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op


<s> static unsigned loongarch_pass_mode_in_fpr_p ( machine_mode mode ) { if ( GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FP_ARG ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return <NUM_LIT> ; } return <NUM_LIT>


<s> if ( NumElts == <NUM_LIT> ) return true ; if ( NumElts == <NUM_LIT> && SVT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , SVT ) || isCommutedMOVLMask ( Mask , SVT , true ) || isSHUFPMask

( Mask , SVT ) || isSHUFPMask ( Mask , SVT , true ) ) ;


<s> static <ISA_LIT>Operand * CreateCoprocNum ( unsigned CopVal , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( CoprocNum ) ; Op -> Cop . Val = CopVal ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) { TS . emitDirectiveSetNoReorder ( ) ; TS . emitDirectiveSetNoMacro ( ) ; TS . emitDirectiveSetNoAt


<s> MachineSDNode :: mmo_iterator MemEnd = std :: copy ( Op0 -> memoperands_begin ( ) , Op0 -> memoperands_end ( ) , MemBegin ) ; MemEnd = std :: copy ( Op1 -> memoperands_begin ( ) , Op1 -> memoperands_end ( ) , MemEnd ) ; MI -> setMemRefs (


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addVecListTwoDOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return true


<s> unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Code == <NUM_LIT> ) O << <STR_LIT> ; else if ( Code == <NUM_LIT>


<s> const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign ,


<s> bool nds32_can_use_bitci_p ( HOST_WIDE_INT ival ) { return ( TARGET_ISA_V3 && ( ival < <NUM_LIT> ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~


<s> APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ,

ElementBits ) || SplatBitSize > ElementBits ) return false ;


<s> if ( needsAggressiveScheduling ( DarwinDirective ) ) { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } Policy . ShouldTrackPressure


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { Triple TT ( STI . getTargetTriple ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ; return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } } if ( ST -> getProcFamily ( ) != <ISA_LIT>Subtarget :: Others && ! ST -> getSchedModel ( ) . isOutOfOrder (


<s> static bool isSupportedCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode ==

<STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ) ;


<s> SDValue X = N0 . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Parity = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Parity ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Hi16 = DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; X = DAG . getNode ( <STR_LIT> , DL


<s> else if ( TARGET_SPE && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_SPE && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V2SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT


<s> Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return false ; } if ( HasExistingPersonality ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; return false ; } StringRef Name ( Parser . getTok ( ) . getIdentifier ( ) ) ; Parser . Lex ( ) ; MCSymbol * PR = getParser ( ) . getContext


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( InVT . isScalableVector ( ) ) return SDValue ( ) ; if ( Idx == <NUM_LIT> && isPackedVectorType ( InVT , DAG ) && Op . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return Op ; return SDValue ( )


<s> if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( std :: is_sorted ( std :: begin ( Groups ) , std :: end ( Groups ) ) && std :: is_sorted ( std :: begin ( RoundGroups ) , std :: end ( RoundGroups ) ) && std :: is_sorted ( std :: begin ( BroadcastGroups ) , std :: end ( BroadcastGroups ) ) && <STR_LIT> ) ; TableChecked . store ( true , std


<s> if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MAYBE_MASK_CLASS_P ( class1 ) != MAYBE_MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) ||

( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ;


<s> InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else


<s> aarch64_simd_builtins_initialized_p = true ; aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( ) ; tree lane_check_fpr = build_function_type_list ( void_type_node , size_type_node , size_type_node , intSI_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , AARCH64_SIMD_BUILTIN_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_builtin_data ) ; i ++ , fcode ++ ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] = { <NUM_LIT> } ; aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ op_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ op_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ op_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = aarch64_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d


<s> static DecodeStatus DecodetGPROddRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( ( RegNo ) + <NUM_LIT> > <NUM_LIT>


<s> x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber


<s> case <STR_LIT> : return LowerF64Op ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op ,


<s> bool <ISA_LIT>AsmParser :: shouldOmitVectorPredicateOperand ( StringRef Mnemonic , OperandVector & Operands ) { if ( ! hasMVE ( ) || Operands . size ( ) < <NUM_LIT> ) return true ; if ( Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) return true ; if ( Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) return false ; if ( Mnemonic . startswith ( <STR_LIT> ) && ! ( Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) ) { for ( auto & Operand : Operands ) { if ( static_cast < <ISA_LIT>Operand & > ( * Operand ) . isVectorIndex ( ) || ( ( * Operand ) . isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( ( * Operand ) . getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( ( * Operand ) . getReg ( ) ) ) ) ) { return true ; } } return false ; } else { for ( auto & Operand : Operands ) { if ( static_cast < <ISA_LIT>Operand & > ( * Operand ) . isVectorIndex ( ) || ( Operand -> isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operand -> getReg ( ) ) ) ) ) return false ; } return true


<s> return __builtin_mve_vmlsldavaq_sv4si ( __a ,


<s> assert ( OrigTy -> getPrimitiveSizeInBits ( ) < ExtTy -> getPrimitiveSizeInBits ( ) && <STR_LIT> ) ; this -> Visited = & Visited ; this -> Sources = & Sources ; this -> Sinks = & Sinks ; this -> SafeToPromote = & SafeToPromote ; for ( auto * I : Sinks ) { if ( auto * Call = dyn_cast < CallInst > ( I ) ) { for ( unsigned i = <NUM_LIT> ; i < Call -> getNumArgOperands ( ) ; ++ i ) { Value * Arg = Call -> getArgOperand ( i ) ; TruncTysMap [ Call ] . push_back ( Arg -> getType ( ) ) ; } } else if ( auto * Switch = dyn_cast < SwitchInst > ( I ) ) TruncTysMap [ I ] . push_back ( Switch -> getCondition ( ) -> getType ( ) ) ; else { for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) TruncTysMap [ I ] . push_back ( I -> getOperand ( i ) -> getType ( ) ) ; } } PrepareConstants ( ) ; ExtendSources ( ) ; ConvertTruncs ( ) ; PromoteTree ( ) ; TruncateSinks (


<s> const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; unsigned Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! MBB . getParent ( ) -> getFunction ( ) -> optForMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end


<s> assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ; MachineInstr * OpMI = MRI . getVRegDef


<s> Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = true ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . instr_end ( ) ) { MachineInstr & InstToDelete = * DI ; ++ DI ; if ( isSpeculationBarrierEndBBOpcode ( InstToDelete . getOpcode ( ) ) ) continue ; InstToDelete . eraseFromParent ( ) ; } } } if ( CantAnalyze


<s> NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . add ( predOps ( <STR_LIT> ) ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; for ( MCPhysReg L : LRs ) if ( ! MRI . isReserved ( L ) ) NewBB -> addLiveIn ( L ) ; MF -> RenumberBlocks ( NewBB ) ; BBUtils -> insert ( NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std ::


<s> rtx insn = emit_set_insn ( sr -> reg , gen_frame_mem ( SImode , addr ) ) ; rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( insn )


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , const DebugLoc & DL , MCRegister DestinationRegister , MCRegister SourceRegister , bool KillSource ) const { if ( ! <STR_LIT> . contains ( DestinationRegister , SourceRegister ) ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock (


<s> return ( __m64 ) __builtin_ia32_punpckhwd ( ( __v4hi ) __m1 ,


<s> Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , DebugLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT>


<s> for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal


<s> SmallVectorImpl < ForwardedRegister > & getForwardedMustTailRegParms ( ) { return


<s> bool <ISA_LIT>AsmPrinter :: isLongBranchPseudo ( int Opcode ) const { return ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ;


<s> return __builtin_mve_vsubq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; Register Reg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MachineInstr * Inst = MRI . getUniqueVRegDef ( Reg1 ) ) { if ( isConvertibleLEA ( Inst ) && Inst -> getParent ( ) == MI . getParent ( ) ) { Commute = true ; return true ; } } if ( MachineInstr * Inst = MRI . getUniqueVRegDef ( Reg2 ) ) { if ( isConvertibleLEA ( Inst ) && Inst -> getParent ( ) == MI . getParent


<s> MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current . first , Current . second ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( RealFnSym ) ; CurrentFnSymForSize =


<s> return ( mode == SImode || ( TARGET_64BIT &&


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG


<s> bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE =


<s> auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeProbability ( & B , Dst0 ) < Prob .


<s> rtx dst = ix86_fixup_binary_operands ( code , mode , operands ) ; gcc_assert ( dst == operands [ <NUM_LIT> ]


<s> std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = TM . getTargetData ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> :


<s> if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return


<s> bool isCortexA8 ( ) const { return <ISA_LIT>ProcFamily ==


<s> if ( ! selectAddress ( Addr , AM ) ) return false ; getAddressOperands ( AM , Addr . getValueType ( ) , Base ,


<s> bool <ISA_LIT>InstrInfo :: isMoveInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SrcSubIdx , unsigned & DstSubIdx ) const { SrcSubIdx = DstSubIdx = <NUM_LIT> ; unsigned oc = MI . getOpcode ( ) ; switch ( oc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 )


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) ; } SymToPrint = StubSym ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * SymToPrint ; else O << '(' << * SymToPrint << '(' ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; PrintPICBaseSymbol ( ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ; PrintPICBaseSymbol ( ) ; break ; case <STR_LIT> : O <<


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn )


<s> case RIT_<ISA_LIT>_64_GOT : Expr = MCSymbolRefExpr :: Create ( Sym , isPCRel ? MCSymbolRefExpr :: VK_GOTPCREL : MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case RIT_<ISA_LIT>_64_Subtractor : { RelocationRef RelNext ; Obj -> getRelocationNext ( Rel . getRawDataRefImpl ( ) , RelNext ) ; RelocationEntry RENext = Obj -> getRelocation ( RelNext . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != RIT_<ISA_LIT>_64_Unsigned ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = RelNext . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( RSym -> isVariable ( ) == false ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ; const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx


<s> case AARCH64_CMODEL_TINY_PIC : return SYMBOL_TINY_TLSIE ; default : return SYMBOL_SMALL_TLSIE ; } case TLS_MODEL_LOCAL_EXEC : if ( aarch64_tls_size == <NUM_LIT> ) return SYMBOL_TLSLE12 ; else if ( aarch64_tls_size == <NUM_LIT> ) return SYMBOL_TLSLE24 ; else if ( aarch64_tls_size == <NUM_LIT> ) return SYMBOL_TLSLE32 ; else if ( aarch64_tls_size == <NUM_LIT> ) return SYMBOL_TLSLE48 ; else gcc_unreachable ( ) ; case TLS_MODEL_EMULATED : case


<s> A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { const Value * V = CI -> getCalledValue ( ) ; Type * T = nullptr ; if ( V ) T = V -> getType ( ) ; PointerType * PFT = nullptr ; if ( T ) PFT = dyn_cast < PointerType > ( T ) ; FunctionType * FT = nullptr ; if ( PFT ) FT = dyn_cast < FunctionType > ( PFT


<s> case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5t ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case


<s> static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ;


<s> bool isVecListFourDAllLanes ( ) const { if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count ==


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( LoMask , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( HiMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( <STR_LIT> , DL , Lo , Hi , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT


<s> unsigned Bitwidth = Op . getScalarValueSizeInBits ( ) ; UsefulBits = APInt ( Bitwidth , <NUM_LIT> ) ; UsefulBits . flipAllBits ( ) ; } APInt UsersUsefulBits ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; for ( SDNode * Node : Op . getNode ( ) -> uses ( ) ) { APInt UsefulBitsForUse = APInt ( UsefulBits ) ; getUsefulBitsForUse ( Node , UsefulBitsForUse , Op , Depth ) ; UsersUsefulBits |=


<s> return __builtin_aarch64_simd_bslv2di_uuuu ( __a ,


<s> return ( uint8x16_t ) __builtin_neon_vrshluv16qi ( (


<s> vaba_s32 ( int32x2_t a , int32x2_t b , int32x2_t c ) { int32x2_t result


<s> return ( int16x4_t ) __builtin_neon_vminsv4hi ( __a ,


, <NUM_LIT> , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( NumElts * EltBits <= <STR_LIT> || <STR_LIT> % EltBits != <NUM_LIT> ) return ; unsigned NewNumElts = <STR_LIT> / EltBits ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , { NewNumElts , true } ) ; if ( ! isTypeLegal (


<s> return std :: make_pair ( domain , domain && lookup ( MI ->

getOpcode ( ) , domain ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> warning ( <NUM_LIT> , <STR_LIT> ) ; return ; } ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; if ( NO_PROFILE_COUNTERS ) { asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; } else if ( TARGET_SECURE_PLT && flag_pic ) { asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; assemble_name ( file , buf ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; assemble_name ( file , buf ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; } else if ( flag_pic == <NUM_LIT> ) { fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; assemble_name ( file , buf ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; } else if ( flag_pic > <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , buf ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; } else { asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; assemble_name ( file , buf ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; assemble_name ( file , buf ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; } fprintf ( file , <STR_LIT> , RS6000_MCOUNT , flag_pic


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] ,


<s> Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT>


<s> return TM -> Options . UseSoftFloat && !


<s> static SDValue combineSBB ( SDNode * N , SelectionDAG & DAG ) { if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } return SDValue ( )


<s> bool <ISA_LIT>DAGToDAGISel :: selectMOV64Imm32 ( SDValue N , SDValue & Imm ) { if ( const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , SDLoc ( N ) , <STR_LIT> ) ; return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return false ; Imm = N


<s> SDLoc DL ( Op ) ; unsigned CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCMask ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , DAG

. getConstant ( CCMask , <STR_LIT> ) , Dest , Flags ) ;


<s> RegUsageState RegUsage = RU_NotUsed ; MachineInstr * MI = I ; for ( unsigned int i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & opnd = MI -> getOperand ( i ) ; if ( opnd . isReg ( ) && opnd . getReg ( ) == p . getReg ( ) ) { if ( opnd . isDef ( ) ) return


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>PostLegalizerLoweringInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { CombinerHelper Helper ( Observer , B ) ; <ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg


<s> __inline__ static void sh_media_unaligned_ST_W ( void * p , unsigned int k ) { char * addr = p ; addr [ <NUM_LIT> ] =


<s> if ( ResVT . is128BitVector ( ) && ( InVT . is256BitVector ( ) || InVT . is512BitVector ( ) ) && isa < ConstantSDNode > ( Idx ) ) { return Extract128BitVector ( In , IdxVal , DAG , dl ) ; } if ( ResVT . is256BitVector ( ) && InVT . is512BitVector ( ) && isa < ConstantSDNode > (


<s> static MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>_32Disassembler (


<s> for ( auto & MI : MBB ) { MachineInstr * CurrInstr = & MI ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( PrevInstr ) { DEBUG ( dbgs ( ) << <STR_LIT> << * PrevInstr << <STR_LIT> << * CurrInstr << <STR_LIT> << isFirstInstructionInSequence ( PrevInstr ) << <STR_LIT> << <STR_LIT> << isSecondInstructionInSequence ( CurrInstr ) << <STR_LIT> ) ; if ( isFirstInstructionInSequence ( PrevInstr )

&& isSecondInstructionInSequence ( CurrInstr ) ) {


<s> static bool verifySymbol ( StringRef name ) { if ( name . equals ( <STR_LIT> ) ) return true ; if ( name . equals ( <STR_LIT> ) ) return true ; if ( name . equals ( <STR_LIT> ) ) return true ; LLVM_DEBUG ( wwarn << <STR_LIT>


<s> unsigned int i , isize = GET_MODE_SIZE ( imode ) ; if ( nvar < nelt ) mips_expand_vi_constant ( vmode , nelt , mem , vals ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx x = XVECEXP ( vals ,


<s> static void add_insn_window ( rtx_insn * insn , dispatch_windows * window_list , int num_uops ) { int byte_len = min_insn_size ( insn ) ; int num_insn = window_list -> num_insn ; int imm_size ; sched_insn_info * window = window_list -> window ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( ! window_list -> violation && group != disp_cmp && ! fits_dispatch_window ( insn


<s> HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX =


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getTLSCallPreservedMask ( ) const { if ( TT . isOSDarwin (

) ) return CSR_Darwin_<ISA_LIT>_TLS_RegMask ;


<s> if ( Opc == <STR_LIT> ) return <STR_LIT> ; else if ( Opc == <STR_LIT> ) return <STR_LIT> ; else if ( Opc ==


<s> } else { FuncOS << <STR_LIT> ; } FuncOS << <STR_LIT> ; for ( RegSaveOffset RO : RegSaveOffsets ) FuncOS << printFPOReg ( MRI , RO . Reg ) << <STR_LIT> << RO . Offset << <STR_LIT> ; CodeViewContext & CVCtx = OS . getContext ( ) . getCVContext ( ) ; unsigned FrameFuncStrTabOff = CVCtx . addToStringTable ( FuncOS . str ( ) ) . second ; unsigned MaxStackSize = <NUM_LIT> ; OS . emitAbsoluteSymbolDiff ( Label , FPO -> Begin , <NUM_LIT> ) ; OS . emitAbsoluteSymbolDiff ( FPO -> End ,


<s> Align StackAlign = LRI -> hasStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign


<s> SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <NUM_LIT> ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getWindowsStackProbePreservedMask ( ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Callee , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl ,


<s> } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; OpIdx += <NUM_LIT> ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; } return true


<s> MCA . registerSymbol ( * GP_Disp ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode (


<s> bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = <NUM_LIT> ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) return true ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable3 ; } if ( OpcodeTablePtr && OpcodeTablePtr -> count


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; if ( VT == <STR_LIT> ) return isShiftedMask_32 (


<s> const char * getModifier ( ) const { return Modifier


<s> int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT>


<s> break ; case MCK__HASH_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op


<s> MCTargetStreamer * llvm :: create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer (


<s> bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT>


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function *


<s> TargetRegistry :: RegisterCodeEmitter ( TheThumbTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterAsmBackend ( TheThumbTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterObjectStreamer (


<s> if ( ! GV ) { if ( const auto * CV = dyn_cast < Constant > ( MemAddr ) ) for ( const auto & CO : CV -> operands ( ) ) if ( memAddrUsesCTR ( TM , CO ) ) return true ; return false ; } if ( ! GV -> isThreadLocal ( ) ) return false ; TLSModel :: Model Model = TM . getTLSModel (


<s> return ( __m512i ) __builtin_ia32_broadcasti32x8_512_mask ( ( __v8si ) __A , (


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { if ( ExtVal . getValueType ( ) . isScalableVector ( ) ) return true ; return false


<s> extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_4 , & base_4 , & offset_4 ) ; if ( base_4 == NULL_RTX || offset_4 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) || ! rtx_equal_p ( base_2 , base_3 ) || ! rtx_equal_p ( base_3 , base_4 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; offval_3 = INTVAL ( offset_3 ) ; offval_4 = INTVAL ( offset_4 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( ( offval_1 != ( offval_2 + msize ) || offval_1 != ( offval_3 + msize * <NUM_LIT> ) || offval_1 != ( offval_4 + msize * <NUM_LIT> ) ) && ( offval_4 != ( offval_3 + msize ) || offval_4 != ( offval_2 + msize * <NUM_LIT> ) || offval_4 != ( offval_1 + msize * <NUM_LIT> ) ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) || reg_mentioned_p ( reg_2 , mem_2 ) || reg_mentioned_p ( reg_3 , mem_3 )


<s> static __inline unsigned long long sh_media_MADD_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode ( V2SI


<s> void WinEHStatePass :: addCXXStateStoresToFunclet ( Value * ParentRegNode , WinEHFuncInfo & FuncInfo , Function & F , int BaseState ) { Function * RestoreFrame = <STR_LIT> ( TheModule , <STR_LIT> ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( auto * CI = dyn_cast < CallInst > ( & I ) ) { if ( CI -> doesNotThrow ( ) ) continue ; insertStateNumberStore ( ParentRegNode , CI , BaseState ) ; } else if ( auto * II = dyn_cast < InvokeInst > (


<s> Type * RetTy = I -> getType ( ) ; if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) && Subtarget -> hasFP64 ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Op ) ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( DstVT , ResultReg ) ; if ( IntReg == <NUM_LIT> ) return false ; updateValueMap ( I , IntReg ) ; return


<s> static unsigned decodeVFPRn ( uint32_t insn , bool isSPVFP ) { return isSPVFP ? ( decodeRn ( insn ) << <NUM_LIT> | getNBit ( insn ) ) : ( decodeRn ( insn ) | getNBit ( insn )


<s> unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; O << * JTISymbol << <STR_LIT> ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset


<s> if ( isGPR64 < RegClassID > ( ) && getShiftExtendType ( ) == <STR_LIT> && getShiftExtendAmount (

) == Log2_32 ( ExtWidth / <NUM_LIT> ) ) return DiagnosticPredicateTy :: Match ;


<s> if ( parse_res == AARCH64_PARSE_OK ) return true ; switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_arch ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , invalid_extension . c_str ( ) , str