<s> operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , ( reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && const_zero_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; if ( REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG && ( mode == SFmode || ( mode == DFmode && ( reload_completed || reload_in_progress ) ) ) ) return false ; operands [ <NUM_LIT> ] = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ; if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = validize_mem ( operands [ <NUM_LIT> ] ) ; return false ; } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; switch ( mode ) { case QImode : break ; case HImode : case SImode : sparc_emit_set_const32 ( operands [ <NUM_LIT> ] , operands [


<s> enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm ->


<s> SmallVector < MachineInstr * , <NUM_LIT> > Phis ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( MI . getOpcode ( ) == TargetOpcode :: G_PHI ) Phis . emplace_back ( & MI ) ; } } for ( auto * MI : Phis ) { bool HasGPROp = false , HasFPROp = false ; for ( unsigned OpIdx = <NUM_LIT> ; OpIdx < MI -> getNumOperands ( ) ; ++ OpIdx ) { const auto & MO = MI -> getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarry_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) { return __builtin_ia32_addcarryx_u64 ( __CF , __X , __Y , __P


<s> return ( uint16x4_t ) __builtin_neon_vdup_lanev4hi ( ( int16x4_t


<s> if ( C -> getAPIntValue ( ) == <NUM_LIT> ) return EmitTest ( Op0 , <ISA_LIT>CC , DAG ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; } if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 ) ; return SDValue ( Sub . getNode


<s> if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ; if ( usesExtendedRegister ( MI ) ) return


<s> DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } else if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } return


<s> getSymbolForDwarfGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { SmallString < <NUM_LIT> > Name ; Mang -> getNameWithPrefix ( Name , GV , false ) ; const MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCExpr * Res = <ISA_LIT>MCTargetExpr :: Create ( Sym , <ISA_LIT>MCTargetExpr :: GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getSymbolForDwarfGlobalReference ( GV , Mang , MMI ,


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec =


<s> if ( ID == & TargetTransformInfo :: ID ) return


<s> return OC == <STR_LIT> || OC == <STR_LIT> || <STR_LIT> ( N .


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , fixup , Fixups , STI ) ; return isNeg ? - ( MO . getImm ( ) >> <NUM_LIT> )


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? &


<s> unsigned <ISA_LIT>MCCodeEmitter :: getT2AddrModeSORegOpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = get<ISA_LIT>RegisterNumbering ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT>


<NUM_LIT> ) + <NUM_LIT> ) * ( <NUM_LIT> << ( ( l1_szword & <NUM_LIT> ) >> <NUM_LIT> ) ) >> <NUM_LIT> ;


<s> unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( )


<s> static unsigned getLoadRegOpcode ( unsigned DestReg , const TargetRegisterClass * RC , bool isStackAligned , const TargetMachine & TM ) { return getLoadStoreRegOpcode ( DestReg , RC , isStackAligned


<s> case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case <STR_LIT>


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const Thumb1RegisterInfo & MRI , DebugLoc dl ) { MachineFunction & MF = * MBB . getParent ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) )


<s> } MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + Twine ( Name ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { Name . erase ( Name . end ( ) - <NUM_LIT> , Name . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( Name . str ( ) ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol (


<s> if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( MI -> definesRegister ( <STR_LIT> ) ) return true ; return


<s> NewImm = ( Imm | Ones ) & Mask ; if ( isShiftedMask_64 ( NewImm ) || isShiftedMask_64 ( ~ ( NewImm | ~ Mask ) ) ) break ; if ( EltSize == <NUM_LIT> ) return false ; EltSize /= <NUM_LIT> ; Mask >>= EltSize ; uint64_t Hi = Imm >> EltSize , DemandedBitsHi = DemandedBits >> EltSize ; if ( ( ( Imm ^ Hi ) & ( DemandedBits & DemandedBitsHi ) & Mask ) != <NUM_LIT> ) return false ; Imm |= Hi ; DemandedBits |= DemandedBitsHi ; } ++ NumOptimizedImms ; while ( EltSize < Size ) { NewImm |= NewImm << EltSize ; EltSize *= <NUM_LIT> ; } ( void ) OldImm ; assert ( ( ( OldImm ^ NewImm ) & Demanded . getZExtValue ( )


<s> assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { expandLoadAddressSym ( Inst , IDLoc , Instructions ) ; return false ; } const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> )


<s> rtx addr = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == LO_SUM && XEXP ( addr , <NUM_LIT> ) == pic_offset_table_rtx ) { rtx inner = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( inner ) == UNSPEC && XINT ( inner , <NUM_LIT> ) == UNSPEC_GOT ) return

XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF


<s> void <ISA_LIT>InstPrinter :: printVectorListThreeSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( )

+ <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) return ! PtrInOperand ? <STR_LIT> ( RegNo , Start , End ) : ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { return <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ; } } return <STR_LIT> ( Disp , Start , End ) ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) )


<s> bool isArgumentHandler ( ) const override { return true


<s> bool <ISA_LIT>TargetLowering :: isExtractSubvectorCheap ( EVT ResVT ,


<s> else if ( arm_carry_operation ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) ) ) return XEXP ( op , <NUM_LIT> ) ; return


<s> if ( ImmMO . isGlobal ( ) ) { const DataLayout & DL = ImmMO . getGlobal ( ) -> getParent ( ) -> getDataLayout ( ) ; if ( ImmMO . getGlobal ( ) -> getPointerAlignment ( DL ) < III . ImmMustBeMultipleOf ) return false ; } return true ; } if ( ImmMO . isImm ( ) ) { APInt ActualValue ( <NUM_LIT> , ImmMO . getImm ( ) + BaseImm , true ) ; if ( III . SignedImm && ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; if ( ! III . SignedImm && ! ActualValue . isIntN ( III . ImmWidth ) ) return false ; Imm = SignExtend64 < <NUM_LIT> > ( ImmMO . getImm ( ) + BaseImm ) ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; } else return


<s> if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI .


<s> src2 = operands [ <NUM_LIT> ] ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( reload_in_progress ) { gcc_assert ( code == PLUS ) ; emit_insn ( op ) ; } else if ( reload_completed && code == PLUS && ! rtx_equal_p ( dst , src1 ) ) { emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob ) ) ) ; } if ( dst != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ]


<s> unsigned Size = ( Ty -> isPtrOrPtrVectorTy ( ) ? <NUM_LIT> : Ty ->


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering . getPointerTy ( ) == <STR_LIT>


<s> } else if ( Tok . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || ! Mapper . validImm ( CE -> getValue ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return MatchOperand_Success ; } Error ( S , <STR_LIT> ) ; return


<s> unsigned ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; if ( InVT . getScalarSizeInBits ( ) <= <NUM_LIT> ) { if ( Subtarget . hasBWI ( ) ) { if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> unsigned MatchResult ; MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { default : break ; case Match_Success : if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } { bool wasInITBlock = inITBlock ( ) ; while ( processInstruction ( Inst , Operands ) ) ; if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) )


<s> getShiftRight16Imm ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op ) . getImm (


<s> static SDValue MarkEHGuard ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue EHGuard = Op . getOperand ( <NUM_LIT> ) ; WinEHFuncInfo * EHInfo = MF . getWinEHFuncInfo ( ) ; if ( ! EHInfo ) report_fatal_error ( <STR_LIT> ) ; auto * FINode = dyn_cast < FrameIndexSDNode > (


<s> bool <ISA_LIT>MIPeephole :: emitRLDICWhenLoweringJumpTables ( MachineInstr & MI ) { if ( MI . getOpcode ( ) != <STR_LIT> ) return false ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI -> getOpcode ( ) != <STR_LIT> ) return false ; MachineOperand MOpSHSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpMBSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpSHMI = MI . getOperand ( <NUM_LIT> ) ; MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHSrc . isImm ( ) && MOpMBSrc . isImm ( ) && MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHSrc = MOpSHSrc . getImm ( ) ; uint64_t MBSrc = MOpMBSrc . getImm ( ) ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; uint64_t NewSH = SHSrc + SHMI ; uint64_t NewMB = MBSrc - SHMI ; if ( NewMB > <NUM_LIT> || NewSH


<s> return llvm :: make_unique < <ISA_LIT>Operand >


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; } return


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SPE4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> .


<s> bool <ISA_LIT>BlockPlacement :: blockIsBefore ( MachineBasicBlock * BB , MachineBasicBlock * Other


<s> if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } if ( CFI != E ) { MachineBasicBlock * MBB = I -> getParent ( ) ; MBB -> splice ( std :: next ( MIB . getInstr ( ) -> getIterator ( ) ) , MBB , CFI ) ; } if (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & , const MCTargetOptions & ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return new <ISA_LIT>AsmBackend ( T , TT .


<s> VectorType * IntTy = VectorType :: getInteger ( cast < VectorType > ( V -> getType ( ) ) ) ; V = ConstantExpr :: getBitCast ( V , IntTy ) ; V = ConstantExpr :: getICmp ( CmpInst :: ICMP_SGT , Constant :: getNullValue


<s> auto MRSMapper = <STR_LIT> ( ) ; uint32_t MRSReg = MRSMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto MSRMapper = <STR_LIT> ( ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext


<s> int64_t LMMOffset = ( * LoadInst -> memoperands_begin ( ) ) -> getOffset ( ) ; int64_t SMMOffset = ( * StoreInst -> memoperands_begin ( ) ) -> getOffset ( ) ; int64_t LdDisp1 = LdDispImm ; int64_t LdDisp2 = <NUM_LIT> ; int64_t StDisp1 = StDispImm ; int64_t StDisp2 = <NUM_LIT> ; unsigned Size1 = <NUM_LIT> ; unsigned Size2 = <NUM_LIT> ; int64_t LdStDelta = StDispImm - LdDispImm ; for ( auto inst : BlockingStoresDisp ) { LdDisp2 = inst . first ; StDisp2 = inst . first + LdStDelta ; Size1 = std :: abs ( std :: abs ( LdDisp2 ) - std :: abs ( LdDisp1 ) ) ; Size2 = inst .


<s> unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> inline hashval_t bundle_state_hasher :: hash ( const value_type * state ) { unsigned result , i ; for ( result = i = <NUM_LIT> ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i % CHAR_BIT ) * <NUM_LIT> + CHAR_BIT ) ) ; return result + state ->


<s> MachineFunction :: iterator MBB = MF . begin ( ) ; MachineBasicBlock :: iterator I = MBB -> begin ( ) ; DebugLoc DL3 = I -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * MoveReturnToD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1

( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return ( __m256i ) __builtin_ia32_pmovzxwd256 ( ( __v8hi )


<s> bool <ISA_LIT>TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , bool Fast


<s> assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ;


<s> unsigned <ISA_LIT>SEInstrInfo :: getAnalyzableBrOpc ( unsigned Opc ) const { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned

? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ;


<s> bool hasVectorEnhancements2 ( ) const


<s> unsigned ExtendOp = is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op0 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ; if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ; if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op0 . getOperand ( <NUM_LIT> ) ) && Op0 . hasOneUse ( ) && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDVTList VTs = DAG . getVTList ( CmpVT , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; return Add . getValue ( <NUM_LIT> ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . hasOneUse ( ) && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDVTList VTs = DAG . getVTList ( CmpVT ,


<s> } } mnemonic = info . mvn ? <STR_LIT> : <STR_LIT> ; shift_op = info . msl ? <STR_LIT> : <STR_LIT> ; gcc_assert ( CONST_INT_P ( info . value ) ) ; if ( lane_count == <NUM_LIT> ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic , UINTVAL ( info . value ) ) ; else if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , shift_op , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic ,

lane_count , element_char , UINTVAL ( info . value ) ) ;


<s> else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( )


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return Success


<s> FuseKind = FuseTest ; break ; } switch ( FirstOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned JTOpIdx = NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j


<s> return DAG . getRegister ( FI -> getGlobalBaseReg ( ) , Ty


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( )


<s> if ( mode == CCFPmode && ( ! flag_finite_math_only || code == UNLT || code == UNLE || code == UNGT || code == UNGE ||

code == UNEQ || code == LTGT ) ) return reverse_condition_maybe_unordered ( code ) ;


<s> SmallVector < int , <NUM_LIT> > BlendMask ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) BlendMask . push_back ( i == IdxVal ? i + NumElts : i ) ; return DAG . getVectorShuffle ( VT , dl , N0 , N1SplatVec , BlendMask ) ; } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getIntPtrConstant ( IdxIn128 , dl ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( IdxVal == <NUM_LIT> && <STR_LIT> ( N0 . getNode ( ) ) ) { if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; MVT ShufVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , ShufVT , N1 ) ; N1 = getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; return DAG . getBitcast ( VT , N1 ) ; } } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } assert ( N1 . getValueType ( ) != <STR_LIT> && <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , DAG .

getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( MO . getImm ( )


<s> MachineInstr * <ISA_LIT>InstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { return


<s> bool hasCCDP ( ) const { return HasCCDP


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo (


<s> } } } uint64_t StackSize = MFFrame . getStackSize ( ) ; bool HasStackObject = false ; for ( unsigned i = <NUM_LIT> , e = MFFrame . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( ! MFFrame . isDeadObjectIndex ( i ) ) { HasStackObject = true ; break ; } if ( HasStackObject || MFFrame . hasCalls ( ) ) StackSize += <STR_LIT> ; StackSize = StackSize > <STR_LIT> ? StackSize - <STR_LIT> : <NUM_LIT> ; MFFrame . setStackSize ( StackSize ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; const unsigned ProbeSize = TLI . getStackProbeSize ( MF ) ; bool FreeProbe = ( ZFI -> getSpillGPRRegs ( ) . GPROffset && ( ZFI -> getSpillGPRRegs ( ) . GPROffset + StackSize ) < ProbeSize ) ; if ( ! FreeProbe && MF . getSubtarget ( ) . getTargetLowering ( ) -> hasInlineStackProbe ( MF ) ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addImm ( StackSize ) ; } else { emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; buildCFAOffs ( MBB , MBBI , DL , SPOffsetFromCFA + Delta , ZII ) ; } SPOffsetFromCFA += Delta ; if ( StoreBackchain ) { int Offset = usePackedStack ( MF ) ? <STR_LIT> - <NUM_LIT> : <NUM_LIT> ; BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; } } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; buildDefCFAReg ( MBB , MBBI , DL , <STR_LIT> , ZII ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode (


<s> if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; if ( isValueAvailable ( LHS ) ) if ( const auto * SI = dyn_cast < BinaryOperator > ( LHS ) ) if ( isa < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) if ( SI -> getOpcode ( ) == Instruction :: Shl ) std :: swap ( LHS , RHS ) ; unsigned LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = C -> getZExtValue ( ) ; ResultReg = emitLogicalOp_ri ( ISDOpc , RetVT , LHSReg , LHSIsKill , Imm ) ; } if ( ResultReg ) return ResultReg ; if ( isValueAvailable ( RHS ) ) if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) if ( SI -> getOpcode ( ) == Instruction :: Shl ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI -> getOperand ( <NUM_LIT> ) ) ; return emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftVal ) ; } unsigned RHSReg = getRegForValue (


<s> frame . spare_pred_reg = INVALID_REGNUM ; for ( regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) frame . reg_offset [ regno ] = SLOT_NOT_REQUIRED ; if ( crtl -> calls_eh_return ) for ( regno = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( regno ) != INVALID_REGNUM ; regno ++ ) frame . reg_offset [ EH_RETURN_DATA_REGNO ( regno ) ] = SLOT_REQUIRED ; for ( regno = R0_REGNUM ; regno <= R30_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ( regno == R30_REGNUM || ! crtl -> abi -> clobbers_full_reg_p ( regno ) ) ) frame . reg_offset [ regno ] = SLOT_REQUIRED ; for ( regno = V0_REGNUM ; regno <= V31_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) ) { frame . reg_offset [ regno ] = SLOT_REQUIRED ; last_fp_reg = regno ; if ( aarch64_emit_cfi_for_reg_p ( regno ) ) frame_related_fp_reg_p = true ; } if ( frame_related_fp_reg_p && crtl -> abi -> id ( ) == ARM_PCS_SVE && BYTES_BIG_ENDIAN ) { bitmap live1 = df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; bitmap live2 = df_get_live_in ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) ) ; for ( regno = P0_REGNUM ; regno <= P7_REGNUM ; regno ++ ) if ( ! bitmap_bit_p ( live1 , regno ) && ! bitmap_bit_p ( live2 , regno ) ) break ; gcc_assert ( regno <= P7_REGNUM ) ; frame . spare_pred_reg = regno ; df_set_regs_ever_live ( regno , true ) ; } for ( regno = P0_REGNUM ; regno <= P15_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) ) frame . reg_offset [ regno ] = SLOT_REQUIRED ; gcc_assert ( crtl -> is_leaf || maybe_ne ( frame . reg_offset [ R30_REGNUM ] , SLOT_NOT_REQUIRED ) ) ; for ( regno = P0_REGNUM ; regno <= P15_REGNUM ; regno ++ ) if ( known_eq ( frame . reg_offset [ regno ] , SLOT_REQUIRED ) ) { frame . reg_offset [ regno ] = offset ; offset += BYTES_PER_SVE_PRED ; } if ( maybe_ne ( offset , <NUM_LIT> ) ) { if ( last_fp_reg == ( int ) INVALID_REGNUM && offset . is_constant ( ) ) offset = aligned_upper_bound ( offset , STACK_BOUNDARY / BITS_PER_UNIT ) ; else { if ( known_le ( offset , vector_save_size ) )


<s> } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> static bool aarch64_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( aarch64_simd_decl_p ( cfun -> decl ) != aarch64_simd_decl_p ( decl ) ) return false ; return


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign ::


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF ::

SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> if ( MBBI == BeginMBBI ) return EndMBBI ; MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI -> isDebugInstr ( ) && PrevMBBI != BeginMBBI ) -- PrevMBBI ; Offset = isIncrementOrDecrement ( * PrevMBBI , Reg , Pred


<s> bool <ISA_LIT>BaseInstrInfo :: getRegSequenceLikeInputs ( const MachineInstr & MI , unsigned DefIdx , SmallVectorImpl < RegSubRegPairAndIdx > & InputRegs ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ; switch ( MI .


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return new <ISA_LIT>FastISel


<s> return ( __m128d ) __builtin_ia32_unpcklpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) , (


<s> PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexX1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth =


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> Value * Ptr = II . getOperand ( <NUM_LIT> ) ; Value * Mask = II . getOperand ( <NUM_LIT> ) ; Value * Vec = II . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantAggregateZero > ( Mask ) ) { IC . eraseInstFromFunction ( II ) ; return true ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) return false ; if ( Value * BoolMask = getBoolVecFromMask ( Mask ) ) { unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( Vec -> getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ; IC . Builder . CreateMaskedStore ( Vec , PtrCast , Align ( <NUM_LIT> ) ,


<s> auto CheckCopy = [ & ] ( ) { assert ( ( I . isCopy ( ) || ( ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) && <STR_LIT> ) ; assert ( KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ) ; return true ; } ; if ( I . isCopy ( ) ) { const TargetRegisterClass * SrcRC = getMinClassForRegBank ( SrcRegBank , RBI . getSizeInBits ( SrcReg , MRI , TRI ) , true ) ; if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRegBank . getID ( ) != SrcRegBank . getID ( ) ) { unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; if ( SrcSize > DstSize ) { const TargetRegisterClass * SubregRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; assert ( SubregRC && <STR_LIT> ) ; unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( DstRC , TRI , SubReg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> static bool isBinary ( MachineInstr & MI ) { return MI . getNumOperands ( )


<s> EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Subtarget -> hasAVX ( ) ? <STR_LIT> :


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ; PSHUFDMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * RepeatedMask [ i ] + <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ) ; } } if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask ,


<s> bool hasDSP ( ) const { return STI . getFeatureBits (


<s> if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( N0 . getNode ( ) ) ; if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( )


<s> case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeSHUFPMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : DecodeUNPCKHMask ( VT , ShuffleMask ) ; break ; case <STR_LIT> : DecodeUNPCKLMask ( VT , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( NumElems , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned OpNum = ( Index == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return getShuffleScalarElt ( V . getOperand ( OpNum ) . getNode ( ) , Index , DAG , Depth + <NUM_LIT> ) ; } case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMILPMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERM2F128Mask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , ShuffleMask ) ; break ; case <STR_LIT> : case <STR_LIT> : case


<s> Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op


<s> int i , j ; switch ( n ) { case <NUM_LIT> : switch ( mode ) { case V16SImode : cmode = V8SImode ; break ; case V16SFmode : cmode = V8SFmode ; break ; case V8DImode : cmode = V4DImode ; break ; case V8DFmode : cmode = V4DFmode ; break ; case V8SImode : cmode = V4SImode ; break ; case V8SFmode : cmode = V4SFmode ; break ; case V4DImode : cmode = V2DImode ; break ; case V4DFmode : cmode = V2DFmode ; break ; case V4SImode : cmode = V2SImode ; break ; case V4SFmode : cmode = V2SFmode ; break ; case V2DImode : cmode = DImode ; break ; case V2SImode : cmode = SImode ; break ; case V2DFmode : cmode = DFmode ; break ; case V2SFmode : cmode = SFmode ; break ; default : gcc_unreachable ( ) ; } if ( ! register_operand ( ops [ <NUM_LIT> ] , cmode ) ) ops [ <NUM_LIT> ] = force_reg ( cmode , ops [ <NUM_LIT> ] ) ; if ( ! register_operand ( ops [ <NUM_LIT> ] , cmode ) ) ops [ <NUM_LIT> ] = force_reg ( cmode , ops [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_VEC_CONCAT ( mode , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ) ; break ; case <NUM_LIT> : switch ( mode ) { case V4DImode : cmode = V2DImode ; break ; case V4DFmode : cmode = V2DFmode ; break ; case V4SImode : cmode = V2SImode ; break ; case V4SFmode : cmode = V2SFmode ; break ; default : gcc_unreachable ( ) ; } goto half


<s> unsigned Op = Win64EH :: UOP_AllocSmall ; if ( Size >= <NUM_LIT> ) Op


<s> report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; if ( STI . isTargetLinux ( ) || STI . isTargetWin32 ( ) || STI . isTargetWin64 ( ) ) { BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ; } else if ( STI . isTargetDarwin ( ) ) { unsigned ScratchReg2 ; bool SaveScratch2 ; if ( CompareStackPointer ) { ScratchReg2 = GetScratchRegister ( Is64Bit , MF , true ) ; SaveScratch2 = false ; } else { ScratchReg2 = GetScratchRegister ( Is64Bit , MF , false ) ; SaveScratch2 = MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) ; } assert ( ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) || SaveScratch2 ) && <STR_LIT> ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg2 , RegState :: Kill ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & prologueMBB ) ; if ( Is64Bit ) { if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( StackSize ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; } else { BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> )


<s> MCInst Thumb2InstrInfo :: getNop ( ) const { return MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> )

. addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm ( MachineInstrBuilder & MIB , const MachineInstr & MI ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; assert ( CstVal && <STR_LIT> ) ; MIB . addImm ( CstVal . getValue ( )


<s> static void mep_function_arg_advance ( cumulative_args_t pcum , machine_mode mode ATTRIBUTE_UNUSED ,

const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) {


<s> mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( <NUM_LIT> * GET_MODE_SIZE ( Pmode ) ) ) ) ; emit_move_insn ( opcode_addr ,


<s> EVT PtrVT = Src1 . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( Size , DL , PtrVT ) , DAG .

getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ;


<s> SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed char ) Op . getImm ( ) ) ; else if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed short ) Op . getImm ( ) ) ; else O << <STR_LIT> << formatImm ( Op . getImm (


<s> return isUndefInRange ( Mask , <NUM_LIT>


<s> if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( StackSize ) ) BuildMI ( MBB , MBBI , dl ,

TII . get ( <STR_LIT> ) ) . addImm ( StackSize ) ;


<s> static scalar_int_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ?


<s> MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) ; } return true


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) . addImm ( Idx * DefSize ) ; if ( ! select ( ExtrInst ) ) return false ; } I . eraseFromParent (


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Lower256IntArith ( Op , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT>

) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; switch ( Count %


<s> if ( IsValidLdStrOpc ) * IsValidLdStrOpc = true ; switch ( Opc ) { default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable ( <STR_LIT> ) ; case FK_SecRel_4 : return Is64Bit ? COFF :: IMAGE_REL_AMD64_SECREL : COFF :: IMAGE_REL_I386_SECREL ; default : llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionBodyStart ( ) { if ( Subtarget -> isELFv2ABI ( ) && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { MCSymbol * GlobalEntryLabel = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: createHa ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr ,


<s> unsigned getThumbBLTargetOpValue ( const MachineInstr & MI , unsigned


<s> vtrnq_p16 ( poly16x8_t a , poly16x8_t b ) { return ( poly16x8x2_t ) { vtrn1q_p16 ( a , b ) , vtrn2q_p16 ( a , b


<s> void <ISA_LIT>16InstrInfo :: loadRegFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return new <ISA_LIT>_MachoTargetObjectFile ( ) ; return new <ISA_LIT>_ELFTargetObjectFile (


<s> return ( uint8x8_t ) __builtin_neon_vqshrnu_nv8hi ( ( int16x8_t


<s> else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE (

type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) {


<s> if ( <STR_LIT> . contains ( DestReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <NUM_LIT> ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <NUM_LIT> ) ; return Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; } } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { assert ( Subtarget . hasBWI ( ) ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( SrcReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( SrcReg ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; return Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; } } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = <STR_LIT> ; else RC = <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { unsigned ArgSize = NextVA . getLocVT ( ) . getSizeInBits (


<s> if ( ! OverwriteExisting ) return ; Item -> Type = AttributeItem :: TextAttribute ; Item -> StringValue = Value ; return ; } AttributeItem Item


<s> assert ( ( Is64Bit || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; unsigned OpCode = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SelectPred = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned SubIdx ; bool SwapOps ; switch ( SelectPred ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = true ; break ; } unsigned FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg =


<s> DCI . CombineTo ( Root . getNode ( ) , getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ) ; return true ; } int MaskSize = Mask . size ( ) ; bool UseInput0 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return <NUM_LIT> <= Idx && Idx < MaskSize ; } ) ; bool UseInput1 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return MaskSize <= Idx ; } ) ; if ( UseInput0 && UseInput1 ) return false ; else if ( UseInput1 ) { std :: swap ( Input0 , Input1 ) ; ShuffleVectorSDNode :: commuteMask ( Mask ) ; } assert ( Input0 && <STR_LIT> ) ; HasVariableMask |= isTargetShuffleVariableMask ( Op . getOpcode ( ) ) ; if ( Op -> isOnlyUserOf ( Input0 . getNode ( ) ) && combine<ISA_LIT>ShufflesRecursively ( Input0 , Root , Mask , Depth + <NUM_LIT> , HasVariableMask , DAG , DCI , Subtarget ) ) return true ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { Mask = std ::


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . ElementWidth = ElementWidth ; Op -> Reg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc =


<s> return DecodeMemAS ( Inst , insn , Address

, Decoder , true , DecodeI64RegisterClass ) ;


<s> return false ; } Save = OffsetVal ; SaveIsReg = false ; } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } Save = SaveOpnd . getGPR32Reg ( ) ; } if ( ! eatComma ( <STR_LIT> ) ) return true ; const MCExpr * Expr ; if ( Parser . parseExpression ( Expr ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) { reportParseError ( <STR_LIT> ) ; return false ; } const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; CpSaveLocation = Save ; CpSaveLocationIsRegister =


<s> SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry


<s> APInt Imm = FPImm . bitcastToAPInt ( ) ; uint64_t Sign = Imm . lshr ( <NUM_LIT> ) . getZExtValue ( ) & <NUM_LIT> ; int64_t Exp = ( Imm . lshr ( <NUM_LIT> ) . getSExtValue ( ) & <NUM_LIT> ) - <NUM_LIT> ; uint64_t Mantissa = Imm . getZExtValue ( ) & <NUM_LIT> ; if ( Mantissa & <NUM_LIT> ) return - <NUM_LIT> ; Mantissa >>= <NUM_LIT> ; if ( ( Mantissa & <NUM_LIT> ) != Mantissa ) return - <NUM_LIT> ; if ( Exp < - <NUM_LIT> || Exp > <NUM_LIT> ) return - <NUM_LIT> ; Exp = ( ( Exp + <NUM_LIT> ) &


<s> if ( tm . getTargetAsmInfo ( ) -> getAssemblerDialect ( ) == <NUM_LIT> ) return new <ISA_LIT>IntelAsmPrinter ( o , tm , tai , verbose ) ; return new <ISA_LIT>ATTAsmPrinter ( o , tm ,


<s> __builtin_neon_vst3_lanev8hi ( ( __builtin_neon_hi * ) __a ,


<s> void setSRetReturnReg ( Register Reg ) { SRetReturnReg =


<s> int regi = pru_function_arg_regi ( cum_v , arg . mode , arg . type ,


<s> unsigned Opcode = <STR_LIT> ; if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS ) && ! isUnsignedIntSetCC ( CC ) ) { Opcode = <STR_LIT> ; RHS = LHS . getOperand ( <NUM_LIT> ) ; LHS = LHS . getOperand


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> * <NUM_LIT> ) ; if ( ! isUInt < <NUM_LIT>


__artificial__ ) ) __writeeflags ( unsigned int X ) {


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( MF . getTarget ( ) .

Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> return ( unsigned long long ) __builtin_ia32_vcvttsd2usi64 ( (


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( <NUM_LIT> ,

rs6000_elf_output_toc_section_asm_op , NULL ) ;


<s> SDValue StackPtr = DAG . getRegister ( StackPtrReg , RegVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , StackPtr , TOCOff ) ; Ops . push_back ( AddTOC ) ; } if ( Subtarget . usesFunctionDescriptors ( ) && ! CFlags . HasNest ) Ops . push_back ( DAG . getRegister ( Subtarget . getEnvironmentPointerRegister ( ) , RegVT ) ) ; if ( CFlags . IsTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; } if ( CFlags . IsTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! CFlags . IsPatchPoint ) Ops . push_back ( DAG . getRegister ( Subtarget . getTOCPointerRegister ( ) , RegVT ) ) ; if ( CFlags . IsVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase (


<s> static const MachineInstrBuilder & AddDReg ( MachineInstrBuilder & MIB , unsigned Reg , unsigned SubIdx , unsigned State , const TargetRegisterInfo * TRI ) { if ( ! SubIdx ) return MIB . addReg ( Reg


<s> SmallVector < int , <NUM_LIT> > Mask ; for ( int M : SVN -> getMask ( ) ) Mask . push_back ( M ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ;


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back (


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( false ) ) ; } bool IsTLS = GVar && GVar -> isThreadLocal ( ) ; if ( IsTLS ) return <NUM_LIT> ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( CModel == CodeModel :: Large || ! GVar || ! GVar -> hasInitializer ( ) || GVar -> hasCommonLinkage ( ) || GVar -> hasAvailableExternallyLinkage ( ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } return DestReg


<s> return Extend . getOperand ( <NUM_LIT> ) . getValueType ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { VTSDNode * TypeNode = dyn_cast < VTSDNode > ( Extend . getOperand ( <NUM_LIT> ) ) ; if ( ! TypeNode ) return <STR_LIT> ; return TypeNode -> getVT ( ) ; } case <STR_LIT> : { ConstantSDNode * Constant = dyn_cast < ConstantSDNode > ( Extend .

getOperand ( <NUM_LIT> ) . getNode ( ) ) ;


<s> Optional < Instruction * > <ISA_LIT>TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { <STR_LIT> IID = II . getIntrinsicID ( ) ; switch ( IID


<s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) || strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) flags = SECTION_SMALL ; flags |= default_section_type_flags ( decl , name


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == <STR_LIT> ) { if ( int CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; CalleeAmt *= - <NUM_LIT> ; unsigned StackReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; const DebugLoc & dl = I -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } return MBB . erase


) , ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> RegisterAsmParser < <ISA_LIT>ATTAsmParser > X (


<s> if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , SDLoc ( LD ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; return DAG . getExtLoad ( LD -> getExtensionType ( ) , SDLoc ( LD ) , ExtendedTy , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> getMemoryVT ( )

, LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> bool CantUseFP = needsStackRealignment ( MF ) ; return CantUseFP && CantUseSP (


<s> int nds32_can_use_return_insn ( void ) { if ( ! reload_completed ) return <NUM_LIT> ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size


<s> static void arm_init_acle_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_ACLE_PATTERN_START ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( acle_builtin_data ) ; i ++


<s> SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot

, MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy .

getSizeInBits ( ) ) ) return SDValue ( ) ;


<s> const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ) { if ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) { auto TstMI = MIRBuilder . buildInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { Ty } , { LHS } ) ; TstMI . addImm ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) ; constrainSelectedInstRegOperands ( * TstMI , TII , TRI , RBI ) ; return & * TstMI ; } } if ( auto Fns = selectLogicalShiftedRegister ( RHS ) ) return emitInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { Ty } , { LHS } , MIRBuilder , Fns ) ; return emitInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { Ty } , { LHS , RHS }


<s> if ( ! MI . mayLoadOrStore ( ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) return false ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemRefBeginIdx = <STR_LIT> ( Desc . TSFlags ) ; if ( MemRefBeginIdx < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ; MI . print ( dbgs ( ) ) ; dbgs ( ) << '\n' ; ) ; return false ; } MemRefBeginIdx += <STR_LIT> ( Desc ) ; const MachineOperand & BaseMO = MI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; const MachineOperand & IndexMO = MI . getOperand ( MemRefBeginIdx


<s> static TargetLoweringObjectFile * createTLOF ( TargetMachine & TM ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return

new <ISA_LIT>MachOTargetObjectFile ( ) ;


<s> labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label , GEN_INT (


<s> return ( __m64 ) __builtin_ia32_vec_init_v2si (


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MI -> getOperand ( i ) , MCOp , AP ) ) OutMI .


<s> return new <ISA_LIT>ReduceCRLogicals (


<s> } Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . Label . Decl ) ) ; return false ; } unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info . Var . Decl ; IsGlobalLV = Info . Var . IsGlobalLV ; } if ( IsGlobalLV && ( BaseReg || IndexReg ) ) { Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Decl ) ) ; return false ; } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale , Start , End , Size , <STR_LIT> ,


<s> if ( ! Src ) return SDValue ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getScalarType ( ) ; if ( SrcSVT != ExtractVT || ( SrcVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = splitVector ( MinPos , DAG , DL ) ; SrcVT = Lo . getValueType ( ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getAllOnesConstant ( DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ; } MinPos = DAG . getBitcast ( <STR_LIT> , MinPos ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MinPos ) ; MinPos = DAG . getBitcast ( SrcVT , MinPos ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; return DAG . getNode ( <STR_LIT> , DL , ExtractVT , MinPos

, DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> Type * FieldTys [ ] = { Type :: getInt8PtrTy ( Context ) , getEHLinkRegistrationType ( ) , Type :: getInt32Ty ( Context ) } ; CXXEHRegistrationTy = StructType :: create


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( )


<s> return ( vector unsigned char ) __builtin_altivec_vpkshus ( ( vector signed short


<s> if ( SDValue Res = tryCombineToEXTR ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineToBSL ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineVecOrNot ( N , DCI ) ) return Res ; return SDValue (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> gcc_assert ( zero_position != - <NUM_LIT> ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , zero_position ) ; return ; case 'e' : gcc_assert ( MEM_P ( x ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; return ; case 'v' : gcc_assert ( CONST_INT_P ( x ) && ( INTVAL ( x ) == <NUM_LIT> || INTVAL ( x ) == <NUM_LIT> || INTVAL ( x ) == <NUM_LIT> || INTVAL ( x ) == <NUM_LIT> ) ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) / <NUM_LIT> ) ; return ; case 'B' : gcc_assert ( CONST_INT_P ( x ) ) ; one_position = exact_log2 ( UINTVAL ( x ) & GET_MODE_MASK ( SImode ) ) ; gcc_assert ( one_position != - <NUM_LIT> ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , one_position ) ; return ; case 'L' : gcc_assert ( REG_P ( x ) ) ; pick_lsb_p = true ; break ; case 'H' : gcc_assert ( REG_P ( x ) ) ; pick_msb_p = true ; break ; case 'V' : gcc_assert ( CONST_INT_P ( x ) ) ; if ( op_value < <NUM_LIT> && op_value >= <NUM_LIT> ) { fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , op_value ) ; } else if ( op_value < <NUM_LIT> || op_value >= ( ( int ) ARRAY_SIZE ( nds32_intrinsic_register_names ) + <NUM_LIT> ) ) { error ( <STR_LIT> ) ; } else { fprintf ( stream , <STR_LIT> , nds32_intrinsic_register_names [ op_value - <NUM_LIT> ] ) ; } return ; case 'R' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value ] ) ; return ; case 'T' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'U' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , nds32_cctl_names [ op_value + <NUM_LIT> ] ) ; return ; case 'X' : if ( op_value < <NUM_LIT> || op_value > <NUM_LIT> ) error


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ! Subtarget . hasFPExtension ( ) ) setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasFPExtension ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> void UpdateRoot ( Instruction * SMLAD ) { Root -> replaceAllUsesWith (


<s> LowerANDOR ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> ,


<s> if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps (

<STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) ;


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; return expand_vec_perm_broadcast_1 (