<s> if ( ! HasFp256 ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ! VT . is256BitVector ( ) || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned LaneSize = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( NumElts != <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + l ] , Mask [ i ] + l ) )


<s> PointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; HasLEB128 = true ; ExceptionsType = ExceptionHandling


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv2di ( ( int64x2_t


<s> if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ; if ( isSigned ) { if ( Hi0 -> getSExtValue ( ) == Lo0 -> getSExtValue ( ) >> <NUM_LIT> && Hi1 -> getSExtValue ( ) == Lo1 -> getSExtValue ( ) >> <NUM_LIT> ) return true ; } else { if ( Hi0 -> isNullValue ( ) && Hi1 -> isNullValue ( ) ) return true ; } return false ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned HalfSize = EltSize / <NUM_LIT> ; if ( isSigned ) { int64_t SExtVal = C -> getSExtValue


<s> static void aarch64_emit_unop ( rtx dest , optab unoptab , rtx op ) { rtx tmp = expand_unop ( GET_MODE ( dest ) , unoptab


<s> AsciiDirective = <STR_LIT> ; AscizDirective = <NUM_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; HasDotTypeDotSizeDirective = false ; HasSingleParameterDotFile = false ; TextSection = getUnnamedSection ( <STR_LIT>


<s> unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ; else return


<s> switch ( SOShOp ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } SDValue SOShImm = CurDAG -> getTargetConstant ( <STR_LIT> ( SOVal ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal


<s> void <ISA_LIT>AsmBackend :: RelaxInstruction ( const MCInst &


<s> min_mp = mp ; min_address = mp -> min_address + fix -> fix_size ; } } } mp = XNEW ( Mnode ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = <NUM_LIT> ; mp -> max_address = minipool_barrier -> address + <NUM_LIT> ; mp -> min_address = min_address ; if ( min_mp == NULL ) { mp -> prev = NULL ; mp -> next = minipool_vector_head ; if ( mp -> next == NULL ) { minipool_vector_tail = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> next -> prev = mp ; minipool_vector_head = mp ; } else { mp -> next = min_mp -> next ; mp -> prev = min_mp ; min_mp -> next = mp ; if ( mp -> next != NULL ) mp -> next -> prev = mp ; else minipool_vector_tail = mp ; } min_mp = mp ; if ( mp -> prev ) mp = mp -> prev ; else mp -> offset = <NUM_LIT> ; while ( mp -> next != NULL ) { if ( mp -> next -> min_address < mp -> min_address + mp -> fix_size ) mp -> next -> min_address = mp -> min_address + mp -> fix_size ; if ( mp -> refcount ) mp -> next -> offset = mp -> offset + mp -> fix_size ; else mp -> next -> offset = mp -> offset ; mp = mp -> next ; } return


<s> IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; } if ( IsRightShift && ShiftAmount <= - <NUM_LIT> && ShiftAmount >= - ( int ) ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - ShiftAmount , <STR_LIT> ) ) ; else if ( ! IsRightShift && ShiftAmount >= <NUM_LIT> && ShiftAmount <= ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT>

) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ShiftAmount , <STR_LIT> ) ) ;


<s> static bool isDomainMVE ( MachineInstr * MI ) { uint64_t Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; return Domain


<s> bool <ISA_LIT>GNULDBackend :: readRelocation ( const llvm :: ELF :: Elf64_Rela & pRel , Relocation :: Type & pType , uint32_t & pSymIdx , uint64_t & pOffset , int64_t & pAddend ) const { uint64_t r_info = <NUM_LIT> ; if ( llvm :: sys :: IsLittleEndianHost ) { pOffset = pRel . r_offset


<s> FPUBitmask |= ( <NUM_LIT> << RegNum ) ; CSFPRegsSize += FGR32RegSize ; } for ( ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = get<ISA_LIT>RegisterNumbering ( Reg ) ; CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } FPUTopSavedRegOff = FPUBitmask ? ( HasAFGR64Reg ? - AFGR64RegSize : - FGR32RegSize ) : <NUM_LIT> ; CPUTopSavedRegOff = CPUBitmask ? - CSFPRegsSize - CPURegSize : <NUM_LIT> ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << CPUTopSavedRegOff << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask , O ) ; O << <STR_LIT> << FPUTopSavedRegOff <<


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , LHS , RHS , Flags ) ; } if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS ) && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , BorrowIn ) ; return SDValue ( )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> int <ISA_LIT>BaseRegisterInfo :: getDwarfRegNum ( unsigned RegNum


<s> static __inline qword si_frsqest ( qword a ) { return ( ( qword ) ( vec_rsqrte ( (


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr * MemMI = I ; MachineBasicBlock :: iterator MBBI = I ; const MachineFunction & MF = * MemMI -> getParent ( ) -> getParent ( ) ; unsigned DestReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = MemMI -> getOperand ( <NUM_LIT> ) . getImm ( ) * TII -> getRegClass ( MemMI -> getDesc ( ) ,


<s> EVT VecVT = Op0 . getValueType ( ) ; if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) { uint64_t Index = CIndexN -> getZExtValue ( ) ; unsigned Mask = VecVT . getVectorNumElements ( ) - <NUM_LIT> ; if ( Index <= Mask ) return Op ; } MVT IntVT = <STR_LIT> ( VT . getSizeInBits (


<s> int CURegNum = getCompactUnwindRegNum ( Reg ) ; if ( CURegNum == - <NUM_LIT> ) return ~ <NUM_LIT> ; RegEnc |= ( CURegNum & <NUM_LIT> ) << ( Idx ++ * <NUM_LIT> ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT> ) ; return RegEnc


<s> if ( NONDEBUG_INSN_P ( insn ) ) { insn_entry [ uid ] . insn = insn ; if ( GET_CODE ( insn ) == CALL_INSN ) insn_entry [ uid ] . is_call = <NUM_LIT> ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref mention ; FOR_EACH_INSN_INFO_USE ( mention , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REAL_REG ( mention ) ) ; if ( mode == DImode && DF_REF_INSN_INFO ( mention ) ) { rtx feeder = DF_REF_INSN ( mention ) ; if ( GET_CODE ( feeder ) == CALL_INSN ) mode = V4SImode ; } if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode || FLOAT128_VECTOR_P ( mode ) ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; union_defs ( insn_entry , insn , mention ) ; } } FOR_EACH_INSN_INFO_DEF ( mention , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REAL_REG ( mention ) ) ; if ( mode == DImode && GET_CODE ( insn ) == SET && ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( SET_DEST ( insn ) ) ) ) mode = GET_MODE ( SET_DEST ( insn ) ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode || FLOAT128_VECTOR_P ( mode ) ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) ,


<s> static SDValue performSRLCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Ty != <STR_LIT> ) || ! Subtarget -> hasDSPR2 ( ) ) && ( Ty != <STR_LIT> )


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm


<s> Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin


<s> void <ISA_LIT>ELFStreamer :: emitCantUnwind


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isPosZero ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> )


<s> case HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : case DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s ,


<s> return vdup_n_bf16 ( vgetq_lane_bf16 (


<s> static unsigned getFixupKindLog2Size ( unsigned Kind ) { switch ( Kind ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MI -> mayLoad ( ) ) { if ( SawStore ) return true ; SawLoad = true ; } if ( MI -> mayStore ( ) ) { if ( SawStore ) return true ; SawStore = true ; if ( SawLoad ) return true ; } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( isRegInSet ( RegDefs , Reg ) || isRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( isRegInSet ( RegDefs , Reg )


<s> if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode )


<s> if ( is32Bit ( VT ) ) Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; else if ( DAG . ComputeNumSignBits ( Op1 ) > <NUM_LIT> ) Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; SDValue Ops [ <NUM_LIT> ] ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op0 , Op1 , Ops [ <NUM_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Lex ( ) ; MCSymbol * Alias = getContext ( ) . GetOrCreateSymbol ( Name ) ; getTargetStreamer ( ) . emitThumbSet (


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , bool InProlog ) const { assert ( InProlog && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; return MBBI


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( <STR_LIT> ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += <STR_LIT> ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT>


<s> } case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF18 ; } } switch ( Kind ) { default : Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : return ELF :: R_<ISA_LIT>_TLS_LDO32 ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; case MCSymbolRefExpr :: VK_TLSDESC : return ELF :: R_<ISA_LIT>_TLS_GOTDESC ; case MCSymbolRefExpr :: VK_TLSLDM : return ELF :: R_<ISA_LIT>_TLS_LDM32 ; case MCSymbolRefExpr ::


<s> tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_vec_setv8hf_0 ( tmp2 , CONST0_RTX ( mode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } else { tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } emit_move_insn ( dperm . op0 , tmp1 ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case E_V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; if ( smode == QImode && ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( wsmode , val , val ) ) ; else { x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case E_V16HImode : case E_V16HFmode : case E_V32QImode


<s> SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } } SDValue Splat = DAG . getNode ( <STR_LIT> , DL , CmpVT , Imm ) ; SDValue ID = DAG . getTargetConstant ( ReplacementIID , DL , <STR_LIT> ) ; SDValue Op0 , Op1 ; if ( Invert ) { Op0 = Splat ; Op1 = N -> getOperand ( <NUM_LIT> ) ; } else { Op0 = N -> getOperand ( <NUM_LIT> ) ; Op1 = Splat ; } return DAG . getNode ( <STR_LIT> , DL , VT , ID , Pred


<s> static MachineInstr * canFoldIntoMOVCC ( unsigned Reg , const MachineRegisterInfo & MRI , const TargetInstrInfo * TII ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> if ( TARGET_ARCH64 && type && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; return default_function_arg_padding ( mode ,


<s> const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return <NUM_LIT> ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . count ( WaterBB ) ) { NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; CreateNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland


<s> OS << <STR_LIT> << Arch << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetArch


<s> } } return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getZExtValue ( ) ; if ( Val == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , DL , Type ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; uint64_t Val = ( uint64_t ) C -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( Val ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= - <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'P' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue (


<s> unsigned DefOpc = DefMI -> getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI -> getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI -> getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI -> getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI -> getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> tmp = SET_DEST ( tmp ) ; if ( GET_CODE ( tmp ) != REG || REGNO ( tmp ) != <NUM_LIT> ) continue ; next = next_insn ( insn ) ; while ( next ) { if ( JUMP_P ( next ) || CALL_P ( next ) || LABEL_P ( next ) ) break ; if ( NONJUMP_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( next ) ) ) == REG && REGNO ( SET_DEST ( PATTERN ( next ) ) ) == <NUM_LIT> ) break ; next = next_insn ( next ) ; } if ( next && JUMP_P ( next ) ) { rtx pattern = PATTERN ( next ) ; if ( GET_CODE ( pattern ) == SET && SET_DEST ( pattern ) == pc_rtx && GET_CODE ( SET_SRC ( pattern ) ) == IF_THEN_ELSE && GET_CODE ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ) == NE && GET_CODE ( XEXP ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && GET_CODE ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ) == PC && ( fcmp_count == fbranch_count || ( check_notes && find_regno_note ( next , REG_DEAD , <NUM_LIT> ) ) ) ) { tmp = XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ; XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) = XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ; XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) = tmp ; INSN_CODE ( next ) = -


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else { const MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) . addReg ( Cond [ <NUM_LIT>


<s> if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( )


<s> if ( code == EQ || code == NE || code == UNEQ || code == LTGT || code == ORDERED || code == UNORDERED ) return false ; if ( ( code == GT || code == UNLE || code == LE || code == UNGT ) && ! TARGET_IEEE_FP ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } start_sequence ( ) ; compare_op = ix86_expand_fp_compare ( code , op0 , op1 ) ; compare_seq = get_insns ( ) ; end_sequence ( ) ; if ( GET_MODE ( XEXP ( compare_op , <NUM_LIT> ) ) == CCFPmode ) code = ix86_fp_compare_code_to_integer ( GET_CODE ( compare_op ) ) ; else code = GET_CODE ( compare_op ) ; if ( code != LTU && code != GEU ) return false ; emit_insn ( compare_seq ) ; * pop = compare_op ; return true ; } if ( ! INTEGRAL_MODE_P ( mode ) ) return false ; switch ( code ) { case LTU : case GEU : break ; case


<s> emit_insn ( gen_aarch64_frecps ( mode , xtmp , xrcp , den ) ) ; if ( iterations > <NUM_LIT> ) aarch64_emit_mult ( xrcp , pg , xrcp , xtmp ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; aarch64_emit_mult ( xrcp , pg , xrcp , xnum ) ; } aarch64_emit_mult ( quo , pg , xrcp , xtmp ) ; return true


<s> static __inline__ float __fmsubs ( float x , float y , float z ) { float r


<s> return ( ( Op . getOpcode ( ) == <STR_LIT> ) && isSetCC ( Op

-> getOperand ( <NUM_LIT> ) , Info ) ) ;


<s> static bool HasControlFlow ( const MachineInstr & MI ) { return MI . getDesc ( ) . isBranch ( ) || MI . getDesc ( ) . isCall ( ) || MI . getDesc ( ) . isReturn ( ) || MI . getDesc ( ) . isTerminator ( ) ||


<s> } switch ( dec -> modrm_type ) { default : debug ( <STR_LIT> ) ; return <NUM_LIT> ; case MODRM_ONEENTRY : return dec -> instructionIDs [ <NUM_LIT> ] ; case MODRM_SPLITRM : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return dec -> instructionIDs [ <NUM_LIT> ] ; else return dec -> instructionIDs [ <NUM_LIT> ] ; case


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) return SDValue ( ) ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode (


<s> bool isCRBitMask ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && isPowerOf2_32


<s> MachineBasicBlock :: iterator I = CmpInstr , E = MI , B = CmpInstr . getParent ( ) -> begin ( ) ; if ( I == B ) return false ; MachineInstr * Sub = nullptr ; if ( SrcReg2 != <NUM_LIT> ) MI = nullptr ; else if ( MI -> getParent ( ) != CmpInstr . getParent ( ) || CmpValue != <NUM_LIT> ) { if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) MI = nullptr ; else return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; for ( -- I ; I != E ; -- I ) { const MachineInstr & Instr = * I ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub

-> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) {


<s> if ( Reg2 == <STR_LIT> ) return true ; if ( ! NeedsWinCFI ) return false ; if ( Reg2 == Reg1 + <NUM_LIT> ) return


<s> Value * <ISA_LIT>IREmitter :: visitFMIN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> bool anyregs = false ; for ( TargetRegisterClass :: const_iterator I = <STR_LIT> . begin ( ) , E = <STR_LIT> . end ( ) ; I != E ; ++ I ) if ( MF -> getRegInfo ( ) . isPhysRegUsed ( * I ) ) { anyregs = true ; break ; } if ( ! anyregs ) return false ; MachineBasicBlock * Entry = MF -> begin ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > DFI = df_ext_begin ( Entry , Visited ) , DFE = df_ext_end ( Entry , Visited ) ; DFI != DFE ; ++ DFI ) { MBB = * DFI ; enterBasicBlock ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { MachineInstr * mi = I ; if ( mi -> isDebugValue ( ) ) continue ; ++


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer (


<s> if ( Subtarget -> isTargetMachO ( ) ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString (


<s> static bool shouldClusterFI ( const MachineFrameInfo & MFI , int FI1 , int64_t Offset1 , unsigned Opcode1 , int FI2 , int64_t Offset2 , unsigned Opcode2 ) { if ( MFI . isFixedObjectIndex ( FI1 ) && MFI . isFixedObjectIndex ( FI2 ) ) { int64_t ObjectOffset1 = MFI . getObjectOffset ( FI1 ) ; int64_t ObjectOffset2 = MFI . getObjectOffset ( FI2


<s> static SDValue getPTest ( SelectionDAG & DAG , EVT VT , SDValue Pg , SDValue Op , <STR_LIT> Cond ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc DL ( Op ) ; assert ( Op . getValueType ( ) . isScalableVector ( ) && TLI . isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ; EVT OutVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , OutVT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , OutVT ) ; SDValue Test = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM_BR : case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent (


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm (


<s> SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( ! SelectAddr ( Node , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return NULL ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; const SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , In2L , In2H , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return ResNode


<s> break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) )


<s> __builtin_mve_vst1q_fv8hf ( ( __builtin_neon_hi *


<s> SDValue <ISA_LIT>TargetLowering :: lowerOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; APInt KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; uint64_t Masks [ ] = { KnownZero [ <NUM_LIT> ] . getZExtValue ( ) , KnownZero [ <NUM_LIT> ] . getZExtValue ( ) } ; unsigned High , Low ; if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else return Op ; SDValue LowOp = Ops [ Low ] ; SDValue HighOp = Ops [ High ] ; if ( HighOp . getOpcode ( ) == <STR_LIT> )


<s> Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( ZeroReg ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp2Reg ) . addReg ( TmpDestReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp3Reg ) . addReg ( TmpReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp4Reg ) . addReg ( Tmp3Reg ) . addReg ( Tmp2Reg ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( Tmp4Reg )


<s> static __inline qword si_ilh ( signed short imm ) { return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm )


<s> Op -> Mem . OffsetReg = <STR_LIT> ; Op -> Mem . Off = nullptr ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> return __builtin_mve_vdwdupq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __c ,


<s> static rtx gen_stack_pointer_inc ( rtx increment ) { return gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , increment


<s> case Match_MissingFeature : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidOperand : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSuffix : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidCondCode : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegExtendSmall : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegExtendLarge : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT>


<s> * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; return true ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; __asm { mov eax , value cpuid mov esi , rEAX mov dword ptr [ esi ] , eax mov esi , rEBX mov dword ptr [ esi ] , ebx mov esi , rECX mov dword ptr [ esi ] , ecx mov esi , rEDX mov dword ptr [ esi ] , edx } return false


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = <NUM_LIT> ; if ( sh_pass_in_reg_p ( * cum , mode , type ) && ! TARGET_FPU_DOUBLE && ( sh_round_reg ( * cum , mode ) + ( mode != BLKmode ? CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) : CEIL ( int_size_in_bytes

( type ) , UNITS_PER_WORD ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - sh_round_reg ( * cum , mode ) ;


<s> static unsigned getFixupKindNumBytes ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return createCMovFP ( DAG , Cond , True ,


<s> DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( Subtarget . hasPA ( ) && MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . setMIFlag ( MachineInstr


<s> unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgArea ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . isExtInLoc ( ) ) Offset += <NUM_LIT> - ValSize ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgArea + Subtarget -> getStackPointerBias ( ) ) ; SmallVector < SDValue , <NUM_LIT> > OutChains ; for ( ; ArgOffset < <NUM_LIT> *


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasDQI


<s> compute_bb_for_insn ( ) ; if ( flag_mitigate_rop ) ix86_mitigate_rop ( ) ; if ( TARGET_SEH && current_function_has_exception_handlers ( ) ) ix86_seh_fixup_eh_fallthru ( ) ; if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS ) ix86_pad_returns


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void ) SetI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SetI -> dump ( ) ) ; ++ NumSetCCsInserted ; return Reg


<s> static SDValue LowerSUB ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) . is256BitVector ( ) && Op .

getValueType ( ) . isInteger ( ) && <STR_LIT> ) ;


<s> if ( ! Ld0 || ! Ld1 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; if ( ! Ld0 -> hasOneUse ( ) || ! Ld1 -> hasOneUse ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! LoadPairs . count ( Ld0 ) || LoadPairs [ Ld0 ] != Ld1 ) return false ; VecMem . clear (


<s> if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( bit ) ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , dst * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT>

) ) Inst . addOperand ( MCOperand :: CreateImm ( dst ) ) ;


<s> assert ( Subtarget -> supportsTailCall ( ) ) ; if ( isVarArg && ! Outs . empty ( ) ) return false ; if ( CallerF -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII =


<s> Cond = Cond . getNode ( ) -> getOperand ( <NUM_LIT> ) ; addTest = false ; break ; } } } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; addTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; SDValue User = SDValue ( * Op . getNode ( ) -> use_begin ( ) , <NUM_LIT> ) ; if ( User . getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User . getOperand ( <NUM_LIT> ) ; SDValue NewBR = DAG . UpdateNodeOperands ( User , User . getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; Cond = Cmp ; addTest = false ; } } } } else if ( Cond . hasOneUse ( ) && isXor1OfSetCC ( Cond ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; Cond = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; addTest = false ; } } if ( addTest


<s> inline ShiftOpc getSORegShOp ( unsigned Op


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : expandLDImm ( MI ) ; return true


<s> return ( __m512d ) __builtin_ia32_getexppd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) -


<s> auto * C1 = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ; Instruction * I = AI -> user_back ( ) ; if ( ! C1 || ! AI -> hasOneUse ( ) || I -> getOpcode ( ) != Instruction :: And || AI -> getParent ( ) != I -> getParent ( ) ) return AtomicExpansionKind :: CmpXChg ; auto * C2 = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Bits = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ! C2 || Bits == <NUM_LIT> || ! isPowerOf2_64 ( C2 -> getZExtValue ( ) ) ) return AtomicExpansionKind :: CmpXChg ; if ( AI -> getOperation ( ) == AtomicRMWInst :: And ) return ~ C1 -> getValue ( ) == C2 -> getValue ( ) ? AtomicExpansionKind :: BitTestIntrinsic : AtomicExpansionKind :: CmpXChg ; return C1 == C2 ? AtomicExpansionKind :: BitTestIntrinsic : AtomicExpansionKind


<s> EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg )


<s> static void rs6000_instantiate_decls ( void ) { if ( cfun -> machine -> sdmode_stack_slot != NULL_RTX ) instantiate_decl_rtl

( cfun -> machine -> sdmode_stack_slot ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo


<s> const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; unsigned Imm = MMO . getOffset ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; unsigned Rs = RegInfo . createVirtualRegister (


<s> bool isTargetWin64 ( ) const { return Is64Bit && isOSWindows ( )


<s> if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueType ( ) . getSizeInBits ( ) ) return false ; ShiftVal = Amount ; return


<s> SDValue PassThru ; bool IsPassThruZeroOrUndef = false ; if ( Load -> getPassThru ( ) -> isUndef ( ) ) { PassThru = DAG . getUNDEF ( ContainerVT ) ; IsPassThruZeroOrUndef = true ; } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; else PassThru = DAG . getConstantFP ( <NUM_LIT> , DL , ContainerVT ) ; if ( isZerosVector ( Load -> getPassThru ( ) . getNode ( ) ) ) IsPassThruZeroOrUndef = true ; } SDValue NewLoad = DAG . getMaskedLoad ( ContainerVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Mask , PassThru , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) , Load ->

getAddressingMode ( ) , Load -> getExtensionType ( ) ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) { if ( Is64Bit ) return & <STR_LIT>


<s> assert ( VT . isInteger ( ) && VT == LHS . getValueType ( ) && VT == RHS . getValueType ( ) && <STR_LIT> ) ; SDValue CC = DAG . getCondCode ( Cond ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( LHS , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( RHS , DAG , dl ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 &&


<s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> EVT VT = LHS . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) { assert ( VT != <STR_LIT> ) ; if ( VT == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; VT = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; } unsigned Opcode =


<s> rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; } else { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH (


<s> default : return SDValue ( ) ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op .


<s> continue ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos ) { <STR_LIT> NCC = getPredicate ( & * MBBI , TII ) ; if ( NCC


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKilled = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool IsPrimed = <STR_LIT> . contains ( SrcReg ) ; Register Reg = <STR_LIT> + ( SrcReg - ( IsPrimed ? <STR_LIT> : <STR_LIT> ) ) * <NUM_LIT> ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; emitAccSpillRestoreInfo ( MBB , IsPrimed , false ) ; if ( IsPrimed ) BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , SrcReg ) . addReg ( SrcReg ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg

, getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? <NUM_LIT> : <NUM_LIT> ) ;


<s> assert ( ( SubMode == ia || SubMode == db ) && <STR_LIT> ) ; return ( ( int ) SubMode << <NUM_LIT> ) | ( ( int


<s> exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( ShiftAmt ) . addReg ( MaskUpper ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskedCmpVal ) . addReg ( CmpVal ) . addImm ( MaskImm ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , ShiftedCmpVal ) . addReg ( ShiftAmt ) . addReg ( MaskedCmpVal ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskedNewVal ) . addReg ( NewVal ) . addImm ( MaskImm ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , ShiftedNewVal ) . addReg ( ShiftAmt ) . addReg ( MaskedNewVal ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskedOldVal0 ) . addReg ( OldVal ) . addReg ( Mask ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MaskedOldVal0 ) . addReg ( ShiftedCmpVal ) . addMBB ( sinkMBB ) ; BB =


<s> DEBUG ( dbgs ( ) << <STR_LIT> << V . getNode ( ) <<

<STR_LIT> << R << <STR_LIT> << S << <STR_LIT> << E << <STR_LIT> ) ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; return vectorCostAdjustment ( Cost , Opcode , ValTy ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static const <ISA_LIT>MCExpr * createLo ( const MCExpr * Expr , bool IsDarwin , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_LO , Expr , IsDarwin , Ctx


<s> bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) { ImmBranch & Br = ImmBranches [ i ] ; unsigned Opcode = Br . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( Br . MI , DestBB , MaxOffs ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Br . MI ) ; Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo &


<s> return __builtin_mve_vmulhq_m_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register (


<s> } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI ->


<s> if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } SymToPrint -> print ( O , MAI ) ; printOffset ( MO . getOffset


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } unsigned ScratchReg = <STR_LIT> ; if ( TRI -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; uint32_t AlignLog = Log2_32 ( MFI -> getMaxAlignment ( ) ) ; if ( isInt < <NUM_LIT> > ( StackSize ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; } else { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addImm ( ( uint32_t ) - StackSize >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - StackSize & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( AlignLog ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( AlignLog ) ; } else if ( isInt < <NUM_LIT> > ( StackSize ) ) { if ( StackSize ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; } } else { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addImm ( ( uint32_t ) - StackSize >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - StackSize & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) ; } if ( TRI -> hasBasePointer ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , TRI

-> getBaseRegister ( ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> arm_builtin_datum * d = & acle_builtin_data [ i ] ; arm_init_builtin ( fcode , d


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum ,

raw_ostream & O , const char * Modifier ) {


<s> int64_t Value = MCE -> getValue ( ) ; return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( static_cast < int32_t


<s> unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , NumBytes , <STR_LIT> , <NUM_LIT> , isThumb , TII , * this , dl ) ; } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( isThumb ) { if ( hasFP ( MF ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , FramePtr , - NumBytes , TII , * this , dl ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , NumBytes , <STR_LIT> , <NUM_LIT> , isThumb , TII , * this , dl ) ; } else emitSPUpdate ( MBB , MBBI , NumBytes , <STR_LIT> , <NUM_LIT> , isThumb , TII , * this , dl ) ; } } else { if ( ( STI . isTargetDarwin ( ) && NumBytes ) || hasFP ( MF ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) || hasFP ( MF ) ) { if ( NumBytes ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( NumBytes ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , <STR_LIT> , <NUM_LIT> , false


<s> int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) != <NUM_LIT> && ( ( i & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) != ( ( ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) return TRUE ; lowbit = ffs ( ( int ) i ) - <NUM_LIT> ; if ( TARGET_ARM ) lowbit &= ~ <NUM_LIT> ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << lowbit ) ) == <NUM_LIT> ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= <NUM_LIT> && ( ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> ) ) return TRUE ; } else if (


<s> Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool isInt = OpVT . isInteger ( ) ; CC = <STR_LIT> ( CC , isInt ) ; if ( ! TLI . isCondCodeLegal ( CC , OpVT ) ) return SDValue ( ) ; DoXform = true ; InvCC = true ; } if ( DoXform ) { SDValue Result = DAG . getNode ( Opc , RHS . getDebugLoc ( ) , VT , OtherOp , RHS ) ; if ( isSlctCC ) return DAG . getSelectCC ( N -> getDebugLoc ( ) , OtherOp , Result , Slct . getOperand ( <NUM_LIT> ) , Slct . getOperand ( <NUM_LIT> ) , CC ) ; SDValue CCOp = Slct . getOperand ( <NUM_LIT> ) ; if ( InvCC ) CCOp = DAG . getSetCC ( Slct . getDebugLoc ( ) , CCOp . getValueType ( ) , CCOp . getOperand ( <NUM_LIT> ) , CCOp . getOperand ( <NUM_LIT> ) , CC ) ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , CCOp , OtherOp , Result ) ; } return SDValue ( )


<s> extern __inline __m512h __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_loadu_ph ( void const * __P ) { return * ( const __m512h_u *


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine


<s> else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return true ; return false ; } else if ( mode ==


<s> if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! Subtarget -> isABI_N64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; } getTargetStreamer ( ) . updateABIInfo ( * Subtarget ) ; if ( Subtarget -> isABI_O32 ( ) && ( Subtarget -> isABI_FPXX ( ) || Subtarget -> isFP64bit ( ) ) ) getTargetStreamer ( ) . emitDirectiveModuleFP ( ) ; if ( Subtarget -> isABI_O32 ( ) && ( ! Subtarget -> useOddSPReg ( ) || Subtarget -> isABI_FPXX ( ) ) ) getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( Subtarget -> useOddSPReg ( ) ,


<s> if ( ! ABI . IsN64 ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ABI . IsN64 ( ) || ABI . IsN32 (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI ,

const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) {


<s> if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0


<s> if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; } return


<s> return PotentialStores . first == StOpcode || PotentialStores . second


<s> return __builtin_aarch64_sqrshldi ( __a ,


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI


<s> if ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) return true ; auto * BV = dyn_cast < BuildVectorSDNode > ( Op ) ; return ( BV && BV -> isConstant ( ) ) ; } ; if ( ( IsFreeTruncation ( Op0 ) && DAG . computeKnownBits ( Op0 ) . countMaxActiveBits ( ) <= <NUM_LIT> ) && ( IsFreeTruncation ( Op1 ) && DAG . ComputeMaxSignificantBits ( Op1 ) <= <NUM_LIT> ) ) return true ; return false


<s> if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> function_return_type = ix86_function_return ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> function_return_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , (

( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> case <NUM_LIT> : align = <NUM_LIT> ; break ; default : return MCDisassembler :: Fail ; } break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg (


<s> SmallVector < LLT > HAddTys ; if ( Ty . isScalar ( ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: scalar ( <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder UADD ; for ( LLT HTy : HAddTys ) { UADD = MIRBuilder . buildIntrinsic ( Opc , { HTy } , false ) . addUse (


( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> MachineInstr * CommutedMI = TII -> commuteInstruction ( MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl ,


<s> if ( CondField == <NUM_LIT> ) return <STR_LIT> ; return CondField


<s> CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT>


<s> void <ISA_LIT>CodeEmitter :: emitMOVi2piecesInstruction ( const MachineInstr & MI ) { const MachineOperand & MO0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI . getOperand ( <NUM_LIT> ) ; assert ( MO1 . isImm ( ) && <STR_LIT> ( MO1 . isImm ( ) ) != - <NUM_LIT> && <STR_LIT> ) ; unsigned V1 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT>


<s> int log = exact_log2 ( INTVAL ( hi_bound ) + <NUM_LIT> ) ; if ( log == - <NUM_LIT> ) return false ; if ( INTVAL ( lo_bound ) == <NUM_LIT> ) { if ( mask ) * mask = log ; if ( signed_sat ) * signed_sat = false ; return true ; } if ( INTVAL ( lo_bound ) == - INTVAL ( hi_bound ) -


<s> assert ( isIntN ( Size * <NUM_LIT> + <NUM_LIT> , Value ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ]

= uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << StringRef ( getRegisterName (


<s> const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) ) Alignment = DL . getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode (


<s> if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . OffsetRegNum ) ) return false ; if ( shift == <NUM_LIT> && Memory . ShiftType != <STR_LIT> ) return false ; if ( shift > <NUM_LIT> && ( Memory . ShiftType != <STR_LIT> || Memory . ShiftImm != shift ) ) return false ; return


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent


<s> if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : return MCDisassembler :: Fail ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>_64Target , create<ISA_LIT>Disassembler


<s> aarch64_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; aarch64_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; aarch64_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; aarch64_simd_types [ Int64x1_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint64x1_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Poly8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype = build_distinct_type_copy ( unsigned_intQI_type_node ) ; aarch64_simd_types [ Poly16_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype = build_distinct_type_copy ( unsigned_intHI_type_node ) ; aarch64_simd_types [ Poly64_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype = build_distinct_type_copy ( unsigned_intDI_type_node ) ; aarch64_simd_types [ Poly128_t ] . eltype = aarch64_simd_types [

Poly128_t ] . itype = build_distinct_type_copy ( unsigned_intTI_type_node ) ;


<s> Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc =


<s> void expand_sf_unop ( rtx ( * fun ) ( rtx , rtx , rtx ) , rtx * operands ) { emit_sf_insn ( ( * fun ) ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( Block . IsOnlyPredicatedOn ( LoLoop . VCTP ) ) { for ( auto I = ++ MachineBasicBlock :: iterator ( Block . getVPST ( ) ) , E = ++ MachineBasicBlock :: iterator ( Divergent -> MI ) ; I != E ; ++ I ) RemovePredicate ( & * I ) ; unsigned Size = <NUM_LIT> ; auto E = MachineBasicBlock :: reverse_iterator ( Divergent -> MI ) ; auto I = MachineBasicBlock :: reverse_iterator ( Insts . back ( ) . MI ) ; MachineInstr * InsertAt = nullptr ; while ( I != E ) { InsertAt = & * I ; ++ Size ; ++ I ; } MachineInstrBuilder MIB = BuildMI ( * InsertAt -> getParent ( ) , InsertAt , InsertAt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( get<ISA_LIT>VPTBlockMask ( Size ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Block . getVPST ( ) ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; return hasGOTReference ( BE -> getLHS ( ) ) || hasGOTReference ( BE -> getRHS ( ) ) ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; return ( SymRef . getSymbol ( ) . getName ( ) == <STR_LIT> ) ; } case MCExpr :: Unary : return hasGOTReference ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( )


<s> if ( BaseType == <STR_LIT> ) MO . push_back ( MachineOperand :: CreateReg ( Base . Reg , false , false , false , false , false , false , <NUM_LIT> , false ) ) ; else { assert ( BaseType == <STR_LIT> ) ; MO . push_back ( MachineOperand :: CreateFI ( Base . FrameIndex ) ) ; } MO . push_back ( MachineOperand :: CreateImm ( Scale ) ) ; MO . push_back ( MachineOperand :: CreateReg ( IndexReg , false , false , false , false , false , false , <NUM_LIT> , false ) ) ; if ( GV ) MO . push_back ( MachineOperand :: CreateGA ( GV , Disp , GVOpFlags ) ) ; else MO . push_back ( MachineOperand :: CreateImm ( Disp ) ) ; MO . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false , false , false , false , false ,


<s> MBBI = PrevMBBI ; UseLDRSP = true ; } } } if ( ! DoIt && ! PopReg && ! TemporaryReg ) return false ; assert ( ( PopReg || TemporaryReg ) && <STR_LIT> ) ; if ( UseLDRSP ) { assert ( PopReg && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( PopReg , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( MBBI -> getNumExplicitOperands ( ) - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( PopReg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; MBBI ++ ; emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , ArgRegsSaveSize + <NUM_LIT> , <STR_LIT> , MachineInstr :: NoFlags ) ; return true ; } if ( TemporaryReg ) { assert ( ! PopReg && <STR_LIT> ) ; PopReg = PopFriendly . find_first ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( TemporaryReg , RegState :: Define ) . addReg ( PopReg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; bool Popped = false ; for ( auto MO : MBBI -> operands ( ) ) if ( MO . isReg ( ) && ( MO . isImplicit ( ) || MO . isDef ( ) ) && MO . getReg ( ) != <STR_LIT> ) { MIB . add ( MO ) ; if ( ! MO . isImplicit ( ) ) Popped = true ; } if ( ! Popped ) MBB . erase ( MIB . getInstr ( ) ) ; MBB . erase ( MBBI ) ; MBBI = BuildMI ( MBB , MBB . end ( ) , dl , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; } assert ( PopReg && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( PopReg , RegState :: Define ) ; emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , ArgRegsSaveSize


<s> MCRegister getTOCPointerRegister ( ) const { assert ( ( is64BitELFABI ( ) || isAIXABI ( ) ) && <STR_LIT> ) ; return Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT>


<s> unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg


<s> if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { assert ( ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetKnownWindowsMSVC ( ) ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget -> isTargetNaCl ( ) ) { RetValReg = Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Zext = DAG . getZExtOrTrunc ( Val , dl , <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Zext , Flag ) ; } else { Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; } Flag = Chain .


<s> SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , Elt ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) ) { if ( IdxVal ) EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return EltInVec ; } if ( IdxVal == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , EltInVec ) ; } if ( IdxVal == NumElems - <NUM_LIT> ) { EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , EltInVec ) ; } SmallVector < int , <NUM_LIT> >


<s> bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val =


<s> return ( float32x2_t ) __builtin_neon_vnegv2sf


<s> return getSTI ( ) . getFeatureBits ( )