<s> int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore ,


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> } else if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ZeroReg = <STR_LIT> ; } if ( ! DstReg ) return false ; for ( MachineRegisterInfo :: use_iterator U = MRI -> use_begin ( DstReg ) , E = MRI -> use_end ( ) ; U != E ; ) { MachineOperand & MO = U . getOperand ( ) ; unsigned OpNo = U . getOperandNo ( ) ; MachineInstr * MI = MO . getParent ( ) ; ++ U ; if ( MI -> isPHI ( ) || MI -> isRegTiedToDefOperand ( OpNo ) || MI -> isPseudo ( ) ) continue ; MO . setReg ( ZeroReg ) ; } return


<s> if ( isPositionIndependent ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> return new <ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; ArgumentPopSize = StackAdjust . getImm ( ) ; } else { ArgumentPopSize = AFI -> getArgumentStackToRestore ( ) ; } return ArgumentPopSize


<s> if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; x = XEXP ( x , <NUM_LIT> ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x


<s> pat = GEN_FCN ( icode ) ( op0 , addr_helper , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( pat )


<s> if ( icode == CODE_FOR_vsx_lxvrbx ) { temp1 = simplify_gen_subreg ( V16QImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_v16qi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrhx ) { temp1 = simplify_gen_subreg ( V8HImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_v8hi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrwx ) { temp1 = simplify_gen_subreg ( V4SImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_v4si_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = simplify_gen_subreg (

V2DImode , tiscratch , TImode , <NUM_LIT> ) ;


<s> if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned MinSplatBits ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , MinSplatBits , HasAnyUndefs ) ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ; SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SDValue Lg2Amt = DAG . getConstant ( lg2 , <STR_LIT> ) ; SDValue SRA = getTargetVShiftNode ( <STR_LIT> , dl , VT , ADD , Lg2Amt , DAG ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG . getConstant ( <NUM_LIT> , EltTy ) ) ; SDValue Zero = DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , NumElts ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Zero , SRA ) ; } return SDValue ( )


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; SDValue Value = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT TheVT = Value . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; EVT ResVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) ; SDValue Cmp ; if ( IsStrict ) Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> , Chain , true ) ; else Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue FltOfs = DAG . getSelect ( DL , TheVT , Cmp , DAG . getConstantFP ( <NUM_LIT> , DL , TheVT ) , ThreshVal ) ; if ( IsStrict ) { Value = DAG . getNode ( <STR_LIT> , DL , { TheVT , <STR_LIT> } , { Chain , Value , FltOfs } ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } else Value = DAG . getNode ( <STR_LIT> ,


<s> Register AddOp1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT PtrTy = MRI . getType ( DstReg ) ; if ( PtrTy . getAddressSpace ( ) != <NUM_LIT> ) return false ; const LLT CastPtrTy = PtrTy . isVector ( ) ? LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) : LLT :: scalar ( <NUM_LIT> ) ; auto PtrToInt = MIB . buildPtrToInt ( CastPtrTy , AddOp1Reg ) ; if ( PtrTy . isVector ( ) ) MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; else MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . setDesc ( TII . get ( TargetOpcode :: G_ADD ) ) ; MRI . setType ( DstReg , CastPtrTy ) ; I . getOperand ( <NUM_LIT> ) . setReg ( PtrToInt . getReg ( <NUM_LIT> ) ) ; if ( ! select ( * PtrToInt )


<s> static DecodeStatus DecodeSORegImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT>


<s> unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( MBB , I , TII , dl , *


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; } llvm_unreachable (


<s> DiagnosticPredicate isSVECpyImm ( ) const { if ( ! isShiftedImm ( ) && ( ! isImm ( ) || ! isa < MCConstantExpr > ( getImm ( ) ) ) ) return DiagnosticPredicateTy :: NoMatch ; bool IsByte = std :: is_same < int8_t , typename std :: make_signed < T > ::


<s> if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS


<s> Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 , TheTriple


<s> void <ISA_LIT>16TargetLowering :: set<ISA_LIT>16LibcallName ( RTLIB :: Libcall L , const char * Name ) { setLibcallName ( L ,


<s> static __inline qword si_rotqbi ( qword a , qword count ) { vec_uchar16 x , y ; vec_uchar16 result ; x = vec_and ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI -> hasOneNonDBGUse ( AccReg ) ; MIB . addReg ( TmpReg , getKillRegState ( true ) ) . addReg ( AccReg , getKillRegState ( AccKill ) ) ; } else { MIB . addReg ( AccReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; } MIB . addImm ( Pred ) . addReg ( PredReg ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << * MI ; dbgs ( ) << <STR_LIT> ; MachineBasicBlock :: iterator MII = MI ; MII = llvm :: prior ( MII ) ; MachineInstr & MI2 = * MII ; MII = llvm :: prior ( MII ) ; MachineInstr & MI1 = * MII ; dbgs ( ) << <STR_LIT> << MI1 ; dbgs ( ) << <STR_LIT> << MI2


<s> assert ( ( NumOps == <ISA_LIT>AddrNumOperands + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , <NUM_LIT> , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode

( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) {


<s> unsigned ParamRegs = <NUM_LIT> ; if ( auto * M = MF -> getFunction ( ) -> getParent ( ) ) ParamRegs = M -> getNumberRegisterParameters ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < Args . size ( ) ; Idx ++ ) { Type * T = Args [ Idx ] . Ty ; if ( T -> isPointerTy ( ) || T -> isIntegerTy ( ) ) if ( MF -> getDataLayout ( ) . getTypeAllocSize (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsmsk_u64 ( unsigned long long __X ) { return __blsmsk_u64 ( __X


<s> bool IsEL = STI . isLittle ( ) ; auto Unmerge = MIRBuilder . buildUnmerge ( LLT :: scalar ( <NUM_LIT> ) , ValVReg ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? <NUM_LIT> : <NUM_LIT> ) ) , Unmerge . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? <NUM_LIT> : <NUM_LIT> ) ) , Unmerge . getReg ( <NUM_LIT> ) ) ; } else if ( VT == <STR_LIT> && PhysReg >= <STR_LIT> && PhysReg <= <STR_LIT> ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return outliner :: InstrType :: Illegal ; } if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> bool <ISA_LIT>TargetLowering :: isReadOnly ( const GlobalValue * GV ) const { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( ! ( GV = GA -> getAliaseeObject ( ) ) ) return false ; if ( const auto * V = dyn_cast < GlobalVariable > ( GV ) ) return V -> isConstant


<s> if ( ! TARGET_AVX ) return - <NUM_LIT> ; return TARGET_AVX512F ? <NUM_LIT> : TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; case 'd' : if ( ! TARGET_AVX2 ) return - <NUM_LIT> ; return TARGET_AVX512F ? <NUM_LIT> : <NUM_LIT> ; case 'e' : if ( ! TARGET_AVX512F ) return - <NUM_LIT> ; return <NUM_LIT>


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Length = Length ; return


<s> return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> ,


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const


<s> if ( Start -> getOpcode ( ) == <STR_LIT> ) { TPNumElements = Start -> getOperand ( <NUM_LIT> ) ; StartInsertPt = Start ; StartInsertBB = Start -> getParent ( ) ; } else { TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; MCRegister NumElements = TPNumElements . getReg ( ) . asMCReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StartInsertPt != StartInsertBB -> end ( ) && ! RDA . isReachingDefLiveOut ( & * StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( StartInsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , & * StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements )


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . has<ISA_LIT>3 ( ) && Subtarget . abiUsesSoftFloat ( )


<s> static __inline vec_ullong2 spu_cmpeq ( vec_double2 a , vec_double2 b ) { return ( ( vec_ullong2 ) ( si_dfceq ( ( qword ) ( a ) , ( qword ) (


<s> unsigned ChooseFrameReg ( unsigned Size ) const { static const MCPhysReg Candidates [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned Reg : Candidates ) { if ( ! std :: count ( BusyRegs . begin ( ) , BusyRegs . end ( ) , Reg ) ) return convReg ( Reg , Size ) ; } return


<s> return ( int32x2_t ) __builtin_aarch64_sqshl_nv2si (


<s> unsigned LinkageSize = <ISA_LIT>SubTarget -> getFrameLowering ( ) -> getLinkageSize ( ) ; CCInfo . AllocateStack ( LinkageSize , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeCallOperands ( ArgVTs , ArgFlags , CC_<ISA_LIT>64_ELF_FIS ) ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> || ArgVT == <STR_LIT> || ! VA . isRegLoc ( ) || VA . needsCustom ( ) ) return false ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) return false ; } NumBytes = CCInfo . getNextStackOffset ( ) ; NumBytes = std :: max ( NumBytes , LinkageSize + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameSetupOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; unsigned NextGPR = <STR_LIT> ; unsigned NextFPR = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign ::


<s> static bool isAddSubSExt ( SDNode * N , SelectionDAG & DAG ) { unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDNode * N0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * N1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; return N0 -> hasOneUse ( ) && N1 -> hasOneUse ( ) && isSignExtended ( N0 , DAG ) && isSignExtended


<s> MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( ! ( DstVT == <STR_LIT> && SrcVT == <STR_LIT> ) && ! ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) ) return SDValue ( ) ; SDLoc dl (


<s> SDValue CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; MVT LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask1 = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 , Mask1 ) ; if ( ConstantFPSDNode * Op0CN = dyn_cast < ConstantFPSDNode > ( Op0 ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; if ( APF . isPosZero ( ) ) return DAG . getNode ( <STR_LIT> , dl , SrcVT , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits ,


<s> const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; if ( ! CN ) return false ; bool IsExact ; APSInt IntVal ( <NUM_LIT> , true ) ; CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * C ) { if ( ! FuncInfo . StaticAllocaMap . count ( C ) ) return <NUM_LIT> ; assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ?


<s> Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , &

RetOps [ <NUM_LIT> ] , RetOps . size ( ) ) ;


<s> void pa_asm_output_aligned_local ( FILE * stream , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { switch_to_section ( bss_section ) ; fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; fprintf ( stream , <STR_LIT> , LOCAL_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( stream , name


<s> if ( LQR != MachineBasicBlock :: LQR_Dead ) return false ; if ( OrigDestSize == <NUM_LIT> ) { unsigned UpperByteReg = get<ISA_LIT>SubSuperRegister ( SuperDestReg , <NUM_LIT> , true ) ; LQR = OrigMI -> getParent ( ) -> computeRegisterLiveness ( & TII -> getRegisterInfo ( ) , UpperByteReg , OrigMI ) ; if ( LQR != MachineBasicBlock :: LQR_Dead ) return false ; } return


<s> reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } if ( rc == RELOAD_REG_VMX && msize == <NUM_LIT> && ( addr_mask & RELOAD_REG_VALID ) != <NUM_LIT> ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ]


<s> return ( __m128i ) __builtin_ia32_vcvttph2uw128_mask ( __C ,


<s> firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; lastRegToSaveIndex = <NUM_LIT> ; } unsigned ArgRegsSize , ArgRegsSaveSize ; computeRegArea ( CCInfo , MF , InRegsParamRecordIdx , ArgSize , ArgRegsSize , ArgRegsSaveSize ) ; if ( ArgRegsSaveSize ) { unsigned Padding = ArgRegsSaveSize - ArgRegsSize ; if ( Padding ) { assert ( AFI -> getStoredByValParamsPadding ( ) == <NUM_LIT> && <STR_LIT> ) ; AFI -> setStoredByValParamsPadding ( Padding ) ; } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) { const TargetRegisterClass *


<s> bool <ISA_LIT>TargetLowering :: reduceSelectOfFPConstantLoads ( bool


<s> static __inline int _mm_getwcx ( const int __regno ) { switch ( __regno ) { case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> bool <ISA_LIT>SelectionDAGInfo :: isBaseRegConflictPossible ( SelectionDAG & DAG , ArrayRef < unsigned > ClobberSet ) const { MachineFrameInfo * MFI = DAG . getMachineFunction


<s> Parser . Lex ( ) ; SMLoc RegLoc = Parser . getTok ( ) . getLoc ( ) ; int Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned FirstReg = Reg ; unsigned Count = <NUM_LIT> ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Count ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly


<s> return ( vector signed int ) __builtin_altivec_vspltisw (


<s> for ( Value * Op : I -> operands ( ) ) if ( ! isa < LoadInst > ( Op ) && ! isa < ConstantInt > ( Op ) ) ExtCost ++ ; return ExtCost


<s> __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; return ret


<s> rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , <NUM_LIT> ) , XEXP ( test , <NUM_LIT> ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode


<s> } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC =


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple TheTriple ( TT ) ; RM = TheTriple . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; } X -> InitMCCodeGenInfo ( RM , CM ,


<s> if ( IsSlow3OpsLEA ) { if ( auto * NewMI = processInstrForSlow3OpLEA ( * I , MFI ) ) { MFI -> erase ( I ) ; I = NewMI ; } continue ; } processInstruction ( I ,


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , ReservedGPRegisters ( <STR_LIT> . getNumRegs ( ) ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo


<s> BlockInfo . resize ( MF -> getNumBlockIDs ( ) ) ; unsigned Offset = <NUM_LIT> ; for ( MachineBasicBlock & MBB : * MF ) { const Align Alignment = MBB . getAlignment (


<s> return :: isUNPCKHMask ( N -> getMask ( ) , N

-> getValueType ( <NUM_LIT> ) , HasAVX2 , V2IsSplat ) ;


<s> static void adjustSubwordCmp ( SelectionDAG & DAG , SDLoc DL , Comparison & C ) { if ( ! C . Op0 . hasOneUse ( ) || C . Op0 . getOpcode ( ) != <STR_LIT> || C . Op1 . getOpcode ( ) != <STR_LIT> ) return ; auto * Load = cast < LoadSDNode > ( C . Op0 ) ; unsigned NumBits = Load -> getMemoryVT ( ) . getStoreSizeInBits ( ) ; if ( NumBits != <NUM_LIT> && NumBits != <NUM_LIT> ) return ; auto * ConstOp1 = cast < ConstantSDNode > ( C . Op1 ) ; uint64_t Value = ConstOp1 -> getZExtValue ( ) ; uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Load -> getExtensionType ( ) == <STR_LIT> ) { int64_t SignedValue = ConstOp1 -> getSExtValue


<s> SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX512 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32

( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ;


<s> if ( LDN ) AddrOp = LDN -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( AddrOp . getOpcode ( ) == <STR_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOperand ( <NUM_LIT> ) ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI -> getIndex ( ) ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; } return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm ) && ! ( Imm % Val ) ; } return AddrOp . getOpcode (


<s> MVT LogicVT ; MVT EltVT ; unsigned NumElts ; if ( VT . isVector ( ) ) { LogicVT = VT ; EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } else if ( IsF128 ) { LogicVT = <STR_LIT> ; EltVT = VT ; NumElts = <NUM_LIT> ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ; SDValue LogicNode = DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LogicNode , DAG .

getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> return __builtin_ia32_vcvtpd2ph256_mask ( ( __v4df ) __A , _mm_setzero_ph ( ) , ( __mmask8


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return

MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } return DAG . getMaskedStore ( Mst -> getChain ( ) , dl , TruncatedVal , Mst -> getBasePtr ( ) , NewMask , StVT , Mst -> getMemOperand


<s> static bool is_end_basic_block ( enum


<s> if ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } if ( SCALAR_FLOAT_MODE_P ( mode ) ) return emit_insn_after ( gen_consttable_float ( value )


<s> if ( hasYmmReg ( MI ) ) { CurState = ST_DIRTY ; continue ; } if ( ! isControlFlow ) continue ; if ( MI -> isCall ( ) && ! clobbersAnyYmmReg ( MI ) ) continue ; BBHasCall = true ; if ( CurState == ST_DIRTY ) { if ( EntryState != ST_UNKNOWN ) { BuildMI ( BB , I , dl , TII -> get ( <STR_LIT> ) ) ; ++ NumVZU ; } CurState = ST_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << BBNum << <STR_LIT> << CurState << '\n' ) ; if ( EntryState != ST_UNKNOWN || ( ! BBHasCall && CurState != ST_UNKNOWN ) ) BBSolved [ BBNum ] = true ; if ( CurState != BBState [ BBNum ] ) Changed = true ; BBState [ BBNum ] = CurState ; return Changed


<s> void EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( const MCSubtargetInfo & STI , unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; void EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI ,


<s> unsigned NewOpc = getNonFlagSettingVariant ( II . getOpcode ( ) ) ; int DeadNZCVIdx = II . findRegisterDefOperandIdx ( <STR_LIT> ) ; if ( DeadNZCVIdx != - <NUM_LIT> ) { if ( InsideCmpRange && NewOpc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << II ) ; II . setDesc ( TII -> get ( NewOpc ) ) ; II . RemoveOperand ( DeadNZCVIdx ) ; constrainOperandRegClass ( MF , * TRI , MRI , * TII , * RBI , II , II . getDesc ( ) , II . getOperand ( <NUM_LIT> ) , <NUM_LIT> ) ; Changed |= true ; } else { II . getOperand ( DeadNZCVIdx ) . setIsDead ( ) ; } } } NZCVDead = NZCVDeadAtCurrInstr ; } return Changed


<s> BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode

:: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ! BytesAdded && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } bool FallThru = FBB == nullptr ; unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) )

. addMBB ( TBB ) . addImm ( <STR_LIT> ) ;


<s> optimizeCompareZero ( MachineInstr * Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { if ( ! isCompareZero ( Compare ) ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock & MBB = * Compare -> getParent ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = MBB . begin ( ) ; Reference CCRefs ; Reference SrcRefs ; while ( MBBI != MBBE ) { -- MBBI ; MachineInstr * MI = MBBI ; if ( resultTests ( MI , SrcReg ) ) { if ( ! CCRefs . Use && ! SrcRefs && convertToBRCT ( MI , Compare , CCUsers


<s> int ShuffleModulus = Mask . size ( ) * ( IsSingleInput ? <NUM_LIT> : <NUM_LIT> ) ; assert ( isPowerOf2_32 ( ( uint32_t ) ShuffleModulus ) && <STR_LIT> ) ; uint64_t ModMask = ( uint64_t ) ShuffleModulus - <NUM_LIT> ; bool ViableForN [ <NUM_LIT> ] = { true , true , true } ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) continue ; bool IsAnyViable = false ; for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) { uint64_t N = j + <NUM_LIT> ; if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t ) i << N ) & ModMask ) ) IsAnyViable = true ; else ViableForN [ j ] = false ; } if ( ! IsAnyViable


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> static SDValue performSpliceCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return N ->


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_storeu_epi32 ( void *


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false ,


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant (


<s> fprintf ( asm_out_file , <STR_LIT> ) ; } else fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; } else if ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && ! TARGET_RELOCATABLE ) fprintf ( asm_out_file , <STR_LIT> , TOC_SECTION_ASM_OP ) ; else { fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; if ( ! toc_initialized ) { ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; toc_initialized =


<s> static bool isUseOfShuffle ( SDNode * N ) { for ( auto * U : N ->


<s> if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p (


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; O << <STR_LIT> (


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type *


<s> b = ( __vector signed char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c ,


<s> return isMem ( MemKind , RegKind ) && inRange ( Mem . Disp ,


<s> } if ( eop0 . ext_code != UNKNOWN && eop1 . ext_code == UNKNOWN ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = simplify_gen_subreg ( subreg_mode , operands [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) , subreg_offset ) ; emit_insn ( subreg_mode == QImode ? gen_zero_extendqisi2 ( tmp0 , tmp1 ) : gen_zero_extendhisi2 ( tmp0 , tmp1 ) ) ; emit_insn ( gen_tstsi_t ( tmp0 , operands [


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetDsp ( ) { setCanHaveModuleDir ( false )


<s> if ( ( offsets -> outgoing_args != ( <NUM_LIT> + num_regs ) ) || cfun -> calls_alloca ) { rtx_insn * insn ; emit_insn ( gen_blockage ( ) ) ; insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - <NUM_LIT> * num_regs ) ) ) ; arm_add_cfa_adjust_cfa_note ( insn , - <NUM_LIT> * num_regs , stack_pointer_rtx , hard_frame_pointer_rtx ) ; } arm_emit_multi_reg_pop ( saved_regs_mask ) ; if ( IS_INTERRUPT ( func_type ) ) { rtx_insn * insn ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; insn = emit_insn ( gen_movsi ( gen_rtx_REG ( SImode , IP_REGNUM ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , IP_REGNUM ) , NULL_RTX ) ; } if ( ! really_return || ( saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ) ) return ; if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , gen_rtx_REG ( SImode , ARM_EH_STACKADJ_REGNUM ) ) ) ; if ( IS_STACKALIGN ( func_type ) ) emit_insn ( gen_movsi ( stack_pointer_rtx , gen_rtx_REG ( SImode , R0_REGNUM ) ) ) ; emit_jump_insn (


<s> void <ISA_LIT>SEInstrInfo :: expandRetRA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const auto & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isGP64bit ( ) ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , I , I -> getDebugLoc ( )


<s> return TFI -> hasFP ( MF ) ? ( IsN64 ? <STR_LIT> : <STR_LIT> ) : ( IsN64 ? <STR_LIT>


<s> if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return <NUM_LIT> ; } return getIntImmCost ( Imm , Ty , CostKind


<s> PrivateLabelPrefix = <STR_LIT> ; SupportsDebugInformation = true ; UseIntegratedAssembler =


<s> if ( NElts <= <NUM_LIT> ) return <STR_LIT> ; for ( unsigned nVT = <STR_LIT> ; nVT <= <STR_LIT> ; ++ nVT ) { MVT SVT = ( <STR_LIT> ) nVT ; if ( isTypeLegal ( SVT ) && SVT . getVectorElementType ( ) ==

EltVT && SVT . getVectorNumElements ( ) > NElts ) return SVT ;


<s> assert ( Kind == k_CondCode && <STR_LIT> ) ; return CondCode .


<s> switch ( mode ) { case CC_DNEmode : return NE ; case CC_DEQmode : return EQ ; case CC_DLEmode : return LE ; case CC_DGTmode : return GT ; case CC_DLTmode : return LT ; case CC_DGEmode : return GE ; case CC_DLEUmode : return LEU ; case CC_DGTUmode


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( UseCmp ) { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IEEE_P ( src_mode ) ) { if ( src_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( src_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( dest_mode ) { case E_DFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_df ; break ; case E_SFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( dest_mode ) ) cvt = trunc_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IBM_P ( dest_mode ) && FLOAT128_IBM_P ( src_mode ) ) do_move = true ; else gcc_unreachable ( ) ; if ( do_move ) emit_move_insn ( dest , gen_lowpart ( dest_mode , src ) ) ; else if ( TARGET_FLOAT128_HW && hw_convert ) emit_insn ( ( hw_convert ) ( dest , src ) ) ; else if ( cvt != unknown_optab ) { libfunc = convert_optab_libfunc ( cvt , dest_mode , src_mode ) ; gcc_assert ( libfunc != NULL_RTX ) ; dest2 = emit_library_call_value ( libfunc , dest , LCT_CONST , dest_mode ,


<s> tree impl_fndecl = rs6000_builtin_decls [ desc -> overloaded_code ] ; tree ret_type = rs6000_builtin_type ( desc -> ret_type ) ; tree argtypes = TYPE_ARG_TYPES ( TREE_TYPE ( impl_fndecl ) ) ; tree arg_type [ <NUM_LIT> ] ; tree call ; int i ; for ( i = <NUM_LIT> ; i < n ; i ++ ) arg_type [ i ] = TREE_VALUE ( argtypes ) , argtypes = TREE_CHAIN ( argtypes ) ; if ( desc -> code == ALTIVEC_BUILTIN_VEC_VCMPGE_P && desc -> overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P && desc -> overloaded_code != VSX_BUILTIN_XVCMPGEDP_P ) { tree t ; t = args [ <NUM_LIT> ] , args [ <NUM_LIT> ] = args [ <NUM_LIT> ] , args [ <NUM_LIT> ] = t ; t = arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] = arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] = t ; args [ <NUM_LIT> ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ <NUM_LIT> ] ) , args [ <NUM_LIT> ] , build_int_cst ( NULL_TREE , <NUM_LIT> ) ) ; } switch ( n ) { case <NUM_LIT> : call = build_call_expr ( impl_fndecl , <NUM_LIT> ) ; break ; case <NUM_LIT> : call = build_call_expr ( impl_fndecl , <NUM_LIT> , fully_fold_convert ( arg_type [ <NUM_LIT> ]


<s> void <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { assert ( InProlog &&


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseRegForGlobalISel ( MachineFunction & MF ) { if ( static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . useCheriCapTable ( ) ) { if ( ! CapGlobalBaseReg ) { getCapGlobalBaseReg ( MF ) ; initCapGlobalBaseReg ( MF ) ; } return CapGlobalBaseReg ; } if ( !


<s> AddValueSymbols_ ( getSubExpr ( ) , Asm


<s> SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; unsigned FirstOp ; unsigned StorageOpcode = N -> getMachineOpcode ( ) ; bool RequiresMod4Offset = false ; switch ( StorageOpcode ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else { if ( auto * C = dyn_cast < ConstantSDNode


<s> <STR_LIT> ) ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; return


<s> if ( Offset % Scale == <NUM_LIT> && ( ( Offset / Scale ) & ~ Mask ) == <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Offset / Scale ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset / Scale ) ; } return true ; } unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Bytes = ( Offset > <NUM_LIT> ) ? Offset : - Offset ; unsigned NumMIs = calcNumMI ( Opcode , <NUM_LIT> , Bytes , NumBits , Scale ) ; if ( NumMIs > <NUM_LIT> ) { emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } if ( Offset > <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = std :: next ( II ) ; emitThumbRegPlusImmediate ( MBB , NII , dl , DestReg , DestReg , Offset , TII , * this ) ; } else { emitThumbConstant ( MBB , II , DestReg , Offset , TII , * this , dl ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( DestReg , false , false , true ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false ) ; } return true ; } else


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo


<s> if ( GET_CODE ( disp ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( disp , <NUM_LIT> ) ) ) return false ; disp = XEXP ( disp , <NUM_LIT> ) ; saw_plus = true ; } if ( TARGET_MACHO && darwin_local_data_pic ( disp ) ) return true ; if ( GET_CODE ( disp ) != UNSPEC ) return false ; switch ( XINT ( disp , <NUM_LIT> ) ) { case UNSPEC_GOT : if ( saw_plus ) return false ; return ( GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) ; case UNSPEC_GOTOFF : if ( ( GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) && ! TARGET_64BIT ) return ! TARGET_PECOFF && gotoff_operand ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) , Pmode ) ; return false ; case UNSPEC_GOTTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : if ( saw_plus ) return false ; disp = XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( disp ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( disp ) == TLS_MODEL_INITIAL_EXEC ) ; case UNSPEC_NTPOFF : disp = XVECEXP ( disp , <NUM_LIT>


<s> MachineOperand LDWb ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( LDWb ) ; } else { LDM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } if ( isThumb1 || ! MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { MachineOperand STWb ( MI -> getOperand ( <NUM_LIT> ) ) ; STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ) ) . add ( STWb ) ; } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT>


<s> static DecodeStatus DecodeQPairRegisterClass ( llvm :: MCInst & Inst , unsigned

RegNo , uint64_t Address , const void * Decoder ) {


<s> bool isCtlzFast ( ) const override { return true


<s> } else if ( getEMachine ( ) == ELF :: EM_386 ) { if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case FK_PCRel_1 : case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC8 ; break ; } break ; case FK_PCRel_2 : case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC16 ; break ; } break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_32 ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_386_GOT32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_386_GOTOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_386_TLS_GD ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_386_TLS_LE_32


<s> MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg


<s> break ; case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ) ; break ; case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; case <STR_LIT> : case <STR_LIT> : assert ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; MovePCtoLROffset = ( void * ) MCE . getCurrentPCValue ( ) ; MCE . emitWordBE ( <NUM_LIT> )


<s> assert ( Section && <STR_LIT> ) ; if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> return __builtin_mve_vmovlbq_m_uv16qi ( __arm_vuninitializedq_u16 ( )


<s> if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Reserved . set ( <STR_LIT> + i ) ; } return


<s> void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf (

asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP ) ; \ in_section = in_const ; \ } \ }


<s> UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; } unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode ; if ( ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) || ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) ) Opcode = LowerOpcode ; else Opcode = UpperOpcode ; MI . setDesc ( get ( Opcode ) ) ; return true ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) { MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else { NumStoreSPILLVSRRCAsGpr ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; } return true ; } case <STR_LIT> : { unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) MI . setDesc ( get ( <STR_LIT> ) ) ; else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; }


<s> if ( MBBI == MBB . begin ( ) ) return false ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; MachineBasicBlock :: iterator PrevInst = MBBI ; -- PrevInst ; if ( isDelayFiller ( MBB , PrevInst )


<s> int getRAIndex ( ) const { return ReturnAddrIndex


<s> bool <ISA_LIT>AsmParser :: parseDataDirective ( unsigned Size , SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex


<s> bool mep_expand_binary_intrinsic ( int ATTRIBUTE_UNUSED immediate , int ATTRIBUTE_UNUSED immediate3 , int ATTRIBUTE_UNUSED reg , int ATTRIBUTE_UNUSED reg3 , rtx * operands


<s> const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm


<s>
assert
(
!
Operands
.
empty
(
)
&&
<STR_LIT>
)
;
assert
(
(
*
Operands
[
<NUM_LIT>
]
)
.
isToken
(
)
&&
<STR_LIT>
)
;
SMRange
EmptyRange
=
;
MatchFPUWaitAlias
(
IDLoc
,
static_cast
<
<ISA_LIT>Operand
&
>
(
*
Operands
[
<NUM_LIT>
]
)
,
Operands
,
Out
,
MatchingInlineAsm
)
;
<ISA_LIT>Operand
&
Op
=
static_cast
<
<ISA_LIT>Operand
&
>
(
*
Operands
[
<NUM_LIT>
]
)
;
unsigned
Prefixes
=
getPrefixes
(
Operands
)
;
MCInst
Inst
;
if
(
ForcedVEXEncoding
==
VEXEncoding_VEX3
)
Prefixes
|=
<STR_LIT>
;
if
(
Prefixes
)
Inst
.
setFlags
(
Prefixes
)
;
FeatureBitset
MissingFeatures
;
unsigned
OriginalError
=
MatchInstruction
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
switch
(
OriginalError
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
Match_Success
:
if
(
!
MatchingInlineAsm
&&
validateInstruction
(
Inst
,
Operands
)
)
return
true
;
if
(
!
MatchingInlineAsm
)
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_InvalidImmUnsignedi4
:
{
SMLoc
ErrorLoc
=
(
(
<ISA_LIT>Operand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
return
Error
(
ErrorLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
}
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
MissingFeatures
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
case
Match_MnemonicFail
:
case
Match_Unsupported
:
break
;
}
if
(
Op
.
getToken
(
)
.
empty
(
)
)
{
Error
(
IDLoc
,
<STR_LIT>
,
EmptyRange
,
MatchingInlineAsm
)
;
return
true
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
FeatureBitset
ErrorInfoMissingFeatures
;
unsigned
Match
[
<NUM_LIT>
]
;
for
(
unsigned
I
=
<NUM_LIT>
,
E
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++
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{
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MatchInstruction
(
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isParsingIntelSyntax
(
)
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if
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}
Op
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unsigned
NumSuccessfulMatches
=
std
::
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(
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begin
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std
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if
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{
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<s> EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( InVT . isScalableVector ( ) ) { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( VT ) || ! VT . isInteger ( ) ) return SDValue ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementCount ( ) != ( InVT . getVectorElementCount ( ) * <NUM_LIT> ) ) return SDValue ( ) ; EVT WideVT = InVT . widenIntegerVectorElementType ( * ( DAG . getContext ( )


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF .


<s> bool hasFP ( const MachineFunction & ) const override { return


<s> char * p ; int dollar_inside = <NUM_LIT> ; struct declare_alias_data data = { file , false } ; strcpy ( buffer , name ) ; p = strchr ( buffer , '$' ) ; while ( p ) { * p = '_' ; dollar_inside ++ ; p = strchr ( p + <NUM_LIT> , '$' ) ; } if ( TREE_PUBLIC ( decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( decl ) ) { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; putc ( '\n' , file ) ; } } else { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; putc ( '\n' , file ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , &


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } unsigned ValReg = getRegForValue


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction


<s> if ( IsStrict ) { Src = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Src } ) ; Chain = Src . getValue ( <NUM_LIT> ) ; } else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; } SDValue Conv ; unsigned Opc = <STR_LIT> ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = IsSigned ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : assert ( ( IsSigned || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Opc = IsSigned ? <STR_LIT> :


<s> if ( ! isImm ( ) || ! evaluateConstantImm ( getImm ( ) , Imm ) )


<s> static const TargetRegisterClass * getRegClassForSVT ( <STR_LIT> SVT , bool Is<ISA_LIT>64 , bool HasP8Vector , bool HasVSX ) { assert ( ( Is<ISA_LIT>64 || SVT != <STR_LIT> ) && <STR_LIT> ) ; switch ( SVT ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: AddMVEPredicateToOps ( SDValueVector & Ops , SDLoc Loc , SDValue PredicateMask , SDValue Inactive ) { Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> ip = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_ip_value ( ip ) ) ; emit_library_call ( gen_mcount_func_rtx ( ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , gen_rtx_REG ( Pmode , BR_REG (

<NUM_LIT> ) ) , Pmode , ip , Pmode , label , Pmode ) ;


<s> MI . setFlags ( Flags ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: IsExact


<s> static DecodeStatus DecodeGPRRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [


<s> } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> void <ISA_LIT>InstrInfo :: StoreRegToStackSlot ( MachineFunction & MF , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Opcode = getStoreOpcodeForSpill ( RC ) ; DebugLoc DL ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills


<s> const LLT Ty = MRI . getType ( LHS ) ; auto Const = getIConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! Const ) return false ; const APInt ConstValue = Const -> Value . sextOrSelf ( Ty . getSizeInBits ( ) ) ; unsigned TrailingZeroes = ConstValue . countTrailingZeros ( ) ; if ( TrailingZeroes ) { if ( MRI . hasOneNonDBGUse ( LHS ) && ( isSignExtended ( LHS , MRI ) || isZeroExtended ( LHS , MRI ) ) ) return false ; if ( MRI . hasOneNonDBGUse ( Dst ) ) { MachineInstr & UseMI = * MRI . use_instr_begin ( Dst ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; if ( UseOpc == TargetOpcode :: G_ADD || UseOpc == TargetOpcode :: G_PTR_ADD || UseOpc == TargetOpcode :: G_SUB ) return false ; } } APInt ShiftedConstValue = ConstValue . ashr ( TrailingZeroes ) ; unsigned ShiftAmt , AddSubOpc ; bool ShiftValUseIsLHS = true ; bool NegateResult = false ; if ( ConstValue . isNonNegative ( ) ) { APInt SCVMinus1 = ShiftedConstValue - <NUM_LIT> ; APInt CVPlus1 = ConstValue + <NUM_LIT> ; if ( SCVMinus1 . isPowerOf2 ( ) ) { ShiftAmt = SCVMinus1 . logBase2 ( ) ; AddSubOpc = TargetOpcode :: G_ADD ; } else if ( CVPlus1 . isPowerOf2 ( ) ) { ShiftAmt = CVPlus1 . logBase2 ( ) ; AddSubOpc = TargetOpcode :: G_SUB ; } else return false ; } else { APInt CVNegPlus1 = - ConstValue + <NUM_LIT> ; APInt CVNegMinus1 = - ConstValue - <NUM_LIT> ; if ( CVNegPlus1 . isPowerOf2 ( ) ) { ShiftAmt = CVNegPlus1 . logBase2 ( ) ; AddSubOpc = TargetOpcode :: G_SUB ; ShiftValUseIsLHS = false ; } else if ( CVNegMinus1 . isPowerOf2 ( ) ) { ShiftAmt = CVNegMinus1 . logBase2 ( ) ; AddSubOpc = TargetOpcode :: G_ADD ; NegateResult = true ; } else return false ; } if ( NegateResult && TrailingZeroes ) return false ; ApplyFn = [ = ] ( MachineIRBuilder & B , Register DstReg ) { auto Shift = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , ShiftAmt ) ; auto ShiftedVal = B . buildShl ( Ty , LHS , Shift ) ; Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal . getReg ( <NUM_LIT> ) : LHS ; Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal . getReg ( <NUM_LIT> ) ; auto Res = B . buildInstr ( AddSubOpc , { Ty } , { AddSubLHS , AddSubRHS } ) ; assert ( ! ( NegateResult && TrailingZeroes ) && <STR_LIT> ) ; if ( NegateResult ) { B . buildSub ( DstReg , B . buildConstant ( Ty , <NUM_LIT> ) , Res ) ; return ; } if ( TrailingZeroes ) { B . buildShl ( DstReg , Res , B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) ,


_mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) { if ( VectorType * VTy = dyn_cast < VectorType > ( Src ) ) { unsigned NumElem = VTy -> getVectorNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( )


<s> EmitAlignment ( <NUM_LIT> ) ; const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; O << * Stub << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << <STR_LIT> ; O << <STR_LIT> << * AnonSymbol << '\n' ; O << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; OutStreamer . SwitchSection ( LSPSection ) ; O << * LazyPtr << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; } O << '\n' ; return ; } const MCSection * StubSection = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; O << * Stub << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << <STR_LIT> << * LazyPtr <<


<s> const MachineInstrBuilder & <ISA_LIT>BaseInstrInfo :: AddDReg ( MachineInstrBuilder & MIB , unsigned Reg , unsigned SubIdx , unsigned

State , const TargetRegisterInfo * TRI ) const {


<s> const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = <NUM_LIT> ; if ( nregs <= <NUM_LIT> )


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { assert ( CC != CallingConv


<s> static inline uint64_t decodeAdvSIMDModImmType5 ( uint8_t Imm ) { uint64_t EncVal


<s> assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; int ShufIdxs [ <NUM_LIT> ] ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VMRGHW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VMRGLW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs


<s> CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( Imm == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return true ; } if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Imm2 ) ) { unsigned MB , ME ; if ( isRunOfOnes ( ~ ( Imm ^ Imm2 ) , MB , ME ) && ! ( ~ Imm & Imm2 ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ) ; return true ; } } } else if ( isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) ) { if ( isMask_64 ( Imm64 ) ) { MB = <NUM_LIT> - countTrailingOnes ( Imm64 ) ; SH = <NUM_LIT> ; if ( Val . getOpcode ( ) == <STR_LIT> ) { auto Op0 = Val . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Op0 . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm


<s> return Kind == Memory && ( ! Mem . Size


<s> BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> getInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = & * MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getITInstrPredicate ( * MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; } if ( STI -> isTargetWindows ( ) && isThumb && MI -> getOpcode ( ) == <STR_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) { -- MI ; assert ( MI -> getOpcode ( ) == <STR_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT>


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this


<s> arm_print_asm_arch_directives ( stream , targ_options ) ; fprintf ( stream , <STR_LIT> ) ; if ( TARGET_THUMB ) { if ( is_called_in_ARM_mode ( decl ) || ( TARGET_THUMB1 && ! TARGET_THUMB1_ONLY && cfun -> is_thunk ) ) fprintf ( stream , <STR_LIT> ) ; else if ( TARGET_THUMB1 ) fprintf ( stream , <STR_LIT> ) ; else fprintf ( stream , <STR_LIT> ) ; } else fprintf ( stream , <STR_LIT>


<s> if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime =


<s> static int aarch64_sched_issue_rate (


<s> MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock ( MBB


<s> mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return


<s> rtx_insn * i0 ; if ( from_mode == QImode ) i0 = emit_insn_after ( gen_extendqisi2 ( r , set_src ) , insn ) ; else if ( from_mode == HImode ) i0 = emit_insn_after ( gen_extendhisi2 ( r , set_src ) , insn ) ; else gcc_unreachable ( ) ; emit_insn_after ( gen_move_insn ( XEXP ( set_rtx , <NUM_LIT> ) , gen_lowpart ( GET_MODE ( set_src ) , r ) ) , i0 ) ; set_insn_deleted ( insn ) ; return r ; } else { rtx extension_dst = XEXP ( set_rtx , <NUM_LIT> ) ; if ( GET_MODE ( extension_dst ) != SImode ) extension_dst = simplify_gen_subreg ( SImode , extension_dst , GET_MODE ( extension_dst ) , <NUM_LIT> ) ; if ( modified_between_p ( extension_dst , insn , use_at_insn ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , REGNO ( extension_dst ) , INSN_UID ( insn ) ) ; rtx r = gen_reg_rtx ( SImode ) ; emit_insn_after ( gen_move_insn ( r , extension_dst ) ,


<s> struct unw_table_entry * ent ; unsigned long segment_base , gp ; ent = _Unwind_FindTableEntry ( pc , & segment_base


<s> return ( __m256d ) __builtin_ia32_cvtps2pd256 ( ( __v4sf )


<s> return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , ( T . getArch (

) == Triple :: thumb || T . getArch ( ) == Triple :: thumbeb ) ) ;


<s> SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , NumMaskElts ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; if ( CCVT . getSizeInBits ( ) != ResVT . getSizeInBits ( ) ) return SDValue ( ) ; assert ( DCI . isBeforeLegalize ( ) || DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > DUPMask ( CCVT

. getVectorNumElements ( ) , <NUM_LIT> ) ;


<s> const Constant * C = CP -> getConstVal ( ) ; if ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , true , GA ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , Subtarget , MOHiFlag , MOLoFlag ) ; if ( isPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , false , GA ) ; } SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo ,


<s> bool isTargetWindows ( ) const { return TargetTriple . isOSWindows (


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_WrappedRegister , S , E ) ; Op -> Reg . RegNum =


<s> FnStart = NULL ; Personality = NULL ; PersonalityIndex = <STR_LIT> :: NUM_PERSONALITY_INDEX ; FPReg = <STR_LIT> ; FPOffset =


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ; OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize / Scale ) ; if ( NeedsWinCFI ) { * HasWinCFI = true ; auto MBBI = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; assert ( MBBI != MI . getParent ( ) -> end ( )