<s> for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case <NUM_LIT> : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - <NUM_LIT> ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case <NUM_LIT> : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence (


<s> BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode (


<s> SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { APInt DemandedBits ( APInt :: getSignMask ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedBits , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewMask = TLI . SimplifyMultipleUseDemandedBits ( Mask , DemandedBits , DAG ) ) return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Mst -> getValue ( ) , Mst -> getBasePtr ( ) , Mst -> getOffset ( ) , NewMask , Mst -> getMemoryVT ( ) , Mst -> getMemOperand ( )


<s> void insertLoadAfterStores ( MachineFunction & MF ) { const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I ) { bool check = true ; if ( I -> mayStore ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } default : { I -> dump ( ) ; errs ( ) << <STR_LIT> ; check = false ; } } if ( check


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return true


<s> int getFramePointerRegister ( ) override final { return <STR_LIT>


<s> if ( Reg == <NUM_LIT> ) Reg = RS -> scavengeRegister ( RC ,


<s> bool Warning ( SMLoc L , const Twine & Msg ,


<s> FunctionPass * llvm :: create<ISA_LIT>CodeGenPreparePass


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; unsigned RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned RD2 = RegInfo . createVirtualRegister (


<s> if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false


<s> EVT PVT = LD -> getValueType ( <NUM_LIT> ) ; if ( PVT != <STR_LIT> && PVT != <STR_LIT> ) return SDValue ( ) ; int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int NumElems = VT . getVectorNumElements ( ) ; EVT CanonVT = VT . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> ; i < NumElems ; ++ i ) Mask . push_back ( EltNo ) ; V1 = DAG . getNode ( <STR_LIT> , dl , CanonVT , V1 ) ; return DAG . getNode ( <STR_LIT> , dl , NVT , DAG . getVectorShuffle ( CanonVT , dl , V1 ,

DAG . getUNDEF ( CanonVT ) , & Mask [ <NUM_LIT> ] ) ) ;


<s> Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ <NUM_LIT> ] , VA , MaxSize ) : Arg . Regs [ <NUM_LIT> ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO


<s> void startFunction ( MachineFunction & MF


<s> static SDValue lowerV16I32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT>


<s> MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; MachineBasicBlock * Latch = End -> getParent ( ) ; MachineInstr * Terminator = & Latch -> instr_back ( ) ; if ( End != Terminator ) { MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Latch -> isLayoutSuccessor ( Exit ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } End -> eraseFromParent ( ) ; Dec -> eraseFromParent ( ) ; } ; auto ExpandBranch = [ this ] ( MachineInstr * Dec , MachineInstr * End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * MBB = Dec -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Dec , Dec -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Dec -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( Dec -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT>


<s> const char * aarch64_output_casesi ( rtx * operands ) { char buf [ <NUM_LIT> ] ; char label [ <NUM_LIT> ] ; rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ <NUM_LIT> ] ) ) ) ; int index ; static const char * const patterns [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> ,


<s> void <ISA_LIT>LinuxAsmPrinter :: emitFunctionBodyStart ( ) { if ( Subtarget -> isELFv2ABI ( ) && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * GlobalEntryLabel = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; OutStreamer -> emitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ; const MCExpr * TOCOffsetDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCOffset , OutContext ) , GlobalEntryLabelExp , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> )

. addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64

( ) ) return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ;


<s> SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue Neg16 = BuildSplatI ( - <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue RHSSwap = BuildIntrinsicOp ( <STR_LIT> , RHS , Neg16 , DAG , dl ) ; LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; RHSSwap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHSSwap ) ; SDValue LoProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; SDValue HiProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHSSwap , Zero , DAG , dl , <STR_LIT> ) ; HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; bool isLittleEndian = Subtarget . isLittleEndian (


<s> * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } if ( known_eq ( GET_MODE_BITSIZE ( mode ) , <NUM_LIT> ) ) { * dst = adjust_address ( * dst , GET_MODE ( src ) , <NUM_LIT> ) ; emit_move_insn ( * dst , src ) ; * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } rtx reg = lowpart_subreg ( mode , src , GET_MODE ( src ) ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_move_insn ( * dst , reg ) ; * dst = aarch64_progress_pointer ( * dst


<s> ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; return ret


<s> return * ( Dis -> getRegInfo ( ) -> getRegClass ( RC


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; return false ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex ( ) ; return


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> Res = DAG . getNode ( Shuffle , DL , ShuffleVT , Res , Res ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Res ) , true ) ; return true ; } if ( NumMaskElts <= <NUM_LIT> && ( ( Subtarget . hasSSE41 ( ) && VT . is128BitVector ( ) ) || ( Subtarget . hasAVX ( ) && VT . is256BitVector ( ) ) ) ) { bool FloatDomain = VT . isFloatingPoint ( ) ; MVT ShuffleVT = FloatDomain ? <STR_LIT> ( MaskEltSizeInBits ) : <STR_LIT> ( MaskEltSizeInBits ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , NumMaskElts ) ; if ( Subtarget . hasAVX2 ( ) ) { if ( ShuffleVT == <STR_LIT> ) ShuffleVT = <STR_LIT> ; else if ( ShuffleVT == <STR_LIT> ) ShuffleVT = <STR_LIT> ; } else { if ( ShuffleVT == <STR_LIT> || ShuffleVT == <STR_LIT> ) ShuffleVT = <STR_LIT> ; else if ( ShuffleVT == <STR_LIT> ) ShuffleVT = <STR_LIT> ; else if ( ShuffleVT == <STR_LIT> ) ShuffleVT = <STR_LIT> ; } if ( isSequentialOrUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts , <NUM_LIT> ) && NumMaskElts <= ShuffleVT . getVectorNumElements ( ) ) { unsigned BlendMask = <NUM_LIT> ; unsigned ShuffleSize = ShuffleVT . getVectorNumElements ( ) ; unsigned MaskRatio = ShuffleSize / NumMaskElts ; if ( Depth == <NUM_LIT> && Root . getOpcode ( ) == <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != ShuffleSize ; ++ i ) if ( Mask [ i / MaskRatio ] < <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; SDValue Zero = getZeroVector ( ShuffleVT , Subtarget , DAG , DL ) ; Res = DAG . getBitcast ( ShuffleVT , Input ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Res , Zero , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Res ) , true ) ; return true ; } } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB ) && ( ( VT . is128BitVector ( ) && Subtarget . hasSSSE3 ( ) ) || ( VT

. is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . hasBWI ( ) ) ) ) {


__m512i __index , float const * __addr , int __scale ) {


<s> case <STR_LIT> : return SelectMoveImmediate ( N ) ; } return SelectCode ( N


<s> rtx start , end ; XVECEXP ( PATTERN ( new ) , <NUM_LIT> , <NUM_LIT> ) = PATTERN ( anchor ) ; XVECEXP ( PATTERN ( new ) , <NUM_LIT> , <NUM_LIT> ) = PATTERN ( floater ) ; INSN_CODE ( new ) = - <NUM_LIT> ; insn_code_number = recog_memoized ( new ) ; if ( insn_code_number < <NUM_LIT> || ( extract_insn ( new ) , ! constrain_operands ( <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( reversed ) { start = anchor ; end = floater ; } else { start = floater ; end = anchor ; } if ( reg_used_between_p ( dest , start , end ) ) return <NUM_LIT> ; if ( reg_set_between_p ( src1 , start , end ) )


<s> else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , <NUM_LIT> ) ; } else { if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold > <NUM_LIT> ) named_section ( <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ; else if ( flag_pic && symbolic_expression_p ( x ) ) named_section ( <NUM_LIT> , <STR_LIT>


<s> } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & <NUM_LIT> ; perm1 = ( perm1 & <NUM_LIT> ) + <NUM_LIT> ; } else if ( perm0 & <NUM_LIT> ) { if ( perm1 & <NUM_LIT> ) return false ; perm0 -= <NUM_LIT> ; perm1 += <NUM_LIT> ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) ==


<s> delete m_pRelocator ; delete m_pPLT ; delete m_pRelPlt ; delete m_pRelDyn ; delete m_pDynamic


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) || TT . isOSWindows ( ) || TT . isOSNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( )


<s> const auto & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; unsigned MinSVESize = Subtarget . getMinSVEVectorSizeInBits ( ) ; unsigned MaxSVESize = Subtarget . getMaxSVEVectorSizeInBits ( ) ; if ( MaxSVESize && MinSVESize == MaxSVESize && MaxSVESize == VT . getSizeInBits ( ) ) PgPattern = <STR_LIT> ; MVT MaskVT ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : MaskVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : MaskVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT>


<s> MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( BB , dl , TII . getBrCond ( CC ) ) . addMBB ( copy1MBB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; for ( MachineBasicBlock :: succ_iterator SI = BB -> succ_begin ( ) , SE = BB -> succ_end ( ) ; SI != SE ; ++ SI ) EM -> insert ( std :: make_pair ( * SI , copy1MBB ) ) ; copy1MBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI


<s> Value * Op0 = visit ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Constant * Initializer = Constant :: getAllOnesValue ( Op0 -> getType ( ) ) ; Value * Op1 = Initializer -> stripInBoundsConstantOffsets ( ) ; StringRef BaseName = getInstructionName ( N ) ; if ( BaseName . empty ( ) ) { BaseName = getBaseValueName ( Op0 -> getName ( ) ) ; } if ( BaseName . empty ( )


<s> void setRegSaveFrameIndex ( int Idx ) { RegSaveFrameIndex =


<s> unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static bool isVTBLMask ( ArrayRef < int > M , EVT VT ) { return VT == <STR_LIT> && M . size (


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , NeedStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue <ISA_LIT>TargetLowering :: LowerToPredicatedOp ( SDValue Op , SelectionDAG & DAG , unsigned NewOp , bool OverrideNEON ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; auto Pg = getPredicateForVector ( DAG , DL , VT ) ; if ( useSVEForFixedLengthVectorVT ( VT , OverrideNEON ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) , OverrideNEON ) &&


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) ,


<s> return __builtin_mve_vbicq_uv8hi ( __a ,


<s> SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , ThreadPointer


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode


<s> const MCExpr * Length ; if ( parseAddress ( Base , Disp , Index , Length , Regs , RegKind ) ) return MatchOperand_ParseFail ; if ( Index && MemKind != BDXMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length && MemKind == BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createMem ( RegKind , Base , Disp

, Index , Length , StartLoc , EndLoc ) ) ;


<s> rtx x = * iter ; if ( GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; unsigned MinSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Opcode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst MCI ; MCI . setOpcode ( Opcode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) MCI . addOperand ( MaybeOperand . getValue ( ) ) ; SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) <


<s> bool DstDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned AccReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const MCInstrDesc & MCID1 = TII -> get ( MulOpc ) ; const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred )


<s> StubLayout Result = { <NUM_LIT> * <NUM_LIT> + <NUM_LIT> , <NUM_LIT> } ; return


<s> if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) return true ; return false


<s> Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( ImmOp ) ; Out . EmitInstruction ( Tmp ) ; EmitRegFix ( <STR_LIT>


<s> gcc_assert ( ! ix86_eax_live_at_start_p ( ) ) ; gcc_assert ( m -> fs . sp_offset >= frame . sse_reg_save_offset ) ; align = GET_MODE_ALIGNMENT ( V4SFmode ) ; addr = choose_baseaddr ( frame . stack_realign_offset + xlogue . get_stub_ptr_offset ( ) , & align , AX_REG ) ; gcc_assert ( align >= GET_MODE_ALIGNMENT ( V4SFmode ) ) ; emit_insn ( gen_rtx_SET ( rax , addr ) ) ; sym = xlogue . get_stub_rtx ( frame_pointer_needed ? XLOGUE_STUB_SAVE_HFP : XLOGUE_STUB_SAVE ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; for ( i = <NUM_LIT> ; i < ncregs ; ++ i ) { const xlogue_layout :: reginfo & r = xlogue . get_reginfo ( i ) ; rtx reg = gen_rtx_REG ( ( SSE_REGNO_P ( r . regno )

? V4SFmode : word_mode ) , r . regno ) ;


<s> if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return SDValue ( ) ; unsigned NumSubElts = SubVT . getVectorNumElements ( ) ; if ( ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) != VecVT . getSizeInBits ( ) || ( IdxVal != <NUM_LIT> && IdxVal != NumSubElts ) ) return SDValue ( ) ; SDValue Lo , Hi ; if ( IdxVal == <NUM_LIT> ) { Lo = SubVec ; Hi = DAG . getNode ( <STR_LIT> , DL , SubVT , Vec , DAG . getVectorIdxConstant ( NumSubElts , DL ) ) ; } else { Lo = DAG . getNode ( <STR_LIT> , DL , SubVT , Vec , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; Hi =


<s> if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) if ( auto * Op1 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Val = Op1 -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) ) { splitLargeImmediate ( Opcode , Node , Node -> getOperand ( <NUM_LIT> ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) if ( tryRxSBG ( Node , <STR_LIT> ) ) return ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( tryRISBGZero ( Node ) ) return ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) { splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node ->


<s> void printGlobalOperand ( const MachineInstr * MI , unsigned OpNo ) { printOp ( MI -> getOperand ( OpNo


<s> if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; assert ( Options . getABIName ( ) . empty ( ) && <STR_LIT> ) ; if ( TT . getArch ( ) == Triple :: mips64 || TT . getArch ( ) == Triple :: mips64el ) return <ISA_LIT>ABIInfo :: N64 ( ) ; return <ISA_LIT>ABIInfo :: O32


<s> RegisterMCAsmInfoFn X ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; for ( Target * T : { & getThe<ISA_LIT>Target ( ) } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend


<s> MachineOperand & MO = MI -> getOperand ( i + <NUM_LIT> ) ; MIB . addOperand ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; MIB . addOperand ( MO ) ; } return


<s> TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; const MCSection * LSPSection = TLOFMacho . getLazySymbolPointerSection ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { const MCSection * StubSection = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; O << * Stub << <STR_LIT> ; O << <STR_LIT> << * RawSym <<


<s> const MCInstrDesc & Desc = OldMI . getDesc ( ) ; for ( unsigned i = Desc . getNumOperands ( ) , e = OldMI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = OldMI . getOperand ( i ) ; assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) )


<s> if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , INSN_UID ( ready [ index ] ) ) ; insn = ready [ index ] ; for ( i = index ; i < n_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ n_ready - <NUM_LIT> ] = insn ; return issue_rate ; } if ( clock_var != <NUM_LIT> && ! sel_sched_p ( ) && swap_top_of_ready_list ( ready , n_ready ) ) { if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , INSN_UID ( ready [ n_ready - <NUM_LIT> ]

) , INSN_UID ( ready [ n_ready - <NUM_LIT> ] ) ) ;


<s> bool useSoftFloat ( ) const { return UseSoftFloat


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer )


<s> DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT>


<s> return FI <= InArgFIRange . first && FI >= InArgFIRange


<s> assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << ( long long )


<s> } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; if ( ix86_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( ix86_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = <NUM_LIT> ; i < ( ix86_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false


<s> static DecodeStatus DecodePRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= array_lengthof ( PRRegDecoderTable ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( PRRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> else if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCLO ; else break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; OutStreamer . EmitLabel ( DotSym ) ; MachineOperand MO = ( MI -> getOpcode ( ) == <STR_LIT> ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; MCSymbol * OpSym = MCInstLowering . GetExternalSymbolSymbol ( MO ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , Kind , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateImm ( <NUM_LIT> ) ; OutStreamer . EmitInstruction ( TmpInst


<s> return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo ,


<s> BuildMI ( jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( sinkMBB ) ; } copy0MBB -> addSuccessor ( sinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = sinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * sinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( copy0MBB ) . addReg ( Op2Reg ) . addMBB ( thisMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } if ( CascadedCMOV ) { MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( jcc1MBB ) ; BuildMI ( * sinkMBB , std :: next ( MachineBasicBlock :: iterator ( MIB . getInstr ( ) ) ) , DL , TII -> get ( TargetOpcode :: COPY ) , CascadedCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CascadedCMOV -> eraseFromParent ( ) ; } for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) ( MIIt ++ ) ->


<s> return ( __m128i ) __builtin_ia32_pmovzxbq128_mask ( ( __v16qi ) __A , ( __v2di )


<s> if ( ! function_label_operand ( symbol , VOIDmode


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectTrunc ( Instruction * I ) { if ( Subtarget -> is64Bit ( ) ) return false ; MVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; unsigned CopyOpc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I


<s> if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Alignment = Align ( <NUM_LIT> ) ; if ( Flags . isByVal ( ) ) { auto BVAlign = Flags . getNonZeroByValAlign ( ) ; if ( BVAlign


<s> if ( isNullConstant ( BasePtr ) ) return ScaledIndex ; SDValue BaseBroadcast = getBroadcast ( IndexVT , BasePtr , AVL ) ; auto ResPtr = getNode ( <STR_LIT> , IndexVT , { BaseBroadcast , ScaledIndex , Mask , AVL } ) ; return ResPtr


<s> OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> )


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . begin ( ) || MBBI == MBB . end ( ) || MBBI -> getOpcode ( ) != <STR_LIT> ) return false ; MachineBasicBlock :: iterator Prev = MBBI ; -- Prev ; if ( Prev -> getOpcode ( ) != <STR_LIT> || ! Prev -> definesRegister ( <STR_LIT> ) ) return false ; for ( auto Use : Prev -> uses ( ) ) if ( Use . isKill ( ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Use . getReg ( ) , RegState :: Kill ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; MBB . erase ( Prev ) ; return true


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand (


<s> } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT , Subtarget ) ; if ( CompareOpc == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( Op1 ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CompareOpc ) ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; return true


<s> if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ <NUM_LIT> ] != <NUM_LIT> && d -> perm [ <NUM_LIT> ] != nelt / <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) if ( d -> perm [ i ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> || d -> perm [ i + <NUM_LIT> ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case


<s> RBI . constrainGenericRegister ( DstPtrCopy , <STR_LIT> , MRI ) ; RBI . constrainGenericRegister ( SrcValCopy , SrcValRegClass , MRI ) ; RBI . constrainGenericRegister ( SizeCopy , <STR_LIT> , MRI ) ; MIB . buildCopy ( DstPtrCopy , DstPtr ) ; MIB . buildCopy ( SrcValCopy , SrcOrVal ) ; MIB . buildCopy ( SizeCopy , Size ) ; Register DefDstPtr = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register DefSize = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( IsSet ) { MIB . buildInstr ( Mopcode , { DefDstPtr , DefSize } , { DstPtrCopy , SizeCopy , SrcValCopy } ) ; } else


<s> if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( Disp , MemStart , ExprEnd ) ; return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . ParseParenExpression ( Disp , ExprEnd ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) return <NUM_LIT> ; if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT>


<s> ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned OpI = Opc != <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( OpI ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( OpI + <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } if ( ! IsThumb1 ) { MI -> getOperand ( <NUM_LIT> ) . setReg


<s> case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | imm ) ) ; break ; } } else { unsigned unrot = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> )


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result


<s> switch ( Variant ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , E , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , E , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA , E , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGH , E , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHA , E , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER , E ,


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> (


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned NumSrcBits = Src . getScalarValueSizeInBits ( ) ; assert ( VTBits < NumSrcBits && <STR_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; if ( Tmp > ( NumSrcBits - VTBits ) ) return Tmp - ( NumSrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { unsigned SrcBits = Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ; unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal


<s> return ( rs6000_builtin_info [ ( int ) fncode ] . attr

& RS6000_BTC_OVERLOADED ) != <NUM_LIT> ;


<s> if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . isOSAIX ( ) ) return Reloc :: PIC_ ; return Reloc :: Static


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( getTheARM64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ;


<s> SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , NULL , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset


<s> return getShuffleAlignrImmediate ( SVOp ,


<s> static inline bool mode_supports_pre_modify_p


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Op = lowerVectorShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG


<s> return ( ( SrcAlign == <NUM_LIT> || SrcAlign % AlignCheck == <NUM_LIT> )

&& ( DstAlign == <NUM_LIT> || DstAlign % AlignCheck == <NUM_LIT> ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return S


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> case PR_REG : case MACL_REG : case MACH_REG : return <NUM_LIT> ; } return


<s> return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : { const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB =


<s> unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getCPUDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> )


<s> Stub * <ISA_LIT>LongBranchStub :: doClone ( ) { return new <ISA_LIT>LongBranchStub ( m_pData , m_Size , fixup_begin (


<s> unsigned BasePtr = ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = getFrameIndexOffset ( MF , FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . setDesc ( TII . getMemoryInstr ( MI . getOpcode ( )


<s> bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> ; bool RHSConst = ( isSplatVector ( N1 . getNode ( ) ) && isa < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) ; if ( ! RHSTrunc && ! RHSConst ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , WideVT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT> ) ; if ( RHSConst ) { N1 = DAG . getNode ( <STR_LIT> , DL , WideVT . getScalarType ( ) , N1 -> getOperand ( <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > C ( WideVT . getVectorNumElements ( ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , DL , WideVT , & C [ <NUM_LIT> ] , C . size ( ) ) ; } else if ( RHSTrunc ) { N1 = N1 -> getOperand ( <NUM_LIT> ) ; } SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , WideVT , N0 , N1 ) ; unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : return Op ; case <STR_LIT> :


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumBits = VT . getScalarSizeInBits ( ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned Idx = <NUM_LIT> , e = Src . getNumOperands ( ) ; Idx < e ; ++ Idx ) { if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Subtarget . hasSSE2 ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG

. getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , DAG


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs

, C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ;


<s> unsigned getCRSaveOffset ( ) const { return CRSaveOffset


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> if ( isTargetDarwin ( ) ) return <STR_LIT> ; return


<s> std :: vector < Type * > RetTyParams ; Type * RetTyElement ; switch ( N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RetTyElement = Type :: getInt8Ty ( * DAG . getContext ( ) ) ; break ; case <STR_LIT> : RetTyElement = Type :: getInt16Ty ( * DAG . getContext ( ) ) ; break ; case <STR_LIT> : RetTyElement = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; break ; case <STR_LIT> : RetTyElement = Type :: getInt64Ty ( * DAG . getContext ( ) ) ; break ; } RetTyParams . push_back ( RetTyElement ) ; RetTyParams . push_back ( RetTyElement ) ; ArrayRef < Type * > ret = ArrayRef < Type * > ( RetTyParams ) ; Type * RetTy = StructType :: get ( * DAG . getContext ( ) , ret ) ; RTLIB :: Libcall LC = getDivRemLibcall ( N , N -> getValueType ( <NUM_LIT>


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv16qi


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; uint64_t MaxNopLength = ( uint64_t ) getMaximumNopSize ( ) ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ; return


<s> OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT>


<s> return ( vector unsigned short ) __builtin_altivec_mfvscr


<s> Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : if ( ( Value & <NUM_LIT> ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; } Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT>


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT>


<s> if ( ! M . getModuleInlineAsm ( ) . empty ( ) && TT

. isThumb ( ) ) OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ;


<s> return __builtin_aarch64_uqrshrn_nhi_uus ( __a ,


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI = MBB ; if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = std :: next ( MBBI


<s> bool hasV8_2aOps ( ) const { return HasV8_2aOps


<s> return ( int8_t ) __builtin_aarch64_sqrshrn_nhi (


<s> ScopedHT . insert ( Entry , std :: make_pair ( P . first + <NUM_LIT> , Reg


<s> } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; return false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) != MaxBitWidth ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) << <STR_LIT> ) ; return false ; } if ( match ( Val , m_Load ( m_Value


<s> assert ( ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) ==


<s> if ( is_fast_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ; if ( is_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ; if ( is_naked_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ; if ( cfun -> static_chain_decl != NULL ) asm_fprintf ( file , <STR_LIT> <STR_LIT>


<s> unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; emitJumpTableAddress ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , <STR_LIT> ) ; emitWordLE ( Binary


<s> int gregs = ( code & <NUM_LIT> ) != <NUM_LIT> ; unsigned char mask = ( code & <NUM_LIT> ) ; if ( gregs ) UNW_DEC_GR_MEM ( P6 , mask ,


<s> bool FPIsUsed = false ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed )


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutStreamer


<s> ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true


<s> static SDValue LowerZERO_EXTEND_AVX512 ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; MVT ExtVT = NumElts == <NUM_LIT> ? <STR_LIT>


<s> RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterXCOFFStreamer ( * T , create<ISA_LIT>XCOFFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createAsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( *


<s> static SDValue lowerVectorShuffleAsTruncBroadcast ( const SDLoc & DL , MVT VT , SDValue V0 , int BroadcastIdx , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; EVT EltVT = VT . getVectorElementType ( ) ; EVT V0VT = V0 . getValueType ( ) ; assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; EVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits


<s> if ( getSVECalleeSaveSlotRange ( MFI , MinCSFrameIndex , MaxCSFrameIndex ) ) { for ( int I = MinCSFrameIndex ; I <= MaxCSFrameIndex ; ++ I ) { Offset += MFI . getObjectSize ( I ) ; Offset = alignTo ( Offset , MFI . getObjectAlign ( I ) ) ; if ( AssignOffsets ) Assign ( I , - Offset ) ; } } Offset = alignTo ( Offset , Align ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > ObjectsToAllocate ; for ( int I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) { unsigned StackID = MFI . getStackID ( I ) ; if ( StackID != TargetStackID :: ScalableVector ) continue ; if ( MaxCSFrameIndex >= I && I >= MinCSFrameIndex ) continue ; if ( MFI . isDeadObjectIndex ( I ) ) continue ; ObjectsToAllocate . push_back ( I ) ; } for ( unsigned FI : ObjectsToAllocate ) { Align Alignment = MFI . getObjectAlign ( FI ) ; if ( Alignment > Align ( <NUM_LIT> ) ) report_fatal_error


<s> unsigned <ISA_LIT>FrameLowering :: getPSPSlotOffsetFromSP ( const MachineFunction & MF ) const { const WinEHFuncInfo & Info = * MF . getWinEHFuncInfo ( ) ; Register SPReg ; int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg ,


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val <


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; return CONSTANT_P ( x ) || large_toc_ok ; } else if ( TARGET_MACHO ) { if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P || ! flag_pic ) return CONSTANT_P ( x ) ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( x ) ) return false ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return CONSTANT_P ( XVECEXP


<s> FunctionPass * llvm :: create<ISA_LIT>JITCodeEmitterPass ( <ISA_LIT>TargetMachine & TM , JITCodeEmitter & JCE


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Op , DAG , <ISA_LIT>cc ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op .


<s> if ( ! TARGET_HAVE_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF )


<s> MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( FSym ) ) ; FSym -> setContainingCsect (


<s> static SDValue LowerVectorCTLZ ( SDValue Op , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; if ( Subtarget . hasCDI ( ) && ( Subtarget . canExtendTo512DQ ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) ) return LowerVectorCTLZ_AVX512CDI ( Op , DAG , Subtarget ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; return LowerVectorCTLZInRegLUT ( Op , DL , Subtarget


<s> MI ( I ) { Predicates . insert ( Preds . begin ( ) , Preds .


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions


<s> static bool ix86_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case AREG : case DREG : case CREG : case BREG : case AD_REGS : case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG


<s> RegisterTarget < Triple :: cpu0 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: cpu0el , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> ,


<s> static Target The<ISA_LIT>BETarget ; return The<ISA_LIT>BETarget


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target


<s> CurrentFnEPMarkerSym = OutContext . createTempSymbol ( Twine ( <STR_LIT> ) . concat ( N ) . str ( ) , true ) ; CurrentFnPPA1Sym = OutContext . createTempSymbol ( Twine ( <STR_LIT> ) . concat ( N ) . str ( ) , true ) ; const MachineFrameInfo & MFFrame = MF -> getFrameInfo ( ) ; bool IsUsingAlloca = MFFrame . hasVarSizedObjects ( ) ; uint8_t Flags = <NUM_LIT> ; if ( IsUsingAlloca ) Flags |= <NUM_LIT> ; uint32_t DSASize = MFFrame . getStackSize ( ) ; uint32_t DSAAndFlags = DSASize & <NUM_LIT> ; DSAAndFlags |= Flags ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitLabel ( CurrentFnEPMarkerSym ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitIntValueInHex ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitInt8 (


<s> return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) )

|| sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ;


<s> auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Store = tryCreateIncrementingGatScat ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase


<s> TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskLow ; SmallVector < int , <NUM_LIT> > MaskLowTemp1 , MaskLowWord ; SmallVector < int , <NUM_LIT> > MaskHighTemp1 , MaskHighWord ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { MaskLow . push_back ( i ) ; MaskLow . push_back ( i + <NUM_LIT> ) ; } createUnpackShuffleMask ( VT , MaskLowTemp1 , true , false ) ; createUnpackShuffleMask ( VT , MaskHighTemp1 , false , false ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskHighTemp1 , MaskHighWord ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskLowTemp1 , MaskLowWord ) ; Value * IntrVec1Low = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT>


<s> const <ISA_LIT>Subtarget * <ISA_LIT>BaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) .


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB ::


<s> HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > <NUM_LIT> ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( size == <NUM_LIT> || for_eh ) ; else if ( sparc_leaf_function_p ) { if ( size <= <NUM_LIT> ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= <NUM_LIT> ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - <NUM_LIT> ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode ,


<s> PM . add ( create<ISA_LIT>ISelDag ( * this


<s> case FK_Data_8 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGE21 ) ; return true ; } return true ; case <STR_LIT> : case <STR_LIT>


<s> static const CostTblEntry < MVT > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup < MVT > ( NEONShuffleTbl , array_lengthof ( NEONShuffleTbl ) , <STR_LIT>


<s> int idx , vlen = XVECLEN ( body , <NUM_LIT> ) ; ASM_OUTPUT_ADDR_VEC_START ( asm_out_file ) ; ASM_OUTPUT_CASE_LABEL ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) , NEXT_INSN ( lab ) ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER (


<s> unsigned <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_H44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_M44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_L44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HH ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HM ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT10 ) . Case ( <STR_LIT> , VK_Sparc_R_DI<ISA_LIT>32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_HI22

) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_LOX10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LDX ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_LOX10 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> MCSymbol * EHInfoLabel = TargetLoweringObjectFileXCOFF :: getEHInfoTableSymbol ( MF ) ; OutStreamer -> emitLabel ( EHInfoLabel ) ; OutStreamer -> emitInt32 ( <NUM_LIT> ) ; const DataLayout & DL = MMI -> getModule ( ) -> getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSize


<s> if ( UsedFP ) { const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; int64_t LastRegSaveSPOffset = SPOffset - PendingOffset ; UnwindOpAsm . EmitSPOffset ( LastRegSaveSPOffset - FPOffset ) ; UnwindOpAsm . EmitSetSP ( MRI -> getEncodingValue ( FPReg ) ) ; } else { FlushPendingOffset ( ) ; } UnwindOpAsm . Finalize ( PersonalityIndex , Opcodes ) ; if ( NoHandlerData && PersonalityIndex == AEABI_UNWIND_CPP_PR0 ) return ; SwitchToExTabSection ( * FnStart ) ; assert ( ! ExTab ) ; ExTab = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( ExTab ) ; if ( Personality ) { const MCSymbolRefExpr * PersonalityRef = MCSymbolRefExpr :: Create ( Personality , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( PersonalityRef , <NUM_LIT> ) ; } EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size (


<s> if ( getDarwinVers ( ) >= <NUM_LIT> ) return


<s> if ( ( TheTriple . getArch ( ) == Triple :: cpu0 ) ) IsLittleEndian = false ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI =


<s> if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun

-> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr ( SDNode * Parent , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { <ISA_LIT>ISelAddressMode AM ; if ( Parent && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> ) { unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( matchAddress ( N , AM ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM

. Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64Bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , Subtarget ( TT , CPU ,

FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Is64Bit ( is64Bit ) {


<s> static bool rs6000_can_eliminate ( const int from


<s> <ISA_LIT>FunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo


<s> static SDValue PerformVMOVRRDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue InDouble = N -> getOperand ( <NUM_LIT> ) ; if ( InDouble . getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , InDouble . getOperand ( <NUM_LIT> ) , InDouble . getOperand ( <NUM_LIT> ) ) ; SDNode * InNode = InDouble . getNode ( ) ; if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) .

getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode > ( InNode ) -> isVolatile ( ) ) {


<s> else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false


<s> if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; case CONST : inner = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( inner ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( inner , <NUM_LIT> ) ) ) return false ; break ; case


<s> bool offset_ok_for_ldrd_strd ( HOST_WIDE_INT offset ) { HOST_WIDE_INT max_offset ; if ( TARGET_THUMB2 && ( ( offset & <NUM_LIT> ) !=


<s> DOUT << <STR_LIT> ; Indent = <NUM_LIT> ; SelectRoot ( * CurDAG ) ; DOUT << <STR_LIT>


<s> rtx tgt_reg = SET_DEST ( body ) ; machine_mode mode = GET_MODE ( tgt_reg ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int half_elts = n_elts / <NUM_LIT> ; rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i , j ; for ( i = <NUM_LIT> , j = half_elts ; i < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; for ( i = half_elts , j = <NUM_LIT> ; j < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; rtx sel = gen_rtx_VEC_SELECT ( mode , mem_op , par ) ; SET_SRC ( body ) = sel ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file ,


<s> if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T0 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T1 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , } ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT> ; } } if ( Glue . getNode ( ) ) AsmNodeOperands


<s> StringRef getPassName ( ) const override { return AARCH64_EXPAND_PSEUDO_NAME


<s> } aa , bb ; aa . v = ( vector unsigned int ) ( a ) ; bb . v = ( vector unsigned int ) ( b ) ; if ( aa . i [ <NUM_LIT> ] > bb . i [ <NUM_LIT> ] ) { SPU_HALT_ACTION


<s> bool isMemThumbRIs4 ( ) const { if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) || Memory . Alignment != <NUM_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else { return false


<s> static void build_sv_uint_offset ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_none , MODE_s64offset ) ; build_32_64 ( b , signature , group ,


<s> StringRef CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) )


<s> bool IsN64 = Subtarget . isABI_N64 ( ) ; return TFI -> hasFP ( MF ) ? ( IsN64 ? <STR_LIT> : <STR_LIT> ) : ( IsN64 ? <STR_LIT>


<s> OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } } } O << <STR_LIT> ; if ( Subtarget -> isTargetELF ( ) ) { std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) O << <STR_LIT> << CPUString << '\n' ; if ( Subtarget -> hasVFP2 ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( ! UnsafeFPMath ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( FiniteOnlyFPMath ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; else O << <STR_LIT>


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }


<s> case MULT : op2_l = gen_reg_rtx ( qimode ) ; op2_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op2_l , op2 , op2 ) ) ; emit_insn ( gen_ih ( op2_h , op2 , op2 ) ) ; op1_l = gen_reg_rtx ( qimode ) ; op1_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op1_l , op1 , op1 ) ) ; emit_insn ( gen_ih ( op1_h , op1 , op1 ) ) ; full_interleave = qimode == V16QImode ; break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; full_interleave = true ; break ; default : gcc_unreachable ( ) ; } res_l = expand_simple_binop ( himode , code , op1_l , op2_l , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; res_h = expand_simple_binop ( himode , code , op1_h , op2_h , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( res_l && res_h ) ; d . target = dest ; d . op0 = gen_lowpart ( qimode , res_l ) ; d . op1 = gen_lowpart ( qimode , res_h ) ; d . vmode = qimode ; d . nelt = GET_MODE_NUNITS ( qimode ) ; d . one_operand_p = false ; d . testing_p = false ; if ( full_interleave


<s> static void pa_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = pa_function_arg_size ( mode


<s> RecurrenceDescriptor RecDesc ; const bool HasFnNoNaNAttr = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; BasicBlock * Latch = L -> getLoopLatch ( ) ; for ( PHINode & Phi : Latch -> phis ( ) ) { const auto * Ty = Phi . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; const bool IsReduction = RecurrenceDescriptor :: AddReductionVar ( & Phi , RecurrenceDescriptor :: RK_IntegerAdd , L , HasFnNoNaNAttr , RecDesc ) ; if ( ! IsReduction ) continue ; Instruction * Acc = dyn_cast < Instruction > ( Phi . getIncomingValueForBlock ( Latch ) ) ; if ( ! Acc ) continue ; Reductions . push_back ( Reduction ( & Phi , Acc ) ) ; } return ! Reductions . empty ( ) ; } ; ReductionList


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelSegmentOverride ( unsigned SegReg , SMLoc Start , unsigned Size ) { assert ( SegReg != <NUM_LIT> && <STR_LIT> ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; int64_t ImmDisp = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { ImmDisp = Tok . getIntVal ( ) ; AsmToken ImmDispToken = Parser . Lex ( ) ; if ( isParsingInlineAsm ( ) ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , ImmDispToken . getLoc ( ) ) ) ; if ( getLexer ( ) . isNot


<s> bool <ISA_LIT>ElimCompare :: convertToLoadAndTest ( MachineInstr * MI ) { unsigned Opcode = TII -> getLoadAndTest ( MI -> getOpcode ( ) ) ; if ( ! Opcode ) return false ; MI -> setDesc ( TII -> get ( Opcode )


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseLO32DSP ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal


<s> bool isImmShift ( ) { if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ! ConstExpr )


<s> Pos = Lsb ; Size = Msbd + <NUM_LIT> - Pos ; break ; case <STR_LIT> : Pos = Lsb ; Size = Msbd + <NUM_LIT> - Pos ; break ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> - Pos ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg (


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { Triple TT ( TM . getTargetTriple


<s> bool disablePostRAScheduler ( ) const { return DisablePostRAScheduler