<s> assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( isUnpackWdShuffleMask ( Mask , <STR_LIT> ) && ! V2 . isUndef ( ) && ! Subtarget . hasAVX512 ( ) ) if ( SDValue V = lowerShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable ,

Mask , V1 , V2 , DAG , Subtarget ) ) return V ;


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ; if ( Modified ) AFI -> setHasITBlocks


<s> int Mask [ ] = { Start , - <NUM_LIT> , Start + <NUM_LIT> , - <NUM_LIT> } ; Op = DAG . getVectorShuffle ( <STR_LIT> , DL , Op , DAG . getUNDEF ( <STR_LIT> ) , Mask ) ; return DAG . getNode ( <STR_LIT> , DL


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Pattern , DL


<s> case <STR_LIT> : OutMI = MCInst ( ) ; OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : OutMI = MCInst ( ) ; OutMI . setOpcode (


<s> Constant * C = ConstantInt :: get ( * DAG . getContext ( ) , APInt :: getAllOnesValue ( ExtVT . getScalarType ( ) . getSizeInBits ( ) ) ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; SDValue Ld = DAG . getLoad ( ExtVT . getScalarType ( ) , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; SDValue Brcst = DAG . getNode ( <STR_LIT> , dl , ExtVT , In , Ld ) ; if ( VT . is512BitVector (


<s> return TARGET_AAPCS_BASED && arm_abi !=


<s> if ( TT . isOSBinFormatELF ( ) ) return make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return make_unique < TargetLoweringObjectFileCOFF > (


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> case <STR_LIT> : BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , II -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; default : return false ; } ( MI -- ) -> eraseFromBundle ( ) ; return true


<s> if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; if ( Reg . isPhysical ( ) ) return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> ; } ; return llvm :: any_of ( MI .


<s> static SDValue lowerShuffleAsLanePermuteAndShuffle ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; if ( VT == <STR_LIT> && ! all_of ( Mask , [ LaneSize ] ( int M ) { return M < LaneSize ; } ) ) if ( SDValue V = lowerShuffleAsLanePermuteAndSHUFP ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; }


<s> void <ISA_LIT>ReduceCRLogicals :: initialize ( MachineFunction & MFParam ) { MF = & MFParam ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget


<s> bool hasSVE2BitPerm ( ) const { return HasSVE2BitPerm


<s> if ( FB [ <STR_LIT> ] ) { fMode = MODE_16BIT ; return ; } else if ( FB [ <STR_LIT> ] ) { fMode = MODE_32BIT ; return ; } else if ( FB [ <STR_LIT> ] ) { fMode =


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10Lsl2 ( SDValue Addr , SDValue & Base , SDValue & Offset


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - ( STI -> isTargetDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if (


<s> emitSled ( MI , SledKind :: FUNCTION_EXIT


<s> return __builtin_mve_vcmpltq_n_sv16qi ( __a ,


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( AP . lowerOperand ( MO , MCOp ) ) OutMI .


<s> if ( generateSignBits ( V ) ) return false ; auto * I = cast < Instruction > ( V ) ; if ( I -> hasOneUse ( ) && isSink ( * I -> use_begin ( ) ) ) return true ; if ( isa < OverflowingBinaryOperator > ( I ) ) return isSafeOverflow


<s> bool <STR_LIT> ( SDNode * N , bool V2IsSplat ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; return :: isUNPCKHMask ( N -> op_begin ( ) ,


<s> conv = BITMAP_ALLOC ( NULL ) ; bitmap_copy ( conv , insns ) ; if ( scalar_copy ) scopy = gen_reg_rtx ( DImode ) ; for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx reg = DF_REF_REG ( ref ) ; if ( ! MEM_P ( src ) ) { replace_with_subreg_in_insn ( insn , reg , reg ) ; bitmap_clear_bit ( conv , INSN_UID ( insn ) ) ; } if ( scalar_copy ) { rtx vcopy = gen_reg_rtx ( V2DImode ) ; start_sequence ( ) ; if ( TARGET_INTER_UNIT_MOVES_FROM_VEC ) { emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; emit_move_insn ( vcopy , gen_rtx_LSHIFTRT ( V2DImode , vcopy , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_TEMP ) ; emit_move_insn ( tmp , reg ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_conversion_insns ( seq , insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , REGNO ( scopy ) , INSN_UID ( insn ) ) ; } } for ( ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { if ( bitmap_bit_p ( conv , DF_REF_INSN_UID ( ref ) ) ) { rtx def_set = single_set ( DF_REF_INSN ( ref ) ) ; if ( ! MEM_P ( SET_DEST ( def_set ) ) || ! REG_P ( SET_SRC ( def_set ) ) ) replace_with_subreg_in_insn ( DF_REF_INSN ( ref ) , reg , reg ) ; bitmap_clear_bit ( conv , DF_REF_INSN_UID ( ref ) ) ; } } else if ( DF_REF_CHAIN ( ref ) && NONDEBUG_INSN_P ( DF_REF_INSN ( ref ) ) ) { gcc_assert ( scopy ) ; replace_rtx ( DF_REF_INSN ( ref ) , reg , scopy ) ; df_insn_rescan ( DF_REF_INSN ( ref )


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg


<s> union { qword q ; signed char c [ <NUM_LIT> ] ; } x ; x . q


<s> if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine -> func_type = arm_compute_func_type ( ) ; return cfun -> machine ->


<s> BBGen = make_unique < const MachineInstr * [ ] > ( NbReg ) ; std :: fill ( BBGen . get ( ) , BBGen . get ( ) + NbReg , nullptr ) ; BitVector & BBKillSet = Kill [ & MBB ] ; BBKillSet . resize ( NbReg ) ; for ( const MachineInstr & MI : MBB ) { bool IsADRP = MI . getOpcode ( ) == <STR_LIT> ; if ( IsADRP || ! ADRPMode ) for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ( ! ADRPMode && ! MO . isUse ( ) ) || ( ADRPMode && ( ! IsADRP || ! MO . isDef ( ) ) ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; CurReg = ItCurRegId -> second ; if ( ! BBGen [ CurReg ] && ! BBKillSet . test ( CurReg ) ) getSet ( ReachableUses , MBB , CurReg , NbReg ) . insert ( & MI ) ; if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( & MI ) ; } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isRegMask ( ) ) continue ; const uint32_t * PreservedRegs = MO . getRegMask ( ) ; for ( const auto Entry : RegToId ) { unsigned Reg = Entry . second ; if ( MachineOperand :: clobbersPhysReg ( PreservedRegs , Entry . first ) ) { BBGen [ Reg ] = ADRPMode ? & MI


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N ,


<s> if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT>


<s> assert ( ( Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ) { BuildCondBr ( MBB , TBB , DL , Cond ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB


<s> if ( AT == <NUM_LIT> ) reportParseError ( Loc , <STR_LIT> ) ; return AT


<s> if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType =


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext &


<s> unsigned getSRetReturnReg ( ) const { return


<s> int8x16x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT>


<s> bool IdxNIsKill = hasTrivialKill ( Idx ) ; MVT PtrVT = TLI . getPointerTy ( DL ) ; EVT IdxVT = EVT :: getEVT ( Idx -> getType ( ) , false ) ; if ( IdxVT . bitsLT ( PtrVT ) ) { IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false


<s> } else if ( <STR_LIT> . contains ( BP ) ) { MinGPR = std :: min < unsigned > ( MinGPR , BP ) ; HasGPSaveArea = true ; } } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { if ( ! GPRegs [ i ] . isSpilledToReg ( ) ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { if ( ! G8Regs [ i ] . isSpilledToReg ( ) ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && Subtarget . is32BitELFABI ( ) ) { for ( const auto & CSInfo : CSI ) { if ( CSInfo . getReg ( ) == <STR_LIT> ) { int FI = CSInfo . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; break ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSAVESaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSaveArea ) { assert ( LowerBound <= <NUM_LIT> && <STR_LIT> ) ; LowerBound &= ~ ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = VRegs . size ( ) ; i


<s> if ( ! PHIBasePtrSCEV ) continue ; const SCEVConstant * PHIBasePtrIncSCEV = dyn_cast < SCEVConstant > ( PHIBasePtrSCEV -> getStepRecurrence ( * SE ) ) ; if ( ! PHIBasePtrIncSCEV ) continue ; if ( CurrentPHINode -> getNumIncomingValues ( ) == <NUM_LIT> ) { if ( ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) || ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) ) { if ( PHIBasePtrIncSCEV == BasePtrIncSCEV ) { if ( Form == UpdateForm && PHIBasePtrSCEV -> getStart ( ) == BasePtrStartSCEV ) { ++ PHINodeAlreadyExistsUpdate ; return true ; } if ( Form == DSForm || Form == DQForm ) { const SCEVConstant * Diff = dyn_cast < SCEVConstant > ( SE -> getMinusSCEV (

PHIBasePtrSCEV -> getStart ( ) , BasePtrStartSCEV ) ) ;


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_<ISA_LIT>_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_GHC ; return Subtarget -> isTargetDarwin ( ) ? CC_<ISA_LIT>_DarwinPCS :


<s> std :: fill ( LiveRegs , LiveRegs + NumRegs , ( DomainValue * ) <NUM_LIT> ) ; } if ( LiveRegs [ rx ] == dv ) return ; if ( LiveRegs [ rx ] ) { assert ( LiveRegs [ rx ] -> Refs


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return


<s> SDValue Tmp1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Tmp1 . getValueType ( ) ; SDValue AbsVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp0 ) ; SDValue Cmp = getVFPCmp ( Tmp1 , DAG . getConstantFP ( <NUM_LIT> , SrcVT


<s> static unsigned int rest_of_insert_endbranch ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx cet_eb ; rtx_insn * insn ; basic_block bb ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( cfun -> decl ) ) ) && ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { cet_eb = gen_nop_endbr ( ) ; bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; emit_insn_before ( cet_eb , insn ) ; } bb = <NUM_LIT> ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) { if ( find_reg_note ( insn , REG_SETJMP , NULL ) == NULL ) continue ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after_setloc ( cet_eb , insn , INSN_LOCATION ( insn ) ) ; continue ; } if ( JUMP_P ( insn ) && flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) continue ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) continue ; edge_iterator ei ; edge e ; basic_block dest_blk ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { rtx_insn * insn ; dest_blk = e -> dest ; insn = BB_HEAD ( dest_blk ) ; gcc_assert ( LABEL_P ( insn ) ) ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after ( cet_eb ,


<s> bool Isload = ( Opc == TargetOpcode :: G_LOAD ) ; bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> == RB . getID ( ) ) return Isload ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> == RB . getID ( ) ) return Isload ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( )


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , dl , <STR_LIT>


<s> unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt


<s> else DecVal = ( Val << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + DecVal + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst .

addOperand ( MCOperand :: createImm ( isNeg ? - DecVal : DecVal ) ) ;


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_tune == PROCESSOR_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; if ( ! ReqIndirectLoad ) BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; else { unsigned Reg = <STR_LIT> ; unsigned LdOp = <STR_LIT> ; if ( DestReg == <STR_LIT> ) LdOp = <STR_LIT> ; if ( Subtarget . getABI ( ) . ArePtrs64bit ( ) ) { Reg = <STR_LIT> ; if ( DestReg == <STR_LIT> ) LdOp = <STR_LIT> ; else LdOp = <STR_LIT> ; } BuildMI ( MBB , I , DL , get ( Opc ) , Reg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; BuildMI ( MBB , I , DL , get


<s> clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoVirt ( ) ; Parser . Lex ( ) ; return


<s> emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( <NUM_LIT> , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , cookie


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> return ( __m128h ) __builtin_ia32_movaps128_mask ( ( __v4sf ) _mm_conj_pch ( __A ) , ( __v4sf ) _mm_setzero_ps ( ) ,


<s> bool hasValue ( ) const { return K ==


<s> assert ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! DAG . getTarget ( ) . Options . NoNaNsFPMath || ! DAG . getTarget ( ) . Options . NoSignedZerosFPMath ) return SDValue ( ) ; unsigned NewOp = <NUM_LIT> ; switch ( N -> getOpcode (


<s> else if ( GET_CODE ( op ) == CONST_VECTOR && CONST_VECTOR_NUNITS ( op ) . is_constant ( & n_elts ) ) ; else return false ; if ( vec_flags & VEC_SVE_PRED ) return ( op == CONST0_RTX ( mode ) || op == CONSTM1_RTX ( mode ) ) ; scalar_float_mode elt_float_mode ; if ( n_elts == <NUM_LIT> && is_a < scalar_float_mode > ( elt_mode , & elt_float_mode ) ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( op , <NUM_LIT> ) ; if ( aarch64_float_const_zero_rtx_p ( elt ) || aarch64_float_const_representable_p ( elt ) ) { if ( info ) * info = simd_immediate_info ( elt_float_mode , elt ) ; return true ; } } unsigned int elt_size = GET_MODE_SIZE ( elt_mode ) ; if ( elt_size > <NUM_LIT> ) return false ; scalar_int_mode elt_int_mode = int_mode_for_mode ( elt_mode ) . require ( ) ; auto_vec < unsigned char , <NUM_LIT> > bytes ; bytes . reserve ( n_elts * elt_size ) ; for ( unsigned int i = <NUM_LIT> ; i < n_elts ; i ++ ) { bool swap_p = ( ( vec_flags & VEC_ADVSIMD ) != <NUM_LIT> && BYTES_BIG_ENDIAN ) ; rtx elt = CONST_VECTOR_ELT ( op , swap_p ? ( n_elts - <NUM_LIT> - i ) : i ) ; if ( elt_mode != elt_int_mode ) elt = gen_lowpart ( elt_int_mode , elt ) ; if ( ! CONST_INT_P ( elt ) ) return false ; unsigned HOST_WIDE_INT elt_val = INTVAL ( elt ) ; for ( unsigned int byte = <NUM_LIT> ; byte < elt_size ; byte ++ ) { bytes . quick_push ( elt_val


<s> if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; if ( VCTP ) dbgs ( ) << <STR_LIT> << * VCTP ; if ( ! FoundAllComponents ( ) )


<s> unsigned A15SDOptimizer :: createDupLane ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned Reg , unsigned Lane , bool QPR ) { unsigned Out = MRI -> createVirtualRegister (


<s> if ( ! SU -> Preds [ i ] . isNormalMemory ( ) && ! SU -> Preds [ i ] . isBarrier ( ) ) continue ; for ( unsigned j = <NUM_LIT> , je = CurGroup . size ( ) ; j != je ; ++ j ) if ( SU -> Preds [ i ] . getSUnit ( ) == CurGroup [ j ] ) return true ; } return false


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr


<s> void <ISA_LIT>ELFStreamer :: emitPad ( int64_t Offset ) { SPOffset -= Offset ; PendingOffset -=


<s> static tree arm_lookup_simd_builtin_type ( machine_mode mode , enum arm_type_qualifiers q ) { int i ; int nelts = sizeof ( arm_simd_types ) / sizeof ( arm_simd_types [ <NUM_LIT> ] ) ; if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode ) ) return arm_simd_builtin_std_type


<s> if ( Subtarget -> hasSSE1 ( ) ) return <ISA_LIT>CompilationCallback_SSE ; return <ISA_LIT>CompilationCallback


<s> return ( __m64 ) __builtin_ia32_paddd ( ( __v2si )


<s> if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = <NUM_LIT> ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno +=


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> rtx tmp = gen_rtx_MEM ( DImode , XEXP ( regbuf , <NUM_LIT> ) ) ; int ofs = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < ns ; i ++ ) { int rn = ( <NUM_LIT> - ns ) + i + <NUM_LIT> ; rtx ptr ; ptr = offset_address ( tmp , GEN_INT ( ofs ) , <NUM_LIT> ) ; emit_move_insn ( ptr , gen_rtx_REG ( DImode , rn ) ) ; ofs +=


<s> SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( SDValue Promote = PromoteMaskArithmetic ( N0 . getNode ( ) , DAG , Subtarget ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Promote , N1 ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode (


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return FrameLowering


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack


<s> if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( InsertMask && isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 , Tmp3 ; bool DisjointMask = ( TargetMask ^ InsertMask ) == <NUM_LIT> ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } else


<s> DebugLoc DL = Op . getDebugLoc ( ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) if ( C -> isOne ( ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) if ( C -> isOne ( ) ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> ,


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , true , NULL ,


<s> void setDPRCalleeSavedAreaOffset ( unsigned o ) { DPRCSOffset =


<s> <ISA_LIT>ConstantPoolJT * <ISA_LIT>ConstantPoolJT :: Create ( Type * Ty , int JTI , unsigned PCAdj , <STR_LIT> Modifier ) { return new <ISA_LIT>ConstantPoolJT ( Ty , JTI , PCAdj , Modifier ,


<s> inline AddrOpc getAM5Op ( unsigned AM5Opc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT>


<s> void rs6000_emit_sISEL ( machine_mode mode ATTRIBUTE_UNUSED , rtx operands [


<s> if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 &&


<s> unsigned OReg64 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned TReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , OReg ) . addReg ( BReg ) . addImm ( <NUM_LIT> ) . addReg ( IReg64 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , OReg64 ) . addReg ( OReg ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , TReg ) . addReg ( OReg64 ) . addReg ( BReg ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TReg ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } } else { BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( IReg ) . addJumpTableIndex ( MJTI ) . addReg ( <NUM_LIT> ) ; } SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > SeenMBBs ; for ( auto & LP : LPadList ) if ( SeenMBBs . insert ( LP ) . second ) DispContBB -> addSuccessor ( LP ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > MBBLPads ; const MCPhysReg * SavedRegs = MF -> getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( MachineBasicBlock * MBB : InvokeBBs ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > Successors ( MBB -> succ_rbegin ( ) , MBB -> succ_rend ( ) ) ; for ( auto MBBS : Successors ) { if ( MBBS -> isEHPad ( ) ) { MBB -> removeSuccessor ( MBBS ) ; MBBLPads . push_back ( MBBS ) ; } } MBB -> addSuccessor ( DispatchBB ) ; for ( auto & II : reverse ( * MBB ) ) { if ( ! II . isCall ( ) ) continue ; DenseMap < unsigned , bool > DefRegs ; for ( auto & MOp : II . operands ( ) ) if ( MOp . isReg ( ) ) DefRegs [ MOp . getReg ( ) ] = true ; MachineInstrBuilder MIB ( * MF , & II ) ; for ( unsigned RI = <NUM_LIT> ; SavedRegs [ RI ] ; ++ RI ) { unsigned Reg = SavedRegs [ RI ] ; if ( ! DefRegs [ Reg ] ) MIB . addReg ( Reg , RegState :: ImplicitDefine | RegState :: Dead ) ; } break ; } } for ( auto & LP : MBBLPads ) LP


<s> Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; const MachineOperand & Base = MI . getOperand ( OpIdx ++ ) ; Binary |= getMachineOpValue ( MI , Base ) << <STR_LIT> ; if ( Base . isReg ( ) ) { const MachineOperand & Offset = MI . getOperand ( OpIdx ) ; if ( unsigned ImmOffs = <STR_LIT> ( Offset . getImm ( ) ) ) { if ( <STR_LIT> ( Offset . getImm ( ) ) == <STR_LIT> ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |=


<s> bool DstIsLarger , SrcIsLarger ; tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg


<s> int Width = <NUM_LIT> ; if ( isThumb ( ) ) { switch ( Suffix ) { case 'n' : Width = <NUM_LIT> ; break ; case 'w' : break ; default : Width = <NUM_LIT> ; break ; } } else { if ( Suffix ) return Error ( Loc , <STR_LIT> ) ; } auto parseOne = [ & ] ( ) -> bool { const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * Value = dyn_cast_or_null < MCConstantExpr > ( Expr ) ; if ( ! Value ) { return Error ( Loc , <STR_LIT> ) ; } char CurSuffix = Suffix ; switch ( Width ) { case <NUM_LIT> : if ( Value -> getValue ( ) > <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( Value -> getValue ( ) > <NUM_LIT> ) return Error ( Loc , StringRef ( Suffix ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> ) ; break ; case <NUM_LIT> : if ( Value -> getValue ( ) < <NUM_LIT> ) CurSuffix = 'n' ; else if ( Value -> getValue ( )


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins


<s> MachineInstr & Reduce = Reduction -> Reduce ; Register DestReg = Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reduction -> Init ) { MachineInstr * Init = Reduction -> Init ; for ( unsigned i = <NUM_LIT> ; i < Init -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = Init -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . isTied ( ) && Init -> findTiedOperandIdx ( i ) == <NUM_LIT> ) Init -> getOperand ( i ) . setReg ( DestReg ) ; } Init -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Init ) ; } else BuildMov ( LoLoop . Preheader -> instr_back ( ) , DestReg , Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reduce ) ; MachineInstr & VPSEL = Reduction -> VPSEL ; if ( VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) != DestReg ) BuildMov ( VPSEL , VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Copy << <STR_LIT> << VPSEL << <STR_LIT> ) ; Copy . eraseFromParent ( ) ; VPSEL . eraseFromParent (


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses (


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned NumAddrOps = MOs . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; if ( NumAddrOps < <NUM_LIT> ) MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else { MIB . addOperand ( MO ) ; } } return


<s> return ( __m128i ) __builtin_ia32_punpcklqdq128 ( ( __v2di ) __A , (


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else { switch ( Val ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> auto * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , HasRelocationAddend , IsN64 , TT . isLittleEndian ( ) ) ; return createELFObjectWriter ( MOTW , OS ,


<s> if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & <NUM_LIT> ; const unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } MBB . erase ( MI


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugValue ( ) ) ++ I ; if ( I != E


<s> SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue (


<s> for ( unsigned i = <NUM_LIT> ; i != NumDstElts ; i ++ ) { Mask . push_back ( i ) ; for ( unsigned j = <NUM_LIT> ; j != Scale ; j ++

) Mask . push_back ( SM_SentinelZero ) ;


<s> unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = nullptr ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> Qm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Qd


<s> return ( uint64_t ) __builtin_aarch64_ashldi (


<s> LaneB = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ViaVecTy = <STR_LIT> ; if ( BigEndian ) std :: swap ( LaneA , LaneB ) ; } else LaneB = LaneA ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getBuildVector ( ViaVecTy , DL , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( ViaVecTy != ResVecTy ) { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ViaVecTy ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Result


<s> SDValue Sel = Op . getOperand ( <NUM_LIT> ) ; SDValue Other = Op . getOperand ( <NUM_LIT> ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Sel ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnesValue ( ) && CFVal


<s> ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ; return ret


<s> if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , Range -> second ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == Range -> second ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; SwitchEQNEToPLMI = true ; } else if ( ! Subtarget -> hasV6T2Ops ( ) ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; NewN = EmitShift ( <STR_LIT> , SDValue ( NewN , <NUM_LIT> ) , Range -> second + ( <NUM_LIT> - Range -> first ) ) ; ReplaceNode ( And . getNode ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( ( format == <NUM_LIT> && write_symbols != DWARF2_DEBUG ) || format == <NUM_LIT> ) return regno ; if ( regno <= <NUM_LIT> ) return regno ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == CA_REGNO


<s> SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectSVESignedArithImm ( SDValue N , SDValue & Imm ) { if ( auto CNode = dyn_cast < ConstantSDNode > ( N ) ) { int64_t ImmVal = CNode -> getSExtValue ( ) ; SDLoc DL ( N ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal < <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true


<s> return ( ( p1 -> mode [ <NUM_LIT> ] == p2 -> mode [ <NUM_LIT> ] ) && ( p1 -> mode [ <NUM_LIT> ] == p2 -> mode [ <NUM_LIT> ] ) && ( p1 -> mode [ <NUM_LIT> ] == p2 -> mode [ <NUM_LIT> ] ) && ( p1 -> mode [ <NUM_LIT> ] == p2 -> mode [ <NUM_LIT> ] ) && (


<s> } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ; if ( HasSecRelSymbolRef ( Bin -> getLHS ( ) ) || HasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_2 ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_1 )


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; align *= ( <NUM_LIT> << size ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) NewMI . add ( condCodeOp ( ) ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > LiveOuts ; LiveOuts = llvm :: findDefsUsedOutsideOfLoop ( L ) ; bool ReductionsDisabled = EnableTailPredication == TailPredication :: EnabledNoReductions || EnableTailPredication == TailPredication :: ForceEnabledNoReductions ; for ( auto * I : LiveOuts ) { if ( ! I -> getType ( ) -> isIntegerTy ( ) && ! I -> getType ( ) -> isFloatTy ( ) && ! I -> getType ( ) -> isHalfTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ReductionsDisabled ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } PredicatedScalarEvolution PSE = LAI -> getPSE ( ) ; SmallVector < Instruction * , <NUM_LIT> > LoadStores ; int ICmpCount = <NUM_LIT> ; for ( BasicBlock * BB : L -> blocks ( ) ) { for ( Instruction & I : BB -> instructionsWithoutDebug ( ) ) { if ( isa < PHINode > ( & I ) ) continue ; if ( ! canTailPredicateInstruction ( I , ICmpCount ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . dump ( ) ) ; return false ; } Type * T = I . getType ( ) ; if ( T -> isPointerTy ( ) ) T = T -> getPointerElementType ( ) ; if ( T -> getScalarSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; T -> dump ( ) ) ; return false ; } if ( isa < StoreInst > ( I ) || isa < LoadInst > ( I ) ) { Value * Ptr = isa < LoadInst > ( I ) ? I . getOperand ( <NUM_LIT> ) : I . getOperand ( <NUM_LIT> ) ; int64_t NextStride = getPtrStride ( PSE , Ptr , L ) ; if ( NextStride == <NUM_LIT> ) { continue ; } else if ( NextStride == - <NUM_LIT> || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } else if ( EnableMaskedGatherScatters


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32


<s> return <STR_LIT> ; case XOR : return <STR_LIT> ; case SHL : return <STR_LIT> ; case SRL : return <STR_LIT> ; case SRA : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size && align < BITS_PER_WORD


<s> else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_64 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_EABI ; else return false ; return true ; case OPT_march_ : case OPT_mtune_ : return mips_parse_cpu ( arg ) != <NUM_LIT> ; case


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . addOperand ( MO )


<s> void addT2SOImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm


<s> MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . addOperand (


<s> createLShiftOri < ShiftAmount > ( MCOperand :: createImm ( Value


<s> } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 , CommOpIdx2 ; if ( ! TII -> findCommutedOpIndices ( MI , CommOpIdx1 , CommOpIdx2 ) || CommOpIdx1 != <NUM_LIT> || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( MI ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl ,


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo >


<s> N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) ->


<s> void mep_final_prescan_insn ( rtx_insn * insn , rtx * operands ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( GET_MODE ( insn ) == BImode && get_attr_slots ( insn ) !=

SLOTS_CORE ) fputc ( '+' , asm_out_file ) ;


<s> else gcc_unreachable ( ) ; call_insn = last_call_insn ( ) ; PATTERN ( call_insn ) = insn ; if ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; emit_library_call_value ( tga , tmp1 , LCT_CONST , Pmode , <NUM_LIT> , const0_rtx , Pmode ) ; r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( TARGET_64BIT ) insn = gen_tls_ld_aix64 ( r3 , got , tga , const0_rtx ) ; else insn = gen_tls_ld_aix32 ( r3 , got , tga , const0_rtx ) ; } else if ( DEFAULT_ABI == ABI_V4 ) insn = gen_tls_ld_sysvsi ( r3 , got , tga , const0_rtx ) ; else gcc_unreachable ( ) ; call_insn = last_call_insn ( ) ; PATTERN ( call_insn ) = insn ; if ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; if ( rs6000_tls_size == <NUM_LIT> ) { if ( TARGET_64BIT ) insn = gen_tls_dtprel_64 ( dest , tmp1 , addr ) ; else insn = gen_tls_dtprel_32 ( dest , tmp1 , addr ) ; } else if ( rs6000_tls_size == <NUM_LIT> ) { tmp2 = gen_reg_rtx ( Pmode ) ; if ( TARGET_64BIT ) insn = gen_tls_dtprel_ha_64 ( tmp2 , tmp1 , addr ) ; else insn = gen_tls_dtprel_ha_32 ( tmp2 , tmp1 , addr ) ; emit_insn ( insn ) ; if ( TARGET_64BIT ) insn = gen_tls_dtprel_lo_64 ( dest , tmp2 , addr ) ; else insn = gen_tls_dtprel_lo_32 ( dest , tmp2 , addr


<s> break ; case LSHIFTRT : if ( outer_code == ZERO_EXTEND && CONST_INT_P ( XEXP ( inner , <NUM_LIT> ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , <NUM_LIT> ) ; break ; case ASHIFTRT : if ( outer_code == SIGN_EXTEND && CONST_INT_P ( XEXP ( inner , <NUM_LIT> ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , <NUM_LIT> ) ; break ; default : break ; } return op


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; enum rs6000_builtins fcode = ( enum rs6000_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; const struct builtin_description * d = bdesc_mma ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_mma ) ; i ++ , d ++ ) if ( d -> code == fcode ) break ; if ( i >= ARRAY_SIZE ( bdesc_mma ) ) { * expandedp = false ; return NULL_RTX ; } * expandedp = true ; tree arg ; call_expr_arg_iterator iter ; enum insn_code icode = d -> icode ; const struct insn_operand_data * insn_op ; rtx op [ MAX_MMA_OPERANDS ] ; unsigned nopnds = <NUM_LIT> ; unsigned attr = rs6000_builtin_info [ fcode ] . attr ; bool void_func = ( attr & RS6000_BTC_VOID ) ; machine_mode tmode = VOIDmode ; if ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) != void_type_node ) { tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ nopnds ++ ] = target ; } else target = const0_rtx ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node ) return const0_rtx ; rtx opnd ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; if ( TREE_CODE ( arg ) == ADDR_EXPR && MEM_P ( DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ) ) opnd = DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ; else opnd = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( opnd , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { if ( ! CONST_INT_P ( opnd ) ) error ( <STR_LIT> , nopnds ) ; else error ( <STR_LIT> <STR_LIT> , nopnds ) ; return const0_rtx ; } opnd = copy_to_mode_reg ( insn_op -> mode , opnd ) ; } if ( ! void_func && nopnds == <NUM_LIT> && ! strcmp ( insn_op -> constraint , <STR_LIT> ) && insn_op -> mode == tmode && REG_P ( opnd ) && ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( opnd , tmode ) ) target = op [ <NUM_LIT> ] = opnd ; op [ nopnds ++ ] = opnd ; } unsigned attr_args = attr & RS6000_BTC_OPND_MASK ; if ( attr & RS6000_BTC_QUAD || fcode == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) attr_args ++ ; gcc_assert ( nopnds == attr_args ) ; rtx pat ; switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ,


<s> case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; getShiftedImmVal ( ) -> print ( OS ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } else { assert ( CanUseBFC ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState

:: Kill ) . addImm ( ~ AlignMask ) . add ( predOps ( <STR_LIT> ) ) ;


<s> SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL ,


<s> return isVectorIndexInRange < <NUM_LIT> > (


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false

, true , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> return ( DEFAULT_ABI == ABI_V4 && ! flag_pic && ! TARGET_TOC && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST ) &&


<s> static bool isNegatedInteger ( SDValue Op ) { return Op . getOpcode ( ) == <STR_LIT> &&

isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ;


<s> unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( MIOperands MO ( memOps [ i ] . MBBI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) || ! MO -> isImplicit ( ) || MO -> isDead ( ) ) continue ; unsigned DefReg = MO -> getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; findUsesOfImpDef ( UsesOfImpDefs , memOps , DefReg , memOps [ i ] . Position , insertPos ) ; } } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs , ImpDefs ) ) return ; Merges . push_back ( prior ( Loc ) ) ; for ( SmallVectorImpl < MachineOperand * > :: iterator I = UsesOfImpDefs . begin ( ) , E = UsesOfImpDefs . end ( ) ; I != E ; ++ I ) ( * I ) -> setIsUndef ( ) ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { if ( Regs [ i - memOpsBegin ] . second ) { unsigned Reg = Regs [ i - memOpsBegin ] . first ; if ( KilledRegs . count ( Reg ) ) { unsigned j = Killer [ Reg ] ; int Idx = memOps [ j ] . MBBI -> findRegisterUseOperandIdx ( Reg , true ) ; assert ( Idx >= <NUM_LIT> && <STR_LIT> ) ; memOps [ j ] . MBBI -> getOperand ( Idx ) . setIsKill ( false ) ; memOps [ j ] . isKill = false ; } memOps [ i ] . isKill


<s> if ( ! regs_ever_live [ GLOBAL_POINTER_REGNUM ] && ! current_function_uses_const_pool && ! mips_function_has_gp_insn ( ) ) return <NUM_LIT> ; if ( TARGET_NEWABI && current_function_is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM


<s> return ( int16x4_t ) __builtin_neon_vqrdmulh_lanev4hi ( __a ,


<s> const char * fmt ; int i ; if ( LABEL_REF_P ( x ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return <NUM_LIT> ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i


<s> int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( <STR_LIT> ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF ,


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSAlignGapSize ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> )

, NumAlignedDPRCS2Regs ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , IsSplitCSR ( false ) {


<s> } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ; return true ; } } if ( ( EltSizeInBits % V1 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && ( EltSizeInBits % V2 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> ) { bool IsBlend = true ; unsigned NumV1Elts = V1 . getValueType ( ) . getVectorNumElements ( ) ; unsigned NumV2Elts = V2 . getValueType ( ) . getVectorNumElements ( ) ; unsigned Scale1 =


<s> bool <ISA_LIT>TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > (


<s> } while ( match ( Acc , m_Add ( m_Value ( A ) , m_Mul ( m_Value ( MulOp0 ) , m_Value ( MulOp1 ) ) ) ) ) { AddCandidateMAC ( Candidates , Acc , MulOp0 , MulOp1 , <NUM_LIT> ) ; Acc = dyn_cast < Instruction > ( A ) ; } if ( match ( Acc , m_Add ( m_Mul ( m_Value ( MulOp0 ) , m_Value ( MulOp1 ) ) , m_Value ( A ) ) ) ) AddCandidateMAC ( Candidates , Acc , MulOp0 , MulOp1 , <NUM_LIT> ) ; std :: reverse ( Candidates . begin ( ) , Candidates . end ( ) ) ; return Candidates


<s> void function_expander :: add_mem_operand ( machine_mode mode , rtx addr ) { gcc_assert ( VECTOR_MODE_P ( mode ) || mode == OImode ) ; rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr )


<s> op_true = force_reg ( mode , op_true ) ; if ( ! nonimmediate_operand ( op_false , mode ) ) op_false = force_reg ( mode , op_false ) ; emit_insn ( gen_rtx_SET ( mode , dest , gen_rtx_IF_THEN_ELSE ( mode , cmp , op_true , op_false ) ) ) ; } else { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) = NULL ; rtx d = dest ; if ( ! nonimmediate_operand ( op_true , mode ) ) op_true = force_reg ( mode , op_true ) ; op_false = force_reg ( mode , op_false ) ; switch ( mode ) { case V4SFmode : if ( TARGET_SSE4_1 ) gen = gen_sse4_1_blendvps ; break ; case V2DFmode : if ( TARGET_SSE4_1 ) gen = gen_sse4_1_blendvpd ; break ; case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE4_1 ) { gen = gen_sse4_1_pblendvb ; if ( mode != V16QImode ) d = gen_reg_rtx ( V16QImode ) ; op_false = gen_lowpart ( V16QImode , op_false ) ; op_true = gen_lowpart ( V16QImode , op_true ) ; cmp = gen_lowpart ( V16QImode , cmp ) ; } break ; case V8SFmode : if ( TARGET_AVX ) gen = gen_avx_blendvps256 ; break ; case V4DFmode : if ( TARGET_AVX ) gen = gen_avx_blendvpd256 ; break ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) { gen = gen_avx2_pblendvb ; if ( mode != V32QImode ) d = gen_reg_rtx ( V32QImode ) ; op_false = gen_lowpart ( V32QImode , op_false ) ; op_true = gen_lowpart ( V32QImode , op_true ) ; cmp = gen_lowpart ( V32QImode , cmp ) ; } break ; case V64QImode : gen = gen_avx512bw_blendmv64qi ; break ; case V32HImode : gen = gen_avx512bw_blendmv32hi ; break ; case V16SImode : gen = gen_avx512f_blendmv16si ; break ; case V8DImode : gen = gen_avx512f_blendmv8di ; break ; case V8DFmode : gen = gen_avx512f_blendmv8df ; break ; case V16SFmode : gen = gen_avx512f_blendmv16sf ; break ; default : break ; } if ( gen != NULL ) { emit_insn ( gen ( d , op_false , op_true , cmp ) ) ; if ( d != dest ) emit_move_insn ( dest , gen_lowpart ( GET_MODE ( dest ) , d ) ) ; } else { op_true = force_reg ( mode , op_true ) ; t2 = gen_reg_rtx ( mode ) ; if ( optimize ) t3 = gen_reg_rtx (


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } Base = N


<s> return inline_secondary_memory_needed ( mode , class1 ,


<s> SelectionDAG & DAG = DCI . DAG ; if ( Subtarget -> isThumb1Only ( ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue


<s> if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT>


<s> const TargetRegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; MachineBasicBlock :: iterator Me = Copy , B = Copy ->


<s> static SDValue lowerV4X128VectorShuffle ( SDLoc DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , WidenedMask


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF


<s> return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext (


__v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ; if ( CmpOpTy != nullptr && CmpOpTy -> isFloatingPointTy ( ) ) Cost ++ ; return Cost ; } } else if ( ST -> hasVector ( ) ) { auto * SrcVecTy = cast < FixedVectorType > ( Src ) ; auto * DstVecTy = cast < FixedVectorType > ( Dst ) ; unsigned VF = SrcVecTy -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src


<s> int nunits = GET_MODE_NUNITS ( mode ) ; rtx val = CONST_VECTOR_ELT ( op , BYTES_BIG_ENDIAN ? nunits - <NUM_LIT> : <NUM_LIT> ) ; unsigned step = nunits / <NUM_LIT> ; unsigned copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , val ) ) ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT>


<s> const MILOHContainer & getLOHContainer ( )


<s> unsigned Mask = <NUM_LIT> ; for ( MachineBasicBlock :: livein_iterator I = MBB -> livein_begin ( ) , E =

MBB -> livein_end ( ) ; I != E ; ++ I ) {


<s> CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { CC = <STR_LIT> ; bool IsSigned = Op . getOpcode ( ) == <STR_LIT> ; if ( Op . getValueType ( ) == <STR_LIT> ) { unsigned ExtendOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; LHS = DAG . getNode ( ExtendOpc , DL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( ExtendOpc , DL , <STR_LIT> , RHS ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , MVT_CC ) ; if ( IsSigned ) { SDValue SExtMul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VTs , Mul , SExtMul ) . getValue ( <NUM_LIT> ) ; } else { SDValue UpperBits = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VTs , Mul , UpperBits ) . getValue ( <NUM_LIT> ) ; } break ; } assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; if ( IsSigned ) { SDValue UpperBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; SDValue LowerBits = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm -> getValue ( )


<s> rtx perm [ <NUM_LIT> ] ; high = ( highp ? <NUM_LIT> : nelt / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { perm [ i * <NUM_LIT> ] = GEN_INT ( i + high ) ; perm [ i * <NUM_LIT> + <NUM_LIT> ] = GEN_INT ( i + nelt


<s> return DAG . getStore ( Chain , DL , DAG . getConstant ( StoreVal , DL , <STR_LIT> ( Size * <NUM_LIT> ) ) , Dst , DstPtrInfo


<s> case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT>


<s> void EmitARM64WinCFISetFP ( ) override { OS <<


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumNotSplitWrongOpcode ++ ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ; CRI . dump ( ) ) ; MachineBasicBlock :: iterator Def1It = CRI . TrueDefs . first ; MachineBasicBlock :: iterator Def2It = CRI . TrueDefs . second ; bool UsingDef1 = false ; MachineInstr * SplitBefore = & * Def2It ; for ( auto E = CRI . MI -> getParent ( ) -> end ( ) ; Def2It != E ; ++ Def2It ) { if ( Def1It == Def2It ) { SplitBefore = & * Def1It ; UsingDef1 = true ; break ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DEBUG ( CRI . MI -> getParent ( ) -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; SplitBefore -> dump ( ) ) ; MachineInstr * Branch = MRI -> use_nodbg_begin ( CRI . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getParent ( ) ; MachineBasicBlock * MBB = SplitBefore -> getParent ( ) ; auto FirstTerminator = MBB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator FirstInstrToMove = UsingDef1 ? CRI . TrueDefs . first : CRI . TrueDefs . second ; MachineBasicBlock :: iterator SecondInstrToMove = UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second ; MBB -> splice ( FirstTerminator , MBB , FirstInstrToMove ) ; if ( FirstInstrToMove != SecondInstrToMove ) MBB -> splice ( FirstTerminator , MBB , SecondInstrToMove ) ; MBB -> splice ( FirstTerminator , MBB , CRI . MI ) ; unsigned Opc = CRI . MI -> getOpcode ( ) ; bool InvertOrigBranch ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFReg ( SMLoc L ) { unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFReg ( Reg ,


<s> bool isMachoABI = <ISA_LIT>SubTarget . isMachoABI ( ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = <ISA_LIT>FrameInfo :: getReturnSaveOffset ( Is<ISA_LIT>64 ,


<s> Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case


<s> bool R ; if ( Outs [ i ] . IsFixed ) R = CC_<ISA_LIT>N ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; else R = CC_<ISA_LIT>N_VarArg ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; if ( R )


<s> bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) if ( ! V1 . getOperand ( i ) . isUndef ( ) ) { IsScalarToVector = false ; break ; } if ( IsScalarToVector ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , V1 , DAG . getConstant ( Lane , dl , <STR_LIT> ) ) ; } bool ReverseVEXT ; unsigned Imm ; if ( isVEXTMask ( ShuffleMask , VT , ReverseVEXT , Imm ) ) { if ( ReverseVEXT ) std :: swap ( V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( V2 -> isUndef ( ) && isSingletonVEXTMask ( ShuffleMask , VT , Imm ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V1 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } unsigned WhichResult ; bool isV_UNDEF ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , VT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) V2 = V1 ; return DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; } if ( V1 -> getOpcode ( ) == <STR_LIT> && V2 -> isUndef ( ) ) { SDValue SubV1 = V1 -> getOperand ( <NUM_LIT> ) ; SDValue SubV2 = V1 -> getOperand ( <NUM_LIT> ) ; EVT SubVT = SubV1 . getValueType ( ) ; assert ( all_of ( ShuffleMask , [ & ] ( int i ) { return i < ( int ) VT . getVectorNumElements (


<s> static bool isIsaMatched ( uint32_t base , uint32_t ext ) { if ( base == ext ) return true ; if ( base == llvm :: ELF :: EF_MIPS_ARCH_32 && isIsaMatched ( llvm :: ELF :: EF_MIPS_ARCH_64 , ext ) ) return true ; if ( base == llvm :: ELF :: EF_MIPS_ARCH_32R2 && isIsaMatched ( llvm :: ELF :: EF_MIPS_ARCH_64R2 , ext ) ) return true ; for ( const auto & edge : isaTree ) { if ( ext == edge . child ) { ext = edge . parent ; if ( ext == base ) return true ; } } return false


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicIndex ( N , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicDUP ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return LowerSVEIntrinsicEXT ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return combineSVEReductionOrderedFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , N ->

getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E =


<s> static SDValue PerformXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) ) return RV ; if ( Subtarget . hasCMov ( ) ) if ( SDValue RV = performIntegerAbsCombine ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; return SDValue


<s> switch ( Reg ) { case D15 : case D14 :


<s> } for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , NumOps + <NUM_LIT> ) ) MIB . add ( MO ) ; updateOperandRegConstraints ( MF , * NewMI , TII ) ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt , NewMI ) ; return MIB


<s> addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ; Module * M = Builder . GetInsertBlock ( ) ->


<s> ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Enable<ISA_LIT>LongCalls ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Enable<ISA_LIT>LongCalls ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( Enable<ISA_LIT>LongCalls ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i )

MIB . addReg ( RegArgs [ i ] , RegState :: Implicit ) ;


<s> bool <ISA_LIT>TargetLowering :: allowTruncateForTailCall ( Type * FromType , Type * ToType ) const { return isTruncateFree ( FromType ,


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; unsigned isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) ->


<s> emitFPCompare ( FCmp . getOperand ( <NUM_LIT> ) . getReg ( ) , FCmp . getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( static_cast < CmpInst :: Predicate > ( FCmp . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) , CC1 , CC2 ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC1 ) . addMBB ( DestMBB ) ; if ( CC2 != <STR_LIT> ) MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC2 ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true


<s> assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Register OldReg = SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI -> clearKillFlags ( OldReg ) ; MRI -> replaceRegWith ( OldReg , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI